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[dxbc] Count clipping and culling planes

This commit is contained in:
Philip Rebohle 2018-03-23 19:48:07 +01:00
parent 7c65764ed8
commit 31772af4a5
No known key found for this signature in database
GPG Key ID: C8CC613427A31C99
5 changed files with 61 additions and 17 deletions

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@ -5,9 +5,17 @@ namespace dxvk {
DxbcAnalyzer::DxbcAnalyzer(
const DxbcOptions& options,
const DxbcProgramVersion& version,
const Rc<DxbcIsgn>& isgn,
const Rc<DxbcIsgn>& osgn,
DxbcAnalysisInfo& analysis)
: m_analysis(&analysis) {
: m_isgn (isgn),
m_osgn (osgn),
m_analysis(&analysis) {
// Get number of clipping and culling planes from the
// input and output signatures. We will need this to
// declare the shader input and output interfaces.
m_analysis->clipCullIn = getClipCullInfo(m_isgn);
m_analysis->clipCullOut = getClipCullInfo(m_osgn);
}
@ -37,4 +45,20 @@ namespace dxvk {
}
}
DxbcClipCullInfo DxbcAnalyzer::getClipCullInfo(const Rc<DxbcIsgn>& sgn) const {
DxbcClipCullInfo result;
for (auto e = sgn->begin(); e != sgn->end(); e++) {
const uint32_t componentCount = e->componentMask.popCount();
if (e->systemValue == DxbcSystemValue::ClipDistance)
result.numClipPlanes += componentCount;
if (e->systemValue == DxbcSystemValue::CullDistance)
result.numCullPlanes += componentCount;
}
return result;
}
}

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@ -21,11 +21,22 @@ namespace dxvk {
bool accessAtomicOp = false;
};
/**
* \brief Counts cull and clip distances
*/
struct DxbcClipCullInfo {
uint32_t numClipPlanes = 0;
uint32_t numCullPlanes = 0;
};
/**
* \brief Shader analysis info
*/
struct DxbcAnalysisInfo {
std::array<DxbcUavInfo, 64> uavInfos;
DxbcClipCullInfo clipCullIn;
DxbcClipCullInfo clipCullOut;
};
/**
@ -42,6 +53,8 @@ namespace dxvk {
DxbcAnalyzer(
const DxbcOptions& options,
const DxbcProgramVersion& version,
const Rc<DxbcIsgn>& isgn,
const Rc<DxbcIsgn>& osgn,
DxbcAnalysisInfo& analysis);
~DxbcAnalyzer();
@ -55,8 +68,14 @@ namespace dxvk {
private:
Rc<DxbcIsgn> m_isgn;
Rc<DxbcIsgn> m_osgn;
DxbcAnalysisInfo* m_analysis = nullptr;
DxbcClipCullInfo getClipCullInfo(
const Rc<DxbcIsgn>& sgn) const;
};
}

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@ -1314,7 +1314,7 @@ namespace dxvk {
DxbcRegisterValue dst;
dst.type.ctype = ins.dst[0].dataType;
dst.type.ccount = ins.dst[0].mask.setCount();
dst.type.ccount = ins.dst[0].mask.popCount();
const uint32_t typeId = getVectorTypeId(dst.type);
@ -1547,7 +1547,7 @@ namespace dxvk {
const DxbcRegisterValue selectTrue = emitRegisterLoad(ins.src[1], ins.dst[0].mask);
const DxbcRegisterValue selectFalse = emitRegisterLoad(ins.src[2], ins.dst[0].mask);
const uint32_t componentCount = ins.dst[0].mask.setCount();
const uint32_t componentCount = ins.dst[0].mask.popCount();
// We'll compare against a vector of zeroes to generate a
// boolean vector, which in turn will be used by OpSelect
@ -1593,7 +1593,7 @@ namespace dxvk {
emitRegisterLoad(ins.src[1], ins.dst[0].mask),
};
const uint32_t componentCount = ins.dst[0].mask.setCount();
const uint32_t componentCount = ins.dst[0].mask.popCount();
// Condition, which is a boolean vector used
// to select between the ~0u and 0u vectors.
@ -1792,7 +1792,7 @@ namespace dxvk {
if (ins.dst[0].type != DxbcOperandType::Null) {
DxbcRegisterValue quotient;
quotient.type.ctype = ins.dst[0].dataType;
quotient.type.ccount = ins.dst[0].mask.setCount();
quotient.type.ccount = ins.dst[0].mask.popCount();
quotient.id = m_module.opUDiv(
getVectorTypeId(quotient.type),
@ -1805,7 +1805,7 @@ namespace dxvk {
if (ins.dst[1].type != DxbcOperandType::Null) {
DxbcRegisterValue remainder;
remainder.type.ctype = ins.dst[1].dataType;
remainder.type.ccount = ins.dst[1].mask.setCount();
remainder.type.ccount = ins.dst[1].mask.popCount();
remainder.id = m_module.opUMod(
getVectorTypeId(remainder.type),
@ -1836,7 +1836,7 @@ namespace dxvk {
DxbcRegisterValue result;
result.type.ctype = ins.dst[1].dataType;
result.type.ccount = ins.dst[1].mask.setCount();
result.type.ccount = ins.dst[1].mask.popCount();
result.id = m_module.opIMul(
getVectorTypeId(result.type),
src.at(0).id, src.at(1).id);
@ -1863,7 +1863,7 @@ namespace dxvk {
DxbcRegisterValue result;
result.type.ctype = ins.dst[0].dataType;
result.type.ccount = ins.dst[0].mask.setCount();
result.type.ccount = ins.dst[0].mask.popCount();
switch (ins.op) {
case DxbcOpcode::IShl:
@ -3705,7 +3705,7 @@ namespace dxvk {
DxbcRegSwizzle swizzle,
DxbcRegMask writeMask) {
if (value.type.ccount == 1)
return emitRegisterExtend(value, writeMask.setCount());
return emitRegisterExtend(value, writeMask.popCount());
std::array<uint32_t, 4> indices;
@ -3764,7 +3764,7 @@ namespace dxvk {
const uint32_t typeId = getVectorTypeId(result.type);
if (srcMask.setCount() == 0) {
if (srcMask.popCount() == 0) {
// Nothing to do if the insertion mask is empty
result.id = dstValue.id;
} else if (dstValue.type.ccount == 1) {
@ -4361,7 +4361,7 @@ namespace dxvk {
// Create result vector
DxbcRegisterValue result;
result.type.ctype = DxbcScalarType::Uint32;
result.type.ccount = writeMask.setCount();
result.type.ccount = writeMask.popCount();
result.id = result.type.ccount > 1
? m_module.opCompositeConstruct(getVectorTypeId(result.type),
result.type.ccount, swizzleIds.data())
@ -4587,9 +4587,9 @@ namespace dxvk {
// If the source value consists of only one component,
// it is stored in all components of the destination.
if (value.type.ccount == 1)
value = emitRegisterExtend(value, writeMask.setCount());
value = emitRegisterExtend(value, writeMask.popCount());
if (ptr.type.ccount == writeMask.setCount()) {
if (ptr.type.ccount == writeMask.popCount()) {
// Simple case: We write to the entire register
m_module.opStore(ptr.id, value.id);
} else {
@ -4679,7 +4679,7 @@ namespace dxvk {
}
result.type.ctype = DxbcScalarType::Uint32;
result.type.ccount = writeMask.setCount();
result.type.ccount = writeMask.popCount();
result.id = indices.at(0);
if (indexId > 1) {
@ -5354,7 +5354,7 @@ namespace dxvk {
&& e->registerId != 0xFFFFFFFF /* depth */) {
DxbcRegisterInfo info;
info.type.ctype = e->componentType;
info.type.ccount = e->componentMask.setCount();
info.type.ccount = e->componentMask.popCount();
info.type.alength = 0;
info.sclass = spv::StorageClassOutput;

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@ -150,7 +150,7 @@ namespace dxvk {
return (m_mask >> id) & 1;
}
uint32_t setCount() const {
uint32_t popCount() const {
const uint8_t n[16] = { 0, 1, 1, 2, 1, 2, 2, 3,
1, 2, 2, 3, 2, 3, 3, 4 };
return n[m_mask & 0xF];

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@ -49,6 +49,7 @@ namespace dxvk {
DxbcAnalyzer analyzer(options,
m_shexChunk->version(),
m_isgnChunk, m_osgnChunk,
analysisInfo);
DxbcCompiler compiler(options,