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[dxso] Implement DxsoOpcode::Sgn
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@ -120,6 +120,7 @@ namespace dxvk {
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case DxsoOpcode::Pow:
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case DxsoOpcode::Crs:
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case DxsoOpcode::Abs:
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case DxsoOpcode::Sgn:
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case DxsoOpcode::Nrm:
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case DxsoOpcode::SinCos:
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case DxsoOpcode::Lit:
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@ -1930,6 +1931,10 @@ namespace dxvk {
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result.id = m_module.opFAbs(typeId,
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emitRegisterLoad(src[0], mask).id);
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break;
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case DxsoOpcode::Sgn:
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result.id = m_module.opFSign(typeId,
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emitRegisterLoad(src[0], mask).id);
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break;
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case DxsoOpcode::Nrm: {
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// Nrm is 3D...
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DxsoRegMask srcMask(true, true, true, false);
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