rooty/dxvk
1
0
Fork 0
mirror of https://github.com/doitsujin/dxvk.git synced 2025-02-27 13:54:16 +01:00
Code Issues Projects Releases Wiki Activity

[dxbc] Implemented some new bit-wise logical instructions

Browse Source
This commit is contained in:
Philip Rebohle 2017-12-19 00:45:31 +01:00
parent 2b6cb25675
commit 6df9fc75d2
4 changed files with 128 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
src/dxbc/dxbc_compiler.cpp
View File

@ -622,6 +622,14 @@ namespace dxvk {
const uint32_t typeId = getVectorTypeId(dst.type);
switch (ins.op) {
/////////////////////
// Move instructions
case DxbcOpcode::Mov:
dst.id = src.at(0).id;
break;
/////////////////////////////////////
// ALU operations on float32 numbers
case DxbcOpcode::Add:
dst.id = m_module.opFAdd(typeId,
src.at(0).id, src.at(1).id);
@ -662,10 +670,6 @@ namespace dxvk {
src.at(0).id, src.at(1).id);
break;
case DxbcOpcode::Mov:
dst.id = src.at(0).id;
break;
case DxbcOpcode::Sqrt:
dst.id = m_module.opSqrt(
typeId, src.at(0).id);
@ -676,6 +680,8 @@ namespace dxvk {
typeId, src.at(0).id);
break;
/////////////////////////////////////
// ALU operations on signed integers
case DxbcOpcode::IAdd:
dst.id = m_module.opIAdd(typeId,
src.at(0).id, src.at(1).id);
@ -702,7 +708,29 @@ namespace dxvk {
dst.id = m_module.opSNegate(
typeId, src.at(0).id);
break;
///////////////////////////////////////
// Bit operations on unsigned integers
case DxbcOpcode::And:
dst.id = m_module.opBitwiseAnd(typeId,
src.at(0).id, src.at(1).id);
break;
case DxbcOpcode::Not:
dst.id = m_module.opNot(
typeId, src.at(0).id);
break;
case DxbcOpcode::Or:
dst.id = m_module.opBitwiseOr(typeId,
src.at(0).id, src.at(1).id);
break;
case DxbcOpcode::Xor:
dst.id = m_module.opBitwiseXor(typeId,
src.at(0).id, src.at(1).id);
break;
default:
Logger::warn(str::format(
"DxbcCompiler: Unhandled instruction: ",

23
src/dxbc/dxbc_defs.cpp
View File

@ -10,7 +10,11 @@ namespace dxvk {
{ DxbcOperandKind::SrcReg, DxbcScalarType::Float32 },
} },
/* And */
{ },
{ 3, DxbcInstClass::VectorAlu, {
{ DxbcOperandKind::DstReg, DxbcScalarType::Uint32 },
{ DxbcOperandKind::SrcReg, DxbcScalarType::Uint32 },
{ DxbcOperandKind::SrcReg, DxbcScalarType::Uint32 },
} },
/* Break */
{ 0, DxbcInstClass::ControlFlow },
/* Breakc */
@ -242,9 +246,16 @@ namespace dxvk {
/* Nop */
{ },
/* Not */
{ },
{ 2, DxbcInstClass::VectorAlu, {
{ DxbcOperandKind::DstReg, DxbcScalarType::Uint32 },
{ DxbcOperandKind::SrcReg, DxbcScalarType::Uint32 },
} },
/* Or */
{ },
{ 3, DxbcInstClass::VectorAlu, {
{ DxbcOperandKind::DstReg, DxbcScalarType::Uint32 },
{ DxbcOperandKind::SrcReg, DxbcScalarType::Uint32 },
{ DxbcOperandKind::SrcReg, DxbcScalarType::Uint32 },
} },
/* ResInfo */
{ },
/* Ret */
@ -325,7 +336,11 @@ namespace dxvk {
/* UtoF */
{ },
/* Xor */
{ },
{ 3, DxbcInstClass::VectorAlu, {
{ DxbcOperandKind::DstReg, DxbcScalarType::Uint32 },
{ DxbcOperandKind::SrcReg, DxbcScalarType::Uint32 },
{ DxbcOperandKind::SrcReg, DxbcScalarType::Uint32 },
} },
/* DclResource */
{ 2, DxbcInstClass::Declaration, {
{ DxbcOperandKind::DstReg, DxbcScalarType::Float32 },

58
src/spirv/spirv_module.cpp
View File

@ -581,6 +581,64 @@ namespace dxvk {
}
uint32_t SpirvModule::opBitwiseAnd(
uint32_t resultType,
uint32_t operand1,
uint32_t operand2) {
uint32_t resultId = this->allocateId();
m_code.putIns (spv::OpBitwiseAnd, 5);
m_code.putWord(resultType);
m_code.putWord(resultId);
m_code.putWord(operand1);
m_code.putWord(operand2);
return resultId;
}
uint32_t SpirvModule::opBitwiseOr(
uint32_t resultType,
uint32_t operand1,
uint32_t operand2) {
uint32_t resultId = this->allocateId();
m_code.putIns (spv::OpBitwiseOr, 5);
m_code.putWord(resultType);
m_code.putWord(resultId);
m_code.putWord(operand1);
m_code.putWord(operand2);
return resultId;
}
uint32_t SpirvModule::opBitwiseXor(
uint32_t resultType,
uint32_t operand1,
uint32_t operand2) {
uint32_t resultId = this->allocateId();
m_code.putIns (spv::OpBitwiseXor, 5);
m_code.putWord(resultType);
m_code.putWord(resultId);
m_code.putWord(operand1);
m_code.putWord(operand2);
return resultId;
}
uint32_t SpirvModule::opNot(
uint32_t resultType,
uint32_t operand) {
uint32_t resultId = this->allocateId();
m_code.putIns (spv::OpNot, 4);
m_code.putWord(resultType);
m_code.putWord(resultId);
m_code.putWord(operand);
return resultId;
}
uint32_t SpirvModule::opCompositeConstruct(
uint32_t resultType,
uint32_t valueCount,

19
src/spirv/spirv_module.h
View File

@ -216,6 +216,25 @@ namespace dxvk {
uint32_t resultType,
uint32_t operand);
uint32_t opBitwiseAnd(
uint32_t resultType,
uint32_t operand1,
uint32_t operand2);
uint32_t opBitwiseOr(
uint32_t resultType,
uint32_t operand1,
uint32_t operand2);
uint32_t opBitwiseXor(
uint32_t resultType,
uint32_t operand1,
uint32_t operand2);
uint32_t opNot(
uint32_t resultType,
uint32_t operand);
uint32_t opCompositeConstruct(
uint32_t resultType,
uint32_t valueCount,