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https://github.com/doitsujin/dxvk.git
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[vulkan] Move stage and access mask definitions to header
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@ -2,54 +2,6 @@
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namespace dxvk {
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constexpr static VkAccessFlags AccessReadMask
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= VK_ACCESS_INDIRECT_COMMAND_READ_BIT
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| VK_ACCESS_INDEX_READ_BIT
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| VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
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| VK_ACCESS_UNIFORM_READ_BIT
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| VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
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| VK_ACCESS_SHADER_READ_BIT
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| VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
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| VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
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| VK_ACCESS_TRANSFER_READ_BIT
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| VK_ACCESS_MEMORY_READ_BIT
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| VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT;
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constexpr static VkAccessFlags AccessWriteMask
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= VK_ACCESS_SHADER_WRITE_BIT
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| VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
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| VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
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| VK_ACCESS_TRANSFER_WRITE_BIT
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| VK_ACCESS_MEMORY_WRITE_BIT
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| VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT
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| VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT;
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constexpr static VkAccessFlags AccessDeviceMask
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= AccessWriteMask | AccessReadMask;
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constexpr static VkAccessFlags AccessHostMask
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= VK_ACCESS_HOST_READ_BIT
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| VK_ACCESS_HOST_WRITE_BIT;
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constexpr static VkPipelineStageFlags StageDeviceMask
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= VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
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| VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
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| VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
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| VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
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| VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
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| VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
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| VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
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| VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
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| VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
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| VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
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| VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
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| VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
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| VK_PIPELINE_STAGE_TRANSFER_BIT
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| VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
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| VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
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| VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
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| VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT;
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DxvkBarrierSet:: DxvkBarrierSet(DxvkCmdBuffer cmdBuffer)
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: m_cmdBuffer(cmdBuffer) {
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@ -69,16 +21,16 @@ namespace dxvk {
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DxvkAccessFlags access = this->getAccessTypes(srcAccess);
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m_allBarrierSrcStages |= srcStages;
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m_memBarrier.srcStageMask |= srcStages & StageDeviceMask;
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m_memBarrier.srcAccessMask |= srcAccess & AccessWriteMask;
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m_memBarrier.dstStageMask |= dstStages & StageDeviceMask;
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m_memBarrier.srcStageMask |= srcStages & vk::StageDeviceMask;
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m_memBarrier.srcAccessMask |= srcAccess & vk::AccessWriteMask;
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m_memBarrier.dstStageMask |= dstStages & vk::StageDeviceMask;
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if (access.test(DxvkAccess::Write)) {
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m_memBarrier.dstAccessMask |= dstAccess & AccessDeviceMask;
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m_memBarrier.dstAccessMask |= dstAccess & vk::AccessDeviceMask;
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if (dstAccess & AccessHostMask) {
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m_hostBarrierSrcStages |= srcStages & StageDeviceMask;
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m_hostBarrierDstAccess |= dstAccess & AccessHostMask;
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if (dstAccess & vk::AccessHostMask) {
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m_hostBarrierSrcStages |= srcStages & vk::StageDeviceMask;
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m_hostBarrierDstAccess |= dstAccess & vk::AccessHostMask;
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}
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}
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}
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@ -93,16 +45,16 @@ namespace dxvk {
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DxvkAccessFlags access = this->getAccessTypes(srcAccess);
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m_allBarrierSrcStages |= srcStages;
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m_memBarrier.srcStageMask |= srcStages & StageDeviceMask;
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m_memBarrier.srcAccessMask |= srcAccess & AccessWriteMask;
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m_memBarrier.dstStageMask |= dstStages & StageDeviceMask;
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m_memBarrier.srcStageMask |= srcStages & vk::StageDeviceMask;
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m_memBarrier.srcAccessMask |= srcAccess & vk::AccessWriteMask;
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m_memBarrier.dstStageMask |= dstStages & vk::StageDeviceMask;
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if (access.test(DxvkAccess::Write)) {
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m_memBarrier.dstAccessMask |= dstAccess & AccessDeviceMask;
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m_memBarrier.dstAccessMask |= dstAccess & vk::AccessDeviceMask;
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if (dstAccess & AccessHostMask) {
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m_hostBarrierSrcStages |= srcStages & StageDeviceMask;
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m_hostBarrierDstAccess |= dstAccess & AccessHostMask;
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if (dstAccess & vk::AccessHostMask) {
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m_hostBarrierSrcStages |= srcStages & vk::StageDeviceMask;
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m_hostBarrierDstAccess |= dstAccess & vk::AccessHostMask;
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}
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}
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@ -122,27 +74,27 @@ namespace dxvk {
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VkAccessFlags dstAccess) {
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DxvkAccessFlags access = this->getAccessTypes(srcAccess);
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m_allBarrierSrcStages |= srcStages & StageDeviceMask;
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m_allBarrierSrcStages |= srcStages & vk::StageDeviceMask;
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if (srcLayout == dstLayout) {
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m_memBarrier.srcStageMask |= srcStages & StageDeviceMask;
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m_memBarrier.srcAccessMask |= srcAccess & AccessWriteMask;
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m_memBarrier.dstStageMask |= dstStages & StageDeviceMask;
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m_memBarrier.srcStageMask |= srcStages & vk::StageDeviceMask;
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m_memBarrier.srcAccessMask |= srcAccess & vk::AccessWriteMask;
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m_memBarrier.dstStageMask |= dstStages & vk::StageDeviceMask;
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if (access.test(DxvkAccess::Write)) {
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m_memBarrier.dstAccessMask |= dstAccess;
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if (dstAccess & AccessHostMask) {
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m_hostBarrierSrcStages |= srcStages & StageDeviceMask;
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m_hostBarrierDstAccess |= dstAccess & AccessHostMask;
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if (dstAccess & vk::AccessHostMask) {
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m_hostBarrierSrcStages |= srcStages & vk::StageDeviceMask;
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m_hostBarrierDstAccess |= dstAccess & vk::AccessHostMask;
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}
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}
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} else {
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VkImageMemoryBarrier2 barrier = { VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER_2 };
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barrier.srcStageMask = srcStages & StageDeviceMask;
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barrier.srcAccessMask = srcAccess & AccessWriteMask;
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barrier.dstStageMask = dstStages & StageDeviceMask;
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barrier.dstAccessMask = dstAccess & AccessDeviceMask;
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barrier.srcStageMask = srcStages & vk::StageDeviceMask;
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barrier.srcAccessMask = srcAccess & vk::AccessWriteMask;
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barrier.dstStageMask = dstStages & vk::StageDeviceMask;
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barrier.dstAccessMask = dstAccess & vk::AccessDeviceMask;
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barrier.oldLayout = srcLayout;
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barrier.newLayout = dstLayout;
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barrier.srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED;
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@ -152,9 +104,9 @@ namespace dxvk {
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barrier.subresourceRange.aspectMask = image->formatInfo()->aspectMask;
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m_imgBarriers.push_back(barrier);
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if (dstAccess & AccessHostMask) {
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if (dstAccess & vk::AccessHostMask) {
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m_hostBarrierSrcStages |= srcStages;
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m_hostBarrierDstAccess |= dstAccess & AccessHostMask;
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m_hostBarrierDstAccess |= dstAccess & vk::AccessHostMask;
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}
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access.set(DxvkAccess::Write);
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@ -179,8 +131,8 @@ namespace dxvk {
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m_allBarrierSrcStages |= srcStages;
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VkBufferMemoryBarrier2 barrier = { VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER_2 };
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barrier.srcStageMask = srcStages & StageDeviceMask;
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barrier.srcAccessMask = srcAccess & AccessWriteMask;
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barrier.srcStageMask = srcStages & vk::StageDeviceMask;
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barrier.srcAccessMask = srcAccess & vk::AccessWriteMask;
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barrier.dstStageMask = VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT;
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barrier.dstAccessMask = 0;
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barrier.srcQueueFamilyIndex = srcQueue;
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@ -196,9 +148,9 @@ namespace dxvk {
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barrier.dstAccessMask = dstAccess;
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acquire.m_bufBarriers.push_back(barrier);
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if (dstAccess & AccessHostMask) {
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acquire.m_hostBarrierSrcStages |= srcStages & StageDeviceMask;
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acquire.m_hostBarrierDstAccess |= dstAccess & AccessHostMask;
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if (dstAccess & vk::AccessHostMask) {
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acquire.m_hostBarrierSrcStages |= srcStages & vk::StageDeviceMask;
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acquire.m_hostBarrierDstAccess |= dstAccess & vk::AccessHostMask;
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}
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DxvkAccessFlags access(DxvkAccess::Read, DxvkAccess::Write);
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@ -226,8 +178,8 @@ namespace dxvk {
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m_allBarrierSrcStages |= srcStages;
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VkImageMemoryBarrier2 barrier = { VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER_2 };
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barrier.srcStageMask = srcStages & StageDeviceMask;
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barrier.srcAccessMask = srcAccess & AccessWriteMask;
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barrier.srcStageMask = srcStages & vk::StageDeviceMask;
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barrier.srcAccessMask = srcAccess & vk::AccessWriteMask;
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barrier.dstStageMask = VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT;
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barrier.dstAccessMask = 0;
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barrier.oldLayout = srcLayout;
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@ -248,9 +200,9 @@ namespace dxvk {
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barrier.dstAccessMask = dstAccess;
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acquire.m_imgBarriers.push_back(barrier);
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if (dstAccess & AccessHostMask) {
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acquire.m_hostBarrierSrcStages |= srcStages & StageDeviceMask;
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acquire.m_hostBarrierDstAccess |= dstAccess & AccessHostMask;
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if (dstAccess & vk::AccessHostMask) {
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acquire.m_hostBarrierSrcStages |= srcStages & vk::StageDeviceMask;
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acquire.m_hostBarrierDstAccess |= dstAccess & vk::AccessHostMask;
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}
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DxvkAccessFlags access(DxvkAccess::Read, DxvkAccess::Write);
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@ -391,8 +343,8 @@ namespace dxvk {
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DxvkAccessFlags DxvkBarrierSet::getAccessTypes(VkAccessFlags flags) {
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DxvkAccessFlags result;
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if (flags & AccessReadMask) result.set(DxvkAccess::Read);
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if (flags & AccessWriteMask) result.set(DxvkAccess::Write);
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if (flags & vk::AccessReadMask) result.set(DxvkAccess::Read);
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if (flags & vk::AccessWriteMask) result.set(DxvkAccess::Write);
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return result;
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}
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@ -11,6 +11,54 @@
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namespace dxvk::vk {
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constexpr static VkAccessFlags AccessReadMask
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= VK_ACCESS_INDIRECT_COMMAND_READ_BIT
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| VK_ACCESS_INDEX_READ_BIT
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| VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
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| VK_ACCESS_UNIFORM_READ_BIT
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| VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
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| VK_ACCESS_SHADER_READ_BIT
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| VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
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| VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
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| VK_ACCESS_TRANSFER_READ_BIT
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| VK_ACCESS_MEMORY_READ_BIT
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| VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT;
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constexpr static VkAccessFlags AccessWriteMask
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= VK_ACCESS_SHADER_WRITE_BIT
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| VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
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| VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
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| VK_ACCESS_TRANSFER_WRITE_BIT
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| VK_ACCESS_MEMORY_WRITE_BIT
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| VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT
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| VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT;
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constexpr static VkAccessFlags AccessDeviceMask
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= AccessWriteMask | AccessReadMask;
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constexpr static VkAccessFlags AccessHostMask
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= VK_ACCESS_HOST_READ_BIT
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| VK_ACCESS_HOST_WRITE_BIT;
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constexpr static VkPipelineStageFlags StageDeviceMask
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= VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
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| VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
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| VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
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| VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
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| VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
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| VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
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| VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
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| VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
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| VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
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| VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
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| VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
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| VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
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| VK_PIPELINE_STAGE_TRANSFER_BIT
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| VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
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| VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
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| VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
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| VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT;
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inline VkImageSubresourceRange makeSubresourceRange(
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const VkImageSubresourceLayers& layers) {
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VkImageSubresourceRange range;
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