/*
 * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the Software),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#ifndef __lr10_dev_nvlphyctl_ip_h__
#define __lr10_dev_nvlphyctl_ip_h__
/* This file is autogenerated.  Do not edit */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6                         0x0000281c      /* RW-4R */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_RXCAL                   0:0             /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_RXCAL_OFF               0x00000000      /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_RXCAL_ON                0x00000001      /* RW--V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_INIT_TRAIN              3:3             /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_INIT_TRAIN_NOT_COMPLETE 0x00000001      /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_INIT_TRAIN_COMPLETE     0x00000000      /* RW--V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_CDR_EN_DELAY            26:16           /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_CDR_EN_DELAY_ZERO       0x00000000      /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_CDR_EN_DELAY_SCL        31:27           /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_CDR_EN_DELAY_SCL_ZERO   0x00000000      /* RWE-V */

#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0                      0x00002838      /* R--4R */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_TX_IDDQ_DIS_STS      0:0             /* R--VF */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_TX_SLEEP_DIS_STS     1:1             /* R--VF */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_RXCAL_DONE           2:2             /* R--VF */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_TX_DATA_READY_STS    3:3             /* R--VF */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_TX_DATA_EN_STS       4:4             /* R--VF */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_RX_IDDQ_DIS_STS      5:5             /* R--VF */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_RX_SLEEP_DIS_STS     6:6             /* R--VF */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_RX_DATA_EN_STS       7:7             /* R--VF */

#define NV_NVLPHYCTL_LANE_PAD_CTL_4(i)                        (0x0000284c+(i)*0x40) /* RW-4A */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4__SIZE_1                   5               /*       */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_CAL_EN                 0:0             /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_CAL_EN_OFF             0x00000000      /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_CAL_EN_ON              0x00000001      /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_CAL_DONE               1:1             /* R--VF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EQ_TRAIN_EN            4:4             /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EQ_TRAIN_EN_OFF        0x00000000      /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EQ_TRAIN_EN_ON         0x00000001      /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EQ_TRAIN_DONE          5:5             /* R--VF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EOM_DONE               9:9             /* R--VF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_CAL_OVRD               12:12           /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_CAL_OVRD_OFF           0x00000000      /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_CAL_OVRD_ON            0x00000001      /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EQ_OVRD                13:13           /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EQ_OVRD_OFF            0x00000000      /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EQ_OVRD_ON             0x00000001      /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_PRECODE_INV_OVRD       14:14           /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_PRECODE_INV_OVRD_OFF   0x00000000      /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_PRECODE_INV_OVRD_ON    0x00000001      /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_PRECODE_INV_EN         15:15           /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_PRECODE_INV_EN_OFF     0x00000000      /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_PRECODE_INV_EN_ON      0x00000001      /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EOM_STATUS             31:16           /* R--VF */

#define NV_NVLPHYCTL_LANE_PAD_CTL_8(i)                        (0x00002864+(i)*0x40) /* RW-4A */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8__SIZE_1                   5               /*       */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EOM_OVRD               0:0             /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EOM_OVRD_OFF           0x00000000      /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EOM_OVRD_ON            0x00000001      /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EOM_EN                 1:1             /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EOM_EN_OFF             0x00000000      /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EOM_EN_ON              0x00000001      /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_TRAIN_MODE          27:27           /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_TRAIN_MODE_INIT     0x00000000      /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_RESET_OVRD          28:28           /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_RESET_OVRD_OFF      0x00000000      /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_RESET_OVRD_ON       0x00000001      /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_CDR_RESET_OVRD            29:29           /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_CDR_RESET_OVRD_OFF        0x00000000      /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_CDR_RESET_OVRD_ON         0x00000001      /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_RESET               30:30           /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_RESET_OFF           0x00000000      /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_RESET_ON            0x00000001      /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_CDR_RESET                 31:31           /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_CDR_RESET_OFF             0x00000000      /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_CDR_RESET_ON              0x00000001      /* RWE-V */
#endif // __lr10_dev_nvlphyctl_ip_h__
