/*
 * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the Software),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#ifndef __lr10_dev_npg_ip_h__
#define __lr10_dev_npg_ip_h__
/* This file is autogenerated.  Do not edit */
#define NV_NPG_NPG_INTERRUPT_STATUS                        0x00000400      /* R--4R */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_FNC_OR            0:0             /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_FNC_OR_INIT       0x00000000      /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_INT_STATUS        3:1             /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_INT_STATUS_INIT   0x00000000      /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_INT_STATUS_FATAL  0x00000001      /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_INT_STATUS_NONFATAL 0x00000002    /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_INT_STATUS_CORRECTABLE 0x00000004 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_FNC_OR            4:4             /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_FNC_OR_INIT       0x00000000      /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_INT_STATUS        7:5             /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_INT_STATUS_INIT   0x00000000      /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_INT_STATUS_FATAL  0x00000001      /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_INT_STATUS_NONFATAL 0x00000002    /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_INT_STATUS_CORRECTABLE 0x00000004 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_FNC_OR            8:8             /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_FNC_OR_INIT       0x00000000      /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_INT_STATUS        11:9            /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_INT_STATUS_INIT   0x00000000      /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_INT_STATUS_FATAL  0x00000001      /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_INT_STATUS_NONFATAL 0x00000002    /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_INT_STATUS_CORRECTABLE 0x00000004 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_FNC_OR            12:12           /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_FNC_OR_INIT       0x00000000      /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_INT_STATUS        15:13           /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_INT_STATUS_INIT   0x00000000      /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_INT_STATUS_FATAL  0x00000001      /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_INT_STATUS_NONFATAL 0x00000002    /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_INT_STATUS_CORRECTABLE 0x00000004 /* R---V */

#define NV_NPG_WARMRESET                                   0x00000140      /* RW-4R */
#define NV_NPG_WARMRESET_NPORTWARMRESET                    11:8            /* RWEVF */
#define NV_NPG_WARMRESET_NPORTWARMRESET_INIT               0x0000000f      /* RWE-V */
#define NV_NPG_WARMRESET_NPORTWARMRESET_ASSERT             0x00000000      /* RW--V */
#define NV_NPG_WARMRESET_NPORTWARMRESET_DEASSERT           0x00000001      /* RW--V */

#define NV_NPG_DEBUG_CLEAR                                 0x00000144      /* RW-4R */
#define NV_NPG_DEBUG_CLEAR_CLEAR                           3:0             /* RWIVF */
#define NV_NPG_DEBUG_CLEAR_CLEAR_ASSERT_NPORT_0            0x00000001      /* RW--V */
#define NV_NPG_DEBUG_CLEAR_CLEAR_ASSERT_NPORT_1            0x00000002      /* RW--V */
#define NV_NPG_DEBUG_CLEAR_CLEAR_ASSERT_NPORT_2            0x00000004      /* RW--V */
#define NV_NPG_DEBUG_CLEAR_CLEAR_ASSERT_NPORT_3            0x00000008      /* RW--V */
#define NV_NPG_DEBUG_CLEAR_CLEAR_ASSERT_ALL                0x0000000f      /* RW--V */
#define NV_NPG_DEBUG_CLEAR_CLEAR_DEASSERT                  0x00000000      /* RWI-V */
#define NV_NPG_DEBUG_CLEAR_CMN_CLEAR                       31:31           /* RWIVF */
#define NV_NPG_DEBUG_CLEAR_CMN_CLEAR_ASSERT                0x00000001      /* RW--V */
#define NV_NPG_DEBUG_CLEAR_CMN_CLEAR_DEASSERT              0x00000000      /* RWI-V */

#define NV_NPG_CTRL_PRI_MULTICAST                          0x000000c0      /* RW-4R */
#define NV_NPG_CTRL_PRI_MULTICAST_NPORT_ENABLE             5:0             /* RWEVF */
#define NV_NPG_CTRL_PRI_MULTICAST_NPORT_ENABLE_NO_NPORT_ENABLED 0x00000000 /* RW--V */
#define NV_NPG_CTRL_PRI_MULTICAST_NPORT_ENABLE_PORT0_NPORT_ENABLED 0x00000001 /* RW--V */
#define NV_NPG_CTRL_PRI_MULTICAST_NPORT_ENABLE_PORT1_NPORT_ENABLED 0x00000002 /* RW--V */
#define NV_NPG_CTRL_PRI_MULTICAST_NPORT_ENABLE_PORT01_NPORT_ENABLED 0x00000003 /* RW--V */
#define NV_NPG_CTRL_PRI_MULTICAST_NPORT_ENABLE_PORT2_NPORT_ENABLED 0x00000004 /* RW--V */
#define NV_NPG_CTRL_PRI_MULTICAST_NPORT_ENABLE_PORT02_NPORT_ENABLED 0x00000005 /* RW--V */
#define NV_NPG_CTRL_PRI_MULTICAST_NPORT_ENABLE_PORT3_NPORT_ENABLED 0x00000008 /* RW--V */
#define NV_NPG_CTRL_PRI_MULTICAST_NPORT_ENABLE_ALL_NPORT_ENABLED 0x0000000f /* RWE-V */
#define NV_NPG_CTRL_PRI_MULTICAST_READ_MODE                7:6             /* RWEVF */
#define NV_NPG_CTRL_PRI_MULTICAST_READ_MODE_LOW_SELECTED_BUS 0x00000000    /* RW--V */
#define NV_NPG_CTRL_PRI_MULTICAST_READ_MODE_OR_ALL_BUSSES  0x00000001      /* RW--V */
#define NV_NPG_CTRL_PRI_MULTICAST_READ_MODE_AND_ALL_BUSSES 0x00000002      /* RWE-V */
#define NV_NPG_CTRL_PRI_MULTICAST_READ_MODE_ZEROS          0x00000003      /* RW--V */
#define NV_NPG_CTRL_PRI_MULTICAST_MCAST_ENABLED            13:8            /* R-EVF */
#define NV_NPG_CTRL_PRI_MULTICAST_MCAST_ENABLED_NO_MCAST_ENABLED 0x00000000 /* R---V */
#define NV_NPG_CTRL_PRI_MULTICAST_MCAST_ENABLED_PORT0_MCAST_ENABLED 0x00000001 /* R---V */
#define NV_NPG_CTRL_PRI_MULTICAST_MCAST_ENABLED_PORT1_MCAST_ENABLED 0x00000002 /* R---V */
#define NV_NPG_CTRL_PRI_MULTICAST_MCAST_ENABLED_PORT01_MCAST_ENABLED 0x00000003 /* R---V */
#define NV_NPG_CTRL_PRI_MULTICAST_MCAST_ENABLED_PORT2_MCAST_ENABLED 0x00000004 /* R---V */
#define NV_NPG_CTRL_PRI_MULTICAST_MCAST_ENABLED_PORT02_MCAST_ENABLED 0x00000005 /* R---V */
#define NV_NPG_CTRL_PRI_MULTICAST_MCAST_ENABLED_PORT3_MCAST_ENABLED 0x00000008 /* R---V */
#define NV_NPG_CTRL_PRI_MULTICAST_MCAST_ENABLED_ALL_MCAST_ENABLED 0x0000000f /* R-E-V */
#endif // __lr10_dev_npg_ip_h__
