/*
 * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 */

/*!
 * Provides the implementation for all GB100+ specific KernelFalcon
 * interfaces.
 */

#include "gpu/falcon/kernel_falcon.h"

#include "published/blackwell/gb100/dev_falcon_v4.h"

/*!
 * Helper function to get IRQSTAT ECC bit
 *
 * @return FALCON_IRQSTAT_EXT_EXTIRQ7 bit set
 */
NvU32
kflcnGetEccInterruptMask_GB100
(
    OBJGPU       *pGpu,
    KernelFalcon *pKernelFlcn
)
{
    return REF_DEF(NV_PFALCON_FALCON_IRQSTAT_EXT_EXTIRQ7, _TRUE);
}
