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89 lines
3.5 KiB
C
89 lines
3.5 KiB
C
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/*******************************************************************************
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Copyright (c) 2018-2019 NVIDIA Corporation
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to
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deal in the Software without restriction, including without limitation the
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rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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sell copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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DEALINGS IN THE SOFTWARE.
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*******************************************************************************/
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#ifndef __UVM_HAL_AMPERE_FAULT_BUFFER_H__
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#define __UVM_HAL_AMPERE_FAULT_BUFFER_H__
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#include "nvtypes.h"
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#include "uvm_common.h"
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#include "uvm_gpu.h"
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// There are up to 8 TPCs per GPC in Ampere, and there are 2 LTP uTLB per TPC.
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// Besides, there is one RGG uTLB per GPC. Each TPC has a number of clients
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// that can make requests to its uTLBs: 1xTPCCS, 1xPE, 2xT1. Requests from
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// these units are routed as follows to the 2 LTP uTLBs:
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//
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// -------- ---------
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// | T1_0 | -----------------> | uTLB0 |
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// -------- ---------
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//
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// -------- ---------
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// | T1_1 | -----------------> | uTLB1 |
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// -------- --------> ---------
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// | ^
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// ------- | |
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// | PE | ----------- |
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// ------- |
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// |
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// --------- |
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// | TPCCS | -----------------------
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// ---------
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//
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//
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// The client ids are local to their GPC and the id mapping is linear across
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// TPCs: TPC_n has TPCCS_n, PE_n, T1_p, and T1_q, where p=2*n and q=p+1.
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//
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// NV_PFAULT_CLIENT_GPC_LTP_UTLB_n and NV_PFAULT_CLIENT_GPC_RGG_UTLB enums can
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// be ignored. These will never be reported in a fault message, and should
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// never be used in an invalidate. Therefore, we define our own values.
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typedef enum {
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UVM_AMPERE_GPC_UTLB_ID_RGG = 0,
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UVM_AMPERE_GPC_UTLB_ID_LTP0 = 1,
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UVM_AMPERE_GPC_UTLB_ID_LTP1 = 2,
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UVM_AMPERE_GPC_UTLB_ID_LTP2 = 3,
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UVM_AMPERE_GPC_UTLB_ID_LTP3 = 4,
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UVM_AMPERE_GPC_UTLB_ID_LTP4 = 5,
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UVM_AMPERE_GPC_UTLB_ID_LTP5 = 6,
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UVM_AMPERE_GPC_UTLB_ID_LTP6 = 7,
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UVM_AMPERE_GPC_UTLB_ID_LTP7 = 8,
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UVM_AMPERE_GPC_UTLB_ID_LTP8 = 9,
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UVM_AMPERE_GPC_UTLB_ID_LTP9 = 10,
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UVM_AMPERE_GPC_UTLB_ID_LTP10 = 11,
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UVM_AMPERE_GPC_UTLB_ID_LTP11 = 12,
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UVM_AMPERE_GPC_UTLB_ID_LTP12 = 13,
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UVM_AMPERE_GPC_UTLB_ID_LTP13 = 14,
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UVM_AMPERE_GPC_UTLB_ID_LTP14 = 15,
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UVM_AMPERE_GPC_UTLB_ID_LTP15 = 16,
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UVM_AMPERE_GPC_UTLB_COUNT,
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} uvm_ampere_gpc_utlb_id_t;
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static NvU32 uvm_ampere_get_utlbs_per_gpc(uvm_parent_gpu_t *parent_gpu)
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{
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NvU32 utlbs = parent_gpu->rm_info.maxTpcPerGpcCount * 2 + 1;
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UVM_ASSERT(utlbs <= UVM_AMPERE_GPC_UTLB_COUNT);
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return utlbs;
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}
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#endif
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