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https://github.com/NVIDIA/open-gpu-kernel-modules.git
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81 lines
2.7 KiB
C
81 lines
2.7 KiB
C
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _NV_IBMNPU_H_
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#define _NV_IBMNPU_H_
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#if defined(NVCPU_PPC64LE)
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#include "ibmnpu_linux.h"
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#define NV_MAX_ATTACHED_IBMNPUS 6
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typedef struct nv_npu_numa_info
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{
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/*
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* 47-bit NVIDIA 'system physical address': the hypervisor real 56-bit
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* address with NVLink address compression scheme applied.
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*/
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NvU64 compr_sys_phys_addr;
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/*
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* 56-bit NVIDIA 'guest physical address'/host virtual address. On
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* unvirtualized systems, applying the NVLink address compression scheme
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* to this address should be the same as compr_sys_phys_addr.
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*/
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NvU64 guest_phys_addr;
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/*
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* L1 data cache block size on P9 - needed to manually flush/invalidate the
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* NUMA region from the CPU caches after offlining.
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*/
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NvU32 l1d_cache_block_size;
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} nv_npu_numa_info_t;
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struct nv_ibmnpu_info
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{
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NvU8 dev_count;
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NvU8 initialized_dev_count;
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struct pci_dev *devs[NV_MAX_ATTACHED_IBMNPUS];
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ibmnpu_genregs_info_t genregs;
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nv_npu_numa_info_t numa_info;
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};
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/*
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* TODO: These parameters are specific to Volta/P9 configurations, and may
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* need to be determined dynamically in the future.
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*/
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static const NvU32 nv_volta_addr_space_width = 37;
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static const NvU32 nv_volta_dma_addr_size = 47;
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#endif
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void nv_init_ibmnpu_info(nv_state_t *nv);
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void nv_destroy_ibmnpu_info(nv_state_t *nv);
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int nv_init_ibmnpu_devices(nv_state_t *nv);
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void nv_unregister_ibmnpu_devices(nv_state_t *nv);
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int nv_get_ibmnpu_chip_id(nv_state_t *nv);
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void nv_ibmnpu_cache_flush_numa_region(nv_state_t *nv);
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#endif
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