2022-05-09 22:18:59 +02:00
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/*******************************************************************************
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2022-10-10 23:59:24 +02:00
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Copyright (c) 2015-2022 NVIDIA Corporation
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2022-05-09 22:18:59 +02:00
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to
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deal in the Software without restriction, including without limitation the
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rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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sell copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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DEALINGS IN THE SOFTWARE.
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*******************************************************************************/
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#ifndef __UVM_CHANNEL_H__
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#define __UVM_CHANNEL_H__
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#include "nv_uvm_types.h"
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#include "uvm_forward_decl.h"
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#include "uvm_gpu_semaphore.h"
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#include "uvm_pushbuffer.h"
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#include "uvm_tracker.h"
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//
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// UVM channels
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//
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// A channel manager is created as part of the GPU addition. This involves
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// creating channels for each of the supported types (uvm_channel_type_t) in
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// separate channel pools possibly using different CE instances in the HW. Each
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// channel has a uvm_gpu_tracking_semaphore_t and a set of uvm_gpfifo_entry_t
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// (one per each HW GPFIFO entry) allowing to track completion of pushes on the
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// channel.
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//
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// Beginning a push on a channel implies reserving a GPFIFO entry in that
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// channel and hence there can only be as many on-going pushes per channel as
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// there are free GPFIFO entries. This ensures that ending a push won't have to
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// wait for a GPFIFO entry to free up.
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//
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2022-09-20 22:54:59 +02:00
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#define UVM_CHANNEL_NUM_GPFIFO_ENTRIES_DEFAULT 1024
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#define UVM_CHANNEL_NUM_GPFIFO_ENTRIES_MIN 32
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#define UVM_CHANNEL_NUM_GPFIFO_ENTRIES_MAX (1024 * 1024)
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// Semaphore payloads cannot advance too much between calls to
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// uvm_gpu_tracking_semaphore_update_completed_value(). In practice the jumps
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// are bound by gpfifo sizing as we have to update the completed value to
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// reclaim gpfifo entries. Set a limit based on the max gpfifo entries we could
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// ever see.
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//
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// Logically this define belongs to uvm_gpu_semaphore.h but it depends on the
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// channel GPFIFO sizing defined here so it's easiest to just have it here as
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// uvm_channel.h includes uvm_gpu_semaphore.h.
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#define UVM_GPU_SEMAPHORE_MAX_JUMP (2 * UVM_CHANNEL_NUM_GPFIFO_ENTRIES_MAX)
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// Channel types
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typedef enum
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{
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// CPU to GPU copies
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UVM_CHANNEL_TYPE_CPU_TO_GPU,
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// GPU to CPU copies
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UVM_CHANNEL_TYPE_GPU_TO_CPU,
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// Memsets and copies within the GPU
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UVM_CHANNEL_TYPE_GPU_INTERNAL,
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// Memops and small memsets/copies for writing PTEs
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UVM_CHANNEL_TYPE_MEMOPS,
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// GPU to GPU peer copies
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UVM_CHANNEL_TYPE_GPU_TO_GPU,
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UVM_CHANNEL_TYPE_CE_COUNT,
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// ^^^^^^
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// Channel types backed by a CE.
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UVM_CHANNEL_TYPE_COUNT = UVM_CHANNEL_TYPE_CE_COUNT,
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} uvm_channel_type_t;
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typedef enum
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{
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// A pool that contains CE channels owned by UVM.
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UVM_CHANNEL_POOL_TYPE_CE = (1 << 0),
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// A proxy pool contains only proxy channels, so it only exists in SR-IOV
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// heavy. The pool is only used for UVM_CHANNEL_TYPE_MEMOPS pushes.
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//
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// A proxy channel is a privileged CE channel owned by the vGPU plugin. A
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// proxy channel cannot be manipulated directly by the UVM driver, who
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// instead can only submit work to it by invoking an RM API.
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//
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// There is a single proxy pool and channel per GPU.
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UVM_CHANNEL_POOL_TYPE_CE_PROXY = (1 << 1),
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UVM_CHANNEL_POOL_TYPE_COUNT = 2,
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// A mask used to select pools of any type.
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UVM_CHANNEL_POOL_TYPE_MASK = ((1U << UVM_CHANNEL_POOL_TYPE_COUNT) - 1)
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} uvm_channel_pool_type_t;
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typedef enum
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{
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// Push-based GPFIFO entry
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UVM_GPFIFO_ENTRY_TYPE_NORMAL,
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// Control GPFIFO entry, i.e., the LENGTH field is zero, not associated with
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// a push.
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UVM_GPFIFO_ENTRY_TYPE_CONTROL
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} uvm_gpfifo_entry_type_t;
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struct uvm_gpfifo_entry_struct
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{
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uvm_gpfifo_entry_type_t type;
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// Channel tracking semaphore value that indicates completion of
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// this entry.
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NvU64 tracking_semaphore_value;
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// The following fields are only valid when type is
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// UVM_GPFIFO_ENTRY_TYPE_NORMAL.
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// Offset of the pushbuffer in the pushbuffer allocation used by
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// this entry.
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NvU32 pushbuffer_offset;
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// Size of the pushbuffer used for this entry.
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NvU32 pushbuffer_size;
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// List node used by the pushbuffer tracking
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struct list_head pending_list_node;
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// Push info for the pending push that used this GPFIFO entry
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uvm_push_info_t *push_info;
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};
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// A channel pool is a set of channels that use the same engine. For example,
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// all channels in a CE pool share the same (logical) Copy Engine.
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typedef struct
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{
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// Owning channel manager
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uvm_channel_manager_t *manager;
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// Channels in this pool
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uvm_channel_t *channels;
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// Number of elements in the channel array
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NvU32 num_channels;
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// Index of the engine associated with the pool (index is an offset from the
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// first engine of the same engine type.)
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unsigned engine_index;
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// Pool type: Refer to the uvm_channel_pool_type_t enum.
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uvm_channel_pool_type_t pool_type;
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// Lock protecting the state of channels in the pool
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union {
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uvm_spinlock_t spinlock;
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uvm_mutex_t mutex;
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};
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2022-05-09 22:18:59 +02:00
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} uvm_channel_pool_t;
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struct uvm_channel_struct
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{
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// Owning pool
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uvm_channel_pool_t *pool;
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// The channel name contains the CE index, and (for UVM internal channels)
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// the HW runlist and channel IDs.
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char name[64];
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// Array of gpfifo entries, one per each HW GPFIFO
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uvm_gpfifo_entry_t *gpfifo_entries;
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// Number of GPFIFO entries in gpfifo_entries
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NvU32 num_gpfifo_entries;
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// Latest GPFIFO entry submitted to the GPU
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// Updated when new pushes are submitted to the GPU in
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// uvm_channel_end_push().
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NvU32 cpu_put;
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// Latest GPFIFO entry completed by the GPU
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// Updated by uvm_channel_update_progress() after checking pending GPFIFOs
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// for completion.
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NvU32 gpu_get;
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// Number of currently on-going gpfifo entries on this channel
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// A new push or control GPFIFO is only allowed to begin on the channel if
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// there is a free GPFIFO entry for it.
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NvU32 current_gpfifo_count;
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// Array of uvm_push_info_t for all pending pushes on the channel
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uvm_push_info_t *push_infos;
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// Array of uvm_push_acquire_info_t for all pending pushes on the channel.
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// Each entry corresponds to the push_infos entry with the same index.
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uvm_push_acquire_info_t *push_acquire_infos;
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// List of uvm_push_info_entry_t that are currently available. A push info
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// entry is not available if it has been assigned to a push
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// (uvm_push_begin), and the GPFIFO entry associated with the push has not
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// been marked as completed.
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struct list_head available_push_infos;
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2022-10-10 23:59:24 +02:00
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// GPU tracking semaphore tracking the work in the channel.
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// Each push on the channel increments the semaphore, see
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// uvm_channel_end_push().
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uvm_gpu_tracking_semaphore_t tracking_sem;
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// RM channel information
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union
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{
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// UVM internal channels
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struct
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{
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// UVM-RM interface handle
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uvmGpuChannelHandle handle;
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// Channel state populated by RM. Includes the GPFIFO, error
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// notifier, work submission information etc.
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UvmGpuChannelInfo channel_info;
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};
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// Proxy channels (SR-IOV heavy only)
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struct
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{
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// UVM-RM interface handle
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UvmGpuPagingChannelHandle handle;
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// Channel state populated by RM. Includes the error notifier.
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UvmGpuPagingChannelInfo channel_info;
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} proxy;
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};
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struct
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{
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struct proc_dir_entry *dir;
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struct proc_dir_entry *info;
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struct proc_dir_entry *pushes;
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} procfs;
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// Information managed by the tools event notification mechanism. Mainly
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// used to keep a list of channels with pending events, which is needed
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// to collect the timestamps of asynchronous operations.
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struct
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{
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struct list_head channel_list_node;
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NvU32 pending_event_count;
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} tools;
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};
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struct uvm_channel_manager_struct
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{
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// The owning GPU
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uvm_gpu_t *gpu;
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// The pushbuffer used for all pushes done with this channel manager
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uvm_pushbuffer_t *pushbuffer;
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// Array of channel pools.
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uvm_channel_pool_t *channel_pools;
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// Number of elements in the pool array
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unsigned num_channel_pools;
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// Mask containing the indexes of the usable Copy Engines. Each usable CE
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// has a pool associated with it, see channel_manager_ce_pool
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DECLARE_BITMAP(ce_mask, UVM_COPY_ENGINE_COUNT_MAX);
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struct
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{
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// Pools to be used by each channel type by default.
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//
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// Transfers of a given type may use a pool different from that in
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// default_for_type[type]. For example, transfers to NvLink GPU
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// peers may instead use the more optimal pool stored in the gpu_to_gpu
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// array
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uvm_channel_pool_t *default_for_type[UVM_CHANNEL_TYPE_COUNT];
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// Optimal pools to use when writing from the owning GPU to its NvLink
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// peers.
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// If there is no optimal pool (the entry is NULL), use default pool
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// default_for_type[UVM_CHANNEL_GPU_TO_GPU] instead.
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uvm_channel_pool_t *gpu_to_gpu[UVM_ID_MAX_GPUS];
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} pool_to_use;
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struct
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{
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struct proc_dir_entry *channels_dir;
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struct proc_dir_entry *pending_pushes;
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} procfs;
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struct
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{
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NvU32 num_gpfifo_entries;
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UVM_BUFFER_LOCATION gpfifo_loc;
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UVM_BUFFER_LOCATION gpput_loc;
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UVM_BUFFER_LOCATION pushbuffer_loc;
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} conf;
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};
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// Create a channel manager for the GPU
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NV_STATUS uvm_channel_manager_create(uvm_gpu_t *gpu, uvm_channel_manager_t **manager_out);
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2022-11-10 17:39:33 +01:00
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void uvm_channel_pool_lock(uvm_channel_pool_t *pool);
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void uvm_channel_pool_unlock(uvm_channel_pool_t *pool);
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void uvm_channel_pool_assert_locked(uvm_channel_pool_t *pool);
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static bool uvm_channel_pool_is_proxy(uvm_channel_pool_t *pool)
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{
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UVM_ASSERT(pool->pool_type < UVM_CHANNEL_POOL_TYPE_MASK);
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return pool->pool_type == UVM_CHANNEL_POOL_TYPE_CE_PROXY;
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}
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2022-05-09 22:18:59 +02:00
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static bool uvm_channel_is_proxy(uvm_channel_t *channel)
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{
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return uvm_channel_pool_is_proxy(channel->pool);
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}
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static bool uvm_channel_is_ce(uvm_channel_t *channel)
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{
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UVM_ASSERT(channel->pool->pool_type < UVM_CHANNEL_POOL_TYPE_MASK);
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return (channel->pool->pool_type == UVM_CHANNEL_POOL_TYPE_CE) || uvm_channel_is_proxy(channel);
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}
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// Proxy channels are used to push page tree related methods, so their channel
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// type is UVM_CHANNEL_TYPE_MEMOPS.
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static uvm_channel_type_t uvm_channel_proxy_channel_type(void)
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{
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return UVM_CHANNEL_TYPE_MEMOPS;
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}
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// Privileged channels support all the Host and engine methods, while
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// non-privileged channels don't support privileged methods.
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//
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// A major limitation of non-privileged CE channels is lack of physical
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// addressing support.
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bool uvm_channel_is_privileged(uvm_channel_t *channel);
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// Destroy the channel manager
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void uvm_channel_manager_destroy(uvm_channel_manager_t *channel_manager);
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// Get the current status of the channel
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// Returns NV_OK if the channel is in a good state and NV_ERR_RC_ERROR
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// otherwise. Notably this never sets the global fatal error.
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NV_STATUS uvm_channel_get_status(uvm_channel_t *channel);
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// Check for channel errors
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// Checks for channel errors by calling uvm_channel_get_status(). If an error
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// occurred, sets the global fatal error and prints errors.
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NV_STATUS uvm_channel_check_errors(uvm_channel_t *channel);
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// Check errors on all channels in the channel manager
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// Also includes uvm_global_get_status
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NV_STATUS uvm_channel_manager_check_errors(uvm_channel_manager_t *channel_manager);
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// Retrieve the GPFIFO entry that caused a channel error
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// The channel has to be in error state prior to calling this function.
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uvm_gpfifo_entry_t *uvm_channel_get_fatal_entry(uvm_channel_t *channel);
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// Update progress of a specific channel
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// Returns the number of still pending GPFIFO entries for that channel.
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// Notably some of the pending GPFIFO entries might be already completed, but
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// the update early-outs after completing a fixed number of them to spread the
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// cost of the updates across calls.
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NvU32 uvm_channel_update_progress(uvm_channel_t *channel);
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// Update progress of all channels
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// Returns the number of still pending GPFIFO entries for all channels.
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// Notably some of the pending GPFIFO entries might be already completed, but
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// the update early-outs after completing a fixed number of them to spread the
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// cost of the updates across calls.
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NvU32 uvm_channel_manager_update_progress(uvm_channel_manager_t *channel_manager);
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// Wait for all channels to idle
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// It waits for anything that is running, but doesn't prevent new work from
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// beginning.
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NV_STATUS uvm_channel_manager_wait(uvm_channel_manager_t *manager);
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// Get the GPU VA of semaphore_channel's tracking semaphore within the VA space
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// associated with access_channel.
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//
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// The channels can belong to different GPUs, the same GPU, or even be
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// identical, in which case uvm_channel_tracking_semaphore_get_gpu_va can be
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// used instead.
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NvU64 uvm_channel_tracking_semaphore_get_gpu_va_in_channel(uvm_channel_t *semaphore_channel,
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uvm_channel_t *access_channel);
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// See above.
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static NvU64 uvm_channel_tracking_semaphore_get_gpu_va(uvm_channel_t *channel)
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{
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return uvm_channel_tracking_semaphore_get_gpu_va_in_channel(channel, channel);
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}
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// Check whether the channel completed a value
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bool uvm_channel_is_value_completed(uvm_channel_t *channel, NvU64 value);
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// Update and get the latest completed value by the channel
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NvU64 uvm_channel_update_completed_value(uvm_channel_t *channel);
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// Select and reserve a channel with the specified type for a push
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NV_STATUS uvm_channel_reserve_type(uvm_channel_manager_t *manager,
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uvm_channel_type_t type,
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uvm_channel_t **channel_out);
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// Select and reserve a channel for a transfer from channel_manager->gpu to
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// dst_gpu.
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NV_STATUS uvm_channel_reserve_gpu_to_gpu(uvm_channel_manager_t *channel_manager,
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uvm_gpu_t *dst_gpu,
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uvm_channel_t **channel_out);
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2022-10-10 23:59:24 +02:00
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// Reserve a specific channel for a push or for a control GPFIFO entry.
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NV_STATUS uvm_channel_reserve(uvm_channel_t *channel, NvU32 num_gpfifo_entries);
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2022-05-09 22:18:59 +02:00
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// Set optimal CE for P2P transfers between manager->gpu and peer
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void uvm_channel_manager_set_p2p_ce(uvm_channel_manager_t *manager, uvm_gpu_t *peer, NvU32 optimal_ce);
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// Begin a push on a previously reserved channel
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// Should be used by uvm_push_*() only.
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NV_STATUS uvm_channel_begin_push(uvm_channel_t *channel, uvm_push_t *push);
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// End a push
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// Should be used by uvm_push_end() only.
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void uvm_channel_end_push(uvm_push_t *push);
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2022-10-10 23:59:24 +02:00
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// Write/send a control GPFIFO to channel. This is not supported by proxy
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// channels.
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// Ordering guarantees:
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// Input: Control GPFIFO entries are guaranteed to be processed by ESCHED after
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// all prior GPFIFO entries and pushbuffers have been fetched, but not
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// necessarily completed.
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// Output ordering: A caller can wait for this control entry to complete with
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// uvm_channel_manager_wait(), or by waiting for any later push in the same
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// channel to complete.
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NV_STATUS uvm_channel_write_ctrl_gpfifo(uvm_channel_t *channel, NvU64 ctrl_fifo_entry_value);
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2022-05-09 22:18:59 +02:00
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const char *uvm_channel_type_to_string(uvm_channel_type_t channel_type);
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const char *uvm_channel_pool_type_to_string(uvm_channel_pool_type_t channel_pool_type);
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void uvm_channel_print_pending_pushes(uvm_channel_t *channel);
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static uvm_gpu_t *uvm_channel_get_gpu(uvm_channel_t *channel)
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{
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return channel->pool->manager->gpu;
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}
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// Index of a channel within the owning pool
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static unsigned uvm_channel_index_in_pool(const uvm_channel_t *channel)
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{
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return channel - channel->pool->channels;
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}
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NvU32 uvm_channel_update_progress_all(uvm_channel_t *channel);
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// Return an arbitrary channel of the given type(s)
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uvm_channel_t *uvm_channel_any_of_type(uvm_channel_manager_t *manager, NvU32 pool_type_mask);
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// Return an arbitrary channel of any type
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static uvm_channel_t *uvm_channel_any(uvm_channel_manager_t *manager)
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{
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return uvm_channel_any_of_type(manager, UVM_CHANNEL_POOL_TYPE_MASK);
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}
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// Helper to iterate over all the channels in a pool.
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#define uvm_for_each_channel_in_pool(channel, pool) \
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for (({UVM_ASSERT(pool->channels); \
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channel = pool->channels;}); \
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channel != pool->channels + pool->num_channels; \
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channel++)
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uvm_channel_pool_t *uvm_channel_pool_first(uvm_channel_manager_t *manager, NvU32 pool_type_mask);
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uvm_channel_pool_t *uvm_channel_pool_next(uvm_channel_manager_t *manager,
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|
|
uvm_channel_pool_t *curr_pool,
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|
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NvU32 pool_type_mask);
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// Helper to iterate over all the channel pools of the given type(s) in a GPU.
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// The pool mask must not be zero.
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#define uvm_for_each_pool_of_type(pool, manager, pool_type_mask) \
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for (pool = uvm_channel_pool_first(manager, pool_type_mask); \
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pool != NULL; \
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pool = uvm_channel_pool_next(manager, pool, pool_type_mask))
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#define uvm_for_each_pool(pool, manager) uvm_for_each_pool_of_type(pool, manager, UVM_CHANNEL_POOL_TYPE_MASK)
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#endif // __UVM_CHANNEL_H__
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