From 4397463e738d2d90aa1164cc5948e723701f7b53 Mon Sep 17 00:00:00 2001 From: Andy Ritger Date: Tue, 28 Feb 2023 11:12:44 -0800 Subject: [PATCH] 530.30.02 --- CHANGELOG.md | 12 + README.md | 8 +- kernel-open/Kbuild | 9 +- kernel-open/common/inc/nv-firmware.h | 14 +- kernel-open/common/inc/nv-hypervisor.h | 24 - kernel-open/common/inc/nv-ioctl.h | 2 +- kernel-open/common/inc/nv-linux.h | 88 +- kernel-open/common/inc/nv-pci.h | 3 + kernel-open/common/inc/nv.h | 13 +- kernel-open/common/inc/nv_uvm_interface.h | 23 +- kernel-open/common/inc/nv_uvm_types.h | 16 +- kernel-open/common/inc/nvkms-kapi.h | 17 +- kernel-open/common/inc/os-interface.h | 1 - kernel-open/common/inc/rm-gpu-ops.h | 1 + kernel-open/conftest.sh | 281 +- kernel-open/nvidia-drm/nvidia-drm-connector.c | 30 + kernel-open/nvidia-drm/nvidia-drm-connector.h | 17 + kernel-open/nvidia-drm/nvidia-drm-crtc.c | 5 +- kernel-open/nvidia-drm/nvidia-drm-crtc.h | 36 +- kernel-open/nvidia-drm/nvidia-drm-drv.c | 527 +- ...a-drm-prime-fence.c => nvidia-drm-fence.c} | 236 +- ...a-drm-prime-fence.h => nvidia-drm-fence.h} | 8 +- kernel-open/nvidia-drm/nvidia-drm-gem.c | 2 +- kernel-open/nvidia-drm/nvidia-drm-helper.c | 14 + kernel-open/nvidia-drm/nvidia-drm-helper.h | 81 +- kernel-open/nvidia-drm/nvidia-drm-ioctl.h | 95 +- kernel-open/nvidia-drm/nvidia-drm.Kbuild | 7 +- .../nvidia-modeset/nvidia-modeset-linux.c | 124 +- .../nvidia-modeset-os-interface.h | 33 - kernel-open/nvidia-modeset/nvkms.h | 17 + kernel-open/nvidia-uvm/clc365.h | 2 +- kernel-open/nvidia-uvm/clc369.h | 2 +- kernel-open/nvidia-uvm/clc3b5.h | 5 +- kernel-open/nvidia-uvm/ctrl2080mc.h | 2 +- .../nvidia-uvm/nvidia-uvm-sources.Kbuild | 14 +- kernel-open/nvidia-uvm/nvidia-uvm.Kbuild | 6 +- kernel-open/nvidia-uvm/uvm.c | 179 +- kernel-open/nvidia-uvm/uvm.h | 32 +- kernel-open/nvidia-uvm/uvm_ampere_ce.c | 6 +- kernel-open/nvidia-uvm/uvm_ampere_host.c | 4 +- kernel-open/nvidia-uvm/uvm_api.h | 13 +- kernel-open/nvidia-uvm/uvm_ce_test.c | 5 +- kernel-open/nvidia-uvm/uvm_channel.c | 240 +- kernel-open/nvidia-uvm/uvm_channel.h | 46 +- kernel-open/nvidia-uvm/uvm_channel_test.c | 36 +- kernel-open/nvidia-uvm/uvm_common.h | 19 + kernel-open/nvidia-uvm/uvm_forward_decl.h | 3 + kernel-open/nvidia-uvm/uvm_global.h | 10 + kernel-open/nvidia-uvm/uvm_gpu.c | 138 +- kernel-open/nvidia-uvm/uvm_gpu.h | 21 +- .../uvm_gpu_non_replayable_faults.c | 2 - .../nvidia-uvm/uvm_gpu_replayable_faults.c | 344 +- kernel-open/nvidia-uvm/uvm_gpu_semaphore.c | 3 +- kernel-open/nvidia-uvm/uvm_hal.c | 106 +- kernel-open/nvidia-uvm/uvm_hal.h | 66 +- kernel-open/nvidia-uvm/uvm_hmm.c | 2824 +- kernel-open/nvidia-uvm/uvm_hmm.h | 294 +- kernel-open/nvidia-uvm/uvm_hmm_sanity_test.c | 90 - kernel-open/nvidia-uvm/uvm_hopper.c | 1 + kernel-open/nvidia-uvm/uvm_hopper_ce.c | 113 +- kernel-open/nvidia-uvm/uvm_linux.h | 21 +- kernel-open/nvidia-uvm/uvm_lock.h | 43 +- kernel-open/nvidia-uvm/uvm_map_external.c | 55 +- kernel-open/nvidia-uvm/uvm_maxwell_ce.c | 69 +- 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+- src/nvidia/generated/g_zbc_api_nvoc.h | 148 +- src/nvidia/generated/rmconfig.h | 6 +- .../kernel/gpu/external_device/dac_p2060.h | 3 + src/nvidia/inc/kernel/gpu/gpu_access.h | 380 +- src/nvidia/inc/kernel/gpu/gpu_acpi_data.h | 3 +- src/nvidia/inc/kernel/gpu/gpu_child_list.h | 166 +- .../inc/kernel/gpu/gpu_shared_data_map.h | 11 +- src/nvidia/inc/kernel/gpu/gsp/gsp_fw_heap.h | 32 + src/nvidia/inc/kernel/gpu/gsp/gsp_init_args.h | 2 + .../inc/kernel/gpu/gsp/gsp_static_config.h | 2 + src/nvidia/inc/kernel/gpu/gsp/message_queue.h | 10 +- .../inc/kernel/gpu/gsp/message_queue_priv.h | 21 +- src/nvidia/inc/kernel/gpu/intr/engine_idx.h | 5 +- .../gpu/mem_mgr/virt_mem_allocator_common.h | 15 +- .../kernel/gpu/mmu/vidmem_access_bit_buffer.h | 3 + src/nvidia/inc/kernel/gpu_mgr/gpu_mgr_sli.h | 59 + src/nvidia/inc/kernel/mem_mgr/ctx_buf_pool.h | 2 +- src/nvidia/inc/kernel/mem_mgr/pool_alloc.h | 2 +- src/nvidia/inc/kernel/os/os_stub.h | 8 - .../platform/platform_request_handler_utils.h | 78 +- src/nvidia/inc/kernel/platform/sli/sli.h | 4 +- src/nvidia/inc/kernel/rmapi/control.h | 15 +- src/nvidia/inc/kernel/rmapi/mapping_list.h | 20 +- src/nvidia/inc/kernel/rmapi/nv_gpu_ops.h | 12 +- src/nvidia/inc/kernel/rmapi/rmapi.h | 11 +- .../kernel/virtualization/common_vgpu_mgr.h | 2 + src/nvidia/inc/lib/base_utils.h | 3 + src/nvidia/inc/lib/protobuf/prb_util.h | 12 +- src/nvidia/inc/libraries/ioaccess/ioaccess.h | 135 +- src/nvidia/inc/libraries/nvoc/object.h | 5 +- src/nvidia/inc/libraries/nvoc/prelude.h | 4 + src/nvidia/inc/libraries/nvoc/runtime.h | 2 + src/nvidia/inc/libraries/resserv/resserv.h | 8 + src/nvidia/inc/libraries/resserv/rs_client.h | 25 + .../inc/libraries/resserv/rs_resource.h | 25 + src/nvidia/inc/libraries/resserv/rs_server.h | 90 +- src/nvidia/inc/libraries/tls/tls.h | 2 +- .../deprecated/rmapi_deprecated_vidheapctrl.c | 64 - .../deprecated/rmapi_gss_legacy_control.c | 3 +- src/nvidia/interface/nv_sriov_defines.h | 9 + src/nvidia/interface/nv_uvm_types.h | 16 +- src/nvidia/interface/nvrm_registry.h | 116 +- src/nvidia/interface/rmapi/src/finn_rm_api.c | 7496 ---- .../interface/rmapi/src/g_finn_rm_api.c | 8887 +++++ src/nvidia/kernel/inc/dev_p2060.h | 8 + src/nvidia/kernel/inc/objrpc.h | 6 - src/nvidia/kernel/inc/vgpu/rpc.h | 32 +- src/nvidia/kernel/inc/vgpu/rpc_global_enums.h | 3 +- src/nvidia/kernel/inc/vgpu/rpc_headers.h | 1 - src/nvidia/kernel/inc/vgpu/sdk-structures.h | 26 +- src/nvidia/kernel/inc/vgpu/vgpu_version.h | 8 +- src/nvidia/kernel/vgpu/nv/rpc.c | 136 +- src/nvidia/src/kernel/core/hal/hal.c | 51 - src/nvidia/src/kernel/core/system.c | 23 +- .../src/kernel/gpu/arch/ada/kern_gpu_ad102.c | 35 +- .../kernel/gpu/arch/ampere/kern_gpu_ga100.c | 70 +- .../kernel/gpu/arch/hopper/kern_gpu_gh100.c | 36 +- .../kernel/gpu/arch/maxwell/kern_gpu_gm107.c | 152 +- .../kernel/gpu/arch/pascal/kern_gpu_gp100.c | 134 + .../kernel/gpu/arch/turing/kern_gpu_tu102.c | 135 +- .../arch/ada/kernel_bif_ad102.c} | 18 +- .../gpu/bif/arch/hopper/kernel_bif_gh100.c | 21 +- .../gpu/bif/arch/maxwell/kernel_bif_gm107.c | 32 + src/nvidia/src/kernel/gpu/bif/kernel_bif.c | 41 +- .../gpu/bus/arch/hopper/kern_bus_gh100.c | 9 +- .../gpu/bus/arch/maxwell/kern_bus_gm107.c | 262 +- .../gpu/bus/arch/pascal/kern_bus_gp100.c | 2 +- .../gpu/bus/arch/volta/kern_bus_gv100.c | 4 +- src/nvidia/src/kernel/gpu/bus/kern_bus.c | 105 +- src/nvidia/src/kernel/gpu/bus/kern_bus_ctrl.c | 12 + .../src/kernel/gpu/bus/kern_bus_vbar2.c | 2 +- src/nvidia/src/kernel/gpu/bus/p2p_api.c | 302 +- .../gpu/ce/arch/hopper/kernel_ce_gh100.c | 51 +- src/nvidia/src/kernel/gpu/ce/kernel_ce.c | 8 +- src/nvidia/src/kernel/gpu/ce/kernel_ce_ctrl.c | 7 +- .../src/kernel/gpu/ce/kernel_ce_shared.c | 5 + src/nvidia/src/kernel/gpu/deferred_api.c | 6 +- src/nvidia/src/kernel/gpu/device.c | 14 - src/nvidia/src/kernel/gpu/device_ctrl.c | 24 + .../kernel/gpu/disp/arch/v02/kern_disp_0207.c | 56 + .../kernel/gpu/disp/arch/v04/kern_disp_0400.c | 209 + .../src/kernel/gpu/disp/disp_capabilities.c | 8 - src/nvidia/src/kernel/gpu/disp/disp_channel.c | 7 + .../kernel/gpu/disp/disp_common_ctrl_acpi.c | 189 +- .../gpu/disp/disp_object_kern_ctrl_minimal.c | 110 +- src/nvidia/src/kernel/gpu/disp/disp_objs.c | 15 +- src/nvidia/src/kernel/gpu/disp/disp_sf_user.c | 9 - src/nvidia/src/kernel/gpu/disp/kern_disp.c | 12 +- .../disp/rg_line_callback/rg_line_callback.c | 5 - .../disp/vblank_callback/vblank_callback.c | 5 - src/nvidia/src/kernel/gpu/eng_state.c | 113 - .../arch/kepler/kern_gsync_p2060.c | 119 +- .../src/kernel/gpu/external_device/gsync.c | 48 +- .../src/kernel/gpu/falcon/kernel_falcon.c | 5 - .../gpu/fifo/arch/ampere/kernel_fifo_ga100.c | 37 +- .../fifo/arch/maxwell/kernel_channel_gm107.c | 38 +- .../arch/maxwell/kernel_channel_group_gm107.c | 62 - .../gpu/fifo/arch/maxwell/kernel_fifo_gm107.c | 187 +- .../gpu/fifo/arch/volta/kernel_fifo_gv100.c | 13 - .../src/kernel/gpu/fifo/channel_descendant.c | 3 +- .../src/kernel/gpu/fifo/kernel_channel.c | 75 +- .../kernel/gpu/fifo/kernel_channel_group.c | 4 +- .../gpu/fifo/kernel_channel_group_api.c | 20 +- .../src/kernel/gpu/fifo/kernel_ctxshare.c | 54 +- src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c | 46 +- .../src/kernel/gpu/fifo/kernel_fifo_ctrl.c | 12 +- .../src/kernel/gpu/fifo/kernel_fifo_init.c | 2 +- .../gpu/fsp/arch/hopper/kern_fsp_gh100.c | 89 +- src/nvidia/src/kernel/gpu/gpu.c | 265 +- src/nvidia/src/kernel/gpu/gpu_access.c | 546 +- src/nvidia/src/kernel/gpu/gpu_fabric_probe.c | 24 +- src/nvidia/src/kernel/gpu/gpu_gspclient.c | 27 +- src/nvidia/src/kernel/gpu/gpu_registry.c | 13 + src/nvidia/src/kernel/gpu/gpu_rmapi.c | 3 + src/nvidia/src/kernel/gpu/gpu_suspend.c | 68 +- src/nvidia/src/kernel/gpu/gpu_timeout.c | 12 +- .../src/kernel/gpu/gpu_user_shared_data.c | 17 +- .../gpu/gr/arch/maxwell/kgraphics_gm200.c | 45 +- .../gpu/gr/arch/pascal/kgraphics_gp100.c | 9 +- .../gpu/gr/arch/turing/kgraphics_tu102.c | 17 + .../src/kernel/gpu/gr/fecs_event_list.c | 28 +- .../src/kernel/gpu/gr/kernel_graphics.c | 90 +- .../kernel/gpu/gr/kernel_graphics_context.c | 190 +- .../kernel/gpu/gr/kernel_graphics_manager.c | 40 +- .../gpu/gsp/arch/ada/kernel_gsp_ad102.c | 24 - .../gpu/gsp/arch/hopper/kernel_gsp_gh100.c | 40 +- .../gsp/arch/turing/kernel_gsp_booter_tu102.c | 28 +- .../gpu/gsp/arch/turing/kernel_gsp_tu102.c | 264 +- .../gsp/arch/turing/kernel_gsp_vbios_tu102.c | 8 +- src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c | 264 +- .../src/kernel/gpu/gsp/message_queue_cpu.c | 372 +- .../hwpm/profiler_v2/kern_profiler_v2_ctrl.c | 129 +- .../gpu/intr/arch/ampere/intr_cpu_ga102.c | 20 +- .../kernel/gpu/intr/arch/ampere/intr_ga100.c | 29 +- .../kernel/gpu/intr/arch/hopper/intr_gh100.c | 89 +- .../gpu/intr/arch/turing/intr_cpu_tu102.c | 26 +- .../intr/arch/turing/intr_nonstall_tu102.c | 160 +- .../gpu/intr/arch/turing/intr_sriov_tu102.c | 41 - .../kernel/gpu/intr/arch/turing/intr_tu102.c | 340 +- src/nvidia/src/kernel/gpu/intr/intr.c | 114 +- src/nvidia/src/kernel/gpu/mc/kernel_mc.c | 2 +- .../gpu/mem_mgr/arch/ampere/mem_mgr_ga100.c | 15 + .../gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c | 15 +- .../mem_mgr/arch/maxwell/mem_utils_gm107.c | 14 +- .../arch/maxwell/virt_mem_allocator_gm107.c | 205 +- src/nvidia/src/kernel/gpu/mem_mgr/heap.c | 6 +- src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c | 44 +- src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c | 179 +- .../src/kernel/gpu/mem_mgr/mem_mgr_pwr_mgmt.c | 9 +- src/nvidia/src/kernel/gpu/mem_mgr/mem_utils.c | 38 +- .../kernel/gpu/mem_mgr/method_notification.c | 8 +- .../gpu/mem_mgr/phys_mem_allocator/numa.c | 29 +- .../src/kernel/gpu/mem_mgr/vaspace_api.c | 48 - .../mem_sys/arch/ampere/kern_mem_sys_ga100.c | 4 +- .../src/kernel/gpu/mem_sys/kern_mem_sys.c | 61 +- .../kernel/gpu/mem_sys/kern_mem_sys_ctrl.c | 8 +- .../gpu/mig_mgr/gpu_instance_subscription.c | 6 + .../kernel/gpu/mig_mgr/kernel_mig_manager.c | 364 +- .../gpu/mmu/arch/hopper/kern_gmmu_gh100.c | 62 + .../gpu/mmu/arch/turing/kern_gmmu_tu102.c | 2 +- .../gpu/mmu/arch/volta/kern_gmmu_gv100.c | 16 +- src/nvidia/src/kernel/gpu/mmu/bar2_walk.c | 21 +- .../src/kernel/gpu/mmu/fault_buffer_ctrl.c | 2 +- src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c | 248 +- .../src/kernel/gpu/mmu/mmu_fault_buffer.c | 6 - .../kernel/gpu/mmu/mmu_fault_buffer_ctrl.c | 102 +- src/nvidia/src/kernel/gpu/mmu/uvm_sw.c | 2 +- .../gpu/mmu/vidmem_access_bit_buffer_v2.c | 40 + .../nvlink/arch/ampere/kernel_nvlink_ga100.c | 5 +- .../nvlink/arch/hopper/kernel_nvlink_gh100.c | 280 +- .../nvlink/arch/pascal/kernel_nvlink_gp100.c | 1 + .../src/kernel/gpu/nvlink/common_nvlinkapi.c | 12 +- .../src/kernel/gpu/nvlink/kernel_nvlink.c | 32 +- .../gpu/nvlink/kernel_nvlinkcorelibcallback.c | 5 +- .../gpu/nvlink/kernel_nvlinkcorelibtrain.c | 30 +- .../gpu/nvlink/kernel_nvlinkoverrides.c | 10 - .../kernel/gpu/nvlink/kernel_nvlinkstate.c | 5 +- .../src/kernel/gpu/perf/kern_perf_boost.c | 2 + .../src/kernel/gpu/perf/kern_perf_pwr.c | 9 +- .../gpu/sec2/arch/turing/kernel_sec2_tu102.c | 12 - src/nvidia/src/kernel/gpu/sec2/kernel_sec2.c | 41 + .../kernel/gpu/subdevice/subdevice_ctrl_fla.c | 2 +- .../gpu/subdevice/subdevice_ctrl_gpu_kernel.c | 43 +- .../gpu/subdevice/subdevice_ctrl_gpu_regops.c | 12 +- src/nvidia/src/kernel/gpu/sw_test.c | 4 +- src/nvidia/src/kernel/gpu/timed_semaphore.c | 12 +- .../gpu/timer/arch/ampere/timer_ga100.c | 4 +- .../gpu/timer/arch/hopper/timer_gh100.c | 4 +- .../gpu/timer/arch/maxwell/timer_gm107.c | 8 +- .../gpu/timer/arch/turing/timer_tu102.c | 16 +- .../kernel/gpu/timer/arch/volta/timer_gv100.c | 4 +- src/nvidia/src/kernel/gpu/timer/timer.c | 148 +- .../kernel/gpu/uvm/arch/turing/uvm_tu102.c | 42 +- .../src/kernel/gpu/uvm/arch/volta/uvm_gv100.c | 16 +- src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c | 252 +- src/nvidia/src/kernel/gpu_mgr/gpu_mgr_sli.c | 598 + src/nvidia/src/kernel/mem_mgr/ctx_buf_pool.c | 27 +- .../src/kernel/mem_mgr/fabric_vaspace.c | 63 +- src/nvidia/src/kernel/mem_mgr/fla_mem.c | 6 +- src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c | 16 +- src/nvidia/src/kernel/mem_mgr/mem.c | 2 +- src/nvidia/src/kernel/mem_mgr/mem_fabric.c | 118 +- src/nvidia/src/kernel/mem_mgr/mem_list.c | 2 +- .../src/kernel/mem_mgr/mem_multicast_fabric.c | 999 +- src/nvidia/src/kernel/mem_mgr/pool_alloc.c | 15 +- src/nvidia/src/kernel/mem_mgr/standard_mem.c | 2 +- src/nvidia/src/kernel/mem_mgr/system_mem.c | 1 - src/nvidia/src/kernel/mem_mgr/video_mem.c | 15 +- src/nvidia/src/kernel/mem_mgr/virtual_mem.c | 50 +- src/nvidia/src/kernel/os/os_init.c | 10 - src/nvidia/src/kernel/os/os_stubs.c | 66 +- src/nvidia/src/kernel/platform/acpi_common.c | 56 +- .../src/kernel/platform/chipset/chipset.c | 40 +- .../kernel/platform/chipset/chipset_pcie.c | 251 +- src/nvidia/src/kernel/platform/cpu.c | 3 - src/nvidia/src/kernel/platform/cpu_arm_def.h | 1 - src/nvidia/src/kernel/platform/hwbc.c | 2 +- .../src/kernel/platform/nbsi/nbsi_init.c | 105 +- src/nvidia/src/kernel/platform/p2p/p2p_caps.c | 2 +- src/nvidia/src/kernel/platform/sli/sli.c | 287 + src/nvidia/src/kernel/rmapi/alloc_free.c | 91 +- src/nvidia/src/kernel/rmapi/client.c | 2 +- src/nvidia/src/kernel/rmapi/client_resource.c | 132 +- .../src/kernel/rmapi/client_resource_sli.c | 52 + src/nvidia/src/kernel/rmapi/control.c | 72 +- .../src/kernel/rmapi/embedded_param_copy.c | 41 +- src/nvidia/src/kernel/rmapi/entry_points.h | 6 +- src/nvidia/src/kernel/rmapi/event_buffer.c | 6 +- src/nvidia/src/kernel/rmapi/mapping_cpu.c | 1 - src/nvidia/src/kernel/rmapi/mapping_list.c | 509 +- src/nvidia/src/kernel/rmapi/nv_gpu_ops.c | 249 +- src/nvidia/src/kernel/rmapi/param_copy.c | 4 + src/nvidia/src/kernel/rmapi/resource.c | 65 +- src/nvidia/src/kernel/rmapi/resource_desc.h | 27 +- .../src/kernel/rmapi/resource_desc_flags.h | 58 + src/nvidia/src/kernel/rmapi/resource_list.h | 289 +- src/nvidia/src/kernel/rmapi/rmapi.c | 34 +- src/nvidia/src/kernel/rmapi/rmapi_cache.c | 722 +- src/nvidia/src/kernel/rmapi/rmapi_finn.c | 334 + src/nvidia/src/kernel/rmapi/rmapi_stubs.c | 8 +- src/nvidia/src/kernel/rmapi/rpc_common.c | 2 +- .../kernel/virtualization/common_vgpu_mgr.c | 2 + .../virtualization/kernel_hostvgpudeviceapi.c | 10 + src/nvidia/src/lib/base_utils.c | 38 + src/nvidia/src/lib/protobuf/prbutil.c | 12 +- src/nvidia/src/lib/zlib/inflate.c | 2 +- src/nvidia/src/libraries/ioaccess/ioaccess.c | 57 +- src/nvidia/src/libraries/mmu/gmmu_fmt.c | 2 +- src/nvidia/src/libraries/mmu/mmu_walk.c | 4 +- src/nvidia/src/libraries/mmu/mmu_walk_fill.c | 2 +- src/nvidia/src/libraries/nvoc/src/runtime.c | 50 +- .../src/libraries/resserv/src/rs_client.c | 13 +- .../src/libraries/resserv/src/rs_resource.c | 36 +- .../src/libraries/resserv/src/rs_server.c | 266 +- src/nvidia/src/libraries/utils/nvassert.c | 16 + src/nvidia/srcs.mk | 17 +- version.mk | 2 +- 928 files changed, 124728 insertions(+), 88525 deletions(-) rename kernel-open/nvidia-drm/{nvidia-drm-prime-fence.c => nvidia-drm-fence.c} (70%) rename kernel-open/nvidia-drm/{nvidia-drm-prime-fence.h => nvidia-drm-fence.h} (84%) delete mode 100644 kernel-open/nvidia-uvm/uvm_hmm_sanity_test.c create mode 100644 kernel-open/nvidia-uvm/uvm_volta_ce.c delete mode 100644 src/common/inc/swref/published/hopper/gh100/dev_fsp_addendum.h create mode 100644 src/common/nvswitch/kernel/inc/inforom/inforom_nvl_v3_nvswitch.h create mode 100644 src/common/nvswitch/kernel/inc/inforom/inforom_nvl_v4_nvswitch.h create mode 100644 src/common/nvswitch/kernel/inforom/inforom_nvl_v3_nvswitch.c create mode 100644 src/common/nvswitch/kernel/inforom/inforom_nvl_v4_nvswitch.c create mode 100644 src/common/sdk/nvidia/inc/class/clc763.h create mode 100644 src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073common.h create mode 100644 src/common/sdk/nvidia/inc/ctrl/ctrlc763.h rename src/common/sdk/nvidia/inc/{finn_rm_api.h => g_finn_rm_api.h} (94%) rename src/{nvidia/arch/nvalloc/common => common/shared}/inc/nvdevid.h (97%) create mode 100644 src/nvidia-modeset/include/nvkms-dpy-override.h create mode 100644 src/nvidia-modeset/include/nvkms-hw-flip.h create mode 100644 src/nvidia-modeset/include/nvkms-utils-flip.h rename src/nvidia-modeset/kapi/src/{nvkms-kapi-channelevent.c => nvkms-kapi-sync.c} (100%) create mode 100644 src/nvidia-modeset/src/nvkms-conf.c create mode 100644 src/nvidia-modeset/src/nvkms-dpy-override.c create mode 100644 src/nvidia-modeset/src/nvkms-hw-flip.c create mode 100644 src/nvidia-modeset/src/nvkms-utils-flip.c create mode 100644 src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_sr_meta.h create mode 100644 src/nvidia/arch/nvalloc/common/inc/inforom/ifrnvl.h create mode 100644 src/nvidia/arch/nvalloc/unix/src/dynamic-power.c create mode 100644 src/nvidia/generated/g_gpu_access_nvoc.c create mode 100644 src/nvidia/generated/g_gpu_access_nvoc.h create mode 100644 src/nvidia/generated/g_ioaccess_nvoc.c create mode 100644 src/nvidia/generated/g_ioaccess_nvoc.h create mode 100644 src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.c create mode 100644 src/nvidia/inc/kernel/gpu/gsp/gsp_fw_heap.h create mode 100644 src/nvidia/inc/kernel/gpu/mmu/vidmem_access_bit_buffer.h create mode 100644 src/nvidia/inc/kernel/gpu_mgr/gpu_mgr_sli.h delete mode 100644 src/nvidia/interface/rmapi/src/finn_rm_api.c create mode 100644 src/nvidia/interface/rmapi/src/g_finn_rm_api.c create mode 100644 src/nvidia/src/kernel/gpu/arch/pascal/kern_gpu_gp100.c rename src/nvidia/src/kernel/gpu/{pmu/arch/ada/kern_pmu_ad102.c => bif/arch/ada/kernel_bif_ad102.c} (83%) delete mode 100644 src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_group_gm107.c create mode 100644 src/nvidia/src/kernel/gpu/mmu/vidmem_access_bit_buffer_v2.c create mode 100644 src/nvidia/src/kernel/gpu_mgr/gpu_mgr_sli.c create mode 100644 src/nvidia/src/kernel/platform/sli/sli.c create mode 100644 src/nvidia/src/kernel/rmapi/client_resource_sli.c create mode 100644 src/nvidia/src/kernel/rmapi/resource_desc_flags.h create mode 100644 src/nvidia/src/kernel/rmapi/rmapi_finn.c diff --git a/CHANGELOG.md b/CHANGELOG.md index 8b974e657..a9dd71835 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,13 @@ # Changelog +## Release 530 Entries + +### [530.30.02] 2023-02-28 + +#### Fixed + +- Add support for resizable BAR on Linux when NVreg_EnableResizableBar=1 module param is set. [#3](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/3) by @sjkelly + ## Release 525 Entries ### [525.89.02] 2023-02-08 @@ -18,6 +26,10 @@ ### [525.60.11] 2022-11-28 +#### Fixed + +- Fixed nvenc compatibility with usermode clients [#104](https://github.com/NVIDIA/open-gpu-kernel-modules/issues/104) + ### [525.53] 2022-11-10 #### Changed diff --git a/README.md b/README.md index 4f6759565..b0d1807bd 100644 --- a/README.md +++ b/README.md @@ -1,7 +1,7 @@ # NVIDIA Linux Open GPU Kernel Module Source This is the source release of the NVIDIA Linux open GPU kernel modules, -version 525.89.02. +version 530.30.02. ## How to Build @@ -17,7 +17,7 @@ as root: Note that the kernel modules built here must be used with GSP firmware and user-space NVIDIA GPU driver components from a corresponding -525.89.02 driver release. This can be achieved by installing +530.30.02 driver release. This can be achieved by installing the NVIDIA GPU driver from the .run file using the `--no-kernel-modules` option. E.g., @@ -167,7 +167,7 @@ for the target kernel. ## Compatible GPUs The open-gpu-kernel-modules can be used on any Turing or later GPU -(see the table below). However, in the 525.89.02 release, +(see the table below). However, in the 530.30.02 release, GeForce and Workstation support is still considered alpha-quality. To enable use of the open kernel modules on GeForce and Workstation GPUs, @@ -175,7 +175,7 @@ set the "NVreg_OpenRmEnableUnsupportedGpus" nvidia.ko kernel module parameter to 1. For more details, see the NVIDIA GPU driver end user README here: -https://us.download.nvidia.com/XFree86/Linux-x86_64/525.89.02/README/kernel_open.html +https://us.download.nvidia.com/XFree86/Linux-x86_64/530.30.02/README/kernel_open.html In the below table, if three IDs are listed, the first is the PCI Device ID, the second is the PCI Subsystem Vendor ID, and the third is the PCI diff --git a/kernel-open/Kbuild b/kernel-open/Kbuild index e33db9f9e..47490c7d8 100644 --- a/kernel-open/Kbuild +++ b/kernel-open/Kbuild @@ -70,9 +70,13 @@ $(foreach _module, $(NV_KERNEL_MODULES), \ EXTRA_CFLAGS += -I$(src)/common/inc EXTRA_CFLAGS += -I$(src) -EXTRA_CFLAGS += -Wall -MD $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-error -Wno-format-extra-args +EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-error -Wno-format-extra-args EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM -EXTRA_CFLAGS += -DNV_VERSION_STRING=\"525.89.02\" +EXTRA_CFLAGS += -DNV_VERSION_STRING=\"530.30.02\" + +ifneq ($(SYSSRCHOST1X),) + EXTRA_CFLAGS += -I$(SYSSRCHOST1X) +endif EXTRA_CFLAGS += -Wno-unused-function @@ -259,6 +263,7 @@ NV_HEADER_PRESENCE_TESTS = \ linux/platform/tegra/dce/dce-client-ipc.h \ linux/nvhost.h \ linux/nvhost_t194.h \ + linux/host1x-next.h \ asm/book3s/64/hash-64k.h \ asm/set_memory.h \ asm/prom.h \ diff --git a/kernel-open/common/inc/nv-firmware.h b/kernel-open/common/inc/nv-firmware.h index 3ddade5b7..d5f161bc3 100644 --- a/kernel-open/common/inc/nv-firmware.h +++ b/kernel-open/common/inc/nv-firmware.h @@ -81,12 +81,12 @@ static inline const char *nv_firmware_path( { switch (fw_chip_family) { - case NV_FIRMWARE_CHIP_FAMILY_AD10X: - return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_ad10x.bin"); + case NV_FIRMWARE_CHIP_FAMILY_AD10X: // fall through + case NV_FIRMWARE_CHIP_FAMILY_GA10X: + return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_ga10x.bin"); case NV_FIRMWARE_CHIP_FAMILY_GH100: // fall through case NV_FIRMWARE_CHIP_FAMILY_GA100: // fall through - case NV_FIRMWARE_CHIP_FAMILY_GA10X: // fall through case NV_FIRMWARE_CHIP_FAMILY_TU11X: // fall through case NV_FIRMWARE_CHIP_FAMILY_TU10X: return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_tu10x.bin"); @@ -100,12 +100,12 @@ static inline const char *nv_firmware_path( { switch (fw_chip_family) { - case NV_FIRMWARE_CHIP_FAMILY_AD10X: - return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_log_ad10x.bin"); + case NV_FIRMWARE_CHIP_FAMILY_AD10X: // fall through + case NV_FIRMWARE_CHIP_FAMILY_GA10X: + return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_log_ga10x.bin"); case NV_FIRMWARE_CHIP_FAMILY_GH100: // fall through case NV_FIRMWARE_CHIP_FAMILY_GA100: // fall through - case NV_FIRMWARE_CHIP_FAMILY_GA10X: // fall through case NV_FIRMWARE_CHIP_FAMILY_TU11X: // fall through case NV_FIRMWARE_CHIP_FAMILY_TU10X: return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_log_tu10x.bin"); @@ -125,7 +125,7 @@ static inline const char *nv_firmware_path( // which will then be invoked (at the top-level) for each // gsp_*.bin (but not gsp_log_*.bin) #if defined(NV_FIRMWARE_DECLARE_GSP_FILENAME) -NV_FIRMWARE_DECLARE_GSP_FILENAME("gsp_ad10x.bin") +NV_FIRMWARE_DECLARE_GSP_FILENAME("gsp_ga10x.bin") NV_FIRMWARE_DECLARE_GSP_FILENAME("gsp_tu10x.bin") #endif // defined(NV_FIRMWARE_DECLARE_GSP_FILENAME) diff --git a/kernel-open/common/inc/nv-hypervisor.h b/kernel-open/common/inc/nv-hypervisor.h index 6ee37f76c..422f258b2 100644 --- a/kernel-open/common/inc/nv-hypervisor.h +++ b/kernel-open/common/inc/nv-hypervisor.h @@ -90,30 +90,6 @@ typedef enum VGPU_DEVICE_STATE_E NV_VGPU_DEV_IN_USE = 2 } VGPU_DEVICE_STATE; -typedef enum _VMBUS_CMD_TYPE -{ - VMBUS_CMD_TYPE_INVALID = 0, - VMBUS_CMD_TYPE_SETUP = 1, - VMBUS_CMD_TYPE_SENDPACKET = 2, - VMBUS_CMD_TYPE_CLEANUP = 3, -} VMBUS_CMD_TYPE; - -typedef struct -{ - NvU32 request_id; - NvU32 page_count; - NvU64 *pPfns; - void *buffer; - NvU32 bufferlen; -} vmbus_send_packet_cmd_params; - - -typedef struct -{ - NvU32 override_sint; - NvU8 *nv_guid; -} vmbus_setup_cmd_params; - /* * Function prototypes */ diff --git a/kernel-open/common/inc/nv-ioctl.h b/kernel-open/common/inc/nv-ioctl.h index ffd1dee87..f2c1aab62 100644 --- a/kernel-open/common/inc/nv-ioctl.h +++ b/kernel-open/common/inc/nv-ioctl.h @@ -104,7 +104,7 @@ typedef struct nv_ioctl_rm_api_version #define NV_RM_API_VERSION_CMD_STRICT 0 #define NV_RM_API_VERSION_CMD_RELAXED '1' -#define NV_RM_API_VERSION_CMD_OVERRIDE '2' +#define NV_RM_API_VERSION_CMD_QUERY '2' #define NV_RM_API_VERSION_REPLY_UNRECOGNIZED 0 #define NV_RM_API_VERSION_REPLY_RECOGNIZED 1 diff --git a/kernel-open/common/inc/nv-linux.h b/kernel-open/common/inc/nv-linux.h index 792287b3e..90df696e4 100644 --- a/kernel-open/common/inc/nv-linux.h +++ b/kernel-open/common/inc/nv-linux.h @@ -633,6 +633,26 @@ static NvBool nv_numa_node_has_memory(int node_id) free_pages(ptr, order); \ } +static inline pgprot_t nv_adjust_pgprot(pgprot_t vm_prot, NvU32 extra) +{ + pgprot_t prot = __pgprot(pgprot_val(vm_prot) | extra); +#if defined(CONFIG_AMD_MEM_ENCRYPT) && defined(NV_PGPROT_DECRYPTED_PRESENT) + /* + * When AMD memory encryption is enabled, device memory mappings with the + * C-bit set read as 0xFF, so ensure the bit is cleared for user mappings. + * + * If cc_mkdec() is present, then pgprot_decrypted() can't be used. + */ +#if defined(NV_CC_MKDEC_PRESENT) + prot = __pgprot(__sme_clr(pgprot_val(vm_prot))); +#else + prot = pgprot_decrypted(prot); +#endif +#endif + + return prot; +} + #if defined(PAGE_KERNEL_NOENC) #if defined(__pgprot_mask) #define NV_PAGE_KERNEL_NOCACHE_NOENC __pgprot_mask(__PAGE_KERNEL_NOCACHE) @@ -654,7 +674,8 @@ static inline NvUPtr nv_vmap(struct page **pages, NvU32 page_count, #if defined(PAGE_KERNEL_NOENC) if (unencrypted) { - prot = cached ? PAGE_KERNEL_NOENC : NV_PAGE_KERNEL_NOCACHE_NOENC; + prot = cached ? nv_adjust_pgprot(PAGE_KERNEL_NOENC, 0) : + nv_adjust_pgprot(NV_PAGE_KERNEL_NOCACHE_NOENC, 0); } else #endif @@ -939,26 +960,6 @@ static inline int nv_remap_page_range(struct vm_area_struct *vma, return ret; } -static inline pgprot_t nv_adjust_pgprot(pgprot_t vm_prot, NvU32 extra) -{ - pgprot_t prot = __pgprot(pgprot_val(vm_prot) | extra); -#if defined(CONFIG_AMD_MEM_ENCRYPT) && defined(NV_PGPROT_DECRYPTED_PRESENT) - /* - * When AMD memory encryption is enabled, device memory mappings with the - * C-bit set read as 0xFF, so ensure the bit is cleared for user mappings. - * - * If cc_mkdec() is present, then pgprot_decrypted() can't be used. - */ -#if defined(NV_CC_MKDEC_PRESENT) - prot = __pgprot(__sme_clr(pgprot_val(vm_prot))); -#else - prot = pgprot_decrypted(prot); -#endif -#endif - - return prot; -} - static inline int nv_io_remap_page_range(struct vm_area_struct *vma, NvU64 phys_addr, NvU64 size, NvU32 extra_prot) { @@ -1182,7 +1183,7 @@ typedef struct nv_alloc_s { NvBool zeroed : 1; NvBool aliased : 1; NvBool user : 1; - NvBool node0 : 1; + NvBool node : 1; NvBool peer_io : 1; NvBool physical : 1; NvBool unencrypted : 1; @@ -1196,6 +1197,7 @@ typedef struct nv_alloc_s { unsigned int pid; struct page **user_pages; NvU64 guest_id; /* id of guest VM */ + NvS32 node_id; /* Node id for memory allocation when node is set in flags */ void *import_priv; struct sg_table *import_sgt; } nv_alloc_t; @@ -1436,6 +1438,24 @@ struct nv_dma_device { NvBool nvlink; }; +#if defined(NV_LINUX_ACPI_EVENTS_SUPPORTED) +/* + * acpi data storage structure + * + * This structure retains the pointer to the device, + * and any other baggage we want to carry along + * + */ +typedef struct +{ + nvidia_stack_t *sp; + struct acpi_device *device; + struct acpi_handle *handle; + void *notifier_data; + int notify_handler_installed; +} nv_acpi_t; +#endif + /* linux-specific version of old nv_state_t */ /* this is a general os-specific state structure. the first element *must* be the general state structure, for the generic unix-based code */ @@ -1530,8 +1550,13 @@ typedef struct nv_linux_state_s { /* Per-device notifier block for ACPI events */ struct notifier_block acpi_nb; +#if defined(NV_LINUX_ACPI_EVENTS_SUPPORTED) + nv_acpi_t* nv_acpi_object; +#endif + /* Lock serializing ISRs for different SOC vectors */ nv_spinlock_t soc_isr_lock; + void *soc_bh_mutex; struct nv_timer snapshot_timer; nv_spinlock_t snapshot_timer_lock; @@ -1577,24 +1602,6 @@ extern struct rw_semaphore nv_system_pm_lock; extern NvBool nv_ats_supported; -#if defined(NV_LINUX_ACPI_EVENTS_SUPPORTED) -/* - * acpi data storage structure - * - * This structure retains the pointer to the device, - * and any other baggage we want to carry along - * - */ -typedef struct -{ - nvidia_stack_t *sp; - struct acpi_device *device; - struct acpi_handle *handle; - int notify_handler_installed; -} nv_acpi_t; - -#endif - /* * file-private data * hide a pointer to our data structures in a file-private ptr @@ -1744,6 +1751,7 @@ static inline NV_STATUS nv_check_gpu_state(nv_state_t *nv) extern NvU32 NVreg_EnableUserNUMAManagement; extern NvU32 NVreg_RegisterPCIDriver; +extern NvU32 NVreg_EnableResizableBar; extern NvU32 num_probed_nv_devices; extern NvU32 num_nv_devices; diff --git a/kernel-open/common/inc/nv-pci.h b/kernel-open/common/inc/nv-pci.h index ba33fdb01..2254e7263 100644 --- a/kernel-open/common/inc/nv-pci.h +++ b/kernel-open/common/inc/nv-pci.h @@ -27,6 +27,9 @@ #include #include "nv-linux.h" +#define NV_GPU_BAR1 1 +#define NV_GPU_BAR3 3 + int nv_pci_register_driver(void); void nv_pci_unregister_driver(void); int nv_pci_count_devices(void); diff --git a/kernel-open/common/inc/nv.h b/kernel-open/common/inc/nv.h index 9318609ad..48f46e309 100644 --- a/kernel-open/common/inc/nv.h +++ b/kernel-open/common/inc/nv.h @@ -315,6 +315,7 @@ typedef enum NV_SOC_IRQ_DPAUX_TYPE, NV_SOC_IRQ_GPIO_TYPE, NV_SOC_IRQ_HDACODEC_TYPE, + NV_SOC_IRQ_TCPC2DISP_TYPE, NV_SOC_IRQ_INVALID_TYPE } nv_soc_irq_type_t; @@ -329,6 +330,7 @@ typedef struct nv_soc_irq_info_s { NvU32 gpio_num; NvU32 dpaux_instance; } irq_data; + NvS32 ref_count; } nv_soc_irq_info_t; #define NV_MAX_SOC_IRQS 6 @@ -384,9 +386,11 @@ typedef struct nv_state_t NvS32 current_soc_irq; NvU32 num_soc_irqs; NvU32 hdacodec_irq; + NvU32 tcpc2disp_irq; NvU8 *soc_dcb_blob; NvU32 soc_dcb_size; NvU32 disp_sw_soc_chip_id; + NvBool soc_is_dpalt_mode_supported; NvU32 igpu_stall_irq[NV_IGPU_MAX_STALL_IRQS]; NvU32 igpu_nonstall_irq; @@ -649,7 +653,8 @@ static inline NvBool IS_REG_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length) static inline NvBool IS_FB_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length) { - return ((nv->fb) && (offset >= nv->fb->cpu_address) && + return ((nv->fb) && (nv->fb->size != 0) && + (offset >= nv->fb->cpu_address) && ((offset + (length - 1)) >= offset) && ((offset + (length - 1)) <= (nv->fb->cpu_address + (nv->fb->size - 1)))); } @@ -739,7 +744,7 @@ nv_state_t* NV_API_CALL nv_get_ctl_state (void); void NV_API_CALL nv_set_dma_address_size (nv_state_t *, NvU32 ); NV_STATUS NV_API_CALL nv_alias_pages (nv_state_t *, NvU32, NvU32, NvU32, NvU64, NvU64 *, void **); -NV_STATUS NV_API_CALL nv_alloc_pages (nv_state_t *, NvU32, NvBool, NvU32, NvBool, NvBool, NvU64 *, void **); +NV_STATUS NV_API_CALL nv_alloc_pages (nv_state_t *, NvU32, NvBool, NvU32, NvBool, NvBool, NvS32, NvU64 *, void **); NV_STATUS NV_API_CALL nv_free_pages (nv_state_t *, NvU32, NvBool, NvU32, void *); NV_STATUS NV_API_CALL nv_register_user_pages (nv_state_t *, NvU64, NvU64 *, void *, void **); @@ -915,7 +920,6 @@ NV_STATUS NV_API_CALL rm_write_registry_string (nvidia_stack_t *, nv_state_t * void NV_API_CALL rm_parse_option_string (nvidia_stack_t *, const char *); char* NV_API_CALL rm_remove_spaces (const char *); char* NV_API_CALL rm_string_token (char **, const char); -void NV_API_CALL rm_vgpu_vfio_set_driver_vm(nvidia_stack_t *, NvBool); NV_STATUS NV_API_CALL rm_run_rc_callback (nvidia_stack_t *, nv_state_t *); void NV_API_CALL rm_execute_work_item (nvidia_stack_t *, void *); @@ -985,11 +989,12 @@ const char* NV_API_CALL rm_get_dynamic_power_management_status(nvidia_stack_t *, const char* NV_API_CALL rm_get_gpu_gcx_support(nvidia_stack_t *, nv_state_t *, NvBool); void NV_API_CALL rm_acpi_notify(nvidia_stack_t *, nv_state_t *, NvU32); +void NV_API_CALL rm_acpi_nvpcf_notify(nvidia_stack_t *); NvBool NV_API_CALL rm_is_altstack_in_use(void); /* vGPU VFIO specific functions */ -NV_STATUS NV_API_CALL nv_vgpu_create_request(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU32, NvU16 *, NvU32); +NV_STATUS NV_API_CALL nv_vgpu_create_request(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU32, NvU16 *, NvU32, NvBool *); NV_STATUS NV_API_CALL nv_vgpu_delete(nvidia_stack_t *, const NvU8 *, NvU16); NV_STATUS NV_API_CALL nv_vgpu_get_type_ids(nvidia_stack_t *, nv_state_t *, NvU32 *, NvU32 *, NvBool, NvU8, NvBool); NV_STATUS NV_API_CALL nv_vgpu_get_type_info(nvidia_stack_t *, nv_state_t *, NvU32, char *, int, NvU8); diff --git a/kernel-open/common/inc/nv_uvm_interface.h b/kernel-open/common/inc/nv_uvm_interface.h index bfff72db8..064162049 100644 --- a/kernel-open/common/inc/nv_uvm_interface.h +++ b/kernel-open/common/inc/nv_uvm_interface.h @@ -921,6 +921,23 @@ NV_STATUS nvUvmInterfaceGetNonReplayableFaults(UvmGpuFaultInfo *pFaultInfo, void *pFaultBuffer, NvU32 *numFaults); +/******************************************************************************* + nvUvmInterfaceFlushReplayableFaultBuffer + + This function sends an RPC to GSP in order to flush the HW replayable fault buffer. + + NOTES: + - This function DOES NOT acquire the RM API or GPU locks. That is because + it is called during fault servicing, which could produce deadlocks. + + Arguments: + device[IN] - Device handle associated with the gpu + + Error codes: + NV_ERR_INVALID_ARGUMENT +*/ +NV_STATUS nvUvmInterfaceFlushReplayableFaultBuffer(uvmGpuDeviceHandle device); + /******************************************************************************* nvUvmInterfaceInitAccessCntrInfo @@ -1054,11 +1071,13 @@ void nvUvmInterfaceP2pObjectDestroy(uvmGpuSessionHandle session, hMemory[IN] - Memory handle. offset [IN] - Offset from the beginning of the allocation where PTE mappings should begin. - Should be aligned with pagesize associated + Should be aligned with mappingPagesize + in gpuExternalMappingInfo associated with the allocation. size [IN] - Length of the allocation for which PTEs should be built. - Should be aligned with pagesize associated + Should be aligned with mappingPagesize + in gpuExternalMappingInfo associated with the allocation. size = 0 will be interpreted as the total size of the allocation. diff --git a/kernel-open/common/inc/nv_uvm_types.h b/kernel-open/common/inc/nv_uvm_types.h index 23889d196..0b9895bf8 100644 --- a/kernel-open/common/inc/nv_uvm_types.h +++ b/kernel-open/common/inc/nv_uvm_types.h @@ -110,7 +110,7 @@ typedef struct UvmGpuMemoryInfo_tag NvBool deviceDescendant; // Out: Page size associated with the phys alloc. - NvU32 pageSize; + NvU64 pageSize; // Out: Set to TRUE, if the allocation is contiguous. NvBool contig; @@ -306,6 +306,7 @@ typedef struct UvmGpuChannelAllocParams_tag // interpreted as UVM_GPU_CHANNEL_ENGINE_TYPE NvU32 engineType; + } UvmGpuChannelAllocParams; typedef struct UvmGpuPagingChannelAllocParams_tag @@ -371,7 +372,6 @@ typedef enum UVM_LINK_TYPE_NVLINK_2, UVM_LINK_TYPE_NVLINK_3, UVM_LINK_TYPE_NVLINK_4, - UVM_LINK_TYPE_C2C, } UVM_LINK_TYPE; typedef struct UvmGpuCaps_tag @@ -409,7 +409,7 @@ typedef struct UvmGpuCaps_tag typedef struct UvmGpuAddressSpaceInfo_tag { - NvU32 bigPageSize; + NvU64 bigPageSize; NvBool atsEnabled; @@ -430,7 +430,7 @@ typedef struct UvmGpuAddressSpaceInfo_tag typedef struct UvmGpuAllocInfo_tag { NvU64 gpuPhysOffset; // Returns gpuPhysOffset if contiguous requested - NvU32 pageSize; // default is RM big page size - 64K or 128 K" else use 4K or 2M + NvU64 pageSize; // default is RM big page size - 64K or 128 K" else use 4K or 2M NvU64 alignment; // Virtual alignment NvBool bContiguousPhysAlloc; // Flag to request contiguous physical allocation NvBool bMemGrowsDown; // Causes RM to reserve physical heap from top of FB @@ -516,6 +516,13 @@ typedef struct UvmGpuExternalMappingInfo_tag // In: Size of the buffer to store PTEs (in bytes). NvU64 pteBufferSize; + // In: Page size for mapping + // If this field is passed as 0, the page size + // of the allocation is used for mapping. + // nvUvmInterfaceGetExternalAllocPtes must pass + // this field as zero. + NvU64 mappingPageSize; + // In: Pointer to a buffer to store PTEs. // Out: The interface will fill the buffer with PTEs NvU64 *pteBuffer; @@ -826,6 +833,7 @@ typedef struct UvmGpuFaultInfo_tag // Preallocated stack for functions called from the UVM isr bottom half void *isr_bh_sp; + } nonReplayable; NvHandle faultBufferHandle; } UvmGpuFaultInfo; diff --git a/kernel-open/common/inc/nvkms-kapi.h b/kernel-open/common/inc/nvkms-kapi.h index 0ae71e170..c76493d74 100644 --- a/kernel-open/common/inc/nvkms-kapi.h +++ b/kernel-open/common/inc/nvkms-kapi.h @@ -520,14 +520,23 @@ struct NvKmsKapiFunctionsTable { ); /*! - * Revoke modeset permissions previously granted. This currently applies for all - * previous grant requests for this device. + * Revoke permissions previously granted. Only one (dispIndex, head, + * display) is currently supported. * - * \param [in] device A device returned by allocateDevice(). + * \param [in] device A device returned by allocateDevice(). + * + * \param [in] head head of display. + * + * \param [in] display The display to revoke. * * \return NV_TRUE on success, NV_FALSE on failure. */ - NvBool (*revokePermissions)(struct NvKmsKapiDevice *device); + NvBool (*revokePermissions) + ( + struct NvKmsKapiDevice *device, + NvU32 head, + NvKmsKapiDisplay display + ); /*! * Registers for notification, via diff --git a/kernel-open/common/inc/os-interface.h b/kernel-open/common/inc/os-interface.h index 9ebeeed83..588092f61 100644 --- a/kernel-open/common/inc/os-interface.h +++ b/kernel-open/common/inc/os-interface.h @@ -181,7 +181,6 @@ NV_STATUS NV_API_CALL os_put_page (NvU64 address); NvU32 NV_API_CALL os_get_page_refcount (NvU64 address); NvU32 NV_API_CALL os_count_tail_pages (NvU64 address); void NV_API_CALL os_free_pages_phys (NvU64, NvU32); -NV_STATUS NV_API_CALL os_call_nv_vmbus (NvU32, void *); NV_STATUS NV_API_CALL os_open_temporary_file (void **); void NV_API_CALL os_close_file (void *); NV_STATUS NV_API_CALL os_write_file (void *, NvU8 *, NvU64, NvU64); diff --git a/kernel-open/common/inc/rm-gpu-ops.h b/kernel-open/common/inc/rm-gpu-ops.h index 7aa09151b..cdf26af8b 100644 --- a/kernel-open/common/inc/rm-gpu-ops.h +++ b/kernel-open/common/inc/rm-gpu-ops.h @@ -74,6 +74,7 @@ NV_STATUS NV_API_CALL rm_gpu_ops_own_page_fault_intr(nvidia_stack_t *, nvgpuDevi NV_STATUS NV_API_CALL rm_gpu_ops_init_fault_info(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuFaultInfo_t); NV_STATUS NV_API_CALL rm_gpu_ops_destroy_fault_info(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuFaultInfo_t); NV_STATUS NV_API_CALL rm_gpu_ops_get_non_replayable_faults(nvidia_stack_t *, nvgpuFaultInfo_t, void *, NvU32 *); +NV_STATUS NV_API_CALL rm_gpu_ops_flush_replayable_fault_buffer(nvidia_stack_t *, nvgpuDeviceHandle_t); NV_STATUS NV_API_CALL rm_gpu_ops_has_pending_non_replayable_faults(nvidia_stack_t *, nvgpuFaultInfo_t, NvBool *); NV_STATUS NV_API_CALL rm_gpu_ops_init_access_cntr_info(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuAccessCntrInfo_t); NV_STATUS NV_API_CALL rm_gpu_ops_destroy_access_cntr_info(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuAccessCntrInfo_t); diff --git a/kernel-open/conftest.sh b/kernel-open/conftest.sh index 9f1b7a413..b6a152af6 100755 --- a/kernel-open/conftest.sh +++ b/kernel-open/conftest.sh @@ -8,19 +8,11 @@ cd $SCRIPTDIR CC="$1" ARCH=$2 -ISYSTEM=`$CC -print-file-name=include 2> /dev/null` SOURCES=$3 HEADERS=$SOURCES/include OUTPUT=$4 XEN_PRESENT=1 PREEMPT_RT_PRESENT=0 -KERNEL_ARCH="$ARCH" - -if [ "$ARCH" = "i386" -o "$ARCH" = "x86_64" ]; then - if [ -d "$SOURCES/arch/x86" ]; then - KERNEL_ARCH="x86" - fi -fi # VGX_BUILD parameter defined only for VGX builds (vGPU Host driver) # VGX_KVM_BUILD parameter defined only vGPU builds on KVM hypervisor @@ -69,16 +61,10 @@ test_header_presence() { # NV_LINUX_FENCE_H_PRESENT, and that is either defined or undefined, in the # output (which goes to stdout, just like the rest of this file). - # -MG or -MD can interfere with the use of -M and -M -MG for testing file - # existence; filter out any occurrences from CFLAGS. CFLAGS is intentionally - # wrapped with whitespace in the input to sed(1) so the regex can match zero - # or more occurrences of "-MD" or "-MG", surrounded by whitespace to avoid - # accidental matches with tokens that happen to contain either of those - # strings, without special handling of the beginning or the end of the line. - TEST_CFLAGS=`echo "-E -M $CFLAGS " | sed -e 's/\( -M[DG]\)* / /g'` + TEST_CFLAGS="-E -M $CFLAGS" file="$1" - file_define=NV_`echo $file | tr '/.' '_' | tr '-' '_' | tr 'a-z' 'A-Z'`_PRESENT + file_define=NV_`echo $file | tr '/.\-a-z' '___A-Z'`_PRESENT CODE="#include <$file>" @@ -99,6 +85,7 @@ test_header_presence() { } build_cflags() { + ISYSTEM=`$CC -print-file-name=include 2> /dev/null` BASE_CFLAGS="-O2 -D__KERNEL__ \ -DKBUILD_BASENAME=\"#conftest$$\" -DKBUILD_MODNAME=\"#conftest$$\" \ -nostdinc -isystem $ISYSTEM \ @@ -125,6 +112,14 @@ build_cflags() { MACH_CFLAGS="-I$HEADERS/asm/mach-xen" fi + KERNEL_ARCH="$ARCH" + + if [ "$ARCH" = "i386" -o "$ARCH" = "x86_64" ]; then + if [ -d "$SOURCES/arch/x86" ]; then + KERNEL_ARCH="x86" + fi + fi + SOURCE_HEADERS="$HEADERS" SOURCE_ARCH_HEADERS="$SOURCES/arch/$KERNEL_ARCH/include" OUTPUT_HEADERS="$OUTPUT/include" @@ -764,24 +759,6 @@ compile_test() { compile_check_conftest "$CODE" "NV_VFIO_INFO_ADD_CAPABILITY_HAS_CAP_TYPE_ID_ARGS" "" "types" ;; - vmbus_channel_has_ringbuffer_page) - # - # Check if ringbuffer_page field exist in vmbus_channel structure - # - # Changed in commit 52a42c2a90226dc61c99bbd0cb096deeb52c334b - # ("vmbus: keep pointer to ring buffer page") in v5.0 (2018-09-14) - # - - CODE=" - #include - - int conftest_vmbus_channel_has_ringbuffer_page(void) { - return offsetof(struct vmbus_channel, ringbuffer_page); - }" - - compile_check_conftest "$CODE" "NV_VMBUS_CHANNEL_HAS_RING_BUFFER_PAGE" "" "types" - ;; - nvidia_grid_build) if [ -n "$GRID_BUILD" ]; then echo "#define NV_GRID_BUILD" | append_conftest "generic" @@ -2691,6 +2668,24 @@ compile_test() { fi ;; + enable_apicv) + # + # Determine if enable_apicv boolean is exported by kernel. + # + # Added by commit fdf513e37a3bd ("KVM: x86: Use common 'enable_apicv' + # variable for both APICv and AVIC") + # + CODE=" + $CONFTEST_PREAMBLE + #include + + bool is_enable_apicv_present() { + return enable_apicv; + }" + + compile_check_conftest "$CODE" "NV_ENABLE_APICV_PRESENT" "" "types" + ;; + pci_driver_has_driver_managed_dma) # # Determine if "struct pci_driver" has .driver_managed_dma member. @@ -2774,6 +2769,63 @@ compile_test() { compile_check_conftest "$CODE" "NV_DRM_MASTER_DROP_HAS_FROM_RELEASE_ARG" "" "types" ;; + drm_master_has_leases) + # + # Determine if drm_master has 'leases', 'lessor', 'lessee_idr' fields. + # Also checks for struct drm_mode_revoke_lease. + # + # Added by commits 2ed077e467ee ("drm: Add drm_object lease infrastructure [v5]") + # and 62884cd386b8 ("drm: Add four ioctls for managing drm mode object leases [v7]") + # in v4.15 (2017-10-24) + # + CODE=" + #if defined(NV_DRM_DRMP_H_PRESENT) + #include + #endif + #if defined(NV_DRM_DRM_AUTH_H_PRESENT) + #include + #endif + #include + + int conftest_drm_master_leases(void) { + return offsetof(struct drm_master, leases); + } + int conftest_drm_master_lessor(void) { + return offsetof(struct drm_master, lessor); + } + int conftest_drm_master_lessee_idr(void) { + return offsetof(struct drm_master, lessee_idr); + } + int conftest_drm_mode_revoke_lease(void) { + return offsetof(struct drm_mode_revoke_lease, lessee_id); + }" + + compile_check_conftest "$CODE" "NV_DRM_MASTER_HAS_LEASES" "" "types" + ;; + + drm_file_get_master) + # + # Determine if function drm_file_get_master() is present. + # + # Added by commit 56f0729a510f ("drm: protect drm_master pointers in drm_lease.c") + # in v5.15 (2021-07-20) + # + + CODE=" + #if defined(NV_DRM_DRMP_H_PRESENT) + #include + #endif + #if defined(NV_DRM_DRM_AUTH_H_PRESENT) + #include + #endif + + void conftest_drm_file_get_master(void) { + drm_file_get_master(); + }" + + compile_check_conftest "$CODE" "NV_DRM_FILE_GET_MASTER_PRESENT" "" "functions" + ;; + drm_connector_lookup) # # Determine if function drm_connector_lookup() is present. @@ -3819,6 +3871,40 @@ compile_test() { compile_check_conftest "$CODE" "NV_TEGRA_BPMP_SEND_RECEIVE" "" "functions" ;; + cmd_uphy_display_port_init) + # + # Determine if CMD_UPHY_DISPLAY_PORT_INIT enum present in bpmp-abi header + # This enum is used only in Tegra down-stream kernel. + # + CODE=" + #include + #include + + int conftest_cmd_uphy_display_port_init(void) { + return CMD_UPHY_DISPLAY_PORT_INIT; + } + " + compile_check_conftest "$CODE" "NV_CMD_UPHY_DISPLAY_PORT_INIT_PRESENT" "" "generic" + + ;; + + cmd_uphy_display_port_off) + # + # Determine if CMD_UPHY_DISPLAY_PORT_OFF enum present in bpmp-abi header + # This enum is used only in Tegra down-stream kernel. + # + CODE=" + #include + #include + + int conftest_cmd_uphy_display_port_off(void) { + return CMD_UPHY_DISPLAY_PORT_OFF; + } + " + compile_check_conftest "$CODE" "NV_CMD_UPHY_DISPLAY_PORT_OFF_PRESENT" "" "generic" + + ;; + drm_alpha_blending_available) # # Determine if the DRM subsystem supports alpha blending @@ -4744,6 +4830,21 @@ compile_test() { compile_check_conftest "$CODE" "NV_REMOVE_MEMORY_HAS_NID_ARG" "" "types" ;; + offline_and_remove_memory) + # + # Determine if the offline_and_remove_memory function is present. + # + # Added by commit 08b3acd7a68fc179 ("mm/memory_hotplug: Introduce + # offline_and_remove_memory()") in v5.8-rc1 (2020-06-05) + # + CODE=" + #include + void conftest_offline_and_remove_memory() { + offline_and_remove_memory(); + }" + + compile_check_conftest "$CODE" "NV_OFFLINE_AND_REMOVE_MEMORY_PRESENT" "" "functions" + ;; device_property_read_u64) # @@ -4825,6 +4926,38 @@ compile_test() { fi ;; + of_property_read_variable_u32_array) + # + # Determine if of_property_read_variable_u32_array is present + # + # Added by commit 1df09bcof (" Move OF property and graph API from + # base.c to property.c" + # + # Test if linux/of.h header file inclusion is successful or not, + # depending on that, check for of_property_read_variable_u32_array + # presence + # + echo "$CONFTEST_PREAMBLE + #include + " > conftest$$.c + + $CC $CFLAGS -c conftest$$.c > /dev/null 2>&1 + rm -f conftest$$.c + + if [ -f conftest$$.o ]; then + rm -f conftest$$.o + CODE=" + #include + void conftest_of_property_read_variable_u32_array() { + of_property_read_variable_u32_array(); + }" + + compile_check_conftest "$CODE" "NV_OF_PROPERTY_READ_VARIABLE_U32_ARRAY_PRESENT" "" "functions" + else + echo "#undef NV_OF_PROPERTY_READ_VARIABLE_U32_ARRAY_PRESENT" | append_conftest "functions" + fi + ;; + devm_of_platform_populate) # # Determine if devm_of_platform_populate() function is present @@ -5168,6 +5301,22 @@ compile_test() { compile_check_conftest "$CODE" "NV_MAKE_DEVICE_EXCLUSIVE_RANGE_PRESENT" "" "functions" ;; + migrate_device_range) + # + # Determine if the migrate_device_range() function is present + # + # migrate_device_range() function was added by commit + # e778406b40dbb ("mm/migrate_device.c: add migrate_device_range()") + # in v6.1 (2022-09-28). + CODE=" + #include + int conftest_migrate_device_range(void) { + migrate_device_range(); + }" + + compile_check_conftest "$CODE" "NV_MIGRATE_DEVICE_RANGE_PRESENT" "" "functions" + ;; + ioasid_get) # # Determine if ioasid_get() function is present @@ -5186,6 +5335,25 @@ compile_test() { compile_check_conftest "$CODE" "NV_IOASID_GET_PRESENT" "" "functions" ;; + mm_pasid_set) + # + # Determine if mm_pasid_set() function is present + # + # mm_pasid_set() function was added by commit + # 701fac40384f07197b106136012804c3cae0b3de (iommu/sva: Assign a + # PASID to mm on PASID allocation and free it on mm exit) in v5.18. + # (2022-02-15). + CODE=" + #if defined(NV_LINUX_SCHED_MM_H_PRESENT) + #include + #endif + void conftest_mm_pasid_set(void) { + mm_pasid_set(); + }" + + compile_check_conftest "$CODE" "NV_MM_PASID_SET_PRESENT" "" "functions" + ;; + drm_crtc_state_has_no_vblank) # # Determine if the 'drm_crtc_state' structure has 'no_vblank'. @@ -5453,6 +5621,22 @@ compile_test() { compile_check_conftest "$CODE" "NV_ACPI_VIDEO_BACKLIGHT_USE_NATIVE" "" "functions" ;; + pci_rebar_get_possible_sizes) + # + # Determine if the pci_rebar_get_possible_sizes() function is present. + # + # Added by commit 8fbdbb66f8c10 ("PCI: Add resizable BAR infrastructure + # ") in v5.12 + # + CODE=" + #include + void conftest_pci_rebar_get_possible_sizes(void) { + pci_rebar_get_possible_sizes(); + }" + + compile_check_conftest "$CODE" "NV_PCI_REBAR_GET_POSSIBLE_SIZES_PRESENT" "" "functions" + ;; + drm_connector_has_override_edid) # # Determine if 'struct drm_connector' has an 'override_edid' member. @@ -5475,6 +5659,27 @@ compile_test() { compile_check_conftest "$CODE" "NV_DRM_CONNECTOR_HAS_OVERRIDE_EDID" "" "types" ;; + iommu_sva_bind_device_has_drvdata_arg) + # + # Check if iommu_sva_bind_device() has drvdata parameter. + # + # Removed by commit be51b1d6bbff48c7d1943a8ff1e5a55777807f6e + # ("iommu/sva: Refactoring iommu_sva_bind/unbind_device()") + # in v6.2 (2022-10-31) + # + CODE=" + #include + #include + #include + void conftest_iommu_sva_bind_device_has_drvdata_arg(struct device *dev, + struct mm_struct *mm, + void *drvdata) { + (void) iommu_sva_bind_device(dev, mm, drvdata); + }" + + compile_check_conftest "$CODE" "NV_IOMMU_SVA_BIND_DEVICE_HAS_DRVDATA_ARG" "" "types" + ;; + # When adding a new conftest entry, please use the correct format for # specifying the relevant upstream Linux kernel commit. # @@ -5743,10 +5948,6 @@ case "$5" in for i in $*; do compile_test $i; done - for file in conftest*.d; do - rm -f $file > /dev/null 2>&1 - done - exit 0 ;; @@ -5882,10 +6083,6 @@ case "$5" in test_header_presence "${7}" - for file in conftest*.d; do - rm -f $file > /dev/null 2>&1 - done - exit $? ;; diff --git a/kernel-open/nvidia-drm/nvidia-drm-connector.c b/kernel-open/nvidia-drm/nvidia-drm-connector.c index 2b893c533..18965cf7b 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-connector.c +++ b/kernel-open/nvidia-drm/nvidia-drm-connector.c @@ -27,6 +27,7 @@ #include "nvidia-drm-helper.h" #include "nvidia-drm-priv.h" #include "nvidia-drm-connector.h" +#include "nvidia-drm-crtc.h" #include "nvidia-drm-utils.h" #include "nvidia-drm-encoder.h" @@ -207,6 +208,11 @@ done: nv_drm_free(pDetectParams); + if (status == connector_status_disconnected && + nv_connector->modeset_permission_filep) { + nv_drm_connector_revoke_permissions(dev, nv_connector); + } + return status; } @@ -372,6 +378,8 @@ nv_drm_connector_new(struct drm_device *dev, nv_connector->physicalIndex = physicalIndex; nv_connector->type = type; nv_connector->internal = internal; + nv_connector->modeset_permission_filep = NULL; + nv_connector->modeset_permission_crtc = NULL; strcpy(nv_connector->dpAddress, dpAddress); @@ -474,4 +482,26 @@ done: return connector; } +/* + * Revoke the permissions on this connector. + */ +bool nv_drm_connector_revoke_permissions(struct drm_device *dev, + struct nv_drm_connector* nv_connector) +{ + struct nv_drm_device *nv_dev = to_nv_device(dev); + bool ret = true; + + if (nv_connector->modeset_permission_crtc) { + if (nv_connector->nv_detected_encoder) { + ret = nvKms->revokePermissions( + nv_dev->pDevice, nv_connector->modeset_permission_crtc->head, + nv_connector->nv_detected_encoder->hDisplay); + } + nv_connector->modeset_permission_crtc->modeset_permission_filep = NULL; + nv_connector->modeset_permission_crtc = NULL; + } + nv_connector->modeset_permission_filep = NULL; + return ret; +} + #endif diff --git a/kernel-open/nvidia-drm/nvidia-drm-connector.h b/kernel-open/nvidia-drm/nvidia-drm-connector.h index fd83d7a56..34ef213c8 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-connector.h +++ b/kernel-open/nvidia-drm/nvidia-drm-connector.h @@ -51,6 +51,20 @@ struct nv_drm_connector { atomic_t connection_status_dirty; + /** + * @modeset_permission_filep: + * + * The filep using this connector with DRM_IOCTL_NVIDIA_GRANT_PERMISSIONS. + */ + struct drm_file *modeset_permission_filep; + + /** + * @modeset_permission_crtc: + * + * The crtc using this connector with DRM_IOCTL_NVIDIA_GRANT_PERMISSIONS. + */ + struct nv_drm_crtc *modeset_permission_crtc; + struct drm_connector base; }; @@ -84,6 +98,9 @@ nv_drm_get_connector(struct drm_device *dev, NvBool internal, char dpAddress[NVKMS_DP_ADDRESS_STRING_LENGTH]); +bool nv_drm_connector_revoke_permissions(struct drm_device *dev, + struct nv_drm_connector *nv_connector); + #endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */ #endif /* __NVIDIA_DRM_CONNECTOR_H__ */ diff --git a/kernel-open/nvidia-drm/nvidia-drm-crtc.c b/kernel-open/nvidia-drm/nvidia-drm-crtc.c index 51d6324cb..e9fc3fd81 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-crtc.c +++ b/kernel-open/nvidia-drm/nvidia-drm-crtc.c @@ -1181,6 +1181,7 @@ static struct drm_crtc *__nv_drm_crtc_create(struct nv_drm_device *nv_dev, nv_crtc->head = head; INIT_LIST_HEAD(&nv_crtc->flip_list); spin_lock_init(&nv_crtc->flip_list_lock); + nv_crtc->modeset_permission_filep = NULL; ret = drm_crtc_init_with_planes(nv_dev->dev, &nv_crtc->base, @@ -1329,7 +1330,7 @@ int nv_drm_get_crtc_crc32_v2_ioctl(struct drm_device *dev, return -ENOENT; } - crtc = nv_drm_crtc_find(dev, params->crtc_id); + crtc = nv_drm_crtc_find(dev, filep, params->crtc_id); if (!crtc) { return -ENOENT; } @@ -1357,7 +1358,7 @@ int nv_drm_get_crtc_crc32_ioctl(struct drm_device *dev, return -ENOENT; } - crtc = nv_drm_crtc_find(dev, params->crtc_id); + crtc = nv_drm_crtc_find(dev, filep, params->crtc_id); if (!crtc) { return -ENOENT; } diff --git a/kernel-open/nvidia-drm/nvidia-drm-crtc.h b/kernel-open/nvidia-drm/nvidia-drm-crtc.h index f5db13022..2562e87c6 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-crtc.h +++ b/kernel-open/nvidia-drm/nvidia-drm-crtc.h @@ -35,38 +35,9 @@ #include -#if defined(NV_DRM_ALPHA_BLENDING_AVAILABLE) || defined(NV_DRM_ROTATION_AVAILABLE) -/* For DRM_ROTATE_* , DRM_REFLECT_* */ -#include -#endif - -#if defined(NV_DRM_ROTATION_AVAILABLE) -/* For DRM_MODE_ROTATE_* and DRM_MODE_REFLECT_* */ -#include -#endif - #include "nvtypes.h" #include "nvkms-kapi.h" -#if defined(NV_DRM_ROTATION_AVAILABLE) -/* - * 19-05-2017 c2c446ad29437bb92b157423c632286608ebd3ec has added - * DRM_MODE_ROTATE_* and DRM_MODE_REFLECT_* to UAPI and removed - * DRM_ROTATE_* and DRM_MODE_REFLECT_* - */ -#if !defined(DRM_MODE_ROTATE_0) -#define DRM_MODE_ROTATE_0 DRM_ROTATE_0 -#define DRM_MODE_ROTATE_90 DRM_ROTATE_90 -#define DRM_MODE_ROTATE_180 DRM_ROTATE_180 -#define DRM_MODE_ROTATE_270 DRM_ROTATE_270 -#define DRM_MODE_REFLECT_X DRM_REFLECT_X -#define DRM_MODE_REFLECT_Y DRM_REFLECT_Y -#define DRM_MODE_ROTATE_MASK DRM_ROTATE_MASK -#define DRM_MODE_REFLECT_MASK DRM_REFLECT_MASK -#endif - -#endif //NV_DRM_ROTATION_AVAILABLE - struct nv_drm_crtc { NvU32 head; @@ -85,6 +56,13 @@ struct nv_drm_crtc { */ spinlock_t flip_list_lock; + /** + * @modeset_permission_filep: + * + * The filep using this crtc with DRM_IOCTL_NVIDIA_GRANT_PERMISSIONS. + */ + struct drm_file *modeset_permission_filep; + struct drm_crtc base; }; diff --git a/kernel-open/nvidia-drm/nvidia-drm-drv.c b/kernel-open/nvidia-drm/nvidia-drm-drv.c index cc6626a0c..e48378faa 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-drv.c +++ b/kernel-open/nvidia-drm/nvidia-drm-drv.c @@ -30,7 +30,7 @@ #include "nvidia-drm-connector.h" #include "nvidia-drm-gem.h" #include "nvidia-drm-crtc.h" -#include "nvidia-drm-prime-fence.h" +#include "nvidia-drm-fence.h" #include "nvidia-drm-helper.h" #include "nvidia-drm-gem-nvkms-memory.h" #include "nvidia-drm-gem-user-memory.h" @@ -706,6 +706,16 @@ static int nv_drm_get_dev_info_ioctl(struct drm_device *dev, return 0; } +static int nv_drm_dmabuf_supported_ioctl(struct drm_device *dev, + void *data, struct drm_file *filep) +{ + /* check the pDevice since this only gets set if modeset = 1 + * which is a requirement for the dma_buf extension to work + */ + struct nv_drm_device *nv_dev = to_nv_device(dev); + return nv_dev->pDevice ? 0 : -EINVAL; +} + static int nv_drm_get_client_capability_ioctl(struct drm_device *dev, void *data, struct drm_file *filep) @@ -735,6 +745,455 @@ int nv_drm_get_client_capability_ioctl(struct drm_device *dev, return 0; } +#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE) +static bool nv_drm_connector_is_dpy_id(struct drm_connector *connector, + NvU32 dpyId) +{ + struct nv_drm_connector *nv_connector = to_nv_connector(connector); + return nv_connector->nv_detected_encoder && + nv_connector->nv_detected_encoder->hDisplay == dpyId; +} + +static int nv_drm_get_dpy_id_for_connector_id_ioctl(struct drm_device *dev, + void *data, + struct drm_file *filep) +{ + struct drm_nvidia_get_dpy_id_for_connector_id_params *params = data; + // Importantly, drm_connector_lookup (with filep) will only return the + // connector if we are master, a lessee with the connector, or not master at + // all. It will return NULL if we are a lessee with other connectors. + struct drm_connector *connector = + nv_drm_connector_lookup(dev, filep, params->connectorId); + struct nv_drm_connector *nv_connector; + int ret = 0; + + if (!connector) { + return -EINVAL; + } + + nv_connector = to_nv_connector(connector); + if (!nv_connector) { + ret = -EINVAL; + goto done; + } + + if (!nv_connector->nv_detected_encoder) { + ret = -EINVAL; + goto done; + } + + params->dpyId = nv_connector->nv_detected_encoder->hDisplay; + +done: + nv_drm_connector_put(connector); + return ret; +} + +static int nv_drm_get_connector_id_for_dpy_id_ioctl(struct drm_device *dev, + void *data, + struct drm_file *filep) +{ + struct drm_nvidia_get_connector_id_for_dpy_id_params *params = data; + struct drm_connector *connector; + int ret = -EINVAL; +#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT) + struct drm_connector_list_iter conn_iter; + nv_drm_connector_list_iter_begin(dev, &conn_iter); +#endif + + /* Lookup for existing connector with same dpyId */ + nv_drm_for_each_connector(connector, &conn_iter, dev) { + if (nv_drm_connector_is_dpy_id(connector, params->dpyId)) { + params->connectorId = connector->base.id; + ret = 0; + break; + } + } +#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT) + nv_drm_connector_list_iter_end(&conn_iter); +#endif + + return ret; +} + +static NvU32 nv_drm_get_head_bit_from_connector(struct drm_connector *connector) +{ + struct nv_drm_connector *nv_connector = to_nv_connector(connector); + + if (connector->state && connector->state->crtc) { + struct nv_drm_crtc *nv_crtc = to_nv_crtc(connector->state->crtc); + return NVBIT(nv_crtc->head); + } else if (nv_connector->nv_detected_encoder && + nv_connector->nv_detected_encoder->base.crtc) { + struct nv_drm_crtc *nv_crtc = + to_nv_crtc(nv_connector->nv_detected_encoder->base.crtc); + return NVBIT(nv_crtc->head); + } + + return 0; +} + +static int nv_drm_grant_permission_ioctl(struct drm_device *dev, void *data, + struct drm_file *filep) +{ + struct drm_nvidia_grant_permissions_params *params = data; + struct nv_drm_device *nv_dev = to_nv_device(dev); + struct nv_drm_connector *target_nv_connector = NULL; + struct nv_drm_crtc *target_nv_crtc = NULL; + struct drm_connector *connector, *target_connector = NULL; + struct drm_crtc *crtc; + NvU32 head = 0, freeHeadBits, targetHeadBit, possible_crtcs; + int ret = 0; +#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT) + struct drm_connector_list_iter conn_iter; +#endif +#if NV_DRM_MODESET_LOCK_ALL_END_ARGUMENT_COUNT == 3 + struct drm_modeset_acquire_ctx ctx; + DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE, + ret); +#else + mutex_lock(&dev->mode_config.mutex); +#endif + + /* Get the connector for the dpyId. */ +#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT) + nv_drm_connector_list_iter_begin(dev, &conn_iter); +#endif + nv_drm_for_each_connector(connector, &conn_iter, dev) { + if (nv_drm_connector_is_dpy_id(connector, params->dpyId)) { + target_connector = + nv_drm_connector_lookup(dev, filep, connector->base.id); + break; + } + } +#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT) + nv_drm_connector_list_iter_end(&conn_iter); +#endif + + // Importantly, drm_connector_lookup/drm_crtc_find (with filep) will only + // return the object if we are master, a lessee with the object, or not + // master at all. It will return NULL if we are a lessee with other objects. + if (!target_connector) { + ret = -EINVAL; + goto done; + } + target_nv_connector = to_nv_connector(target_connector); + possible_crtcs = + target_nv_connector->nv_detected_encoder->base.possible_crtcs; + + /* Target connector must not be previously granted. */ + if (target_nv_connector->modeset_permission_filep) { + ret = -EINVAL; + goto done; + } + + /* Add all heads that are owned and not already granted. */ + freeHeadBits = 0; + nv_drm_for_each_crtc(crtc, dev) { + struct nv_drm_crtc *nv_crtc = to_nv_crtc(crtc); + if (nv_drm_crtc_find(dev, filep, crtc->base.id) && + !nv_crtc->modeset_permission_filep && + (drm_crtc_mask(crtc) & possible_crtcs)) { + freeHeadBits |= NVBIT(nv_crtc->head); + } + } + + targetHeadBit = nv_drm_get_head_bit_from_connector(target_connector); + if (targetHeadBit & freeHeadBits) { + /* If a crtc is already being used by this connector, use it. */ + freeHeadBits = targetHeadBit; + } else { + /* Otherwise, remove heads that are in use by other connectors. */ +#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT) + nv_drm_connector_list_iter_begin(dev, &conn_iter); +#endif + nv_drm_for_each_connector(connector, &conn_iter, dev) { + freeHeadBits &= ~nv_drm_get_head_bit_from_connector(connector); + } +#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT) + nv_drm_connector_list_iter_end(&conn_iter); +#endif + } + + /* Fail if no heads are available. */ + if (!freeHeadBits) { + ret = -EINVAL; + goto done; + } + + /* + * Loop through the crtc again and find a matching head. + * Record the filep that is using the crtc and the connector. + */ + nv_drm_for_each_crtc(crtc, dev) { + struct nv_drm_crtc *nv_crtc = to_nv_crtc(crtc); + if (freeHeadBits & NVBIT(nv_crtc->head)) { + target_nv_crtc = nv_crtc; + head = nv_crtc->head; + break; + } + } + + if (!nvKms->grantPermissions(params->fd, nv_dev->pDevice, head, + params->dpyId)) { + ret = -EINVAL; + goto done; + } + + target_nv_connector->modeset_permission_crtc = target_nv_crtc; + target_nv_connector->modeset_permission_filep = filep; + target_nv_crtc->modeset_permission_filep = filep; + +done: + if (target_connector) { + nv_drm_connector_put(target_connector); + } + +#if NV_DRM_MODESET_LOCK_ALL_END_ARGUMENT_COUNT == 3 + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret); +#else + mutex_unlock(&dev->mode_config.mutex); +#endif + + return ret; +} + +static bool nv_drm_revoke_connector(struct nv_drm_device *nv_dev, + struct nv_drm_connector *nv_connector) +{ + bool ret = true; + if (nv_connector->modeset_permission_crtc) { + if (nv_connector->nv_detected_encoder) { + ret = nvKms->revokePermissions( + nv_dev->pDevice, nv_connector->modeset_permission_crtc->head, + nv_connector->nv_detected_encoder->hDisplay); + } + nv_connector->modeset_permission_crtc->modeset_permission_filep = NULL; + nv_connector->modeset_permission_crtc = NULL; + } + nv_connector->modeset_permission_filep = NULL; + return ret; +} + +static int nv_drm_revoke_permission(struct drm_device *dev, + struct drm_file *filep, NvU32 dpyId) +{ + struct drm_connector *connector; + struct drm_crtc *crtc; + int ret = 0; +#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT) + struct drm_connector_list_iter conn_iter; +#endif +#if NV_DRM_MODESET_LOCK_ALL_END_ARGUMENT_COUNT == 3 + struct drm_modeset_acquire_ctx ctx; + DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE, + ret); +#else + mutex_lock(&dev->mode_config.mutex); +#endif + + /* + * If dpyId is set, only revoke those specific resources. Otherwise, + * it is from closing the file so revoke all resources for that filep. + */ +#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT) + nv_drm_connector_list_iter_begin(dev, &conn_iter); +#endif + nv_drm_for_each_connector(connector, &conn_iter, dev) { + struct nv_drm_connector *nv_connector = to_nv_connector(connector); + if (nv_connector->modeset_permission_filep == filep && + (!dpyId || nv_drm_connector_is_dpy_id(connector, dpyId))) { + if (!nv_drm_connector_revoke_permissions(dev, nv_connector)) { + ret = -EINVAL; + // Continue trying to revoke as much as possible. + } + } + } +#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT) + nv_drm_connector_list_iter_end(&conn_iter); +#endif + + nv_drm_for_each_crtc(crtc, dev) { + struct nv_drm_crtc *nv_crtc = to_nv_crtc(crtc); + if (nv_crtc->modeset_permission_filep == filep && !dpyId) { + nv_crtc->modeset_permission_filep = NULL; + } + } + +#if NV_DRM_MODESET_LOCK_ALL_END_ARGUMENT_COUNT == 3 + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret); +#else + mutex_unlock(&dev->mode_config.mutex); +#endif + + return ret; +} + +static int nv_drm_revoke_permission_ioctl(struct drm_device *dev, void *data, + struct drm_file *filep) +{ + struct drm_nvidia_revoke_permissions_params *params = data; + if (!params->dpyId) { + return -EINVAL; + } + return nv_drm_revoke_permission(dev, filep, params->dpyId); +} + +static void nv_drm_postclose(struct drm_device *dev, struct drm_file *filep) +{ + /* + * Some systems like android can reach here without initializing the + * device, so check for that. + */ + if (dev->mode_config.num_crtc > 0 && + dev->mode_config.crtc_list.next != NULL && + dev->mode_config.crtc_list.prev != NULL && + dev->mode_config.num_connector > 0 && + dev->mode_config.connector_list.next != NULL && + dev->mode_config.connector_list.prev != NULL) { + nv_drm_revoke_permission(dev, filep, 0); + } +} +#endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */ + +#if defined(NV_DRM_MASTER_HAS_LEASES) +static struct drm_master *nv_drm_find_lessee(struct drm_master *master, + int lessee_id) +{ + int object; + void *entry; + + while (master->lessor != NULL) { + master = master->lessor; + } + + idr_for_each_entry(&master->lessee_idr, entry, object) + { + if (object == lessee_id) { + return entry; + } + } + + return NULL; +} + +static void nv_drm_get_revoked_objects(struct drm_device *dev, + struct drm_file *filep, unsigned int cmd, + unsigned long arg, int **objects, + int *objects_count) +{ + unsigned int ioc_size; + struct drm_mode_revoke_lease revoke_lease; + struct drm_master *lessor, *lessee; + void *entry; + int *objs; + int obj, obj_count, obj_i; + + ioc_size = _IOC_SIZE(cmd); + if (ioc_size > sizeof(revoke_lease)) { + return; + } + + if (copy_from_user(&revoke_lease, (void __user *)arg, ioc_size) != 0) { + return; + } + + lessor = nv_drm_file_get_master(filep); + if (lessor == NULL) { + return; + } + + mutex_lock(&dev->mode_config.idr_mutex); + lessee = nv_drm_find_lessee(lessor, revoke_lease.lessee_id); + + if (lessee == NULL) { + goto done; + } + + obj_count = 0; + idr_for_each_entry(&lessee->leases, entry, obj) { + ++obj_count; + } + if (obj_count == 0) { + goto done; + } + + objs = nv_drm_calloc(obj_count, sizeof(int)); + if (objs == NULL) { + goto done; + } + + obj_i = 0; + idr_for_each_entry(&lessee->leases, entry, obj) { + objs[obj_i++] = obj; + } + *objects = objs; + *objects_count = obj_count; + +done: + mutex_unlock(&dev->mode_config.idr_mutex); + drm_master_put(&lessor); +} + +static bool nv_drm_is_in_objects(int object, int *objects, int objects_count) +{ + int i; + for (i = 0; i < objects_count; ++i) { + if (objects[i] == object) { + return true; + } + } + return false; +} + +static void nv_drm_finish_revoking_objects(struct drm_device *dev, + struct drm_file *filep, int *objects, + int objects_count) +{ + struct drm_connector *connector; + struct drm_crtc *crtc; +#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT) + struct drm_connector_list_iter conn_iter; +#endif +#if NV_DRM_MODESET_LOCK_ALL_END_ARGUMENT_COUNT == 3 + int ret = 0; + struct drm_modeset_acquire_ctx ctx; + DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE, + ret); +#else + mutex_lock(&dev->mode_config.mutex); +#endif + +#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT) + nv_drm_connector_list_iter_begin(dev, &conn_iter); +#endif + nv_drm_for_each_connector(connector, &conn_iter, dev) { + struct nv_drm_connector *nv_connector = to_nv_connector(connector); + if (nv_connector->modeset_permission_filep && + nv_drm_is_in_objects(connector->base.id, objects, objects_count)) { + nv_drm_connector_revoke_permissions(dev, nv_connector); + } + } +#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT) + nv_drm_connector_list_iter_end(&conn_iter); +#endif + + nv_drm_for_each_crtc(crtc, dev) { + struct nv_drm_crtc *nv_crtc = to_nv_crtc(crtc); + if (nv_crtc->modeset_permission_filep && + nv_drm_is_in_objects(crtc->base.id, objects, objects_count)) { + nv_crtc->modeset_permission_filep = NULL; + } + } + +#if NV_DRM_MODESET_LOCK_ALL_END_ARGUMENT_COUNT == 3 + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret); +#else + mutex_unlock(&dev->mode_config.mutex); +#endif +} +#endif /* NV_DRM_MASTER_HAS_LEASES */ + #if defined(NV_DRM_BUS_PRESENT) #if defined(NV_DRM_BUS_HAS_GET_IRQ) @@ -766,12 +1225,50 @@ static struct drm_bus nv_drm_bus = { #endif /* NV_DRM_BUS_PRESENT */ +/* + * Wrapper around drm_ioctl to hook in to upstream ioctl. + * + * Currently used to add additional handling to REVOKE_LEASE. + */ +static long nv_drm_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + long retcode; + +#if defined(NV_DRM_MASTER_HAS_LEASES) + struct drm_file *file_priv = filp->private_data; + struct drm_device *dev = file_priv->minor->dev; + int *objects = NULL; + int objects_count = 0; + + if (cmd == DRM_IOCTL_MODE_REVOKE_LEASE) { + // Save the revoked objects before revoking. + nv_drm_get_revoked_objects(dev, file_priv, cmd, arg, &objects, + &objects_count); + } +#endif + + retcode = drm_ioctl(filp, cmd, arg); + +#if defined(NV_DRM_MASTER_HAS_LEASES) + if (cmd == DRM_IOCTL_MODE_REVOKE_LEASE && objects) { + if (retcode == 0) { + // If revoking was successful, finish revoking the objects. + nv_drm_finish_revoking_objects(dev, file_priv, objects, + objects_count); + } + nv_drm_free(objects); + } +#endif + + return retcode; +} + static const struct file_operations nv_drm_fops = { .owner = THIS_MODULE, .open = drm_open, .release = drm_release, - .unlocked_ioctl = drm_ioctl, + .unlocked_ioctl = nv_drm_ioctl, #if defined(CONFIG_COMPAT) .compat_ioctl = drm_compat_ioctl, #endif @@ -807,11 +1304,11 @@ static const struct drm_ioctl_desc nv_drm_ioctls[] = { DRM_IOCTL_DEF_DRV(NVIDIA_FENCE_SUPPORTED, nv_drm_fence_supported_ioctl, DRM_RENDER_ALLOW|DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(NVIDIA_FENCE_CONTEXT_CREATE, - nv_drm_fence_context_create_ioctl, + DRM_IOCTL_DEF_DRV(NVIDIA_PRIME_FENCE_CONTEXT_CREATE, + nv_drm_prime_fence_context_create_ioctl, DRM_RENDER_ALLOW|DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(NVIDIA_GEM_FENCE_ATTACH, - nv_drm_gem_fence_attach_ioctl, + DRM_IOCTL_DEF_DRV(NVIDIA_GEM_PRIME_FENCE_ATTACH, + nv_drm_gem_prime_fence_attach_ioctl, DRM_RENDER_ALLOW|DRM_UNLOCKED), #endif @@ -837,6 +1334,21 @@ static const struct drm_ioctl_desc nv_drm_ioctls[] = { DRM_IOCTL_DEF_DRV(NVIDIA_GEM_IDENTIFY_OBJECT, nv_drm_gem_identify_object_ioctl, DRM_RENDER_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF_DRV(NVIDIA_DMABUF_SUPPORTED, + nv_drm_dmabuf_supported_ioctl, + DRM_RENDER_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF_DRV(NVIDIA_GET_DPY_ID_FOR_CONNECTOR_ID, + nv_drm_get_dpy_id_for_connector_id_ioctl, + DRM_RENDER_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF_DRV(NVIDIA_GET_CONNECTOR_ID_FOR_DPY_ID, + nv_drm_get_connector_id_for_dpy_id_ioctl, + DRM_RENDER_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF_DRV(NVIDIA_GRANT_PERMISSIONS, + nv_drm_grant_permission_ioctl, + DRM_UNLOCKED|DRM_MASTER), + DRM_IOCTL_DEF_DRV(NVIDIA_REVOKE_PERMISSIONS, + nv_drm_revoke_permission_ioctl, + DRM_UNLOCKED|DRM_MASTER), #endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */ }; @@ -879,6 +1391,9 @@ static struct drm_driver nv_drm_driver = { .load = nv_drm_load, .unload = nv_drm_unload, +#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE) + .postclose = nv_drm_postclose, +#endif .fops = &nv_drm_fops, diff --git a/kernel-open/nvidia-drm/nvidia-drm-prime-fence.c b/kernel-open/nvidia-drm/nvidia-drm-fence.c similarity index 70% rename from kernel-open/nvidia-drm/nvidia-drm-prime-fence.c rename to kernel-open/nvidia-drm/nvidia-drm-fence.c index 39b44a11b..71d7275a2 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-prime-fence.c +++ b/kernel-open/nvidia-drm/nvidia-drm-fence.c @@ -31,17 +31,28 @@ #include "nvidia-drm-priv.h" #include "nvidia-drm-ioctl.h" #include "nvidia-drm-gem.h" -#include "nvidia-drm-prime-fence.h" +#include "nvidia-drm-fence.h" #include "nvidia-dma-resv-helper.h" #if defined(NV_DRM_FENCE_AVAILABLE) #include "nvidia-dma-fence-helper.h" -struct nv_drm_fence_context { - struct nv_drm_device *nv_dev; +struct nv_drm_fence_context; +struct nv_drm_fence_context_ops { + void (*destroy)(struct nv_drm_fence_context *nv_fence_context); +}; + +struct nv_drm_fence_context { + const struct nv_drm_fence_context_ops *ops; + + struct nv_drm_device *nv_dev; uint32_t context; +}; + +struct nv_drm_prime_fence_context { + struct nv_drm_fence_context base; NvU64 fenceSemIndex; /* Index into semaphore surface */ @@ -53,10 +64,10 @@ struct nv_drm_fence_context { spinlock_t lock; /* - * Software signaling structures. __nv_drm_fence_context_new() - * allocates channel event and __nv_drm_fence_context_destroy() frees it. - * There are no simultaneous read/write access to 'cb', therefore it does - * not require spin-lock protection. + * Software signaling structures. __nv_drm_prime_fence_context_new() + * allocates channel event and __nv_drm_prime_fence_context_destroy() frees + * it. There are no simultaneous read/write access to 'cb', therefore it + * does not require spin-lock protection. */ struct NvKmsKapiChannelEvent *cb; @@ -79,7 +90,7 @@ struct nv_drm_prime_fence *to_nv_drm_prime_fence(nv_dma_fence_t *fence) } static const char* -nv_drm_gem_prime_fence_op_get_driver_name(nv_dma_fence_t *fence) +nv_drm_gem_fence_op_get_driver_name(nv_dma_fence_t *fence) { return "NVIDIA"; } @@ -122,7 +133,7 @@ nv_drm_gem_prime_fence_op_wait(nv_dma_fence_t *fence, } static const nv_dma_fence_ops_t nv_drm_gem_prime_fence_ops = { - .get_driver_name = nv_drm_gem_prime_fence_op_get_driver_name, + .get_driver_name = nv_drm_gem_fence_op_get_driver_name, .get_timeline_name = nv_drm_gem_prime_fence_op_get_timeline_name, .enable_signaling = nv_drm_gem_prime_fence_op_enable_signaling, .release = nv_drm_gem_prime_fence_op_release, @@ -138,7 +149,7 @@ __nv_drm_prime_fence_signal(struct nv_drm_prime_fence *nv_fence) } static void nv_drm_gem_prime_force_fence_signal( - struct nv_drm_fence_context *nv_fence_context) + struct nv_drm_prime_fence_context *nv_fence_context) { WARN_ON(!spin_is_locked(&nv_fence_context->lock)); @@ -158,7 +169,7 @@ static void nv_drm_gem_prime_fence_event NvU32 dataU32 ) { - struct nv_drm_fence_context *nv_fence_context = dataPtr; + struct nv_drm_prime_fence_context *nv_fence_context = dataPtr; spin_lock(&nv_fence_context->lock); @@ -187,11 +198,53 @@ static void nv_drm_gem_prime_fence_event spin_unlock(&nv_fence_context->lock); } -static inline struct nv_drm_fence_context *__nv_drm_fence_context_new( - struct nv_drm_device *nv_dev, - struct drm_nvidia_fence_context_create_params *p) +static inline struct nv_drm_prime_fence_context* +to_prime_fence_context(struct nv_drm_fence_context *nv_fence_context) { + return (struct nv_drm_prime_fence_context *)nv_fence_context; +} + +static void __nv_drm_prime_fence_context_destroy( + struct nv_drm_fence_context *nv_fence_context) { - struct nv_drm_fence_context *nv_fence_context; + struct nv_drm_device *nv_dev = nv_fence_context->nv_dev; + struct nv_drm_prime_fence_context *nv_prime_fence_context = + to_prime_fence_context(nv_fence_context); + + /* + * Free channel event before destroying the fence context, otherwise event + * callback continue to get called. + */ + nvKms->freeChannelEvent(nv_dev->pDevice, nv_prime_fence_context->cb); + + /* Force signal all pending fences and empty pending list */ + spin_lock(&nv_prime_fence_context->lock); + + nv_drm_gem_prime_force_fence_signal(nv_prime_fence_context); + + spin_unlock(&nv_prime_fence_context->lock); + + /* Free nvkms resources */ + + nvKms->unmapMemory(nv_dev->pDevice, + nv_prime_fence_context->pSemSurface, + NVKMS_KAPI_MAPPING_TYPE_KERNEL, + (void *) nv_prime_fence_context->pLinearAddress); + + nvKms->freeMemory(nv_dev->pDevice, nv_prime_fence_context->pSemSurface); + + nv_drm_free(nv_fence_context); +} + +static struct nv_drm_fence_context_ops nv_drm_prime_fence_context_ops = { + .destroy = __nv_drm_prime_fence_context_destroy, +}; + +static inline struct nv_drm_prime_fence_context * +__nv_drm_prime_fence_context_new( + struct nv_drm_device *nv_dev, + struct drm_nvidia_prime_fence_context_create_params *p) +{ + struct nv_drm_prime_fence_context *nv_prime_fence_context; struct NvKmsKapiMemory *pSemSurface; NvU32 *pLinearAddress; @@ -225,9 +278,9 @@ static inline struct nv_drm_fence_context *__nv_drm_fence_context_new( * event for it. */ - if ((nv_fence_context = nv_drm_calloc( + if ((nv_prime_fence_context = nv_drm_calloc( 1, - sizeof(*nv_fence_context))) == NULL) { + sizeof(*nv_prime_fence_context))) == NULL) { goto failed_alloc_fence_context; } @@ -236,17 +289,18 @@ static inline struct nv_drm_fence_context *__nv_drm_fence_context_new( * to check a return value. */ - *nv_fence_context = (struct nv_drm_fence_context) { - .nv_dev = nv_dev, - .context = nv_dma_fence_context_alloc(1), + *nv_prime_fence_context = (struct nv_drm_prime_fence_context) { + .base.ops = &nv_drm_prime_fence_context_ops, + .base.nv_dev = nv_dev, + .base.context = nv_dma_fence_context_alloc(1), .pSemSurface = pSemSurface, .pLinearAddress = pLinearAddress, .fenceSemIndex = p->index, }; - INIT_LIST_HEAD(&nv_fence_context->pending); + INIT_LIST_HEAD(&nv_prime_fence_context->pending); - spin_lock_init(&nv_fence_context->lock); + spin_lock_init(&nv_prime_fence_context->lock); /* * Except 'cb', the fence context should be completely initialized @@ -256,22 +310,22 @@ static inline struct nv_drm_fence_context *__nv_drm_fence_context_new( * There are no simultaneous read/write access to 'cb', therefore it does * not require spin-lock protection. */ - nv_fence_context->cb = + nv_prime_fence_context->cb = nvKms->allocateChannelEvent(nv_dev->pDevice, nv_drm_gem_prime_fence_event, - nv_fence_context, + nv_prime_fence_context, p->event_nvkms_params_ptr, p->event_nvkms_params_size); - if (!nv_fence_context->cb) { + if (!nv_prime_fence_context->cb) { NV_DRM_DEV_LOG_ERR(nv_dev, "Failed to allocate fence signaling event"); goto failed_to_allocate_channel_event; } - return nv_fence_context; + return nv_prime_fence_context; failed_to_allocate_channel_event: - nv_drm_free(nv_fence_context); + nv_drm_free(nv_prime_fence_context); failed_alloc_fence_context: @@ -287,38 +341,8 @@ failed: return NULL; } -static void __nv_drm_fence_context_destroy( - struct nv_drm_fence_context *nv_fence_context) -{ - struct nv_drm_device *nv_dev = nv_fence_context->nv_dev; - - /* - * Free channel event before destroying the fence context, otherwise event - * callback continue to get called. - */ - nvKms->freeChannelEvent(nv_dev->pDevice, nv_fence_context->cb); - - /* Force signal all pending fences and empty pending list */ - spin_lock(&nv_fence_context->lock); - - nv_drm_gem_prime_force_fence_signal(nv_fence_context); - - spin_unlock(&nv_fence_context->lock); - - /* Free nvkms resources */ - - nvKms->unmapMemory(nv_dev->pDevice, - nv_fence_context->pSemSurface, - NVKMS_KAPI_MAPPING_TYPE_KERNEL, - (void *) nv_fence_context->pLinearAddress); - - nvKms->freeMemory(nv_dev->pDevice, nv_fence_context->pSemSurface); - - nv_drm_free(nv_fence_context); -} - -static nv_dma_fence_t *__nv_drm_fence_context_create_fence( - struct nv_drm_fence_context *nv_fence_context, +static nv_dma_fence_t *__nv_drm_prime_fence_context_create_fence( + struct nv_drm_prime_fence_context *nv_prime_fence_context, unsigned int seqno) { struct nv_drm_prime_fence *nv_fence; @@ -329,14 +353,14 @@ static nv_dma_fence_t *__nv_drm_fence_context_create_fence( goto out; } - spin_lock(&nv_fence_context->lock); + spin_lock(&nv_prime_fence_context->lock); /* * If seqno wrapped, force signal fences to make sure none of them * get stuck. */ - if (seqno < nv_fence_context->last_seqno) { - nv_drm_gem_prime_force_fence_signal(nv_fence_context); + if (seqno < nv_prime_fence_context->last_seqno) { + nv_drm_gem_prime_force_fence_signal(nv_prime_fence_context); } INIT_LIST_HEAD(&nv_fence->list_entry); @@ -344,17 +368,17 @@ static nv_dma_fence_t *__nv_drm_fence_context_create_fence( spin_lock_init(&nv_fence->lock); nv_dma_fence_init(&nv_fence->base, &nv_drm_gem_prime_fence_ops, - &nv_fence->lock, nv_fence_context->context, + &nv_fence->lock, nv_prime_fence_context->base.context, seqno); /* The context maintains a reference to any pending fences. */ nv_dma_fence_get(&nv_fence->base); - list_add_tail(&nv_fence->list_entry, &nv_fence_context->pending); + list_add_tail(&nv_fence->list_entry, &nv_prime_fence_context->pending); - nv_fence_context->last_seqno = seqno; + nv_prime_fence_context->last_seqno = seqno; - spin_unlock(&nv_fence_context->lock); + spin_unlock(&nv_prime_fence_context->lock); out: return ret != 0 ? ERR_PTR(ret) : &nv_fence->base; @@ -388,12 +412,15 @@ static inline struct nv_drm_gem_fence_context *to_gem_fence_context( * because tear down sequence calls to flush all existing * worker thread. */ -static void __nv_drm_gem_fence_context_free(struct nv_drm_gem_object *nv_gem) +static void +__nv_drm_gem_fence_context_free(struct nv_drm_gem_object *nv_gem) { struct nv_drm_gem_fence_context *nv_gem_fence_context = to_gem_fence_context(nv_gem); + struct nv_drm_fence_context *nv_fence_context = + nv_gem_fence_context->nv_fence_context; - __nv_drm_fence_context_destroy(nv_gem_fence_context->nv_fence_context); + nv_fence_context->ops->destroy(nv_fence_context); nv_drm_free(nv_gem_fence_context); } @@ -403,7 +430,8 @@ const struct nv_drm_gem_object_funcs nv_gem_fence_context_ops = { }; static inline -struct nv_drm_gem_fence_context *__nv_drm_gem_object_fence_context_lookup( +struct nv_drm_gem_fence_context * +__nv_drm_gem_object_fence_context_lookup( struct drm_device *dev, struct drm_file *filp, u32 handle) @@ -419,11 +447,13 @@ struct nv_drm_gem_fence_context *__nv_drm_gem_object_fence_context_lookup( return to_gem_fence_context(nv_gem); } -int nv_drm_fence_context_create_ioctl(struct drm_device *dev, - void *data, struct drm_file *filep) +static int +__nv_drm_gem_fence_context_create(struct drm_device *dev, + struct nv_drm_fence_context *nv_fence_context, + u32 *handle, + struct drm_file *filep) { struct nv_drm_device *nv_dev = to_nv_device(dev); - struct drm_nvidia_fence_context_create_params *p = data; struct nv_drm_gem_fence_context *nv_gem_fence_context = NULL; if ((nv_gem_fence_context = nv_drm_calloc( @@ -432,10 +462,7 @@ int nv_drm_fence_context_create_ioctl(struct drm_device *dev, goto done; } - if ((nv_gem_fence_context->nv_fence_context = - __nv_drm_fence_context_new(nv_dev, p)) == NULL) { - goto fence_context_new_failed; - } + nv_gem_fence_context->nv_fence_context = nv_fence_context; nv_drm_gem_object_init(nv_dev, &nv_gem_fence_context->base, @@ -445,21 +472,45 @@ int nv_drm_fence_context_create_ioctl(struct drm_device *dev, return nv_drm_gem_handle_create_drop_reference(filep, &nv_gem_fence_context->base, - &p->handle); - -fence_context_new_failed: - nv_drm_free(nv_gem_fence_context); + handle); done: return -ENOMEM; } -int nv_drm_gem_fence_attach_ioctl(struct drm_device *dev, - void *data, struct drm_file *filep) +int nv_drm_prime_fence_context_create_ioctl(struct drm_device *dev, + void *data, struct drm_file *filep) +{ + struct nv_drm_device *nv_dev = to_nv_device(dev); + struct drm_nvidia_prime_fence_context_create_params *p = data; + struct nv_drm_prime_fence_context *nv_prime_fence_context = + __nv_drm_prime_fence_context_new(nv_dev, p); + int err; + + if (!nv_prime_fence_context) { + goto done; + } + + err = __nv_drm_gem_fence_context_create(dev, + &nv_prime_fence_context->base, + &p->handle, + filep); + if (err) { + __nv_drm_prime_fence_context_destroy(&nv_prime_fence_context->base); + } + + return err; + +done: + return -ENOMEM; +} + +int nv_drm_gem_prime_fence_attach_ioctl(struct drm_device *dev, + void *data, struct drm_file *filep) { int ret = -EINVAL; struct nv_drm_device *nv_dev = to_nv_device(dev); - struct drm_nvidia_gem_fence_attach_params *p = data; + struct drm_nvidia_gem_prime_fence_attach_params *p = data; struct nv_drm_gem_object *nv_gem; struct nv_drm_gem_fence_context *nv_gem_fence_context; @@ -490,9 +541,22 @@ int nv_drm_gem_fence_attach_ioctl(struct drm_device *dev, goto fence_context_lookup_failed; } - if (IS_ERR(fence = __nv_drm_fence_context_create_fence( - nv_gem_fence_context->nv_fence_context, - p->sem_thresh))) { + if (nv_gem_fence_context->nv_fence_context->ops != + &nv_drm_prime_fence_context_ops) { + + NV_DRM_DEV_LOG_ERR( + nv_dev, + "Wrong fence context type: 0x%08x", + p->fence_context_handle); + + goto fence_context_create_fence_failed; + } + + fence = __nv_drm_prime_fence_context_create_fence( + to_prime_fence_context(nv_gem_fence_context->nv_fence_context), + p->sem_thresh); + + if (IS_ERR(fence)) { ret = PTR_ERR(fence); NV_DRM_DEV_LOG_ERR( diff --git a/kernel-open/nvidia-drm/nvidia-drm-prime-fence.h b/kernel-open/nvidia-drm/nvidia-drm-fence.h similarity index 84% rename from kernel-open/nvidia-drm/nvidia-drm-prime-fence.h rename to kernel-open/nvidia-drm/nvidia-drm-fence.h index 5afa2ae95..10689e1db 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-prime-fence.h +++ b/kernel-open/nvidia-drm/nvidia-drm-fence.h @@ -35,11 +35,11 @@ struct drm_device; int nv_drm_fence_supported_ioctl(struct drm_device *dev, void *data, struct drm_file *filep); -int nv_drm_fence_context_create_ioctl(struct drm_device *dev, - void *data, struct drm_file *filep); +int nv_drm_prime_fence_context_create_ioctl(struct drm_device *dev, + void *data, struct drm_file *filep); -int nv_drm_gem_fence_attach_ioctl(struct drm_device *dev, - void *data, struct drm_file *filep); +int nv_drm_gem_prime_fence_attach_ioctl(struct drm_device *dev, + void *data, struct drm_file *filep); #endif /* NV_DRM_FENCE_AVAILABLE */ diff --git a/kernel-open/nvidia-drm/nvidia-drm-gem.c b/kernel-open/nvidia-drm/nvidia-drm-gem.c index 92d61a6ee..9a019d87c 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-gem.c +++ b/kernel-open/nvidia-drm/nvidia-drm-gem.c @@ -26,7 +26,7 @@ #include "nvidia-drm-priv.h" #include "nvidia-drm-ioctl.h" -#include "nvidia-drm-prime-fence.h" +#include "nvidia-drm-fence.h" #include "nvidia-drm-gem.h" #include "nvidia-drm-gem-nvkms-memory.h" #include "nvidia-drm-gem-user-memory.h" diff --git a/kernel-open/nvidia-drm/nvidia-drm-helper.c b/kernel-open/nvidia-drm/nvidia-drm-helper.c index 8fc862068..dd6f89a7c 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-helper.c +++ b/kernel-open/nvidia-drm/nvidia-drm-helper.c @@ -28,6 +28,8 @@ */ #include "nvidia-drm-helper.h" +#include "nvidia-drm-priv.h" +#include "nvidia-drm-crtc.h" #include "nvmisc.h" @@ -148,6 +150,18 @@ int nv_drm_atomic_helper_disable_all(struct drm_device *dev, goto free; } +#if defined(NV_DRM_ROTATION_AVAILABLE) + nv_drm_for_each_plane(plane, dev) { + plane_state = drm_atomic_get_plane_state(state, plane); + if (IS_ERR(plane_state)) { + ret = PTR_ERR(plane_state); + goto free; + } + + plane_state->rotation = DRM_MODE_ROTATE_0; + } +#endif + nv_drm_for_each_connector_in_state(state, conn, conn_state, i) { ret = drm_atomic_set_crtc_for_connector(conn_state, NULL); if (ret < 0) diff --git a/kernel-open/nvidia-drm/nvidia-drm-helper.h b/kernel-open/nvidia-drm/nvidia-drm-helper.h index ecc5ecfdb..85a5d2e9c 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-helper.h +++ b/kernel-open/nvidia-drm/nvidia-drm-helper.h @@ -35,6 +35,35 @@ #include #endif +#if defined(NV_DRM_ALPHA_BLENDING_AVAILABLE) || defined(NV_DRM_ROTATION_AVAILABLE) +/* For DRM_ROTATE_* , DRM_REFLECT_* */ +#include +#endif + +#if defined(NV_DRM_ROTATION_AVAILABLE) +/* For DRM_MODE_ROTATE_* and DRM_MODE_REFLECT_* */ +#include +#endif + +#if defined(NV_DRM_ROTATION_AVAILABLE) +/* + * 19-05-2017 c2c446ad29437bb92b157423c632286608ebd3ec has added + * DRM_MODE_ROTATE_* and DRM_MODE_REFLECT_* to UAPI and removed + * DRM_ROTATE_* and DRM_REFLECT_* + */ +#if !defined(DRM_MODE_ROTATE_0) +#define DRM_MODE_ROTATE_0 DRM_ROTATE_0 +#define DRM_MODE_ROTATE_90 DRM_ROTATE_90 +#define DRM_MODE_ROTATE_180 DRM_ROTATE_180 +#define DRM_MODE_ROTATE_270 DRM_ROTATE_270 +#define DRM_MODE_REFLECT_X DRM_REFLECT_X +#define DRM_MODE_REFLECT_Y DRM_REFLECT_Y +#define DRM_MODE_ROTATE_MASK DRM_ROTATE_MASK +#define DRM_MODE_REFLECT_MASK DRM_REFLECT_MASK +#endif + +#endif //NV_DRM_ROTATION_AVAILABLE + /* * drm_dev_put() is added by commit 9a96f55034e41b4e002b767e9218d55f03bdff7d * (2017-09-26) and drm_dev_unref() is removed by @@ -277,11 +306,33 @@ int nv_drm_atomic_helper_disable_all(struct drm_device *dev, for_each_plane_in_state(__state, plane, plane_state, __i) #endif -static inline struct drm_crtc *nv_drm_crtc_find(struct drm_device *dev, - uint32_t id) +static inline struct drm_connector * +nv_drm_connector_lookup(struct drm_device *dev, struct drm_file *filep, + uint32_t id) +{ +#if !defined(NV_DRM_CONNECTOR_LOOKUP_PRESENT) + return drm_connector_find(dev, id); +#elif defined(NV_DRM_MODE_OBJECT_FIND_HAS_FILE_PRIV_ARG) + return drm_connector_lookup(dev, filep, id); +#else + return drm_connector_lookup(dev, id); +#endif +} + +static inline void nv_drm_connector_put(struct drm_connector *connector) +{ +#if defined(NV_DRM_CONNECTOR_PUT_PRESENT) + drm_connector_put(connector); +#elif defined(NV_DRM_CONNECTOR_LOOKUP_PRESENT) + drm_connector_unreference(connector); +#endif +} + +static inline struct drm_crtc * +nv_drm_crtc_find(struct drm_device *dev, struct drm_file *filep, uint32_t id) { #if defined(NV_DRM_MODE_OBJECT_FIND_HAS_FILE_PRIV_ARG) - return drm_crtc_find(dev, NULL /* file_priv */, id); + return drm_crtc_find(dev, filep, id); #else return drm_crtc_find(dev, id); #endif @@ -297,6 +348,30 @@ static inline struct drm_encoder *nv_drm_encoder_find(struct drm_device *dev, #endif } +#if defined(NV_DRM_DRM_AUTH_H_PRESENT) +#include +#endif +#if defined(NV_DRM_DRM_FILE_H_PRESENT) +#include +#endif + +/* + * drm_file_get_master() added by commit 56f0729a510f ("drm: protect drm_master + * pointers in drm_lease.c") in v5.15 (2021-07-20) + */ +static inline struct drm_master *nv_drm_file_get_master(struct drm_file *filep) +{ +#if defined(NV_DRM_FILE_GET_MASTER_PRESENT) + return drm_file_get_master(filep); +#else + if (filep->master) { + return drm_master_get(filep->master); + } else { + return NULL; + } +#endif +} + /* * drm_connector_for_each_possible_encoder() is added by commit * 83aefbb887b59df0b3520965c3701e01deacfc52 which was Signed-off-by: diff --git a/kernel-open/nvidia-drm/nvidia-drm-ioctl.h b/kernel-open/nvidia-drm/nvidia-drm-ioctl.h index 9cfca16f1..1d0e73859 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-ioctl.h +++ b/kernel-open/nvidia-drm/nvidia-drm-ioctl.h @@ -34,8 +34,8 @@ #define DRM_NVIDIA_GEM_IMPORT_USERSPACE_MEMORY 0x02 #define DRM_NVIDIA_GET_DEV_INFO 0x03 #define DRM_NVIDIA_FENCE_SUPPORTED 0x04 -#define DRM_NVIDIA_FENCE_CONTEXT_CREATE 0x05 -#define DRM_NVIDIA_GEM_FENCE_ATTACH 0x06 +#define DRM_NVIDIA_PRIME_FENCE_CONTEXT_CREATE 0x05 +#define DRM_NVIDIA_GEM_PRIME_FENCE_ATTACH 0x06 #define DRM_NVIDIA_GET_CLIENT_CAPABILITY 0x08 #define DRM_NVIDIA_GEM_EXPORT_NVKMS_MEMORY 0x09 #define DRM_NVIDIA_GEM_MAP_OFFSET 0x0a @@ -43,6 +43,11 @@ #define DRM_NVIDIA_GET_CRTC_CRC32_V2 0x0c #define DRM_NVIDIA_GEM_EXPORT_DMABUF_MEMORY 0x0d #define DRM_NVIDIA_GEM_IDENTIFY_OBJECT 0x0e +#define DRM_NVIDIA_DMABUF_SUPPORTED 0x0f +#define DRM_NVIDIA_GET_DPY_ID_FOR_CONNECTOR_ID 0x10 +#define DRM_NVIDIA_GET_CONNECTOR_ID_FOR_DPY_ID 0x11 +#define DRM_NVIDIA_GRANT_PERMISSIONS 0x12 +#define DRM_NVIDIA_REVOKE_PERMISSIONS 0x13 #define DRM_IOCTL_NVIDIA_GEM_IMPORT_NVKMS_MEMORY \ DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_IMPORT_NVKMS_MEMORY), \ @@ -65,50 +70,69 @@ #if defined(NV_LINUX) #define DRM_IOCTL_NVIDIA_FENCE_SUPPORTED \ DRM_IO(DRM_COMMAND_BASE + DRM_NVIDIA_FENCE_SUPPORTED) +#define DRM_IOCTL_NVIDIA_DMABUF_SUPPORTED \ + DRM_IO(DRM_COMMAND_BASE + DRM_NVIDIA_DMABUF_SUPPORTED) #else #define DRM_IOCTL_NVIDIA_FENCE_SUPPORTED 0 +#define DRM_IOCTL_NVIDIA_DMABUF_SUPPORTED 0 #endif -#define DRM_IOCTL_NVIDIA_FENCE_CONTEXT_CREATE \ - DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_FENCE_CONTEXT_CREATE), \ - struct drm_nvidia_fence_context_create_params) +#define DRM_IOCTL_NVIDIA_PRIME_FENCE_CONTEXT_CREATE \ + DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_PRIME_FENCE_CONTEXT_CREATE),\ + struct drm_nvidia_prime_fence_context_create_params) -#define DRM_IOCTL_NVIDIA_GEM_FENCE_ATTACH \ - DRM_IOW((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_FENCE_ATTACH), \ - struct drm_nvidia_gem_fence_attach_params) +#define DRM_IOCTL_NVIDIA_GEM_PRIME_FENCE_ATTACH \ + DRM_IOW((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_PRIME_FENCE_ATTACH), \ + struct drm_nvidia_gem_prime_fence_attach_params) -#define DRM_IOCTL_NVIDIA_GET_CLIENT_CAPABILITY \ - DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CLIENT_CAPABILITY), \ +#define DRM_IOCTL_NVIDIA_GET_CLIENT_CAPABILITY \ + DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CLIENT_CAPABILITY), \ struct drm_nvidia_get_client_capability_params) -#define DRM_IOCTL_NVIDIA_GET_CRTC_CRC32 \ - DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CRTC_CRC32), \ +#define DRM_IOCTL_NVIDIA_GET_CRTC_CRC32 \ + DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CRTC_CRC32), \ struct drm_nvidia_get_crtc_crc32_params) -#define DRM_IOCTL_NVIDIA_GET_CRTC_CRC32_V2 \ - DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CRTC_CRC32_V2), \ +#define DRM_IOCTL_NVIDIA_GET_CRTC_CRC32_V2 \ + DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CRTC_CRC32_V2), \ struct drm_nvidia_get_crtc_crc32_v2_params) -#define DRM_IOCTL_NVIDIA_GEM_EXPORT_NVKMS_MEMORY \ - DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_EXPORT_NVKMS_MEMORY), \ +#define DRM_IOCTL_NVIDIA_GEM_EXPORT_NVKMS_MEMORY \ + DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_EXPORT_NVKMS_MEMORY), \ struct drm_nvidia_gem_export_nvkms_memory_params) -#define DRM_IOCTL_NVIDIA_GEM_MAP_OFFSET \ - DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_MAP_OFFSET), \ +#define DRM_IOCTL_NVIDIA_GEM_MAP_OFFSET \ + DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_MAP_OFFSET), \ struct drm_nvidia_gem_map_offset_params) -#define DRM_IOCTL_NVIDIA_GEM_ALLOC_NVKMS_MEMORY \ - DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_ALLOC_NVKMS_MEMORY), \ +#define DRM_IOCTL_NVIDIA_GEM_ALLOC_NVKMS_MEMORY \ + DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_ALLOC_NVKMS_MEMORY), \ struct drm_nvidia_gem_alloc_nvkms_memory_params) -#define DRM_IOCTL_NVIDIA_GEM_EXPORT_DMABUF_MEMORY \ - DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_EXPORT_DMABUF_MEMORY), \ +#define DRM_IOCTL_NVIDIA_GEM_EXPORT_DMABUF_MEMORY \ + DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_EXPORT_DMABUF_MEMORY), \ struct drm_nvidia_gem_export_dmabuf_memory_params) -#define DRM_IOCTL_NVIDIA_GEM_IDENTIFY_OBJECT \ - DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_IDENTIFY_OBJECT), \ +#define DRM_IOCTL_NVIDIA_GEM_IDENTIFY_OBJECT \ + DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_IDENTIFY_OBJECT), \ struct drm_nvidia_gem_identify_object_params) +#define DRM_IOCTL_NVIDIA_GET_DPY_ID_FOR_CONNECTOR_ID \ + DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_DPY_ID_FOR_CONNECTOR_ID),\ + struct drm_nvidia_get_dpy_id_for_connector_id_params) + +#define DRM_IOCTL_NVIDIA_GET_CONNECTOR_ID_FOR_DPY_ID \ + DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CONNECTOR_ID_FOR_DPY_ID),\ + struct drm_nvidia_get_connector_id_for_dpy_id_params) + +#define DRM_IOCTL_NVIDIA_GRANT_PERMISSIONS \ + DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GRANT_PERMISSIONS), \ + struct drm_nvidia_grant_permissions_params) + +#define DRM_IOCTL_NVIDIA_REVOKE_PERMISSIONS \ + DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_REVOKE_PERMISSIONS), \ + struct drm_nvidia_revoke_permissions_params) + struct drm_nvidia_gem_import_nvkms_memory_params { uint64_t mem_size; /* IN */ @@ -136,7 +160,7 @@ struct drm_nvidia_get_dev_info_params { uint32_t sector_layout; /* OUT */ }; -struct drm_nvidia_fence_context_create_params { +struct drm_nvidia_prime_fence_context_create_params { uint32_t handle; /* OUT GEM handle to fence context */ uint32_t index; /* IN Index of semaphore to use for fencing */ @@ -151,7 +175,7 @@ struct drm_nvidia_fence_context_create_params { uint64_t event_nvkms_params_size; /* IN */ }; -struct drm_nvidia_gem_fence_attach_params { +struct drm_nvidia_gem_prime_fence_attach_params { uint32_t handle; /* IN GEM handle to attach fence to */ uint32_t fence_context_handle; /* IN GEM handle to fence context on which fence is run on */ uint32_t sem_thresh; /* IN Semaphore value to reach before signal */ @@ -232,4 +256,23 @@ struct drm_nvidia_gem_identify_object_params { drm_nvidia_gem_object_type object_type; /* OUT GEM object type */ }; +struct drm_nvidia_get_dpy_id_for_connector_id_params { + uint32_t connectorId; /* IN */ + uint32_t dpyId; /* OUT */ +}; + +struct drm_nvidia_get_connector_id_for_dpy_id_params { + uint32_t dpyId; /* IN */ + uint32_t connectorId; /* OUT */ +}; + +struct drm_nvidia_grant_permissions_params { + int32_t fd; /* IN */ + uint32_t dpyId; /* IN */ +}; + +struct drm_nvidia_revoke_permissions_params { + uint32_t dpyId; /* IN */ +}; + #endif /* _UAPI_NVIDIA_DRM_IOCTL_H_ */ diff --git a/kernel-open/nvidia-drm/nvidia-drm.Kbuild b/kernel-open/nvidia-drm/nvidia-drm.Kbuild index 6eef7f534..815539adb 100644 --- a/kernel-open/nvidia-drm/nvidia-drm.Kbuild +++ b/kernel-open/nvidia-drm/nvidia-drm.Kbuild @@ -16,7 +16,7 @@ NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-connector.c NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-gem.c NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-fb.c NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-modeset.c -NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-prime-fence.c +NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-fence.c NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-linux.c NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-helper.c NVIDIA_DRM_SOURCES += nvidia-drm/nv-pci-table.c @@ -124,3 +124,8 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += dma_resv_add_fence NV_CONFTEST_TYPE_COMPILE_TESTS += dma_resv_reserve_fences NV_CONFTEST_TYPE_COMPILE_TESTS += reservation_object_reserve_shared_has_num_fences_arg NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_has_override_edid +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_master_has_leases +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_file_get_master +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_modeset_lock_all_end +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_lookup +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_put diff --git a/kernel-open/nvidia-modeset/nvidia-modeset-linux.c b/kernel-open/nvidia-modeset/nvidia-modeset-linux.c index e48a58960..7f876432b 100644 --- a/kernel-open/nvidia-modeset/nvidia-modeset-linux.c +++ b/kernel-open/nvidia-modeset/nvidia-modeset-linux.c @@ -75,6 +75,15 @@ MODULE_PARM_DESC(malloc_verbose, "Report information about malloc calls on modul static bool malloc_verbose = false; module_param_named(malloc_verbose, malloc_verbose, bool, 0400); +/* This parameter is used to find the dpy override conf file */ +#define NVKMS_CONF_FILE_SPECIFIED (nvkms_conf != NULL) + +MODULE_PARM_DESC(config_file, + "Path to the nvidia-modeset configuration file " + "(default: disabled)"); +static char *nvkms_conf = NULL; +module_param_named(config_file, nvkms_conf, charp, 0400); + static atomic_t nvkms_alloc_called_count; NvBool nvkms_output_rounding_fix(void) @@ -1362,6 +1371,117 @@ static void nvkms_proc_exit(void) #endif /* CONFIG_PROC_FS */ } +/************************************************************************* + * NVKMS Config File Read + ************************************************************************/ +static NvBool nvkms_fs_mounted(void) +{ + return current->fs != NULL; +} + +static size_t nvkms_config_file_open +( + char *fname, + char ** const buff +) +{ + int i = 0; + struct file *file; + struct inode *file_inode; + size_t file_size = 0; + size_t read_size = 0; +#if defined(NV_KERNEL_READ_HAS_POINTER_POS_ARG) + loff_t pos = 0; +#endif + + if (!nvkms_fs_mounted()) { + printk(KERN_ERR NVKMS_LOG_PREFIX "ERROR: Filesystems not mounted\n"); + return 0; + } + + file = filp_open(fname, O_RDONLY, 0); + if (file == NULL || IS_ERR(file)) { + printk(KERN_WARNING NVKMS_LOG_PREFIX "WARNING: Failed to open %s\n", + fname); + return 0; + } + + file_inode = file->f_inode; + if (file_inode == NULL || IS_ERR(file_inode)) { + printk(KERN_WARNING NVKMS_LOG_PREFIX "WARNING: Inode is invalid\n"); + goto done; + } + file_size = file_inode->i_size; + if (file_size > NVKMS_READ_FILE_MAX_SIZE) { + printk(KERN_WARNING NVKMS_LOG_PREFIX "WARNING: File exceeds maximum size\n"); + goto done; + } + + *buff = nvkms_alloc(file_size, NV_FALSE); + if (*buff == NULL) { + printk(KERN_WARNING NVKMS_LOG_PREFIX "WARNING: Out of memory\n"); + goto done; + } + + /* + * TODO: Once we have access to GPL symbols, this can be replaced with + * kernel_read_file for kernels >= 4.6 + */ + while ((read_size < file_size) && (i++ < NVKMS_READ_FILE_MAX_LOOPS)) { +#if defined(NV_KERNEL_READ_HAS_POINTER_POS_ARG) + ssize_t ret = kernel_read(file, *buff + read_size, + file_size - read_size, &pos); +#else + ssize_t ret = kernel_read(file, read_size, + *buff + read_size, + file_size - read_size); +#endif + if (ret <= 0) { + break; + } + read_size += ret; + } + + if (read_size != file_size) { + printk(KERN_WARNING NVKMS_LOG_PREFIX "WARNING: Failed to read %s\n", + fname); + goto done; + } + + filp_close(file, current->files); + return file_size; + +done: + nvkms_free(*buff, file_size); + filp_close(file, current->files); + return 0; +} + +/* must be called with nvkms_lock locked */ +static void nvkms_read_config_file_locked(void) +{ + char *buffer = NULL; + size_t buf_size = 0; + + /* only read the config file if the kernel parameter is set */ + if (!NVKMS_CONF_FILE_SPECIFIED) { + return; + } + + buf_size = nvkms_config_file_open(nvkms_conf, &buffer); + + if (buf_size == 0) { + return; + } + + if (nvKmsReadConf(buffer, buf_size, nvkms_config_file_open)) { + printk(KERN_INFO NVKMS_LOG_PREFIX "Successfully read %s\n", + nvkms_conf); + } + + nvkms_free(buffer, buf_size); +} + /************************************************************************* * NVKMS KAPI functions ************************************************************************/ @@ -1533,10 +1653,12 @@ static int __init nvkms_init(void) if (!nvKmsModuleLoad()) { ret = -ENOMEM; } - up(&nvkms_lock); if (ret != 0) { + up(&nvkms_lock); goto fail_module_load; } + nvkms_read_config_file_locked(); + up(&nvkms_lock); nvkms_proc_init(); diff --git a/kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h b/kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h index 8036811f9..000600bde 100644 --- a/kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h +++ b/kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h @@ -43,14 +43,9 @@ enum NvKmsSyncPtOp { NVKMS_SYNCPT_OP_ALLOC, NVKMS_SYNCPT_OP_GET, NVKMS_SYNCPT_OP_PUT, - NVKMS_SYNCPT_OP_INCR_MAX, - NVKMS_SYNCPT_OP_CPU_INCR, NVKMS_SYNCPT_OP_FD_TO_ID_AND_THRESH, NVKMS_SYNCPT_OP_ID_AND_THRESH_TO_FD, NVKMS_SYNCPT_OP_READ_MINVAL, - NVKMS_SYNCPT_OP_READ_MAXVAL, - NVKMS_SYNCPT_OP_SET_MIN_EQ_MAX, - NVKMS_SYNCPT_OP_SET_MAXVAL, }; typedef struct { @@ -60,24 +55,10 @@ typedef struct { NvU32 id; /* out */ } alloc; - struct { - NvU32 id; /* in */ - } get; - struct { NvU32 id; /* in */ } put; - struct { - NvU32 id; /* in */ - NvU32 incr; /* in */ - NvU32 value; /* out */ - } incr_max; - - struct { - NvU32 id; /* in */ - } cpu_incr; - struct { NvS32 fd; /* in */ NvU32 id; /* out */ @@ -94,20 +75,6 @@ typedef struct { NvU32 id; /* in */ NvU32 minval; /* out */ } read_minval; - - struct { - NvU32 id; /* in */ - NvU32 maxval; /* out */ - } read_maxval; - - struct { - NvU32 id; /* in */ - } set_min_eq_max; - - struct { - NvU32 id; /* in */ - NvU32 val; /* in */ - } set_maxval; } NvKmsSyncPtOpParams; NvBool nvkms_output_rounding_fix(void); diff --git a/kernel-open/nvidia-modeset/nvkms.h b/kernel-open/nvidia-modeset/nvkms.h index 1276186ce..e770341b8 100644 --- a/kernel-open/nvidia-modeset/nvkms.h +++ b/kernel-open/nvidia-modeset/nvkms.h @@ -42,6 +42,20 @@ typedef void nvkms_procfs_proc_t(void *data, char *buffer, size_t size, nvkms_procfs_out_string_func_t *outString); +/* max number of loops to prevent hanging the kernel if an edge case is hit */ +#define NVKMS_READ_FILE_MAX_LOOPS 1000 +/* max size for any file read by the config system */ +#define NVKMS_READ_FILE_MAX_SIZE 8192 + +/* + * The read file callback should allocate a buffer pointed to by *buff, fill it + * with the contents of fname, and return the size of the buffer. Buffer is not + * guaranteed to be null-terminated. The caller is responsible for freeing the + * buffer with nvkms_free, not nvFree. + */ +typedef size_t nvkms_config_read_file_func_t(char *fname, + char ** const buff); + typedef struct { const char *name; nvkms_procfs_proc_t *func; @@ -74,6 +88,9 @@ void nvKmsResume(NvU32 gpuId); void nvKmsGetProcFiles(const nvkms_procfs_file_t **ppProcFiles); +NvBool nvKmsReadConf(const char *buff, size_t size, + nvkms_config_read_file_func_t readfile); + void nvKmsKapiHandleEventQueueChange ( struct NvKmsKapiDevice *device diff --git a/kernel-open/nvidia-uvm/clc365.h b/kernel-open/nvidia-uvm/clc365.h index 10d286bed..82c6cce11 100644 --- a/kernel-open/nvidia-uvm/clc365.h +++ b/kernel-open/nvidia-uvm/clc365.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2021 NVIDIA Corporation + Copyright (c) 2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to diff --git a/kernel-open/nvidia-uvm/clc369.h b/kernel-open/nvidia-uvm/clc369.h index 5b35067d8..49b01d901 100644 --- a/kernel-open/nvidia-uvm/clc369.h +++ b/kernel-open/nvidia-uvm/clc369.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2021 NVIDIA Corporation + Copyright (c) 2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to diff --git a/kernel-open/nvidia-uvm/clc3b5.h b/kernel-open/nvidia-uvm/clc3b5.h index 1e79c7526..04d4ba29c 100644 --- a/kernel-open/nvidia-uvm/clc3b5.h +++ b/kernel-open/nvidia-uvm/clc3b5.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016 NVIDIA Corporation + Copyright (c) 2016-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -69,6 +69,9 @@ extern "C" { #define NVC3B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 #define NVC3B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) #define NVC3B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC3B5_LAUNCH_DMA_FLUSH_TYPE 25:25 +#define NVC3B5_LAUNCH_DMA_FLUSH_TYPE_SYS (0x00000000) +#define NVC3B5_LAUNCH_DMA_FLUSH_TYPE_GL (0x00000001) #define NVC3B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 #define NVC3B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) #define NVC3B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) diff --git a/kernel-open/nvidia-uvm/ctrl2080mc.h b/kernel-open/nvidia-uvm/ctrl2080mc.h index 99f32fab8..f41af44f6 100644 --- a/kernel-open/nvidia-uvm/ctrl2080mc.h +++ b/kernel-open/nvidia-uvm/ctrl2080mc.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2013-2021 NVIDIA Corporation + Copyright (c) 2013-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to diff --git a/kernel-open/nvidia-uvm/nvidia-uvm-sources.Kbuild b/kernel-open/nvidia-uvm/nvidia-uvm-sources.Kbuild index 705421fef..12fc09ff8 100644 --- a/kernel-open/nvidia-uvm/nvidia-uvm-sources.Kbuild +++ b/kernel-open/nvidia-uvm/nvidia-uvm-sources.Kbuild @@ -1,12 +1,6 @@ NVIDIA_UVM_SOURCES ?= NVIDIA_UVM_SOURCES_CXX ?= -NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hopper.c -NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hopper_fault_buffer.c -NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hopper_ce.c -NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hopper_host.c -NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hopper_mmu.c -NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_ada.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_common.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_linux.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_debug_optimized.c @@ -58,6 +52,7 @@ NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_pascal_ce.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_pascal_host.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_pascal_mmu.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_pascal_fault_buffer.c +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_volta_ce.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_volta_host.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_volta_mmu.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_volta.c @@ -72,6 +67,12 @@ NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_ampere.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_ampere_ce.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_ampere_host.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_ampere_mmu.c +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hopper.c +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hopper_fault_buffer.c +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hopper_ce.c +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hopper_host.c +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hopper_mmu.c +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_ada.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_policy.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_perf_utils.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_kvmalloc.c @@ -94,7 +95,6 @@ NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_test_rng.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_range_tree_test.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_range_allocator_test.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_gpu_semaphore_test.c -NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hmm_sanity_test.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_mem_test.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_rm_mem_test.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_page_tree_test.c diff --git a/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild b/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild index cdc636193..c5ca3d4d1 100644 --- a/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild +++ b/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild @@ -36,7 +36,7 @@ NVIDIA_UVM_KO = nvidia-uvm/nvidia-uvm.ko # ifeq ($(UVM_BUILD_TYPE),debug) - NVIDIA_UVM_CFLAGS += -DDEBUG $(call cc-option,-Og,-O0) -g + NVIDIA_UVM_CFLAGS += -DDEBUG -O1 -g else ifeq ($(UVM_BUILD_TYPE),develop) # -DDEBUG is required, in order to allow pr_devel() print statements to @@ -81,8 +81,10 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += set_memory_uc NV_CONFTEST_FUNCTION_COMPILE_TESTS += set_pages_uc NV_CONFTEST_FUNCTION_COMPILE_TESTS += ktime_get_raw_ts64 NV_CONFTEST_FUNCTION_COMPILE_TESTS += ioasid_get +NV_CONFTEST_FUNCTION_COMPILE_TESTS += mm_pasid_set NV_CONFTEST_FUNCTION_COMPILE_TESTS += migrate_vma_setup NV_CONFTEST_FUNCTION_COMPILE_TESTS += mmget_not_zero +NV_CONFTEST_FUNCTION_COMPILE_TESTS += iommu_sva_bind_device_has_drvdata_arg NV_CONFTEST_TYPE_COMPILE_TESTS += backing_dev_info NV_CONFTEST_TYPE_COMPILE_TESTS += mm_context_t @@ -100,6 +102,6 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += proc_ops NV_CONFTEST_TYPE_COMPILE_TESTS += timespec64 NV_CONFTEST_TYPE_COMPILE_TESTS += mm_has_mmap_lock NV_CONFTEST_TYPE_COMPILE_TESTS += migrate_vma_added_flags -NV_CONFTEST_TYPE_COMPILE_TESTS += make_device_exclusive_range +NV_CONFTEST_TYPE_COMPILE_TESTS += migrate_device_range NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_int_active_memcg diff --git a/kernel-open/nvidia-uvm/uvm.c b/kernel-open/nvidia-uvm/uvm.c index f537c7e1b..31daf8401 100644 --- a/kernel-open/nvidia-uvm/uvm.c +++ b/kernel-open/nvidia-uvm/uvm.c @@ -35,26 +35,95 @@ #include "uvm_linux_ioctl.h" #include "uvm_hmm.h" #include "uvm_mem.h" +#include "uvm_kvmalloc.h" #define NVIDIA_UVM_DEVICE_NAME "nvidia-uvm" static dev_t g_uvm_base_dev; static struct cdev g_uvm_cdev; +static const struct file_operations uvm_fops; -static int uvm_open(struct inode *inode, struct file *filp) +bool uvm_file_is_nvidia_uvm(struct file *filp) { - NV_STATUS status = uvm_global_get_status(); + return (filp != NULL) && (filp->f_op == &uvm_fops); +} - if (status == NV_OK) { - if (!uvm_down_read_trylock(&g_uvm_global.pm.lock)) - return -EAGAIN; +uvm_fd_type_t uvm_fd_type(struct file *filp, void **ptr_val) +{ + unsigned long uptr; + uvm_fd_type_t type; + void *ptr; - status = uvm_va_space_create(inode, filp); + UVM_ASSERT(uvm_file_is_nvidia_uvm(filp)); - uvm_up_read(&g_uvm_global.pm.lock); + uptr = atomic_long_read_acquire((atomic_long_t *) (&filp->private_data)); + type = (uvm_fd_type_t)(uptr & UVM_FD_TYPE_MASK); + ptr = (void *)(uptr & ~UVM_FD_TYPE_MASK); + BUILD_BUG_ON(UVM_FD_COUNT > UVM_FD_TYPE_MASK + 1); + + switch (type) { + case UVM_FD_UNINITIALIZED: + case UVM_FD_INITIALIZING: + UVM_ASSERT(!ptr); + break; + + case UVM_FD_VA_SPACE: + UVM_ASSERT(ptr); + BUILD_BUG_ON(__alignof__(uvm_va_space_t) < (1UL << UVM_FD_TYPE_BITS)); + break; + + default: + UVM_ASSERT(0); } - return -nv_status_to_errno(status); + if (ptr_val) + *ptr_val = ptr; + + return type; +} + +// Called when opening /dev/nvidia-uvm. This code doesn't take any UVM locks, so +// there's no need to acquire g_uvm_global.pm.lock, but if that changes the PM +// lock will need to be taken. +static int uvm_open(struct inode *inode, struct file *filp) +{ + struct address_space *mapping; + NV_STATUS status = uvm_global_get_status(); + + if (status != NV_OK) + return -nv_status_to_errno(status); + + mapping = uvm_kvmalloc(sizeof(*mapping)); + if (!mapping) + return -ENOMEM; + + // By default all struct files on the same inode share the same + // address_space structure (the inode's) across all processes. This means + // unmap_mapping_range would unmap virtual mappings across all processes on + // that inode. + // + // Since the UVM driver uses the mapping offset as the VA of the file's + // process, we need to isolate the mappings to each process. + address_space_init_once(mapping); + mapping->host = inode; + + // Some paths in the kernel, for example force_page_cache_readahead which + // can be invoked from user-space via madvise MADV_WILLNEED and fadvise + // POSIX_FADV_WILLNEED, check the function pointers within + // file->f_mapping->a_ops for validity. However, those paths assume that a_ops + // itself is always valid. Handle that by using the inode's a_ops pointer, + // which is what f_mapping->a_ops would point to anyway if we weren't re- + // assigning f_mapping. + mapping->a_ops = inode->i_mapping->a_ops; + +#if defined(NV_ADDRESS_SPACE_HAS_BACKING_DEV_INFO) + mapping->backing_dev_info = inode->i_mapping->backing_dev_info; +#endif + + filp->private_data = NULL; + filp->f_mapping = mapping; + + return NV_OK; } static int uvm_open_entry(struct inode *inode, struct file *filp) @@ -80,9 +149,18 @@ static void uvm_release_deferred(void *data) static int uvm_release(struct inode *inode, struct file *filp) { - uvm_va_space_t *va_space = uvm_va_space_get(filp); + uvm_va_space_t *va_space; + uvm_fd_type_t fd_type; int ret; + fd_type = uvm_fd_type(filp, (void **)&va_space); + UVM_ASSERT(fd_type != UVM_FD_INITIALIZING); + if (fd_type == UVM_FD_UNINITIALIZED) { + uvm_kvfree(filp->f_mapping); + return 0; + } + + UVM_ASSERT(fd_type == UVM_FD_VA_SPACE); filp->private_data = NULL; filp->f_mapping = NULL; @@ -100,7 +178,7 @@ static int uvm_release(struct inode *inode, struct file *filp) // been destroyed, and va_space->mapping won't be used again. Still, // the va_space survives the inode if its destruction is deferred, in // which case the references are rendered stale. - address_space_init_once(&va_space->mapping); + address_space_init_once(va_space->mapping); nv_kthread_q_item_init(&va_space->deferred_release_q_item, uvm_release_deferred, va_space); ret = nv_kthread_q_schedule_q_item(&g_uvm_global.deferred_release_q, &va_space->deferred_release_q_item); @@ -363,14 +441,12 @@ static void uvm_vm_open_managed_entry(struct vm_area_struct *vma) static void uvm_vm_close_managed(struct vm_area_struct *vma) { uvm_va_space_t *va_space = uvm_va_space_get(vma->vm_file); - uvm_gpu_t *gpu; + uvm_processor_id_t gpu_id; bool make_zombie = false; if (current->mm != NULL) uvm_record_lock_mmap_lock_write(current->mm); - UVM_ASSERT(uvm_va_space_initialized(va_space) == NV_OK); - // current->mm will be NULL on process teardown, in which case we have // special handling. if (current->mm == NULL) { @@ -400,13 +476,11 @@ static void uvm_vm_close_managed(struct vm_area_struct *vma) uvm_destroy_vma_managed(vma, make_zombie); - // Notify GPU address spaces that the fault buffer needs to be flushed to avoid finding stale entries - // that can be attributed to new VA ranges reallocated at the same address - for_each_va_space_gpu_in_mask(gpu, va_space, &va_space->registered_gpu_va_spaces) { - uvm_gpu_va_space_t *gpu_va_space = uvm_gpu_va_space_get(va_space, gpu); - UVM_ASSERT(gpu_va_space); - - gpu_va_space->needs_fault_buffer_flush = true; + // Notify GPU address spaces that the fault buffer needs to be flushed to + // avoid finding stale entries that can be attributed to new VA ranges + // reallocated at the same address. + for_each_gpu_id_in_mask(gpu_id, &va_space->registered_gpu_va_spaces) { + uvm_processor_mask_set_atomic(&va_space->needs_fault_buffer_flush, gpu_id); } uvm_va_space_up_write(va_space); @@ -556,7 +630,7 @@ static struct vm_operations_struct uvm_vm_ops_semaphore_pool = static int uvm_mmap(struct file *filp, struct vm_area_struct *vma) { - uvm_va_space_t *va_space = uvm_va_space_get(filp); + uvm_va_space_t *va_space; uvm_va_range_t *va_range; NV_STATUS status = uvm_global_get_status(); int ret = 0; @@ -565,8 +639,8 @@ static int uvm_mmap(struct file *filp, struct vm_area_struct *vma) if (status != NV_OK) return -nv_status_to_errno(status); - status = uvm_va_space_initialized(va_space); - if (status != NV_OK) + va_space = uvm_fd_va_space(filp); + if (!va_space) return -EBADFD; // When the VA space is associated with an mm, all vmas under the VA space @@ -618,7 +692,11 @@ static int uvm_mmap(struct file *filp, struct vm_area_struct *vma) // Using VM_DONTCOPY would be nice, but madvise(MADV_DOFORK) can reset that // so we have to handle vm_open on fork anyway. We could disable MADV_DOFORK // with VM_IO, but that causes other mapping issues. - vma->vm_flags |= VM_MIXEDMAP | VM_DONTEXPAND; + // Make the default behavior be VM_DONTCOPY to avoid the performance impact + // of removing CPU mappings in the parent on fork()+exec(). Users can call + // madvise(MDV_DOFORK) if the child process requires access to the + // allocation. + vma->vm_flags |= VM_MIXEDMAP | VM_DONTEXPAND | VM_DONTCOPY; vma->vm_ops = &uvm_vm_ops_managed; @@ -685,7 +763,53 @@ static int uvm_mmap_entry(struct file *filp, struct vm_area_struct *vma) static NV_STATUS uvm_api_initialize(UVM_INITIALIZE_PARAMS *params, struct file *filp) { - return uvm_va_space_initialize(uvm_va_space_get(filp), params->flags); + uvm_va_space_t *va_space; + NV_STATUS status; + uvm_fd_type_t old_fd_type; + + // Normally we expect private_data == UVM_FD_UNINITIALIZED. However multiple + // threads may call this ioctl concurrently so we have to be careful to + // avoid initializing multiple va_spaces and/or leaking memory. To do this + // we do an atomic compare and swap. Only one thread will observe + // UVM_FD_UNINITIALIZED and that thread will allocate and setup the + // va_space. + // + // Other threads will either see UVM_FD_INITIALIZING or UVM_FD_VA_SPACE. In + // the case of UVM_FD_VA_SPACE we return success if and only if the + // initialization flags match. If another thread is still initializing the + // va_space we return NV_ERR_BUSY_RETRY. + // + // If va_space initialization fails we return the failure code and reset the + // FD state back to UVM_FD_UNINITIALIZED to allow another initialization + // attempt to be made. This is safe because other threads will have only had + // a chance to observe UVM_FD_INITIALIZING and not UVM_FD_VA_SPACE in this + // case. + old_fd_type = nv_atomic_long_cmpxchg((atomic_long_t *)&filp->private_data, + UVM_FD_UNINITIALIZED, UVM_FD_INITIALIZING); + old_fd_type &= UVM_FD_TYPE_MASK; + if (old_fd_type == UVM_FD_UNINITIALIZED) { + status = uvm_va_space_create(filp->f_mapping, &va_space, params->flags); + if (status != NV_OK) { + atomic_long_set_release((atomic_long_t *)&filp->private_data, UVM_FD_UNINITIALIZED); + return status; + } + + atomic_long_set_release((atomic_long_t *)&filp->private_data, (long)va_space | UVM_FD_VA_SPACE); + } + else if (old_fd_type == UVM_FD_VA_SPACE) { + va_space = uvm_va_space_get(filp); + + if (params->flags != va_space->initialization_flags) + status = NV_ERR_INVALID_ARGUMENT; + else + status = NV_OK; + } + else { + UVM_ASSERT(old_fd_type == UVM_FD_INITIALIZING); + status = NV_ERR_BUSY_RETRY; + } + + return status; } static NV_STATUS uvm_api_pageable_mem_access(UVM_PAGEABLE_MEM_ACCESS_PARAMS *params, struct file *filp) @@ -782,11 +906,6 @@ static const struct file_operations uvm_fops = .owner = THIS_MODULE, }; -bool uvm_file_is_nvidia_uvm(struct file *filp) -{ - return (filp != NULL) && (filp->f_op == &uvm_fops); -} - NV_STATUS uvm_test_register_unload_state_buffer(UVM_TEST_REGISTER_UNLOAD_STATE_BUFFER_PARAMS *params, struct file *filp) { long ret; diff --git a/kernel-open/nvidia-uvm/uvm.h b/kernel-open/nvidia-uvm/uvm.h index 69c25677e..db13a30f0 100644 --- a/kernel-open/nvidia-uvm/uvm.h +++ b/kernel-open/nvidia-uvm/uvm.h @@ -211,12 +211,12 @@ NV_STATUS UvmDeinitialize(void); // UvmReopen // // Reinitializes the UVM driver after checking for minimal user-mode state. -// Before calling this function, all GPUs must be unregistered with +// Before calling this function, all GPUs must be unregistered with // UvmUnregisterGpu() and all allocated VA ranges must be freed with UvmFree(). // Note that it is not required to release VA ranges that were reserved with // UvmReserveVa(). // -// UvmReopen() closes the open file returned by UvmGetFileDescriptor() and +// UvmReopen() closes the open file returned by UvmGetFileDescriptor() and // replaces it with a new open file with the same name. // // Arguments: @@ -1746,17 +1746,20 @@ NV_STATUS UvmCreateExternalRange(void *base, // GPUs. The external allocation can be unmapped from a specific GPU using // UvmUnmapExternal or from all GPUs using UvmFree. // -// The virtual address range specified by (base, length) must be aligned to the -// allocation's physical page size and must fall within a VA range previously -// created with UvmCreateExternalRange. A GPU VA space must have been registered -// for each GPU in the list. The offset in the physical allocation at which the -// allocation must be mapped should also be aligned to the allocation's physical -// page size. The (base, length) range must lie within the largest possible -// virtual address supported by the specified GPUs. +// The virtual address range specified by (base, length) must fall within a VA +// range previously created with UvmCreateExternalRange. A GPU VA space must +// have been registered for each GPU in the list. The (base, length) range must +// lie within the largest possible virtual address supported by the specified +// GPUs. +// +// The page size used for the mapping is the largest supported page size less +// than or equal to the alignments of base, length, offset, and the allocation +// page size. // // If the range specified by (base, length) falls within any existing mappings, // the behavior is the same as if UvmUnmapExternal with the range specified by -// (base, length) had been called first. +// (base, length) had been called first, provided that base and length are +// aligned to the page size used for the existing one. // // If the allocation resides in GPU memory, that GPU must have been registered // via UvmRegisterGpu. If the allocation resides in GPU memory and a mapping is @@ -1838,8 +1841,9 @@ NV_STATUS UvmCreateExternalRange(void *base, // - The requested address range does not fall entirely within an // existing external VA range created with a single call to // UvmCreateExternalRange. -// - At least one of base and length is not aligned to the allocation's -// physical page size. +// - The mapping page size allowed by the alignments of base, length, +// and offset is smaller than the minimum supported page size on the +// GPU. // - base or base + length fall within an existing mapping but are not // aligned to that mapping's page size. // @@ -1848,8 +1852,7 @@ NV_STATUS UvmCreateExternalRange(void *base, // address supported by one or more of the specified GPUs. // // NV_ERR_INVALID_OFFSET: -// offset is not aligned to the allocation's physical page size or -// offset+length exceeds the allocation size. +// - offset+length exceeds the allocation size. // // NV_ERR_INVALID_DEVICE: // One of the following occurred: @@ -3758,6 +3761,7 @@ NV_STATUS UvmToolsDisableCounters(UvmToolsCountersHandle counters, // NV_ERR_INVALID_ARGUMENT: // Read spans more than a single target process allocation. // +// //------------------------------------------------------------------------------ NV_STATUS UvmToolsReadProcessMemory(UvmToolsSessionHandle session, void *buffer, diff --git a/kernel-open/nvidia-uvm/uvm_ampere_ce.c b/kernel-open/nvidia-uvm/uvm_ampere_ce.c index fdac5bdbd..f7037cab4 100644 --- a/kernel-open/nvidia-uvm/uvm_ampere_ce.c +++ b/kernel-open/nvidia-uvm/uvm_ampere_ce.c @@ -27,7 +27,7 @@ #include "clc7b5.h" #include "clc56f.h" // Needed because HAL ce_init pushes SET_OBJECT -bool uvm_hal_ampere_ce_method_validate_c6b5(uvm_push_t *push, NvU32 method_address, NvU32 method_data) +bool uvm_hal_ampere_ce_method_is_valid_c6b5(uvm_push_t *push, NvU32 method_address, NvU32 method_data) { if (!uvm_channel_is_proxy(push->channel)) return true; @@ -112,7 +112,7 @@ NvU32 uvm_hal_ampere_ce_plc_mode_c7b5(void) return HWCONST(C7B5, LAUNCH_DMA, DISABLE_PLC, TRUE); } -bool uvm_hal_ampere_ce_memcopy_validate_c6b5(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src) +bool uvm_hal_ampere_ce_memcopy_is_valid_c6b5(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src) { NvU64 push_begin_gpu_va; uvm_gpu_t *gpu = uvm_push_get_gpu(push); @@ -183,7 +183,7 @@ void uvm_hal_ampere_ce_memcopy_patch_src_c6b5(uvm_push_t *push, uvm_gpu_address_ src->address -= uvm_pushbuffer_get_gpu_va_for_push(push->channel->pool->manager->pushbuffer, push); } -bool uvm_hal_ampere_ce_memset_validate_c6b5(uvm_push_t *push, uvm_gpu_address_t dst, size_t element_size) +bool uvm_hal_ampere_ce_memset_is_valid_c6b5(uvm_push_t *push, uvm_gpu_address_t dst, size_t element_size) { uvm_gpu_t *gpu = uvm_push_get_gpu(push); diff --git a/kernel-open/nvidia-uvm/uvm_ampere_host.c b/kernel-open/nvidia-uvm/uvm_ampere_host.c index 1c5053a23..dbf7a06a8 100644 --- a/kernel-open/nvidia-uvm/uvm_ampere_host.c +++ b/kernel-open/nvidia-uvm/uvm_ampere_host.c @@ -29,7 +29,7 @@ #include "clc56f.h" #include "clc076.h" -bool uvm_hal_ampere_host_method_validate(uvm_push_t *push, NvU32 method_address, NvU32 method_data) +bool uvm_hal_ampere_host_method_is_valid(uvm_push_t *push, NvU32 method_address, NvU32 method_data) { uvm_gpu_t *gpu = uvm_push_get_gpu(push); @@ -82,7 +82,7 @@ bool uvm_hal_ampere_host_method_validate(uvm_push_t *push, NvU32 method_address, return true; } -bool uvm_hal_ampere_host_sw_method_validate(uvm_push_t *push, NvU32 method_address, NvU32 method_data) +bool uvm_hal_ampere_host_sw_method_is_valid(uvm_push_t *push, NvU32 method_address, NvU32 method_data) { if (!uvm_channel_is_proxy(push->channel)) return true; diff --git a/kernel-open/nvidia-uvm/uvm_api.h b/kernel-open/nvidia-uvm/uvm_api.h index 7f8d31194..66ddeaa9a 100644 --- a/kernel-open/nvidia-uvm/uvm_api.h +++ b/kernel-open/nvidia-uvm/uvm_api.h @@ -25,6 +25,7 @@ #define __UVM_API_H__ #include "uvm_types.h" +#include "uvm_common.h" #include "uvm_ioctl.h" #include "uvm_linux.h" #include "uvm_lock.h" @@ -51,8 +52,10 @@ \ params.rmStatus = uvm_global_get_status(); \ if (params.rmStatus == NV_OK) { \ - if (do_init_check) \ - params.rmStatus = uvm_va_space_initialized(uvm_va_space_get(filp)); \ + if (do_init_check) { \ + if (!uvm_fd_va_space(filp)) \ + params.rmStatus = NV_ERR_ILLEGAL_ACTION; \ + } \ if (likely(params.rmStatus == NV_OK)) \ params.rmStatus = function_name(¶ms, filp); \ } \ @@ -88,8 +91,10 @@ \ params->rmStatus = uvm_global_get_status(); \ if (params->rmStatus == NV_OK) { \ - if (do_init_check) \ - params->rmStatus = uvm_va_space_initialized(uvm_va_space_get(filp)); \ + if (do_init_check) { \ + if (!uvm_fd_va_space(filp)) \ + params->rmStatus = NV_ERR_ILLEGAL_ACTION; \ + } \ if (likely(params->rmStatus == NV_OK)) \ params->rmStatus = function_name(params, filp); \ } \ diff --git a/kernel-open/nvidia-uvm/uvm_ce_test.c b/kernel-open/nvidia-uvm/uvm_ce_test.c index e12242f97..5bb1c106d 100644 --- a/kernel-open/nvidia-uvm/uvm_ce_test.c +++ b/kernel-open/nvidia-uvm/uvm_ce_test.c @@ -24,6 +24,7 @@ #include "uvm_channel.h" #include "uvm_global.h" #include "uvm_hal.h" +#include "uvm_kvmalloc.h" #include "uvm_push.h" #include "uvm_test.h" #include "uvm_tracker.h" @@ -655,9 +656,11 @@ static NV_STATUS test_ce(uvm_va_space_t *va_space, bool skipTimestampTest) TEST_NV_CHECK_RET(test_memcpy_and_memset(gpu)); TEST_NV_CHECK_RET(test_semaphore_reduction_inc(gpu)); TEST_NV_CHECK_RET(test_semaphore_release(gpu)); + if (!skipTimestampTest) TEST_NV_CHECK_RET(test_semaphore_timestamp(gpu)); - } + + } return NV_OK; } diff --git a/kernel-open/nvidia-uvm/uvm_channel.c b/kernel-open/nvidia-uvm/uvm_channel.c index bcc9aeb2f..895fd846f 100644 --- a/kernel-open/nvidia-uvm/uvm_channel.c +++ b/kernel-open/nvidia-uvm/uvm_channel.c @@ -77,7 +77,7 @@ static void channel_pool_lock_init(uvm_channel_pool_t *pool) uvm_spin_lock_init(&pool->spinlock, UVM_LOCK_ORDER_CHANNEL); } -void uvm_channel_pool_lock(uvm_channel_pool_t *pool) +static void channel_pool_lock(uvm_channel_pool_t *pool) { if (uvm_channel_pool_is_proxy(pool)) uvm_mutex_lock(&pool->mutex); @@ -85,7 +85,7 @@ void uvm_channel_pool_lock(uvm_channel_pool_t *pool) uvm_spin_lock(&pool->spinlock); } -void uvm_channel_pool_unlock(uvm_channel_pool_t *pool) +static void channel_pool_unlock(uvm_channel_pool_t *pool) { if (uvm_channel_pool_is_proxy(pool)) uvm_mutex_unlock(&pool->mutex); @@ -93,14 +93,6 @@ void uvm_channel_pool_unlock(uvm_channel_pool_t *pool) uvm_spin_unlock(&pool->spinlock); } -void uvm_channel_pool_assert_locked(uvm_channel_pool_t *pool) -{ - if (uvm_channel_pool_is_proxy(pool)) - uvm_assert_mutex_locked(&pool->mutex); - else - uvm_assert_spinlock_locked(&pool->spinlock); -} - // Update channel progress, completing up to max_to_complete entries static NvU32 uvm_channel_update_progress_with_max(uvm_channel_t *channel, NvU32 max_to_complete, @@ -113,12 +105,14 @@ static NvU32 uvm_channel_update_progress_with_max(uvm_channel_t *channel, NvU64 completed_value = uvm_channel_update_completed_value(channel); - uvm_channel_pool_lock(channel->pool); + channel_pool_lock(channel->pool); // Completed value should never exceed the queued value UVM_ASSERT_MSG_RELEASE(completed_value <= channel->tracking_sem.queued_value, "GPU %s channel %s unexpected completed_value 0x%llx > queued_value 0x%llx\n", - channel->pool->manager->gpu->parent->name, channel->name, completed_value, + channel->pool->manager->gpu->parent->name, + channel->name, + completed_value, channel->tracking_sem.queued_value); cpu_put = channel->cpu_put; @@ -141,7 +135,7 @@ static NvU32 uvm_channel_update_progress_with_max(uvm_channel_t *channel, channel->gpu_get = gpu_get; - uvm_channel_pool_unlock(channel->pool); + channel_pool_unlock(channel->pool); if (cpu_put >= gpu_get) pending_gpfifos = cpu_put - gpu_get; @@ -154,7 +148,8 @@ static NvU32 uvm_channel_update_progress_with_max(uvm_channel_t *channel, NvU32 uvm_channel_update_progress(uvm_channel_t *channel) { // By default, don't complete too many entries at a time to spread the cost - // of doing so across callers and avoid holding a spin lock for too long. + // of doing so across callers and avoid potentially holding a spin lock for + // too long. return uvm_channel_update_progress_with_max(channel, 8, UVM_CHANNEL_UPDATE_MODE_COMPLETED); } @@ -186,70 +181,95 @@ NvU32 uvm_channel_manager_update_progress(uvm_channel_manager_t *channel_manager return pending_gpfifos; } -static bool channel_is_available(uvm_channel_t *channel, NvU32 num_gpfifo_entries) +static NvU32 channel_get_available_gpfifo_entries(uvm_channel_t *channel) { - NvU32 pending_entries; + NvU32 available = channel->num_gpfifo_entries; uvm_channel_pool_assert_locked(channel->pool); - if (channel->cpu_put >= channel->gpu_get) - pending_entries = channel->cpu_put - channel->gpu_get; - else - pending_entries = channel->cpu_put + channel->num_gpfifo_entries - channel->gpu_get; + // Remove sentinel entry + available -= 1; - return (pending_entries + channel->current_gpfifo_count + num_gpfifo_entries < channel->num_gpfifo_entries); + // Remove entries of ongoing pushes + available -= channel->current_gpfifo_count; + + // Remove pending entries + if (channel->cpu_put >= channel->gpu_get) + available -= (channel->cpu_put - channel->gpu_get); + else + available -= (channel->cpu_put + channel->num_gpfifo_entries - channel->gpu_get); + + UVM_ASSERT(available < channel->num_gpfifo_entries); + + return available; } -static bool try_claim_channel(uvm_channel_t *channel, NvU32 num_gpfifo_entries) +NvU32 uvm_channel_get_available_gpfifo_entries(uvm_channel_t *channel) +{ + NvU32 available; + + channel_pool_lock(channel->pool); + available = channel_get_available_gpfifo_entries(channel); + channel_pool_unlock(channel->pool); + + return available; +} + +static bool try_claim_channel_locked(uvm_channel_t *channel, NvU32 num_gpfifo_entries) { bool claimed = false; UVM_ASSERT(num_gpfifo_entries > 0); UVM_ASSERT(num_gpfifo_entries < channel->num_gpfifo_entries); - uvm_channel_pool_lock(channel->pool); + uvm_channel_pool_assert_locked(channel->pool); - if (channel_is_available(channel, num_gpfifo_entries)) { + if (channel_get_available_gpfifo_entries(channel) >= num_gpfifo_entries) { channel->current_gpfifo_count += num_gpfifo_entries; claimed = true; } - uvm_channel_pool_unlock(channel->pool); + return claimed; +} + +static bool try_claim_channel(uvm_channel_t *channel, NvU32 num_gpfifo_entries) +{ + bool claimed; + + channel_pool_lock(channel->pool); + claimed = try_claim_channel_locked(channel, num_gpfifo_entries); + channel_pool_unlock(channel->pool); return claimed; } -static void lock_push(uvm_channel_t *channel) +static void unlock_channel_for_push(uvm_channel_t *channel) { } -static void unlock_push(uvm_channel_t *channel) +static bool is_channel_locked_for_push(uvm_channel_t *channel) { -} -static bool trylock_push(uvm_channel_t *channel) -{ + // For CE and proxy channels, we always return that the channel is locked, + // which has no functional impact in the UVM channel code-flow, this is only + // used on UVM_ASSERTs. return true; } -// Reserve a channel in the specified pool -static NV_STATUS channel_reserve_in_pool(uvm_channel_pool_t *pool, uvm_channel_t **channel_out) +// Reserve a channel in the specified CE pool +static NV_STATUS channel_reserve_in_ce_pool(uvm_channel_pool_t *pool, uvm_channel_t **channel_out) { uvm_channel_t *channel; uvm_spin_loop_t spin; UVM_ASSERT(pool); + UVM_ASSERT(uvm_channel_pool_is_ce(pool)); uvm_for_each_channel_in_pool(channel, pool) { // TODO: Bug 1764953: Prefer idle/less busy channels - if (trylock_push(channel)) { - if (try_claim_channel(channel, 1)) { - *channel_out = channel; - return NV_OK; - } - else { - unlock_push(channel); - } + if (try_claim_channel(channel, 1)) { + *channel_out = channel; + return NV_OK; } } @@ -261,7 +281,6 @@ static NV_STATUS channel_reserve_in_pool(uvm_channel_pool_t *pool, uvm_channel_t uvm_channel_update_progress(channel); if (try_claim_channel(channel, 1)) { - lock_push(channel); *channel_out = channel; return NV_OK; @@ -281,9 +300,12 @@ static NV_STATUS channel_reserve_in_pool(uvm_channel_pool_t *pool, uvm_channel_t NV_STATUS uvm_channel_reserve_type(uvm_channel_manager_t *manager, uvm_channel_type_t type, uvm_channel_t **channel_out) { + uvm_channel_pool_t *pool = manager->pool_to_use.default_for_type[type]; + + UVM_ASSERT(pool != NULL); UVM_ASSERT(type < UVM_CHANNEL_TYPE_COUNT); - return channel_reserve_in_pool(manager->pool_to_use.default_for_type[type], channel_out); + return channel_reserve_in_ce_pool(pool, channel_out); } NV_STATUS uvm_channel_reserve_gpu_to_gpu(uvm_channel_manager_t *manager, @@ -299,7 +321,7 @@ NV_STATUS uvm_channel_reserve_gpu_to_gpu(uvm_channel_manager_t *manager, UVM_ASSERT(pool->pool_type == UVM_CHANNEL_POOL_TYPE_CE); - return channel_reserve_in_pool(pool, channel_out); + return channel_reserve_in_ce_pool(pool, channel_out); } NV_STATUS uvm_channel_manager_wait(uvm_channel_manager_t *manager) @@ -323,14 +345,14 @@ static NvU32 channel_get_available_push_info_index(uvm_channel_t *channel) { uvm_push_info_t *push_info; - uvm_channel_pool_lock(channel->pool); + channel_pool_lock(channel->pool); push_info = list_first_entry_or_null(&channel->available_push_infos, uvm_push_info_t, available_list_node); UVM_ASSERT(push_info != NULL); UVM_ASSERT(push_info->on_complete == NULL && push_info->on_complete_data == NULL); list_del(&push_info->available_list_node); - uvm_channel_pool_unlock(channel->pool); + channel_pool_unlock(channel->pool); return push_info - channel->push_infos; } @@ -345,6 +367,8 @@ NV_STATUS uvm_channel_begin_push(uvm_channel_t *channel, uvm_push_t *push) manager = channel->pool->manager; + UVM_ASSERT(is_channel_locked_for_push(channel)); + status = uvm_pushbuffer_begin_push(manager->pushbuffer, push); if (status != NV_OK) return status; @@ -439,7 +463,7 @@ void uvm_channel_end_push(uvm_push_t *push) NvU32 cpu_put; NvU32 new_cpu_put; - uvm_channel_pool_lock(channel->pool); + channel_pool_lock(channel->pool); new_tracking_value = ++channel->tracking_sem.queued_value; new_payload = (NvU32)new_tracking_value; @@ -476,8 +500,8 @@ void uvm_channel_end_push(uvm_push_t *push) // may notice the GPU work to be completed and hence all state tracking the // push must be updated before that. Notably uvm_pushbuffer_end_push() has // to be called first. - uvm_channel_pool_unlock(channel->pool); - unlock_push(channel); + unlock_channel_for_push(channel); + channel_pool_unlock(channel->pool); // This memory barrier is borrowed from CUDA, as it supposedly fixes perf // issues on some systems. Comment from CUDA: "fixes throughput-related @@ -500,7 +524,7 @@ static void write_ctrl_gpfifo(uvm_channel_t *channel, NvU64 ctrl_fifo_entry_valu NvU32 new_cpu_put; uvm_gpu_t *gpu = channel->pool->manager->gpu; - uvm_channel_pool_lock(channel->pool); + channel_pool_lock(channel->pool); cpu_put = channel->cpu_put; new_cpu_put = (cpu_put + 1) % channel->num_gpfifo_entries; @@ -534,9 +558,10 @@ static void write_ctrl_gpfifo(uvm_channel_t *channel, NvU64 ctrl_fifo_entry_valu // The moment the channel is unlocked uvm_channel_update_progress_with_max() // may notice the GPU work to be completed and hence all state tracking the - // push must be updated before that. - uvm_channel_pool_unlock(channel->pool); - unlock_push(channel); + // push must be updated before that. Note that we do not call + // unlock_channel_for_push() because a control GPFIFO is followed by a + // semaphore release, where the channel is unlocked. + channel_pool_unlock(channel->pool); // This memory barrier is borrowed from CUDA, as it supposedly fixes perf // issues on some systems. Comment from CUDA: "fixes throughput-related @@ -593,7 +618,7 @@ NV_STATUS uvm_channel_reserve(uvm_channel_t *channel, NvU32 num_gpfifo_entries) uvm_spin_loop_t spin; if (try_claim_channel(channel, num_gpfifo_entries)) - goto out; + return NV_OK; uvm_channel_update_progress(channel); @@ -604,10 +629,6 @@ NV_STATUS uvm_channel_reserve(uvm_channel_t *channel, NvU32 num_gpfifo_entries) uvm_channel_update_progress(channel); } -out: - if (status == NV_OK) - lock_push(channel); - return status; } @@ -621,12 +642,12 @@ static uvm_gpfifo_entry_t *uvm_channel_get_first_pending_entry(uvm_channel_t *ch if (pending_count == 0) return NULL; - uvm_channel_pool_lock(channel->pool); + channel_pool_lock(channel->pool); if (channel->gpu_get != channel->cpu_put) entry = &channel->gpfifo_entries[channel->gpu_get]; - uvm_channel_pool_unlock(channel->pool); + channel_pool_unlock(channel->pool); return entry; } @@ -780,18 +801,17 @@ static NV_STATUS internal_channel_create(uvm_channel_t *channel, unsigned engine uvm_channel_manager_t *manager = channel->pool->manager; uvm_gpu_t *gpu = manager->gpu; - if (uvm_channel_is_ce(channel)) { - UVM_ASSERT(channel->pool->pool_type == UVM_CHANNEL_POOL_TYPE_CE); - } - memset(&channel_alloc_params, 0, sizeof(channel_alloc_params)); channel_alloc_params.numGpFifoEntries = manager->conf.num_gpfifo_entries; channel_alloc_params.gpFifoLoc = manager->conf.gpfifo_loc; channel_alloc_params.gpPutLoc = manager->conf.gpput_loc; channel_alloc_params.engineIndex = engine_index; - if (uvm_channel_is_ce(channel)) + if (uvm_channel_is_ce(channel)) { + UVM_ASSERT(channel->pool->pool_type == UVM_CHANNEL_POOL_TYPE_CE); + channel_alloc_params.engineType = UVM_GPU_CHANNEL_ENGINE_TYPE_CE; + } status = uvm_rm_locked_call(nvUvmInterfaceChannelAllocate(gpu->rm_address_space, &channel_alloc_params, @@ -923,7 +943,7 @@ NvU64 uvm_channel_tracking_semaphore_get_gpu_va_in_channel(uvm_channel_t *semaph return uvm_gpu_semaphore_get_gpu_va(semaphore, gpu, uvm_channel_is_proxy(access_channel)); } -static NV_STATUS init_channel(uvm_channel_t *channel) +static NV_STATUS channel_init(uvm_channel_t *channel) { uvm_push_t push; uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); @@ -1010,6 +1030,7 @@ static NV_STATUS channel_pool_add(uvm_channel_manager_t *channel_manager, channel_pool_lock_init(pool); num_channels = channel_pool_type_num_channels(pool_type); + UVM_ASSERT(num_channels <= UVM_CHANNEL_MAX_NUM_CHANNELS_PER_POOL); pool->channels = uvm_kvmalloc_zero(sizeof(*pool->channels) * num_channels); if (!pool->channels) @@ -1024,7 +1045,7 @@ static NV_STATUS channel_pool_add(uvm_channel_manager_t *channel_manager, if (status != NV_OK) goto error; - status = init_channel(channel); + status = channel_init(channel); if (status != NV_OK) goto error; } @@ -1404,15 +1425,55 @@ static void init_channel_manager_conf(uvm_channel_manager_t *manager) manager->conf.gpput_loc = string_to_buffer_location(gpput_loc_value); } -// A pool is created for each usable CE, even if it has not been selected as the -// preferred CE for any type, because as more information is discovered (for -// example, a pair of peer GPUs is added) we may start using the previously idle -// channels. +// Returns the maximum number of pools that are needed in the current +// configuration. The implementation may choose to create a smaller number of +// pools. +static unsigned channel_manager_get_max_pools(uvm_channel_manager_t *manager) +{ + unsigned num_channel_pools; + unsigned num_used_ce = bitmap_weight(manager->ce_mask, UVM_COPY_ENGINE_COUNT_MAX); + + // Create one CE channel pool per usable CE + num_channel_pools = num_used_ce; + + // CE proxy channel pool. + if (uvm_gpu_uses_proxy_channel_pool(manager->gpu)) + num_channel_pools++; + + return num_channel_pools; +} + +static NV_STATUS channel_manager_create_ce_pools(uvm_channel_manager_t *manager, unsigned *preferred_ce) +{ + unsigned ce; + + // A pool is created for each usable CE, even if it has not been selected as + // the preferred CE for any type, because as more information is discovered + // (for example, a pair of peer GPUs is added) we may start using the + // previously idle pools. + for_each_set_bit(ce, manager->ce_mask, UVM_COPY_ENGINE_COUNT_MAX) { + NV_STATUS status; + unsigned type; + uvm_channel_pool_t *pool = NULL; + + status = channel_pool_add(manager, UVM_CHANNEL_POOL_TYPE_CE, ce, &pool); + if (status != NV_OK) + return status; + + for (type = 0; type < UVM_CHANNEL_TYPE_CE_COUNT; type++) { + if (preferred_ce[type] == ce) + manager->pool_to_use.default_for_type[type] = pool; + } + } + + return NV_OK; +} + static NV_STATUS channel_manager_create_pools(uvm_channel_manager_t *manager) { NV_STATUS status; - unsigned ce, type; - unsigned num_channel_pools; + uvm_channel_type_t type; + unsigned max_channel_pools; unsigned preferred_ce[UVM_CHANNEL_TYPE_CE_COUNT]; uvm_channel_pool_t *pool = NULL; @@ -1423,36 +1484,21 @@ static NV_STATUS channel_manager_create_pools(uvm_channel_manager_t *manager) if (status != NV_OK) return status; - // CE channel pools - num_channel_pools = bitmap_weight(manager->ce_mask, UVM_COPY_ENGINE_COUNT_MAX); + max_channel_pools = channel_manager_get_max_pools(manager); - // CE proxy channel pool. - if (uvm_gpu_uses_proxy_channel_pool(manager->gpu)) - num_channel_pools++; - - manager->channel_pools = uvm_kvmalloc_zero(sizeof(*manager->channel_pools) * num_channel_pools); + manager->channel_pools = uvm_kvmalloc_zero(sizeof(*manager->channel_pools) * max_channel_pools); if (!manager->channel_pools) return NV_ERR_NO_MEMORY; - for_each_set_bit(ce, manager->ce_mask, UVM_COPY_ENGINE_COUNT_MAX) { - status = channel_pool_add(manager, UVM_CHANNEL_POOL_TYPE_CE, ce, &pool); - if (status != NV_OK) - return status; - } - - // Assign channel types to pools - for (type = 0; type < ARRAY_SIZE(preferred_ce); type++) { - unsigned ce = preferred_ce[type]; - - UVM_ASSERT(test_bit(ce, manager->ce_mask)); - - manager->pool_to_use.default_for_type[type] = channel_manager_ce_pool(manager, ce); - } + status = channel_manager_create_ce_pools(manager, preferred_ce); + if (status != NV_OK) + return status; // In SR-IOV heavy, add an additional, single-channel, pool that is // dedicated to the MEMOPS type. if (uvm_gpu_uses_proxy_channel_pool(manager->gpu)) { uvm_channel_type_t channel_type = uvm_channel_proxy_channel_type(); + status = channel_pool_add(manager, UVM_CHANNEL_POOL_TYPE_CE_PROXY, preferred_ce[channel_type], &pool); if (status != NV_OK) return status; @@ -1613,7 +1659,7 @@ static void uvm_channel_print_info(uvm_channel_t *channel, struct seq_file *s) uvm_channel_manager_t *manager = channel->pool->manager; UVM_SEQ_OR_DBG_PRINT(s, "Channel %s\n", channel->name); - uvm_channel_pool_lock(channel->pool); + channel_pool_lock(channel->pool); UVM_SEQ_OR_DBG_PRINT(s, "completed %llu\n", uvm_channel_update_completed_value(channel)); UVM_SEQ_OR_DBG_PRINT(s, "queued %llu\n", channel->tracking_sem.queued_value); @@ -1625,7 +1671,7 @@ static void uvm_channel_print_info(uvm_channel_t *channel, struct seq_file *s) UVM_SEQ_OR_DBG_PRINT(s, "Semaphore GPU VA 0x%llx\n", uvm_channel_tracking_semaphore_get_gpu_va(channel)); UVM_SEQ_OR_DBG_PRINT(s, "Semaphore CPU VA 0x%llx\n", (NvU64)(uintptr_t)channel->tracking_sem.semaphore.payload); - uvm_channel_pool_unlock(channel->pool); + channel_pool_unlock(channel->pool); } static void channel_print_push_acquires(uvm_push_acquire_info_t *push_acquire_info, struct seq_file *seq) @@ -1669,7 +1715,7 @@ static void channel_print_pushes(uvm_channel_t *channel, NvU32 finished_pushes_c NvU64 completed_value = uvm_channel_update_completed_value(channel); - uvm_channel_pool_lock(channel->pool); + channel_pool_lock(channel->pool); cpu_put = channel->cpu_put; @@ -1717,7 +1763,7 @@ static void channel_print_pushes(uvm_channel_t *channel, NvU32 finished_pushes_c channel_print_push_acquires(push_acquire_info, seq); } } - uvm_channel_pool_unlock(channel->pool); + channel_pool_unlock(channel->pool); } void uvm_channel_print_pending_pushes(uvm_channel_t *channel) diff --git a/kernel-open/nvidia-uvm/uvm_channel.h b/kernel-open/nvidia-uvm/uvm_channel.h index 2a0a5926a..2ccb7beeb 100644 --- a/kernel-open/nvidia-uvm/uvm_channel.h +++ b/kernel-open/nvidia-uvm/uvm_channel.h @@ -50,6 +50,9 @@ #define UVM_CHANNEL_NUM_GPFIFO_ENTRIES_MIN 32 #define UVM_CHANNEL_NUM_GPFIFO_ENTRIES_MAX (1024 * 1024) +// Maximum number of channels per pool. +#define UVM_CHANNEL_MAX_NUM_CHANNELS_PER_POOL 8 + // Semaphore payloads cannot advance too much between calls to // uvm_gpu_tracking_semaphore_update_completed_value(). In practice the jumps // are bound by gpfifo sizing as we have to update the completed value to @@ -61,6 +64,14 @@ // uvm_channel.h includes uvm_gpu_semaphore.h. #define UVM_GPU_SEMAPHORE_MAX_JUMP (2 * UVM_CHANNEL_NUM_GPFIFO_ENTRIES_MAX) +#define uvm_channel_pool_assert_locked(pool) ( \ +{ \ + if (uvm_channel_pool_is_proxy(pool)) \ + uvm_assert_mutex_locked(&(pool)->mutex); \ + else \ + uvm_assert_spinlock_locked(&(pool)->spinlock); \ +}) + // Channel types typedef enum { @@ -162,7 +173,20 @@ typedef struct // Pool type: Refer to the uvm_channel_pool_type_t enum. uvm_channel_pool_type_t pool_type; - // Lock protecting the state of channels in the pool + // Lock protecting the state of channels in the pool. + // + // There are two pool lock types available: spinlock and mutex. The mutex + // variant is required when the thread holding the pool lock must + // sleep (ex: acquire another mutex) deeper in the call stack, either in UVM + // or RM. For example, work submission to proxy channels in SR-IOV heavy + // entails calling an RM API that acquires a mutex, so the proxy channel + // pool must use the mutex variant. + // + // Unless the mutex is required, the spinlock is preferred. This is because, + // other than for proxy channels, work submission takes little time and does + // not involve any RM calls, so UVM can avoid any invocation that may result + // on a sleep. All non-proxy channel pools use the spinlock variant, even in + // SR-IOV heavy. union { uvm_spinlock_t spinlock; uvm_mutex_t mutex; @@ -275,7 +299,7 @@ struct uvm_channel_manager_struct unsigned num_channel_pools; // Mask containing the indexes of the usable Copy Engines. Each usable CE - // has a pool associated with it, see channel_manager_ce_pool + // has at least one pool associated with it. DECLARE_BITMAP(ce_mask, UVM_COPY_ENGINE_COUNT_MAX); struct @@ -313,10 +337,6 @@ struct uvm_channel_manager_struct // Create a channel manager for the GPU NV_STATUS uvm_channel_manager_create(uvm_gpu_t *gpu, uvm_channel_manager_t **manager_out); -void uvm_channel_pool_lock(uvm_channel_pool_t *pool); -void uvm_channel_pool_unlock(uvm_channel_pool_t *pool); -void uvm_channel_pool_assert_locked(uvm_channel_pool_t *pool); - static bool uvm_channel_pool_is_proxy(uvm_channel_pool_t *pool) { UVM_ASSERT(pool->pool_type < UVM_CHANNEL_POOL_TYPE_MASK); @@ -329,10 +349,16 @@ static bool uvm_channel_is_proxy(uvm_channel_t *channel) return uvm_channel_pool_is_proxy(channel->pool); } +static bool uvm_channel_pool_is_ce(uvm_channel_pool_t *pool) +{ + UVM_ASSERT(pool->pool_type < UVM_CHANNEL_POOL_TYPE_MASK); + + return (pool->pool_type == UVM_CHANNEL_POOL_TYPE_CE) || uvm_channel_pool_is_proxy(pool); +} + static bool uvm_channel_is_ce(uvm_channel_t *channel) { - UVM_ASSERT(channel->pool->pool_type < UVM_CHANNEL_POOL_TYPE_MASK); - return (channel->pool->pool_type == UVM_CHANNEL_POOL_TYPE_CE) || uvm_channel_is_proxy(channel); + return uvm_channel_pool_is_ce(channel->pool); } // Proxy channels are used to push page tree related methods, so their channel @@ -449,6 +475,10 @@ NV_STATUS uvm_channel_write_ctrl_gpfifo(uvm_channel_t *channel, NvU64 ctrl_fifo_ const char *uvm_channel_type_to_string(uvm_channel_type_t channel_type); const char *uvm_channel_pool_type_to_string(uvm_channel_pool_type_t channel_pool_type); +// Returns the number of available GPFIFO entries. The function internally +// acquires the channel pool lock. +NvU32 uvm_channel_get_available_gpfifo_entries(uvm_channel_t *channel); + void uvm_channel_print_pending_pushes(uvm_channel_t *channel); static uvm_gpu_t *uvm_channel_get_gpu(uvm_channel_t *channel) diff --git a/kernel-open/nvidia-uvm/uvm_channel_test.c b/kernel-open/nvidia-uvm/uvm_channel_test.c index eaca0acd9..1b7a81c4b 100644 --- a/kernel-open/nvidia-uvm/uvm_channel_test.c +++ b/kernel-open/nvidia-uvm/uvm_channel_test.c @@ -153,7 +153,6 @@ done: static NV_STATUS test_unexpected_completed_values(uvm_va_space_t *va_space) { - NV_STATUS status; uvm_gpu_t *gpu; for_each_va_space_gpu(gpu, va_space) { @@ -168,11 +167,12 @@ static NV_STATUS test_unexpected_completed_values(uvm_va_space_t *va_space) completed_value = uvm_channel_update_completed_value(channel); uvm_gpu_semaphore_set_payload(&channel->tracking_sem.semaphore, (NvU32)completed_value + 1); - TEST_CHECK_RET(uvm_global_get_status() == NV_OK); + TEST_NV_CHECK_RET(uvm_global_get_status()); uvm_channel_update_progress_all(channel); TEST_CHECK_RET(uvm_global_reset_fatal_error() == NV_ERR_INVALID_STATE); uvm_channel_manager_destroy(gpu->channel_manager); + // Destruction will hit the error again, so clear one more time. uvm_global_reset_fatal_error(); @@ -743,22 +743,6 @@ NV_STATUS test_write_ctrl_gpfifo_and_pushes(uvm_va_space_t *va_space) return NV_OK; } -static NvU32 get_available_gpfifo_entries(uvm_channel_t *channel) -{ - NvU32 pending_entries; - - uvm_channel_pool_lock(channel->pool); - - if (channel->cpu_put >= channel->gpu_get) - pending_entries = channel->cpu_put - channel->gpu_get; - else - pending_entries = channel->cpu_put + channel->num_gpfifo_entries - channel->gpu_get; - - uvm_channel_pool_unlock(channel->pool); - - return channel->num_gpfifo_entries - pending_entries - 1; -} - NV_STATUS test_write_ctrl_gpfifo_tight(uvm_va_space_t *va_space) { NV_STATUS status = NV_OK; @@ -771,9 +755,10 @@ NV_STATUS test_write_ctrl_gpfifo_tight(uvm_va_space_t *va_space) NvU64 entry; uvm_push_t push; + gpu = uvm_va_space_find_first_gpu(va_space); + for_each_va_space_gpu(gpu, va_space) { uvm_channel_manager_t *manager = gpu->channel_manager; - gpu = manager->gpu; TEST_NV_CHECK_RET(uvm_rm_mem_alloc_and_map_cpu(gpu, UVM_RM_MEM_TYPE_SYS, sizeof(*cpu_ptr), 0, &mem)); cpu_ptr = uvm_rm_mem_get_cpu_va(mem); @@ -791,6 +776,12 @@ NV_STATUS test_write_ctrl_gpfifo_tight(uvm_va_space_t *va_space) gpu->parent->host_hal->semaphore_acquire(&push, gpu_va, 1); uvm_push_end(&push); + // Flush all completed entries from the GPFIFO ring buffer. This test + // requires this flush because we verify (below with + // uvm_channel_get_available_gpfifo_entries) the number of free entries + // in the channel. + uvm_channel_update_progress_all(channel); + // Populate the remaining GPFIFO entries, leaving 2 slots available. // 2 available entries + 1 semaphore acquire (above) + 1 spare entry to // indicate a terminal condition for the GPFIFO ringbuffer, therefore we @@ -800,7 +791,7 @@ NV_STATUS test_write_ctrl_gpfifo_tight(uvm_va_space_t *va_space) uvm_push_end(&push); } - TEST_CHECK_GOTO(get_available_gpfifo_entries(channel) == 2, error); + TEST_CHECK_GOTO(uvm_channel_get_available_gpfifo_entries(channel) == 2, error); // We should have room for the control GPFIFO and the subsequent // semaphore release. @@ -936,7 +927,7 @@ done: static NV_STATUS uvm_test_channel_stress_stream(uvm_va_space_t *va_space, const UVM_TEST_CHANNEL_STRESS_PARAMS *params) { - NV_STATUS status; + NV_STATUS status = NV_OK; if (params->iterations == 0 || params->num_streams == 0) return NV_ERR_INVALID_PARAMETER; @@ -951,10 +942,7 @@ static NV_STATUS uvm_test_channel_stress_stream(uvm_va_space_t *va_space, params->iterations, params->seed, params->verbose); - if (status != NV_OK) - goto done; -done: uvm_va_space_up_read_rm(va_space); uvm_mutex_unlock(&g_uvm_global.global_lock); diff --git a/kernel-open/nvidia-uvm/uvm_common.h b/kernel-open/nvidia-uvm/uvm_common.h index f5e320b41..c890ee81c 100644 --- a/kernel-open/nvidia-uvm/uvm_common.h +++ b/kernel-open/nvidia-uvm/uvm_common.h @@ -347,6 +347,21 @@ typedef struct NvHandle user_object; } uvm_rm_user_object_t; +typedef enum +{ + UVM_FD_UNINITIALIZED, + UVM_FD_INITIALIZING, + UVM_FD_VA_SPACE, + UVM_FD_COUNT +} uvm_fd_type_t; + +// This should be large enough to fit the valid values from uvm_fd_type_t above. +// Note we can't use order_base_2(UVM_FD_COUNT) to define this because our code +// coverage tool fails due when the preprocessor expands that to a huge mess of +// ternary operators. +#define UVM_FD_TYPE_BITS 2 +#define UVM_FD_TYPE_MASK ((1UL << UVM_FD_TYPE_BITS) - 1) + // Macro used to compare two values for types that support less than operator. // It returns -1 if a < b, 1 if a > b and 0 if a == 0 #define UVM_CMP_DEFAULT(a,b) \ @@ -369,6 +384,10 @@ typedef struct // file. A NULL input returns false. bool uvm_file_is_nvidia_uvm(struct file *filp); +// Returns the type of data filp->private_data contains to and if ptr_val != +// NULL returns the value of the pointer. +uvm_fd_type_t uvm_fd_type(struct file *filp, void **ptr_val); + // Reads the first word in the supplied struct page. static inline void uvm_touch_page(struct page *page) { diff --git a/kernel-open/nvidia-uvm/uvm_forward_decl.h b/kernel-open/nvidia-uvm/uvm_forward_decl.h index 6c4a16e38..bb5fb7291 100644 --- a/kernel-open/nvidia-uvm/uvm_forward_decl.h +++ b/kernel-open/nvidia-uvm/uvm_forward_decl.h @@ -28,6 +28,8 @@ typedef struct uvm_global_struct uvm_global_t; typedef struct uvm_gpu_struct uvm_gpu_t; typedef struct uvm_parent_gpu_struct uvm_parent_gpu_t; +typedef struct uvm_gpu_chunk_struct uvm_gpu_chunk_t; +typedef struct uvm_cpu_chunk_struct uvm_cpu_chunk_t; typedef struct uvm_rm_mem_struct uvm_rm_mem_t; typedef struct uvm_mem_struct uvm_mem_t; typedef struct uvm_host_hal_struct uvm_host_hal_t; @@ -56,6 +58,7 @@ typedef struct uvm_va_range_struct uvm_va_range_t; typedef struct uvm_va_block_struct uvm_va_block_t; typedef struct uvm_va_block_test_struct uvm_va_block_test_t; typedef struct uvm_va_block_wrapper_struct uvm_va_block_wrapper_t; +typedef struct uvm_va_block_retry_struct uvm_va_block_retry_t; typedef struct uvm_va_space_struct uvm_va_space_t; typedef struct uvm_va_space_mm_struct uvm_va_space_mm_t; diff --git a/kernel-open/nvidia-uvm/uvm_global.h b/kernel-open/nvidia-uvm/uvm_global.h index 8ef84cacf..736dd3a5a 100644 --- a/kernel-open/nvidia-uvm/uvm_global.h +++ b/kernel-open/nvidia-uvm/uvm_global.h @@ -191,6 +191,16 @@ static void uvm_global_remove_parent_gpu(uvm_parent_gpu_t *parent_gpu) g_uvm_global.parent_gpus[gpu_index] = NULL; } +// Get a parent gpu by its id. +// Returns a pointer to the parent GPU object, or NULL if not found. +// +// LOCKING: requires that you hold the gpu_table_lock, the global lock, or have +// retained at least one of the child GPUs. +static uvm_parent_gpu_t *uvm_parent_gpu_get(uvm_gpu_id_t id) +{ + return g_uvm_global.parent_gpus[uvm_id_gpu_index(id)]; +} + // Get a gpu by its global id. // Returns a pointer to the GPU object, or NULL if not found. // diff --git a/kernel-open/nvidia-uvm/uvm_gpu.c b/kernel-open/nvidia-uvm/uvm_gpu.c index ecf5d02b8..3f233fac2 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu.c +++ b/kernel-open/nvidia-uvm/uvm_gpu.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -94,8 +94,6 @@ static uvm_gpu_link_type_t get_gpu_link_type(UVM_LINK_TYPE link_type) return UVM_GPU_LINK_NVLINK_3; case UVM_LINK_TYPE_NVLINK_4: return UVM_GPU_LINK_NVLINK_4; - case UVM_LINK_TYPE_C2C: - return UVM_GPU_LINK_C2C; default: return UVM_GPU_LINK_INVALID; } @@ -210,27 +208,12 @@ static bool gpu_supports_uvm(uvm_parent_gpu_t *parent_gpu) return parent_gpu->rm_info.subdeviceCount == 1; } -static bool parent_gpu_uses_canonical_form_address(uvm_parent_gpu_t *parent_gpu) +static bool platform_uses_canonical_form_address(void) { - NvU64 gpu_addr_shift; - NvU64 cpu_addr_shift; - - // PPC64LE doesn't use canonical form addresses. if (NVCPU_IS_PPC64LE) return false; - // We use big_page_size as UVM_PAGE_SIZE_64K because num_va_bits() is - // big_page_size invariant in the MMU HAL. - UVM_ASSERT(!parent_gpu->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_128K) || - (parent_gpu->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_64K)->num_va_bits() == - parent_gpu->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_128K)->num_va_bits())); - - gpu_addr_shift = parent_gpu->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_64K)->num_va_bits(); - cpu_addr_shift = fls64(TASK_SIZE - 1) + 1; - - // Refer to the comments and diagram in uvm_gpu.c:uvm_gpu_can_address(). - return gpu_addr_shift >= cpu_addr_shift; - + return true; } bool uvm_gpu_can_address(uvm_gpu_t *gpu, NvU64 addr, NvU64 size) @@ -239,6 +222,9 @@ bool uvm_gpu_can_address(uvm_gpu_t *gpu, NvU64 addr, NvU64 size) // the canonical address form. NvU64 max_va_lower; NvU64 addr_end = addr + size - 1; + NvU8 gpu_addr_shift; + NvU8 cpu_addr_shift; + NvU8 addr_shift; // Watch out for calling this too early in init UVM_ASSERT(gpu->address_space_tree.hal); @@ -246,6 +232,10 @@ bool uvm_gpu_can_address(uvm_gpu_t *gpu, NvU64 addr, NvU64 size) UVM_ASSERT(addr <= addr_end); UVM_ASSERT(size > 0); + gpu_addr_shift = gpu->address_space_tree.hal->num_va_bits(); + cpu_addr_shift = fls64(TASK_SIZE - 1) + 1; + addr_shift = gpu_addr_shift; + // Pascal+ GPUs are capable of accessing kernel pointers in various modes // by applying the same upper-bit checks that x86, ARM, and Power // processors do. x86 and ARM use canonical form addresses. For ARM, even @@ -255,13 +245,15 @@ bool uvm_gpu_can_address(uvm_gpu_t *gpu, NvU64 addr, NvU64 size) // mapped (or addressed) by the GPU/CPU when the CPU uses canonical form. // (C) regions are only accessible by the CPU. Similarly, (G) regions // are only accessible by the GPU. (X) regions are not addressible. + // Note that we only consider (V) regions, i.e., address ranges that are + // addressable by both, the CPU and GPU. // // GPU MAX VA < CPU MAX VA GPU MAX VA >= CPU MAX VA // 0xF..F +----------------+ 0xF..F +----------------+ - // |CCCCCCCCCCCCCCCC| |VVVVVVVVVVVVVVVV| - // |CCCCCCCCCCCCCCCC| |VVVVVVVVVVVVVVVV| - // |CCCCCCCCCCCCCCCC| |VVVVVVVVVVVVVVVV| - // |CCCCCCCCCCCCCCCC| CPU MIN UPPER VA|----------------| + // |VVVVVVVVVVVVVVVV| |VVVVVVVVVVVVVVVV| + // |VVVVVVVVVVVVVVVV| |VVVVVVVVVVVVVVVV| + // |VVVVVVVVVVVVVVVV| |VVVVVVVVVVVVVVVV| + // GPU MIN UPPER VA|----------------| CPU MIN UPPER VA|----------------| // |CCCCCCCCCCCCCCCC| |GGGGGGGGGGGGGGGG| // |CCCCCCCCCCCCCCCC| |GGGGGGGGGGGGGGGG| // CPU MIN UPPER VA|----------------| GPU MIN UPPER VA|----------------| @@ -270,32 +262,83 @@ bool uvm_gpu_can_address(uvm_gpu_t *gpu, NvU64 addr, NvU64 size) // CPU MAX LOWER VA|----------------| GPU MAX LOWER VA|----------------| // |CCCCCCCCCCCCCCCC| |GGGGGGGGGGGGGGGG| // |CCCCCCCCCCCCCCCC| |GGGGGGGGGGGGGGGG| - // GPU MAX VA|----------------| CPU MAX LOWER VA|----------------| + // GPU MAX LOWER VA|----------------| CPU MAX LOWER VA|----------------| // |VVVVVVVVVVVVVVVV| |VVVVVVVVVVVVVVVV| // |VVVVVVVVVVVVVVVV| |VVVVVVVVVVVVVVVV| // |VVVVVVVVVVVVVVVV| |VVVVVVVVVVVVVVVV| // 0 +----------------+ 0 +----------------+ - if (parent_gpu_uses_canonical_form_address(gpu->parent)) { - NvU64 min_va_upper = (NvU64)((NvS64)(1ULL << 63) >> (64 - gpu->address_space_tree.hal->num_va_bits())); - max_va_lower = 1ULL << (gpu->address_space_tree.hal->num_va_bits() - 1); + // On canonical form address platforms and Pascal+ GPUs. + if (platform_uses_canonical_form_address() && gpu_addr_shift > 40) { + NvU64 min_va_upper; + + // On x86, when cpu_addr_shift > gpu_addr_shift, it means the CPU uses + // 5-level paging and the GPU is pre-Hopper. On Pascal-Ada GPUs (49b + // wide VA) we set addr_shift to match a 4-level paging x86 (48b wide). + // See more details on uvm_parent_gpu_canonical_address(..); + if (cpu_addr_shift > gpu_addr_shift) + addr_shift = NVCPU_IS_X86_64 ? 48 : 49; + else if (gpu_addr_shift == 57) + addr_shift = gpu_addr_shift; + else + addr_shift = cpu_addr_shift; + + min_va_upper = (NvU64)((NvS64)(1ULL << 63) >> (64 - addr_shift)); + max_va_lower = 1ULL << (addr_shift - 1); return (addr_end < max_va_lower) || (addr >= min_va_upper); } else { - max_va_lower = 1ULL << gpu->address_space_tree.hal->num_va_bits(); + max_va_lower = 1ULL << addr_shift; return addr_end < max_va_lower; } } +// The internal UVM VAS does not use canonical form addresses. +bool uvm_gpu_can_address_kernel(uvm_gpu_t *gpu, NvU64 addr, NvU64 size) +{ + NvU64 addr_end = addr + size - 1; + NvU64 max_gpu_va; + + // Watch out for calling this too early in init + UVM_ASSERT(gpu->address_space_tree.hal); + UVM_ASSERT(gpu->address_space_tree.hal->num_va_bits() < 64); + UVM_ASSERT(addr <= addr_end); + UVM_ASSERT(size > 0); + + max_gpu_va = 1ULL << gpu->address_space_tree.hal->num_va_bits(); + return addr_end < max_gpu_va; +} + NvU64 uvm_parent_gpu_canonical_address(uvm_parent_gpu_t *parent_gpu, NvU64 addr) { - NvU32 gpu_va_bits; - NvU32 shift; + NvU8 gpu_addr_shift; + NvU8 cpu_addr_shift; + NvU8 addr_shift; + NvU64 input_addr = addr; - if (parent_gpu_uses_canonical_form_address(parent_gpu)) { - gpu_va_bits = parent_gpu->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_64K)->num_va_bits(); - shift = 64 - gpu_va_bits; - addr = (NvU64)((NvS64)(addr << shift) >> shift); + if (platform_uses_canonical_form_address()) { + // When the CPU VA width is larger than GPU's, it means that: + // On ARM: the CPU is on LVA mode and the GPU is pre-Hopper. + // On x86: the CPU uses 5-level paging and the GPU is pre-Hopper. + // We sign-extend on the 48b on ARM and on the 47b on x86 to mirror the + // behavior of CPUs with smaller (than GPU) VA widths. + gpu_addr_shift = parent_gpu->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_64K)->num_va_bits(); + cpu_addr_shift = fls64(TASK_SIZE - 1) + 1; + + if (cpu_addr_shift > gpu_addr_shift) + addr_shift = NVCPU_IS_X86_64 ? 48 : 49; + else if (gpu_addr_shift == 57) + addr_shift = gpu_addr_shift; + else + addr_shift = cpu_addr_shift; + + addr = (NvU64)((NvS64)(addr << (64 - addr_shift)) >> (64 - addr_shift)); + + // This protection acts on when the address is not covered by the GPU's + // OOR_ADDR_CHECK. This can only happen when OOR_ADDR_CHECK is in + // permissive (NO_CHECK) mode. + if ((addr << (64 - gpu_addr_shift)) != (input_addr << (64 - gpu_addr_shift))) + return input_addr; } return addr; @@ -351,7 +394,7 @@ static const char *uvm_gpu_virt_type_string(UVM_VIRT_MODE virtMode) static const char *uvm_gpu_link_type_string(uvm_gpu_link_type_t link_type) { - BUILD_BUG_ON(UVM_GPU_LINK_MAX != 7); + BUILD_BUG_ON(UVM_GPU_LINK_MAX != 6); switch (link_type) { UVM_ENUM_STRING_CASE(UVM_GPU_LINK_INVALID); @@ -360,7 +403,6 @@ static const char *uvm_gpu_link_type_string(uvm_gpu_link_type_t link_type) UVM_ENUM_STRING_CASE(UVM_GPU_LINK_NVLINK_2); UVM_ENUM_STRING_CASE(UVM_GPU_LINK_NVLINK_3); UVM_ENUM_STRING_CASE(UVM_GPU_LINK_NVLINK_4); - UVM_ENUM_STRING_CASE(UVM_GPU_LINK_C2C); UVM_ENUM_STRING_DEFAULT(); } } @@ -866,6 +908,7 @@ static NV_STATUS alloc_parent_gpu(const NvProcessorUuid *gpu_uuid, uvm_parent_gpu_t **parent_gpu_out) { uvm_parent_gpu_t *parent_gpu; + NV_STATUS status; parent_gpu = uvm_kvmalloc_zero(sizeof(*parent_gpu)); if (!parent_gpu) @@ -882,11 +925,14 @@ static NV_STATUS alloc_parent_gpu(const NvProcessorUuid *gpu_uuid, uvm_rb_tree_init(&parent_gpu->instance_ptr_table); uvm_rb_tree_init(&parent_gpu->tsg_table); + // TODO: Bug 3881835: revisit whether to use nv_kthread_q_t or workqueue. + status = errno_to_nv_status(nv_kthread_q_init(&parent_gpu->lazy_free_q, "vidmem lazy free")); + nv_kref_init(&parent_gpu->gpu_kref); *parent_gpu_out = parent_gpu; - return NV_OK; + return status; } // Allocates a uvm_gpu_t struct and initializes the basic fields and leaves all @@ -1539,6 +1585,8 @@ static void uvm_parent_gpu_destroy(nv_kref_t *nv_kref) UVM_ASSERT(parent_gpu->num_retained_gpus == 0); UVM_ASSERT(bitmap_empty(parent_gpu->valid_gpus, UVM_ID_MAX_SUB_PROCESSORS)); + nv_kthread_q_stop(&parent_gpu->lazy_free_q); + for (sub_processor_index = 0; sub_processor_index < UVM_ID_MAX_SUB_PROCESSORS; sub_processor_index++) UVM_ASSERT(!parent_gpu->gpus[sub_processor_index]); @@ -2165,12 +2213,9 @@ static NV_STATUS init_peer_access(uvm_gpu_t *gpu0, { NV_STATUS status; - UVM_ASSERT(p2p_caps_params->p2pLink != UVM_LINK_TYPE_C2C); - // check for peer-to-peer compatibility (PCI-E or NvLink). peer_caps->link_type = get_gpu_link_type(p2p_caps_params->p2pLink); if (peer_caps->link_type == UVM_GPU_LINK_INVALID - || peer_caps->link_type == UVM_GPU_LINK_C2C ) return NV_ERR_NOT_SUPPORTED; @@ -2553,7 +2598,10 @@ uvm_aperture_t uvm_gpu_peer_aperture(uvm_gpu_t *local_gpu, uvm_gpu_t *remote_gpu uvm_aperture_t uvm_gpu_page_tree_init_location(const uvm_gpu_t *gpu) { // See comment in page_tree_set_location - return uvm_gpu_is_virt_mode_sriov_heavy(gpu)? UVM_APERTURE_VID : UVM_APERTURE_DEFAULT; + if (uvm_gpu_is_virt_mode_sriov_heavy(gpu)) + return UVM_APERTURE_VID; + + return UVM_APERTURE_DEFAULT; } uvm_processor_id_t uvm_gpu_get_processor_id_by_address(uvm_gpu_t *gpu, uvm_gpu_phys_address_t addr) @@ -2964,9 +3012,6 @@ NV_STATUS uvm_gpu_fault_entry_to_va_space(uvm_gpu_t *gpu, exit_unlock: uvm_spin_unlock(&gpu->parent->instance_ptr_table_lock); - if (status == NV_OK) - UVM_ASSERT(uvm_va_space_initialized(*out_va_space) == NV_OK); - return status; } @@ -3005,9 +3050,6 @@ NV_STATUS uvm_gpu_access_counter_entry_to_va_space(uvm_gpu_t *gpu, exit_unlock: uvm_spin_unlock(&gpu->parent->instance_ptr_table_lock); - if (status == NV_OK) - UVM_ASSERT(uvm_va_space_initialized(*out_va_space) == NV_OK); - return status; } diff --git a/kernel-open/nvidia-uvm/uvm_gpu.h b/kernel-open/nvidia-uvm/uvm_gpu.h index 2ddcd32eb..ca68a256c 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu.h +++ b/kernel-open/nvidia-uvm/uvm_gpu.h @@ -386,7 +386,8 @@ struct uvm_access_counter_service_batch_context_struct // Virtual address notifications are always aligned to 64k. This means up to 16 // different physical locations could have been accessed to trigger one notification. // The sub-granularity mask can correspond to any of them. - struct { + struct + { uvm_processor_id_t resident_processors[16]; uvm_gpu_phys_address_t phys_addresses[16]; uvm_access_counter_buffer_entry_t phys_entry; @@ -523,7 +524,6 @@ typedef enum UVM_GPU_LINK_NVLINK_2, UVM_GPU_LINK_NVLINK_3, UVM_GPU_LINK_NVLINK_4, - UVM_GPU_LINK_C2C, UVM_GPU_LINK_MAX } uvm_gpu_link_type_t; @@ -957,6 +957,10 @@ struct uvm_parent_gpu_struct // NUMA info, mainly for ATS uvm_numa_info_t numa_info; + // PMM lazy free processing queue. + // TODO: Bug 3881835: revisit whether to use nv_kthread_q_t or workqueue. + nv_kthread_q_t lazy_free_q; + // Access counter buffer info. This is only valid if supports_access_counters is set to true uvm_access_counter_buffer_info_t access_counter_buffer_info; @@ -1120,7 +1124,8 @@ struct uvm_gpu_peer_struct // deletion. NvHandle p2p_handle; - struct { + struct + { struct proc_dir_entry *peer_file[2]; struct proc_dir_entry *peer_symlink_file[2]; @@ -1364,6 +1369,16 @@ void uvm_gpu_dma_free_page(uvm_parent_gpu_t *parent_gpu, void *va, NvU64 dma_add // The GPU must be initialized before calling this function. bool uvm_gpu_can_address(uvm_gpu_t *gpu, NvU64 addr, NvU64 size); +// Returns whether the given range is within the GPU's addressable VA ranges in +// the internal GPU VA "kernel" address space, which is a linear address space. +// Therefore, the input 'addr' must not be in canonical form, even platforms +// that use to the canonical form addresses, i.e., ARM64, and x86. +// Warning: This only checks whether the GPU's MMU can support the given +// address. Some HW units on that GPU might only support a smaller range. +// +// The GPU must be initialized before calling this function. +bool uvm_gpu_can_address_kernel(uvm_gpu_t *gpu, NvU64 addr, NvU64 size); + // Returns addr's canonical form for host systems that use canonical form // addresses. NvU64 uvm_parent_gpu_canonical_address(uvm_parent_gpu_t *parent_gpu, NvU64 addr); diff --git a/kernel-open/nvidia-uvm/uvm_gpu_non_replayable_faults.c b/kernel-open/nvidia-uvm/uvm_gpu_non_replayable_faults.c index 6faf3555b..2373511a8 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_non_replayable_faults.c +++ b/kernel-open/nvidia-uvm/uvm_gpu_non_replayable_faults.c @@ -459,8 +459,6 @@ static void kill_channel_delayed(void *_user_channel) uvm_user_channel_t *user_channel = (uvm_user_channel_t *)_user_channel; uvm_va_space_t *va_space = user_channel->kill_channel.va_space; - UVM_ASSERT(uvm_va_space_initialized(va_space) == NV_OK); - uvm_va_space_down_read_rm(va_space); if (user_channel->gpu_va_space) { // RM handles the fault, which will do the correct fault reporting in the diff --git a/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c b/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c index aaca5fc1b..8160fa791 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c +++ b/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c @@ -1034,6 +1034,61 @@ static NV_STATUS preprocess_fault_batch(uvm_gpu_t *gpu, uvm_fault_service_batch_ return NV_OK; } +static bool check_fault_entry_duplicate(const uvm_fault_buffer_entry_t *current_entry, + const uvm_fault_buffer_entry_t *previous_entry) +{ + bool is_duplicate = false; + + if (previous_entry) { + is_duplicate = (current_entry->va_space == previous_entry->va_space) && + (current_entry->fault_address == previous_entry->fault_address); + } + + return is_duplicate; +} + +static void fault_entry_duplicate_flags(uvm_fault_buffer_entry_t *current_entry, + const uvm_fault_buffer_entry_t *previous_entry) +{ + UVM_ASSERT(previous_entry); + UVM_ASSERT(check_fault_entry_duplicate(current_entry, previous_entry)); + + // Propagate the is_invalid_prefetch flag across all prefetch faults + // on the page + if (previous_entry->is_invalid_prefetch) + current_entry->is_invalid_prefetch = true; + + // If a page is throttled, all faults on the page must be skipped + if (previous_entry->is_throttled) + current_entry->is_throttled = true; +} + +static void update_batch_context(uvm_fault_service_batch_context_t *batch_context, + uvm_fault_buffer_entry_t *current_entry, + const uvm_fault_buffer_entry_t *previous_entry) +{ + bool is_duplicate = check_fault_entry_duplicate(current_entry, previous_entry); + uvm_fault_utlb_info_t *utlb = &batch_context->utlbs[current_entry->fault_source.utlb_id]; + + UVM_ASSERT(utlb->num_pending_faults > 0); + + if (is_duplicate) + batch_context->num_duplicate_faults += current_entry->num_instances; + else + batch_context->num_duplicate_faults += current_entry->num_instances - 1; + + if (current_entry->is_invalid_prefetch) + batch_context->num_invalid_prefetch_faults += current_entry->num_instances; + + if (current_entry->is_fatal) { + utlb->has_fatal_faults = true; + batch_context->has_fatal_faults = true; + } + + if (current_entry->is_throttled) + batch_context->has_throttled_faults = true; +} + // This function computes the maximum access type that can be serviced for the // reported fault instances given the logical permissions of the VA range. If // none of the fault instances can be serviced UVM_FAULT_ACCESS_TYPE_COUNT is @@ -1122,12 +1177,12 @@ static uvm_fault_access_type_t check_fault_access_permissions(uvm_gpu_t *gpu, // - NV_ERR_MORE_PROCESSING_REQUIRED if servicing needs allocation retry // - NV_ERR_NO_MEMORY if the faults could not be serviced due to OOM // - Any other value is a UVM-global error -static NV_STATUS service_batch_managed_faults_in_block_locked(uvm_gpu_t *gpu, - uvm_va_block_t *va_block, - uvm_va_block_retry_t *va_block_retry, - NvU32 first_fault_index, - uvm_fault_service_batch_context_t *batch_context, - NvU32 *block_faults) +static NV_STATUS service_fault_batch_block_locked(uvm_gpu_t *gpu, + uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_fault_service_batch_context_t *batch_context, + NvU32 first_fault_index, + NvU32 *block_faults) { NV_STATUS status = NV_OK; NvU32 i; @@ -1200,7 +1255,7 @@ static NV_STATUS service_batch_managed_faults_in_block_locked(uvm_gpu_t *gpu, if (i > first_fault_index) { previous_entry = ordered_fault_cache[i - 1]; - is_duplicate = current_entry->fault_address == previous_entry->fault_address; + is_duplicate = check_fault_entry_duplicate(current_entry, previous_entry); } if (block_context->num_retries == 0) { @@ -1215,12 +1270,7 @@ static NV_STATUS service_batch_managed_faults_in_block_locked(uvm_gpu_t *gpu, // Service the most intrusive fault per page, only. Waive the rest if (is_duplicate) { - // Propagate the is_invalid_prefetch flag across all prefetch - // faults on the page - current_entry->is_invalid_prefetch = previous_entry->is_invalid_prefetch; - - // If a page is throttled, all faults on the page must be skipped - current_entry->is_throttled = previous_entry->is_throttled; + fault_entry_duplicate_flags(current_entry, previous_entry); // The previous fault was non-fatal so the page has been already // serviced @@ -1316,25 +1366,8 @@ static NV_STATUS service_batch_managed_faults_in_block_locked(uvm_gpu_t *gpu, // Only update counters the first time since logical permissions cannot // change while we hold the VA space lock // TODO: Bug 1750144: That might not be true with HMM. - if (block_context->num_retries == 0) { - uvm_fault_utlb_info_t *utlb = &batch_context->utlbs[current_entry->fault_source.utlb_id]; - - if (current_entry->is_invalid_prefetch) - batch_context->num_invalid_prefetch_faults += current_entry->num_instances; - - if (is_duplicate) - batch_context->num_duplicate_faults += current_entry->num_instances; - else - batch_context->num_duplicate_faults += current_entry->num_instances - 1; - - if (current_entry->is_throttled) - batch_context->has_throttled_faults = true; - - if (current_entry->is_fatal) { - utlb->has_fatal_faults = true; - batch_context->has_fatal_faults = true; - } - } + if (block_context->num_retries == 0) + update_batch_context(batch_context, current_entry, previous_entry); } // Apply the changes computed in the fault service block context, if there @@ -1361,11 +1394,11 @@ static NV_STATUS service_batch_managed_faults_in_block_locked(uvm_gpu_t *gpu, // // See the comments for function service_fault_batch_block_locked for // implementation details and error codes. -static NV_STATUS service_batch_managed_faults_in_block(uvm_gpu_t *gpu, - uvm_va_block_t *va_block, - NvU32 first_fault_index, - uvm_fault_service_batch_context_t *batch_context, - NvU32 *block_faults) +static NV_STATUS service_fault_batch_block(uvm_gpu_t *gpu, + uvm_va_block_t *va_block, + uvm_fault_service_batch_context_t *batch_context, + NvU32 first_fault_index, + NvU32 *block_faults) { NV_STATUS status; uvm_va_block_retry_t va_block_retry; @@ -1378,12 +1411,12 @@ static NV_STATUS service_batch_managed_faults_in_block(uvm_gpu_t *gpu, uvm_mutex_lock(&va_block->lock); status = UVM_VA_BLOCK_RETRY_LOCKED(va_block, &va_block_retry, - service_batch_managed_faults_in_block_locked(gpu, - va_block, - &va_block_retry, - first_fault_index, - batch_context, - block_faults)); + service_fault_batch_block_locked(gpu, + va_block, + &va_block_retry, + batch_context, + first_fault_index, + block_faults)); tracker_status = uvm_tracker_add_tracker_safe(&batch_context->tracker, &va_block->tracker); @@ -1402,94 +1435,128 @@ typedef enum FAULT_SERVICE_MODE_CANCEL, } fault_service_mode_t; -static NV_STATUS service_non_managed_fault(uvm_fault_buffer_entry_t *current_entry, - const uvm_fault_buffer_entry_t *previous_entry, - NV_STATUS lookup_status, - uvm_gpu_va_space_t *gpu_va_space, - struct mm_struct *mm, - uvm_fault_service_batch_context_t *batch_context, - uvm_ats_fault_invalidate_t *ats_invalidate, - uvm_fault_utlb_info_t *utlb) +static NV_STATUS service_fault_batch_ats(uvm_gpu_va_space_t *gpu_va_space, + struct mm_struct *mm, + uvm_fault_service_batch_context_t *batch_context, + NvU32 first_fault_index, + NvU32 *block_faults) { - NV_STATUS status = lookup_status; - bool is_duplicate = false; - UVM_ASSERT(utlb->num_pending_faults > 0); - UVM_ASSERT(lookup_status != NV_OK); + NV_STATUS status; + uvm_gpu_t *gpu = gpu_va_space->gpu; + uvm_ats_fault_invalidate_t *ats_invalidate = &gpu->parent->fault_buffer_info.replayable.ats_invalidate; + uvm_fault_buffer_entry_t *current_entry = batch_context->ordered_fault_cache[first_fault_index]; + const uvm_fault_buffer_entry_t *previous_entry = first_fault_index > 0 ? + batch_context->ordered_fault_cache[first_fault_index - 1] : NULL; + bool is_duplicate = check_fault_entry_duplicate(current_entry, previous_entry); - if (previous_entry) { - is_duplicate = (current_entry->va_space == previous_entry->va_space) && - (current_entry->fault_address == previous_entry->fault_address); - - if (is_duplicate) { - // Propagate the is_invalid_prefetch flag across all prefetch faults - // on the page - if (previous_entry->is_invalid_prefetch) - current_entry->is_invalid_prefetch = true; - - // If a page is throttled, all faults on the page must be skipped - if (previous_entry->is_throttled) - current_entry->is_throttled = true; - } - } + if (is_duplicate) + fault_entry_duplicate_flags(current_entry, previous_entry); // Generate fault events for all fault packets uvm_perf_event_notify_gpu_fault(¤t_entry->va_space->perf_events, NULL, - gpu_va_space->gpu->id, + gpu->id, UVM_ID_INVALID, current_entry, batch_context->batch_id, is_duplicate); - if (status != NV_ERR_INVALID_ADDRESS) - return status; + // The VA isn't managed. See if ATS knows about it, unless it is a + // duplicate and the previous fault was non-fatal so the page has + // already been serviced + // + // TODO: Bug 2103669: Service more than one ATS fault at a time so we + // don't do an unconditional VA range lookup for every ATS fault. + if (!is_duplicate || previous_entry->is_fatal) + status = uvm_ats_service_fault_entry(gpu_va_space, current_entry, ats_invalidate); + else + status = NV_OK; - if (uvm_ats_can_service_faults(gpu_va_space, mm)) { - // The VA isn't managed. See if ATS knows about it, unless it is a - // duplicate and the previous fault was non-fatal so the page has - // already been serviced - if (!is_duplicate || previous_entry->is_fatal) - status = uvm_ats_service_fault_entry(gpu_va_space, current_entry, ats_invalidate); - else - status = NV_OK; + (*block_faults)++; + + update_batch_context(batch_context, current_entry, previous_entry); + + return status; +} + +static void service_fault_batch_fatal(uvm_gpu_t *gpu, + uvm_fault_service_batch_context_t *batch_context, + NvU32 first_fault_index, + NV_STATUS status, + NvU32 *block_faults) +{ + uvm_fault_buffer_entry_t *current_entry = batch_context->ordered_fault_cache[first_fault_index]; + const uvm_fault_buffer_entry_t *previous_entry = first_fault_index > 0 ? + batch_context->ordered_fault_cache[first_fault_index - 1] : NULL; + bool is_duplicate = check_fault_entry_duplicate(current_entry, previous_entry); + + if (is_duplicate) + fault_entry_duplicate_flags(current_entry, previous_entry); + + // The VA block cannot be found, set the fatal fault flag, + // unless it is a prefetch fault + if (current_entry->fault_access_type == UVM_FAULT_ACCESS_TYPE_PREFETCH) { + current_entry->is_invalid_prefetch = true; } else { - // If the VA block cannot be found, set the fatal fault flag, - // unless it is a prefetch fault - if (current_entry->fault_access_type == UVM_FAULT_ACCESS_TYPE_PREFETCH) { - current_entry->is_invalid_prefetch = true; - } - else { - current_entry->is_fatal = true; - current_entry->fatal_reason = uvm_tools_status_to_fatal_fault_reason(status); - current_entry->replayable.cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_ALL; - } + current_entry->is_fatal = true; + current_entry->fatal_reason = uvm_tools_status_to_fatal_fault_reason(status); + current_entry->replayable.cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_ALL; + } + + update_batch_context(batch_context, current_entry, previous_entry); + + uvm_perf_event_notify_gpu_fault(¤t_entry->va_space->perf_events, + NULL, + gpu->id, + UVM_ID_INVALID, + current_entry, + batch_context->batch_id, + is_duplicate); + + (*block_faults)++; +} + +static NV_STATUS service_fault_batch_dispatch(uvm_va_space_t *va_space, + uvm_gpu_va_space_t *gpu_va_space, + uvm_fault_service_batch_context_t *batch_context, + NvU32 first_fault_index, + NvU32 *block_faults) +{ + NV_STATUS status; + uvm_va_range_t *va_range; + uvm_va_block_t *va_block; + uvm_gpu_t *gpu = gpu_va_space->gpu; + uvm_va_block_context_t *va_block_context = + &gpu->parent->fault_buffer_info.replayable.block_service_context.block_context; + uvm_fault_buffer_entry_t *current_entry = batch_context->ordered_fault_cache[first_fault_index]; + struct mm_struct *mm = va_block_context->mm; + NvU64 fault_address = current_entry->fault_address; + + (*block_faults) = 0; + + va_range = uvm_va_range_find(va_space, fault_address); + status = uvm_va_block_find_create_in_range(va_space, va_range, fault_address, va_block_context, &va_block); + if (status == NV_OK) { + status = service_fault_batch_block(gpu, va_block, batch_context, first_fault_index, block_faults); + } + else if ((status == NV_ERR_INVALID_ADDRESS) && uvm_ats_can_service_faults(gpu_va_space, mm)) { + status = service_fault_batch_ats(gpu_va_space, mm, batch_context, first_fault_index, block_faults); + } + else { + service_fault_batch_fatal(gpu_va_space->gpu, batch_context, first_fault_index, status, block_faults); // Do not fail due to logical errors status = NV_OK; } - if (is_duplicate) - batch_context->num_duplicate_faults += current_entry->num_instances; - else - batch_context->num_duplicate_faults += current_entry->num_instances - 1; - - if (current_entry->is_invalid_prefetch) - batch_context->num_invalid_prefetch_faults += current_entry->num_instances; - - if (current_entry->is_fatal) { - utlb->has_fatal_faults = true; - batch_context->has_fatal_faults = true; - } - - if (current_entry->is_throttled) - batch_context->has_throttled_faults = true; - return status; } -// Scan the ordered view of faults and group them by different va_blocks. -// Service faults for each va_block, in batch. +// Scan the ordered view of faults and group them by different va_blocks +// (managed faults) and service faults for each va_block, in batch. +// Service non-managed faults one at a time as they are encountered during the +// scan. // // This function returns NV_WARN_MORE_PROCESSING_REQUIRED if the fault buffer // was flushed because the needs_fault_buffer_flush flag was set on some GPU VA @@ -1503,9 +1570,9 @@ static NV_STATUS service_fault_batch(uvm_gpu_t *gpu, uvm_va_space_t *va_space = NULL; uvm_gpu_va_space_t *gpu_va_space = NULL; uvm_ats_fault_invalidate_t *ats_invalidate = &gpu->parent->fault_buffer_info.replayable.ats_invalidate; + struct mm_struct *mm = NULL; const bool replay_per_va_block = service_mode != FAULT_SERVICE_MODE_CANCEL && gpu->parent->fault_buffer_info.replayable.replay_policy == UVM_PERF_FAULT_REPLAY_POLICY_BLOCK; - struct mm_struct *mm = NULL; uvm_va_block_context_t *va_block_context = &gpu->parent->fault_buffer_info.replayable.block_service_context.block_context; @@ -1514,7 +1581,6 @@ static NV_STATUS service_fault_batch(uvm_gpu_t *gpu, ats_invalidate->write_faults_in_batch = false; for (i = 0; i < batch_context->num_coalesced_faults;) { - uvm_va_block_t *va_block; NvU32 block_faults; uvm_fault_buffer_entry_t *current_entry = batch_context->ordered_fault_cache[i]; uvm_fault_utlb_info_t *utlb = &batch_context->utlbs[current_entry->fault_source.utlb_id]; @@ -1548,14 +1614,11 @@ static NV_STATUS service_fault_batch(uvm_gpu_t *gpu, uvm_va_space_down_read(va_space); gpu_va_space = uvm_gpu_va_space_get_by_parent_gpu(va_space, gpu->parent); - if (gpu_va_space && gpu_va_space->needs_fault_buffer_flush) { - // flush if required and clear the flush flag + if (uvm_processor_mask_test_and_clear_atomic(&va_space->needs_fault_buffer_flush, gpu->id)) { status = fault_buffer_flush_locked(gpu, UVM_GPU_BUFFER_FLUSH_MODE_UPDATE_PUT, UVM_FAULT_REPLAY_TYPE_START, batch_context); - gpu_va_space->needs_fault_buffer_flush = false; - if (status == NV_OK) status = NV_WARN_MORE_PROCESSING_REQUIRED; @@ -1586,49 +1649,22 @@ static NV_STATUS service_fault_batch(uvm_gpu_t *gpu, continue; } - // TODO: Bug 2103669: Service more than one ATS fault at a time so we - // don't do an unconditional VA range lookup for every ATS fault. - status = uvm_va_block_find_create(va_space, - current_entry->fault_address, - va_block_context, - &va_block); - if (status == NV_OK) { - status = service_batch_managed_faults_in_block(gpu_va_space->gpu, - va_block, - i, - batch_context, - &block_faults); - - // When service_batch_managed_faults_in_block returns != NV_OK - // something really bad happened - if (status != NV_OK) - goto fail; - - i += block_faults; - } - else { - const uvm_fault_buffer_entry_t *previous_entry = i == 0? NULL : batch_context->ordered_fault_cache[i - 1]; - - status = service_non_managed_fault(current_entry, - previous_entry, - status, - gpu_va_space, - mm, - batch_context, - ats_invalidate, - utlb); - - // When service_non_managed_fault returns != NV_OK something really - // bad happened - if (status != NV_OK) - goto fail; - - ++i; + status = service_fault_batch_dispatch(va_space, gpu_va_space, batch_context, i, &block_faults); + // TODO: Bug 3900733: clean up locking in service_fault_batch(). + if (status == NV_WARN_MORE_PROCESSING_REQUIRED) { + uvm_va_space_up_read(va_space); + uvm_va_space_mm_release_unlock(va_space, mm); + mm = NULL; + va_space = NULL; continue; } + if (status != NV_OK) + goto fail; + + i += block_faults; // Don't issue replays in cancel mode - if (replay_per_va_block) { + if (replay_per_va_block && !batch_context->has_fatal_faults) { status = push_replay_on_gpu(gpu, UVM_FAULT_REPLAY_TYPE_START, batch_context); if (status != NV_OK) goto fail; diff --git a/kernel-open/nvidia-uvm/uvm_gpu_semaphore.c b/kernel-open/nvidia-uvm/uvm_gpu_semaphore.c index 616d67241..8b455715b 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_semaphore.c +++ b/kernel-open/nvidia-uvm/uvm_gpu_semaphore.c @@ -131,6 +131,7 @@ static NV_STATUS pool_alloc_page(uvm_gpu_semaphore_pool_t *pool) uvm_gpu_semaphore_pool_page_t *pool_page; NvU32 *payloads; size_t i; + uvm_rm_mem_type_t rm_mem_type = UVM_RM_MEM_TYPE_SYS; uvm_assert_mutex_locked(&pool->mutex); @@ -142,7 +143,7 @@ static NV_STATUS pool_alloc_page(uvm_gpu_semaphore_pool_t *pool) pool_page->pool = pool; status = uvm_rm_mem_alloc_and_map_all(pool->gpu, - UVM_RM_MEM_TYPE_SYS, + rm_mem_type, UVM_SEMAPHORE_PAGE_SIZE, 0, &pool_page->memory); diff --git a/kernel-open/nvidia-uvm/uvm_hal.c b/kernel-open/nvidia-uvm/uvm_hal.c index 2188a949b..7ef0e8497 100644 --- a/kernel-open/nvidia-uvm/uvm_hal.c +++ b/kernel-open/nvidia-uvm/uvm_hal.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2021 NVIDIA Corporation + Copyright (c) 2015-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -44,6 +44,10 @@ #include "clc86f.h" #include "clc8b5.h" +static int uvm_downgrade_force_membar_sys = 1; +module_param(uvm_downgrade_force_membar_sys, uint, 0644); +MODULE_PARM_DESC(uvm_downgrade_force_membar_sys, "Force all TLB invalidation downgrades to use MEMBAR_SYS"); + #define CE_OP_COUNT (sizeof(uvm_ce_hal_t) / sizeof(void *)) #define HOST_OP_COUNT (sizeof(uvm_host_hal_t) / sizeof(void *)) #define ARCH_OP_COUNT (sizeof(uvm_arch_hal_t) / sizeof(void *)) @@ -61,7 +65,7 @@ static uvm_hal_class_ops_t ce_table[] = .id = MAXWELL_DMA_COPY_A, .u.ce_ops = { .init = uvm_hal_maxwell_ce_init, - .method_validate = uvm_hal_method_validate_stub, + .method_is_valid = uvm_hal_method_is_valid_stub, .semaphore_release = uvm_hal_maxwell_ce_semaphore_release, .semaphore_timestamp = uvm_hal_maxwell_ce_semaphore_timestamp, .semaphore_reduction_inc = uvm_hal_maxwell_ce_semaphore_reduction_inc, @@ -69,11 +73,11 @@ static uvm_hal_class_ops_t ce_table[] = .offset_in_out = uvm_hal_maxwell_ce_offset_in_out, .phys_mode = uvm_hal_maxwell_ce_phys_mode, .plc_mode = uvm_hal_maxwell_ce_plc_mode, - .memcopy_validate = uvm_hal_ce_memcopy_validate_stub, + .memcopy_is_valid = uvm_hal_ce_memcopy_is_valid_stub, .memcopy_patch_src = uvm_hal_ce_memcopy_patch_src_stub, .memcopy = uvm_hal_maxwell_ce_memcopy, .memcopy_v_to_v = uvm_hal_maxwell_ce_memcopy_v_to_v, - .memset_validate = uvm_hal_ce_memset_validate_stub, + .memset_is_valid = uvm_hal_ce_memset_is_valid_stub, .memset_1 = uvm_hal_maxwell_ce_memset_1, .memset_4 = uvm_hal_maxwell_ce_memset_4, .memset_8 = uvm_hal_maxwell_ce_memset_8, @@ -99,7 +103,15 @@ static uvm_hal_class_ops_t ce_table[] = { .id = VOLTA_DMA_COPY_A, .parent_id = PASCAL_DMA_COPY_B, - .u.ce_ops = {}, + .u.ce_ops = { + .semaphore_release = uvm_hal_volta_ce_semaphore_release, + .semaphore_timestamp = uvm_hal_volta_ce_semaphore_timestamp, + .semaphore_reduction_inc = uvm_hal_volta_ce_semaphore_reduction_inc, + .memcopy = uvm_hal_volta_ce_memcopy, + .memset_1 = uvm_hal_volta_ce_memset_1, + .memset_4 = uvm_hal_volta_ce_memset_4, + .memset_8 = uvm_hal_volta_ce_memset_8, + }, }, { .id = TURING_DMA_COPY_A, @@ -110,22 +122,22 @@ static uvm_hal_class_ops_t ce_table[] = .id = AMPERE_DMA_COPY_A, .parent_id = TURING_DMA_COPY_A, .u.ce_ops = { - .method_validate = uvm_hal_ampere_ce_method_validate_c6b5, + .method_is_valid = uvm_hal_ampere_ce_method_is_valid_c6b5, .phys_mode = uvm_hal_ampere_ce_phys_mode, - .memcopy_validate = uvm_hal_ampere_ce_memcopy_validate_c6b5, + .memcopy_is_valid = uvm_hal_ampere_ce_memcopy_is_valid_c6b5, .memcopy_patch_src = uvm_hal_ampere_ce_memcopy_patch_src_c6b5, - .memset_validate = uvm_hal_ampere_ce_memset_validate_c6b5, + .memset_is_valid = uvm_hal_ampere_ce_memset_is_valid_c6b5, }, }, { .id = AMPERE_DMA_COPY_B, .parent_id = AMPERE_DMA_COPY_A, .u.ce_ops = { - .method_validate = uvm_hal_method_validate_stub, + .method_is_valid = uvm_hal_method_is_valid_stub, .plc_mode = uvm_hal_ampere_ce_plc_mode_c7b5, - .memcopy_validate = uvm_hal_ce_memcopy_validate_stub, + .memcopy_is_valid = uvm_hal_ce_memcopy_is_valid_stub, .memcopy_patch_src = uvm_hal_ce_memcopy_patch_src_stub, - .memset_validate = uvm_hal_ce_memset_validate_stub, + .memset_is_valid = uvm_hal_ce_memset_is_valid_stub, }, }, { @@ -140,6 +152,8 @@ static uvm_hal_class_ops_t ce_table[] = .memset_1 = uvm_hal_hopper_ce_memset_1, .memset_4 = uvm_hal_hopper_ce_memset_4, .memset_8 = uvm_hal_hopper_ce_memset_8, + .memcopy_is_valid = uvm_hal_hopper_ce_memcopy_is_valid, + .memset_is_valid = uvm_hal_hopper_ce_memset_is_valid, }, }, }; @@ -152,8 +166,8 @@ static uvm_hal_class_ops_t host_table[] = .id = KEPLER_CHANNEL_GPFIFO_B, .u.host_ops = { .init = uvm_hal_maxwell_host_init_noop, - .method_validate = uvm_hal_method_validate_stub, - .sw_method_validate = uvm_hal_method_validate_stub, + .method_is_valid = uvm_hal_method_is_valid_stub, + .sw_method_is_valid = uvm_hal_method_is_valid_stub, .wait_for_idle = uvm_hal_maxwell_host_wait_for_idle, .membar_sys = uvm_hal_maxwell_host_membar_sys, // No MEMBAR GPU until Pascal, just do a MEMBAR SYS. @@ -235,8 +249,8 @@ static uvm_hal_class_ops_t host_table[] = .id = AMPERE_CHANNEL_GPFIFO_A, .parent_id = TURING_CHANNEL_GPFIFO_A, .u.host_ops = { - .method_validate = uvm_hal_ampere_host_method_validate, - .sw_method_validate = uvm_hal_ampere_host_sw_method_validate, + .method_is_valid = uvm_hal_ampere_host_method_is_valid, + .sw_method_is_valid = uvm_hal_ampere_host_sw_method_is_valid, .clear_faulted_channel_sw_method = uvm_hal_ampere_host_clear_faulted_channel_sw_method, .clear_faulted_channel_register = uvm_hal_ampere_host_clear_faulted_channel_register, .tlb_invalidate_all = uvm_hal_ampere_host_tlb_invalidate_all, @@ -248,8 +262,8 @@ static uvm_hal_class_ops_t host_table[] = .id = HOPPER_CHANNEL_GPFIFO_A, .parent_id = AMPERE_CHANNEL_GPFIFO_A, .u.host_ops = { - .method_validate = uvm_hal_method_validate_stub, - .sw_method_validate = uvm_hal_method_validate_stub, + .method_is_valid = uvm_hal_method_is_valid_stub, + .sw_method_is_valid = uvm_hal_method_is_valid_stub, .semaphore_acquire = uvm_hal_hopper_host_semaphore_acquire, .semaphore_release = uvm_hal_hopper_host_semaphore_release, .semaphore_timestamp = uvm_hal_hopper_host_semaphore_timestamp, @@ -637,14 +651,20 @@ NV_STATUS uvm_hal_init_gpu(uvm_parent_gpu_t *parent_gpu) return NV_OK; } +static void hal_override_properties(uvm_parent_gpu_t *parent_gpu) +{ + // Access counters are currently not supported in vGPU. + // + // TODO: Bug 200692962: Add support for access counters in vGPU + if (parent_gpu->virt_mode != UVM_VIRT_MODE_NONE) + parent_gpu->access_counters_supported = false; +} + void uvm_hal_init_properties(uvm_parent_gpu_t *parent_gpu) { parent_gpu->arch_hal->init_properties(parent_gpu); - // Override the HAL when in non-passthrough virtualization - // TODO: Bug 200692962: [UVM] Add support for access counters in UVM on SR-IOV configurations - if (parent_gpu->virt_mode != UVM_VIRT_MODE_NONE) - parent_gpu->access_counters_supported = false; + hal_override_properties(parent_gpu); } void uvm_hal_tlb_invalidate_membar(uvm_push_t *push, uvm_membar_t membar) @@ -663,6 +683,44 @@ void uvm_hal_tlb_invalidate_membar(uvm_push_t *push, uvm_membar_t membar) uvm_hal_membar(gpu, push, membar); } +bool uvm_hal_membar_before_semaphore(uvm_push_t *push) +{ + uvm_membar_t membar = uvm_push_get_and_reset_membar_flag(push); + + if (membar == UVM_MEMBAR_NONE) { + // No MEMBAR requested, don't use a flush. + return false; + } + + if (membar == UVM_MEMBAR_GPU) { + // MEMBAR GPU requested, do it on the HOST and skip the engine flush as + // it doesn't have this capability. + uvm_hal_wfi_membar(push, UVM_MEMBAR_GPU); + return false; + } + + // By default do a MEMBAR SYS and for that we can just use flush on the + // semaphore operation. + return true; +} + +uvm_membar_t uvm_hal_downgrade_membar_type(uvm_gpu_t *gpu, bool is_local_vidmem) +{ + // If the mapped memory was local, and we're not using a coherence protocol, + // we only need a GPU-local membar. This is because all accesses to this + // memory, including those from other processors like the CPU or peer GPUs, + // must come through this GPU's L2. In all current architectures, MEMBAR_GPU + // is sufficient to resolve ordering at the L2 level. + if (is_local_vidmem && !gpu->parent->numa_info.enabled && !uvm_downgrade_force_membar_sys) + return UVM_MEMBAR_GPU; + + // If the mapped memory was remote, or if a coherence protocol can cache + // this GPU's memory, then there are external ways for other processors to + // access the memory without always going the local GPU L2, so we must use a + // MEMBAR_SYS. + return UVM_MEMBAR_SYS; +} + const char *uvm_aperture_string(uvm_aperture_t aperture) { BUILD_BUG_ON(UVM_APERTURE_MAX != 12); @@ -823,12 +881,12 @@ void uvm_hal_print_access_counter_buffer_entry(const uvm_access_counter_buffer_e UVM_DBG_PRINT(" tag %x\n", entry->tag); } -bool uvm_hal_method_validate_stub(uvm_push_t *push, NvU32 method_address, NvU32 method_data) +bool uvm_hal_method_is_valid_stub(uvm_push_t *push, NvU32 method_address, NvU32 method_data) { return true; } -bool uvm_hal_ce_memcopy_validate_stub(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src) +bool uvm_hal_ce_memcopy_is_valid_stub(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src) { return true; } @@ -837,7 +895,7 @@ void uvm_hal_ce_memcopy_patch_src_stub(uvm_push_t *push, uvm_gpu_address_t *src) { } -bool uvm_hal_ce_memset_validate_stub(uvm_push_t *push, uvm_gpu_address_t dst, size_t element_size) +bool uvm_hal_ce_memset_is_valid_stub(uvm_push_t *push, uvm_gpu_address_t dst, size_t element_size) { return true; } diff --git a/kernel-open/nvidia-uvm/uvm_hal.h b/kernel-open/nvidia-uvm/uvm_hal.h index 4f09734ff..75cbb38d5 100644 --- a/kernel-open/nvidia-uvm/uvm_hal.h +++ b/kernel-open/nvidia-uvm/uvm_hal.h @@ -34,7 +34,7 @@ // A dummy method validation that always returns true; it can be used to skip // CE/Host/SW method validations for a given architecture -bool uvm_hal_method_validate_stub(uvm_push_t *push, NvU32 method_address, NvU32 method_data); +bool uvm_hal_method_is_valid_stub(uvm_push_t *push, NvU32 method_address, NvU32 method_data); typedef void (*uvm_hal_init_t)(uvm_push_t *push); void uvm_hal_maxwell_ce_init(uvm_push_t *push); @@ -42,12 +42,12 @@ void uvm_hal_maxwell_host_init_noop(uvm_push_t *push); void uvm_hal_pascal_host_init(uvm_push_t *push); // Host method validation -typedef bool (*uvm_hal_host_method_validate)(uvm_push_t *push, NvU32 method_address, NvU32 method_data); -bool uvm_hal_ampere_host_method_validate(uvm_push_t *push, NvU32 method_address, NvU32 method_data); +typedef bool (*uvm_hal_host_method_is_valid)(uvm_push_t *push, NvU32 method_address, NvU32 method_data); +bool uvm_hal_ampere_host_method_is_valid(uvm_push_t *push, NvU32 method_address, NvU32 method_data); // SW method validation -typedef bool (*uvm_hal_host_sw_method_validate)(uvm_push_t *push, NvU32 method_address, NvU32 method_data); -bool uvm_hal_ampere_host_sw_method_validate(uvm_push_t *push, NvU32 method_address, NvU32 method_data); +typedef bool (*uvm_hal_host_sw_method_is_valid)(uvm_push_t *push, NvU32 method_address, NvU32 method_data); +bool uvm_hal_ampere_host_sw_method_is_valid(uvm_push_t *push, NvU32 method_address, NvU32 method_data); // Wait for idle typedef void (*uvm_hal_wait_for_idle_t)(uvm_push_t *push); @@ -208,6 +208,7 @@ typedef void (*uvm_hal_semaphore_release_t)(uvm_push_t *push, NvU64 gpu_va, NvU3 void uvm_hal_maxwell_host_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_maxwell_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_pascal_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); +void uvm_hal_volta_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_turing_host_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_hopper_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_hopper_host_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); @@ -220,6 +221,7 @@ void uvm_hal_hopper_host_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 typedef void (*uvm_hal_semaphore_timestamp_t)(uvm_push_t *push, NvU64 gpu_va); void uvm_hal_maxwell_ce_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va); void uvm_hal_pascal_ce_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va); +void uvm_hal_volta_ce_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va); void uvm_hal_hopper_ce_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va); void uvm_hal_maxwell_host_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va); @@ -272,16 +274,17 @@ NvU32 uvm_hal_maxwell_ce_plc_mode(void); NvU32 uvm_hal_ampere_ce_plc_mode_c7b5(void); // CE method validation -typedef bool (*uvm_hal_ce_method_validate)(uvm_push_t *push, NvU32 method_address, NvU32 method_data); -bool uvm_hal_ampere_ce_method_validate_c6b5(uvm_push_t *push, NvU32 method_address, NvU32 method_data); +typedef bool (*uvm_hal_ce_method_is_valid)(uvm_push_t *push, NvU32 method_address, NvU32 method_data); +bool uvm_hal_ampere_ce_method_is_valid_c6b5(uvm_push_t *push, NvU32 method_address, NvU32 method_data); // Memcopy validation. // The validation happens at the start of the memcopy (uvm_hal_memcopy_t) -// execution. Use uvm_hal_ce_memcopy_validate_stub to skip the validation for +// execution. Use uvm_hal_ce_memcopy_is_valid_stub to skip the validation for // a given architecture. -typedef bool (*uvm_hal_ce_memcopy_validate)(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src); -bool uvm_hal_ce_memcopy_validate_stub(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src); -bool uvm_hal_ampere_ce_memcopy_validate_c6b5(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src); +typedef bool (*uvm_hal_ce_memcopy_is_valid)(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src); +bool uvm_hal_ce_memcopy_is_valid_stub(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src); +bool uvm_hal_ampere_ce_memcopy_is_valid_c6b5(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src); +bool uvm_hal_hopper_ce_memcopy_is_valid(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src); // Patching of the memcopy source; if not needed for a given architecture use // the (empty) uvm_hal_ce_memcopy_patch_src_stub implementation @@ -296,6 +299,7 @@ void uvm_hal_ampere_ce_memcopy_patch_src_c6b5(uvm_push_t *push, uvm_gpu_address_ // UVM_PUSH_FLAG_NEXT_CE_* flags with uvm_push_set_flag(). typedef void (*uvm_hal_memcopy_t)(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src, size_t size); void uvm_hal_maxwell_ce_memcopy(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src, size_t size); +void uvm_hal_volta_ce_memcopy(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src, size_t size); // Simple wrapper for uvm_hal_memcopy_t with both addresses being virtual typedef void (*uvm_hal_memcopy_v_to_v_t)(uvm_push_t *push, NvU64 dst, NvU64 src, size_t size); @@ -303,11 +307,12 @@ void uvm_hal_maxwell_ce_memcopy_v_to_v(uvm_push_t *push, NvU64 dst, NvU64 src, s // Memset validation. // The validation happens at the start of the memset (uvm_hal_memset_*_t) -// execution. Use uvm_hal_ce_memset_validate_stub to skip the validation for +// execution. Use uvm_hal_ce_memset_is_valid_stub to skip the validation for // a given architecture. -typedef bool (*uvm_hal_ce_memset_validate)(uvm_push_t *push, uvm_gpu_address_t dst, size_t element_size); -bool uvm_hal_ce_memset_validate_stub(uvm_push_t *push, uvm_gpu_address_t dst, size_t element_size); -bool uvm_hal_ampere_ce_memset_validate_c6b5(uvm_push_t *push, uvm_gpu_address_t dst, size_t element_size); +typedef bool (*uvm_hal_ce_memset_is_valid)(uvm_push_t *push, uvm_gpu_address_t dst, size_t element_size); +bool uvm_hal_ce_memset_is_valid_stub(uvm_push_t *push, uvm_gpu_address_t dst, size_t element_size); +bool uvm_hal_ampere_ce_memset_is_valid_c6b5(uvm_push_t *push, uvm_gpu_address_t dst, size_t element_size); +bool uvm_hal_hopper_ce_memset_is_valid(uvm_push_t *push, uvm_gpu_address_t dst, size_t element_size); // Memset size bytes at dst to a given N-byte input value. // @@ -329,6 +334,10 @@ void uvm_hal_maxwell_ce_memset_4(uvm_push_t *push, uvm_gpu_address_t dst, NvU32 void uvm_hal_maxwell_ce_memset_8(uvm_push_t *push, uvm_gpu_address_t dst, NvU64 value, size_t size); void uvm_hal_maxwell_ce_memset_v_4(uvm_push_t *push, NvU64 dst_va, NvU32 value, size_t size); +void uvm_hal_volta_ce_memset_1(uvm_push_t *push, uvm_gpu_address_t dst, NvU8 value, size_t size); +void uvm_hal_volta_ce_memset_4(uvm_push_t *push, uvm_gpu_address_t dst, NvU32 value, size_t size); +void uvm_hal_volta_ce_memset_8(uvm_push_t *push, uvm_gpu_address_t dst, NvU64 value, size_t size); + void uvm_hal_hopper_ce_memset_1(uvm_push_t *push, uvm_gpu_address_t dst, NvU8 value, size_t size); void uvm_hal_hopper_ce_memset_4(uvm_push_t *push, uvm_gpu_address_t dst, NvU32 value, size_t size); void uvm_hal_hopper_ce_memset_8(uvm_push_t *push, uvm_gpu_address_t dst, NvU64 value, size_t size); @@ -342,6 +351,7 @@ void uvm_hal_hopper_ce_memset_8(uvm_push_t *push, uvm_gpu_address_t dst, NvU64 v typedef void (*uvm_hal_semaphore_reduction_inc_t)(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_maxwell_ce_semaphore_reduction_inc(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_pascal_ce_semaphore_reduction_inc(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); +void uvm_hal_volta_ce_semaphore_reduction_inc(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); void uvm_hal_hopper_ce_semaphore_reduction_inc(uvm_push_t *push, NvU64 gpu_va, NvU32 payload); // Initialize GPU architecture dependent properties @@ -579,8 +589,8 @@ void uvm_hal_turing_clear_access_counter_notifications(uvm_parent_gpu_t *parent_ struct uvm_host_hal_struct { uvm_hal_init_t init; - uvm_hal_host_method_validate method_validate; - uvm_hal_host_sw_method_validate sw_method_validate; + uvm_hal_host_method_is_valid method_is_valid; + uvm_hal_host_sw_method_is_valid sw_method_is_valid; uvm_hal_wait_for_idle_t wait_for_idle; uvm_hal_membar_sys_t membar_sys; uvm_hal_membar_gpu_t membar_gpu; @@ -612,18 +622,18 @@ struct uvm_host_hal_struct struct uvm_ce_hal_struct { uvm_hal_init_t init; - uvm_hal_ce_method_validate method_validate; + uvm_hal_ce_method_is_valid method_is_valid; uvm_hal_semaphore_release_t semaphore_release; uvm_hal_semaphore_timestamp_t semaphore_timestamp; uvm_hal_ce_offset_out_t offset_out; uvm_hal_ce_offset_in_out_t offset_in_out; uvm_hal_ce_phys_mode_t phys_mode; uvm_hal_ce_plc_mode_t plc_mode; - uvm_hal_ce_memcopy_validate memcopy_validate; + uvm_hal_ce_memcopy_is_valid memcopy_is_valid; uvm_hal_ce_memcopy_patch_src memcopy_patch_src; uvm_hal_memcopy_t memcopy; uvm_hal_memcopy_v_to_v_t memcopy_v_to_v; - uvm_hal_ce_memset_validate memset_validate; + uvm_hal_ce_memset_is_valid memset_is_valid; uvm_hal_memset_1_t memset_1; uvm_hal_memset_4_t memset_4; uvm_hal_memset_8_t memset_8; @@ -726,4 +736,20 @@ static void uvm_hal_wfi_membar(uvm_push_t *push, uvm_membar_t membar) // appropriate Host membar(s) after a TLB invalidate. void uvm_hal_tlb_invalidate_membar(uvm_push_t *push, uvm_membar_t membar); +// Internal helper used by architectures/engines that don't support a FLUSH +// operation with a FLUSH_TYPE on the semaphore release method, e.g., pre-Volta +// CE. It inspects and clears the MEMBAR push flags, issues a Host WFI + +// membar.gpu for MEMBAR_GPU or returns true to indicate the caller to use the +// engine's FLUSH for MEMBAR_SYS. +bool uvm_hal_membar_before_semaphore(uvm_push_t *push); + +// Determine the appropriate membar to use on TLB invalidates for GPU PTE +// permissions downgrades. +// +// gpu is the GPU on which the TLB invalidate is happening. +// +// is_local_vidmem indicates whether all mappings being invalidated pointed to +// the local GPU's memory. +uvm_membar_t uvm_hal_downgrade_membar_type(uvm_gpu_t *gpu, bool is_local_vidmem); + #endif // __UVM_HAL_H__ diff --git a/kernel-open/nvidia-uvm/uvm_hmm.c b/kernel-open/nvidia-uvm/uvm_hmm.c index 518424755..05fd2d47a 100644 --- a/kernel-open/nvidia-uvm/uvm_hmm.c +++ b/kernel-open/nvidia-uvm/uvm_hmm.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2022 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -23,31 +23,96 @@ #include "uvm_hmm.h" -static bool uvm_disable_hmm = false; +// TODO: Bug 1750144: Enable HMM by default once the feature is formally +// enabled for production use. + +// Support for HMM ( https://docs.kernel.org/mm/hmm.html ). HMM features are +// disabled in this driver because they are still in development. In order to +// experiment with the early, "alpha" version of HMM features in this driver, +// set "uvm_disable_hmm=0" on the kernel or module loading command line. +// However, again: +// +// HMM FEATURES IN THIS DRIVER ARE UNSUPPORTED BECAUSE THEY ARE NOT READY. +// +// ENABLING HMM IN THIS DRIVER MAY CAUSE YOUR KERNEL TO CRASH, CORRUPT DATA, +// OR OTHERWISE MISBEHAVE. DO NOT ENABLE HMM HERE UNLESS YOU ARE FULLY +// PREPARED TO DEAL WITH THE INEVITABLE BUGS AND LIMITATIONS IN THIS ALPHA +// FEATURE. +// +static bool uvm_disable_hmm = true; module_param(uvm_disable_hmm, bool, 0444); MODULE_PARM_DESC(uvm_disable_hmm, "Force-disable HMM functionality in the UVM driver. " - "Default: false (i.e, HMM is potentially enabled). Ignored if " - "HMM is not supported in the driver, or if ATS settings " - "conflict with HMM."); + "Default: true. Setting to false potentially enables HMM. USE " + "AT YOUR OWN RISK: HMM FEATURES ARE NOT READY IN THIS DRIVER. " + "Also, even with uvm_disable_hmm=false, HMM will not be " + "enabled if is not supported in this driver build " + "configuration, or if ATS settings conflict with HMM."); #if UVM_IS_CONFIG_HMM() #include +#include +#include #include +#include +#include #include "uvm_common.h" #include "uvm_gpu.h" +#include "uvm_pmm_gpu.h" +#include "uvm_hal_types.h" #include "uvm_va_block_types.h" #include "uvm_va_space_mm.h" #include "uvm_va_space.h" #include "uvm_va_range.h" #include "uvm_range_tree.h" +#include "uvm_pmm_sysmem.h" #include "uvm_lock.h" #include "uvm_api.h" #include "uvm_va_policy.h" #include "uvm_tools.h" +static NV_STATUS hmm_va_block_migrate_locked(uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t dest_id, + uvm_va_block_region_t region, + uvm_make_resident_cause_t cause); + +typedef struct +{ + uvm_processor_id_t processor_id; + uvm_processor_id_t new_residency; + uvm_va_block_t *va_block; + uvm_va_block_retry_t *va_block_retry; + uvm_service_block_context_t *service_context; + uvm_page_mask_t page_mask; + uvm_page_mask_t same_devmem_page_mask; +} uvm_hmm_gpu_fault_event_t; + +typedef struct +{ + uvm_va_block_t *va_block; + uvm_va_block_retry_t *va_block_retry; + uvm_va_block_context_t *va_block_context; + uvm_va_block_region_t region; + uvm_processor_id_t dest_id; + uvm_make_resident_cause_t cause; + uvm_page_mask_t page_mask; + uvm_page_mask_t same_devmem_page_mask; +} uvm_hmm_migrate_event_t; + +typedef struct +{ + uvm_processor_id_t processor_id; + uvm_va_block_t *va_block; + uvm_va_block_retry_t *va_block_retry; + uvm_service_block_context_t *service_context; + uvm_page_mask_t page_mask; + uvm_page_mask_t same_devmem_page_mask; +} uvm_hmm_devmem_fault_context_t; + bool uvm_hmm_is_enabled_system_wide(void) { return !uvm_disable_hmm && !g_uvm_global.ats.enabled && uvm_va_space_mm_enabled_system(); @@ -55,11 +120,9 @@ bool uvm_hmm_is_enabled_system_wide(void) bool uvm_hmm_is_enabled(uvm_va_space_t *va_space) { - // TODO: Bug 3351822: [UVM-HMM] Remove temporary testing changes. return uvm_hmm_is_enabled_system_wide() && uvm_va_space_mm_enabled(va_space) && - !(va_space->initialization_flags & UVM_INIT_FLAGS_DISABLE_HMM) && - !va_space->hmm.disable; + !(va_space->initialization_flags & UVM_INIT_FLAGS_DISABLE_HMM); } static uvm_va_block_t *hmm_va_block_from_node(uvm_range_tree_node_t *node) @@ -70,32 +133,13 @@ static uvm_va_block_t *hmm_va_block_from_node(uvm_range_tree_node_t *node) } NV_STATUS uvm_hmm_va_space_initialize(uvm_va_space_t *va_space) -{ - struct mm_struct *mm = va_space->va_space_mm.mm; - - if (!uvm_hmm_is_enabled(va_space)) - return NV_OK; - - uvm_assert_mmap_lock_locked_write(mm); - uvm_assert_rwsem_locked_write(&va_space->lock); - - // TODO: Bug 3351822: [UVM-HMM] Remove temporary testing changes. - // Disable HMM by default for each va_space until enough functionality is - // implemented that this can be enabled by default. - // Note that it can be enabled for testing under controlled circumstances. - va_space->hmm.disable = true; - - return NV_OK; -} - -NV_STATUS uvm_hmm_va_space_initialize_test(uvm_va_space_t *va_space) { uvm_hmm_va_space_t *hmm_va_space = &va_space->hmm; struct mm_struct *mm = va_space->va_space_mm.mm; int ret; - if (!uvm_hmm_is_enabled_system_wide() || !mm) - return NV_WARN_NOTHING_TO_DO; + if (!uvm_hmm_is_enabled(va_space) || !mm) + return NV_OK; if (va_space->initialization_flags & UVM_INIT_FLAGS_DISABLE_HMM) return NV_ERR_INVALID_STATE; @@ -103,9 +147,6 @@ NV_STATUS uvm_hmm_va_space_initialize_test(uvm_va_space_t *va_space) uvm_assert_mmap_lock_locked_write(mm); uvm_assert_rwsem_locked_write(&va_space->lock); - // Temporarily enable HMM for testing. - va_space->hmm.disable = false; - // Initialize MMU interval notifiers for this process. // This allows mmu_interval_notifier_insert() to be called without holding // the mmap_lock for write. @@ -128,7 +169,7 @@ void uvm_hmm_va_space_destroy(uvm_va_space_t *va_space) uvm_range_tree_node_t *node, *next; uvm_va_block_t *va_block; - if (!uvm_hmm_is_enabled(va_space) || uvm_va_space_initialized(va_space) != NV_OK) + if (!uvm_hmm_is_enabled(va_space)) return; uvm_assert_rwsem_locked_write(&va_space->lock); @@ -140,17 +181,104 @@ void uvm_hmm_va_space_destroy(uvm_va_space_t *va_space) mmu_interval_notifier_remove(&va_block->hmm.notifier); uvm_va_block_kill(va_block); } +} - // TODO: Bug 3351822: [UVM-HMM] Remove temporary testing changes. - va_space->hmm.disable = true; +static void hmm_va_block_unregister_gpu(uvm_va_block_t *va_block, + uvm_gpu_t *gpu, + struct mm_struct *mm) +{ + uvm_va_policy_node_t *node; + + uvm_mutex_lock(&va_block->lock); + + // Reset preferred location and accessed-by of policy nodes if needed. + uvm_for_each_va_policy_node_in(node, va_block, va_block->start, va_block->end) { + if (uvm_id_equal(node->policy.preferred_location, gpu->id)) + node->policy.preferred_location = UVM_ID_INVALID; + + uvm_processor_mask_clear(&node->policy.accessed_by, gpu->id); + } + + // Migrate and free any remaining resident allocations on this GPU. + uvm_va_block_unregister_gpu_locked(va_block, gpu, mm); + + uvm_mutex_unlock(&va_block->lock); +} + +void uvm_hmm_unregister_gpu(uvm_va_space_t *va_space, uvm_gpu_t *gpu, struct mm_struct *mm) +{ + uvm_range_tree_node_t *node; + uvm_va_block_t *va_block; + + if (!uvm_hmm_is_enabled(va_space)) + return; + + if (mm) + uvm_assert_mmap_lock_locked(mm); + uvm_assert_rwsem_locked_write(&va_space->lock); + + uvm_range_tree_for_each(node, &va_space->hmm.blocks) { + va_block = hmm_va_block_from_node(node); + + hmm_va_block_unregister_gpu(va_block, gpu, mm); + } + + // By now, all GPU VA spaces are removed and all HMM pages local to the + // GPU have been migrated to the CPU. Check for any orphaned pages that + // Linux might still have a reference to. + uvm_pmm_gpu_free_orphan_pages(&gpu->pmm); +} + +static void hmm_va_block_remove_gpu_va_space(uvm_va_block_t *va_block, + uvm_gpu_va_space_t *gpu_va_space, + uvm_va_block_context_t *va_block_context) +{ + uvm_mutex_lock(&va_block->lock); + + uvm_va_block_remove_gpu_va_space(va_block, gpu_va_space, va_block_context); + + uvm_mutex_unlock(&va_block->lock); + + // TODO: Bug 3660922: Need to handle read duplication at some point. + // See range_remove_gpu_va_space_managed(). +} + +void uvm_hmm_remove_gpu_va_space(uvm_va_space_t *va_space, + uvm_gpu_va_space_t *gpu_va_space, + struct mm_struct *mm) +{ + uvm_va_block_context_t *va_block_context; + uvm_range_tree_node_t *node, *next; + uvm_va_block_t *va_block; + + if (!uvm_hmm_is_enabled(va_space)) + return; + + if (mm) + uvm_assert_mmap_lock_locked(mm); + uvm_assert_rwsem_locked_write(&va_space->lock); + + va_block_context = uvm_va_space_block_context(va_space, mm); + + uvm_range_tree_for_each_safe(node, next, &va_space->hmm.blocks) { + va_block = hmm_va_block_from_node(node); + + hmm_va_block_remove_gpu_va_space(va_block, gpu_va_space, va_block_context); + } } static bool hmm_invalidate(uvm_va_block_t *va_block, const struct mmu_notifier_range *range, unsigned long cur_seq) { + uvm_thread_context_t *uvm_context = uvm_thread_context(); struct mmu_interval_notifier *mni = &va_block->hmm.notifier; + struct mm_struct *mm = mni->mm; + uvm_va_block_context_t *va_block_context; + uvm_va_block_region_t region; NvU64 start, end; + uvm_processor_id_t id; + NV_STATUS status = NV_OK; // The MMU_NOTIFY_RELEASE event isn't really needed since mn_itree_release() // doesn't remove the interval notifiers from the struct_mm so there will @@ -165,13 +293,13 @@ static bool hmm_invalidate(uvm_va_block_t *va_block, if (!mmu_notifier_range_blockable(range)) return false; - // Ignore invalidation callbacks for device private pages since the - // invalidation is handled as part of the migration process. - // Note that the va_space pointer won't be NULL if the callback is for - // MMU_NOTIFY_MIGRATE/MMU_NOTIFY_EXCLUSIVE because the va_block lock - // is already held and we have to prevent recursively getting the lock. - if ((range->event == MMU_NOTIFY_MIGRATE || range->event == MMU_NOTIFY_EXCLUSIVE) && - range->owner == va_block->hmm.va_space) + // Ignore invalidation callbacks when migrating pages since unmapping the + // source pages is handled as part of the migration process. + if (uvm_context->ignore_hmm_invalidate_va_block == va_block) + return true; + + va_block_context = uvm_va_block_context_alloc(mm); + if (!va_block_context) return true; uvm_mutex_lock(&va_block->lock); @@ -180,8 +308,6 @@ static bool hmm_invalidate(uvm_va_block_t *va_block, if (uvm_va_block_is_dead(va_block)) goto unlock; - mmu_interval_set_seq(mni, cur_seq); - // Note: unmap_vmas() does MMU_NOTIFY_UNMAP [0, 0xffffffffffffffff] // Also note that hmm_invalidate() can be called when a new va_block is not // yet inserted into the va_space->hmm.blocks table while the original @@ -197,12 +323,42 @@ static bool hmm_invalidate(uvm_va_block_t *va_block, if (start > end) goto unlock; - if (range->event == MMU_NOTIFY_UNMAP) - uvm_va_policy_clear(va_block, start, end); + mmu_interval_set_seq(mni, cur_seq); + + region = uvm_va_block_region_from_start_end(va_block, start, end); + + va_block_context->hmm.vma = NULL; + va_block_context->policy = NULL; + + // We only need to unmap GPUs since Linux handles the CPUs. + for_each_gpu_id_in_mask(id, &va_block->mapped) { + status = uvm_va_block_unmap(va_block, + va_block_context, + id, + region, + uvm_va_block_map_mask_get(va_block, id), + &va_block->tracker); + // Note that the va_block lock can be dropped, relocked, and + // NV_ERR_MORE_PROCESSING_REQUIRED returned. + if (status != NV_OK) + break; + } + + if (range->event == MMU_NOTIFY_UNMAP || range->event == MMU_NOTIFY_CLEAR) + uvm_va_block_munmap_region(va_block, region); + + if (status == NV_OK) + status = uvm_tracker_wait(&va_block->tracker); + + // Remove stale HMM struct page pointers to system memory. + uvm_va_block_remove_cpu_chunks(va_block, region); unlock: uvm_mutex_unlock(&va_block->lock); + uvm_va_block_context_free(va_block_context); + + UVM_ASSERT(status == NV_OK); return true; } @@ -229,7 +385,6 @@ NV_STATUS uvm_hmm_va_block_find(uvm_va_space_t *va_space, if (!uvm_hmm_is_enabled(va_space)) return NV_ERR_INVALID_ADDRESS; - UVM_ASSERT(uvm_va_space_initialized(va_space) == NV_OK); uvm_assert_rwsem_locked(&va_space->lock); uvm_mutex_lock(&va_space->hmm.blocks_lock); @@ -244,6 +399,84 @@ NV_STATUS uvm_hmm_va_block_find(uvm_va_space_t *va_space, return NV_OK; } +NV_STATUS uvm_hmm_va_block_cpu_find(uvm_va_space_t *va_space, + uvm_service_block_context_t *service_context, + struct vm_fault *vmf, + uvm_va_block_t **va_block_ptr) +{ + uvm_thread_context_t *uvm_context = uvm_thread_context(); + uvm_range_tree_node_t *node; + NvU64 fault_addr = vmf->address; + struct vm_area_struct *vma = vmf->vma; + uvm_va_block_t *va_block; + uvm_page_index_t page_index; + struct migrate_vma *args; + int ret; + + UVM_ASSERT(uvm_hmm_is_enabled(va_space)); + uvm_assert_rwsem_locked(&va_space->lock); + UVM_ASSERT(fault_addr >= vma->vm_start && fault_addr < vma->vm_end); + + // Note that we must find a va_block for the faulting address because + // the block had to be migrated to the GPU and a device private PTE + // inserted into the CPU page tables in order for migrate_to_ram() to be + // called. Not finding it means the va_block was destroyed while the + // Linux kernel still has a reference to the device private page which + // can only be an error. + uvm_mutex_lock(&va_space->hmm.blocks_lock); + node = uvm_range_tree_find(&va_space->hmm.blocks, fault_addr); + uvm_mutex_unlock(&va_space->hmm.blocks_lock); + + if (!node) + return NV_ERR_INVALID_ADDRESS; + + va_block = hmm_va_block_from_node(node); + page_index = uvm_va_block_cpu_page_index(va_block, fault_addr); + + // In order to reduce live locks when multiple CPU threads fault on the + // same device private PTE, call migrate_vma_setup() now before acquiring + // the va_block lock. Otherwise, each thread locks the block, sees the + // wrong reference count, unlocks the va_block, and then the next thread + // does the same thing. Winning the race here means the migration PTE is + // inserted and the other threads are more likely to wait for the migration + // PTE to be removed. TODO: Bug 3949334: migrate_vma_setup() is called + // without the va_block lock. + args = &service_context->block_context.hmm.migrate_vma_args; + args->vma = vma; + args->src = service_context->block_context.hmm.src_pfns + page_index; + args->dst = service_context->block_context.hmm.dst_pfns + page_index; + args->start = fault_addr; + args->end = fault_addr + PAGE_SIZE; + args->flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE; + args->pgmap_owner = &g_uvm_global; + args->fault_page = vmf->page; + + // Prevent MMU invalidation callbacks from deadlocking in this thread. + uvm_context->ignore_hmm_invalidate_va_block = va_block; + + ret = migrate_vma_setup(args); + UVM_ASSERT(!ret); + + uvm_context->ignore_hmm_invalidate_va_block = NULL; + + if (!(args->src[0] & MIGRATE_PFN_MIGRATE)) + return NV_ERR_BUSY_RETRY; + + service_context->block_context.hmm.vma = vma; + + *va_block_ptr = va_block; + + return NV_OK; +} + +void uvm_hmm_cpu_fault_finish(uvm_service_block_context_t *service_context) +{ + // This is here to catch retries before uvm_hmm_service_locked() is called. + // If migrate_vma_finalize() has already been called, don't call it again. + if (service_context->block_context.hmm.migrate_vma_args.vma) + migrate_vma_finalize(&service_context->block_context.hmm.migrate_vma_args); +} + static bool uvm_hmm_vma_is_valid(struct vm_area_struct *vma, unsigned long addr, bool allow_unreadable_vma) @@ -275,7 +508,6 @@ static NV_STATUS hmm_va_block_find_create(uvm_va_space_t *va_space, if (!uvm_hmm_is_enabled(va_space)) return NV_ERR_INVALID_ADDRESS; - UVM_ASSERT(uvm_va_space_initialized(va_space) == NV_OK); UVM_ASSERT(mm); UVM_ASSERT(!va_block_context || va_block_context->mm == mm); uvm_assert_mmap_lock_locked(mm); @@ -323,6 +555,8 @@ static NV_STATUS hmm_va_block_find_create(uvm_va_space_t *va_space, va_block->hmm.node.end = end; va_block->hmm.va_space = va_space; uvm_range_tree_init(&va_block->hmm.va_policy_tree); + init_waitqueue_head(&va_block->hmm.atomic_waitq); + uvm_page_mask_zero(&va_block->hmm.atomic_busy); ret = mmu_interval_notifier_insert(&va_block->hmm.notifier, mm, @@ -379,9 +613,9 @@ NV_STATUS uvm_hmm_find_vma(uvm_va_block_context_t *va_block_context, NvU64 addr) return NV_OK; } -bool uvm_hmm_va_block_context_vma_is_valid(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, - uvm_va_block_region_t region) +bool uvm_hmm_check_context_vma_is_valid(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_va_block_region_t region) { uvm_assert_mutex_locked(&va_block->lock); @@ -398,6 +632,48 @@ bool uvm_hmm_va_block_context_vma_is_valid(uvm_va_block_t *va_block, return true; } +// Migrate the given range [start end] within a va_block to dest_id. +static NV_STATUS hmm_migrate_range(uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t dest_id, + NvU64 start, + NvU64 end, + uvm_migrate_mode_t mode, + uvm_tracker_t *out_tracker) +{ + uvm_va_block_region_t region; + uvm_va_policy_node_t *node; + const uvm_va_policy_t *policy; + NV_STATUS status = NV_OK; + + uvm_mutex_lock(&va_block->lock); + + uvm_for_each_va_policy_in(policy, va_block, start, end, node, region) { + va_block_context->policy = policy; + + // Even though UVM_VA_BLOCK_RETRY_LOCKED() may unlock and relock the + // va_block lock, the policy remains valid because we hold the mmap + // lock so munmap can't remove the policy, and the va_space lock so the + // policy APIs can't change the policy. + status = UVM_VA_BLOCK_RETRY_LOCKED(va_block, + va_block_retry, + uvm_va_block_migrate_locked(va_block, + va_block_retry, + va_block_context, + region, + dest_id, + mode, + out_tracker)); + if (status != NV_OK) + break; + } + + uvm_mutex_unlock(&va_block->lock); + + return status; +} + NV_STATUS uvm_hmm_test_va_block_inject_split_error(uvm_va_space_t *va_space, NvU64 addr) { uvm_va_block_test_t *block_test; @@ -484,6 +760,8 @@ static NV_STATUS hmm_split_block(uvm_va_block_t *va_block, new_va_block->hmm.node.end = new_va_block->end; new_va_block->hmm.va_space = va_space; uvm_range_tree_init(&new_va_block->hmm.va_policy_tree); + init_waitqueue_head(&new_va_block->hmm.atomic_waitq); + uvm_page_mask_zero(&new_va_block->hmm.atomic_busy); ret = mmu_interval_notifier_insert(&new_va_block->hmm.notifier, mm, @@ -565,6 +843,12 @@ static NV_STATUS split_block_if_needed(uvm_va_block_t *va_block, NvU64 end, uvm_va_block_t **out_va_block) { + uvm_va_block_context_t *va_block_context; + uvm_va_space_t *va_space; + struct mm_struct *mm; + struct vm_area_struct *vma; + uvm_va_block_region_t region; + NvU64 addr, from, to; uvm_va_block_t *new; NV_STATUS status; @@ -587,6 +871,40 @@ static NV_STATUS split_block_if_needed(uvm_va_block_t *va_block, *out_va_block = va_block; + // Migrate any GPU data to sysmem before destroying the HMM va_block. + // We do this because the new va_range might be for a UVM external + // allocation which could be converting an address range that was first + // operated on by UVM-HMM and the exteral allocation should see that data. + va_space = va_block->hmm.va_space; + mm = va_space->va_space_mm.mm; + va_block_context = uvm_va_space_block_context(va_space, mm); + + for (addr = va_block->start; addr < va_block->end; addr = to + 1) { + vma = find_vma_intersection(mm, addr, va_block->end); + if (!vma) + break; + + from = max(addr, (NvU64)vma->vm_start); + to = min(va_block->end, (NvU64)vma->vm_end - 1); + region = uvm_va_block_region_from_start_end(va_block, from, to); + + if (!uvm_hmm_vma_is_valid(vma, from, false)) + continue; + + va_block_context->hmm.vma = vma; + + status = hmm_migrate_range(va_block, + NULL, + va_block_context, + UVM_ID_CPU, + from, + to, + UVM_MIGRATE_MODE_MAKE_RESIDENT_AND_MAP, + NULL); + if (status != NV_OK) + return status; + } + return NV_OK; } @@ -598,9 +916,9 @@ static NV_STATUS split_block_if_needed(uvm_va_block_t *va_block, // the invalidate callback due to Linux locking constraints. If a process // calls mmap()/munmap() for SAM and then creates a managed allocation, // the same VMA range can be picked and there would be a UVM/HMM va_block -// conflict. Creating a managed allocation (or other va_range) calls this -// function to remove stale HMM va_blocks or split the HMM va_block so there -// is no overlap. +// conflict. Creating a managed allocation, external allocation, or other +// va_range types, calls this function to remove stale HMM va_blocks or split +// the HMM va_block so there is no overlap. NV_STATUS uvm_hmm_va_block_reclaim(uvm_va_space_t *va_space, struct mm_struct *mm, NvU64 start, @@ -613,10 +931,8 @@ NV_STATUS uvm_hmm_va_block_reclaim(uvm_va_space_t *va_space, if (!uvm_hmm_is_enabled(va_space)) return NV_OK; - if (mm) { - UVM_ASSERT(mm == va_space->va_space_mm.mm); + if (mm) uvm_assert_mmap_lock_locked(mm); - } uvm_assert_rwsem_locked_write(&va_space->lock); // Process each HMM va_block that overlaps the interval [start, end]. @@ -692,12 +1008,80 @@ done: return status; } +static NV_STATUS hmm_set_preferred_location_locked(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t preferred_location, + NvU64 addr, + NvU64 end, + uvm_tracker_t *out_tracker) +{ + uvm_processor_mask_t set_accessed_by_processors; + const uvm_va_policy_t *old_policy; + uvm_va_policy_node_t *node; + uvm_va_block_region_t region; + uvm_processor_id_t id; + NV_STATUS status, tracker_status; + + // Note that we can't just call uvm_va_policy_set_range() for the whole + // range [addr end] because we need to examine the old value of + // policy->preferred_location before setting it. Thus we iterate over + // the existing policy nodes. + uvm_for_each_va_policy_in(old_policy, va_block, addr, end, node, region) { + if (uvm_id_equal(old_policy->preferred_location, preferred_location)) + continue; + + // If the old preferred location is a valid processor ID, remote + // mappings should be established to the new preferred location if + // accessed-by is set. + uvm_processor_mask_zero(&set_accessed_by_processors); + + if (UVM_ID_IS_VALID(old_policy->preferred_location) && + uvm_processor_mask_test(&old_policy->accessed_by, old_policy->preferred_location)) + uvm_processor_mask_set(&set_accessed_by_processors, old_policy->preferred_location); + + va_block_context->policy = uvm_va_policy_set_preferred_location(va_block, + region, + preferred_location, + old_policy); + if (!va_block_context->policy) + return NV_ERR_NO_MEMORY; + + // Establish new remote mappings if the old preferred location had + // accessed-by set. + for_each_id_in_mask(id, &set_accessed_by_processors) { + status = uvm_va_block_set_accessed_by_locked(va_block, va_block_context, id, region, out_tracker); + if (status != NV_OK) + return status; + } + + // Even though the UVM_VA_BLOCK_RETRY_LOCKED() may unlock and relock + // the va_block lock, the policy remains valid because we hold the mmap + // lock so munmap can't remove the policy, and the va_space lock so the + // policy APIs can't change the policy. + status = UVM_VA_BLOCK_RETRY_LOCKED(va_block, + NULL, + uvm_va_block_set_preferred_location_locked(va_block, + va_block_context, + region)); + + tracker_status = uvm_tracker_add_tracker_safe(out_tracker, &va_block->tracker); + if (status == NV_OK) + status = tracker_status; + + if (status != NV_OK) + return status; + } + + return NV_OK; +} + NV_STATUS uvm_hmm_set_preferred_location(uvm_va_space_t *va_space, uvm_processor_id_t preferred_location, NvU64 base, - NvU64 last_address) + NvU64 last_address, + uvm_tracker_t *out_tracker) { - bool is_default = UVM_ID_IS_INVALID(preferred_location); + uvm_va_block_context_t *va_block_context; uvm_va_block_t *va_block; NvU64 addr; NV_STATUS status = NV_OK; @@ -713,10 +1097,12 @@ NV_STATUS uvm_hmm_set_preferred_location(uvm_va_space_t *va_space, // Update HMM preferred location policy. + va_block_context = uvm_va_space_block_context(va_space, va_space->va_space_mm.mm); + for (addr = base; addr < last_address; addr = va_block->end + 1) { NvU64 end; - status = hmm_va_block_find_create(va_space, addr, true, NULL, &va_block); + status = hmm_va_block_find_create(va_space, addr, true, va_block_context, &va_block); if (status != NV_OK) break; @@ -724,18 +1110,12 @@ NV_STATUS uvm_hmm_set_preferred_location(uvm_va_space_t *va_space, uvm_mutex_lock(&va_block->lock); - status = uvm_va_policy_set_range(va_block, - addr, - end, - UVM_VA_POLICY_PREFERRED_LOCATION, - is_default, - preferred_location, - UVM_READ_DUPLICATION_MAX); - - // TODO: Bug 1750144: unset requires re-evaluating accessed-by mappings - // (see uvm_va_range_set_preferred_location's call of - // uvm_va_block_set_accessed_by), and set requires unmapping remote - // mappings (uvm_va_block_set_preferred_location_locked). + status = hmm_set_preferred_location_locked(va_block, + va_block_context, + preferred_location, + addr, + end, + out_tracker); uvm_mutex_unlock(&va_block->lock); @@ -746,12 +1126,49 @@ NV_STATUS uvm_hmm_set_preferred_location(uvm_va_space_t *va_space, return status; } +static NV_STATUS hmm_set_accessed_by_start_end_locked(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t processor_id, + NvU64 start, + NvU64 end, + uvm_tracker_t *out_tracker) +{ + uvm_va_space_t *va_space = va_block->hmm.va_space; + uvm_va_policy_node_t *node; + uvm_va_block_region_t region; + NV_STATUS status = NV_OK; + + uvm_for_each_va_policy_node_in(node, va_block, start, end) { + // Read duplication takes precedence over SetAccessedBy. + // Do not add mappings if read duplication is enabled. + if (uvm_va_policy_is_read_duplicate(&node->policy, va_space)) + continue; + + va_block_context->policy = &node->policy; + region = uvm_va_block_region_from_start_end(va_block, + max(start, node->node.start), + min(end, node->node.end)); + + status = uvm_va_block_set_accessed_by_locked(va_block, + va_block_context, + processor_id, + region, + out_tracker); + if (status != NV_OK) + break; + } + + return status; +} + NV_STATUS uvm_hmm_set_accessed_by(uvm_va_space_t *va_space, uvm_processor_id_t processor_id, bool set_bit, NvU64 base, - NvU64 last_address) + NvU64 last_address, + uvm_tracker_t *out_tracker) { + uvm_va_block_context_t *va_block_context; uvm_va_block_t *va_block; NvU64 addr; NV_STATUS status = NV_OK; @@ -767,10 +1184,12 @@ NV_STATUS uvm_hmm_set_accessed_by(uvm_va_space_t *va_space, // Update HMM accessed by policy. + va_block_context = uvm_va_space_block_context(va_space, va_space->va_space_mm.mm); + for (addr = base; addr < last_address; addr = va_block->end + 1) { NvU64 end; - status = hmm_va_block_find_create(va_space, addr, true, NULL, &va_block); + status = hmm_va_block_find_create(va_space, addr, true, va_block_context, &va_block); if (status != NV_OK) break; @@ -786,8 +1205,14 @@ NV_STATUS uvm_hmm_set_accessed_by(uvm_va_space_t *va_space, processor_id, UVM_READ_DUPLICATION_MAX); - // TODO: Bug 1750144: need to call va_block_set_accessed_by_locked() - // if read duplication isn't enabled. + if (status == NV_OK && set_bit) { + status = hmm_set_accessed_by_start_end_locked(va_block, + va_block_context, + processor_id, + addr, + end, + out_tracker); + } uvm_mutex_unlock(&va_block->lock); @@ -798,13 +1223,92 @@ NV_STATUS uvm_hmm_set_accessed_by(uvm_va_space_t *va_space, return status; } +void uvm_hmm_block_add_eviction_mappings(uvm_va_space_t *va_space, + uvm_va_block_t *va_block, + uvm_va_block_context_t *block_context) +{ + uvm_tracker_t local_tracker = UVM_TRACKER_INIT(); + uvm_va_policy_node_t *node; + uvm_va_block_region_t region; + uvm_processor_mask_t map_processors; + uvm_processor_id_t id; + NV_STATUS tracker_status; + NV_STATUS status = NV_OK; + + UVM_ASSERT(uvm_va_block_is_hmm(va_block)); + uvm_assert_mmap_lock_locked(va_space->va_space_mm.mm); + uvm_assert_rwsem_locked(&va_space->lock); + + uvm_mutex_lock(&va_block->lock); + + uvm_for_each_va_policy_node_in(node, va_block, va_block->start, va_block->end) { + block_context->policy = &node->policy; + + for_each_id_in_mask(id, &node->policy.accessed_by) { + status = hmm_set_accessed_by_start_end_locked(va_block, + block_context, + id, + node->node.start, + node->node.end, + &local_tracker); + if (status != NV_OK) + break; + + if (!uvm_va_space_map_remote_on_eviction(va_space)) + continue; + + // Exclude the processors that have been already mapped due to + // AccessedBy. + uvm_processor_mask_andnot(&map_processors, &va_block->evicted_gpus, &node->policy.accessed_by); + + for_each_gpu_id_in_mask(id, &map_processors) { + uvm_gpu_t *gpu = uvm_va_space_get_gpu(va_space, id); + uvm_va_block_gpu_state_t *gpu_state; + + if (!gpu->parent->access_counters_supported) + continue; + + gpu_state = uvm_va_block_gpu_state_get(va_block, id); + UVM_ASSERT(gpu_state); + + // TODO: Bug 2096389: uvm_va_block_add_mappings does not add + // remote mappings to read-duplicated pages. Add support for it + // or create a new function. + status = uvm_va_block_add_mappings(va_block, + block_context, + id, + region, + &gpu_state->evicted, + UvmEventMapRemoteCauseEviction); + tracker_status = uvm_tracker_add_tracker_safe(&local_tracker, &va_block->tracker); + status = (status == NV_OK) ? tracker_status : status; + if (status != NV_OK) { + UVM_ASSERT(status != NV_ERR_MORE_PROCESSING_REQUIRED); + break; + } + } + } + } + + uvm_mutex_unlock(&va_block->lock); + + tracker_status = uvm_tracker_wait_deinit(&local_tracker); + status = (status == NV_OK) ? tracker_status : status; + if (status != NV_OK) { + UVM_ERR_PRINT("Deferred mappings to evicted memory for block [0x%llx, 0x%llx] failed %s\n", + va_block->start, + va_block->end, + nvstatusToString(status)); + } +} + void uvm_hmm_find_policy_end(uvm_va_block_t *va_block, uvm_va_block_context_t *va_block_context, unsigned long addr, NvU64 *endp) { struct vm_area_struct *vma = va_block_context->hmm.vma; - uvm_va_policy_node_t *node; + const uvm_va_policy_node_t *node; NvU64 end = va_block->end; uvm_assert_mmap_lock_locked(vma->vm_mm); @@ -860,7 +1364,7 @@ NV_STATUS uvm_hmm_find_policy_vma_and_outer(uvm_va_block_t *va_block, static NV_STATUS hmm_clear_thrashing_policy(uvm_va_block_t *va_block, uvm_va_block_context_t *block_context) { - uvm_va_policy_t *policy; + const uvm_va_policy_t *policy; uvm_va_policy_node_t *node; uvm_va_block_region_t region; NV_STATUS status = NV_OK; @@ -917,7 +1421,7 @@ uvm_va_block_region_t uvm_hmm_get_prefetch_region(uvm_va_block_t *va_block, NvU64 address) { struct vm_area_struct *vma = va_block_context->hmm.vma; - uvm_va_policy_t *policy = va_block_context->policy; + const uvm_va_policy_t *policy = va_block_context->policy; NvU64 start, end; UVM_ASSERT(uvm_va_block_is_hmm(va_block)); @@ -927,7 +1431,7 @@ uvm_va_block_region_t uvm_hmm_get_prefetch_region(uvm_va_block_t *va_block, end = min(va_block->end, (NvU64)vma->vm_end - 1); // Also, we need to limit the prefetch region to the policy range. - if (policy == &uvm_va_policy_default) { + if (uvm_va_policy_is_default(policy)) { NV_STATUS status = uvm_range_tree_find_hole_in(&va_block->hmm.va_policy_tree, address, &start, @@ -936,7 +1440,7 @@ uvm_va_block_region_t uvm_hmm_get_prefetch_region(uvm_va_block_t *va_block, UVM_ASSERT(status == NV_OK); } else { - uvm_va_policy_node_t *node = uvm_va_policy_node_from_policy(policy); + const uvm_va_policy_node_t *node = uvm_va_policy_node_from_policy(policy); start = max(start, node->node.start); end = min(end, node->node.end); @@ -963,6 +1467,2139 @@ uvm_prot_t uvm_hmm_compute_logical_prot(uvm_va_block_t *va_block, return UVM_PROT_READ_WRITE_ATOMIC; } +static NV_STATUS hmm_va_block_cpu_page_populate(uvm_va_block_t *va_block, + uvm_page_index_t page_index, + struct page *page) +{ + uvm_cpu_chunk_t *chunk; + NV_STATUS status; + + UVM_ASSERT(uvm_va_block_is_hmm(va_block)); + UVM_ASSERT(!uvm_page_mask_test(&va_block->cpu.allocated, page_index)); + + if (page == ZERO_PAGE(uvm_va_block_cpu_page_address(va_block, page_index))) + return NV_ERR_INVALID_ADDRESS; + + status = uvm_cpu_chunk_alloc_hmm(page, &chunk); + if (status != NV_OK) + return status; + + status = uvm_cpu_chunk_insert_in_block(va_block, chunk, page_index); + if (status != NV_OK) { + uvm_cpu_chunk_free(chunk); + return status; + } + + status = uvm_va_block_map_cpu_chunk_on_gpus(va_block, page_index); + if (status != NV_OK) { + uvm_cpu_chunk_remove_from_block(va_block, page_index); + uvm_cpu_chunk_free(chunk); + } + + return status; +} + +static void hmm_va_block_cpu_page_unpopulate(uvm_va_block_t *va_block, + uvm_page_index_t page_index) +{ + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(va_block, page_index); + + UVM_ASSERT(uvm_va_block_is_hmm(va_block)); + + if (!chunk) + return; + + UVM_ASSERT(uvm_cpu_chunk_is_hmm(chunk)); + UVM_ASSERT(!uvm_processor_mask_test(&va_block->resident, UVM_ID_CPU) || + !uvm_page_mask_test(&va_block->cpu.resident, page_index)); + + uvm_cpu_chunk_remove_from_block(va_block, page_index); + uvm_va_block_unmap_cpu_chunk_on_gpus(va_block, chunk, page_index); + uvm_cpu_chunk_free(chunk); +} + +static bool hmm_va_block_cpu_page_is_same(uvm_va_block_t *va_block, + uvm_page_index_t page_index, + struct page *page) +{ + struct page *old_page = uvm_cpu_chunk_get_cpu_page(va_block, page_index); + + UVM_ASSERT(uvm_cpu_chunk_is_hmm(uvm_cpu_chunk_get_chunk_for_page(va_block, page_index))); + return old_page == page; +} + +// uvm_va_block_service_copy() and uvm_va_block_service_finish() expect the +// service_context masks to match what is being processed. Since a page +// that was expected to be processed isn't migrating, we have to clear the +// masks to make service_context consistent with what is actually being +// handled. +static NV_STATUS clear_service_context_masks(uvm_service_block_context_t *service_context, + uvm_processor_id_t new_residency, + uvm_page_index_t page_index) +{ + uvm_page_mask_clear(&service_context->per_processor_masks[uvm_id_value(new_residency)].new_residency, + page_index); + + if (uvm_page_mask_empty(&service_context->per_processor_masks[uvm_id_value(new_residency)].new_residency)) + uvm_processor_mask_clear(&service_context->resident_processors, new_residency); + + if (UVM_ID_IS_VALID(service_context->prefetch_hint.residency)) + uvm_page_mask_clear(&service_context->prefetch_hint.prefetch_pages_mask, page_index); + + if (service_context->thrashing_pin_count > 0 && + uvm_page_mask_test_and_clear(&service_context->thrashing_pin_mask, page_index)) { + service_context->thrashing_pin_count--; + } + + if (service_context->read_duplicate_count > 0 && + uvm_page_mask_test_and_clear(&service_context->read_duplicate_mask, page_index)) { + service_context->read_duplicate_count--; + } + + if (service_context->access_type[page_index] != UVM_FAULT_ACCESS_TYPE_PREFETCH) + return NV_WARN_MORE_PROCESSING_REQUIRED; + + return NV_OK; +} + +static void cpu_mapping_set(uvm_va_block_t *va_block, + bool is_write, + uvm_page_index_t page_index) +{ + uvm_processor_mask_set(&va_block->mapped, UVM_ID_CPU); + uvm_page_mask_set(&va_block->maybe_mapped_pages, page_index); + uvm_page_mask_set(&va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_READ], page_index); + if (is_write) + uvm_page_mask_set(&va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_WRITE], page_index); + else + uvm_page_mask_clear(&va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_WRITE], page_index); +} + +static void cpu_mapping_clear(uvm_va_block_t *va_block, uvm_page_index_t page_index) +{ + uvm_page_mask_clear(&va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_WRITE], page_index); + uvm_page_mask_clear(&va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_READ], page_index); + if (uvm_page_mask_empty(&va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_READ])) + uvm_processor_mask_clear(&va_block->mapped, UVM_ID_CPU); +} + +static void gpu_chunk_remove(uvm_va_block_t *va_block, + uvm_page_index_t page_index, + struct page *page) +{ + uvm_va_block_gpu_state_t *gpu_state; + uvm_gpu_chunk_t *gpu_chunk; + uvm_gpu_id_t id; + + id = uvm_pmm_devmem_page_to_gpu_id(page); + gpu_state = uvm_va_block_gpu_state_get(va_block, id); + UVM_ASSERT(gpu_state); + + gpu_chunk = gpu_state->chunks[page_index]; + UVM_ASSERT(gpu_chunk); + + // TODO: Bug 3898467: unmap indirect peers when freeing GPU chunks + + uvm_mmu_chunk_unmap(gpu_chunk, NULL); + gpu_state->chunks[page_index] = NULL; +} + +static NV_STATUS gpu_chunk_add(uvm_va_block_t *va_block, + uvm_page_index_t page_index, + struct page *page) +{ + uvm_va_block_gpu_state_t *gpu_state; + uvm_gpu_chunk_t *gpu_chunk; + uvm_gpu_id_t id; + NV_STATUS status; + + id = uvm_pmm_devmem_page_to_gpu_id(page); + gpu_state = uvm_va_block_gpu_state_get(va_block, id); + UVM_ASSERT(gpu_state); + + // Note that a mremap() might be to a CPU virtual address that is nolonger + // aligned with a larger GPU chunk size. We would need to allocate a new + // aligned GPU chunk and copy from old to new. + // TODO: Bug 3368756: add support for large GPU pages. + gpu_chunk = uvm_pmm_devmem_page_to_chunk(page); + UVM_ASSERT(gpu_chunk->state == UVM_PMM_GPU_CHUNK_STATE_ALLOCATED); + UVM_ASSERT(gpu_chunk->is_referenced); + UVM_ASSERT(page->zone_device_data == va_block->hmm.va_space); + + if (gpu_state->chunks[page_index] == gpu_chunk) + return NV_OK; + + UVM_ASSERT(!gpu_state->chunks[page_index]); + + // In some configurations such as SR-IOV heavy, the chunk cannot be + // referenced using its physical address. Create a virtual mapping. + status = uvm_mmu_chunk_map(gpu_chunk); + if (status != NV_OK) + return status; + + // TODO: Bug 3898467: map indirect peers. + + uvm_processor_mask_set(&va_block->resident, id); + uvm_page_mask_set(&gpu_state->resident, page_index); + + // It is safe to modify the page index field without holding any PMM locks + // because the chunk is allocated, which means that none of the other + // fields in the bitmap can change. + gpu_chunk->va_block = va_block; + gpu_chunk->va_block_page_index = page_index; + + gpu_state->chunks[page_index] = gpu_chunk; + + return NV_OK; +} + +static void clean_up(uvm_va_block_t *va_block, + const unsigned long *src_pfns, + uvm_va_block_region_t region, + uvm_page_mask_t *page_mask, + uvm_page_mask_t *same_devmem_page_mask) +{ + uvm_page_index_t page_index; + + va_block->hmm.changed++; + + for_each_va_block_page_in_region_mask(page_index, page_mask, region) { + struct page *src_page; + + if (uvm_page_mask_test(same_devmem_page_mask, page_index)) + continue; + + UVM_ASSERT(src_pfns[page_index] & MIGRATE_PFN_MIGRATE); + + // A zero source page (pte_none) needs no clean up. + src_page = migrate_pfn_to_page(src_pfns[page_index]); + if (!src_page) + continue; + + if (is_device_private_page(src_page)) { + gpu_chunk_remove(va_block, page_index, src_page); + } + else { + // If the source page is a system memory page, + // migrate_vma_finalize() will release the reference so we should + // clear our pointer to it. + // TODO: Bug 3660922: Need to handle read duplication at some point. + hmm_va_block_cpu_page_unpopulate(va_block, page_index); + } + } +} + +// Update va_block state to reflect that the page isn't migrating. +static void clean_up_non_migrating_page(uvm_va_block_t *va_block, + const unsigned long *src_pfns, + unsigned long *dst_pfns, + uvm_page_index_t page_index) +{ + struct page *src_page = migrate_pfn_to_page(src_pfns[page_index]); + struct page *dst_page = migrate_pfn_to_page(dst_pfns[page_index]); + + // If the source page is a normal page that is not migrating, then + // migrate_vma_finalize() will restore the CPU page table with the page PTE. + // Note that the va_block lock has to be held across the migrate_vma_setup, + // migrate_vma_finalize for this to be true so invalidate callbacks don't + // clear the residency and mapping state. + // TODO: Bug 3949334: migrate_vma_setup() is called without the va_block + // lock. + if (src_page && !is_device_private_page(src_page)) + cpu_mapping_set(va_block, src_pfns[page_index] & MIGRATE_PFN_WRITE, page_index); + + if (!dst_page) + return; + + // migrate_vma_finalize() will release the dst_page reference so don't keep + // a pointer to it. + if (is_device_private_page(dst_page)) { + gpu_chunk_remove(va_block, page_index, dst_page); + } + else { + UVM_ASSERT(uvm_cpu_chunk_is_hmm(uvm_cpu_chunk_get_chunk_for_page(va_block, page_index))); + UVM_ASSERT(page_ref_count(dst_page) == 1); + + hmm_va_block_cpu_page_unpopulate(va_block, page_index); + } + + unlock_page(dst_page); + put_page(dst_page); + dst_pfns[page_index] = 0; +} + +static void clean_up_non_migrating_pages(uvm_va_block_t *va_block, + const unsigned long *src_pfns, + unsigned long *dst_pfns, + uvm_va_block_region_t region, + uvm_page_mask_t *page_mask) +{ + uvm_page_index_t page_index; + + for_each_va_block_page_in_region_mask(page_index, page_mask, region) { + clean_up_non_migrating_page(va_block, src_pfns, dst_pfns, page_index); + } +} + +// CPU page fault handling. + +// Fill in the dst_pfns[page_index] entry given that there is an allocated +// CPU page. +static void lock_block_cpu_page(uvm_va_block_t *va_block, + uvm_page_index_t page_index, + struct page *src_page, + unsigned long *dst_pfns, + uvm_page_mask_t *same_devmem_page_mask) +{ + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(va_block, page_index); + uvm_va_block_region_t chunk_region; + struct page *dst_page; + + UVM_ASSERT(chunk); + UVM_ASSERT(chunk->page); + + chunk_region = uvm_va_block_chunk_region(va_block, uvm_cpu_chunk_get_size(chunk), page_index); + + dst_page = chunk->page + (page_index - chunk_region.first); + + UVM_ASSERT(dst_page != ZERO_PAGE(uvm_va_block_cpu_page_address(va_block, page_index))); + UVM_ASSERT(!is_device_private_page(dst_page)); + + // The source page is usually a device private page but it could be a GPU + // remote mapped system memory page. It could also be a driver allocated + // page for GPU-to-GPU staged copies (i.e., not a resident copy and owned + // by the driver). + if (is_device_private_page(src_page)) { + // Since the page isn't mirrored, it was allocated by alloc_pages() + // and UVM owns the reference. We leave the reference count unchanged + // and mark the page pointer as mirrored since UVM is transferring + // ownership to Linux and we don't want UVM to double free the page in + // hmm_va_block_cpu_page_unpopulate() or block_kill(). If the page + // does not migrate, it will be freed though. + UVM_ASSERT(!uvm_processor_mask_test(&va_block->resident, UVM_ID_CPU) || + !uvm_page_mask_test(&va_block->cpu.resident, page_index)); + UVM_ASSERT(chunk->type == UVM_CPU_CHUNK_TYPE_PHYSICAL); + UVM_ASSERT(page_ref_count(dst_page) == 1); + uvm_cpu_chunk_make_hmm(chunk); + } + else { + UVM_ASSERT(same_devmem_page_mask); + UVM_ASSERT(src_page == dst_page); + uvm_page_mask_set(same_devmem_page_mask, page_index); + return; + } + + lock_page(dst_page); + dst_pfns[page_index] = migrate_pfn(page_to_pfn(dst_page)); +} + +static void hmm_mark_gpu_chunk_referenced(uvm_va_block_t *va_block, + uvm_gpu_t *gpu, + uvm_gpu_chunk_t *gpu_chunk) +{ + // Tell PMM to expect a callback from Linux to free the page since the + // device private struct page reference count will determine when the + // GPU chunk is free. + UVM_ASSERT(gpu_chunk->state == UVM_PMM_GPU_CHUNK_STATE_TEMP_PINNED); + list_del_init(&gpu_chunk->list); + uvm_pmm_gpu_unpin_referenced(&gpu->pmm, gpu_chunk, va_block); +} + +static void fill_dst_pfn(uvm_va_block_t *va_block, + uvm_gpu_t *gpu, + const unsigned long *src_pfns, + unsigned long *dst_pfns, + uvm_page_index_t page_index, + uvm_page_mask_t *same_devmem_page_mask) +{ + unsigned long src_pfn = src_pfns[page_index]; + uvm_gpu_chunk_t *gpu_chunk; + unsigned long pfn; + struct page *dpage; + + gpu_chunk = uvm_va_block_lookup_gpu_chunk(va_block, gpu, uvm_va_block_cpu_page_address(va_block, page_index)); + UVM_ASSERT(gpu_chunk); + UVM_ASSERT(gpu_chunk->log2_size == PAGE_SHIFT); + pfn = uvm_pmm_gpu_devmem_get_pfn(&gpu->pmm, gpu_chunk); + + // If the same GPU page is both source and destination, migrate_vma_pages() + // will see the wrong "expected" reference count and not migrate it, so we + // mark it as not migrating but we keep track of this so we don't confuse + // it with a page that migrate_vma_pages() actually does not migrate. + if ((src_pfn & MIGRATE_PFN_VALID) && (src_pfn >> MIGRATE_PFN_SHIFT) == pfn) { + uvm_page_mask_set(same_devmem_page_mask, page_index); + return; + } + + dpage = pfn_to_page(pfn); + UVM_ASSERT(is_device_private_page(dpage)); + UVM_ASSERT(dpage->pgmap->owner == &g_uvm_global); + + hmm_mark_gpu_chunk_referenced(va_block, gpu, gpu_chunk); + UVM_ASSERT(!page_count(dpage)); + zone_device_page_init(dpage); + dpage->zone_device_data = va_block->hmm.va_space; + + dst_pfns[page_index] = migrate_pfn(pfn); +} + +static void fill_dst_pfns(uvm_va_block_t *va_block, + const unsigned long *src_pfns, + unsigned long *dst_pfns, + uvm_va_block_region_t region, + uvm_page_mask_t *page_mask, + uvm_page_mask_t *same_devmem_page_mask, + uvm_processor_id_t dest_id) +{ + uvm_gpu_t *gpu = uvm_va_space_get_gpu(va_block->hmm.va_space, dest_id); + uvm_page_index_t page_index; + + uvm_page_mask_zero(same_devmem_page_mask); + + for_each_va_block_page_in_region_mask(page_index, page_mask, region) { + if (!(src_pfns[page_index] & MIGRATE_PFN_MIGRATE)) + continue; + + fill_dst_pfn(va_block, + gpu, + src_pfns, + dst_pfns, + page_index, + same_devmem_page_mask); + } +} + +static NV_STATUS alloc_and_copy_to_cpu(uvm_va_block_t *va_block, + struct vm_area_struct *vma, + const unsigned long *src_pfns, + unsigned long *dst_pfns, + uvm_va_block_region_t region, + uvm_page_mask_t *page_mask, + uvm_page_mask_t *same_devmem_page_mask, + uvm_processor_id_t processor_id, + uvm_service_block_context_t *service_context) +{ + uvm_page_index_t page_index; + NV_STATUS status = NV_OK; + + // Normally the source page will be a device private page that is being + // migrated to system memory. However, when it is a GPU fault, the source + // page can be a system memory page that the GPU will remote map. If the + // GPU needs atomic access, the destination PTE be a device exclusive PTE + // which migrate_vma_setup() won't select. We check for that and set + // same_devmem_page_mask to record that it should be processed. Also, + // if the source and destination page are the same, the page reference + // count won't be the "expected" count and migrate_vma_pages() won't migrate + // it. This mask tracks that too. + if (same_devmem_page_mask) + uvm_page_mask_zero(same_devmem_page_mask); + + for_each_va_block_page_in_region_mask(page_index, page_mask, region) { + struct page *src_page; + struct page *dst_page; + gfp_t gfp; + + if (!(src_pfns[page_index] & MIGRATE_PFN_MIGRATE)) { + // Device exclusive PTEs are not selected but we still want to + // process the page so record it as such. + if (service_context && !UVM_ID_IS_CPU(processor_id) && + service_context->access_type[page_index] == UVM_FAULT_ACCESS_TYPE_ATOMIC_STRONG) { + uvm_page_mask_set(same_devmem_page_mask, page_index); + continue; + } + goto clr_mask; + } + + // This is the page that will be copied to system memory. + src_page = migrate_pfn_to_page(src_pfns[page_index]); + + if (src_page) { + // The call to migrate_vma_setup() will have inserted a migration + // PTE so the CPU has no access. + cpu_mapping_clear(va_block, page_index); + + if (uvm_page_mask_test(&va_block->cpu.allocated, page_index)) { + lock_block_cpu_page(va_block, page_index, src_page, dst_pfns, same_devmem_page_mask); + continue; + } + } + + UVM_ASSERT(!uvm_processor_mask_test(&va_block->resident, UVM_ID_CPU) || + !uvm_page_mask_test(&va_block->cpu.resident, page_index)); + + // Allocate a user system memory page for the destination. + // This is the typical case since Linux will free the source page when + // migrating to device private memory. + // If there is no source page, it means the page is pte_none() or the + // zero page. This case "shouldn't happen" because we asked + // migrate_vma_setup() only for device private pages but + // migrate_vma_collect_hole() doesn't check the + // MIGRATE_VMA_SELECT_SYSTEM flag. + gfp = GFP_HIGHUSER_MOVABLE; + if (!src_page) + gfp |= __GFP_ZERO; + + dst_page = alloc_page_vma(gfp, + vma, + va_block->start + (page_index << PAGE_SHIFT)); + if (!dst_page) { + // Ignore errors if the page is only for prefetching. + if (service_context && + service_context->access_type[page_index] == UVM_FAULT_ACCESS_TYPE_PREFETCH) + goto clr_mask; + UVM_ERR_PRINT("cannot allocate page %u (addr 0x%llx)\n", + page_index, va_block->start + (page_index << PAGE_SHIFT)); + status = NV_ERR_NO_MEMORY; + break; + } + + status = hmm_va_block_cpu_page_populate(va_block, page_index, dst_page); + if (status != NV_OK) { + __free_page(dst_page); + // Ignore errors if the page is only for prefetching. + if (service_context && + service_context->access_type[page_index] == UVM_FAULT_ACCESS_TYPE_PREFETCH) + goto clr_mask; + break; + } + + // Note that we don't call get_page(dst_page) since alloc_page_vma() + // returns with a page reference count of one and we are passing + // ownership to Linux. Also, uvm_va_block_cpu_page_populate() recorded + // the page as "mirrored" so that migrate_vma_finalize() and + // hmm_va_block_cpu_page_unpopulate() don't double free the page. + lock_page(dst_page); + dst_pfns[page_index] = migrate_pfn(page_to_pfn(dst_page)); + continue; + + clr_mask: + // TODO: Bug 3900774: clean up murky mess of mask clearing. + uvm_page_mask_clear(page_mask, page_index); + if (service_context) { + status = clear_service_context_masks(service_context, UVM_ID_CPU, page_index); + if (status != NV_OK) + break; + } + + if (uvm_page_mask_empty(page_mask)) + return NV_WARN_NOTHING_TO_DO; + } + + if (status != NV_OK) + clean_up_non_migrating_pages(va_block, src_pfns, dst_pfns, region, page_mask); + + return status; +} + +static NV_STATUS uvm_hmm_devmem_fault_alloc_and_copy(uvm_hmm_devmem_fault_context_t *devmem_fault_context) +{ + uvm_processor_id_t processor_id; + uvm_service_block_context_t *service_context; + uvm_va_block_retry_t *va_block_retry; + const unsigned long *src_pfns; + unsigned long *dst_pfns; + uvm_page_mask_t *page_mask; + uvm_page_mask_t *same_devmem_page_mask = &devmem_fault_context->same_devmem_page_mask; + uvm_va_block_t *va_block; + NV_STATUS status = NV_OK; + + processor_id = devmem_fault_context->processor_id; + service_context = devmem_fault_context->service_context; + va_block_retry = devmem_fault_context->va_block_retry; + va_block = devmem_fault_context->va_block; + src_pfns = service_context->block_context.hmm.src_pfns; + dst_pfns = service_context->block_context.hmm.dst_pfns; + + // Build the migration page mask. + // Note that thrashing pinned pages and prefetch pages are already + // accounted for in service_context->per_processor_masks. + page_mask = &devmem_fault_context->page_mask; + uvm_page_mask_copy(page_mask, &service_context->per_processor_masks[UVM_ID_CPU_VALUE].new_residency); + + status = alloc_and_copy_to_cpu(va_block, + service_context->block_context.hmm.vma, + src_pfns, + dst_pfns, + service_context->region, + page_mask, + same_devmem_page_mask, + processor_id, + service_context); + if (status != NV_OK) + return status; + + // Do the copy but don't update the residency or mapping for the new + // location yet. + return uvm_va_block_service_copy(processor_id, UVM_ID_CPU, va_block, va_block_retry, service_context); +} + +static NV_STATUS uvm_hmm_devmem_fault_finalize_and_map(uvm_hmm_devmem_fault_context_t *devmem_fault_context) +{ + uvm_processor_id_t processor_id; + uvm_service_block_context_t *service_context; + uvm_perf_prefetch_hint_t *prefetch_hint; + uvm_va_block_retry_t *va_block_retry; + const unsigned long *src_pfns; + unsigned long *dst_pfns; + uvm_page_mask_t *page_mask; + uvm_va_block_t *va_block; + uvm_va_block_region_t region; + uvm_page_index_t page_index; + NV_STATUS status, tracker_status; + + processor_id = devmem_fault_context->processor_id; + service_context = devmem_fault_context->service_context; + prefetch_hint = &service_context->prefetch_hint; + va_block = devmem_fault_context->va_block; + va_block_retry = devmem_fault_context->va_block_retry; + src_pfns = service_context->block_context.hmm.src_pfns; + dst_pfns = service_context->block_context.hmm.dst_pfns; + region = service_context->region; + + page_mask = &devmem_fault_context->page_mask; + + // There are a number of reasons why HMM will mark a page as not migrating + // even if we set a valid entry in dst_pfns[]. Mark these pages accordingly. + for_each_va_block_page_in_region_mask(page_index, page_mask, region) { + if (src_pfns[page_index] & MIGRATE_PFN_MIGRATE) + continue; + + // If a page isn't migrating and only the GPU page table is being + // updated, continue to process it normally. + if (uvm_page_mask_test(&devmem_fault_context->same_devmem_page_mask, page_index)) + continue; + + clean_up_non_migrating_page(va_block, src_pfns, dst_pfns, page_index); + + // TODO: Bug 3900774: clean up murky mess of mask clearing. + uvm_page_mask_clear(page_mask, page_index); + status = clear_service_context_masks(service_context, UVM_ID_CPU, page_index); + if (status != NV_OK) + return status; + + // Return if nothing is actually migrating. + if (uvm_page_mask_empty(page_mask)) + return NV_WARN_MORE_PROCESSING_REQUIRED; + } + + status = uvm_va_block_service_finish(processor_id, va_block, service_context); + + // Wait for the GPU CE to finish. + // After this callback returns, the kernel will unmap all migrated + // pages, so the copy must be finished by then. + tracker_status = uvm_tracker_wait(&va_block->tracker); + if (status == NV_OK) + status = tracker_status; + + clean_up(va_block, + src_pfns, + region, + page_mask, + &devmem_fault_context->same_devmem_page_mask); + + return status; +} + +static NV_STATUS populate_region(uvm_va_block_t *va_block, + unsigned long *pfns, + uvm_va_block_region_t region) +{ + uvm_page_index_t page_index; + NV_STATUS status; + + // Make sure GPU state is allocated or else the GPU DMA mappings to + // system memory won't be saved. + status = uvm_va_block_gpu_state_alloc(va_block); + if (status != NV_OK) + return status; + + for_each_va_block_page_in_region(page_index, region) { + struct page *page; + + // This case should only happen when querying CPU residency and we ask + // for something not covered by a VMA. Otherwise, hmm_range_fault() + // returns -EFAULT instead of setting the HMM_PFN_ERROR bit. + if (pfns[page_index] & HMM_PFN_ERROR) + return NV_ERR_INVALID_ADDRESS; + + if (pfns[page_index] & HMM_PFN_VALID) { + page = hmm_pfn_to_page(pfns[page_index]); + } + else { + // The page can't be evicted since it has to be migrated to the GPU + // first which would leave a device private page entry so this has + // to be a pte_none(), swapped out, or similar entry. + // The page would have been allocated if populate_region() is being + // called from uvm_hmm_va_block_service_locked() so this must be + // for uvm_hmm_va_block_update_residency_info(). Just leave the + // residency/populated information unchanged since + // uvm_hmm_invalidate() should handle that if the underlying page + // is invalidated. + // Also note there can be an allocated page due to GPU-to-GPU + // migration between non-peer or indirect peer GPUs. + continue; + } + + if (is_device_private_page(page)) { + // Linux can call hmm_invalidate() and we have to clear the GPU + // chunk pointer in uvm_va_block_gpu_state_t::chunks[] but it might + // not release the device private struct page reference. Since + // hmm_range_fault() did find a device private PTE, we can + // re-establish the GPU chunk pointer. + status = gpu_chunk_add(va_block, page_index, page); + if (status != NV_OK) + return status; + continue; + } + + // If a CPU chunk is already allocated, check to see it matches what + // hmm_range_fault() found. + if (uvm_page_mask_test(&va_block->cpu.allocated, page_index)) { + UVM_ASSERT(hmm_va_block_cpu_page_is_same(va_block, page_index, page)); + } + else { + status = hmm_va_block_cpu_page_populate(va_block, page_index, page); + if (status != NV_OK) + return status; + } + + // Since we have a stable snapshot of the CPU pages, we can + // update the residency and protection information. + uvm_processor_mask_set(&va_block->resident, UVM_ID_CPU); + uvm_page_mask_set(&va_block->cpu.resident, page_index); + + cpu_mapping_set(va_block, pfns[page_index] & HMM_PFN_WRITE, page_index); + } + + return NV_OK; +} + +// Make the service_context->region be resident on the CPU by calling +// hmm_range_fault() to fault in CPU pages. +static NV_STATUS hmm_va_block_make_resident_cpu(uvm_va_block_t *va_block, + uvm_service_block_context_t *service_context) +{ + uvm_thread_context_t *uvm_context = uvm_thread_context(); + uvm_page_index_t page_index; + uvm_va_block_region_t region = service_context->region; + unsigned long *hmm_pfns = service_context->block_context.hmm.src_pfns; + unsigned long seqnum; + int ret; + struct hmm_range range = { + .notifier = &va_block->hmm.notifier, + .start = uvm_va_block_region_start(va_block, region), + .end = uvm_va_block_region_end(va_block, region) + 1, + .hmm_pfns = hmm_pfns + region.first, + .pfn_flags_mask = HMM_PFN_REQ_FAULT | HMM_PFN_REQ_WRITE, + .dev_private_owner = &g_uvm_global, + }; + + for_each_va_block_page_in_region(page_index, region) { + if (service_context->access_type[page_index] >= UVM_FAULT_ACCESS_TYPE_WRITE || + (service_context->block_context.hmm.vma->vm_flags & VM_WRITE)) + hmm_pfns[page_index] = HMM_PFN_REQ_FAULT | HMM_PFN_REQ_WRITE; + else + hmm_pfns[page_index] = HMM_PFN_REQ_FAULT; + } + + // Save the current sequence number so we can detect residency and mapping + // changes while not holding the va_block lock. + seqnum = va_block->hmm.changed; + + // Mirror the VA block to the HMM address range. + // Note that we request HMM to handle page faults, which means that it will + // populate and map potentially not-yet-existing pages to the VMA. + // Also note that mmu_interval_read_begin() calls wait_event() for any + // parallel invalidation callbacks to finish so we can't hold locks that + // the invalidation callback acquires. + uvm_mutex_unlock(&va_block->lock); + + // Prevent MMU invalidation callbacks in this thread from invalidating + // the hmm_range_fault() results. + uvm_context->ignore_hmm_invalidate_va_block = va_block; + + range.notifier_seq = mmu_interval_read_begin(range.notifier); + ret = hmm_range_fault(&range); + + uvm_context->ignore_hmm_invalidate_va_block = NULL; + + uvm_mutex_lock(&va_block->lock); + + if (ret) + return (ret == -EBUSY) ? NV_WARN_MORE_PROCESSING_REQUIRED : errno_to_nv_status(ret); + + if (mmu_interval_read_retry(range.notifier, range.notifier_seq)) + return NV_WARN_MORE_PROCESSING_REQUIRED; + + // We unlocked and relocked the block lock so the va_block state might have + // changed. We know there were no invalidation callbacks due to the above + // check. The mmap lock and va_space lock are stil being held so pages + // could be evicted or migrated but not destroyed. The VMAs will be + // unchanged since we hold the mmap lock. The policies will still be + // unchanged since no invalidate() callback was seen and holding the + // va_space lock prevents API policy changes. + if (seqnum != va_block->hmm.changed) + return NV_WARN_MORE_PROCESSING_REQUIRED; + + return populate_region(va_block, + service_context->block_context.hmm.src_pfns, + region); +} + +static void hmm_handle_prefetch_setup(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_va_block_region_t region, + struct migrate_vma *args) +{ + uvm_page_index_t fault_index = args->src - va_block_context->hmm.src_pfns; + unsigned long src_pfn; + int ret; + + // Save the src_pfn. The migrate_vma_setup() will see a migration PTE and + // mark the faulting address entry as not migrating. Then restore the + // original entry. + src_pfn = args->src[0]; + UVM_ASSERT(src_pfn & MIGRATE_PFN_MIGRATE); + UVM_ASSERT(!args->dst[0]); + + args->src = va_block_context->hmm.src_pfns + region.first; + args->dst = va_block_context->hmm.dst_pfns + region.first; + args->start = uvm_va_block_region_start(va_block, region); + args->end = uvm_va_block_region_end(va_block, region) + 1; + fault_index -= region.first; + + ret = migrate_vma_setup(args); + UVM_ASSERT(!ret); + + UVM_ASSERT(!args->src[fault_index]); + args->src[fault_index] = src_pfn; + UVM_ASSERT(!args->dst[fault_index]); +} + +// Release the reference count on any pages that were made device exclusive. +static void hmm_release_atomic_pages(uvm_va_block_t *va_block, + uvm_service_block_context_t *service_context) +{ + uvm_va_block_region_t region = service_context->region; + uvm_page_index_t page_index; + + for_each_va_block_page_in_region(page_index, region) { + struct page *page = service_context->block_context.hmm.pages[page_index]; + + if (!page) + continue; + + unlock_page(page); + put_page(page); + } +} + +// Wait for any atomic migrations to finish before doing further migrations. +// This function drops the va_block lock and reacquires it so callers need to +// validate any cached va_block state after this function returns. +static void hmm_wait_for_atomic(uvm_va_block_t *va_block, + uvm_va_block_region_t region) +{ + uvm_assert_mutex_locked(&va_block->lock); + + while (!uvm_page_mask_region_empty(&va_block->hmm.atomic_busy, region)) { + uvm_mutex_unlock(&va_block->lock); + + wait_event(va_block->hmm.atomic_waitq, uvm_page_mask_region_empty(&va_block->hmm.atomic_busy, region)); + + uvm_mutex_lock(&va_block->lock); + } +} + +static NV_STATUS hmm_block_atomic_fault_locked(uvm_processor_id_t processor_id, + uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_service_block_context_t *service_context) +{ + uvm_thread_context_t *uvm_context = uvm_thread_context(); + uvm_va_block_region_t region = service_context->region; + struct page **pages = service_context->block_context.hmm.pages; + unsigned long notifier_seq; + int npages; + uvm_page_index_t page_index; + uvm_make_resident_cause_t cause; + NV_STATUS status; + + hmm_wait_for_atomic(va_block, region); + + uvm_page_mask_region_fill(&va_block->hmm.atomic_busy, region); + + if (!uvm_processor_mask_test(&va_block->resident, UVM_ID_CPU) || + !uvm_page_mask_region_full(&va_block->cpu.resident, region)) { + // There is an atomic GPU fault. We need to make sure no pages are + // GPU resident so that make_device_exclusive_range() doesn't call + // migrate_to_ram() and cause a va_space lock recursion problem. + if (service_context->operation == UVM_SERVICE_OPERATION_REPLAYABLE_FAULTS) + cause = UVM_MAKE_RESIDENT_CAUSE_REPLAYABLE_FAULT; + else if (service_context->operation == UVM_SERVICE_OPERATION_NON_REPLAYABLE_FAULTS) + cause = UVM_MAKE_RESIDENT_CAUSE_NON_REPLAYABLE_FAULT; + else + cause = UVM_MAKE_RESIDENT_CAUSE_ACCESS_COUNTER; + + status = hmm_va_block_migrate_locked(va_block, + va_block_retry, + &service_context->block_context, + UVM_ID_CPU, + region, + cause); + if (status != NV_OK) + goto clear; + + // make_device_exclusive_range() will try to call migrate_to_ram() + // and deadlock with ourself if the data isn't CPU resident. + if (!uvm_processor_mask_test(&va_block->resident, UVM_ID_CPU) || + !uvm_page_mask_region_full(&va_block->cpu.resident, region)) { + status = NV_WARN_MORE_PROCESSING_REQUIRED; + goto clear; + } + } + + uvm_mutex_unlock(&va_block->lock); + + // Prevent MMU invalidation callbacks from deadlocking in this thread. + uvm_context->ignore_hmm_invalidate_va_block = va_block; + + notifier_seq = mmu_interval_read_begin(&va_block->hmm.notifier); + + npages = make_device_exclusive_range(service_context->block_context.mm, + uvm_va_block_cpu_page_address(va_block, region.first), + uvm_va_block_cpu_page_address(va_block, region.outer - 1) + PAGE_SIZE, + pages + region.first, + &g_uvm_global); + + uvm_context->ignore_hmm_invalidate_va_block = NULL; + + uvm_mutex_lock(&va_block->lock); + + if (npages < 0) { + status = (npages == -EBUSY) ? NV_WARN_MORE_PROCESSING_REQUIRED : errno_to_nv_status(npages); + goto clear; + } + + while ((size_t)npages < uvm_va_block_region_num_pages(region)) + pages[region.first + npages++] = NULL; + + if (mmu_interval_read_retry(&va_block->hmm.notifier, notifier_seq)) { + status = NV_WARN_MORE_PROCESSING_REQUIRED; + goto release; + } + + status = NV_OK; + + for_each_va_block_page_in_region(page_index, region) { + struct page *page = pages[page_index]; + + if (!page) { + // Record that one of the pages isn't exclusive but keep converting + // the others. + status = NV_WARN_MORE_PROCESSING_REQUIRED; + continue; + } + + // If a CPU chunk is already allocated, check to see it matches what + // make_device_exclusive_range() found. + if (uvm_page_mask_test(&va_block->cpu.allocated, page_index)) { + UVM_ASSERT(hmm_va_block_cpu_page_is_same(va_block, page_index, page)); + UVM_ASSERT(uvm_processor_mask_test(&va_block->resident, UVM_ID_CPU)); + UVM_ASSERT(uvm_page_mask_test(&va_block->cpu.resident, page_index)); + } + else { + NV_STATUS s = hmm_va_block_cpu_page_populate(va_block, page_index, page); + + if (s == NV_OK) { + uvm_processor_mask_set(&va_block->resident, UVM_ID_CPU); + uvm_page_mask_set(&va_block->cpu.resident, page_index); + } + } + + cpu_mapping_clear(va_block, page_index); + } + + if (status != NV_OK) + goto release; + + status = uvm_va_block_service_copy(processor_id, UVM_ID_CPU, va_block, va_block_retry, service_context); + if (status != NV_OK) + goto release; + + status = uvm_va_block_service_finish(processor_id, va_block, service_context); + +release: + hmm_release_atomic_pages(va_block, service_context); + +clear: + uvm_page_mask_region_clear(&va_block->hmm.atomic_busy, region); + wake_up_all(&va_block->hmm.atomic_waitq); + + return status; +} + +static bool is_atomic_fault(NvU8 *access_type, uvm_va_block_region_t region) +{ + uvm_page_index_t page_index; + + for_each_va_block_page_in_region(page_index, region) { + if (access_type[page_index] == UVM_FAULT_ACCESS_TYPE_ATOMIC_STRONG) + return true; + } + + return false; +} + +static NV_STATUS hmm_block_cpu_fault_locked(uvm_processor_id_t processor_id, + uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_service_block_context_t *service_context) +{ + uvm_thread_context_t *uvm_context = uvm_thread_context(); + uvm_va_block_region_t region = service_context->region; + struct migrate_vma *args = &service_context->block_context.hmm.migrate_vma_args; + NV_STATUS status; + int ret; + uvm_hmm_devmem_fault_context_t fault_context = { + .processor_id = processor_id, + .va_block = va_block, + .va_block_retry = va_block_retry, + .service_context = service_context, + }; + + // uvm_va_block_select_residency() should select the CPU for the + // new_residency. This might not be true if GPU memory is accessible + // from the CPU and the preferred location is the GPU, but then HMM + // wouldn't be needed. + UVM_ASSERT(uvm_processor_mask_get_count(&service_context->resident_processors) == 1); + UVM_ASSERT(UVM_ID_IS_CPU(uvm_processor_mask_find_first_id(&service_context->resident_processors))); + + if (!UVM_ID_IS_CPU(processor_id)) { + if (is_atomic_fault(service_context->access_type, region)) { + return hmm_block_atomic_fault_locked(processor_id, + va_block, + va_block_retry, + service_context); + } + + hmm_wait_for_atomic(va_block, region); + + status = hmm_va_block_make_resident_cpu(va_block, service_context); + if (status != NV_OK) + return status; + } + + // Prevent MMU invalidation callbacks from deadlocking in this thread. + uvm_context->ignore_hmm_invalidate_va_block = va_block; + + if (UVM_ID_IS_CPU(processor_id)) { + // args were set by uvm_hmm_va_block_cpu_find() but the prefetch + // calculation might have expanded the region. + if (uvm_va_block_region_num_pages(region) > 1) { + hmm_handle_prefetch_setup(va_block, + &service_context->block_context, + region, + args); + } + } + else { + args->vma = service_context->block_context.hmm.vma; + args->src = service_context->block_context.hmm.src_pfns + region.first; + args->dst = service_context->block_context.hmm.dst_pfns + region.first; + args->start = uvm_va_block_region_start(va_block, region); + args->end = uvm_va_block_region_end(va_block, region) + 1; + args->flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE | MIGRATE_VMA_SELECT_SYSTEM; + args->pgmap_owner = &g_uvm_global; + args->fault_page = NULL; + + ret = migrate_vma_setup(args); + UVM_ASSERT(!ret); + } + + // The overall process here is to migrate pages from the GPU to the CPU + // and possibly remote map the GPU to sysmem if accessed_by is set. + // This is safe because we hold the va_block lock across the calls to + // uvm_hmm_devmem_fault_alloc_and_copy(), migrate_vma_pages(), + // uvm_hmm_devmem_fault_finalize_and_map(), and migrate_vma_finalize(). + // If uvm_hmm_devmem_fault_alloc_and_copy() needs to drop the va_block + // lock, a sequence number is used to tell if an invalidate() callback + // occurred while not holding the lock. If the sequence number changes, + // all the locks need to be dropped (mm, va_space, va_block) and the whole + // uvm_va_block_service_locked() called again. Otherwise, there were no + // conflicting invalidate callbacks and our snapshots of the CPU page + // tables are accurate and can be used to DMA pages and update GPU page + // tables. + status = uvm_hmm_devmem_fault_alloc_and_copy(&fault_context); + if (status == NV_OK) { + migrate_vma_pages(args); + status = uvm_hmm_devmem_fault_finalize_and_map(&fault_context); + } + + uvm_context->ignore_hmm_invalidate_va_block = NULL; + + migrate_vma_finalize(args); + + // Notify uvm_hmm_cpu_fault_finish() that migrate_vma_finalize() has been + // called. + service_context->block_context.hmm.migrate_vma_args.vma = NULL; + + if (status == NV_WARN_NOTHING_TO_DO) + status = NV_OK; + + return status; +} + +static NV_STATUS dmamap_src_sysmem_pages(uvm_va_block_t *va_block, + struct vm_area_struct *vma, + const unsigned long *src_pfns, + unsigned long *dst_pfns, + uvm_va_block_region_t region, + uvm_page_mask_t *page_mask, + uvm_processor_id_t dest_id, + uvm_service_block_context_t *service_context) +{ + uvm_page_index_t page_index; + NV_STATUS status = NV_OK; + + for_each_va_block_page_in_region_mask(page_index, page_mask, region) { + struct page *src_page; + + if (!(src_pfns[page_index] & MIGRATE_PFN_MIGRATE)) { + // HMM currently has some limitations on what pages can be migrated. + // For example, no file backed pages, device private pages owned by + // a different device, device exclusive or swapped out pages. + goto clr_mask; + } + + // This is the page that will be copied to the destination GPU. + src_page = migrate_pfn_to_page(src_pfns[page_index]); + if (src_page) { + if (is_device_private_page(src_page)) { + status = gpu_chunk_add(va_block, page_index, src_page); + if (status != NV_OK) + break; + continue; + } + + // If the page is already allocated, it is most likely a mirrored + // page. Check to be sure it matches what we have recorded. The + // page shouldn't be a staging page from a GPU to GPU migration + // or a remote mapped atomic sysmem page because migrate_vma_setup() + // found a normal page and non-mirrored pages are only known + // privately to the UVM driver. + if (uvm_page_mask_test(&va_block->cpu.allocated, page_index)) { + UVM_ASSERT(hmm_va_block_cpu_page_is_same(va_block, page_index, src_page)); + UVM_ASSERT(uvm_processor_mask_test(&va_block->resident, UVM_ID_CPU)); + UVM_ASSERT(uvm_page_mask_test(&va_block->cpu.resident, page_index)); + } + else { + status = hmm_va_block_cpu_page_populate(va_block, page_index, src_page); + if (status != NV_OK) + goto clr_mask; + + // Since there is a CPU resident page, there shouldn't be one + // anywhere else. TODO: Bug 3660922: Need to handle read + // duplication at some point. + UVM_ASSERT(!uvm_va_block_page_resident_processors_count(va_block, page_index)); + + // migrate_vma_setup() was able to isolate and lock the page; + // therefore, it is CPU resident and not mapped. + uvm_processor_mask_set(&va_block->resident, UVM_ID_CPU); + uvm_page_mask_set(&va_block->cpu.resident, page_index); + } + + // The call to migrate_vma_setup() will have inserted a migration + // PTE so the CPU has no access. + cpu_mapping_clear(va_block, page_index); + } + else { + // It is OK to migrate an empty anonymous page, a zero page will + // be allocated on the GPU. Just be sure to free any pages + // used for GPU to GPU copies. It can't be an evicted page because + // migrate_vma_setup() would have found a source page. + if (uvm_page_mask_test(&va_block->cpu.allocated, page_index)) { + UVM_ASSERT(!uvm_va_block_page_resident_processors_count(va_block, page_index)); + + hmm_va_block_cpu_page_unpopulate(va_block, page_index); + } + } + + continue; + + clr_mask: + // TODO: Bug 3900774: clean up murky mess of mask clearing. + uvm_page_mask_clear(page_mask, page_index); + if (service_context) { + status = clear_service_context_masks(service_context, dest_id, page_index); + if (status != NV_OK) + break; + } + + // Return if nothing is actually migrating. + // TODO: Bug 3900021: investigate thrashing improvements. + if (uvm_page_mask_empty(page_mask)) + return NV_WARN_NOTHING_TO_DO; + } + + if (status != NV_OK) + clean_up_non_migrating_pages(va_block, src_pfns, dst_pfns, region, page_mask); + + return status; +} + +static NV_STATUS uvm_hmm_gpu_fault_alloc_and_copy(struct vm_area_struct *vma, + uvm_hmm_gpu_fault_event_t *uvm_hmm_gpu_fault_event) +{ + uvm_processor_id_t processor_id; + uvm_processor_id_t new_residency; + uvm_va_block_t *va_block; + uvm_va_block_retry_t *va_block_retry; + uvm_service_block_context_t *service_context; + uvm_perf_prefetch_hint_t *prefetch_hint; + const unsigned long *src_pfns; + unsigned long *dst_pfns; + uvm_va_block_region_t region; + uvm_page_mask_t *page_mask; + NV_STATUS status; + + processor_id = uvm_hmm_gpu_fault_event->processor_id; + new_residency = uvm_hmm_gpu_fault_event->new_residency; + va_block = uvm_hmm_gpu_fault_event->va_block; + va_block_retry = uvm_hmm_gpu_fault_event->va_block_retry; + service_context = uvm_hmm_gpu_fault_event->service_context; + region = service_context->region; + prefetch_hint = &service_context->prefetch_hint; + src_pfns = service_context->block_context.hmm.src_pfns; + dst_pfns = service_context->block_context.hmm.dst_pfns; + + // Build the migration mask. + // Note that thrashing pinned pages are already accounted for in + // service_context->resident_processors. + page_mask = &uvm_hmm_gpu_fault_event->page_mask; + uvm_page_mask_copy(page_mask, + &service_context->per_processor_masks[uvm_id_value(new_residency)].new_residency); + + status = dmamap_src_sysmem_pages(va_block, + vma, + src_pfns, + dst_pfns, + region, + page_mask, + new_residency, + service_context); + if (status != NV_OK) + return status; + + // Do the alloc and copy but don't update the residency or mapping for the + // new location yet. + status = uvm_va_block_service_copy(processor_id, new_residency, va_block, va_block_retry, service_context); + if (status != NV_OK) + return status; + + // Record the destination PFNs of device private struct pages now that + // uvm_va_block_service_copy() has populated the GPU destination pages. + fill_dst_pfns(va_block, + src_pfns, + dst_pfns, + region, + page_mask, + &uvm_hmm_gpu_fault_event->same_devmem_page_mask, + new_residency); + + return status; +} + +static NV_STATUS uvm_hmm_gpu_fault_finalize_and_map(uvm_hmm_gpu_fault_event_t *uvm_hmm_gpu_fault_event) +{ + uvm_processor_id_t processor_id; + uvm_processor_id_t new_residency; + uvm_va_block_t *va_block; + uvm_va_block_retry_t *va_block_retry; + uvm_service_block_context_t *service_context; + const unsigned long *src_pfns; + unsigned long *dst_pfns; + uvm_va_block_region_t region; + uvm_page_index_t page_index; + uvm_page_mask_t *page_mask; + NV_STATUS status; + + processor_id = uvm_hmm_gpu_fault_event->processor_id; + new_residency = uvm_hmm_gpu_fault_event->new_residency; + va_block = uvm_hmm_gpu_fault_event->va_block; + va_block_retry = uvm_hmm_gpu_fault_event->va_block_retry; + service_context = uvm_hmm_gpu_fault_event->service_context; + src_pfns = service_context->block_context.hmm.src_pfns; + dst_pfns = service_context->block_context.hmm.dst_pfns; + region = service_context->region; + page_mask = &uvm_hmm_gpu_fault_event->page_mask; + + // There are a number of reasons why HMM will mark a page as not migrating + // even if we set a valid entry in dst_pfns[]. Mark these pages accordingly. + for_each_va_block_page_in_region_mask(page_index, page_mask, region) { + unsigned long src_pfn = src_pfns[page_index]; + + if (src_pfn & MIGRATE_PFN_MIGRATE) + continue; + + // If a device private page isn't migrating and only the GPU page table + // is being updated, continue to process it normally. + if (uvm_page_mask_test(&uvm_hmm_gpu_fault_event->same_devmem_page_mask, page_index)) + continue; + + clean_up_non_migrating_page(va_block, src_pfns, dst_pfns, page_index); + + // TODO: Bug 3900774: clean up murky mess of mask clearing. + uvm_page_mask_clear(page_mask, page_index); + status = clear_service_context_masks(service_context, new_residency, page_index); + if (status != NV_OK) + return status; + + // Return if nothing is actually migrating. + if (uvm_page_mask_empty(page_mask)) + return NV_WARN_NOTHING_TO_DO; + } + + // Update the va_block state and GPU mappings. + status = uvm_va_block_service_finish(processor_id, va_block, service_context); + if (status == NV_OK) { + // Wait for the GPU to finish. + // After this callback returns, the kernel will free all migrated + // system memory pages, so the copy must be finished by then. + status = uvm_tracker_wait(&va_block->tracker); + } + + clean_up(va_block, + src_pfns, + region, + page_mask, + &uvm_hmm_gpu_fault_event->same_devmem_page_mask); + + return status; +} + +NV_STATUS uvm_hmm_va_block_service_locked(uvm_processor_id_t processor_id, + uvm_processor_id_t new_residency, + uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_service_block_context_t *service_context) +{ + uvm_thread_context_t *uvm_context = uvm_thread_context(); + struct mm_struct *mm = service_context->block_context.mm; + struct vm_area_struct *vma = service_context->block_context.hmm.vma; + uvm_va_block_region_t region = service_context->region; + uvm_hmm_gpu_fault_event_t uvm_hmm_gpu_fault_event; + struct migrate_vma *args = &service_context->block_context.hmm.migrate_vma_args; + int ret; + NV_STATUS status = NV_ERR_INVALID_ADDRESS; + + if (!mm) + return status; + + uvm_assert_mmap_lock_locked(mm); + uvm_assert_mutex_locked(&va_block->lock); + UVM_ASSERT(vma); + + // If the desired destination is the CPU, try to fault in CPU pages. + if (UVM_ID_IS_CPU(new_residency)) + return hmm_block_cpu_fault_locked(processor_id, va_block, va_block_retry, service_context); + + hmm_wait_for_atomic(va_block, region); + + uvm_hmm_gpu_fault_event.processor_id = processor_id; + uvm_hmm_gpu_fault_event.new_residency = new_residency; + uvm_hmm_gpu_fault_event.va_block = va_block; + uvm_hmm_gpu_fault_event.va_block_retry = va_block_retry; + uvm_hmm_gpu_fault_event.service_context = service_context; + + args->vma = vma; + args->src = service_context->block_context.hmm.src_pfns + region.first; + args->dst = service_context->block_context.hmm.dst_pfns + region.first; + args->start = uvm_va_block_region_start(va_block, region); + args->end = uvm_va_block_region_end(va_block, region) + 1; + args->flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE | MIGRATE_VMA_SELECT_SYSTEM; + args->pgmap_owner = &g_uvm_global; + args->fault_page = NULL; + + // Prevent MMU invalidation callbacks from deadlocking in this thread. + uvm_context->ignore_hmm_invalidate_va_block = va_block; + + ret = migrate_vma_setup(args); + UVM_ASSERT(!ret); + + // The overall process here is to migrate pages from the CPU or GPUs to the + // faulting GPU. + // This is safe because we hold the va_block lock across the calls to + // uvm_hmm_gpu_fault_alloc_and_copy(), migrate_vma_pages(), + // uvm_hmm_gpu_fault_finalize_and_map(), and migrate_vma_finalize(). + // If uvm_hmm_gpu_fault_alloc_and_copy() needs to drop the va_block + // lock, a sequence number is used to tell if an invalidate() callback + // occurred while not holding the lock. If the sequence number changes, + // all the locks need to be dropped (mm, va_space, va_block) and the whole + // uvm_va_block_service_locked() called again. Otherwise, there were no + // conflicting invalidate callbacks and our snapshots of the CPU page + // tables are accurate and can be used to DMA pages and update GPU page + // tables. TODO: Bug 3901904: there might be better ways of handling no + // page being migrated. + status = uvm_hmm_gpu_fault_alloc_and_copy(vma, &uvm_hmm_gpu_fault_event); + if (status == NV_WARN_MORE_PROCESSING_REQUIRED) { + uvm_context->ignore_hmm_invalidate_va_block = NULL; + migrate_vma_finalize(args); + + // migrate_vma_setup() might have not been able to lock/isolate any + // pages because they are swapped out or are device exclusive. + // We do know that none of the pages in the region are zero pages + // since migrate_vma_setup() would have reported that information. + // Try to make it resident in system memory and retry the migration. + status = hmm_va_block_make_resident_cpu(va_block, service_context); + return NV_WARN_MORE_PROCESSING_REQUIRED; + } + + if (status == NV_OK) { + migrate_vma_pages(args); + status = uvm_hmm_gpu_fault_finalize_and_map(&uvm_hmm_gpu_fault_event); + } + + uvm_context->ignore_hmm_invalidate_va_block = NULL; + migrate_vma_finalize(args); + + if (status == NV_WARN_NOTHING_TO_DO) + status = NV_OK; + + return status; +} + +static NV_STATUS uvm_hmm_migrate_alloc_and_copy(struct vm_area_struct *vma, + uvm_hmm_migrate_event_t *uvm_hmm_migrate_event) +{ + uvm_va_block_t *va_block; + uvm_va_block_retry_t *va_block_retry; + uvm_va_block_context_t *va_block_context; + const unsigned long *src_pfns; + unsigned long *dst_pfns; + uvm_va_block_region_t region; + uvm_processor_id_t dest_id; + uvm_page_mask_t *page_mask; + NV_STATUS status; + + va_block = uvm_hmm_migrate_event->va_block; + va_block_retry = uvm_hmm_migrate_event->va_block_retry; + va_block_context = uvm_hmm_migrate_event->va_block_context; + src_pfns = va_block_context->hmm.src_pfns; + dst_pfns = va_block_context->hmm.dst_pfns; + region = uvm_hmm_migrate_event->region; + dest_id = uvm_hmm_migrate_event->dest_id; + page_mask = &uvm_hmm_migrate_event->page_mask; + uvm_page_mask_init_from_region(page_mask, region, NULL); + + uvm_assert_mutex_locked(&va_block->lock); + + if (UVM_ID_IS_CPU(dest_id)) { + status = alloc_and_copy_to_cpu(va_block, + vma, + src_pfns, + dst_pfns, + region, + page_mask, + &uvm_hmm_migrate_event->same_devmem_page_mask, + UVM_ID_INVALID, + NULL); + } + else { + status = dmamap_src_sysmem_pages(va_block, + vma, + src_pfns, + dst_pfns, + region, + page_mask, + dest_id, + NULL); + } + if (status != NV_OK) + return status; + + UVM_ASSERT(!uvm_va_policy_is_read_duplicate(va_block_context->policy, va_block->hmm.va_space)); + + status = uvm_va_block_make_resident_copy(va_block, + va_block_retry, + va_block_context, + dest_id, + region, + page_mask, + NULL, + uvm_hmm_migrate_event->cause); + if (status != NV_OK) + return status; + + if (!UVM_ID_IS_CPU(dest_id)) { + // Record the destination PFNs of device private struct pages now that + // uvm_va_block_make_resident_copy() has populated the GPU destination + // pages. + fill_dst_pfns(va_block, + src_pfns, + dst_pfns, + region, + page_mask, + &uvm_hmm_migrate_event->same_devmem_page_mask, + dest_id); + } + + return status; +} + +static NV_STATUS uvm_hmm_migrate_finalize(uvm_hmm_migrate_event_t *uvm_hmm_migrate_event) +{ + uvm_va_block_t *va_block; + uvm_va_block_retry_t *va_block_retry; + uvm_va_block_context_t *va_block_context; + uvm_va_block_region_t region; + uvm_processor_id_t dest_id; + uvm_page_index_t page_index; + uvm_page_mask_t *page_mask; + const unsigned long *src_pfns; + unsigned long *dst_pfns; + NV_STATUS status; + + va_block = uvm_hmm_migrate_event->va_block; + va_block_retry = uvm_hmm_migrate_event->va_block_retry; + va_block_context = uvm_hmm_migrate_event->va_block_context; + region = uvm_hmm_migrate_event->region; + dest_id = uvm_hmm_migrate_event->dest_id; + page_mask = &uvm_hmm_migrate_event->page_mask; + src_pfns = va_block_context->hmm.src_pfns; + dst_pfns = va_block_context->hmm.dst_pfns; + + uvm_assert_mutex_locked(&va_block->lock); + + // There are a number of reasons why HMM will mark a page as not migrating + // even if we set a valid entry in dst_pfns[]. Mark these pages accordingly. + for_each_va_block_page_in_region_mask(page_index, page_mask, region) { + unsigned long src_pfn = src_pfns[page_index]; + + if (src_pfn & MIGRATE_PFN_MIGRATE) + continue; + + // If a device private page isn't migrating and only the GPU page table + // is being updated, continue to process it normally. + if (uvm_page_mask_test(&uvm_hmm_migrate_event->same_devmem_page_mask, page_index)) + continue; + + clean_up_non_migrating_page(va_block, src_pfns, dst_pfns, page_index); + + uvm_page_mask_clear(page_mask, page_index); + } + + uvm_va_block_make_resident_finish(va_block, va_block_context, region, page_mask); + + // Wait for the GPU CE to finish. + // After this callback returns, the kernel will unmap all migrated + // pages, so the copy must be finished by then. + status = uvm_tracker_wait(&va_block->tracker); + if (status != NV_OK) + UVM_ERR_PRINT("uvm_tracker_wait failed, error %s\n", nvstatusToString(status)); + + clean_up(va_block, + src_pfns, + region, + page_mask, + &uvm_hmm_migrate_event->same_devmem_page_mask); + + return status; +} + +static NV_STATUS hmm_va_block_migrate_make_resident_cpu(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_page_mask_t *page_mask) +{ + uvm_thread_context_t *uvm_context = uvm_thread_context(); + struct vm_area_struct *vma = va_block_context->hmm.vma; + uvm_page_index_t page_index; + uvm_va_block_region_t region = uvm_va_block_region_from_mask(va_block, page_mask); + unsigned long *hmm_pfns = va_block_context->hmm.src_pfns; + unsigned long seqnum; + int ret; + struct hmm_range range = { + .notifier = &va_block->hmm.notifier, + .start = uvm_va_block_region_start(va_block, region), + .end = uvm_va_block_region_end(va_block, region) + 1, + .hmm_pfns = hmm_pfns + region.first, + .pfn_flags_mask = HMM_PFN_REQ_FAULT | HMM_PFN_REQ_WRITE, + .dev_private_owner = &g_uvm_global, + }; + + for_each_va_block_page_in_region(page_index, region) { + if (vma->vm_flags & VM_WRITE) + hmm_pfns[page_index] = HMM_PFN_REQ_FAULT | HMM_PFN_REQ_WRITE; + else + hmm_pfns[page_index] = HMM_PFN_REQ_FAULT; + } + + // Save the current sequence number so we can detect residency and mapping + // changes while not holding the va_block lock. + seqnum = va_block->hmm.changed; + + // Mirror the VA block to the HMM address range. + // Note that we request HMM to handle page faults, which means that it will + // populate and map potentially not-yet-existing pages to the VMA. + // Also note that mmu_interval_read_begin() calls wait_event() for any + // parallel invalidation callbacks to finish so we can't hold locks that + // the invalidation callback acquires. + uvm_mutex_unlock(&va_block->lock); + + // Prevent MMU invalidation callbacks in this thread from invalidating + // the hmm_range_fault() results. + uvm_context->ignore_hmm_invalidate_va_block = va_block; + + range.notifier_seq = mmu_interval_read_begin(range.notifier); + ret = hmm_range_fault(&range); + + uvm_context->ignore_hmm_invalidate_va_block = NULL; + + uvm_mutex_lock(&va_block->lock); + + if (ret) + return (ret == -EBUSY) ? NV_WARN_MORE_PROCESSING_REQUIRED : errno_to_nv_status(ret); + + if (mmu_interval_read_retry(range.notifier, range.notifier_seq)) + return NV_WARN_MORE_PROCESSING_REQUIRED; + + // We unlocked and relocked the block lock but held the mmap lock and + // va_space lock so pages could only be migrated, not destroyed. The VMAs + // will be unchanged since we hold the mmap lock. The policies will still + // be unchanged since no invalidate() callback was seen and holding the + // va_space lock prevents API policy changes. + if (seqnum != va_block->hmm.changed) + return NV_WARN_MORE_PROCESSING_REQUIRED; + + return populate_region(va_block, hmm_pfns, region); +} + +// Note that migrate_vma_*() doesn't handle asynchronous migrations so the +// migration flag UVM_MIGRATE_FLAG_SKIP_CPU_MAP doesn't have an effect. +// TODO: Bug 3900785: investigate ways to implement async migration. +static NV_STATUS hmm_va_block_migrate_locked(uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t dest_id, + uvm_va_block_region_t region, + uvm_make_resident_cause_t cause) +{ + uvm_thread_context_t *uvm_context = uvm_thread_context(); + uvm_hmm_migrate_event_t uvm_hmm_migrate_event; + struct vm_area_struct *vma = va_block_context->hmm.vma; + NvU64 start; + NvU64 end; + struct migrate_vma *args = &va_block_context->hmm.migrate_vma_args; + NV_STATUS status; + int ret; + + UVM_ASSERT(vma); + UVM_ASSERT(va_block_context->mm == vma->vm_mm); + uvm_assert_mmap_lock_locked(va_block_context->mm); + uvm_assert_mutex_locked(&va_block->lock); + + start = uvm_va_block_region_start(va_block, region); + end = uvm_va_block_region_end(va_block, region); + UVM_ASSERT(vma->vm_start <= start && end < vma->vm_end); + + uvm_hmm_migrate_event.va_block = va_block; + uvm_hmm_migrate_event.va_block_retry = va_block_retry; + uvm_hmm_migrate_event.va_block_context = va_block_context; + uvm_hmm_migrate_event.region = region; + uvm_hmm_migrate_event.dest_id = dest_id; + uvm_hmm_migrate_event.cause = cause; + + args->vma = vma; + args->src = va_block_context->hmm.src_pfns + region.first; + args->dst = va_block_context->hmm.dst_pfns + region.first; + args->start = uvm_va_block_region_start(va_block, region); + args->end = uvm_va_block_region_end(va_block, region) + 1; + args->flags = UVM_ID_IS_CPU(dest_id) ? MIGRATE_VMA_SELECT_DEVICE_PRIVATE : + MIGRATE_VMA_SELECT_DEVICE_PRIVATE | MIGRATE_VMA_SELECT_SYSTEM; + args->pgmap_owner = &g_uvm_global; + args->fault_page = NULL; + + // Prevent MMU invalidation callbacks from deadlocking in this thread. + uvm_context->ignore_hmm_invalidate_va_block = va_block; + + ret = migrate_vma_setup(args); + UVM_ASSERT(!ret); + + if (!args->cpages) { + uvm_processor_id_t id; + uvm_page_mask_t *page_mask; + + uvm_context->ignore_hmm_invalidate_va_block = NULL; + migrate_vma_finalize(args); + + // The CPU pages tables might contain only device private pages or + // the migrate_vma_setup() might have not been able to lock/isolate + // any pages because they are swapped out, or on another device. + // We do know that none of the pages in the region are zero pages + // since migrate_vma_setup() would have reported that information. + // Collect all the pages that need to be faulted in and made CPU + // resident, then do the hmm_range_fault() and retry. + page_mask = &va_block_context->caller_page_mask; + uvm_page_mask_init_from_region(page_mask, region, NULL); + + for_each_id_in_mask(id, &va_block->resident) { + if (!uvm_page_mask_andnot(page_mask, + page_mask, + uvm_va_block_resident_mask_get(va_block, id))) + return NV_OK; + } + + return hmm_va_block_migrate_make_resident_cpu(va_block, va_block_context, page_mask); + } + + // The overall process here is to migrate pages from the CPU or GPUs to the + // destination processor. Note that block_migrate_add_mappings() handles + // updating GPU mappings after the migration. + // This is safe because we hold the va_block lock across the calls to + // uvm_hmm_migrate_alloc_and_copy(), migrate_vma_pages(), + // uvm_hmm_migrate_finalize(), migrate_vma_finalize() and + // block_migrate_add_mappings(). + // If uvm_hmm_migrate_alloc_and_copy() needs to drop the va_block + // lock, a sequence number is used to tell if an invalidate() callback + // occurred while not holding the lock. If the sequence number changes, + // all the locks need to be dropped (mm, va_space, va_block) and the whole + // uvm_hmm_va_block_migrate_locked() called again. Otherwise, there were no + // conflicting invalidate callbacks and our snapshots of the CPU page + // tables are accurate and can be used to DMA pages and update GPU page + // tables. + status = uvm_hmm_migrate_alloc_and_copy(vma, &uvm_hmm_migrate_event); + if (status == NV_OK) { + migrate_vma_pages(args); + status = uvm_hmm_migrate_finalize(&uvm_hmm_migrate_event); + } + + uvm_context->ignore_hmm_invalidate_va_block = NULL; + migrate_vma_finalize(args); + + if (status == NV_WARN_NOTHING_TO_DO) + status = NV_OK; + + return status; +} + +NV_STATUS uvm_hmm_va_block_migrate_locked(uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t dest_id, + uvm_va_block_region_t region, + uvm_make_resident_cause_t cause) +{ + hmm_wait_for_atomic(va_block, region); + + return hmm_va_block_migrate_locked(va_block, + va_block_retry, + va_block_context, + dest_id, + region, + cause); +} + +NV_STATUS uvm_hmm_migrate_ranges(uvm_va_space_t *va_space, + uvm_va_block_context_t *va_block_context, + NvU64 base, + NvU64 length, + uvm_processor_id_t dest_id, + uvm_migrate_mode_t mode, + uvm_tracker_t *out_tracker) +{ + struct mm_struct *mm; + uvm_va_block_t *va_block; + uvm_va_block_retry_t va_block_retry; + NvU64 addr, end, last_address; + NV_STATUS status = NV_OK; + + if (!uvm_hmm_is_enabled(va_space)) + return NV_ERR_INVALID_ADDRESS; + + mm = va_block_context->mm; + UVM_ASSERT(mm == va_space->va_space_mm.mm); + uvm_assert_mmap_lock_locked(mm); + uvm_assert_rwsem_locked(&va_space->lock); + + last_address = base + length - 1; + + for (addr = base; addr < last_address; addr = end + 1) { + struct vm_area_struct *vma; + + status = hmm_va_block_find_create(va_space, addr, false, va_block_context, &va_block); + if (status != NV_OK) + return status; + + end = va_block->end; + if (end > last_address) + end = last_address; + + vma = va_block_context->hmm.vma; + if (end > vma->vm_end - 1) + end = vma->vm_end - 1; + + status = hmm_migrate_range(va_block, + &va_block_retry, + va_block_context, + dest_id, + addr, + end, + mode, + out_tracker); + if (status != NV_OK) + break; + } + + return status; +} + +NV_STATUS uvm_hmm_va_block_evict_chunk_prep(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_gpu_chunk_t *gpu_chunk, + uvm_va_block_region_t chunk_region) +{ + uvm_thread_context_t *uvm_context = uvm_thread_context(); + unsigned long *src_pfns = va_block_context->hmm.src_pfns; + uvm_gpu_t *gpu = uvm_gpu_chunk_get_gpu(gpu_chunk); + unsigned long pfn = uvm_pmm_gpu_devmem_get_pfn(&gpu->pmm, gpu_chunk); + uvm_page_index_t page_index = chunk_region.first; + int ret; + + uvm_assert_mutex_locked(&va_block->lock); + // TODO: Bug 3368756: add support for large GPU pages. + UVM_ASSERT(uvm_va_block_region_num_pages(chunk_region) == 1); + + uvm_context->ignore_hmm_invalidate_va_block = va_block; + ret = migrate_device_range(src_pfns + page_index, pfn, uvm_va_block_region_num_pages(chunk_region)); + uvm_context->ignore_hmm_invalidate_va_block = NULL; + if (ret) + return errno_to_nv_status(ret); + + return NV_OK; +} + +// Note that the caller must initialize va_block_context->hmm.src_pfns by +// calling uvm_hmm_va_block_evict_chunk_prep() before calling this. +static NV_STATUS hmm_va_block_evict_chunks(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + const uvm_page_mask_t *pages_to_evict, + uvm_va_block_region_t region, + uvm_make_resident_cause_t cause, + bool *out_accessed_by_set) +{ + NvU64 start = uvm_va_block_region_start(va_block, region); + NvU64 end = uvm_va_block_region_end(va_block, region); + unsigned long *src_pfns = va_block_context->hmm.src_pfns; + unsigned long *dst_pfns = va_block_context->hmm.dst_pfns; + uvm_hmm_migrate_event_t uvm_hmm_migrate_event = { + .va_block = va_block, + .va_block_retry = NULL, + .va_block_context = va_block_context, + .region = region, + .dest_id = UVM_ID_CPU, + .cause = cause, + }; + uvm_page_mask_t *page_mask = &uvm_hmm_migrate_event.page_mask; + const uvm_va_policy_t *policy; + uvm_va_policy_node_t *node; + unsigned long npages; + NV_STATUS status; + + uvm_assert_mutex_locked(&va_block->lock); + + if (out_accessed_by_set) + *out_accessed_by_set = false; + + // Note that there is no VMA available when evicting HMM pages. + va_block_context->hmm.vma = NULL; + + uvm_page_mask_copy(page_mask, pages_to_evict); + + uvm_for_each_va_policy_in(policy, va_block, start, end, node, region) { + npages = uvm_va_block_region_num_pages(region); + + va_block_context->policy = policy; + if (out_accessed_by_set && uvm_processor_mask_get_count(&policy->accessed_by) > 0) + *out_accessed_by_set = true; + + // Pages resident on the GPU should not have a resident page in system + // memory. + // TODO: Bug 3660922: Need to handle read duplication at some point. + UVM_ASSERT(uvm_page_mask_region_empty(&va_block->cpu.resident, region)); + + status = alloc_and_copy_to_cpu(va_block, + NULL, + src_pfns, + dst_pfns, + region, + page_mask, + NULL, + UVM_ID_INVALID, + NULL); + if (status != NV_OK) + goto err; + + status = uvm_va_block_make_resident_copy(va_block, + NULL, + va_block_context, + UVM_ID_CPU, + region, + page_mask, + NULL, + cause); + if (status != NV_OK) + goto err; + + migrate_device_pages(src_pfns + region.first, dst_pfns + region.first, npages); + + uvm_hmm_migrate_event.region = region; + + status = uvm_hmm_migrate_finalize(&uvm_hmm_migrate_event); + if (status != NV_OK) + goto err; + + migrate_device_finalize(src_pfns + region.first, dst_pfns + region.first, npages); + } + + return NV_OK; + +err: + migrate_device_finalize(src_pfns + region.first, dst_pfns + region.first, npages); + return status; +} + +NV_STATUS uvm_hmm_va_block_evict_chunks(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + const uvm_page_mask_t *pages_to_evict, + uvm_va_block_region_t region, + bool *out_accessed_by_set) +{ + return hmm_va_block_evict_chunks(va_block, + va_block_context, + pages_to_evict, + region, + UVM_MAKE_RESIDENT_CAUSE_EVICTION, + out_accessed_by_set); +} + +NV_STATUS uvm_hmm_va_block_evict_pages_from_gpu(uvm_va_block_t *va_block, + uvm_gpu_t *gpu, + uvm_va_block_context_t *va_block_context, + const uvm_page_mask_t *pages_to_evict, + uvm_va_block_region_t region) +{ + unsigned long *src_pfns = va_block_context->hmm.src_pfns; + uvm_va_block_gpu_state_t *gpu_state; + uvm_page_index_t page_index; + uvm_gpu_chunk_t *gpu_chunk; + NV_STATUS status; + + uvm_assert_mutex_locked(&va_block->lock); + + gpu_state = uvm_va_block_gpu_state_get(va_block, gpu->id); + UVM_ASSERT(gpu_state); + UVM_ASSERT(gpu_state->chunks); + + // Fill in the src_pfns[] with the ZONE_DEVICE private PFNs of the GPU. + memset(src_pfns, 0, sizeof(va_block_context->hmm.src_pfns)); + + // TODO: Bug 3368756: add support for large GPU pages. + for_each_va_block_page_in_region_mask(page_index, pages_to_evict, region) { + gpu_chunk = uvm_va_block_lookup_gpu_chunk(va_block, + gpu, + uvm_va_block_cpu_page_address(va_block, page_index)); + status = uvm_hmm_va_block_evict_chunk_prep(va_block, + va_block_context, + gpu_chunk, + uvm_va_block_region_for_page(page_index)); + if (status != NV_OK) + return status; + } + + return hmm_va_block_evict_chunks(va_block, + va_block_context, + pages_to_evict, + region, + UVM_MAKE_RESIDENT_CAUSE_API_MIGRATE, + NULL); +} + +NV_STATUS uvm_hmm_pmm_gpu_evict_chunk(uvm_gpu_t *gpu, + uvm_gpu_chunk_t *gpu_chunk) +{ + uvm_thread_context_t *uvm_context = uvm_thread_context(); + unsigned long pfn = uvm_pmm_gpu_devmem_get_pfn(&gpu->pmm, gpu_chunk); + unsigned long src_pfn = 0; + unsigned long dst_pfn = 0; + struct page *dst_page; + NV_STATUS status = NV_OK; + int ret; + + // TODO: Bug 3368756: add support for large GPU pages. + UVM_ASSERT(uvm_gpu_chunk_get_size(gpu_chunk) == PAGE_SIZE); + + uvm_context->ignore_hmm_invalidate_va_block = gpu_chunk->va_block; + ret = migrate_device_range(&src_pfn, pfn, 1); + uvm_context->ignore_hmm_invalidate_va_block = NULL; + if (ret) + return errno_to_nv_status(ret); + + if (src_pfn & MIGRATE_PFN_MIGRATE) { + // All the code for copying a vidmem page to sysmem relies on having + // a va_block. This case is only to support fork() and the child isn't + // guaranteed to get valid data. + // TODO: Bug 3902536: add code to migrate GPU memory without having a + // va_block. + dst_page = alloc_page(GFP_HIGHUSER_MOVABLE | __GFP_ZERO); + if (!dst_page) { + status = NV_ERR_NO_MEMORY; + goto out; + } + + lock_page(dst_page); + dst_pfn = migrate_pfn(page_to_pfn(dst_page)); + + migrate_device_pages(&src_pfn, &dst_pfn, 1); + } + +out: + migrate_device_finalize(&src_pfn, &dst_pfn, 1); + + return status; +} + +// The routines below are all for UVM-HMM tests. + +NV_STATUS uvm_hmm_va_block_range_bounds(uvm_va_space_t *va_space, + struct mm_struct *mm, + NvU64 lookup_address, + NvU64 *startp, + NvU64 *endp, + UVM_TEST_VA_RESIDENCY_INFO_PARAMS *params) +{ + struct vm_area_struct *vma; + NvU64 start; + NvU64 end; + + if (!uvm_hmm_is_enabled(va_space) || !mm) + return NV_ERR_INVALID_ADDRESS; + + uvm_assert_mmap_lock_locked(mm); + uvm_assert_rwsem_locked(&va_space->lock); + + // The VMA might have changed while not holding mmap_lock so check it. + vma = find_vma(mm, lookup_address); + if (!uvm_hmm_vma_is_valid(vma, lookup_address, false)) + return NV_ERR_INVALID_ADDRESS; + + // Since managed VA ranges don't cover more than one VMA, return only the + // intersecting range of the VA block and VMA. + start = UVM_VA_BLOCK_ALIGN_DOWN(lookup_address); + end = start + UVM_VA_BLOCK_SIZE - 1; + if (start < vma->vm_start) + start = vma->vm_start; + if (end > vma->vm_end - 1) + end = vma->vm_end - 1; + + *startp = start; + *endp = end; + + if (params) { + uvm_va_space_processor_uuid(va_space, ¶ms->resident_on[0], UVM_ID_CPU); + params->resident_physical_size[0] = PAGE_SIZE; + params->resident_on_count = 1; + + uvm_va_space_processor_uuid(va_space, ¶ms->mapped_on[0], UVM_ID_CPU); + params->mapping_type[0] = (vma->vm_flags & VM_WRITE) ? + UVM_PROT_READ_WRITE_ATOMIC : UVM_PROT_READ_ONLY; + params->page_size[0] = PAGE_SIZE; + params->mapped_on_count = 1; + + uvm_va_space_processor_uuid(va_space, ¶ms->populated_on[0], UVM_ID_CPU); + params->populated_on_count = 1; + } + + return NV_OK; +} + +NV_STATUS uvm_hmm_va_block_update_residency_info(uvm_va_block_t *va_block, + struct mm_struct *mm, + NvU64 lookup_address, + bool populate) +{ + uvm_va_space_t *va_space = va_block->hmm.va_space; + struct vm_area_struct *vma; + struct hmm_range range; + uvm_va_block_region_t region; + unsigned long seqnum; + unsigned long pfn; + NvU64 end; + int ret; + NV_STATUS status; + + if (!uvm_hmm_is_enabled(va_space) || !mm) + return NV_ERR_INVALID_ADDRESS; + + uvm_assert_mmap_lock_locked(mm); + uvm_assert_rwsem_locked(&va_space->lock); + + // The VMA might have changed while not holding mmap_lock so check it. + vma = find_vma(mm, lookup_address); + if (!uvm_hmm_vma_is_valid(vma, lookup_address, false)) + return NV_ERR_INVALID_ADDRESS; + + end = lookup_address + PAGE_SIZE; + region = uvm_va_block_region_from_start_end(va_block, lookup_address, end - 1); + + range.notifier = &va_block->hmm.notifier; + range.start = lookup_address; + range.end = end; + range.hmm_pfns = &pfn; + range.default_flags = 0; + range.pfn_flags_mask = 0; + range.dev_private_owner = &g_uvm_global; + range.notifier_seq = mmu_interval_read_begin(range.notifier); + + if (populate) { + range.default_flags = HMM_PFN_REQ_FAULT; + if (vma->vm_flags & VM_WRITE) + range.default_flags |= HMM_PFN_REQ_WRITE; + } + + // Save the current sequence number so we can detect residency and mapping + // changes while not holding the va_block lock. + uvm_mutex_lock(&va_block->lock); + seqnum = va_block->hmm.changed; + uvm_mutex_unlock(&va_block->lock); + + while (true) { + ret = hmm_range_fault(&range); + if (ret == -EBUSY) + continue; + if (ret) + return errno_to_nv_status(ret); + + uvm_mutex_lock(&va_block->lock); + + if (!mmu_interval_read_retry(range.notifier, range.notifier_seq) && + seqnum == va_block->hmm.changed) + break; + + seqnum = va_block->hmm.changed; + + uvm_mutex_unlock(&va_block->lock); + } + + // Update the va_block CPU state based on the snapshot. + // Note that we have to adjust the pfns address since it will be indexed + // by region.first. + status = populate_region(va_block, &pfn - region.first, region); + + uvm_mutex_unlock(&va_block->lock); + + return NV_OK; +} + NV_STATUS uvm_test_split_invalidate_delay(UVM_TEST_SPLIT_INVALIDATE_DELAY_PARAMS *params, struct file *filp) { uvm_va_space_t *va_space = uvm_va_space_get(filp); @@ -972,35 +3609,12 @@ NV_STATUS uvm_test_split_invalidate_delay(UVM_TEST_SPLIT_INVALIDATE_DELAY_PARAMS return NV_OK; } -NV_STATUS uvm_test_hmm_init(UVM_TEST_HMM_INIT_PARAMS *params, struct file *filp) -{ - uvm_va_space_t *va_space = uvm_va_space_get(filp); - struct mm_struct *mm; - NV_STATUS status; - - mm = uvm_va_space_mm_or_current_retain(va_space); - if (!mm) - return NV_WARN_NOTHING_TO_DO; - - uvm_down_write_mmap_lock(mm); - uvm_va_space_down_write(va_space); - if (va_space->hmm.disable) - status = uvm_hmm_va_space_initialize_test(va_space); - else - status = NV_OK; - uvm_va_space_up_write(va_space); - uvm_up_write_mmap_lock(mm); - uvm_va_space_mm_or_current_release(va_space, mm); - - return status; -} - NV_STATUS uvm_hmm_va_range_info(uvm_va_space_t *va_space, struct mm_struct *mm, UVM_TEST_VA_RANGE_INFO_PARAMS *params) { uvm_range_tree_node_t *tree_node; - uvm_va_policy_node_t *node; + const uvm_va_policy_node_t *node; struct vm_area_struct *vma; uvm_va_block_t *va_block; diff --git a/kernel-open/nvidia-uvm/uvm_hmm.h b/kernel-open/nvidia-uvm/uvm_hmm.h index 738ebcbe5..b6ecdae6d 100644 --- a/kernel-open/nvidia-uvm/uvm_hmm.h +++ b/kernel-open/nvidia-uvm/uvm_hmm.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2022 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -37,19 +37,10 @@ typedef struct // This stores pointers to uvm_va_block_t for HMM blocks. uvm_range_tree_t blocks; uvm_mutex_t blocks_lock; - - // TODO: Bug 3351822: [UVM-HMM] Remove temporary testing changes. - // This flag is set true by default for each va_space so most processes - // don't see partially implemented UVM-HMM behavior but can be enabled by - // test code for a given va_space so the test process can do some interim - // testing. It needs to be a separate flag instead of modifying - // uvm_disable_hmm or va_space->flags since those are user inputs and are - // visible/checked by test code. - // Remove this when UVM-HMM is fully integrated into chips_a. - bool disable; } uvm_hmm_va_space_t; #if UVM_IS_CONFIG_HMM() + // Tells whether HMM is enabled for the given va_space. // If it is not enabled, all of the functions below are no-ops. bool uvm_hmm_is_enabled(uvm_va_space_t *va_space); @@ -62,17 +53,25 @@ typedef struct // and the va_space lock must be held in write mode. NV_STATUS uvm_hmm_va_space_initialize(uvm_va_space_t *va_space); - // Initialize HMM for the given the va_space for testing. - // Bug 1750144: UVM: Add HMM (Heterogeneous Memory Management) support to - // the UVM driver. Remove this when enough HMM functionality is implemented. - // Locking: the va_space->va_space_mm.mm mmap_lock must be write locked - // and the va_space lock must be held in write mode. - NV_STATUS uvm_hmm_va_space_initialize_test(uvm_va_space_t *va_space); - // Destroy any HMM state for the given the va_space. // Locking: va_space lock must be held in write mode. void uvm_hmm_va_space_destroy(uvm_va_space_t *va_space); + // Unmap all page tables in this VA space which map memory owned by this + // GPU. Any memory still resident on this GPU will be evicted to system + // memory. Note that 'mm' can be NULL (e.g., when closing the UVM file) + // in which case any GPU memory is simply freed. + // Locking: if mm is not NULL, the caller must hold mm->mmap_lock in at + // least read mode and the va_space lock must be held in write mode. + void uvm_hmm_unregister_gpu(uvm_va_space_t *va_space, uvm_gpu_t *gpu, struct mm_struct *mm); + + // Destroy the VA space's mappings on the GPU, if it has any. + // Locking: if mm is not NULL, the caller must hold mm->mmap_lock in at + // least read mode and the va_space lock must be held in write mode. + void uvm_hmm_remove_gpu_va_space(uvm_va_space_t *va_space, + uvm_gpu_va_space_t *gpu_va_space, + struct mm_struct *mm); + // Find an existing HMM va_block. // This function can be called without having retained and locked the mm, // but in that case, the only allowed operations on the returned block are @@ -85,6 +84,25 @@ typedef struct NvU64 addr, uvm_va_block_t **va_block_ptr); + // Find an existing HMM va_block when processing a CPU fault and try to + // isolate and lock the faulting page. + // Return NV_ERR_INVALID_ADDRESS if the block is not found, + // NV_ERR_BUSY_RETRY if the page could not be locked, and + // NV_OK if the block is found and the page is locked. Also, + // uvm_hmm_cpu_fault_finish() must be called if NV_OK is returned. + // Locking: This must be called with the vma->vm_mm locked and the va_space + // read locked. + NV_STATUS uvm_hmm_va_block_cpu_find(uvm_va_space_t *va_space, + uvm_service_block_context_t *service_context, + struct vm_fault *vmf, + uvm_va_block_t **va_block_ptr); + + // This must be called after uvm_va_block_cpu_fault() if + // uvm_hmm_va_block_cpu_find() returns NV_OK. + // Locking: This must be called with the vma->vm_mm locked and the va_space + // read locked. + void uvm_hmm_cpu_fault_finish(uvm_service_block_context_t *service_context); + // Find or create a new HMM va_block. // // Return NV_ERR_INVALID_ADDRESS if there is no VMA associated with the @@ -114,9 +132,9 @@ typedef struct // Locking: This function must be called with the va_block lock held and if // va_block is a HMM block, va_block_context->mm must be retained and // locked for at least read. - bool uvm_hmm_va_block_context_vma_is_valid(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, - uvm_va_block_region_t region); + bool uvm_hmm_check_context_vma_is_valid(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_va_block_region_t region); // Find or create a HMM va_block and mark it so the next va_block split // will fail for testing purposes. @@ -168,7 +186,8 @@ typedef struct NV_STATUS uvm_hmm_set_preferred_location(uvm_va_space_t *va_space, uvm_processor_id_t preferred_location, NvU64 base, - NvU64 last_address); + NvU64 last_address, + uvm_tracker_t *out_tracker); // Set the accessed by policy for the given range. This also tries to // map the range. Note that 'last_address' is inclusive. @@ -178,7 +197,17 @@ typedef struct uvm_processor_id_t processor_id, bool set_bit, NvU64 base, - NvU64 last_address); + NvU64 last_address, + uvm_tracker_t *out_tracker); + + // Deferred work item to reestablish accessed by mappings after eviction. On + // GPUs with access counters enabled, the evicted GPU will also get remote + // mappings. + // Locking: the va_space->va_space_mm.mm mmap_lock must be locked + // and the va_space lock must be held in at least read mode. + void uvm_hmm_block_add_eviction_mappings(uvm_va_space_t *va_space, + uvm_va_block_t *va_block, + uvm_va_block_context_t *block_context); // Set the read duplication policy for the given range. // Note that 'last_address' is inclusive. @@ -248,7 +277,104 @@ typedef struct uvm_va_block_context_t *va_block_context, NvU64 addr); - NV_STATUS uvm_test_hmm_init(UVM_TEST_HMM_INIT_PARAMS *params, struct file *filp); + // This is called to service a GPU fault. + // Locking: the va_space->va_space_mm.mm mmap_lock must be locked, + // the va_space read lock must be held, and the va_block lock held. + NV_STATUS uvm_hmm_va_block_service_locked(uvm_processor_id_t processor_id, + uvm_processor_id_t new_residency, + uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_service_block_context_t *service_context); + + // This is called to migrate a region within a HMM va_block. + // va_block_context must not be NULL and va_block_context->policy and + // va_block_context->hmm.vma must be valid. + // Locking: the va_block_context->mm must be retained, mmap_lock must be + // locked, and the va_block lock held. + NV_STATUS uvm_hmm_va_block_migrate_locked(uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t dest_id, + uvm_va_block_region_t region, + uvm_make_resident_cause_t cause); + + // This is called to migrate an address range of HMM allocations via + // UvmMigrate(). + // + // va_block_context must not be NULL. The caller is not required to set + // va_block_context->policy or va_block_context->hmm.vma. + // + // Locking: the va_space->va_space_mm.mm mmap_lock must be locked and + // the va_space read lock must be held. + NV_STATUS uvm_hmm_migrate_ranges(uvm_va_space_t *va_space, + uvm_va_block_context_t *va_block_context, + NvU64 base, + NvU64 length, + uvm_processor_id_t dest_id, + uvm_migrate_mode_t mode, + uvm_tracker_t *out_tracker); + + // This sets the va_block_context->hmm.src_pfns[] to the ZONE_DEVICE private + // PFN for the GPU chunk memory. + NV_STATUS uvm_hmm_va_block_evict_chunk_prep(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_gpu_chunk_t *gpu_chunk, + uvm_va_block_region_t chunk_region); + + // Migrate pages to system memory for the given page mask. + // Note that the mmap lock is not held and there is no MM retained. + // This must be called after uvm_hmm_va_block_evict_chunk_prep() has + // initialized va_block_context->hmm.src_pfns[] for the source GPU physical + // PFNs being migrated. Note that the input mask 'pages_to_evict' can be + // modified. If any of the evicted pages has the accessed by policy set, + // then record that by setting out_accessed_by_set. + // Locking: the va_block lock must be locked. + NV_STATUS uvm_hmm_va_block_evict_chunks(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + const uvm_page_mask_t *pages_to_evict, + uvm_va_block_region_t region, + bool *out_accessed_by_set); + + // Migrate pages from the given GPU to system memory for the given page + // mask and region. va_block_context must not be NULL. + // Note that the mmap lock is not held and there is no MM retained. + // Locking: the va_block lock must be locked. + NV_STATUS uvm_hmm_va_block_evict_pages_from_gpu(uvm_va_block_t *va_block, + uvm_gpu_t *gpu, + uvm_va_block_context_t *va_block_context, + const uvm_page_mask_t *pages_to_evict, + uvm_va_block_region_t region); + + // Migrate a GPU chunk to system memory. This called to remove CPU page + // table references to device private struct pages for the given GPU after + // all other references in va_blocks have been released and the GPU is + // in the process of being removed/torn down. Note that there is no mm, + // VMA, va_block or any user channel activity on this GPU. + NV_STATUS uvm_hmm_pmm_gpu_evict_chunk(uvm_gpu_t *gpu, + uvm_gpu_chunk_t *gpu_chunk); + + // This returns what would be the intersection of va_block start/end and + // VMA start/end-1 for the given 'lookup_address' if + // uvm_hmm_va_block_find_create() was called. + // Locking: the caller must hold mm->mmap_lock in at least read mode and + // the va_space lock must be held in at least read mode. + NV_STATUS uvm_hmm_va_block_range_bounds(uvm_va_space_t *va_space, + struct mm_struct *mm, + NvU64 lookup_address, + NvU64 *startp, + NvU64 *endp, + UVM_TEST_VA_RESIDENCY_INFO_PARAMS *params); + + // This updates the HMM va_block CPU residency information for a single + // page at 'lookup_address' by calling hmm_range_fault(). If 'populate' is + // true, the CPU page will be faulted in read/write or read-only + // (depending on the permission of the underlying VMA at lookup_address). + // Locking: the caller must hold mm->mmap_lock in at least read mode and + // the va_space lock must be held in at least read mode. + NV_STATUS uvm_hmm_va_block_update_residency_info(uvm_va_block_t *va_block, + struct mm_struct *mm, + NvU64 lookup_address, + bool populate); NV_STATUS uvm_test_split_invalidate_delay(UVM_TEST_SPLIT_INVALIDATE_DELAY_PARAMS *params, struct file *filp); @@ -285,12 +411,17 @@ typedef struct return NV_OK; } - static NV_STATUS uvm_hmm_va_space_initialize_test(uvm_va_space_t *va_space) + static void uvm_hmm_va_space_destroy(uvm_va_space_t *va_space) { - return NV_WARN_NOTHING_TO_DO; } - static void uvm_hmm_va_space_destroy(uvm_va_space_t *va_space) + static void uvm_hmm_unregister_gpu(uvm_va_space_t *va_space, uvm_gpu_t *gpu, struct mm_struct *mm) + { + } + + static void uvm_hmm_remove_gpu_va_space(uvm_va_space_t *va_space, + uvm_gpu_va_space_t *gpu_va_space, + struct mm_struct *mm) { } @@ -301,6 +432,18 @@ typedef struct return NV_ERR_INVALID_ADDRESS; } + static NV_STATUS uvm_hmm_va_block_cpu_find(uvm_va_space_t *va_space, + uvm_service_block_context_t *service_context, + struct vm_fault *vmf, + uvm_va_block_t **va_block_ptr) + { + return NV_ERR_INVALID_ADDRESS; + } + + static void uvm_hmm_cpu_fault_finish(uvm_service_block_context_t *service_context) + { + } + static NV_STATUS uvm_hmm_va_block_find_create(uvm_va_space_t *va_space, NvU64 addr, uvm_va_block_context_t *va_block_context, @@ -314,9 +457,9 @@ typedef struct return NV_OK; } - static bool uvm_hmm_va_block_context_vma_is_valid(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, - uvm_va_block_region_t region) + static bool uvm_hmm_check_context_vma_is_valid(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_va_block_region_t region) { return true; } @@ -349,7 +492,8 @@ typedef struct static NV_STATUS uvm_hmm_set_preferred_location(uvm_va_space_t *va_space, uvm_processor_id_t preferred_location, NvU64 base, - NvU64 last_address) + NvU64 last_address, + uvm_tracker_t *out_tracker) { return NV_ERR_INVALID_ADDRESS; } @@ -358,11 +502,18 @@ typedef struct uvm_processor_id_t processor_id, bool set_bit, NvU64 base, - NvU64 last_address) + NvU64 last_address, + uvm_tracker_t *out_tracker) { return NV_ERR_INVALID_ADDRESS; } + static void uvm_hmm_block_add_eviction_mappings(uvm_va_space_t *va_space, + uvm_va_block_t *va_block, + uvm_va_block_context_t *block_context) + { + } + static NV_STATUS uvm_hmm_set_read_duplication(uvm_va_space_t *va_space, uvm_read_duplication_policy_t new_policy, NvU64 base, @@ -405,9 +556,84 @@ typedef struct return UVM_PROT_NONE; } - static NV_STATUS uvm_test_hmm_init(UVM_TEST_HMM_INIT_PARAMS *params, struct file *filp) + static NV_STATUS uvm_hmm_va_block_service_locked(uvm_processor_id_t processor_id, + uvm_processor_id_t new_residency, + uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_service_block_context_t *service_context) { - return NV_WARN_NOTHING_TO_DO; + return NV_ERR_INVALID_ADDRESS; + } + + static NV_STATUS uvm_hmm_va_block_migrate_locked(uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t dest_id, + uvm_va_block_region_t region, + uvm_make_resident_cause_t cause) + { + return NV_ERR_INVALID_ADDRESS; + } + + static NV_STATUS uvm_hmm_migrate_ranges(uvm_va_space_t *va_space, + uvm_va_block_context_t *va_block_context, + NvU64 base, + NvU64 length, + uvm_processor_id_t dest_id, + uvm_migrate_mode_t mode, + uvm_tracker_t *out_tracker) + { + return NV_ERR_INVALID_ADDRESS; + } + + static NV_STATUS uvm_hmm_va_block_evict_chunk_prep(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_gpu_chunk_t *gpu_chunk, + uvm_va_block_region_t chunk_region) + { + return NV_OK; + } + + static NV_STATUS uvm_hmm_va_block_evict_chunks(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + const uvm_page_mask_t *pages_to_evict, + uvm_va_block_region_t region, + bool *out_accessed_by_set) + { + return NV_OK; + } + + static NV_STATUS uvm_hmm_va_block_evict_pages_from_gpu(uvm_va_block_t *va_block, + uvm_gpu_t *gpu, + uvm_va_block_context_t *va_block_context, + const uvm_page_mask_t *pages_to_evict, + uvm_va_block_region_t region) + { + return NV_OK; + } + + static NV_STATUS uvm_hmm_pmm_gpu_evict_chunk(uvm_gpu_t *gpu, + uvm_gpu_chunk_t *gpu_chunk) + { + return NV_OK; + } + + static NV_STATUS uvm_hmm_va_block_range_bounds(uvm_va_space_t *va_space, + struct mm_struct *mm, + NvU64 lookup_address, + NvU64 *startp, + NvU64 *endp, + UVM_TEST_VA_RESIDENCY_INFO_PARAMS *params) + { + return NV_ERR_INVALID_ADDRESS; + } + + static NV_STATUS uvm_hmm_va_block_update_residency_info(uvm_va_block_t *va_block, + struct mm_struct *mm, + NvU64 lookup_address, + bool populate) + { + return NV_ERR_INVALID_ADDRESS; } static NV_STATUS uvm_test_split_invalidate_delay(UVM_TEST_SPLIT_INVALIDATE_DELAY_PARAMS *params, diff --git a/kernel-open/nvidia-uvm/uvm_hmm_sanity_test.c b/kernel-open/nvidia-uvm/uvm_hmm_sanity_test.c deleted file mode 100644 index 98f060c92..000000000 --- a/kernel-open/nvidia-uvm/uvm_hmm_sanity_test.c +++ /dev/null @@ -1,90 +0,0 @@ -/******************************************************************************* - Copyright (c) 2021-2022 NVIDIA Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. - -*******************************************************************************/ - -#include "uvm_common.h" -#include "uvm_linux.h" -#include "uvm_test.h" -#include "uvm_va_space.h" -#include "uvm_va_range.h" -#include "uvm_hmm.h" - -NV_STATUS uvm_test_hmm_sanity(UVM_TEST_HMM_SANITY_PARAMS *params, struct file *filp) -{ - uvm_va_space_t *va_space = uvm_va_space_get(filp); - struct mm_struct *mm; - uvm_va_block_t *hmm_block = NULL; - NV_STATUS status; - - mm = uvm_va_space_mm_or_current_retain(va_space); - if (!mm) - return NV_WARN_NOTHING_TO_DO; - - uvm_down_write_mmap_lock(mm); - uvm_va_space_down_write(va_space); - - // TODO: Bug 3351822: [UVM-HMM] Remove temporary testing changes. - // By default, HMM is enabled system wide but disabled per va_space. - // This will initialize the va_space for HMM. - status = uvm_hmm_va_space_initialize_test(va_space); - if (status != NV_OK) - goto out; - - uvm_va_space_up_write(va_space); - uvm_up_write_mmap_lock(mm); - - uvm_down_read_mmap_lock(mm); - uvm_va_space_down_read(va_space); - - // Try to create an HMM va_block to virtual address zero (NULL). - // It should fail. There should be no VMA but a va_block for range - // [0x0 0x1fffff] is possible. - status = uvm_hmm_va_block_find_create(va_space, 0UL, NULL, &hmm_block); - TEST_CHECK_GOTO(status == NV_ERR_INVALID_ADDRESS, done); - - // Try to create an HMM va_block which overlaps a managed block. - // It should fail. - status = uvm_hmm_va_block_find_create(va_space, params->uvm_address, NULL, &hmm_block); - TEST_CHECK_GOTO(status == NV_ERR_INVALID_ADDRESS, done); - - // Try to create an HMM va_block; it should succeed. - status = uvm_hmm_va_block_find_create(va_space, params->hmm_address, NULL, &hmm_block); - TEST_CHECK_GOTO(status == NV_OK, done); - - // Try to find an existing HMM va_block; it should succeed. - status = uvm_hmm_va_block_find(va_space, params->hmm_address, &hmm_block); - TEST_CHECK_GOTO(status == NV_OK, done); - -done: - uvm_va_space_up_read(va_space); - uvm_up_read_mmap_lock(mm); - uvm_va_space_mm_or_current_release(va_space, mm); - - return status; - -out: - uvm_va_space_up_write(va_space); - uvm_up_write_mmap_lock(mm); - uvm_va_space_mm_or_current_release(va_space, mm); - - return status; -} diff --git a/kernel-open/nvidia-uvm/uvm_hopper.c b/kernel-open/nvidia-uvm/uvm_hopper.c index a08d1522d..5aa7e9b51 100644 --- a/kernel-open/nvidia-uvm/uvm_hopper.c +++ b/kernel-open/nvidia-uvm/uvm_hopper.c @@ -54,6 +54,7 @@ void uvm_hal_hopper_arch_init_properties(uvm_parent_gpu_t *parent_gpu) parent_gpu->uvm_mem_va_base = parent_gpu->rm_va_size + 384ull * 1024 * 1024 * 1024 * 1024; parent_gpu->uvm_mem_va_size = UVM_MEM_VA_SIZE; + parent_gpu->peer_copy_mode = g_uvm_global.peer_copy_mode; // All GR context buffers may be mapped to 57b wide VAs. All "compute" units diff --git a/kernel-open/nvidia-uvm/uvm_hopper_ce.c b/kernel-open/nvidia-uvm/uvm_hopper_ce.c index 3d6c34ad1..f1b81a608 100644 --- a/kernel-open/nvidia-uvm/uvm_hopper_ce.c +++ b/kernel-open/nvidia-uvm/uvm_hopper_ce.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2020 NVIDIA Corporation + Copyright (c) 2020-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -23,25 +23,9 @@ #include "uvm_hal.h" #include "uvm_push.h" +#include "uvm_mem.h" #include "clc8b5.h" -static void hopper_membar_after_transfer(uvm_push_t *push) -{ - uvm_gpu_t *gpu = uvm_push_get_gpu(push); - - if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE)) - return; - - // TODO: [UVM-Volta] Remove Host WFI + Membar WAR for CE flush-only bug - // http://nvbugs/1734761 - gpu->parent->host_hal->wait_for_idle(push); - - if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU)) - gpu->parent->host_hal->membar_gpu(push); - else - gpu->parent->host_hal->membar_sys(push); -} - static NvU32 ce_aperture(uvm_aperture_t aperture) { BUILD_BUG_ON(HWCONST(C8B5, SET_SRC_PHYS_MODE, TARGET, LOCAL_FB) != @@ -78,45 +62,32 @@ void uvm_hal_hopper_ce_offset_in_out(uvm_push_t *push, NvU64 offset_in, NvU64 of OFFSET_OUT_LOWER, HWVALUE(C8B5, OFFSET_OUT_LOWER, VALUE, NvOffset_LO32(offset_out))); } -// Perform an appropriate membar before a semaphore operation. Returns whether -// the semaphore operation should include a flush. -static bool hopper_membar_before_semaphore(uvm_push_t *push) +// Return the flush type and the flush enablement. +static NvU32 hopper_get_flush_value(uvm_push_t *push) { - uvm_gpu_t *gpu; + NvU32 flush_value; + uvm_membar_t membar = uvm_push_get_and_reset_membar_flag(push); - if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE)) { + if (membar == UVM_MEMBAR_NONE) { // No MEMBAR requested, don't use a flush. - return false; + flush_value = HWCONST(C8B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE); + } + else { + flush_value = HWCONST(C8B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE); + + if (membar == UVM_MEMBAR_GPU) + flush_value |= HWCONST(C8B5, LAUNCH_DMA, FLUSH_TYPE, GL); + else + flush_value |= HWCONST(C8B5, LAUNCH_DMA, FLUSH_TYPE, SYS); } - if (!uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU)) { - // By default do a MEMBAR SYS and for that we can just use flush on the - // semaphore operation. - return true; - } - - // TODO: Bug 1734761: Remove the HOST WFI+membar WAR, i.e, perform the CE - // flush when MEMBAR GPU is requested. - gpu = uvm_push_get_gpu(push); - gpu->parent->host_hal->wait_for_idle(push); - gpu->parent->host_hal->membar_gpu(push); - - return false; + return flush_value; } void uvm_hal_hopper_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload) { uvm_gpu_t *gpu = uvm_push_get_gpu(push); - NvU32 flush_value; NvU32 launch_dma_plc_mode; - bool use_flush; - - use_flush = hopper_membar_before_semaphore(push); - - if (use_flush) - flush_value = HWCONST(C8B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE); - else - flush_value = HWCONST(C8B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE); NV_PUSH_3U(C8B5, SET_SEMAPHORE_A, HWVALUE(C8B5, SET_SEMAPHORE_A, UPPER, NvOffset_HI32(gpu_va)), SET_SEMAPHORE_B, HWVALUE(C8B5, SET_SEMAPHORE_B, LOWER, NvOffset_LO32(gpu_va)), @@ -124,7 +95,7 @@ void uvm_hal_hopper_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 p launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode(); - NV_PUSH_1U(C8B5, LAUNCH_DMA, flush_value | + NV_PUSH_1U(C8B5, LAUNCH_DMA, hopper_get_flush_value(push) | HWCONST(C8B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NONE) | HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_TYPE, RELEASE_ONE_WORD_SEMAPHORE) | launch_dma_plc_mode); @@ -133,16 +104,7 @@ void uvm_hal_hopper_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 p void uvm_hal_hopper_ce_semaphore_reduction_inc(uvm_push_t *push, NvU64 gpu_va, NvU32 payload) { uvm_gpu_t *gpu = uvm_push_get_gpu(push); - NvU32 flush_value; NvU32 launch_dma_plc_mode; - bool use_flush; - - use_flush = hopper_membar_before_semaphore(push); - - if (use_flush) - flush_value = HWCONST(C8B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE); - else - flush_value = HWCONST(C8B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE); NV_PUSH_3U(C8B5, SET_SEMAPHORE_A, HWVALUE(C8B5, SET_SEMAPHORE_A, UPPER, NvOffset_HI32(gpu_va)), SET_SEMAPHORE_B, HWVALUE(C8B5, SET_SEMAPHORE_B, LOWER, NvOffset_LO32(gpu_va)), @@ -150,7 +112,7 @@ void uvm_hal_hopper_ce_semaphore_reduction_inc(uvm_push_t *push, NvU64 gpu_va, N launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode(); - NV_PUSH_1U(C8B5, LAUNCH_DMA, flush_value | + NV_PUSH_1U(C8B5, LAUNCH_DMA, hopper_get_flush_value(push) | HWCONST(C8B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NONE) | HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_TYPE, RELEASE_ONE_WORD_SEMAPHORE) | HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_REDUCTION, INC) | @@ -162,16 +124,7 @@ void uvm_hal_hopper_ce_semaphore_reduction_inc(uvm_push_t *push, NvU64 gpu_va, N void uvm_hal_hopper_ce_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va) { uvm_gpu_t *gpu; - NvU32 flush_value; NvU32 launch_dma_plc_mode; - bool use_flush; - - use_flush = hopper_membar_before_semaphore(push); - - if (use_flush) - flush_value = HWCONST(C8B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE); - else - flush_value = HWCONST(C8B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE); NV_PUSH_3U(C8B5, SET_SEMAPHORE_A, HWVALUE(C8B5, SET_SEMAPHORE_A, UPPER, NvOffset_HI32(gpu_va)), SET_SEMAPHORE_B, HWVALUE(C8B5, SET_SEMAPHORE_B, LOWER, NvOffset_LO32(gpu_va)), @@ -180,7 +133,7 @@ void uvm_hal_hopper_ce_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va) gpu = uvm_push_get_gpu(push); launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode(); - NV_PUSH_1U(C8B5, LAUNCH_DMA, flush_value | + NV_PUSH_1U(C8B5, LAUNCH_DMA, hopper_get_flush_value(push) | HWCONST(C8B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NONE) | HWCONST(C8B5, LAUNCH_DMA, SEMAPHORE_TYPE, RELEASE_FOUR_WORD_SEMAPHORE) | launch_dma_plc_mode); @@ -218,8 +171,9 @@ static void hopper_memset_common(uvm_push_t *push, NvU32 launch_dma_plc_mode; NvU32 launch_dma_remap_enable; NvU32 launch_dma_scrub_enable; + NvU32 flush_value = HWCONST(C8B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE); - UVM_ASSERT_MSG(gpu->parent->ce_hal->memset_validate(push, dst, memset_element_size), + UVM_ASSERT_MSG(gpu->parent->ce_hal->memset_is_valid(push, dst, memset_element_size), "Memset validation failed in channel %s, GPU %s", push->channel->name, uvm_gpu_name(gpu)); @@ -252,6 +206,10 @@ static void hopper_memset_common(uvm_push_t *push, do { NvU32 memset_this_time = (NvU32)min(num_elements, max_single_memset); + // In the last operation, a flush/membar may be issued after the memset. + if (num_elements == memset_this_time) + flush_value = hopper_get_flush_value(push); + gpu->parent->ce_hal->offset_out(push, dst.address); NV_PUSH_1U(C8B5, LINE_LENGTH_IN, memset_this_time); @@ -260,7 +218,7 @@ static void hopper_memset_common(uvm_push_t *push, HWCONST(C8B5, LAUNCH_DMA, SRC_MEMORY_LAYOUT, PITCH) | HWCONST(C8B5, LAUNCH_DMA, DST_MEMORY_LAYOUT, PITCH) | HWCONST(C8B5, LAUNCH_DMA, MULTI_LINE_ENABLE, FALSE) | - HWCONST(C8B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE) | + flush_value | launch_dma_remap_enable | launch_dma_scrub_enable | launch_dma_dst_type | @@ -269,10 +227,8 @@ static void hopper_memset_common(uvm_push_t *push, dst.address += memset_this_time * memset_element_size; num_elements -= memset_this_time; - pipelined_value = HWCONST(C8B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED); + pipelined_value = HWCONST(C8B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, PIPELINED); } while (num_elements > 0); - - hopper_membar_after_transfer(push); } void uvm_hal_hopper_ce_memset_8(uvm_push_t *push, uvm_gpu_address_t dst, NvU64 value, size_t size) @@ -337,3 +293,16 @@ void uvm_hal_hopper_ce_memset_4(uvm_push_t *push, uvm_gpu_address_t dst, NvU32 v hopper_memset_common(push, dst, size, 4); } + +bool uvm_hal_hopper_ce_memset_is_valid(uvm_push_t *push, uvm_gpu_address_t dst, size_t element_size) +{ + + return true; +} + +bool uvm_hal_hopper_ce_memcopy_is_valid(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src) +{ + + return true; +} + diff --git a/kernel-open/nvidia-uvm/uvm_linux.h b/kernel-open/nvidia-uvm/uvm_linux.h index 94a5c3ce4..561af31fa 100644 --- a/kernel-open/nvidia-uvm/uvm_linux.h +++ b/kernel-open/nvidia-uvm/uvm_linux.h @@ -108,7 +108,7 @@ static inline const struct cpumask *uvm_cpumask_of_node(int node) #endif } - #if defined(CONFIG_HMM_MIRROR) && defined(CONFIG_DEVICE_PRIVATE) && defined(NV_MAKE_DEVICE_EXCLUSIVE_RANGE_PRESENT) + #if defined(CONFIG_HMM_MIRROR) && defined(CONFIG_DEVICE_PRIVATE) && defined(NV_MIGRATE_DEVICE_RANGE_PRESENT) #define UVM_IS_CONFIG_HMM() 1 #else #define UVM_IS_CONFIG_HMM() 0 @@ -404,6 +404,7 @@ static inline NvU64 NV_GETTIME(void) // 654672d4ba1a6001c365833be895f9477c4d5eab ("locking/atomics: // Add _{acquire|release|relaxed}() variants of some atomic operations") in v4.3 // (2015-08-06). +// TODO: Bug 3849079: We always use this definition on newer kernels. #ifndef atomic_read_acquire #define atomic_read_acquire(p) smp_load_acquire(&(p)->counter) #endif @@ -412,6 +413,24 @@ static inline NvU64 NV_GETTIME(void) #define atomic_set_release(p, v) smp_store_release(&(p)->counter, v) #endif +// atomic_long_read_acquire and atomic_long_set_release were added in commit +// b5d47ef9ea5c5fe31d7eabeb79f697629bd9e2cb ("locking/atomics: Switch to +// generated atomic-long") in v5.1 (2019-05-05). +// TODO: Bug 3849079: We always use these definitions on newer kernels. +#define atomic_long_read_acquire uvm_atomic_long_read_acquire +static inline long uvm_atomic_long_read_acquire(atomic_long_t *p) +{ + long val = atomic_long_read(p); + smp_mb(); + return val; +} + +#define atomic_long_set_release uvm_atomic_long_set_release +static inline void uvm_atomic_long_set_release(atomic_long_t *p, long v) +{ + smp_mb(); + atomic_long_set(p, v); +} // Added in 3.11 #ifndef PAGE_ALIGNED diff --git a/kernel-open/nvidia-uvm/uvm_lock.h b/kernel-open/nvidia-uvm/uvm_lock.h index d6bd70649..570a4ec46 100644 --- a/kernel-open/nvidia-uvm/uvm_lock.h +++ b/kernel-open/nvidia-uvm/uvm_lock.h @@ -75,26 +75,29 @@ // // Protects: // - gpu->parent->isr.replayable_faults.service_lock: -// Changes to the state of a GPU as it transitions from top-half to bottom-half -// interrupt handler for replayable faults. This lock is acquired for that GPU, -// in the ISR top-half. Then a bottom-half is scheduled (to run in a workqueue). -// Then the bottom-half releases the lock when that GPU's processing appears to -// be done. +// Changes to the state of a GPU as it transitions from top-half to +// bottom-half interrupt handler for replayable faults. This lock is +// acquired for that GPU, in the ISR top-half. Then a bottom-half is +// scheduled (to run in a workqueue). Then the bottom-half releases the +// lock when that GPU's processing appears to be done. +// // - gpu->parent->isr.non_replayable_faults.service_lock: -// Changes to the state of a GPU in the bottom-half for non-replayable faults. -// Non-replayable faults are handed-off from RM instead of directly from the GPU -// hardware. This means that we do not keep receiving interrupts after RM pops -// out the faults from the HW buffer. In order not to miss fault notifications, -// we will always schedule a bottom-half for non-replayable faults if there are -// faults ready to be consumed in the buffer, even if there already is some -// bottom-half running or scheduled. This lock serializes all scheduled bottom -// halves per GPU which service non-replayable faults. +// Changes to the state of a GPU in the bottom-half for non-replayable +// faults. Non-replayable faults are handed-off from RM instead of +// directly from the GPU hardware. This means that we do not keep +// receiving interrupts after RM pops out the faults from the HW buffer. +// In order not to miss fault notifications, we will always schedule a +// bottom-half for non-replayable faults if there are faults ready to be +// consumed in the buffer, even if there already is some bottom-half +// running or scheduled. This lock serializes all scheduled bottom halves +// per GPU which service non-replayable faults. +// // - gpu->parent->isr.access_counters.service_lock: -// Changes to the state of a GPU as it transitions from top-half to bottom-half -// interrupt handler for access counter notifications. This lock is acquired for -// that GPU, in the ISR top-half. Then a bottom-half is scheduled (to run in a -// workqueue). Then the bottom-half releases the lock when that GPU's processing -// appears to be done. +// Changes to the state of a GPU as it transitions from top-half to +// bottom-half interrupt handler for access counter notifications. This +// lock is acquired for that GPU, in the ISR top-half. Then a bottom-half +// is scheduled (to run in a workqueue). Then the bottom-half releases +// the lock when that GPU's processing appears to be done. // // - mmap_lock (mmap_sem in kernels < 5.8) // Order: UVM_LOCK_ORDER_MMAP_LOCK @@ -339,7 +342,9 @@ // Order: UVM_LOCK_ORDER_CHANNEL // Spinlock (uvm_spinlock_t) or exclusive lock (mutex) // -// Lock protecting the state of all the channels in a channel pool. +// Lock protecting the state of all the channels in a channel pool. The +// channel pool lock documentation contains the guidelines about which lock +// type (mutex or spinlock) to use. // // - Tools global VA space list lock (g_tools_va_space_list_lock) // Order: UVM_LOCK_ORDER_TOOLS_VA_SPACE_LIST diff --git a/kernel-open/nvidia-uvm/uvm_map_external.c b/kernel-open/nvidia-uvm/uvm_map_external.c index e6404e667..839929517 100644 --- a/kernel-open/nvidia-uvm/uvm_map_external.c +++ b/kernel-open/nvidia-uvm/uvm_map_external.c @@ -106,6 +106,9 @@ static NV_STATUS uvm_pte_buffer_init(uvm_va_range_t *va_range, pte_buffer->mapping_info.formatType = map_rm_params->format_type; pte_buffer->mapping_info.elementBits = map_rm_params->element_bits; pte_buffer->mapping_info.compressionType = map_rm_params->compression_type; + if (va_range->type == UVM_VA_RANGE_TYPE_EXTERNAL) + pte_buffer->mapping_info.mappingPageSize = page_size; + pte_buffer->page_size = page_size; pte_buffer->pte_size = uvm_mmu_pte_size(tree, page_size); num_all_ptes = uvm_div_pow2_64(length, page_size); @@ -341,9 +344,8 @@ static NV_STATUS map_rm_pt_range(uvm_page_tree_t *tree, static uvm_membar_t va_range_downgrade_membar(uvm_va_range_t *va_range, uvm_ext_gpu_map_t *ext_gpu_map) { if (va_range->type == UVM_VA_RANGE_TYPE_CHANNEL) { - if (va_range->channel.aperture == UVM_APERTURE_VID) - return UVM_MEMBAR_GPU; - return UVM_MEMBAR_SYS; + return uvm_hal_downgrade_membar_type(va_range->channel.gpu_va_space->gpu, + va_range->channel.aperture == UVM_APERTURE_VID); } // If there is no mem_handle, this is a sparse mapping. @@ -353,9 +355,8 @@ static uvm_membar_t va_range_downgrade_membar(uvm_va_range_t *va_range, uvm_ext_ if (!ext_gpu_map->mem_handle) return UVM_MEMBAR_GPU; - if (ext_gpu_map->is_sysmem || ext_gpu_map->gpu != ext_gpu_map->owning_gpu) - return UVM_MEMBAR_SYS; - return UVM_MEMBAR_GPU; + return uvm_hal_downgrade_membar_type(ext_gpu_map->gpu, + !ext_gpu_map->is_sysmem && ext_gpu_map->gpu == ext_gpu_map->owning_gpu); } NV_STATUS uvm_va_range_map_rm_allocation(uvm_va_range_t *va_range, @@ -398,9 +399,7 @@ NV_STATUS uvm_va_range_map_rm_allocation(uvm_va_range_t *va_range, page_tree = &gpu_va_space->page_tables; - // Verify that the GPU VA space supports this page size - if ((mem_info->pageSize & page_tree->hal->page_sizes()) == 0) - return NV_ERR_INVALID_ADDRESS; + UVM_ASSERT(uvm_mmu_page_size_supported(page_tree, mem_info->pageSize)); if (va_range->type == UVM_VA_RANGE_TYPE_EXTERNAL) { // We should be never called with ext_gpu_map == NULL @@ -414,13 +413,12 @@ NV_STATUS uvm_va_range_map_rm_allocation(uvm_va_range_t *va_range, pt_range_vec = &va_range->channel.pt_range_vec; } - if (!IS_ALIGNED(map_offset, mem_info->pageSize) || - map_offset + uvm_range_tree_node_size(node) > mem_info->size) + if (map_offset + uvm_range_tree_node_size(node) > mem_info->size) return NV_ERR_INVALID_OFFSET; - // Consolidate input checks for API-level callers - if (!IS_ALIGNED(node->start, mem_info->pageSize) || !IS_ALIGNED(node->end + 1, mem_info->pageSize)) - return NV_ERR_INVALID_ADDRESS; + UVM_ASSERT(IS_ALIGNED(node->start, mem_info->pageSize) && + IS_ALIGNED(node->end + 1, mem_info->pageSize) && + IS_ALIGNED(map_offset, mem_info->pageSize)); status = uvm_pte_buffer_init(va_range, mapping_gpu, @@ -845,6 +843,10 @@ static NV_STATUS uvm_map_external_allocation_on_gpu(uvm_va_range_t *va_range, uvm_ext_gpu_map_t *ext_gpu_map = NULL; uvm_ext_gpu_range_tree_t *range_tree = uvm_ext_gpu_range_tree(va_range, mapping_gpu); UvmGpuMemoryInfo mem_info; + uvm_gpu_va_space_t *gpu_va_space = uvm_gpu_va_space_get(va_space, mapping_gpu); + NvU32 mapping_page_size; + NvU64 alignments; + NvU32 smallest_alignment; NV_STATUS status; uvm_assert_rwsem_locked_read(&va_space->lock); @@ -915,12 +917,25 @@ static NV_STATUS uvm_map_external_allocation_on_gpu(uvm_va_range_t *va_range, if (status != NV_OK) goto error; - status = uvm_va_range_map_rm_allocation(va_range, - mapping_gpu, - &mem_info, - map_rm_params, - ext_gpu_map, - out_tracker); + // Determine the proper mapping page size. + // This will be the largest supported page size less than or equal to the + // smallest of the base VA address, length, offset, and allocation page size + // alignments. + alignments = mem_info.pageSize | base | length | map_rm_params->map_offset; + smallest_alignment = alignments & ~(alignments - 1); + + // Check that alignment bits did not get truncated. + UVM_ASSERT(smallest_alignment); + + mapping_page_size = uvm_mmu_biggest_page_size_up_to(&gpu_va_space->page_tables, smallest_alignment); + if (!mapping_page_size) { + status = NV_ERR_INVALID_ADDRESS; + goto error; + } + + mem_info.pageSize = mapping_page_size; + + status = uvm_va_range_map_rm_allocation(va_range, mapping_gpu, &mem_info, map_rm_params, ext_gpu_map, out_tracker); if (status != NV_OK) goto error; diff --git a/kernel-open/nvidia-uvm/uvm_maxwell_ce.c b/kernel-open/nvidia-uvm/uvm_maxwell_ce.c index f96e97918..6144bb46b 100644 --- a/kernel-open/nvidia-uvm/uvm_maxwell_ce.c +++ b/kernel-open/nvidia-uvm/uvm_maxwell_ce.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2021 NVIDIA Corporation + Copyright (c) 2021-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -50,38 +50,12 @@ void uvm_hal_maxwell_ce_offset_in_out(uvm_push_t *push, NvU64 offset_in, NvU64 o OFFSET_OUT_LOWER, HWVALUE(B0B5, OFFSET_OUT_LOWER, VALUE, NvOffset_LO32(offset_out))); } -// Perform an appropriate membar before a semaphore operation. Returns whether -// the semaphore operation should include a flush. -static bool maxwell_membar_before_semaphore(uvm_push_t *push) -{ - uvm_gpu_t *gpu; - - if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE)) { - // No MEMBAR requested, don't use a flush. - return false; - } - - if (!uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU)) { - // By default do a MEMBAR SYS and for that we can just use flush on the - // semaphore operation. - return true; - } - - // MEMBAR GPU requested, do it on the HOST and skip the CE flush as CE - // doesn't have this capability. - gpu = uvm_push_get_gpu(push); - gpu->parent->host_hal->wait_for_idle(push); - gpu->parent->host_hal->membar_gpu(push); - - return false; -} - void uvm_hal_maxwell_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload) { NvU32 flush_value; bool use_flush; - use_flush = maxwell_membar_before_semaphore(push); + use_flush = uvm_hal_membar_before_semaphore(push); if (use_flush) flush_value = HWCONST(B0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE); @@ -102,7 +76,7 @@ void uvm_hal_maxwell_ce_semaphore_reduction_inc(uvm_push_t *push, NvU64 gpu_va, NvU32 flush_value; bool use_flush; - use_flush = maxwell_membar_before_semaphore(push); + use_flush = uvm_hal_membar_before_semaphore(push); if (use_flush) flush_value = HWCONST(B0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE); @@ -126,7 +100,7 @@ void uvm_hal_maxwell_ce_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va) NvU32 flush_value; bool use_flush; - use_flush = maxwell_membar_before_semaphore(push); + use_flush = uvm_hal_membar_before_semaphore(push); if (use_flush) flush_value = HWCONST(B0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE); @@ -221,10 +195,9 @@ void uvm_hal_maxwell_ce_memcopy(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu NvU32 pipelined_value; NvU32 launch_dma_src_dst_type; NvU32 launch_dma_plc_mode; - bool first_operation = true; - UVM_ASSERT_MSG(gpu->parent->ce_hal->memcopy_validate(push, dst, src), - "Memcopy validation failed in channel %s, GPU %s", + UVM_ASSERT_MSG(gpu->parent->ce_hal->memcopy_is_valid(push, dst, src), + "Memcopy validation failed in channel %s, GPU %s.\n", push->channel->name, uvm_gpu_name(gpu)); @@ -233,14 +206,14 @@ void uvm_hal_maxwell_ce_memcopy(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu launch_dma_src_dst_type = gpu->parent->ce_hal->phys_mode(push, dst, src); launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode(); + if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED)) + pipelined_value = HWCONST(B0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, PIPELINED); + else + pipelined_value = HWCONST(B0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED); + do { NvU32 copy_this_time = (NvU32)min(size, max_single_copy_size); - if (first_operation && uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED)) - pipelined_value = HWCONST(B0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, PIPELINED); - else - pipelined_value = HWCONST(B0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED); - gpu->parent->ce_hal->offset_in_out(push, src.address, dst.address); NV_PUSH_1U(B0B5, LINE_LENGTH_IN, copy_this_time); @@ -255,10 +228,10 @@ void uvm_hal_maxwell_ce_memcopy(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu launch_dma_plc_mode | pipelined_value); + pipelined_value = HWCONST(B0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, PIPELINED); dst.address += copy_this_time; src.address += copy_this_time; size -= copy_this_time; - first_operation = false; } while (size > 0); maxwell_membar_after_transfer(push); @@ -266,11 +239,14 @@ void uvm_hal_maxwell_ce_memcopy(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu void uvm_hal_maxwell_ce_memcopy_v_to_v(uvm_push_t *push, NvU64 dst_va, NvU64 src_va, size_t size) { - uvm_hal_maxwell_ce_memcopy(push, uvm_gpu_address_virtual(dst_va), uvm_gpu_address_virtual(src_va), size); + uvm_push_get_gpu(push)->parent->ce_hal->memcopy(push, + uvm_gpu_address_virtual(dst_va), + uvm_gpu_address_virtual(src_va), + size); } // Push SET_DST_PHYS mode if needed and return LAUNCH_DMA_DST_TYPE flags -static NvU32 memset_push_phys_mode(uvm_push_t *push, uvm_gpu_address_t dst) +static NvU32 maxwell_memset_push_phys_mode(uvm_push_t *push, uvm_gpu_address_t dst) { if (dst.is_virtual) return HWCONST(B0B5, LAUNCH_DMA, DST_TYPE, VIRTUAL); @@ -290,12 +266,12 @@ static void memset_common(uvm_push_t *push, uvm_gpu_address_t dst, size_t size, NvU32 launch_dma_dst_type; NvU32 launch_dma_plc_mode; - UVM_ASSERT_MSG(gpu->parent->ce_hal->memset_validate(push, dst, memset_element_size), - "Memset validation failed in channel %s, GPU %s", + UVM_ASSERT_MSG(gpu->parent->ce_hal->memset_is_valid(push, dst, memset_element_size), + "Memset validation failed in channel %s, GPU %s.\n", push->channel->name, uvm_gpu_name(gpu)); - launch_dma_dst_type = memset_push_phys_mode(push, dst); + launch_dma_dst_type = maxwell_memset_push_phys_mode(push, dst); launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode(); if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED)) @@ -322,7 +298,7 @@ static void memset_common(uvm_push_t *push, uvm_gpu_address_t dst, size_t size, dst.address += memset_this_time * memset_element_size; size -= memset_this_time; - pipelined_value = HWCONST(B0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED); + pipelined_value = HWCONST(B0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, PIPELINED); } while (size > 0); maxwell_membar_after_transfer(push); @@ -373,5 +349,6 @@ void uvm_hal_maxwell_ce_memset_8(uvm_push_t *push, uvm_gpu_address_t dst, NvU64 void uvm_hal_maxwell_ce_memset_v_4(uvm_push_t *push, NvU64 dst_va, NvU32 value, size_t size) { - uvm_hal_maxwell_ce_memset_4(push, uvm_gpu_address_virtual(dst_va), value, size); + uvm_push_get_gpu(push)->parent->ce_hal->memset_4(push, uvm_gpu_address_virtual(dst_va), value, size); } + diff --git a/kernel-open/nvidia-uvm/uvm_mem.c b/kernel-open/nvidia-uvm/uvm_mem.c index 1839b836d..4370af944 100644 --- a/kernel-open/nvidia-uvm/uvm_mem.c +++ b/kernel-open/nvidia-uvm/uvm_mem.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2021 NVIDIA Corporation + Copyright (c) 2016-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -455,7 +455,7 @@ static gfp_t sysmem_allocation_gfp_flags(int order, bool zero) // // In case of failure, the caller is required to handle cleanup by calling // uvm_mem_free -static NV_STATUS mem_alloc_sysmem_dma_chunks(uvm_mem_t *mem, struct mm_struct *mm, gfp_t gfp_flags) +static NV_STATUS mem_alloc_sysmem_dma_chunks(uvm_mem_t *mem, gfp_t gfp_flags) { size_t i; NV_STATUS status; @@ -500,7 +500,7 @@ error: // In case of failure, the caller is required to handle cleanup by calling // uvm_mem_free -static NV_STATUS mem_alloc_sysmem_chunks(uvm_mem_t *mem, struct mm_struct *mm, gfp_t gfp_flags) +static NV_STATUS mem_alloc_sysmem_chunks(uvm_mem_t *mem, gfp_t gfp_flags) { size_t i; int order; @@ -573,9 +573,9 @@ static NV_STATUS mem_alloc_chunks(uvm_mem_t *mem, struct mm_struct *mm, bool zer uvm_memcg_context_start(&memcg_context, mm); if (uvm_mem_is_sysmem_dma(mem)) - status = mem_alloc_sysmem_dma_chunks(mem, mm, gfp_flags); + status = mem_alloc_sysmem_dma_chunks(mem, gfp_flags); else - status = mem_alloc_sysmem_chunks(mem, mm, gfp_flags); + status = mem_alloc_sysmem_chunks(mem, gfp_flags); uvm_memcg_context_end(&memcg_context); return status; @@ -584,14 +584,6 @@ static NV_STATUS mem_alloc_chunks(uvm_mem_t *mem, struct mm_struct *mm, bool zer return mem_alloc_vidmem_chunks(mem, zero, is_protected); } -static const char *mem_physical_source(uvm_mem_t *mem) -{ - if (uvm_mem_is_vidmem(mem)) - return uvm_gpu_name(mem->backing_gpu); - - return "CPU"; -} - NV_STATUS uvm_mem_map_kernel(uvm_mem_t *mem, const uvm_global_processor_mask_t *mask) { uvm_gpu_t *gpu; @@ -617,6 +609,7 @@ NV_STATUS uvm_mem_map_kernel(uvm_mem_t *mem, const uvm_global_processor_mask_t * NV_STATUS uvm_mem_alloc(const uvm_mem_alloc_params_t *params, uvm_mem_t **mem_out) { NV_STATUS status; + NvU64 physical_size; uvm_mem_t *mem = NULL; bool is_protected = false; @@ -637,8 +630,8 @@ NV_STATUS uvm_mem_alloc(const uvm_mem_alloc_params_t *params, uvm_mem_t **mem_ou UVM_ASSERT(mem->chunk_size > 0); - mem->physical_allocation_size = UVM_ALIGN_UP(mem->size, mem->chunk_size); - mem->chunks_count = mem->physical_allocation_size / mem->chunk_size; + physical_size = UVM_ALIGN_UP(mem->size, mem->chunk_size); + mem->chunks_count = physical_size / mem->chunk_size; status = mem_alloc_chunks(mem, params->mm, params->zero, is_protected); if (status != NV_OK) @@ -665,7 +658,7 @@ static NV_STATUS mem_init_user_mapping(uvm_mem_t *mem, uvm_va_space_t *user_va_s } UVM_ASSERT(IS_ALIGNED((NvU64)user_addr, mem->chunk_size)); - UVM_ASSERT(mem->physical_allocation_size == mem->size); + UVM_ASSERT(uvm_mem_physical_size(mem) == mem->size); mem->user = uvm_kvmalloc_zero(sizeof(*mem->user)); if (mem->user == NULL) @@ -691,7 +684,7 @@ static void mem_deinit_user_mapping(uvm_mem_t *mem) static NvU64 reserved_gpu_va(uvm_mem_t *mem, uvm_gpu_t *gpu) { - UVM_ASSERT(mem->kernel.range_alloc.aligned_start + mem->physical_allocation_size < gpu->parent->uvm_mem_va_size); + UVM_ASSERT(mem->kernel.range_alloc.aligned_start + uvm_mem_physical_size(mem) < gpu->parent->uvm_mem_va_size); return gpu->parent->uvm_mem_va_base + mem->kernel.range_alloc.aligned_start; } @@ -709,7 +702,7 @@ static struct page *mem_cpu_page(uvm_mem_t *mem, NvU64 offset) static NV_STATUS mem_map_cpu_to_sysmem_kernel(uvm_mem_t *mem) { struct page **pages = mem->sysmem.pages; - size_t num_pages = mem->physical_allocation_size / PAGE_SIZE; + size_t num_pages = uvm_mem_physical_size(mem) / PAGE_SIZE; pgprot_t prot = PAGE_KERNEL; UVM_ASSERT(uvm_mem_is_sysmem(mem)); @@ -743,7 +736,7 @@ static NV_STATUS mem_map_cpu_to_vidmem_kernel(uvm_mem_t *mem) { struct page **pages; size_t num_chunk_pages = mem->chunk_size / PAGE_SIZE; - size_t num_pages = mem->physical_allocation_size / PAGE_SIZE; + size_t num_pages = uvm_mem_physical_size(mem) / PAGE_SIZE; size_t page_index; size_t chunk_index; @@ -798,7 +791,7 @@ static NV_STATUS mem_map_cpu_to_sysmem_user(uvm_mem_t *mem, struct vm_area_struc // compound pages in order to be able to use vm_insert_page on them. This // is not currently being exercised because the only allocations using this // are semaphore pools (which typically use a single page). - for (offset = 0; offset < mem->physical_allocation_size; offset += PAGE_SIZE) { + for (offset = 0; offset < uvm_mem_physical_size(mem); offset += PAGE_SIZE) { int ret = vm_insert_page(vma, (unsigned long)mem->user->addr + offset, mem_cpu_page(mem, offset)); if (ret) { UVM_ASSERT_MSG(ret == -ENOMEM, "ret: %d\n", ret); @@ -810,7 +803,7 @@ static NV_STATUS mem_map_cpu_to_sysmem_user(uvm_mem_t *mem, struct vm_area_struc return NV_OK; error: - unmap_mapping_range(&mem->user->va_space->mapping, (size_t)mem->user->addr, mem->physical_allocation_size, 1); + unmap_mapping_range(mem->user->va_space->mapping, (size_t)mem->user->addr, uvm_mem_physical_size(mem), 1); return status; } @@ -819,7 +812,7 @@ void uvm_mem_unmap_cpu_user(uvm_mem_t *mem) if (!uvm_mem_mapped_on_cpu_user(mem)) return; - unmap_mapping_range(&mem->user->va_space->mapping, (size_t)mem->user->addr, mem->physical_allocation_size, 1); + unmap_mapping_range(mem->user->va_space->mapping, (size_t)mem->user->addr, uvm_mem_physical_size(mem), 1); mem_clear_mapped_on_cpu_user(mem); mem_deinit_user_mapping(mem); } @@ -959,21 +952,17 @@ static uvm_gpu_phys_address_t mem_gpu_physical_sysmem(uvm_mem_t *mem, uvm_gpu_t return uvm_gpu_phys_address(UVM_APERTURE_SYS, dma_addr + offset % mem->chunk_size); } -static bool mem_check_range(uvm_mem_t *mem, NvU64 offset, NvU64 size) +bool uvm_mem_is_physically_contiguous(uvm_mem_t *mem, NvU64 offset, NvU64 size) { UVM_ASSERT(size != 0); - UVM_ASSERT_MSG(UVM_ALIGN_DOWN(offset, mem->chunk_size) == UVM_ALIGN_DOWN(offset + size - 1, mem->chunk_size), - "offset %llu size %llu page_size %u\n", - offset, - size, - mem->chunk_size); - UVM_ASSERT_MSG(offset / mem->chunk_size < mem->chunks_count, "offset %llu\n", offset); - return true; + UVM_ASSERT((offset + size) <= uvm_mem_physical_size(mem)); + + return UVM_ALIGN_DOWN(offset, mem->chunk_size) == UVM_ALIGN_DOWN(offset + size - 1, mem->chunk_size); } uvm_gpu_phys_address_t uvm_mem_gpu_physical(uvm_mem_t *mem, uvm_gpu_t *gpu, NvU64 offset, NvU64 size) { - UVM_ASSERT(mem_check_range(mem, offset, size)); + UVM_ASSERT(uvm_mem_is_physically_contiguous(mem, offset, size)); if (uvm_mem_is_vidmem(mem)) { UVM_ASSERT(uvm_mem_is_local_vidmem(mem, gpu)); @@ -990,7 +979,7 @@ uvm_gpu_address_t uvm_mem_gpu_address_copy(uvm_mem_t *mem, uvm_gpu_t *accessing_ size_t chunk_offset; uvm_gpu_chunk_t *chunk; - UVM_ASSERT(mem_check_range(mem, offset, size)); + UVM_ASSERT(uvm_mem_is_physically_contiguous(mem, offset, size)); if (uvm_mem_is_sysmem(mem) || uvm_mem_is_local_vidmem(mem, accessing_gpu)) return uvm_mem_gpu_address_physical(mem, accessing_gpu, offset, size); @@ -1024,13 +1013,8 @@ static NvU64 mem_pte_maker(uvm_page_table_range_vec_t *range_vec, NvU64 offset, static void mem_unmap_gpu(uvm_mem_t *mem, uvm_gpu_t *gpu, uvm_page_table_range_vec_t **range_vec) { - NV_STATUS status; - uvm_membar_t tlb_membar = UVM_MEMBAR_SYS; - - if (uvm_mem_is_local_vidmem(mem, gpu)) - tlb_membar = UVM_MEMBAR_GPU; - - status = uvm_page_table_range_vec_clear_ptes(*range_vec, tlb_membar); + uvm_membar_t tlb_membar = uvm_hal_downgrade_membar_type(gpu, uvm_mem_is_local_vidmem(mem, gpu)); + NV_STATUS status = uvm_page_table_range_vec_clear_ptes(*range_vec, tlb_membar); if (status != NV_OK) UVM_ERR_PRINT("Clearing PTEs failed: %s, GPU %s\n", nvstatusToString(status), uvm_gpu_name(gpu)); @@ -1054,22 +1038,19 @@ static NV_STATUS mem_map_gpu(uvm_mem_t *mem, .attrs = attrs }; - if (!uvm_gpu_can_address(gpu, gpu_va, mem->size)) - return NV_ERR_OUT_OF_RANGE; - page_size = mem_pick_gpu_page_size(mem, gpu, tree); UVM_ASSERT_MSG(uvm_mmu_page_size_supported(tree, page_size), "page_size 0x%x\n", page_size); status = uvm_page_table_range_vec_create(tree, gpu_va, - mem->physical_allocation_size, + uvm_mem_physical_size(mem), page_size, pmm_flags, range_vec); if (status != NV_OK) { UVM_ERR_PRINT("Failed to init page mapping at [0x%llx, 0x%llx): %s, GPU %s\n", gpu_va, - gpu_va + mem->physical_allocation_size, + gpu_va + uvm_mem_physical_size(mem), nvstatusToString(status), uvm_gpu_name(gpu)); return status; @@ -1079,7 +1060,7 @@ static NV_STATUS mem_map_gpu(uvm_mem_t *mem, if (status != NV_OK) { UVM_ERR_PRINT("Failed to write PTEs for mapping at [0x%llx, 0x%llx): %s, GPU %s\n", gpu_va, - gpu_va + mem->physical_allocation_size, + gpu_va + uvm_mem_physical_size(mem), nvstatusToString(status), uvm_gpu_name(gpu)); goto error; @@ -1098,7 +1079,7 @@ static NV_STATUS mem_init_gpu_kernel_range(uvm_mem_t *mem) return NV_OK; return uvm_range_allocator_alloc(&g_free_ranges, - mem->physical_allocation_size, + uvm_mem_physical_size(mem), mem->chunk_size, &mem->kernel.range_alloc); } @@ -1139,7 +1120,7 @@ NV_STATUS uvm_mem_map_gpu_kernel(uvm_mem_t *mem, uvm_gpu_t *gpu) if (status != NV_OK) return status; - gpu_va = uvm_parent_gpu_canonical_address(gpu->parent, reserved_gpu_va(mem, gpu)); + gpu_va = reserved_gpu_va(mem, gpu); range_vec = &mem->kernel.range_vecs[uvm_global_id_gpu_index(gpu->global_id)]; status = mem_map_gpu(mem, gpu, gpu_va, &gpu->address_space_tree, &attrs, range_vec); @@ -1165,6 +1146,7 @@ NV_STATUS uvm_mem_map_gpu_user(uvm_mem_t *mem, NV_STATUS status; uvm_gpu_va_space_t *gpu_va_space; uvm_page_table_range_vec_t **range_vec; + NvU64 gpu_va; UVM_ASSERT(mem_can_be_mapped_on_gpu_user(mem, gpu)); uvm_assert_rwsem_locked(&user_va_space->lock); @@ -1172,6 +1154,10 @@ NV_STATUS uvm_mem_map_gpu_user(uvm_mem_t *mem, if (uvm_mem_mapped_on_gpu_user(mem, gpu)) return NV_OK; + gpu_va = (NvU64)user_addr; + if (!uvm_gpu_can_address(gpu, gpu_va, mem->size)) + return NV_ERR_OUT_OF_RANGE; + status = uvm_mem_map_gpu_phys(mem, gpu); if (status != NV_OK) return status; @@ -1183,7 +1169,7 @@ NV_STATUS uvm_mem_map_gpu_user(uvm_mem_t *mem, gpu_va_space = uvm_gpu_va_space_get(mem->user->va_space, gpu); range_vec = &mem->user->range_vecs[uvm_global_id_gpu_index(gpu->global_id)]; - status = mem_map_gpu(mem, gpu, (NvU64)mem->user->addr, &gpu_va_space->page_tables, attrs, range_vec); + status = mem_map_gpu(mem, gpu, gpu_va, &gpu_va_space->page_tables, attrs, range_vec); if (status != NV_OK) goto cleanup; diff --git a/kernel-open/nvidia-uvm/uvm_mem.h b/kernel-open/nvidia-uvm/uvm_mem.h index 361e70f45..7dba2f121 100644 --- a/kernel-open/nvidia-uvm/uvm_mem.h +++ b/kernel-open/nvidia-uvm/uvm_mem.h @@ -163,9 +163,6 @@ struct uvm_mem_struct uvm_gpu_t *dma_owner; - // Size of the physical chunks. - NvU32 chunk_size; - union { struct @@ -194,12 +191,12 @@ struct uvm_mem_struct // Count of chunks (vidmem) or CPU pages (sysmem) above size_t chunks_count; + // Size of each physical chunk (vidmem) or CPU page (sysmem) + NvU32 chunk_size; + // Size of the allocation NvU64 size; - // Size of the physical allocation backing - NvU64 physical_allocation_size; - uvm_mem_user_mapping_t *user; // Information specific to allocations mapped in UVM internal VA space. @@ -235,6 +232,20 @@ NV_STATUS uvm_mem_translate_gpu_attributes(const UvmGpuMappingAttributes *attrs, uvm_chunk_sizes_mask_t uvm_mem_kernel_chunk_sizes(uvm_gpu_t *gpu); +// Size of all the physical allocations backing the given memory. +static inline NvU64 uvm_mem_physical_size(const uvm_mem_t *mem) +{ + NvU64 physical_size = mem->chunks_count * mem->chunk_size; + + UVM_ASSERT(mem->size <= physical_size); + + return physical_size; +} + +// Returns true if the memory is physically contiguous in the +// [offset, offset + size) interval. +bool uvm_mem_is_physically_contiguous(uvm_mem_t *mem, NvU64 offset, NvU64 size); + // Allocate memory according to the given allocation parameters. // // In the case of sysmem, the memory is immediately physically accessible from diff --git a/kernel-open/nvidia-uvm/uvm_mem_test.c b/kernel-open/nvidia-uvm/uvm_mem_test.c index fcf1279e3..787063cf5 100644 --- a/kernel-open/nvidia-uvm/uvm_mem_test.c +++ b/kernel-open/nvidia-uvm/uvm_mem_test.c @@ -62,7 +62,7 @@ static NV_STATUS check_accessible_from_gpu(uvm_gpu_t *gpu, uvm_mem_t *mem) verif_size = UVM_ALIGN_UP(verif_size, sizeof(*sys_verif)); - UVM_ASSERT(mem->physical_allocation_size >= verif_size); + UVM_ASSERT(uvm_mem_physical_size(mem) >= verif_size); UVM_ASSERT(verif_size >= sizeof(*sys_verif)); TEST_NV_CHECK_GOTO(__alloc_map_sysmem(verif_size, gpu, &sys_mem), done); @@ -185,7 +185,7 @@ static NV_STATUS test_map_gpu(uvm_mem_t *mem, uvm_gpu_t *gpu) gpu_va = uvm_mem_get_gpu_va_kernel(mem, gpu); TEST_CHECK_RET(gpu_va >= gpu->parent->uvm_mem_va_base); - TEST_CHECK_RET(gpu_va + mem->physical_allocation_size <= gpu->parent->uvm_mem_va_base + gpu->parent->uvm_mem_va_size); + TEST_CHECK_RET(gpu_va + uvm_mem_physical_size(mem) <= gpu->parent->uvm_mem_va_base + gpu->parent->uvm_mem_va_size); // Mapping if already mapped is OK TEST_NV_CHECK_RET(uvm_mem_map_gpu_kernel(mem, gpu)); @@ -370,6 +370,7 @@ static NV_STATUS test_all(uvm_va_space_t *va_space) static const int max_supported_page_sizes = 4 + 1; int i; + gpu_count = uvm_processor_mask_get_gpu_count(&va_space->registered_gpus); // +1 for the CPU diff --git a/kernel-open/nvidia-uvm/uvm_migrate.c b/kernel-open/nvidia-uvm/uvm_migrate.c index 4ee87903e..1fb125df1 100644 --- a/kernel-open/nvidia-uvm/uvm_migrate.c +++ b/kernel-open/nvidia-uvm/uvm_migrate.c @@ -86,7 +86,8 @@ static NV_STATUS block_migrate_map_mapped_pages(uvm_va_block_t *va_block, // Only map those pages that are not already mapped on destination for_each_va_block_unset_page_in_region_mask(page_index, pages_mapped_on_destination, region) { prot = uvm_va_block_page_compute_highest_permission(va_block, dest_id, page_index); - UVM_ASSERT(prot != UVM_PROT_NONE); + if (prot == UVM_PROT_NONE) + continue; if (va_block_context->mask_by_prot[prot - 1].count++ == 0) uvm_page_mask_zero(&va_block_context->mask_by_prot[prot - 1].page_mask); @@ -206,28 +207,39 @@ NV_STATUS uvm_va_block_migrate_locked(uvm_va_block_t *va_block, NV_STATUS status, tracker_status = NV_OK; uvm_assert_mutex_locked(&va_block->lock); + UVM_ASSERT(uvm_hmm_check_context_vma_is_valid(va_block, va_block_context, region)); - va_block_context->policy = uvm_va_range_get_policy(va_block->va_range); - - if (uvm_va_policy_is_read_duplicate(va_block_context->policy, va_space)) { - status = uvm_va_block_make_resident_read_duplicate(va_block, - va_block_retry, - va_block_context, - dest_id, - region, - NULL, - NULL, - UVM_MAKE_RESIDENT_CAUSE_API_MIGRATE); + if (uvm_va_block_is_hmm(va_block)) { + status = uvm_hmm_va_block_migrate_locked(va_block, + va_block_retry, + va_block_context, + dest_id, + region, + UVM_MAKE_RESIDENT_CAUSE_API_MIGRATE); } else { - status = uvm_va_block_make_resident(va_block, - va_block_retry, - va_block_context, - dest_id, - region, - NULL, - NULL, - UVM_MAKE_RESIDENT_CAUSE_API_MIGRATE); + va_block_context->policy = uvm_va_range_get_policy(va_block->va_range); + + if (uvm_va_policy_is_read_duplicate(va_block_context->policy, va_space)) { + status = uvm_va_block_make_resident_read_duplicate(va_block, + va_block_retry, + va_block_context, + dest_id, + region, + NULL, + NULL, + UVM_MAKE_RESIDENT_CAUSE_API_MIGRATE); + } + else { + status = uvm_va_block_make_resident(va_block, + va_block_retry, + va_block_context, + dest_id, + region, + NULL, + NULL, + UVM_MAKE_RESIDENT_CAUSE_API_MIGRATE); + } } if (status == NV_OK && mode == UVM_MIGRATE_MODE_MAKE_RESIDENT_AND_MAP) { @@ -316,7 +328,8 @@ static bool migration_should_do_cpu_preunmap(uvm_va_space_t *va_space, // read-duplication is enabled in the VA range. This is because, when migrating // read-duplicated VA blocks, the source processor doesn't need to be unmapped // (though it may need write access revoked). -static bool va_range_should_do_cpu_preunmap(uvm_va_policy_t *policy, uvm_va_space_t *va_space) +static bool va_range_should_do_cpu_preunmap(const uvm_va_policy_t *policy, + uvm_va_space_t *va_space) { return !uvm_va_policy_is_read_duplicate(policy, va_space); } @@ -406,7 +419,7 @@ static void preunmap_multi_block(uvm_va_range_t *va_range, } if (num_unmap_pages > 0) - unmap_mapping_range(&va_range->va_space->mapping, start, end - start + 1, 1); + unmap_mapping_range(va_range->va_space->mapping, start, end - start + 1, 1); } static NV_STATUS uvm_va_range_migrate_multi_block(uvm_va_range_t *va_range, @@ -524,6 +537,17 @@ static NV_STATUS uvm_migrate_ranges(uvm_va_space_t *va_space, NV_STATUS status = NV_OK; bool skipped_migrate = false; + if (!first_va_range) { + // For HMM, we iterate over va_blocks since there is no va_range. + return uvm_hmm_migrate_ranges(va_space, + va_block_context, + base, + length, + dest_id, + mode, + out_tracker); + } + UVM_ASSERT(first_va_range == uvm_va_space_iter_first(va_space, base, base)); va_range_last = NULL; @@ -594,10 +618,10 @@ static NV_STATUS uvm_migrate(uvm_va_space_t *va_space, NvU64 length, uvm_processor_id_t dest_id, NvU32 migrate_flags, + uvm_va_range_t *first_va_range, uvm_tracker_t *out_tracker) { NV_STATUS status = NV_OK; - uvm_va_range_t *first_va_range = uvm_va_space_iter_first(va_space, base, base); uvm_va_block_context_t *va_block_context; bool do_mappings; bool do_two_passes; @@ -606,9 +630,6 @@ static NV_STATUS uvm_migrate(uvm_va_space_t *va_space, uvm_assert_rwsem_locked(&va_space->lock); - if (!first_va_range || first_va_range->type != UVM_VA_RANGE_TYPE_MANAGED) - return NV_ERR_INVALID_ADDRESS; - // If the GPU has its memory disabled, just skip the migration and let // faults take care of things. if (!uvm_va_space_processor_has_memory(va_space, dest_id)) @@ -616,6 +637,7 @@ static NV_STATUS uvm_migrate(uvm_va_space_t *va_space, if (mm) uvm_assert_mmap_lock_locked(mm); + va_block_context = uvm_va_block_context_alloc(mm); if (!va_block_context) return NV_ERR_NO_MEMORY; @@ -638,7 +660,9 @@ static NV_STATUS uvm_migrate(uvm_va_space_t *va_space, // 1- Transfer all VA blocks (do not add mappings) // 2- Go block by block reexecuting the transfer (in case someone moved it // since the first pass), and adding the mappings. - is_single_block = is_migration_single_block(first_va_range, base, length); + // + // For HMM (!first_va_range), we always do a single pass. + is_single_block = !first_va_range || is_migration_single_block(first_va_range, base, length); do_mappings = UVM_ID_IS_GPU(dest_id) || !(migrate_flags & UVM_MIGRATE_FLAG_SKIP_CPU_MAP); do_two_passes = do_mappings && !is_single_block; @@ -854,6 +878,7 @@ NV_STATUS uvm_api_migrate(UVM_MIGRATE_PARAMS *params, struct file *filp) if ((params->flags & UVM_MIGRATE_FLAGS_TEST_ALL) && !uvm_enable_builtin_tests) { UVM_INFO_PRINT("Test flag set for UVM_MIGRATE. Did you mean to insmod with uvm_enable_builtin_tests=1?\n"); + UVM_INFO_PRINT("TEMP\n"); return NV_ERR_INVALID_ARGUMENT; } @@ -916,6 +941,9 @@ NV_STATUS uvm_api_migrate(UVM_MIGRATE_PARAMS *params, struct file *filp) params->length, (dest_gpu ? dest_gpu->id : UVM_ID_CPU), params->flags, + uvm_va_space_iter_first(va_space, + params->base, + params->base), tracker_ptr); } else if (status == NV_WARN_NOTHING_TO_DO) { @@ -1029,10 +1057,26 @@ NV_STATUS uvm_api_migrate_range_group(UVM_MIGRATE_RANGE_GROUP_PARAMS *params, st NvU64 start = rgr->node.start; NvU64 length = rgr->node.end - rgr->node.start + 1; - if (gpu && !uvm_gpu_can_address(gpu, start, length)) + if (gpu && !uvm_gpu_can_address(gpu, start, length)) { status = NV_ERR_OUT_OF_RANGE; - else - status = uvm_migrate(va_space, mm, start, length, dest_id, migrate_flags, &local_tracker); + } + else { + uvm_va_range_t *first_va_range = uvm_va_space_iter_first(va_space, start, start); + + if (!first_va_range || first_va_range->type != UVM_VA_RANGE_TYPE_MANAGED) { + status = NV_ERR_INVALID_ADDRESS; + goto done; + } + + status = uvm_migrate(va_space, + mm, + start, + length, + dest_id, + migrate_flags, + first_va_range, + &local_tracker); + } if (status != NV_OK) goto done; diff --git a/kernel-open/nvidia-uvm/uvm_mmu.c b/kernel-open/nvidia-uvm/uvm_mmu.c index db4785e1b..50b8b627c 100644 --- a/kernel-open/nvidia-uvm/uvm_mmu.c +++ b/kernel-open/nvidia-uvm/uvm_mmu.c @@ -727,16 +727,19 @@ error: // static void page_tree_set_location(uvm_page_tree_t *tree, uvm_aperture_t location) { + bool should_location_be_vidmem; UVM_ASSERT(tree->gpu != NULL); UVM_ASSERT_MSG((location == UVM_APERTURE_VID) || (location == UVM_APERTURE_SYS) || (location == UVM_APERTURE_DEFAULT), "Invalid location %s (%d)\n", uvm_aperture_string(location), (int)location); - // The tree must be explicitly initialized in vidmem when in SR-IOV heavy. - // The only exception are "fake" GPUs used during page tree testing, which - // can be identified by having no channel manager. - if ((tree->gpu->channel_manager != NULL) && uvm_gpu_is_virt_mode_sriov_heavy(tree->gpu)) + should_location_be_vidmem = uvm_gpu_is_virt_mode_sriov_heavy(tree->gpu); + + // The page tree of a "fake" GPU used during page tree testing can be in + // sysmem even if should_location_be_vidmem is true. A fake GPU can be + // identified by having no channel manager. + if ((tree->gpu->channel_manager != NULL) && should_location_be_vidmem) UVM_ASSERT(location == UVM_APERTURE_VID); if (location == UVM_APERTURE_DEFAULT) { @@ -874,6 +877,7 @@ void uvm_page_tree_put_ptes_async(uvm_page_tree_t *tree, uvm_page_table_range_t // traverse until we hit an in-use page, or the root while (dir->host_parent != NULL && dir->ref_count == 0) { uvm_page_directory_t *parent = dir->host_parent; + uvm_membar_t this_membar; if (free_count == 0) { @@ -902,10 +906,9 @@ void uvm_page_tree_put_ptes_async(uvm_page_tree_t *tree, uvm_page_table_range_t invalidate_depth = dir->host_parent->depth; - // If any of the pointed to PDEs were in sysmem then a SYS membar is - // required after the TLB invalidate. - if (dir->phys_alloc.addr.aperture == UVM_APERTURE_SYS) - membar_after_invalidate = UVM_MEMBAR_SYS; + // Take the membar with the widest scope of any of the pointed-to PDEs + this_membar = uvm_hal_downgrade_membar_type(tree->gpu, dir->phys_alloc.addr.aperture == UVM_APERTURE_VID); + membar_after_invalidate = max(membar_after_invalidate, this_membar); // If any of the cleared PDEs were in sysmem then a SYS membar is // required after the clears and before the TLB invalidate. @@ -978,7 +981,8 @@ static NV_STATUS try_get_ptes(uvm_page_tree_t *tree, { uvm_mmu_mode_hal_t *hal = tree->hal; - // bit index just beyond the most significant bit used to index the current entry + // bit index just beyond the most significant bit used to index the current + // entry NvU32 addr_bit_shift = hal->num_va_bits(); // track depth upon which the invalidate occured @@ -997,19 +1001,28 @@ static NV_STATUS try_get_ptes(uvm_page_tree_t *tree, // ensure that the caller has specified a valid page size UVM_ASSERT((page_size & hal->page_sizes()) != 0); - // This algorithm will work with unaligned ranges, but the caller's intent is unclear - UVM_ASSERT_MSG(start % page_size == 0 && size % page_size == 0, "start 0x%llx size 0x%zx page_size 0x%x", - start, (size_t)size, page_size); + // This algorithm will work with unaligned ranges, but the caller's intent + // is unclear + UVM_ASSERT_MSG(start % page_size == 0 && size % page_size == 0, + "start 0x%llx size 0x%zx page_size 0x%x\n", + start, + (size_t)size, + page_size); // The GPU should be capable of addressing the passed range - UVM_ASSERT(uvm_gpu_can_address(tree->gpu, start, size)); + if (tree->type == UVM_PAGE_TREE_TYPE_USER) + UVM_ASSERT(uvm_gpu_can_address(tree->gpu, start, size)); + else + UVM_ASSERT(uvm_gpu_can_address_kernel(tree->gpu, start, size)); while (true) { - // index of the entry, for the first byte of the range, within its containing directory + // index of the entry, for the first byte of the range, within its + // containing directory NvU32 start_index; - // index of the entry, for the last byte of the range, within its containing directory + // index of the entry, for the last byte of the range, within its + // containing directory NvU32 end_index; // pointer to PDE/PTE @@ -2280,9 +2293,9 @@ static NV_STATUS create_dynamic_sysmem_mapping(uvm_gpu_t *gpu) UVM_ASSERT(gpu->parent->flat_sysmem_va_base != 0); // The DMA addressable window is the maximum system physical memory - // addressable by the GPU (this limit is 128TB in Pascal-Ampere). The - // virtual mapping to sysmem is linear, so its size matches that of the - // physical address space. + // addressable by the GPU (this limit is 128TB in Pascal-Ada). The virtual + // mapping to sysmem is linear, so its size matches that of the physical + // address space. flat_sysmem_va_size = gpu->parent->dma_addressable_limit + 1 - gpu->parent->dma_addressable_start; // The optimal mapping granularity is dependent on multiple factors: @@ -2351,7 +2364,7 @@ NV_STATUS uvm_mmu_sysmem_map(uvm_gpu_t *gpu, NvU64 pa, NvU64 size) // because in the common case the VA block lock is held. pmm_flags = UVM_PMM_ALLOC_FLAGS_NONE; - sysmem_mapping->base = uvm_parent_gpu_canonical_address(gpu->parent, virtual_address.address); + sysmem_mapping->base = virtual_address.address; status = create_identity_mapping(gpu, sysmem_mapping->base, diff --git a/kernel-open/nvidia-uvm/uvm_mmu.h b/kernel-open/nvidia-uvm/uvm_mmu.h index 8e80ab68f..1935b4cc5 100644 --- a/kernel-open/nvidia-uvm/uvm_mmu.h +++ b/kernel-open/nvidia-uvm/uvm_mmu.h @@ -36,7 +36,9 @@ #define UVM_PAGE_SIZE_AGNOSTIC 0 // Memory layout of UVM's kernel VA space. -// The following memory regions are not to scale. +// The following memory regions are not to scale. The memory layout is linear, +// i.e., no canonical form address conversion. +// // Hopper: // +----------------+ 128PB // | | @@ -57,7 +59,7 @@ // | | // +----------------+ 0 (rm_va_base) // -// Pascal-Ampere: +// Pascal-Ada: // +----------------+ 512TB // | | // | (not used) | @@ -592,13 +594,18 @@ static bool uvm_mmu_page_size_supported(uvm_page_tree_t *tree, NvU32 page_size) static NvU32 uvm_mmu_biggest_page_size_up_to(uvm_page_tree_t *tree, NvU32 max_page_size) { + NvU32 gpu_page_sizes = tree->hal->page_sizes(); + NvU32 smallest_gpu_page_size = gpu_page_sizes & ~(gpu_page_sizes - 1); NvU32 page_sizes; NvU32 page_size; UVM_ASSERT_MSG(is_power_of_2(max_page_size), "0x%x\n", max_page_size); + if (max_page_size < smallest_gpu_page_size) + return 0; + // Calculate the supported page sizes that are not larger than the max - page_sizes = tree->hal->page_sizes() & (max_page_size | (max_page_size - 1)); + page_sizes = gpu_page_sizes & (max_page_size | (max_page_size - 1)); // And pick the biggest one of them page_size = 1 << __fls(page_sizes); diff --git a/kernel-open/nvidia-uvm/uvm_page_tree_test.c b/kernel-open/nvidia-uvm/uvm_page_tree_test.c index 1e5e81ecb..5b5dedf5d 100644 --- a/kernel-open/nvidia-uvm/uvm_page_tree_test.c +++ b/kernel-open/nvidia-uvm/uvm_page_tree_test.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2021 NVIDIA Corporation + Copyright (c) 2015-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -305,18 +305,25 @@ static NV_STATUS test_page_tree_init(uvm_gpu_t *gpu, NvU32 big_page_size, uvm_pa return uvm_page_tree_init(gpu, NULL, UVM_PAGE_TREE_TYPE_USER, big_page_size, UVM_APERTURE_SYS, tree); } +static NV_STATUS test_page_tree_init_kernel(uvm_gpu_t *gpu, NvU32 big_page_size, uvm_page_tree_t *tree) +{ + return uvm_page_tree_init(gpu, NULL, UVM_PAGE_TREE_TYPE_KERNEL, big_page_size, UVM_APERTURE_SYS, tree); +} + static NV_STATUS test_page_tree_get_ptes(uvm_page_tree_t *tree, NvU32 page_size, NvU64 start, NvLength size, uvm_page_table_range_t *range) { - return uvm_page_tree_get_ptes(tree, - page_size, - uvm_parent_gpu_canonical_address(tree->gpu->parent, start), - size, - UVM_PMM_ALLOC_FLAGS_NONE, - range); + uvm_mmu_mode_hal_t *hal = tree->gpu->parent->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_64K); + + // Maxwell GPUs don't use canonical form address even on platforms that + // support it. + start = (tree->type == UVM_PAGE_TREE_TYPE_USER) && (hal->num_va_bits() > 40) ? + uvm_parent_gpu_canonical_address(tree->gpu->parent, start) : + start; + return uvm_page_tree_get_ptes(tree, page_size, start, size, UVM_PMM_ALLOC_FLAGS_NONE, range); } static NV_STATUS test_page_tree_get_entry(uvm_page_tree_t *tree, @@ -324,11 +331,13 @@ static NV_STATUS test_page_tree_get_entry(uvm_page_tree_t *tree, NvU64 start, uvm_page_table_range_t *single) { - return uvm_page_tree_get_entry(tree, - page_size, - uvm_parent_gpu_canonical_address(tree->gpu->parent, start), - UVM_PMM_ALLOC_FLAGS_NONE, - single); + uvm_mmu_mode_hal_t *hal = tree->gpu->parent->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_64K); + + // See comment above (test_page_tree_get_ptes) + start = (tree->type == UVM_PAGE_TREE_TYPE_USER) && (hal->num_va_bits() > 40) ? + uvm_parent_gpu_canonical_address(tree->gpu->parent, start) : + start; + return uvm_page_tree_get_entry(tree, page_size, start, UVM_PMM_ALLOC_FLAGS_NONE, single); } static NV_STATUS test_page_tree_alloc_table(uvm_page_tree_t *tree, @@ -411,7 +420,10 @@ static NV_STATUS alloc_64k_memory_57b_va(uvm_gpu_t *gpu) uvm_page_table_range_t range; NvLength size = 64 * 1024; - MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); + + // We use a kernel-type page tree to decouple the test from the CPU VA width + // and canonical form address limits. + MEM_NV_CHECK_RET(test_page_tree_init_kernel(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); MEM_NV_CHECK_RET(test_page_tree_get_ptes(&tree, UVM_PAGE_SIZE_64K, 0x100000000000000ULL, size, &range), NV_OK); TEST_CHECK_RET(range.entry_count == 1); TEST_CHECK_RET(range.table->depth == 5); @@ -532,7 +544,7 @@ static NV_STATUS allocate_then_free_8_8_64k(uvm_gpu_t *gpu) NvLength start = stride * 248 + 256LL * 1024 * 1024 * 1024 + (1LL << 47); int i; - MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); + MEM_NV_CHECK_RET(test_page_tree_init_kernel(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); for (i = 0; i < 16; i++) MEM_NV_CHECK_RET(test_page_tree_get_ptes(&tree, UVM_PAGE_SIZE_64K, start + i * stride, size, range + i), NV_OK); @@ -652,7 +664,7 @@ static NV_STATUS get_entire_table_4k(uvm_gpu_t *gpu) NvLength size = 1 << 21; - MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); + MEM_NV_CHECK_RET(test_page_tree_init_kernel(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); MEM_NV_CHECK_RET(test_page_tree_get_ptes(&tree, UVM_PAGE_SIZE_4K, start, size, &range), NV_OK); TEST_CHECK_RET(range.table == tree.root->entries[1]->entries[0]->entries[0]->entries[1]); @@ -672,13 +684,13 @@ static NV_STATUS get_entire_table_512m(uvm_gpu_t *gpu) uvm_page_tree_t tree; uvm_page_table_range_t range; - NvU64 start = 1UL << 47; + NvU64 start = 1UL << 48; NvLength size = 512UL * 512 * 1024 * 1024; - MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); + MEM_NV_CHECK_RET(test_page_tree_init_kernel(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); MEM_NV_CHECK_RET(test_page_tree_get_ptes(&tree, UVM_PAGE_SIZE_512M, start, size, &range), NV_OK); - TEST_CHECK_RET(range.table == tree.root->entries[1]->entries[0]); + TEST_CHECK_RET(range.table == tree.root->entries[2]->entries[0]); TEST_CHECK_RET(range.entry_count == 512); TEST_CHECK_RET(range.table->depth == 2); TEST_CHECK_RET(range.page_size == UVM_PAGE_SIZE_512M); @@ -701,7 +713,7 @@ static NV_STATUS split_4k_from_2m(uvm_gpu_t *gpu) NvU64 start = 1UL << 48; NvLength size = 1 << 21; - MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); + MEM_NV_CHECK_RET(test_page_tree_init_kernel(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); MEM_NV_CHECK_RET(test_page_tree_get_ptes(&tree, UVM_PAGE_SIZE_2M, start, size, &range_2m), NV_OK); MEM_NV_CHECK_RET(test_page_tree_get_ptes(&tree, UVM_PAGE_SIZE_2M, start + size, size, &range_adj), NV_OK); @@ -749,7 +761,7 @@ static NV_STATUS split_2m_from_512m(uvm_gpu_t *gpu) NvU64 start = 1UL << 48; NvLength size = 512UL * 1024 * 1024; - MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); + MEM_NV_CHECK_RET(test_page_tree_init_kernel(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); MEM_NV_CHECK_RET(test_page_tree_get_ptes(&tree, UVM_PAGE_SIZE_512M, start, size, &range_512m), NV_OK); MEM_NV_CHECK_RET(test_page_tree_get_ptes(&tree, UVM_PAGE_SIZE_512M, start + size, size, &range_adj), NV_OK); @@ -1025,7 +1037,7 @@ static NV_STATUS test_tlb_invalidates(uvm_gpu_t *gpu) // Depth 1 NvU64 extent_pde2 = extent_pde1 * (1ull << 9); - MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); + MEM_NV_CHECK_RET(test_page_tree_init_kernel(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK); fake_tlb_invals_enable(); @@ -1270,7 +1282,7 @@ static NV_STATUS test_range_vec(uvm_gpu_t *gpu, NvU32 big_page_size, NvU32 page_ NvU32 i; NvU64 offsets[4]; - MEM_NV_CHECK_RET(test_page_tree_init(gpu, big_page_size, &tree), NV_OK); + MEM_NV_CHECK_RET(test_page_tree_init_kernel(gpu, big_page_size, &tree), NV_OK); pde_coverage = uvm_mmu_pde_coverage(&tree, page_size); page_table_entries = pde_coverage / page_size; diff --git a/kernel-open/nvidia-uvm/uvm_pascal_ce.c b/kernel-open/nvidia-uvm/uvm_pascal_ce.c index 369afbd5e..d8db4476c 100644 --- a/kernel-open/nvidia-uvm/uvm_pascal_ce.c +++ b/kernel-open/nvidia-uvm/uvm_pascal_ce.c @@ -39,32 +39,6 @@ void uvm_hal_pascal_ce_offset_in_out(uvm_push_t *push, NvU64 offset_in, NvU64 of OFFSET_OUT_LOWER, HWVALUE(C0B5, OFFSET_OUT_LOWER, VALUE, NvOffset_LO32(offset_out))); } -// Perform an appropriate membar before a semaphore operation. Returns whether -// the semaphore operation should include a flush. -static bool pascal_membar_before_semaphore(uvm_push_t *push) -{ - uvm_gpu_t *gpu; - - if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE)) { - // No MEMBAR requested, don't use a flush. - return false; - } - - if (!uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU)) { - // By default do a MEMBAR SYS and for that we can just use flush on the - // semaphore operation. - return true; - } - - // MEMBAR GPU requested, do it on the HOST and skip the CE flush as CE - // doesn't have this capability. - gpu = uvm_push_get_gpu(push); - gpu->parent->host_hal->wait_for_idle(push); - gpu->parent->host_hal->membar_gpu(push); - - return false; -} - void uvm_hal_pascal_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload) { uvm_gpu_t *gpu = uvm_push_get_gpu(push); @@ -72,7 +46,7 @@ void uvm_hal_pascal_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 p NvU32 launch_dma_plc_mode; bool use_flush; - use_flush = pascal_membar_before_semaphore(push); + use_flush = uvm_hal_membar_before_semaphore(push); if (use_flush) flush_value = HWCONST(C0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE); @@ -98,7 +72,7 @@ void uvm_hal_pascal_ce_semaphore_reduction_inc(uvm_push_t *push, NvU64 gpu_va, N NvU32 launch_dma_plc_mode; bool use_flush; - use_flush = pascal_membar_before_semaphore(push); + use_flush = uvm_hal_membar_before_semaphore(push); if (use_flush) flush_value = HWCONST(C0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE); @@ -127,7 +101,7 @@ void uvm_hal_pascal_ce_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va) NvU32 launch_dma_plc_mode; bool use_flush; - use_flush = pascal_membar_before_semaphore(push); + use_flush = uvm_hal_membar_before_semaphore(push); if (use_flush) flush_value = HWCONST(C0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE); diff --git a/kernel-open/nvidia-uvm/uvm_perf_events.h b/kernel-open/nvidia-uvm/uvm_perf_events.h index 9179d6cb8..43e0047eb 100644 --- a/kernel-open/nvidia-uvm/uvm_perf_events.h +++ b/kernel-open/nvidia-uvm/uvm_perf_events.h @@ -54,6 +54,9 @@ typedef enum // Locking: uvm_va_space: write UVM_PERF_EVENT_BLOCK_SHRINK, + // Locking: HMM uvm_va_block lock + UVM_PERF_EVENT_BLOCK_MUNMAP, + // Locking: uvm_va_space: write UVM_PERF_EVENT_RANGE_DESTROY, @@ -89,6 +92,12 @@ typedef union uvm_va_block_t *block; } block_shrink; + struct + { + uvm_va_block_t *block; + uvm_va_block_region_t region; + } block_munmap; + struct { uvm_va_range_t *range; diff --git a/kernel-open/nvidia-uvm/uvm_perf_prefetch.c b/kernel-open/nvidia-uvm/uvm_perf_prefetch.c index 106620f77..4af9c126f 100644 --- a/kernel-open/nvidia-uvm/uvm_perf_prefetch.c +++ b/kernel-open/nvidia-uvm/uvm_perf_prefetch.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2022 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -236,7 +236,7 @@ static NvU32 uvm_perf_prefetch_prenotify_fault_migrations(uvm_va_block_t *va_blo const uvm_page_mask_t *resident_mask = NULL; const uvm_page_mask_t *thrashing_pages = NULL; uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); - uvm_va_policy_t *policy = va_block_context->policy; + const uvm_va_policy_t *policy = va_block_context->policy; uvm_va_block_region_t max_prefetch_region; NvU32 big_page_size; uvm_va_block_region_t big_pages_region; @@ -372,7 +372,7 @@ void uvm_perf_prefetch_get_hint(uvm_va_block_t *va_block, uvm_perf_prefetch_bitmap_tree_t *bitmap_tree, uvm_perf_prefetch_hint_t *out_hint) { - uvm_va_policy_t *policy = va_block_context->policy; + const uvm_va_policy_t *policy = va_block_context->policy; uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); uvm_page_mask_t *prefetch_pages = &out_hint->prefetch_pages_mask; NvU32 pending_prefetch_pages; @@ -380,9 +380,10 @@ void uvm_perf_prefetch_get_hint(uvm_va_block_t *va_block, uvm_assert_rwsem_locked(&va_space->lock); uvm_assert_mutex_locked(&va_block->lock); UVM_ASSERT(uvm_va_block_check_policy_is_valid(va_block, policy, faulted_region)); - UVM_ASSERT(uvm_hmm_va_block_context_vma_is_valid(va_block, va_block_context, faulted_region)); + UVM_ASSERT(uvm_hmm_check_context_vma_is_valid(va_block, va_block_context, faulted_region)); out_hint->residency = UVM_ID_INVALID; + uvm_page_mask_zero(prefetch_pages); if (!g_uvm_perf_prefetch_enable) return; diff --git a/kernel-open/nvidia-uvm/uvm_perf_thrashing.c b/kernel-open/nvidia-uvm/uvm_perf_thrashing.c index 57a80ddab..0aae1817c 100644 --- a/kernel-open/nvidia-uvm/uvm_perf_thrashing.c +++ b/kernel-open/nvidia-uvm/uvm_perf_thrashing.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2022 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -398,11 +398,13 @@ static uvm_perf_module_t g_module_thrashing; // Callback declaration for the performance heuristics events static void thrashing_event_cb(uvm_perf_event_t event_id, uvm_perf_event_data_t *event_data); static void thrashing_block_destroy_cb(uvm_perf_event_t event_id, uvm_perf_event_data_t *event_data); +static void thrashing_block_munmap_cb(uvm_perf_event_t event_id, uvm_perf_event_data_t *event_data); static uvm_perf_module_event_callback_desc_t g_callbacks_thrashing[] = { { UVM_PERF_EVENT_BLOCK_DESTROY, thrashing_block_destroy_cb }, { UVM_PERF_EVENT_MODULE_UNLOAD, thrashing_block_destroy_cb }, { UVM_PERF_EVENT_BLOCK_SHRINK , thrashing_block_destroy_cb }, + { UVM_PERF_EVENT_BLOCK_MUNMAP , thrashing_block_munmap_cb }, { UVM_PERF_EVENT_MIGRATION, thrashing_event_cb }, { UVM_PERF_EVENT_REVOCATION, thrashing_event_cb } }; @@ -533,7 +535,7 @@ static void gpu_thrashing_stats_destroy(uvm_gpu_t *gpu) // VA space lock needs to be held static va_space_thrashing_info_t *va_space_thrashing_info_get_or_null(uvm_va_space_t *va_space) { - uvm_assert_rwsem_locked(&va_space->lock); + // TODO: Bug 3898454: check locking requirement for UVM-HMM. return uvm_perf_module_type_data(va_space->perf_modules_data, UVM_PERF_MODULE_TYPE_THRASHING); } @@ -689,6 +691,20 @@ void thrashing_block_destroy_cb(uvm_perf_event_t event_id, uvm_perf_event_data_t uvm_perf_thrashing_info_destroy(va_block); } +void thrashing_block_munmap_cb(uvm_perf_event_t event_id, uvm_perf_event_data_t *event_data) +{ + uvm_va_block_t *va_block = event_data->block_munmap.block; + uvm_va_block_region_t region = event_data->block_munmap.region; + + UVM_ASSERT(g_uvm_perf_thrashing_enable); + UVM_ASSERT(event_id == UVM_PERF_EVENT_BLOCK_MUNMAP); + UVM_ASSERT(va_block); + + thrashing_reset_pages_in_region(va_block, + uvm_va_block_region_start(va_block, region), + uvm_va_block_region_size(region)); +} + // Sanity checks of the thrashing tracking state static bool thrashing_state_checks(uvm_va_block_t *va_block, block_thrashing_info_t *block_thrashing, @@ -1075,7 +1091,7 @@ static NV_STATUS unmap_remote_pinned_pages(uvm_va_block_t *va_block, NV_STATUS tracker_status; uvm_tracker_t local_tracker = UVM_TRACKER_INIT(); uvm_processor_id_t processor_id; - uvm_va_policy_t *policy = va_block_context->policy; + const uvm_va_policy_t *policy = va_block_context->policy; uvm_assert_mutex_locked(&va_block->lock); @@ -1121,7 +1137,7 @@ NV_STATUS uvm_perf_thrashing_unmap_remote_pinned_pages_all(uvm_va_block_t *va_bl { block_thrashing_info_t *block_thrashing; uvm_processor_mask_t unmap_processors; - uvm_va_policy_t *policy = va_block_context->policy; + const uvm_va_policy_t *policy = va_block_context->policy; uvm_assert_mutex_locked(&va_block->lock); UVM_ASSERT(uvm_va_block_check_policy_is_valid(va_block, policy, region)); @@ -1425,7 +1441,7 @@ static uvm_perf_thrashing_hint_t get_hint_for_migration_thrashing(va_space_thras uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); uvm_processor_id_t do_not_throttle_processor = page_thrashing->do_not_throttle_processor_id; uvm_processor_id_t pinned_residency = page_thrashing->pinned_residency_id; - uvm_va_policy_t *policy; + const uvm_va_policy_t *policy; uvm_processor_id_t preferred_location; policy = uvm_va_policy_get(va_block, uvm_va_block_cpu_page_address(va_block, page_index)); @@ -1519,8 +1535,9 @@ static uvm_perf_thrashing_hint_t get_hint_for_migration_thrashing(va_space_thras } } } - else if (uvm_processor_mask_test(&va_space->accessible_from[uvm_id_value(page_thrashing->pinned_residency_id)], requester)) { - UVM_ASSERT(uvm_id_equal(closest_resident_id, pinned_residency)); + else if (uvm_processor_mask_test(&va_space->accessible_from[uvm_id_value(pinned_residency)], requester)) { + if (!uvm_va_block_is_hmm(va_block)) + UVM_ASSERT(uvm_id_equal(closest_resident_id, pinned_residency)); hint.type = UVM_PERF_THRASHING_HINT_TYPE_PIN; hint.pin.residency = pinned_residency; @@ -1790,8 +1807,6 @@ static void thrashing_unpin_pages(struct work_struct *work) uvm_va_space_t *va_space = va_space_thrashing->va_space; uvm_va_block_context_t *va_block_context = &va_space_thrashing->pinned_pages.va_block_context; - UVM_ASSERT(uvm_va_space_initialized(va_space) == NV_OK); - // Take the VA space lock so that VA blocks don't go away during this // operation. uvm_va_space_down_read(va_space); diff --git a/kernel-open/nvidia-uvm/uvm_pmm_gpu.c b/kernel-open/nvidia-uvm/uvm_pmm_gpu.c index b50297563..511430256 100644 --- a/kernel-open/nvidia-uvm/uvm_pmm_gpu.c +++ b/kernel-open/nvidia-uvm/uvm_pmm_gpu.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -100,10 +100,10 @@ // All allocated user memory root chunks are tracked in an LRU list // (root_chunks.va_block_used). A root chunk is moved to the tail of that list // whenever any of its subchunks is allocated (unpinned) by a VA block (see -// uvm_pmm_gpu_unpin_temp()). When a root chunk is selected for eviction, it has -// the eviction flag set (see pick_root_chunk_to_evict()). This flag affects -// many of the PMM operations on all of the subchunks of the root chunk being -// evicted. See usage of (root_)chunk_is_in_eviction(), in particular in +// uvm_pmm_gpu_unpin_allocated()). When a root chunk is selected for eviction, +// it has the eviction flag set (see pick_root_chunk_to_evict()). This flag +// affects many of the PMM operations on all of the subchunks of the root chunk +// being evicted. See usage of (root_)chunk_is_in_eviction(), in particular in // chunk_free_locked() and claim_free_chunk(). // // To evict a root chunk, all of its free subchunks are pinned, then all @@ -394,7 +394,8 @@ static bool chunk_is_root_chunk_pinned(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chun return chunk->suballoc->pinned_leaf_chunks > 0; } -// Pin a chunk and update its root chunk's pinned leaf chunks count if the chunk is not a root chunk +// Pin a chunk and update its root chunk's pinned leaf chunks count if the +// chunk is not a root chunk. static void chunk_pin(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk) { uvm_gpu_root_chunk_t *root_chunk = root_chunk_from_chunk(pmm, chunk); @@ -406,17 +407,20 @@ static void chunk_pin(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk) if (chunk_is_root_chunk(chunk)) return; - // For subchunks, update the pinned leaf chunks count tracked in the suballoc of the root chunk. + // For subchunks, update the pinned leaf chunks count tracked in the + // suballoc of the root chunk. chunk = &root_chunk->chunk; - // The passed-in subchunk is not the root chunk so the root chunk has to be split + // The passed-in subchunk is not the root chunk so the root chunk has to be + // split. UVM_ASSERT_MSG(chunk->state == UVM_PMM_GPU_CHUNK_STATE_IS_SPLIT, "chunk state %s\n", uvm_pmm_gpu_chunk_state_string(chunk->state)); chunk->suballoc->pinned_leaf_chunks++; } -// Unpin a chunk and update its root chunk's pinned leaf chunks count if the chunk is not a root chunk +// Unpin a chunk and update its root chunk's pinned leaf chunks count if the +// chunk is not a root chunk. static void chunk_unpin(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk, uvm_pmm_gpu_chunk_state_t new_state) { uvm_gpu_root_chunk_t *root_chunk = root_chunk_from_chunk(pmm, chunk); @@ -432,10 +436,12 @@ static void chunk_unpin(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk, uvm_pmm_gpu_ if (chunk_is_root_chunk(chunk)) return; - // For subchunks, update the pinned leaf chunks count tracked in the suballoc of the root chunk. + // For subchunks, update the pinned leaf chunks count tracked in the + // suballoc of the root chunk. chunk = &root_chunk->chunk; - // The passed-in subchunk is not the root chunk so the root chunk has to be split + // The passed-in subchunk is not the root chunk so the root chunk has to be + // split. UVM_ASSERT_MSG(chunk->state == UVM_PMM_GPU_CHUNK_STATE_IS_SPLIT, "chunk state %s\n", uvm_pmm_gpu_chunk_state_string(chunk->state)); @@ -609,6 +615,7 @@ static NV_STATUS pmm_gpu_alloc_kernel(uvm_pmm_gpu_t *pmm, uvm_spin_lock(&pmm->list_lock); chunk_unpin(pmm, chunks[i], UVM_PMM_GPU_CHUNK_STATE_ALLOCATED); + chunks[i]->is_referenced = false; uvm_spin_unlock(&pmm->list_lock); } @@ -653,7 +660,10 @@ static void chunk_update_lists_locked(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk list_del_init(&chunk->list); } -void uvm_pmm_gpu_unpin_temp(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk, uvm_va_block_t *va_block) +static void gpu_unpin_temp(uvm_pmm_gpu_t *pmm, + uvm_gpu_chunk_t *chunk, + uvm_va_block_t *va_block, + bool is_referenced) { UVM_ASSERT(chunk->state == UVM_PMM_GPU_CHUNK_STATE_TEMP_PINNED); UVM_ASSERT(uvm_pmm_gpu_memory_type_is_user(chunk->type)); @@ -667,16 +677,26 @@ void uvm_pmm_gpu_unpin_temp(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk, uvm_va_b UVM_ASSERT(chunk->va_block_page_index < uvm_va_block_num_cpu_pages(va_block)); chunk_unpin(pmm, chunk, UVM_PMM_GPU_CHUNK_STATE_ALLOCATED); + chunk->is_referenced = is_referenced; chunk->va_block = va_block; chunk_update_lists_locked(pmm, chunk); uvm_spin_unlock(&pmm->list_lock); } +void uvm_pmm_gpu_unpin_allocated(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk, uvm_va_block_t *va_block) +{ + gpu_unpin_temp(pmm, chunk, va_block, false); +} + +void uvm_pmm_gpu_unpin_referenced(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk, uvm_va_block_t *va_block) +{ + gpu_unpin_temp(pmm, chunk, va_block, true); +} + void uvm_pmm_gpu_free(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk, uvm_tracker_t *tracker) { NV_STATUS status; - uvm_gpu_root_chunk_t *root_chunk; if (!chunk) return; @@ -684,11 +704,12 @@ void uvm_pmm_gpu_free(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk, uvm_tracker_t UVM_ASSERT(chunk->state == UVM_PMM_GPU_CHUNK_STATE_ALLOCATED || chunk->state == UVM_PMM_GPU_CHUNK_STATE_TEMP_PINNED); - root_chunk = root_chunk_from_chunk(pmm, chunk); - if (tracker) { + uvm_gpu_root_chunk_t *root_chunk; + uvm_tracker_remove_completed(tracker); + root_chunk = root_chunk_from_chunk(pmm, chunk); root_chunk_lock(pmm, root_chunk); // Remove any completed entries from the root tracker to prevent it from @@ -756,6 +777,7 @@ static bool assert_chunk_mergeable(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk) UVM_ASSERT(child->va_block == child_va_block); UVM_ASSERT(child->va_block_page_index == prev_child->va_block_page_index + uvm_gpu_chunk_get_size(prev_child) / PAGE_SIZE); + UVM_ASSERT(child->is_referenced == prev_child->is_referenced); } } @@ -799,6 +821,7 @@ static void merge_gpu_chunk(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk) UVM_ASSERT(subchunk->va_block); chunk->va_block = subchunk->va_block; chunk->va_block_page_index = subchunk->va_block_page_index; + chunk->is_referenced = subchunk->is_referenced; } else if (child_state == UVM_PMM_GPU_CHUNK_STATE_TEMP_PINNED) { UVM_ASSERT(root_chunk->chunk.suballoc->pinned_leaf_chunks >= num_sub); @@ -2013,8 +2036,8 @@ static NV_STATUS alloc_chunk_with_splits(uvm_pmm_gpu_t *pmm, UVM_PANIC(); } -// Allocates a single chunk of a given size. If needed splits a chunk of bigger size -// or, if that is not possible, allocates from PMA or evicts. +// Allocates a single chunk of a given size. If needed, splits a chunk of +// bigger size or, if that is not possible, allocates from PMA or evicts. NV_STATUS alloc_chunk(uvm_pmm_gpu_t *pmm, uvm_pmm_gpu_memory_type_t type, uvm_chunk_size_t chunk_size, @@ -2027,8 +2050,7 @@ NV_STATUS alloc_chunk(uvm_pmm_gpu_t *pmm, chunk = claim_free_chunk(pmm, type, chunk_size); if (chunk) { // A free chunk could be claimed, we are done. - *out_chunk = chunk; - return NV_OK; + goto out; } if (chunk_size == UVM_CHUNK_SIZE_MAX) { @@ -2039,11 +2061,11 @@ NV_STATUS alloc_chunk(uvm_pmm_gpu_t *pmm, if (status != NV_OK) return status; - *out_chunk = chunk; - return NV_OK; + goto out; } - // We didn't find a free chunk and we will require splits so acquire the PMM lock. + // We didn't find a free chunk and we will require splits so acquire the + // PMM lock. uvm_mutex_lock(&pmm->lock); status = alloc_chunk_with_splits(pmm, type, chunk_size, flags, &chunk); @@ -2055,6 +2077,7 @@ NV_STATUS alloc_chunk(uvm_pmm_gpu_t *pmm, return status; } +out: *out_chunk = chunk; return NV_OK; @@ -2273,7 +2296,8 @@ void free_root_chunk(uvm_pmm_gpu_t *pmm, uvm_gpu_root_chunk_t *root_chunk, free_ } // Splits the input chunk into subchunks of the next size down. The chunk state -// can be UVM_PMM_GPU_CHUNK_STATE_TEMP_PINNED or UVM_PMM_GPU_CHUNK_STATE_ALLOCATED. +// can be UVM_PMM_GPU_CHUNK_STATE_TEMP_PINNED or +// UVM_PMM_GPU_CHUNK_STATE_ALLOCATED. // // UVM_PMM_GPU_CHUNK_STATE_TEMP_PINNED: This is a split for allocation. // @@ -2339,6 +2363,7 @@ NV_STATUS split_gpu_chunk(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk) uvm_assert_mutex_locked(&chunk->va_block->lock); subchunk->va_block = chunk->va_block; subchunk->va_block_page_index = chunk->va_block_page_index + (i * subchunk_size) / PAGE_SIZE; + subchunk->is_referenced = chunk->is_referenced; } } @@ -2354,6 +2379,7 @@ NV_STATUS split_gpu_chunk(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk) if (chunk->state == UVM_PMM_GPU_CHUNK_STATE_ALLOCATED) { chunk->va_block = NULL; chunk->va_block_page_index = PAGES_PER_UVM_VA_BLOCK; + chunk->is_referenced = false; } else if (chunk->state == UVM_PMM_GPU_CHUNK_STATE_TEMP_PINNED) { // -1 for the parent chunk that is going to transition into the split state. @@ -2511,6 +2537,8 @@ static bool try_chunk_free(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk) uvm_spin_lock(&pmm->list_lock); + UVM_ASSERT(chunk->state != UVM_PMM_GPU_CHUNK_STATE_ALLOCATED || !chunk->is_referenced); + chunk->inject_split_error = false; // Chunks that are the last allocated child need to trigger a merge and are @@ -3254,6 +3282,270 @@ NvU32 uvm_pmm_gpu_phys_to_virt(uvm_pmm_gpu_t *pmm, NvU64 phys_addr, NvU64 region return num_mappings; } +#if UVM_IS_CONFIG_HMM() + +static uvm_pmm_gpu_t *devmem_page_to_pmm(struct page *page) +{ + return container_of(page->pgmap, uvm_pmm_gpu_t, devmem.pagemap); +} + +static uvm_gpu_chunk_t *devmem_page_to_chunk_locked(struct page *page) +{ + uvm_pmm_gpu_t *pmm = devmem_page_to_pmm(page); + NvU64 chunk_addr = ((NvU64)page_to_pfn(page) << PAGE_SHIFT) - pmm->devmem.pagemap.range.start; + size_t index = chunk_addr / UVM_CHUNK_SIZE_MAX; + uvm_gpu_chunk_t *root_chunk; + uvm_gpu_chunk_t *chunk; + uvm_gpu_chunk_t *parent; + uvm_chunk_size_t chunk_size; + + UVM_ASSERT(index < pmm->root_chunks.count); + root_chunk = &pmm->root_chunks.array[index].chunk; + UVM_ASSERT(root_chunk->address == UVM_ALIGN_DOWN(chunk_addr, UVM_CHUNK_SIZE_MAX)); + + // Find the uvm_gpu_chunk_t that corresponds to the device private struct + // page's PFN. The loop is only 0, 1, or 2 iterations. + for (chunk = root_chunk; + uvm_gpu_chunk_get_size(chunk) != page_size(page); + chunk = parent->suballoc->subchunks[index]) { + + parent = chunk; + UVM_ASSERT(parent->state == UVM_PMM_GPU_CHUNK_STATE_IS_SPLIT); + UVM_ASSERT(parent->suballoc); + + chunk_size = uvm_gpu_chunk_get_size(parent->suballoc->subchunks[0]); + index = (size_t)uvm_div_pow2_64(chunk_addr - parent->address, chunk_size); + UVM_ASSERT(index < num_subchunks(parent)); + } + + UVM_ASSERT(chunk->address = chunk_addr); + UVM_ASSERT(chunk->state == UVM_PMM_GPU_CHUNK_STATE_ALLOCATED); + UVM_ASSERT(chunk->is_referenced); + + return chunk; +} + +uvm_gpu_chunk_t *uvm_pmm_devmem_page_to_chunk(struct page *page) +{ + uvm_pmm_gpu_t *pmm = devmem_page_to_pmm(page); + uvm_gpu_chunk_t *chunk; + + UVM_ASSERT(is_device_private_page(page)); + + uvm_spin_lock(&pmm->list_lock); + chunk = devmem_page_to_chunk_locked(page); + uvm_spin_unlock(&pmm->list_lock); + + return chunk; +} + +uvm_gpu_id_t uvm_pmm_devmem_page_to_gpu_id(struct page *page) +{ + uvm_pmm_gpu_t *pmm = devmem_page_to_pmm(page); + uvm_gpu_t *gpu = uvm_pmm_to_gpu(pmm); + + UVM_ASSERT(is_device_private_page(page)); + + return gpu->id; +} + +static void evict_orphan_pages(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk) +{ + NvU32 i; + + UVM_ASSERT(chunk->state == UVM_PMM_GPU_CHUNK_STATE_IS_SPLIT); + UVM_ASSERT(chunk->suballoc); + + for (i = 0; i < num_subchunks(chunk); i++) { + uvm_gpu_chunk_t *subchunk = chunk->suballoc->subchunks[i]; + + uvm_spin_lock(&pmm->list_lock); + + if (subchunk->state == UVM_PMM_GPU_CHUNK_STATE_IS_SPLIT) { + uvm_spin_unlock(&pmm->list_lock); + + evict_orphan_pages(pmm, subchunk); + continue; + } + + if (subchunk->state == UVM_PMM_GPU_CHUNK_STATE_ALLOCATED && subchunk->is_referenced) { + uvm_spin_unlock(&pmm->list_lock); + + uvm_hmm_pmm_gpu_evict_chunk(uvm_pmm_to_gpu(pmm), subchunk); + continue; + } + + uvm_spin_unlock(&pmm->list_lock); + } +} + +void uvm_pmm_gpu_free_orphan_pages(uvm_pmm_gpu_t *pmm) +{ + size_t i; + + if (!pmm->initialized) + return; + + // Scan all the root chunks looking for subchunks which are still + // referenced. This is slow, but we only do this when unregistering a GPU + // and is not critical for performance. + for (i = 0; i < pmm->root_chunks.count; i++) { + uvm_gpu_root_chunk_t *root_chunk = &pmm->root_chunks.array[i]; + + root_chunk_lock(pmm, root_chunk); + if (root_chunk->chunk.state == UVM_PMM_GPU_CHUNK_STATE_IS_SPLIT) + evict_orphan_pages(pmm, &root_chunk->chunk); + root_chunk_unlock(pmm, root_chunk); + } +} + +static void devmem_page_free(struct page *page) +{ + uvm_pmm_gpu_t *pmm = devmem_page_to_pmm(page); + uvm_gpu_t *gpu = uvm_pmm_to_gpu(pmm); + uvm_gpu_chunk_t *chunk; + + page->zone_device_data = NULL; + + // We should be calling free_chunk() except that it acquires a mutex and + // we may be in an interrupt context where we can't do that. Instead, + // do a lazy free. Note that we have to use a "normal" spin lock because + // the UVM context is not available. + spin_lock(&pmm->list_lock.lock); + + chunk = devmem_page_to_chunk_locked(page); + UVM_ASSERT(chunk->is_referenced); + chunk->is_referenced = false; + list_add_tail(&chunk->list, &pmm->root_chunks.va_block_lazy_free); + + spin_unlock(&pmm->list_lock.lock); + + nv_kthread_q_schedule_q_item(&gpu->parent->lazy_free_q, + &pmm->root_chunks.va_block_lazy_free_q_item); +} + +// This is called by HMM when the CPU faults on a ZONE_DEVICE private entry. +static vm_fault_t devmem_fault(struct vm_fault *vmf) +{ + uvm_va_space_t *va_space = vmf->page->zone_device_data; + + if (!va_space) + return VM_FAULT_SIGBUS; + + return uvm_va_space_cpu_fault_hmm(va_space, vmf->vma, vmf); +} + +static vm_fault_t devmem_fault_entry(struct vm_fault *vmf) +{ + UVM_ENTRY_RET(devmem_fault(vmf)); +} + +static const struct dev_pagemap_ops uvm_pmm_devmem_ops = +{ + .page_free = devmem_page_free, + .migrate_to_ram = devmem_fault_entry, +}; + +static NV_STATUS devmem_init(uvm_pmm_gpu_t *pmm) +{ + unsigned long size = pmm->root_chunks.count * UVM_CHUNK_SIZE_MAX; + uvm_pmm_gpu_devmem_t *devmem = &pmm->devmem; + struct resource *res; + void *ptr; + NV_STATUS status; + + if (!uvm_hmm_is_enabled_system_wide()) { + devmem->pagemap.owner = NULL; + return NV_OK; + } + + res = request_free_mem_region(&iomem_resource, size, "nvidia-uvm-hmm"); + if (IS_ERR(res)) { + UVM_ERR_PRINT("request_free_mem_region() err %ld\n", PTR_ERR(res)); + status = errno_to_nv_status(PTR_ERR(res)); + goto err; + } + + devmem->pagemap.type = MEMORY_DEVICE_PRIVATE; + devmem->pagemap.range.start = res->start; + devmem->pagemap.range.end = res->end; + devmem->pagemap.nr_range = 1; + devmem->pagemap.ops = &uvm_pmm_devmem_ops; + devmem->pagemap.owner = &g_uvm_global; + + // Numa node ID doesn't matter for ZONE_DEVICE private pages. + ptr = memremap_pages(&devmem->pagemap, NUMA_NO_NODE); + if (IS_ERR(ptr)) { + UVM_ERR_PRINT("memremap_pages() err %ld\n", PTR_ERR(ptr)); + status = errno_to_nv_status(PTR_ERR(ptr)); + goto err_release; + } + + return NV_OK; + +err_release: + release_mem_region(res->start, resource_size(res)); +err: + devmem->pagemap.owner = NULL; + return status; +} + +static void devmem_deinit(uvm_pmm_gpu_t *pmm) +{ + uvm_pmm_gpu_devmem_t *devmem = &pmm->devmem; + + if (!devmem->pagemap.owner) + return; + + memunmap_pages(&devmem->pagemap); + release_mem_region(devmem->pagemap.range.start, range_len(&devmem->pagemap.range)); +} + +unsigned long uvm_pmm_gpu_devmem_get_pfn(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk) +{ + return (pmm->devmem.pagemap.range.start + chunk->address) >> PAGE_SHIFT; +} + +#endif // UVM_IS_CONFIG_HMM() + +#if !UVM_IS_CONFIG_HMM() +static NV_STATUS devmem_init(uvm_pmm_gpu_t *pmm) +{ + return NV_OK; +} + +static void devmem_deinit(uvm_pmm_gpu_t *pmm) +{ +} +#endif // UVM_IS_CONFIG_HMM() + +static void process_lazy_free(uvm_pmm_gpu_t *pmm) +{ + uvm_gpu_chunk_t *chunk; + + uvm_spin_lock(&pmm->list_lock); + + // Note: We can't use list_for_each_safe_entry() because we drop the lock + // in the loop. Instead, just keep removing the first entry until the list + // is empty. + while (!list_empty(&pmm->root_chunks.va_block_lazy_free)) { + chunk = list_first_entry(&pmm->root_chunks.va_block_lazy_free, uvm_gpu_chunk_t, list); + list_del_init(&chunk->list); + uvm_spin_unlock(&pmm->list_lock); + + free_chunk(pmm, chunk); + + uvm_spin_lock(&pmm->list_lock); + } + + uvm_spin_unlock(&pmm->list_lock); +} + +static void process_lazy_free_entry(void *args) +{ + UVM_ENTRY_VOID(process_lazy_free(args)); +} + NV_STATUS uvm_pmm_gpu_init(uvm_pmm_gpu_t *pmm) { uvm_gpu_t *gpu = uvm_pmm_to_gpu(pmm); @@ -3279,6 +3571,8 @@ NV_STATUS uvm_pmm_gpu_init(uvm_pmm_gpu_t *pmm) } INIT_LIST_HEAD(&pmm->root_chunks.va_block_used); INIT_LIST_HEAD(&pmm->root_chunks.va_block_unused); + INIT_LIST_HEAD(&pmm->root_chunks.va_block_lazy_free); + nv_kthread_q_item_init(&pmm->root_chunks.va_block_lazy_free_q_item, process_lazy_free_entry, pmm); uvm_mutex_init(&pmm->lock, UVM_LOCK_ORDER_PMM); uvm_init_rwsem(&pmm->pma_lock, UVM_LOCK_ORDER_PMM_PMA); @@ -3354,6 +3648,10 @@ NV_STATUS uvm_pmm_gpu_init(uvm_pmm_gpu_t *pmm) } } + status = devmem_init(pmm); + if (status != NV_OK) + goto cleanup; + return NV_OK; cleanup: uvm_pmm_gpu_deinit(pmm); @@ -3387,9 +3685,11 @@ void uvm_pmm_gpu_deinit(uvm_pmm_gpu_t *pmm) if (!pmm->initialized) return; + gpu = uvm_pmm_to_gpu(pmm); + nv_kthread_q_flush(&gpu->parent->lazy_free_q); + UVM_ASSERT(list_empty(&pmm->root_chunks.va_block_lazy_free)); release_free_root_chunks(pmm); - gpu = uvm_pmm_to_gpu(pmm); if (gpu->mem_info.size != 0 && gpu_supports_pma_eviction(gpu)) nvUvmInterfacePmaUnregisterEvictionCallbacks(pmm->pma); @@ -3425,6 +3725,8 @@ void uvm_pmm_gpu_deinit(uvm_pmm_gpu_t *pmm) deinit_caches(pmm); + devmem_deinit(pmm); + pmm->initialized = false; } diff --git a/kernel-open/nvidia-uvm/uvm_pmm_gpu.h b/kernel-open/nvidia-uvm/uvm_pmm_gpu.h index b48314d66..71f04da79 100644 --- a/kernel-open/nvidia-uvm/uvm_pmm_gpu.h +++ b/kernel-open/nvidia-uvm/uvm_pmm_gpu.h @@ -59,6 +59,9 @@ #include "uvm_linux.h" #include "uvm_types.h" #include "nv_uvm_types.h" +#if UVM_IS_CONFIG_HMM() +#include +#endif typedef enum { @@ -195,7 +198,35 @@ typedef uvm_chunk_size_t uvm_chunk_sizes_mask_t; typedef struct uvm_pmm_gpu_chunk_suballoc_struct uvm_pmm_gpu_chunk_suballoc_t; -typedef struct uvm_gpu_chunk_struct uvm_gpu_chunk_t; +#if UVM_IS_CONFIG_HMM() + +typedef struct uvm_pmm_gpu_struct uvm_pmm_gpu_t; + +typedef struct +{ + struct dev_pagemap pagemap; +} uvm_pmm_gpu_devmem_t; + +// Return the GPU chunk for a given device private struct page. +uvm_gpu_chunk_t *uvm_pmm_devmem_page_to_chunk(struct page *page); + +// Return the GPU id for a given device private struct page. +uvm_gpu_id_t uvm_pmm_devmem_page_to_gpu_id(struct page *page); + +// Return the PFN of the device private struct page for the given GPU chunk. +unsigned long uvm_pmm_gpu_devmem_get_pfn(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk); + +// Free any orphan pages. +// This should be called as part of removing a GPU: after all work is stopped +// and all va_blocks have been destroyed. There normally won't be any +// device private struct page references left but there can be cases after +// fork() where a child process still holds a reference. This function searches +// for pages that still have a reference and migrates the page to the GPU in +// order to release the reference in the CPU page table. +void uvm_pmm_gpu_free_orphan_pages(uvm_pmm_gpu_t *pmm); + +#endif + struct uvm_gpu_chunk_struct { // Physical address of GPU chunk. This may be removed to save memory @@ -208,15 +239,15 @@ struct uvm_gpu_chunk_struct // We use +1 in the order_base_2 calls appropriately to avoid compiler // warnings due to the bitfields being too narrow for the values of // their types. - uvm_pmm_gpu_memory_type_t type : order_base_2(UVM_PMM_GPU_MEMORY_TYPE_COUNT + 1); + uvm_pmm_gpu_memory_type_t type : order_base_2(UVM_PMM_GPU_MEMORY_TYPE_COUNT + 1); // The eviction flag is internal and used only for root chunks. It's // set by the eviction path once a chunk is chosen for eviction in // chunk_start_eviction(). Also see the (root_)chunk_is_in_eviction() // helpers. - bool in_eviction : 1; + bool in_eviction : 1; - bool inject_split_error : 1; + bool inject_split_error : 1; // This flag is initalized when allocating a new root chunk from PMA. // It is set to true, if PMA already scrubbed the chunk. The flag is @@ -224,19 +255,23 @@ struct uvm_gpu_chunk_struct // the caller is not required to clear it before freeing the chunk. The // VA block chunk population code can query it to skip zeroing the // chunk. - bool is_zero : 1; + bool is_zero : 1; - uvm_pmm_gpu_chunk_state_t state : order_base_2(UVM_PMM_GPU_CHUNK_STATE_COUNT + 1); + // This flag indicates an allocated chunk is referenced by a device + // private struct page PTE and therefore expects a page_free() callback. + bool is_referenced : 1; - size_t log2_size : order_base_2(UVM_CHUNK_SIZE_MASK_SIZE); + uvm_pmm_gpu_chunk_state_t state : order_base_2(UVM_PMM_GPU_CHUNK_STATE_COUNT + 1); + + size_t log2_size : order_base_2(UVM_CHUNK_SIZE_MASK_SIZE); // Start page index within va_block - uvm_page_index_t va_block_page_index : order_base_2(PAGES_PER_UVM_VA_BLOCK + 1); + uvm_page_index_t va_block_page_index : order_base_2(PAGES_PER_UVM_VA_BLOCK + 1); // This allows determining what PMM owns the chunk. Users of this field // must only use it if the owning GPU is retained. // TODO: Bug 2008200: Enforce single PMM instance per GPU - NvU32 gpu_global_index : order_base_2(UVM_GLOBAL_ID_MAX_PROCESSORS); + NvU32 gpu_global_index : order_base_2(UVM_GLOBAL_ID_MAX_PROCESSORS); }; // List entry. @@ -309,7 +344,7 @@ typedef struct atomic64_t map_count; } uvm_gpu_root_chunk_indirect_peer_t; -typedef struct +typedef struct uvm_pmm_gpu_struct { // Sizes of the MMU uvm_chunk_sizes_mask_t chunk_sizes[UVM_PMM_GPU_MEMORY_TYPE_COUNT]; @@ -348,9 +383,19 @@ typedef struct // List of root chunks used by VA blocks struct list_head va_block_used; + // List of chunks needing to be lazily freed and a queue for processing + // the list. TODO: Bug 3881835: revisit whether to use nv_kthread_q_t + // or workqueue. + struct list_head va_block_lazy_free; + nv_kthread_q_item_t va_block_lazy_free_q_item; + uvm_gpu_root_chunk_indirect_peer_t indirect_peer[UVM_ID_MAX_GPUS]; } root_chunks; +#if UVM_IS_CONFIG_HMM() + uvm_pmm_gpu_devmem_t devmem; +#endif + // Lock protecting PMA allocation, freeing and eviction uvm_rw_semaphore_t pma_lock; @@ -410,16 +455,17 @@ struct page *uvm_gpu_chunk_to_page(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk); // Allocates num_chunks chunks of size chunk_size in caller-supplied array (chunks). // // Returned chunks are in the TEMP_PINNED state, requiring a call to either -// uvm_pmm_gpu_unpin_temp or uvm_pmm_gpu_free. If a tracker is passed in, all +// uvm_pmm_gpu_unpin_allocated, uvm_pmm_gpu_unpin_referenced, or +// uvm_pmm_gpu_free. If a tracker is passed in, all // the pending operations on the allocated chunks will be added to it // guaranteeing that all the entries come from the same GPU as the PMM. // Otherwise, when tracker is NULL, all the pending operations will be // synchronized before returning to the caller. // // Each of the allocated chunks list nodes (uvm_gpu_chunk_t::list) can be used -// by the caller until the chunk is unpinned (uvm_pmm_gpu_unpin_temp) or freed -// (uvm_pmm_gpu_free). If used, the list node has to be returned to a valid -// state before calling either of the APIs. +// by the caller until the chunk is unpinned (uvm_pmm_gpu_unpin_allocated, +// uvm_pmm_gpu_unpin_referenced) or freed (uvm_pmm_gpu_free). If used, the list +// node has to be returned to a valid state before calling either of the APIs. // // In case of an error, the chunks array is guaranteed to be cleared. NV_STATUS uvm_pmm_gpu_alloc(uvm_pmm_gpu_t *pmm, @@ -459,10 +505,17 @@ static NV_STATUS uvm_pmm_gpu_alloc_user(uvm_pmm_gpu_t *pmm, return uvm_pmm_gpu_alloc(pmm, num_chunks, chunk_size, UVM_PMM_GPU_MEMORY_TYPE_USER, flags, chunks, out_tracker); } -// Unpin a temporarily pinned chunk and set its reverse map to a VA block +// Unpin a temporarily pinned chunk, set its reverse map to a VA block, and +// mark it as allocated. // // Can only be used on user memory. -void uvm_pmm_gpu_unpin_temp(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk, uvm_va_block_t *va_block); +void uvm_pmm_gpu_unpin_allocated(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk, uvm_va_block_t *va_block); + +// Unpin a temporarily pinned chunk, set its reverse map to a VA block, and +// mark it as referenced. +// +// Can only be used on user memory. +void uvm_pmm_gpu_unpin_referenced(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk, uvm_va_block_t *va_block); // Frees the chunk. This also unpins the chunk if it is temporarily pinned. // diff --git a/kernel-open/nvidia-uvm/uvm_pmm_sysmem.c b/kernel-open/nvidia-uvm/uvm_pmm_sysmem.c index d8345f95e..7e843282c 100644 --- a/kernel-open/nvidia-uvm/uvm_pmm_sysmem.c +++ b/kernel-open/nvidia-uvm/uvm_pmm_sysmem.c @@ -40,6 +40,15 @@ NV_STATUS uvm_pmm_sysmem_init(void) if (!g_reverse_page_map_cache) return NV_ERR_NO_MEMORY; + // Ensure that only supported CPU chunk sizes are enabled. + uvm_cpu_chunk_allocation_sizes &= UVM_CPU_CHUNK_SIZES; + if (!uvm_cpu_chunk_allocation_sizes || !(uvm_cpu_chunk_allocation_sizes & PAGE_SIZE)) { + pr_info("Invalid value for uvm_cpu_chunk_allocation_sizes = 0x%x, using 0x%lx instead\n", + uvm_cpu_chunk_allocation_sizes, + UVM_CPU_CHUNK_SIZES); + uvm_cpu_chunk_allocation_sizes = UVM_CPU_CHUNK_SIZES; + } + return NV_OK; } @@ -430,1031 +439,669 @@ uvm_chunk_sizes_mask_t uvm_cpu_chunk_get_allocation_sizes(void) static void uvm_cpu_chunk_set_size(uvm_cpu_chunk_t *chunk, uvm_chunk_size_t size) { -#if !UVM_CPU_CHUNK_SIZE_IS_PAGE_SIZE() chunk->log2_size = ilog2(size); -#endif } uvm_chunk_size_t uvm_cpu_chunk_get_size(uvm_cpu_chunk_t *chunk) { -#if UVM_CPU_CHUNK_SIZE_IS_PAGE_SIZE() - return PAGE_SIZE; -#else return ((uvm_chunk_size_t)1) << chunk->log2_size; -#endif } -#if UVM_CPU_CHUNK_SIZE_IS_PAGE_SIZE() -struct page *uvm_cpu_chunk_get_cpu_page(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) +static NvU32 compute_gpu_mappings_entry_index(uvm_processor_mask_t *dma_addrs_mask, uvm_gpu_id_t id) { - UVM_ASSERT(chunk); - return chunk; -} + uvm_processor_mask_t subset_mask; -void uvm_cpu_chunk_put(uvm_cpu_chunk_t *chunk) -{ - UVM_ASSERT(chunk); - put_page(chunk); -} + // Compute the array index for the given GPU ID by masking off all bits + // above and including the id and then counting the number of bits + // remaining. + uvm_processor_mask_zero(&subset_mask); + bitmap_set(subset_mask.bitmap, UVM_ID_GPU0_VALUE, uvm_id_gpu_index(id)); + uvm_processor_mask_and(&subset_mask, dma_addrs_mask, &subset_mask); -NV_STATUS uvm_cpu_chunk_gpu_mapping_alloc(uvm_va_block_t *va_block, uvm_gpu_id_t id) -{ - uvm_va_block_gpu_state_t *gpu_state = uvm_va_block_gpu_state_get(va_block, id); - size_t num_pages = uvm_va_block_num_cpu_pages(va_block); - - UVM_ASSERT(gpu_state); - gpu_state->cpu_chunks_dma_addrs = uvm_kvmalloc_zero(num_pages * sizeof(gpu_state->cpu_chunks_dma_addrs[0])); - if (!gpu_state->cpu_chunks_dma_addrs) - return NV_ERR_NO_MEMORY; - - return NV_OK; -} - -void uvm_cpu_chunk_gpu_mapping_split(uvm_va_block_t *existing, uvm_va_block_t *new, uvm_gpu_id_t id) -{ - uvm_va_block_gpu_state_t *existing_state = uvm_va_block_gpu_state_get(existing, id); - uvm_va_block_gpu_state_t *new_state = uvm_va_block_gpu_state_get(new, id); - size_t new_pages = uvm_va_block_num_cpu_pages(new); - - memcpy(&new_state->cpu_chunks_dma_addrs[0], - &existing_state->cpu_chunks_dma_addrs[uvm_va_block_num_cpu_pages(existing) - new_pages], - new_pages * sizeof(new_state->cpu_chunks_dma_addrs[0])); -} - -void uvm_cpu_chunk_gpu_mapping_free(uvm_va_block_t *va_block, uvm_gpu_id_t id) -{ - uvm_va_block_gpu_state_t *gpu_state = uvm_va_block_gpu_state_get(va_block, id); - - if (gpu_state) - uvm_kvfree(gpu_state->cpu_chunks_dma_addrs); -} - -NV_STATUS uvm_cpu_chunk_set_gpu_mapping_addr(uvm_va_block_t *va_block, - uvm_page_index_t page_index, - uvm_cpu_chunk_t *chunk, - uvm_gpu_id_t id, - NvU64 dma_addr) -{ - uvm_va_block_gpu_state_t *gpu_state = uvm_va_block_gpu_state_get(va_block, id); - - gpu_state->cpu_chunks_dma_addrs[page_index] = dma_addr; - return NV_OK; -} - -NvU64 uvm_cpu_chunk_get_gpu_mapping_addr(uvm_va_block_t *va_block, - uvm_page_index_t page_index, - uvm_cpu_chunk_t *chunk, - uvm_gpu_id_t id) -{ - uvm_va_block_gpu_state_t *gpu_state = uvm_va_block_gpu_state_get(va_block, id); - - return gpu_state->cpu_chunks_dma_addrs[page_index]; -} - -NV_STATUS uvm_cpu_chunk_insert_in_block(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) -{ - if (!va_block->cpu.chunks) { - va_block->cpu.chunks = (unsigned long)uvm_kvmalloc_zero(uvm_va_block_num_cpu_pages(va_block) * - sizeof(uvm_cpu_chunk_t *)); - if (!va_block->cpu.chunks) - return NV_ERR_NO_MEMORY; - } - - UVM_ASSERT(!uvm_page_mask_test(&va_block->cpu.allocated, page_index)); - UVM_ASSERT(((uvm_cpu_chunk_t **)va_block->cpu.chunks)[page_index] == NULL); - ((uvm_cpu_chunk_t **)va_block->cpu.chunks)[page_index] = chunk; - uvm_page_mask_set(&va_block->cpu.allocated, page_index); - return NV_OK; -} - -void uvm_cpu_chunk_remove_from_block(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) -{ - UVM_ASSERT(uvm_page_mask_test(&va_block->cpu.allocated, page_index)); - UVM_ASSERT(((uvm_cpu_chunk_t **)va_block->cpu.chunks)[page_index] != NULL); - ((uvm_cpu_chunk_t **)va_block->cpu.chunks)[page_index] = NULL; - uvm_page_mask_clear(&va_block->cpu.allocated, page_index); -} - -uvm_cpu_chunk_t *uvm_cpu_chunk_get_chunk_for_page(uvm_va_block_t *va_block, uvm_page_index_t page_index) -{ - UVM_ASSERT(page_index < uvm_va_block_num_cpu_pages(va_block)); - if (!uvm_page_mask_test(&va_block->cpu.allocated, page_index)) - return NULL; - - return ((uvm_cpu_chunk_t **)va_block->cpu.chunks)[page_index]; -} - -NV_STATUS uvm_cpu_chunk_alloc(uvm_va_block_t *va_block, - uvm_page_index_t page_index, - struct mm_struct *mm, - uvm_cpu_chunk_t **new_chunk) -{ - uvm_cpu_chunk_t *chunk = NULL; - gfp_t alloc_flags; - NV_STATUS status; - - UVM_ASSERT(!uvm_page_mask_test(&va_block->cpu.allocated, page_index)); - UVM_ASSERT(new_chunk); - - alloc_flags = (mm ? NV_UVM_GFP_FLAGS_ACCOUNT : NV_UVM_GFP_FLAGS) | GFP_HIGHUSER; - - if (!uvm_va_block_page_resident_processors_count(va_block, page_index)) - alloc_flags |= __GFP_ZERO; - - chunk = alloc_pages(alloc_flags, 0); - if (!chunk) - return NV_ERR_NO_MEMORY; - - if (alloc_flags & __GFP_ZERO) - SetPageDirty(chunk); - - status = uvm_cpu_chunk_insert_in_block(va_block, chunk, page_index); - if (status != NV_OK) { - uvm_cpu_chunk_put(chunk); - return status; - } - - *new_chunk = chunk; - return NV_OK; -} - -#else - -struct page *uvm_cpu_chunk_get_cpu_page(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) -{ - uvm_va_block_region_t chunk_region; - - UVM_ASSERT(chunk); - UVM_ASSERT(chunk->page); - chunk_region = uvm_va_block_chunk_region(va_block, uvm_cpu_chunk_get_size(chunk), page_index); - return chunk->page + (page_index - chunk_region.first); -} - -static NvU64 uvm_cpu_chunk_get_virt_addr(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk) -{ - UVM_ASSERT(chunk); - UVM_ASSERT(chunk->region.first < chunk->region.outer); - return uvm_va_block_cpu_page_address(va_block, chunk->region.first); + return uvm_processor_mask_get_gpu_count(&subset_mask); } static void cpu_chunk_release(nv_kref_t *kref) { uvm_cpu_chunk_t *chunk = container_of(kref, uvm_cpu_chunk_t, refcount); - uvm_cpu_chunk_t *parent = chunk->parent; + uvm_processor_mask_t *mapping_mask; + uvm_processor_id_t id; + uvm_cpu_physical_chunk_t *phys_chunk = NULL; + uvm_cpu_logical_chunk_t *logical_chunk = NULL; - if (uvm_processor_mask_get_gpu_count(&chunk->gpu_mappings.dma_addrs_mask) > 1) - uvm_kvfree(chunk->gpu_mappings.dynamic_entries); - - if (!parent) { - uvm_assert_spinlock_unlocked(&chunk->lock); - uvm_kvfree(chunk->dirty_bitmap); - put_page(chunk->page); + if (uvm_cpu_chunk_is_physical(chunk)) { + phys_chunk = uvm_cpu_chunk_to_physical(chunk); + uvm_assert_mutex_unlocked(&phys_chunk->lock); + mapping_mask = &phys_chunk->gpu_mappings.dma_addrs_mask; } else { - uvm_cpu_chunk_put(parent); + logical_chunk = uvm_cpu_chunk_to_logical(chunk); + mapping_mask = &logical_chunk->mapped_gpus; + } + + for_each_id_in_mask(id, mapping_mask) { + uvm_parent_gpu_t *parent_gpu = uvm_parent_gpu_get(id); + uvm_cpu_chunk_unmap_gpu_phys(chunk, parent_gpu); + } + + if (uvm_cpu_chunk_is_physical(chunk)) { + if (phys_chunk->gpu_mappings.max_entries > 1) + uvm_kvfree(phys_chunk->gpu_mappings.dynamic_entries); + + if (uvm_cpu_chunk_get_size(chunk) > PAGE_SIZE && + !bitmap_empty(phys_chunk->dirty_bitmap, uvm_cpu_chunk_num_pages(chunk))) + SetPageDirty(phys_chunk->common.page); + + uvm_kvfree(phys_chunk->dirty_bitmap); + + if (chunk->type != UVM_CPU_CHUNK_TYPE_HMM) + put_page(phys_chunk->common.page); + } + else { + uvm_cpu_chunk_free(logical_chunk->parent); } uvm_kvfree(chunk); } -void uvm_cpu_chunk_get(uvm_cpu_chunk_t *chunk) +static void uvm_cpu_chunk_get(uvm_cpu_chunk_t *chunk) { UVM_ASSERT(chunk); nv_kref_get(&chunk->refcount); } -void uvm_cpu_chunk_put(uvm_cpu_chunk_t *chunk) +void uvm_cpu_chunk_free(uvm_cpu_chunk_t *chunk) { - UVM_ASSERT(chunk); + if (!chunk) + return; nv_kref_put(&chunk->refcount, cpu_chunk_release); } -NV_STATUS uvm_cpu_chunk_gpu_mapping_alloc(uvm_va_block_t *va_block, uvm_gpu_id_t id) +static uvm_cpu_physical_chunk_t *get_physical_parent(uvm_cpu_chunk_t *chunk) { - return NV_OK; + UVM_ASSERT(chunk); + UVM_ASSERT(chunk->page); + + while (!uvm_cpu_chunk_is_physical(chunk)) + chunk = uvm_cpu_chunk_to_logical(chunk)->parent; + + return uvm_cpu_chunk_to_physical(chunk); } -void uvm_cpu_chunk_gpu_mapping_split(uvm_va_block_t *existing, uvm_va_block_t *va_block, uvm_gpu_id_t id) +static uvm_page_index_t cpu_chunk_get_phys_index(uvm_cpu_logical_chunk_t *chunk) { - return; + uvm_cpu_physical_chunk_t *phys_chunk = get_physical_parent(&chunk->common); + + UVM_ASSERT(phys_chunk->common.page); + return (uvm_page_index_t)(chunk->common.page - phys_chunk->common.page); } -void uvm_cpu_chunk_gpu_mapping_free(uvm_va_block_t *va_block, uvm_gpu_id_t id) +static uvm_cpu_phys_mapping_t *chunk_phys_mapping_alloc(uvm_cpu_physical_chunk_t *chunk, uvm_gpu_id_t id) { - return; -} - -static NvU32 compute_gpu_mappings_entry_index(uvm_processor_mask_t dma_addrs_mask, uvm_gpu_id_t id) -{ - uvm_processor_mask_t subset_mask; - - // Compute the array index for the given GPU ID by masking off all bits - // above the id and then counting the number of bits remaining. - uvm_processor_mask_zero(&subset_mask); - bitmap_set(subset_mask.bitmap, 0, uvm_id_value(id) + 1); - uvm_processor_mask_and(&subset_mask, &dma_addrs_mask, &subset_mask); - - if (uvm_processor_mask_empty(&subset_mask)) - return 0; - - return uvm_processor_mask_get_gpu_count(&subset_mask) - 1; -} - -NV_STATUS uvm_cpu_chunk_set_gpu_mapping_addr(uvm_va_block_t *va_block, - uvm_page_index_t page_index, - uvm_cpu_chunk_t *chunk, - uvm_gpu_id_t id, - NvU64 dma_addr) -{ - NvU32 num_existing_entries = uvm_processor_mask_get_gpu_count(&chunk->gpu_mappings.dma_addrs_mask); - NvU32 num_new_entries; + NvU32 num_active_entries = uvm_processor_mask_get_gpu_count(&chunk->gpu_mappings.dma_addrs_mask); + uvm_cpu_phys_mapping_t *new_entries; NvU32 array_index; - NvU64 *new_entries; - if (uvm_processor_mask_empty(&chunk->gpu_mappings.dma_addrs_mask)) { - uvm_processor_mask_set(&chunk->gpu_mappings.dma_addrs_mask, id); - chunk->gpu_mappings.static_entry = dma_addr; - return NV_OK; - } + uvm_assert_mutex_locked(&chunk->lock); - if (uvm_processor_mask_test(&chunk->gpu_mappings.dma_addrs_mask, id)) { - if (num_existing_entries == 1) { - chunk->gpu_mappings.static_entry = dma_addr; + if (chunk->gpu_mappings.max_entries == 1 && num_active_entries == 0) + return &chunk->gpu_mappings.static_entry; + + if (num_active_entries == chunk->gpu_mappings.max_entries) { + NvU32 num_new_entries = chunk->gpu_mappings.max_entries * 2; + + if (chunk->gpu_mappings.max_entries == 1) { + new_entries = uvm_kvmalloc(sizeof(*new_entries) * num_new_entries); + if (new_entries) + new_entries[0] = chunk->gpu_mappings.static_entry; } else { - array_index = compute_gpu_mappings_entry_index(chunk->gpu_mappings.dma_addrs_mask, id); - chunk->gpu_mappings.dynamic_entries[array_index] = dma_addr; + new_entries = uvm_kvrealloc(chunk->gpu_mappings.dynamic_entries, + sizeof(*new_entries) * num_new_entries); } - return NV_OK; + + if (!new_entries) + return NULL; + + chunk->gpu_mappings.max_entries = num_new_entries; + chunk->gpu_mappings.dynamic_entries = new_entries; } - num_new_entries = num_existing_entries + 1; - if (num_existing_entries == 1) { - new_entries = uvm_kvmalloc(sizeof(*new_entries) * num_new_entries); - - if (new_entries) { - uvm_processor_id_t first = uvm_processor_mask_find_first_id(&chunk->gpu_mappings.dma_addrs_mask); - - if (uvm_id_value(first) < uvm_id_value(id)) - new_entries[0] = chunk->gpu_mappings.static_entry; - else - new_entries[1] = chunk->gpu_mappings.static_entry; - } - } - else { - new_entries = uvm_kvrealloc(chunk->gpu_mappings.dynamic_entries, - sizeof(*new_entries) * num_new_entries); - if (new_entries) { - // Get the number of bits set below the input id. - num_existing_entries = compute_gpu_mappings_entry_index(chunk->gpu_mappings.dma_addrs_mask, id); - for (; num_existing_entries < num_new_entries - 1; num_existing_entries++) - new_entries[num_existing_entries + 1] = new_entries[num_existing_entries]; - } + array_index = compute_gpu_mappings_entry_index(&chunk->gpu_mappings.dma_addrs_mask, id); + while (num_active_entries > array_index) { + chunk->gpu_mappings.dynamic_entries[num_active_entries] = + chunk->gpu_mappings.dynamic_entries[num_active_entries - 1]; + num_active_entries--; } - if (!new_entries) - return NV_ERR_NO_MEMORY; - - chunk->gpu_mappings.dynamic_entries = new_entries; - uvm_processor_mask_set(&chunk->gpu_mappings.dma_addrs_mask, id); - array_index = compute_gpu_mappings_entry_index(chunk->gpu_mappings.dma_addrs_mask, id); - chunk->gpu_mappings.dynamic_entries[array_index] = dma_addr; - - return NV_OK; + return &chunk->gpu_mappings.dynamic_entries[array_index]; } -NvU64 uvm_cpu_chunk_get_gpu_mapping_addr(uvm_va_block_t *va_block, - uvm_page_index_t page_index, - uvm_cpu_chunk_t *chunk, - uvm_gpu_id_t id) +static uvm_cpu_phys_mapping_t *chunk_phys_mapping_get(uvm_cpu_physical_chunk_t *chunk, uvm_gpu_id_t id) { - NvU64 dma_addr; - - if (!uvm_processor_mask_test(&chunk->gpu_mappings.dma_addrs_mask, id)) - return 0; - - if (uvm_processor_mask_get_gpu_count(&chunk->gpu_mappings.dma_addrs_mask) == 1) { - dma_addr = chunk->gpu_mappings.static_entry; - } - else { - NvU32 array_index = compute_gpu_mappings_entry_index(chunk->gpu_mappings.dma_addrs_mask, id); - - dma_addr = chunk->gpu_mappings.dynamic_entries[array_index]; + uvm_assert_mutex_locked(&chunk->lock); + if (uvm_processor_mask_test(&chunk->gpu_mappings.dma_addrs_mask, id)) { + if (chunk->gpu_mappings.max_entries == 1) { + return &chunk->gpu_mappings.static_entry; + } + else { + NvU32 array_index = compute_gpu_mappings_entry_index(&chunk->gpu_mappings.dma_addrs_mask, id); + return &chunk->gpu_mappings.dynamic_entries[array_index]; + } } + return NULL; +} + +static void chunk_inc_gpu_mapping(uvm_cpu_physical_chunk_t *chunk, uvm_gpu_id_t id) +{ + uvm_cpu_phys_mapping_t *mapping; + + uvm_assert_mutex_locked(&chunk->lock); + mapping = chunk_phys_mapping_get(chunk, id); + UVM_ASSERT(mapping); + mapping->map_count++; +} + +static void chunk_dec_gpu_mapping(uvm_cpu_physical_chunk_t *chunk, uvm_gpu_id_t id) +{ + uvm_cpu_phys_mapping_t *mapping; + + uvm_assert_mutex_locked(&chunk->lock); + mapping = chunk_phys_mapping_get(chunk, id); + UVM_ASSERT(mapping); + UVM_ASSERT(mapping->dma_addr && mapping->map_count); + mapping->map_count--; + if (mapping->map_count == 0) { + uvm_parent_gpu_t *parent_gpu = uvm_parent_gpu_get(id); + + uvm_gpu_unmap_cpu_pages(parent_gpu, mapping->dma_addr, uvm_cpu_chunk_get_size(&chunk->common)); + mapping->dma_addr = 0; + if (chunk->gpu_mappings.max_entries > 1) { + NvU32 num_active_entries = uvm_processor_mask_get_gpu_count(&chunk->gpu_mappings.dma_addrs_mask); + NvU32 array_index = compute_gpu_mappings_entry_index(&chunk->gpu_mappings.dma_addrs_mask, id); + + // Shift any GPU mappings above this one down in the mappings array. + for (; array_index < num_active_entries - 1; array_index++) + chunk->gpu_mappings.dynamic_entries[array_index] = chunk->gpu_mappings.dynamic_entries[array_index+1]; + } + + uvm_processor_mask_clear(&chunk->gpu_mappings.dma_addrs_mask, id); + } +} + +NvU64 uvm_cpu_chunk_get_gpu_phys_addr(uvm_cpu_chunk_t *chunk, uvm_parent_gpu_t *parent_gpu) +{ + uvm_cpu_physical_chunk_t *phys_chunk = get_physical_parent(chunk); + uvm_cpu_phys_mapping_t *mapping; + uvm_page_index_t parent_offset = 0; + NvU64 dma_addr = 0; + + if (uvm_cpu_chunk_is_logical(chunk)) { + uvm_cpu_logical_chunk_t *logical_chunk = uvm_cpu_chunk_to_logical(chunk); + + if (!uvm_processor_mask_test(&logical_chunk->mapped_gpus, parent_gpu->id)) + return 0; + + parent_offset = cpu_chunk_get_phys_index(logical_chunk); + } + + uvm_mutex_lock(&phys_chunk->lock); + mapping = chunk_phys_mapping_get(phys_chunk, parent_gpu->id); + if (mapping) + dma_addr = mapping->dma_addr + (parent_offset * PAGE_SIZE); + + uvm_mutex_unlock(&phys_chunk->lock); return dma_addr; } -// The bottom two bits of uvm_va_block_t::chunks is used to indicate how -// CPU chunks are stored. +// Create a DMA mapping for the chunk on the given parent GPU. This will map the +// entire parent physical chunk on the GPU. // -// CPU chunk storage is handled in three different ways depending on the -// type of chunks the VA block owns. This is done to minimize the memory -// required to hold metadata. -typedef enum +// Returns NV_OK on success. On error, any of the errors returned by +// uvm_gpu_map_cpu_pages() can be returned. In the case that the DMA mapping +// structure could not be allocated, NV_ERR_NO_MEMORY is returned. +static NV_STATUS cpu_chunk_map_gpu_phys(uvm_cpu_chunk_t *chunk, uvm_parent_gpu_t *parent_gpu) { - // The uvm_va_block_t::chunk pointer points to a single 2MB - // CPU chunk. - UVM_CPU_CHUNK_STORAGE_CHUNK = 0, + uvm_cpu_physical_chunk_t *phys_chunk; + uvm_cpu_logical_chunk_t *logical_chunk = NULL; + NV_STATUS status = NV_OK; - // The uvm_va_block_t::chunks pointer points to an array of - // pointers to CPU chunks. - UVM_CPU_CHUNK_STORAGE_ARRAY, - - // The uvm_va_block_t::chunks pointer points to a - // structure of mixed (64K and 4K) chunks. - UVM_CPU_CHUNK_STORAGE_MIXED, - UVM_CPU_CHUNK_STORAGE_COUNT, -} uvm_cpu_chunk_storage_type_t; - -#define UVM_CPU_CHUNK_STORAGE_MASK 0x3 - -#define UVM_CPU_STORAGE_GET_PTR(block) ((void *)((block)->cpu.chunks & ~UVM_CPU_CHUNK_STORAGE_MASK)) -#define UVM_CPU_STORAGE_GET_TYPE(block) \ - ((uvm_cpu_chunk_storage_type_t)((block)->cpu.chunks & UVM_CPU_CHUNK_STORAGE_MASK)) - -// The maximum number of slots in the mixed chunk mode (64K + 4K chunks) is one -// more than MAX_BIG_PAGES_PER_UVM_VA_BLOCK to account for misaligned VA blocks. -#define MAX_BIG_CPU_CHUNK_SLOTS_PER_UVM_VA_BLOCK (MAX_BIG_PAGES_PER_UVM_VA_BLOCK + 1) - -#define MAX_SMALL_CHUNK_PER_BIG_SLOT (UVM_CHUNK_SIZE_64K / PAGE_SIZE) - -// This structure is used when a VA block contains 64K or a mix of 64K and 4K -// CPU chunks. -// For every 64K CPU chunks, big_chunks will have its corresponding bit set -// and the corresponding index in slots will point directly to the -// uvm_cpu_chunk_t structure. -// -// For 4K CPU chunks, the corresponding bit in big_chunks will be clear and -// the element in slots will point to an array of 16 uvm_cpu_chunk_t pointers. -typedef struct { - DECLARE_BITMAP(big_chunks, MAX_BIG_CPU_CHUNK_SLOTS_PER_UVM_VA_BLOCK); - void *slots[MAX_BIG_CPU_CHUNK_SLOTS_PER_UVM_VA_BLOCK]; -} uvm_cpu_chunk_storage_mixed_t; - -static uvm_page_index_t compute_slot_index(uvm_va_block_t *va_block, uvm_page_index_t page_index) -{ - uvm_va_block_region_t block_region = uvm_va_block_region_from_block(va_block); - size_t prefix; - uvm_page_index_t big_page_index; - - if (page_index < block_region.first || page_index >= block_region.outer) - return MAX_BIG_PAGES_PER_UVM_VA_BLOCK; - - prefix = (UVM_ALIGN_UP(va_block->start, UVM_CHUNK_SIZE_64K) - va_block->start) / PAGE_SIZE; - - if (page_index < prefix) - return 0; - - big_page_index = ((page_index - prefix) / MAX_SMALL_CHUNK_PER_BIG_SLOT) + !!prefix; - UVM_ASSERT(big_page_index < MAX_BIG_CPU_CHUNK_SLOTS_PER_UVM_VA_BLOCK); - - return big_page_index; -} - -static size_t compute_small_index(uvm_va_block_t *va_block, uvm_page_index_t page_index) -{ - size_t prefix = (UVM_ALIGN_UP(va_block->start, UVM_CHUNK_SIZE_64K) - va_block->start) / PAGE_SIZE; - - if (page_index < prefix) - return page_index; - - return (page_index - prefix) % MAX_SMALL_CHUNK_PER_BIG_SLOT; -} - -NV_STATUS uvm_cpu_chunk_insert_in_block(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) -{ - uvm_chunk_size_t chunk_size = uvm_cpu_chunk_get_size(chunk); - uvm_page_index_t big_page_index; - uvm_cpu_chunk_storage_mixed_t *mixed; - uvm_cpu_chunk_t **chunks = NULL; - - // We only want to use the bottom two bits of a pointer. - BUILD_BUG_ON(UVM_CPU_CHUNK_STORAGE_COUNT > 4); - - chunk->region = uvm_va_block_region(page_index, page_index + uvm_cpu_chunk_num_pages(chunk)); - UVM_ASSERT(chunk->region.outer <= PAGES_PER_UVM_VA_BLOCK); - - // We want to protect against two threads manipulating the VA block's CPU - // chunks at the same time. However, when a block is split, the new block's - // lock is locked without tracking. So, we can't use - // uvm_assert_mutex_locked(). - UVM_ASSERT(mutex_is_locked(&va_block->lock.m)); - - if (!va_block->cpu.chunks) { - switch (chunk_size) { - case UVM_CHUNK_SIZE_2M: - break; - case UVM_CHUNK_SIZE_64K: - mixed = uvm_kvmalloc_zero(sizeof(*mixed)); - if (!mixed) - return NV_ERR_NO_MEMORY; - - va_block->cpu.chunks = (unsigned long)mixed | UVM_CPU_CHUNK_STORAGE_MIXED; - break; - case UVM_CHUNK_SIZE_4K: - chunks = uvm_kvmalloc_zero(sizeof(*chunks) * uvm_va_block_num_cpu_pages(va_block)); - if (!chunks) - return NV_ERR_NO_MEMORY; - - va_block->cpu.chunks = (unsigned long)chunks | UVM_CPU_CHUNK_STORAGE_ARRAY; - break; - default: - return NV_ERR_INVALID_ARGUMENT; - } + if (uvm_cpu_chunk_is_logical(chunk)) { + logical_chunk = uvm_cpu_chunk_to_logical(chunk); + if (uvm_processor_mask_test(&logical_chunk->mapped_gpus, parent_gpu->id)) + return status; } - switch (UVM_CPU_STORAGE_GET_TYPE(va_block)) { - case UVM_CPU_CHUNK_STORAGE_CHUNK: - if (va_block->cpu.chunks) - return NV_ERR_INVALID_STATE; - UVM_ASSERT(chunk_size == UVM_CHUNK_SIZE_2M); - va_block->cpu.chunks = (unsigned long)chunk | UVM_CPU_CHUNK_STORAGE_CHUNK; - break; - case UVM_CPU_CHUNK_STORAGE_MIXED: - mixed = UVM_CPU_STORAGE_GET_PTR(va_block); - big_page_index = compute_slot_index(va_block, page_index); - UVM_ASSERT(big_page_index != MAX_BIG_PAGES_PER_UVM_VA_BLOCK); - UVM_ASSERT(compute_slot_index(va_block, page_index + uvm_cpu_chunk_num_pages(chunk) - 1) == big_page_index); + phys_chunk = get_physical_parent(chunk); + uvm_mutex_lock(&phys_chunk->lock); - if (test_bit(big_page_index, mixed->big_chunks)) - return NV_ERR_INVALID_STATE; + if (!uvm_processor_mask_test(&phys_chunk->gpu_mappings.dma_addrs_mask, parent_gpu->id)) { + uvm_chunk_size_t chunk_size = uvm_cpu_chunk_get_size(&phys_chunk->common); + uvm_cpu_phys_mapping_t *mapping; + NvU64 dma_addr; - if (chunk_size == UVM_CHUNK_SIZE_64K) { - mixed->slots[big_page_index] = chunk; - set_bit(big_page_index, mixed->big_chunks); - } - else { - size_t slot_index; + status = uvm_gpu_map_cpu_pages(parent_gpu, phys_chunk->common.page, chunk_size, &dma_addr); + if (status != NV_OK) + goto done; - UVM_ASSERT(chunk_size == UVM_CHUNK_SIZE_4K); - chunks = mixed->slots[big_page_index]; - - if (!chunks) { - chunks = uvm_kvmalloc_zero(sizeof(*chunks) * MAX_SMALL_CHUNK_PER_BIG_SLOT); - if (!chunks) - return NV_ERR_NO_MEMORY; - mixed->slots[big_page_index] = chunks; - } - - slot_index = compute_small_index(va_block, page_index); - chunks[slot_index] = chunk; - } - break; - case UVM_CPU_CHUNK_STORAGE_ARRAY: - chunks = UVM_CPU_STORAGE_GET_PTR(va_block); - if (chunk_size == UVM_CHUNK_SIZE_64K) { - uvm_cpu_chunk_t **subchunks = NULL; - uvm_page_index_t sub_page_index; - - mixed = uvm_kvmalloc_zero(sizeof(*mixed)); - if (!mixed) - return NV_ERR_NO_MEMORY; - - big_page_index = compute_slot_index(va_block, page_index); - UVM_ASSERT(big_page_index != MAX_BIG_PAGES_PER_UVM_VA_BLOCK); - UVM_ASSERT(compute_slot_index(va_block, page_index + uvm_cpu_chunk_num_pages(chunk) - 1) == - big_page_index); - mixed->slots[big_page_index] = chunk; - set_bit(big_page_index, mixed->big_chunks); - - for (sub_page_index = 0; sub_page_index < uvm_va_block_num_cpu_pages(va_block); sub_page_index++) { - uvm_cpu_chunk_t *subchunk = chunks[sub_page_index]; - size_t subchunk_index = compute_small_index(va_block, sub_page_index); - - if (!subchunk) - continue; - - if (!subchunks || compute_slot_index(va_block, sub_page_index) != big_page_index) { - subchunks = uvm_kvmalloc_zero(sizeof(*subchunks) * MAX_SMALL_CHUNK_PER_BIG_SLOT); - if (!subchunks) { - size_t i; - - for (i = 0; i < MAX_BIG_CPU_CHUNK_SLOTS_PER_UVM_VA_BLOCK; i++) { - if (!test_bit(i, mixed->big_chunks) && mixed->slots[i]) - uvm_kvfree(mixed->slots[i]); - } - - uvm_kvfree(mixed); - return NV_ERR_NO_MEMORY; - } - - big_page_index = compute_slot_index(va_block, sub_page_index); - UVM_ASSERT(mixed->slots[big_page_index] == NULL); - mixed->slots[big_page_index] = subchunks; - } - - subchunks[subchunk_index] = subchunk; - if (subchunk_index == MAX_SMALL_CHUNK_PER_BIG_SLOT - 1) - subchunks = NULL; - } - - va_block->cpu.chunks = (unsigned long)mixed | UVM_CPU_CHUNK_STORAGE_MIXED; - uvm_kvfree(chunks); - } - else { - chunks[page_index] = chunk; - } - - default: - break; - } - - uvm_page_mask_region_fill(&va_block->cpu.allocated, - uvm_va_block_region(page_index, page_index + uvm_cpu_chunk_num_pages(chunk))); - - return NV_OK; -} - -void uvm_cpu_chunk_remove_from_block(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) -{ - uvm_cpu_chunk_storage_mixed_t *mixed; - uvm_page_index_t big_page_index; - uvm_cpu_chunk_t **chunks; - - // We want to protect against two threads manipulating the VA block's CPU - // chunks at the same time. However, when a block is split, the new block's - // lock is locked without tracking. So, we can't use - // uvm_assert_mutex_locked(). - UVM_ASSERT(mutex_is_locked(&va_block->lock.m)); - UVM_ASSERT(va_block->cpu.chunks); - - switch (UVM_CPU_STORAGE_GET_TYPE(va_block)) { - case UVM_CPU_CHUNK_STORAGE_CHUNK: - UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) == UVM_CHUNK_SIZE_2M); - UVM_ASSERT(UVM_CPU_STORAGE_GET_PTR(va_block) == chunk); - va_block->cpu.chunks = 0; - break; - case UVM_CPU_CHUNK_STORAGE_MIXED: - UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) != UVM_CHUNK_SIZE_2M); - mixed = UVM_CPU_STORAGE_GET_PTR(va_block); - big_page_index = compute_slot_index(va_block, page_index); - UVM_ASSERT(big_page_index != MAX_BIG_PAGES_PER_UVM_VA_BLOCK); - UVM_ASSERT(mixed->slots[big_page_index] != NULL); - - if (test_bit(big_page_index, mixed->big_chunks)) { - UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) == UVM_CHUNK_SIZE_64K); - UVM_ASSERT(mixed->slots[big_page_index] == chunk); - mixed->slots[big_page_index] = NULL; - clear_bit(big_page_index, mixed->big_chunks); - } - else { - size_t slot_index; - - UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) == UVM_CHUNK_SIZE_4K); - chunks = mixed->slots[big_page_index]; - slot_index = compute_small_index(va_block, page_index); - UVM_ASSERT(chunks[slot_index] == chunk); - chunks[slot_index] = NULL; - - for (slot_index = 0; slot_index < MAX_SMALL_CHUNK_PER_BIG_SLOT; slot_index++) { - if (chunks[slot_index]) - break; - } - - if (slot_index == MAX_SMALL_CHUNK_PER_BIG_SLOT) { - uvm_kvfree(chunks); - mixed->slots[big_page_index] = NULL; - } - } - - break; - case UVM_CPU_CHUNK_STORAGE_ARRAY: - UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) == UVM_CHUNK_SIZE_4K); - chunks = UVM_CPU_STORAGE_GET_PTR(va_block); - UVM_ASSERT(chunks[page_index] == chunk); - chunks[page_index] = NULL; - break; - default: - return; - }; - - uvm_page_mask_region_clear(&va_block->cpu.allocated, chunk->region); - - if (uvm_page_mask_empty(&va_block->cpu.allocated)) { - if (UVM_CPU_STORAGE_GET_TYPE(va_block) != UVM_CPU_CHUNK_STORAGE_CHUNK) - uvm_kvfree(UVM_CPU_STORAGE_GET_PTR(va_block)); - va_block->cpu.chunks = 0; - } -} - -uvm_cpu_chunk_t *uvm_cpu_chunk_get_chunk_for_page(uvm_va_block_t *va_block, uvm_page_index_t page_index) -{ - uvm_cpu_chunk_storage_mixed_t *mixed; - uvm_cpu_chunk_t *chunk; - uvm_cpu_chunk_t **chunks; - uvm_page_index_t big_page_index; - size_t slot_index; - - if (page_index >= uvm_va_block_num_cpu_pages(va_block) || !uvm_page_mask_test(&va_block->cpu.allocated, page_index)) - return NULL; - - UVM_ASSERT(va_block->cpu.chunks); - - switch (UVM_CPU_STORAGE_GET_TYPE(va_block)) { - case UVM_CPU_CHUNK_STORAGE_CHUNK: - return UVM_CPU_STORAGE_GET_PTR(va_block); - case UVM_CPU_CHUNK_STORAGE_MIXED: - mixed = UVM_CPU_STORAGE_GET_PTR(va_block); - big_page_index = compute_slot_index(va_block, page_index); - UVM_ASSERT(big_page_index != MAX_BIG_PAGES_PER_UVM_VA_BLOCK); - UVM_ASSERT(mixed->slots[big_page_index] != NULL); - if (test_bit(big_page_index, mixed->big_chunks)) - return mixed->slots[big_page_index]; - - chunks = mixed->slots[big_page_index]; - slot_index = compute_small_index(va_block, page_index); - chunk = chunks[slot_index]; - break; - case UVM_CPU_CHUNK_STORAGE_ARRAY: - chunks = UVM_CPU_STORAGE_GET_PTR(va_block); - chunk = chunks[page_index]; - break; - default: - return NULL; - } - - UVM_ASSERT(chunk); - return chunk; -} - -NV_STATUS uvm_cpu_chunk_alloc(uvm_va_block_t *va_block, - uvm_page_index_t page_index, - struct mm_struct *mm, - uvm_cpu_chunk_t **new_chunk) -{ - uvm_va_block_test_t *block_test = uvm_va_block_get_test(va_block); - uvm_cpu_chunk_t *chunk = NULL; - NvU32 cpu_allocation_sizes; - uvm_page_mask_t zero_page_mask; - uvm_gpu_id_t id; - struct page *page = NULL; - uvm_chunk_size_t alloc_size; - uvm_va_block_region_t region; - uvm_va_space_t *va_space; - uvm_processor_mask_t uvm_lite_gpus; - gfp_t base_alloc_flags; - NV_STATUS status; - - UVM_ASSERT(new_chunk); - - // Limit the allocation sizes only to the ones supported. - cpu_allocation_sizes = uvm_cpu_chunk_get_allocation_sizes(); - - if (block_test && block_test->cpu_chunk_allocation_size_mask) - cpu_allocation_sizes &= block_test->cpu_chunk_allocation_size_mask; - - // Get a mask of all the block pages that are resident somewhere. - uvm_page_mask_zero(&zero_page_mask); - for_each_id_in_mask(id, &va_block->resident) - uvm_page_mask_or(&zero_page_mask, &zero_page_mask, uvm_va_block_resident_mask_get(va_block, id)); - - // If the VA space has a UVM-Lite GPU registered, only PAGE_SIZE allocations - // should be used in order to avoid extra copies due to dirty compound - // pages. - va_space = uvm_va_block_get_va_space(va_block); - uvm_processor_mask_andnot(&uvm_lite_gpus, &va_space->registered_gpus, &va_space->faultable_processors); - if (!uvm_processor_mask_empty(&uvm_lite_gpus)) - cpu_allocation_sizes = PAGE_SIZE; - - base_alloc_flags = (mm ? NV_UVM_GFP_FLAGS_ACCOUNT : NV_UVM_GFP_FLAGS) | GFP_HIGHUSER; - - // Attempt to allocate CPU pages with the largest physically contiguous - // size from the set of CPU chunk sizes that we can. - // This is accomplished by: - // 1. Aligning the CPU page address down to the allocation size. - // 2. Ensuring that the entire allocation region fits withing the VA - // block. - // 3. Ensuring that the region covered by the allocation is empty. - for_each_chunk_size_rev(alloc_size, cpu_allocation_sizes) { - NvU64 alloc_virt_addr; - uvm_page_mask_t scratch_page_mask; - uvm_page_index_t alloc_page_index; - gfp_t alloc_flags = base_alloc_flags; - - if (alloc_size < PAGE_SIZE) - break; - - alloc_virt_addr = UVM_ALIGN_DOWN(uvm_va_block_cpu_page_address(va_block, page_index), alloc_size); - - if (!uvm_va_block_contains_address(va_block, alloc_virt_addr) || - !uvm_va_block_contains_address(va_block, alloc_virt_addr + alloc_size - 1)) - continue; - - alloc_page_index = uvm_va_block_cpu_page_index(va_block, alloc_virt_addr); - region = uvm_va_block_region(alloc_page_index, alloc_page_index + (alloc_size / PAGE_SIZE)); - uvm_page_mask_init_from_region(&scratch_page_mask, region, NULL); - uvm_page_mask_and(&scratch_page_mask, &va_block->cpu.allocated, &scratch_page_mask); - - if (!uvm_page_mask_empty(&scratch_page_mask)) - continue; - - // For allocation sizes higher than PAGE_SIZE, use __GFP_NORETRY in - // order to avoid higher allocation latency from the kernel compacting - // memory to satisfy the request. - if (alloc_size > PAGE_SIZE) - alloc_flags |= __GFP_COMP | __GFP_NORETRY; - - // If not all pages in the allocation region are resident somewhere, - // zero out the allocated page. - // This could be wasteful if only a few pages in high-order allocation - // need to be zero'ed out but the alternative is to map single sub- - // pages one-by-one. - if (!uvm_page_mask_region_full(&zero_page_mask, region)) - alloc_flags |= __GFP_ZERO; - - page = alloc_pages(alloc_flags, get_order(alloc_size)); - if (page) { - if (alloc_flags & __GFP_ZERO) - SetPageDirty(page); - break; - } - } - - if (!page) { - status = NV_ERR_NO_MEMORY; - goto error; - } - - chunk = uvm_kvmalloc_zero(sizeof(*chunk)); - if (!chunk) { - status = NV_ERR_NO_MEMORY; - goto error; - } - - chunk->page = page; - uvm_cpu_chunk_set_size(chunk, alloc_size); - chunk->region = region; - nv_kref_init(&chunk->refcount); - uvm_spin_lock_init(&chunk->lock, UVM_LOCK_ORDER_LEAF); - if (alloc_size > PAGE_SIZE) { - chunk->dirty_bitmap = uvm_kvmalloc_zero(BITS_TO_LONGS(alloc_size / PAGE_SIZE) * sizeof(*chunk->dirty_bitmap)); - if (!chunk->dirty_bitmap) { + mapping = chunk_phys_mapping_alloc(phys_chunk, parent_gpu->id); + if (!mapping) { + uvm_gpu_unmap_cpu_pages(parent_gpu, dma_addr, chunk_size); status = NV_ERR_NO_MEMORY; - goto error; + goto done; } + + mapping->dma_addr = dma_addr; + mapping->map_count = 1; + uvm_processor_mask_set(&phys_chunk->gpu_mappings.dma_addrs_mask, parent_gpu->id); + } + else { + // The mapping count on the physical chunk is only increased when + // mapping logical chunks. + if (uvm_cpu_chunk_is_logical(chunk)) + chunk_inc_gpu_mapping(phys_chunk, parent_gpu->id); } - status = uvm_cpu_chunk_insert_in_block(va_block, chunk, chunk->region.first); - if (status != NV_OK) - goto error; +done: + uvm_mutex_unlock(&phys_chunk->lock); - if (new_chunk) - *new_chunk = chunk; - - return NV_OK; - -error: - - // If chunk has been allocated, uvm_cpu_chunk_put() will release the chunk - // and the page. Otherwise, only release the page. - if (chunk) - uvm_cpu_chunk_put(chunk); - else if (page) - __free_pages(page, get_order(alloc_size)); + if (status == NV_OK && uvm_cpu_chunk_is_logical(chunk)) + uvm_processor_mask_set(&logical_chunk->mapped_gpus, parent_gpu->id); return status; } -NV_STATUS uvm_cpu_chunk_split(uvm_va_block_t *va_block, - uvm_cpu_chunk_t *chunk, - uvm_chunk_size_t new_size, - uvm_page_index_t page_index, - uvm_cpu_chunk_t **new_chunks) +void uvm_cpu_chunk_unmap_gpu_phys(uvm_cpu_chunk_t *chunk, uvm_parent_gpu_t *parent_gpu) +{ + uvm_cpu_physical_chunk_t *phys_chunk; + uvm_cpu_logical_chunk_t *logical_chunk; + + if (uvm_cpu_chunk_is_logical(chunk)) { + logical_chunk = uvm_cpu_chunk_to_logical(chunk); + if (!uvm_processor_mask_test_and_clear(&logical_chunk->mapped_gpus, parent_gpu->id)) + return; + } + + phys_chunk = get_physical_parent(chunk); + uvm_mutex_lock(&phys_chunk->lock); + if (uvm_processor_mask_test(&phys_chunk->gpu_mappings.dma_addrs_mask, parent_gpu->id)) + chunk_dec_gpu_mapping(phys_chunk, parent_gpu->id); + + uvm_mutex_unlock(&phys_chunk->lock); +} + +NV_STATUS uvm_cpu_chunk_map_gpu(uvm_cpu_chunk_t *chunk, uvm_gpu_t *gpu) +{ + NV_STATUS status; + uvm_chunk_size_t chunk_size = uvm_cpu_chunk_get_size(chunk); + + status = cpu_chunk_map_gpu_phys(chunk, gpu->parent); + if (status != NV_OK) + return status; + + status = uvm_mmu_sysmem_map(gpu, uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent), chunk_size); + if (status != NV_OK) + uvm_cpu_chunk_unmap_gpu_phys(chunk, gpu->parent); + + return status; +} + +static struct page *uvm_cpu_chunk_alloc_page(uvm_chunk_size_t alloc_size, + uvm_cpu_chunk_alloc_flags_t alloc_flags) +{ + gfp_t kernel_alloc_flags; + struct page *page; + + UVM_ASSERT(is_power_of_2(alloc_size)); + UVM_ASSERT(alloc_size & uvm_cpu_chunk_get_allocation_sizes()); + + if (alloc_flags & UVM_CPU_CHUNK_ALLOC_FLAGS_ACCOUNT) + kernel_alloc_flags = NV_UVM_GFP_FLAGS_ACCOUNT; + else + kernel_alloc_flags = NV_UVM_GFP_FLAGS; + + kernel_alloc_flags |= GFP_HIGHUSER; + + // For allocation sizes higher than PAGE_SIZE, use __GFP_NORETRY in + // order to avoid higher allocation latency from the kernel compacting + // memory to satisfy the request. + if (alloc_size > PAGE_SIZE) + kernel_alloc_flags |= __GFP_COMP | __GFP_NORETRY; + + if (alloc_flags & UVM_CPU_CHUNK_ALLOC_FLAGS_ZERO) + kernel_alloc_flags |= __GFP_ZERO; + + page = alloc_pages(kernel_alloc_flags, get_order(alloc_size)); + if (page && (alloc_flags & UVM_CPU_CHUNK_ALLOC_FLAGS_ZERO)) + SetPageDirty(page); + + return page; +} + +static uvm_cpu_physical_chunk_t *uvm_cpu_chunk_create(uvm_chunk_size_t alloc_size) +{ + uvm_cpu_physical_chunk_t *chunk; + + chunk = uvm_kvmalloc_zero(sizeof(*chunk)); + if (!chunk) + return NULL; + + uvm_cpu_chunk_set_size(&chunk->common, alloc_size); + nv_kref_init(&chunk->common.refcount); + uvm_mutex_init(&chunk->lock, UVM_LOCK_ORDER_LEAF); + chunk->gpu_mappings.max_entries = 1; + if (alloc_size > PAGE_SIZE) { + chunk->dirty_bitmap = uvm_kvmalloc_zero(BITS_TO_LONGS(alloc_size / PAGE_SIZE) * sizeof(*chunk->dirty_bitmap)); + if (!chunk->dirty_bitmap) { + uvm_kvfree(chunk); + return NULL; + } + } + + return chunk; +} + +NV_STATUS uvm_cpu_chunk_alloc(uvm_chunk_size_t alloc_size, + uvm_cpu_chunk_alloc_flags_t alloc_flags, + uvm_cpu_chunk_t **new_chunk) +{ + uvm_cpu_physical_chunk_t *chunk; + struct page *page; + + UVM_ASSERT(new_chunk); + + page = uvm_cpu_chunk_alloc_page(alloc_size, alloc_flags); + if (!page) + return NV_ERR_NO_MEMORY; + + chunk = uvm_cpu_chunk_create(alloc_size); + if (!chunk) { + __free_pages(page, get_order(alloc_size)); + return NV_ERR_NO_MEMORY; + } + + chunk->common.type = UVM_CPU_CHUNK_TYPE_PHYSICAL; + chunk->common.page = page; + + *new_chunk = &chunk->common; + return NV_OK; +} + +NV_STATUS uvm_cpu_chunk_alloc_hmm(struct page *page, + uvm_cpu_chunk_t **new_chunk) +{ + uvm_cpu_physical_chunk_t *chunk; + + UVM_ASSERT(new_chunk); + + chunk = uvm_cpu_chunk_create(PAGE_SIZE); + if (!chunk) + return NV_ERR_NO_MEMORY; + + chunk->common.type = UVM_CPU_CHUNK_TYPE_HMM; + chunk->common.page = page; + + *new_chunk = &chunk->common; + return NV_OK; +} + +NV_STATUS uvm_cpu_chunk_split(uvm_cpu_chunk_t *chunk, uvm_cpu_chunk_t **new_chunks) { NV_STATUS status = NV_OK; - uvm_cpu_chunk_t *new_chunk; - uvm_page_index_t running_page_index = page_index; + uvm_cpu_logical_chunk_t *new_chunk; + uvm_cpu_physical_chunk_t *phys_chunk = get_physical_parent(chunk); + uvm_cpu_logical_chunk_t *logical_chunk = NULL; + uvm_processor_id_t id; + uvm_processor_mask_t *dma_map_mask; + uvm_chunk_size_t new_size; size_t num_new_chunks; size_t num_subchunk_pages; size_t i; UVM_ASSERT(chunk); - UVM_ASSERT(is_power_of_2(new_size)); - UVM_ASSERT(new_size < uvm_cpu_chunk_get_size(chunk)); UVM_ASSERT(new_chunks); + UVM_ASSERT(chunk->type != UVM_CPU_CHUNK_TYPE_HMM); + // This should never be true as HMM chunks are currently all of size + // PAGE_SIZE and can't be split and attempting to won't work as it requires + // kernel interaction. + // TODO: Bug 3368756: add support for transparent huge page (THP) + if (chunk->type == UVM_CPU_CHUNK_TYPE_HMM) + return NV_ERR_INVALID_ARGUMENT; + + // Get the largest size below the size of the input chunk. + new_size = uvm_chunk_find_prev_size(uvm_cpu_chunk_get_allocation_sizes(), uvm_cpu_chunk_get_size(chunk)); + UVM_ASSERT(new_size != UVM_CHUNK_SIZE_INVALID); num_new_chunks = uvm_cpu_chunk_get_size(chunk) / new_size; num_subchunk_pages = new_size / PAGE_SIZE; - for (i = 0; i < num_new_chunks; i++) { - uvm_page_index_t relative_page_index = running_page_index - page_index; - uvm_gpu_id_t id; + if (uvm_cpu_chunk_is_physical(chunk)) { + dma_map_mask = &phys_chunk->gpu_mappings.dma_addrs_mask; + } + else { + logical_chunk = uvm_cpu_chunk_to_logical(chunk); + dma_map_mask = &logical_chunk->mapped_gpus; + } - new_chunk = uvm_kvmalloc_zero(sizeof(*new_chunk)); + uvm_mutex_lock(&phys_chunk->lock); + for (i = 0; i < num_new_chunks; i++) { + new_chunk = uvm_kvmalloc_zero(sizeof(*logical_chunk)); if (!new_chunk) { + uvm_mutex_unlock(&phys_chunk->lock); status = NV_ERR_NO_MEMORY; goto error; } - new_chunk->page = chunk->page + relative_page_index; - new_chunk->offset = chunk->offset + relative_page_index; - new_chunk->region = uvm_va_block_region(running_page_index, running_page_index + num_subchunk_pages); - uvm_cpu_chunk_set_size(new_chunk, new_size); - nv_kref_init(&new_chunk->refcount); - - // This lock is unused for logical chunks but initialize it for - // consistency. - uvm_spin_lock_init(&new_chunk->lock, UVM_LOCK_ORDER_LEAF); + new_chunk->common.type = UVM_CPU_CHUNK_TYPE_LOGICAL; + new_chunk->common.page = chunk->page + (i * num_subchunk_pages); + uvm_cpu_chunk_set_size(&new_chunk->common, new_size); + nv_kref_init(&new_chunk->common.refcount); new_chunk->parent = chunk; uvm_cpu_chunk_get(new_chunk->parent); - - for_each_gpu_id(id) { - NvU64 parent_dma_addr = uvm_cpu_chunk_get_gpu_mapping_addr(va_block, running_page_index, chunk, id); - - if (!parent_dma_addr) - continue; - - uvm_cpu_chunk_set_gpu_mapping_addr(va_block, - relative_page_index, - new_chunk, - id, - parent_dma_addr + (relative_page_index * PAGE_SIZE)); - } - - new_chunks[i] = new_chunk; - running_page_index += num_subchunk_pages; + for_each_id_in_mask(id, dma_map_mask) + chunk_inc_gpu_mapping(phys_chunk, id); + uvm_processor_mask_copy(&new_chunk->mapped_gpus, dma_map_mask); + new_chunks[i] = &new_chunk->common; } + // Release the references that are held by the chunk being split. + for_each_id_in_mask(id, dma_map_mask) + chunk_dec_gpu_mapping(phys_chunk, id); + + // If the chunk being split is a logical chunk clear it's mapped_gpus mask. + if (uvm_cpu_chunk_is_logical(chunk)) + uvm_processor_mask_zero(&logical_chunk->mapped_gpus); + + uvm_mutex_unlock(&phys_chunk->lock); + // Drop the original reference count on the parent (from its creation). This // is done so the parent's reference count goes to 0 when all the children // are released. - uvm_cpu_chunk_put(chunk); + uvm_cpu_chunk_free(chunk); error: if (status != NV_OK) { while (i--) - uvm_cpu_chunk_put(new_chunk); + uvm_cpu_chunk_free(new_chunks[i]); } return status; } -NV_STATUS uvm_cpu_chunk_merge(uvm_va_block_t *va_block, - uvm_cpu_chunk_t **chunks, - size_t num_merge_chunks, - uvm_chunk_size_t merge_size, - uvm_cpu_chunk_t **merged_chunk) +static bool verify_merging_chunks(uvm_cpu_chunk_t **chunks, size_t num_chunks) +{ + uvm_cpu_logical_chunk_t *logical_chunk; + uvm_cpu_chunk_t *first_chunk_parent; + uvm_processor_mask_t *first_chunk_mapped_gpus; + uvm_chunk_size_t first_chunk_size; + size_t i; + + logical_chunk = uvm_cpu_chunk_to_logical(chunks[0]); + first_chunk_size = uvm_cpu_chunk_get_size(chunks[0]); + first_chunk_parent = logical_chunk->parent; + first_chunk_mapped_gpus = &logical_chunk->mapped_gpus; + + // Only chunks with the same size and parent can be merged. + for (i = 1; i < num_chunks; i++) { + UVM_ASSERT(uvm_cpu_chunk_is_logical(chunks[i])); + + logical_chunk = uvm_cpu_chunk_to_logical(chunks[i]); + UVM_ASSERT(logical_chunk->parent); + UVM_ASSERT(logical_chunk->parent == first_chunk_parent); + UVM_ASSERT(uvm_cpu_chunk_get_size(&logical_chunk->common) == first_chunk_size); + UVM_ASSERT(nv_kref_read(&logical_chunk->common.refcount) == 1); + + // For now, we require that all logical chunks to be merged have to be + // mapped on the same set of processors in order to be merged. + // + // If this requirement is relaxed in the future, the process to handle + // GPU mappings would be: + // 1. If mapped_gpus matches for all child chunks, the parent chunk's + // mapped_gpus mask is set to + // (child_mapped_gpus | parent_mapped_gpus). + // 2. If the mapped_gpus masks for the child chunks don't match: + // 2.1 All mappings to GPUs in each of child chunks' masks that are + // not also present in the parent chunk's mask are destroyed. + // 2.2 mapped_gpus mask of the parent chunk remains unmodified. + UVM_ASSERT(uvm_processor_mask_equal(&logical_chunk->mapped_gpus, first_chunk_mapped_gpus)); + } + + return true; +} + +uvm_cpu_chunk_t *uvm_cpu_chunk_merge(uvm_cpu_chunk_t **chunks) { uvm_cpu_chunk_t *parent; + uvm_cpu_logical_chunk_t *logical_chunk; + uvm_cpu_physical_chunk_t *phys_chunk; + uvm_processor_id_t id; uvm_chunk_size_t chunk_size; + uvm_chunk_size_t parent_chunk_size; + size_t num_merge_chunks; size_t i; UVM_ASSERT(chunks); - UVM_ASSERT(num_merge_chunks > 0); - UVM_ASSERT(merged_chunk); + UVM_ASSERT(!uvm_cpu_chunk_is_physical(chunks[0])); - parent = chunks[0]->parent; - if (!parent) - return NV_WARN_NOTHING_TO_DO; + logical_chunk = uvm_cpu_chunk_to_logical(chunks[0]); + parent = logical_chunk->parent; + UVM_ASSERT(parent); chunk_size = uvm_cpu_chunk_get_size(chunks[0]); + parent_chunk_size = uvm_cpu_chunk_get_size(parent); + UVM_ASSERT(IS_ALIGNED(parent_chunk_size, chunk_size)); + num_merge_chunks = parent_chunk_size / chunk_size; - UVM_ASSERT(uvm_cpu_chunk_get_size(parent) == merge_size); - UVM_ASSERT(merge_size > chunk_size); - - for (i = 1; i < num_merge_chunks; i++) { - if (chunks[i]->parent != parent || uvm_cpu_chunk_get_size(chunks[i]) != chunk_size) - return NV_ERR_INVALID_ARGUMENT; - - UVM_ASSERT(nv_kref_read(&chunks[i]->refcount) == 1); - } + // This assert will never trigger since verify_merging_chunks() always + // returns true. However, it will eliminate the call on release builds. + UVM_ASSERT(verify_merging_chunks(chunks, num_merge_chunks)); // Take a reference on the parent chunk so it doesn't get released when all // of the children are released below. uvm_cpu_chunk_get(parent); + phys_chunk = get_physical_parent(chunks[0]); + + uvm_mutex_lock(&phys_chunk->lock); + for_each_id_in_mask(id, &logical_chunk->mapped_gpus) + chunk_inc_gpu_mapping(phys_chunk, id); + + if (!uvm_cpu_chunk_is_physical(parent)) + uvm_processor_mask_copy(&uvm_cpu_chunk_to_logical(parent)->mapped_gpus, &logical_chunk->mapped_gpus); + + uvm_mutex_unlock(&phys_chunk->lock); for (i = 0; i < num_merge_chunks; i++) - uvm_cpu_chunk_put(chunks[i]); + uvm_cpu_chunk_free(chunks[i]); - *merged_chunk = parent; - - return NV_OK; -} - -static uvm_cpu_chunk_t *get_parent_cpu_chunk(uvm_cpu_chunk_t *chunk) -{ - UVM_ASSERT(chunk); - - while (chunk->parent) - chunk = chunk->parent; - - return chunk; + return parent; } // Check the CPU PTE dirty bit and if set, clear it and fill the // physical chunk's dirty bitmap. -static void check_cpu_dirty_flag(uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) +static void check_cpu_dirty_flag(uvm_cpu_physical_chunk_t *chunk, uvm_page_index_t page_index) { struct page *page; - UVM_ASSERT(!chunk->parent); - uvm_assert_spinlock_locked(&chunk->lock); + uvm_assert_mutex_locked(&chunk->lock); // Kernels prior to v4.5 used the flags within the individual pages even for - // compound pages. - page = chunk->page + page_index; - if (PageDirty(page)) { - bitmap_fill(chunk->dirty_bitmap, uvm_cpu_chunk_get_size(chunk) / PAGE_SIZE); - ClearPageDirty(page); - } -} - -static uvm_cpu_chunk_t *get_parent_and_page_index(uvm_cpu_chunk_t *chunk, uvm_page_index_t *out_page_index) -{ - uvm_cpu_chunk_t *parent; - uvm_page_index_t page_index; - - UVM_ASSERT(chunk); - UVM_ASSERT(chunk->page); - UVM_ASSERT(out_page_index); - page_index = *out_page_index; - UVM_ASSERT(chunk->region.first <= page_index && page_index < chunk->region.outer); - - page_index = chunk->offset + (page_index - chunk->region.first); - parent = get_parent_cpu_chunk(chunk); - UVM_ASSERT(page_index < uvm_cpu_chunk_get_size(parent) / PAGE_SIZE); - *out_page_index = page_index; - return parent; + // compound pages. For those kernels, we don't necessarily need the bitmap + // but using it allows for a single implementation. + page = chunk->common.page + page_index; + if (TestClearPageDirty(page)) + bitmap_fill(chunk->dirty_bitmap, uvm_cpu_chunk_num_pages(&chunk->common)); } void uvm_cpu_chunk_mark_dirty(uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) { - uvm_cpu_chunk_t *parent; + uvm_cpu_physical_chunk_t *parent; - parent = get_parent_and_page_index(chunk, &page_index); - if (uvm_cpu_chunk_get_size(parent) == PAGE_SIZE) { - SetPageDirty(parent->page); + UVM_ASSERT(page_index < uvm_cpu_chunk_num_pages(chunk)); + UVM_ASSERT(!uvm_cpu_chunk_is_hmm(chunk)); + + if (uvm_cpu_chunk_is_physical(chunk) && uvm_cpu_chunk_get_size(chunk) == PAGE_SIZE) { + SetPageDirty(chunk->page); return; } - uvm_spin_lock(&parent->lock); + parent = get_physical_parent(chunk); + if (uvm_cpu_chunk_is_logical(chunk)) { + uvm_cpu_logical_chunk_t *logical_chunk = uvm_cpu_chunk_to_logical(chunk); + page_index += cpu_chunk_get_phys_index(logical_chunk); + } + + uvm_mutex_lock(&parent->lock); set_bit(page_index, parent->dirty_bitmap); - uvm_spin_unlock(&parent->lock); + uvm_mutex_unlock(&parent->lock); } void uvm_cpu_chunk_mark_clean(uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) { - uvm_cpu_chunk_t *parent; + uvm_cpu_physical_chunk_t *parent; - parent = get_parent_and_page_index(chunk, &page_index); - if (uvm_cpu_chunk_get_size(parent) == PAGE_SIZE) { - ClearPageDirty(parent->page); + UVM_ASSERT(page_index < uvm_cpu_chunk_num_pages(chunk)); + UVM_ASSERT(!uvm_cpu_chunk_is_hmm(chunk)); + + if (uvm_cpu_chunk_is_physical(chunk) && uvm_cpu_chunk_get_size(chunk) == PAGE_SIZE) { + ClearPageDirty(chunk->page); return; } - uvm_spin_lock(&parent->lock); + parent = get_physical_parent(chunk); + if (uvm_cpu_chunk_is_logical(chunk)) { + uvm_cpu_logical_chunk_t *logical_chunk = uvm_cpu_chunk_to_logical(chunk); + page_index += cpu_chunk_get_phys_index(logical_chunk); + } + + uvm_mutex_lock(&parent->lock); check_cpu_dirty_flag(parent, page_index); clear_bit(page_index, parent->dirty_bitmap); - uvm_spin_unlock(&parent->lock); + uvm_mutex_unlock(&parent->lock); } bool uvm_cpu_chunk_is_dirty(uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) { - uvm_cpu_chunk_t *parent; + uvm_cpu_physical_chunk_t *parent; bool dirty; - parent = get_parent_and_page_index(chunk, &page_index); - if (uvm_cpu_chunk_get_size(parent) == PAGE_SIZE) - return PageDirty(parent->page); + UVM_ASSERT(page_index < uvm_cpu_chunk_num_pages(chunk)); + UVM_ASSERT(!uvm_cpu_chunk_is_hmm(chunk)); - uvm_spin_lock(&parent->lock); + if (uvm_cpu_chunk_is_physical(chunk) && uvm_cpu_chunk_get_size(chunk) == PAGE_SIZE) + return PageDirty(chunk->page); + + parent = get_physical_parent(chunk); + if (uvm_cpu_chunk_is_logical(chunk)) { + uvm_cpu_logical_chunk_t *logical_chunk = uvm_cpu_chunk_to_logical(chunk); + page_index += cpu_chunk_get_phys_index(logical_chunk); + } + + uvm_mutex_lock(&parent->lock); check_cpu_dirty_flag(parent, page_index); dirty = test_bit(page_index, parent->dirty_bitmap); - uvm_spin_unlock(&parent->lock); + uvm_mutex_unlock(&parent->lock); return dirty; } -#endif // !UVM_CPU_CHUNK_SIZE_IS_PAGE_SIZE() - -uvm_cpu_chunk_t *uvm_cpu_chunk_first_in_block(uvm_va_block_t *va_block, uvm_page_index_t *out_page_index) -{ - uvm_cpu_chunk_t *chunk = NULL; - uvm_page_index_t page_index; - uvm_va_block_region_t block_region = uvm_va_block_region_from_block(va_block); - - page_index = uvm_va_block_first_page_in_mask(block_region, &va_block->cpu.allocated); - if (page_index < block_region.outer) - chunk = uvm_cpu_chunk_get_chunk_for_page(va_block, page_index); - - if (out_page_index) - *out_page_index = page_index; - - return chunk; -} - -uvm_cpu_chunk_t *uvm_cpu_chunk_next(uvm_va_block_t *va_block, uvm_page_index_t *previous_page_index) -{ - uvm_va_block_region_t block_region; - - UVM_ASSERT(va_block); - UVM_ASSERT(previous_page_index); - - block_region = uvm_va_block_region_from_block(va_block); - *previous_page_index = uvm_va_block_next_page_in_mask(block_region, &va_block->cpu.allocated, *previous_page_index); - if (*previous_page_index == block_region.outer) - return NULL; - - return uvm_cpu_chunk_get_chunk_for_page(va_block, *previous_page_index); -} diff --git a/kernel-open/nvidia-uvm/uvm_pmm_sysmem.h b/kernel-open/nvidia-uvm/uvm_pmm_sysmem.h index cbb9ccb95..a09a003b7 100644 --- a/kernel-open/nvidia-uvm/uvm_pmm_sysmem.h +++ b/kernel-open/nvidia-uvm/uvm_pmm_sysmem.h @@ -28,6 +28,7 @@ #include "uvm_linux.h" #include "uvm_forward_decl.h" #include "uvm_lock.h" +#include "uvm_pmm_gpu.h" // Module to handle per-GPU user mappings to sysmem physical memory. Notably, // this implements a reverse map of the DMA address to {va_block, virt_addr}. @@ -176,17 +177,25 @@ size_t uvm_pmm_sysmem_mappings_dma_to_virt(uvm_pmm_sysmem_mappings_t *sysmem_map uvm_reverse_map_t *out_mappings, size_t max_out_mappings); -#define UVM_CPU_CHUNK_SIZES PAGE_SIZE +#define UVM_CPU_CHUNK_SIZES (UVM_PAGE_SIZE_2M | UVM_PAGE_SIZE_64K | PAGE_SIZE) -#if UVM_CPU_CHUNK_SIZES == PAGE_SIZE -#define UVM_CPU_CHUNK_SIZE_IS_PAGE_SIZE() 1 -typedef struct page uvm_cpu_chunk_t; +typedef enum +{ + UVM_CPU_CHUNK_ALLOC_FLAGS_NONE = 0, -#define UVM_CPU_CHUNK_PAGE_INDEX(chunk, page_index) (page_index) + // Zero the chunk. + UVM_CPU_CHUNK_ALLOC_FLAGS_ZERO = (1 << 0), -#else -#define UVM_CPU_CHUNK_SIZE_IS_PAGE_SIZE() 0 -typedef struct uvm_cpu_chunk_struct uvm_cpu_chunk_t; + // Account for the chunk in the cgroup context. + UVM_CPU_CHUNK_ALLOC_FLAGS_ACCOUNT = (1 << 1), +} uvm_cpu_chunk_alloc_flags_t; + +typedef enum +{ + UVM_CPU_CHUNK_TYPE_PHYSICAL, + UVM_CPU_CHUNK_TYPE_LOGICAL, + UVM_CPU_CHUNK_TYPE_HMM +} uvm_cpu_chunk_type_t; // CPU memory chunk descriptor. // CPU memory chunks represent a physically contiguous CPU memory @@ -197,6 +206,22 @@ typedef struct uvm_cpu_chunk_struct uvm_cpu_chunk_t; // splitting are referred to as "logical chunks". struct uvm_cpu_chunk_struct { + uvm_cpu_chunk_type_t type:2; + + // Size of the chunk. + // For chunks resulting from page allocations (physical chunks), + // this value is the size of the physical allocation. + size_t log2_size : order_base_2(UVM_CHUNK_SIZE_MASK_SIZE); + + // Chunk reference count used when a CPU chunk is split. Each + // child sub-chunk will increment the reference count of its + // parent. + // The reference count is set to 1 when the chunk is created. + // This initial reference is dropped if the chunk is split in + // order to automatically destroy the chunk when all logical + // chunks resulting from the split are destroyed. + nv_kref_t refcount; + // Pointer to the CPU page backing this CPU chunk. // For physical chunks, this will point to the head page. Physical // chunk allocation will set the reference count for the struct @@ -209,100 +234,110 @@ struct uvm_cpu_chunk_struct // reference counted, there is no need to take separate references // to the struct page for logical chunks. struct page *page; +}; - // For logical chunks, this points to the parent chunk (which - // could also be a logical chunk). For physical chunks, this - // is NULL. - uvm_cpu_chunk_t *parent; +typedef struct +{ + NvU64 dma_addr; + NvU32 map_count; +} uvm_cpu_phys_mapping_t; - // Page offset of this chunk within the physical size of - // the parent. - uvm_page_index_t offset; +typedef struct +{ + uvm_cpu_chunk_t common; - // Region within the VA block covered by this CPU chunk. - uvm_va_block_region_t region; + // Lock protecting dirty_bitmap and gpu_mappings. + uvm_mutex_t lock; - // Chunk reference count used when a CPU chunk is split. Each - // child sub-chunk will increment the reference count of its - // parent. - nv_kref_t refcount; - - // Size of the chunk. - // For chunks resulting from page allocations (physical chunks), - // this value is the size of the physical allocation. - size_t log2_size : order_base_2(UVM_CHUNK_SIZE_MASK_SIZE); - - struct { + struct + { // Per-GPU array of DMA mapping addresses for the chunk. // The DMA mapping addresses for logical chunks are adjusted // to the correct offset within the parent chunk. - union { - NvU64 static_entry; - NvU64 *dynamic_entries; + union + { + uvm_cpu_phys_mapping_t static_entry; + uvm_cpu_phys_mapping_t *dynamic_entries; }; + + // Miximum number of physical mapping entries available. + // The initial value is 1 since the static_entry is always + // available. + // When using the dynamic_entries, it holds the size of the + // dynamic_entries array. This may be more than the number + // of GPUs with active mappings. The number of active entries + // is the number of set bits in dma_addrs_mask. + size_t max_entries; + + // The set of GPU ID's that have an active physical mapping. + // Since physical mappings are shared by all GPUs under a + // parent GPU, this mask only needs to track uvm_parent_gpu_t. uvm_processor_mask_t dma_addrs_mask; } gpu_mappings; - // Lock protecting dirty_bitmap - uvm_spinlock_t lock; - // A dynamically allocated bitmap (one per PAGE_SIZE page) used // to track dirty state of each PAGE_SIZE page. - // Dirty state is tracked only by physical chunks. Therefore, - // for logical chunks this will be NULL; + // Large CPU chunks are allocated as compound pages. For such + // pages, the kernel keeps dirtiness state with a single bit + // (in the compound page head) that covers the entire compound + // page. + // + // In the case of UVM-Lite GPUs, using the dirty bit of the + // the compound page will cause performance regression due to + // the copying of extra data. We mitigate this by using this + // bitmap to track which base pages are dirty. unsigned long *dirty_bitmap; -}; -#define UVM_CPU_CHUNK_PAGE_INDEX(chunk, page_index) (chunk->region.first) -#endif // UVM_CPU_CHUNK_SIZES == PAGE_SIZE +} uvm_cpu_physical_chunk_t; + +typedef struct +{ + uvm_cpu_chunk_t common; + + // Pointer to the parent chunk (which could also be a logical chunk). + uvm_cpu_chunk_t *parent; + uvm_processor_mask_t mapped_gpus; +} uvm_cpu_logical_chunk_t; // Return the set of allowed CPU chunk allocation sizes. uvm_chunk_sizes_mask_t uvm_cpu_chunk_get_allocation_sizes(void); -// Allocate a physical CPU chunk for the specified page index and owned by -// va_block. +// Allocate a physical CPU chunk of the specified size. // -// The size of the allocated CPU chunk may be any of the allowed sizes and -// depends on several factors: -// * Allocation will be attempted in reverse order - highest to lowest - in -// order ensure that the highest possible size is used. -// * An allocation size will be used if: -// - the VA region within the block covered by the allocation size is -// aligned to that allocation size, -// - the VA block region corresponding to the allocation size is empty -// (has no previously populated pages), and -// - the system allows a page allocation of that size. -// -// If mm is not NULL, the chunks memory will be added to the mm's memory cgroup. -// -// If a CPU chunk allocation succeeds, NV_OK is returned. If new_chunk is not -// NULL it will be set to point to the newly allocated chunk. On failure, -// NV_ERR_NO_MEMORY is returned. -NV_STATUS uvm_cpu_chunk_alloc(uvm_va_block_t *va_block, - uvm_page_index_t page_index, - struct mm_struct *mm, +// If a CPU chunk allocation succeeds, NV_OK is returned. new_chunk will be set +// to point to the newly allocated chunk. On failure, NV_ERR_NO_MEMORY is +// returned. +NV_STATUS uvm_cpu_chunk_alloc(uvm_chunk_size_t alloc_size, + uvm_cpu_chunk_alloc_flags_t flags, uvm_cpu_chunk_t **new_chunk); -// Insert a CPU chunk in the va_block's storage structures. +// Allocate a HMM CPU chunk. // -// On success, NV_OK is returned. On error, -// - NV_ERR_NO_MEMORY is returned if memory allocation for any if the internal -// structures did not succeed. -// - NV_ERR_INVALID_ARGUMENT is returned if the size of the chunk to be inserted -// in invalid. -// - NV_ERR_INVALID_STATE is returned if a matching chunk already exists in the -// block. -NV_STATUS uvm_cpu_chunk_insert_in_block(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index); +// HMM chunks differ from normal CPU chunks in that the kernel has already +// allocated the page for them. This means we don't allocate any CPU memory +// here. It also means the kernel holds the reference to the page, so we +// shouldn't call put_page() when freeing the chunk. +// +// If a CPU chunk allocation succeeds NV_OK is returned and new_chunk will be +// set to point to the newly allocated chunk. On failure, NV_ERR_NO_MEMORY is +// returned. +// +// Note that the kernel retains logical ownership of the page. This means page +// properties should not be directly modified by UVM. In particular page flags +// such as PageDirty should not be modified by UVM, nor can UVM directly free +// the page. The kernel is also responsible for mapping/unmapping the page on +// the CPU. We create a CPU chunk for the page primarily to allow GPU mappings +// for the page to be created. +NV_STATUS uvm_cpu_chunk_alloc_hmm(struct page *page, + uvm_cpu_chunk_t **new_chunk); -// Remove a CPU chunk from the va_block's storage structures. -// The chunk is not freed, only removed from the block's storage structures. -void uvm_cpu_chunk_remove_from_block(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index); +// Convert a physical chunk to an HMM chunk. +static void uvm_cpu_chunk_make_hmm(uvm_cpu_chunk_t *chunk) +{ + UVM_ASSERT(chunk->type == UVM_CPU_CHUNK_TYPE_PHYSICAL); -// Return the CPU chunk backing page_index within the VA block. -// If page_index is beyond the boundary of the VA block or a CPU chunk for -// the specified page has not been allocated and/or inserted into the block, -// NULL is returned. -uvm_cpu_chunk_t *uvm_cpu_chunk_get_chunk_for_page(uvm_va_block_t *block, uvm_page_index_t page_index); + chunk->type = UVM_CPU_CHUNK_TYPE_HMM; +} uvm_chunk_size_t uvm_cpu_chunk_get_size(uvm_cpu_chunk_t *chunk); @@ -313,158 +348,105 @@ static size_t uvm_cpu_chunk_num_pages(uvm_cpu_chunk_t *chunk) return uvm_cpu_chunk_get_size(chunk) / PAGE_SIZE; } +static inline bool uvm_cpu_chunk_is_hmm(uvm_cpu_chunk_t *chunk) +{ + return chunk->type == UVM_CPU_CHUNK_TYPE_HMM; +} + static bool uvm_cpu_chunk_is_physical(uvm_cpu_chunk_t *chunk) { -#if UVM_CPU_CHUNK_SIZE_IS_PAGE_SIZE() - return true; -#else - return chunk->parent == NULL; -#endif + return (chunk->type == UVM_CPU_CHUNK_TYPE_PHYSICAL || uvm_cpu_chunk_is_hmm(chunk)); } -// Return a pointer to the struct page backing page_index within the owning -// VA block. -struct page *uvm_cpu_chunk_get_cpu_page(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index); +static bool uvm_cpu_chunk_is_logical(uvm_cpu_chunk_t *chunk) +{ + return chunk->type == UVM_CPU_CHUNK_TYPE_LOGICAL; +} -// Take a reference to the CPU chunk. -void uvm_cpu_chunk_get(uvm_cpu_chunk_t *chunk); +static uvm_cpu_physical_chunk_t *uvm_cpu_chunk_to_physical(uvm_cpu_chunk_t *chunk) +{ + UVM_ASSERT(uvm_cpu_chunk_is_physical(chunk)); + return container_of((chunk), uvm_cpu_physical_chunk_t, common); +} -// Release a reference to the CPU chunk. When the reference count -// drops to zero, the CPU chunk will be freed. Physical CPU chunks -// will also free the CPU pages backing the chunk. -void uvm_cpu_chunk_put(uvm_cpu_chunk_t *chunk); +static uvm_cpu_logical_chunk_t *uvm_cpu_chunk_to_logical(uvm_cpu_chunk_t *chunk) +{ + UVM_ASSERT(uvm_cpu_chunk_is_logical(chunk)); + return container_of((chunk), uvm_cpu_logical_chunk_t, common); +} -NV_STATUS uvm_cpu_chunk_gpu_mapping_alloc(uvm_va_block_t *va_block, uvm_gpu_id_t id); -void uvm_cpu_chunk_gpu_mapping_split(uvm_va_block_t *existing, uvm_va_block_t *new, uvm_gpu_id_t id); -void uvm_cpu_chunk_gpu_mapping_free(uvm_va_block_t *va_block, uvm_gpu_id_t id); +// Free a CPU chunk. +// This may not result in the immediate freeing of the physical pages of the +// chunk if this is a logical chunk and there are other logical chunks holding +// references to the physical chunk. +// If any DMA mappings to this chunk are still active, they are implicitly +// destroyed. +void uvm_cpu_chunk_free(uvm_cpu_chunk_t *chunk); -// Set the CPU chunk's DMA mapping address for the specified GPU ID. -NV_STATUS uvm_cpu_chunk_set_gpu_mapping_addr(uvm_va_block_t *va_block, - uvm_page_index_t page_index, - uvm_cpu_chunk_t *chunk, - uvm_gpu_id_t id, - NvU64 dma_addr); +// In some configurations such as SR-IOV heavy, a CPU chunk cannot be +// referenced using its physical address. There needs to be a kernel virtual +// mapping created. +// +// This helper function creates a DMA mapping on the GPU (see +// uvm_cpu_chunk_map_gpu()) and if necessary a kernel virtual mapping for the +// chunk. The virtual mapping persists until GPU deinitialization, such that no +// unmap functionality is exposed. For more details see uvm_mmu_sysmem_map(). +// +// Note that unlike uvm_cpu_chunk_map_gpu(), this helper requires the GPU +// object instead of the parent GPU object. +NV_STATUS uvm_cpu_chunk_map_gpu(uvm_cpu_chunk_t *chunk, uvm_gpu_t *gpu); + +// Destroy a CPU chunk's DMA mapping for the parent GPU. +// If chunk is a logical chunk, this call may not necessary destroy the DMA +// mapping of the parent physical chunk since all logical chunks share the +// parent's DMA mapping. +void uvm_cpu_chunk_unmap_gpu_phys(uvm_cpu_chunk_t *chunk, uvm_parent_gpu_t *parent_gpu); // Get the CPU chunk's DMA mapping address for the specified GPU ID. -NvU64 uvm_cpu_chunk_get_gpu_mapping_addr(uvm_va_block_t *block, - uvm_page_index_t page_index, - uvm_cpu_chunk_t *chunk, - uvm_gpu_id_t id); +// If there is no mapping for the GPU, 0 is returned. +NvU64 uvm_cpu_chunk_get_gpu_phys_addr(uvm_cpu_chunk_t *chunk, uvm_parent_gpu_t *parent_gpu); -#if !UVM_CPU_CHUNK_SIZE_IS_PAGE_SIZE() -// Split a CPU chunk into a set of CPU chunks of size new_size. -// new_size has to be one of the supported CPU chunk allocation sizes and has to -// be smaller than the current size of chunk. +// Split a CPU chunk into a set of CPU chunks of the next size down from the set +// of enabled CPU chunk sizes. // -// On success, NV_OK is returned. On failure NV_ERR_NO_MEMORY will be returned. -NV_STATUS uvm_cpu_chunk_split(uvm_va_block_t *va_block, - uvm_cpu_chunk_t *chunk, - uvm_chunk_size_t new_size, - uvm_page_index_t page_index, - uvm_cpu_chunk_t **new_chunks); +// This function expects that the chunk to be split is larger than the minimum +// enabled chunk size and that new_chunks has enough space for all chunks +// resulting from the split. +// +// On success, NV_OK is returned and the caller-provided new_chunks array will +// be filled out with the newly-created logical chunks. +// +// After a successfull split, the input chunk can no longer be used. +// +// On failure NV_ERR_NO_MEMORY will be returned. +// +// Should never be called for HMM chunks as these don't need splitting (they can +// only be PAGE_SIZE) and even if larger chunks could exist UVM could not split +// them without kernel interaction which currently isn't exported. Will return +// NV_ERR_INVALID_ARGUMENT for a HMM chunk. +// TODO: Bug 3368756: add support for transparent huge page (THP) +NV_STATUS uvm_cpu_chunk_split(uvm_cpu_chunk_t *chunk, uvm_cpu_chunk_t **new_chunks); -// Merge chunks to merge_size. -// -// All input chunks must have the same parent and size. If not, -// NV_ERR_INVALID_ARGUMENT is returned. -// -// If a merge cannot be done, NV_WARN_NOTHING_TO_DO is returned. -// -// On success, NV_OK is returned and merged_chunk is set to point to the -// merged chunk. -NV_STATUS uvm_cpu_chunk_merge(uvm_va_block_t *va_block, - uvm_cpu_chunk_t **chunks, - size_t num_merge_chunks, - uvm_chunk_size_t merge_size, - uvm_cpu_chunk_t **merged_chunk); +// Merge an array of logical chunks into their parent chunk. All chunks have to +// have the same size, parent, and set of mapped GPUs. +uvm_cpu_chunk_t *uvm_cpu_chunk_merge(uvm_cpu_chunk_t **chunks); -// Mark the CPU sub-page page_index in the CPU chunk as dirty. -// page_index has to be a page withing the chunk's region. +// Mark the page_index sub-page of the chunk as dirty. +// page_index is an offset into the chunk. +// +// Note that dirty status for HMM chunks should not be modified directly from +// UVM. Instead the kernel will mark the backing struct pages dirty either on +// fault when written to from the CPU, or when the PTE is mirrored to the GPU +// using hmm_range_fault(). void uvm_cpu_chunk_mark_dirty(uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index); -// Mark the CPU sub-pages page_index in the CPU chunk as clean. -// page_index has to be a page withing the chunk's region. +// Mark the page_index sub-page of the chunk as clean. +// page_index is an offset into the chunk. void uvm_cpu_chunk_mark_clean(uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index); -// Return true if the CPU sub-pages page_index in the CPU chunk are dirty. -// page_index has to be a page withing the chunk's region. +// Return true if the page_index base page of the CPU chunk is dirty. bool uvm_cpu_chunk_is_dirty(uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index); -#else // UVM_CPU_CHUNK_SIZE_IS_PAGE_SIZE() - -static NV_STATUS uvm_cpu_chunk_split(uvm_va_block_t *va_block, - uvm_cpu_chunk_t *chunk, - uvm_chunk_size_t new_size, - uvm_page_index_t page_index, - uvm_cpu_chunk_t **new_chunks) -{ - return NV_OK; -} - -static NV_STATUS uvm_cpu_chunk_merge(uvm_va_block_t *va_block, - uvm_cpu_chunk_t **chunk, - size_t num_merge_chunks, - uvm_chunk_size_t merge_size, - uvm_cpu_chunk_t **merged_chunk) -{ - return NV_WARN_NOTHING_TO_DO; -} - -static void uvm_cpu_chunk_mark_dirty(uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) -{ - SetPageDirty(chunk); -} - -static void uvm_cpu_chunk_mark_clean(uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) -{ - ClearPageDirty(chunk); -} - -static bool uvm_cpu_chunk_is_dirty(uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) -{ - return PageDirty(chunk); -} -#endif // !UVM_CPU_CHUNK_SIZE_IS_PAGE_SIZE() - -// Return the first CPU chunk in the block. If no CPU chunks have been -// allocated and/or inserted into the block, NULL is returned. -// If not NULL, page_index will be set to the first page of the block covered by -// the returned chunk. -uvm_cpu_chunk_t *uvm_cpu_chunk_first_in_block(uvm_va_block_t *va_block, uvm_page_index_t *out_page_index); - -// Return the next CPU chunk in the block owning chunk. -// previous_page_index is the index after which to start searching. Its value -// will be updated with the starting page index of the next chunk in the block. -uvm_cpu_chunk_t *uvm_cpu_chunk_next(uvm_va_block_t *va_block, uvm_page_index_t *previous_page_index); - -#define for_each_cpu_chunk_in_block(chunk, page_index, va_block) \ - for ((chunk) = uvm_cpu_chunk_first_in_block((va_block), &(page_index)); \ - (chunk) != NULL; \ - (page_index) += uvm_cpu_chunk_num_pages(chunk) - 1, (chunk) = uvm_cpu_chunk_next((va_block), &(page_index))) - -#define for_each_cpu_chunk_in_block_safe(chunk, page_index, next_page_index, va_block) \ - for ((chunk) = uvm_cpu_chunk_first_in_block((va_block), &(page_index)), \ - (next_page_index) = (page_index) + ((chunk) ? uvm_cpu_chunk_num_pages(chunk) : 0); \ - (chunk) != NULL; \ - (page_index) = (next_page_index) - 1, (chunk) = uvm_cpu_chunk_next((va_block), &(page_index)), \ - (next_page_index) = (page_index) + ((chunk) ? uvm_cpu_chunk_num_pages(chunk) : 0)) - -// Use a special symbol for the region so it does not replace the chunk's region -// structure member. -#define for_each_cpu_chunk_in_block_region(chunk, page_index, va_block, __region) \ - for ((page_index) = uvm_va_block_first_page_in_mask((__region), &(va_block)->cpu.allocated), \ - (chunk) = uvm_cpu_chunk_get_chunk_for_page((va_block), (page_index)); \ - (chunk) != NULL && page_index < (__region).outer; \ - (page_index) += uvm_cpu_chunk_num_pages(chunk) - 1, (chunk) = uvm_cpu_chunk_next((va_block), &(page_index)) - -#define for_each_cpu_chunk_in_block_region_safe(chunk, page_index, next_page_index, va_block, __region) \ - for ((page_index) = uvm_va_block_first_page_in_mask((__region), &(va_block)->cpu.allocated), \ - (chunk) = uvm_cpu_chunk_get_chunk_for_page((va_block), (page_index)), \ - (next_page_index) = (page_index) + (chunk ? uvm_cpu_chunk_num_pages(chunk) : 0); \ - (chunk) != NULL && page_index < (__region).outer; \ - (page_index) = (next_page_index) - 1, (chunk) = uvm_cpu_chunk_next((va_block), &(page_index)), \ - (next_page_index) = (page_index) + (chunk ? uvm_cpu_chunk_num_pages(chunk) : 0)) - static NV_STATUS uvm_test_get_cpu_chunk_allocation_sizes(UVM_TEST_GET_CPU_CHUNK_ALLOC_SIZES_PARAMS *params, struct file *filp) { diff --git a/kernel-open/nvidia-uvm/uvm_pmm_sysmem_test.c b/kernel-open/nvidia-uvm/uvm_pmm_sysmem_test.c index 5e8646951..d9f84ed52 100644 --- a/kernel-open/nvidia-uvm/uvm_pmm_sysmem_test.c +++ b/kernel-open/nvidia-uvm/uvm_pmm_sysmem_test.c @@ -30,6 +30,10 @@ #include "uvm_va_block.h" #include "uvm_va_range.h" #include "uvm_va_space.h" +#include "uvm_kvmalloc.h" +#include "uvm_hal.h" +#include "uvm_push.h" +#include "uvm_processors.h" // Pre-allocated array used for dma-to-virt translations static uvm_reverse_map_t g_sysmem_translations[PAGES_PER_UVM_VA_BLOCK]; @@ -576,3 +580,640 @@ NV_STATUS uvm_test_pmm_sysmem(UVM_TEST_PMM_SYSMEM_PARAMS *params, struct file *f return status; } + +static NV_STATUS cpu_chunk_map_on_cpu(uvm_cpu_chunk_t *chunk, void **cpu_addr) +{ + struct page **pages; + uvm_chunk_size_t chunk_size = uvm_cpu_chunk_get_size(chunk); + size_t num_pages = uvm_cpu_chunk_num_pages(chunk); + NV_STATUS status = NV_OK; + + UVM_ASSERT(cpu_addr); + + // Map the CPU chunk on the CPU. + if (chunk_size > PAGE_SIZE) { + size_t i; + + pages = uvm_kvmalloc(num_pages * sizeof(*pages)); + if (!pages) + return NV_ERR_NO_MEMORY; + + for (i = 0; i < num_pages; i++) + pages[i] = chunk->page + i; + } + else { + pages = &chunk->page; + } + + *cpu_addr = vmap(pages, num_pages, VM_MAP, PAGE_KERNEL); + if (!*cpu_addr) + status = NV_ERR_NO_MEMORY; + + if (chunk_size > PAGE_SIZE) + uvm_kvfree(pages); + + return status; +} + +static NV_STATUS test_cpu_chunk_mapping_access(uvm_cpu_chunk_t *chunk, uvm_gpu_t *gpu) +{ + NvU64 dma_addr; + uvm_gpu_phys_address_t gpu_phys_addr; + uvm_gpu_address_t gpu_addr; + uvm_push_t push; + NvU32 *cpu_addr; + uvm_chunk_size_t chunk_size = uvm_cpu_chunk_get_size(chunk); + size_t i; + NV_STATUS status = NV_OK; + + TEST_NV_CHECK_RET(cpu_chunk_map_on_cpu(chunk, (void **)&cpu_addr)); + memset(cpu_addr, 0, chunk_size); + + dma_addr = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent); + gpu_phys_addr = uvm_gpu_phys_address(UVM_APERTURE_SYS, dma_addr); + + if (uvm_mmu_gpu_needs_dynamic_sysmem_mapping(gpu)) + gpu_addr = uvm_gpu_address_virtual_from_sysmem_phys(gpu, gpu_phys_addr.address); + else + gpu_addr = uvm_gpu_address_from_phys(gpu_phys_addr); + + TEST_NV_CHECK_GOTO(uvm_push_begin_acquire(gpu->channel_manager, + UVM_CHANNEL_TYPE_GPU_TO_CPU, + NULL, + &push, + "GPU -> CPU {%s, %llx} %u bytes", + uvm_gpu_address_aperture_string(gpu_addr), + gpu_addr.address, + chunk_size), + done); + gpu->parent->ce_hal->memset_4(&push, gpu_addr, 0xdeadc0de, chunk_size); + TEST_NV_CHECK_GOTO(uvm_push_end_and_wait(&push), done); + + for (i = 0; i < chunk_size / sizeof(*cpu_addr); i++) { + if (cpu_addr[i] != 0xdeadc0de) { + UVM_TEST_PRINT("GPU write of {%s, 0x%llx} %u bytes expected pattern 0x%08x, but offset %zu is 0x%08x\n", + uvm_gpu_address_aperture_string(gpu_addr), + gpu_addr.address, + chunk_size, + 0xdeadc0de, + i * sizeof(*cpu_addr), + cpu_addr[i]); + status = NV_ERR_INVALID_STATE; + break; + } + } + +done: + vunmap(cpu_addr); + return status; +} + +static NV_STATUS test_cpu_chunk_alloc(uvm_chunk_size_t size, + uvm_cpu_chunk_alloc_flags_t flags, + uvm_cpu_chunk_t **out_chunk) +{ + uvm_cpu_chunk_t *chunk; + NV_STATUS status = NV_OK; + size_t i; + + UVM_ASSERT(out_chunk); + + // It is possible that the allocation fails due to lack of large pages + // rather than an API issue, which will result in a false negative. + // However, that should be very rare. + TEST_NV_CHECK_RET(uvm_cpu_chunk_alloc(size, flags, &chunk)); + + // Check general state of the chunk: + // - chunk should be a physical chunk, + // - chunk should have the correct size, + // - chunk should have the correct number of base pages, and + TEST_CHECK_GOTO(uvm_cpu_chunk_is_physical(chunk), done); + TEST_CHECK_GOTO(uvm_cpu_chunk_get_size(chunk) == size, done); + TEST_CHECK_GOTO(uvm_cpu_chunk_num_pages(chunk) == size / PAGE_SIZE, done); + + if (flags & UVM_CPU_CHUNK_ALLOC_FLAGS_ZERO) { + NvU64 *cpu_addr; + + TEST_NV_CHECK_GOTO(cpu_chunk_map_on_cpu(chunk, (void **)&cpu_addr), done); + for (i = 0; i < size / sizeof(*cpu_addr); i++) + TEST_CHECK_GOTO(cpu_addr[i] == 0, done); + vunmap(cpu_addr); + } + + for (i = 0; i < size / PAGE_SIZE; i++) { + if (flags & UVM_CPU_CHUNK_ALLOC_FLAGS_ZERO) + TEST_CHECK_GOTO(uvm_cpu_chunk_is_dirty(chunk, i), done); + else + TEST_CHECK_GOTO(!uvm_cpu_chunk_is_dirty(chunk, i), done); + } + +done: + if (status == NV_OK) + *out_chunk = chunk; + else + uvm_cpu_chunk_free(chunk); + + return status; +} + +static NV_STATUS test_cpu_chunk_mapping_basic_verify(uvm_gpu_t *gpu, + uvm_cpu_chunk_alloc_flags_t flags, + uvm_chunk_size_t size) +{ + uvm_cpu_chunk_t *chunk; + uvm_cpu_physical_chunk_t *phys_chunk; + NvU64 dma_addr; + NV_STATUS status = NV_OK; + + TEST_NV_CHECK_RET(test_cpu_chunk_alloc(size, flags, &chunk)); + phys_chunk = uvm_cpu_chunk_to_physical(chunk); + + // Check state of the physical chunk: + // - gpu_mappings.max_entries should be 1 (for the static entry), + // - gpu_mappings.dma_addrs_mask should be 0. + // - no GPU mapping address. + TEST_CHECK_GOTO(phys_chunk->gpu_mappings.max_entries == 1, done); + TEST_CHECK_GOTO(uvm_processor_mask_get_gpu_count(&phys_chunk->gpu_mappings.dma_addrs_mask) == 0, done); + TEST_CHECK_GOTO(uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent) == 0, done); + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(chunk, gpu), done); + + // Test basic access. + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu), done); + + // Test double map is harmless. + dma_addr = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent); + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(chunk, gpu), done); + TEST_CHECK_GOTO(uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent) == dma_addr, done); + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu), done); + + // Test unmap, remap. + uvm_cpu_chunk_unmap_gpu_phys(chunk, gpu->parent); + TEST_CHECK_GOTO(uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent) == 0, done); + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(chunk, gpu), done); + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu), done); + +done: + // Test free with mapped GPUs still works. + uvm_cpu_chunk_free(chunk); + return status;; +} + +static NV_STATUS test_cpu_chunk_mapping_basic(uvm_gpu_t *gpu, uvm_cpu_chunk_alloc_flags_t flags) +{ + uvm_chunk_sizes_mask_t chunk_sizes = uvm_cpu_chunk_get_allocation_sizes(); + uvm_chunk_size_t size; + + for_each_chunk_size(size, chunk_sizes) + TEST_NV_CHECK_RET(test_cpu_chunk_mapping_basic_verify(gpu, flags, size)); + + return NV_OK; +} + +static NV_STATUS test_cpu_chunk_mapping_array(uvm_gpu_t *gpu1, uvm_gpu_t *gpu2, uvm_gpu_t *gpu3) +{ + NV_STATUS status = NV_OK; + uvm_cpu_chunk_t *chunk; + uvm_cpu_physical_chunk_t *phys_chunk; + NvU64 dma_addr_gpu2; + + TEST_NV_CHECK_RET(test_cpu_chunk_alloc(PAGE_SIZE, UVM_CPU_CHUNK_ALLOC_FLAGS_NONE, &chunk)); + phys_chunk = uvm_cpu_chunk_to_physical(chunk); + + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(chunk, gpu2), done); + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu2), done); + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(chunk, gpu3), done); + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu2), done); + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu3), done); + dma_addr_gpu2 = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu2->parent); + uvm_cpu_chunk_unmap_gpu_phys(chunk, gpu3->parent); + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu2), done); + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(chunk, gpu1), done); + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu1), done); + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu2), done); + + // DMA mapping addresses for different GPUs live in different IOMMU spaces, + // so it would be perfectly legal for them to have the same IOVA, and even + // if they lived in the same space we freed GPU3's address so it would be + // available for reuse. + // What we need to ensure is that GPU2's address didn't change after we map + // GPU1. It's true that we may get a false negative if both addresses + // happened to alias and we had a bug in how the addresses are shifted in + // the dense array, but that's better than intermittent failure. + TEST_CHECK_GOTO(uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu2->parent) == dma_addr_gpu2, done); + +done: + uvm_cpu_chunk_free(chunk); + return status; +} + +static NV_STATUS do_test_cpu_chunk_split_and_merge(uvm_cpu_chunk_t *chunk, uvm_gpu_t *gpu) +{ + NV_STATUS status = NV_OK; + uvm_chunk_size_t size = uvm_cpu_chunk_get_size(chunk); + uvm_chunk_sizes_mask_t alloc_sizes = uvm_cpu_chunk_get_allocation_sizes(); + size_t num_split_chunks; + uvm_cpu_chunk_t **split_chunks; + uvm_cpu_chunk_t *merged_chunk; + uvm_chunk_size_t split_size; + NvU64 phys_dma_addr; + size_t map_chunk; + size_t i; + + split_size = uvm_chunk_find_prev_size(alloc_sizes, size); + UVM_ASSERT(split_size != UVM_CHUNK_SIZE_INVALID); + num_split_chunks = size / split_size; + split_chunks = uvm_kvmalloc_zero(num_split_chunks * sizeof(*split_chunks)); + + if (!split_chunks) + return NV_ERR_NO_MEMORY; + + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(chunk, gpu), done_free); + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu), done_free); + uvm_cpu_chunk_unmap_gpu_phys(chunk, gpu->parent); + + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_split(chunk, split_chunks), done_free); + TEST_CHECK_GOTO(nv_kref_read(&chunk->refcount) == num_split_chunks, done); + + for (i = 0; i < num_split_chunks; i++) { + TEST_CHECK_GOTO(split_chunks[i], done); + TEST_CHECK_GOTO(uvm_cpu_chunk_is_logical(split_chunks[i]), done); + TEST_CHECK_GOTO(uvm_cpu_chunk_get_size(split_chunks[i]) == split_size, done); + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(split_chunks[i], gpu), done); + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(split_chunks[i], gpu), done); + } + + // Test CPU chunk merging. + merged_chunk = uvm_cpu_chunk_merge(split_chunks); + TEST_CHECK_GOTO(uvm_cpu_chunk_get_size(merged_chunk) == size, done_free); + TEST_CHECK_GOTO(merged_chunk == chunk, done_free); + + // Since all logical chunks were mapped, the entire merged chunk should + // be accessible without needing to map it. + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(merged_chunk, gpu), done_free); + + // Test that GPU mappings are transferred after a split + phys_dma_addr = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent); + + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_split(chunk, split_chunks), done_free); + + for (i = 0; i < num_split_chunks; i++) { + NvU64 dma_addr; + + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(split_chunks[i], gpu), done); + dma_addr = uvm_cpu_chunk_get_gpu_phys_addr(split_chunks[i], gpu->parent); + TEST_CHECK_GOTO(dma_addr == phys_dma_addr + (i * split_size), done); + uvm_cpu_chunk_unmap_gpu_phys(split_chunks[i], gpu->parent); + } + + // Test that mapping one logical chunk does not affect others. + map_chunk = num_split_chunks / 2; + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(split_chunks[map_chunk], gpu), done); + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(split_chunks[map_chunk], gpu), done); + + for (i = 0; i < num_split_chunks; i++) { + if (i != map_chunk) + TEST_CHECK_GOTO(uvm_cpu_chunk_get_gpu_phys_addr(split_chunks[i], gpu->parent) == 0, done); + } + + if (split_size > PAGE_SIZE) { + for (i = 0; i < num_split_chunks; i++) + TEST_NV_CHECK_GOTO(do_test_cpu_chunk_split_and_merge(split_chunks[i], gpu), done); + } + + // Map all chunks before merging. + for (i = 0; i < num_split_chunks; i++) + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(split_chunks[i], gpu), done); + + // Test CPU chunk merging. + merged_chunk = uvm_cpu_chunk_merge(split_chunks); + + // At this point, all split chunks have been merged. + num_split_chunks = 0; + + TEST_CHECK_GOTO(uvm_cpu_chunk_get_size(merged_chunk) == size, done_free); + TEST_CHECK_GOTO(merged_chunk == chunk, done_free); + + // Since all logical chunks were mapped, the entire merged chunk should + // be accessible without needing to map it. + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(merged_chunk, gpu), done_free); + +done: + for (i = 0; i < num_split_chunks; i++) + uvm_cpu_chunk_free(split_chunks[i]); + +done_free: + uvm_kvfree(split_chunks); + + return status; +} + +static NV_STATUS test_cpu_chunk_split_and_merge(uvm_gpu_t *gpu) +{ + uvm_chunk_sizes_mask_t alloc_sizes = uvm_cpu_chunk_get_allocation_sizes(); + uvm_chunk_size_t size; + + size = uvm_chunk_find_next_size(alloc_sizes, PAGE_SIZE); + for_each_chunk_size_from(size, alloc_sizes) { + uvm_cpu_chunk_t *chunk; + NV_STATUS status; + + TEST_NV_CHECK_RET(test_cpu_chunk_alloc(size, UVM_CPU_CHUNK_ALLOC_FLAGS_NONE, &chunk)); + status = do_test_cpu_chunk_split_and_merge(chunk, gpu); + uvm_cpu_chunk_free(chunk); + + if (status != NV_OK) + return status; + } + + return NV_OK; +} + +static NV_STATUS test_cpu_chunk_dirty_split(uvm_cpu_chunk_t *chunk) +{ + uvm_chunk_size_t size = uvm_cpu_chunk_get_size(chunk); + uvm_chunk_size_t split_size; + uvm_chunk_sizes_mask_t alloc_sizes = uvm_cpu_chunk_get_allocation_sizes(); + uvm_cpu_chunk_t **split_chunks; + uvm_cpu_chunk_t *merged_chunk; + size_t num_pages = size / PAGE_SIZE; + size_t num_split_chunks; + size_t num_split_chunk_pages; + size_t i; + NV_STATUS status = NV_OK; + + split_size = uvm_chunk_find_prev_size(alloc_sizes, size); + UVM_ASSERT(split_size != UVM_CHUNK_SIZE_INVALID); + num_split_chunks = size / split_size; + num_split_chunk_pages = split_size / PAGE_SIZE; + split_chunks = uvm_kvmalloc_zero(num_split_chunks * sizeof(*split_chunks)); + if (!split_chunks) + return NV_ERR_NO_MEMORY; + + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_split(chunk, split_chunks), done_free); + + // The parent chunk had only the even pages set as dirty. Make sure + // that's still the case after the split. + for (i = 0; i < num_split_chunks; i++) { + uvm_page_index_t chunk_page; + + for (chunk_page = 0; chunk_page < num_split_chunk_pages; chunk_page++) { + if (((i * num_split_chunk_pages) + chunk_page) % 2) + TEST_CHECK_GOTO(!uvm_cpu_chunk_is_dirty(split_chunks[i], chunk_page), done); + else + TEST_CHECK_GOTO(uvm_cpu_chunk_is_dirty(split_chunks[i], chunk_page), done); + } + } + + if (split_size > PAGE_SIZE) { + for (i = 0; i < num_split_chunks; i++) + TEST_NV_CHECK_GOTO(test_cpu_chunk_dirty_split(split_chunks[i]), done); + } + + merged_chunk = uvm_cpu_chunk_merge(split_chunks); + num_split_chunks = 0; + for (i = 0; i < num_pages; i++) { + if (i % 2) + TEST_CHECK_GOTO(!uvm_cpu_chunk_is_dirty(merged_chunk, i), done_free); + else + TEST_CHECK_GOTO(uvm_cpu_chunk_is_dirty(merged_chunk, i), done_free); + } + +done: + for (i = 0; i < num_split_chunks; i++) + uvm_cpu_chunk_free(split_chunks[i]); + +done_free: + uvm_kvfree(split_chunks); + return status; +} + +static NV_STATUS test_cpu_chunk_dirty(uvm_gpu_t *gpu) +{ + NV_STATUS status = NV_OK; + uvm_cpu_chunk_t *chunk; + uvm_chunk_size_t size; + uvm_chunk_sizes_mask_t alloc_sizes = uvm_cpu_chunk_get_allocation_sizes(); + size_t i; + + for_each_chunk_size(size, alloc_sizes) { + uvm_cpu_physical_chunk_t *phys_chunk; + size_t num_pages; + + TEST_NV_CHECK_RET(test_cpu_chunk_alloc(size, UVM_CPU_CHUNK_ALLOC_FLAGS_NONE, &chunk)); + phys_chunk = uvm_cpu_chunk_to_physical(chunk); + num_pages = uvm_cpu_chunk_num_pages(chunk); + + for (i = 0; i < num_pages; i++) + TEST_CHECK_GOTO(!uvm_cpu_chunk_is_dirty(chunk, i), done); + + if (size > PAGE_SIZE) + TEST_CHECK_GOTO(bitmap_empty(phys_chunk->dirty_bitmap, num_pages), done); + + uvm_cpu_chunk_free(chunk); + + TEST_NV_CHECK_RET(test_cpu_chunk_alloc(size, UVM_CPU_CHUNK_ALLOC_FLAGS_ZERO, &chunk)); + phys_chunk = uvm_cpu_chunk_to_physical(chunk); + num_pages = uvm_cpu_chunk_num_pages(chunk); + + // Allocating the chunk with UVM_CPU_CHUNK_ALLOC_FLAGS_ZERO will set the + // entire chunk as dirty. + for (i = 0; i < num_pages; i++) + TEST_CHECK_GOTO(uvm_cpu_chunk_is_dirty(chunk, i), done); + + if (size > PAGE_SIZE) + TEST_CHECK_GOTO(bitmap_full(phys_chunk->dirty_bitmap, num_pages), done); + + // For chunks larger than PAGE_SIZE, marking individual pages in a + // physical chunk should not affect the entire chunk. + for (i = 0; i < num_pages; i++) { + uvm_cpu_chunk_mark_clean(chunk, i); + TEST_CHECK_GOTO(!uvm_cpu_chunk_is_dirty(chunk, i), done); + if (size > PAGE_SIZE) { + TEST_CHECK_GOTO(bitmap_empty(phys_chunk->dirty_bitmap, i + 1), done); + TEST_CHECK_GOTO(bitmap_weight(phys_chunk->dirty_bitmap, num_pages) == num_pages - (i + 1), done); + } + } + + for (i = 0; i < num_pages; i++) { + uvm_cpu_chunk_mark_dirty(chunk, i); + TEST_CHECK_GOTO(uvm_cpu_chunk_is_dirty(chunk, i), done); + if (size > PAGE_SIZE) { + TEST_CHECK_GOTO(bitmap_full(phys_chunk->dirty_bitmap, i + 1), done); + TEST_CHECK_GOTO(bitmap_weight(phys_chunk->dirty_bitmap, num_pages) == i + 1, done); + } + } + + // Leave only even pages as dirty + for (i = 1; i < num_pages; i += 2) + uvm_cpu_chunk_mark_clean(chunk, i); + + for (i = 0; i < num_pages; i++) { + if (i % 2) { + TEST_CHECK_GOTO(!uvm_cpu_chunk_is_dirty(chunk, i), done); + if (size > PAGE_SIZE) + TEST_CHECK_GOTO(!test_bit(i, phys_chunk->dirty_bitmap), done); + } + else { + TEST_CHECK_GOTO(uvm_cpu_chunk_is_dirty(chunk, i), done); + if (size > PAGE_SIZE) + TEST_CHECK_GOTO(test_bit(i, phys_chunk->dirty_bitmap), done); + } + } + + if (size > PAGE_SIZE) + TEST_NV_CHECK_GOTO(test_cpu_chunk_dirty_split(chunk), done); + +done: + uvm_cpu_chunk_free(chunk); + + if (status != NV_OK) + break; + } + + return status; +} + +NV_STATUS do_test_cpu_chunk_free(uvm_cpu_chunk_t *chunk, uvm_va_space_t *va_space, uvm_processor_mask_t *test_gpus) +{ + NV_STATUS status = NV_OK; + uvm_cpu_chunk_t **split_chunks; + uvm_chunk_sizes_mask_t alloc_sizes = uvm_cpu_chunk_get_allocation_sizes(); + size_t size = uvm_cpu_chunk_get_size(chunk); + uvm_chunk_size_t split_size = uvm_chunk_find_prev_size(alloc_sizes, size); + size_t num_split_chunks = size / split_size; + uvm_gpu_t *gpu; + size_t i; + size_t j; + + split_chunks = uvm_kvmalloc_zero(num_split_chunks * sizeof(*split_chunks)); + if (!split_chunks) { + UVM_TEST_PRINT("Failed to allocate split chunk array memory"); + status = NV_ERR_NO_MEMORY; + goto done_free; + } + + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_split(chunk, split_chunks), done_free); + + // The caller does not free the input chunk. + // So, we have to do it in this function. However, beyond this point + // the input chunk will be freed by freeing the split chunks. + chunk = NULL; + + // Map every other chunk. + // The call to uvm_cpu_chunk_unmap_gpu_phys() is here in case this is part + // of a double split (see below). In that case, the parent chunk would be + // either mapped or unmapped. + // + // If it is mapped, we have to unmap the subchunks in + // order for the mapping check below to succeed. If it is unmapped, the + // calls are noops. + for (i = 0; i < num_split_chunks; i++) { + for_each_va_space_gpu_in_mask(gpu, va_space, test_gpus) { + if (i & (1 << uvm_id_gpu_index(gpu->id))) + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(split_chunks[i], gpu), done); + else + uvm_cpu_chunk_unmap_gpu_phys(split_chunks[i], gpu->parent); + } + } + + // Do a double split if we can + if (split_size > PAGE_SIZE) { + size_t chunk_to_be_resplit; + + // Test an even (mapped) chunk. + chunk_to_be_resplit = num_split_chunks / 2; + TEST_NV_CHECK_GOTO(do_test_cpu_chunk_free(split_chunks[chunk_to_be_resplit], va_space, test_gpus), done); + + // The chunk would have been freed by do_test_cpu_chunk_free(). + split_chunks[chunk_to_be_resplit] = NULL; + + // Test an odd (unmapped) chunk. + chunk_to_be_resplit += 1; + TEST_NV_CHECK_GOTO(do_test_cpu_chunk_free(split_chunks[chunk_to_be_resplit], va_space, test_gpus), done); + split_chunks[chunk_to_be_resplit] = NULL; + } + + for (i = 0; i < num_split_chunks; i++) { + if (!split_chunks[i]) + continue; + + uvm_cpu_chunk_free(split_chunks[i]); + split_chunks[i] = NULL; + + for (j = i + 1; j < num_split_chunks; j++) { + if (!split_chunks[j]) + continue; + + TEST_CHECK_GOTO(uvm_cpu_chunk_is_logical(split_chunks[j]), done); + TEST_CHECK_GOTO(uvm_cpu_chunk_get_size(split_chunks[j]) == split_size, done); + for_each_va_space_gpu_in_mask(gpu, va_space, test_gpus) { + if (j & (1 << uvm_id_gpu_index(gpu->id))) + TEST_CHECK_GOTO(uvm_cpu_chunk_get_gpu_phys_addr(split_chunks[j], gpu->parent), done); + else + TEST_CHECK_GOTO(!uvm_cpu_chunk_get_gpu_phys_addr(split_chunks[j], gpu->parent), done); + } + } + } + +done: + for (i = 0; i < num_split_chunks; i++) { + if (split_chunks[i]) + uvm_cpu_chunk_free(split_chunks[i]); + } + +done_free: + if (chunk) + uvm_cpu_chunk_free(chunk); + + uvm_kvfree(split_chunks); + return status; +} + +NV_STATUS test_cpu_chunk_free(uvm_va_space_t *va_space, uvm_processor_mask_t *test_gpus) +{ + uvm_cpu_chunk_t *chunk; + uvm_chunk_sizes_mask_t alloc_sizes = uvm_cpu_chunk_get_allocation_sizes(); + size_t size = uvm_chunk_find_next_size(alloc_sizes, PAGE_SIZE); + + for_each_chunk_size_from(size, alloc_sizes) { + TEST_NV_CHECK_RET(test_cpu_chunk_alloc(size, UVM_CPU_CHUNK_ALLOC_FLAGS_NONE, &chunk)); + TEST_NV_CHECK_RET(do_test_cpu_chunk_free(chunk, va_space, test_gpus)); + } + + return NV_OK; +} + +NV_STATUS uvm_test_cpu_chunk_api(UVM_TEST_CPU_CHUNK_API_PARAMS *params, struct file *filp) +{ + uvm_va_space_t *va_space = uvm_va_space_get(filp); + uvm_processor_mask_t test_gpus; + uvm_gpu_t *gpu; + NV_STATUS status = NV_OK; + + uvm_va_space_down_read(va_space); + uvm_processor_mask_and(&test_gpus, + &va_space->registered_gpus, + &va_space->accessible_from[uvm_id_value(UVM_ID_CPU)]); + + for_each_va_space_gpu_in_mask(gpu, va_space, &test_gpus) { + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_basic(gpu, UVM_CPU_CHUNK_ALLOC_FLAGS_NONE), done); + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_basic(gpu, UVM_CPU_CHUNK_ALLOC_FLAGS_ZERO), done); + TEST_NV_CHECK_GOTO(test_cpu_chunk_split_and_merge(gpu), done); + TEST_NV_CHECK_GOTO(test_cpu_chunk_dirty(gpu), done); + } + + TEST_NV_CHECK_GOTO(test_cpu_chunk_free(va_space, &test_gpus), done); + + if (uvm_processor_mask_get_gpu_count(&test_gpus) >= 3) { + uvm_gpu_t *gpu2, *gpu3; + + gpu = uvm_processor_mask_find_first_va_space_gpu(&test_gpus, va_space); + gpu2 = uvm_processor_mask_find_next_va_space_gpu(&test_gpus, va_space, gpu); + gpu3 = uvm_processor_mask_find_next_va_space_gpu(&test_gpus, va_space, gpu2); + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_array(gpu, gpu2, gpu3), done); + } + +done: + uvm_va_space_up_read(va_space); + return status; +} diff --git a/kernel-open/nvidia-uvm/uvm_policy.c b/kernel-open/nvidia-uvm/uvm_policy.c index 772c14615..66f5033df 100644 --- a/kernel-open/nvidia-uvm/uvm_policy.c +++ b/kernel-open/nvidia-uvm/uvm_policy.c @@ -141,7 +141,7 @@ static NV_STATUS split_span_as_needed(uvm_va_space_t *va_space, return split_as_needed(va_space, end_addr, split_needed_cb, data); } -static bool preferred_location_is_split_needed(uvm_va_policy_t *policy, void *data) +static bool preferred_location_is_split_needed(const uvm_va_policy_t *policy, void *data) { uvm_processor_id_t processor_id; @@ -152,12 +152,13 @@ static bool preferred_location_is_split_needed(uvm_va_policy_t *policy, void *da } static NV_STATUS preferred_location_unmap_remote_pages(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context) + uvm_va_block_context_t *va_block_context, + uvm_va_block_region_t region) { NV_STATUS status = NV_OK; NV_STATUS tracker_status; uvm_tracker_t local_tracker = UVM_TRACKER_INIT(); - uvm_va_policy_t *policy = va_block_context->policy; + const uvm_va_policy_t *policy = va_block_context->policy; uvm_processor_id_t preferred_location = policy->preferred_location; uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); const uvm_page_mask_t *mapped_mask; @@ -185,7 +186,7 @@ static NV_STATUS preferred_location_unmap_remote_pages(uvm_va_block_t *va_block, status = uvm_va_block_unmap(va_block, va_block_context, preferred_location, - uvm_va_block_region_from_block(va_block), + region, &va_block_context->caller_page_mask, &local_tracker); @@ -200,17 +201,15 @@ done: } NV_STATUS uvm_va_block_set_preferred_location_locked(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context) + uvm_va_block_context_t *va_block_context, + uvm_va_block_region_t region) { uvm_assert_mutex_locked(&va_block->lock); - // TODO: Bug 1750144: remove this restriction when HMM handles setting - // the preferred location semantics instead of just recording the policy. - UVM_ASSERT(!uvm_va_block_is_hmm(va_block)); - UVM_ASSERT(va_block_context->policy == uvm_va_range_get_policy(va_block->va_range)); - uvm_va_block_mark_cpu_dirty(va_block); + if (!uvm_va_block_is_hmm(va_block)) + uvm_va_block_mark_cpu_dirty(va_block); - return preferred_location_unmap_remote_pages(va_block, va_block_context); + return preferred_location_unmap_remote_pages(va_block, va_block_context, region); } static NV_STATUS preferred_location_set(uvm_va_space_t *va_space, @@ -278,7 +277,7 @@ static NV_STATUS preferred_location_set(uvm_va_space_t *va_space, return NV_OK; } - return uvm_hmm_set_preferred_location(va_space, preferred_location, base, last_address); + return uvm_hmm_set_preferred_location(va_space, preferred_location, base, last_address, out_tracker); } NV_STATUS uvm_api_set_preferred_location(const UVM_SET_PREFERRED_LOCATION_PARAMS *params, struct file *filp) @@ -405,20 +404,22 @@ NV_STATUS uvm_api_unset_preferred_location(const UVM_UNSET_PREFERRED_LOCATION_PA return status == NV_OK ? tracker_status : status; } -static NV_STATUS va_block_set_accessed_by_locked(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, - uvm_processor_id_t processor_id, - uvm_tracker_t *out_tracker) +NV_STATUS uvm_va_block_set_accessed_by_locked(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t processor_id, + uvm_va_block_region_t region, + uvm_tracker_t *out_tracker) { NV_STATUS status; NV_STATUS tracker_status; uvm_assert_mutex_locked(&va_block->lock); + UVM_ASSERT(uvm_va_block_check_policy_is_valid(va_block, va_block_context->policy, region)); status = uvm_va_block_add_mappings(va_block, va_block_context, processor_id, - uvm_va_block_region_from_block(va_block), + region, NULL, UvmEventMapRemoteCausePolicy); @@ -432,6 +433,7 @@ NV_STATUS uvm_va_block_set_accessed_by(uvm_va_block_t *va_block, uvm_processor_id_t processor_id) { uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); + uvm_va_block_region_t region = uvm_va_block_region_from_block(va_block); NV_STATUS status; uvm_tracker_t local_tracker = UVM_TRACKER_INIT(); @@ -443,11 +445,13 @@ NV_STATUS uvm_va_block_set_accessed_by(uvm_va_block_t *va_block, if (uvm_va_policy_is_read_duplicate(va_block_context->policy, va_space)) return NV_OK; - status = UVM_VA_BLOCK_LOCK_RETRY(va_block, NULL, - va_block_set_accessed_by_locked(va_block, - va_block_context, - processor_id, - &local_tracker)); + status = UVM_VA_BLOCK_LOCK_RETRY(va_block, + NULL, + uvm_va_block_set_accessed_by_locked(va_block, + va_block_context, + processor_id, + region, + &local_tracker)); // TODO: Bug 1767224: Combine all accessed_by operations into single tracker if (status == NV_OK) @@ -463,7 +467,7 @@ typedef struct bool set_bit; } accessed_by_split_params_t; -static bool accessed_by_is_split_needed(uvm_va_policy_t *policy, void *data) +static bool accessed_by_is_split_needed(const uvm_va_policy_t *policy, void *data) { accessed_by_split_params_t *params = (accessed_by_split_params_t*)data; @@ -560,7 +564,8 @@ static NV_STATUS accessed_by_set(uvm_va_space_t *va_space, processor_id, set_bit, base, - last_address); + last_address, + &local_tracker); done: tracker_status = uvm_tracker_wait_deinit(&local_tracker); @@ -641,7 +646,7 @@ static NV_STATUS va_block_unset_read_duplication_locked(uvm_va_block_t *va_block uvm_processor_id_t processor_id; uvm_va_block_region_t block_region = uvm_va_block_region_from_block(va_block); uvm_page_mask_t *break_read_duplication_pages = &va_block_context->caller_page_mask; - uvm_va_policy_t *policy = va_block_context->policy; + const uvm_va_policy_t *policy = va_block_context->policy; uvm_processor_id_t preferred_location = policy->preferred_location; uvm_processor_mask_t accessed_by = policy->accessed_by; @@ -703,10 +708,11 @@ static NV_STATUS va_block_unset_read_duplication_locked(uvm_va_block_t *va_block // 2- Re-establish SetAccessedBy mappings for_each_id_in_mask(processor_id, &accessed_by) { - status = va_block_set_accessed_by_locked(va_block, - va_block_context, - processor_id, - out_tracker); + status = uvm_va_block_set_accessed_by_locked(va_block, + va_block_context, + processor_id, + block_region, + out_tracker); if (status != NV_OK) return status; } @@ -738,7 +744,7 @@ NV_STATUS uvm_va_block_unset_read_duplication(uvm_va_block_t *va_block, return status; } -static bool read_duplication_is_split_needed(uvm_va_policy_t *policy, void *data) +static bool read_duplication_is_split_needed(const uvm_va_policy_t *policy, void *data) { uvm_read_duplication_policy_t new_policy; diff --git a/kernel-open/nvidia-uvm/uvm_processors.h b/kernel-open/nvidia-uvm/uvm_processors.h index 39b5a0be7..6ffd293c8 100644 --- a/kernel-open/nvidia-uvm/uvm_processors.h +++ b/kernel-open/nvidia-uvm/uvm_processors.h @@ -314,6 +314,14 @@ static bool uvm_id_equal(uvm_processor_id_t id1, uvm_processor_id_t id2) return id1.val == id2.val; } +static int uvm_global_id_cmp(uvm_global_processor_id_t id1, uvm_global_processor_id_t id2) +{ + UVM_GLOBAL_ID_CHECK_BOUNDS(id1); + UVM_GLOBAL_ID_CHECK_BOUNDS(id2); + + return UVM_CMP_DEFAULT(id1.val, id2.val); +} + static bool uvm_global_id_equal(uvm_global_processor_id_t id1, uvm_global_processor_id_t id2) { UVM_GLOBAL_ID_CHECK_BOUNDS(id1); diff --git a/kernel-open/nvidia-uvm/uvm_push.c b/kernel-open/nvidia-uvm/uvm_push.c index aecffdb0f..07fd4828b 100644 --- a/kernel-open/nvidia-uvm/uvm_push.c +++ b/kernel-open/nvidia-uvm/uvm_push.c @@ -447,16 +447,16 @@ NvU64 *uvm_push_timestamp(uvm_push_t *push) return timestamp; } -bool uvm_push_method_validate(uvm_push_t *push, NvU8 subch, NvU32 method_address, NvU32 method_data) +bool uvm_push_method_is_valid(uvm_push_t *push, NvU8 subch, NvU32 method_address, NvU32 method_data) { uvm_gpu_t *gpu = uvm_push_get_gpu(push); if (subch == UVM_SUBCHANNEL_CE) - return gpu->parent->ce_hal->method_validate(push, method_address, method_data); + return gpu->parent->ce_hal->method_is_valid(push, method_address, method_data); else if (subch == UVM_SUBCHANNEL_HOST) - return gpu->parent->host_hal->method_validate(push, method_address, method_data); + return gpu->parent->host_hal->method_is_valid(push, method_address, method_data); else if (subch == UVM_SW_OBJ_SUBCHANNEL) - return gpu->parent->host_hal->sw_method_validate(push, method_address, method_data); + return gpu->parent->host_hal->sw_method_is_valid(push, method_address, method_data); UVM_ERR_PRINT("Unsupported subchannel 0x%x\n", subch); return false; diff --git a/kernel-open/nvidia-uvm/uvm_push.h b/kernel-open/nvidia-uvm/uvm_push.h index 0cd72752a..8c2915661 100644 --- a/kernel-open/nvidia-uvm/uvm_push.h +++ b/kernel-open/nvidia-uvm/uvm_push.h @@ -149,7 +149,8 @@ struct uvm_push_info_struct char description[128]; // Procedure to be called when the corresponding push is complete. - // This procedure is called with the UVM_LOCK_ORDER_CHANNEL spin lock held. + // This procedure is called with the channel pool lock held, which + // may be a spinlock. void (*on_complete)(void *); void *on_complete_data; }; @@ -438,7 +439,7 @@ static uvm_gpu_t *uvm_push_get_gpu(uvm_push_t *push) // Validate that the given method can be pushed to the underlying channel. The // method contents can be used to further validate individual fields. -bool uvm_push_method_validate(uvm_push_t *push, NvU8 subch, NvU32 method_address, NvU32 method_data); +bool uvm_push_method_is_valid(uvm_push_t *push, NvU8 subch, NvU32 method_address, NvU32 method_data); // Retrieve the push info object for a push that has already started static uvm_push_info_t *uvm_push_info_from_push(uvm_push_t *push) diff --git a/kernel-open/nvidia-uvm/uvm_push_macros.h b/kernel-open/nvidia-uvm/uvm_push_macros.h index 4c6aae4aa..4b50638ac 100644 --- a/kernel-open/nvidia-uvm/uvm_push_macros.h +++ b/kernel-open/nvidia-uvm/uvm_push_macros.h @@ -34,6 +34,7 @@ #include "clb06f.h" #define HWMASK(d, r, f) DRF_MASK(NV ## d ## _ ## r ## _ ## f) +#define HWSHIFT(d, r, f) DRF_SHIFT(NV ## d ## _ ## r ## _ ## f) #define HWSHIFTMASK(d, r, f) DRF_SHIFTMASK(NV ## d ## _ ## r ## _ ## f) #define HWSIZE(d, r, f) DRF_SIZE(NV ## d ## _ ## r ## _ ## f) #define HWCONST(d, r, f, c) DRF_DEF(d, _ ## r, _ ## f, _ ## c) @@ -92,6 +93,8 @@ #define UVM_SUBCHANNEL_C0B5 UVM_SUBCHANNEL_CE #define UVM_SUBCHANNEL_C36F UVM_SUBCHANNEL_HOST +#define UVM_SUBCHANNEL_C3B5 UVM_SUBCHANNEL_CE + #define UVM_SUBCHANNEL_C46F UVM_SUBCHANNEL_HOST #define UVM_SUBCHANNEL_C56F UVM_SUBCHANNEL_HOST @@ -143,7 +146,7 @@ do { \ __NV_PUSH_0U(subch, count, a1); \ push->next[0] = d1; \ - UVM_ASSERT_MSG(uvm_push_method_validate(push, subch, a1, d1), \ + UVM_ASSERT_MSG(uvm_push_method_is_valid(push, subch, a1, d1), \ "Method validation failed in channel %s\n", \ push->channel->name); \ ++push->next; \ @@ -153,7 +156,7 @@ do { \ __UVM_ASSERT_CONTIGUOUS_METHODS(a1, a2); \ __NV_PUSH_1U(subch, count, a1,d1); \ - UVM_ASSERT_MSG(uvm_push_method_validate(push, subch, a2, d2), \ + UVM_ASSERT_MSG(uvm_push_method_is_valid(push, subch, a2, d2), \ "Method validation failed in channel %s\n", \ push->channel->name); \ push->next[0] = d2; \ @@ -164,7 +167,7 @@ do { \ __UVM_ASSERT_CONTIGUOUS_METHODS(a2, a3); \ __NV_PUSH_2U(subch, count, a1,d1, a2,d2); \ - UVM_ASSERT_MSG(uvm_push_method_validate(push, subch, a3, d3), \ + UVM_ASSERT_MSG(uvm_push_method_is_valid(push, subch, a3, d3), \ "Method validation failed in channel %s\n", \ push->channel->name); \ push->next[0] = d3; \ @@ -175,7 +178,7 @@ do { \ __UVM_ASSERT_CONTIGUOUS_METHODS(a3, a4); \ __NV_PUSH_3U(subch, count, a1,d1, a2,d2, a3,d3); \ - UVM_ASSERT_MSG(uvm_push_method_validate(push, subch, a4, d4), \ + UVM_ASSERT_MSG(uvm_push_method_is_valid(push, subch, a4, d4), \ "Method validation failed in channel %s\n", \ push->channel->name); \ push->next[0] = d4; \ @@ -186,7 +189,7 @@ do { \ __UVM_ASSERT_CONTIGUOUS_METHODS(a4, a5); \ __NV_PUSH_4U(subch, count, a1,d1, a2,d2, a3,d3, a4,d4); \ - UVM_ASSERT_MSG(uvm_push_method_validate(push, subch, a5, d5), \ + UVM_ASSERT_MSG(uvm_push_method_is_valid(push, subch, a5, d5), \ "Method validation failed in channel %s\n", \ push->channel->name); \ push->next[0] = d5; \ @@ -197,7 +200,7 @@ do { \ __UVM_ASSERT_CONTIGUOUS_METHODS(a5, a6); \ __NV_PUSH_5U(subch, count, a1,d1, a2,d2, a3,d3, a4,d4, a5,d5); \ - UVM_ASSERT_MSG(uvm_push_method_validate(push, subch, a6, d6), \ + UVM_ASSERT_MSG(uvm_push_method_is_valid(push, subch, a6, d6), \ "Method validation failed in channel %s\n", \ push->channel->name); \ push->next[0] = d6; \ diff --git a/kernel-open/nvidia-uvm/uvm_push_test.c b/kernel-open/nvidia-uvm/uvm_push_test.c index 22a1953a9..fba988036 100644 --- a/kernel-open/nvidia-uvm/uvm_push_test.c +++ b/kernel-open/nvidia-uvm/uvm_push_test.c @@ -48,40 +48,46 @@ static NvU32 get_push_end_size(uvm_channel_t *channel) static NV_STATUS test_push_end_size(uvm_va_space_t *va_space) { - NV_STATUS status = NV_OK; uvm_gpu_t *gpu; - NvU32 push_size; - NvU32 i; for_each_va_space_gpu(gpu, va_space) { - for (i = 0; i < UVM_CHANNEL_TYPE_COUNT; ++i) { + uvm_channel_type_t type; + + for (type = 0; type < UVM_CHANNEL_TYPE_COUNT; ++type) { uvm_push_t push; - NvU32 push_end_size; - uvm_channel_type_t type = i; + NvU32 push_size_before; + NvU32 push_end_size_observed, push_end_size_expected; - status = uvm_push_begin(gpu->channel_manager, type, &push, "type %u\n", (unsigned)type); - TEST_CHECK_GOTO(status == NV_OK, done); + TEST_NV_CHECK_RET(uvm_push_begin(gpu->channel_manager, + type, + &push, + "type %s\n", + uvm_channel_type_to_string(type))); - push_end_size = get_push_end_size(push.channel); - push_size = uvm_push_get_size(&push); + push_size_before = uvm_push_get_size(&push); uvm_push_end(&push); - if (uvm_push_get_size(&push) - push_size != push_end_size) { - UVM_TEST_PRINT("push_end_size incorrect, %u instead of %u for GPU %s\n", - uvm_push_get_size(&push) - push_size, - push_end_size, + + push_end_size_expected = get_push_end_size(push.channel); + push_end_size_observed = uvm_push_get_size(&push) - push_size_before; + + if (push_end_size_observed != push_end_size_expected) { + UVM_TEST_PRINT("push_end_size incorrect, %u instead of %u on channel type %s for GPU %s\n", + push_end_size_observed, + push_end_size_expected, + uvm_channel_type_to_string(type), uvm_gpu_name(gpu)); - status = NV_ERR_INVALID_STATE; - goto done; + + // The size mismatch error gets precedence over a wait error + (void) uvm_push_wait(&push); + + return NV_ERR_INVALID_STATE; } + + TEST_NV_CHECK_RET(uvm_push_wait(&push)); } } -done: - for_each_va_space_gpu(gpu, va_space) { - uvm_channel_manager_wait(gpu->channel_manager); - } - - return status; + return NV_OK; } typedef enum { @@ -201,6 +207,7 @@ static NV_STATUS test_concurrent_pushes(uvm_va_space_t *va_space) NvU32 i; uvm_push_t *pushes; uvm_tracker_t tracker = UVM_TRACKER_INIT(); + uvm_channel_type_t channel_type = UVM_CHANNEL_TYPE_GPU_INTERNAL; // As noted above, this test does unsafe things that would be detected by // lock tracking, opt-out. @@ -213,9 +220,10 @@ static NV_STATUS test_concurrent_pushes(uvm_va_space_t *va_space) } for_each_va_space_gpu(gpu, va_space) { + for (i = 0; i < UVM_PUSH_MAX_CONCURRENT_PUSHES; ++i) { uvm_push_t *push = &pushes[i]; - status = uvm_push_begin(gpu->channel_manager, UVM_CHANNEL_TYPE_CPU_TO_GPU, push, "concurrent push %u", i); + status = uvm_push_begin(gpu->channel_manager, channel_type, push, "concurrent push %u", i); TEST_CHECK_GOTO(status == NV_OK, done); } for (i = 0; i < UVM_PUSH_MAX_CONCURRENT_PUSHES; ++i) { @@ -760,6 +768,7 @@ static NV_STATUS test_push_gpu_to_gpu(uvm_va_space_t *va_space) bool waive = true; for_each_va_space_gpu(gpu_a, va_space) { + for_each_va_space_gpu(gpu_b, va_space) { if (can_do_peer_copies(va_space, gpu_a, gpu_b)) { waive = false; diff --git a/kernel-open/nvidia-uvm/uvm_rm_mem.c b/kernel-open/nvidia-uvm/uvm_rm_mem.c index 5a6f424b7..255c70bcb 100644 --- a/kernel-open/nvidia-uvm/uvm_rm_mem.c +++ b/kernel-open/nvidia-uvm/uvm_rm_mem.c @@ -284,12 +284,12 @@ NV_STATUS uvm_rm_mem_map_gpu(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu, NvU64 gpu_ali UVM_ASSERT(rm_mem); UVM_ASSERT(gpu); - // Peer mappings not supported yet - UVM_ASSERT(rm_mem->type == UVM_RM_MEM_TYPE_SYS); - if (uvm_rm_mem_mapped_on_gpu(rm_mem, gpu)) return NV_OK; + // Peer mappings are not supported yet + UVM_ASSERT(rm_mem->type == UVM_RM_MEM_TYPE_SYS); + gpu_owner = rm_mem->gpu_owner; gpu_owner_va = uvm_rm_mem_get_gpu_uvm_va(rm_mem, gpu_owner); @@ -334,8 +334,9 @@ void uvm_rm_mem_unmap_gpu(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu) UVM_ASSERT(rm_mem); UVM_ASSERT(gpu); - // Cannot unmap from the gpu that owns the allocation. - UVM_ASSERT_MSG(rm_mem->gpu_owner != gpu, "GPU %s\n", uvm_gpu_name(gpu)); + // The GPU owner mapping remains valid until the memory is freed. + if (gpu == rm_mem->gpu_owner) + return; rm_mem_unmap_gpu(rm_mem, gpu); } diff --git a/kernel-open/nvidia-uvm/uvm_rm_mem.h b/kernel-open/nvidia-uvm/uvm_rm_mem.h index 43e0f0e13..ec087cc2f 100644 --- a/kernel-open/nvidia-uvm/uvm_rm_mem.h +++ b/kernel-open/nvidia-uvm/uvm_rm_mem.h @@ -120,8 +120,9 @@ NV_STATUS uvm_rm_mem_alloc_and_map_all(uvm_gpu_t *gpu, // Map/Unmap on UVM's internal address space of a GPU. In SR-IOV heavy the // operation is also applied on the GPU's proxy address space. // -// Supported only for sysmem (UVM_RM_MEM_TYPE_SYS). The GPU has to be different -// from the one the memory was originally allocated for. +// Mapping/unmapping on the GPU owner, or mapping on an already mapped GPU, are +// no-ops. Mapping/unmapping on a GPU different from the owner is only supported +// for system memory. // // Locking same as uvm_rm_mem_alloc() NV_STATUS uvm_rm_mem_map_gpu(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu, NvU64 gpu_alignment); diff --git a/kernel-open/nvidia-uvm/uvm_rm_mem_test.c b/kernel-open/nvidia-uvm/uvm_rm_mem_test.c index c436fe2d9..ba1e56c2d 100644 --- a/kernel-open/nvidia-uvm/uvm_rm_mem_test.c +++ b/kernel-open/nvidia-uvm/uvm_rm_mem_test.c @@ -64,10 +64,9 @@ static NV_STATUS check_alignment(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu, NvU64 ali { // Alignment requirements only apply to mappings in the UVM-owned VA space if (alignment != 0) { - bool is_proxy_va_space = false; - NvU64 gpu_va = uvm_rm_mem_get_gpu_va(rm_mem, gpu, is_proxy_va_space); + NvU64 gpu_uvm_va = uvm_rm_mem_get_gpu_uvm_va(rm_mem, gpu); - TEST_CHECK_RET(IS_ALIGNED(gpu_va, alignment)); + TEST_CHECK_RET(IS_ALIGNED(gpu_uvm_va, alignment)); } return NV_OK; @@ -76,20 +75,51 @@ static NV_STATUS check_alignment(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu, NvU64 ali static NV_STATUS map_gpu_owner(uvm_rm_mem_t *rm_mem, NvU64 alignment) { uvm_gpu_t *gpu = rm_mem->gpu_owner; + NvU64 gpu_uvm_va; + NvU64 gpu_proxy_va = 0; // The memory should have been automatically mapped in the GPU owner TEST_CHECK_RET(uvm_rm_mem_mapped_on_gpu(rm_mem, gpu)); + gpu_uvm_va = uvm_rm_mem_get_gpu_uvm_va(rm_mem, gpu); + // In SR-IOV heavy, there are two VA spaces per GPU, so there are two // mappings for a single rm_mem object on a GPU, even if the memory is // located in vidmem. - TEST_CHECK_RET(uvm_rm_mem_mapped_on_gpu_proxy(rm_mem, gpu) == uvm_gpu_uses_proxy_channel_pool(gpu)); + if (uvm_gpu_uses_proxy_channel_pool(gpu)) { + TEST_CHECK_RET(uvm_rm_mem_mapped_on_gpu_proxy(rm_mem, gpu)); + + gpu_proxy_va = uvm_rm_mem_get_gpu_proxy_va(rm_mem, gpu); + } + else { + TEST_CHECK_RET(!uvm_rm_mem_mapped_on_gpu_proxy(rm_mem, gpu)); + } TEST_NV_CHECK_RET(check_alignment(rm_mem, gpu, alignment)); - // Explicitly mapping or unmapping to the GPU that owns the allocation is - // not allowed, so the testing related to GPU owners is simpler than that of - // other GPUs. + // Mappings are not ref counted, so additional map calls are no-ops; the + // GPU VA should remain the same for all the applicable VA spaces. + TEST_NV_CHECK_RET(uvm_rm_mem_map_gpu(rm_mem, gpu, alignment)); + + TEST_CHECK_RET(gpu_uvm_va == uvm_rm_mem_get_gpu_uvm_va(rm_mem, gpu)); + + if (uvm_gpu_uses_proxy_channel_pool(gpu)) + TEST_CHECK_RET(gpu_proxy_va == uvm_rm_mem_get_gpu_proxy_va(rm_mem, gpu)); + + // Unmapping the GPU owner is a no-op + uvm_rm_mem_unmap_gpu(rm_mem, gpu); + + TEST_CHECK_RET(uvm_rm_mem_mapped_on_gpu(rm_mem, gpu)); + TEST_CHECK_RET(gpu_uvm_va == uvm_rm_mem_get_gpu_uvm_va(rm_mem, gpu)); + + if (uvm_gpu_uses_proxy_channel_pool(gpu)) { + TEST_CHECK_RET(uvm_rm_mem_mapped_on_gpu_proxy(rm_mem, gpu)); + TEST_CHECK_RET(gpu_proxy_va == uvm_rm_mem_get_gpu_proxy_va(rm_mem, gpu)); + } + else { + TEST_CHECK_RET(!uvm_rm_mem_mapped_on_gpu_proxy(rm_mem, gpu)); + } + return NV_OK; } diff --git a/kernel-open/nvidia-uvm/uvm_test.c b/kernel-open/nvidia-uvm/uvm_test.c index f4f8cc136..a8434d050 100644 --- a/kernel-open/nvidia-uvm/uvm_test.c +++ b/kernel-open/nvidia-uvm/uvm_test.c @@ -324,13 +324,12 @@ long uvm_test_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_RB_TREE_RANDOM, uvm_test_rb_tree_random); UVM_ROUTE_CMD_STACK_NO_INIT_CHECK(UVM_TEST_GET_USER_SPACE_END_ADDRESS, uvm_test_get_user_space_end_address); UVM_ROUTE_CMD_STACK_NO_INIT_CHECK(UVM_TEST_GET_CPU_CHUNK_ALLOC_SIZES, uvm_test_get_cpu_chunk_allocation_sizes); - UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_HMM_SANITY, uvm_test_hmm_sanity); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_VA_RANGE_INJECT_ADD_GPU_VA_SPACE_ERROR, uvm_test_va_range_inject_add_gpu_va_space_error); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_DESTROY_GPU_VA_SPACE_DELAY, uvm_test_destroy_gpu_va_space_delay); UVM_ROUTE_CMD_STACK_NO_INIT_CHECK(UVM_TEST_CGROUP_ACCOUNTING_SUPPORTED, uvm_test_cgroup_accounting_supported); - UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_HMM_INIT, uvm_test_hmm_init); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_SPLIT_INVALIDATE_DELAY, uvm_test_split_invalidate_delay); + UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_CPU_CHUNK_API, uvm_test_cpu_chunk_api); } return -EINVAL; diff --git a/kernel-open/nvidia-uvm/uvm_test.h b/kernel-open/nvidia-uvm/uvm_test.h index f79a52f5d..8c7b7cbe1 100644 --- a/kernel-open/nvidia-uvm/uvm_test.h +++ b/kernel-open/nvidia-uvm/uvm_test.h @@ -187,5 +187,5 @@ NV_STATUS uvm_test_tools_flush_replay_events(UVM_TEST_TOOLS_FLUSH_REPLAY_EVENTS_ NV_STATUS uvm_test_register_unload_state_buffer(UVM_TEST_REGISTER_UNLOAD_STATE_BUFFER_PARAMS *params, struct file *filp); NV_STATUS uvm_test_rb_tree_directed(UVM_TEST_RB_TREE_DIRECTED_PARAMS *params, struct file *filp); NV_STATUS uvm_test_rb_tree_random(UVM_TEST_RB_TREE_RANDOM_PARAMS *params, struct file *filp); -NV_STATUS uvm_test_hmm_sanity(UVM_TEST_HMM_SANITY_PARAMS *params, struct file *filp); +NV_STATUS uvm_test_cpu_chunk_api(UVM_TEST_CPU_CHUNK_API_PARAMS *params, struct file *filp); #endif diff --git a/kernel-open/nvidia-uvm/uvm_test_ioctl.h b/kernel-open/nvidia-uvm/uvm_test_ioctl.h index 3da600df0..eaae4ce11 100644 --- a/kernel-open/nvidia-uvm/uvm_test_ioctl.h +++ b/kernel-open/nvidia-uvm/uvm_test_ioctl.h @@ -616,6 +616,7 @@ typedef struct // Array of processors which have a virtual mapping covering lookup_address. NvProcessorUuid mapped_on[UVM_MAX_PROCESSORS]; // Out NvU32 mapping_type[UVM_MAX_PROCESSORS]; // Out + NvU64 mapping_physical_address[UVM_MAX_PROCESSORS] NV_ALIGN_BYTES(8); // Out NvU32 mapped_on_count; // Out // The size of the virtual mapping covering lookup_address on each @@ -1394,16 +1395,6 @@ typedef struct NvU32 rmStatus; // Out } UVM_TEST_GET_CPU_CHUNK_ALLOC_SIZES_PARAMS; -#define UVM_TEST_HMM_SANITY UVM_TEST_IOCTL_BASE(92) -typedef struct -{ - NvU64 hmm_address NV_ALIGN_BYTES(8); // In - NvU64 hmm_length NV_ALIGN_BYTES(8); // In - NvU64 uvm_address NV_ALIGN_BYTES(8); // In - NvU64 uvm_length NV_ALIGN_BYTES(8); // In - NV_STATUS rmStatus; // Out -} UVM_TEST_HMM_SANITY_PARAMS; - // Forces the next range covering the lookup_address to fail in // uvm_va_range_add_gpu_va_space() with an out-of-memory error. Only the next // uvm_va_range_add_gpu_va_space() will fail. Subsequent ones will succeed. @@ -1435,12 +1426,6 @@ typedef struct NV_STATUS rmStatus; // Out } UVM_TEST_CGROUP_ACCOUNTING_SUPPORTED_PARAMS; -#define UVM_TEST_HMM_INIT UVM_TEST_IOCTL_BASE(97) -typedef struct -{ - NV_STATUS rmStatus; // Out -} UVM_TEST_HMM_INIT_PARAMS; - #define UVM_TEST_SPLIT_INVALIDATE_DELAY UVM_TEST_IOCTL_BASE(98) typedef struct { @@ -1448,6 +1433,11 @@ typedef struct NV_STATUS rmStatus; // Out } UVM_TEST_SPLIT_INVALIDATE_DELAY_PARAMS; +#define UVM_TEST_CPU_CHUNK_API UVM_TEST_IOCTL_BASE(100) +typedef struct +{ + NV_STATUS rmStatus; // Out +} UVM_TEST_CPU_CHUNK_API_PARAMS; #ifdef __cplusplus } #endif diff --git a/kernel-open/nvidia-uvm/uvm_thread_context.c b/kernel-open/nvidia-uvm/uvm_thread_context.c index b54764d02..966b64429 100644 --- a/kernel-open/nvidia-uvm/uvm_thread_context.c +++ b/kernel-open/nvidia-uvm/uvm_thread_context.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2019 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -498,6 +498,7 @@ bool uvm_thread_context_add(uvm_thread_context_t *thread_context) uvm_thread_context_global_init(); thread_context->task = current; + thread_context->ignore_hmm_invalidate_va_block = NULL; table_entry = thread_context_non_interrupt_table_entry(&array_index); return thread_context_non_interrupt_add(thread_context, table_entry, array_index); } diff --git a/kernel-open/nvidia-uvm/uvm_thread_context.h b/kernel-open/nvidia-uvm/uvm_thread_context.h index bb101ca12..6be2e41f5 100644 --- a/kernel-open/nvidia-uvm/uvm_thread_context.h +++ b/kernel-open/nvidia-uvm/uvm_thread_context.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2019 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -70,6 +70,12 @@ struct uvm_thread_context_struct // This field is ignored in interrupt paths NvU32 array_index; + // Set if uvm_hmm_invalidate() callbacks should be ignored on this va_block. + // This needs to be set whenever the va_block lock is held and + // migrate_vma_setup() needs to be called since the "slow path" which + // calls try_to_migrate() doesn't pass the pgmap_owner. + uvm_va_block_t *ignore_hmm_invalidate_va_block; + // Pointer to enclosing node (if any) in red-black tree // // This field is ignored in interrupt paths diff --git a/kernel-open/nvidia-uvm/uvm_tools.c b/kernel-open/nvidia-uvm/uvm_tools.c index ea7179db7..09edb220b 100644 --- a/kernel-open/nvidia-uvm/uvm_tools.c +++ b/kernel-open/nvidia-uvm/uvm_tools.c @@ -208,7 +208,6 @@ static uvm_va_space_t *tools_event_tracker_va_space(uvm_tools_event_tracker_t *e uvm_va_space_t *va_space; UVM_ASSERT(event_tracker->uvm_file); va_space = uvm_va_space_get(event_tracker->uvm_file); - UVM_ASSERT(uvm_va_space_initialized(va_space) == NV_OK); return va_space; } @@ -1614,10 +1613,10 @@ NV_STATUS uvm_api_tools_init_event_tracker(UVM_TOOLS_INIT_EVENT_TRACKER_PARAMS * goto fail; } - status = uvm_va_space_initialized(uvm_va_space_get(event_tracker->uvm_file)); - if (status != NV_OK) { + if (!uvm_fd_va_space(event_tracker->uvm_file)) { fput(event_tracker->uvm_file); event_tracker->uvm_file = NULL; + status = NV_ERR_ILLEGAL_ACTION; goto fail; } @@ -1758,7 +1757,6 @@ static NV_STATUS tools_update_status(uvm_va_space_t *va_space) uvm_assert_rwsem_locked_write(&g_tools_va_space_list_lock); uvm_assert_rwsem_locked_write(&va_space->perf_events.lock); uvm_assert_rwsem_locked_write(&va_space->tools.lock); - UVM_ASSERT(uvm_va_space_initialized(va_space) == NV_OK); status = tools_update_perf_events_callbacks(va_space); if (status != NV_OK) @@ -2016,12 +2014,10 @@ static NV_STATUS tools_access_process_memory(uvm_va_space_t *va_space, if (status != NV_OK) goto exit; - if (is_write) { - block_context = uvm_va_block_context_alloc(mm); - if (!block_context) { - status = NV_ERR_NO_MEMORY; - goto exit; - } + block_context = uvm_va_block_context_alloc(mm); + if (!block_context) { + status = NV_ERR_NO_MEMORY; + goto exit; } stage_addr = uvm_mem_get_cpu_addr_kernel(stage_mem); @@ -2044,11 +2040,16 @@ static NV_STATUS tools_access_process_memory(uvm_va_space_t *va_space, } } + if (mm) + uvm_down_read_mmap_lock(mm); + // The RM flavor of the lock is needed to perform ECC checks. uvm_va_space_down_read_rm(va_space); - status = uvm_va_block_find_create_managed(va_space, target_va_start, &block); + status = uvm_va_block_find_create(va_space, UVM_ALIGN_DOWN(target_va_start, PAGE_SIZE), block_context, &block); if (status != NV_OK) { uvm_va_space_up_read_rm(va_space); + if (mm) + uvm_up_read_mmap_lock(mm); goto exit; } @@ -2070,6 +2071,22 @@ static NV_STATUS tools_access_process_memory(uvm_va_space_t *va_space, status = uvm_mem_map_gpu_kernel(stage_mem, gpu); if (status != NV_OK) { uvm_va_space_up_read_rm(va_space); + if (mm) + uvm_up_read_mmap_lock(mm); + goto exit; + } + } + + // Make sure a CPU resident page has an up to date struct page pointer. + if (uvm_va_block_is_hmm(block)) { + status = uvm_hmm_va_block_update_residency_info(block, + mm, + UVM_ALIGN_DOWN(target_va_start, PAGE_SIZE), + true); + if (status != NV_OK) { + uvm_va_space_up_read_rm(va_space); + if (mm) + uvm_up_read_mmap_lock(mm); goto exit; } } @@ -2082,6 +2099,9 @@ static NV_STATUS tools_access_process_memory(uvm_va_space_t *va_space, status = uvm_global_mask_check_ecc_error(global_gpus); uvm_va_space_up_read_rm(va_space); + if (mm) + uvm_up_read_mmap_lock(mm); + if (status != NV_OK) goto exit; diff --git a/kernel-open/nvidia-uvm/uvm_user_channel.c b/kernel-open/nvidia-uvm/uvm_user_channel.c index 937f19d7e..757a263be 100644 --- a/kernel-open/nvidia-uvm/uvm_user_channel.c +++ b/kernel-open/nvidia-uvm/uvm_user_channel.c @@ -984,14 +984,13 @@ NV_STATUS uvm_test_check_channel_va_space(UVM_TEST_CHECK_CHANNEL_VA_SPACE_PARAMS goto out; } - va_space = uvm_va_space_get(va_space_filp); - uvm_va_space_down_read(va_space); - - // We can do this query outside of the lock, but doing it within the lock - // simplifies error handling. - status = uvm_va_space_initialized(va_space); - if (status != NV_OK) + va_space = uvm_fd_va_space(va_space_filp); + if (!va_space) { + status = NV_ERR_INVALID_ARGUMENT; goto out; + } + + uvm_va_space_down_read(va_space); gpu = uvm_va_space_get_gpu_by_uuid(va_space, ¶ms->gpu_uuid); if (!gpu || !uvm_processor_mask_test(&va_space->faultable_processors, gpu->id)) { diff --git a/kernel-open/nvidia-uvm/uvm_va_block.c b/kernel-open/nvidia-uvm/uvm_va_block.c index 7b6d8de2c..ef37013ed 100644 --- a/kernel-open/nvidia-uvm/uvm_va_block.c +++ b/kernel-open/nvidia-uvm/uvm_va_block.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -78,7 +78,7 @@ MODULE_PARM_DESC(uvm_exp_gpu_cache_sysmem, "Force caching for mappings to system memory. " "This is an experimental parameter that may cause correctness issues if used."); -static void block_deferred_eviction_mappings_entry(void *args); +static void block_add_eviction_mappings_entry(void *args); uvm_va_space_t *uvm_va_block_get_va_space_maybe_dead(uvm_va_block_t *va_block) { @@ -106,15 +106,15 @@ uvm_va_space_t *uvm_va_block_get_va_space(uvm_va_block_t *va_block) } bool uvm_va_block_check_policy_is_valid(uvm_va_block_t *va_block, - uvm_va_policy_t *policy, + const uvm_va_policy_t *policy, uvm_va_block_region_t region) { uvm_assert_mutex_locked(&va_block->lock); if (uvm_va_block_is_hmm(va_block)) { - uvm_va_policy_node_t *node; + const uvm_va_policy_node_t *node; - if (policy == &uvm_va_policy_default) { + if (uvm_va_policy_is_default(policy)) { // There should only be the default policy within the region. node = uvm_va_policy_node_iter_first(va_block, uvm_va_block_region_start(va_block, region), @@ -180,7 +180,7 @@ static bool is_uvm_fault_force_sysmem_set(void) return uvm_enable_builtin_tests && uvm_fault_force_sysmem != 0; } -static bool va_space_map_remote_on_eviction(uvm_va_space_t *va_space) +bool uvm_va_space_map_remote_on_eviction(uvm_va_space_t *va_space) { return uvm_perf_map_remote_on_eviction && uvm_va_space_has_access_counter_migrations(va_space); @@ -208,78 +208,338 @@ void uvm_va_block_retry_init(uvm_va_block_retry_t *retry) INIT_LIST_HEAD(&retry->free_chunks); } -static bool block_verify_cpu_chunks(uvm_va_block_t *block) +// The bottom bit of uvm_va_block_t::chunks is used to indicate how CPU chunks +// are stored. +// +// CPU chunk storage is handled in three different ways depending on the +// type of chunks the VA block owns. This is done to minimize the memory +// required to hold metadata. +typedef enum +{ + // The uvm_va_block_t::chunk pointer points to a single 2MB + // CPU chunk. + UVM_CPU_CHUNK_STORAGE_CHUNK = 0, + + // The uvm_va_block_t::chunks pointer points to a + // structure of mixed (64K and 4K) chunks. + UVM_CPU_CHUNK_STORAGE_MIXED, + UVM_CPU_CHUNK_STORAGE_COUNT, +} uvm_cpu_chunk_storage_type_t; + +#define UVM_CPU_CHUNK_STORAGE_MASK 0x1 + +// The maximum number of slots in the mixed chunk mode (64K + 4K chunks) is +// MAX_BIG_PAGES_PER_UVM_VA_BLOCK. Any leading/trailing misaligned pages will +// be stored in the first/last entry, respectively. +#define MAX_BIG_CPU_CHUNK_SLOTS_PER_UVM_VA_BLOCK MAX_BIG_PAGES_PER_UVM_VA_BLOCK + +#define MAX_SMALL_CHUNKS_PER_BIG_SLOT (UVM_MIN_BIG_PAGE_SIZE / PAGE_SIZE) + +// This structure is used when a VA block contains 64K or a mix of 64K and 4K +// CPU chunks. +// For every 64K CPU chunks, big_chunks will have its corresponding bit set +// and the corresponding index in slots will point directly to the +// uvm_cpu_chunk_t structure. +// +// For 4K CPU chunks, the corresponding bit in big_chunks will be clear and +// the element in slots will point to an array of 16 uvm_cpu_chunk_t pointers. +typedef struct { + DECLARE_BITMAP(big_chunks, MAX_BIG_CPU_CHUNK_SLOTS_PER_UVM_VA_BLOCK); + void *slots[MAX_BIG_CPU_CHUNK_SLOTS_PER_UVM_VA_BLOCK]; +} uvm_cpu_chunk_storage_mixed_t; + +static uvm_va_block_region_t uvm_cpu_chunk_block_region(uvm_va_block_t *va_block, + uvm_cpu_chunk_t *chunk, + uvm_page_index_t page_index) +{ + UVM_ASSERT(chunk); + return uvm_va_block_chunk_region(va_block, uvm_cpu_chunk_get_size(chunk), page_index); +} + +static void *uvm_cpu_storage_get_ptr(uvm_va_block_t *block) +{ + return (void *)(block->cpu.chunks & ~UVM_CPU_CHUNK_STORAGE_MASK); +} + +static uvm_cpu_chunk_storage_type_t uvm_cpu_storage_get_type(uvm_va_block_t *block) +{ + return block->cpu.chunks & UVM_CPU_CHUNK_STORAGE_MASK; +} + +static uvm_page_index_t compute_page_prefix(uvm_va_block_t *va_block, uvm_chunk_size_t size) +{ + return (UVM_ALIGN_UP(va_block->start, size) - va_block->start) / PAGE_SIZE; +} + +static size_t compute_slot_index(uvm_va_block_t *va_block, uvm_page_index_t page_index) +{ + uvm_va_block_region_t block_region = uvm_va_block_region_from_block(va_block); + uvm_page_index_t prefix; + size_t slot_index; + + UVM_ASSERT(page_index < block_region.outer); + prefix = compute_page_prefix(va_block, UVM_PAGE_SIZE_64K); + + if (page_index < prefix) + return 0; + + slot_index = ((page_index - prefix) / MAX_SMALL_CHUNKS_PER_BIG_SLOT) + !!prefix; + UVM_ASSERT(slot_index < MAX_BIG_CPU_CHUNK_SLOTS_PER_UVM_VA_BLOCK); + + return slot_index; +} + +static size_t compute_small_index(uvm_va_block_t *va_block, uvm_page_index_t page_index) +{ + size_t prefix = compute_page_prefix(va_block, UVM_PAGE_SIZE_64K); + + if (page_index < prefix) + return page_index; + + return (page_index - prefix) % MAX_SMALL_CHUNKS_PER_BIG_SLOT; +} + +NV_STATUS uvm_cpu_chunk_insert_in_block(uvm_va_block_t *va_block, + uvm_cpu_chunk_t *chunk, + uvm_page_index_t page_index) +{ + uvm_chunk_size_t chunk_size = uvm_cpu_chunk_get_size(chunk); + uvm_va_block_region_t chunk_region = uvm_va_block_region(page_index, page_index + uvm_cpu_chunk_num_pages(chunk)); + size_t slot_index; + uvm_cpu_chunk_storage_mixed_t *mixed; + uvm_cpu_chunk_t **chunks = NULL; + + // We only want to use the bottom bit of a pointer. + BUILD_BUG_ON(UVM_CPU_CHUNK_STORAGE_COUNT > 2); + + // We want to protect against two threads manipulating the VA block's CPU + // chunks at the same time. However, when a block is split, the new block's + // lock is locked without tracking. So, we can't use + // uvm_assert_mutex_locked(). + UVM_ASSERT(mutex_is_locked(&va_block->lock.m)); + + if (chunk_size == UVM_CHUNK_SIZE_2M) { + UVM_ASSERT(uvm_va_block_size(va_block) == UVM_PAGE_SIZE_2M); + UVM_ASSERT(!va_block->cpu.chunks); + va_block->cpu.chunks = (unsigned long)chunk | UVM_CPU_CHUNK_STORAGE_CHUNK; + } + else { + if (!va_block->cpu.chunks) { + mixed = uvm_kvmalloc_zero(sizeof(*mixed)); + if (!mixed) + return NV_ERR_NO_MEMORY; + + va_block->cpu.chunks = (unsigned long)mixed | UVM_CPU_CHUNK_STORAGE_MIXED; + } + + UVM_ASSERT(uvm_cpu_storage_get_type(va_block) == UVM_CPU_CHUNK_STORAGE_MIXED); + mixed = uvm_cpu_storage_get_ptr(va_block); + slot_index = compute_slot_index(va_block, page_index); + UVM_ASSERT(compute_slot_index(va_block, page_index + uvm_cpu_chunk_num_pages(chunk) - 1) == slot_index); + UVM_ASSERT(!test_bit(slot_index, mixed->big_chunks)); + + if (chunk_size == UVM_CHUNK_SIZE_64K) { + mixed->slots[slot_index] = chunk; + set_bit(slot_index, mixed->big_chunks); + } + else { + size_t small_index; + + UVM_ASSERT(chunk_size == UVM_CHUNK_SIZE_4K); + chunks = mixed->slots[slot_index]; + + if (!chunks) { + chunks = uvm_kvmalloc_zero(sizeof(*chunks) * MAX_SMALL_CHUNKS_PER_BIG_SLOT); + if (!chunks) + return NV_ERR_NO_MEMORY; + mixed->slots[slot_index] = chunks; + } + + small_index = compute_small_index(va_block, page_index); + chunks[small_index] = chunk; + } + } + + uvm_page_mask_region_fill(&va_block->cpu.allocated, chunk_region); + return NV_OK; +} + +uvm_cpu_chunk_t *uvm_cpu_chunk_get_chunk_for_page(uvm_va_block_t *va_block, uvm_page_index_t page_index) +{ + uvm_cpu_chunk_storage_mixed_t *mixed; + uvm_cpu_chunk_t *chunk; + uvm_cpu_chunk_t **chunks; + size_t slot_index; + + UVM_ASSERT(page_index < uvm_va_block_num_cpu_pages(va_block)); + if (!uvm_page_mask_test(&va_block->cpu.allocated, page_index)) + return NULL; + + UVM_ASSERT(va_block->cpu.chunks); + + if (uvm_cpu_storage_get_type(va_block) == UVM_CPU_CHUNK_STORAGE_CHUNK) { + return uvm_cpu_storage_get_ptr(va_block); + } + else { + mixed = uvm_cpu_storage_get_ptr(va_block); + slot_index = compute_slot_index(va_block, page_index); + UVM_ASSERT(mixed->slots[slot_index] != NULL); + if (test_bit(slot_index, mixed->big_chunks)) + return mixed->slots[slot_index]; + + chunks = mixed->slots[slot_index]; + chunk = chunks[compute_small_index(va_block, page_index)]; + } + + UVM_ASSERT(chunk); + return chunk; +} + +void uvm_cpu_chunk_remove_from_block(uvm_va_block_t *va_block, + uvm_page_index_t page_index) +{ + uvm_cpu_chunk_storage_mixed_t *mixed; + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(va_block, page_index); + uvm_va_block_region_t chunk_region = uvm_cpu_chunk_block_region(va_block, chunk, page_index); + size_t slot_index; + uvm_cpu_chunk_t **chunks; + + // We want to protect against two threads manipulating the VA block's CPU + // chunks at the same time. However, when a block is split, the new block's + // lock is locked without tracking. So, we can't use + // uvm_assert_mutex_locked(). + UVM_ASSERT(mutex_is_locked(&va_block->lock.m)); + UVM_ASSERT(va_block->cpu.chunks); + UVM_ASSERT(uvm_va_block_region_num_pages(chunk_region) == uvm_cpu_chunk_num_pages(chunk)); + + if (uvm_cpu_storage_get_type(va_block) == UVM_CPU_CHUNK_STORAGE_CHUNK) { + UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) == UVM_CHUNK_SIZE_2M); + UVM_ASSERT(uvm_cpu_storage_get_ptr(va_block) == chunk); + va_block->cpu.chunks = 0; + } + else { + UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) != UVM_CHUNK_SIZE_2M); + mixed = uvm_cpu_storage_get_ptr(va_block); + slot_index = compute_slot_index(va_block, page_index); + UVM_ASSERT(mixed->slots[slot_index] != NULL); + + if (test_bit(slot_index, mixed->big_chunks)) { + UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) == UVM_CHUNK_SIZE_64K); + UVM_ASSERT(mixed->slots[slot_index] == chunk); + mixed->slots[slot_index] = NULL; + clear_bit(slot_index, mixed->big_chunks); + } + else { + size_t small_index; + + UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) == UVM_CHUNK_SIZE_4K); + chunks = mixed->slots[slot_index]; + small_index = compute_small_index(va_block, page_index); + UVM_ASSERT(chunks[small_index] == chunk); + chunks[small_index] = NULL; + + for (small_index = 0; small_index < MAX_SMALL_CHUNKS_PER_BIG_SLOT; small_index++) { + if (chunks[small_index]) + break; + } + + if (small_index == MAX_SMALL_CHUNKS_PER_BIG_SLOT) { + uvm_kvfree(chunks); + mixed->slots[slot_index] = NULL; + } + } + } + + uvm_page_mask_region_clear(&va_block->cpu.allocated, chunk_region); + + if (uvm_page_mask_empty(&va_block->cpu.allocated) && va_block->cpu.chunks) { + uvm_kvfree(uvm_cpu_storage_get_ptr(va_block)); + va_block->cpu.chunks = 0; + } +} + +struct page *uvm_cpu_chunk_get_cpu_page(uvm_va_block_t *va_block, uvm_page_index_t page_index) +{ + uvm_va_block_region_t chunk_region; + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(va_block, page_index); + + UVM_ASSERT(chunk); + UVM_ASSERT(chunk->page); + chunk_region = uvm_va_block_chunk_region(va_block, uvm_cpu_chunk_get_size(chunk), page_index); + return chunk->page + (page_index - chunk_region.first); +} + +static uvm_cpu_chunk_t *uvm_cpu_chunk_first_in_region(uvm_va_block_t *va_block, + uvm_va_block_region_t region, + uvm_page_index_t *first_chunk_page) +{ + uvm_cpu_chunk_t *chunk = NULL; + uvm_page_index_t page_index; + + page_index = uvm_va_block_first_page_in_mask(region, &va_block->cpu.allocated); + if (page_index < region.outer) + chunk = uvm_cpu_chunk_get_chunk_for_page(va_block, page_index); + + if (first_chunk_page && chunk) { + uvm_va_block_region_t chunk_region = uvm_cpu_chunk_block_region(va_block, chunk, page_index); + *first_chunk_page = chunk_region.first; + } + + return chunk; +} + +#define for_each_cpu_chunk_in_block_region(chunk, page_index, va_block, region) \ + for ((chunk) = uvm_cpu_chunk_first_in_region((va_block), (region), &(page_index)); \ + (chunk) != NULL; \ + (chunk) = uvm_cpu_chunk_first_in_region((va_block), \ + uvm_va_block_region((page_index) + uvm_cpu_chunk_num_pages((chunk)), \ + (region).outer), \ + &(page_index))) + +#define for_each_cpu_chunk_in_block_region_safe(chunk, page_index, next_page_index, va_block, region) \ + for ((chunk) = uvm_cpu_chunk_first_in_region((va_block), (region), &(page_index)), \ + (next_page_index) = (page_index) + (chunk ? uvm_cpu_chunk_num_pages(chunk) : 0); \ + (chunk) != NULL; \ + (chunk) = uvm_cpu_chunk_first_in_region((va_block), \ + uvm_va_block_region((next_page_index), (region).outer), \ + &(page_index)), \ + (next_page_index) = (page_index) + ((chunk) ? uvm_cpu_chunk_num_pages((chunk)) : 0)) + +#define for_each_cpu_chunk_in_block(chunk, page_index, va_block) \ + for_each_cpu_chunk_in_block_region((chunk), (page_index), (va_block), uvm_va_block_region_from_block((va_block))) + +#define for_each_cpu_chunk_in_block_safe(chunk, page_index, next_page_index, va_block) \ + for_each_cpu_chunk_in_block_region_safe((chunk), \ + (page_index), \ + (next_page_index), \ + (va_block), \ + uvm_va_block_region_from_block((va_block))) + +static bool block_check_cpu_chunks(uvm_va_block_t *block) { uvm_cpu_chunk_t *chunk; size_t alloced_pages = 0; - NvU64 tracking_virt_addr = block->start; - uvm_page_mask_t region_mask; + uvm_va_block_region_t prev_region = { 0 }; uvm_page_index_t page_index; - uvm_va_block_region_t block_region = uvm_va_block_region_from_block(block); for_each_cpu_chunk_in_block(chunk, page_index, block) { - NvU64 chunk_virt_addr = uvm_va_block_cpu_page_address(block, page_index); + uvm_va_block_region_t chunk_region = uvm_cpu_chunk_block_region(block, chunk, page_index); size_t num_chunk_pages = uvm_cpu_chunk_num_pages(chunk); uvm_page_index_t chunk_page; - UVM_ASSERT(tracking_virt_addr <= chunk_virt_addr); - if (tracking_virt_addr > chunk_virt_addr) - return false; - - UVM_ASSERT(uvm_va_block_contains_address(block, chunk_virt_addr)); - if (!uvm_va_block_contains_address(block, chunk_virt_addr)) - return false; + UVM_ASSERT(prev_region.outer <= chunk_region.first); + UVM_ASSERT(IS_ALIGNED(uvm_va_block_region_start(block, chunk_region), uvm_cpu_chunk_get_size(chunk))); + UVM_ASSERT(chunk_region.outer <= uvm_va_block_num_cpu_pages(block)); alloced_pages += uvm_cpu_chunk_num_pages(chunk); - uvm_page_mask_init_from_region(®ion_mask, - uvm_va_block_region(page_index, page_index + uvm_cpu_chunk_num_pages(chunk)), - NULL); - UVM_ASSERT(uvm_page_mask_intersects(&block->cpu.allocated, ®ion_mask)); - if (!uvm_page_mask_intersects(&block->cpu.allocated, ®ion_mask)) - return false; + UVM_ASSERT(uvm_page_mask_region_full(&block->cpu.allocated, chunk_region)); + prev_region = chunk_region; - tracking_virt_addr = chunk_virt_addr; - - for (chunk_page = page_index; chunk_page < page_index + num_chunk_pages; chunk_page++) { + for (chunk_page = page_index; chunk_page < page_index + num_chunk_pages; chunk_page++) UVM_ASSERT(uvm_cpu_chunk_get_chunk_for_page(block, chunk_page) == chunk); - if (uvm_cpu_chunk_get_chunk_for_page(block, chunk_page) != chunk) - return false; - } } UVM_ASSERT(alloced_pages == uvm_page_mask_weight(&block->cpu.allocated)); - if (alloced_pages != uvm_page_mask_weight(&block->cpu.allocated)) - return false; - - for_each_va_block_page_in_region_mask(page_index, &block->cpu.allocated, block_region) { - uvm_cpu_chunk_t *next; - uvm_page_index_t next_page_index; - - chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); - UVM_ASSERT(chunk); - if (!chunk) - return false; - - next_page_index = uvm_va_block_next_page_in_mask(block_region, - &block->cpu.allocated, - page_index + uvm_cpu_chunk_num_pages(chunk) - 1); - next = uvm_cpu_chunk_next(block, &next_page_index); - - if (next_page_index < block_region.outer) { - UVM_ASSERT(next && - uvm_va_block_cpu_page_address(block, page_index) + uvm_cpu_chunk_get_size(chunk) <= - uvm_va_block_cpu_page_address(block, next_page_index)); - if (!next || - (uvm_va_block_cpu_page_address(block, page_index) + uvm_cpu_chunk_get_size(chunk) > - uvm_va_block_cpu_page_address(block, next_page_index))) - return false; - } - else { - UVM_ASSERT(next == NULL); - if (next != NULL) - return false; - } - } return true; } @@ -307,7 +567,12 @@ void uvm_va_block_retry_deinit(uvm_va_block_retry_t *retry, uvm_va_block_t *va_b list_for_each_entry_safe(gpu_chunk, next_chunk, &retry->used_chunks, list) { list_del_init(&gpu_chunk->list); gpu = uvm_gpu_chunk_get_gpu(gpu_chunk); - uvm_pmm_gpu_unpin_temp(&gpu->pmm, gpu_chunk, va_block); + // HMM should have already moved allocated blocks to the referenced + // state so any left over were not migrated and should be freed. + if (uvm_va_block_is_hmm(va_block)) + uvm_pmm_gpu_free(&gpu->pmm, gpu_chunk, NULL); + else + uvm_pmm_gpu_unpin_allocated(&gpu->pmm, gpu_chunk, va_block); } } @@ -440,9 +705,6 @@ size_t uvm_va_block_gpu_chunk_index_range(NvU64 start, // Next common case: the whole block is aligned and sized to perfectly fit // the largest page size. - // - // TODO: Bug 1750144: This might not be the common case for HMM. Verify that - // this helps performance more than it hurts. final_chunk_size = uvm_chunk_find_last_size(chunk_sizes); if (IS_ALIGNED(start, final_chunk_size) && IS_ALIGNED(size, final_chunk_size)) { num_chunks_total = (size_t)uvm_div_pow2_64(page_index * PAGE_SIZE, final_chunk_size); @@ -519,6 +781,22 @@ out: return num_chunks_total; } +static size_t block_gpu_chunk_index_range(uvm_va_block_t *va_block, + NvU64 start, + NvU64 size, + uvm_gpu_t *gpu, + uvm_page_index_t page_index, + uvm_chunk_size_t *out_chunk_size) +{ + if (uvm_va_block_is_hmm(va_block)) { + if (out_chunk_size) + *out_chunk_size = PAGE_SIZE; + return page_index; + } + + return uvm_va_block_gpu_chunk_index_range(start, size, gpu, page_index, out_chunk_size); +} + static size_t block_gpu_chunk_index(uvm_va_block_t *block, uvm_gpu_t *gpu, uvm_page_index_t page_index, @@ -527,8 +805,9 @@ static size_t block_gpu_chunk_index(uvm_va_block_t *block, uvm_va_block_gpu_state_t *gpu_state = uvm_va_block_gpu_state_get(block, gpu->id); uvm_chunk_size_t size; uvm_gpu_chunk_t *chunk; + size_t index; - size_t index = uvm_va_block_gpu_chunk_index_range(block->start, uvm_va_block_size(block), gpu, page_index, &size); + index = block_gpu_chunk_index_range(block, block->start, uvm_va_block_size(block), gpu, page_index, &size); UVM_ASSERT(size >= PAGE_SIZE); @@ -556,6 +835,9 @@ static uvm_chunk_size_t block_gpu_chunk_size(uvm_va_block_t *block, uvm_gpu_t *g NvU64 start = uvm_va_block_cpu_page_address(block, start_page_index); NvU64 size = block->end - start + 1; + if (uvm_va_block_is_hmm(block)) + return PAGE_SIZE; + // Create a mask of all sizes for which start is aligned. x ^ (x-1) yields a // mask of the rightmost 1 bit in x, as well as all trailing 0 bits in x. // Example: 1011000 -> 0001111 @@ -582,10 +864,10 @@ static size_t block_num_gpu_chunks(uvm_va_block_t *block, uvm_gpu_t *gpu) return block_gpu_chunk_index(block, gpu, uvm_va_block_cpu_page_index(block, block->end), NULL) + 1; } -static size_t block_num_gpu_chunks_range(NvU64 start, NvU64 size, uvm_gpu_t *gpu) +static size_t block_num_gpu_chunks_range(uvm_va_block_t *block, NvU64 start, NvU64 size, uvm_gpu_t *gpu) { uvm_page_index_t last_page_index = (size_t)((size / PAGE_SIZE) - 1); - return uvm_va_block_gpu_chunk_index_range(start, size, gpu, last_page_index, NULL) + 1; + return block_gpu_chunk_index_range(block, start, size, gpu, last_page_index, NULL) + 1; } uvm_gpu_chunk_t *uvm_va_block_lookup_gpu_chunk(uvm_va_block_t *va_block, uvm_gpu_t *gpu, NvU64 address) @@ -649,28 +931,58 @@ NV_STATUS uvm_va_block_create(uvm_va_range_t *va_range, uvm_tracker_init(&block->tracker); block->prefetch_info.last_migration_proc_id = UVM_ID_INVALID; - nv_kthread_q_item_init(&block->eviction_mappings_q_item, block_deferred_eviction_mappings_entry, block); + nv_kthread_q_item_init(&block->eviction_mappings_q_item, block_add_eviction_mappings_entry, block); *out_block = block; return NV_OK; } +static void cpu_chunk_remove_sysmem_gpu_mapping(uvm_cpu_chunk_t *chunk, uvm_gpu_t *gpu) +{ + NvU64 gpu_mapping_addr = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent); + if (gpu_mapping_addr == 0) + return; + + uvm_pmm_sysmem_mappings_remove_gpu_mapping(&gpu->pmm_reverse_sysmem_mappings, gpu_mapping_addr); + uvm_cpu_chunk_unmap_gpu_phys(chunk, gpu->parent); +} + +static NV_STATUS cpu_chunk_add_sysmem_gpu_mapping(uvm_cpu_chunk_t *chunk, + uvm_va_block_t *block, + uvm_page_index_t page_index, + uvm_gpu_t *gpu) +{ + NV_STATUS status; + uvm_chunk_size_t chunk_size; + + status = uvm_cpu_chunk_map_gpu(chunk, gpu); + if (status != NV_OK) + return status; + + chunk_size = uvm_cpu_chunk_get_size(chunk); + + // TODO: Bug 3744779: Handle benign assertion in + // pmm_sysmem_mappings_remove_gpu_mapping() in case of a + // failure. + status = uvm_pmm_sysmem_mappings_add_gpu_mapping(&gpu->pmm_reverse_sysmem_mappings, + uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent), + uvm_va_block_cpu_page_address(block, page_index), + chunk_size, + block, + UVM_ID_CPU); + if (status != NV_OK) + cpu_chunk_remove_sysmem_gpu_mapping(chunk, gpu); + + return status; +} + static void block_gpu_unmap_phys_all_cpu_pages(uvm_va_block_t *block, uvm_gpu_t *gpu) { uvm_cpu_chunk_t *chunk; uvm_page_index_t page_index; - for_each_cpu_chunk_in_block(chunk, page_index, block) { - NvU64 gpu_mapping_addr; - - UVM_ASSERT(chunk); - gpu_mapping_addr = uvm_cpu_chunk_get_gpu_mapping_addr(block, page_index, chunk, gpu->id); - if (gpu_mapping_addr != 0) { - uvm_pmm_sysmem_mappings_remove_gpu_mapping(&gpu->pmm_reverse_sysmem_mappings, gpu_mapping_addr); - uvm_gpu_unmap_cpu_pages(gpu->parent, gpu_mapping_addr, uvm_cpu_chunk_get_size(chunk)); - uvm_cpu_chunk_set_gpu_mapping_addr(block, page_index, chunk, gpu->id, 0); - } - } + for_each_cpu_chunk_in_block(chunk, page_index, block) + cpu_chunk_remove_sysmem_gpu_mapping(chunk, gpu); } static NV_STATUS block_gpu_map_phys_all_cpu_pages(uvm_va_block_t *block, uvm_gpu_t *gpu) @@ -683,35 +995,12 @@ static NV_STATUS block_gpu_map_phys_all_cpu_pages(uvm_va_block_t *block, uvm_gpu UVM_ASSERT(IS_ALIGNED(block_mapping_size, UVM_PAGE_SIZE_4K)); for_each_cpu_chunk_in_block(chunk, page_index, block) { - uvm_chunk_size_t chunk_size = uvm_cpu_chunk_get_size(chunk); - NvU64 gpu_mapping_addr = uvm_cpu_chunk_get_gpu_mapping_addr(block, page_index, chunk, gpu->id); + UVM_ASSERT_MSG(uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent) == 0, + "GPU%u DMA address 0x%llx\n", + uvm_id_value(gpu->id), + uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent)); - UVM_ASSERT_MSG(gpu_mapping_addr == 0, "GPU%u DMA address 0x%llx\n", uvm_id_value(gpu->id), gpu_mapping_addr); - - status = uvm_gpu_map_cpu_pages(gpu->parent, - uvm_cpu_chunk_get_cpu_page(block, chunk, page_index), - chunk_size, - &gpu_mapping_addr); - if (status != NV_OK) - goto error; - - uvm_cpu_chunk_set_gpu_mapping_addr(block, page_index, chunk, gpu->id, gpu_mapping_addr); - - // In some configurations such as SR-IOV heavy, the chunk cannot be - // referenced using its physical address. Create a kernel mapping. - status = uvm_mmu_sysmem_map(gpu, gpu_mapping_addr, chunk_size); - if (status != NV_OK) - goto error; - - status = uvm_pmm_sysmem_mappings_add_gpu_mapping(&gpu->pmm_reverse_sysmem_mappings, - uvm_cpu_chunk_get_gpu_mapping_addr(block, - page_index, - chunk, - gpu->id), - uvm_va_block_cpu_page_address(block, page_index), - chunk_size, - block, - UVM_ID_CPU); + status = cpu_chunk_add_sysmem_gpu_mapping(chunk, block, page_index, gpu); if (status != NV_OK) goto error; } @@ -819,7 +1108,9 @@ static void block_gpu_unmap_all_chunks_indirect_peer(uvm_va_block_t *block, } } -// Retrieves the gpu_state for the given GPU, allocating it if it doesn't exist +// Retrieves the gpu_state for the given GPU. The returned pointer is +// internally managed and will be allocated (and freed) automatically, +// rather than by the caller. static uvm_va_block_gpu_state_t *block_gpu_state_get_alloc(uvm_va_block_t *block, uvm_gpu_t *gpu) { NV_STATUS status; @@ -838,10 +1129,6 @@ static uvm_va_block_gpu_state_t *block_gpu_state_get_alloc(uvm_va_block_t *block block->gpus[uvm_id_gpu_index(gpu->id)] = gpu_state; - status = uvm_cpu_chunk_gpu_mapping_alloc(block, gpu->id); - if (status != NV_OK) - goto error; - status = block_gpu_map_phys_all_cpu_pages(block, gpu); if (status != NV_OK) goto error; @@ -849,40 +1136,43 @@ static uvm_va_block_gpu_state_t *block_gpu_state_get_alloc(uvm_va_block_t *block return gpu_state; error: - if (gpu_state) { - if (gpu_state->chunks) - uvm_kvfree(gpu_state->chunks); - uvm_cpu_chunk_gpu_mapping_free(block, gpu->id); - kmem_cache_free(g_uvm_va_block_gpu_state_cache, gpu_state); - } + uvm_kvfree(gpu_state->chunks); + kmem_cache_free(g_uvm_va_block_gpu_state_cache, gpu_state); block->gpus[uvm_id_gpu_index(gpu->id)] = NULL; return NULL; } -static void block_unmap_cpu_chunk_on_gpus(uvm_va_block_t *block, uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) +NV_STATUS uvm_va_block_gpu_state_alloc(uvm_va_block_t *va_block) +{ + uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); + uvm_gpu_id_t gpu_id; + + UVM_ASSERT(uvm_va_block_is_hmm(va_block)); + uvm_assert_mutex_locked(&va_block->lock); + + for_each_gpu_id_in_mask(gpu_id, &va_space->registered_gpus) { + if (!block_gpu_state_get_alloc(va_block, uvm_va_space_get_gpu(va_space, gpu_id))) + return NV_ERR_NO_MEMORY; + } + + return NV_OK; +} + +void uvm_va_block_unmap_cpu_chunk_on_gpus(uvm_va_block_t *block, + uvm_cpu_chunk_t *chunk, + uvm_page_index_t page_index) { uvm_gpu_id_t id; for_each_gpu_id(id) { - NvU64 gpu_mapping_addr; - uvm_gpu_t *gpu; - - if (!uvm_va_block_gpu_state_get(block, id)) - continue; - - gpu_mapping_addr = uvm_cpu_chunk_get_gpu_mapping_addr(block, page_index, chunk, id); - if (gpu_mapping_addr == 0) - continue; - - gpu = block_get_gpu(block, id); - uvm_pmm_sysmem_mappings_remove_gpu_mapping(&gpu->pmm_reverse_sysmem_mappings, gpu_mapping_addr); - uvm_gpu_unmap_cpu_pages(gpu->parent, gpu_mapping_addr, uvm_cpu_chunk_get_size(chunk)); - uvm_cpu_chunk_set_gpu_mapping_addr(block, page_index, chunk, id, 0); + if (uvm_va_block_gpu_state_get(block, id)) + cpu_chunk_remove_sysmem_gpu_mapping(chunk, block_get_gpu(block, id)); } } -static NV_STATUS block_map_cpu_chunk_on_gpus(uvm_va_block_t *block, uvm_page_index_t page_index) +NV_STATUS uvm_va_block_map_cpu_chunk_on_gpus(uvm_va_block_t *block, + uvm_page_index_t page_index) { NV_STATUS status; uvm_gpu_id_t id; @@ -890,51 +1180,19 @@ static NV_STATUS block_map_cpu_chunk_on_gpus(uvm_va_block_t *block, uvm_page_ind uvm_chunk_size_t chunk_size = uvm_cpu_chunk_get_size(chunk); uvm_va_block_region_t chunk_region = uvm_va_block_chunk_region(block, chunk_size, page_index); - UVM_ASSERT(chunk); - // We can't iterate over va_space->registered_gpus because we might be // on the eviction path, which does not have the VA space lock held. We have // the VA block lock held however, so the gpu_states can't change. uvm_assert_mutex_locked(&block->lock); - // Only physical chunks can be mapped. - UVM_ASSERT(uvm_cpu_chunk_is_physical(chunk)); - for_each_gpu_id(id) { - NvU64 gpu_mapping_addr; uvm_gpu_t *gpu; if (!uvm_va_block_gpu_state_get(block, id)) continue; - gpu_mapping_addr = uvm_cpu_chunk_get_gpu_mapping_addr(block, page_index, chunk, id); - UVM_ASSERT_MSG(gpu_mapping_addr == 0, "GPU%u DMA address 0x%llx\n", uvm_id_value(id), gpu_mapping_addr); - gpu = block_get_gpu(block, id); - status = uvm_gpu_map_cpu_pages(gpu->parent, - uvm_cpu_chunk_get_cpu_page(block, chunk, chunk_region.first), - chunk_size, - &gpu_mapping_addr); - if (status != NV_OK) - goto error; - - uvm_cpu_chunk_set_gpu_mapping_addr(block, chunk_region.first, chunk, id, gpu_mapping_addr); - - // In some configurations such as SR-IOV heavy, the chunk cannot be - // referenced using its physical address. Create a kernel mapping. - status = uvm_mmu_sysmem_map(gpu, gpu_mapping_addr, chunk_size); - if (status != NV_OK) - goto error; - - status = uvm_pmm_sysmem_mappings_add_gpu_mapping(&gpu->pmm_reverse_sysmem_mappings, - uvm_cpu_chunk_get_gpu_mapping_addr(block, - chunk_region.first, - chunk, - id), - uvm_va_block_cpu_page_address(block, chunk_region.first), - chunk_size, - block, - UVM_ID_CPU); + status = cpu_chunk_add_sysmem_gpu_mapping(chunk, block, chunk_region.first, gpu); if (status != NV_OK) goto error; } @@ -942,10 +1200,33 @@ static NV_STATUS block_map_cpu_chunk_on_gpus(uvm_va_block_t *block, uvm_page_ind return NV_OK; error: - block_unmap_cpu_chunk_on_gpus(block, chunk, page_index); + uvm_va_block_unmap_cpu_chunk_on_gpus(block, chunk, page_index); return status; } +void uvm_va_block_remove_cpu_chunks(uvm_va_block_t *va_block, uvm_va_block_region_t region) +{ + uvm_cpu_chunk_t *chunk; + uvm_page_index_t page_index, next_page_index; + uvm_va_block_region_t chunk_region; + + for_each_cpu_chunk_in_block_region_safe(chunk, page_index, next_page_index, va_block, region) { + chunk_region = uvm_va_block_region(page_index, page_index + uvm_cpu_chunk_num_pages(chunk)); + + uvm_page_mask_region_clear(&va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_READ], chunk_region); + uvm_page_mask_region_clear(&va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_WRITE], chunk_region); + uvm_page_mask_region_clear(&va_block->cpu.resident, chunk_region); + uvm_cpu_chunk_remove_from_block(va_block, page_index); + uvm_va_block_unmap_cpu_chunk_on_gpus(va_block, chunk, page_index); + uvm_cpu_chunk_free(chunk); + } + + if (uvm_page_mask_empty(&va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_READ])) + uvm_processor_mask_clear(&va_block->mapped, UVM_ID_CPU); + if (uvm_page_mask_empty(&va_block->cpu.resident)) + uvm_processor_mask_clear(&va_block->resident, UVM_ID_CPU); +} + // Create physical mappings to allow other GPUs to access this chunk. static NV_STATUS block_map_indirect_peers_to_gpu_chunk(uvm_va_block_t *block, uvm_gpu_t *gpu, uvm_gpu_chunk_t *chunk) { @@ -953,8 +1234,8 @@ static NV_STATUS block_map_indirect_peers_to_gpu_chunk(uvm_va_block_t *block, uv uvm_gpu_t *accessing_gpu, *remove_gpu; NV_STATUS status; - // Unlike block_map_cpu_chunk_on_gpus, this function isn't called on the - // eviction path, so we can assume that the VA space is locked. + // Unlike uvm_va_block_map_cpu_chunk_on_gpus, this function isn't called on + // the eviction path, so we can assume that the VA space is locked. // // TODO: Bug 2007346: In the future we may want to enable eviction to peers, // meaning we may need to allocate peer memory and map it on the @@ -1009,41 +1290,33 @@ static void block_unmap_indirect_peers_from_gpu_chunk(uvm_va_block_t *block, uvm static void block_mark_cpu_page_dirty(uvm_va_block_t *block, uvm_page_index_t page_index) { uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); - uvm_cpu_chunk_mark_dirty(chunk, page_index); + uvm_va_block_region_t chunk_region = uvm_va_block_chunk_region(block, uvm_cpu_chunk_get_size(chunk), page_index); + uvm_cpu_chunk_mark_dirty(chunk, page_index - chunk_region.first); } // Mark a CPU page as clean. static void block_mark_cpu_page_clean(uvm_va_block_t *block, uvm_page_index_t page_index) { uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); - uvm_cpu_chunk_mark_clean(chunk, page_index); + uvm_va_block_region_t chunk_region = uvm_va_block_chunk_region(block, uvm_cpu_chunk_get_size(chunk), page_index); + uvm_cpu_chunk_mark_clean(chunk, page_index - chunk_region.first); } // Check if a CPU page is dirty. static bool block_cpu_page_is_dirty(uvm_va_block_t *block, uvm_page_index_t page_index) { uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); - return uvm_cpu_chunk_is_dirty(chunk, page_index); + uvm_va_block_region_t chunk_region = uvm_va_block_chunk_region(block, uvm_cpu_chunk_get_size(chunk), page_index); + return uvm_cpu_chunk_is_dirty(chunk, page_index - chunk_region.first); } -// Allocates the input page in the block, if it doesn't already exist -// -// Also maps the page for physical access by all GPUs used by the block, which -// is required for IOMMU support. -// -// TODO: Bug 1995015: Optimize this function and its callers to avoid calling for -// each page index. -static NV_STATUS block_populate_page_cpu(uvm_va_block_t *block, uvm_page_index_t page_index, struct mm_struct *mm) +static NV_STATUS block_alloc_cpu_chunk(uvm_va_block_t *block, + uvm_chunk_size_t alloc_size, + uvm_cpu_chunk_alloc_flags_t flags, + uvm_cpu_chunk_t **chunk) { - NV_STATUS status; - uvm_cpu_chunk_t *chunk = NULL; uvm_va_block_test_t *block_test = uvm_va_block_get_test(block); - if (uvm_page_mask_test(&block->cpu.allocated, page_index)) - return NV_OK; - - UVM_ASSERT(!uvm_page_mask_test(&block->cpu.resident, page_index)); - // Return out of memory error if the tests have requested it. As opposed to // other error injection settings, this one fails N times and then succeeds. // TODO: Bug 3701182: This will print a warning in Linux kernels newer than @@ -1054,16 +1327,133 @@ static NV_STATUS block_populate_page_cpu(uvm_va_block_t *block, uvm_page_index_t return NV_ERR_NO_MEMORY; } - status = uvm_cpu_chunk_alloc(block, page_index, mm, &chunk); - if (status != NV_OK) - goto error; + return uvm_cpu_chunk_alloc(alloc_size, flags, chunk); +} - status = block_map_cpu_chunk_on_gpus(block, page_index); +// Allocates the input page in the block, if it doesn't already exist +// +// Also maps the page for physical access by all GPUs used by the block, which +// is required for IOMMU support. Skipped on GPUs without access to CPU memory. +static NV_STATUS block_populate_pages_cpu(uvm_va_block_t *block, + uvm_page_mask_t *populate_page_mask, + uvm_va_block_region_t populate_region, + uvm_va_block_context_t *block_context) +{ + NV_STATUS status = NV_OK; + uvm_cpu_chunk_t *chunk; + uvm_va_block_test_t *block_test = uvm_va_block_get_test(block); + uvm_chunk_sizes_mask_t cpu_allocation_sizes = uvm_cpu_chunk_get_allocation_sizes(); + uvm_chunk_size_t alloc_size; + uvm_page_mask_t *resident_mask = &block_context->scratch_page_mask; + uvm_cpu_chunk_alloc_flags_t alloc_flags = UVM_CPU_CHUNK_ALLOC_FLAGS_NONE; + uvm_va_space_t *va_space = uvm_va_block_get_va_space(block); + uvm_processor_mask_t uvm_lite_gpus; + uvm_page_index_t page_index; + uvm_gpu_id_t id; + + // Check whether all requested pages have already been allocated. + uvm_page_mask_init_from_region(&block_context->scratch_page_mask, populate_region, populate_page_mask); + if (!uvm_page_mask_andnot(&block_context->scratch_page_mask, + &block_context->scratch_page_mask, + &block->cpu.allocated)) + return NV_OK; + + if (block_test) { + if (block_test->cpu_chunk_allocation_size_mask) + cpu_allocation_sizes &= block_test->cpu_chunk_allocation_size_mask; + } + + uvm_page_mask_zero(resident_mask); + for_each_id_in_mask (id, &block->resident) + uvm_page_mask_or(resident_mask, resident_mask, uvm_va_block_resident_mask_get(block, id)); + + // If the VA space has a UVM-Lite GPU registered, only PAGE_SIZE allocations + // should be used in order to avoid extra copies due to dirty compound + // pages. HMM va_blocks also require PAGE_SIZE allocations. + // TODO: Bug 3368756: add support for HMM transparent huge page (THP) + // migrations. + uvm_processor_mask_andnot(&uvm_lite_gpus, &va_space->registered_gpus, &va_space->faultable_processors); + if (!uvm_processor_mask_empty(&uvm_lite_gpus) || uvm_va_block_is_hmm(block)) + cpu_allocation_sizes = PAGE_SIZE; + + if (block_context->mm) + alloc_flags |= UVM_CPU_CHUNK_ALLOC_FLAGS_ACCOUNT; + + UVM_ASSERT(cpu_allocation_sizes >= PAGE_SIZE); + UVM_ASSERT(cpu_allocation_sizes & PAGE_SIZE); + + for_each_va_block_page_in_region_mask(page_index, populate_page_mask, populate_region) { + uvm_cpu_chunk_alloc_flags_t chunk_alloc_flags; + uvm_va_block_region_t region = populate_region; + + if (uvm_page_mask_test(&block->cpu.allocated, page_index)) { + page_index = uvm_va_block_next_unset_page_in_mask(populate_region, &block->cpu.allocated, page_index) - 1; + continue; + } + + UVM_ASSERT(!uvm_page_mask_test(&block->cpu.resident, page_index)); + + chunk_alloc_flags = alloc_flags; + + // Attempt to allocate CPU pages with the largest physically contiguous + // size from the set of CPU chunk sizes that we can. + // This is accomplished by: + // 1. Aligning the CPU page address down to the allocation size. + // 2. Ensuring that the entire allocation region fits withing the VA + // block. + // 3. Ensuring that the region covered by the allocation is empty. + for_each_chunk_size_rev(alloc_size, cpu_allocation_sizes) { + NvU64 alloc_virt_addr; + + chunk = NULL; + alloc_virt_addr = UVM_ALIGN_DOWN(uvm_va_block_cpu_page_address(block, page_index), alloc_size); + + if (!uvm_va_block_contains_address(block, alloc_virt_addr) || + !uvm_va_block_contains_address(block, alloc_virt_addr + alloc_size - 1)) + continue; + + region = uvm_va_block_region_from_start_end(block, alloc_virt_addr, alloc_virt_addr + alloc_size - 1); + + if (!uvm_page_mask_region_empty(&block->cpu.allocated, region)) + continue; + + // If not all pages in the allocation region are resident somewhere, + // zero out the allocated page. + // This could be wasteful if only a few pages in high-order + // allocation need to be zero'ed out but the alternative is to map + // single sub-pages one-by-one. + if (!uvm_page_mask_region_full(resident_mask, region)) + chunk_alloc_flags |= UVM_CPU_CHUNK_ALLOC_FLAGS_ZERO; + + status = block_alloc_cpu_chunk(block, alloc_size, chunk_alloc_flags, &chunk); + if (status == NV_OK) { + page_index = region.first; + break; + } + + UVM_ASSERT(status == NV_ERR_NO_MEMORY); + } + + if (status != NV_OK) + break; + + status = uvm_cpu_chunk_insert_in_block(block, chunk, page_index); + if (status != NV_OK) { + uvm_cpu_chunk_free(chunk); + return status; + } + + status = uvm_va_block_map_cpu_chunk_on_gpus(block, page_index); + if (status != NV_OK) + break; + + // Skip iterating over all pages covered by the allocated chunk. + page_index = region.outer - 1; + } -error: if (status != NV_OK && chunk) { - uvm_cpu_chunk_remove_from_block(block, chunk, page_index); - uvm_cpu_chunk_put(chunk); + uvm_cpu_chunk_remove_from_block(block, page_index); + uvm_cpu_chunk_free(chunk); } return status; @@ -1172,7 +1562,8 @@ static bool block_gpu_supports_2m(uvm_va_block_t *block, uvm_gpu_t *gpu) { uvm_gpu_va_space_t *gpu_va_space; - if (uvm_va_block_size(block) < UVM_PAGE_SIZE_2M) + // TODO: Bug 3368756: add HMM support for transparent huge page migrations. + if (uvm_va_block_size(block) < UVM_PAGE_SIZE_2M || uvm_va_block_is_hmm(block)) return false; UVM_ASSERT(uvm_va_block_size(block) == UVM_PAGE_SIZE_2M); @@ -1499,7 +1890,10 @@ static bool block_processor_page_is_resident_on(uvm_va_block_t *block, uvm_proce return uvm_page_mask_test(resident_mask, page_index); } -void uvm_va_block_region_authorized_gpus(uvm_va_block_t *va_block, +// Compute the gpus that have at least the given access permissions for the +// range described by region and page_mask. The function sets the bit if any +// page in the region has the permissions. +static void block_region_authorized_gpus(uvm_va_block_t *va_block, uvm_va_block_region_t region, uvm_prot_t access_permission, uvm_processor_mask_t *authorized_gpus) @@ -1517,7 +1911,10 @@ void uvm_va_block_region_authorized_gpus(uvm_va_block_t *va_block, } } -void uvm_va_block_region_authorized_processors(uvm_va_block_t *va_block, +// Compute the processors that have at least the given access permissions for +// the range described by region and page_mask. The function sets the bit if any +// page in the region has the permissions. +static void block_region_authorized_processors(uvm_va_block_t *va_block, uvm_va_block_region_t region, uvm_prot_t access_permission, uvm_processor_mask_t *authorized_processors) @@ -1525,7 +1922,7 @@ void uvm_va_block_region_authorized_processors(uvm_va_block_t *va_block, uvm_pte_bits_cpu_t search_cpu_bit = get_cpu_pte_bit_index(access_permission); // Compute GPUs - uvm_va_block_region_authorized_gpus(va_block, region, access_permission, authorized_processors); + block_region_authorized_gpus(va_block, region, access_permission, authorized_processors); // Test CPU if (uvm_processor_mask_test(&va_block->mapped, UVM_ID_CPU) && @@ -1534,29 +1931,18 @@ void uvm_va_block_region_authorized_processors(uvm_va_block_t *va_block, } } -void uvm_va_block_page_authorized_gpus(uvm_va_block_t *va_block, - uvm_page_index_t page_index, - uvm_prot_t access_permission, - uvm_processor_mask_t *authorized_gpus) -{ - uvm_va_block_region_authorized_gpus(va_block, - uvm_va_block_region_for_page(page_index), - access_permission, - authorized_gpus); -} - -void uvm_va_block_page_authorized_processors(uvm_va_block_t *va_block, +static void block_page_authorized_processors(uvm_va_block_t *va_block, uvm_page_index_t page_index, uvm_prot_t access_permission, uvm_processor_mask_t *authorized_processors) { - uvm_va_block_region_authorized_processors(va_block, - uvm_va_block_region_for_page(page_index), - access_permission, - authorized_processors); + block_region_authorized_processors(va_block, + uvm_va_block_region_for_page(page_index), + access_permission, + authorized_processors); } -bool uvm_va_block_is_gpu_authorized_on_whole_region(uvm_va_block_t *va_block, +static bool block_is_gpu_authorized_on_whole_region(uvm_va_block_t *va_block, uvm_va_block_region_t region, uvm_gpu_id_t gpu_id, uvm_prot_t required_prot) @@ -1570,7 +1956,7 @@ bool uvm_va_block_is_gpu_authorized_on_whole_region(uvm_va_block_t *va_block, return uvm_page_mask_region_full(&gpu_state->pte_bits[search_gpu_bit], region); } -bool uvm_va_block_is_processor_authorized_on_whole_region(uvm_va_block_t *va_block, +static bool block_is_processor_authorized_on_whole_region(uvm_va_block_t *va_block, uvm_va_block_region_t region, uvm_processor_id_t processor_id, uvm_prot_t required_prot) @@ -1581,7 +1967,7 @@ bool uvm_va_block_is_processor_authorized_on_whole_region(uvm_va_block_t *va_blo return uvm_page_mask_region_full(&va_block->cpu.pte_bits[search_cpu_bit], region); } else { - return uvm_va_block_is_gpu_authorized_on_whole_region(va_block, region, processor_id, required_prot); + return block_is_gpu_authorized_on_whole_region(va_block, region, processor_id, required_prot); } } @@ -1590,24 +1976,25 @@ bool uvm_va_block_page_is_gpu_authorized(uvm_va_block_t *va_block, uvm_gpu_id_t gpu_id, uvm_prot_t required_prot) { - return uvm_va_block_is_gpu_authorized_on_whole_region(va_block, - uvm_va_block_region_for_page(page_index), - gpu_id, - required_prot); + return block_is_gpu_authorized_on_whole_region(va_block, + uvm_va_block_region_for_page(page_index), + gpu_id, + required_prot); } -bool uvm_va_block_page_is_processor_authorized(uvm_va_block_t *va_block, +static bool block_page_is_processor_authorized(uvm_va_block_t *va_block, uvm_page_index_t page_index, uvm_processor_id_t processor_id, uvm_prot_t required_prot) { - return uvm_va_block_is_processor_authorized_on_whole_region(va_block, - uvm_va_block_region_for_page(page_index), - processor_id, - required_prot); + return block_is_processor_authorized_on_whole_region(va_block, + uvm_va_block_region_for_page(page_index), + processor_id, + required_prot); } -void uvm_va_block_page_resident_gpus(uvm_va_block_t *va_block, +// Compute the gpus that have a copy of the given page resident in their memory +static void block_page_resident_gpus(uvm_va_block_t *va_block, uvm_page_index_t page_index, uvm_processor_mask_t *resident_gpus) { @@ -1626,7 +2013,7 @@ void uvm_va_block_page_resident_processors(uvm_va_block_t *va_block, uvm_page_index_t page_index, uvm_processor_mask_t *resident_processors) { - uvm_va_block_page_resident_gpus(va_block, page_index, resident_processors); + block_page_resident_gpus(va_block, page_index, resident_processors); if (uvm_page_mask_test(uvm_va_block_resident_mask_get(va_block, UVM_ID_CPU), page_index)) { UVM_ASSERT(block_processor_page_is_populated(va_block, UVM_ID_CPU, page_index)); @@ -1642,14 +2029,7 @@ NvU32 uvm_va_block_page_resident_processors_count(uvm_va_block_t *va_block, uvm_ return uvm_processor_mask_get_count(&resident_processors); } -uvm_processor_id_t uvm_va_block_page_get_closest_resident(uvm_va_block_t *va_block, - uvm_page_index_t page_index, - uvm_processor_id_t processor) -{ - return uvm_va_block_page_get_closest_resident_in_mask(va_block, page_index, processor, NULL); -} - -uvm_processor_id_t uvm_va_block_page_get_closest_resident_in_mask(uvm_va_block_t *va_block, +static uvm_processor_id_t block_page_get_closest_resident_in_mask(uvm_va_block_t *va_block, uvm_page_index_t page_index, uvm_processor_id_t processor, const uvm_processor_mask_t *processor_mask) @@ -1668,9 +2048,22 @@ uvm_processor_id_t uvm_va_block_page_get_closest_resident_in_mask(uvm_va_block_t return id; } + // HMM va_blocks don't know if a page is CPU resident until either + // migrate_vma_setup() or hmm_range_fault() is called. If a page isn't + // resident anywhere, assume it is CPU resident. + if (uvm_va_block_is_hmm(va_block)) + return UVM_ID_CPU; + return UVM_ID_INVALID; } +uvm_processor_id_t uvm_va_block_page_get_closest_resident(uvm_va_block_t *va_block, + uvm_page_index_t page_index, + uvm_processor_id_t processor) +{ + return block_page_get_closest_resident_in_mask(va_block, page_index, processor, NULL); +} + // We don't track the specific aperture of each mapped page. Instead, we assume // that each virtual mapping from a given processor always targets the closest // processor on which that page is resident (with special rules for UVM-Lite). @@ -2053,9 +2446,8 @@ static NV_STATUS block_populate_pages(uvm_va_block_t *block, uvm_va_block_region_t region, const uvm_page_mask_t *page_mask) { - NV_STATUS status = NV_OK; + NV_STATUS status; const uvm_page_mask_t *resident_mask = block_resident_mask_get_alloc(block, dest_id); - uvm_page_index_t page_index; uvm_page_mask_t *populate_page_mask = &block_context->make_resident.page_mask; uvm_memcg_context_t memcg_context; @@ -2071,13 +2463,7 @@ static NV_STATUS block_populate_pages(uvm_va_block_t *block, return block_populate_pages_gpu(block, retry, block_get_gpu(block, dest_id), region, populate_page_mask); uvm_memcg_context_start(&memcg_context, block_context->mm); - - for_each_va_block_page_in_region_mask(page_index, populate_page_mask, region) { - status = block_populate_page_cpu(block, page_index, block_context->mm); - if (status != NV_OK) - break; - } - + status = block_populate_pages_cpu(block, populate_page_mask, region, block_context); uvm_memcg_context_end(&memcg_context); return status; } @@ -2133,7 +2519,7 @@ static uvm_gpu_phys_address_t block_phys_page_address(uvm_va_block_t *block, if (UVM_ID_IS_CPU(block_page.processor)) { uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, block_page.page_index); - NvU64 dma_addr = uvm_cpu_chunk_get_gpu_mapping_addr(block, block_page.page_index, chunk, gpu->id); + NvU64 dma_addr = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent); uvm_va_block_region_t chunk_region = uvm_va_block_chunk_region(block, uvm_cpu_chunk_get_size(chunk), block_page.page_index); @@ -2232,16 +2618,40 @@ uvm_gpu_phys_address_t uvm_va_block_gpu_phys_page_address(uvm_va_block_t *va_blo return uvm_va_block_res_phys_page_address(va_block, page_index, gpu->id, gpu); } +typedef struct +{ + // Location of the memory + uvm_processor_id_t id; + + // Whether the whole block has a single physically-contiguous chunk of + // storage on the processor. + bool is_block_contig; + + // Starting address of the physically-contiguous allocation, from the view + // of the copying GPU. Valid only if is_block_contig. + uvm_gpu_address_t gpu_address; +} block_copy_addr_t; + +typedef struct +{ + block_copy_addr_t src; + block_copy_addr_t dst; +} block_copy_state_t; + // Begin a push appropriate for copying data from src_id processor to dst_id processor. // One of src_id and dst_id needs to be a GPU. static NV_STATUS block_copy_begin_push(uvm_va_block_t *va_block, - uvm_processor_id_t dst_id, - uvm_processor_id_t src_id, + block_copy_state_t *copy_state, uvm_tracker_t *tracker, uvm_push_t *push) { - uvm_channel_type_t channel_type; uvm_gpu_t *gpu; + NV_STATUS status; + uvm_channel_type_t channel_type; + uvm_tracker_t *tracker_ptr = tracker; + uvm_processor_id_t dst_id = copy_state->dst.id; + uvm_processor_id_t src_id = copy_state->src.id; + uvm_tracker_t local_tracker = UVM_TRACKER_INIT(); UVM_ASSERT_MSG(!uvm_id_equal(src_id, dst_id), "Unexpected copy to self, processor %s\n", @@ -2287,15 +2697,18 @@ static NV_STATUS block_copy_begin_push(uvm_va_block_t *va_block, va_block->end); } - return uvm_push_begin_acquire(gpu->channel_manager, - channel_type, - tracker, - push, - "Copy from %s to %s for block [0x%llx, 0x%llx]", - block_processor_name(va_block, src_id), - block_processor_name(va_block, dst_id), - va_block->start, - va_block->end); + status = uvm_push_begin_acquire(gpu->channel_manager, + channel_type, + tracker_ptr, + push, + "Copy from %s to %s for block [0x%llx, 0x%llx]", + block_processor_name(va_block, src_id), + block_processor_name(va_block, dst_id), + va_block->start, + va_block->end); + + uvm_tracker_deinit(&local_tracker); + return status; } // A page is clean iff... @@ -2323,7 +2736,7 @@ static void block_update_page_dirty_state(uvm_va_block_t *block, uvm_processor_id_t src_id, uvm_page_index_t page_index) { - if (UVM_ID_IS_GPU(dst_id) || uvm_va_block_is_hmm(block)) + if (UVM_ID_IS_GPU(dst_id)) return; if (uvm_id_equal(src_id, uvm_va_range_get_policy(block->va_range)->preferred_location)) @@ -2343,7 +2756,10 @@ static void block_mark_memory_used(uvm_va_block_t *block, uvm_processor_id_t id) // If the block is of the max size and the GPU supports eviction, mark the // root chunk as used in PMM. - if (uvm_va_block_size(block) == UVM_CHUNK_SIZE_MAX && uvm_gpu_supports_eviction(gpu)) { + // HMM always allocates PAGE_SIZE GPU chunks so skip HMM va_blocks. + if (!uvm_va_block_is_hmm(block) && + uvm_va_block_size(block) == UVM_CHUNK_SIZE_MAX && + uvm_gpu_supports_eviction(gpu)) { // The chunk has to be there if this GPU is resident UVM_ASSERT(uvm_processor_mask_test(&block->resident, id)); uvm_pmm_gpu_mark_root_chunk_used(&gpu->pmm, uvm_va_block_gpu_state_get(block, gpu->id)->chunks[0]); @@ -2376,7 +2792,9 @@ static void block_clear_resident_processor(uvm_va_block_t *block, uvm_processor_ // If the block is of the max size and the GPU supports eviction, mark the // root chunk as unused in PMM. - if (uvm_va_block_size(block) == UVM_CHUNK_SIZE_MAX && uvm_gpu_supports_eviction(gpu)) { + if (!uvm_va_block_is_hmm(block) && + uvm_va_block_size(block) == UVM_CHUNK_SIZE_MAX && + uvm_gpu_supports_eviction(gpu)) { // The chunk may not be there any more when residency is cleared. uvm_va_block_gpu_state_t *gpu_state = uvm_va_block_gpu_state_get(block, gpu->id); if (gpu_state && gpu_state->chunks[0]) @@ -2384,39 +2802,6 @@ static void block_clear_resident_processor(uvm_va_block_t *block, uvm_processor_ } } -typedef enum -{ - BLOCK_TRANSFER_MODE_INTERNAL_MOVE = 1, - BLOCK_TRANSFER_MODE_INTERNAL_COPY = 2, - BLOCK_TRANSFER_MODE_INTERNAL_MOVE_TO_STAGE = 3, - BLOCK_TRANSFER_MODE_INTERNAL_MOVE_FROM_STAGE = 4, - BLOCK_TRANSFER_MODE_INTERNAL_COPY_TO_STAGE = 5, - BLOCK_TRANSFER_MODE_INTERNAL_COPY_FROM_STAGE = 6, - BLOCK_TRANSFER_MODE_INTERNAL_COPY_ONLY = 7 -} block_transfer_mode_internal_t; - -static uvm_va_block_transfer_mode_t get_block_transfer_mode_from_internal(block_transfer_mode_internal_t transfer_mode) -{ - switch (transfer_mode) { - // For HMM, BLOCK_TRANSFER_MODE_INTERNAL_COPY_ONLY is just part of a - // two phase move. First the pages are copied, then after - // migrate_vma_pages() succeeds, residency and mapping are updated. - case BLOCK_TRANSFER_MODE_INTERNAL_COPY_ONLY: - case BLOCK_TRANSFER_MODE_INTERNAL_MOVE: - case BLOCK_TRANSFER_MODE_INTERNAL_MOVE_TO_STAGE: - case BLOCK_TRANSFER_MODE_INTERNAL_MOVE_FROM_STAGE: - return UVM_VA_BLOCK_TRANSFER_MODE_MOVE; - - case BLOCK_TRANSFER_MODE_INTERNAL_COPY: - case BLOCK_TRANSFER_MODE_INTERNAL_COPY_TO_STAGE: - case BLOCK_TRANSFER_MODE_INTERNAL_COPY_FROM_STAGE: - return UVM_VA_BLOCK_TRANSFER_MODE_COPY; - } - - UVM_ASSERT_MSG(0, "Invalid transfer mode %u\n", transfer_mode); - return 0; -} - static bool block_phys_copy_contig_check(uvm_va_block_t *block, uvm_page_index_t page_index, const uvm_gpu_address_t *base_address, @@ -2437,12 +2822,13 @@ static bool block_phys_copy_contig_check(uvm_va_block_t *block, // on the processor. static bool is_block_phys_contig(uvm_va_block_t *block, uvm_processor_id_t id) { - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_first_in_block(block, NULL); + uvm_cpu_chunk_t *chunk; if (UVM_ID_IS_GPU(id)) return uvm_va_block_size(block) == block_gpu_chunk_size(block, block_get_gpu(block, id), 0); - return chunk && (uvm_va_block_size(block) <= uvm_cpu_chunk_get_size(chunk)); + chunk = uvm_cpu_chunk_first_in_region(block, uvm_va_block_region_from_block(block), NULL); + return chunk && (uvm_va_block_size(block) == uvm_cpu_chunk_get_size(chunk)); } static uvm_va_block_region_t block_phys_contig_region(uvm_va_block_t *block, @@ -2460,26 +2846,6 @@ static uvm_va_block_region_t block_phys_contig_region(uvm_va_block_t *block, } } -typedef struct -{ - // Location of the memory - uvm_processor_id_t id; - - // Whether the whole block has a single physically-contiguous chunk of - // storage on the processor. - bool is_block_contig; - - // Starting address of the physically-contiguous allocation, from the view - // of the copying GPU. Valid only if is_block_contig. - uvm_gpu_address_t address; -} block_copy_addr_t; - -typedef struct -{ - block_copy_addr_t src; - block_copy_addr_t dst; -} block_copy_state_t; - // Like block_phys_page_copy_address, but uses the address cached in bca when // possible. static uvm_gpu_address_t block_copy_get_address(uvm_va_block_t *block, @@ -2488,27 +2854,59 @@ static uvm_gpu_address_t block_copy_get_address(uvm_va_block_t *block, uvm_gpu_t *copying_gpu) { if (bca->is_block_contig) { - uvm_gpu_address_t addr = bca->address; + uvm_gpu_address_t addr = bca->gpu_address; addr.address += page_index * PAGE_SIZE; - UVM_ASSERT(block_phys_copy_contig_check(block, page_index, &bca->address, bca->id, copying_gpu)); + UVM_ASSERT(block_phys_copy_contig_check(block, page_index, &bca->gpu_address, bca->id, copying_gpu)); return addr; } return block_phys_page_copy_address(block, block_phys_page(bca->id, page_index), copying_gpu); } +static uvm_gpu_address_t block_copy_addr_get_virt(uvm_va_block_t *block, + block_copy_addr_t *bca, + uvm_page_index_t page_index, + uvm_gpu_t *copying_gpu) +{ + uvm_gpu_address_t gpu_address = block_copy_get_address(block, bca, page_index, copying_gpu); + return uvm_gpu_address_virtual_from_vidmem_phys(copying_gpu, gpu_address.address); +} + static void block_copy_push(uvm_va_block_t *block, - block_copy_state_t *state, + block_copy_state_t *copy_state, uvm_va_block_region_t region, uvm_push_t *push) { + uvm_gpu_address_t gpu_dst_address; + uvm_gpu_address_t gpu_src_address; + uvm_gpu_t *gpu = uvm_push_get_gpu(push); - uvm_gpu_t *copying_gpu = uvm_push_get_gpu(push); uvm_push_set_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); - copying_gpu->parent->ce_hal->memcopy(push, - block_copy_get_address(block, &state->dst, region.first, copying_gpu), - block_copy_get_address(block, &state->src, region.first, copying_gpu), - uvm_va_block_region_size(region)); + + gpu_dst_address = block_copy_get_address(block, ©_state->dst, region.first, gpu); + gpu_src_address = block_copy_get_address(block, ©_state->src, region.first, gpu); + gpu->parent->ce_hal->memcopy(push, gpu_dst_address, gpu_src_address, uvm_va_block_region_size(region)); +} + +static NV_STATUS block_copy_end_push(uvm_va_block_t *block, + block_copy_state_t *copy_state, + uvm_tracker_t *copy_tracker, + NV_STATUS push_status, + uvm_push_t *push) +{ + NV_STATUS tracker_status; + + // TODO: Bug 1766424: If the destination is a GPU and the copy was done + // by that GPU, use a GPU-local membar if no peer can currently + // map this page. When peer access gets enabled, do a MEMBAR_SYS + // at that point. + uvm_push_end(push); + + tracker_status = uvm_tracker_add_push_safe(copy_tracker, push); + if (push_status == NV_OK) + push_status = tracker_status; + + return push_status; } // Copies pages resident on the src_id processor to the dst_id processor @@ -2525,13 +2923,12 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, uvm_va_block_region_t region, uvm_page_mask_t *copy_mask, const uvm_page_mask_t *prefetch_page_mask, - block_transfer_mode_internal_t transfer_mode, + uvm_va_block_transfer_mode_t transfer_mode, uvm_page_mask_t *migrated_pages, NvU32 *copied_pages, uvm_tracker_t *copy_tracker) { - NV_STATUS tracker_status, status = NV_OK; - uvm_page_mask_t *src_resident_mask = uvm_va_block_resident_mask_get(block, src_id); + NV_STATUS status = NV_OK; uvm_page_mask_t *dst_resident_mask = uvm_va_block_resident_mask_get(block, dst_id); uvm_gpu_t *copying_gpu = NULL; uvm_push_t push; @@ -2545,15 +2942,14 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, const bool may_prefetch = (cause == UVM_MAKE_RESIDENT_CAUSE_REPLAYABLE_FAULT || cause == UVM_MAKE_RESIDENT_CAUSE_NON_REPLAYABLE_FAULT || cause == UVM_MAKE_RESIDENT_CAUSE_ACCESS_COUNTER) && !!prefetch_page_mask; - block_copy_state_t state = {0}; + block_copy_state_t copy_state = {0}; uvm_va_range_t *va_range = block->va_range; uvm_va_space_t *va_space = uvm_va_block_get_va_space(block); - const uvm_va_block_transfer_mode_t block_transfer_mode = get_block_transfer_mode_from_internal(transfer_mode); - state.src.id = src_id; - state.dst.id = dst_id; - state.src.is_block_contig = is_block_phys_contig(block, src_id); - state.dst.is_block_contig = is_block_phys_contig(block, dst_id); + copy_state.src.id = src_id; + copy_state.dst.id = dst_id; + copy_state.src.is_block_contig = is_block_phys_contig(block, src_id); + copy_state.dst.is_block_contig = is_block_phys_contig(block, dst_id); *copied_pages = 0; @@ -2572,28 +2968,27 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, rgr_has_changed = true; } + if (UVM_ID_IS_CPU(dst_id)) { + uvm_memcg_context_t memcg_context; + + // To support staging through CPU, populate CPU pages on demand. + // GPU destinations should have their pages populated already, but + // that might change if we add staging through GPUs. + uvm_memcg_context_start(&memcg_context, block_context->mm); + status = block_populate_pages_cpu(block, copy_mask, region, block_context); + uvm_memcg_context_end(&memcg_context); + if (status != NV_OK) + return status; + } + // TODO: Bug 3745051: This function is complicated and needs refactoring for_each_va_block_page_in_region_mask(page_index, copy_mask, region) { NvU64 page_start = uvm_va_block_cpu_page_address(block, page_index); - uvm_make_resident_cause_t page_cause = (may_prefetch && uvm_page_mask_test(prefetch_page_mask, page_index))? + uvm_make_resident_cause_t page_cause = (may_prefetch && uvm_page_mask_test(prefetch_page_mask, page_index)) ? UVM_MAKE_RESIDENT_CAUSE_PREFETCH: cause; UVM_ASSERT(block_check_resident_proximity(block, page_index, dst_id)); - - if (UVM_ID_IS_CPU(dst_id)) { - uvm_memcg_context_t memcg_context; - - // To support staging through CPU, populate CPU pages on demand. - // GPU destinations should have their pages populated already, but - // that might change if we add staging through GPUs. - uvm_memcg_context_start(&memcg_context, block_context->mm); - status = block_populate_page_cpu(block, page_index, block_context->mm); - uvm_memcg_context_end(&memcg_context); - if (status != NV_OK) - break; - } - UVM_ASSERT(block_processor_page_is_populated(block, dst_id, page_index)); // If we're not evicting and we're migrating away from the preferred @@ -2637,7 +3032,8 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, continue; if (!copying_gpu) { - status = block_copy_begin_push(block, dst_id, src_id, &block->tracker, &push); + status = block_copy_begin_push(block, ©_state, &block->tracker, &push); + if (status != NV_OK) break; copying_gpu = uvm_push_get_gpu(&push); @@ -2657,9 +3053,12 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, uvm_push_set_flag(&push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); } - block_update_page_dirty_state(block, dst_id, src_id, page_index); + if (!uvm_va_block_is_hmm(block)) + block_update_page_dirty_state(block, dst_id, src_id, page_index); if (last_index == region.outer) { + bool can_cache_src_phys_addr = copy_state.src.is_block_contig; + bool can_cache_dst_phys_addr = copy_state.dst.is_block_contig; contig_start_index = page_index; contig_cause = page_cause; @@ -2668,10 +3067,16 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, // NVLINK links. Therefore, for physically-contiguous block // storage, we cache the start address and compute the page address // using the page index. - if (state.src.is_block_contig) - state.src.address = block_phys_page_copy_address(block, block_phys_page(src_id, 0), copying_gpu); - if (state.dst.is_block_contig) - state.dst.address = block_phys_page_copy_address(block, block_phys_page(dst_id, 0), copying_gpu); + if (can_cache_src_phys_addr) { + copy_state.src.gpu_address = block_phys_page_copy_address(block, + block_phys_page(src_id, 0), + copying_gpu); + } + if (can_cache_dst_phys_addr) { + copy_state.dst.gpu_address = block_phys_page_copy_address(block, + block_phys_page(dst_id, 0), + copying_gpu); + } } else if ((page_index != last_index + 1) || contig_cause != page_cause) { uvm_va_block_region_t contig_region = uvm_va_block_region(contig_start_index, last_index + 1); @@ -2679,8 +3084,8 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, // If both src and dst are physically-contiguous, consolidate copies // of contiguous pages into a single method. - if (state.src.is_block_contig && state.dst.is_block_contig) - block_copy_push(block, &state, contig_region, &push); + if (copy_state.src.is_block_contig && copy_state.dst.is_block_contig) + block_copy_push(block, ©_state, contig_region, &push); uvm_perf_event_notify_migration(&va_space->perf_events, &push, @@ -2689,7 +3094,7 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, src_id, uvm_va_block_region_start(block, contig_region), uvm_va_block_region_size(contig_region), - block_transfer_mode, + transfer_mode, contig_cause, &block_context->make_resident); @@ -2697,8 +3102,8 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, contig_cause = page_cause; } - if (!state.src.is_block_contig || !state.dst.is_block_contig) - block_copy_push(block, &state, uvm_va_block_region_for_page(page_index), &push); + if (!copy_state.src.is_block_contig || !copy_state.dst.is_block_contig) + block_copy_push(block, ©_state, uvm_va_block_region_for_page(page_index), &push); last_index = page_index; } @@ -2708,8 +3113,8 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, uvm_va_block_region_t contig_region = uvm_va_block_region(contig_start_index, last_index + 1); UVM_ASSERT(uvm_va_block_region_contains_region(region, contig_region)); - if (state.src.is_block_contig && state.dst.is_block_contig) - block_copy_push(block, &state, contig_region, &push); + if (copy_state.src.is_block_contig && copy_state.dst.is_block_contig) + block_copy_push(block, ©_state, contig_region, &push); uvm_perf_event_notify_migration(&va_space->perf_events, &push, @@ -2718,83 +3123,23 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, src_id, uvm_va_block_region_start(block, contig_region), uvm_va_block_region_size(contig_region), - block_transfer_mode, + transfer_mode, contig_cause, &block_context->make_resident); - // TODO: Bug 1766424: If the destination is a GPU and the copy was done - // by that GPU, use a GPU-local membar if no peer can currently - // map this page. When peer access gets enabled, do a MEMBAR_SYS - // at that point. - uvm_push_end(&push); - tracker_status = uvm_tracker_add_push_safe(copy_tracker, &push); - if (status == NV_OK) - status = tracker_status; + status = block_copy_end_push(block, ©_state, copy_tracker, status, &push); } // Update VA block status bits // - // Only update the bits for the pages that succeded + // Only update the bits for the pages that succeeded if (status != NV_OK) uvm_page_mask_region_clear(copy_mask, uvm_va_block_region(page_index, PAGES_PER_UVM_VA_BLOCK)); *copied_pages = uvm_page_mask_weight(copy_mask); - - if (*copied_pages) { + if (*copied_pages) uvm_page_mask_or(migrated_pages, migrated_pages, copy_mask); - // For HMM, the residency is updated after migrate_vma_pages() succeeds. - if (transfer_mode != BLOCK_TRANSFER_MODE_INTERNAL_COPY_ONLY) { - uvm_page_mask_or(dst_resident_mask, dst_resident_mask, copy_mask); - block_set_resident_processor(block, dst_id); - } - - if (transfer_mode == BLOCK_TRANSFER_MODE_INTERNAL_MOVE_FROM_STAGE) { - // Check whether there are any resident pages left on src - if (!uvm_page_mask_andnot(src_resident_mask, src_resident_mask, copy_mask)) - block_clear_resident_processor(block, src_id); - } - - // If we are staging the copy due to read duplication, we keep the copy - // there - if (transfer_mode == BLOCK_TRANSFER_MODE_INTERNAL_COPY || - transfer_mode == BLOCK_TRANSFER_MODE_INTERNAL_COPY_TO_STAGE) - uvm_page_mask_or(&block->read_duplicated_pages, &block->read_duplicated_pages, copy_mask); - - if (transfer_mode == BLOCK_TRANSFER_MODE_INTERNAL_COPY_FROM_STAGE) - UVM_ASSERT(uvm_page_mask_subset(copy_mask, &block->read_duplicated_pages)); - - // Any move operation implies that mappings have been removed from all - // non-UVM-Lite GPUs - if (transfer_mode == BLOCK_TRANSFER_MODE_INTERNAL_MOVE || - transfer_mode == BLOCK_TRANSFER_MODE_INTERNAL_MOVE_TO_STAGE) - uvm_page_mask_andnot(&block->maybe_mapped_pages, &block->maybe_mapped_pages, copy_mask); - - // Record ReadDuplicate events here, after the residency bits have been - // updated - if (block_transfer_mode == UVM_VA_BLOCK_TRANSFER_MODE_COPY) - uvm_tools_record_read_duplicate(block, dst_id, region, copy_mask); - - // If we are migrating due to an eviction, set the GPU as evicted and - // mark the evicted pages. If we are migrating away from the CPU this - // means that those pages are not evicted. - if (cause == UVM_MAKE_RESIDENT_CAUSE_EVICTION) { - uvm_va_block_gpu_state_t *src_gpu_state = uvm_va_block_gpu_state_get(block, src_id); - UVM_ASSERT(src_gpu_state); - UVM_ASSERT(UVM_ID_IS_CPU(dst_id)); - - uvm_page_mask_or(&src_gpu_state->evicted, &src_gpu_state->evicted, copy_mask); - uvm_processor_mask_set(&block->evicted_gpus, src_id); - } - else if (UVM_ID_IS_GPU(dst_id) && uvm_processor_mask_test(&block->evicted_gpus, dst_id)) { - uvm_va_block_gpu_state_t *dst_gpu_state = uvm_va_block_gpu_state_get(block, dst_id); - UVM_ASSERT(dst_gpu_state); - - if (!uvm_page_mask_andnot(&dst_gpu_state->evicted, &dst_gpu_state->evicted, copy_mask)) - uvm_processor_mask_clear(&block->evicted_gpus, dst_id); - } - } - return status; } @@ -2811,7 +3156,7 @@ static NV_STATUS block_copy_resident_pages_mask(uvm_va_block_t *block, uvm_va_block_region_t region, const uvm_page_mask_t *page_mask, const uvm_page_mask_t *prefetch_page_mask, - block_transfer_mode_internal_t transfer_mode, + uvm_va_block_transfer_mode_t transfer_mode, NvU32 max_pages_to_copy, uvm_page_mask_t *migrated_pages, NvU32 *copied_pages_out, @@ -2820,7 +3165,7 @@ static NV_STATUS block_copy_resident_pages_mask(uvm_va_block_t *block, uvm_va_space_t *va_space = uvm_va_block_get_va_space(block); uvm_processor_id_t src_id; uvm_processor_mask_t search_mask; - uvm_page_mask_t *copy_mask = &block_context->make_resident.copy_resident_pages_between_mask; + uvm_page_mask_t *copy_mask = &block_context->make_resident.copy_resident_pages_mask; uvm_processor_mask_copy(&search_mask, src_processor_mask); @@ -2926,17 +3271,11 @@ static void block_copy_set_first_touch_residency(uvm_va_block_t *block, first_touch_mask); } -// Copy resident pages from other processors to the destination and mark any -// pages not resident anywhere as resident on the destination. +// Copy resident pages from other processors to the destination. // All the pages on the destination need to be populated by the caller first. // Pages not resident anywhere else need to be zeroed out as well. -// -// If UVM_VA_BLOCK_TRANSFER_MODE_COPY is passed, processors that already have a -// copy of the page will keep it. Conversely, if UVM_VA_BLOCK_TRANSFER_MODE_MOVE -// is passed, the page will no longer be resident in any processor other than -// dst_id. If UVM_VA_BLOCK_TRANSFER_MODE_COPY_ONLY is passed, the destination -// pages are copied into but the residency bits for source and destination are -// not updated. +// The transfer_mode is only used to tell uvm_perf_event_notify_migration() +// whether the copy is for a migration or read duplication. static NV_STATUS block_copy_resident_pages(uvm_va_block_t *block, uvm_va_block_context_t *block_context, uvm_processor_id_t dst_id, @@ -2956,9 +3295,9 @@ static NV_STATUS block_copy_resident_pages(uvm_va_block_t *block, uvm_page_mask_t *copy_page_mask = &block_context->make_resident.page_mask; uvm_page_mask_t *migrated_pages = &block_context->make_resident.pages_migrated; uvm_page_mask_t *staged_pages = &block_context->make_resident.pages_staged; - block_transfer_mode_internal_t transfer_mode_internal; uvm_page_mask_zero(migrated_pages); + uvm_page_mask_zero(staged_pages); if (page_mask) uvm_page_mask_andnot(copy_page_mask, page_mask, resident_mask); @@ -2967,8 +3306,6 @@ static NV_STATUS block_copy_resident_pages(uvm_va_block_t *block, missing_pages_count = uvm_page_mask_region_weight(copy_page_mask, region); - // If nothing needs to be copied, just check if we need to break - // read-duplication (i.e. transfer_mode is UVM_VA_BLOCK_TRANSFER_MODE_MOVE) if (missing_pages_count == 0) goto out; @@ -2980,20 +3317,13 @@ static NV_STATUS block_copy_resident_pages(uvm_va_block_t *block, uvm_processor_mask_zero(&src_processor_mask); if (!uvm_id_equal(dst_id, UVM_ID_CPU)) { - // If the destination is a GPU, first move everything from processors - // with copy access supported. Notably this will move pages from the CPU + // If the destination is a GPU, first copy everything from processors + // with copy access supported. Notably this will copy pages from the CPU // as well even if later some extra copies from CPU are required for // staged copies. uvm_processor_mask_and(&src_processor_mask, block_get_can_copy_from_mask(block, dst_id), &block->resident); uvm_processor_mask_clear(&src_processor_mask, dst_id); - if (transfer_mode == UVM_VA_BLOCK_TRANSFER_MODE_MOVE) - transfer_mode_internal = BLOCK_TRANSFER_MODE_INTERNAL_MOVE; - else if (transfer_mode == UVM_VA_BLOCK_TRANSFER_MODE_COPY) - transfer_mode_internal = BLOCK_TRANSFER_MODE_INTERNAL_COPY; - else - transfer_mode_internal = BLOCK_TRANSFER_MODE_INTERNAL_COPY_ONLY; - status = block_copy_resident_pages_mask(block, block_context, dst_id, @@ -3001,7 +3331,7 @@ static NV_STATUS block_copy_resident_pages(uvm_va_block_t *block, region, copy_page_mask, prefetch_page_mask, - transfer_mode_internal, + transfer_mode, missing_pages_count, migrated_pages, &pages_copied, @@ -3027,21 +3357,6 @@ static NV_STATUS block_copy_resident_pages(uvm_va_block_t *block, uvm_processor_mask_clear(&src_processor_mask, dst_id); uvm_processor_mask_clear(&src_processor_mask, UVM_ID_CPU); - uvm_page_mask_zero(staged_pages); - - if (transfer_mode == UVM_VA_BLOCK_TRANSFER_MODE_COPY_ONLY) - transfer_mode_internal = BLOCK_TRANSFER_MODE_INTERNAL_COPY_ONLY; - else if (UVM_ID_IS_CPU(dst_id)) { - transfer_mode_internal = transfer_mode == UVM_VA_BLOCK_TRANSFER_MODE_COPY? - BLOCK_TRANSFER_MODE_INTERNAL_COPY: - BLOCK_TRANSFER_MODE_INTERNAL_MOVE; - } - else { - transfer_mode_internal = transfer_mode == UVM_VA_BLOCK_TRANSFER_MODE_COPY? - BLOCK_TRANSFER_MODE_INTERNAL_COPY_TO_STAGE: - BLOCK_TRANSFER_MODE_INTERNAL_MOVE_TO_STAGE; - } - status = block_copy_resident_pages_mask(block, block_context, UVM_ID_CPU, @@ -3049,7 +3364,7 @@ static NV_STATUS block_copy_resident_pages(uvm_va_block_t *block, region, copy_page_mask, prefetch_page_mask, - transfer_mode_internal, + transfer_mode, missing_pages_count, staged_pages, &pages_copied_to_cpu, @@ -3072,13 +3387,6 @@ static NV_STATUS block_copy_resident_pages(uvm_va_block_t *block, goto out; uvm_tracker_clear(&local_tracker); - if (transfer_mode == UVM_VA_BLOCK_TRANSFER_MODE_MOVE) - transfer_mode_internal = BLOCK_TRANSFER_MODE_INTERNAL_MOVE_FROM_STAGE; - else if (transfer_mode == UVM_VA_BLOCK_TRANSFER_MODE_COPY) - transfer_mode_internal = BLOCK_TRANSFER_MODE_INTERNAL_COPY_FROM_STAGE; - else - transfer_mode_internal = BLOCK_TRANSFER_MODE_INTERNAL_COPY_ONLY; - // Now copy staged pages from the CPU to the destination. status = block_copy_resident_pages_between(block, block_context, @@ -3087,7 +3395,7 @@ static NV_STATUS block_copy_resident_pages(uvm_va_block_t *block, region, staged_pages, prefetch_page_mask, - transfer_mode_internal, + transfer_mode, migrated_pages, &pages_copied, &local_tracker); @@ -3103,57 +3411,23 @@ static NV_STATUS block_copy_resident_pages(uvm_va_block_t *block, UVM_ASSERT(pages_copied == pages_copied_to_cpu); out: - // Pages that weren't resident anywhere else were populated at the - // destination directly. Mark them as resident now. We only do it if there - // have been no errors because we cannot identify which pages failed. - // For HMM, don't do this until migrate_vma_pages() succeeds. - if (status == NV_OK && missing_pages_count > 0 && transfer_mode != UVM_VA_BLOCK_TRANSFER_MODE_COPY_ONLY) - block_copy_set_first_touch_residency(block, block_context, dst_id, region, page_mask); - - // Break read duplication - if (transfer_mode == UVM_VA_BLOCK_TRANSFER_MODE_MOVE) { - const uvm_page_mask_t *break_read_duplication_mask; - - if (status == NV_OK) { - break_read_duplication_mask = page_mask; - } - else { - // We reuse this mask since copy_page_mask is no longer used in the - // function - - if (page_mask) - uvm_page_mask_and(&block_context->make_resident.page_mask, resident_mask, page_mask); - else - uvm_page_mask_copy(&block_context->make_resident.page_mask, resident_mask); - - break_read_duplication_mask = &block_context->make_resident.page_mask; - } - break_read_duplication_in_region(block, block_context, dst_id, region, break_read_duplication_mask); - } - - // Accumulate the pages that migrated into the output mask - uvm_page_mask_or(&block_context->make_resident.pages_changed_residency, - &block_context->make_resident.pages_changed_residency, - migrated_pages); - // Add everything from the local tracker to the block's tracker. - // Notably this is also needed for handling block_copy_resident_pages_between() - // failures in the first loop. + // Notably this is also needed for handling + // block_copy_resident_pages_between() failures in the first loop. tracker_status = uvm_tracker_add_tracker_safe(&block->tracker, &local_tracker); uvm_tracker_deinit(&local_tracker); return status == NV_OK ? tracker_status : status; } -static NV_STATUS block_make_resident(uvm_va_block_t *va_block, - uvm_va_block_retry_t *va_block_retry, - uvm_va_block_context_t *va_block_context, - uvm_processor_id_t dest_id, - uvm_va_block_region_t region, - const uvm_page_mask_t *page_mask, - const uvm_page_mask_t *prefetch_page_mask, - uvm_make_resident_cause_t cause, - uvm_va_block_transfer_mode_t transfer_mode) +NV_STATUS uvm_va_block_make_resident_copy(uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t dest_id, + uvm_va_block_region_t region, + const uvm_page_mask_t *page_mask, + const uvm_page_mask_t *prefetch_page_mask, + uvm_make_resident_cause_t cause) { NV_STATUS status; uvm_processor_mask_t unmap_processor_mask; @@ -3185,6 +3459,7 @@ static NV_STATUS block_make_resident(uvm_va_block_t *va_block, uvm_page_mask_andnot(unmap_page_mask, page_mask, resident_mask); else uvm_page_mask_complement(unmap_page_mask, resident_mask); + uvm_page_mask_region_clear_outside(unmap_page_mask, region); // Unmap all pages not resident on the destination status = uvm_va_block_unmap_mask(va_block, va_block_context, &unmap_processor_mask, region, unmap_page_mask); @@ -3195,6 +3470,7 @@ static NV_STATUS block_make_resident(uvm_va_block_t *va_block, uvm_page_mask_and(unmap_page_mask, page_mask, &va_block->read_duplicated_pages); else uvm_page_mask_init_from_region(unmap_page_mask, region, &va_block->read_duplicated_pages); + uvm_page_mask_region_clear_outside(unmap_page_mask, region); // Also unmap read-duplicated pages excluding dest_id uvm_processor_mask_clear(&unmap_processor_mask, dest_id); @@ -3207,7 +3483,7 @@ static NV_STATUS block_make_resident(uvm_va_block_t *va_block, region, unmap_page_mask); - // Note that block_populate_pages and block_move_resident_pages also use + // Note that block_populate_pages and block_copy_resident_pages also use // va_block_context->make_resident.page_mask. unmap_page_mask = NULL; @@ -3215,76 +3491,77 @@ static NV_STATUS block_make_resident(uvm_va_block_t *va_block, if (status != NV_OK) return status; - status = block_copy_resident_pages(va_block, - va_block_context, - dest_id, - region, - page_mask, - prefetch_page_mask, - transfer_mode); - if (status != NV_OK) - return status; - - // Update eviction heuristics, if needed. Notably this could repeat the call - // done in block_set_resident_processor(), but that doesn't do anything bad - // and it's simpler to keep it in both places. - // - // Skip this if we didn't do anything (the input region and/or page mask was - // empty). - if (transfer_mode == UVM_VA_BLOCK_TRANSFER_MODE_MOVE && uvm_processor_mask_test(&va_block->resident, dest_id)) - block_mark_memory_used(va_block, dest_id); - - return NV_OK; + return block_copy_resident_pages(va_block, + va_block_context, + dest_id, + region, + page_mask, + prefetch_page_mask, + UVM_VA_BLOCK_TRANSFER_MODE_MOVE); } -NV_STATUS uvm_va_block_make_resident(uvm_va_block_t *va_block, - uvm_va_block_retry_t *va_block_retry, - uvm_va_block_context_t *va_block_context, - uvm_processor_id_t dest_id, - uvm_va_block_region_t region, - const uvm_page_mask_t *page_mask, - const uvm_page_mask_t *prefetch_page_mask, - uvm_make_resident_cause_t cause) +static void block_make_resident_clear_evicted(uvm_va_block_t *va_block, + uvm_processor_id_t dst_id, + uvm_page_mask_t *page_mask) { - return block_make_resident(va_block, - va_block_retry, - va_block_context, - dest_id, - region, - page_mask, - prefetch_page_mask, - cause, - UVM_VA_BLOCK_TRANSFER_MODE_MOVE); + uvm_va_block_gpu_state_t *dst_gpu_state = uvm_va_block_gpu_state_get(va_block, dst_id); + + UVM_ASSERT(dst_gpu_state); + + if (!uvm_page_mask_andnot(&dst_gpu_state->evicted, &dst_gpu_state->evicted, page_mask)) + uvm_processor_mask_clear(&va_block->evicted_gpus, dst_id); } -NV_STATUS uvm_va_block_make_resident_pre(uvm_va_block_t *va_block, - uvm_va_block_retry_t *va_block_retry, - uvm_va_block_context_t *va_block_context, - uvm_processor_id_t dest_id, - uvm_va_block_region_t region, - const uvm_page_mask_t *page_mask, - const uvm_page_mask_t *prefetch_page_mask, - uvm_make_resident_cause_t cause) +static void block_make_resident_update_state(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t dst_id, + uvm_va_block_region_t region, + uvm_page_mask_t *copy_mask, + uvm_make_resident_cause_t cause) { - return block_make_resident(va_block, - va_block_retry, - va_block_context, - dest_id, - region, - page_mask, - prefetch_page_mask, - cause, - UVM_VA_BLOCK_TRANSFER_MODE_COPY_ONLY); + uvm_page_mask_t *dst_resident_mask = uvm_va_block_resident_mask_get(va_block, dst_id); + + uvm_page_mask_or(dst_resident_mask, dst_resident_mask, copy_mask); + block_set_resident_processor(va_block, dst_id); + + // Accumulate the pages that migrated into the output mask. + uvm_page_mask_or(&va_block_context->make_resident.pages_changed_residency, + &va_block_context->make_resident.pages_changed_residency, + copy_mask); + + // Any move operation implies that mappings have been removed from all + // non-UVM-Lite GPUs. + uvm_page_mask_andnot(&va_block->maybe_mapped_pages, &va_block->maybe_mapped_pages, copy_mask); + + // If we are migrating due to an eviction, set the GPU as evicted and + // mark the evicted pages. If we are migrating away from the CPU this + // means that those pages are not evicted. + if (cause == UVM_MAKE_RESIDENT_CAUSE_EVICTION) { + uvm_processor_id_t src_id; + + UVM_ASSERT(UVM_ID_IS_CPU(dst_id)); + + // Note that the destination is the CPU so this loop excludes it. + for_each_gpu_id_in_mask(src_id, &va_block_context->make_resident.all_involved_processors) { + uvm_va_block_gpu_state_t *src_gpu_state = uvm_va_block_gpu_state_get(va_block, src_id); + + UVM_ASSERT(src_gpu_state); + + uvm_page_mask_or(&src_gpu_state->evicted, &src_gpu_state->evicted, copy_mask); + uvm_processor_mask_set(&va_block->evicted_gpus, src_id); + } + } + else if (UVM_ID_IS_GPU(dst_id) && uvm_processor_mask_test(&va_block->evicted_gpus, dst_id)) + block_make_resident_clear_evicted(va_block, dst_id, copy_mask); } -void uvm_va_block_make_resident_post(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, - uvm_va_block_region_t region, - const uvm_page_mask_t *page_mask) +void uvm_va_block_make_resident_finish(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_va_block_region_t region, + const uvm_page_mask_t *page_mask) { uvm_page_mask_t *migrated_pages = &va_block_context->make_resident.pages_migrated; uvm_processor_id_t dst_id = va_block_context->make_resident.dest_id; - uvm_page_mask_t *dst_resident_mask = uvm_va_block_resident_mask_get(va_block, dst_id); uvm_assert_mutex_locked(&va_block->lock); @@ -3293,20 +3570,18 @@ void uvm_va_block_make_resident_post(uvm_va_block_t *va_block, if (!uvm_page_mask_empty(migrated_pages)) { // The migrated pages are now resident on the destination. - uvm_page_mask_or(dst_resident_mask, dst_resident_mask, migrated_pages); - block_set_resident_processor(va_block, dst_id); + block_make_resident_update_state(va_block, + va_block_context, + dst_id, + region, + migrated_pages, + va_block_context->make_resident.cause); } // Pages that weren't resident anywhere else were populated at the - // destination directly. Mark them as resident now. We only do it if there - // have been no errors because we cannot identify which pages failed. - // For HMM, don't do this until migrate_vma_pages() succeeds. + // destination directly. Mark them as resident now. block_copy_set_first_touch_residency(va_block, va_block_context, dst_id, region, page_mask); - // Any move operation implies that mappings have been removed from all - // non-UVM-Lite GPUs. - uvm_page_mask_andnot(&va_block->maybe_mapped_pages, &va_block->maybe_mapped_pages, migrated_pages); - // Break read duplication and clear residency from other processors. break_read_duplication_in_region(va_block, va_block_context, dst_id, region, page_mask); @@ -3320,6 +3595,36 @@ void uvm_va_block_make_resident_post(uvm_va_block_t *va_block, block_mark_memory_used(va_block, dst_id); } +NV_STATUS uvm_va_block_make_resident(uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t dest_id, + uvm_va_block_region_t region, + const uvm_page_mask_t *page_mask, + const uvm_page_mask_t *prefetch_page_mask, + uvm_make_resident_cause_t cause) +{ + NV_STATUS status; + + status = uvm_va_block_make_resident_copy(va_block, + va_block_retry, + va_block_context, + dest_id, + region, + page_mask, + prefetch_page_mask, + cause); + if (status != NV_OK) + return status; + + uvm_va_block_make_resident_finish(va_block, + va_block_context, + region, + page_mask); + + return NV_OK; +} + // Combination function which prepares the input {region, page_mask} for // entering read-duplication. It: // - Unmaps all processors but revoke_id @@ -3379,6 +3684,11 @@ NV_STATUS uvm_va_block_make_resident_read_duplicate(uvm_va_block_t *va_block, { NV_STATUS status = NV_OK; uvm_processor_id_t src_id; + uvm_page_mask_t *dst_resident_mask; + uvm_page_mask_t *cpu_resident_mask; + uvm_page_mask_t *migrated_pages; + uvm_page_mask_t *staged_pages; + uvm_page_mask_t *first_touch_mask; // TODO: Bug 3660922: need to implement HMM read duplication support. UVM_ASSERT(!uvm_va_block_is_hmm(va_block)); @@ -3405,7 +3715,7 @@ NV_STATUS uvm_va_block_make_resident_read_duplicate(uvm_va_block_t *va_block, // - Revokes write access from the processor with the resident copy for_each_id_in_mask(src_id, &va_block->resident) { // Note that the below calls to block_populate_pages and - // block_move_resident_pages also use + // block_copy_resident_pages also use // va_block_context->make_resident.page_mask. uvm_page_mask_t *preprocess_page_mask = &va_block_context->make_resident.page_mask; const uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(va_block, src_id); @@ -3440,6 +3750,42 @@ NV_STATUS uvm_va_block_make_resident_read_duplicate(uvm_va_block_t *va_block, if (status != NV_OK) return status; + // Pages that weren't resident anywhere else were populated at the + // destination directly. Mark them as resident now, since there were no + // errors from block_copy_resident_pages() above. + // Note that va_block_context->scratch_page_mask is passed to + // block_copy_set_first_touch_residency() which is generally unsafe but in + // this case, block_copy_set_first_touch_residency() copies page_mask + // before scratch_page_mask could be clobbered. + migrated_pages = &va_block_context->make_resident.pages_migrated; + first_touch_mask = &va_block_context->scratch_page_mask; + uvm_page_mask_init_from_region(first_touch_mask, region, page_mask); + uvm_page_mask_andnot(first_touch_mask, first_touch_mask, migrated_pages); + + if (!uvm_page_mask_empty(first_touch_mask)) + block_copy_set_first_touch_residency(va_block, va_block_context, dest_id, region, first_touch_mask); + + staged_pages = &va_block_context->make_resident.pages_staged; + if (!UVM_ID_IS_CPU(dest_id) && !uvm_page_mask_empty(staged_pages)) { + cpu_resident_mask = uvm_va_block_resident_mask_get(va_block, UVM_ID_CPU); + uvm_page_mask_or(cpu_resident_mask, cpu_resident_mask, staged_pages); + block_set_resident_processor(va_block, UVM_ID_CPU); + uvm_page_mask_or(&va_block->read_duplicated_pages, &va_block->read_duplicated_pages, staged_pages); + uvm_tools_record_read_duplicate(va_block, UVM_ID_CPU, region, staged_pages); + } + + if (!uvm_page_mask_empty(migrated_pages)) { + dst_resident_mask = uvm_va_block_resident_mask_get(va_block, dest_id); + uvm_page_mask_or(dst_resident_mask, dst_resident_mask, migrated_pages); + block_set_resident_processor(va_block, dest_id); + uvm_page_mask_or(&va_block->read_duplicated_pages, &va_block->read_duplicated_pages, migrated_pages); + uvm_tools_record_read_duplicate(va_block, dest_id, region, migrated_pages); + } + + UVM_ASSERT(cause != UVM_MAKE_RESIDENT_CAUSE_EVICTION); + if (UVM_ID_IS_GPU(dest_id) && uvm_processor_mask_test(&va_block->evicted_gpus, dest_id)) + block_make_resident_clear_evicted(va_block, dest_id, migrated_pages); + // Update eviction heuristics, if needed. Notably this could repeat the call // done in block_set_resident_processor(), but that doesn't do anything bad // and it's simpler to keep it in both places. @@ -3558,7 +3904,7 @@ static bool block_check_chunk_indirect_peers(uvm_va_block_t *block, uvm_gpu_t *g } // Sanity check the given GPU's chunks array -static bool block_check_chunks(uvm_va_block_t *block, uvm_gpu_id_t id) +static bool block_check_gpu_chunks(uvm_va_block_t *block, uvm_gpu_id_t id) { uvm_va_block_gpu_state_t *gpu_state = uvm_va_block_gpu_state_get(block, id); uvm_gpu_t *gpu; @@ -3624,6 +3970,18 @@ static bool block_check_chunks(uvm_va_block_t *block, uvm_gpu_id_t id) return true; } +static bool block_check_chunks(uvm_va_block_t *va_block) +{ + uvm_gpu_id_t id; + + for_each_gpu_id(id) { + if (!block_check_gpu_chunks(va_block, id)) + return false; + } + + return block_check_cpu_chunks(va_block); +} + // Sanity checks for page mappings static bool block_check_mappings_page(uvm_va_block_t *block, uvm_page_index_t page_index) { @@ -3641,12 +3999,9 @@ static bool block_check_mappings_page(uvm_va_block_t *block, uvm_page_index_t pa UVM_ID_INVALID; const uvm_processor_mask_t *uvm_lite_gpus = block_get_uvm_lite_gpus(block); - uvm_va_block_page_authorized_processors(block, page_index, UVM_PROT_READ_WRITE_ATOMIC, - &atomic_mappings); - uvm_va_block_page_authorized_processors(block, page_index, UVM_PROT_READ_WRITE, - &write_mappings); - uvm_va_block_page_authorized_processors(block, page_index, UVM_PROT_READ_ONLY, - &read_mappings); + block_page_authorized_processors(block, page_index, UVM_PROT_READ_WRITE_ATOMIC, &atomic_mappings); + block_page_authorized_processors(block, page_index, UVM_PROT_READ_WRITE, &write_mappings); + block_page_authorized_processors(block, page_index, UVM_PROT_READ_ONLY, &read_mappings); // Each access bit implies all accesses below it UVM_ASSERT(uvm_processor_mask_subset(&atomic_mappings, &write_mappings)); @@ -3952,7 +4307,9 @@ static bool block_check_mappings_ptes(uvm_va_block_t *block, uvm_gpu_t *gpu) UVM_ASSERT(uvm_gpu_chunk_get_size(resident_gpu_state->chunks[0]) == UVM_CHUNK_SIZE_2M); } else { - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_first_in_block(block, NULL); + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_first_in_region(block, + uvm_va_block_region_from_block(block), + NULL); UVM_ASSERT(uvm_page_mask_full(&block->cpu.allocated)); UVM_ASSERT(chunk); @@ -4078,10 +4435,18 @@ static void block_unmap_cpu(uvm_va_block_t *block, uvm_va_block_region_t region, uvm_va_block_region_t subregion; NvU32 num_mapped_processors; - // Early-out if nothing in the region is mapped - if (!block_has_valid_mapping_cpu(block, region)) + // Early-out if nothing in the region is mapped or being unmapped. + if (!block_has_valid_mapping_cpu(block, region) || + (unmap_pages && !uvm_page_mask_intersects(unmap_pages, &block->cpu.pte_bits[UVM_PTE_BITS_CPU_READ]))) return; + // We can't actually unmap HMM ranges from the CPU here. + // Unmapping happens as part of migrate_vma_setup(). + if (uvm_va_block_is_hmm(block)) { + UVM_ASSERT(!uvm_va_block_is_hmm(block)); + return; + } + num_mapped_processors = uvm_processor_mask_get_count(&block->mapped); // If we are unmapping a page which we are tracking due to CPU faults with @@ -4095,12 +4460,9 @@ static void block_unmap_cpu(uvm_va_block_t *block, uvm_va_block_region_t region, if (!block_has_valid_mapping_cpu(block, subregion)) continue; - // We can't actually unmap HMM ranges from the CPU here. - // It happens as part of migrate_vma_setup(). - if (!uvm_va_block_is_hmm(block)) - unmap_mapping_range(&va_space->mapping, - uvm_va_block_region_start(block, subregion), - uvm_va_block_region_size(subregion), 1); + unmap_mapping_range(va_space->mapping, + uvm_va_block_region_start(block, subregion), + uvm_va_block_region_size(subregion), 1); for (pte_bit = 0; pte_bit < UVM_PTE_BITS_CPU_MAX; pte_bit++) uvm_page_mask_region_clear(&block->cpu.pte_bits[pte_bit], subregion); @@ -4226,7 +4588,7 @@ static void block_gpu_pte_write_4k(uvm_va_block_t *block, size_t i; // Assume that this mapping will be used to write to the page - if (new_prot > UVM_PROT_READ_ONLY && UVM_ID_IS_CPU(resident_id)) + if (new_prot > UVM_PROT_READ_ONLY && UVM_ID_IS_CPU(resident_id) && !uvm_va_block_is_hmm(block)) block_mark_cpu_page_dirty(block, page_index); if (page_index >= contig_region.outer) { @@ -4434,7 +4796,7 @@ static void block_gpu_pte_write_big(uvm_va_block_t *block, uvm_va_block_region_t big_region = uvm_va_block_big_page_region(block, big_page_index, big_page_size); // Assume that this mapping will be used to write to the page - if (new_prot > UVM_PROT_READ_ONLY && UVM_ID_IS_CPU(resident_id)) { + if (new_prot > UVM_PROT_READ_ONLY && UVM_ID_IS_CPU(resident_id) && !uvm_va_block_is_hmm(block)) { uvm_page_index_t page_index; for_each_va_block_page_in_region(page_index, big_region) @@ -4586,7 +4948,7 @@ static void block_gpu_pte_write_2m(uvm_va_block_t *block, UVM_ASSERT(new_prot != UVM_PROT_NONE); UVM_ASSERT(UVM_ID_IS_VALID(resident_id)); - if (UVM_ID_IS_CPU(resident_id)) + if (UVM_ID_IS_CPU(resident_id) && !uvm_va_block_is_hmm(block)) block_mark_cpu_page_dirty(block, 0); page_addr = block_phys_page_address(block, block_phys_page(resident_id, 0), gpu); @@ -4775,13 +5137,7 @@ static uvm_membar_t block_pte_op_membar(block_pte_op_t pte_op, uvm_gpu_t *gpu, u UVM_ASSERT(UVM_ID_IS_VALID(resident_id)); UVM_ASSERT(pte_op == BLOCK_PTE_OP_REVOKE); - // Permissions downgrades always need a membar on TLB invalidate. If the - // mapped memory was local, we only need a GPU-local membar. - if (uvm_id_equal(gpu->id, resident_id)) - return UVM_MEMBAR_GPU; - - // Otherwise, remote memory needs a sysmembar - return UVM_MEMBAR_SYS; + return uvm_hal_downgrade_membar_type(gpu, uvm_id_equal(gpu->id, resident_id)); } // Write the 2M PTE for {block, gpu} to the memory on resident_id with new_prot @@ -5605,17 +5961,26 @@ static void block_gpu_compute_new_pte_state(uvm_va_block_t *block, if (gpu_state->force_4k_ptes) return; + // Limit HMM GPU allocations to PAGE_SIZE since migrate_vma_*(), + // hmm_range_fault(), and make_device_exclusive_range() don't handle folios + // yet. Also, it makes mremap() difficult since the new address may not + // align with the GPU block size otherwise. + // If PAGE_SIZE is 64K, the code following this check is OK since 64K + // big_pages is supported on all HMM supported GPUs (Turing+). + // TODO: Bug 3368756: add support for transparent huge pages (THP). + if (uvm_va_block_is_hmm(block) && PAGE_SIZE == UVM_PAGE_SIZE_4K) + return; + UVM_ASSERT(uvm_page_mask_subset(pages_changing, page_mask_after)); - if (block_gpu_supports_2m(block, gpu)) { - // If all pages in the 2M mask have the same attributes after the - // operation is applied, we can use a 2M PTE. - if (uvm_page_mask_full(page_mask_after) && - (!UVM_ID_IS_CPU(resident_id) || is_block_phys_contig(block, UVM_ID_CPU))) { - new_pte_state->pte_is_2m = true; - new_pte_state->needs_4k = false; - return; - } + // If all pages in the 2M mask have the same attributes after the + // operation is applied, we can use a 2M PTE. + if (block_gpu_supports_2m(block, gpu) && + uvm_page_mask_full(page_mask_after) && + (UVM_ID_IS_INVALID(resident_id) || is_block_phys_contig(block, resident_id))) { + new_pte_state->pte_is_2m = true; + new_pte_state->needs_4k = false; + return; } // Find big PTEs with matching attributes @@ -5736,7 +6101,6 @@ static NV_STATUS block_alloc_pt_range_with_retry(uvm_va_block_t *va_block, uvm_tracker_t *pending_tracker) { uvm_va_block_gpu_state_t *gpu_state = uvm_va_block_gpu_state_get(va_block, gpu->id); - uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); uvm_gpu_va_space_t *gpu_va_space = uvm_va_block_get_gpu_va_space(va_block, gpu); uvm_page_tree_t *page_tables = &gpu_va_space->page_tables; uvm_va_block_test_t *va_block_test = uvm_va_block_get_test(va_block); @@ -5754,7 +6118,7 @@ static NV_STATUS block_alloc_pt_range_with_retry(uvm_va_block_t *va_block, // to allocate the lower levels. bool use_alloc_table = block_gpu_supports_2m(va_block, gpu) && page_size < UVM_PAGE_SIZE_2M; - uvm_assert_rwsem_locked(&va_space->lock); + // TODO: Bug 3898454: check locking requirement for UVM-HMM. UVM_ASSERT(page_table_range->table == NULL); if (va_block_test && va_block_test->page_table_allocation_retry_force_count > 0) { @@ -6004,7 +6368,8 @@ static NV_STATUS block_unmap_gpu(uvm_va_block_t *block, uvm_va_block_gpu_state_t *gpu_state = uvm_va_block_gpu_state_get(block, gpu->id); uvm_pte_bits_gpu_t pte_bit; uvm_push_t push; - uvm_membar_t tlb_membar = UVM_MEMBAR_GPU; + uvm_membar_t tlb_membar; + bool only_local_mappings; uvm_page_mask_t *pages_to_unmap = &block_context->mapping.page_mask; NV_STATUS status; uvm_va_block_new_pte_state_t *new_pte_state = &block_context->mapping.new_pte_state; @@ -6038,10 +6403,8 @@ static NV_STATUS block_unmap_gpu(uvm_va_block_t *block, if (status != NV_OK) return status; - // All PTE downgrades need a membar. If any of the unmapped PTEs pointed to - // remote memory, we must use a sysmembar. - if (block_has_remote_mapping_gpu(block, block_context, gpu->id, pages_to_unmap)) - tlb_membar = UVM_MEMBAR_SYS; + only_local_mappings = !block_has_remote_mapping_gpu(block, block_context, gpu->id, pages_to_unmap); + tlb_membar = uvm_hal_downgrade_membar_type(gpu, only_local_mappings); status = uvm_push_begin_acquire(gpu->channel_manager, UVM_CHANNEL_TYPE_MEMOPS, @@ -6210,6 +6573,27 @@ static uvm_prot_t compute_logical_prot(uvm_va_block_t *va_block, return logical_prot; } +static struct page *block_page_get(uvm_va_block_t *block, block_phys_page_t block_page) +{ + struct page *page; + + if (UVM_ID_IS_CPU(block_page.processor)) { + page = uvm_cpu_chunk_get_cpu_page(block, block_page.page_index); + } + else { + uvm_va_space_t *va_space = uvm_va_block_get_va_space(block); + uvm_gpu_t *gpu = uvm_va_space_get_gpu(va_space, block_page.processor); + size_t chunk_offset; + uvm_gpu_chunk_t *chunk = block_phys_page_chunk(block, block_page, &chunk_offset); + + UVM_ASSERT(gpu->parent->numa_info.enabled); + page = uvm_gpu_chunk_to_page(&gpu->pmm, chunk) + chunk_offset / PAGE_SIZE; + } + + UVM_ASSERT(page); + return page; +} + // Creates or upgrades a CPU mapping for the given page, updating the block's // mapping and pte_bits bitmaps as appropriate. Upon successful return, the page // will be mapped with at least new_prot permissions. @@ -6304,7 +6688,7 @@ static NV_STATUS block_map_cpu_page_to(uvm_va_block_t *block, // there's already a mapping present at fault_addr, so we have to unmap // first anyway when upgrading from RO -> RW. if (curr_prot != UVM_PROT_NONE) - unmap_mapping_range(&va_space->mapping, addr, PAGE_SIZE, 1); + unmap_mapping_range(va_space->mapping, addr, PAGE_SIZE, 1); // Don't map the CPU until prior copies and GPU PTE updates finish, // otherwise we might not stay coherent. @@ -6312,24 +6696,7 @@ static NV_STATUS block_map_cpu_page_to(uvm_va_block_t *block, if (status != NV_OK) return status; - if (UVM_ID_IS_CPU(resident_id)) { - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); - - // TODO: Bug 3283417: This can be removed if vm_insert_pages() is used instead of - // vm_insert_page(). - page = uvm_cpu_chunk_get_cpu_page(block, chunk, page_index); - UVM_ASSERT(page); - } - else { - uvm_gpu_t *gpu = uvm_va_space_get_gpu(va_space, resident_id); - size_t chunk_offset; - uvm_gpu_chunk_t *chunk = block_phys_page_chunk(block, block_phys_page(resident_id, page_index), &chunk_offset); - - UVM_ASSERT(gpu->parent->numa_info.enabled); - - page = uvm_gpu_chunk_to_page(&gpu->pmm, chunk) + chunk_offset / PAGE_SIZE; - } - + page = block_page_get(block, block_phys_page(resident_id, page_index)); return uvm_cpu_insert_page(vma, addr, page, new_prot); } @@ -6559,7 +6926,7 @@ static NV_STATUS block_map_gpu_to(uvm_va_block_t *va_block, } static void map_get_allowed_destinations(uvm_va_block_t *block, - uvm_va_policy_t *policy, + const uvm_va_policy_t *policy, uvm_processor_id_t id, uvm_processor_mask_t *allowed_mask) { @@ -6893,6 +7260,12 @@ NV_STATUS uvm_va_block_revoke_prot(uvm_va_block_t *va_block, if (prot_to_revoke == UVM_PROT_READ_WRITE_ATOMIC) return NV_OK; + if (uvm_va_block_is_hmm(va_block)) { + // Linux is responsible for CPU page table updates. + uvm_page_mask_region_clear(&va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_WRITE], region); + return NV_OK; + } + uvm_page_mask_init_from_region(running_page_mask, region, revoke_page_mask); if (uvm_page_mask_and(running_page_mask, running_page_mask, &va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_WRITE])) @@ -7151,7 +7524,6 @@ static void block_destroy_gpu_state(uvm_va_block_t *block, uvm_gpu_id_t id) uvm_tracker_wait(&block->tracker); block_gpu_unmap_phys_all_cpu_pages(block, gpu); - uvm_cpu_chunk_gpu_mapping_free(block, gpu->id); uvm_processor_mask_clear(&block->evicted_gpus, id); kmem_cache_free(g_uvm_va_block_gpu_state_cache, gpu_state); @@ -7405,13 +7777,22 @@ static NV_STATUS block_evict_pages_from_gpu(uvm_va_block_t *va_block, uvm_gpu_t // Move all subregions resident on the GPU to the CPU for_each_va_block_subregion_in_mask(subregion, resident, region) { - status = uvm_va_block_migrate_locked(va_block, - NULL, - block_context, - subregion, - UVM_ID_CPU, - UVM_MIGRATE_MODE_MAKE_RESIDENT_AND_MAP, - NULL); + if (uvm_va_block_is_hmm(va_block)) { + status = uvm_hmm_va_block_evict_pages_from_gpu(va_block, + gpu, + block_context, + resident, + subregion); + } + else { + status = uvm_va_block_migrate_locked(va_block, + NULL, + block_context, + subregion, + UVM_ID_CPU, + UVM_MIGRATE_MODE_MAKE_RESIDENT_AND_MAP, + NULL); + } if (status != NV_OK) return status; } @@ -7420,9 +7801,7 @@ static NV_STATUS block_evict_pages_from_gpu(uvm_va_block_t *va_block, uvm_gpu_t return NV_OK; } -// This handles allocation-retry internally and hence might unlock and relock -// block's lock. -static void block_unregister_gpu_locked(uvm_va_block_t *va_block, uvm_gpu_t *gpu, struct mm_struct *mm) +void uvm_va_block_unregister_gpu_locked(uvm_va_block_t *va_block, uvm_gpu_t *gpu, struct mm_struct *mm) { NV_STATUS status; uvm_va_block_gpu_state_t *gpu_state = uvm_va_block_gpu_state_get(va_block, gpu->id); @@ -7467,7 +7846,7 @@ void uvm_va_block_unregister_gpu(uvm_va_block_t *va_block, uvm_gpu_t *gpu, struc // Take the lock internally to not expose the caller to allocation-retry. uvm_mutex_lock(&va_block->lock); - block_unregister_gpu_locked(va_block, gpu, mm); + uvm_va_block_unregister_gpu_locked(va_block, gpu, mm); uvm_mutex_unlock(&va_block->lock); } @@ -7496,6 +7875,7 @@ static void block_kill(uvm_va_block_t *block) NV_STATUS status; uvm_va_block_region_t region = uvm_va_block_region_from_block(block); uvm_page_index_t page_index; + uvm_page_index_t next_page_index; if (uvm_va_block_is_dead(block)) return; @@ -7510,6 +7890,14 @@ static void block_kill(uvm_va_block_t *block) if (!uvm_processor_mask_empty(&block->mapped)) { uvm_va_block_context_t *block_context = uvm_va_space_block_context(va_space, NULL); + // HMM CPU mappings are controlled by Linux so no need to unmap. + // Remote GPU mappings will be removed below. + if (uvm_va_block_is_hmm(block) && uvm_processor_mask_test(&block->mapped, UVM_ID_CPU)) { + uvm_page_mask_zero(&block->cpu.pte_bits[UVM_PTE_BITS_CPU_WRITE]); + uvm_page_mask_zero(&block->cpu.pte_bits[UVM_PTE_BITS_CPU_READ]); + uvm_processor_mask_clear(&block->mapped, UVM_ID_CPU); + } + // We could only be killed with mapped GPU state by VA range free or VA // space teardown, so it's safe to use the va_space's block_context // because both of those have the VA space lock held in write mode. @@ -7530,16 +7918,14 @@ static void block_kill(uvm_va_block_t *block) UVM_ASSERT(block_check_processor_not_mapped(block, UVM_ID_CPU)); // Free CPU pages - for_each_va_block_page(page_index, block) { - chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); - if (!chunk) - continue; - + for_each_cpu_chunk_in_block_safe(chunk, page_index, next_page_index, block) { // be conservative. - // Tell the OS we wrote to the page because we sometimes clear the dirty bit after writing to it. - uvm_cpu_chunk_mark_dirty(chunk, page_index); - uvm_cpu_chunk_remove_from_block(block, chunk, page_index); - uvm_cpu_chunk_put(chunk); + // Tell the OS we wrote to the page because we sometimes clear the dirty + // bit after writing to it. HMM dirty flags are managed by the kernel. + if (!uvm_va_block_is_hmm(block)) + uvm_cpu_chunk_mark_dirty(chunk, 0); + uvm_cpu_chunk_remove_from_block(block, page_index); + uvm_cpu_chunk_free(chunk); } uvm_kvfree((void *)block->cpu.chunks); @@ -7591,6 +7977,83 @@ void uvm_va_block_kill(uvm_va_block_t *va_block) uvm_va_block_release(va_block); } +static void block_gpu_release_region(uvm_va_block_t *va_block, + uvm_gpu_id_t gpu_id, + uvm_va_block_gpu_state_t *gpu_state, + uvm_page_mask_t *page_mask, + uvm_va_block_region_t region) +{ + uvm_page_index_t page_index; + + for_each_va_block_page_in_region_mask(page_index, page_mask, region) { + uvm_gpu_chunk_t *gpu_chunk = gpu_state->chunks[page_index]; + + if (!gpu_chunk) + continue; + + // TODO: Bug 3898467: unmap indirect peers when freeing GPU chunks + + uvm_mmu_chunk_unmap(gpu_chunk, &va_block->tracker); + + // The GPU chunk will be freed when the device private reference drops. + if (uvm_page_mask_test_and_clear(&gpu_state->resident, page_index) && + uvm_page_mask_empty(&gpu_state->resident)) + block_clear_resident_processor(va_block, gpu_id); + + gpu_state->chunks[page_index] = NULL; + } +} + +void uvm_va_block_munmap_region(uvm_va_block_t *va_block, + uvm_va_block_region_t region) +{ + uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); + uvm_perf_event_data_t event_data; + uvm_gpu_id_t gpu_id; + + UVM_ASSERT(uvm_va_block_is_hmm(va_block)); + uvm_assert_mutex_locked(&va_block->lock); + + // Reset thrashing state for the region. + event_data.block_munmap.block = va_block; + event_data.block_munmap.region = region; + uvm_perf_event_notify(&va_space->perf_events, UVM_PERF_EVENT_BLOCK_MUNMAP, &event_data); + + // Set a flag so that GPU fault events are flushed since they might refer + // to the region being unmapped. + // Note that holding the va_block lock prevents GPU VA spaces from + // being removed so the registered_gpu_va_spaces mask is stable. + for_each_gpu_id_in_mask(gpu_id, &va_space->registered_gpu_va_spaces) { + uvm_processor_mask_set_atomic(&va_space->needs_fault_buffer_flush, gpu_id); + } + + // Release any remaining vidmem chunks in the given region. + for_each_gpu_id(gpu_id) { + uvm_va_block_gpu_state_t *gpu_state = uvm_va_block_gpu_state_get(va_block, gpu_id); + + if (!gpu_state) + continue; + + uvm_page_mask_region_clear(&gpu_state->evicted, region); + if (uvm_page_mask_empty(&gpu_state->evicted)) + uvm_processor_mask_clear(&va_block->evicted_gpus, gpu_id); + + if (gpu_state->chunks) { + block_gpu_release_region(va_block, gpu_id, gpu_state, NULL, region); + + // TODO: bug 3660922: Need to update the read duplicated pages mask + // when read duplication is supported for HMM. + } + else { + UVM_ASSERT(!uvm_processor_mask_test(&va_block->resident, gpu_id)); + } + } + + uvm_va_policy_clear(va_block, + uvm_va_block_region_start(va_block, region), + uvm_va_block_region_end(va_block, region)); +} + static NV_STATUS block_split_presplit_ptes_gpu(uvm_va_block_t *existing, uvm_va_block_t *new, uvm_gpu_t *gpu) { uvm_va_block_gpu_state_t *existing_gpu_state = uvm_va_block_gpu_state_get(existing, gpu->id); @@ -7713,15 +8176,16 @@ typedef struct uvm_chunk_size_t chunk_size; } block_gpu_chunk_split_state_t; -static void block_gpu_chunk_get_split_state(block_gpu_chunk_split_state_t *state, +static void block_gpu_chunk_get_split_state(uvm_va_block_t *block, + block_gpu_chunk_split_state_t *state, NvU64 start, NvU64 end, uvm_page_index_t page_index, uvm_gpu_t *gpu) { NvU64 size = end - start + 1; - state->num_chunks = block_num_gpu_chunks_range(start, size, gpu); - state->chunk_index = uvm_va_block_gpu_chunk_index_range(start, size, gpu, page_index, &state->chunk_size); + state->num_chunks = block_num_gpu_chunks_range(block, start, size, gpu); + state->chunk_index = block_gpu_chunk_index_range(block, start, size, gpu, page_index, &state->chunk_size); } static void block_merge_chunk(uvm_va_block_t *block, uvm_gpu_t *gpu, uvm_gpu_chunk_t *chunk) @@ -7755,9 +8219,24 @@ static NV_STATUS block_presplit_gpu_chunks(uvm_va_block_t *existing, uvm_va_bloc NV_STATUS status; block_gpu_chunk_split_state_t existing_before_state, existing_after_state, new_state; - block_gpu_chunk_get_split_state(&existing_before_state, existing->start, existing->end, split_page_index, gpu); - block_gpu_chunk_get_split_state(&existing_after_state, existing->start, new->start - 1, split_page_index - 1, gpu); - block_gpu_chunk_get_split_state(&new_state, new->start, new->end, 0, gpu); + block_gpu_chunk_get_split_state(existing, + &existing_before_state, + existing->start, + existing->end, + split_page_index, + gpu); + block_gpu_chunk_get_split_state(existing, + &existing_after_state, + existing->start, + new->start - 1, + split_page_index - 1, + gpu); + block_gpu_chunk_get_split_state(new, + &new_state, + new->start, + new->end, + 0, + gpu); // Even though we're splitting existing, we could wind up requiring a larger // chunks array if we split a large chunk into many smaller ones. @@ -7837,33 +8316,89 @@ error: return status; } -static NV_STATUS block_split_cpu_chunk_to_size(uvm_va_block_t *block, - uvm_page_index_t page_index, - uvm_cpu_chunk_t *chunk, - uvm_chunk_size_t new_size) +static NV_STATUS block_split_cpu_chunk_to_64k(uvm_va_block_t *block) { - size_t num_new_chunks = uvm_cpu_chunk_get_size(chunk) / new_size; - uvm_cpu_chunk_t **new_chunks = NULL; + uvm_cpu_chunk_storage_mixed_t *mixed; + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, 0); + NV_STATUS status; + + UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) == UVM_CHUNK_SIZE_2M); + UVM_ASSERT(uvm_cpu_storage_get_type(block) == UVM_CPU_CHUNK_STORAGE_CHUNK); + + mixed = uvm_kvmalloc_zero(sizeof(*mixed)); + if (!mixed) + return NV_ERR_NO_MEMORY; + + status = uvm_cpu_chunk_split(chunk, (uvm_cpu_chunk_t **)&mixed->slots); + if (status != NV_OK) { + uvm_kvfree(mixed); + return status; + } + + bitmap_fill(mixed->big_chunks, MAX_BIG_CPU_CHUNK_SLOTS_PER_UVM_VA_BLOCK); + block->cpu.chunks = (unsigned long)mixed | UVM_CPU_CHUNK_STORAGE_MIXED; + return status; +} + +static NV_STATUS block_split_cpu_chunk_to_4k(uvm_va_block_t *block, uvm_page_index_t page_index) +{ + uvm_cpu_chunk_storage_mixed_t *mixed; + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); + uvm_cpu_chunk_t **small_chunks; + size_t slot_index; + NV_STATUS status; + + UVM_ASSERT(chunk); + UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) == UVM_CHUNK_SIZE_64K); + UVM_ASSERT(uvm_cpu_storage_get_type(block) == UVM_CPU_CHUNK_STORAGE_MIXED); + + mixed = uvm_cpu_storage_get_ptr(block); + slot_index = compute_slot_index(block, page_index); + small_chunks = uvm_kvmalloc_zero(sizeof(*small_chunks) * MAX_SMALL_CHUNKS_PER_BIG_SLOT); + if (!small_chunks) + return NV_ERR_NO_MEMORY; + + status = uvm_cpu_chunk_split(chunk, small_chunks); + if (status != NV_OK) { + uvm_kvfree(small_chunks); + return status; + } + + mixed->slots[slot_index] = small_chunks; + clear_bit(slot_index, mixed->big_chunks); + return status; +} + +static NV_STATUS block_split_cpu_chunk_one(uvm_va_block_t *block, uvm_page_index_t page_index) +{ + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); + uvm_chunk_size_t chunk_size = uvm_cpu_chunk_get_size(chunk); + uvm_chunk_size_t new_size; uvm_gpu_t *gpu; NvU64 gpu_mapping_addr; uvm_processor_mask_t gpu_split_mask; uvm_gpu_id_t id; NV_STATUS status; - size_t i; - UVM_ASSERT(IS_ALIGNED(uvm_cpu_chunk_get_size(chunk), new_size)); + if (chunk_size == UVM_CHUNK_SIZE_2M) + new_size = UVM_CHUNK_SIZE_64K; + else + new_size = UVM_CHUNK_SIZE_4K; + + UVM_ASSERT(IS_ALIGNED(chunk_size, new_size)); uvm_processor_mask_zero(&gpu_split_mask); for_each_gpu_id(id) { if (!uvm_va_block_gpu_state_get(block, id)) continue; + gpu = block_get_gpu(block, id); + // If the parent chunk has not been mapped, there is nothing to split. - gpu_mapping_addr = uvm_cpu_chunk_get_gpu_mapping_addr(block, page_index, chunk, id); + gpu_mapping_addr = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent); if (gpu_mapping_addr == 0) continue; - gpu = block_get_gpu(block, id); status = uvm_pmm_sysmem_mappings_split_gpu_mappings(&gpu->pmm_reverse_sysmem_mappings, gpu_mapping_addr, new_size); @@ -7873,39 +8408,91 @@ static NV_STATUS block_split_cpu_chunk_to_size(uvm_va_block_t *block, uvm_processor_mask_set(&gpu_split_mask, id); } - uvm_cpu_chunk_remove_from_block(block, chunk, page_index); - new_chunks = uvm_kvmalloc(num_new_chunks * sizeof(*new_chunks)); - if (new_chunks) - status = uvm_cpu_chunk_split(block, chunk, new_size, UVM_CPU_CHUNK_PAGE_INDEX(chunk, page_index), new_chunks); + if (new_size == UVM_CHUNK_SIZE_64K) + status = block_split_cpu_chunk_to_64k(block); else - status = NV_ERR_NO_MEMORY; + status = block_split_cpu_chunk_to_4k(block, page_index); if (status != NV_OK) { - uvm_cpu_chunk_insert_in_block(block, chunk, UVM_CPU_CHUNK_PAGE_INDEX(chunk, page_index)); - merge: - for_each_gpu_id_in_mask (id, &gpu_split_mask) { - gpu_mapping_addr = uvm_cpu_chunk_get_gpu_mapping_addr(block, page_index, chunk, id); + for_each_gpu_id_in_mask(id, &gpu_split_mask) { gpu = block_get_gpu(block, id); + gpu_mapping_addr = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent); uvm_pmm_sysmem_mappings_merge_gpu_mappings(&gpu->pmm_reverse_sysmem_mappings, gpu_mapping_addr, - uvm_cpu_chunk_get_size(chunk)); - } - } else { - for (i = 0; i < num_new_chunks; i++) { - status = uvm_cpu_chunk_insert_in_block(block, - new_chunks[i], - UVM_CPU_CHUNK_PAGE_INDEX(new_chunks[i], - (page_index + - (i * (new_size / PAGE_SIZE))))); - UVM_ASSERT(status == NV_OK); + chunk_size); } } - uvm_kvfree(new_chunks); return status; } +static NV_STATUS block_prealloc_cpu_chunk_storage(uvm_va_block_t *existing, uvm_va_block_t *new) +{ + uvm_cpu_chunk_storage_mixed_t *existing_mixed; + uvm_cpu_chunk_storage_mixed_t *new_mixed = NULL; + size_t slot_offset; + size_t existing_slot; + NV_STATUS status = NV_OK; + + UVM_ASSERT(uvm_cpu_storage_get_type(existing) == UVM_CPU_CHUNK_STORAGE_MIXED); + existing_mixed = uvm_cpu_storage_get_ptr(existing); + + // Pre-allocate chunk storage for the new block. By definition, the new block + // will contain either 64K and/or 4K chunks. + // + // We do this here so there are no failures in block_split_cpu(). + new_mixed = uvm_kvmalloc_zero(sizeof(*new_mixed)); + if (!new_mixed) + return NV_ERR_NO_MEMORY; + + slot_offset = compute_slot_index(existing, uvm_va_block_cpu_page_index(existing, new->start)); + existing_slot = slot_offset; + for_each_clear_bit_from(existing_slot, existing_mixed->big_chunks, MAX_BIG_CPU_CHUNK_SLOTS_PER_UVM_VA_BLOCK) { + size_t new_slot = existing_slot - slot_offset; + + if (existing_mixed->slots[existing_slot]) { + uvm_cpu_chunk_t **small_chunks = uvm_kvmalloc_zero(sizeof(*small_chunks) * MAX_SMALL_CHUNKS_PER_BIG_SLOT); + + if (!small_chunks) { + status = NV_ERR_NO_MEMORY; + goto done; + } + + new_mixed->slots[new_slot] = small_chunks; + } + } + + new->cpu.chunks = (unsigned long)new_mixed | UVM_CPU_CHUNK_STORAGE_MIXED; + UVM_ASSERT(status == NV_OK); + +done: + if (status != NV_OK) { + for (; existing_slot > slot_offset; existing_slot--) + uvm_kvfree(new_mixed->slots[existing_slot - slot_offset]); + + uvm_kvfree(new_mixed); + } + + return status; +} + +static void block_free_cpu_chunk_storage(uvm_va_block_t *block) +{ + if (block->cpu.chunks) { + uvm_cpu_chunk_storage_mixed_t *mixed; + size_t slot_index; + + UVM_ASSERT(uvm_cpu_storage_get_type(block) == UVM_CPU_CHUNK_STORAGE_MIXED); + mixed = uvm_cpu_storage_get_ptr(block); + for (slot_index = 0; slot_index < MAX_BIG_CPU_CHUNK_SLOTS_PER_UVM_VA_BLOCK; slot_index++) + uvm_kvfree(mixed->slots[slot_index]); + + uvm_kvfree(mixed); + block->cpu.chunks = 0; + } +} + // Perform any CPU chunk splitting that may be required for this block split. // Just like block_presplit_gpu_chunks, no chunks are moved to the new block. static NV_STATUS block_presplit_cpu_chunks(uvm_va_block_t *existing, uvm_va_block_t *new) @@ -7917,16 +8504,15 @@ static NV_STATUS block_presplit_cpu_chunks(uvm_va_block_t *existing, uvm_va_bloc NV_STATUS status = NV_OK; UVM_ASSERT(!IS_ALIGNED(new->start, UVM_VA_BLOCK_SIZE)); + splitting_chunk = uvm_cpu_chunk_get_chunk_for_page(existing, page_index); // If the page covering the split point has not been populated, there is no // need to split. - if (!uvm_page_mask_test(&existing->cpu.allocated, page_index)) + if (!splitting_chunk) return NV_OK; - splitting_chunk = uvm_cpu_chunk_get_chunk_for_page(existing, page_index); - - // If the chunk spanning the split point is already at the correct size, - // there is nothing to do. + // If the split point is aligned on the chunk size, there is no need to + // split. if (IS_ALIGNED(new->start, uvm_cpu_chunk_get_size(splitting_chunk))) return NV_OK; @@ -7936,59 +8522,59 @@ static NV_STATUS block_presplit_cpu_chunks(uvm_va_block_t *existing, uvm_va_bloc split_sizes &= ~(IS_ALIGNED(new->start, UVM_CHUNK_SIZE_64K) ? UVM_CHUNK_SIZE_64K - 1 : 0); for_each_chunk_size_rev(subchunk_size, split_sizes) { - status = block_split_cpu_chunk_to_size(existing, page_index, splitting_chunk, subchunk_size); + status = block_split_cpu_chunk_one(existing, page_index); if (status != NV_OK) return status; - - splitting_chunk = uvm_cpu_chunk_get_chunk_for_page(existing, page_index); } - return NV_OK; + return block_prealloc_cpu_chunk_storage(existing, new); } -static NV_STATUS block_merge_cpu_chunks_to_size(uvm_va_block_t *block, - uvm_chunk_size_t size, - uvm_page_index_t page_index) +static void block_merge_cpu_chunks_to_64k(uvm_va_block_t *block, uvm_page_index_t page_index) { - uvm_cpu_chunk_t *chunk; - size_t num_merge_chunks; - uvm_chunk_size_t chunk_size; - uvm_cpu_chunk_t **merge_chunks; + uvm_cpu_chunk_storage_mixed_t *mixed = uvm_cpu_storage_get_ptr(block); + size_t slot_index = compute_slot_index(block, page_index); + uvm_cpu_chunk_t **small_chunks = mixed->slots[slot_index]; + uvm_cpu_chunk_t *merged_chunk; + + UVM_ASSERT(uvm_cpu_storage_get_type(block) == UVM_CPU_CHUNK_STORAGE_MIXED); + UVM_ASSERT(small_chunks); + UVM_ASSERT(!test_bit(slot_index, mixed->big_chunks)); + + merged_chunk = uvm_cpu_chunk_merge(small_chunks); + mixed->slots[slot_index] = merged_chunk; + set_bit(slot_index, mixed->big_chunks); + uvm_kvfree(small_chunks); +} + +static void block_merge_cpu_chunks_to_2m(uvm_va_block_t *block, uvm_page_index_t page_index) +{ + uvm_cpu_chunk_storage_mixed_t *mixed = uvm_cpu_storage_get_ptr(block); + uvm_cpu_chunk_t **big_chunks = (uvm_cpu_chunk_t **)&mixed->slots; + uvm_cpu_chunk_t *merged_chunk; + + UVM_ASSERT(uvm_cpu_storage_get_type(block) == UVM_CPU_CHUNK_STORAGE_MIXED); + UVM_ASSERT(bitmap_full(mixed->big_chunks, MAX_BIG_CPU_CHUNK_SLOTS_PER_UVM_VA_BLOCK)); + + merged_chunk = uvm_cpu_chunk_merge(big_chunks); + block->cpu.chunks = (unsigned long)merged_chunk | UVM_CPU_CHUNK_STORAGE_CHUNK; + uvm_kvfree(mixed); +} + +static void block_merge_cpu_chunks_one(uvm_va_block_t *block, uvm_page_index_t page_index) +{ + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); uvm_gpu_id_t id; - size_t i; - NV_STATUS status; + + if (uvm_cpu_chunk_get_size(chunk) == UVM_CHUNK_SIZE_4K) { + block_merge_cpu_chunks_to_64k(block, page_index); + } + else { + UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) == UVM_CHUNK_SIZE_64K); + block_merge_cpu_chunks_to_2m(block, page_index); + } chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); - chunk_size = uvm_cpu_chunk_get_size(chunk); - num_merge_chunks = size / chunk_size; - - // It's OK if we can't merge here. We know that the CPU chunk split - // operation completed successfully. Therefore, the CPU chunks are in a - // sane state. - merge_chunks = uvm_kvmalloc(num_merge_chunks * sizeof(*merge_chunks)); - if (!merge_chunks) - return NV_ERR_NO_MEMORY; - - for (i = 0; i < num_merge_chunks; i++) { - merge_chunks[i] = uvm_cpu_chunk_get_chunk_for_page(block, page_index + (i * (chunk_size / PAGE_SIZE))); - UVM_ASSERT(merge_chunks[i]); - UVM_ASSERT(uvm_cpu_chunk_get_size(merge_chunks[i]) == chunk_size); - uvm_cpu_chunk_remove_from_block(block, merge_chunks[i], page_index + (i * (chunk_size / PAGE_SIZE))); - } - - // Merge the CPU chunk. If a merge was not done, re-insert the original chunks. - status = uvm_cpu_chunk_merge(block, merge_chunks, num_merge_chunks, size, &chunk); - if (status == NV_WARN_NOTHING_TO_DO) { - for (i = 0; i < num_merge_chunks; i++) - uvm_cpu_chunk_insert_in_block(block, merge_chunks[i], page_index + (i * (chunk_size / PAGE_SIZE))); - - goto done; - } - - UVM_ASSERT(status == NV_OK); - - status = uvm_cpu_chunk_insert_in_block(block, chunk, page_index); - UVM_ASSERT(status == NV_OK); for_each_gpu_id(id) { NvU64 gpu_mapping_addr; @@ -7997,17 +8583,15 @@ static NV_STATUS block_merge_cpu_chunks_to_size(uvm_va_block_t *block, if (!uvm_va_block_gpu_state_get(block, id)) continue; - gpu_mapping_addr = uvm_cpu_chunk_get_gpu_mapping_addr(block, page_index, chunk, id); + gpu = block_get_gpu(block, id); + gpu_mapping_addr = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent); if (gpu_mapping_addr == 0) continue; - gpu = block_get_gpu(block, id); - uvm_pmm_sysmem_mappings_merge_gpu_mappings(&gpu->pmm_reverse_sysmem_mappings, gpu_mapping_addr, size); + uvm_pmm_sysmem_mappings_merge_gpu_mappings(&gpu->pmm_reverse_sysmem_mappings, + gpu_mapping_addr, + uvm_cpu_chunk_get_size(chunk)); } - -done: - uvm_kvfree(merge_chunks); - return status; } static void block_merge_cpu_chunks(uvm_va_block_t *existing, uvm_va_block_t *new) @@ -8019,9 +8603,8 @@ static void block_merge_cpu_chunks(uvm_va_block_t *existing, uvm_va_block_t *new uvm_chunk_size_t chunk_size; uvm_chunk_size_t merge_size; size_t block_size = uvm_va_block_size(existing); - NV_STATUS status; - if (!chunk) + if (!chunk || uvm_cpu_chunk_is_physical(chunk)) return; chunk_size = uvm_cpu_chunk_get_size(chunk); @@ -8051,10 +8634,13 @@ static void block_merge_cpu_chunks(uvm_va_block_t *existing, uvm_va_block_t *new if (!uvm_page_mask_region_full(&existing->cpu.allocated, chunk_region)) break; - status = block_merge_cpu_chunks_to_size(existing, merge_size, chunk_region.first); - if (status != NV_OK) + block_merge_cpu_chunks_one(existing, chunk_region.first); + chunk = uvm_cpu_chunk_get_chunk_for_page(existing, page_index); + if (uvm_cpu_chunk_is_physical(chunk)) break; } + + block_free_cpu_chunk_storage(new); } // Pre-allocate everything which doesn't require retry on both existing and new @@ -8228,6 +8814,7 @@ static void block_split_cpu(uvm_va_block_t *existing, uvm_va_block_t *new) uvm_va_block_region_t block_region = uvm_va_block_region_from_block(existing); uvm_page_index_t split_page_index = uvm_va_block_cpu_page_index(existing, new->start); uvm_page_index_t page_index; + uvm_page_index_t next_page_index; uvm_cpu_chunk_t *chunk; uvm_va_range_t *existing_va_range = existing->va_range; @@ -8235,6 +8822,7 @@ static void block_split_cpu(uvm_va_block_t *existing, uvm_va_block_t *new) UVM_ASSERT(existing->va_range->type == UVM_VA_RANGE_TYPE_MANAGED); UVM_ASSERT(existing->va_range->type == new->va_range->type); } + UVM_ASSERT(existing->start < new->start); UVM_ASSERT(existing->end == new->end); @@ -8248,22 +8836,23 @@ static void block_split_cpu(uvm_va_block_t *existing, uvm_va_block_t *new) page_index = uvm_va_block_next_page_in_mask(block_region, &existing->cpu.allocated, split_page_index - 1); - while (page_index < block_region.outer) { + for_each_cpu_chunk_in_block_region_safe(chunk, + page_index, + next_page_index, + existing, + uvm_va_block_region(split_page_index, block_region.outer)) { uvm_page_index_t new_chunk_page_index; NV_STATUS status; - chunk = uvm_cpu_chunk_get_chunk_for_page(existing, page_index); - UVM_ASSERT(chunk); - - uvm_cpu_chunk_remove_from_block(existing, chunk, page_index); + uvm_cpu_chunk_remove_from_block(existing, page_index); // The chunk has to be adjusted for the new block before inserting it. new_chunk_page_index = page_index - split_page_index; + + // This should never fail because all necessary storage was allocated + // in block_presplit_cpu_chunks(). status = uvm_cpu_chunk_insert_in_block(new, chunk, new_chunk_page_index); UVM_ASSERT(status == NV_OK); - page_index = uvm_va_block_next_page_in_mask(block_region, - &existing->cpu.allocated, - page_index + uvm_cpu_chunk_num_pages(chunk) - 1); } new->cpu.ever_mapped = existing->cpu.ever_mapped; @@ -8287,9 +8876,24 @@ static void block_copy_split_gpu_chunks(uvm_va_block_t *existing, uvm_va_block_t uvm_page_index_t split_page_index = uvm_va_block_cpu_page_index(existing, new->start); size_t i; - block_gpu_chunk_get_split_state(&existing_before_state, existing->start, existing->end, split_page_index, gpu); - block_gpu_chunk_get_split_state(&existing_after_state, existing->start, new->start - 1, split_page_index - 1, gpu); - block_gpu_chunk_get_split_state(&new_state, new->start, new->end, 0, gpu); + block_gpu_chunk_get_split_state(existing, + &existing_before_state, + existing->start, + existing->end, + split_page_index, + gpu); + block_gpu_chunk_get_split_state(existing, + &existing_after_state, + existing->start, + new->start - 1, + split_page_index - 1, + gpu); + block_gpu_chunk_get_split_state(new, + &new_state, + new->start, + new->end, + 0, + gpu); // General case (B is original_chunk): // split @@ -8416,14 +9020,9 @@ static void block_split_gpu(uvm_va_block_t *existing, uvm_va_block_t *new, uvm_g UVM_ASSERT(PAGE_ALIGNED(existing->start)); existing_pages = (new->start - existing->start) / PAGE_SIZE; - uvm_cpu_chunk_gpu_mapping_split(existing, new, gpu_id); - for_each_cpu_chunk_in_block(cpu_chunk, page_index, new) { uvm_pmm_sysmem_mappings_reparent_gpu_mapping(&gpu->pmm_reverse_sysmem_mappings, - uvm_cpu_chunk_get_gpu_mapping_addr(new, - page_index, - cpu_chunk, - gpu_id), + uvm_cpu_chunk_get_gpu_phys_addr(cpu_chunk, gpu->parent), new); } @@ -8594,8 +9193,7 @@ NV_STATUS uvm_va_block_split_locked(uvm_va_block_t *existing_va_block, NV_STATUS status; uvm_perf_event_data_t event_data; - for_each_gpu_id(id) - UVM_ASSERT(block_check_chunks(existing_va_block, id)); + UVM_ASSERT(block_check_chunks(existing_va_block)); // As soon as we update existing's reverse mappings to point to the newly- // split block, the eviction path could try to operate on the new block. @@ -8672,17 +9270,14 @@ NV_STATUS uvm_va_block_split_locked(uvm_va_block_t *existing_va_block, out: // Run checks on existing_va_block even on failure, since an error must // leave the block in a consistent state. - for_each_gpu_id(id) { - UVM_ASSERT(block_check_chunks(existing_va_block, id)); - if (status == NV_OK) - UVM_ASSERT(block_check_chunks(new_block, id)); - } - + UVM_ASSERT(block_check_chunks(existing_va_block)); UVM_ASSERT(block_check_mappings(existing_va_block)); - UVM_ASSERT(block_verify_cpu_chunks(existing_va_block)); if (status == NV_OK) { + UVM_ASSERT(block_check_chunks(new_block)); UVM_ASSERT(block_check_mappings(new_block)); - UVM_ASSERT(block_verify_cpu_chunks(new_block)); + } + else { + block_free_cpu_chunk_storage(new_block); } uvm_mutex_unlock_no_tracking(&new_block->lock); @@ -8740,24 +9335,31 @@ static uvm_prot_t compute_new_permission(uvm_va_block_t *va_block, uvm_processor_mask_t processors_with_atomic_mapping; uvm_processor_mask_t revoke_processors; - uvm_va_block_page_authorized_processors(va_block, - page_index, - UVM_PROT_READ_WRITE_ATOMIC, - &processors_with_atomic_mapping); + block_page_authorized_processors(va_block, + page_index, + UVM_PROT_READ_WRITE_ATOMIC, + &processors_with_atomic_mapping); uvm_processor_mask_andnot(&revoke_processors, &processors_with_atomic_mapping, &va_space->has_native_atomics[uvm_id_value(new_residency)]); - // Only check if there are no faultable processors in the revoke processors mask + // Only check if there are no faultable processors in the revoke + // processors mask. uvm_processor_mask_and(&revoke_processors, &revoke_processors, &va_space->faultable_processors); if (uvm_processor_mask_empty(&revoke_processors)) new_prot = UVM_PROT_READ_WRITE; } - if (logical_prot == UVM_PROT_READ_WRITE_ATOMIC && new_prot == UVM_PROT_READ_WRITE) { - if (uvm_processor_mask_test(&va_space->has_native_atomics[uvm_id_value(new_residency)], fault_processor_id)) - new_prot = UVM_PROT_READ_WRITE_ATOMIC; + if (logical_prot == UVM_PROT_READ_WRITE_ATOMIC) { + // HMM allocations with logical read/write/atomic permission can be + // upgraded without notifying the driver so assume read/write/atomic + // even if the fault is only for reading. + if (new_prot == UVM_PROT_READ_WRITE || + (UVM_ID_IS_CPU(fault_processor_id) && uvm_va_block_is_hmm(va_block))) { + if (uvm_processor_mask_test(&va_space->has_native_atomics[uvm_id_value(new_residency)], fault_processor_id)) + new_prot = UVM_PROT_READ_WRITE_ATOMIC; + } } return new_prot; @@ -8873,7 +9475,7 @@ NV_STATUS uvm_va_block_add_mappings_after_migration(uvm_va_block_t *va_block, uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); const uvm_page_mask_t *final_page_mask = map_page_mask; uvm_tracker_t local_tracker = UVM_TRACKER_INIT(); - uvm_va_policy_t *policy = va_block_context->policy; + const uvm_va_policy_t *policy = va_block_context->policy; uvm_processor_id_t preferred_location; uvm_assert_mutex_locked(&va_block->lock); @@ -9049,7 +9651,7 @@ uvm_prot_t uvm_va_block_page_compute_highest_permission(uvm_va_block_t *va_block if (!uvm_page_mask_test(&va_block->maybe_mapped_pages, page_index)) return UVM_PROT_READ_WRITE_ATOMIC; - uvm_va_block_page_authorized_processors(va_block, page_index, UVM_PROT_READ_WRITE_ATOMIC, &atomic_mappings); + block_page_authorized_processors(va_block, page_index, UVM_PROT_READ_WRITE_ATOMIC, &atomic_mappings); // Exclude processors with system-wide atomics disabled from atomic_mappings uvm_processor_mask_and(&atomic_mappings, @@ -9067,7 +9669,7 @@ uvm_prot_t uvm_va_block_page_compute_highest_permission(uvm_va_block_t *va_block return UVM_PROT_READ_ONLY; } - uvm_va_block_page_authorized_processors(va_block, page_index, UVM_PROT_READ_WRITE, &write_mappings); + block_page_authorized_processors(va_block, page_index, UVM_PROT_READ_WRITE, &write_mappings); // Exclude the processor for which the mapping protections are being computed uvm_processor_mask_clear(&write_mappings, processor_id); @@ -9164,7 +9766,7 @@ NV_STATUS uvm_va_block_add_mappings(uvm_va_block_t *va_block, static bool can_read_duplicate(uvm_va_block_t *va_block, uvm_page_index_t page_index, - uvm_va_policy_t *policy, + const uvm_va_policy_t *policy, const uvm_perf_thrashing_hint_t *thrashing_hint) { if (uvm_va_policy_is_read_duplicate(policy, uvm_va_block_get_va_space(va_block))) @@ -9225,7 +9827,7 @@ static uvm_processor_id_t block_select_residency(uvm_va_block_t *va_block, uvm_page_index_t page_index, uvm_processor_id_t processor_id, NvU32 access_type_mask, - uvm_va_policy_t *policy, + const uvm_va_policy_t *policy, const uvm_perf_thrashing_hint_t *thrashing_hint, uvm_service_operation_t operation, bool *read_duplicate) @@ -9274,6 +9876,12 @@ static uvm_processor_id_t block_select_residency(uvm_va_block_t *va_block, return processor_id; } + // If the faulting processor is the CPU, HMM has to migrate the block to + // system memory. + // TODO: Bug 3900021: [UVM-HMM] investigate thrashing improvements. + if (UVM_ID_IS_CPU(processor_id) && uvm_va_block_is_hmm(va_block)) + return processor_id; + if (thrashing_hint->type == UVM_PERF_THRASHING_HINT_TYPE_PIN) { UVM_ASSERT(uvm_processor_mask_test(&va_space->accessible_from[uvm_id_value(thrashing_hint->pin.residency)], processor_id)); @@ -9336,7 +9944,7 @@ uvm_processor_id_t uvm_va_block_select_residency(uvm_va_block_t *va_block, uvm_page_index_t page_index, uvm_processor_id_t processor_id, NvU32 access_type_mask, - uvm_va_policy_t *policy, + const uvm_va_policy_t *policy, const uvm_perf_thrashing_hint_t *thrashing_hint, uvm_service_operation_t operation, bool *read_duplicate) @@ -9346,9 +9954,9 @@ uvm_processor_id_t uvm_va_block_select_residency(uvm_va_block_t *va_block, UVM_ASSERT(uvm_va_block_check_policy_is_valid(va_block, va_block_context->policy, uvm_va_block_region_for_page(page_index))); - UVM_ASSERT(uvm_hmm_va_block_context_vma_is_valid(va_block, - va_block_context, - uvm_va_block_region_for_page(page_index))); + UVM_ASSERT(uvm_hmm_check_context_vma_is_valid(va_block, + va_block_context, + uvm_va_block_region_for_page(page_index))); id = block_select_residency(va_block, va_block_context, @@ -9401,7 +10009,7 @@ static void uvm_va_block_get_prefetch_hint(uvm_va_block_t *va_block, if (uvm_processor_mask_get_count(&service_context->resident_processors) == 1) { uvm_page_index_t page_index; uvm_page_mask_t *new_residency_mask; - uvm_va_policy_t *policy = service_context->block_context.policy; + const uvm_va_policy_t *policy = service_context->block_context.policy; new_residency = uvm_processor_mask_find_first_id(&service_context->resident_processors); new_residency_mask = &service_context->per_processor_masks[uvm_id_value(new_residency)].new_residency; @@ -9445,221 +10053,89 @@ static void uvm_va_block_get_prefetch_hint(uvm_va_block_t *va_block, } } -NV_STATUS uvm_va_block_service_locked(uvm_processor_id_t processor_id, - uvm_va_block_t *va_block, - uvm_va_block_retry_t *block_retry, - uvm_service_block_context_t *service_context) +NV_STATUS uvm_va_block_service_copy(uvm_processor_id_t processor_id, + uvm_processor_id_t new_residency, + uvm_va_block_t *va_block, + uvm_va_block_retry_t *block_retry, + uvm_service_block_context_t *service_context) { - NV_STATUS status = NV_OK; - uvm_processor_id_t new_residency; - uvm_prot_t new_prot; uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); - uvm_processor_mask_t processors_involved_in_cpu_migration; + uvm_processor_mask_t *all_involved_processors = + &service_context->block_context.make_resident.all_involved_processors; + uvm_page_mask_t *new_residency_mask = + &service_context->per_processor_masks[uvm_id_value(new_residency)].new_residency; + uvm_page_mask_t *did_migrate_mask = &service_context->block_context.make_resident.pages_changed_residency; + uvm_page_mask_t *caller_page_mask = &service_context->block_context.caller_page_mask; + uvm_make_resident_cause_t cause; + NV_STATUS status; - uvm_assert_mutex_locked(&va_block->lock); - UVM_ASSERT(uvm_va_block_check_policy_is_valid(va_block, - service_context->block_context.policy, - service_context->region)); - - // GPU fault servicing must be done under the VA space read lock. GPU fault - // servicing is required for RM to make forward progress, and we allow other - // threads to call into RM while holding the VA space lock in read mode. If - // we took the VA space lock in write mode on the GPU fault service path, - // we could deadlock because the thread in RM which holds the VA space lock - // for read wouldn't be able to complete until fault servicing completes. - if (service_context->operation != UVM_SERVICE_OPERATION_REPLAYABLE_FAULTS || UVM_ID_IS_CPU(processor_id)) - uvm_assert_rwsem_locked(&va_space->lock); - else - uvm_assert_rwsem_locked_read(&va_space->lock); - - uvm_va_block_get_prefetch_hint(va_block, service_context); - - for (new_prot = UVM_PROT_READ_ONLY; new_prot < UVM_PROT_MAX; ++new_prot) - service_context->mappings_by_prot[new_prot-1].count = 0; - - uvm_processor_mask_zero(&processors_involved_in_cpu_migration); - - // 1- Migrate pages and compute mapping protections - for_each_id_in_mask(new_residency, &service_context->resident_processors) { - uvm_processor_mask_t *all_involved_processors = &service_context->block_context.make_resident.all_involved_processors; - uvm_page_mask_t *new_residency_mask = &service_context->per_processor_masks[uvm_id_value(new_residency)].new_residency; - uvm_page_mask_t *did_migrate_mask = &service_context->block_context.make_resident.pages_changed_residency; - uvm_page_index_t page_index; - uvm_make_resident_cause_t cause; - - UVM_ASSERT_MSG(service_context->operation == UVM_SERVICE_OPERATION_REPLAYABLE_FAULTS || - service_context->operation == UVM_SERVICE_OPERATION_NON_REPLAYABLE_FAULTS || - service_context->operation == UVM_SERVICE_OPERATION_ACCESS_COUNTERS, - "Invalid operation value %u\n", service_context->operation); - - if (service_context->operation == UVM_SERVICE_OPERATION_REPLAYABLE_FAULTS) + // 1- Migrate pages + switch (service_context->operation) { + case UVM_SERVICE_OPERATION_REPLAYABLE_FAULTS: cause = UVM_MAKE_RESIDENT_CAUSE_REPLAYABLE_FAULT; - else if (service_context->operation == UVM_SERVICE_OPERATION_NON_REPLAYABLE_FAULTS) + break; + case UVM_SERVICE_OPERATION_NON_REPLAYABLE_FAULTS: cause = UVM_MAKE_RESIDENT_CAUSE_NON_REPLAYABLE_FAULT; - else + break; + case UVM_SERVICE_OPERATION_ACCESS_COUNTERS: cause = UVM_MAKE_RESIDENT_CAUSE_ACCESS_COUNTER; - - // 1.1- Migrate pages - - // Reset masks before all of the make_resident calls - uvm_page_mask_zero(did_migrate_mask); - uvm_processor_mask_zero(all_involved_processors); - - if (UVM_ID_IS_VALID(service_context->prefetch_hint.residency)) { - UVM_ASSERT(uvm_id_equal(service_context->prefetch_hint.residency, new_residency)); - - uvm_page_mask_or(new_residency_mask, new_residency_mask, &service_context->prefetch_hint.prefetch_pages_mask); - } - - if (service_context->read_duplicate_count == 0 || - uvm_page_mask_andnot(&service_context->block_context.caller_page_mask, - new_residency_mask, - &service_context->read_duplicate_mask)) { - status = uvm_va_block_make_resident(va_block, - block_retry, - &service_context->block_context, - new_residency, - service_context->region, - service_context->read_duplicate_count == 0? - new_residency_mask: - &service_context->block_context.caller_page_mask, - &service_context->prefetch_hint.prefetch_pages_mask, - cause); - if (status != NV_OK) - return status; - } - - if (service_context->read_duplicate_count != 0 && - uvm_page_mask_and(&service_context->block_context.caller_page_mask, - new_residency_mask, - &service_context->read_duplicate_mask)) { - status = uvm_va_block_make_resident_read_duplicate(va_block, - block_retry, - &service_context->block_context, - new_residency, - service_context->region, - &service_context->block_context.caller_page_mask, - &service_context->prefetch_hint.prefetch_pages_mask, - cause); - if (status != NV_OK) - return status; - } - - if (UVM_ID_IS_CPU(new_residency)) { - // Save all the processors involved in migrations to the CPU for - // an ECC check before establishing the CPU mappings. - uvm_processor_mask_copy(&processors_involved_in_cpu_migration, all_involved_processors); - } - - if (UVM_ID_IS_CPU(processor_id) && !uvm_processor_mask_empty(all_involved_processors)) - service_context->cpu_fault.did_migrate = true; - - uvm_page_mask_andnot(&service_context->did_not_migrate_mask, new_residency_mask, did_migrate_mask); - - // 1.2 - Compute mapping protections for the requesting processor on - // the new residency - for_each_va_block_page_in_region_mask(page_index, new_residency_mask, service_context->region) { - new_prot = compute_new_permission(va_block, - &service_context->block_context, - page_index, - processor_id, - new_residency, - service_context->access_type[page_index]); - - if (service_context->mappings_by_prot[new_prot-1].count++ == 0) - uvm_page_mask_zero(&service_context->mappings_by_prot[new_prot-1].page_mask); - - uvm_page_mask_set(&service_context->mappings_by_prot[new_prot-1].page_mask, page_index); - } - - // 1.3- Revoke permissions - // - // NOTE: uvm_va_block_make_resident destroys mappings to old locations. - // Thus, we need to revoke only if residency did not change and we - // are mapping higher than READ ONLY. - for (new_prot = UVM_PROT_READ_WRITE; new_prot <= UVM_PROT_READ_WRITE_ATOMIC; ++new_prot) { - bool pages_need_revocation; - uvm_processor_mask_t revoke_processors; - uvm_prot_t revoke_prot; - bool this_processor_has_enabled_atomics; - - if (service_context->mappings_by_prot[new_prot-1].count == 0) - continue; - - pages_need_revocation = uvm_page_mask_and(&service_context->revocation_mask, - &service_context->did_not_migrate_mask, - &service_context->mappings_by_prot[new_prot-1].page_mask); - if (!pages_need_revocation) - continue; - - uvm_processor_mask_and(&revoke_processors, &va_block->mapped, &va_space->faultable_processors); - - // Do not revoke the processor that took the fault - uvm_processor_mask_clear(&revoke_processors, processor_id); - - this_processor_has_enabled_atomics = uvm_processor_mask_test(&va_space->system_wide_atomics_enabled_processors, - processor_id); - - // Atomic operations on processors with system-wide atomics - // disabled or with native atomics access to new_residency - // behave like writes. - if (new_prot == UVM_PROT_READ_WRITE || - !this_processor_has_enabled_atomics || - uvm_processor_mask_test(&va_space->has_native_atomics[uvm_id_value(new_residency)], processor_id)) { - - // Exclude processors with native atomics on the resident copy - uvm_processor_mask_andnot(&revoke_processors, - &revoke_processors, - &va_space->has_native_atomics[uvm_id_value(new_residency)]); - - // Exclude processors with disabled system-wide atomics - uvm_processor_mask_and(&revoke_processors, - &revoke_processors, - &va_space->system_wide_atomics_enabled_processors); - } - - if (UVM_ID_IS_CPU(processor_id)) { - revoke_prot = UVM_PROT_READ_WRITE_ATOMIC; - } - else { - revoke_prot = (new_prot == UVM_PROT_READ_WRITE_ATOMIC)? UVM_PROT_READ_WRITE: - UVM_PROT_READ_WRITE_ATOMIC; - } - - // UVM-Lite processors must always have RWA mappings - if (uvm_processor_mask_andnot(&revoke_processors, &revoke_processors, block_get_uvm_lite_gpus(va_block))) { - // Access counters should never trigger revocations apart from - // read-duplication, which are performed in the calls to - // uvm_va_block_make_resident_read_duplicate, above. - if (service_context->operation == UVM_SERVICE_OPERATION_ACCESS_COUNTERS) { - UVM_ASSERT(check_access_counters_dont_revoke(va_block, - &service_context->block_context, - service_context->region, - &revoke_processors, - &service_context->revocation_mask, - revoke_prot)); - } - - // Downgrade other processors' mappings - status = uvm_va_block_revoke_prot_mask(va_block, - &service_context->block_context, - &revoke_processors, - service_context->region, - &service_context->revocation_mask, - revoke_prot); - if (status != NV_OK) - return status; - } - } + break; + default: + UVM_ASSERT_MSG(false, "Invalid operation value %d\n", service_context->operation); + // Set cause to silence compiler warning that it may be unused. + cause = UVM_MAKE_RESIDENT_CAUSE_ACCESS_COUNTER; + break; } + // Reset masks before all of the make_resident calls + uvm_page_mask_zero(did_migrate_mask); + uvm_processor_mask_zero(all_involved_processors); + + // Handle read duplication first so that the caller_page_mask will be free + // to use below and still valid in uvm_va_block_service_finish(). + // TODO: Bug 3660922: need to implement HMM read duplication support. + if (service_context->read_duplicate_count != 0 && + uvm_page_mask_and(caller_page_mask, + new_residency_mask, + &service_context->read_duplicate_mask)) { + status = uvm_va_block_make_resident_read_duplicate(va_block, + block_retry, + &service_context->block_context, + new_residency, + service_context->region, + caller_page_mask, + &service_context->prefetch_hint.prefetch_pages_mask, + cause); + if (status != NV_OK) + return status; + } + + if (service_context->read_duplicate_count == 0 || + uvm_page_mask_andnot(caller_page_mask, new_residency_mask, &service_context->read_duplicate_mask)) { + if (service_context->read_duplicate_count == 0) + uvm_page_mask_copy(caller_page_mask, new_residency_mask); + status = uvm_va_block_make_resident_copy(va_block, + block_retry, + &service_context->block_context, + new_residency, + service_context->region, + caller_page_mask, + &service_context->prefetch_hint.prefetch_pages_mask, + cause); + if (status != NV_OK) + return status; + } + + if (UVM_ID_IS_CPU(processor_id) && !uvm_processor_mask_empty(all_involved_processors)) + service_context->cpu_fault.did_migrate = true; + // 2- Check for ECC errors on all GPUs involved in the migration if CPU is // the destination. Migrations in response to CPU faults are special // because they're on the only path (apart from tools) where CUDA is not // involved and wouldn't have a chance to do its own ECC checking. if (service_context->operation == UVM_SERVICE_OPERATION_REPLAYABLE_FAULTS && - UVM_ID_IS_CPU(processor_id) && - !uvm_processor_mask_empty(&processors_involved_in_cpu_migration)) { + UVM_ID_IS_CPU(new_residency) && + !uvm_processor_mask_empty(all_involved_processors)) { uvm_gpu_t *gpu; // Before checking for ECC errors, make sure all of the GPU work @@ -9669,7 +10145,7 @@ NV_STATUS uvm_va_block_service_locked(uvm_processor_id_t processor_id, if (status != NV_OK) return status; - for_each_va_space_gpu_in_mask(gpu, va_space, &processors_involved_in_cpu_migration) { + for_each_va_space_gpu_in_mask(gpu, va_space, all_involved_processors) { // We cannot call into RM here so use the no RM ECC check. status = uvm_gpu_check_ecc_error_no_rm(gpu); if (status == NV_WARN_MORE_PROCESSING_REQUIRED) { @@ -9691,16 +10167,152 @@ NV_STATUS uvm_va_block_service_locked(uvm_processor_id_t processor_id, } } + return NV_OK; +} + +NV_STATUS uvm_va_block_service_finish(uvm_processor_id_t processor_id, + uvm_va_block_t *va_block, + uvm_service_block_context_t *service_context) +{ + uvm_processor_id_t new_residency = service_context->block_context.make_resident.dest_id; + uvm_page_mask_t *new_residency_mask = + &service_context->per_processor_masks[uvm_id_value(new_residency)].new_residency; + uvm_page_mask_t *did_migrate_mask = &service_context->block_context.make_resident.pages_changed_residency; + uvm_page_mask_t *caller_page_mask = &service_context->block_context.caller_page_mask; + uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); + uvm_prot_t new_prot; + uvm_page_index_t page_index; + NV_STATUS status; + + // Update residency. + if (service_context->read_duplicate_count == 0 || !uvm_page_mask_empty(caller_page_mask)) + uvm_va_block_make_resident_finish(va_block, + &service_context->block_context, + service_context->region, + caller_page_mask); + + uvm_page_mask_andnot(&service_context->did_not_migrate_mask, new_residency_mask, did_migrate_mask); + + // The loops below depend on the enums having the following values in order + // to index into service_context->mappings_by_prot[]. + BUILD_BUG_ON(UVM_PROT_READ_ONLY != 1); + BUILD_BUG_ON(UVM_PROT_READ_WRITE != 2); + BUILD_BUG_ON(UVM_PROT_READ_WRITE_ATOMIC != 3); + BUILD_BUG_ON(UVM_PROT_MAX != 4); + + // 1- Compute mapping protections for the requesting processor on the new + // residency. + for (new_prot = UVM_PROT_READ_ONLY; new_prot < UVM_PROT_MAX; ++new_prot) + service_context->mappings_by_prot[new_prot - 1].count = 0; + + for_each_va_block_page_in_region_mask(page_index, new_residency_mask, service_context->region) { + new_prot = compute_new_permission(va_block, + &service_context->block_context, + page_index, + processor_id, + new_residency, + service_context->access_type[page_index]); + + if (service_context->mappings_by_prot[new_prot - 1].count++ == 0) + uvm_page_mask_zero(&service_context->mappings_by_prot[new_prot - 1].page_mask); + + uvm_page_mask_set(&service_context->mappings_by_prot[new_prot - 1].page_mask, page_index); + } + + // 2- Revoke permissions + // + // NOTE: uvm_va_block_make_resident_copy destroys mappings to old locations. + // Thus, we need to revoke only if residency did not change and we + // are mapping higher than READ ONLY. + for (new_prot = UVM_PROT_READ_WRITE; new_prot <= UVM_PROT_READ_WRITE_ATOMIC; ++new_prot) { + bool pages_need_revocation; + uvm_processor_mask_t revoke_processors; + uvm_prot_t revoke_prot; + bool this_processor_has_enabled_atomics; + + if (service_context->mappings_by_prot[new_prot - 1].count == 0) + continue; + + pages_need_revocation = uvm_page_mask_and(&service_context->revocation_mask, + &service_context->did_not_migrate_mask, + &service_context->mappings_by_prot[new_prot - 1].page_mask); + if (!pages_need_revocation) + continue; + + uvm_processor_mask_and(&revoke_processors, &va_block->mapped, &va_space->faultable_processors); + + // Do not revoke the processor that took the fault + uvm_processor_mask_clear(&revoke_processors, processor_id); + + this_processor_has_enabled_atomics = uvm_processor_mask_test(&va_space->system_wide_atomics_enabled_processors, + processor_id); + + // Atomic operations on processors with system-wide atomics + // disabled or with native atomics access to new_residency + // behave like writes. + if (new_prot == UVM_PROT_READ_WRITE || + !this_processor_has_enabled_atomics || + uvm_processor_mask_test(&va_space->has_native_atomics[uvm_id_value(new_residency)], processor_id)) { + + // Exclude processors with native atomics on the resident copy + uvm_processor_mask_andnot(&revoke_processors, + &revoke_processors, + &va_space->has_native_atomics[uvm_id_value(new_residency)]); + + // Exclude processors with disabled system-wide atomics + uvm_processor_mask_and(&revoke_processors, + &revoke_processors, + &va_space->system_wide_atomics_enabled_processors); + } + + if (UVM_ID_IS_CPU(processor_id)) { + revoke_prot = UVM_PROT_READ_WRITE_ATOMIC; + } + else { + revoke_prot = (new_prot == UVM_PROT_READ_WRITE_ATOMIC)? UVM_PROT_READ_WRITE: + UVM_PROT_READ_WRITE_ATOMIC; + } + + // UVM-Lite processors must always have RWA mappings + if (uvm_processor_mask_andnot(&revoke_processors, &revoke_processors, block_get_uvm_lite_gpus(va_block))) { + // Access counters should never trigger revocations apart from + // read-duplication, which are performed in the calls to + // uvm_va_block_make_resident_read_duplicate, above. + if (service_context->operation == UVM_SERVICE_OPERATION_ACCESS_COUNTERS) { + UVM_ASSERT(check_access_counters_dont_revoke(va_block, + &service_context->block_context, + service_context->region, + &revoke_processors, + &service_context->revocation_mask, + revoke_prot)); + } + + // Downgrade other processors' mappings + status = uvm_va_block_revoke_prot_mask(va_block, + &service_context->block_context, + &revoke_processors, + service_context->region, + &service_context->revocation_mask, + revoke_prot); + if (status != NV_OK) + return status; + } + } + // 3- Map requesting processor with the necessary privileges for (new_prot = UVM_PROT_READ_ONLY; new_prot <= UVM_PROT_READ_WRITE_ATOMIC; ++new_prot) { - const uvm_page_mask_t *map_prot_mask = &service_context->mappings_by_prot[new_prot-1].page_mask; + const uvm_page_mask_t *map_prot_mask = &service_context->mappings_by_prot[new_prot - 1].page_mask; - if (service_context->mappings_by_prot[new_prot-1].count == 0) + if (service_context->mappings_by_prot[new_prot - 1].count == 0) continue; // 3.1 - Unmap CPU pages - if (service_context->operation != UVM_SERVICE_OPERATION_ACCESS_COUNTERS && UVM_ID_IS_CPU(processor_id)) { - // The kernel can downgrade our CPU mappings at any time without + // HMM cpu mappings can be upgraded at any time without notification + // so no need to downgrade first. + if (service_context->operation != UVM_SERVICE_OPERATION_ACCESS_COUNTERS && + UVM_ID_IS_CPU(processor_id) && + !uvm_va_block_is_hmm(va_block)) { + // The kernel can downgrade managed CPU mappings at any time without // notifying us, which means our PTE state could be stale. We // handle this by unmapping the CPU PTE and re-mapping it again. // @@ -9763,76 +10375,122 @@ NV_STATUS uvm_va_block_service_locked(uvm_processor_id_t processor_id, return status; } - // 4- If pages did migrate, map SetAccessedBy processors, except for UVM-Lite - for_each_id_in_mask(new_residency, &service_context->resident_processors) { - const uvm_page_mask_t *new_residency_mask; - new_residency_mask = &service_context->per_processor_masks[uvm_id_value(new_residency)].new_residency; + // 4- If pages did migrate, map SetAccessedBy processors, except for + // UVM-Lite + for (new_prot = UVM_PROT_READ_ONLY; new_prot <= UVM_PROT_READ_WRITE_ATOMIC; ++new_prot) { + bool pages_need_mapping; - for (new_prot = UVM_PROT_READ_ONLY; new_prot <= UVM_PROT_READ_WRITE_ATOMIC; ++new_prot) { - uvm_page_mask_t *map_prot_mask = &service_context->block_context.caller_page_mask; - bool pages_need_mapping; + if (service_context->mappings_by_prot[new_prot - 1].count == 0) + continue; - if (service_context->mappings_by_prot[new_prot-1].count == 0) - continue; + pages_need_mapping = uvm_page_mask_and(caller_page_mask, + new_residency_mask, + &service_context->mappings_by_prot[new_prot - 1].page_mask); + if (!pages_need_mapping) + continue; - pages_need_mapping = uvm_page_mask_and(map_prot_mask, - new_residency_mask, - &service_context->mappings_by_prot[new_prot-1].page_mask); - if (!pages_need_mapping) - continue; + // Map pages that are thrashing + if (service_context->thrashing_pin_count > 0) { + uvm_page_index_t page_index; - // Map pages that are thrashing - if (service_context->thrashing_pin_count > 0) { - uvm_page_index_t page_index; + for_each_va_block_page_in_region_mask(page_index, + &service_context->thrashing_pin_mask, + service_context->region) { + uvm_processor_mask_t *map_thrashing_processors = NULL; + NvU64 page_addr = uvm_va_block_cpu_page_address(va_block, page_index); - for_each_va_block_page_in_region_mask(page_index, - &service_context->thrashing_pin_mask, - service_context->region) { - uvm_processor_mask_t *map_thrashing_processors = NULL; - NvU64 page_addr = uvm_va_block_cpu_page_address(va_block, page_index); - - // Check protection type - if (!uvm_page_mask_test(map_prot_mask, page_index)) - continue; - - map_thrashing_processors = uvm_perf_thrashing_get_thrashing_processors(va_block, page_addr); - - status = uvm_va_block_add_mappings_after_migration(va_block, - &service_context->block_context, - new_residency, - processor_id, - uvm_va_block_region_for_page(page_index), - map_prot_mask, - new_prot, - map_thrashing_processors); - if (status != NV_OK) - return status; - } - - pages_need_mapping = uvm_page_mask_andnot(map_prot_mask, - map_prot_mask, - &service_context->thrashing_pin_mask); - if (!pages_need_mapping) + // Check protection type + if (!uvm_page_mask_test(caller_page_mask, page_index)) continue; + + map_thrashing_processors = uvm_perf_thrashing_get_thrashing_processors(va_block, page_addr); + + status = uvm_va_block_add_mappings_after_migration(va_block, + &service_context->block_context, + new_residency, + processor_id, + uvm_va_block_region_for_page(page_index), + caller_page_mask, + new_prot, + map_thrashing_processors); + if (status != NV_OK) + return status; } - // Map the the rest of pages in a single shot - status = uvm_va_block_add_mappings_after_migration(va_block, - &service_context->block_context, - new_residency, - processor_id, - service_context->region, - map_prot_mask, - new_prot, - NULL); - if (status != NV_OK) - return status; + pages_need_mapping = uvm_page_mask_andnot(caller_page_mask, + caller_page_mask, + &service_context->thrashing_pin_mask); + if (!pages_need_mapping) + continue; } + + // Map the rest of pages in a single shot + status = uvm_va_block_add_mappings_after_migration(va_block, + &service_context->block_context, + new_residency, + processor_id, + service_context->region, + caller_page_mask, + new_prot, + NULL); + if (status != NV_OK) + return status; } return NV_OK; } +NV_STATUS uvm_va_block_service_locked(uvm_processor_id_t processor_id, + uvm_va_block_t *va_block, + uvm_va_block_retry_t *block_retry, + uvm_service_block_context_t *service_context) +{ + uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); + uvm_processor_id_t new_residency; + NV_STATUS status = NV_OK; + + uvm_assert_mutex_locked(&va_block->lock); + UVM_ASSERT(uvm_va_block_check_policy_is_valid(va_block, + service_context->block_context.policy, + service_context->region)); + UVM_ASSERT(uvm_hmm_check_context_vma_is_valid(va_block, + &service_context->block_context, + service_context->region)); + + // GPU fault servicing must be done under the VA space read lock. GPU fault + // servicing is required for RM to make forward progress, and we allow other + // threads to call into RM while holding the VA space lock in read mode. If + // we took the VA space lock in write mode on the GPU fault service path, + // we could deadlock because the thread in RM which holds the VA space lock + // for read wouldn't be able to complete until fault servicing completes. + if (service_context->operation != UVM_SERVICE_OPERATION_REPLAYABLE_FAULTS || UVM_ID_IS_CPU(processor_id)) + uvm_assert_rwsem_locked(&va_space->lock); + else + uvm_assert_rwsem_locked_read(&va_space->lock); + + uvm_va_block_get_prefetch_hint(va_block, service_context); + + for_each_id_in_mask(new_residency, &service_context->resident_processors) { + if (uvm_va_block_is_hmm(va_block)) { + status = uvm_hmm_va_block_service_locked(processor_id, new_residency, va_block, block_retry, service_context); + if (status != NV_OK) + break; + + continue; + } + + status = uvm_va_block_service_copy(processor_id, new_residency, va_block, block_retry, service_context); + if (status != NV_OK) + break; + + status = uvm_va_block_service_finish(processor_id, va_block, service_context); + if (status != NV_OK) + break; + } + + return status; +} + NV_STATUS uvm_va_block_check_logical_permissions(uvm_va_block_t *va_block, uvm_va_block_context_t *va_block_context, uvm_processor_id_t processor_id, @@ -9846,9 +10504,9 @@ NV_STATUS uvm_va_block_check_logical_permissions(uvm_va_block_t *va_block, UVM_ASSERT(uvm_va_block_check_policy_is_valid(va_block, va_block_context->policy, uvm_va_block_region_for_page(page_index))); - UVM_ASSERT(uvm_hmm_va_block_context_vma_is_valid(va_block, - va_block_context, - uvm_va_block_region_for_page(page_index))); + UVM_ASSERT(uvm_hmm_check_context_vma_is_valid(va_block, + va_block_context, + uvm_va_block_region_for_page(page_index))); // CPU permissions are checked later by block_map_cpu_page. // @@ -9899,10 +10557,15 @@ static bool skip_cpu_fault_with_valid_permissions(uvm_va_block_t *va_block, uvm_page_index_t page_index, uvm_fault_access_type_t fault_access_type) { - if (uvm_va_block_page_is_processor_authorized(va_block, - page_index, - UVM_ID_CPU, - uvm_fault_access_type_to_prot(fault_access_type))) { + // TODO: Bug 3900038: is skip_cpu_fault_with_valid_permissions() needed for + // HMM? + if (uvm_va_block_is_hmm(va_block)) + return false; + + if (block_page_is_processor_authorized(va_block, + page_index, + UVM_ID_CPU, + uvm_fault_access_type_to_prot(fault_access_type))) { NvU64 now = NV_GETTIME(); pid_t pid = current->pid; @@ -9941,7 +10604,6 @@ static NV_STATUS block_cpu_fault_locked(uvm_va_block_t *va_block, uvm_fault_access_type_t fault_access_type, uvm_service_block_context_t *service_context) { - uvm_va_range_t *va_range = va_block->va_range; uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); NV_STATUS status = NV_OK; uvm_page_index_t page_index; @@ -9950,7 +10612,6 @@ static NV_STATUS block_cpu_fault_locked(uvm_va_block_t *va_block, bool read_duplicate; uvm_assert_rwsem_locked(&va_space->lock); - UVM_ASSERT(va_range->type == UVM_VA_RANGE_TYPE_MANAGED); UVM_ASSERT(fault_addr >= va_block->start); UVM_ASSERT(fault_addr <= va_block->end); @@ -10105,24 +10766,26 @@ NV_STATUS uvm_va_block_find(uvm_va_space_t *va_space, NvU64 addr, uvm_va_block_t return NV_OK; } -NV_STATUS uvm_va_block_find_create(uvm_va_space_t *va_space, - NvU64 addr, - uvm_va_block_context_t *va_block_context, - uvm_va_block_t **out_block) +NV_STATUS uvm_va_block_find_create_in_range(uvm_va_space_t *va_space, + uvm_va_range_t *va_range, + NvU64 addr, + uvm_va_block_context_t *va_block_context, + uvm_va_block_t **out_block) { - uvm_va_range_t *va_range; size_t index; if (uvm_enable_builtin_tests && atomic_dec_if_positive(&va_space->test.va_block_allocation_fail_nth) == 0) return NV_ERR_NO_MEMORY; - va_range = uvm_va_range_find(va_space, addr); if (!va_range) { if (!va_block_context || !va_block_context->mm) return NV_ERR_INVALID_ADDRESS; return uvm_hmm_va_block_find_create(va_space, addr, va_block_context, out_block); } + UVM_ASSERT(addr >= va_range->node.start); + UVM_ASSERT(addr <= va_range->node.end); + UVM_ASSERT(uvm_hmm_va_block_find(va_space, addr, out_block) == NV_ERR_INVALID_ADDRESS || uvm_hmm_va_block_find(va_space, addr, out_block) == NV_ERR_OBJECT_NOT_FOUND); @@ -10133,6 +10796,16 @@ NV_STATUS uvm_va_block_find_create(uvm_va_space_t *va_space, return uvm_va_range_block_create(va_range, index, out_block); } +NV_STATUS uvm_va_block_find_create(uvm_va_space_t *va_space, + NvU64 addr, + uvm_va_block_context_t *va_block_context, + uvm_va_block_t **out_block) +{ + uvm_va_range_t *va_range = uvm_va_range_find(va_space, addr); + + return uvm_va_block_find_create_in_range(va_space, va_range, addr, va_block_context, out_block); +} + NV_STATUS uvm_va_block_write_from_cpu(uvm_va_block_t *va_block, uvm_va_block_context_t *block_context, NvU64 dst, @@ -10178,8 +10851,7 @@ NV_STATUS uvm_va_block_write_from_cpu(uvm_va_block_t *va_block, if (UVM_ID_IS_CPU(proc)) { char *mapped_page; - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(va_block, page_index); - struct page *page = uvm_cpu_chunk_get_cpu_page(va_block, chunk, page_index); + struct page *page = uvm_cpu_chunk_get_cpu_page(va_block, page_index); status = uvm_tracker_wait(&va_block->tracker); if (status != NV_OK) @@ -10236,8 +10908,7 @@ NV_STATUS uvm_va_block_read_to_cpu(uvm_va_block_t *va_block, uvm_mem_t *dst_mem, if (UVM_ID_IS_CPU(proc)) { char *mapped_page; - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(va_block, page_index); - struct page *page = uvm_cpu_chunk_get_cpu_page(va_block, chunk, page_index); + struct page *page = uvm_cpu_chunk_get_cpu_page(va_block, page_index); status = uvm_tracker_wait(&va_block->tracker); if (status != NV_OK) @@ -10275,7 +10946,7 @@ NV_STATUS uvm_va_block_read_to_cpu(uvm_va_block_t *va_block, uvm_mem_t *dst_mem, // Deferred work item reestablishing accessed by mappings after eviction. On // GPUs with access counters enabled, the evicted GPU will also get remote // mappings. -static void block_deferred_eviction_mappings(void *args) +static void block_add_eviction_mappings(void *args) { uvm_va_block_t *va_block = (uvm_va_block_t*)args; uvm_va_space_t *va_space; @@ -10309,7 +10980,10 @@ static void block_deferred_eviction_mappings(void *args) if (uvm_va_block_is_dead(va_block)) goto unlock; - if (!uvm_va_block_is_hmm(va_block)) { + if (uvm_va_block_is_hmm(va_block)) { + uvm_hmm_block_add_eviction_mappings(va_space, va_block, block_context); + } + else { uvm_va_range_t *va_range = va_block->va_range; NV_STATUS status = NV_OK; @@ -10320,9 +10994,7 @@ static void block_deferred_eviction_mappings(void *args) break; } - // On Volta+ GPUs, we can map evicted memory since we can pull it back - // thanks to the access counters notifications - if (status == NV_OK && va_space_map_remote_on_eviction(va_space)) { + if (status == NV_OK && uvm_va_space_map_remote_on_eviction(va_space)) { uvm_processor_mask_t map_processors; // Exclude the processors that have been already mapped due to @@ -10374,9 +11046,9 @@ done: uvm_va_block_release(va_block); } -static void block_deferred_eviction_mappings_entry(void *args) +static void block_add_eviction_mappings_entry(void *args) { - UVM_ENTRY_VOID(block_deferred_eviction_mappings(args)); + UVM_ENTRY_VOID(block_add_eviction_mappings(args)); } NV_STATUS uvm_va_block_evict_chunks(uvm_va_block_t *va_block, @@ -10395,6 +11067,7 @@ NV_STATUS uvm_va_block_evict_chunks(uvm_va_block_t *va_block, uvm_va_block_test_t *va_block_test = uvm_va_block_get_test(va_block); uvm_va_space_t *va_space = uvm_va_block_get_va_space_maybe_dead(va_block); struct mm_struct *mm; + bool accessed_by_set = false; uvm_assert_mutex_locked(&va_block->lock); @@ -10414,7 +11087,7 @@ NV_STATUS uvm_va_block_evict_chunks(uvm_va_block_t *va_block, // We cannot take this block's VA space or mmap_lock locks on the eviction // path, however, we retain mm in order to support accounting of CPU memory // allocations. If mappings need to be created, - // block_deferred_eviction_mappings() will be scheduled below. + // block_add_eviction_mappings() will be scheduled below. mm = uvm_va_space_mm_retain(va_space); block_context = uvm_va_block_context_alloc(mm); if (!block_context) { @@ -10440,6 +11113,12 @@ NV_STATUS uvm_va_block_evict_chunks(uvm_va_block_t *va_block, if (!uvm_gpu_chunk_same_root(gpu_state->chunks[i], root_chunk)) continue; + if (uvm_va_block_is_hmm(va_block)) { + status = uvm_hmm_va_block_evict_chunk_prep(va_block, block_context, gpu_state->chunks[i], chunk_region); + if (status != NV_OK) + break; + } + uvm_page_mask_region_fill(pages_to_evict, chunk_region); ++chunks_to_evict; } @@ -10449,20 +11128,31 @@ NV_STATUS uvm_va_block_evict_chunks(uvm_va_block_t *va_block, // Only move pages resident on the GPU uvm_page_mask_and(pages_to_evict, pages_to_evict, uvm_va_block_resident_mask_get(va_block, gpu->id)); + uvm_processor_mask_zero(&block_context->make_resident.all_involved_processors); - block_context->policy = uvm_va_range_get_policy(va_block->va_range); + if (uvm_va_block_is_hmm(va_block)) { + status = uvm_hmm_va_block_evict_chunks(va_block, + block_context, + pages_to_evict, + uvm_va_block_region_from_block(va_block), + &accessed_by_set); + } + else { + block_context->policy = uvm_va_range_get_policy(va_block->va_range); + accessed_by_set = uvm_processor_mask_get_count(&block_context->policy->accessed_by) > 0; - // TODO: Bug 1765193: make_resident() breaks read-duplication, but it's not - // necessary to do so for eviction. Add a version that unmaps only the - // processors that have mappings to the pages being evicted. - status = uvm_va_block_make_resident(va_block, - NULL, - block_context, - UVM_ID_CPU, - uvm_va_block_region_from_block(va_block), - pages_to_evict, - NULL, - UVM_MAKE_RESIDENT_CAUSE_EVICTION); + // TODO: Bug 1765193: make_resident() breaks read-duplication, but it's + // not necessary to do so for eviction. Add a version that unmaps only + // the processors that have mappings to the pages being evicted. + status = uvm_va_block_make_resident(va_block, + NULL, + block_context, + UVM_ID_CPU, + uvm_va_block_region_from_block(va_block), + pages_to_evict, + NULL, + UVM_MAKE_RESIDENT_CAUSE_EVICTION); + } if (status != NV_OK) goto out; @@ -10482,16 +11172,13 @@ NV_STATUS uvm_va_block_evict_chunks(uvm_va_block_t *va_block, // // If a processor gets removed from the mask then we might not notice and // schedule the work item anyway, but that's benign as - // block_deferred_eviction_mappings() re-examines the mask. + // block_add_eviction_mappings() re-examines the mask. // // Checking if access counters migrations are enabled on a VA space is racy // without holding the VA space lock. However, this is fine as - // block_deferred_eviction_mappings() reexamines the value with the VA space + // block_add_eviction_mappings() reexamines the value with the VA space // lock being held. - if (uvm_processor_mask_get_count(&block_context->policy->accessed_by) > 0 || - (gpu->parent->access_counters_supported && - va_space_map_remote_on_eviction(va_space) && - !uvm_va_block_is_hmm(va_block))) { + if (accessed_by_set || (gpu->parent->access_counters_supported && uvm_va_space_map_remote_on_eviction(va_space))) { // Always retain the VA block first so that it's safe for the deferred // callback to release it immediately after it runs. uvm_va_block_retain(va_block); @@ -10670,8 +11357,15 @@ NV_STATUS uvm_test_va_block_inject_error(UVM_TEST_VA_BLOCK_INJECT_ERROR_PARAMS * if (params->user_pages_allocation_retry_force_count) va_block_test->user_pages_allocation_retry_force_count = params->user_pages_allocation_retry_force_count; - if (params->cpu_chunk_allocation_size_mask) - va_block_test->cpu_chunk_allocation_size_mask = params->cpu_chunk_allocation_size_mask; + if (params->cpu_chunk_allocation_size_mask) { + if (params->cpu_chunk_allocation_size_mask & ~UVM_CPU_CHUNK_SIZES || + !(params->cpu_chunk_allocation_size_mask & PAGE_SIZE)) { + status = NV_ERR_INVALID_ARGUMENT; + goto block_unlock; + } + + va_block_test->cpu_chunk_allocation_size_mask = params->cpu_chunk_allocation_size_mask & UVM_CPU_CHUNK_SIZES; + } if (params->eviction_error) va_block_test->inject_eviction_error = params->eviction_error; @@ -10682,6 +11376,7 @@ NV_STATUS uvm_test_va_block_inject_error(UVM_TEST_VA_BLOCK_INJECT_ERROR_PARAMS * if (params->populate_error) va_block_test->inject_populate_error = params->populate_error; +block_unlock: uvm_mutex_unlock(&va_block->lock); out: @@ -10762,6 +11457,10 @@ NV_STATUS uvm_test_change_pte_mapping(UVM_TEST_CHANGE_PTE_MAPPING_PARAMS *params if (status != NV_OK) goto out; + // TODO: Bug 3912902: UvmTestChangePteMapping() doesn't work on CPU. + if (UVM_ID_IS_CPU(id) && uvm_va_block_is_hmm(block)) + goto out; + uvm_mutex_lock(&block->lock); region = uvm_va_block_region_from_start_size(block, params->va, PAGE_SIZE); @@ -10791,7 +11490,7 @@ NV_STATUS uvm_test_change_pte_mapping(UVM_TEST_CHANGE_PTE_MAPPING_PARAMS *params // Revoking CPU mappings performs a combination of unmap + map. The map // portion requires a valid mm. - if (UVM_ID_IS_CPU(id) && !uvm_va_block_is_hmm(block) && !uvm_va_range_vma_check(block->va_range, mm)) { + if (UVM_ID_IS_CPU(id) && !uvm_va_range_vma_check(block->va_range, mm)) { status = NV_ERR_INVALID_STATE; } else { @@ -10827,21 +11526,47 @@ NV_STATUS uvm_test_va_block_info(UVM_TEST_VA_BLOCK_INFO_PARAMS *params, struct f { uvm_va_space_t *va_space = uvm_va_space_get(filp); uvm_va_block_t *va_block; + uvm_va_range_t *va_range; + struct mm_struct *mm; + size_t index; NV_STATUS status = NV_OK; BUILD_BUG_ON(UVM_TEST_VA_BLOCK_SIZE != UVM_VA_BLOCK_SIZE); + mm = uvm_va_space_mm_or_current_retain_lock(va_space); uvm_va_space_down_read(va_space); - status = uvm_va_block_find(va_space, params->lookup_address, &va_block); - if (status != NV_OK) - goto out; + va_range = uvm_va_range_find(va_space, params->lookup_address); + if (!va_range) { + status = uvm_hmm_va_block_find(va_space, params->lookup_address, &va_block); + if (status == NV_ERR_OBJECT_NOT_FOUND) { + status = uvm_hmm_va_block_range_bounds(va_space, + mm, + params->lookup_address, + ¶ms->va_block_start, + ¶ms->va_block_end, + NULL); + goto out; + } + else if (status != NV_OK) { + goto out; + } + } + else { + index = uvm_va_range_block_index(va_range, params->lookup_address); + va_block = uvm_va_range_block(va_range, index); + if (!va_block) { + status = NV_ERR_OBJECT_NOT_FOUND; + goto out; + } + } params->va_block_start = va_block->start; params->va_block_end = va_block->end; out: uvm_va_space_up_read(va_space); + uvm_va_space_mm_or_current_release_unlock(va_space, mm); return status; } @@ -10849,34 +11574,55 @@ NV_STATUS uvm_test_va_residency_info(UVM_TEST_VA_RESIDENCY_INFO_PARAMS *params, { NV_STATUS status = NV_OK; uvm_va_space_t *va_space = uvm_va_space_get(filp); - uvm_va_range_t *va_range = NULL; + uvm_va_range_t *va_range; uvm_va_block_t *block = NULL; + struct mm_struct *mm; NvU32 count = 0; uvm_processor_mask_t resident_on_mask; uvm_processor_id_t id; uvm_page_index_t page_index; unsigned release_block_count = 0; NvU64 addr = UVM_ALIGN_DOWN(params->lookup_address, PAGE_SIZE); + size_t index; + mm = uvm_va_space_mm_or_current_retain_lock(va_space); uvm_va_space_down_read(va_space); + // Inline uvm_va_block_find() to get the va_range. va_range = uvm_va_range_find(va_space, addr); - if (!va_range || va_range->type != UVM_VA_RANGE_TYPE_MANAGED) { + if (!va_range) { + NvU64 start, end; + + status = uvm_hmm_va_block_find(va_space, addr, &block); + if (status != NV_OK) { + if (status != NV_ERR_OBJECT_NOT_FOUND) + goto out; + status = uvm_hmm_va_block_range_bounds(va_space, mm, addr, &start, &end, params); + goto out; + } + // Update current CPU mapping information. + status = uvm_hmm_va_block_update_residency_info(block, mm, addr, false); + if (status != NV_OK) { + block = NULL; + goto out; + } + } + else if (va_range->type != UVM_VA_RANGE_TYPE_MANAGED) { status = NV_ERR_INVALID_ADDRESS; goto out; } + else { + index = uvm_va_range_block_index(va_range, addr); + block = uvm_va_range_block(va_range, index); + if (!block) { + params->resident_on_count = 0; + params->populated_on_count = 0; + params->mapped_on_count = 0; - status = uvm_va_block_find(va_space, addr, &block); - if (status != NV_OK) { - UVM_ASSERT(status == NV_ERR_OBJECT_NOT_FOUND); + status = NV_OK; - params->resident_on_count = 0; - params->populated_on_count = 0; - params->mapped_on_count = 0; - - status = NV_OK; - - goto out; + goto out; + } } uvm_mutex_lock(&block->lock); @@ -10889,11 +11635,7 @@ NV_STATUS uvm_test_va_residency_info(UVM_TEST_VA_RESIDENCY_INFO_PARAMS *params, uvm_va_space_processor_uuid(va_space, ¶ms->resident_on[count], id); params->resident_physical_size[count] = block_phys_page_size(block, block_page); if (UVM_ID_IS_CPU(id)) { - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); - - params->resident_physical_address[count] = page_to_phys(uvm_cpu_chunk_get_cpu_page(block, - chunk, - page_index)); + params->resident_physical_address[count] = page_to_phys(uvm_cpu_chunk_get_cpu_page(block, page_index)); } else { params->resident_physical_address[count] = @@ -10905,7 +11647,10 @@ NV_STATUS uvm_test_va_residency_info(UVM_TEST_VA_RESIDENCY_INFO_PARAMS *params, count = 0; for_each_id_in_mask(id, &block->mapped) { + uvm_processor_id_t processor_to_map; + block_phys_page_t block_page; NvU32 page_size = uvm_va_block_page_size_processor(block, id, page_index); + if (page_size == 0) continue; @@ -10913,6 +11658,20 @@ NV_STATUS uvm_test_va_residency_info(UVM_TEST_VA_RESIDENCY_INFO_PARAMS *params, params->mapping_type[count] = g_uvm_prot_to_test_pte_mapping[block_page_prot(block, id, page_index)]; UVM_ASSERT(params->mapping_type[count] != UVM_TEST_PTE_MAPPING_INVALID); + processor_to_map = block_get_processor_to_map(block, id, page_index); + block_page = block_phys_page(processor_to_map, page_index); + + if (!UVM_ID_IS_CPU(id)) { + uvm_gpu_phys_address_t gpu_phys_addr = block_phys_page_address(block, + block_page, + uvm_va_space_get_gpu(va_space, id)); + params->mapping_physical_address[count] = gpu_phys_addr.address; + } + else { + struct page *page = block_page_get(block, block_page); + + params->mapping_physical_address[count] = page_to_phys(page); + } params->page_size[count] = page_size; ++count; @@ -10937,10 +11696,7 @@ NV_STATUS uvm_test_va_residency_info(UVM_TEST_VA_RESIDENCY_INFO_PARAMS *params, continue; num_pages = uvm_pmm_sysmem_mappings_dma_to_virt(&gpu->pmm_reverse_sysmem_mappings, - uvm_cpu_chunk_get_gpu_mapping_addr(block, - page_index, - chunk, - id), + uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent), uvm_cpu_chunk_get_size(chunk), &sysmem_page, 1); @@ -11002,6 +11758,7 @@ out: uvm_va_block_release(block); } uvm_va_space_up_read(va_space); + uvm_va_space_mm_or_current_release_unlock(va_space, mm); return status; } diff --git a/kernel-open/nvidia-uvm/uvm_va_block.h b/kernel-open/nvidia-uvm/uvm_va_block.h index f4b847b78..a7d5730f8 100644 --- a/kernel-open/nvidia-uvm/uvm_va_block.h +++ b/kernel-open/nvidia-uvm/uvm_va_block.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -43,6 +43,7 @@ #include "nv-kthread-q.h" #include +#include // VA blocks are the leaf nodes in the uvm_va_space tree for managed allocations // (VA ranges with type == UVM_VA_RANGE_TYPE_MANAGED): @@ -328,7 +329,7 @@ struct uvm_va_block_struct // allocations. See uvm_pmm_sysmem.h for more details on CPU chunks. // This member is meant to hold an opaque value indicating the CPU // chunk storage method. For more details on CPU chunk storage, - // see uvm_cpu_chunk_storage_type_t in uvm_pmm_sysmem.c. + // see uvm_cpu_chunk_storage_type_t in uvm_va_block.c. unsigned long chunks; // Per-page allocation bit vector. @@ -352,12 +353,18 @@ struct uvm_va_block_struct // UVM_PTE_BITS_CPU_WRITE is not set, the mapping is read-only. // Otherwise, the mapping is read-write. // - // Note that this is the maximum permissions a PTE could have, but not - // necessarily the actual current permissions of the CPU PTEs. The UVM - // driver will never change the PTEs without updating this state, but - // the kernel can downgrade our CPU mappings at any time without - // notifying the UVM driver (for example in response to user space - // calling madvise with MADV_DONTNEED). + // For managed allocations, this is the maximum permissions a PTE + // could have, but not necessarily the actual current permissions of the + // CPU PTEs. The UVM driver will never change the PTEs without updating + // this state, but the kernel can downgrade our CPU mappings at any time + // without notifying the UVM driver (for example in response to user + // space calling madvise with MADV_DONTNEED). + // + // For HMM allocations, this is the minimum permission the CPU has since + // Linux can upgrade a read-only PTE to read-write without notifying + // the UVM driver. This is why read duplication isn't currently + // supported. + // TODO: Bug 3660922: Need to handle read duplication at some point. uvm_page_mask_t pte_bits[UVM_PTE_BITS_CPU_MAX]; // Whether the CPU has ever mapped a page on this VA block. This is @@ -452,6 +459,19 @@ struct uvm_va_block_struct // The MMU notifier is registered per va_block. struct mmu_interval_notifier notifier; + // Wait queue for GPU atomic operations to system memory. + struct wait_queue_head atomic_waitq; + + // Mask of pages being migrated to system memory for GPU atomic access. + // It is used so other threads don't try to migrate those pages while + // make_device_exclusive_range() is called without holding the va_block + // lock. + uvm_page_mask_t atomic_busy; + + // Sequence number to tell if any changes were made to the va_block + // while not holding the block lock and calling hmm_range_fault(). + unsigned long changed; + // Parent VA space pointer. It is NULL for managed blocks or if // the HMM block is dead. This field can be read while holding the // block lock and is only modified while holding the va_space write @@ -522,7 +542,7 @@ struct uvm_va_block_wrapper_struct }; // Tracking needed for supporting allocation-retry of user GPU memory -typedef struct +struct uvm_va_block_retry_struct { // A tracker used for all allocations from PMM. uvm_tracker_t tracker; @@ -537,7 +557,7 @@ typedef struct // can contain chunks from multiple GPUs. All the used chunks are unpinned // when the operation is finished with uvm_va_block_retry_deinit(). struct list_head used_chunks; -} uvm_va_block_retry_t; +}; // Module load/exit NV_STATUS uvm_va_block_init(void); @@ -635,6 +655,12 @@ uvm_va_space_t *uvm_va_block_get_va_space_maybe_dead(uvm_va_block_t *va_block); // is held in write mode. uvm_va_space_t *uvm_va_block_get_va_space(uvm_va_block_t *va_block); +// Return true if the VA space has access counter migrations enabled and should +// remote map pages evicted to system memory. This is OK since access counters +// can pull the data back to vidmem if sufficient accesses trigger a migration. +// The caller must ensure that the VA space cannot go away. +bool uvm_va_space_map_remote_on_eviction(uvm_va_space_t *va_space); + // Dynamic cache-based allocation for uvm_va_block_context_t. // // See uvm_va_block_context_init() for a description of the mm parameter. @@ -663,7 +689,7 @@ static void uvm_va_block_context_init(uvm_va_block_context_t *va_block_context, // This always returns true and is intended to only be used with UVM_ASSERT(). // Locking: the va_block lock must be held. bool uvm_va_block_check_policy_is_valid(uvm_va_block_t *va_block, - uvm_va_policy_t *policy, + const uvm_va_policy_t *policy, uvm_va_block_region_t region); // TODO: Bug 1766480: Using only page masks instead of a combination of regions @@ -697,7 +723,7 @@ bool uvm_va_block_check_policy_is_valid(uvm_va_block_t *va_block, // // Allocation-retry: this operation may need to perform eviction to be able to // allocate GPU memory successfully and if that happens, -// NV_WARN_MORE_PROCESSING_REQUIRED will be returned. That also means that the +// NV_ERR_MORE_PROCESSING_REQUIRED will be returned. That also means that the // block's lock has been unlocked and relocked as part of the call and that the // whole sequence of operations performed under the block's lock needs to be // attempted again. To facilitate that, the caller needs to provide the same @@ -707,14 +733,15 @@ bool uvm_va_block_check_policy_is_valid(uvm_va_block_t *va_block, // caller. // // If dest_id is the CPU then va_block_retry can be NULL and allocation-retry of -// user memory is guaranteed not to happen. Allocation-retry of page tables can -// still occur though. +// user memory is guaranteed not to happen. Allocation-retry of GPU page tables +// can still occur though. // // va_block_context must not be NULL. This function will set a bit in // va_block_context->make_resident.pages_changed_residency for each page that // changed residency (due to a migration or first population) as a result of the -// operation. This function only sets bits in that mask. It is the caller's -// responsiblity to zero the mask or not first. +// operation and va_block_context->make_resident.all_involved_processors for +// each processor involved in the copy. This function only sets bits in those +// masks. It is the caller's responsiblity to zero the masks or not first. // // va_block_context->policy must also be set by the caller for the given region. // See the comments for uvm_va_block_check_policy_is_valid(). @@ -723,6 +750,8 @@ bool uvm_va_block_check_policy_is_valid(uvm_va_block_t *va_block, // have been unlocked and relocked. // // LOCKING: The caller must hold the va_block lock. +// If va_block_context->mm != NULL, va_block_context->mm->mmap_lock must be +// held in at least read mode. NV_STATUS uvm_va_block_make_resident(uvm_va_block_t *va_block, uvm_va_block_retry_t *va_block_retry, uvm_va_block_context_t *va_block_context, @@ -743,8 +772,6 @@ NV_STATUS uvm_va_block_make_resident(uvm_va_block_t *va_block, // are broken // - Only managed va_blocks are supported. // TODO: Bug 3660922: need to implement HMM read duplication support. -// - LOCKING: If va_block_context->mm != NULL, va_block_context->mm->mmap_lock -// must be held in at least read mode. NV_STATUS uvm_va_block_make_resident_read_duplicate(uvm_va_block_t *va_block, uvm_va_block_retry_t *va_block_retry, uvm_va_block_context_t *va_block_context, @@ -756,31 +783,35 @@ NV_STATUS uvm_va_block_make_resident_read_duplicate(uvm_va_block_t *va_block, // Similar to uvm_va_block_make_resident() (read documentation there). The // difference is that source pages are only copied to the destination and the -// residency is not updated until uvm_va_block_make_resident_post() is called. -// Otherwise, the combination of uvm_va_block_make_resident_pre() and -// uvm_va_block_make_resident_post() should be the same as just calling -// uvm_va_block_make_resident(). +// residency is not updated until uvm_va_block_make_resident_finish() is called. +// Otherwise, the combination of uvm_va_block_make_resident_copy() and +// uvm_va_block_make_resident_finish() is the same as just calling +// uvm_va_block_make_resident(). Note, however, that the va_block lock must be +// held across the two calls for the operation to be complete. The va_block +// lock can be dropped after calling uvm_va_block_make_resident_copy() but +// uvm_va_block_make_resident_copy() must be called again after relocking the +// va_block lock and before calling uvm_va_block_make_resident_finish(). // This split is needed when using migrate_vma_setup() and migrate_vma_pages() // so that when migrate_vma_pages() indicates a page is not migrating, the // va_block state is not updated. // LOCKING: The caller must hold the va_block lock. -NV_STATUS uvm_va_block_make_resident_pre(uvm_va_block_t *va_block, - uvm_va_block_retry_t *va_block_retry, - uvm_va_block_context_t *va_block_context, - uvm_processor_id_t dest_id, - uvm_va_block_region_t region, - const uvm_page_mask_t *page_mask, - const uvm_page_mask_t *prefetch_page_mask, - uvm_make_resident_cause_t cause); +NV_STATUS uvm_va_block_make_resident_copy(uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t dest_id, + uvm_va_block_region_t region, + const uvm_page_mask_t *page_mask, + const uvm_page_mask_t *prefetch_page_mask, + uvm_make_resident_cause_t cause); // The page_mask must be the same or a subset of the page_mask passed to -// uvm_va_block_make_resident_pre(). This step updates the residency and breaks +// uvm_va_block_make_resident_copy(). This step updates the residency and breaks // read duplication. // LOCKING: The caller must hold the va_block lock. -void uvm_va_block_make_resident_post(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, - uvm_va_block_region_t region, - const uvm_page_mask_t *page_mask); +void uvm_va_block_make_resident_finish(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_va_block_region_t region, + const uvm_page_mask_t *page_mask); // Creates or upgrades a mapping from the input processor to the given virtual // address region. Pages which already have new_prot permissions or higher are @@ -905,7 +936,8 @@ NV_STATUS uvm_va_block_unmap_mask(uvm_va_block_t *va_block, // // LOCKING: The caller must hold the VA block lock. NV_STATUS uvm_va_block_set_preferred_location_locked(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context); + uvm_va_block_context_t *va_block_context, + uvm_va_block_region_t region); // Maps the given processor to all resident pages in this block, as allowed by // location and policy. Waits for the operation to complete before returning. @@ -921,6 +953,22 @@ NV_STATUS uvm_va_block_set_accessed_by(uvm_va_block_t *va_block, uvm_va_block_context_t *va_block_context, uvm_processor_id_t processor_id); +// Maps given processor to all resident pages in this block and region, as +// allowed by location and policy. The caller is responsible for waiting for +// the tracker after all mappings have been started. +// This function can be called with HMM and managed va_blocks. +// +// va_block_context must not be NULL and va_block_context->policy must be valid. +// See the comments for uvm_va_block_check_policy_is_valid(). +// +// LOCKING: The caller must hold the va_block lock and +// va_block_context->mm->mmap_lock must be held in at least read mode. +NV_STATUS uvm_va_block_set_accessed_by_locked(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t processor_id, + uvm_va_block_region_t region, + uvm_tracker_t *out_tracker); + // Breaks SetAccessedBy and remote mappings // This function should only be called with managed va_blocks. // @@ -1124,6 +1172,11 @@ void uvm_va_block_unmap_preferred_location_uvm_lite(uvm_va_block_t *va_block, uv // must hold mm->mmap_lock in at least read mode. void uvm_va_block_unregister_gpu(uvm_va_block_t *va_block, uvm_gpu_t *gpu, struct mm_struct *mm); +// Same as uvm_va_block_unregister_gpu() but the VA block lock must be held. +// Note that this handles allocation-retry internally and hence might unlock +// and relock block's lock. +void uvm_va_block_unregister_gpu_locked(uvm_va_block_t *va_block, uvm_gpu_t *gpu, struct mm_struct *mm); + // Unmaps all memory associated with the block and drops the ref count of the // block. This allows the caller to free resources associated with this block // regardless of the block's current ref count. Most importantly it allows the @@ -1186,9 +1239,13 @@ NV_STATUS uvm_va_block_cpu_fault(uvm_va_block_t *va_block, // Performs any operations necessary to establish a coherent mapping // (migrations, cache invalidates, etc.) in response to the given service block -// context +// context. // -// service_context->block_context.policy is set by this function. +// service_context must not be NULL and service_context->block_context.policy +// must be valid. See the comments for uvm_va_block_check_policy_is_valid(). +// If va_block is a HMM block, va_block_context->hmm.vma must be valid. +// See the comments for uvm_hmm_check_context_vma_is_valid() in uvm_hmm.h. +// service_context->prefetch_hint is set by this function. // // Locking: // - service_context->block_context.mm->mmap_lock must be held in at least @@ -1197,8 +1254,8 @@ NV_STATUS uvm_va_block_cpu_fault(uvm_va_block_t *va_block, // - va_block lock must be held // // If allocation-retry was required as part of the operation and was successful, -// NV_ERR_MORE_PROCESSING_REQUIRED is returned. In this case, the block's lock was -// unlocked and relocked. +// NV_ERR_MORE_PROCESSING_REQUIRED is returned. In this case, the block's lock +// was unlocked and relocked. // // NV_WARN_MORE_PROCESSING_REQUIRED indicates that thrashing has been detected // and the performance heuristics logic decided to throttle execution. @@ -1209,6 +1266,77 @@ NV_STATUS uvm_va_block_service_locked(uvm_processor_id_t processor_id, uvm_va_block_retry_t *block_retry, uvm_service_block_context_t *service_context); +// Performs population of the destination pages, unmapping and copying source +// pages to new_residency. +// +// service_context must not be NULL and service_context->block_context.policy +// must be valid. See the comments for uvm_va_block_check_policy_is_valid(). +// If va_block is a HMM block, va_block_context->hmm.vma must be valid. +// See the comments for uvm_hmm_check_context_vma_is_valid() in uvm_hmm.h. +// service_context->prefetch_hint should be set before calling this function. +// +// Locking: +// - service_context->block_context.mm->mmap_lock must be held in at least +// read mode, if valid. +// - va_space lock must be held in at least read mode +// - va_block lock must be held +// +// If allocation-retry was required as part of the operation and was successful, +// NV_ERR_MORE_PROCESSING_REQUIRED is returned. In this case, the block's lock +// was unlocked and relocked. +// +// NV_WARN_MORE_PROCESSING_REQUIRED indicates that thrashing has been detected +// and the performance heuristics logic decided to throttle execution. +// Any other error code different than NV_OK indicates OOM or a global fatal +// error. +NV_STATUS uvm_va_block_service_copy(uvm_processor_id_t processor_id, + uvm_processor_id_t new_residency, + uvm_va_block_t *va_block, + uvm_va_block_retry_t *block_retry, + uvm_service_block_context_t *service_context); + +// This updates the va_block residency state and maps the faulting processor_id +// to the new residency (which may be remote). +// +// service_context must not be NULL and service_context->block_context.policy +// must be valid. See the comments for uvm_va_block_check_policy_is_valid(). +// If va_block is a HMM block, va_block_context->hmm.vma must be valid. +// See the comments for uvm_hmm_check_context_vma_is_valid() in uvm_hmm.h. +// service_context must be initialized by calling uvm_va_block_service_copy() +// before calling this function. +// +// Locking: +// - service_context->block_context.mm->mmap_lock must be held in at least +// read mode, if valid. +// - va_space lock must be held in at least read mode +// - va_block lock must be held +// - the mmap lock and va_space lock must be held across the calls to +// uvm_va_block_service_copy() and this function. If the va_block lock is +// dropped inbetween, special care is needed to check for eviction and +// invalidation callbacks. +// +// If allocation-retry was required as part of the operation and was successful, +// NV_ERR_MORE_PROCESSING_REQUIRED is returned. In this case, the block's lock +// was unlocked and relocked. +// +// NV_WARN_MORE_PROCESSING_REQUIRED indicates that thrashing has been detected +// and the performance heuristics logic decided to throttle execution. +// Any other error code different than NV_OK indicates OOM or a global fatal +// error. +NV_STATUS uvm_va_block_service_finish(uvm_processor_id_t processor_id, + uvm_va_block_t *va_block, + uvm_service_block_context_t *service_context); + +// Allocate GPU state for the given va_block and registered GPUs. +// Locking: The block lock must be held. +NV_STATUS uvm_va_block_gpu_state_alloc(uvm_va_block_t *va_block); + +// Release any GPU or policy data associated with the given region in response +// to munmap(). +// Locking: The va_block lock must be held. +void uvm_va_block_munmap_region(uvm_va_block_t *va_block, + uvm_va_block_region_t region); + // Size of the block in bytes. Guaranteed to be a page-aligned value between // PAGE_SIZE and UVM_VA_BLOCK_SIZE. static inline NvU64 uvm_va_block_size(uvm_va_block_t *block) @@ -1275,7 +1403,7 @@ const uvm_page_mask_t *uvm_va_block_map_mask_get(uvm_va_block_t *block, uvm_proc // VA block lookup functions. There are a number of permutations which might be // useful, such as looking up the block from {va_space, va_range} x {addr, // block index}. The ones implemented here and in uvm_va_range.h support the -// primary two use cases, which are: +// primary three use cases, which are: // 1) Iterating over all VA blocks in a VA range. This uses block indices on the // VA range: // uvm_va_range_num_blocks @@ -1286,6 +1414,9 @@ const uvm_page_mask_t *uvm_va_block_map_mask_get(uvm_va_block_t *block, uvm_proc // VA space and address: // uvm_va_block_find // uvm_va_block_find_create +// 3) Operating on a single VA block (fault). This looks up the block using the +// supplied VA range and address: +// uvm_va_block_find_create_in_range // Finds the UVM or HMM VA block containing addr, if any. The va_space->lock // must be held in at least read mode. Return values: @@ -1315,6 +1446,15 @@ NV_STATUS uvm_va_block_find_create(uvm_va_space_t *va_space, uvm_va_block_context_t *va_block_context, uvm_va_block_t **out_block); +// Same as uvm_va_block_find_create except that va_range lookup was already done +// by the caller. If the supplied va_range is NULL, this function behaves just +// like when the va_range lookup in uvm_va_block_find_create is NULL. +NV_STATUS uvm_va_block_find_create_in_range(uvm_va_space_t *va_space, + uvm_va_range_t *va_range, + NvU64 addr, + uvm_va_block_context_t *va_block_context, + uvm_va_block_t **out_block); + // Same as uvm_va_block_find_create except that only managed va_blocks are // created if not already present in the VA range. static NV_STATUS uvm_va_block_find_create_managed(uvm_va_space_t *va_space, @@ -1324,15 +1464,10 @@ static NV_STATUS uvm_va_block_find_create_managed(uvm_va_space_t *va_space, return uvm_va_block_find_create(va_space, addr, NULL, out_block); } -// Look up a chunk backing a specific address within the VA block. Returns NULL if none. +// Look up a chunk backing a specific address within the VA block. +// Returns NULL if none. uvm_gpu_chunk_t *uvm_va_block_lookup_gpu_chunk(uvm_va_block_t *va_block, uvm_gpu_t *gpu, NvU64 address); -typedef enum -{ - UVM_MIGRATE_MODE_MAKE_RESIDENT, - UVM_MIGRATE_MODE_MAKE_RESIDENT_AND_MAP, -} uvm_migrate_mode_t; - // Implementation of the UvmMigrate() API at the VA block scope. // // The out_tracker can be NULL. @@ -1345,6 +1480,8 @@ typedef enum // // va_block_context must not be NULL and va_block_context->policy must be valid. // See the comments for uvm_va_block_check_policy_is_valid(). +// If va_block is a HMM block, va_block_context->hmm.vma must be valid. +// See the comments for uvm_hmm_check_context_vma_is_valid() in uvm_hmm.h. // // LOCKING: The caller must hold the va_block lock. If va_block_context->mm != // NULL, va_block_context->mm->mmap_lock must be held in at least @@ -1362,7 +1499,7 @@ NV_STATUS uvm_va_block_migrate_locked(uvm_va_block_t *va_block, // The [dst, dst + size) range has to fit within a single PAGE_SIZE page. // // va_block_context must not be NULL. The caller is not required to set -// va_block_context->policy. +// va_block_context->policy or va_block_context->hmm.vma. // // The caller needs to support allocation-retry of page tables. // @@ -1416,6 +1553,8 @@ static uvm_page_index_t uvm_va_block_cpu_page_index(uvm_va_block_t *va_block, Nv // Computes the size and index in the gpu_state chunks array of the GPU chunk // which corresponds to the given page_index of the VA region. +// Note this is only used for testing and does not work on HMM va_blocks as it +// returns incorrect results for those. size_t uvm_va_block_gpu_chunk_index_range(NvU64 start, NvU64 size, uvm_gpu_t *gpu, @@ -1868,77 +2007,66 @@ static uvm_va_block_region_t uvm_va_block_chunk_region(uvm_va_block_t *block, // Helpers for page state (permissions, size, residency) // -// Compute the gpus that have at least the given access permissions for the -// range described by region and page_mask. The function sets the bit if any -// page in the region has the permissions. -void uvm_va_block_region_authorized_gpus(uvm_va_block_t *va_block, - uvm_va_block_region_t region, - uvm_prot_t access_permission, - uvm_processor_mask_t *authorized_gpus); - -// Compute the processors that have at least the given access permissions for the -// range described by region and page_mask. The function sets the bit if any -// page in the region has the permissions. -void uvm_va_block_region_authorized_processors(uvm_va_block_t *va_block, - uvm_va_block_region_t region, - uvm_prot_t access_permission, - uvm_processor_mask_t *authorized_processors); - -void uvm_va_block_page_authorized_gpus(uvm_va_block_t *va_block, - uvm_page_index_t page_index, - uvm_prot_t access_permission, - uvm_processor_mask_t *authorized_gpus); - -void uvm_va_block_page_authorized_processors(uvm_va_block_t *va_block, - uvm_page_index_t page_index, - uvm_prot_t access_permission, - uvm_processor_mask_t *authorized_processors); - -bool uvm_va_block_is_gpu_authorized_on_whole_region(uvm_va_block_t *va_block, - uvm_va_block_region_t region, - uvm_gpu_id_t gpu_id, - uvm_prot_t required_prot); - -bool uvm_va_block_is_processor_authorized_on_whole_region(uvm_va_block_t *va_block, - uvm_va_block_region_t region, - uvm_processor_id_t processor_id, - uvm_prot_t required_prot); - bool uvm_va_block_page_is_gpu_authorized(uvm_va_block_t *va_block, uvm_page_index_t page_index, uvm_gpu_id_t gpu_id, uvm_prot_t required_prot); -bool uvm_va_block_page_is_processor_authorized(uvm_va_block_t *va_block, - uvm_page_index_t page_index, - uvm_processor_id_t processor_id, - uvm_prot_t required_prot); - -// Compute the gpus that have a copy of the given page resident in their memory -void uvm_va_block_page_resident_gpus(uvm_va_block_t *va_block, - uvm_page_index_t page_index, - uvm_processor_mask_t *resident_gpus); - -// Compute the processors that have a copy of the given page resident in their memory +// Compute the processors that have a copy of the given page resident in their +// memory. void uvm_va_block_page_resident_processors(uvm_va_block_t *va_block, uvm_page_index_t page_index, uvm_processor_mask_t *resident_processors); -// Count how many processors have a copy of the given page resident in their memory +// Count how many processors have a copy of the given page resident in their +// memory. NvU32 uvm_va_block_page_resident_processors_count(uvm_va_block_t *va_block, uvm_page_index_t page_index); -// Get the processor with a resident copy of a page closest to the given processor +// Get the processor with a resident copy of a page closest to the given +// processor. uvm_processor_id_t uvm_va_block_page_get_closest_resident(uvm_va_block_t *va_block, uvm_page_index_t page_index, uvm_processor_id_t processor); -uvm_processor_id_t uvm_va_block_page_get_closest_resident_in_mask(uvm_va_block_t *va_block, - uvm_page_index_t page_index, - uvm_processor_id_t processor, - const uvm_processor_mask_t *processor_mask); +// Insert a CPU chunk at the given page_index into the va_block. +// Locking: The va_block lock must be held. +NV_STATUS uvm_cpu_chunk_insert_in_block(uvm_va_block_t *va_block, + uvm_cpu_chunk_t *chunk, + uvm_page_index_t page_index); + +// Remove a CPU chunk at the given page_index from the va_block. +// Locking: The va_block lock must be held. +void uvm_cpu_chunk_remove_from_block(uvm_va_block_t *va_block, + uvm_page_index_t page_index); + +// Return the CPU chunk at the given page_index from the va_block. +// Locking: The va_block lock must be held. +uvm_cpu_chunk_t *uvm_cpu_chunk_get_chunk_for_page(uvm_va_block_t *va_block, + uvm_page_index_t page_index); + +// Return the CPU chunk at the given page_index from the va_block. +// Locking: The va_block lock must be held. +struct page *uvm_cpu_chunk_get_cpu_page(uvm_va_block_t *va_block, + uvm_page_index_t page_index); + +// Physically map a CPU chunk so it is DMA'able from all registered GPUs. +// Locking: The va_block lock must be held. +NV_STATUS uvm_va_block_map_cpu_chunk_on_gpus(uvm_va_block_t *va_block, + uvm_page_index_t page_index); + +// Physically unmap a CPU chunk from all registered GPUs. +// Locking: The va_block lock must be held. +void uvm_va_block_unmap_cpu_chunk_on_gpus(uvm_va_block_t *va_block, + uvm_cpu_chunk_t *chunk, + uvm_page_index_t page_index); + +// Remove any CPU chunks in the given region. +// Locking: The va_block lock must be held. +void uvm_va_block_remove_cpu_chunks(uvm_va_block_t *va_block, uvm_va_block_region_t region); // Get CPU page size or 0 if it is not mapped -NvU32 uvm_va_block_page_size_cpu(uvm_va_block_t *va_block, uvm_page_index_t page_index); +NvU32 uvm_va_block_page_size_cpu(uvm_va_block_t *va_block, + uvm_page_index_t page_index); // Get GPU page size or 0 if it is not mapped on the given GPU NvU32 uvm_va_block_page_size_gpu(uvm_va_block_t *va_block, uvm_gpu_id_t gpu_id, uvm_page_index_t page_index); @@ -1999,14 +2127,14 @@ size_t uvm_va_block_big_page_index(uvm_va_block_t *va_block, uvm_page_index_t pa // and if the va_block is a HMM block, va_block_context->hmm.vma must be valid // which also means the va_block_context->mm is not NULL, retained, and locked // for at least read. See the comments for uvm_va_block_check_policy_is_valid() -// and uvm_hmm_va_block_context_vma_is_valid() in uvm_hmm.h. +// and uvm_hmm_check_context_vma_is_valid() in uvm_hmm.h. // Locking: the va_block lock must be held. uvm_processor_id_t uvm_va_block_select_residency(uvm_va_block_t *va_block, uvm_va_block_context_t *va_block_context, uvm_page_index_t page_index, uvm_processor_id_t processor_id, NvU32 access_type_mask, - uvm_va_policy_t *policy, + const uvm_va_policy_t *policy, const uvm_perf_thrashing_hint_t *thrashing_hint, uvm_service_operation_t operation, bool *read_duplicate); diff --git a/kernel-open/nvidia-uvm/uvm_va_block_types.h b/kernel-open/nvidia-uvm/uvm_va_block_types.h index 8f5e233bb..29bdda4af 100644 --- a/kernel-open/nvidia-uvm/uvm_va_block_types.h +++ b/kernel-open/nvidia-uvm/uvm_va_block_types.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2019 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -27,6 +27,11 @@ #include "uvm_common.h" #include "uvm_pte_batch.h" #include "uvm_tlb_batch.h" +#include "uvm_forward_decl.h" + +#if UVM_IS_CONFIG_HMM() +#include +#endif // UVM_VA_BLOCK_BITS is 21, meaning the maximum block size is 2MB. Rationale: // - 2MB matches the largest Pascal GPU page size so it's a natural fit @@ -161,8 +166,12 @@ typedef struct { // Masks used internally uvm_page_mask_t page_mask; - uvm_page_mask_t copy_resident_pages_between_mask; + uvm_page_mask_t copy_resident_pages_mask; uvm_page_mask_t pages_staged; + + // This is used to store which pages were successfully copied to the + // destination processor and used by uvm_va_block_make_resident_finish() + // to update the va_block state. uvm_page_mask_t pages_migrated; // Out mask filled in by uvm_va_block_make_resident to indicate which @@ -225,13 +234,24 @@ typedef struct // the mm, such as creating CPU mappings. struct mm_struct *mm; - uvm_va_policy_t *policy; + const uvm_va_policy_t *policy; #if UVM_IS_CONFIG_HMM() struct { + // These are used for migrate_vma_*(), hmm_range_fault(), and + // make_device_exclusive_range() handling. + unsigned long src_pfns[PAGES_PER_UVM_VA_BLOCK]; + union { + unsigned long dst_pfns[PAGES_PER_UVM_VA_BLOCK]; + struct page *pages[PAGES_PER_UVM_VA_BLOCK]; + }; + // Cached VMA pointer. This is only valid while holding the mmap_lock. struct vm_area_struct *vma; + + // Used for migrate_vma_*() to migrate pages to/from GPU/CPU. + struct migrate_vma migrate_vma_args; } hmm; #endif @@ -242,8 +262,7 @@ typedef struct typedef enum { UVM_VA_BLOCK_TRANSFER_MODE_MOVE = 1, - UVM_VA_BLOCK_TRANSFER_MODE_COPY = 2, - UVM_VA_BLOCK_TRANSFER_MODE_COPY_ONLY = 3 + UVM_VA_BLOCK_TRANSFER_MODE_COPY = 2 } uvm_va_block_transfer_mode_t; struct uvm_reverse_map_struct @@ -266,4 +285,10 @@ typedef enum UVM_SERVICE_OPERATION_ACCESS_COUNTERS, } uvm_service_operation_t; +typedef enum +{ + UVM_MIGRATE_MODE_MAKE_RESIDENT, + UVM_MIGRATE_MODE_MAKE_RESIDENT_AND_MAP, +} uvm_migrate_mode_t; + #endif diff --git a/kernel-open/nvidia-uvm/uvm_va_policy.c b/kernel-open/nvidia-uvm/uvm_va_policy.c index 5efa1ca58..a55f2ec1d 100644 --- a/kernel-open/nvidia-uvm/uvm_va_policy.c +++ b/kernel-open/nvidia-uvm/uvm_va_policy.c @@ -29,23 +29,23 @@ #include "uvm_va_space.h" #include "uvm_va_range.h" -uvm_va_policy_t uvm_va_policy_default __read_mostly = { +const uvm_va_policy_t uvm_va_policy_default = { .preferred_location = UVM_ID_INVALID, .read_duplication = UVM_READ_DUPLICATION_UNSET, }; -bool uvm_va_policy_is_read_duplicate(uvm_va_policy_t *policy, uvm_va_space_t *va_space) +bool uvm_va_policy_is_read_duplicate(const uvm_va_policy_t *policy, uvm_va_space_t *va_space) { return policy->read_duplication == UVM_READ_DUPLICATION_ENABLED && uvm_va_space_can_read_duplicate(va_space, NULL); } -uvm_va_policy_t *uvm_va_policy_get(uvm_va_block_t *va_block, NvU64 addr) +const uvm_va_policy_t *uvm_va_policy_get(uvm_va_block_t *va_block, NvU64 addr) { uvm_assert_mutex_locked(&va_block->lock); if (uvm_va_block_is_hmm(va_block)) { - uvm_va_policy_node_t *node = uvm_va_policy_node_find(va_block, addr); + const uvm_va_policy_node_t *node = uvm_va_policy_node_find(va_block, addr); return node ? &node->policy : &uvm_va_policy_default; } @@ -63,14 +63,6 @@ static uvm_va_policy_node_t *uvm_va_policy_node_container(uvm_range_tree_node_t return container_of(tree_node, uvm_va_policy_node_t, node); } -static uvm_va_policy_t *uvm_va_policy_container(uvm_range_tree_node_t *tree_node) -{ - if (!tree_node) - return NULL; - - return &uvm_va_policy_node_container(tree_node)->policy; -} - NV_STATUS uvm_va_policy_init(void) { g_uvm_va_policy_node_cache = NV_KMEM_CACHE_CREATE("uvm_va_policy_node_t", uvm_va_policy_node_t); @@ -173,15 +165,15 @@ uvm_va_policy_node_t *uvm_va_policy_node_iter_next(uvm_va_block_t *va_block, return uvm_va_policy_node_container(tree_node); } -uvm_va_policy_t *uvm_va_policy_iter_first(uvm_va_block_t *va_block, - NvU64 start, - NvU64 end, - uvm_va_policy_node_t **out_node, - uvm_va_block_region_t *out_region) +const uvm_va_policy_t *uvm_va_policy_iter_first(uvm_va_block_t *va_block, + NvU64 start, + NvU64 end, + uvm_va_policy_node_t **out_node, + uvm_va_block_region_t *out_region) { uvm_range_tree_node_t *tree_node; uvm_va_policy_node_t *node; - uvm_va_policy_t *policy; + const uvm_va_policy_t *policy; uvm_va_block_region_t region; UVM_ASSERT(uvm_va_block_is_hmm(va_block)); @@ -219,11 +211,11 @@ uvm_va_policy_t *uvm_va_policy_iter_first(uvm_va_block_t *va_block, return policy; } -uvm_va_policy_t *uvm_va_policy_iter_next(uvm_va_block_t *va_block, - uvm_va_policy_t *policy, - NvU64 end, - uvm_va_policy_node_t **inout_node, - uvm_va_block_region_t *inout_region) +const uvm_va_policy_t *uvm_va_policy_iter_next(uvm_va_block_t *va_block, + const uvm_va_policy_t *policy, + NvU64 end, + uvm_va_policy_node_t **inout_node, + uvm_va_block_region_t *inout_region) { uvm_va_policy_node_t *node = *inout_node; uvm_va_policy_node_t *next; @@ -234,7 +226,7 @@ uvm_va_policy_t *uvm_va_policy_iter_next(uvm_va_block_t *va_block, next = uvm_va_policy_node_iter_next(va_block, node, end); - if (policy == &uvm_va_policy_default) { + if (uvm_va_policy_is_default(policy)) { // We haven't used the current policy node yet so use it now. next = node; policy = &node->policy; @@ -563,4 +555,39 @@ NV_STATUS uvm_va_policy_set_range(uvm_va_block_t *va_block, return NV_OK; } +const uvm_va_policy_t *uvm_va_policy_set_preferred_location(uvm_va_block_t *va_block, + uvm_va_block_region_t region, + uvm_processor_id_t processor_id, + const uvm_va_policy_t *old_policy) +{ + NvU64 start = uvm_va_block_region_start(va_block, region); + NvU64 end = uvm_va_block_region_end(va_block, region); + uvm_va_policy_node_t *node; + + if (uvm_va_policy_is_default(old_policy)) { + + UVM_ASSERT(!UVM_ID_IS_INVALID(processor_id)); + UVM_ASSERT(!uvm_range_tree_iter_first(&va_block->hmm.va_policy_tree, start, end)); + + node = uvm_va_policy_node_create(va_block, start, end); + if (!node) + return NULL; + } + else { + // Since the old_policy isn't the constant default policy, we know it + // is an allocated uvm_va_policy_node_t and can be cast. + node = container_of((uvm_va_policy_t *)old_policy, uvm_va_policy_node_t, policy); + + // The caller guarantees that the policy node doesn't require splitting + // and that the policy is changing. + UVM_ASSERT(node->node.start >= start); + UVM_ASSERT(node->node.end <= end); + UVM_ASSERT(!uvm_id_equal(node->policy.preferred_location, processor_id)); + } + + node->policy.preferred_location = processor_id; + + return &node->policy; +} + #endif // UVM_IS_CONFIG_HMM() diff --git a/kernel-open/nvidia-uvm/uvm_va_policy.h b/kernel-open/nvidia-uvm/uvm_va_policy.h index 59963c515..ab72a75e4 100644 --- a/kernel-open/nvidia-uvm/uvm_va_policy.h +++ b/kernel-open/nvidia-uvm/uvm_va_policy.h @@ -82,20 +82,26 @@ typedef struct uvm_va_policy_node_struct } uvm_va_policy_node_t; // Function pointer prototype for uvm_hmm_split_as_needed() callback. -typedef bool (*uvm_va_policy_is_split_needed_t)(uvm_va_policy_t *policy, void *data); +typedef bool (*uvm_va_policy_is_split_needed_t)(const uvm_va_policy_t *policy, void *data); // Default policy to save uvm_va_policy_node_t space in HMM va_blocks. -extern uvm_va_policy_t uvm_va_policy_default; +extern const uvm_va_policy_t uvm_va_policy_default; -bool uvm_va_policy_is_read_duplicate(uvm_va_policy_t *policy, uvm_va_space_t *va_space); +// Return true if policy is the default policy. +static bool uvm_va_policy_is_default(const uvm_va_policy_t *policy) +{ + return policy == &uvm_va_policy_default; +} + +bool uvm_va_policy_is_read_duplicate(const uvm_va_policy_t *policy, uvm_va_space_t *va_space); // Returns the uvm_va_policy_t containing addr or default policy if not found. // The va_block can be either a UVM or HMM va_block. // Locking: The va_block lock must be held. -uvm_va_policy_t *uvm_va_policy_get(uvm_va_block_t *va_block, NvU64 addr); +const uvm_va_policy_t *uvm_va_policy_get(uvm_va_block_t *va_block, NvU64 addr); // Return a uvm_va_policy_node_t given a uvm_va_policy_t pointer. -static uvm_va_policy_node_t *uvm_va_policy_node_from_policy(uvm_va_policy_t *policy) +static const uvm_va_policy_node_t *uvm_va_policy_node_from_policy(const uvm_va_policy_t *policy) { return container_of(policy, uvm_va_policy_node_t, policy); } @@ -151,6 +157,17 @@ NV_STATUS uvm_va_policy_set_range(uvm_va_block_t *va_block, uvm_processor_id_t processor_id, uvm_read_duplication_policy_t new_policy); +// This is an optimized version of uvm_va_policy_set_range() where the caller +// guarantees that the the processor_id is not the same as the existing +// policy for the given region and that the region doesn't require splitting +// the existing policy node 'old_policy'. +// Returns the updated policy or NULL if memory could not be allocated. +// Locking: The va_block lock must be held. +const uvm_va_policy_t *uvm_va_policy_set_preferred_location(uvm_va_block_t *va_block, + uvm_va_block_region_t region, + uvm_processor_id_t processor_id, + const uvm_va_policy_t *old_policy); + // Iterators for specific VA policy ranges. // Returns the first policy node in the range [start, end], if any. @@ -177,20 +194,20 @@ uvm_va_policy_node_t *uvm_va_policy_node_iter_next(uvm_va_block_t *va_block, uvm // Returns the first policy in the range [start, end], if any. // Locking: The va_block lock must be held. -uvm_va_policy_t *uvm_va_policy_iter_first(uvm_va_block_t *va_block, - NvU64 start, - NvU64 end, - uvm_va_policy_node_t **out_node, - uvm_va_block_region_t *out_region); +const uvm_va_policy_t *uvm_va_policy_iter_first(uvm_va_block_t *va_block, + NvU64 start, + NvU64 end, + uvm_va_policy_node_t **out_node, + uvm_va_block_region_t *out_region); // Returns the next VA policy following the provided policy in address order, // if that policy's start <= the provided end. // Locking: The va_block lock must be held. -uvm_va_policy_t *uvm_va_policy_iter_next(uvm_va_block_t *va_block, - uvm_va_policy_t *policy, - NvU64 end, - uvm_va_policy_node_t **inout_node, - uvm_va_block_region_t *inout_region); +const uvm_va_policy_t *uvm_va_policy_iter_next(uvm_va_block_t *va_block, + const uvm_va_policy_t *policy, + NvU64 end, + uvm_va_policy_node_t **inout_node, + uvm_va_block_region_t *inout_region); // Note that policy and region are set and usable in the loop body. // The 'node' variable is used to retain loop state and 'policy' doesn't diff --git a/kernel-open/nvidia-uvm/uvm_va_range.c b/kernel-open/nvidia-uvm/uvm_va_range.c index e89edfbf0..0f3435745 100644 --- a/kernel-open/nvidia-uvm/uvm_va_range.c +++ b/kernel-open/nvidia-uvm/uvm_va_range.c @@ -25,6 +25,7 @@ #include "uvm_linux.h" #include "uvm_types.h" #include "uvm_api.h" +#include "uvm_hal.h" #include "uvm_va_range.h" #include "uvm_va_block.h" #include "uvm_kvmalloc.h" @@ -114,7 +115,6 @@ static uvm_va_range_t *uvm_va_range_alloc(uvm_va_space_t *va_space, NvU64 start, return NULL; uvm_assert_rwsem_locked_write(&va_space->lock); - UVM_ASSERT(uvm_va_space_initialized(va_space) == NV_OK); va_range->va_space = va_space; va_range->node.start = start; @@ -466,11 +466,7 @@ static void uvm_va_range_destroy_channel(uvm_va_range_t *va_range) // Unmap the buffer if (gpu_va_space && va_range->channel.pt_range_vec.ranges) { - if (va_range->channel.aperture == UVM_APERTURE_VID) - membar = UVM_MEMBAR_GPU; - else - membar = UVM_MEMBAR_SYS; - + membar = uvm_hal_downgrade_membar_type(gpu_va_space->gpu, va_range->channel.aperture == UVM_APERTURE_VID); uvm_page_table_range_vec_clear_ptes(&va_range->channel.pt_range_vec, membar); uvm_page_table_range_vec_deinit(&va_range->channel.pt_range_vec); } @@ -1079,7 +1075,7 @@ static NV_STATUS uvm_va_range_split_blocks(uvm_va_range_t *existing, uvm_va_rang // Even if there was no block split above, there is no guarantee that one // of our blocks doesn't have the 'inject_split_error' flag set. We clear // that here to prevent multiple errors caused by one - // 'uvm_test_va_range_inject_split_error' call. + // 'uvm_test_va_range_inject_split_error' call. if (existing->inject_split_error) { UVM_ASSERT(!block); existing->inject_split_error = false; @@ -1539,6 +1535,7 @@ NV_STATUS uvm_va_range_set_preferred_location(uvm_va_range_t *va_range, for_each_va_block_in_va_range(va_range, va_block) { uvm_processor_id_t id; + uvm_va_block_region_t region = uvm_va_block_region_from_block(va_block); for_each_id_in_mask(id, &set_accessed_by_processors) { status = uvm_va_block_set_accessed_by(va_block, va_block_context, id); @@ -1551,16 +1548,22 @@ NV_STATUS uvm_va_range_set_preferred_location(uvm_va_range_t *va_range, uvm_mutex_lock(&va_block->lock); status = UVM_VA_BLOCK_RETRY_LOCKED(va_block, NULL, - uvm_va_block_set_preferred_location_locked(va_block, va_block_context)); + uvm_va_block_set_preferred_location_locked(va_block, + va_block_context, + region)); - if (out_tracker) - uvm_tracker_add_tracker_safe(out_tracker, &va_block->tracker); + if (out_tracker) { + NV_STATUS tracker_status; + + tracker_status = uvm_tracker_add_tracker_safe(out_tracker, &va_block->tracker); + if (status == NV_OK) + status = tracker_status; + } uvm_mutex_unlock(&va_block->lock); if (status != NV_OK) return status; - } // And lastly map all of the current UVM-Lite GPUs to the resident pages on diff --git a/kernel-open/nvidia-uvm/uvm_va_space.c b/kernel-open/nvidia-uvm/uvm_va_space.c index ce1681d83..c9a43056e 100644 --- a/kernel-open/nvidia-uvm/uvm_va_space.c +++ b/kernel-open/nvidia-uvm/uvm_va_space.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -160,15 +160,21 @@ static bool va_space_check_processors_masks(uvm_va_space_t *va_space) return true; } -NV_STATUS uvm_va_space_create(struct inode *inode, struct file *filp) +NV_STATUS uvm_va_space_create(struct address_space *mapping, uvm_va_space_t **va_space_ptr, NvU64 flags) { NV_STATUS status; uvm_va_space_t *va_space = uvm_kvmalloc_zero(sizeof(*va_space)); uvm_gpu_id_t gpu_id; + *va_space_ptr = NULL; if (!va_space) return NV_ERR_NO_MEMORY; + if (flags & ~UVM_INIT_FLAGS_MASK) { + uvm_kvfree(va_space); + return NV_ERR_INVALID_ARGUMENT; + } + uvm_init_rwsem(&va_space->lock, UVM_LOCK_ORDER_VA_SPACE); uvm_mutex_init(&va_space->serialize_writers_lock, UVM_LOCK_ORDER_VA_SPACE_SERIALIZE_WRITERS); uvm_mutex_init(&va_space->read_acquire_write_release_lock, @@ -177,29 +183,6 @@ NV_STATUS uvm_va_space_create(struct inode *inode, struct file *filp) uvm_range_tree_init(&va_space->va_range_tree); uvm_ats_init_va_space(va_space); - // By default all struct files on the same inode share the same - // address_space structure (the inode's) across all processes. This means - // unmap_mapping_range would unmap virtual mappings across all processes on - // that inode. - // - // Since the UVM driver uses the mapping offset as the VA of the file's - // process, we need to isolate the mappings to each process. - address_space_init_once(&va_space->mapping); - va_space->mapping.host = inode; - - // Some paths in the kernel, for example force_page_cache_readahead which - // can be invoked from user-space via madvise MADV_WILLNEED and fadvise - // POSIX_FADV_WILLNEED, check the function pointers within - // file->f_mapping->a_ops for validity. However, those paths assume that a_ops - // itself is always valid. Handle that by using the inode's a_ops pointer, - // which is what f_mapping->a_ops would point to anyway if we weren't re- - // assigning f_mapping. - va_space->mapping.a_ops = inode->i_mapping->a_ops; - -#if defined(NV_ADDRESS_SPACE_HAS_BACKING_DEV_INFO) - va_space->mapping.backing_dev_info = inode->i_mapping->backing_dev_info; -#endif - // Init to 0 since we rely on atomic_inc_return behavior to return 1 as the first ID atomic64_set(&va_space->range_group_id_counter, 0); @@ -231,13 +214,12 @@ NV_STATUS uvm_va_space_create(struct inode *inode, struct file *filp) init_waitqueue_head(&va_space->va_space_mm.last_retainer_wait_queue); init_waitqueue_head(&va_space->gpu_va_space_deferred_free.wait_queue); - filp->private_data = va_space; - filp->f_mapping = &va_space->mapping; - + va_space->mapping = mapping; va_space->test.page_prefetch_enabled = true; init_tools_data(va_space); + uvm_down_write_mmap_lock(current->mm); uvm_va_space_down_write(va_space); status = uvm_perf_init_va_space_events(va_space, &va_space->perf_events); @@ -254,18 +236,35 @@ NV_STATUS uvm_va_space_create(struct inode *inode, struct file *filp) UVM_ASSERT(va_space_check_processors_masks(va_space)); + va_space->initialization_flags = flags; + + status = uvm_va_space_mm_register(va_space); + if (status != NV_OK) + goto fail; + + status = uvm_hmm_va_space_initialize(va_space); + if (status != NV_OK) + goto fail; + uvm_va_space_up_write(va_space); + uvm_up_write_mmap_lock(current->mm); uvm_mutex_lock(&g_uvm_global.va_spaces.lock); list_add_tail(&va_space->list_node, &g_uvm_global.va_spaces.list); uvm_mutex_unlock(&g_uvm_global.va_spaces.lock); + *va_space_ptr = va_space; + return NV_OK; fail: uvm_perf_heuristics_unload(va_space); uvm_perf_destroy_va_space_events(&va_space->perf_events); uvm_va_space_up_write(va_space); + uvm_up_write_mmap_lock(current->mm); + // See the comment in uvm_va_space_mm_unregister() for why this has to be + // called after releasing the locks. + uvm_va_space_mm_unregister(va_space); uvm_kvfree(va_space); @@ -296,6 +295,8 @@ static void unregister_gpu(uvm_va_space_t *va_space, uvm_for_each_va_range(va_range, va_space) uvm_va_range_unregister_gpu(va_range, gpu, mm, deferred_free_list); + uvm_hmm_unregister_gpu(va_space, gpu, mm); + // If this GPU has any peer-to-peer pair that was explicitly enabled, but // not explicitly disabled, disable it. // Notably do this only after unregistering the GPU from VA ranges to make @@ -560,55 +561,10 @@ void uvm_va_space_destroy(uvm_va_space_t *va_space) uvm_mutex_unlock(&g_uvm_global.global_lock); + uvm_kvfree(va_space->mapping); uvm_kvfree(va_space); } -NV_STATUS uvm_va_space_initialize(uvm_va_space_t *va_space, NvU64 flags) -{ - NV_STATUS status = NV_OK; - - if (flags & ~UVM_INIT_FLAGS_MASK) - return NV_ERR_INVALID_ARGUMENT; - - uvm_down_write_mmap_lock(current->mm); - uvm_va_space_down_write(va_space); - - if (atomic_read(&va_space->initialized)) { - // Already initialized - check if parameters match - if (flags != va_space->initialization_flags) - status = NV_ERR_INVALID_ARGUMENT; - } - else { - va_space->initialization_flags = flags; - - status = uvm_va_space_mm_register(va_space); - if (status != NV_OK) - goto out; - - status = uvm_hmm_va_space_initialize(va_space); - if (status != NV_OK) - goto unreg; - - // Use release semantics to match the acquire semantics in - // uvm_va_space_initialized. See that function for details. All - // initialization must be complete by this point. - atomic_set_release(&va_space->initialized, 1); - } - -out: - uvm_va_space_up_write(va_space); - uvm_up_write_mmap_lock(current->mm); - return status; - -unreg: - uvm_va_space_up_write(va_space); - uvm_up_write_mmap_lock(current->mm); - // See the comment in uvm_va_space_mm_unregister() for why this has to be - // called after releasing the locks. - uvm_va_space_mm_unregister(va_space); - return status; -} - void uvm_va_space_stop_all_user_channels(uvm_va_space_t *va_space) { uvm_gpu_va_space_t *gpu_va_space; @@ -700,6 +656,7 @@ NV_STATUS uvm_va_space_register_gpu(uvm_va_space_t *va_space, uvm_va_range_t *va_range; uvm_gpu_t *gpu; uvm_gpu_t *other_gpu; + bool gpu_can_access_sysmem = true; status = uvm_gpu_retain_by_uuid(gpu_uuid, user_rm_device, &gpu); if (status != NV_OK) @@ -756,7 +713,6 @@ NV_STATUS uvm_va_space_register_gpu(uvm_va_space_t *va_space, // All GPUs have native atomics on their own memory processor_mask_array_set(va_space->has_native_atomics, gpu->id, gpu->id); - // TODO: Bug 3252572: Support the new link type UVM_GPU_LINK_C2C if (gpu->parent->sysmem_link >= UVM_GPU_LINK_NVLINK_1) { processor_mask_array_set(va_space->has_nvlink, gpu->id, UVM_ID_CPU); processor_mask_array_set(va_space->has_nvlink, UVM_ID_CPU, gpu->id); @@ -776,8 +732,7 @@ NV_STATUS uvm_va_space_register_gpu(uvm_va_space_t *va_space, processor_mask_array_set(va_space->can_access, gpu->id, gpu->id); processor_mask_array_set(va_space->accessible_from, gpu->id, gpu->id); - // All GPUs have direct access to sysmem, unless we're in SEV mode - if (!g_uvm_global.sev_enabled) { + if (gpu_can_access_sysmem) { processor_mask_array_set(va_space->can_access, gpu->id, UVM_ID_CPU); processor_mask_array_set(va_space->accessible_from, UVM_ID_CPU, gpu->id); } @@ -1558,6 +1513,8 @@ static void remove_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space, uvm_for_each_va_range_safe(va_range, va_range_next, va_space) uvm_va_range_remove_gpu_va_space(va_range, gpu_va_space, mm, deferred_free_list); + uvm_hmm_remove_gpu_va_space(va_space, gpu_va_space, mm); + uvm_deferred_free_object_add(deferred_free_list, &gpu_va_space->deferred_free, UVM_DEFERRED_FREE_OBJECT_GPU_VA_SPACE); @@ -1567,6 +1524,7 @@ static void remove_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space, atomic_inc(&va_space->gpu_va_space_deferred_free.num_pending); uvm_processor_mask_clear(&va_space->registered_gpu_va_spaces, gpu_va_space->gpu->id); + uvm_processor_mask_clear_atomic(&va_space->needs_fault_buffer_flush, gpu_va_space->gpu->id); va_space->gpu_va_spaces[uvm_id_gpu_index(gpu_va_space->gpu->id)] = NULL; gpu_va_space->state = UVM_GPU_VA_SPACE_STATE_DEAD; } @@ -1840,8 +1798,6 @@ error: bool uvm_va_space_pageable_mem_access_supported(uvm_va_space_t *va_space) { - UVM_ASSERT(uvm_va_space_initialized(va_space) == NV_OK); - // Any pageable memory access requires that we have mm_struct association // via va_space_mm. if (!uvm_va_space_mm_enabled(va_space)) @@ -2243,7 +2199,12 @@ static vm_fault_t uvm_va_space_cpu_fault(uvm_va_space_t *va_space, if (do_sleep) uvm_tools_record_throttling_end(va_space, fault_addr, UVM_ID_CPU); - if (!is_hmm) { + if (is_hmm) { + status = uvm_hmm_va_block_cpu_find(va_space, service_context, vmf, &va_block); + if (status != NV_OK) + break; + } + else { status = uvm_va_block_find_create_managed(va_space, fault_addr, &va_block); if (status != NV_OK) { UVM_ASSERT_MSG(status == NV_ERR_NO_MEMORY, "status: %s\n", nvstatusToString(status)); @@ -2256,6 +2217,9 @@ static vm_fault_t uvm_va_space_cpu_fault(uvm_va_space_t *va_space, // Loop until thrashing goes away. status = uvm_va_block_cpu_fault(va_block, fault_addr, is_write, service_context); + + if (is_hmm) + uvm_hmm_cpu_fault_finish(service_context); } while (status == NV_WARN_MORE_PROCESSING_REQUIRED); if (status != NV_OK) { @@ -2318,3 +2282,10 @@ vm_fault_t uvm_va_space_cpu_fault_managed(uvm_va_space_t *va_space, return uvm_va_space_cpu_fault(va_space, vma, vmf, false); } + +vm_fault_t uvm_va_space_cpu_fault_hmm(uvm_va_space_t *va_space, + struct vm_area_struct *vma, + struct vm_fault *vmf) +{ + return uvm_va_space_cpu_fault(va_space, vma, vmf, true); +} diff --git a/kernel-open/nvidia-uvm/uvm_va_space.h b/kernel-open/nvidia-uvm/uvm_va_space.h index 20f94e207..fe39dbeb5 100644 --- a/kernel-open/nvidia-uvm/uvm_va_space.h +++ b/kernel-open/nvidia-uvm/uvm_va_space.h @@ -124,16 +124,6 @@ struct uvm_gpu_va_space_struct // because multiple threads may set it to 1 concurrently. atomic_t disallow_new_channels; - // On VMA destruction, the fault buffer needs to be flushed for all the GPUs - // registered in the VA space to avoid leaving stale entries of the VA range - // that is going to be destroyed. Otherwise, these fault entries can be - // attributed to new VA ranges reallocated at the same addresses. However, - // uvm_vm_close is called with mm->mmap_lock taken and we cannot take the ISR - // lock. Therefore, we use a flag no notify the GPU fault handler that the - // fault buffer needs to be flushed, before servicing the faults that belong - // to the va_space. - bool needs_fault_buffer_flush; - // Node for the deferred free list where this GPU VA space is stored upon // being unregistered. uvm_deferred_free_object_t deferred_free; @@ -189,7 +179,7 @@ struct uvm_va_space_struct // Kernel mapping structure passed to unmap_mapping range to unmap CPU PTEs // in this process. - struct address_space mapping; + struct address_space *mapping; // Storage in g_uvm_global.va_spaces.list struct list_head list_node; @@ -262,6 +252,17 @@ struct uvm_va_space_struct // corrupting state. uvm_processor_mask_t gpu_unregister_in_progress; + // On VMA destruction, the fault buffer needs to be flushed for all the GPUs + // registered in the VA space to avoid leaving stale entries of the VA range + // that is going to be destroyed. Otherwise, these fault entries can be + // attributed to new VA ranges reallocated at the same addresses. However, + // uvm_vm_close is called with mm->mmap_lock taken and we cannot take the + // ISR lock. Therefore, we use a flag to notify the GPU fault handler that + // the fault buffer needs to be flushed, before servicing the faults that + // belong to the va_space. The bits are set and cleared atomically so no + // va_space lock is required. + uvm_processor_mask_t needs_fault_buffer_flush; + // Mask of processors that are participating in system-wide atomics uvm_processor_mask_t system_wide_atomics_enabled_processors; @@ -330,10 +331,6 @@ struct uvm_va_space_struct // lock is held in write mode. Access using uvm_va_space_block_context(). uvm_va_block_context_t va_block_context; - // UVM_INITIALIZE has been called. Until this is set, the VA space is - // inoperable. Use uvm_va_space_initialized() to check whether the VA space - // has been initialized. - atomic_t initialized; NvU64 initialization_flags; // The mm currently associated with this VA space, if any. @@ -409,34 +406,7 @@ static bool uvm_va_space_processor_has_memory(uvm_va_space_t *va_space, uvm_proc return uvm_va_space_get_gpu(va_space, id)->mem_info.size > 0; } -// Checks if the VA space has been fully initialized (UVM_INITIALIZE has been -// called). Returns NV_OK if so, NV_ERR_ILLEGAL_ACTION otherwise. -// -// Locking: No requirements. The VA space lock does NOT need to be held when -// calling this function, though it is allowed. -static NV_STATUS uvm_va_space_initialized(uvm_va_space_t *va_space) -{ - // The common case by far is for the VA space to have already been - // initialized. This combined with the fact that some callers may never hold - // the VA space lock means we don't want the VA space lock to be taken to - // perform this check. - // - // Instead of locks, we rely on acquire/release memory ordering semantics. - // The release is done at the end of uvm_api_initialize() when the - // UVM_INITIALIZE ioctl completes. That opens the gate for any other - // threads. - // - // Using acquire semantics as opposed to a normal read will add slight - // overhead to every entry point on platforms with relaxed ordering. Should - // that overhead become noticeable we could have UVM_INITIALIZE use - // on_each_cpu to broadcast memory barriers. - if (likely(atomic_read_acquire(&va_space->initialized))) - return NV_OK; - - return NV_ERR_ILLEGAL_ACTION; -} - -NV_STATUS uvm_va_space_create(struct inode *inode, struct file *filp); +NV_STATUS uvm_va_space_create(struct address_space *mapping, uvm_va_space_t **va_space_ptr, NvU64 flags); void uvm_va_space_destroy(uvm_va_space_t *va_space); // All VA space locking should be done with these wrappers. They're macros so @@ -497,10 +467,6 @@ void uvm_va_space_destroy(uvm_va_space_t *va_space); uvm_mutex_unlock(&(__va_space)->serialize_writers_lock); \ } while (0) -// Initialize the VA space with the user-provided flags, enabling ioctls and -// mmap. -NV_STATUS uvm_va_space_initialize(uvm_va_space_t *va_space, NvU64 flags); - // Get a registered gpu by uuid. This restricts the search for GPUs, to those that // have been registered with a va_space. This returns NULL if the GPU is not present, or not // registered with the va_space. @@ -571,12 +537,30 @@ void uvm_va_space_detach_all_user_channels(uvm_va_space_t *va_space, struct list // VA space. Both GPUs must be registered in the VA space. bool uvm_va_space_peer_enabled(uvm_va_space_t *va_space, uvm_gpu_t *gpu1, uvm_gpu_t *gpu2); +// Returns the va_space this file points to. Returns NULL if this file +// does not point to a va_space. +static uvm_va_space_t *uvm_fd_va_space(struct file *filp) +{ + uvm_va_space_t *va_space; + uvm_fd_type_t type; + + type = uvm_fd_type(filp, (void **) &va_space); + if (type != UVM_FD_VA_SPACE) + return NULL; + + return va_space; +} + static uvm_va_space_t *uvm_va_space_get(struct file *filp) { - UVM_ASSERT(uvm_file_is_nvidia_uvm(filp)); - UVM_ASSERT_MSG(filp->private_data != NULL, "filp: 0x%llx", (NvU64)filp); + uvm_fd_type_t fd_type; + uvm_va_space_t *va_space; - return (uvm_va_space_t *)filp->private_data; + fd_type = uvm_fd_type(filp, (void **)&va_space); + UVM_ASSERT(uvm_file_is_nvidia_uvm(filp)); + UVM_ASSERT_MSG(fd_type == UVM_FD_VA_SPACE, "filp: 0x%llx", (NvU64)filp); + + return va_space; } static uvm_va_block_context_t *uvm_va_space_block_context(uvm_va_space_t *va_space, struct mm_struct *mm) @@ -868,4 +852,20 @@ vm_fault_t uvm_va_space_cpu_fault_managed(uvm_va_space_t *va_space, struct vm_area_struct *vma, struct vm_fault *vmf); +// Handle a CPU fault in the given VA space for a HMM allocation, +// performing any operations necessary to establish a coherent CPU mapping +// (migrations, cache invalidates, etc.). +// +// Locking: +// - vma->vm_mm->mmap_lock must be held in at least read mode. Note, that +// might not be the same as current->mm->mmap_lock. +// Returns: +// VM_FAULT_NOPAGE: if page was faulted in OK +// (possibly or'ed with VM_FAULT_MAJOR if a migration was needed). +// VM_FAULT_OOM: if system memory wasn't available. +// VM_FAULT_SIGBUS: if a CPU mapping to fault_addr cannot be accessed. +vm_fault_t uvm_va_space_cpu_fault_hmm(uvm_va_space_t *va_space, + struct vm_area_struct *vma, + struct vm_fault *vmf); + #endif // __UVM_VA_SPACE_H__ diff --git a/kernel-open/nvidia-uvm/uvm_va_space_mm.c b/kernel-open/nvidia-uvm/uvm_va_space_mm.c index cca3d5143..5d038d55c 100644 --- a/kernel-open/nvidia-uvm/uvm_va_space_mm.c +++ b/kernel-open/nvidia-uvm/uvm_va_space_mm.c @@ -303,7 +303,6 @@ NV_STATUS uvm_va_space_mm_register(uvm_va_space_t *va_space) uvm_assert_mmap_lock_locked_write(current->mm); uvm_assert_rwsem_locked_write(&va_space->lock); - UVM_ASSERT(uvm_va_space_initialized(va_space) != NV_OK); if (!uvm_va_space_mm_enabled(va_space)) return NV_OK; @@ -357,8 +356,6 @@ struct mm_struct *uvm_va_space_mm_retain(uvm_va_space_t *va_space) uvm_va_space_mm_t *va_space_mm = &va_space->va_space_mm; struct mm_struct *mm = NULL; - UVM_ASSERT(uvm_va_space_initialized(va_space) == NV_OK); - if (!uvm_va_space_mm_enabled(va_space)) return NULL; @@ -382,8 +379,6 @@ struct mm_struct *uvm_va_space_mm_or_current_retain(uvm_va_space_t *va_space) // We should only attempt to use current->mm from a user thread UVM_ASSERT(!(current->flags & PF_KTHREAD)); - UVM_ASSERT(uvm_va_space_initialized(va_space) == NV_OK); - // current->mm is NULL when we're in process teardown. In that case it // doesn't make sense to use any mm. if (!current->mm) @@ -646,7 +641,7 @@ NV_STATUS uvm_test_va_space_mm_retain(UVM_TEST_VA_SPACE_MM_RETAIN_PARAMS *params uvm_mutex_lock(&g_uvm_global.va_spaces.lock); list_for_each_entry(va_space, &g_uvm_global.va_spaces.list, list_node) { - if ((uintptr_t)va_space == params->va_space_ptr && uvm_va_space_initialized(va_space) == NV_OK) { + if ((uintptr_t)va_space == params->va_space_ptr) { mm = uvm_va_space_mm_retain(va_space); break; } diff --git a/kernel-open/nvidia-uvm/uvm_volta_ce.c b/kernel-open/nvidia-uvm/uvm_volta_ce.c new file mode 100644 index 000000000..6fad6a7f5 --- /dev/null +++ b/kernel-open/nvidia-uvm/uvm_volta_ce.c @@ -0,0 +1,278 @@ +/******************************************************************************* + Copyright (c) 2022 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "uvm_hal.h" +#include "uvm_push.h" +#include "clc3b5.h" + +// Return the flush type and the flush enablement. +static NvU32 volta_get_flush_value(uvm_push_t *push) +{ + NvU32 flush_value; + uvm_membar_t membar = uvm_push_get_and_reset_membar_flag(push); + + if (membar == UVM_MEMBAR_NONE) { + // No MEMBAR requested, don't use a flush. + flush_value = HWCONST(C3B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE); + } + else { + flush_value = HWCONST(C3B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE); + + if (membar == UVM_MEMBAR_GPU) + flush_value |= HWCONST(C3B5, LAUNCH_DMA, FLUSH_TYPE, GL); + else + flush_value |= HWCONST(C3B5, LAUNCH_DMA, FLUSH_TYPE, SYS); + } + + return flush_value; +} + +void uvm_hal_volta_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload) +{ + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + NvU32 launch_dma_plc_mode; + + NV_PUSH_3U(C3B5, SET_SEMAPHORE_A, HWVALUE(C3B5, SET_SEMAPHORE_A, UPPER, NvOffset_HI32(gpu_va)), + SET_SEMAPHORE_B, HWVALUE(C3B5, SET_SEMAPHORE_B, LOWER, NvOffset_LO32(gpu_va)), + SET_SEMAPHORE_PAYLOAD, payload); + + launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode(); + + NV_PUSH_1U(C3B5, LAUNCH_DMA, volta_get_flush_value(push) | + HWCONST(C3B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NONE) | + HWCONST(C3B5, LAUNCH_DMA, SEMAPHORE_TYPE, RELEASE_ONE_WORD_SEMAPHORE) | + launch_dma_plc_mode); +} + +void uvm_hal_volta_ce_semaphore_reduction_inc(uvm_push_t *push, NvU64 gpu_va, NvU32 payload) +{ + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + NvU32 launch_dma_plc_mode; + + NV_PUSH_3U(C3B5, SET_SEMAPHORE_A, HWVALUE(C3B5, SET_SEMAPHORE_A, UPPER, NvOffset_HI32(gpu_va)), + SET_SEMAPHORE_B, HWVALUE(C3B5, SET_SEMAPHORE_B, LOWER, NvOffset_LO32(gpu_va)), + SET_SEMAPHORE_PAYLOAD, payload); + + launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode(); + + NV_PUSH_1U(C3B5, LAUNCH_DMA, volta_get_flush_value(push) | + HWCONST(C3B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NONE) | + HWCONST(C3B5, LAUNCH_DMA, SEMAPHORE_TYPE, RELEASE_ONE_WORD_SEMAPHORE) | + HWCONST(C3B5, LAUNCH_DMA, SEMAPHORE_REDUCTION, INC) | + HWCONST(C3B5, LAUNCH_DMA, SEMAPHORE_REDUCTION_SIGN, UNSIGNED) | + HWCONST(C3B5, LAUNCH_DMA, SEMAPHORE_REDUCTION_ENABLE, TRUE) | + launch_dma_plc_mode); +} + +void uvm_hal_volta_ce_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va) +{ + uvm_gpu_t *gpu; + NvU32 launch_dma_plc_mode; + + NV_PUSH_3U(C3B5, SET_SEMAPHORE_A, HWVALUE(C3B5, SET_SEMAPHORE_A, UPPER, NvOffset_HI32(gpu_va)), + SET_SEMAPHORE_B, HWVALUE(C3B5, SET_SEMAPHORE_B, LOWER, NvOffset_LO32(gpu_va)), + SET_SEMAPHORE_PAYLOAD, 0xdeadbeef); + + gpu = uvm_push_get_gpu(push); + launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode(); + + NV_PUSH_1U(C3B5, LAUNCH_DMA, volta_get_flush_value(push) | + HWCONST(C3B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NONE) | + HWCONST(C3B5, LAUNCH_DMA, SEMAPHORE_TYPE, RELEASE_FOUR_WORD_SEMAPHORE) | + launch_dma_plc_mode); +} + +void uvm_hal_volta_ce_memcopy(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src, size_t size) +{ + // If >4GB copies ever become an important use case, this function should + // use multi-line transfers so we don't have to iterate (bug 1766588). + static const size_t max_single_copy_size = 0xFFFFFFFF; + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + + NvU32 pipelined_value; + NvU32 launch_dma_src_dst_type; + NvU32 launch_dma_plc_mode; + NvU32 flush_value = HWCONST(C3B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE); + + UVM_ASSERT_MSG(gpu->parent->ce_hal->memcopy_is_valid(push, dst, src), + "Memcopy validation failed in channel %s, GPU %s.\n", + push->channel->name, + uvm_gpu_name(gpu)); + + gpu->parent->ce_hal->memcopy_patch_src(push, &src); + + launch_dma_src_dst_type = gpu->parent->ce_hal->phys_mode(push, dst, src); + launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode(); + + if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED)) + pipelined_value = HWCONST(C3B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, PIPELINED); + else + pipelined_value = HWCONST(C3B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED); + + do { + NvU32 copy_this_time = (NvU32)min(size, max_single_copy_size); + + // In the last operation, a flush/membar may be issued after the copy. + if (size == copy_this_time) + flush_value = volta_get_flush_value(push); + + gpu->parent->ce_hal->offset_in_out(push, src.address, dst.address); + + NV_PUSH_1U(C3B5, LINE_LENGTH_IN, copy_this_time); + + NV_PUSH_1U(C3B5, LAUNCH_DMA, + HWCONST(C3B5, LAUNCH_DMA, SRC_MEMORY_LAYOUT, PITCH) | + HWCONST(C3B5, LAUNCH_DMA, DST_MEMORY_LAYOUT, PITCH) | + HWCONST(C3B5, LAUNCH_DMA, MULTI_LINE_ENABLE, FALSE) | + HWCONST(C3B5, LAUNCH_DMA, REMAP_ENABLE, FALSE) | + flush_value | + launch_dma_src_dst_type | + launch_dma_plc_mode | + pipelined_value); + + pipelined_value = HWCONST(C3B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, PIPELINED); + dst.address += copy_this_time; + src.address += copy_this_time; + size -= copy_this_time; + } while (size > 0); +} + +static NvU32 ce_aperture(uvm_aperture_t aperture) +{ + BUILD_BUG_ON(HWCONST(C3B5, SET_SRC_PHYS_MODE, TARGET, LOCAL_FB) != + HWCONST(C3B5, SET_DST_PHYS_MODE, TARGET, LOCAL_FB)); + BUILD_BUG_ON(HWCONST(C3B5, SET_SRC_PHYS_MODE, TARGET, COHERENT_SYSMEM) != + HWCONST(C3B5, SET_DST_PHYS_MODE, TARGET, COHERENT_SYSMEM)); + + UVM_ASSERT_MSG(aperture == UVM_APERTURE_VID || aperture == UVM_APERTURE_SYS, "aperture 0x%x\n", aperture); + + if (aperture == UVM_APERTURE_SYS) + return HWCONST(C3B5, SET_SRC_PHYS_MODE, TARGET, COHERENT_SYSMEM); + else + return HWCONST(C3B5, SET_SRC_PHYS_MODE, TARGET, LOCAL_FB); +} + +static NvU32 volta_memset_push_phys_mode(uvm_push_t *push, uvm_gpu_address_t dst) +{ + if (dst.is_virtual) + return HWCONST(C3B5, LAUNCH_DMA, DST_TYPE, VIRTUAL); + + NV_PUSH_1U(C3B5, SET_DST_PHYS_MODE, ce_aperture(dst.aperture)); + return HWCONST(C3B5, LAUNCH_DMA, DST_TYPE, PHYSICAL); +} + +static void memset_common(uvm_push_t *push, uvm_gpu_address_t dst, size_t size, size_t memset_element_size) +{ + // If >4GB memsets ever become an important use case, this function should + // use multi-line transfers so we don't have to iterate (bug 1766588). + static const size_t max_single_memset_size = 0xFFFFFFFF; + + uvm_gpu_t *gpu = uvm_push_get_gpu(push); + NvU32 pipelined_value; + NvU32 launch_dma_dst_type; + NvU32 launch_dma_plc_mode; + NvU32 flush_value = HWCONST(C3B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE); + + UVM_ASSERT_MSG(gpu->parent->ce_hal->memset_is_valid(push, dst, memset_element_size), + "Memset validation failed in channel %s, GPU %s.\n", + push->channel->name, + uvm_gpu_name(gpu)); + + launch_dma_dst_type = volta_memset_push_phys_mode(push, dst); + launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode(); + + if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED)) + pipelined_value = HWCONST(C3B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, PIPELINED); + else + pipelined_value = HWCONST(C3B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED); + + do { + NvU32 memset_this_time = (NvU32)min(size, max_single_memset_size); + + // In the last operation, a flush/membar may be issue after the memset. + if (size == memset_this_time) + flush_value = volta_get_flush_value(push); + + gpu->parent->ce_hal->offset_out(push, dst.address); + + NV_PUSH_1U(C3B5, LINE_LENGTH_IN, memset_this_time); + + NV_PUSH_1U(C3B5, LAUNCH_DMA, + HWCONST(C3B5, LAUNCH_DMA, SRC_MEMORY_LAYOUT, PITCH) | + HWCONST(C3B5, LAUNCH_DMA, DST_MEMORY_LAYOUT, PITCH) | + HWCONST(C3B5, LAUNCH_DMA, MULTI_LINE_ENABLE, FALSE) | + HWCONST(C3B5, LAUNCH_DMA, REMAP_ENABLE, TRUE) | + flush_value | + launch_dma_dst_type | + launch_dma_plc_mode | + pipelined_value); + + dst.address += memset_this_time * memset_element_size; + size -= memset_this_time; + pipelined_value = HWCONST(C3B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED); + } while (size > 0); +} + +void uvm_hal_volta_ce_memset_1(uvm_push_t *push, uvm_gpu_address_t dst, NvU8 value, size_t size) +{ + NV_PUSH_2U(C3B5, SET_REMAP_CONST_B, (NvU32)value, + SET_REMAP_COMPONENTS, + HWCONST(C3B5, SET_REMAP_COMPONENTS, DST_X, CONST_B) | + HWCONST(C3B5, SET_REMAP_COMPONENTS, COMPONENT_SIZE, ONE) | + HWCONST(C3B5, SET_REMAP_COMPONENTS, NUM_DST_COMPONENTS, ONE)); + + memset_common(push, dst, size, 1); +} + +void uvm_hal_volta_ce_memset_4(uvm_push_t *push, uvm_gpu_address_t dst, NvU32 value, size_t size) +{ + UVM_ASSERT_MSG(size % 4 == 0, "size: %zd\n", size); + + size /= 4; + + NV_PUSH_2U(C3B5, SET_REMAP_CONST_B, value, + SET_REMAP_COMPONENTS, + HWCONST(C3B5, SET_REMAP_COMPONENTS, DST_X, CONST_B) | + HWCONST(C3B5, SET_REMAP_COMPONENTS, COMPONENT_SIZE, FOUR) | + HWCONST(C3B5, SET_REMAP_COMPONENTS, NUM_DST_COMPONENTS, ONE)); + + memset_common(push, dst, size, 4); +} + +void uvm_hal_volta_ce_memset_8(uvm_push_t *push, uvm_gpu_address_t dst, NvU64 value, size_t size) +{ + UVM_ASSERT_MSG(size % 8 == 0, "size: %zd\n", size); + + size /= 8; + + NV_PUSH_3U(C3B5, SET_REMAP_CONST_A, (NvU32)value, + SET_REMAP_CONST_B, (NvU32)(value >> 32), + SET_REMAP_COMPONENTS, + HWCONST(C3B5, SET_REMAP_COMPONENTS, DST_X, CONST_A) | + HWCONST(C3B5, SET_REMAP_COMPONENTS, DST_Y, CONST_B) | + HWCONST(C3B5, SET_REMAP_COMPONENTS, COMPONENT_SIZE, FOUR) | + HWCONST(C3B5, SET_REMAP_COMPONENTS, NUM_DST_COMPONENTS, TWO)); + + memset_common(push, dst, size, 8); +} + diff --git a/kernel-open/nvidia/export_nvswitch.h b/kernel-open/nvidia/export_nvswitch.h index 86b38ecfc..1ea393bd8 100644 --- a/kernel-open/nvidia/export_nvswitch.h +++ b/kernel-open/nvidia/export_nvswitch.h @@ -899,7 +899,6 @@ nvswitch_os_vsnprintf void nvswitch_os_assert_log ( - int cond, const char *pFormat, ... ); diff --git a/kernel-open/nvidia/linux_nvswitch.c b/kernel-open/nvidia/linux_nvswitch.c index 8e5cb3c4f..e7a5b8ec7 100644 --- a/kernel-open/nvidia/linux_nvswitch.c +++ b/kernel-open/nvidia/linux_nvswitch.c @@ -2509,26 +2509,22 @@ nvswitch_os_vsnprintf void nvswitch_os_assert_log ( - int cond, const char *fmt, ... ) { - if(cond == 0x0) + if (printk_ratelimit()) { - if (printk_ratelimit()) - { - va_list arglist; - char fmt_printk[NVSWITCH_LOG_BUFFER_SIZE]; + va_list arglist; + char fmt_printk[NVSWITCH_LOG_BUFFER_SIZE]; - va_start(arglist, fmt); - vsnprintf(fmt_printk, sizeof(fmt_printk), fmt, arglist); - va_end(arglist); - nvswitch_os_print(NVSWITCH_DBG_LEVEL_ERROR, fmt_printk); - WARN_ON(1); - } - dbg_breakpoint(); - } + va_start(arglist, fmt); + vsnprintf(fmt_printk, sizeof(fmt_printk), fmt, arglist); + va_end(arglist); + nvswitch_os_print(NVSWITCH_DBG_LEVEL_ERROR, fmt_printk); + WARN_ON(1); + } + dbg_breakpoint(); } /* diff --git a/kernel-open/nvidia/linux_nvswitch.h b/kernel-open/nvidia/linux_nvswitch.h index 14b1fa8da..b86bbacb7 100644 --- a/kernel-open/nvidia/linux_nvswitch.h +++ b/kernel-open/nvidia/linux_nvswitch.h @@ -37,8 +37,12 @@ #define NVSWITCH_IRQ_PIN 3 #define NVSWITCH_OS_ASSERT(_cond) \ - nvswitch_os_assert_log((_cond), "NVSwitch: Assertion failed in %s() at %s:%d\n", \ - __FUNCTION__ , __FILE__, __LINE__) + do { \ + if (!(_cond)) { \ + nvswitch_os_assert_log("NVSwitch: Assertion failed in %s() at %s:%d\n", \ + __FUNCTION__ , __FILE__, __LINE__); \ + } \ + } while(0) #define NVSWITCH_KMALLOC_LIMIT (128 * 1024) diff --git a/kernel-open/nvidia/nv-acpi.c b/kernel-open/nvidia/nv-acpi.c index 7db9db1d2..4ef0c2281 100644 --- a/kernel-open/nvidia/nv-acpi.c +++ b/kernel-open/nvidia/nv-acpi.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -36,6 +36,7 @@ static NV_STATUS nv_acpi_extract_package (const union acpi_object *, void *, N static NV_STATUS nv_acpi_extract_object (const union acpi_object *, void *, NvU32, NvU32 *); static void nv_acpi_powersource_hotplug_event(acpi_handle, u32, void *); +static void nv_acpi_nvpcf_event (acpi_handle, u32, void *); static acpi_status nv_acpi_find_methods (acpi_handle, u32, void *, void **); static NV_STATUS nv_acpi_nvif_method (NvU32, NvU32, void *, NvU16, NvU32 *, void *, NvU16 *); @@ -65,6 +66,13 @@ static NvBool battery_present = NV_FALSE; #define ACPI_VIDEO_CLASS "video" #endif +// Used for NVPCF event handling +static acpi_handle nvpcf_handle = NULL; +static acpi_handle nvpcf_device_handle = NULL; +static nv_acpi_t *nvpcf_nv_acpi_object = NULL; + +#define ACPI_NVPCF_EVENT_CHANGE 0xC0 + static int nv_acpi_get_device_handle(nv_state_t *nv, acpi_handle *dev_handle) { nv_linux_state_t *nvl = NV_GET_NVL_FROM_NV_STATE(nv); @@ -80,51 +88,42 @@ static int nv_acpi_get_device_handle(nv_state_t *nv, acpi_handle *dev_handle) #endif } -static int nv_acpi_notify(struct notifier_block *nb, - unsigned long val, void *data) +/* + * This callback will be invoked by the acpi_notifier_call_chain() + */ +static int nv_acpi_notifier_call_chain_handler( + struct notifier_block *nb, + unsigned long val, + void *data +) { struct acpi_bus_event *info = data; nv_stack_t *sp = NULL; nv_linux_state_t *nvl = container_of(nb, nv_linux_state_t, acpi_nb); nv_state_t *nv = NV_STATE_PTR(nvl); - if (!strcmp(info->device_class, ACPI_VIDEO_CLASS)) { - if (nv_kmem_cache_alloc_stack(&sp) == 0) { - /* - * Function to handle device specific ACPI events - * such as display hotplug and D-notifier events. - */ - rm_acpi_notify(sp, nv, info->type); - nv_kmem_cache_free_stack(sp); - } - else - nv_printf(NV_DBG_ERRORS, - "NVRM: nv_acpi_notify: failed to allocate stack\n"); - + /* + * The ACPI_VIDEO_NOTIFY_PROBE will be sent for display hot-plug/unplug. + * This event will be received first by the acpi-video driver + * and then it will be notified through acpi_notifier_call_chain(). + */ + if (!strcmp(info->device_class, ACPI_VIDEO_CLASS) && + (info->type == ACPI_VIDEO_NOTIFY_PROBE)) + { /* - * Special case for ACPI_VIDEO_NOTIFY_PROBE event: intentionally return - * NOTIFY_BAD to inform acpi-video to stop generating keypresses for - * this event. + * Intentionally return NOTIFY_BAD to inform acpi-video to stop + * generating keypresses for this event. The default behavior in the + * acpi-video driver for an ACPI_VIDEO_NOTIFY_PROBE, is to send a + * KEY_SWITCHVIDEOMODE evdev event, which causes the desktop settings + * daemons like gnome-setting-daemon to switch mode and this impacts + * the notebooks having external HDMI connected. */ - if (info->type == ACPI_VIDEO_NOTIFY_PROBE) { - return NOTIFY_BAD; - } + return NOTIFY_BAD; } return NOTIFY_DONE; } -void nv_acpi_register_notifier(nv_linux_state_t *nvl) -{ - nvl->acpi_nb.notifier_call = nv_acpi_notify; - register_acpi_notifier(&nvl->acpi_nb); -} - -void nv_acpi_unregister_notifier(nv_linux_state_t *nvl) -{ - unregister_acpi_notifier(&nvl->acpi_nb); -} - NV_STATUS NV_API_CALL nv_acpi_get_powersource(NvU32 *ac_plugged) { unsigned long long val; @@ -167,12 +166,31 @@ static void nv_acpi_powersource_hotplug_event(acpi_handle handle, u32 event_type rm_power_source_change_event(pNvAcpiObject->sp, !ac_plugged); } } + +static void nv_acpi_nvpcf_event(acpi_handle handle, u32 event_type, void *data) +{ + nv_acpi_t *pNvAcpiObject = data; + + if (event_type == ACPI_NVPCF_EVENT_CHANGE) + { + rm_acpi_nvpcf_notify(pNvAcpiObject->sp); + } + else + { + nv_printf(NV_DBG_INFO,"NVRM: %s: NVPCF event 0x%x is not supported\n", event_type, __FUNCTION__); + } +} + /* * End of ACPI event handler functions */ /* Do the necessary allocations and install notifier "handler" on the device-node "device" */ -static nv_acpi_t* nv_install_notifier(struct acpi_handle *handle, acpi_notify_handler handler) +static nv_acpi_t* nv_install_notifier( + struct acpi_handle *handle, + acpi_notify_handler handler, + void *notifier_data +) { nvidia_stack_t *sp = NULL; nv_acpi_t *pNvAcpiObject = NULL; @@ -196,6 +214,7 @@ static nv_acpi_t* nv_install_notifier(struct acpi_handle *handle, acpi_notify_ha // store a handle reference in our object pNvAcpiObject->handle = handle; pNvAcpiObject->sp = sp; + pNvAcpiObject->notifier_data = notifier_data; status = acpi_install_notify_handler(handle, ACPI_DEVICE_NOTIFY, handler, pNvAcpiObject); @@ -237,6 +256,49 @@ static void nv_uninstall_notifier(nv_acpi_t *pNvAcpiObject, acpi_notify_handler return; } +static void nv_acpi_notify_event(acpi_handle handle, u32 event_type, void *data) +{ + nv_acpi_t *pNvAcpiObject = data; + nv_state_t *nvl = pNvAcpiObject->notifier_data; + + /* + * Function to handle device specific ACPI events such as display hotplug, + * GPS and D-notifier events. + */ + rm_acpi_notify(pNvAcpiObject->sp, NV_STATE_PTR(nvl), event_type); +} + +void nv_acpi_register_notifier(nv_linux_state_t *nvl) +{ + acpi_handle dev_handle = NULL; + + /* Install the ACPI notifier corresponding to dGPU ACPI device. */ + if ((nvl->nv_acpi_object == NULL) && + nv_acpi_get_device_handle(NV_STATE_PTR(nvl), &dev_handle) && + (dev_handle != NULL)) + { + nvl->nv_acpi_object = nv_install_notifier(dev_handle, nv_acpi_notify_event, nvl); + if (nvl->nv_acpi_object == NULL) + { + nv_printf(NV_DBG_ERRORS, + "NVRM: nv_acpi_register_notifier: failed to install notifier\n"); + } + } + + nvl->acpi_nb.notifier_call = nv_acpi_notifier_call_chain_handler; + register_acpi_notifier(&nvl->acpi_nb); +} + +void nv_acpi_unregister_notifier(nv_linux_state_t *nvl) +{ + unregister_acpi_notifier(&nvl->acpi_nb); + if (nvl->nv_acpi_object != NULL) + { + nv_uninstall_notifier(nvl->nv_acpi_object, nv_acpi_notify_event); + nvl->nv_acpi_object = NULL; + } +} + /* * acpi methods init function. * check if the NVIF, _DSM and WMMX methods are present in the acpi namespace. @@ -268,10 +330,15 @@ void NV_API_CALL nv_acpi_methods_init(NvU32 *handlesPresent) // devices if (psr_nv_acpi_object == NULL) { - psr_nv_acpi_object = nv_install_notifier(psr_device_handle, nv_acpi_powersource_hotplug_event); + psr_nv_acpi_object = nv_install_notifier(psr_device_handle, nv_acpi_powersource_hotplug_event, NULL); } } + if (nvpcf_handle && (nvpcf_nv_acpi_object == NULL)) + { + nvpcf_nv_acpi_object = nv_install_notifier(nvpcf_device_handle, nv_acpi_nvpcf_event, NULL); + } + return; } @@ -300,6 +367,12 @@ acpi_status nv_acpi_find_methods( psr_device_handle = handle; } + if (!acpi_get_handle(handle, "NPCF", &method_handle)) + { + nvpcf_handle = method_handle; + nvpcf_device_handle = handle; + } + return 0; } @@ -316,6 +389,15 @@ void NV_API_CALL nv_acpi_methods_uninit(void) psr_device_handle = NULL; psr_nv_acpi_object = NULL; } + + if (nvpcf_nv_acpi_object != NULL) + { + nv_uninstall_notifier(nvpcf_nv_acpi_object, nv_acpi_nvpcf_event); + + nvpcf_handle = NULL; + nvpcf_device_handle = NULL; + nvpcf_nv_acpi_object = NULL; + } } static NV_STATUS nv_acpi_extract_integer( diff --git a/kernel-open/nvidia/nv-mmap.c b/kernel-open/nvidia/nv-mmap.c index 35a0347d1..2cad8d099 100644 --- a/kernel-open/nvidia/nv-mmap.c +++ b/kernel-open/nvidia/nv-mmap.c @@ -350,9 +350,15 @@ int nv_encode_caching( return 1; #endif case NV_MEMORY_CACHED: - if (NV_ALLOW_CACHING(memory_type)) - break; - // Intentional fallthrough. + if (!NV_ALLOW_CACHING(memory_type)) + { + nv_printf(NV_DBG_ERRORS, + "NVRM: VM: memory type %d does not allow caching!\n", + memory_type); + return 1; + } + break; + default: nv_printf(NV_DBG_ERRORS, "NVRM: VM: cache type %d not supported for memory type %d!\n", @@ -529,6 +535,7 @@ int nvidia_mmap_helper( { return -ENXIO; } + if (IS_REG_OFFSET(nv, access_start, access_len)) { if (nv_encode_caching(&vma->vm_page_prot, NV_MEMORY_UNCACHED, diff --git a/kernel-open/nvidia/nv-pci.c b/kernel-open/nvidia/nv-pci.c index 311d9fd12..ad2bfee1c 100644 --- a/kernel-open/nvidia/nv-pci.c +++ b/kernel-open/nvidia/nv-pci.c @@ -156,6 +156,119 @@ static void nv_init_dynamic_power_management rm_init_dynamic_power_management(sp, nv, pr3_acpi_method_present); } +static int nv_resize_pcie_bars(struct pci_dev *pci_dev) { +#if defined(NV_PCI_REBAR_GET_POSSIBLE_SIZES_PRESENT) + u16 cmd; + int r, old_size, requested_size; + unsigned long sizes; + int ret = 0; +#if NV_IS_EXPORT_SYMBOL_PRESENT_pci_find_host_bridge + struct pci_host_bridge *host; +#endif + + if (NVreg_EnableResizableBar == 0) + { + nv_printf(NV_DBG_INFO, "NVRM: resizable BAR disabled by regkey, skipping\n"); + return 0; + } + + // Check if BAR1 has PCIe rebar capabilities + sizes = pci_rebar_get_possible_sizes(pci_dev, NV_GPU_BAR1); + if (sizes == 0) { + /* ReBAR not available. Nothing to do. */ + return 0; + } + + /* Try to resize the BAR to the largest supported size */ + requested_size = fls(sizes) - 1; + + /* Save the current size, just in case things go wrong */ + old_size = pci_rebar_bytes_to_size(pci_resource_len(pci_dev, NV_GPU_BAR1)); + + if (old_size == requested_size) { + nv_printf(NV_DBG_INFO, "NVRM: %04x:%02x:%02x.%x: BAR1 already at requested size.\n", + NV_PCI_DOMAIN_NUMBER(pci_dev), NV_PCI_BUS_NUMBER(pci_dev), + NV_PCI_SLOT_NUMBER(pci_dev), PCI_FUNC(pci_dev->devfn)); + return 0; + } +#if NV_IS_EXPORT_SYMBOL_PRESENT_pci_find_host_bridge + /* If the kernel will refuse us, don't even try to resize, + but give an informative error */ + host = pci_find_host_bridge(pci_dev->bus); + if (host->preserve_config) { + nv_printf(NV_DBG_INFO, "NVRM: Not resizing BAR because the firmware forbids moving windows.\n"); + return 0; + } +#endif + nv_printf(NV_DBG_INFO, "NVRM: %04x:%02x:%02x.%x: Attempting to resize BAR1.\n", + NV_PCI_DOMAIN_NUMBER(pci_dev), NV_PCI_BUS_NUMBER(pci_dev), + NV_PCI_SLOT_NUMBER(pci_dev), PCI_FUNC(pci_dev->devfn)); + + /* Disable memory decoding - required by the kernel APIs */ + pci_read_config_word(pci_dev, PCI_COMMAND, &cmd); + pci_write_config_word(pci_dev, PCI_COMMAND, cmd & ~PCI_COMMAND_MEMORY); + + /* Release BAR1 */ + pci_release_resource(pci_dev, NV_GPU_BAR1); + + /* Release BAR3 - we don't want to resize it, it's in the same bridge, so we'll want to move it */ + pci_release_resource(pci_dev, NV_GPU_BAR3); + +resize: + /* Attempt to resize BAR1 to the largest supported size */ + r = pci_resize_resource(pci_dev, NV_GPU_BAR1, requested_size); + + if (r) { + if (r == -ENOSPC) + { + /* step through smaller sizes down to original size */ + if (requested_size > old_size) + { + clear_bit(fls(sizes) - 1, &sizes); + requested_size = fls(sizes) - 1; + goto resize; + } + else + { + nv_printf(NV_DBG_ERRORS, "NVRM: No address space to allocate resized BAR1.\n"); + } + } + else if (r == -EOPNOTSUPP) + { + nv_printf(NV_DBG_WARNINGS, "NVRM: BAR resize resource not supported.\n"); + } + else + { + nv_printf(NV_DBG_WARNINGS, "NVRM: BAR resizing failed with error `%d`.\n", r); + } + } + + /* Re-attempt assignment of PCIe resources */ + pci_assign_unassigned_bus_resources(pci_dev->bus); + + if ((pci_resource_flags(pci_dev, NV_GPU_BAR1) & IORESOURCE_UNSET) || + (pci_resource_flags(pci_dev, NV_GPU_BAR3) & IORESOURCE_UNSET)) { + if (requested_size != old_size) { + /* Try to get the BAR back with the original size */ + requested_size = old_size; + goto resize; + } + /* Something went horribly wrong and the kernel didn't manage to re-allocate BAR1. + This is unlikely (because we had space before), but can happen. */ + nv_printf(NV_DBG_ERRORS, "NVRM: FATAL: Failed to re-allocate BAR1.\n"); + ret = -ENODEV; + } + + /* Re-enable memory decoding */ + pci_write_config_word(pci_dev, PCI_COMMAND, cmd); + + return ret; +#else + nv_printf(NV_DBG_INFO, "NVRM: Resizable BAR is not supported on this kernel version.\n"); + return 0; +#endif /* NV_PCI_REBAR_GET_POSSIBLE_SIZES_PRESENT */ +} + /* find nvidia devices and set initial state */ static int nv_pci_probe @@ -349,6 +462,7 @@ next_bar: (NvU64)NV_PCI_RESOURCE_START(pci_dev, i), NV_PCI_DOMAIN_NUMBER(pci_dev), NV_PCI_BUS_NUMBER(pci_dev), NV_PCI_SLOT_NUMBER(pci_dev), PCI_FUNC(pci_dev->devfn)); + goto failed; } @@ -365,6 +479,12 @@ next_bar: goto failed; } + if (nv_resize_pcie_bars(pci_dev)) { + nv_printf(NV_DBG_ERRORS, + "NVRM: Fatal Error while attempting to resize PCIe BARs.\n"); + goto failed; + } + NV_KZALLOC(nvl, sizeof(nv_linux_state_t)); if (nvl == NULL) { diff --git a/kernel-open/nvidia/nv-reg.h b/kernel-open/nvidia/nv-reg.h index 31d3560f5..cdb51417f 100644 --- a/kernel-open/nvidia/nv-reg.h +++ b/kernel-open/nvidia/nv-reg.h @@ -699,6 +699,22 @@ #define NV_REG_ENABLE_PCIE_RELAXED_ORDERING_MODE \ NV_REG_STRING(__NV_ENABLE_PCIE_RELAXED_ORDERING_MODE) +/* + * Option: EnableResizableBar + * + * Description: + * + * When this option is enabled, the NVIDIA driver will attempt to resize + * BAR1 to match framebuffer size, or the next largest available size on + * supported machines. This is currently only implemented for Linux. + * + * Possible values: + * 0 - Do not enable PCI BAR resizing + * 1 - Enable PCI BAR resizing + */ +#define __NV_ENABLE_RESIZABLE_BAR EnableResizableBar +#define NV_REG_ENABLE_RESIZABLE_BAR NV_REG_STRING(__NV_ENABLE_RESIZABLE_BAR) + /* * Option: EnableGpuFirmware * @@ -825,6 +841,26 @@ #define NV_DMA_REMAP_PEER_MMIO_DISABLE 0x00000000 #define NV_DMA_REMAP_PEER_MMIO_ENABLE 0x00000001 +/* + * Option: NVreg_RmNvlinkBandwidth + * + * Description: + * + * This option allows user to reduce the NVLINK P2P bandwidth to save power. + * The option is in the string format. + * + * Possible string values: + * OFF: 0% bandwidth + * MIN: 15%-25% bandwidth depending on the system's NVLink topology + * HALF: 50% bandwidth + * 3QUARTER: 75% bandwidth + * FULL: 100% bandwidth (default) + * + * This option is only for Hopper+ GPU with NVLINK version 4.0. + */ +#define __NV_RM_NVLINK_BW RmNvlinkBandwidth +#define NV_RM_NVLINK_BW NV_REG_STRING(__NV_RM_NVLINK_BW) + #if defined(NV_DEFINE_REGISTRY_KEY_TABLE) /* @@ -861,6 +897,7 @@ NV_DEFINE_REG_ENTRY_GLOBAL(__NV_IGNORE_MMIO_CHECK, 0); NV_DEFINE_REG_ENTRY_GLOBAL(__NV_NVLINK_DISABLE, 0); NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_PCIE_RELAXED_ORDERING_MODE, 0); NV_DEFINE_REG_ENTRY_GLOBAL(__NV_REGISTER_PCI_DRIVER, 1); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_RESIZABLE_BAR, 0); NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_DBG_BREAKPOINT, 0); NV_DEFINE_REG_STRING_ENTRY(__NV_REGISTRY_DWORDS, NULL); @@ -870,6 +907,7 @@ NV_DEFINE_REG_STRING_ENTRY(__NV_GPU_BLACKLIST, NULL); NV_DEFINE_REG_STRING_ENTRY(__NV_TEMPORARY_FILE_PATH, NULL); NV_DEFINE_REG_STRING_ENTRY(__NV_EXCLUDED_GPUS, NULL); NV_DEFINE_REG_ENTRY(__NV_DMA_REMAP_PEER_MMIO, NV_DMA_REMAP_PEER_MMIO_ENABLE); +NV_DEFINE_REG_STRING_ENTRY(__NV_RM_NVLINK_BW, NULL); /* *----------------registry database definition---------------------- @@ -910,6 +948,7 @@ nv_parm_t nv_parms[] = { NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_REGISTER_PCI_DRIVER), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_PCIE_RELAXED_ORDERING_MODE), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_RESIZABLE_BAR), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_GPU_FIRMWARE), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_GPU_FIRMWARE_LOGS), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_DBG_BREAKPOINT), diff --git a/kernel-open/nvidia/nv-vm.c b/kernel-open/nvidia/nv-vm.c index 2bfceb612..d183b7c5c 100644 --- a/kernel-open/nvidia/nv-vm.c +++ b/kernel-open/nvidia/nv-vm.c @@ -265,7 +265,7 @@ static unsigned int nv_compute_gfp_mask( gfp_mask |= __GFP_ZERO; #endif #if defined(__GFP_THISNODE) - if (at->flags.node0) + if (at->flags.node) gfp_mask |= __GFP_THISNODE; #endif // Compound pages are required by vm_insert_page for high-order page @@ -384,9 +384,9 @@ NV_STATUS nv_alloc_contig_pages( at->order = get_order(at->num_pages * PAGE_SIZE); gfp_mask = nv_compute_gfp_mask(nv, at); - if (at->flags.node0) + if (at->flags.node) { - NV_ALLOC_PAGES_NODE(virt_addr, 0, at->order, gfp_mask); + NV_ALLOC_PAGES_NODE(virt_addr, at->node_id, at->order, gfp_mask); } else { @@ -529,9 +529,9 @@ NV_STATUS nv_alloc_system_pages( gfp_mask); at->flags.coherent = NV_TRUE; } - else if (at->flags.node0) + else if (at->flags.node) { - NV_ALLOC_PAGES_NODE(virt_addr, 0, 0, gfp_mask); + NV_ALLOC_PAGES_NODE(virt_addr, at->node_id, 0, gfp_mask); } else { diff --git a/kernel-open/nvidia/nv.c b/kernel-open/nvidia/nv.c index 976449973..3a166ec60 100644 --- a/kernel-open/nvidia/nv.c +++ b/kernel-open/nvidia/nv.c @@ -280,11 +280,12 @@ void nv_sev_init( static nv_alloc_t *nvos_create_alloc( struct device *dev, - int num_pages + int num_pages ) { - nv_alloc_t *at; - unsigned int pt_size, i; + nv_alloc_t *at; + unsigned int pt_size; + unsigned int i; NV_KZALLOC(at, sizeof(nv_alloc_t)); if (at == NULL) @@ -295,6 +296,7 @@ nv_alloc_t *nvos_create_alloc( at->dev = dev; pt_size = num_pages * sizeof(nvidia_pte_t *); + if (os_alloc_mem((void **)&at->page_table, pt_size) != NV_OK) { nv_printf(NV_DBG_ERRORS, "NVRM: failed to allocate page table\n"); @@ -3303,6 +3305,7 @@ NV_STATUS NV_API_CALL nv_alloc_pages( NvU32 cache_type, NvBool zeroed, NvBool unencrypted, + NvS32 node_id, NvU64 *pte_array, void **priv_data ) @@ -3314,7 +3317,7 @@ NV_STATUS NV_API_CALL nv_alloc_pages( NvU32 i; struct device *dev = NULL; - nv_printf(NV_DBG_MEMINFO, "NVRM: VM: nv_alloc_pages: %d pages\n", page_count); + nv_printf(NV_DBG_MEMINFO, "NVRM: VM: nv_alloc_pages: %d pages, nodeid %d\n", page_count, node_id); nv_printf(NV_DBG_MEMINFO, "NVRM: VM: contig %d cache_type %d\n", contiguous, cache_type); @@ -3372,9 +3375,18 @@ NV_STATUS NV_API_CALL nv_alloc_pages( * See Bug 1920398 for more details. */ if (nv && nvl->npu && !nvl->dma_dev.nvlink) - at->flags.node0 = NV_TRUE; + { + at->flags.node = NV_TRUE; + at->node_id = 0; + } #endif + if (node_id != NUMA_NO_NODE) + { + at->flags.node = NV_TRUE; + at->node_id = node_id; + } + if (at->flags.contig) status = nv_alloc_contig_pages(nv, at); else @@ -5069,23 +5081,36 @@ void nv_linux_remove_device_locked(nv_linux_state_t *nvl) void NV_API_CALL nv_control_soc_irqs(nv_state_t *nv, NvBool bEnable) { int count; + unsigned long flags; + nv_linux_state_t *nvl = NV_GET_NVL_FROM_NV_STATE(nv); + if (nv->current_soc_irq != -1) + return; + + NV_SPIN_LOCK_IRQSAVE(&nvl->soc_isr_lock, flags); if (bEnable) { for (count = 0; count < nv->num_soc_irqs; count++) { - nv->soc_irq_info[count].bh_pending = NV_FALSE; - nv->current_soc_irq = -1; - enable_irq(nv->soc_irq_info[count].irq_num); + if (nv->soc_irq_info[count].ref_count == 0) + { + nv->soc_irq_info[count].ref_count++; + enable_irq(nv->soc_irq_info[count].irq_num); + } } } else { for (count = 0; count < nv->num_soc_irqs; count++) { - disable_irq_nosync(nv->soc_irq_info[count].irq_num); + if (nv->soc_irq_info[count].ref_count == 1) + { + nv->soc_irq_info[count].ref_count--; + disable_irq_nosync(nv->soc_irq_info[count].irq_num); + } } } + NV_SPIN_UNLOCK_IRQRESTORE(&nvl->soc_isr_lock, flags); } NvU32 NV_API_CALL nv_get_dev_minor(nv_state_t *nv) @@ -5509,3 +5534,4 @@ void NV_API_CALL nv_get_updated_emu_seg( *end = min((resource_size_t)*end, p->end); } } + diff --git a/kernel-open/nvidia/nv_gpu_ops.h b/kernel-open/nvidia/nv_gpu_ops.h index 63ea73afe..7a5dcadb8 100644 --- a/kernel-open/nvidia/nv_gpu_ops.h +++ b/kernel-open/nvidia/nv_gpu_ops.h @@ -76,26 +76,26 @@ NV_STATUS nvGpuOpsMemoryAllocSys (gpuAddressSpaceHandle vaSpace, NV_STATUS nvGpuOpsPmaAllocPages(void *pPma, NvLength pageCount, - NvU32 pageSize, + NvU64 pageSize, gpuPmaAllocationOptions *pPmaAllocOptions, NvU64 *pPages); void nvGpuOpsPmaFreePages(void *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize, + NvU64 pageSize, NvU32 flags); NV_STATUS nvGpuOpsPmaPinPages(void *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize, + NvU64 pageSize, NvU32 flags); NV_STATUS nvGpuOpsPmaUnpinPages(void *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize); + NvU64 pageSize); NV_STATUS nvGpuOpsChannelAllocate(gpuAddressSpaceHandle vaSpace, const gpuChannelAllocParams *params, @@ -112,7 +112,7 @@ void nvGpuOpsMemoryFree(gpuAddressSpaceHandle vaSpace, NV_STATUS nvGpuOpsMemoryCpuMap(gpuAddressSpaceHandle vaSpace, NvU64 memory, NvLength length, - void **cpuPtr, NvU32 pageSize); + void **cpuPtr, NvU64 pageSize); void nvGpuOpsMemoryCpuUnMap(gpuAddressSpaceHandle vaSpace, void* cpuPtr); @@ -276,4 +276,6 @@ NV_STATUS nvGpuOpsPagingChannelPushStream(UvmGpuPagingChannel *channel, char *methodStream, NvU32 methodStreamSize); +NV_STATUS nvGpuOpsFlushReplayableFaultBuffer(struct gpuDevice *device); + #endif /* _NV_GPU_OPS_H_*/ diff --git a/kernel-open/nvidia/nv_uvm_interface.c b/kernel-open/nvidia/nv_uvm_interface.c index abb459750..5fd603636 100644 --- a/kernel-open/nvidia/nv_uvm_interface.c +++ b/kernel-open/nvidia/nv_uvm_interface.c @@ -957,6 +957,18 @@ NV_STATUS nvUvmInterfaceGetNonReplayableFaults(UvmGpuFaultInfo *pFaultInfo, } EXPORT_SYMBOL(nvUvmInterfaceGetNonReplayableFaults); +NV_STATUS nvUvmInterfaceFlushReplayableFaultBuffer(uvmGpuDeviceHandle device) +{ + nvidia_stack_t *sp = nvUvmGetSafeStack(); + NV_STATUS status; + + status = rm_gpu_ops_flush_replayable_fault_buffer(sp, (gpuDeviceHandle)device); + + nvUvmFreeSafeStack(sp); + return status; +} +EXPORT_SYMBOL(nvUvmInterfaceFlushReplayableFaultBuffer); + NV_STATUS nvUvmInterfaceDestroyAccessCntrInfo(uvmGpuDeviceHandle device, UvmGpuAccessCntrInfo *pAccessCntrInfo) { diff --git a/kernel-open/nvidia/nvidia.Kbuild b/kernel-open/nvidia/nvidia.Kbuild index 5d8b4d0b8..821035dc4 100644 --- a/kernel-open/nvidia/nvidia.Kbuild +++ b/kernel-open/nvidia/nvidia.Kbuild @@ -135,6 +135,7 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += pnv_pci_get_npu_dev NV_CONFTEST_FUNCTION_COMPILE_TESTS += of_get_ibm_chip_id NV_CONFTEST_FUNCTION_COMPILE_TESTS += pci_bus_address NV_CONFTEST_FUNCTION_COMPILE_TESTS += pci_stop_and_remove_bus_device +NV_CONFTEST_FUNCTION_COMPILE_TESTS += pci_rebar_get_possible_sizes NV_CONFTEST_FUNCTION_COMPILE_TESTS += register_cpu_notifier NV_CONFTEST_FUNCTION_COMPILE_TESTS += cpuhp_setup_state NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_map_resource @@ -166,6 +167,7 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += devm_of_platform_populate NV_CONFTEST_FUNCTION_COMPILE_TESTS += of_dma_configure NV_CONFTEST_FUNCTION_COMPILE_TESTS += of_property_count_elems_of_size NV_CONFTEST_FUNCTION_COMPILE_TESTS += of_property_read_variable_u8_array +NV_CONFTEST_FUNCTION_COMPILE_TESTS += of_property_read_variable_u32_array NV_CONFTEST_FUNCTION_COMPILE_TESTS += i2c_new_client_device NV_CONFTEST_FUNCTION_COMPILE_TESTS += i2c_unregister_device NV_CONFTEST_FUNCTION_COMPILE_TESTS += of_get_named_gpio @@ -189,6 +191,7 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_set_mask_and_coherent NV_CONFTEST_FUNCTION_COMPILE_TESTS += devm_clk_bulk_get_all NV_CONFTEST_FUNCTION_COMPILE_TESTS += get_task_ioprio NV_CONFTEST_FUNCTION_COMPILE_TESTS += mdev_set_iommu_device +NV_CONFTEST_FUNCTION_COMPILE_TESTS += offline_and_remove_memory NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl_of_node_to_nid NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl_sme_active @@ -209,6 +212,10 @@ NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_get_dram_num_channe NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tegra_dram_types NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_pxm_to_node NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_screen_info +NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_i2c_bus_status +NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tegra_fuse_control_read +NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tegra_get_platform +NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_pci_find_host_bridge NV_CONFTEST_TYPE_COMPILE_TESTS += dma_ops NV_CONFTEST_TYPE_COMPILE_TESTS += swiotlb_dma_ops @@ -217,7 +224,6 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += vm_fault_has_address NV_CONFTEST_TYPE_COMPILE_TESTS += vm_insert_pfn_prot NV_CONFTEST_TYPE_COMPILE_TESTS += vmf_insert_pfn_prot NV_CONFTEST_TYPE_COMPILE_TESTS += vm_ops_fault_removed_vma_arg -NV_CONFTEST_TYPE_COMPILE_TESTS += vmbus_channel_has_ringbuffer_page NV_CONFTEST_TYPE_COMPILE_TESTS += kmem_cache_has_kobj_remove_work NV_CONFTEST_TYPE_COMPILE_TESTS += sysfs_slab_unlink NV_CONFTEST_TYPE_COMPILE_TESTS += proc_ops @@ -244,3 +250,5 @@ NV_CONFTEST_GENERIC_COMPILE_TESTS += vm_fault_t NV_CONFTEST_GENERIC_COMPILE_TESTS += pci_class_multimedia_hd_audio NV_CONFTEST_GENERIC_COMPILE_TESTS += drm_available NV_CONFTEST_GENERIC_COMPILE_TESTS += vfio_pci_core_available +NV_CONFTEST_GENERIC_COMPILE_TESTS += cmd_uphy_display_port_init +NV_CONFTEST_GENERIC_COMPILE_TESTS += cmd_uphy_display_port_off diff --git a/kernel-open/nvidia/os-interface.c b/kernel-open/nvidia/os-interface.c index 6d5bcfa20..1885030ac 100644 --- a/kernel-open/nvidia/os-interface.c +++ b/kernel-open/nvidia/os-interface.c @@ -1790,11 +1790,6 @@ NV_STATUS NV_API_CALL os_numa_memblock_size return NV_OK; } -NV_STATUS NV_API_CALL os_call_nv_vmbus(NvU32 vmbus_cmd, void *input) -{ - return NV_ERR_NOT_SUPPORTED; -} - NV_STATUS NV_API_CALL os_open_temporary_file ( void **ppFile diff --git a/kernel-open/nvidia/os-registry.c b/kernel-open/nvidia/os-registry.c index ed0d09e93..7a42ec881 100644 --- a/kernel-open/nvidia/os-registry.c +++ b/kernel-open/nvidia/os-registry.c @@ -317,6 +317,14 @@ NV_STATUS NV_API_CALL os_registry_init(void) return NV_ERR_NO_MEMORY; } + if (NVreg_RmNvlinkBandwidth != NULL) + { + rm_write_registry_string(sp, NULL, + "RmNvlinkBandwidth", + NVreg_RmNvlinkBandwidth, + strlen(NVreg_RmNvlinkBandwidth)); + } + if (NVreg_RmMsg != NULL) { rm_write_registry_string(sp, NULL, diff --git a/src/common/displayport/inc/dp_address.h b/src/common/displayport/inc/dp_address.h index 505632df0..d49eebc3d 100644 --- a/src/common/displayport/inc/dp_address.h +++ b/src/common/displayport/inc/dp_address.h @@ -72,7 +72,7 @@ namespace DisplayPort } } - void clear() + void clear() { hops = 0; for (unsigned i = 0; i < maxHops; i++) @@ -83,7 +83,11 @@ namespace DisplayPort Address parent() const { - DP_ASSERT(hops != 0); + if (hops == 0) + { + DP_ASSERT(hops != 0); + return 0; + } Address addr = *this; addr.hops --; return addr; diff --git a/src/common/displayport/inc/dp_configcaps.h b/src/common/displayport/inc/dp_configcaps.h index a79a8ea65..fc570fee0 100644 --- a/src/common/displayport/inc/dp_configcaps.h +++ b/src/common/displayport/inc/dp_configcaps.h @@ -304,6 +304,7 @@ namespace DisplayPort virtual unsigned lttprGetRevisionMinor() = 0; virtual bool getSDPExtnForColorimetry() = 0; + virtual bool getRootAsyncSDPSupported() = 0; bool isAtLeastVersion(unsigned major, unsigned minor) { @@ -522,7 +523,6 @@ namespace DisplayPort virtual bool readPsrErrorStatus(vesaPsrErrorStatus *psrErr) = 0; virtual bool writePsrEvtIndicator(vesaPsrEventIndicator psrErr) = 0; virtual bool readPsrEvtIndicator(vesaPsrEventIndicator *psrErr) = 0; - virtual ~DPCDHAL() {} }; diff --git a/src/common/displayport/inc/dp_connector.h b/src/common/displayport/inc/dp_connector.h index 8f7a8e04b..1a7094723 100644 --- a/src/common/displayport/inc/dp_connector.h +++ b/src/common/displayport/inc/dp_connector.h @@ -43,6 +43,7 @@ #include "dp_vrr.h" #include "../../modeset/timing/nvt_dsc_pps.h" #include "ctrl/ctrl0073/ctrl0073dp.h" +#include "nvcfg_sdk.h" namespace DisplayPort { @@ -202,6 +203,7 @@ namespace DisplayPort virtual bool getDpcdRevision(unsigned * major, unsigned * minor) = 0; // get the dpcd revision (maybe cached) virtual bool getSDPExtnForColorimetrySupported() = 0; + virtual bool getAsyncSDPSupported() = 0; virtual bool getPanelFwRevision(NvU16 *revision) = 0; @@ -261,7 +263,6 @@ namespace DisplayPort // If the sink support MSA override in MST environment. virtual bool isMSAOverMSTCapable() = 0; virtual bool isFakedMuxDevice() = 0; - virtual bool setPanelReplayConfig(panelReplayConfig prcfg) = 0; virtual bool isPanelReplaySupported() = 0; virtual bool getPanelReplayStatus(PanelReplayStatus *pPrStatus) = 0; diff --git a/src/common/displayport/inc/dp_connectorimpl.h b/src/common/displayport/inc/dp_connectorimpl.h index 76b89bbd3..496946700 100644 --- a/src/common/displayport/inc/dp_connectorimpl.h +++ b/src/common/displayport/inc/dp_connectorimpl.h @@ -299,8 +299,6 @@ namespace DisplayPort bool bEnableFastLT; NvU32 maxLinkRateFromRegkey; - bool bEnableOuiRestoring; - // // Latency(ms) to apply between link-train and FEC enable for bug // 2561206. diff --git a/src/common/displayport/inc/dp_deviceimpl.h b/src/common/displayport/inc/dp_deviceimpl.h index b5bbe6dc4..62cdeaf33 100644 --- a/src/common/displayport/inc/dp_deviceimpl.h +++ b/src/common/displayport/inc/dp_deviceimpl.h @@ -76,7 +76,7 @@ namespace DisplayPort { struct _Enum_Path { - unsigned total, free; + unsigned availableStreams, total, free; bool bPathFECCapable; bool dataValid; // Is the cache valid? } enum_path; @@ -167,7 +167,7 @@ namespace DisplayPort NvU8 rawDscCaps[16]; DscCaps dscCaps; - // Panel replay Caps + // Panel replay Caps PanelReplayCaps prCaps; bool bIsFakedMuxDevice; @@ -195,6 +195,7 @@ namespace DisplayPort bool bFECParitySupported; TriState bSdpExtCapable; + TriState bAsyncSDPCapable; bool bMSAOverMSTCapable; bool bDscPassThroughColorFormatWar; @@ -380,6 +381,7 @@ namespace DisplayPort virtual void queryGUID2(); virtual bool getSDPExtnForColorimetrySupported(); + virtual bool getAsyncSDPSupported(); virtual bool getPanelFwRevision(NvU16 *revision); diff --git a/src/common/displayport/inc/dp_discovery.h b/src/common/displayport/inc/dp_discovery.h index d0a8fa7eb..c950136c6 100644 --- a/src/common/displayport/inc/dp_discovery.h +++ b/src/common/displayport/inc/dp_discovery.h @@ -223,6 +223,7 @@ namespace DisplayPort : device(device), address(device.address), parent(parent), completed(false), retriesRemoteDpcdWriteMessage(0), retryRemoteDpcdWriteMessage(false), retriesRemoteDpcdReadMessage(0), retryRemoteDpcdReadMessage(false), + retriesLinkAddressMessage(0), retryLinkAddressMessage(false), bFromCSN(bFromCSN) {} diff --git a/src/common/displayport/inc/dp_evoadapter.h b/src/common/displayport/inc/dp_evoadapter.h index b14d81a1b..733817e2b 100644 --- a/src/common/displayport/inc/dp_evoadapter.h +++ b/src/common/displayport/inc/dp_evoadapter.h @@ -182,8 +182,8 @@ namespace DisplayPort }_DSC; private: - virtual void initializeRegkeyDatabase(); - virtual void applyRegkeyOverrides(); + void initializeRegkeyDatabase(); + void applyRegkeyOverrides(); public: EvoMainLink(EvoInterface * provider, Timer * timer); diff --git a/src/common/displayport/inc/dp_linkconfig.h b/src/common/displayport/inc/dp_linkconfig.h index 7a9994404..0a565fc8c 100644 --- a/src/common/displayport/inc/dp_linkconfig.h +++ b/src/common/displayport/inc/dp_linkconfig.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2010-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -47,7 +47,15 @@ namespace DisplayPort NvU8 element[NV_DPCD_SUPPORTED_LINK_RATES__SIZE]; NvU8 entries; - LinkRates() : entries(0) {} + LinkRates() + { + entries = 0; + + for (int i = 0; i < NV_DPCD_SUPPORTED_LINK_RATES__SIZE; i++) + { + element[i] = 0; + } + } void clear() { diff --git a/src/common/displayport/inc/dp_mainlink.h b/src/common/displayport/inc/dp_mainlink.h index aac2f9a17..10bec81c6 100644 --- a/src/common/displayport/inc/dp_mainlink.h +++ b/src/common/displayport/inc/dp_mainlink.h @@ -101,10 +101,6 @@ namespace DisplayPort class MainLink : virtual public Object { - private: - virtual void initializeRegkeyDatabase() = 0; - virtual void applyRegkeyOverrides() = 0; - public: virtual bool physicalLayerSetTestPattern(PatternInfo * patternInfo) = 0; diff --git a/src/common/displayport/inc/dp_messagecodings.h b/src/common/displayport/inc/dp_messagecodings.h index 0ae4d88d7..e483d0079 100644 --- a/src/common/displayport/inc/dp_messagecodings.h +++ b/src/common/displayport/inc/dp_messagecodings.h @@ -274,6 +274,7 @@ namespace DisplayPort struct { unsigned portNumber; + unsigned availableStreams; bool bFECCapability; unsigned TotalPBN; unsigned FreePBN; @@ -354,6 +355,8 @@ namespace DisplayPort struct { unsigned port; + unsigned availableStreams; + bool bFECCapability; GUID guid; unsigned PBN; } request; diff --git a/src/common/displayport/inc/dp_messages.h b/src/common/displayport/inc/dp_messages.h index 496b18a15..01231ff9a 100644 --- a/src/common/displayport/inc/dp_messages.h +++ b/src/common/displayport/inc/dp_messages.h @@ -159,7 +159,7 @@ namespace DisplayPort splitterUpReply(hal, timer), mergerUpRequest(hal, timer, Address(0), this), mergerDownReply(hal, timer, Address(0), this), - isBeingDestroyed(false) + isBeingDestroyed(false), isPaused(false) { } diff --git a/src/common/displayport/inc/dp_regkeydatabase.h b/src/common/displayport/inc/dp_regkeydatabase.h index 12afaf2ca..7e3b11a6b 100644 --- a/src/common/displayport/inc/dp_regkeydatabase.h +++ b/src/common/displayport/inc/dp_regkeydatabase.h @@ -59,9 +59,6 @@ #define NV_DP_REGKEY_FORCE_EDP_ILR "DP_BYPASS_EDP_ILR_REV_CHECK" -// Regkey to enable OUI caching/restoring in release branch. -#define NV_DP_REGKEY_ENABLE_OUI_RESTORING "DP_ENABLE_OUI_RESTORING" - // Message to power down video stream before power down link (set D3) #define NV_DP_REGKEY_POWER_DOWN_PHY "DP_POWER_DOWN_PHY" @@ -102,7 +99,6 @@ struct DP_REGKEY_DATABASE bool bOptLinkKeptAliveSst; bool bBypassEDPRevCheck; bool bDscMstCapBug3143315; - bool bEnableOuiRestoring; bool bPowerDownPhyBeforeD3; }; diff --git a/src/common/displayport/inc/dp_splitter.h b/src/common/displayport/inc/dp_splitter.h index 827ae1bb8..f632cf5f0 100644 --- a/src/common/displayport/inc/dp_splitter.h +++ b/src/common/displayport/inc/dp_splitter.h @@ -44,10 +44,13 @@ namespace DisplayPort class MessageTransactionSplitter { - EncodedMessage * messageOutstanding; // If set we've pulled an item out of the downQueue queue. + // + // If set we've pulled an item out of the downQueue queue. // One or more transactions have been sent as a result // messageOutstanding->messageOffset show how far into // the message we are. + // + EncodedMessage * messageOutstanding; unsigned assemblyTransmitted; public: void set(EncodedMessage * messageOutstanding) @@ -62,7 +65,7 @@ namespace DisplayPort // bool get(Buffer & assemblyBuffer); - MessageTransactionSplitter() + MessageTransactionSplitter() : messageOutstanding(0), assemblyTransmitted(0) {} }; diff --git a/src/common/displayport/src/dp_configcaps.cpp b/src/common/displayport/src/dp_configcaps.cpp index 91cfd6ff0..49f156e4c 100644 --- a/src/common/displayport/src/dp_configcaps.cpp +++ b/src/common/displayport/src/dp_configcaps.cpp @@ -115,14 +115,6 @@ struct DPCDHALImpl : DPCDHAL // DPCD Offset 0119h [0] - If we grant the extendedSleepWakeTimeoutRequest bool bExtendedSleepWakeTimeoutGranted; - // 0x2206, if the sink supports 128b/132b - bool bDP20ChannelCodingSupported; - // 0x2215 - bool bUHBR_10GSupported; - bool bUHBR_13_5GSupported; - bool bUHBR_20GSupported; - - // DPCD Offset F0002h - Number of Physical Repeaters present (after mapping) between Source and Sink unsigned phyRepeaterCount; // DPCD offset 700 - EDP_DPCD_REV @@ -134,13 +126,6 @@ struct DPCDHALImpl : DPCDHAL LinkRate maxLinkRate; // DPCD offset F0001h unsigned maxLaneCount; // DPCD offset F0004h unsigned phyRepeaterExtendedWakeTimeoutMs; // DPCD offset F0005h - - // 0xF0006, if the PHY Repeater supports 128b/132b - bool bDP20ChannelCodingSupported; - // 0xF0007 - bool UHBR_10GSupported; - bool UHBR_13_5GSupported; - bool UHBR_20GSupported; } repeaterCaps; PCONCaps pconCaps; @@ -506,45 +491,6 @@ struct DPCDHALImpl : DPCDHAL caps.numberAudioEndpoints = (unsigned)(DRF_VAL(_DPCD, _NUMBER_OF_AUDIO_ENDPOINTS, _VALUE, buffer[0x2])); - // 02206h - if (AuxRetry::ack == bus.read(NV_DPCD14_EXTENDED_MAIN_LINK_CHANNEL_CODING, &buffer[0], 1)) - { - caps.bDP20ChannelCodingSupported = - FLD_TEST_DRF(_DPCD14, - _EXTENDED_MAIN_LINK_CHANNEL_CODING, - _ANSI_128B_132B, - _YES, - buffer[0]); - if (caps.bDP20ChannelCodingSupported == true) - { - // 0x2215 - if (AuxRetry::ack == bus.read(NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES, &buffer[0], 1)) - { - caps.bUHBR_10GSupported = - FLD_TEST_DRF(_DPCD20, - _128B_132B_SUPPORTED_LINK_RATES, - _UHBR10, - _YES, - buffer[0]); - - caps.bUHBR_13_5GSupported = - FLD_TEST_DRF(_DPCD20, - _128B_132B_SUPPORTED_LINK_RATES, - _UHBR13_5, - _YES, - buffer[0]); - - caps.bUHBR_20GSupported = - FLD_TEST_DRF(_DPCD20, - _128B_132B_SUPPORTED_LINK_RATES, - _UHBR20, - _YES, - buffer[0]); - } - DP_ASSERT(caps.bUHBR_10GSupported && "Unknown max link rate or HBR2 without at least DP 1.2. Assuming DP 1.1 defaults"); - } - } - if (bLttprSupported) { // Burst read from 0xF0000 to 0xF0007 @@ -583,42 +529,6 @@ struct DPCDHALImpl : DPCDHAL _PHY_REPEATER_EXTENDED_WAKE_TIMEOUT, _REQ, buffer[0x5]) * 10; - // An LTTPR that supports 128b/132b channel coding shall program this register to 20h. - if (lttprIsAtLeastVersion(2, 0)) - { - caps.repeaterCaps.bDP20ChannelCodingSupported = - FLD_TEST_DRF(_DPCD14, - _PHY_REPEATER_MAIN_LINK_CHANNEL_CODING, - _128B_132B_SUPPORTED, - _YES, - buffer[6]); - - caps.repeaterCaps.UHBR_10GSupported = - FLD_TEST_DRF(_DPCD14, - _PHY_REPEATER_128B_132B_RATES, - _10G_SUPPORTED, - _YES, - buffer[7]); - - caps.repeaterCaps.UHBR_13_5GSupported = - FLD_TEST_DRF(_DPCD14, - _PHY_REPEATER_128B_132B_RATES, - _13_5G_SUPPORTED, - _YES, - buffer[7]); - - caps.repeaterCaps.UHBR_20GSupported = - FLD_TEST_DRF(_DPCD14, - _PHY_REPEATER_128B_132B_RATES, - _20G_SUPPORTED, - _YES, - buffer[7]); - - if (buffer[7] && !caps.repeaterCaps.bDP20ChannelCodingSupported) - { - DP_ASSERT(0 && "UHBR is supported without 128b/132b Channel Encoding Supported!"); - } - } } else { @@ -829,6 +739,24 @@ struct DPCDHALImpl : DPCDHAL } return bSDPExtnForColorimetry; } + + virtual bool getRootAsyncSDPSupported() + { + NvU8 byte = 0; + if (!caps.extendedRxCapsPresent) + return false; + if (AuxRetry::ack != bus.read(NV_DPCD14_DPRX_FEATURE_ENUM_LIST, &byte, sizeof byte) || + FLD_TEST_DRF(_DPCD14, _DPRX_FEATURE_ENUM_LIST, _ADAPTIVE_SYNC_SDP_SUPPORTED, _NO, byte)) + { + return false; + } + if (AuxRetry::ack != bus.read(NV_DPCD_DOWN_STREAM_PORT, &byte, sizeof byte) || + FLD_TEST_DRF(_DPCD, _DOWN_STREAM_PORT, _MSA_TIMING_PAR_IGNORED, _NO, byte)) + { + return false; + } + return true; + } virtual AuxRetry::status setOuiSource(unsigned ouiId, const char * model, size_t modelNameLength, NvU8 chipRevision) @@ -2721,8 +2649,8 @@ struct DPCDHALImpl : DPCDHAL virtual void resetProtocolConverter() { NvU8 data = 0; - bus.write(NV_DPCD20_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data)); - bus.write(NV_DPCD20_PCON_FRL_LINK_CONFIG_2, &data, sizeof(data)); + bus.write(NV_DPCD14_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data)); + bus.write(NV_DPCD14_PCON_FRL_LINK_CONFIG_2, &data, sizeof(data)); } @@ -2732,26 +2660,26 @@ struct DPCDHALImpl : DPCDHAL if (bEnableSourceControlMode) { - data = FLD_SET_DRF(_DPCD20, _PCON_FRL_LINK_CONFIG_1, _SRC_CONTROL_MODE, _ENABLE, data); + data = FLD_SET_DRF(_DPCD14, _PCON_FRL_LINK_CONFIG_1, _SRC_CONTROL_MODE, _ENABLE, data); if (bEnableFRLMode) { - data = FLD_SET_DRF(_DPCD20, _PCON_FRL_LINK_CONFIG_1, _LINK_FRL_MODE, _ENABLE, data); - data = FLD_SET_DRF(_DPCD20, _PCON_FRL_LINK_CONFIG_1, _IRQ_LINK_FRL_MODE, _ENABLE, data); + data = FLD_SET_DRF(_DPCD14, _PCON_FRL_LINK_CONFIG_1, _LINK_FRL_MODE, _ENABLE, data); + data = FLD_SET_DRF(_DPCD14, _PCON_FRL_LINK_CONFIG_1, _IRQ_LINK_FRL_MODE, _ENABLE, data); } else { - data = FLD_SET_DRF(_DPCD20, _PCON_FRL_LINK_CONFIG_1, _LINK_FRL_MODE, _DISABLE, data); - data = FLD_SET_DRF(_DPCD20, _PCON_FRL_LINK_CONFIG_1, _IRQ_LINK_FRL_MODE, _DISABLE, data); + data = FLD_SET_DRF(_DPCD14, _PCON_FRL_LINK_CONFIG_1, _LINK_FRL_MODE, _DISABLE, data); + data = FLD_SET_DRF(_DPCD14, _PCON_FRL_LINK_CONFIG_1, _IRQ_LINK_FRL_MODE, _DISABLE, data); } } else { - data = FLD_SET_DRF(_DPCD20, _PCON_FRL_LINK_CONFIG_1, _SRC_CONTROL_MODE, _DISABLE, data); - data = FLD_SET_DRF(_DPCD20, _PCON_FRL_LINK_CONFIG_1, _LINK_FRL_MODE, _DISABLE, data); - data = FLD_SET_DRF(_DPCD20, _PCON_FRL_LINK_CONFIG_1, _IRQ_LINK_FRL_MODE, _DISABLE, data); + data = FLD_SET_DRF(_DPCD14, _PCON_FRL_LINK_CONFIG_1, _SRC_CONTROL_MODE, _DISABLE, data); + data = FLD_SET_DRF(_DPCD14, _PCON_FRL_LINK_CONFIG_1, _LINK_FRL_MODE, _DISABLE, data); + data = FLD_SET_DRF(_DPCD14, _PCON_FRL_LINK_CONFIG_1, _IRQ_LINK_FRL_MODE, _DISABLE, data); } - if (AuxRetry::ack != bus.write(NV_DPCD20_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data))) + if (AuxRetry::ack != bus.write(NV_DPCD14_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data))) { return false; } @@ -2789,12 +2717,12 @@ struct DPCDHALImpl : DPCDHAL // Clear only this interrupt bit. this->clearHdmiLinkStatusChanged(); - if (AuxRetry::ack != bus.read(NV_DPCD20_PCON_HDMI_TX_LINK_STATUS, &data, sizeof(data))) + if (AuxRetry::ack != bus.read(NV_DPCD14_PCON_HDMI_TX_LINK_STATUS, &data, sizeof(data))) { return false; } - if (FLD_TEST_DRF(_DPCD20, _PCON_HDMI_TX_LINK_STATUS, _LINK_READY, _YES, data)) + if (FLD_TEST_DRF(_DPCD14, _PCON_HDMI_TX_LINK_STATUS, _LINK_READY, _YES, data)) { *bFrlReady = true; } @@ -2819,22 +2747,22 @@ struct DPCDHALImpl : DPCDHAL // PCON FW trains for all Link BW selected in Link BW Mask (Bit 0~5) // data = linkBwMask; - data = FLD_SET_DRF(_DPCD20, _PCON_FRL_LINK_CONFIG_2, _FRL_LT_CONTROL, + data = FLD_SET_DRF(_DPCD14, _PCON_FRL_LINK_CONFIG_2, _FRL_LT_CONTROL, _EXTENDED, data); } else { // Set FRL_LT_CONTROL to Normal mode, so PCON stops when first FRL LT succeed. - data = FLD_SET_DRF(_DPCD20, _PCON_FRL_LINK_CONFIG_2, _FRL_LT_CONTROL, + data = FLD_SET_DRF(_DPCD14, _PCON_FRL_LINK_CONFIG_2, _FRL_LT_CONTROL, _NORMAL, data); } - if (AuxRetry::ack != bus.write(NV_DPCD20_PCON_FRL_LINK_CONFIG_2, &data, sizeof(data))) + if (AuxRetry::ack != bus.write(NV_DPCD14_PCON_FRL_LINK_CONFIG_2, &data, sizeof(data))) { return false; } - if (AuxRetry::ack != bus.read(NV_DPCD20_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data))) + if (AuxRetry::ack != bus.read(NV_DPCD14_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data))) { return false; } @@ -2842,7 +2770,7 @@ struct DPCDHALImpl : DPCDHAL if (bEnableConcurrentMode && caps.pconCaps.bConcurrentLTSupported) { // Client selects concurrent. - data = FLD_SET_DRF(_DPCD20, _PCON_FRL_LINK_CONFIG_1, _CONCURRENT_LT_MODE, + data = FLD_SET_DRF(_DPCD14, _PCON_FRL_LINK_CONFIG_1, _CONCURRENT_LT_MODE, _ENABLE, data); } else @@ -2850,15 +2778,15 @@ struct DPCDHALImpl : DPCDHAL // // Don't do concurrent LT for now. // - data = FLD_SET_DRF(_DPCD20, _PCON_FRL_LINK_CONFIG_1, _CONCURRENT_LT_MODE, + data = FLD_SET_DRF(_DPCD14, _PCON_FRL_LINK_CONFIG_1, _CONCURRENT_LT_MODE, _DISABLE, data); } - data = FLD_SET_DRF(_DPCD20, _PCON_FRL_LINK_CONFIG_1, _HDMI_LINK, + data = FLD_SET_DRF(_DPCD14, _PCON_FRL_LINK_CONFIG_1, _HDMI_LINK, _ENABLE, data); - data = FLD_SET_DRF_NUM(_DPCD20, _PCON_FRL_LINK_CONFIG_1, _MAX_LINK_BW, + data = FLD_SET_DRF_NUM(_DPCD14, _PCON_FRL_LINK_CONFIG_1, _MAX_LINK_BW, targetBw, data); - if (AuxRetry::ack != bus.write(NV_DPCD20_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data))) + if (AuxRetry::ack != bus.write(NV_DPCD14_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data))) { return false; } @@ -2888,16 +2816,16 @@ struct DPCDHALImpl : DPCDHAL return false; } // Check HDMI Link Active status (0x303B Bit 0) and Link Config (0x3036) - if (AuxRetry::ack != bus.read(NV_DPCD20_PCON_HDMI_TX_LINK_STATUS, &data, sizeof(data))) + if (AuxRetry::ack != bus.read(NV_DPCD14_PCON_HDMI_TX_LINK_STATUS, &data, sizeof(data))) { return false; } - if (FLD_TEST_DRF(_DPCD20, _PCON_HDMI_TX_LINK_STATUS, _LINK_ACTIVE, _YES, data)) + if (FLD_TEST_DRF(_DPCD14, _PCON_HDMI_TX_LINK_STATUS, _LINK_ACTIVE, _YES, data)) { - if (AuxRetry::ack == bus.read(NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS, &data, sizeof(data))) + if (AuxRetry::ack == bus.read(NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS, &data, sizeof(data))) { - *frlRateMask = DRF_VAL(_DPCD20, _PCON_HDMI_LINK_CONFIG_STATUS, _LT_RESULT, data); + *frlRateMask = DRF_VAL(_DPCD14, _PCON_HDMI_LINK_CONFIG_STATUS, _LT_RESULT, data); } } @@ -2912,18 +2840,18 @@ struct DPCDHALImpl : DPCDHAL if (bLinkActive == NULL && bLinkReady == NULL) return false; - if (AuxRetry::ack != bus.read(NV_DPCD20_PCON_HDMI_TX_LINK_STATUS, &data, sizeof(data))) + if (AuxRetry::ack != bus.read(NV_DPCD14_PCON_HDMI_TX_LINK_STATUS, &data, sizeof(data))) { return false; } if (bLinkReady != NULL) { - *bLinkReady = (FLD_TEST_DRF(_DPCD20, _PCON_HDMI_TX_LINK_STATUS, + *bLinkReady = (FLD_TEST_DRF(_DPCD14, _PCON_HDMI_TX_LINK_STATUS, _LINK_READY, _YES, data)); } if (bLinkActive != NULL) { - *bLinkActive = (FLD_TEST_DRF(_DPCD20, _PCON_HDMI_TX_LINK_STATUS, + *bLinkActive = (FLD_TEST_DRF(_DPCD14, _PCON_HDMI_TX_LINK_STATUS, _LINK_ACTIVE, _YES, data)); } return true; @@ -2938,12 +2866,12 @@ struct DPCDHALImpl : DPCDHAL NvU8 data = 0; NvU32 loopCount; NvU32 frlRate; - if (AuxRetry::ack != bus.read(NV_DPCD20_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data))) + if (AuxRetry::ack != bus.read(NV_DPCD14_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data))) { return false; } - data = FLD_SET_DRF(_DPCD20, _PCON_FRL_LINK_CONFIG_1, _HDMI_LINK, _DISABLE, data); - if (AuxRetry::ack != bus.write(NV_DPCD20_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data))) + data = FLD_SET_DRF(_DPCD14, _PCON_FRL_LINK_CONFIG_1, _HDMI_LINK, _DISABLE, data); + if (AuxRetry::ack != bus.write(NV_DPCD14_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data))) { return false; } @@ -2954,14 +2882,14 @@ struct DPCDHALImpl : DPCDHAL data = 0; do { - if (AuxRetry::ack != bus.read(NV_DPCD20_PCON_HDMI_TX_LINK_STATUS, + if (AuxRetry::ack != bus.read(NV_DPCD14_PCON_HDMI_TX_LINK_STATUS, &data, sizeof(data))) continue; - if (FLD_TEST_DRF(_DPCD20, _PCON_HDMI_TX_LINK_STATUS, _LINK_READY, _YES, data)) + if (FLD_TEST_DRF(_DPCD14, _PCON_HDMI_TX_LINK_STATUS, _LINK_READY, _YES, data)) break; } while (timeout.valid()); - if (FLD_TEST_DRF(_DPCD20, _PCON_HDMI_TX_LINK_STATUS, _LINK_READY, _NO, data)) + if (FLD_TEST_DRF(_DPCD14, _PCON_HDMI_TX_LINK_STATUS, _LINK_READY, _NO, data)) { return false; } @@ -2970,12 +2898,12 @@ struct DPCDHALImpl : DPCDHAL // 5. Set HDMI Enable Bit. data = 0; - if (AuxRetry::ack != bus.read(NV_DPCD20_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data))) + if (AuxRetry::ack != bus.read(NV_DPCD14_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data))) { return false; } - data = FLD_SET_DRF(_DPCD20, _PCON_FRL_LINK_CONFIG_1, _HDMI_LINK, _ENABLE, data); - if (AuxRetry::ack != bus.write(NV_DPCD20_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data))) + data = FLD_SET_DRF(_DPCD14, _PCON_FRL_LINK_CONFIG_1, _HDMI_LINK, _ENABLE, data); + if (AuxRetry::ack != bus.write(NV_DPCD14_PCON_FRL_LINK_CONFIG_1, &data, sizeof(data))) { return false; } @@ -3202,9 +3130,9 @@ struct DPCDHALImpl : DPCDHAL if (retVal) { psrEvt->sinkCapChange = DRF_VAL(_DPCD, - _PANEL_SELF_REFRESH_EVENT_STATUS, - _CAP_CHANGE, - config); + _PANEL_SELF_REFRESH_EVENT_STATUS, + _CAP_CHANGE, + config); } return retVal; } diff --git a/src/common/displayport/src/dp_connectorimpl.cpp b/src/common/displayport/src/dp_connectorimpl.cpp index 4ce6142d9..d0dd5401c 100644 --- a/src/common/displayport/src/dp_connectorimpl.cpp +++ b/src/common/displayport/src/dp_connectorimpl.cpp @@ -116,6 +116,7 @@ ConnectorImpl::ConnectorImpl(MainLink * main, AuxBus * auxBus, Timer * timer, Co bKeepOptLinkAlive(false), bNoFallbackInPostLQA(false), LT2FecLatencyMs(0), + bFECEnable(false), bDscCapBasedOnParent(false), ResStatus(this) { @@ -126,7 +127,6 @@ ConnectorImpl::ConnectorImpl(MainLink * main, AuxBus * auxBus, Timer * timer, Co constructorFailed = true; return; } - highestAssessedLC = getMaxLinkConfig(); firmwareGroup = createFirmwareGroup(); if (firmwareGroup == NULL) @@ -135,6 +135,9 @@ ConnectorImpl::ConnectorImpl(MainLink * main, AuxBus * auxBus, Timer * timer, Co return; } + main->queryGPUCapability(); + main->queryAndUpdateDfpParams(); + hal->setPC2Disabled(main->isPC2Disabled()); // @@ -149,10 +152,13 @@ ConnectorImpl::ConnectorImpl(MainLink * main, AuxBus * auxBus, Timer * timer, Co // Set if LTTPR training is supported per regKey hal->setLttprSupported(main->isLttprSupported()); + const DP_REGKEY_DATABASE& dpRegkeyDatabase = main->getRegkeyDatabase(); this->applyRegkeyOverrides(dpRegkeyDatabase); hal->applyRegkeyOverrides(dpRegkeyDatabase); + highestAssessedLC = getMaxLinkConfig(); + // Initialize DSC callbacks DSC_CALLBACK callback; callback.clientHandle = NULL; @@ -188,7 +194,6 @@ void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatab this->bDisableSSC = dpRegkeyDatabase.bSscDisabled; this->bEnableFastLT = dpRegkeyDatabase.bFastLinkTrainingEnabled; this->bDscMstCapBug3143315 = dpRegkeyDatabase.bDscMstCapBug3143315; - this->bEnableOuiRestoring = dpRegkeyDatabase.bEnableOuiRestoring; this->bPowerDownPhyBeforeD3 = dpRegkeyDatabase.bPowerDownPhyBeforeD3; } @@ -706,7 +711,7 @@ create: newDev->applyOUIOverrides(); - if (main->isEDP() && this->bEnableOuiRestoring) + if (main->isEDP()) { // Save Source OUI information for eDP. hal->getOuiSource(cachedSourceOUI, &cachedSourceModelName[0], @@ -1861,7 +1866,7 @@ void ConnectorImpl::populateDscCaps(DSC_INFO* dscInfo, DeviceImpl * dev, DSC_INF bool ConnectorImpl::endCompoundQuery() { - DP_ASSERT( compoundQueryActive && "Spurious compoundQuery end."); + DP_ASSERT(compoundQueryActive && "Spurious compoundQuery end."); compoundQueryActive = false; return compoundQueryResult; } @@ -1890,7 +1895,7 @@ void ConnectorImpl::releaseLinkHandsOff() { if (!isLinkQuiesced) { - DP_ASSERT(0 && "Link is already in use."); + DP_LOG(("DPCONN> Link is already in use.")); return; } @@ -2695,7 +2700,7 @@ bool ConnectorImpl::notifyAttachBegin(Group * target, // Gr this->bFECEnable |= bEnableFEC; highestAssessedLC.enableFEC(this->bFECEnable); - if (main->isEDP() && this->bEnableOuiRestoring) + if (main->isEDP()) { main->configurePowerState(true); hal->setOuiSource(cachedSourceOUI, &cachedSourceModelName[0], 6 /* string length of ieeeOuiDevId */, @@ -3130,8 +3135,6 @@ bool ConnectorImpl::trainPCONFrlLink(PCONLinkControl *pconControl) bool ConnectorImpl::assessPCONLinkCapability(PCONLinkControl *pConControl) { - NvU32 status; - if (pConControl == NULL || !this->previousPlugged) return false; @@ -3144,8 +3147,7 @@ bool ConnectorImpl::assessPCONLinkCapability(PCONLinkControl *pConControl) if (pConControl->flags.bSourceControlMode) { - status = trainPCONFrlLink(pConControl); - if (status == false) + if (trainPCONFrlLink(pConControl) == false) { // restore Autonomous mode and treat this as an active DP dongle. hal->resetProtocolConverter(); @@ -3156,12 +3158,17 @@ bool ConnectorImpl::assessPCONLinkCapability(PCONLinkControl *pConControl) bSkipAssessLinkForPCon = false; assessLink(); } - return status; + return false; } activePConLinkControl.flags = pConControl->flags; activePConLinkControl.frlHdmiBwMask = pConControl->frlHdmiBwMask; activePConLinkControl.result = pConControl->result; } + else + { + // restore Autonomous mode and treat this as an active DP dongle. + hal->resetProtocolConverter(); + } // Step 3: Assess DP Link capability. LinkConfiguration lConfig = getMaxLinkConfig(); @@ -3187,7 +3194,7 @@ bool ConnectorImpl::assessPCONLinkCapability(PCONLinkControl *pConControl) disableFlush(); this->bKeepLinkAliveForPCON = pConControl->flags.bKeepPCONLinkAlive; - return status; + return true; } bool ConnectorImpl::getOuiSink(unsigned &ouiId, char * modelName, size_t modelNameBufferSize, NvU8 & chipRevision) @@ -5651,7 +5658,7 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected) // Reset all settings for previous downstream device configInit(); - if (! hal->isAtLeastVersion(1, 0 ) ) + if (!hal->isAtLeastVersion(1, 0)) goto completed; DP_LOG(("DP> HPD v%d.%d", hal->getRevisionMajor(), hal->getRevisionMinor())); @@ -6913,7 +6920,6 @@ void ConnectorImpl::notifyGPUCapabilityChange() { // Query current GPU capabilities. main->queryGPUCapability(); - } void ConnectorImpl::notifyHBR2WAREngage() diff --git a/src/common/displayport/src/dp_deviceimpl.cpp b/src/common/displayport/src/dp_deviceimpl.cpp index b06c0c81a..0feb578e0 100644 --- a/src/common/displayport/src/dp_deviceimpl.cpp +++ b/src/common/displayport/src/dp_deviceimpl.cpp @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -94,6 +94,7 @@ DeviceImpl::DeviceImpl(DPCDHAL * hal, ConnectorImpl * connector, DeviceImpl * pa bIgnoreMsaCap(false), bIgnoreMsaCapCached(false), bSdpExtCapable(Indeterminate), + bAsyncSDPCapable(Indeterminate), bDscPassThroughColorFormatWar(false) { bandwidth.enum_path.dataValid = false; @@ -953,6 +954,53 @@ void DeviceImpl::applyOUIOverrides() } } +bool DeviceImpl::getAsyncSDPSupported() +{ + NvU8 byte = 0; + unsigned size = 0; + unsigned sizeCompleted; + unsigned nakReason = NakUndefined; + // + // On faked mux devices, we cannot check if the device has + // the capability as we don't have access to aux. + // + if (this->isFakedMuxDevice()) + { + return false; + } + // If the capability is queried/set already. + if (this->bAsyncSDPCapable != Indeterminate) + { + return (this->bAsyncSDPCapable == True); + } + // Check device capabilities first. + if (AuxBus::success != this->getDpcdData(NV_DPCD_DOWN_STREAM_PORT, &byte, + size, &sizeCompleted, &nakReason) || + (FLD_TEST_DRF(_DPCD, _DOWN_STREAM_PORT, _MSA_TIMING_PAR_IGNORED, _NO, byte))) + { + this->bAsyncSDPCapable = False; + return false; + } + if (AuxBus::success != this->getDpcdData(NV_DPCD14_DPRX_FEATURE_ENUM_LIST, &byte, + size, &sizeCompleted, &nakReason) || + (FLD_TEST_DRF(_DPCD14, _DPRX_FEATURE_ENUM_LIST, _ADAPTIVE_SYNC_SDP_SUPPORTED, _NO, byte))) + { + this->bAsyncSDPCapable = False; + return false; + } + if (this->isMultistream()) + { + // For MST devices, check root branch capability. + this->bAsyncSDPCapable = hal->getRootAsyncSDPSupported() ? True : False; + } + else + { + // For SST, it supports Async SDP once reaches here. + this->bAsyncSDPCapable = True; + } + return (this->bAsyncSDPCapable == True); +} + bool DeviceImpl::getSDPExtnForColorimetrySupported() { DeviceImpl *targetDevice = NULL; @@ -1279,7 +1327,9 @@ LinkConfiguration * DeviceImpl::inferLeafLink(unsigned * totalLinkSlots) if (nack.reason == NakDefer || nack.reason == NakTimeout) continue; - bandwidth.enum_path.total = bandwidth.enum_path.free = 0; + bandwidth.enum_path.total = 0; + bandwidth.enum_path.free = 0; + bandwidth.enum_path.availableStreams = 0; break; } else @@ -1287,6 +1337,8 @@ LinkConfiguration * DeviceImpl::inferLeafLink(unsigned * totalLinkSlots) bandwidth.enum_path.total = epr.reply.TotalPBN; bandwidth.enum_path.free = epr.reply.FreePBN; bandwidth.enum_path.bPathFECCapable = epr.reply.bFECCapability; + bandwidth.enum_path.availableStreams = epr.reply.availableStreams; + break; } } @@ -1601,11 +1653,10 @@ bool DeviceImpl::getPanelReplayStatus(PanelReplayStatus *pPrStatus) return true; } else - { + { return false; } } - bool DeviceImpl::getFECSupport() { NvU8 byte = 0; @@ -1796,7 +1847,7 @@ bool DeviceImpl::parseBranchSpecificDscCaps(const NvU8 *buffer, NvU32 bufferSize return false; } - dscCaps.branchDSCOverallThroughputMode0 = DRF_VAL(_DPCD20, _BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0, _VALUE, buffer[0x0]); + dscCaps.branchDSCOverallThroughputMode0 = DRF_VAL(_DPCD14, _BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0, _VALUE, buffer[0x0]); if (dscCaps.branchDSCOverallThroughputMode0 == 1) { dscCaps.branchDSCOverallThroughputMode0 = 680; @@ -1806,7 +1857,7 @@ bool DeviceImpl::parseBranchSpecificDscCaps(const NvU8 *buffer, NvU32 bufferSize dscCaps.branchDSCOverallThroughputMode0 = 600 + dscCaps.branchDSCOverallThroughputMode0 * 50; } - dscCaps.branchDSCOverallThroughputMode1 = DRF_VAL(_DPCD20, _BRANCH_DSC_OVERALL_THROUGHPUT_MODE_1, _VALUE, buffer[0x1]); + dscCaps.branchDSCOverallThroughputMode1 = DRF_VAL(_DPCD14, _BRANCH_DSC_OVERALL_THROUGHPUT_MODE_1, _VALUE, buffer[0x1]); if (dscCaps.branchDSCOverallThroughputMode1 == 1) { dscCaps.branchDSCOverallThroughputMode1 = 680; @@ -1816,7 +1867,7 @@ bool DeviceImpl::parseBranchSpecificDscCaps(const NvU8 *buffer, NvU32 bufferSize dscCaps.branchDSCOverallThroughputMode1 = 600 + dscCaps.branchDSCOverallThroughputMode1 * 50; } - dscCaps.branchDSCMaximumLineBufferWidth = DRF_VAL(_DPCD20, _BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH, _VALUE, buffer[0x2]); + dscCaps.branchDSCMaximumLineBufferWidth = DRF_VAL(_DPCD14, _BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH, _VALUE, buffer[0x2]); if (dscCaps.branchDSCMaximumLineBufferWidth != 0) { if (dscCaps.branchDSCMaximumLineBufferWidth >= 16) @@ -1857,8 +1908,10 @@ bool DeviceImpl::readAndParseBranchSpecificDSCCaps() unsigned nakReason = NakUndefined; NvU8 rawBranchSpecificDscCaps[3]; - if(AuxBus::success != this->getDpcdData(NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0, - &rawBranchSpecificDscCaps[0], sizeof(rawBranchSpecificDscCaps), &sizeCompleted, &nakReason)) + if(AuxBus::success != this->getDpcdData(NV_DPCD14_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0, + &rawBranchSpecificDscCaps[0], + sizeof(rawBranchSpecificDscCaps), + &sizeCompleted, &nakReason)) { return false; } @@ -1873,8 +1926,8 @@ void DeviceImpl::queryGUID2() Address::StringBuffer sb; DP_USED(sb); - if(AuxBus::success == this->getDpcdData(NV_DPCD20_GUID_2, - &this->guid2.data[0], DPCD_GUID_SIZE, &sizeCompleted, &nakReason)) + if(AuxBus::success == this->getDpcdData(NV_DPCD14_GUID_2, &this->guid2.data[0], + DPCD_GUID_SIZE, &sizeCompleted, &nakReason)) { if (!(this->guid2.isGuidZero())) { @@ -1940,8 +1993,8 @@ void DeviceImpl::setDscDecompressionDevice(bool bDscCapBasedOnParent) else { // - // Check the device's own and its parent's DSC capability. - // - Sink device will do DSC cecompression when + // Check the device's own and its parent's DSC capability. + // - Sink device will do DSC cecompression when // 1. Sink device is capable of DSC decompression // 2. Sink is on a logical port (8-15) // @@ -1951,7 +2004,7 @@ void DeviceImpl::setDscDecompressionDevice(bool bDscCapBasedOnParent) // 2. Parent of sink is a Virtual Peer device // 3. Parent of sink supports DSC Pass through // - // - Sink device's parent will do DSC decompression + // - Sink device's parent will do DSC decompression // 1. Above conditions are not true. // 2. Parent of sink supports DSC decompression. // @@ -1964,11 +2017,11 @@ void DeviceImpl::setDscDecompressionDevice(bool bDscCapBasedOnParent) this->devDoingDscDecompression = this; this->bDSCPossible = true; } - else if (this->parent->isVirtualPeerDevice() && + else if (this->parent->isVirtualPeerDevice() && this->parent->isDSCPassThroughSupported()) { // - // This condition takes care of DSC capable sink devices + // This condition takes care of DSC capable sink devices // connected behind a DSC Pass through capable branch // this->devDoingDscDecompression = this; @@ -1977,12 +2030,12 @@ void DeviceImpl::setDscDecompressionDevice(bool bDscCapBasedOnParent) else if (this->parent->isDSCSupported()) { // - // This condition takes care of DSC capable sink devices + // This condition takes care of DSC capable sink devices // connected behind a branch device that is not capable // of DSC pass through but can do DSC decompression. // this->bDSCPossible = true; - this->devDoingDscDecompression = this->parent; + this->devDoingDscDecompression = this->parent; } } else @@ -1991,11 +2044,11 @@ void DeviceImpl::setDscDecompressionDevice(bool bDscCapBasedOnParent) this->devDoingDscDecompression = this; this->bDSCPossible = true; } - } + } else if (this->parent && this->parent->isDSCSupported()) { // - // This condition takes care of sink devices not capable of DSC + // This condition takes care of sink devices not capable of DSC // but parent is capable of DSC decompression. // this->bDSCPossible = true; @@ -2015,7 +2068,7 @@ void DeviceImpl::setDscDecompressionDevice(bool bDscCapBasedOnParent) bool DeviceImpl::setDscEnable(bool enable) { - NvU8 dscEnableByte = 0; + NvU8 dscEnableByte = 0; NvU8 dscPassthroughByte = 0; unsigned size = 0; unsigned nakReason = NakUndefined; @@ -2036,8 +2089,8 @@ bool DeviceImpl::setDscEnable(bool enable) { // // If the device has a parent, that means the sink is on a MST link and - // and on a MST link if DSC is possible on the path and devDoingDscDecompression - // is the sink itself and sink is not on a logical port, then the parent should be + // and on a MST link if DSC is possible on the path and devDoingDscDecompression + // is the sink itself and sink is not on a logical port, then the parent should be // DSC Pass through capable. // bDscPassThrough = true; @@ -2047,7 +2100,7 @@ bool DeviceImpl::setDscEnable(bool enable) // Get Current DSC Enable State // Ideally we don't need to check the current state but Synaptics DSC device, // which was used for inital DSC code developement did not follow spec and so - // we have added this code. Overwriting the same value should not have any + // we have added this code. Overwriting the same value should not have any // impact as per the spec. Will remove this check once all DSC devices follow spec. // if (!getDscEnable(&bCurrDscEnable)) @@ -2060,7 +2113,7 @@ bool DeviceImpl::setDscEnable(bool enable) { if(bDscPassThrough) { - dscPassthroughByte = FLD_SET_DRF(_DPCD20, _DSC_PASS_THROUGH, _ENABLE, _YES, dscPassthroughByte); + dscPassthroughByte = FLD_SET_DRF(_DPCD20, _DSC_ENABLE, _PASS_THROUGH, _YES, dscPassthroughByte); DP_LOG(("DP-DEV> Enabling DSC Pass through on branch device - %s", this->parent->getTopologyAddress().toString(buffer))); } @@ -2073,7 +2126,7 @@ bool DeviceImpl::setDscEnable(bool enable) } else { - DP_LOG(("DP-DEV> DSC decompression is already enabled on device - %s", + DP_LOG(("DP-DEV> DSC decompression is already enabled on device - %s", this->devDoingDscDecompression->getTopologyAddress().toString(buffer))); } } @@ -2081,7 +2134,7 @@ bool DeviceImpl::setDscEnable(bool enable) { if(bDscPassThrough) { - dscPassthroughByte = FLD_SET_DRF(_DPCD20, _DSC_PASS_THROUGH, _ENABLE, _NO, dscPassthroughByte); + dscPassthroughByte = FLD_SET_DRF(_DPCD20, _DSC_ENABLE, _PASS_THROUGH, _NO, dscPassthroughByte); DP_LOG(("DP-DEV> Disabling DSC Pass through on branch device - %s", this->parent->getTopologyAddress().toString(buffer))); } @@ -2094,18 +2147,18 @@ bool DeviceImpl::setDscEnable(bool enable) } else { - DP_LOG(("DP-DEV> DSC decompression is already disabled on device - %s", + DP_LOG(("DP-DEV> DSC decompression is already disabled on device - %s", this->devDoingDscDecompression->getTopologyAddress().toString(buffer))); } } if (bDscPassThrough) { - dscPassThroughStatus = this->parent->setDpcdData(NV_DPCD20_DSC_PASS_THROUGH, + dscPassThroughStatus = this->parent->setDpcdData(NV_DPCD14_DSC_ENABLE, &dscPassthroughByte, sizeof dscPassthroughByte, &size, &nakReason); if (dscPassThroughStatus != AuxBus::success) { - DP_LOG(("DP-DEV> Setting DSC Passthrough on parent branch %s failed", + DP_LOG(("DP-DEV> Setting DSC Passthrough on parent branch %s failed", this->parent->getTopologyAddress().toString(buffer))); } } @@ -2116,9 +2169,9 @@ bool DeviceImpl::setDscEnable(bool enable) &dscEnableByte, sizeof dscEnableByte, &size, &nakReason); if (dscEnableStatus != AuxBus::success) { - DP_LOG(("DP-DEV> Setting DSC Enable on sink %s failed", + DP_LOG(("DP-DEV> Setting DSC Enable on sink %s failed", this->devDoingDscDecompression->getTopologyAddress().toString(buffer))); - + } } @@ -2136,7 +2189,7 @@ bool DeviceImpl::setDscEnable(bool enable) bool DeviceImpl::setDscEnableDPToHDMIPCON(bool bDscEnable, bool bEnablePassThroughForPCON) { - NvU8 dscEnableByte = 0; + NvU8 dscEnableByte = 0; unsigned size = 0; unsigned nakReason = NakUndefined; AuxBus::status dscEnableStatus = AuxBus::success; @@ -2153,7 +2206,7 @@ bool DeviceImpl::setDscEnableDPToHDMIPCON(bool bDscEnable, bool bEnablePassThrou { if(bEnablePassThroughForPCON) { - dscEnableByte = FLD_SET_DRF(_DPCD20, _DSC_PASS_THROUGH, _ENABLE, _YES, dscEnableByte); + dscEnableByte = FLD_SET_DRF(_DPCD20, _DSC_ENABLE, _PASS_THROUGH, _YES, dscEnableByte); DP_LOG(("DP-DEV> Enabling DSC Pass through on DP to HDMI PCON device - %s", this->getTopologyAddress().toString(buffer))); } @@ -2171,10 +2224,10 @@ bool DeviceImpl::setDscEnableDPToHDMIPCON(bool bDscEnable, bool bEnablePassThrou if (dscEnableStatus != AuxBus::success) { - DP_LOG(("DP-DEV> Setting DSC Enable on DP to HDMI PCON %s failed", + DP_LOG(("DP-DEV> Setting DSC Enable on DP to HDMI PCON %s failed", this->getTopologyAddress().toString(buffer))); return false; - + } return true; diff --git a/src/common/displayport/src/dp_edid.cpp b/src/common/displayport/src/dp_edid.cpp index 6a21db0fc..41f3ea917 100644 --- a/src/common/displayport/src/dp_edid.cpp +++ b/src/common/displayport/src/dp_edid.cpp @@ -193,9 +193,11 @@ Edid::Edid(): buffer() fallbackEdid = false; patchedChecksum = false; - // clear the WARFlags - _WARFlags temp = {0}; - WARFlags = temp; + // clear the WARFlags and WARData. + _WARFlags flagTemp = {0}; + _WARData dataTemp = {0}; + WARFlags = flagTemp; + WARData = dataTemp; } Edid::~Edid() diff --git a/src/common/displayport/src/dp_evoadapter.cpp b/src/common/displayport/src/dp_evoadapter.cpp index 7d55eefeb..ebc306347 100644 --- a/src/common/displayport/src/dp_evoadapter.cpp +++ b/src/common/displayport/src/dp_evoadapter.cpp @@ -94,7 +94,6 @@ const struct {NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE_SST, &dpRegkeyDatabase.bOptLinkKeptAliveSst, DP_REG_VAL_BOOL}, {NV_DP_REGKEY_FORCE_EDP_ILR, &dpRegkeyDatabase.bBypassEDPRevCheck, DP_REG_VAL_BOOL}, {NV_DP_DSC_MST_CAP_BUG_3143315, &dpRegkeyDatabase.bDscMstCapBug3143315, DP_REG_VAL_BOOL}, - {NV_DP_REGKEY_ENABLE_OUI_RESTORING, &dpRegkeyDatabase.bEnableOuiRestoring, DP_REG_VAL_BOOL}, {NV_DP_REGKEY_POWER_DOWN_PHY, &dpRegkeyDatabase.bPowerDownPhyBeforeD3, DP_REG_VAL_BOOL} }; @@ -117,9 +116,6 @@ EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) : _isLTPhyRepeaterSupported = true; _rmPhyRepeaterCount = 0; dpMemZero(&_DSC, sizeof(_DSC)); - queryGPUCapability(); - - queryAndUpdateDfpParams(); // // Tell RM to hands off on the DisplayPort hardware @@ -1162,8 +1158,12 @@ bool EvoMainLink::train(const LinkConfiguration & link, bool force, // 1. CR or EQ phase failed. // 2. The request link bandwidth is NOT RBR // + if (!requestRmLC.lowerConfig()) + { + // If no valid link config could be found, break here. + break; + } fallback = true; - requestRmLC.lowerConfig(); } else { diff --git a/src/common/displayport/src/dp_messagecodings.cpp b/src/common/displayport/src/dp_messagecodings.cpp index ac5ad7a17..20f98d829 100644 --- a/src/common/displayport/src/dp_messagecodings.cpp +++ b/src/common/displayport/src/dp_messagecodings.cpp @@ -227,11 +227,11 @@ EnumPathResMessage::EnumPathResMessage(const Address & target, unsigned port, bo ParseResponseStatus EnumPathResMessage::parseResponseAck(EncodedMessage * message, BitStreamReader * reader) { - reply.portNumber = reader->readOrDefault(4 /*Port_Number*/, 0xF); - reader->readOrDefault(3 /*zeroes*/, 0); - reply.bFECCapability = (reader->readOrDefault(1 /*FEC*/, 0x0) == 1) ? true : false; - reply.TotalPBN = reader->readOrDefault(16 /*PBN*/, 0xFFFF); - reply.FreePBN = reader->readOrDefault(16 /*PBN*/, 0xFFFF); + reply.portNumber = reader->readOrDefault(4 /*Port_Number*/, 0xF); + reply.availableStreams = reader->readOrDefault(3 /*Available_Streams*/, 0); + reply.bFECCapability = (reader->readOrDefault(1 /*FEC*/, 0x0) == 1) ? true : false; + reply.TotalPBN = reader->readOrDefault(16 /*PBN*/, 0xFFFF); + reply.FreePBN = reader->readOrDefault(16 /*PBN*/, 0xFFFF); if (this->getSinkPort() != reply.portNumber) return ParseResponseWrong; @@ -353,10 +353,11 @@ bool ResStatusNotifyMessage::processByType(EncodedMessage * message, BitStreamRe bool status; // read the request body - request.port = reader->readOrDefault(4/*Port_Number*/, 0xF); - reader->readOrDefault(4/*zeroes*/, 0); - status = DisplayPort::extractGUID(reader, &request.guid); - request.PBN = reader->readOrDefault(16/*Available_PBN*/, 0); + request.port = reader->readOrDefault(4 /*Port_Number*/, 0xF); + request.availableStreams = reader->readOrDefault(3 /*Available_Streams*/, 0); + request.bFECCapability = reader->readOrDefault(1 /*FEC Capability*/, 0); + status = DisplayPort::extractGUID(reader, &request.guid); + request.PBN = reader->readOrDefault(16/*Available_PBN*/, 0); // action will be implemented by evensink this->sink->messageProcessed(this); diff --git a/src/common/inc/displayport/dpcd14.h b/src/common/inc/displayport/dpcd14.h index 8610a96bb..3b57df8f1 100644 --- a/src/common/inc/displayport/dpcd14.h +++ b/src/common/inc/displayport/dpcd14.h @@ -24,6 +24,8 @@ #ifndef _DISPLAYPORT14_H_ #define _DISPLAYPORT14_H_ +#define NV_DPCD14_GUID_2 (0x00000040) /* R-XUR */ + #define NV_DPCD14_EXTEND_CAP_BASE (0x00002200) #define NV_DPCD14_MAX_LINK_BANDWIDTH (0x00000001) /* R-XUR */ @@ -187,11 +189,6 @@ #define NV_DPCD14_DSC_BITS_PER_PIXEL_INCREMENT_SUPPORTED_1_2 (0x00000003) /* R-XUV */ #define NV_DPCD14_DSC_BITS_PER_PIXEL_INCREMENT_SUPPORTED_1 (0x00000004) /* R-XUV */ -// Field definition only used only with 128b/132b for DP2.0+ -#define NV_DPCD20_TRAINING_LANE_SET(i) (0x00000103+(i)) /* RW-1A */ -#define NV_DPCD20_TRAINING_LANE_SET__SIZE 4 /* RW--S */ -#define NV_DPCD20_TRAINING_LANE_SET_TX_FFE_PRESET_VALUE 3:0 /* RWXUF */ - #define NV_DPCD14_DSC_ENABLE (0x00000160) /* R-XUR */ #define NV_DPCD14_DSC_ENABLE_SINK 0:0 /* R-XUF */ #define NV_DPCD14_DSC_ENABLE_SINK_NO (0x00000000) /* R-XUV */ @@ -239,15 +236,6 @@ #define NV_DPCD14_TRAINING_PATTERN_SET_SYM_ERR_SEL_DISPARITY_ERROR (0x00000001) /* RWXUV */ #define NV_DPCD14_TRAINING_PATTERN_SET_SYM_ERR_SEL_ILLEGAL_SYMBOL_ERROR (0x00000002) /* RWXUV */ -// Field definition only used only with 128b/132b for DP2.0+ -#define NV_DPCD20_128B_132B_TRAINING_PATTERN (0x00000102) /* RWXUR */ -#define NV_DPCD20_128B_132B_TRAINING_PATTERN_SELECT 3:0 /* RWXUF */ -#define NV_DPCD20_128B_132B_TRAINING_PATTERN_SELECT_NONE (0x00000000) /* RWXUV */ -#define NV_DPCD20_128B_132B_TRAINING_PATTERN_SELECT_TPS1 (0x00000001) /* RWXUV */ -#define NV_DPCD20_128B_132B_TRAINING_PATTERN_SELECT_TPS2 (0x00000002) /* RWXUV */ -#define NV_DPCD20_128B_132B_TRAINING_PATTERN_SELECT_TPS2_CDS (0x00000003) /* RWXUV */ -// Note: Bit 7:4 are reserved for 128b/132b. Driver should keep them 0 - #define NV_DPCD14_LINK_QUAL_LANE_SET(i) (0x0000010B+(i)) /* RW-1A */ #define NV_DPCD14_LINK_QUAL_LANE_SET__SIZE 4 /* R---S */ #define NV_DPCD14_LINK_QUAL_LANE_SET_LQS 2:0 /* RWXUF */ @@ -270,36 +258,6 @@ #define NV_DPCD14_FEC_CONFIGURATION_LANE_SELECT_LANE_2 (0x00000002) /* RWXUV */ #define NV_DPCD14_FEC_CONFIGURATION_LANE_SELECT_LANE_3 (0x00000003) /* RWXUV */ -// Field definition only used only with 128b/132b for DP2.0+ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED (0x00000204) /* R-XUR */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE 2:2 /* R-XUF */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE_YES (0x00000001) /* R-XUV */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE 3:3 /* R-XUF */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE_YES (0x00000001) /* R-XUV */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_LT_FAILED 4:4 /* R-XUF */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_LT_FAILED_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_LT_FAILED_YES (0x00000001) /* R-XUV */ - -// Field definition for 0x0206/0x0207h (ADJUST_REQUEST_LANEX), only used only with 128b/132b for DP2.0+ -#define NV_DPCD20_LANEX_XPLUS1_ADJUST_REQ_LANEX_TX_FFE_PRESET_VALUE 3:0 /* R-XUF */ -#define NV_DPCD20_LANEX_XPLUS1_ADJUST_REQ_LANEXPLUS1_TX_FFE_PRESET_VALUE 7:4 /* R-XUF */ - -// PANEL REPLAY RELATED DPCD -#define NV_DPCD20_PANEL_REPLAY_CAPABILITY (0x000000B0) -#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SUPPORTED 0:0 -#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SUPPORTED_NO (0x00000000) -#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SUPPORTED_YES (0x00000001) -#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SEL_UPDATE 1:1 -#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SEL_UPDATE_NO (0x00000000) -#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SEL_UPDATE_YES (0x00000001) - -#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION (0x000001B0) -#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE 0:0 -#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE_NO (0x00000000) -#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE_YES (0x00000001) - #define NV_DPCD14_PHY_TEST_PATTERN (0x00000248) /* R-XUR */ #define NV_DPCD14_PHY_TEST_PATTERN_SEL_CP2520PAT3 (0x00000007) /* R-XUV */ @@ -334,24 +292,6 @@ #define NV_DPCD14_FW_SW_REVISION_MAJOR (0x0000040A) /* R-XUR */ #define NV_DPCD14_FW_SW_REVISION_MINOR (0x0000040B) /* R-XUR */ -// Field definition for 0x0200E (LANE_ALIGN_STATUS_UPDATED_ESI), used only when DP2.0+ 128b/132b is enabled. -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI (0x0000200E) /* R-XUR */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE 2:2 /* R-XUF */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE_YES (0x00000001) /* R-XUV */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE 3:3 /* R-XUF */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE_YES (0x00000001) /* R-XUV */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_LT_FAILED 4:4 /* R-XUF */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_LT_FAILED_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_LT_FAILED_YES (0x00000001) /* R-XUV */ - -// Field definition for 0x0200F (SINK_STATUS_ESI), used only when DP2.0+ 128b/132b is enabled. -#define NV_DPCD20_SINK_STATUS_ESI (0x0000200F) /* R-XUR */ -#define NV_DPCD20_SINK_STATUS_ESI_INTRA_HOP_AUX_REPLY 3:3 /* R-XUF */ -#define NV_DPCD20_SINK_STATUS_ESI_INTRA_HOP_AUX_REPLY_DPRX (0x00000000) /* R-XUV */ -#define NV_DPCD20_SINK_STATUS_ESI_INTRA_HOP_AUX_REPLY_LTTPR (0x00000001) /* R-XUV */ - #define NV_DPCD14_EXTENDED_REV (0x00002200) /* R-XUR */ #define NV_DPCD14_EXTENDED_REV_MAJOR 7:4 /* R-XUF */ #define NV_DPCD14_EXTENDED_REV_MAJOR_1 (0x00000001) /* R-XUV */ @@ -532,98 +472,76 @@ #define NV_DPCD14_DPRX_FEATURE_ENUM_LIST_VSC_EXT_FRAMEWORK_V1_SUPPORTED_NO (0x00000000) /* R-XUV */ #define NV_DPCD14_DPRX_FEATURE_ENUM_LIST_VSC_EXT_FRAMEWORK_V1_SUPPORTED_YES (0x00000001) /* R-XUV */ -#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES (0x00002215) /* R-XUR */ -#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR10 0:0 /* R-XUF */ -#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR10_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR10_YES (0x00000001) /* R-XUV */ -#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR20 1:1 /* R-XUF */ -#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR20_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR20_YES (0x00000001) /* R-XUV */ -#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR13_5 2:2 /* R-XUF */ -#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR13_5_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR13_5_YES (0x00000001) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS (0x00003036) /* R-XUR */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_MODE 0:0 /* R-XUF */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_MODE_TMDS (0x00000000) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_MODE_FRL (0x00000001) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RESULT 6:1 /* R-XUF */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_9G 1:1 /* R-XUF */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_9G_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_9G_YES (0x00000001) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_18G 2:2 /* R-XUF */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_18G_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_18G_YES (0x00000001) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_24G 3:3 /* R-XUF */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_24G_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_24G_YES (0x00000001) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_32G 4:4 /* R-XUF */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_32G_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_32G_YES (0x00000001) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_40G 5:5 /* R-XUF */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_40G_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_40G_YES (0x00000001) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_48G 6:6 /* R-XUF */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_48G_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_48G_YES (0x00000001) /* R-XUV */ -// -// The interval is (128b/132b_TRAINING_AUX_RD_INTERVAL value + 1) * INTERVAL_UNIT. -// The maximum is 256 ms. -// -#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL (0x00002216) /* R-XUR */ -#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL_VAL 6:0 /* R-XUF */ -#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL_UNIT 7:7 /* R-XUF */ -#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL_UNIT_2MS (0x00000000) /* R-XUV */ -#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL_UNIT_1MS (0x00000001) /* R-XUV */ -#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL_MAX_MS 256 +#define NV_DPCD14_PCON_DOWNSTREAM_LINK_ERROR_LANE(i) (0x00003037+(i)) /* RW-1A */ +#define NV_DPCD14_PCON_DOWNSTREAM_LINK_ERROR_LANE__SIZE 4 /* R---S */ +#define NV_DPCD14_PCON_DOWNSTREAM_LINK_ERROR_LANE_COUNT 3:0 /* R-XUF */ +#define NV_DPCD14_PCON_DOWNSTREAM_LINK_ERROR_LANE_COUNT_ZERO (0x00000000) /* R-XUV */ +#define NV_DPCD14_PCON_DOWNSTREAM_LINK_ERROR_LANE_COUNT_THREE (0x00000001) /* R-XUV */ +#define NV_DPCD14_PCON_DOWNSTREAM_LINK_ERROR_LANE_COUNT_TEN (0x00000002) /* R-XUV */ +#define NV_DPCD14_PCON_DOWNSTREAM_LINK_ERROR_LANE_COUNT_HUNDRED (0x00000004) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS (0x00003036) /* R-XUR */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_MODE 0:0 /* R-XUF */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_MODE_TMDS (0x00000000) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_MODE_FRL (0x00000001) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RESULT 6:1 /* R-XUF */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_9G 1:1 /* R-XUF */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_9G_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_9G_YES (0x00000001) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_18G 2:2 /* R-XUF */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_18G_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_18G_YES (0x00000001) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_24G 3:3 /* R-XUF */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_24G_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_24G_YES (0x00000001) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_32G 4:4 /* R-XUF */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_32G_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_32G_YES (0x00000001) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_40G 5:5 /* R-XUF */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_40G_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_40G_YES (0x00000001) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_48G 6:6 /* R-XUF */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_48G_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_48G_YES (0x00000001) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_TX_LINK_STATUS (0x0000303B) /* R-XUR */ +#define NV_DPCD14_PCON_HDMI_TX_LINK_STATUS_LINK_ACTIVE 0:0 /* R-XUF */ +#define NV_DPCD14_PCON_HDMI_TX_LINK_STATUS_LINK_ACTIVE_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_TX_LINK_STATUS_LINK_ACTIVE_YES (0x00000001) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_TX_LINK_STATUS_LINK_READY 1:1 /* R-XUF */ +#define NV_DPCD14_PCON_HDMI_TX_LINK_STATUS_LINK_READY_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_PCON_HDMI_TX_LINK_STATUS_LINK_READY_YES (0x00000001) /* R-XUV */ -#define NV_DPCD20_PCON_DOWNSTREAM_LINK_ERROR_LANE(i) (0x00003037+(i)) /* RW-1A */ -#define NV_DPCD20_PCON_DOWNSTREAM_LINK_ERROR_LANE__SIZE 4 /* R---S */ -#define NV_DPCD20_PCON_DOWNSTREAM_LINK_ERROR_LANE_COUNT 3:0 /* R-XUF */ -#define NV_DPCD20_PCON_DOWNSTREAM_LINK_ERROR_LANE_COUNT_ZERO (0x00000000) /* R-XUV */ -#define NV_DPCD20_PCON_DOWNSTREAM_LINK_ERROR_LANE_COUNT_THREE (0x00000001) /* R-XUV */ -#define NV_DPCD20_PCON_DOWNSTREAM_LINK_ERROR_LANE_COUNT_TEN (0x00000002) /* R-XUV */ -#define NV_DPCD20_PCON_DOWNSTREAM_LINK_ERROR_LANE_COUNT_HUNDRED (0x00000004) /* R-XUV */ +#define NV_DPCD14_PCON_CONTROL_0 (0x00003050) /* RWXUR */ +#define NV_DPCD14_PCON_CONTROL_0_OUTPUT_CONFIG 0:0 /* RWXUF */ +#define NV_DPCD14_PCON_CONTROL_0_OUTPUT_CONFIG_DVI (0x00000000) /* RWXUV */ +#define NV_DPCD14_PCON_CONTROL_0_OUTPUT_CONFIG_HDMI (0x00000001) /* RWXUV */ -#define NV_DPCD20_PCON_HDMI_TX_LINK_STATUS (0x0000303B) /* R-XUR */ -#define NV_DPCD20_PCON_HDMI_TX_LINK_STATUS_LINK_ACTIVE 0:0 /* R-XUF */ -#define NV_DPCD20_PCON_HDMI_TX_LINK_STATUS_LINK_ACTIVE_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_TX_LINK_STATUS_LINK_ACTIVE_YES (0x00000001) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_TX_LINK_STATUS_LINK_READY 1:1 /* R-XUF */ -#define NV_DPCD20_PCON_HDMI_TX_LINK_STATUS_LINK_READY_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_PCON_HDMI_TX_LINK_STATUS_LINK_READY_YES (0x00000001) /* R-XUV */ +#define NV_DPCD14_PCON_CONTROL_1 (0x00003051) /* RWXUR */ +#define NV_DPCD14_PCON_CONTROL_1_CONVERT_YCBCR420 0:0 /* RWXUF */ +#define NV_DPCD14_PCON_CONTROL_1_CONVERT_YCBCR420_DISABLE (0x00000000) /* RWXUV */ +#define NV_DPCD14_PCON_CONTROL_1_CONVERT_YCBCR420_ENABLE (0x00000001) /* RWXUV */ +#define NV_DPCD14_PCON_CONTROL_1_DISABLE_HDMI_EDID_PROCESS 1:1 /* RWXUF */ +#define NV_DPCD14_PCON_CONTROL_1_DISABLE_HDMI_EDID_PROCESS_NO (0x00000000) /* RWXUV */ +#define NV_DPCD14_PCON_CONTROL_1_DISABLE_HDMI_EDID_PROCESS_YES (0x00000001) /* RWXUV */ +#define NV_DPCD14_PCON_CONTROL_1_DISABLE_HDMI_AUTO_SCRAMBLING 2:2 /* RWXUF */ +#define NV_DPCD14_PCON_CONTROL_1_DISABLE_HDMI_AUTO_SCRAMBLING_NO (0x00000000) /* RWXUV */ +#define NV_DPCD14_PCON_CONTROL_1_DISABLE_HDMI_AUTO_SCRAMBLING_YES (0x00000001) /* RWXUV */ +#define NV_DPCD14_PCON_CONTROL_1_DISABLE_HDMI_FORCE_SCRAMBLING 3:3 /* RWXUF */ +#define NV_DPCD14_PCON_CONTROL_1_DISABLE_HDMI_FORCE_SCRAMBLING_NO (0x00000000) /* RWXUV */ +#define NV_DPCD14_PCON_CONTROL_1_DISABLE_HDMI_FORCE_SCRAMBLING_YES (0x00000001) /* RWXUV */ -#define NV_DPCD20_PCON_CONTROL_0 (0x00003050) /* RWXUR */ -#define NV_DPCD20_PCON_CONTROL_0_OUTPUT_CONFIG 0:0 /* RWXUF */ -#define NV_DPCD20_PCON_CONTROL_0_OUTPUT_CONFIG_DVI (0x00000000) /* RWXUV */ -#define NV_DPCD20_PCON_CONTROL_0_OUTPUT_CONFIG_HDMI (0x00000001) /* RWXUV */ +#define NV_DPCD14_PCON_CONTROL_2 (0x00003052) /* RWXUR */ +#define NV_DPCD14_PCON_CONTROL_2_CONVERT_YCBCR422 0:0 /* RWXUF */ +#define NV_DPCD14_PCON_CONTROL_2_CONVERT_YCBCR422_DISABLE (0x00000000) /* RWXUV */ +#define NV_DPCD14_PCON_CONTROL_2_CONVERT_YCBCR422_ENABLE (0x00000001) /* RWXUV */ -#define NV_DPCD20_PCON_CONTROL_1 (0x00003051) /* RWXUR */ -#define NV_DPCD20_PCON_CONTROL_1_CONVERT_YCBCR420 0:0 /* RWXUF */ -#define NV_DPCD20_PCON_CONTROL_1_CONVERT_YCBCR420_DISABLE (0x00000000) /* RWXUV */ -#define NV_DPCD20_PCON_CONTROL_1_CONVERT_YCBCR420_ENABLE (0x00000001) /* RWXUV */ -#define NV_DPCD20_PCON_CONTROL_1_DISABLE_HDMI_EDID_PROCESS 1:1 /* RWXUF */ -#define NV_DPCD20_PCON_CONTROL_1_DISABLE_HDMI_EDID_PROCESS_NO (0x00000000) /* RWXUV */ -#define NV_DPCD20_PCON_CONTROL_1_DISABLE_HDMI_EDID_PROCESS_YES (0x00000001) /* RWXUV */ -#define NV_DPCD20_PCON_CONTROL_1_DISABLE_HDMI_AUTO_SCRAMBLING 2:2 /* RWXUF */ -#define NV_DPCD20_PCON_CONTROL_1_DISABLE_HDMI_AUTO_SCRAMBLING_NO (0x00000000) /* RWXUV */ -#define NV_DPCD20_PCON_CONTROL_1_DISABLE_HDMI_AUTO_SCRAMBLING_YES (0x00000001) /* RWXUV */ -#define NV_DPCD20_PCON_CONTROL_1_DISABLE_HDMI_FORCE_SCRAMBLING 3:3 /* RWXUF */ -#define NV_DPCD20_PCON_CONTROL_1_DISABLE_HDMI_FORCE_SCRAMBLING_NO (0x00000000) /* RWXUV */ -#define NV_DPCD20_PCON_CONTROL_1_DISABLE_HDMI_FORCE_SCRAMBLING_YES (0x00000001) /* RWXUV */ - -#define NV_DPCD20_PCON_CONTROL_2 (0x00003052) /* RWXUR */ -#define NV_DPCD20_PCON_CONTROL_2_CONVERT_YCBCR422 0:0 /* RWXUF */ -#define NV_DPCD20_PCON_CONTROL_2_CONVERT_YCBCR422_DISABLE (0x00000000) /* RWXUV */ -#define NV_DPCD20_PCON_CONTROL_2_CONVERT_YCBCR422_ENABLE (0x00000001) /* RWXUV */ - -#define NV_DPCD20_PCON_CONTROL_3 (0x00003053) /* RWXUR */ -#define NV_DPCD20_PCON_CONTROL_3_COMPONENT_BIT_DEPTH 1:0 /* RWXUF */ -#define NV_DPCD20_PCON_CONTROL_3_COMPONENT_BIT_DEPTH_SAME_AS_INC (0x00000000) /* RWXUV */ -#define NV_DPCD20_PCON_CONTROL_3_COMPONENT_BIT_DEPTH_8BPC (0x00000001) /* RWXUV */ -#define NV_DPCD20_PCON_CONTROL_3_COMPONENT_BIT_DEPTH_10BPC (0x00000002) /* RWXUV */ -#define NV_DPCD20_PCON_CONTROL_3_COMPONENT_BIT_DEPTH_12BPC (0x00000003) /* RWXUV */ +#define NV_DPCD14_PCON_CONTROL_3 (0x00003053) /* RWXUR */ +#define NV_DPCD14_PCON_CONTROL_3_COMPONENT_BIT_DEPTH 1:0 /* RWXUF */ +#define NV_DPCD14_PCON_CONTROL_3_COMPONENT_BIT_DEPTH_SAME_AS_INC (0x00000000) /* RWXUV */ +#define NV_DPCD14_PCON_CONTROL_3_COMPONENT_BIT_DEPTH_8BPC (0x00000001) /* RWXUV */ +#define NV_DPCD14_PCON_CONTROL_3_COMPONENT_BIT_DEPTH_10BPC (0x00000002) /* RWXUV */ +#define NV_DPCD14_PCON_CONTROL_3_COMPONENT_BIT_DEPTH_12BPC (0x00000003) /* RWXUV */ #define NV_DPCD14_OUTPUT_HTOTAL_LOW (0x00003054) /* RWXUR */ #define NV_DPCD14_OUTPUT_HTOTAL_HIGH (0x00003055) /* RWXUR */ @@ -638,42 +556,42 @@ #define NV_DPCD14_OUTPUT_HSP_HSW_HIGH_OUTPUT_HSP_POSITIVE (0x00000000) /* RWXUV */ #define NV_DPCD14_OUTPUT_HSP_HSW_HIGH_OUTPUT_HSP_NEGATIVE (0x00000001) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1 (0x0000305A) /* RWXUR */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW 2:0 /* RWXUF */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_ZERO (0x00000000) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_9G (0x00000001) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_18G (0x00000002) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_24G (0x00000003) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_32G (0x00000004) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_40G (0x00000005) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_48G (0x00000006) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_SRC_CONTROL_MODE 3:3 /* RWXUF */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_SRC_CONTROL_MODE_DISABLE (0x00000000) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_SRC_CONTROL_MODE_ENABLE (0x00000001) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_CONCURRENT_LT_MODE 4:4 /* RWXUF */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_CONCURRENT_LT_MODE_DISABLE (0x00000000) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_CONCURRENT_LT_MODE_ENABLE (0x00000001) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_LINK_FRL_MODE 5:5 /* RWXUF */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_LINK_FRL_MODE_DISABLE (0x00000000) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_LINK_FRL_MODE_ENABLE (0x00000001) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_IRQ_LINK_FRL_MODE 6:6 /* RWXUF */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_IRQ_LINK_FRL_MODE_DISABLE (0x00000000) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_IRQ_LINK_FRL_MODE_ENABLE (0x00000001) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_HDMI_LINK 7:7 /* RWXUF */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_HDMI_LINK_DISABLE (0x00000000) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_HDMI_LINK_ENABLE (0x00000001) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1 (0x0000305A) /* RWXUR */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW 2:0 /* RWXUF */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_ZERO (0x00000000) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_9G (0x00000001) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_18G (0x00000002) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_24G (0x00000003) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_32G (0x00000004) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_40G (0x00000005) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_48G (0x00000006) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_SRC_CONTROL_MODE 3:3 /* RWXUF */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_SRC_CONTROL_MODE_DISABLE (0x00000000) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_SRC_CONTROL_MODE_ENABLE (0x00000001) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_CONCURRENT_LT_MODE 4:4 /* RWXUF */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_CONCURRENT_LT_MODE_DISABLE (0x00000000) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_CONCURRENT_LT_MODE_ENABLE (0x00000001) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_LINK_FRL_MODE 5:5 /* RWXUF */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_LINK_FRL_MODE_DISABLE (0x00000000) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_LINK_FRL_MODE_ENABLE (0x00000001) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_IRQ_LINK_FRL_MODE 6:6 /* RWXUF */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_IRQ_LINK_FRL_MODE_DISABLE (0x00000000) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_IRQ_LINK_FRL_MODE_ENABLE (0x00000001) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_HDMI_LINK 7:7 /* RWXUF */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_HDMI_LINK_DISABLE (0x00000000) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_1_HDMI_LINK_ENABLE (0x00000001) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2 (0x0000305B) /* RWXUR */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK 5:0 /* RWXUF */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK_9G (0x00000001) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK_18G (0x00000002) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK_24G (0x00000004) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK_32G (0x00000008) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK_40G (0x00000010) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK_48G (0x00000020) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2_FRL_LT_CONTROL 6:6 /* RWXUF */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2_FRL_LT_CONTROL_NORMAL (0x00000000) /* RWXUV */ -#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2_FRL_LT_CONTROL_EXTENDED (0x00000001) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_2 (0x0000305B) /* RWXUR */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK 5:0 /* RWXUF */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK_9G (0x00000001) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK_18G (0x00000002) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK_24G (0x00000004) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK_32G (0x00000008) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK_40G (0x00000010) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK_48G (0x00000020) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_2_FRL_LT_CONTROL 6:6 /* RWXUF */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_2_FRL_LT_CONTROL_NORMAL (0x00000000) /* RWXUV */ +#define NV_DPCD14_PCON_FRL_LINK_CONFIG_2_FRL_LT_CONTROL_EXTENDED (0x00000001) /* RWXUV */ // LT Tunable Repeater Related offsets @@ -790,5 +708,15 @@ #define NV_DPCD14_ADJUST_REQUEST_LANE0_1_PHY_REPEATER (0x00000023) /* R-XUR */ #define NV_DPCD14_ADJUST_REQUEST_LANE2_3_PHY_REPEATER (0x00000024) /* R-XUR */ +// BRANCH SPECIFIC DSC CAPS +#define NV_DPCD14_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0 (0x000000A0) +#define NV_DPCD14_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0_VALUE 7:0 + +#define NV_DPCD14_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_1 (0x000000A1) +#define NV_DPCD14_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_1_VALUE 7:0 + +#define NV_DPCD14_BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH (0x000000A2) +#define NV_DPCD14_BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH_VALUE 7:0 + #endif // #ifndef _DISPLAYPORT14_H_ diff --git a/src/common/inc/displayport/dpcd20.h b/src/common/inc/displayport/dpcd20.h index 29ce9a750..a6c49a3c2 100644 --- a/src/common/inc/displayport/dpcd20.h +++ b/src/common/inc/displayport/dpcd20.h @@ -21,17 +21,16 @@ * DEALINGS IN THE SOFTWARE. */ -#define NV_DPCD20_DSC_SUPPORT (0x00000060) /* R-XUR */ +#include "nvcfg_sdk.h" + +// DSC Pass Through related DPCD. New bits in DPCD 0x0060h defined in DPCD2.0. #define NV_DPCD20_DSC_SUPPORT_PASS_THROUGH_SUPPORT 1:1 /* R-XUF */ #define NV_DPCD20_DSC_SUPPORT_PASS_THROUGH_SUPPORT_NO (0x00000000) /* R-XUV */ #define NV_DPCD20_DSC_SUPPORT_PASS_THROUGH_SUPPORT_YES (0x00000001) /* R-XUV */ - -#define NV_DPCD20_DSC_PASS_THROUGH (0x00000160) /* R-XUR */ -#define NV_DPCD20_DSC_PASS_THROUGH_ENABLE 1:1 /* R-XUF */ -#define NV_DPCD20_DSC_PASS_THROUGH_ENABLE_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_DSC_PASS_THROUGH_ENABLE_YES (0x00000001) /* R-XUV */ - -#define NV_DPCD20_GUID_2 (0x00000040) /* R-XUR */ +// DSC Pass Through related DPCD. New bits in DPCD 0x0160h defined in DPCD2.0. +#define NV_DPCD20_DSC_ENABLE_PASS_THROUGH 1:1 /* R-XUF */ +#define NV_DPCD20_DSC_ENABLE_PASS_THROUGH_NO (0x00000000) /* R-XUV */ +#define NV_DPCD20_DSC_ENABLE_PASS_THROUGH_YES (0x00000001) /* R-XUV */ // PANEL REPLAY RELATED DPCD #define NV_DPCD20_PANEL_REPLAY_CAPABILITY (0x000000B0) @@ -59,12 +58,3 @@ #define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_GOVERNING (0x00000002) #define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_RELOCKING (0x00000003) -// BRANCH SPECIFIC DSC CAPS -#define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0 (0x000000A0) -#define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0_VALUE 7:0 - -#define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_1 (0x000000A1) -#define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_1_VALUE 7:0 - -#define NV_DPCD20_BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH (0x000000A2) -#define NV_DPCD20_BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH_VALUE 7:0 diff --git a/src/common/inc/nvBldVer.h b/src/common/inc/nvBldVer.h index 9374a8823..46db9eddb 100644 --- a/src/common/inc/nvBldVer.h +++ b/src/common/inc/nvBldVer.h @@ -36,26 +36,26 @@ // and then checked back in. You cannot make changes to these sections without // corresponding changes to the buildmeister script #ifndef NV_BUILD_BRANCH - #define NV_BUILD_BRANCH r528_37 + #define NV_BUILD_BRANCH r530_99 #endif #ifndef NV_PUBLIC_BRANCH - #define NV_PUBLIC_BRANCH r528_37 + #define NV_PUBLIC_BRANCH r530_99 #endif #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) -#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r525/r528_37-265" -#define NV_BUILD_CHANGELIST_NUM (32376659) +#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r530/r530_99-89" +#define NV_BUILD_CHANGELIST_NUM (32484765) #define NV_BUILD_TYPE "Official" -#define NV_BUILD_NAME "rel/gpu_drv/r525/r528_37-265" -#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32376659) +#define NV_BUILD_NAME "rel/gpu_drv/r530/r530_99-89" +#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32484765) #else /* Windows builds */ -#define NV_BUILD_BRANCH_VERSION "r528_37-4" -#define NV_BUILD_CHANGELIST_NUM (32375411) +#define NV_BUILD_BRANCH_VERSION "r530_99-8" +#define NV_BUILD_CHANGELIST_NUM (32470325) #define NV_BUILD_TYPE "Official" -#define NV_BUILD_NAME "528.46" -#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32375411) -#define NV_BUILD_BRANCH_BASE_VERSION R525 +#define NV_BUILD_NAME "531.08" +#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32470325) +#define NV_BUILD_BRANCH_BASE_VERSION R530 #endif // End buildmeister python edited section diff --git a/src/common/inc/nvPNPVendorIds.h b/src/common/inc/nvPNPVendorIds.h index 8c0ae38e4..7aaf73e5d 100644 --- a/src/common/inc/nvPNPVendorIds.h +++ b/src/common/inc/nvPNPVendorIds.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2009 - 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -504,6 +504,7 @@ static const PNPVendorId PNPVendorIds[] = { "TEI", _VENDOR_NAME_ENTRY("TECO") }, { "TGI", _VENDOR_NAME_ENTRY("TriGem") }, { "TGS", _VENDOR_NAME_ENTRY("Torus") }, + { "TMA", _VENDOR_NAME_ENTRY("Tianma Microelectronics") }, { "TOS", _VENDOR_NAME_ENTRY("Toshiba") }, { "TRI", _VENDOR_NAME_ENTRY("Tricord") }, { "TRM", _VENDOR_NAME_ENTRY("Tekram") }, diff --git a/src/common/inc/nvUnixVersion.h b/src/common/inc/nvUnixVersion.h index 1b1d10516..cfc4522a6 100644 --- a/src/common/inc/nvUnixVersion.h +++ b/src/common/inc/nvUnixVersion.h @@ -4,7 +4,7 @@ #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \ (defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1) -#define NV_VERSION_STRING "525.89.02" +#define NV_VERSION_STRING "530.30.02" #else diff --git a/src/common/inc/swref/published/ada/ad102/dev_bus.h b/src/common/inc/swref/published/ada/ad102/dev_bus.h index 30005f9a2..7eea0fd2c 100644 --- a/src/common/inc/swref/published/ada/ad102/dev_bus.h +++ b/src/common/inc/swref/published/ada/ad102/dev_bus.h @@ -30,3 +30,4 @@ #define NV_PBUS_SW_SCRATCH_FIELD_INIT 0x00000000 /* RWI-V */ #endif // ad102_dev_nv_bus_h + diff --git a/src/common/inc/swref/published/ada/ad102/dev_bus_addendum.h b/src/common/inc/swref/published/ada/ad102/dev_bus_addendum.h index e1a616721..0f99fe2bd 100644 --- a/src/common/inc/swref/published/ada/ad102/dev_bus_addendum.h +++ b/src/common/inc/swref/published/ada/ad102/dev_bus_addendum.h @@ -37,3 +37,4 @@ #define NV_PBUS_SW_GLOBAL_EROT_GRANT_ALLOW_NO 0 #endif // ad102_dev_nv_bus_addendum_h + diff --git a/src/common/inc/swref/published/hopper/gh100/dev_fsp_addendum.h b/src/common/inc/swref/published/hopper/gh100/dev_fsp_addendum.h deleted file mode 100644 index 137fbe6ac..000000000 --- a/src/common/inc/swref/published/hopper/gh100/dev_fsp_addendum.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __gh100_dev_fsp_addendum_h__ -#define __gh100_dev_fsp_addendum_h__ - -// -// RM uses channel 0 for FSP EMEM on GH100. -// -#define FSP_EMEM_CHANNEL_RM 0x0 - -// -// PMU/SOE use channel 4 for FSP EMEM on GH100. -// -#define FSP_EMEM_CHANNEL_PMU_SOE 0x4 -#define FSP_EMEM_CHANNEL_MAX 0x8 - -// EMEM channel 0 (RM) is allocated 1K bytes. -#define FSP_EMEM_CHANNEL_RM_SIZE 1024 - -// EMEM channel 4 (PMU/SOE) is allocated 1K bytes. -#define FSP_EMEM_CHANNEL_PMU_SOE_SIZE 1024 -#define FSP_EMEM_CHANNEL_PMU_SOE_OFFSET 4096 - -// -// MCTP (Management Component Transport Protocol) overlayed on NVDM (NVIDIA Data -// Model) is the mechanism used between FSP management partition and CPU-RM. -// - -#define MCTP_HEADER_RSVD 7:4 -#define MCTP_HEADER_VERSION 3:0 - -#define MCTP_HEADER_DEID 15:8 - -#define MCTP_HEADER_SEID 23:16 - -#define MCTP_HEADER_SOM 31:31 -#define MCTP_HEADER_EOM 30:30 -#define MCTP_HEADER_SEQ 29:28 -#define MCTP_HEADER_TO 27:27 -#define MCTP_HEADER_TAG 26:24 - -#define MCTP_MSG_HEADER_IC 7:7 -#define MCTP_MSG_HEADER_TYPE 6:0 -#define MCTP_MSG_HEADER_VENDOR_ID 23:8 -#define MCTP_MSG_HEADER_NVDM_TYPE 31:24 - -#define MCTP_MSG_HEADER_TYPE_VENDOR_PCI 0x7e -#define MCTP_MSG_HEADER_VENDOR_ID_NV 0x10de - -#define NVDM_TYPE_HULK 0x11 -#define NVDM_TYPE_FIRMWARE_UPDATE 0x12 -#define NVDM_TYPE_COT 0x14 -#define NVDM_TYPE_FSP_RESPONSE 0x15 -#define NVDM_TYPE_INFOROM 0x17 -#define NVDM_TYPE_SMBPBI 0x18 - -#endif // __gh100_dev_fsp_addendum_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_gsp.h b/src/common/inc/swref/published/hopper/gh100/dev_gsp.h index 0e9125ccc..c598d2b1a 100644 --- a/src/common/inc/swref/published/hopper/gh100/dev_gsp.h +++ b/src/common/inc/swref/published/hopper/gh100/dev_gsp.h @@ -22,6 +22,7 @@ */ #ifndef __gh100_dev_gsp_h__ #define __gh100_dev_gsp_h__ +#define NV_PGSP 0x113fff:0x110000 /* RW--D */ #define NV_PGSP_FALCON_ENGINE 0x1103c0 /* RW-4R */ #define NV_PGSP_FALCON_ENGINE_RESET 0:0 /* RWEVF */ #define NV_PGSP_FALCON_ENGINE_RESET_DEASSERT 0 /* */ diff --git a/src/common/inc/swref/published/maxwell/gm107/dev_ram.h b/src/common/inc/swref/published/maxwell/gm107/dev_ram.h index b12c44e08..53f25790e 100644 --- a/src/common/inc/swref/published/maxwell/gm107/dev_ram.h +++ b/src/common/inc/swref/published/maxwell/gm107/dev_ram.h @@ -47,6 +47,7 @@ #define NV_RAMUSERD_GP_GET (34*32+31):(34*32+0) /* RWXUF */ #define NV_RAMUSERD_GP_PUT (35*32+31):(35*32+0) /* RWXUF */ #define NV_RAMUSERD_BASE_SHIFT 9 /* */ +#define NV_RAMUSERD_CHAN_SIZE 512 /* */ #define NV_RAMUSERD_GP_TOP_LEVEL_GET (22*32+31):(22*32+0) /* RWXUF */ #define NV_RAMUSERD_GP_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) /* RWXUF */ #define NV_RAMRL_BASE_SHIFT 12 /* */ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_nvldl_ip_addendum.h b/src/common/inc/swref/published/nvswitch/ls10/dev_nvldl_ip_addendum.h index 71dfacd4a..7a7d50d07 100644 --- a/src/common/inc/swref/published/nvswitch/ls10/dev_nvldl_ip_addendum.h +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_nvldl_ip_addendum.h @@ -25,12 +25,12 @@ #define __ls10_dev_nvldl_ip_addendum_h__ #define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN 2:0 -#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN_DEFAULT 0x00000007 +#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN_DEFAULT 0x00000003 #define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP 3:3 -#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP_DEFAULT 0x00000000 +#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP_DEFAULT 0x00000001 #define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN 6:4 -#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN_DEFAULT 0x00000005 +#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN_DEFAULT 0x00000000 #define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP 12:8 -#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP_DEFAULT 0x00000005 +#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP_DEFAULT 0x00000006 #endif // __ls10_dev_nvldl_ip_addendum_h__ diff --git a/src/common/modeset/timing/nvt_displayid20.c b/src/common/modeset/timing/nvt_displayid20.c index 072d36159..83ab4e1cb 100644 --- a/src/common/modeset/timing/nvt_displayid20.c +++ b/src/common/modeset/timing/nvt_displayid20.c @@ -1,6 +1,6 @@ //***************************************************************************** // -// SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +// SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-License-Identifier: MIT // // Permission is hereby granted, free of charge, to any person obtaining a @@ -42,7 +42,7 @@ static NVT_STATUS parseDisplayId20SectionDataBlocks(const DISPLAYID_2_0_SECTION static NVT_STATUS parseDisplayId20ExtensionSection(const DISPLAYID_2_0_SECTION *pSection, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // DisplayID20 Data Block Tag Alloction -static NVT_STATUS parseDisplayId20ProductIdentity(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x20 Product Identificaton Block Tag +static NVT_STATUS parseDisplayId20ProductIdentity(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x20 Product Identificaton static NVT_STATUS parseDisplayId20DisplayParam(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x21 Display Parameters static NVT_STATUS parseDisplayId20Timing7(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x22 Type VII Timing - Detailed Timing static NVT_STATUS parseDisplayId20Timing8(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x23 Type VIII Timing - Enumerated Timing @@ -52,10 +52,10 @@ static NVT_STATUS parseDisplayId20DisplayInterfaceFeatures(const DISPLAYID_2_0_D static NVT_STATUS parseDisplayId20Stereo(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x27 Stereo Display Interface static NVT_STATUS parseDisplayId20TiledDisplay(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x28 Tiled Display Topology static NVT_STATUS parseDisplayId20ContainerId(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x29 ContainerID -static NVT_STATUS parseDisplayId20Timing10(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2A Type X Timing - Formula-based RR up to 1024Hz +static NVT_STATUS parseDisplayId20Timing10(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2A Type X Timing - Formula-based Timing static NVT_STATUS parseDisplayId20AdaptiveSync(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2B Adaptive-Sync -static NVT_STATUS parseDisplayId20ARVRHMD(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2C ARVR HMD -static NVT_STATUS parseDisplayId20ARVRLayer(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2D ARVR Layer +static NVT_STATUS parseDisplayId20ARVRHMD(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2C ARVR HMD +static NVT_STATUS parseDisplayId20ARVRLayer(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2D ARVR Layer static NVT_STATUS parseDisplayId20VendorSpecific(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x7E Vendor-specific static NVT_STATUS parseDisplayId20CtaData(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x81 CTA DisplayID @@ -63,7 +63,6 @@ static NVT_STATUS parseDisplayId20CtaData(const DISPLAYID_2_0_DATA_BLOCK_HEADER static NVT_STATUS getPrimaryUseCase(NvU8 product_type, NVT_DISPLAYID_PRODUCT_PRIMARY_USE_CASE *primary_use_case); static NVT_STATUS parseDisplayId20Timing7Descriptor(const DISPLAYID_2_0_TIMING_7_DESCRIPTOR *pDescriptor, NVT_TIMING *pTiming, NvU8 revision, NvU8 count); static NVT_STATUS parseDisplayId20Timing9Descriptor(const DISPLAYID_2_0_TIMING_9_DESCRIPTOR *pDescriptor, NVT_TIMING *pTiming, NvU8 count); -static NVT_STATUS parseDisplayId20Timing10Descriptor(const void *pDescriptor, NVT_TIMING *pTiming, NvU8 payloadbytes, NvU8 count); static NvU32 greatestCommonDenominator(NvU32 x, NvU32 y); static NvU8 getExistedTimingSeqNumber(NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo, enum NVT_TIMING_TYPE); @@ -812,11 +811,13 @@ parseDisplayId20Timing10( NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) { NVT_STATUS status = NVT_STATUS_SUCCESS; - const DISPLAYID_2_0_TIMING_10_BLOCK *pTiming10Block = NULL; - NvU32 descriptorCount = 0; - NvU8 startSeqNumber = 0; - NvU8 i = 0; - NvU8 eachOfDescriptorsSize = sizeof(DISPLAYID_2_0_TIMING_10_6BYTES_DESCRIPTOR); + NvU32 descriptorCount = 0; + NvU8 startSeqNumber = 0; + NvU8 i = 0; + NvU8 eachOfDescriptorsSize = sizeof(DISPLAYID_2_0_TIMING_10_6BYTES_DESCRIPTOR); + + const DISPLAYID_2_0_TIMING_10_BLOCK *pTiming10Block = NULL; + const DISPLAYID_2_0_TIMING_10_6BYTES_DESCRIPTOR *p6bytesDescriptor = NULL; NVT_TIMING newTiming; @@ -858,10 +859,44 @@ parseDisplayId20Timing10( for (i = 0; i < descriptorCount; i++) { + startSeqNumber += i; NVMISC_MEMSET(&newTiming, 0, sizeof(newTiming)); - - if (NVT_STATUS_SUCCESS == parseDisplayId20Timing10Descriptor(&pTiming10Block->descriptors[i*eachOfDescriptorsSize], &newTiming, pTiming10Block->header.payload_bytes_len, startSeqNumber+i)) + if (NVT_STATUS_SUCCESS == parseDisplayId20Timing10Descriptor(&pTiming10Block->descriptors[i*eachOfDescriptorsSize], + &newTiming, + pTiming10Block->header.payload_bytes_len)) { + p6bytesDescriptor = (const DISPLAYID_2_0_TIMING_10_6BYTES_DESCRIPTOR *)&pTiming10Block->descriptors[i*eachOfDescriptorsSize]; + + if (p6bytesDescriptor->options.ycc420_support) + { + UPDATE_BPC_FOR_COLORFORMAT(newTiming.etc.yuv420, 0, 1, 1, 1, 0, 1); + } + + if (p6bytesDescriptor->options.timing_formula == DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_STANDARD) + { + NVT_SNPRINTF((char *)newTiming.etc.name, sizeof(newTiming.etc.name), "DID20-Type10:#%3d:%dx%dx%3d.%03dHz/%s", + (int)NVT_GET_TIMING_STATUS_SEQ(newTiming.etc.status), + (int)newTiming.HVisible, + (int)newTiming.VVisible, + (int)newTiming.etc.rrx1k/1000, + (int)newTiming.etc.rrx1k%1000, + (newTiming.interlaced ? "I":"P")); + } + else + { + NVT_SNPRINTF((char *)newTiming.etc.name, sizeof(newTiming.etc.name), "DID20-Type10RB%d:#%3d:%dx%dx%3d.%03dHz/%s", + p6bytesDescriptor->options.timing_formula, + (int)NVT_GET_TIMING_STATUS_SEQ(newTiming.etc.status), + (int)newTiming.HVisible, + (int)newTiming.VVisible, + (int)newTiming.etc.rrx1k/1000, + (int)newTiming.etc.rrx1k%1000, + (newTiming.interlaced ? "I":"P")); + + } + newTiming.etc.status = NVT_STATUS_DISPLAYID_10N(++startSeqNumber); + newTiming.etc.name[sizeof(newTiming.etc.name) - 1] = '\0'; + if (!assignNextAvailableDisplayId20Timing(pDisplayIdInfo, &newTiming)) { break; @@ -869,7 +904,11 @@ parseDisplayId20Timing10( } else { - if (pDisplayIdInfo == NULL) return NVT_STATUS_ERR; + if (pDisplayIdInfo == NULL) + { + return NVT_STATUS_ERR; + } + continue; } } @@ -1306,14 +1345,18 @@ parseDisplayId20VendorSpecific( // TODO: below parser shall be updated if DID21 changed in the future if (pDataBlock->data_bytes == NVT_VESA_VENDOR_SPECIFIC_LENGTH) { - pVendorSpecific->vesaVsdb.data_struct_type.type = block->vendor_specific_data[3] & NVT_VESA_ORG_VSDB_DATA_TYPE_MASK; - pVendorSpecific->vesaVsdb.data_struct_type.color_space_and_eotf = (block->vendor_specific_data[3] & NVT_VESA_ORG_VSDB_COLOR_SPACE_AND_EOTF_MASK) >> NVT_VESA_ORG_VSDB_COLOR_SPACE_AND_EOTF_SHIFT; - - pVendorSpecific->vesaVsdb.overlapping.pixels_overlapping_count = block->vendor_specific_data[4] & NVT_VESA_ORG_VSDB_PIXELS_OVERLAPPING_MASK; - pVendorSpecific->vesaVsdb.overlapping.multi_sst = (block->vendor_specific_data[4] & NVT_VESA_ORG_VSDB_MULTI_SST_MODE_MASK) >> NVT_VESA_ORG_VSDB_MULTI_SST_MODE_SHIFT; - - pVendorSpecific->vesaVsdb.pass_through_integer.pass_through_integer_dsc = block->vendor_specific_data[5] & NVT_VESA_ORG_VSDB_PASS_THROUGH_INTEGER_MASK; - pVendorSpecific->vesaVsdb.pass_through_fractional.pass_through_fraction_dsc = block->vendor_specific_data[6] & NVT_VESA_ORG_VSDB_PASS_THROUGH_FRACTIOINAL_MASK; + pVendorSpecific->vesaVsdb.data_struct_type.type = + block->vendor_specific_data[3] & NVT_VESA_ORG_VSDB_DATA_TYPE_MASK; + pVendorSpecific->vesaVsdb.data_struct_type.color_space_and_eotf = + (block->vendor_specific_data[3] & NVT_VESA_ORG_VSDB_COLOR_SPACE_AND_EOTF_MASK) >> NVT_VESA_ORG_VSDB_COLOR_SPACE_AND_EOTF_SHIFT; + pVendorSpecific->vesaVsdb.overlapping.pixels_overlapping_count = + block->vendor_specific_data[4] & NVT_VESA_ORG_VSDB_PIXELS_OVERLAPPING_MASK; + pVendorSpecific->vesaVsdb.overlapping.multi_sst = + (block->vendor_specific_data[4] & NVT_VESA_ORG_VSDB_MULTI_SST_MODE_MASK) >> NVT_VESA_ORG_VSDB_MULTI_SST_MODE_SHIFT; + pVendorSpecific->vesaVsdb.pass_through_integer.pass_through_integer_dsc = + block->vendor_specific_data[5] & NVT_VESA_ORG_VSDB_PASS_THROUGH_INTEGER_MASK; + pVendorSpecific->vesaVsdb.pass_through_fractional.pass_through_fraction_dsc = + block->vendor_specific_data[6] & NVT_VESA_ORG_VSDB_PASS_THROUGH_FRACTIOINAL_MASK; } else { @@ -1655,18 +1698,21 @@ parseDisplayId20Timing9Descriptor( status = NvTiming_CalcCVT_RB2(width, height, rr, pDescriptor->options.rr_1000div1001_support, pTiming); break; default: + { + nvt_assert(0 && "Unknown timing formula"); status = NVT_STATUS_ERR; + } break; } if (status == NVT_STATUS_SUCCESS) - { + { NVMISC_MEMSET(pTiming->etc.name, 0, sizeof(pTiming->etc.name)); pTiming->etc.status = NVT_STATUS_DISPLAYID_9N(++count); - if ( pDescriptor->options.timing_formula== DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_STANDARD) + if (pDescriptor->options.timing_formula == DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_STANDARD) { - NVT_SNPRINTF((char *)pTiming->etc.name, sizeof(pTiming->etc.name), "DID20-Type9:#%3d:%dx%dx%3d.%03dHz/%s", + NVT_SNPRINTF((char *)pTiming->etc.name, sizeof(pTiming->etc.name), "DID20-Type9:#%3d:%dx%dx%3d.%03dHz/%s", (int)NVT_GET_TIMING_STATUS_SEQ(pTiming->etc.status), (int)pTiming->HVisible, (int)pTiming->VVisible, @@ -1674,19 +1720,10 @@ parseDisplayId20Timing9Descriptor( (int)pTiming->etc.rrx1k%1000, (pTiming->interlaced ? "I":"P")); } - else if (pDescriptor->options.timing_formula == DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_REDUCED_BLANKING_1) + else { - NVT_SNPRINTF((char *)pTiming->etc.name, sizeof(pTiming->etc.name), "DID20-Type9-RB1:#%3d:%dx%dx%3d.%03dHz/%s", - (int)NVT_GET_TIMING_STATUS_SEQ(pTiming->etc.status), - (int)pTiming->HVisible, - (int)pTiming->VVisible, - (int)pTiming->etc.rrx1k/1000, - (int)pTiming->etc.rrx1k%1000, - (pTiming->interlaced ? "I":"P")); - } - else if (pDescriptor->options.timing_formula == DISPLAYID_2_0_TIMING_FORMULA_CVT_2_0_REDUCED_BLANKING_2) - { - NVT_SNPRINTF((char *)pTiming->etc.name, sizeof(pTiming->etc.name), "DID20-Type9-RB2:#%3d:%dx%dx%3d.%03dHz/%s", + NVT_SNPRINTF((char *)pTiming->etc.name, sizeof(pTiming->etc.name), "DID20-Type9RB%d:#%3d:%dx%dx%3d.%03dHz/%s", + pDescriptor->options.timing_formula, (int)NVT_GET_TIMING_STATUS_SEQ(pTiming->etc.status), (int)pTiming->HVisible, (int)pTiming->VVisible, @@ -1695,19 +1732,17 @@ parseDisplayId20Timing9Descriptor( (pTiming->interlaced ? "I":"P")); } } - pTiming->etc.name[sizeof(pTiming->etc.name) - 1] = '\0'; return status; } CODE_SEGMENT(PAGE_DD_CODE) -static NVT_STATUS +NVT_STATUS parseDisplayId20Timing10Descriptor( const void *pDescriptor, NVT_TIMING *pTiming, - NvU8 payloadbytes, - NvU8 count) + NvU8 payloadBytes) { NVT_STATUS status = NVT_STATUS_SUCCESS; const DISPLAYID_2_0_TIMING_10_6BYTES_DESCRIPTOR* p6bytesDescriptor = NULL; @@ -1722,7 +1757,7 @@ parseDisplayId20Timing10Descriptor( height = (p6bytesDescriptor->vertical_active_lines[1] << 8 | p6bytesDescriptor->vertical_active_lines[0]) + 1; rr = p6bytesDescriptor->refresh_rate + 1; - if (payloadbytes == DISPLAYID_2_0_TIMING_10_PAYLOAD_BYTES_7) + if (payloadBytes == DISPLAYID_2_0_TIMING_10_PAYLOAD_BYTES_7) { p7bytesDescriptor = (const DISPLAYID_2_0_TIMING_10_7BYTES_DESCRIPTOR *)pDescriptor; rr = (p7bytesDescriptor->descriptor_6_bytes.refresh_rate | p7bytesDescriptor->refresh_rate_high << 8) + 1; @@ -1740,92 +1775,42 @@ parseDisplayId20Timing10Descriptor( status = NvTiming_CalcCVT_RB2(width, height, rr, p6bytesDescriptor->options.rr1000div1001_or_hblank, pTiming); break; case DISPLAYID_2_0_TIMING_FORMULA_CVT_2_0_REDUCED_BLANKING_3: - { - NvU32 deltaHBlank = 0; - - if (p7bytesDescriptor != NULL) - { - if (p6bytesDescriptor->options.rr1000div1001_or_hblank == 0) // Horizontal Blank in Pixels = [Field Value] * 8 + 80 - { - deltaHBlank = p7bytesDescriptor->delta_hblank * 8; - } - else if (p6bytesDescriptor->options.rr1000div1001_or_hblank == 1) - { - if (p7bytesDescriptor->delta_hblank <= 5) - deltaHBlank = (p7bytesDescriptor->delta_hblank * 8 + 160) - 80; - else // if 5 < Field Value <=7 - deltaHBlank = (160 - ((p7bytesDescriptor->delta_hblank - 5) * 8)) - 80; - } - - status = NvTiming_CalcCVT_RB3(width, height, rr, deltaHBlank, p7bytesDescriptor->additional_vblank_timing * 35, p6bytesDescriptor->options.early_vsync, pTiming); - } - else // 6 bytes descriptor - { - if (p6bytesDescriptor->options.rr1000div1001_or_hblank == 1) - deltaHBlank = 80; - - status = NvTiming_CalcCVT_RB3(width, height, rr, deltaHBlank, 0, p6bytesDescriptor->options.early_vsync, pTiming); - } - - break; - } - } - - if ( status == NVT_STATUS_SUCCESS ) { - NVMISC_MEMSET(pTiming->etc.name, 0, sizeof(pTiming->etc.name)); - pTiming->etc.status = NVT_STATUS_DISPLAYID_10N(++count); + NvU32 deltaHBlank = 0; + if (p7bytesDescriptor != NULL) + { + if (p6bytesDescriptor->options.rr1000div1001_or_hblank == 0) // Horizontal Blank in Pixels = [Field Value] * 8 + 80 + { + deltaHBlank = p7bytesDescriptor->delta_hblank * 8; + } + else if (p6bytesDescriptor->options.rr1000div1001_or_hblank == 1) + { + if (p7bytesDescriptor->delta_hblank <= 5) + deltaHBlank = (p7bytesDescriptor->delta_hblank * 8 + 160) - 80; + else // if 5 < Field Value <=7 + deltaHBlank = (160 - ((p7bytesDescriptor->delta_hblank - 5) * 8)) - 80; + } - if (p6bytesDescriptor->options.ycc420_support) - { - // YCC 420 support - UPDATE_BPC_FOR_COLORFORMAT(pTiming->etc.yuv420, 0, 1, 1, 1, 0, 1); + status = NvTiming_CalcCVT_RB3(width, height, rr, deltaHBlank, p7bytesDescriptor->additional_vblank_timing * 35, p6bytesDescriptor->options.early_vsync, pTiming); } + else // 6 bytes descriptor + { + if (p6bytesDescriptor->options.rr1000div1001_or_hblank == 1) + deltaHBlank = 80; - if (p6bytesDescriptor->options.timing_formula == DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_STANDARD) - { - NVT_SNPRINTF((char *)pTiming->etc.name, sizeof(pTiming->etc.name), "DID20-Type10:#%3d:%dx%dx%3d.%03dHz/%s", - (int)NVT_GET_TIMING_STATUS_SEQ(pTiming->etc.status), - (int)pTiming->HVisible, - (int)pTiming->VVisible, - (int)pTiming->etc.rrx1k/1000, - (int)pTiming->etc.rrx1k%1000, - (pTiming->interlaced ? "I":"P")); - - } - else if (p6bytesDescriptor->options.timing_formula == DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_REDUCED_BLANKING_1) - { - NVT_SNPRINTF((char *)pTiming->etc.name, sizeof(pTiming->etc.name), "DID20-Type10RB1:#%3d:%dx%dx%3d.%03dHz/%s", - (int)NVT_GET_TIMING_STATUS_SEQ(pTiming->etc.status), - (int)pTiming->HVisible, - (int)pTiming->VVisible, - (int)pTiming->etc.rrx1k/1000, - (int)pTiming->etc.rrx1k%1000, - (pTiming->interlaced ? "I":"P")); - } - else if (p6bytesDescriptor->options.timing_formula == DISPLAYID_2_0_TIMING_FORMULA_CVT_2_0_REDUCED_BLANKING_2) - { - NVT_SNPRINTF((char *)pTiming->etc.name, sizeof(pTiming->etc.name), "DID20-Type10RB2:#%3d:%dx%dx%3d.%03dHz/%s", - (int)NVT_GET_TIMING_STATUS_SEQ(pTiming->etc.status), - (int)pTiming->HVisible, - (int)pTiming->VVisible, - (int)pTiming->etc.rrx1k/1000, - (int)pTiming->etc.rrx1k%1000, - (pTiming->interlaced ? "I":"P")); - } - else if (p6bytesDescriptor->options.timing_formula == DISPLAYID_2_0_TIMING_FORMULA_CVT_2_0_REDUCED_BLANKING_3) - { - NVT_SNPRINTF((char *)pTiming->etc.name, sizeof(pTiming->etc.name), "DID20-Type10RB3:#%3d:%dx%dx%3d.%03dHz/%s", - (int)NVT_GET_TIMING_STATUS_SEQ(pTiming->etc.status), - (int)pTiming->HVisible, - (int)pTiming->VVisible, - (int)pTiming->etc.rrx1k/1000, - (int)pTiming->etc.rrx1k%1000, - (pTiming->interlaced ? "I":"P")); + status = NvTiming_CalcCVT_RB3(width, height, rr, deltaHBlank, 0, p6bytesDescriptor->options.early_vsync, pTiming); } } + break; + default: + { + nvt_assert(0 && "Unknown timing formula"); + status = NVT_STATUS_ERR; + } + break; + } - pTiming->etc.name[sizeof(pTiming->etc.name) - 1] = '\0'; + if (status == NVT_STATUS_SUCCESS) return status; return status; } @@ -1842,7 +1827,7 @@ getExistedTimingSeqNumber( switch (timingType) { - case NVT_TYPE_DISPLAYID_7: + case NVT_TYPE_DISPLAYID_7: case NVT_TYPE_DISPLAYID_8: case NVT_TYPE_DISPLAYID_9: case NVT_TYPE_DISPLAYID_10: diff --git a/src/common/modeset/timing/nvt_edid.c b/src/common/modeset/timing/nvt_edid.c index 3a6551e28..f428bf590 100644 --- a/src/common/modeset/timing/nvt_edid.c +++ b/src/common/modeset/timing/nvt_edid.c @@ -1079,6 +1079,11 @@ NVT_STATUS NV_STDCALL NvTiming_ParseEDIDInfo(NvU8 *pEdid, NvU32 length, NVT_EDID // add the detailed timings in 18-byte long display descriptor parse861ExtDetailedTiming(pExt, p861Info->basic_caps, pInfo); + if (p861Info->revision >= NVT_CTA861_REV_H && p861Info->total_did_type10db != 0) + { + parseCta861DIDType10VideoTimingDataBlock(p861Info, pInfo); + } + // CEA861-F at 7.5.12 section about VFPDB block. if (p861Info->revision >= NVT_CEA861_REV_F && p861Info->total_vfpdb != 0) { @@ -2169,9 +2174,8 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length) NvBool bAllZero = NV_TRUE; NvU32 ret = 0; - // check the EDID base size to avoid accessing beyond the EDID buffer, do not proceed with - // further validation. - if (length < sizeof(EDIDV1STRUC)) + // check the EDID base size to avoid accessing beyond the EDID buffer + if (length < sizeof(EDIDV1STRUC) || (length > sizeof(EDIDV1STRUC) && (length % sizeof(EDIDV1STRUC) != 0))) ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_SIZE); // check the EDID version and signature @@ -2254,6 +2258,11 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length) ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXTENSION_COUNT); } + // we shall not trust any extension blocks with wrong input EDID size + if (NVT_IS_EDID_VALIDATION_FLAGS(ret, NVT_EDID_VALIDATION_ERR_SIZE) || + NVT_IS_EDID_VALIDATION_FLAGS(ret, NVT_EDID_VALIDATION_ERR_EXTENSION_COUNT)) + return ret; + // validate extension blocks for (j = 1; j <= p->bExtensionFlag; j++) { @@ -2415,7 +2424,7 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length) } // compare the remain 0 value are correct or not before meet checksum byte - for (i = 0; i <= (NvU32)(&pDisplayid->data[NVT_DID_MAX_EXT_PAYLOAD-1] - pData_collection); i++) + for (i = 0; i < (NvU32)(&pDisplayid->data[NVT_DID_MAX_EXT_PAYLOAD-1] - pData_collection); i++) { if (pData_collection[i] != 0) { @@ -2465,7 +2474,7 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length) } // compare the remain 0 value are correct or not before meet checksum byte - for (i = 0; i <= (NvU32)(&pDisplayid->data[NVT_DID_MAX_EXT_PAYLOAD-1] - pData_collection); i++) + for (i = 0; i < (NvU32)(&pDisplayid->data[NVT_DID_MAX_EXT_PAYLOAD-1] - pData_collection); i++) { if (pData_collection[i] != 0) { diff --git a/src/common/modeset/timing/nvt_edidext_861.c b/src/common/modeset/timing/nvt_edidext_861.c index c3a975ff1..da9f6fdde 100644 --- a/src/common/modeset/timing/nvt_edidext_861.c +++ b/src/common/modeset/timing/nvt_edidext_861.c @@ -720,7 +720,7 @@ void parse861bShortPreferredTiming(NVT_EDID_CEA861_INFO *pExt861, return; } - // finding all the DTD + // finding all the DTD in Base 0 or CTA861 if (flag == FROM_CTA861_EXTENSION) { for (j = 0; j < pInfo->total_timings; j++) @@ -1288,6 +1288,7 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p, NvU32 vendor_index = 0; NvU32 yuv420vdb_index = 0; NvU32 yuv420cmdb_index = 0; + NvU32 didT10_index = 0; NvU8 svr_index = 0; NvU32 ieee_id = 0; NvU32 tag, ext_tag, payload; @@ -1330,6 +1331,11 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p, else if (ext_tag == NVT_CEA861_EXT_TAG_VENDOR_SPECIFIC_VIDEO && payload < 4) return NVT_STATUS_ERR; else if (ext_tag == NVT_CTA861_EXT_TAG_SCDB && payload < 7) return NVT_STATUS_ERR; else if (ext_tag == NVT_CEA861_EXT_TAG_HF_EEODB && payload != 2) return NVT_STATUS_ERR; + else if (ext_tag == NVT_CTA861_EXT_TAG_DID_TYPE_X) + { + if (((p[i+1] & 0x70) >> 4 == 0) && (payload-2) % 6) return NVT_STATUS_ERR; + if (((p[i+1] & 0x70) >> 4 == 1) && (payload-2) % 7) return NVT_STATUS_ERR; + } } break; default: @@ -1549,6 +1555,29 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p, i += payload; } } + else if (ext_tag == NVT_CTA861_EXT_TAG_DID_TYPE_X && ((payload-2) % 6 == 0 || (payload-2) % 7 == 0)) + { + i++; payload--; + + p861info->did_type10_data_block[didT10_index].version.revision = p[i] & 0x7; + p861info->did_type10_data_block[didT10_index].version.t10_m = (p[i] & 0x70) >> 4; + + // do not consider Byte 3 + i++; payload--; + + if (p861info->did_type10_data_block[didT10_index].version.t10_m == 0) + p861info->did_type10_data_block[didT10_index].total_descriptors = (NvU8)(payload / 6); + else if (p861info->did_type10_data_block[didT10_index].version.t10_m == 1) + p861info->did_type10_data_block[didT10_index].total_descriptors = (NvU8)(payload / 7); + + for (j = 0; j < payload; j++, i++) + { + p861info->did_type10_data_block[didT10_index].payload[j] = p[i]; + } + // next type10 data block if it exists + p861info->total_did_type10db++; + didT10_index++; + } else if(ext_tag == NVT_CTA861_EXT_TAG_SCDB && payload >= 7) // sizeof(HDMI Forum Sink Capability Data Block) ranges between 7 to 31 bytes { // As per HDMI2.1 A1 amendment Sink Capability Data Structure(SCDS) can alternatively be included in HDMI Forum Sink Capability Data Block(HF-SCDB), @@ -1561,7 +1590,7 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p, // Copy SCDS over to p861info->vsdb[vendor_index]. Parsing will later be handled in parseEdidHdmiForumVSDB(). for (j = 0; (j < payload - 3) && (j < NVT_CTA861_EXT_SCDB_PAYLOAD_MAX_LENGTH); j ++, i ++) { - p861info->hfscdb[j] = p[i]; + p861info->hfscdb[j] = p[i]; } p861info->hfscdbSize = MIN(payload - 3, NVT_CTA861_EXT_SCDB_PAYLOAD_MAX_LENGTH); p861info->valid.SCDB = 1; @@ -1706,8 +1735,7 @@ NVT_STATUS NvTiming_CalcCEA861bTiming(NvU32 width, NvU32 height, NvU32 rr, NvU32 // loop through the table for (i = 0; i < MAX_CEA861B_FORMAT; i ++) - { - + { if ((EIA861B[i].etc.rep & pixelRepeatMask) == 0) { continue; @@ -3060,4 +3088,85 @@ void parseCea861Hdr10PlusDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo NVMISC_MEMCPY(pHdr10PlusInfo, &pExt861->vsvdb.vendor_data, sizeof(NVT_HDR10PLUS_INFO)); } +CODE_SEGMENT(PAGE_DD_CODE) +void parseCta861DIDType10VideoTimingDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo) +{ + NvU8 i = 0; + NvU8 t10db_idx = 0; + + NVT_TIMING newTiming; + NVT_EDID_INFO *pInfo = (NVT_EDID_INFO *)pRawInfo; + const DISPLAYID_2_0_TIMING_10_6BYTES_DESCRIPTOR *p6bytesDescriptor = NULL; + NvU8 eachOfDescriptorsSize = sizeof (DISPLAYID_2_0_TIMING_10_6BYTES_DESCRIPTOR); + + for (t10db_idx = 0; t10db_idx < pExt861->total_did_type10db; t10db_idx++) + { + // 6 or 7 bytes length + eachOfDescriptorsSize = sizeof(DISPLAYID_2_0_TIMING_10_6BYTES_DESCRIPTOR) + pExt861->did_type10_data_block[t10db_idx].version.t10_m; + + for (i = 0; i < pExt861->did_type10_data_block[t10db_idx].total_descriptors; i++) + { + if (pExt861->did_type10_data_block[t10db_idx].total_descriptors < NVT_CTA861_DID_TYPE10_DESCRIPTORS_MIN || + pExt861->did_type10_data_block[t10db_idx].total_descriptors > NVT_CTA861_DID_TYPE10_DESCRIPTORS_MAX) + { + nvt_assert(0 && "payload descriptor invalid. expect minimum 1 descriptor, maximum 4 descriptors"); + continue; + } + + NVMISC_MEMSET(&newTiming, 0, sizeof(newTiming)); + if (NVT_STATUS_SUCCESS == parseDisplayId20Timing10Descriptor(&pExt861->did_type10_data_block[t10db_idx].payload[i*eachOfDescriptorsSize], + &newTiming, + pExt861->did_type10_data_block[t10db_idx].version.t10_m)) + { + p6bytesDescriptor = (const DISPLAYID_2_0_TIMING_10_6BYTES_DESCRIPTOR *) + &pExt861->did_type10_data_block[t10db_idx].payload[i*eachOfDescriptorsSize]; + + if (p6bytesDescriptor->options.ycc420_support) + { + UPDATE_BPC_FOR_COLORFORMAT(newTiming.etc.yuv420, 0, 1, + pInfo->hdmiForumInfo.dc_30bit_420, + pInfo->hdmiForumInfo.dc_36bit_420, 0, + pInfo->hdmiForumInfo.dc_48bit_420); + } + + if (p6bytesDescriptor->options.timing_formula == DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_STANDARD) + { + NVT_SNPRINTF((char *)newTiming.etc.name, sizeof(newTiming.etc.name), "CTA861-T10:#%3d:%dx%dx%3d.%03dHz/%s", + (int)NVT_GET_TIMING_STATUS_SEQ(newTiming.etc.status), + (int)newTiming.HVisible, + (int)newTiming.VVisible, + (int)newTiming.etc.rrx1k/1000, + (int)newTiming.etc.rrx1k%1000, + (newTiming.interlaced ? "I":"P")); + } + else + { + NVT_SNPRINTF((char *)newTiming.etc.name, sizeof(newTiming.etc.name), "CTA861-T10RB%d:#%3d:%dx%dx%3d.%03dHz/%s", + p6bytesDescriptor->options.timing_formula, + (int)NVT_GET_TIMING_STATUS_SEQ(newTiming.etc.status), + (int)newTiming.HVisible, + (int)newTiming.VVisible, + (int)newTiming.etc.rrx1k/1000, + (int)newTiming.etc.rrx1k%1000, + (newTiming.interlaced ? "I":"P")); + } + newTiming.etc.status = NVT_STATUS_DISPLAYID_10N(i+1); + newTiming.etc.flag |= NVT_FLAG_DISPLAYID_T10_TIMING; + newTiming.etc.name[sizeof(newTiming.etc.name) - 1] = '\0'; + + if (!assignNextAvailableTiming(pInfo, &newTiming)) + { + break; + } + } + else + { + continue; + } + } + } + + return; +} + POP_SEGMENTS diff --git a/src/common/modeset/timing/nvtiming.h b/src/common/modeset/timing/nvtiming.h index c791b86bc..f0bc762f7 100644 --- a/src/common/modeset/timing/nvtiming.h +++ b/src/common/modeset/timing/nvtiming.h @@ -1,6 +1,6 @@ //**************************************************************************** // -// SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +// SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-License-Identifier: MIT // // Permission is hereby granted, free of charge, to any person obtaining a @@ -438,6 +438,7 @@ typedef enum NVT_TV_FORMAT #define NVT_CEA861_REV_E 3 #define NVT_CEA861_REV_F 3 #define NVT_CTA861_REV_G 3 +#define NVT_CTA861_REV_H 3 // // max data after misc/basic_caps in EIA861EXTENSION #define NVT_CEA861_MAX_PAYLOAD 123 @@ -469,28 +470,39 @@ typedef enum NVT_TV_FORMAT // the extended tag codes when NVT_CEA861_TAG_EXTENDED_FLAG #define NVT_CEA861_EXT_TAG_VIDEO_CAP 0 // Video Capability Data Block #define NVT_CEA861_EXT_TAG_VENDOR_SPECIFIC_VIDEO 1 // Vendor-Specific Video Data Block -#define NVT_CEA861_EXT_TAG_VESA_VIDEO_DISPLAY_DEVICE 2 // Reserved for VESA Video Display Device Information Data Block +#define NVT_CEA861_EXT_TAG_VESA_VIDEO_DISPLAY_DEVICE 2 // VESA Video Display Device Information Data Block #define NVT_CEA861_EXT_TAG_VESA_VIDEO 3 // Reserved for VESA Video Data BLock #define NVT_CEA861_EXT_TAG_HDMI_VIDEO 4 // Reserved for HDMI Video Data Block #define NVT_CEA861_EXT_TAG_COLORIMETRY 5 // Colorimetry Data Block #define NVT_CEA861_EXT_TAG_HDR_STATIC_METADATA 6 // HDR Static Metadata Data Block CEA861.3 HDR extension for HDMI 2.0a -#define NVT_CEA861_EXT_TAG_VIDEO_RSVD_MIN 7 // 7...12 : Reserved for video-related blocks -#define NVT_CEA861_EXT_TAG_VIDEO_RSVD_MAX 12 +#define NVT_CTA861_EXT_TAG_HDR_DYNAMIC_METADATA 7 // CTA861-H HDR Dynamic Metadata Data Block +#define NVT_CTA861_EXT_TAG_VIDEO_RSVD_MIN 8 // 8...12 : Reserved for video-related blocks +#define NVT_CTA861_EXT_TAG_VIDEO_RSVD_MAX 12 #define NVT_CEA861_EXT_TAG_VIDEO_FORMAT_PREFERENCE 13 // CEA861F Video Format Preference Data Block #define NVT_CEA861_EXT_TAG_YCBCR420_VIDEO 14 // CEA861F YCBCR 4:2:0 Video Data Block #define NVT_CEA861_EXT_TAG_YCBCR420_CAP 15 // CEA861F YCBCR 4:2:0 Capability Map Data Block #define NVT_CEA861_EXT_TAG_MISC_AUDIO 16 // CEA Miscellaneous Audio Fields #define NVT_CEA861_EXT_TAG_VENDOR_SPECIFIC_AUDIO 17 // Vendor-Specific Audio Data Block #define NVT_CEA861_EXT_TAG_HDMI_AUDIO 18 // Reserved for HDMI Audio Data Block -#define NVT_CEA861_EXT_TAG_AUDIO_RSVD_MIN 19 // 19...31 : Reserved for audio-related blocks -#define NVT_CEA861_EXT_TAG_AUDIO_RSVD_MAX 31 +#define NVT_CTA861_EXT_TAG_ROOM_CONFIGURATION 19 // CTA861-H Room Configuration Data Block +#define NVT_CTA861_EXT_TAG_SPEACKER_LOCATION 20 // CTA861-H Speaker Location Data Block +#define NVT_CTA861_EXT_TAG_AUDIO_RSVD_MIN 21 // 21...31 : Reserved for audio-related blocks +#define NVT_CTA861_EXT_TAG_AUDIO_RSVD_MAX 31 #define NVT_CEA861_EXT_TAG_INFOFRAME 32 // Infoframe Data Block -#define NVT_CEA861_EXT_TAG_RSVD_MIN_1 33 // 33...120 : Reserved for general -#define NVT_CEA861_EXT_TAG_RSVD_MAX_1 119 +#define NVT_CEA861_EXT_TAG_RSVD 33 // Reserved +#define NVT_CTA861_EXT_TAG_DID_TYPE_VII 34 // DisplayID Type VII Video Timing Data Block +#define NVT_CTA861_EXT_TAG_DID_TYPE_VIII 35 // DisplayID Type VIII Video Timing Data Block +#define NVT_CTA861_EXT_TAG_RSVD_MIN_1 36 // 36...41 : Reserved for general +#define NVT_CTA861_EXT_TAG_RSVD_MAX_1 41 +#define NVT_CTA861_EXT_TAG_DID_TYPE_X 42 // DisplayID Type X Video Timing Data Block +#define NVT_CTA861_EXT_TAG_RSVD_MIN_2 43 // 43...119 : Reserved for general +#define NVT_CEA861_EXT_TAG_RSVD_MAX_2 119 #define NVT_CEA861_EXT_TAG_HF_EEODB 120 // HDMI Forum Edid Extension Override Data Block #define NVT_CTA861_EXT_TAG_SCDB 121 // 0x79 == Tag for Sink Capability Data Block -#define NVT_CEA861_EXT_TAG_RSVD_MIN_2 122 // 122...255 : Reserved for general -#define NVT_CEA861_EXT_TAG_RSVD_MAX_2 255 +#define NVT_CEA861_EXT_TAG_HDMI_RSVD_MIN 122 // 122...127 : Reserved for HDMI +#define NVT_CEA861_EXT_TAG_HDMI_RSVD_MAX 127 +#define NVT_CEA861_EXT_TAG_RSVD_MIN_3 128 // 128...255 : Reserved for general +#define NVT_CEA861_EXT_TAG_RSVD_MAX_3 255 // //the extended tag payload size; the size includes the extended tag code #define NVT_CEA861_EXT_VIDEO_CAP_SD_SIZE 2 @@ -1108,7 +1120,28 @@ typedef struct tagNVT_2BYTES NvU8 byte1; NvU8 byte2; } NVT_2BYTES; -// + +//*********************** +// DisplayID 10 Timing Data Block +//*********************** +#define NVT_CTA861_DID_TYPE10_DESCRIPTORS_MIN 1 +#define NVT_CTA861_DID_TYPE10_DESCRIPTORS_MAX 4 +#define NVT_CTA861_DID_TYPE10_MAX_DATA_BLOCK 4 + +typedef struct DID_TYPE10_DATA +{ + struct { + NvU8 revision : 3; + NvU8 F33 : 1; + NvU8 t10_m : 3; + NvU8 F37 : 1; + } version; + + NvU8 total_descriptors; + + NvU8 payload[28]; // given the 7bytes * 4 space +} DID_TYPE10_DATA; + // See CEA-861E, Table 42, 43 Extended Tags; indicates that the corresponding CEA extended data block value is valid, e.g. if colorimetry is set, then NVT_EDID_CEA861_INFO::colorimetry is valid typedef struct tagNVT_VALID_EXTENDED_BLOCKS { @@ -1127,7 +1160,6 @@ typedef struct tagNVT_VALID_EXTENDED_BLOCKS NvU32 msft_vsdb : 1; } NVT_VALID_EXTENDED_BLOCKS; - //************************* // extended data blocks //************************* @@ -1206,6 +1238,10 @@ typedef struct tagEDID_CEA861_INFO NvU32 hfscdbSize; NvU8 hfscdb[NVT_CTA861_EXT_SCDB_PAYLOAD_MAX_LENGTH]; + // DID Type X Video extended block, see CTA861-H, section 3.5.17.3 DisplayID Type X Video Timing Data Block + NvU8 total_did_type10db; + DID_TYPE10_DATA did_type10_data_block[NVT_CTA861_DID_TYPE10_MAX_DATA_BLOCK]; + NvU8 hfeeodb; // HDMI Forum Edid Extension Override Data Block. } NVT_EDID_CEA861_INFO; @@ -5312,6 +5348,9 @@ typedef enum #define NVT_FLAG_DISPLAYID_T7_DSC_PASSTHRU 0x00400000 #define NVT_FLAG_DISPLAYID_2_0_TIMING 0x00800000 // this one for the CTA861 embedded in DID20 #define NVT_FLAG_DISPLAYID_T7_T8_EXPLICT_YUV420 0x01000000 // DID2 E7 spec. supported yuv420 indicated +#define NVT_FLAG_DISPLAYID_T7_TIMING 0x02000000 +#define NVT_FLAG_DISPLAYID_T8_TIMING 0x04000000 +#define NVT_FLAG_DISPLAYID_T10_TIMING 0x08000000 #define NVT_FLAG_INTERLACED_MASK (NVT_FLAG_INTERLACED_TIMING | NVT_FLAG_INTERLACED_TIMING2) diff --git a/src/common/modeset/timing/nvtiming_pvt.h b/src/common/modeset/timing/nvtiming_pvt.h index 0e33e08e4..ef553aa29 100644 --- a/src/common/modeset/timing/nvtiming_pvt.h +++ b/src/common/modeset/timing/nvtiming_pvt.h @@ -1,6 +1,6 @@ //***************************************************************************** // -// SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +// SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-License-Identifier: MIT // // Permission is hereby granted, free of charge, to any person obtaining a @@ -81,6 +81,7 @@ void parseEdidNvidiaVSDBBlock(VSDB_DATA *pVsdb, NVDA_VSDB_PARSED_INFO *vsd void parseCea861HdrStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); void parseCea861DvStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); void parseCea861Hdr10PlusDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); +void parseCta861DIDType10VideoTimingDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo); NvBool isMatchedCTA861Timing(NVT_EDID_INFO *pInfo, NVT_TIMING *pT); NvU32 isHdmi3DStereoType(NvU8 StereoStructureType); NvU32 getCEA861TimingAspectRatio(NvU32 vic); @@ -95,6 +96,7 @@ NVT_STATUS getDisplayIdEDIDExtInfo(NvU8* pEdid, NvU32 edidSize, NVT_EDID_INFO* p NVT_STATUS parseDisplayIdBlock(NvU8* pBlock, NvU8 max_length, NvU8* pLength, NVT_EDID_INFO* pEdidInfo); NVT_STATUS getDisplayId20EDIDExtInfo(NvU8* pDisplayid, NvU32 edidSize, NVT_EDID_INFO* pEdidInfo); NVT_STATUS parseDisplayId20EDIDExtDataBlocks(NvU8* pDataBlock, NvU8 remainSectionLength, NvU8* pCurrentDBLength, NVT_EDID_INFO* pEdidInfo); +NVT_STATUS parseDisplayId20Timing10Descriptor(const void *pDescriptor, NVT_TIMING *pTiming, NvU8 payloadBytes); void updateColorFormatForDisplayIdExtnTimings(NVT_EDID_INFO* pInfo, NvU32 timingIdx); void updateColorFormatForDisplayId20ExtnTimings(NVT_EDID_INFO* pInfo, NvU32 timingIdx); NvBool assignNextAvailableDisplayId20Timing(NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo, const NVT_TIMING *pTiming); diff --git a/src/common/nvlink/kernel/nvlink/core/nvlink_link_mgmt.c b/src/common/nvlink/kernel/nvlink/core/nvlink_link_mgmt.c index a76989085..eba23115c 100644 --- a/src/common/nvlink/kernel/nvlink/core/nvlink_link_mgmt.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_link_mgmt.c @@ -83,7 +83,18 @@ nvlink_core_check_link_state return NV_FALSE; } - if (crntTlLinkMode == NVLINK_LINKSTATE_HS) + status = link->link_handlers->get_dl_link_mode(link, &crntDlLinkMode); + if (status != NVL_SUCCESS) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: Unable to get DL link mode for %s:%s\n", + __FUNCTION__, link->dev->deviceName, link->linkName)); + return NV_FALSE; + } + + if (crntTlLinkMode == NVLINK_LINKSTATE_HS && + (crntDlLinkMode == NVLINK_LINKSTATE_HS || + crntDlLinkMode == NVLINK_LINKSTATE_SLEEP)) { return NV_TRUE; } diff --git a/src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c b/src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c index 0bdc93e81..282139e45 100644 --- a/src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c @@ -995,12 +995,9 @@ nvlink_core_powerdown_floorswept_conns_to_off conn = NULL; nvlink_core_get_intranode_conn(links[j], &(conn)); if (conn == NULL || - _nvlink_core_check_if_conn_in_array(visitedConns, connCount, conn) || + _nvlink_core_check_if_conn_in_array(visitedConns, connCount, conn) || (conn->end0 == NULL || conn->end1 == NULL)) { - NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, - "%s: AC debug -- conn gotten: 0x%x\n", - __FUNCTION__, conn)); continue; } else if(nvlink_core_check_intranode_conn_state(conn, NVLINK_LINKSTATE_OFF) == diff --git a/src/common/nvswitch/common/inc/soe/soeifcore.h b/src/common/nvswitch/common/inc/soe/soeifcore.h index c48cb6b70..621cb279e 100644 --- a/src/common/nvswitch/common/inc/soe/soeifcore.h +++ b/src/common/nvswitch/common/inc/soe/soeifcore.h @@ -74,14 +74,13 @@ enum /*! * Read VRs - * Needed to be in sync with chips_a defines */ RM_SOE_CORE_CMD_GET_VOLTAGE_VALUES, /*! * Init PLM2 protected registers */ - RM_SOE_CORE_CMD_INIT_L2_STATE + RM_SOE_CORE_CMD_INIT_L2_STATE, }; // Timeout for SOE reset callback function diff --git a/src/common/nvswitch/common/inc/soe/soeififr.h b/src/common/nvswitch/common/inc/soe/soeififr.h index 3a70d6f48..b7504ce3f 100644 --- a/src/common/nvswitch/common/inc/soe/soeififr.h +++ b/src/common/nvswitch/common/inc/soe/soeififr.h @@ -27,6 +27,7 @@ #include "flcnifcmn.h" #define INFOROM_FS_FILE_NAME_SIZE 3 +#define INFOROM_BBX_OBJ_XID_ENTRIES 10 enum { @@ -70,6 +71,7 @@ typedef struct typedef struct { NvU8 cmdType; + NvU32 sizeInBytes; RM_FLCN_U64 dmaHandle; } RM_SOE_IFR_CMD_BBX_SXID_GET_PARAMS; @@ -82,4 +84,19 @@ typedef union RM_SOE_IFR_CMD_BBX_SXID_GET_PARAMS bbxSxidGet; } RM_SOE_IFR_CMD; +// entry of getSxid +typedef struct +{ + NvU32 sxid; + NvU32 timestamp; +} RM_SOE_BBX_SXID_ENTRY; + +// SXID data array return to getSxid +typedef struct +{ + NvU32 sxidCount; + RM_SOE_BBX_SXID_ENTRY sxidFirst[INFOROM_BBX_OBJ_XID_ENTRIES]; + RM_SOE_BBX_SXID_ENTRY sxidLast[INFOROM_BBX_OBJ_XID_ENTRIES]; +} RM_SOE_BBX_GET_SXID_DATA; + #endif // _SOEIFIFR_H_ diff --git a/src/common/nvswitch/common/inc/soe/soeiftherm.h b/src/common/nvswitch/common/inc/soe/soeiftherm.h index 1478ed4ee..58dea8452 100644 --- a/src/common/nvswitch/common/inc/soe/soeiftherm.h +++ b/src/common/nvswitch/common/inc/soe/soeiftherm.h @@ -75,7 +75,6 @@ enum { RM_SOE_THERM_MSG_ID_SLOWDOWN_STATUS, RM_SOE_THERM_MSG_ID_SHUTDOWN_STATUS, - RM_SOE_THERM_MSG_ID_ACK_FORCE_SLOWDOWN, }; /*! @@ -103,7 +102,6 @@ typedef struct NvBool bSlowdown; NvTemp maxTemperature; NvTemp warnThreshold; - NvBool bLinksL1Status; struct { diff --git a/src/common/nvswitch/interface/ctrl_dev_nvswitch.h b/src/common/nvswitch/interface/ctrl_dev_nvswitch.h index 693107b2c..5b54d67c1 100644 --- a/src/common/nvswitch/interface/ctrl_dev_nvswitch.h +++ b/src/common/nvswitch/interface/ctrl_dev_nvswitch.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -3816,8 +3816,8 @@ typedef struct #define CTRL_NVSWITCH_CLEAR_COUNTERS 0x51 #define CTRL_NVSWITCH_SET_NVLINK_ERROR_THRESHOLD 0x52 #define CTRL_NVSWITCH_GET_NVLINK_ERROR_THRESHOLD 0x53 -#define CTRL_NVSWITCH_GET_VOLTAGE 0x55 -#define CTRL_NVSWITCH_GET_BOARD_PART_NUMBER 0x54 +#define CTRL_NVSWITCH_GET_VOLTAGE 0x54 +#define CTRL_NVSWITCH_GET_BOARD_PART_NUMBER 0x55 #ifdef __cplusplus } diff --git a/src/common/nvswitch/interface/export_nvswitch.h b/src/common/nvswitch/interface/export_nvswitch.h index 08c9a7a7f..6e7999b5a 100644 --- a/src/common/nvswitch/interface/export_nvswitch.h +++ b/src/common/nvswitch/interface/export_nvswitch.h @@ -895,7 +895,6 @@ nvswitch_os_vsnprintf void nvswitch_os_assert_log ( - int cond, const char *pFormat, ... ); diff --git a/src/common/nvswitch/kernel/flcn/flcnqueue_nvswitch.c b/src/common/nvswitch/kernel/flcn/flcnqueue_nvswitch.c index 4a5b3ea24..6bd283ca6 100644 --- a/src/common/nvswitch/kernel/flcn/flcnqueue_nvswitch.c +++ b/src/common/nvswitch/kernel/flcn/flcnqueue_nvswitch.c @@ -1172,6 +1172,14 @@ _flcnQueueResponseHandle_IMPL NVSWITCH_ASSERT(pQueueInfo != NULL); + if (pMsgGen == NULL) + { + NVSWITCH_PRINT(device, ERROR, + "%s: NULL message\n", + __FUNCTION__); + return NV_ERR_GENERIC; + } + // get the sequence info data associated with this message pSeqInfo = flcnableQueueSeqInfoGet(device, pFlcn->pFlcnable, pMsgGen->hdr.seqNumId); if ((pSeqInfo == NULL) || @@ -1188,7 +1196,7 @@ _flcnQueueResponseHandle_IMPL } // If response was requested - if (pSeqInfo->pMsgResp != NULL && pMsgGen != NULL) + if (pSeqInfo->pMsgResp != NULL) { NVSWITCH_ASSERT(pSeqInfo->pMsgResp->hdr.size == pMsgGen->hdr.size); msgSize = pMsgGen->hdr.size - RM_FLCN_QUEUE_HDR_SIZE; diff --git a/src/common/nvswitch/kernel/inc/common_nvswitch.h b/src/common/nvswitch/kernel/inc/common_nvswitch.h index e65bea6f6..f7f66f698 100644 --- a/src/common/nvswitch/kernel/inc/common_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/common_nvswitch.h @@ -125,12 +125,21 @@ static NV_INLINE void nvswitch_clear_flags(NvU32 *val, NvU32 flags) // This macro should be used to check assertion statements and print Error messages. // #if defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS) -#define NVSWITCH_ASSERT(_cond) \ - nvswitch_os_assert_log((_cond), "NVSwitch: Assertion failed in %s() at %s:%d\n", \ - __FUNCTION__ , __FILE__, __LINE__) +void nvswitch_assert_log +( + const char *function, + const char *file, + NvU32 line +); + +#define NVSWITCH_ASSERT(_cond) \ + ((void)((!(_cond)) ? nvswitch_assert_log(__FUNCTION__, __FILE__, __LINE__) : 0)) + #else -#define NVSWITCH_ASSERT(_cond) \ - nvswitch_os_assert_log((_cond), "NVSwitch: Assertion failed \n") +void nvswitch_assert_log(void); + +#define NVSWITCH_ASSERT(_cond) \ + ((void)((!(_cond)) ? nvswitch_assert_log() : 0)) #endif #define NVSWITCH_ASSERT_ERROR_INFO(errorCategory, errorInfo) NVSWITCH_ASSERT(0x0) diff --git a/src/common/nvswitch/kernel/inc/haldef_nvswitch.h b/src/common/nvswitch/kernel/inc/haldef_nvswitch.h index bdb80f5e1..1fce5962b 100644 --- a/src/common/nvswitch/kernel/inc/haldef_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/haldef_nvswitch.h @@ -52,6 +52,7 @@ _op(void, nvswitch_destroy_device_state, (nvswitch_device *device), _arch) \ _op(void, nvswitch_determine_platform, (nvswitch_device *device), _arch) \ _op(NvU32, nvswitch_get_num_links, (nvswitch_device *device), _arch) \ + _op(NvU8, nvswitch_get_num_links_per_nvlipt,(nvswitch_device *device), _arch) \ _op(NvBool, nvswitch_is_link_valid, (nvswitch_device *device, NvU32 link_id), _arch) \ _op(void, nvswitch_set_fatal_error, (nvswitch_device *device, NvBool device_fatal, NvU32 link_id), _arch) \ _op(NvU32, nvswitch_get_swap_clk_default, (nvswitch_device *device), _arch) \ @@ -119,7 +120,6 @@ _op(NvlStatus, nvswitch_deassert_link_reset, (nvswitch_device *device, nvlink_link *link), _arch) \ _op(NvBool, nvswitch_is_soe_supported, (nvswitch_device *device), _arch) \ _op(NvlStatus, nvswitch_init_soe, (nvswitch_device *device), _arch) \ - _op(void, nvswitch_soe_init_l2_state, (nvswitch_device *device), _arch) \ _op(NvBool, nvswitch_is_inforom_supported, (nvswitch_device *device), _arch) \ _op(NvBool, nvswitch_is_spi_supported, (nvswitch_device *device), _arch) \ _op(NvBool, nvswitch_is_smbpbi_supported, (nvswitch_device *device), _arch) \ @@ -138,6 +138,9 @@ _op(NvlStatus, nvswitch_inforom_nvl_update_link_correctable_error_info, (nvswitch_device *device, void *pNvlGeneric, void *pData, NvU8 linkId, NvU8 nvliptInstance, NvU8 localLinkIdx, void *pErrorCounts, NvBool *bDirty), _arch) \ _op(NvlStatus, nvswitch_inforom_nvl_get_max_correctable_error_rate, (nvswitch_device *device, NVSWITCH_GET_NVLINK_MAX_CORRECTABLE_ERROR_RATES_PARAMS *p), _arch) \ _op(NvlStatus, nvswitch_inforom_nvl_get_errors, (nvswitch_device *device, NVSWITCH_GET_NVLINK_ERROR_COUNTS_PARAMS *p), _arch) \ + _op(NvlStatus, nvswitch_inforom_nvl_setL1Threshold, (nvswitch_device *device, void *pNvlGeneric, NvU32 word1, NvU32 word2), _arch) \ + _op(NvlStatus, nvswitch_inforom_nvl_getL1Threshold, (nvswitch_device *device, void *pNvlGeneric, NvU32 *word1, NvU32 *word2), _arch) \ + _op(NvlStatus, nvswitch_inforom_nvl_setup_nvlink_state, (nvswitch_device *device, INFOROM_NVLINK_STATE *pNvlinkState, NvU8 version), _arch) \ _op(NvlStatus, nvswitch_inforom_ecc_get_errors, (nvswitch_device *device, NVSWITCH_GET_ECC_ERROR_COUNTS_PARAMS *p), _arch) \ _op(void, nvswitch_load_uuid, (nvswitch_device *device), _arch) \ _op(void, nvswitch_i2c_set_hw_speed_mode, (nvswitch_device *device, NvU32 port, NvU32 speedMode), _arch) \ @@ -223,8 +226,9 @@ _op(NvlStatus, nvswitch_ctrl_clear_counters, (nvswitch_device *device, NVSWITCH_NVLINK_CLEAR_COUNTERS_PARAMS *ret), _arch) \ _op(NvlStatus, nvswitch_ctrl_set_nvlink_error_threshold, (nvswitch_device *device, NVSWITCH_SET_NVLINK_ERROR_THRESHOLD_PARAMS *pParams), _arch) \ _op(NvlStatus, nvswitch_ctrl_get_nvlink_error_threshold, (nvswitch_device *device, NVSWITCH_GET_NVLINK_ERROR_THRESHOLD_PARAMS *pParams), _arch) \ + _op(NvlStatus, nvswitch_ctrl_get_board_part_number, (nvswitch_device *device, NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR *p), _arch) \ _op(NvlStatus, nvswitch_ctrl_therm_read_voltage, (nvswitch_device *device, NVSWITCH_CTRL_GET_VOLTAGE_PARAMS *info), _arch) \ - _op(NvlStatus, nvswitch_ctrl_get_board_part_number, (nvswitch_device *device, NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR *p), _arch) + _op(void, nvswitch_soe_init_l2_state, (nvswitch_device *device), _arch) \ #define NVSWITCH_HAL_FUNCTION_LIST_LS10(_op, _arch) \ _op(NvlStatus, nvswitch_launch_ALI, (nvswitch_device *device), _arch) \ diff --git a/src/common/nvswitch/kernel/inc/inforom/inforom_nvl_v3_nvswitch.h b/src/common/nvswitch/kernel/inc/inforom/inforom_nvl_v3_nvswitch.h new file mode 100644 index 000000000..8483caf79 --- /dev/null +++ b/src/common/nvswitch/kernel/inc/inforom/inforom_nvl_v3_nvswitch.h @@ -0,0 +1,94 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _INFOROM_NVL_V3_NVSWITCH_H_ +#define _INFOROM_NVL_V3_NVSWITCH_H_ + +#include "inforom/inforom_nvswitch.h" + +#define LUT_ELEMENT(block, dir, subtype, type, sev) \ + { INFOROM_NVL_ERROR_TYPE ## type, \ + FLD_SET_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _SEVERITY, sev, 0) | \ + FLD_SET_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _DIRECTION, dir, 0), \ + block ## dir ## subtype ## type, \ + INFOROM_NVL_ERROR_BLOCK_TYPE_ ## block \ + } + +NvlStatus inforom_nvl_v3_map_error +( + INFOROM_NVLINK_ERROR_TYPES error, + NvU8 *pHeader, + NvU16 *pMetadata, + NvU8 *pErrorSubtype, + INFOROM_NVL_ERROR_BLOCK_TYPE *pBlockType +); + +NvlStatus +inforom_nvl_v3_encode_nvlipt_error_subtype +( + NvU8 localLinkIdx, + NvU8 *pSubtype +); + +NvBool +inforom_nvl_v3_should_replace_error_rate_entry +( + INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE *pErrorRate, + NvU32 flitCrcRate, + NvU32 *pLaneCrcRates +); + +void +inforom_nvl_v3_seconds_to_day_and_month +( + NvU32 sec, + NvU32 *pDay, + NvU32 *pMonth +); + +void +inforom_nvl_v3_update_error_rate_entry +( + INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE *pErrorRate, + NvU32 newSec, + NvU32 newFlitCrcRate, + NvU32 *pNewLaneCrcRates +); + +NvlStatus +inforom_nvl_v3_map_error_to_userspace_error +( + nvswitch_device *device, + INFOROM_NVL_OBJECT_V3_ERROR_ENTRY *pErrorLog, + NVSWITCH_NVLINK_ERROR_ENTRY *pNvlError +); + +void +inforom_nvl_v3_update_correctable_error_rates +( + INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V3S *pState, + NvU8 link, + INFOROM_NVLINK_CORRECTABLE_ERROR_COUNTS *pCounts +); + +#endif //_INFOROM_NVL_V3_NVSWITCH_H_ diff --git a/src/common/nvswitch/kernel/inc/inforom/inforom_nvl_v4_nvswitch.h b/src/common/nvswitch/kernel/inc/inforom/inforom_nvl_v4_nvswitch.h new file mode 100644 index 000000000..5b6f0318b --- /dev/null +++ b/src/common/nvswitch/kernel/inc/inforom/inforom_nvl_v4_nvswitch.h @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _INFOROM_NVL_V4_NVSWITCH_H_ +#define _INFOROM_NVL_V4_NVSWITCH_H_ + +#include "inforom/inforom_nvswitch.h" + +void +inforom_nvl_v4_update_correctable_error_rates +( + INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V4S *pState, + NvU8 link, + INFOROM_NVLINK_CORRECTABLE_ERROR_COUNTS *pCounts +); + +#endif //_INFOROM_NVL_V4_NVSWITCH_H_ diff --git a/src/common/nvswitch/kernel/inc/inforom/inforom_nvswitch.h b/src/common/nvswitch/kernel/inc/inforom/inforom_nvswitch.h index ffad80a8d..7ca5dd415 100644 --- a/src/common/nvswitch/kernel/inc/inforom/inforom_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/inforom/inforom_nvswitch.h @@ -46,6 +46,12 @@ (destName)[2] = (srcName)[2]; \ } +#define m_inforom_nvl_get_new_errors_per_minute(value, pSum) \ + do \ + { \ + *pSum = (*pSum - (*pSum / 60)) + value; \ + } while (NV_FALSE) \ + // // OS type defines. // @@ -99,6 +105,7 @@ struct inforom INFOROM_IMG_OBJECT_V1_00 object; } IMG; + INFOROM_NVLINK_STATE *pNvlinkState; INFOROM_ECC_STATE *pEccState; INFOROM_OMS_STATE *pOmsState; @@ -111,23 +118,23 @@ struct inforom // Generic InfoROM APIs NvlStatus nvswitch_initialize_inforom(nvswitch_device *device); NvlStatus nvswitch_inforom_read_object(nvswitch_device* device, - const char *objectName, const char *pObjectFormat, + const char objectName[3], const char *pObjectFormat, NvU8 *pPackedObject, void *pObject); NvlStatus nvswitch_inforom_write_object(nvswitch_device* device, - const char *objectName, const char *pObjectFormat, + const char objectName[3], const char *pObjectFormat, void *pObject, NvU8 *pOldPackedObject); void nvswitch_destroy_inforom(nvswitch_device *device); NvlStatus nvswitch_inforom_add_object(struct inforom *pInforom, INFOROM_OBJECT_HEADER_V1_00 *pHeader); NvlStatus nvswitch_inforom_get_object_version_info(nvswitch_device *device, - const char *objectName, NvU8 *pVersion, NvU8 *pSubVersion); + const char objectName[3], NvU8 *pVersion, NvU8 *pSubVersion); void *nvswitch_add_halinfo_node(NVListPtr head, int type, int size); void *nvswitch_get_halinfo_node(NVListPtr head, int type); void nvswitch_inforom_post_init(nvswitch_device *device); NvlStatus nvswitch_initialize_inforom_objects(nvswitch_device *device); void nvswitch_destroy_inforom_objects(nvswitch_device *device); NvlStatus nvswitch_inforom_load_object(nvswitch_device* device, - struct inforom *pInforom, const char *objectName, + struct inforom *pInforom, const char objectName[3], const char *pObjectFormat, NvU8 *pPackedObject, void *pObject); void nvswitch_inforom_read_static_data(nvswitch_device *device, struct inforom *pInforom, RM_SOE_SMBPBI_INFOROM_DATA *pData); @@ -149,6 +156,8 @@ NvlStatus nvswitch_inforom_nvlink_get_max_correctable_error_rate(nvswitch_device NVSWITCH_GET_NVLINK_MAX_CORRECTABLE_ERROR_RATES_PARAMS *params); NvlStatus nvswitch_inforom_nvlink_get_errors(nvswitch_device *device, NVSWITCH_GET_NVLINK_ERROR_COUNTS_PARAMS *params); +NvlStatus nvswitch_inforom_nvlink_setL1Threshold(nvswitch_device *device, NvU32 word1, NvU32 word2); +NvlStatus nvswitch_inforom_nvlink_getL1Threshold(nvswitch_device *device, NvU32 *word1, NvU32 *word2); // InfoROM ECC APIs NvlStatus nvswitch_inforom_ecc_load(nvswitch_device *device); diff --git a/src/common/nvswitch/kernel/inc/lr10/inforom_lr10.h b/src/common/nvswitch/kernel/inc/lr10/inforom_lr10.h index 1bea27489..bf12d836f 100644 --- a/src/common/nvswitch/kernel/inc/lr10/inforom_lr10.h +++ b/src/common/nvswitch/kernel/inc/lr10/inforom_lr10.h @@ -58,6 +58,29 @@ nvswitch_inforom_nvl_get_errors_lr10 NVSWITCH_GET_NVLINK_ERROR_COUNTS_PARAMS *params ); +NvlStatus nvswitch_inforom_nvl_setL1Threshold_lr10 +( + nvswitch_device *device, + void *pNvlGeneric, + NvU32 word1, + NvU32 word2 +); + +NvlStatus nvswitch_inforom_nvl_getL1Threshold_lr10 +( + nvswitch_device *device, + void *pNvlGeneric, + NvU32 *word1, + NvU32 *word2 +); + +NvlStatus nvswitch_inforom_nvl_setup_nvlink_state_lr10 +( + nvswitch_device *device, + INFOROM_NVLINK_STATE *pNvlinkState, + NvU8 version +); + NvlStatus nvswitch_inforom_ecc_log_error_event_lr10 ( diff --git a/src/common/nvswitch/kernel/inc/lr10/lr10.h b/src/common/nvswitch/kernel/inc/lr10/lr10.h index 782a573bd..b156426db 100644 --- a/src/common/nvswitch/kernel/inc/lr10/lr10.h +++ b/src/common/nvswitch/kernel/inc/lr10/lr10.h @@ -643,8 +643,8 @@ NvlStatus nvswitch_ctrl_get_nvlink_lp_counters_lr10(nvswitch_device *device, NVS NvlStatus nvswitch_service_nvldl_fatal_link_lr10(nvswitch_device *device, NvU32 nvliptInstance, NvU32 link); NvlStatus nvswitch_ctrl_inband_send_data_lr10(nvswitch_device *device, NVSWITCH_INBAND_SEND_DATA_PARAMS *p); NvlStatus nvswitch_ctrl_inband_read_data_lr10(nvswitch_device *device, NVSWITCH_INBAND_READ_DATA_PARAMS *p); -void nvswitch_send_inband_nack_lr10(nvswitch_device *device, NvU32 *msghdr, NvU32 linkId); -NvU32 nvswitch_get_max_persistent_message_count_lr10(nvswitch_device *device); +void nvswitch_send_inband_nack_lr10(nvswitch_device *device, NvU32 *msghdr, NvU32 linkId); +NvU32 nvswitch_get_max_persistent_message_count_lr10(nvswitch_device *device); NvlStatus nvswitch_launch_ALI_link_training_lr10(nvswitch_device *device, nvlink_link *link, NvBool bSync); NvlStatus nvswitch_service_minion_link_lr10(nvswitch_device *device, NvU32 nvliptInstance); void nvswitch_apply_recal_settings_lr10(nvswitch_device *device, nvlink_link *link); diff --git a/src/common/nvswitch/kernel/inc/ls10/inforom_ls10.h b/src/common/nvswitch/kernel/inc/ls10/inforom_ls10.h index 7848e9943..7ce0e5c73 100644 --- a/src/common/nvswitch/kernel/inc/ls10/inforom_ls10.h +++ b/src/common/nvswitch/kernel/inc/ls10/inforom_ls10.h @@ -44,6 +44,43 @@ NvlStatus nvswitch_inforom_nvl_update_link_correctable_error_info_ls10 NvBool *bDirty ); +NvlStatus +nvswitch_inforom_nvl_get_max_correctable_error_rate_ls10 +( + nvswitch_device *device, + NVSWITCH_GET_NVLINK_MAX_CORRECTABLE_ERROR_RATES_PARAMS *params +); + +NvlStatus +nvswitch_inforom_nvl_get_errors_ls10 +( + nvswitch_device *device, + NVSWITCH_GET_NVLINK_ERROR_COUNTS_PARAMS *params +); + +NvlStatus nvswitch_inforom_nvl_setL1Threshold_ls10 +( + nvswitch_device *device, + void *pNvlGeneric, + NvU32 word1, + NvU32 word2 +); + +NvlStatus nvswitch_inforom_nvl_getL1Threshold_ls10 +( + nvswitch_device *device, + void *pNvlGeneric, + NvU32 *word1, + NvU32 *word2 +); + +NvlStatus nvswitch_inforom_nvl_setup_nvlink_state_ls10 +( + nvswitch_device *device, + INFOROM_NVLINK_STATE *pNvlinkState, + NvU8 version +); + void nvswitch_initialize_oms_state_ls10 ( diff --git a/src/common/nvswitch/kernel/inc/ls10/ls10.h b/src/common/nvswitch/kernel/inc/ls10/ls10.h index 1ed15760d..aa93b0148 100644 --- a/src/common/nvswitch/kernel/inc/ls10/ls10.h +++ b/src/common/nvswitch/kernel/inc/ls10/ls10.h @@ -175,6 +175,9 @@ #define NVSWITCH_NUM_LINKS_PER_NVLIPT_LS10 (NVSWITCH_NUM_LINKS_LS10/NUM_NVLIPT_ENGINE_LS10) +#define NVSWITCH_NVLIPT_GET_PUBLIC_ID_LS10(_physlinknum) \ + ((_physlinknum)/NVSWITCH_LINKS_PER_NVLIPT_LS10) + #define NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LS10(_physlinknum) \ ((_physlinknum)%NVSWITCH_NUM_LINKS_PER_NVLIPT_LS10) @@ -809,10 +812,6 @@ typedef const struct #define nvswitch_corelib_write_discovery_token_ls10 nvswitch_corelib_write_discovery_token_lr10 #define nvswitch_corelib_read_discovery_token_ls10 nvswitch_corelib_read_discovery_token_lr10 -#define nvswitch_inforom_nvl_get_minion_data_ls10 nvswitch_inforom_nvl_get_minion_data_lr10 -#define nvswitch_inforom_nvl_set_minion_data_ls10 nvswitch_inforom_nvl_set_minion_data_lr10 -#define nvswitch_inforom_nvl_get_max_correctable_error_rate_ls10 nvswitch_inforom_nvl_get_max_correctable_error_rate_lr10 -#define nvswitch_inforom_nvl_get_errors_ls10 nvswitch_inforom_nvl_get_errors_lr10 #define nvswitch_inforom_ecc_log_error_event_ls10 nvswitch_inforom_ecc_log_error_event_lr10 #define nvswitch_inforom_ecc_get_errors_ls10 nvswitch_inforom_ecc_get_errors_lr10 #define nvswitch_inforom_bbx_get_sxid_ls10 nvswitch_inforom_bbx_get_sxid_lr10 @@ -889,10 +888,6 @@ NvlStatus nvswitch_corelib_set_tx_mode_lr10(nvlink_link *link, NvU64 mode, NvU32 NvlStatus nvswitch_corelib_get_tl_link_mode_lr10(nvlink_link *link, NvU64 *mode); void nvswitch_init_buffer_ready_lr10(nvswitch_device *device, nvlink_link *link, NvBool bNportBufferReady); -NvlStatus nvswitch_inforom_nvl_get_minion_data_lr10(nvswitch_device *device, void *pNvlGeneric, NvU8 linkId, NvU32 *seedData); -NvlStatus nvswitch_inforom_nvl_set_minion_data_lr10(nvswitch_device *device, void *pNvlGeneric, NvU8 linkId, NvU32 *seedData, NvU32 size, NvBool *bDirty); -NvlStatus nvswitch_inforom_nvl_get_max_correctable_error_rate_lr10(nvswitch_device *device, NVSWITCH_GET_NVLINK_MAX_CORRECTABLE_ERROR_RATES_PARAMS *params); -NvlStatus nvswitch_inforom_nvl_get_errors_lr10(nvswitch_device *device, NVSWITCH_GET_NVLINK_ERROR_COUNTS_PARAMS *params); NvlStatus nvswitch_inforom_ecc_log_error_event_lr10(nvswitch_device *device, INFOROM_ECC_OBJECT *pEccGeneric, INFOROM_NVS_ECC_ERROR_EVENT *err_event); NvlStatus nvswitch_inforom_ecc_get_errors_lr10(nvswitch_device *device, NVSWITCH_GET_ECC_ERROR_COUNTS_PARAMS *params); NvlStatus nvswitch_inforom_bbx_get_sxid_lr10(nvswitch_device *device, NVSWITCH_GET_SXIDS_PARAMS *params); @@ -972,10 +967,10 @@ void nvswitch_store_topology_information_ls10(nvswitch_device *device, nvli NvlStatus nvswitch_ctrl_i2c_indexed_ls10(nvswitch_device *device, NVSWITCH_CTRL_I2C_INDEXED_PARAMS *pParams); NvBool nvswitch_i2c_is_device_access_allowed_ls10(nvswitch_device *device, NvU32 port, NvU8 addr, NvBool bIsRead); NvlStatus nvswitch_minion_get_ali_debug_registers_ls10(nvswitch_device *device, nvlink_link *link, NVSWITCH_MINION_ALI_DEBUG_REGISTERS *params); +void nvswitch_execute_unilateral_link_shutdown_ls10(nvlink_link *link); void nvswitch_setup_link_system_registers_ls10(nvswitch_device *device, nvlink_link *link); void nvswitch_load_link_disable_settings_ls10(nvswitch_device *device, nvlink_link *link); void nvswitch_link_disable_interrupts_ls10(nvswitch_device *device, NvU32 link); -void nvswitch_execute_unilateral_link_shutdown_ls10(nvlink_link *link); void nvswitch_init_dlpl_interrupts_ls10(nvlink_link *link); NvlStatus nvswitch_reset_and_drain_links_ls10(nvswitch_device *device, NvU64 link_mask); @@ -1007,6 +1002,7 @@ void nvswitch_set_error_rate_threshold_ls10(nvlink_link *link, NvBool bIsDe void nvswitch_configure_error_rate_threshold_interrupt_ls10(nvlink_link *link, NvBool bEnable); NvlStatus nvswitch_reset_and_train_link_ls10(nvswitch_device *device, nvlink_link *link); NvBool nvswitch_are_link_clocks_on_ls10(nvswitch_device *device, nvlink_link *link, NvU32 clocksMask); +void nvswitch_get_error_rate_threshold_ls10(nvlink_link *link); #endif //_LS10_H_ diff --git a/src/common/nvswitch/kernel/inc/ls10/multicast_ls10.h b/src/common/nvswitch/kernel/inc/ls10/multicast_ls10.h index 8d4bcc67c..d7046b2b5 100644 --- a/src/common/nvswitch/kernel/inc/ls10/multicast_ls10.h +++ b/src/common/nvswitch/kernel/inc/ls10/multicast_ls10.h @@ -111,10 +111,12 @@ NvlStatus nvswitch_mc_build_mcp_list_ls10(nvswitch_device *device, NvU32 *port_l NvU32 *entries_used); NvlStatus nvswitch_mc_unwind_directives_ls10(nvswitch_device *device, - NVSWITCH_TCP_DIRECTIVE_LS10* directives, - NvU32 *ports, NvU8 *vc_hop, - NvU32 *ports_per_spray_group, NvU32 *replica_offset, - NvBool *replica_valid); + NVSWITCH_TCP_DIRECTIVE_LS10 directives[NVSWITCH_MC_TCP_LIST_SIZE_LS10], + NvU32 ports[NVSWITCH_MC_MAX_PORTS], + NvU8 vc_hop[NVSWITCH_MC_MAX_PORTS], + NvU32 ports_per_spray_group[NVSWITCH_MC_MAX_SPRAYGROUPS], + NvU32 replica_offset[NVSWITCH_MC_MAX_SPRAYGROUPS], + NvBool replica_valid[NVSWITCH_MC_MAX_SPRAYGROUPS]); NvlStatus nvswitch_mc_invalidate_mc_rid_entry_ls10(nvswitch_device *device, NvU32 port, NvU32 index, NvBool use_extended_table, NvBool zero); diff --git a/src/common/nvswitch/kernel/inc/ls10/soe_ls10.h b/src/common/nvswitch/kernel/inc/ls10/soe_ls10.h index 9cb717da8..d01843642 100644 --- a/src/common/nvswitch/kernel/inc/ls10/soe_ls10.h +++ b/src/common/nvswitch/kernel/inc/ls10/soe_ls10.h @@ -39,8 +39,6 @@ void nvswitch_cci_soe_callback_ls10(nvswitch_device *device, RM_FLCN_MSG *pGenMs void *pParams, NvU32 seqDesc, NV_STATUS status); NvlStatus nvswitch_set_nport_tprod_state_ls10(nvswitch_device *device, NvU32 nport); void nvswitch_soe_unregister_events_ls10(nvswitch_device *device); -void nvswitch_therm_soe_callback_ls10(nvswitch_device *device, union RM_FLCN_MSG *pMsg, - void *pParams, NvU32 seqDesc, NV_STATUS status); NvlStatus nvswitch_soe_register_event_callbacks_ls10(nvswitch_device *device); NvlStatus nvswitch_soe_restore_nport_state_ls10(nvswitch_device *device, NvU32 nport); NvlStatus nvswitch_soe_issue_nport_reset_ls10(nvswitch_device *device, NvU32 nport); diff --git a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h index 6f8acdc8e..bbc53edd8 100644 --- a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h +++ b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h @@ -444,7 +444,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xfeffbf22, 0x99900149, 0x0142fe14, 0x94bd9fa0, 0xa00c2290, 0x3da37e29, 0x00a03300, 0xda040b56, 0x00002944, 0x2db2bcb2, 0x0042d77e, 0xa433a032, 0x41fe4300, 0x10119001, 0x8e7e1ab2, 0xa0320033, 0x3100a433, 0x2bbf1cbf, 0x24d1a4bd, 0x7e000014, 0xa000b06c, 0x00a0b31a, 0x7eb43d1a, 0xb300b104, - 0xbf1200a0, 0x7eff001a, 0x3e00b63b, 0x00003371, 0x0149feff, 0xbf149990, 0x05dcd99f, 0x99bf0000, + 0xbf1200a0, 0x7eff001a, 0x3e00b63e, 0x00003371, 0x0149feff, 0xbf149990, 0x05dcd99f, 0x99bf0000, 0xf9a60a32, 0x7e070bf4, 0xfb003a31, 0x0e090c25, 0xa43da9a0, 0x30f400f8, 0x05dcdfd8, 0x62f90000, 0x30f4ffbf, 0x0149fef4, 0xa04c9990, 0xb2a93f9f, 0x01a398a6, 0x0d019033, 0x60489d33, 0x35a33e03, 0x04301800, 0x1b010d33, 0x03329801, 0x3d043198, 0x10dc4ba4, 0xd501004c, 0x00000644, 0x0038327e, @@ -569,7 +569,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x328908f4, 0xfbfa324f, 0xbf02f971, 0xbcb0b2b9, 0xb9a6b0c9, 0xe41708f4, 0xbcffffd9, 0xfba6f09b, 0x980b08f4, 0xf9a60109, 0xf8050df4, 0xb2dc7202, 0x28d77eed, 0xb201fb00, 0x05ab98b9, 0xdeb2cfb2, 0xfd729cb2, 0x0042a97e, 0xf0fc00f8, 0xf9fc30f4, 0xbf62f9f0, 0x08e1b0b9, 0xd4b2a5b2, 0xa630c9bc, - 0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x010124bd, 0x763efc06, 0x02f80043, + 0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x24bd0101, 0x763efc06, 0x02f80043, 0x853e0101, 0x42bc0043, 0x0096b192, 0x060df401, 0x90010049, 0x96ff0399, 0x0b947e04, 0xb23bb200, 0xdd0c725a, 0x00001200, 0x7e3030bc, 0x320028d7, 0x00a433a1, 0x08b0b434, 0xb209c0b4, 0x1200da2d, 0x20bc0000, 0x01004e20, 0x0021367e, 0x0a00a033, 0x853e02f8, 0x00da0043, 0xbd000012, 0x01004cb4, @@ -646,7 +646,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x01b024a1, 0x08113001, 0x300c1130, 0x050d1c01, 0xda00c04e, 0x000005d0, 0x005d0a7e, 0x001404da, 0x0c040b00, 0x59377e08, 0x00ad3300, 0x4d4c00f6, 0x00c3f171, 0x00d8db00, 0xa1300000, 0x00a13028, 0x3010a130, 0xa13014a1, 0x20a13018, 0xb024a130, 0x11300101, 0x0c113008, 0x0d1c0130, 0x00804e09, - 0x0005d4da, 0x5d0a7e00, 0x1428da00, 0x040b0000, 0x377e080c, 0xad330059, 0x4c00a900, 0xc3f1b7c7, + 0x0005d4da, 0x5d0a7e00, 0x1428da00, 0x040b0000, 0x377e080c, 0xad330059, 0x4c00a900, 0xc3f1b7ca, 0xb4db0000, 0x30000000, 0xa13028a1, 0x10a13000, 0x3014a130, 0xa13018a1, 0x24a13020, 0x300c1130, 0x01b01c01, 0x08113001, 0xc04e0a0d, 0x05d8da00, 0x0a7e0000, 0x1cda005d, 0x0b000014, 0x7e080c04, 0x33005937, 0x7e5c00a4, 0x7e005c97, 0x7e004db4, 0x7e005931, 0x7e000a74, 0x7e003cf7, 0x7e005249, @@ -662,7 +662,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x3d071bf4, 0xc700f8a4, 0x96b024f9, 0x0b9cf002, 0x00f89a32, 0x0089050f, 0x9ff60180, 0xb8060f00, 0x00010099, 0xf8009ff6, 0x02008900, 0x0099cf01, 0x1000008f, 0xf4049ffd, 0x34da181b, 0x7e008204, 0xf0001a27, 0x1bf401a4, 0x0a02f809, 0x3d00f824, 0xd900f8a4, 0x00001430, 0x34da99bf, 0x98000014, - 0x95f90e99, 0x1e0a00f8, 0x00b99e7e, 0x0600a033, 0x00f802f8, 0x0100008f, 0xf6590049, 0x00f8009f, + 0x95f90e99, 0x1e0a00f8, 0x00b9a17e, 0x0600a033, 0x00f802f8, 0x0100008f, 0xf6590049, 0x00f8009f, 0x00900089, 0xf00099ce, 0x0bf40194, 0xf1008e20, 0x00e9ce00, 0x9ffdef0f, 0x00e9f704, 0x5200eeb8, 0x00e9ce02, 0xf7049ffd, 0x00f800e9, 0x7e0a004a, 0xe7001a27, 0xb30114aa, 0x4f1e06a4, 0xf9cf4f00, 0xe899c700, 0x110f94b3, 0xf000f9cf, 0x9cf0ff94, 0xf89a320b, 0xf8a43d00, 0x8902f900, 0xce009000, @@ -859,7 +859,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x4c99c700, 0x6a0090b3, 0xf60190b3, 0xde3e02f8, 0xf9cf0066, 0x4c99c700, 0x3a0090b3, 0xf60190b3, 0xf23e02f8, 0x00d90066, 0xbf000014, 0x014bfe9a, 0xbb90080c, 0x006e7e14, 0x0149fe00, 0xbf1c9990, 0x05dcd99f, 0x99bf0000, 0x0bf5f9a6, 0xe03e00ba, 0x00890067, 0x99cf01c2, 0x0608de00, 0x9fc70000, - 0x1899c710, 0x3516ef35, 0x063e15e9, 0xff900067, 0xc1008960, 0x009ff601, 0x0000f1df, 0x0099b880, + 0x1899c710, 0x3515ef35, 0x063e14e9, 0xff900067, 0xc1008960, 0x009ff601, 0x0000f1df, 0x0099b880, 0x9ff70201, 0x009fcf00, 0xf23e9fb2, 0x00890066, 0x99cf01c2, 0x009fe400, 0xff94f120, 0x00fdb33f, 0xc13eff40, 0x448f0066, 0x0089066f, 0x9ff601c1, 0x00f1df00, 0x99b88000, 0xf7020100, 0x9fcf009f, 0x3e9fb200, 0x890066a8, 0xcf01c200, 0x9fe40099, 0x94f12000, 0xfdb33fff, 0x3efec700, 0x8f006681, @@ -1347,17 +1347,17 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xf4004096, 0x9631251d, 0x1cf4005a, 0x00d0331e, 0xffefc41b, 0xf404f9c4, 0xf9c4151b, 0x0294b30a, 0x07a9180b, 0x08009033, 0x00f8060a, 0x00f8a4bd, 0x020f12f9, 0xa0b2b1b2, 0x2200a0b3, 0x94f0a93f, 0x171bf408, 0x00a30f7e, 0x060010b3, 0x09181a20, 0x26060f08, 0x051bf4a9, 0xfab2f4bd, 0xa9b211fb, - 0xc0b3020a, 0x9abf1200, 0xb4b6cdb2, 0x00804c07, 0x00b75e7e, 0x30f400f8, 0x05dcdff8, 0x22f90000, + 0xc0b3020a, 0x9abf1200, 0xb4b6cdb2, 0x00804c07, 0x00b7617e, 0x30f400f8, 0x05dcdff8, 0x22f90000, 0x49feffbf, 0x10999001, 0x9fa0a0b2, 0x00b3020a, 0x0abf3400, 0xb294943d, 0x0141fe07, 0x11902bb2, - 0x20010c0f, 0x7e1db219, 0xb300b775, 0x3f1700a4, 0xb20abf19, 0xf01db22b, 0x010cfd94, 0x5e7e1920, + 0x20010c0f, 0x7e1db219, 0xb300b778, 0x3f1700a4, 0xb20abf19, 0xf01db22b, 0x010cfd94, 0x617e1920, 0x49fe00b7, 0x10999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x25fb003a, 0xf830f408, 0x0005dcdf, 0xbf42f900, 0x0149feff, 0xb2189990, 0xb29fa0a1, 0xb2c0b2b4, 0x00a0b3d3, 0x00c0b356, 0x07cf1852, 0x42fe94bd, 0x14229001, 0xa001ff10, 0x07cf3529, 0x0f7ecab2, 0x2bb200a3, 0xb2080a35, 0xa7b17e1a, 0x00a4b300, 0xb22bbf2c, 0x7e1ab20c, 0xb300a43e, 0xb21e00a4, 0x7e4bb21a, 0xb300a456, 0xb31200a4, 0xbf0e0030, 0x3e32a022, 0x0a00a531, 0x0149fe02, 0xbf189990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0845fb00, 0xc0b202f9, 0x2400a0b3, 0x2000c0b3, 0xb4b6aabf, 0x00804c07, - 0x757e0db2, 0xa4b300b7, 0x0ab21000, 0x00a32f7e, 0x00a5763e, 0x01fb020a, 0x1700a0b3, 0x1300c0b3, - 0xcdb2aabf, 0x0c07b4b6, 0xb7757e10, 0x0a00f800, 0xf900f802, 0xb2b3b242, 0x00a2b2c4, 0x00a0b302, + 0x787e0db2, 0xa4b300b7, 0x0ab21000, 0x00a32f7e, 0x00a5763e, 0x01fb020a, 0x1700a0b3, 0x1300c0b3, + 0xcdb2aabf, 0x0c07b4b6, 0xb7787e10, 0x0a00f800, 0xf900f802, 0xb2b3b242, 0x00a2b2c4, 0x00a0b302, 0xa5e97e42, 0xb2030000, 0x00a0b3a1, 0xb23bb236, 0x7e1cb22a, 0xb200a54c, 0x00a4b3a0, 0xbd1ab21e, 0xa4107eb4, 0xb3a0b200, 0xb31000a4, 0x180c0040, 0x94f00619, 0xb249a0ff, 0x7e1bb22a, 0xb200a60b, 0xf841fb0a, 0xf800f800, 0x98aeb200, 0xa0b30eaa, 0xf4bd0a00, 0x00a6013e, 0xb30fea98, 0x0f0e00a0, @@ -1366,40 +1366,40 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x32a0b222, 0x0ad2b2c1, 0x00b0b302, 0x400cb85e, 0xd4bd0001, 0xb304c998, 0x33440090, 0xb3080014, 0x3f3c0390, 0x26b93fcf, 0x321bf4f9, 0x1801cf18, 0xf92601b9, 0x18271bf4, 0xbf1802ce, 0x90ddbc02, 0xb6909dbc, 0x99b80394, 0xbc000140, 0xef269009, 0xa00b1bf4, 0x3ea4bd29, 0x9000a6a7, 0xcc9001dd, - 0x14d4b318, 0xfb040ab3, 0xb2abbf21, 0xa6f009ac, 0x0d0bf4b9, 0xb503aa98, 0x5b7e01cb, 0x00f800b6, + 0x14d4b318, 0xfb040ab3, 0xb2abbf21, 0xa6f009ac, 0x0d0bf4b9, 0xb503aa98, 0x5e7e01cb, 0x00f800b6, 0xa1b232f9, 0x04bdb2b2, 0xef3ef003, 0x19bf00a6, 0xb2010090, 0xf493a61a, 0x030a090d, 0x00a6f63e, 0x1bf493a6, 0x3e020a09, 0x7e00a6f6, 0xa600a6a9, 0xdd08f402, 0x31fba4bd, 0xdff830f4, 0x000005dc, 0xffbf82f9, 0x900149fe, 0xa3b22899, 0xb8b29fa0, 0x8400a9b3, 0x00b0b300, 0x0147fe7f, 0xbd05a498, - 0xbd54bd24, 0x24779014, 0x00a7603e, 0xbd0c3a98, 0xb002bc94, 0x7cb279a0, 0x00b65b7e, 0xff0f79bf, + 0xbd54bd24, 0x24779014, 0x00a7603e, 0xbd0c3a98, 0xb002bc94, 0x7cb279a0, 0x00b65e7e, 0xff0f79bf, 0x0bf49fa6, 0x3e643d09, 0x9000a74e, 0x00900155, 0xf404a601, 0x6033d908, 0x11900700, 0x2024bc01, 0xa6033998, 0x0b18f429, 0x04bd0106, 0x00a7513e, 0x1ab24bb2, 0x0016fc7e, 0x0df45aa6, 0x01119006, 0x3d063998, 0xf419a6f4, 0x010f050c, 0xa4bd8f20, 0x00a7963e, 0x49fe020a, 0x28999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x85fb003a, 0xf030f408, 0x0005dcdf, 0xbf82f900, 0x0149feff, 0xfe309990, 0x9fa00147, 0xb208a998, 0x09b1b0a6, 0x91b0f105, 0xb2843d0a, 0x2c779090, 0xbd036998, 0xa67fa0f4, 0x0708f409, 0x010804bd, 0xa60a90b4, 0x351bf409, 0x32008033, 0x00a8593e, 0xbc0c6a98, - 0x7cb24010, 0x5b7e4bb2, 0x79bf00b6, 0x9fa6ff0f, 0x900f1bf4, 0xf1090122, 0x1bf439a6, 0x9043b205, - 0x2c3e0111, 0x24bd00a8, 0xf10314bd, 0xa6056998, 0xcb08f419, 0x1e0020b3, 0x18f429a6, 0x0860b50f, + 0x7cb24010, 0x5e7e4bb2, 0x79bf00b6, 0x9fa6ff0f, 0x900f1bf4, 0xf1090122, 0x1bf439a6, 0x9043b205, + 0x2c3e0111, 0x14bd00a8, 0x24bdf103, 0xa6056998, 0xcb08f419, 0x1e0020b3, 0x18f429a6, 0x0860b50f, 0xa009f0b4, 0xa86a3ef3, 0xa6f10f00, 0x051bf45f, 0x09bc05b2, 0xa7dc3e00, 0x091a0a00, 0xf459a6f1, 0x65b50d0b, 0x0990b408, 0xa4bd95a0, 0x900149fe, 0x9fbf3099, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf41085fb, 0xdcd9f830, 0xf9000005, 0xfe99bf82, 0xff90014f, 0xa0a3b228, 0xb2b4b2f9, - 0x00c033d0, 0x3ddab20e, 0x7e140cb4, 0xfe00b78c, 0x14bd0142, 0x08242290, 0x06ff07fe, 0x3efb05fc, - 0x9800a939, 0x94bd0c3a, 0xa0b014bc, 0x7e2cb229, 0xbf00b65b, 0xa6f00f29, 0x560df49f, 0x9fa6fd0f, + 0x00c033d0, 0x3ddab20e, 0x7e140cb4, 0xfe00b78f, 0x14bd0142, 0x08242290, 0x06ff07fe, 0x3efb05fc, + 0x9800a939, 0x94bd0c3a, 0xa0b014bc, 0x7e2cb229, 0xbf00b65e, 0xa6f00f29, 0x560df49f, 0x9fa6fd0f, 0xa6110cf4, 0x3018f496, 0x1bf495a6, 0xa9083e45, 0xf498a600, 0x97a62f0b, 0x98371bf4, 0x99900109, 0x0109b501, 0x00a9363e, 0x90040998, 0x09b50199, 0xa9363e04, 0x02099800, 0xb5019990, 0x363e0209, 0x099800a9, 0x01999003, 0x3e0309b5, 0xbf00a936, 0x01999009, 0x119009a0, 0x05399801, 0x08f419a6, 0x0149fe85, 0xbf289990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0885fb00, 0xdff830f4, 0x000005dc, 0xa1b222f9, 0xb2b2ffbf, 0xbf03aa98, 0x0149fe1b, 0xfe109990, 0x9fa00140, 0xb20c0090, - 0xb65b7e0c, 0x980cbf00, 0x2bb2031a, 0x00b6727e, 0x09011b98, 0xf4b9a6ff, 0x1998101b, 0x0212b504, - 0x3e0292b5, 0x9800a9b0, 0x2cb2031a, 0x00b6727e, 0xbf031a98, 0x7efd0c1b, 0xfe00b672, 0x99900149, + 0xb65e7e0c, 0x980cbf00, 0x2bb2031a, 0x00b6757e, 0x09011b98, 0xf4b9a6ff, 0x1998101b, 0x0212b504, + 0x3e0292b5, 0x9800a9b0, 0x2cb2031a, 0x00b6757e, 0xbf031a98, 0x7efd0c1b, 0xfe00b675, 0x99900149, 0xbf12a010, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0825fb00, 0xdfc830f4, 0x000005dc, 0xffbf82f9, 0xfef830f4, 0x99900149, 0x929fa060, 0xae180499, 0xa0f4bd1c, 0x05a9989f, 0x050aa2b2, - 0x330b91b0, 0x021a00e9, 0x980c2b98, 0x4afe092c, 0x90f10001, 0x44fe44aa, 0x01a6b201, 0xb6877e20, + 0x330b91b0, 0x021a00e9, 0x980c2b98, 0x4afe092c, 0x90f10001, 0x44fe44aa, 0x01a6b201, 0xb68a7e20, 0xb205b200, 0x304490a3, 0x00aa713e, 0xa6082998, 0x310bf439, 0x3bb22ab2, 0x4db2010c, 0x00a8877e, 0xb3044998, 0x981f0094, 0x94b30349, 0x49981800, 0x0094b302, 0xa649bf3b, 0x0918f491, 0x643e30b2, - 0x19b200aa, 0xb20bb0b4, 0x7e6ab291, 0xb200b6a0, 0xf435a6a3, 0x030ab91b, 0x0bf503a6, 0x14b301a3, + 0x19b200aa, 0xb20bb0b4, 0x7e6ab291, 0xb200b6a3, 0xf435a6a3, 0x030ab91b, 0x0bf503a6, 0x14b301a3, 0x03b20c00, 0x8e3e743d, 0x03b200aa, 0x38940107, 0xb254bd07, 0xab9a3e86, 0x0c2a9800, 0x53bce4bd, - 0x014cfe10, 0x9016e1b0, 0x1bb258cc, 0x00b65b7e, 0xf300adb3, 0x1690b400, 0x9fa6f00f, 0x00d80cf5, - 0x2ab294bd, 0x7e1591b0, 0xb200a5e9, 0x00a9b3a4, 0x2abf00d6, 0x804c6bb2, 0x7e4db200, 0xb200b775, + 0x014cfe10, 0x9016e1b0, 0x1bb258cc, 0x00b65e7e, 0xf300adb3, 0x1690b400, 0x9fa6f00f, 0x00d80cf5, + 0x2ab294bd, 0x7e1591b0, 0xb200a5e9, 0x00a9b3a4, 0x2abf00d6, 0x804c6bb2, 0x7e4db200, 0xb200b778, 0x00adb3a0, 0x2ab200a7, 0x4cb21bb2, 0x90014dfe, 0xbd7e50dd, 0xa0b200a4, 0x9000adb3, 0x902ab200, 0x010c014b, 0x90014dfe, 0x3f7e54dd, 0xa0b200a6, 0x7800a4b3, 0x9815b0b4, 0x4afe0c2c, 0x30aa9001, 0x00a6277e, 0xa60c90b4, 0x1e1bf491, 0xfe14b0b4, 0xaa90014a, 0xa95c7e30, 0x1590b400, 0xb3059f98, @@ -1407,8 +1407,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xf99800ab, 0x14e0b402, 0x1bf491a6, 0x02feb506, 0x91a6f9bf, 0xa0091bf4, 0xab883efe, 0x01f99800, 0x1bf491a6, 0x01feb506, 0x2ab24bb2, 0x00a60b7e, 0x130004b3, 0x90015590, 0x29988066, 0xf559a605, 0x33fefa08, 0x98460070, 0x8db2042f, 0x2ab2e4bd, 0x0b00f1b0, 0x0070dc02, 0x41fe0000, 0x5c119001, - 0x7e0111b0, 0x9800a5e3, 0x2abf042c, 0xfb048bb2, 0x00b7477e, 0x2c981ebf, 0xbda0b204, 0xb22ab2b4, - 0xa5e57e0d, 0x0004b300, 0xbdff0406, 0xac003e04, 0x0c2a9800, 0xb2b003bc, 0x0100904c, 0x00b6727e, + 0x7e0111b0, 0x9800a5e3, 0x2abf042c, 0xfb048bb2, 0x00b74a7e, 0x2c981ebf, 0xbda0b204, 0xb22ab2b4, + 0xa5e57e0d, 0x0004b300, 0xbdff0406, 0xac003e04, 0x0c2a9800, 0xb2b003bc, 0x0100904c, 0x00b6757e, 0xa60b90b4, 0xec08f409, 0xbc032f98, 0x29b59039, 0xf49fa609, 0x94bd0808, 0xbd0929b5, 0x0149fea4, 0xbf609990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0830f400, 0xf43885fb, 0xdcd9cc30, 0xf9000005, 0xf499bf82, 0x4ffef830, 0x5cff9001, 0xe1b0f9a0, 0xb2c8b20b, 0xb3a3b2d6, 0x028400b9, @@ -1416,18 +1416,18 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xb3a0b200, 0x025e00ad, 0x68bc17bf, 0x017998f0, 0x08f59fa6, 0x7998024d, 0x0194b304, 0x3e05000a, 0xb300aee1, 0x023e0069, 0x09027f98, 0xf5f9a6f0, 0xb2022a0b, 0xa5e97e3a, 0xb3a2b200, 0x021e00a9, 0xb20c3c98, 0x0140fe7b, 0xb2340090, 0xa6277e0a, 0xb50ab200, 0x8bcc0570, 0xa6c07e70, 0xb3a0b200, - 0x01e900ad, 0x010d00b4, 0xf501a6f0, 0xf501ce0b, 0x3d01d00c, 0x00804cb4, 0x8c7e2ab2, 0x3abf00b7, - 0x4c070b94, 0x2db20080, 0x00b7757e, 0xb30ca1b0, 0x01b600ad, 0x18052918, 0x9476042f, 0xfff4f008, + 0x01e900ad, 0x010d00b4, 0xf501a6f0, 0xf501ce0b, 0x3d01d00c, 0x00804cb4, 0x8f7e2ab2, 0x3abf00b7, + 0x4c070b94, 0x2db20080, 0x00b7787e, 0xb30ca1b0, 0x01b600ad, 0x18052918, 0x9476042f, 0xfff4f008, 0x09e59fff, 0xf5e966ff, 0xe401980b, 0xa6ffffe9, 0x8e08f589, 0xbcf4bd01, 0x9918902f, 0x009d3309, 0xff900182, 0x07f4b301, 0xaefb3ef2, 0xf28e3c00, 0x08f59f26, 0xfdc4016d, 0xff94f0ff, 0xa6529dbc, - 0x050df456, 0xd99065b2, 0xbca43d10, 0xc43db029, 0xa63ee4bd, 0xd6b100ad, 0x0cf5006f, 0x10b40145, + 0x050df456, 0xd99065b2, 0xbce4bd10, 0xa43db029, 0xa63ec43d, 0xd6b100ad, 0x0cf5006f, 0x10b40145, 0x98be3c0b, 0x26f81e3c, 0x170bf4f9, 0x39ff94f0, 0x9ffd0099, 0x00903304, 0x3c010a06, 0x010ce9bf, 0x9001ee90, 0xe5a601dd, 0x33ce08f4, 0x00ed00c9, 0x94f0293f, 0x080bf408, 0xd000a933, 0xb294bd00, 0x1491b03a, 0xb01391b0, 0x91301291, 0x014bfe5b, 0x7e5bbb90, 0xb200a6f8, 0x00adb3a0, 0x903400ef, 0x0090335b, 0x7e3ab211, 0xb200a9d8, 0x00adb3a0, 0x00b400db, 0x1140b40d, 0x90014ffe, 0x2eb250ff, 0xb0070d94, 0x804101f1, 0x0b3ab200, 0xb04cb201, 0xe37e0011, 0x0bb200a5, 0x3ab22cb2, 0x90014dfe, 0xbd7e4cdd, 0xe0b400a4, 0xb2a0b214, 0xbd3ab21c, 0x7e0db2b4, 0xb300a5e5, 0x0091000d, 0xfe13b0b4, - 0xaa90014a, 0xa95c7e34, 0x0c3a9800, 0xfe0db0b4, 0xcc90014c, 0xb65b7e48, 0xb3a0b200, 0xb46d00a4, + 0xaa90014a, 0xa95c7e34, 0x0c3a9800, 0xfe0db0b4, 0xcc90014c, 0xb65e7e48, 0xb3a0b200, 0xb46d00a4, 0xf0011290, 0x1bf491a6, 0x014e9832, 0xb370efcd, 0x0f0600f4, 0x06291870, 0xbcff94f0, 0x9fbb909e, 0x0149b502, 0x00ae983e, 0x3ab20bb2, 0x3e7e2cb2, 0xa0b200a4, 0x3400a4b3, 0xfe0265bb, 0xaa90014a, 0xa6a97e34, 0x0060b300, 0x0b90b420, 0xbc8085bc, 0x91b09095, 0xace43e0b, 0x3e020000, 0x0000aec8, @@ -1440,88 +1440,88 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x00a6277e, 0x2bcc0ab2, 0xa6c07e70, 0xb3a8b200, 0x00ad00ad, 0xfe7021cd, 0x80420147, 0x44779000, 0x00b0373e, 0xbd0c00b4, 0x0979a094, 0xf409a6f0, 0x0200091b, 0x00b03e3e, 0x09a6f009, 0x00090df4, 0xb03e3e03, 0x0bc0b400, 0xbd0704b6, 0xb20db2e4, 0xb0b4bd5a, 0x71b00021, 0xa5e37e01, 0xb25abf00, - 0xb22cb20b, 0xb7757e3d, 0xb27ebf00, 0xb23bb2a0, 0xb22cb25a, 0xa5e57e0d, 0x0004b300, 0xbd3ab245, + 0xb22cb20b, 0xb7787e3d, 0xb27ebf00, 0xb23bb2a0, 0xb22cb25a, 0xa5e57e0d, 0x0004b300, 0xbd3ab245, 0xa4107eb4, 0xb3a0b200, 0x003700a4, 0x0201bb70, 0x0df404a6, 0x9040b205, 0x6ab2101b, 0xb2b03bbc, - 0xb7957e0c, 0x014afe00, 0x900240bb, 0x60bc30aa, 0xa6a97e60, 0xb314bd00, 0xff6d004d, 0x5ab280b2, + 0xb7987e0c, 0x014afe00, 0x900240bb, 0x60bc30aa, 0xa6a97e60, 0xb314bd00, 0xff6d004d, 0x5ab280b2, 0x0b7e3bb2, 0x4c3e00a6, 0x020000b0, 0x900149fe, 0x9fbf4c99, 0x0005dcd9, 0xb299bf00, 0xf4f9a60a, 0x317e070b, 0x30f4003a, 0x2485fb08, 0xd9f830f4, 0x000005dc, 0x99bf32f9, 0x90014ffe, 0xa1b214ff, - 0x94bdf9a0, 0xc3b2b2b2, 0x4b0140fe, 0x00900320, 0xb209a010, 0xb79b7e0a, 0xb309bf00, 0xb34c0090, + 0x94bdf9a0, 0xc3b2b2b2, 0x4b0140fe, 0x00900320, 0xb209a010, 0xb79e7e0a, 0xb309bf00, 0xb34c0090, 0xa04800a4, 0xb509bf91, 0x0fbf0192, 0xb5100049, 0x0fbf04f9, 0xf9b52009, 0xb509bf05, 0x0fbf0693, 0xf9350109, 0x3509bf1c, 0x0fbf2c9a, 0xf9b5f009, 0x900fbf0a, 0xf9b540f9, 0x900fbf0e, 0xf9b5c0f9, 0x3e0abf0f, 0xbd00b0e9, 0x0149fea4, 0xbf149990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, - 0x0835fb00, 0xdfd030f4, 0x000005dc, 0xffbf82f9, 0x900149fe, 0xa3b25099, 0x02059fa0, 0xf800a9b3, - 0x00b63004, 0x350b9cf0, 0x94bd2ca9, 0x7e0ca9b5, 0xb200a5e9, 0xbd3abfa0, 0x00804cb4, 0x757e0db2, - 0xa5b200b7, 0xae00adb3, 0x33093f04, 0x049f4a9d, 0x33010918, 0x0497469d, 0x33020918, 0x048f469d, - 0x33030918, 0x0487539d, 0x18040e18, 0x0f180509, 0x070d1806, 0xf0ffe4f0, 0xf4f0ff94, 0x0894b6ff, - 0xfd10f4b6, 0xd4b6059e, 0x05f9fd18, 0xf505dffd, 0x05045b0b, 0x03d6b005, 0x045a0cf5, 0xb3013db5, + 0x0835fb00, 0xdfd030f4, 0x000005dc, 0xffbf82f9, 0x900149fe, 0xa3b25099, 0x02059fa0, 0xfb00a9b3, + 0x00b63004, 0x350b9cf0, 0x94bd2ca9, 0x7e0ca9b5, 0xb200a5e9, 0xbd3abfa0, 0x00804cb4, 0x787e0db2, + 0xa5b200b7, 0xb100adb3, 0x33093f04, 0x04a24a9d, 0x33010918, 0x049a469d, 0x33020918, 0x0492469d, + 0x33030918, 0x048a539d, 0x18040e18, 0x0f180509, 0x070d1806, 0xf0ffe4f0, 0xf4f0ff94, 0x0894b6ff, + 0xfd10f4b6, 0xd4b6059e, 0x05f9fd18, 0xf505dffd, 0x05045e0b, 0x03d6b005, 0x045d0cf5, 0xb3013db5, 0x490e01d4, 0x39b55000, 0xb1d73e02, 0x080d1800, 0x18090918, 0x0e180a0f, 0xffd4f00b, 0xf0ff94f0, 0x94b6fff4, 0x10f4b608, 0xb6059dfd, 0xf9fd18e4, 0x05effd05, 0xb2023eb5, 0x7e0bb23a, 0x9800a60b, - 0xff09023a, 0xa9a60305, 0x04080bf5, 0x9007a5b6, 0x3ab5303b, 0xb6ce7e03, 0xb3a5b200, 0x03f500ad, - 0x09033b98, 0x343a90c0, 0xfd3fbb90, 0xb5b604b9, 0xb79b7e03, 0xb3a5b200, 0x03d900ad, 0xfe0147fe, - 0x77900148, 0x9044bd40, 0x88900179, 0x0991b03c, 0x00b3443e, 0x8ea0e4bd, 0x0f0044b3, 0xbd0c3a98, - 0x3efe0cb4, 0xb200b267, 0xb24bb23a, 0xa5787e7c, 0xb3a5b200, 0x039d00ad, 0x94f0793f, 0x120bf401, - 0xb20c3a98, 0x7eff0c4b, 0x3e00b672, 0xb200b341, 0xa32f7e7a, 0x00a0b300, 0x0c3a980f, 0xfd0c4bb2, - 0x00b2673e, 0x94f0793f, 0x0e1bf402, 0xb20c3a98, 0x3efd0c4b, 0xb400b336, 0x3ab209b0, 0x8db2010c, - 0x00a63f7e, 0x5d00a0b3, 0x3fb2793f, 0x99c724bd, 0x01999002, 0x980a91b0, 0x54b354f5, 0xb0b43900, - 0x0022bc09, 0x02bc030c, 0x0304b600, 0x014001b8, 0x1031bc00, 0x957e1ab2, 0x30bc00b7, 0x4309b800, - 0x95200001, 0xb45302b5, 0x0fb50af0, 0x3e81a054, 0x9000b301, 0xff900122, 0x1424b318, 0xb62e3ebe, - 0x3f8ebf00, 0x027f5879, 0x98077d18, 0x3a9803ee, 0x0299c70d, 0xcc00f3f0, 0x96cb70ff, 0xcb4bb21f, - 0x010cd8e6, 0xebf0d6cb, 0x7e01e0f6, 0x9800a2e5, 0x4bb20c3a, 0x727e6cb2, 0xa5b200b6, 0xb400adb3, - 0x01449002, 0xa6033b98, 0xeb08f54b, 0xbc94bdfe, 0x89a0b0bb, 0xb17e8ab2, 0xa5b200b7, 0x9400adb3, - 0xbd37b202, 0x547f9884, 0xbc9088bc, 0x94b69098, 0x4099b803, 0x39bc0001, 0x0b91b090, 0x5300f9b3, - 0x033c9802, 0x3d0fa0b4, 0xbc24bdb4, 0x44bdc0cc, 0x00b78c7e, 0x3e0f60b4, 0x9800b45f, 0x2bb20d3a, - 0x7e0c41b0, 0x3300a2f5, 0x00b500a9, 0xfe0c3a98, 0x2bb2014c, 0x7e38cc90, 0xb300b65b, 0x020c00ad, - 0xb40be0b4, 0xef980e90, 0xd899c703, 0x1bf59fa6, 0x3a98008e, 0x0c2bb20d, 0xa2ed7e01, 0x014cfe00, - 0x2bb23ab2, 0x7e30cc90, 0xb300a593, 0x981306a4, 0x2bb20c3a, 0x727efd0c, 0x5c3e00b6, 0xadb300b4, - 0x7401cb00, 0x93f01c90, 0x9099bc00, 0x7f0069bc, 0xff19e401, 0x091bf4ff, 0x5c3e0260, 0x3a9800b4, - 0x014cfe0c, 0xffff1be4, 0x7e34cc90, 0xb300b65b, 0x019800ad, 0x343af034, 0xf9263690, 0x60100df4, - 0xff1be402, 0x0c3a98ff, 0x00b4513e, 0xb20c3a98, 0x7efd0c2b, 0xb300b672, 0x017000ad, 0x98012290, - 0x2aa6033a, 0xff3708f5, 0x6eb264b2, 0xd43db43d, 0xc4bdf4bd, 0x00b4933e, 0x9473e97f, 0x010d0a00, - 0x00b48d3e, 0x0600d033, 0xcc90010b, 0x01ff9001, 0xa602ee90, 0xe308f4fa, 0x0b00c4b3, 0x3e547cb5, - 0x3300b5cf, 0x00a600b9, 0xb0013998, 0x0cf40296, 0xb2030930, 0x5479b56d, 0xf4bde4bd, 0x00b4d23e, - 0x9073d97f, 0x697c0a00, 0x01ee90e9, 0x9001ff90, 0x399802dd, 0xf4f9a603, 0x493ee908, 0x94bd00b5, - 0x79b5f101, 0xb224bd54, 0xb5233e1b, 0xe4407f00, 0xf4ffff09, 0xf10f260b, 0x1bf4bfa6, 0xff0be40b, - 0xb51b3eff, 0x0c3a9800, 0xffff0ce4, 0x00b6727e, 0xb900adb3, 0xff0be400, 0x9019b2ff, 0x44900122, - 0x9891b202, 0x29a60339, 0x09c508f4, 0xf5b9a6f1, 0x9800a00b, 0x3c980c3a, 0xb6727e0a, 0x00adb300, - 0x31b5008c, 0xb5cf3e0a, 0xbd6f7f00, 0x01c19294, 0xf05179b5, 0x04bd00f3, 0x3e527fb5, 0x7f00b587, - 0x014c584b, 0x900c3a98, 0xb3f00100, 0x00c3f000, 0x7e024490, 0xb300b672, 0xb45200a4, 0xe9980be0, - 0x70999001, 0xa601e9b5, 0xd608f401, 0x9808607c, 0xf00c0c3a, 0xffff0be4, 0x00b6727e, 0x2d00a4b3, - 0xe4014cfe, 0xb2ffff0b, 0x40cc903a, 0x00a5787e, 0x1900a4b3, 0x98469034, 0x94f0517f, 0xf0f9bcff, - 0x3e517fb5, 0x0a00b5cf, 0x3ea5b203, 0x9000b5da, 0x77900188, 0x148db318, 0x49fefd90, 0x3c999001, - 0x457e9abf, 0xf03e00b7, 0x030500b5, 0x00b5f23e, 0x0bb204bd, 0x0b7e3ab2, 0x50b300a6, 0x3a981a00, - 0x7e04bd0c, 0x9800b6c4, 0x30b50d3a, 0xb7457e0c, 0x0d30b500, 0x900149fe, 0x9fbf5099, 0x0005dcd9, - 0xb299bf00, 0xf4f9a65a, 0x343e110b, 0x010500b6, 0x00b5f03e, 0x003a317e, 0xf93085fb, 0x7ea0b202, - 0x9800a5e7, 0xc47e0c0a, 0x0a9800b6, 0xb7457e0d, 0x7e0ab200, 0xbd00b745, 0xbf01fba4, 0x0aafb2a9, - 0xf4b9a602, 0xb9900d18, 0x98f9bc01, 0xc9a0a4bd, 0xa9bf00f8, 0x020aafb2, 0x18f4b9a6, 0x01b9900b, - 0xfcbca4bd, 0xbf00f899, 0xb2afb2b9, 0xf4c9a6ca, 0xf10a0708, 0xfbb500f8, 0xb5fca002, 0x00f801fc, - 0xaf98a9bf, 0x90b9bc02, 0xfbbfa9a0, 0x08f49ba6, 0x029bbb08, 0xa998a9a0, 0xa6aabf01, 0x051bf4a9, - 0x00f8f10a, 0x0800a0b3, 0x00b7457e, 0x30f400f8, 0x05dcdff8, 0x32f90000, 0x49feffbf, 0x14999001, - 0x9fa0a0b2, 0xa0b3b3b2, 0xfd024200, 0x0cf4a2a6, 0x01ab903a, 0xb60141fe, 0x119002b4, 0x7e1ab210, - 0xb300b7b1, 0xbf2700a4, 0xb21db219, 0xa0e4bd2c, 0x90dfbf90, 0x9eb201e9, 0xa699fcbc, 0xf408f490, - 0x3da0ddbf, 0x00b72a3e, 0x49fe020a, 0x14999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, - 0x35fb003a, 0xda00f808, 0x00002944, 0x0041c77e, 0xf000a630, 0xa6f00bac, 0x01aab901, 0x44da00f8, - 0x7e000029, 0x30004142, 0xacf000a6, 0x01a6f00b, 0xf801aab9, 0x2944da00, 0xd77e0000, 0xa6300042, - 0x0bacf000, 0xb901a6f0, 0x00f801aa, 0x7effb4f0, 0xf8000b94, 0x0b7e7e00, 0xf900f800, 0x3da0b202, - 0x384c7ea4, 0x00a6b000, 0xa00b9cf0, 0xfb9ab20a, 0xb202f901, 0x7ea43da0, 0xb000382a, 0x9cf000a6, - 0xb20aa00b, 0xf401fb9a, 0xdcdfe430, 0xf9000005, 0xfeffbf82, 0x45fe0149, 0x3c999001, 0xa00147fe, - 0x2455909f, 0xd9347790, 0x0000141c, 0x4bfe9abf, 0x90080c01, 0xff0d2cbb, 0x0000c17e, 0xeb00a433, - 0x3f0c30b4, 0x0c943339, 0x043118e2, 0x0f001033, 0xb0011933, 0x3e043d00, 0x9800b96d, 0x2cd9023f, - 0x98000014, 0x34580431, 0x3f5fa00a, 0x0339989f, 0xb5183690, 0xff090159, 0xf43379a0, 0xf77e1800, - 0xa0320032, 0x2900ad33, 0xdf010901, 0x0000142c, 0x1272f920, 0xbd0043f0, 0xb8ad3e14, 0x0241bc00, - 0x010006b1, 0x40060df4, 0x947e0100, 0x24d9000b, 0xbf000014, 0xff2ce49a, 0xb26bb2ff, 0x1300de0d, - 0x117e0000, 0x7aa000af, 0xd400adb3, 0x985bbf00, 0x1d90015c, 0x7c0eb204, 0x10bc2020, 0x1300da10, - 0x367e0000, 0xa0320021, 0xc500ad33, 0x4cb4bd00, 0x00da0100, 0xa6000013, 0xa408f414, 0x00b95c3e, - 0xd9023f98, 0x0000142c, 0x58043498, 0x5fa00a32, 0x39989f3f, 0x18389003, 0x090159b5, 0x3379a0ff, - 0x7e1600f4, 0x320032f7, 0x00ad33a0, 0x2cdf0084, 0x20000014, 0xff26e4f1, 0x3e24bdff, 0xbc00b94d, - 0x16b11262, 0x0df40100, 0x01004106, 0x000b947e, 0x5c985bbf, 0x042d9001, 0x00da1eb2, 0x7e000013, - 0xe40020d0, 0xbcffff4c, 0xa0322021, 0x1db28bb2, 0x001300de, 0x40417c00, 0x3500a433, 0x001424d9, - 0x7e9abf00, 0xa000ac3b, 0x00a4b37a, 0x4cb4bd13, 0x00da0100, 0xa6000013, 0xa608f426, 0x5c985bbf, - 0xbd7ab201, 0x7e040ed4, 0x32002136, 0x2db034a0, 0x817e3ab2, 0x0d33000f, 0x30fe7100, 0x020f3a01, - 0x1838f130, 0x04090333, 0x30014afe, 0x31303991, 0x90b4bd3b, 0x717e38aa, 0xe73e000f, 0x02f900b7, - 0x002930d9, 0xbfa0b200, 0x7e640b9a, 0x090000de, 0x00a43310, 0xa6008961, 0x009fcf02, 0x1000f5f1, - 0x8a009ff6, 0x4b02a600, 0xc4bd1000, 0xbd27104d, 0x198b7ee4, 0x00a43300, 0x2930d915, 0x9abf0000, - 0x00009b7e, 0x123e0409, 0x0ab200ba, 0x7e03e84b, 0x890016fc, 0xb802a400, 0x000200aa, 0x920aa5b6, - 0x9af601aa, 0x01114f00, 0x020099b8, 0x009ff600, 0x9a32943d, 0x000001fb, 0x00000000, 0x00000000, + 0xff09023a, 0x1bf4a9a6, 0x3e04bd09, 0xb600b5ed, 0x3b9007a5, 0x033ab530, 0x00b6d17e, 0xadb3a5b2, + 0x9803f500, 0xc009033b, 0x90343a90, 0xb9fd3fbb, 0x03b5b604, 0x00b79e7e, 0xadb3a5b2, 0xfe03d900, + 0x48fe0147, 0x40779001, 0x799044bd, 0x3c889001, 0x3e0991b0, 0xbd00b347, 0xb38ea0e4, 0x980f0044, + 0xb4bd0c3a, 0x6a3efe0c, 0x3ab200b2, 0x7cb24bb2, 0x00a5787e, 0xadb3a5b2, 0x3f039d00, 0x0194f079, + 0x98120bf4, 0x4bb20c3a, 0x757eff0c, 0x443e00b6, 0x7ab200b3, 0x00a32f7e, 0x0f00a0b3, 0xb20c3a98, + 0x3efd0c4b, 0x3f00b26a, 0x0294f079, 0x980e1bf4, 0x4bb20c3a, 0x393efd0c, 0xb0b400b3, 0x0c3ab209, + 0x7e8db201, 0xb300a63f, 0x3f5d00a0, 0xbd3fb279, 0x0299c724, 0xb0019990, 0xf5980a91, 0x0054b354, + 0x09b0b439, 0x0c0022bc, 0x0002bc03, 0xb80304b6, 0x00014001, 0xb21031bc, 0xb7987e1a, 0x0030bc00, + 0x014309b8, 0xb5952000, 0xf0b45302, 0x540fb50a, 0x043e81a0, 0x229000b3, 0x18ff9001, 0xbe1424b3, + 0x00b6313e, 0x793f8ebf, 0x18027f58, 0xee98077d, 0x0d3a9803, 0xf00299c7, 0xffcc00f3, 0x1f96cb70, + 0xe6cb4bb2, 0xcb010cd8, 0xf6ebf0d6, 0xe57e01e0, 0x3a9800a2, 0xb24bb20c, 0xb6757e6c, 0xb3a5b200, + 0x02b400ad, 0x98014490, 0x4ba6033b, 0xfeeb08f5, 0xbbbc94bd, 0xb289a0b0, 0xb7b47e8a, 0xb3a5b200, + 0x029400ad, 0x84bd37b2, 0xbc547f98, 0x98bc9088, 0x0394b690, 0x014099b8, 0x9039bc00, 0xb30b91b0, + 0x025300f9, 0xb4033c98, 0xb43d0fa0, 0xccbc24bd, 0x7e44bdc0, 0xb400b78f, 0x623e0f60, 0x3a9800b4, + 0xb02bb20d, 0xf57e0c41, 0xa93300a2, 0x9800b500, 0x4cfe0c3a, 0x902bb201, 0x5e7e38cc, 0xadb300b6, + 0xb4020c00, 0x90b40be0, 0x03ef980e, 0xa6d899c7, 0x8e1bf59f, 0x0d3a9800, 0x010c2bb2, 0x00a2ed7e, + 0xb2014cfe, 0x902bb23a, 0x937e30cc, 0xa4b300a5, 0x3a981306, 0x0c2bb20c, 0xb6757efd, 0xb45f3e00, + 0x00adb300, 0x907401cb, 0x0093f01c, 0xbc9099bc, 0x017f0069, 0xffff19e4, 0x60091bf4, 0xb45f3e02, + 0x0c3a9800, 0xe4014cfe, 0x90ffff1b, 0x5e7e34cc, 0xadb300b6, 0x34019800, 0x90343af0, 0xf4f92636, + 0x0260100d, 0xffff1be4, 0x3e0c3a98, 0x9800b454, 0x2bb20c3a, 0x757efd0c, 0xadb300b6, 0x90017000, + 0x3a980122, 0xf52aa603, 0xb2ff3708, 0x3d6eb264, 0xbdd43db4, 0x3ec4bdf4, 0x7f00b496, 0x009473e9, + 0x3e010d0a, 0x3300b490, 0x0b0600d0, 0x01cc9001, 0x9001ff90, 0xfaa602ee, 0xb3e308f4, 0xb50b00c4, + 0xd23e547c, 0xb93300b5, 0x9800a600, 0x96b00139, 0x300cf402, 0x6db20309, 0xbd5479b5, 0x3ef4bde4, + 0x7f00b4d5, 0x009073d9, 0xe9697c0a, 0x9001ee90, 0xdd9001ff, 0x03399802, 0x08f4f9a6, 0xb54c3ee9, + 0x0194bd00, 0x5479b5f1, 0x1bb224bd, 0x00b5263e, 0x09e4407f, 0x0bf4ffff, 0xa6f10f26, 0x0b1bf4bf, + 0xffff0be4, 0x00b51e3e, 0xe40c3a98, 0x7effff0c, 0xb300b675, 0x00b900ad, 0xffff0be4, 0x229019b2, + 0x02449001, 0x399891b2, 0xf429a603, 0xf109c508, 0x0bf5b9a6, 0x3a9800a0, 0x0a3c980c, 0x00b6757e, + 0x8c00adb3, 0x0a31b500, 0x00b5d23e, 0x94bd6f7f, 0xb501c192, 0xf3f05179, 0xb504bd00, 0x8a3e527f, + 0x4b7f00b5, 0x98014c58, 0x00900c3a, 0x00b3f001, 0x9000c3f0, 0x757e0244, 0xa4b300b6, 0xe0b45200, + 0x01e9980b, 0xb5709990, 0x01a601e9, 0x7cd608f4, 0x3a980860, 0xe4f00c0c, 0x7effff0b, 0xb300b675, + 0xfe2d00a4, 0x0be4014c, 0x3ab2ffff, 0x7e40cc90, 0xb300a578, 0x341900a4, 0x7f984690, 0xff94f051, + 0xb5f0f9bc, 0xd23e517f, 0x030a00b5, 0xdd3ea5b2, 0x889000b5, 0x18779001, 0x90148db3, 0x0149fefd, + 0xbf3c9990, 0xb7487e9a, 0xb5f33e00, 0x3e030500, 0xbd00b5f5, 0xb20bb204, 0xa60b7e3a, 0x0050b300, + 0x0c3a981a, 0xc77e04bd, 0x3a9800b6, 0x0c30b50d, 0x00b7487e, 0xfe0d30b5, 0x99900149, 0xd99fbf50, + 0x000005dc, 0x5ab299bf, 0x0bf4f9a6, 0xb6373e11, 0x3e010500, 0x7e00b5f3, 0xfb003a31, 0x02f93085, + 0xe77ea0b2, 0x0a9800a5, 0xb6c77e0c, 0x0d0a9800, 0x00b7487e, 0x487e0ab2, 0xa4bd00b7, 0xa9bf01fb, + 0x020aafb2, 0x18f4b9a6, 0x01b9900d, 0xbd98f9bc, 0xf8c9a0a4, 0xb2a9bf00, 0xa6020aaf, 0x0b18f4b9, + 0xbd01b990, 0x99fcbca4, 0xb9bf00f8, 0xcab2afb2, 0x08f4c9a6, 0xf8f10a07, 0x02fbb500, 0xfcb5fca0, + 0xbf00f801, 0x02af98a9, 0xa090b9bc, 0xa6fbbfa9, 0x0808f49b, 0xa0029bbb, 0x01a998a9, 0xa9a6aabf, + 0x0a051bf4, 0xb300f8f1, 0x7e0800a0, 0xf800b748, 0xf830f400, 0x0005dcdf, 0xbf32f900, 0x0149feff, + 0xb2149990, 0xb29fa0a0, 0x00a0b3b3, 0xa6fd0242, 0x3a0cf4a2, 0xfe01ab90, 0xb4b60141, 0x10119002, + 0xb47e1ab2, 0xa4b300b7, 0x19bf2700, 0x2cb21db2, 0x90a0e4bd, 0xe990dfbf, 0xbc9eb201, 0x90a699fc, + 0xbff408f4, 0x3e3da0dd, 0x0a00b72d, 0x0149fe02, 0xbf149990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, + 0x3a317e07, 0x0835fb00, 0x44da00f8, 0x7e000029, 0x300041c7, 0xacf000a6, 0x01a6f00b, 0xf801aab9, + 0x2944da00, 0x427e0000, 0xa6300041, 0x0bacf000, 0xb901a6f0, 0x00f801aa, 0x002944da, 0x42d77e00, + 0x00a63000, 0xf00bacf0, 0xaab901a6, 0xf000f801, 0x947effb4, 0x00f8000b, 0x000b7e7e, 0x02f900f8, + 0xa43da0b2, 0x00384c7e, 0xf000a6b0, 0x0aa00b9c, 0x01fb9ab2, 0xa0b202f9, 0x2a7ea43d, 0xa6b00038, + 0x0b9cf000, 0x9ab20aa0, 0x30f401fb, 0x05dcdfe4, 0x82f90000, 0x49feffbf, 0x0145fe01, 0xfe3c9990, + 0x9fa00147, 0x90245590, 0x1cd93477, 0xbf000014, 0x014bfe9a, 0xbb90080c, 0x7eff0d2c, 0x330000c1, + 0xb4eb00a4, 0x393f0c30, 0xe20c9433, 0x33043118, 0x330f0010, 0x00b00119, 0x703e043d, 0x3f9800b9, + 0x142cd902, 0x31980000, 0x0a345804, 0x9f3f5fa0, 0x90033998, 0x59b51836, 0xa0ff0901, 0x00f43379, + 0x32f77e18, 0x33a03200, 0x012900ad, 0x2cdf0109, 0x20000014, 0xf01272f9, 0x14bd0043, 0x00b8b03e, + 0xb10241bc, 0xf4010006, 0x0040060d, 0x0b947e01, 0x1424d900, 0x9abf0000, 0xffff2ce4, 0x0db26bb2, + 0x001300de, 0xaf117e00, 0xb37aa000, 0x00d400ad, 0x5c985bbf, 0x041d9001, 0x207c0eb2, 0x1010bc20, + 0x001300da, 0x21367e00, 0x33a03200, 0x00c500ad, 0x004cb4bd, 0x1300da01, 0x14a60000, 0x3ea408f4, + 0x9800b95f, 0x2cd9023f, 0x98000014, 0x32580434, 0x3f5fa00a, 0x0339989f, 0xb5183890, 0xff090159, + 0xf43379a0, 0xf77e1600, 0xa0320032, 0x8400ad33, 0x142cdf00, 0xf1200000, 0xffff26e4, 0x503e24bd, + 0x62bc00b9, 0x0016b112, 0x060df401, 0x7e010041, 0xbf000b94, 0x015c985b, 0xb2042d90, 0x1300da1e, + 0xd07e0000, 0x4ce40020, 0x21bcffff, 0xb2a03220, 0xde1db28b, 0x00001300, 0x3340417c, 0xd93500a4, + 0x00001424, 0x3b7e9abf, 0x7aa000ac, 0x1300a4b3, 0x004cb4bd, 0x1300da01, 0x26a60000, 0xbfa608f4, + 0x015c985b, 0xd4bd7ab2, 0x367e040e, 0xa0320021, 0xb22db034, 0x0f817e3a, 0x000d3300, 0x0130fe71, + 0x30020f3a, 0x331838f1, 0xfe040903, 0x9130014a, 0x3b313039, 0xaa90b4bd, 0x0f717e38, 0xb7ea3e00, + 0xd902f900, 0x00002930, 0x9abfa0b2, 0xde7e640b, 0x10090000, 0x6100a433, 0x02a60089, 0xf1009fcf, + 0xf61000f5, 0x008a009f, 0x004b02a6, 0x4dc4bd10, 0xe4bd2710, 0x00198b7e, 0x1500a433, 0x002930d9, + 0x7e9abf00, 0x0900009b, 0xba153e04, 0x4b0ab200, 0xfc7e03e8, 0x00890016, 0xaab802a4, 0xb6000200, + 0xaa920aa5, 0x009af601, 0xb801114f, 0x00020099, 0x3d009ff6, 0xfb9a3294, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0xb22438cf, 0xcfd90bc8, 0xf23ebc55, 0x2e5c0e40, - 0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0x0d4a5d7d, 0x9c31ffb3, 0x95bc604f, 0x40cc834d, + 0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0x1289f13d, 0xdc6acca2, 0x50be285c, 0xd086f67e, + 0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0xc901a2e3, 0xd0a96e16, 0x4a0da134, 0xc2405c59, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, diff --git a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h index eeebeb6dc..78426d9d2 100644 --- a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h +++ b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h @@ -444,7 +444,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xfeffbf22, 0x99900149, 0x0142fe14, 0x94bd9fa0, 0xa00c2290, 0x3da37e29, 0x00a03300, 0xda040b56, 0x00002944, 0x2db2bcb2, 0x0042d77e, 0xa433a032, 0x41fe4300, 0x10119001, 0x8e7e1ab2, 0xa0320033, 0x3100a433, 0x2bbf1cbf, 0x24d1a4bd, 0x7e000014, 0xa000b06c, 0x00a0b31a, 0x7eb43d1a, 0xb300b104, - 0xbf1200a0, 0x7eff001a, 0x3e00b63b, 0x00003371, 0x0149feff, 0xbf149990, 0x05dcd99f, 0x99bf0000, + 0xbf1200a0, 0x7eff001a, 0x3e00b63e, 0x00003371, 0x0149feff, 0xbf149990, 0x05dcd99f, 0x99bf0000, 0xf9a60a32, 0x7e070bf4, 0xfb003a31, 0x0e090c25, 0xa43da9a0, 0x30f400f8, 0x05dcdfd8, 0x62f90000, 0x30f4ffbf, 0x0149fef4, 0xa04c9990, 0xb2a93f9f, 0x01a398a6, 0x0d019033, 0x60489d33, 0x35a33e03, 0x04301800, 0x1b010d33, 0x03329801, 0x3d043198, 0x10dc4ba4, 0xd501004c, 0x00000644, 0x0038327e, @@ -569,7 +569,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x328908f4, 0xfbfa324f, 0xbf02f971, 0xbcb0b2b9, 0xb9a6b0c9, 0xe41708f4, 0xbcffffd9, 0xfba6f09b, 0x980b08f4, 0xf9a60109, 0xf8050df4, 0xb2dc7202, 0x28d77eed, 0xb201fb00, 0x05ab98b9, 0xdeb2cfb2, 0xfd729cb2, 0x0042a97e, 0xf0fc00f8, 0xf9fc30f4, 0xbf62f9f0, 0x08e1b0b9, 0xd4b2a5b2, 0xa630c9bc, - 0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x010124bd, 0x763efc06, 0x02f80043, + 0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x24bd0101, 0x763efc06, 0x02f80043, 0x853e0101, 0x42bc0043, 0x0096b192, 0x060df401, 0x90010049, 0x96ff0399, 0x0b947e04, 0xb23bb200, 0xdd0c725a, 0x00001200, 0x7e3030bc, 0x320028d7, 0x00a433a1, 0x08b0b434, 0xb209c0b4, 0x1200da2d, 0x20bc0000, 0x01004e20, 0x0021367e, 0x0a00a033, 0x853e02f8, 0x00da0043, 0xbd000012, 0x01004cb4, @@ -646,7 +646,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x01b024a1, 0x08113001, 0x300c1130, 0x050d1c01, 0xda00c04e, 0x000005d0, 0x005d0a7e, 0x001404da, 0x0c040b00, 0x59377e08, 0x00ad3300, 0x4d4c00f6, 0x00c3f171, 0x00d8db00, 0xa1300000, 0x00a13028, 0x3010a130, 0xa13014a1, 0x20a13018, 0xb024a130, 0x11300101, 0x0c113008, 0x0d1c0130, 0x00804e09, - 0x0005d4da, 0x5d0a7e00, 0x1428da00, 0x040b0000, 0x377e080c, 0xad330059, 0x4c00a900, 0xc3f1b7c7, + 0x0005d4da, 0x5d0a7e00, 0x1428da00, 0x040b0000, 0x377e080c, 0xad330059, 0x4c00a900, 0xc3f1b7ca, 0xb4db0000, 0x30000000, 0xa13028a1, 0x10a13000, 0x3014a130, 0xa13018a1, 0x24a13020, 0x300c1130, 0x01b01c01, 0x08113001, 0xc04e0a0d, 0x05d8da00, 0x0a7e0000, 0x1cda005d, 0x0b000014, 0x7e080c04, 0x33005937, 0x7e5c00a4, 0x7e005c97, 0x7e004db4, 0x7e005931, 0x7e000a74, 0x7e003cf7, 0x7e005249, @@ -662,7 +662,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x3d071bf4, 0xc700f8a4, 0x96b024f9, 0x0b9cf002, 0x00f89a32, 0x0089050f, 0x9ff60180, 0xb8060f00, 0x00010099, 0xf8009ff6, 0x02008900, 0x0099cf01, 0x1000008f, 0xf4049ffd, 0x34da181b, 0x7e008204, 0xf0001a27, 0x1bf401a4, 0x0a02f809, 0x3d00f824, 0xd900f8a4, 0x00001430, 0x34da99bf, 0x98000014, - 0x95f90e99, 0x1e0a00f8, 0x00b99e7e, 0x0600a033, 0x00f802f8, 0x0100008f, 0xf6590049, 0x00f8009f, + 0x95f90e99, 0x1e0a00f8, 0x00b9a17e, 0x0600a033, 0x00f802f8, 0x0100008f, 0xf6590049, 0x00f8009f, 0x00900089, 0xf00099ce, 0x0bf40194, 0xf1008e20, 0x00e9ce00, 0x9ffdef0f, 0x00e9f704, 0x5200eeb8, 0x00e9ce02, 0xf7049ffd, 0x00f800e9, 0x7e0a004a, 0xe7001a27, 0xb30114aa, 0x4f1e06a4, 0xf9cf4f00, 0xe899c700, 0x110f94b3, 0xf000f9cf, 0x9cf0ff94, 0xf89a320b, 0xf8a43d00, 0x8902f900, 0xce009000, @@ -859,7 +859,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x4c99c700, 0x6a0090b3, 0xf60190b3, 0xde3e02f8, 0xf9cf0066, 0x4c99c700, 0x3a0090b3, 0xf60190b3, 0xf23e02f8, 0x00d90066, 0xbf000014, 0x014bfe9a, 0xbb90080c, 0x006e7e14, 0x0149fe00, 0xbf1c9990, 0x05dcd99f, 0x99bf0000, 0x0bf5f9a6, 0xe03e00ba, 0x00890067, 0x99cf01c2, 0x0608de00, 0x9fc70000, - 0x1899c710, 0x3516ef35, 0x063e15e9, 0xff900067, 0xc1008960, 0x009ff601, 0x0000f1df, 0x0099b880, + 0x1899c710, 0x3515ef35, 0x063e14e9, 0xff900067, 0xc1008960, 0x009ff601, 0x0000f1df, 0x0099b880, 0x9ff70201, 0x009fcf00, 0xf23e9fb2, 0x00890066, 0x99cf01c2, 0x009fe400, 0xff94f120, 0x00fdb33f, 0xc13eff40, 0x448f0066, 0x0089066f, 0x9ff601c1, 0x00f1df00, 0x99b88000, 0xf7020100, 0x9fcf009f, 0x3e9fb200, 0x890066a8, 0xcf01c200, 0x9fe40099, 0x94f12000, 0xfdb33fff, 0x3efec700, 0x8f006681, @@ -1347,17 +1347,17 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xf4004096, 0x9631251d, 0x1cf4005a, 0x00d0331e, 0xffefc41b, 0xf404f9c4, 0xf9c4151b, 0x0294b30a, 0x07a9180b, 0x08009033, 0x00f8060a, 0x00f8a4bd, 0x020f12f9, 0xa0b2b1b2, 0x2200a0b3, 0x94f0a93f, 0x171bf408, 0x00a30f7e, 0x060010b3, 0x09181a20, 0x26060f08, 0x051bf4a9, 0xfab2f4bd, 0xa9b211fb, - 0xc0b3020a, 0x9abf1200, 0xb4b6cdb2, 0x00804c07, 0x00b75e7e, 0x30f400f8, 0x05dcdff8, 0x22f90000, + 0xc0b3020a, 0x9abf1200, 0xb4b6cdb2, 0x00804c07, 0x00b7617e, 0x30f400f8, 0x05dcdff8, 0x22f90000, 0x49feffbf, 0x10999001, 0x9fa0a0b2, 0x00b3020a, 0x0abf3400, 0xb294943d, 0x0141fe07, 0x11902bb2, - 0x20010c0f, 0x7e1db219, 0xb300b775, 0x3f1700a4, 0xb20abf19, 0xf01db22b, 0x010cfd94, 0x5e7e1920, + 0x20010c0f, 0x7e1db219, 0xb300b778, 0x3f1700a4, 0xb20abf19, 0xf01db22b, 0x010cfd94, 0x617e1920, 0x49fe00b7, 0x10999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x25fb003a, 0xf830f408, 0x0005dcdf, 0xbf42f900, 0x0149feff, 0xb2189990, 0xb29fa0a1, 0xb2c0b2b4, 0x00a0b3d3, 0x00c0b356, 0x07cf1852, 0x42fe94bd, 0x14229001, 0xa001ff10, 0x07cf3529, 0x0f7ecab2, 0x2bb200a3, 0xb2080a35, 0xa7b17e1a, 0x00a4b300, 0xb22bbf2c, 0x7e1ab20c, 0xb300a43e, 0xb21e00a4, 0x7e4bb21a, 0xb300a456, 0xb31200a4, 0xbf0e0030, 0x3e32a022, 0x0a00a531, 0x0149fe02, 0xbf189990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0845fb00, 0xc0b202f9, 0x2400a0b3, 0x2000c0b3, 0xb4b6aabf, 0x00804c07, - 0x757e0db2, 0xa4b300b7, 0x0ab21000, 0x00a32f7e, 0x00a5763e, 0x01fb020a, 0x1700a0b3, 0x1300c0b3, - 0xcdb2aabf, 0x0c07b4b6, 0xb7757e10, 0x0a00f800, 0xf900f802, 0xb2b3b242, 0x00a2b2c4, 0x00a0b302, + 0x787e0db2, 0xa4b300b7, 0x0ab21000, 0x00a32f7e, 0x00a5763e, 0x01fb020a, 0x1700a0b3, 0x1300c0b3, + 0xcdb2aabf, 0x0c07b4b6, 0xb7787e10, 0x0a00f800, 0xf900f802, 0xb2b3b242, 0x00a2b2c4, 0x00a0b302, 0xa5e97e42, 0xb2030000, 0x00a0b3a1, 0xb23bb236, 0x7e1cb22a, 0xb200a54c, 0x00a4b3a0, 0xbd1ab21e, 0xa4107eb4, 0xb3a0b200, 0xb31000a4, 0x180c0040, 0x94f00619, 0xb249a0ff, 0x7e1bb22a, 0xb200a60b, 0xf841fb0a, 0xf800f800, 0x98aeb200, 0xa0b30eaa, 0xf4bd0a00, 0x00a6013e, 0xb30fea98, 0x0f0e00a0, @@ -1366,40 +1366,40 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x32a0b222, 0x0ad2b2c1, 0x00b0b302, 0x400cb85e, 0xd4bd0001, 0xb304c998, 0x33440090, 0xb3080014, 0x3f3c0390, 0x26b93fcf, 0x321bf4f9, 0x1801cf18, 0xf92601b9, 0x18271bf4, 0xbf1802ce, 0x90ddbc02, 0xb6909dbc, 0x99b80394, 0xbc000140, 0xef269009, 0xa00b1bf4, 0x3ea4bd29, 0x9000a6a7, 0xcc9001dd, - 0x14d4b318, 0xfb040ab3, 0xb2abbf21, 0xa6f009ac, 0x0d0bf4b9, 0xb503aa98, 0x5b7e01cb, 0x00f800b6, + 0x14d4b318, 0xfb040ab3, 0xb2abbf21, 0xa6f009ac, 0x0d0bf4b9, 0xb503aa98, 0x5e7e01cb, 0x00f800b6, 0xa1b232f9, 0x04bdb2b2, 0xef3ef003, 0x19bf00a6, 0xb2010090, 0xf493a61a, 0x030a090d, 0x00a6f63e, 0x1bf493a6, 0x3e020a09, 0x7e00a6f6, 0xa600a6a9, 0xdd08f402, 0x31fba4bd, 0xdff830f4, 0x000005dc, 0xffbf82f9, 0x900149fe, 0xa3b22899, 0xb8b29fa0, 0x8400a9b3, 0x00b0b300, 0x0147fe7f, 0xbd05a498, - 0xbd54bd24, 0x24779014, 0x00a7603e, 0xbd0c3a98, 0xb002bc94, 0x7cb279a0, 0x00b65b7e, 0xff0f79bf, + 0xbd54bd24, 0x24779014, 0x00a7603e, 0xbd0c3a98, 0xb002bc94, 0x7cb279a0, 0x00b65e7e, 0xff0f79bf, 0x0bf49fa6, 0x3e643d09, 0x9000a74e, 0x00900155, 0xf404a601, 0x6033d908, 0x11900700, 0x2024bc01, 0xa6033998, 0x0b18f429, 0x04bd0106, 0x00a7513e, 0x1ab24bb2, 0x0016fc7e, 0x0df45aa6, 0x01119006, 0x3d063998, 0xf419a6f4, 0x010f050c, 0xa4bd8f20, 0x00a7963e, 0x49fe020a, 0x28999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x85fb003a, 0xf030f408, 0x0005dcdf, 0xbf82f900, 0x0149feff, 0xfe309990, 0x9fa00147, 0xb208a998, 0x09b1b0a6, 0x91b0f105, 0xb2843d0a, 0x2c779090, 0xbd036998, 0xa67fa0f4, 0x0708f409, 0x010804bd, 0xa60a90b4, 0x351bf409, 0x32008033, 0x00a8593e, 0xbc0c6a98, - 0x7cb24010, 0x5b7e4bb2, 0x79bf00b6, 0x9fa6ff0f, 0x900f1bf4, 0xf1090122, 0x1bf439a6, 0x9043b205, - 0x2c3e0111, 0x24bd00a8, 0xf10314bd, 0xa6056998, 0xcb08f419, 0x1e0020b3, 0x18f429a6, 0x0860b50f, + 0x7cb24010, 0x5e7e4bb2, 0x79bf00b6, 0x9fa6ff0f, 0x900f1bf4, 0xf1090122, 0x1bf439a6, 0x9043b205, + 0x2c3e0111, 0x14bd00a8, 0x24bdf103, 0xa6056998, 0xcb08f419, 0x1e0020b3, 0x18f429a6, 0x0860b50f, 0xa009f0b4, 0xa86a3ef3, 0xa6f10f00, 0x051bf45f, 0x09bc05b2, 0xa7dc3e00, 0x091a0a00, 0xf459a6f1, 0x65b50d0b, 0x0990b408, 0xa4bd95a0, 0x900149fe, 0x9fbf3099, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf41085fb, 0xdcd9f830, 0xf9000005, 0xfe99bf82, 0xff90014f, 0xa0a3b228, 0xb2b4b2f9, - 0x00c033d0, 0x3ddab20e, 0x7e140cb4, 0xfe00b78c, 0x14bd0142, 0x08242290, 0x06ff07fe, 0x3efb05fc, - 0x9800a939, 0x94bd0c3a, 0xa0b014bc, 0x7e2cb229, 0xbf00b65b, 0xa6f00f29, 0x560df49f, 0x9fa6fd0f, + 0x00c033d0, 0x3ddab20e, 0x7e140cb4, 0xfe00b78f, 0x14bd0142, 0x08242290, 0x06ff07fe, 0x3efb05fc, + 0x9800a939, 0x94bd0c3a, 0xa0b014bc, 0x7e2cb229, 0xbf00b65e, 0xa6f00f29, 0x560df49f, 0x9fa6fd0f, 0xa6110cf4, 0x3018f496, 0x1bf495a6, 0xa9083e45, 0xf498a600, 0x97a62f0b, 0x98371bf4, 0x99900109, 0x0109b501, 0x00a9363e, 0x90040998, 0x09b50199, 0xa9363e04, 0x02099800, 0xb5019990, 0x363e0209, 0x099800a9, 0x01999003, 0x3e0309b5, 0xbf00a936, 0x01999009, 0x119009a0, 0x05399801, 0x08f419a6, 0x0149fe85, 0xbf289990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0885fb00, 0xdff830f4, 0x000005dc, 0xa1b222f9, 0xb2b2ffbf, 0xbf03aa98, 0x0149fe1b, 0xfe109990, 0x9fa00140, 0xb20c0090, - 0xb65b7e0c, 0x980cbf00, 0x2bb2031a, 0x00b6727e, 0x09011b98, 0xf4b9a6ff, 0x1998101b, 0x0212b504, - 0x3e0292b5, 0x9800a9b0, 0x2cb2031a, 0x00b6727e, 0xbf031a98, 0x7efd0c1b, 0xfe00b672, 0x99900149, + 0xb65e7e0c, 0x980cbf00, 0x2bb2031a, 0x00b6757e, 0x09011b98, 0xf4b9a6ff, 0x1998101b, 0x0212b504, + 0x3e0292b5, 0x9800a9b0, 0x2cb2031a, 0x00b6757e, 0xbf031a98, 0x7efd0c1b, 0xfe00b675, 0x99900149, 0xbf12a010, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0825fb00, 0xdfc830f4, 0x000005dc, 0xffbf82f9, 0xfef830f4, 0x99900149, 0x929fa060, 0xae180499, 0xa0f4bd1c, 0x05a9989f, 0x050aa2b2, - 0x330b91b0, 0x021a00e9, 0x980c2b98, 0x4afe092c, 0x90f10001, 0x44fe44aa, 0x01a6b201, 0xb6877e20, + 0x330b91b0, 0x021a00e9, 0x980c2b98, 0x4afe092c, 0x90f10001, 0x44fe44aa, 0x01a6b201, 0xb68a7e20, 0xb205b200, 0x304490a3, 0x00aa713e, 0xa6082998, 0x310bf439, 0x3bb22ab2, 0x4db2010c, 0x00a8877e, 0xb3044998, 0x981f0094, 0x94b30349, 0x49981800, 0x0094b302, 0xa649bf3b, 0x0918f491, 0x643e30b2, - 0x19b200aa, 0xb20bb0b4, 0x7e6ab291, 0xb200b6a0, 0xf435a6a3, 0x030ab91b, 0x0bf503a6, 0x14b301a3, + 0x19b200aa, 0xb20bb0b4, 0x7e6ab291, 0xb200b6a3, 0xf435a6a3, 0x030ab91b, 0x0bf503a6, 0x14b301a3, 0x03b20c00, 0x8e3e743d, 0x03b200aa, 0x38940107, 0xb254bd07, 0xab9a3e86, 0x0c2a9800, 0x53bce4bd, - 0x014cfe10, 0x9016e1b0, 0x1bb258cc, 0x00b65b7e, 0xf300adb3, 0x1690b400, 0x9fa6f00f, 0x00d80cf5, - 0x2ab294bd, 0x7e1591b0, 0xb200a5e9, 0x00a9b3a4, 0x2abf00d6, 0x804c6bb2, 0x7e4db200, 0xb200b775, + 0x014cfe10, 0x9016e1b0, 0x1bb258cc, 0x00b65e7e, 0xf300adb3, 0x1690b400, 0x9fa6f00f, 0x00d80cf5, + 0x2ab294bd, 0x7e1591b0, 0xb200a5e9, 0x00a9b3a4, 0x2abf00d6, 0x804c6bb2, 0x7e4db200, 0xb200b778, 0x00adb3a0, 0x2ab200a7, 0x4cb21bb2, 0x90014dfe, 0xbd7e50dd, 0xa0b200a4, 0x9000adb3, 0x902ab200, 0x010c014b, 0x90014dfe, 0x3f7e54dd, 0xa0b200a6, 0x7800a4b3, 0x9815b0b4, 0x4afe0c2c, 0x30aa9001, 0x00a6277e, 0xa60c90b4, 0x1e1bf491, 0xfe14b0b4, 0xaa90014a, 0xa95c7e30, 0x1590b400, 0xb3059f98, @@ -1407,8 +1407,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xf99800ab, 0x14e0b402, 0x1bf491a6, 0x02feb506, 0x91a6f9bf, 0xa0091bf4, 0xab883efe, 0x01f99800, 0x1bf491a6, 0x01feb506, 0x2ab24bb2, 0x00a60b7e, 0x130004b3, 0x90015590, 0x29988066, 0xf559a605, 0x33fefa08, 0x98460070, 0x8db2042f, 0x2ab2e4bd, 0x0b00f1b0, 0x0070dc02, 0x41fe0000, 0x5c119001, - 0x7e0111b0, 0x9800a5e3, 0x2abf042c, 0xfb048bb2, 0x00b7477e, 0x2c981ebf, 0xbda0b204, 0xb22ab2b4, - 0xa5e57e0d, 0x0004b300, 0xbdff0406, 0xac003e04, 0x0c2a9800, 0xb2b003bc, 0x0100904c, 0x00b6727e, + 0x7e0111b0, 0x9800a5e3, 0x2abf042c, 0xfb048bb2, 0x00b74a7e, 0x2c981ebf, 0xbda0b204, 0xb22ab2b4, + 0xa5e57e0d, 0x0004b300, 0xbdff0406, 0xac003e04, 0x0c2a9800, 0xb2b003bc, 0x0100904c, 0x00b6757e, 0xa60b90b4, 0xec08f409, 0xbc032f98, 0x29b59039, 0xf49fa609, 0x94bd0808, 0xbd0929b5, 0x0149fea4, 0xbf609990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0830f400, 0xf43885fb, 0xdcd9cc30, 0xf9000005, 0xf499bf82, 0x4ffef830, 0x5cff9001, 0xe1b0f9a0, 0xb2c8b20b, 0xb3a3b2d6, 0x028400b9, @@ -1416,18 +1416,18 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xb3a0b200, 0x025e00ad, 0x68bc17bf, 0x017998f0, 0x08f59fa6, 0x7998024d, 0x0194b304, 0x3e05000a, 0xb300aee1, 0x023e0069, 0x09027f98, 0xf5f9a6f0, 0xb2022a0b, 0xa5e97e3a, 0xb3a2b200, 0x021e00a9, 0xb20c3c98, 0x0140fe7b, 0xb2340090, 0xa6277e0a, 0xb50ab200, 0x8bcc0570, 0xa6c07e70, 0xb3a0b200, - 0x01e900ad, 0x010d00b4, 0xf501a6f0, 0xf501ce0b, 0x3d01d00c, 0x00804cb4, 0x8c7e2ab2, 0x3abf00b7, - 0x4c070b94, 0x2db20080, 0x00b7757e, 0xb30ca1b0, 0x01b600ad, 0x18052918, 0x9476042f, 0xfff4f008, + 0x01e900ad, 0x010d00b4, 0xf501a6f0, 0xf501ce0b, 0x3d01d00c, 0x00804cb4, 0x8f7e2ab2, 0x3abf00b7, + 0x4c070b94, 0x2db20080, 0x00b7787e, 0xb30ca1b0, 0x01b600ad, 0x18052918, 0x9476042f, 0xfff4f008, 0x09e59fff, 0xf5e966ff, 0xe401980b, 0xa6ffffe9, 0x8e08f589, 0xbcf4bd01, 0x9918902f, 0x009d3309, 0xff900182, 0x07f4b301, 0xaefb3ef2, 0xf28e3c00, 0x08f59f26, 0xfdc4016d, 0xff94f0ff, 0xa6529dbc, - 0x050df456, 0xd99065b2, 0xbca43d10, 0xc43db029, 0xa63ee4bd, 0xd6b100ad, 0x0cf5006f, 0x10b40145, + 0x050df456, 0xd99065b2, 0xbce4bd10, 0xa43db029, 0xa63ec43d, 0xd6b100ad, 0x0cf5006f, 0x10b40145, 0x98be3c0b, 0x26f81e3c, 0x170bf4f9, 0x39ff94f0, 0x9ffd0099, 0x00903304, 0x3c010a06, 0x010ce9bf, 0x9001ee90, 0xe5a601dd, 0x33ce08f4, 0x00ed00c9, 0x94f0293f, 0x080bf408, 0xd000a933, 0xb294bd00, 0x1491b03a, 0xb01391b0, 0x91301291, 0x014bfe5b, 0x7e5bbb90, 0xb200a6f8, 0x00adb3a0, 0x903400ef, 0x0090335b, 0x7e3ab211, 0xb200a9d8, 0x00adb3a0, 0x00b400db, 0x1140b40d, 0x90014ffe, 0x2eb250ff, 0xb0070d94, 0x804101f1, 0x0b3ab200, 0xb04cb201, 0xe37e0011, 0x0bb200a5, 0x3ab22cb2, 0x90014dfe, 0xbd7e4cdd, 0xe0b400a4, 0xb2a0b214, 0xbd3ab21c, 0x7e0db2b4, 0xb300a5e5, 0x0091000d, 0xfe13b0b4, - 0xaa90014a, 0xa95c7e34, 0x0c3a9800, 0xfe0db0b4, 0xcc90014c, 0xb65b7e48, 0xb3a0b200, 0xb46d00a4, + 0xaa90014a, 0xa95c7e34, 0x0c3a9800, 0xfe0db0b4, 0xcc90014c, 0xb65e7e48, 0xb3a0b200, 0xb46d00a4, 0xf0011290, 0x1bf491a6, 0x014e9832, 0xb370efcd, 0x0f0600f4, 0x06291870, 0xbcff94f0, 0x9fbb909e, 0x0149b502, 0x00ae983e, 0x3ab20bb2, 0x3e7e2cb2, 0xa0b200a4, 0x3400a4b3, 0xfe0265bb, 0xaa90014a, 0xa6a97e34, 0x0060b300, 0x0b90b420, 0xbc8085bc, 0x91b09095, 0xace43e0b, 0x3e020000, 0x0000aec8, @@ -1440,88 +1440,88 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x00a6277e, 0x2bcc0ab2, 0xa6c07e70, 0xb3a8b200, 0x00ad00ad, 0xfe7021cd, 0x80420147, 0x44779000, 0x00b0373e, 0xbd0c00b4, 0x0979a094, 0xf409a6f0, 0x0200091b, 0x00b03e3e, 0x09a6f009, 0x00090df4, 0xb03e3e03, 0x0bc0b400, 0xbd0704b6, 0xb20db2e4, 0xb0b4bd5a, 0x71b00021, 0xa5e37e01, 0xb25abf00, - 0xb22cb20b, 0xb7757e3d, 0xb27ebf00, 0xb23bb2a0, 0xb22cb25a, 0xa5e57e0d, 0x0004b300, 0xbd3ab245, + 0xb22cb20b, 0xb7787e3d, 0xb27ebf00, 0xb23bb2a0, 0xb22cb25a, 0xa5e57e0d, 0x0004b300, 0xbd3ab245, 0xa4107eb4, 0xb3a0b200, 0x003700a4, 0x0201bb70, 0x0df404a6, 0x9040b205, 0x6ab2101b, 0xb2b03bbc, - 0xb7957e0c, 0x014afe00, 0x900240bb, 0x60bc30aa, 0xa6a97e60, 0xb314bd00, 0xff6d004d, 0x5ab280b2, + 0xb7987e0c, 0x014afe00, 0x900240bb, 0x60bc30aa, 0xa6a97e60, 0xb314bd00, 0xff6d004d, 0x5ab280b2, 0x0b7e3bb2, 0x4c3e00a6, 0x020000b0, 0x900149fe, 0x9fbf4c99, 0x0005dcd9, 0xb299bf00, 0xf4f9a60a, 0x317e070b, 0x30f4003a, 0x2485fb08, 0xd9f830f4, 0x000005dc, 0x99bf32f9, 0x90014ffe, 0xa1b214ff, - 0x94bdf9a0, 0xc3b2b2b2, 0x4b0140fe, 0x00900320, 0xb209a010, 0xb79b7e0a, 0xb309bf00, 0xb34c0090, + 0x94bdf9a0, 0xc3b2b2b2, 0x4b0140fe, 0x00900320, 0xb209a010, 0xb79e7e0a, 0xb309bf00, 0xb34c0090, 0xa04800a4, 0xb509bf91, 0x0fbf0192, 0xb5100049, 0x0fbf04f9, 0xf9b52009, 0xb509bf05, 0x0fbf0693, 0xf9350109, 0x3509bf1c, 0x0fbf2c9a, 0xf9b5f009, 0x900fbf0a, 0xf9b540f9, 0x900fbf0e, 0xf9b5c0f9, 0x3e0abf0f, 0xbd00b0e9, 0x0149fea4, 0xbf149990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, - 0x0835fb00, 0xdfd030f4, 0x000005dc, 0xffbf82f9, 0x900149fe, 0xa3b25099, 0x02059fa0, 0xf800a9b3, - 0x00b63004, 0x350b9cf0, 0x94bd2ca9, 0x7e0ca9b5, 0xb200a5e9, 0xbd3abfa0, 0x00804cb4, 0x757e0db2, - 0xa5b200b7, 0xae00adb3, 0x33093f04, 0x049f4a9d, 0x33010918, 0x0497469d, 0x33020918, 0x048f469d, - 0x33030918, 0x0487539d, 0x18040e18, 0x0f180509, 0x070d1806, 0xf0ffe4f0, 0xf4f0ff94, 0x0894b6ff, - 0xfd10f4b6, 0xd4b6059e, 0x05f9fd18, 0xf505dffd, 0x05045b0b, 0x03d6b005, 0x045a0cf5, 0xb3013db5, + 0x0835fb00, 0xdfd030f4, 0x000005dc, 0xffbf82f9, 0x900149fe, 0xa3b25099, 0x02059fa0, 0xfb00a9b3, + 0x00b63004, 0x350b9cf0, 0x94bd2ca9, 0x7e0ca9b5, 0xb200a5e9, 0xbd3abfa0, 0x00804cb4, 0x787e0db2, + 0xa5b200b7, 0xb100adb3, 0x33093f04, 0x04a24a9d, 0x33010918, 0x049a469d, 0x33020918, 0x0492469d, + 0x33030918, 0x048a539d, 0x18040e18, 0x0f180509, 0x070d1806, 0xf0ffe4f0, 0xf4f0ff94, 0x0894b6ff, + 0xfd10f4b6, 0xd4b6059e, 0x05f9fd18, 0xf505dffd, 0x05045e0b, 0x03d6b005, 0x045d0cf5, 0xb3013db5, 0x490e01d4, 0x39b55000, 0xb1d73e02, 0x080d1800, 0x18090918, 0x0e180a0f, 0xffd4f00b, 0xf0ff94f0, 0x94b6fff4, 0x10f4b608, 0xb6059dfd, 0xf9fd18e4, 0x05effd05, 0xb2023eb5, 0x7e0bb23a, 0x9800a60b, - 0xff09023a, 0xa9a60305, 0x04080bf5, 0x9007a5b6, 0x3ab5303b, 0xb6ce7e03, 0xb3a5b200, 0x03f500ad, - 0x09033b98, 0x343a90c0, 0xfd3fbb90, 0xb5b604b9, 0xb79b7e03, 0xb3a5b200, 0x03d900ad, 0xfe0147fe, - 0x77900148, 0x9044bd40, 0x88900179, 0x0991b03c, 0x00b3443e, 0x8ea0e4bd, 0x0f0044b3, 0xbd0c3a98, - 0x3efe0cb4, 0xb200b267, 0xb24bb23a, 0xa5787e7c, 0xb3a5b200, 0x039d00ad, 0x94f0793f, 0x120bf401, - 0xb20c3a98, 0x7eff0c4b, 0x3e00b672, 0xb200b341, 0xa32f7e7a, 0x00a0b300, 0x0c3a980f, 0xfd0c4bb2, - 0x00b2673e, 0x94f0793f, 0x0e1bf402, 0xb20c3a98, 0x3efd0c4b, 0xb400b336, 0x3ab209b0, 0x8db2010c, - 0x00a63f7e, 0x5d00a0b3, 0x3fb2793f, 0x99c724bd, 0x01999002, 0x980a91b0, 0x54b354f5, 0xb0b43900, - 0x0022bc09, 0x02bc030c, 0x0304b600, 0x014001b8, 0x1031bc00, 0x957e1ab2, 0x30bc00b7, 0x4309b800, - 0x95200001, 0xb45302b5, 0x0fb50af0, 0x3e81a054, 0x9000b301, 0xff900122, 0x1424b318, 0xb62e3ebe, - 0x3f8ebf00, 0x027f5879, 0x98077d18, 0x3a9803ee, 0x0299c70d, 0xcc00f3f0, 0x96cb70ff, 0xcb4bb21f, - 0x010cd8e6, 0xebf0d6cb, 0x7e01e0f6, 0x9800a2e5, 0x4bb20c3a, 0x727e6cb2, 0xa5b200b6, 0xb400adb3, - 0x01449002, 0xa6033b98, 0xeb08f54b, 0xbc94bdfe, 0x89a0b0bb, 0xb17e8ab2, 0xa5b200b7, 0x9400adb3, - 0xbd37b202, 0x547f9884, 0xbc9088bc, 0x94b69098, 0x4099b803, 0x39bc0001, 0x0b91b090, 0x5300f9b3, - 0x033c9802, 0x3d0fa0b4, 0xbc24bdb4, 0x44bdc0cc, 0x00b78c7e, 0x3e0f60b4, 0x9800b45f, 0x2bb20d3a, - 0x7e0c41b0, 0x3300a2f5, 0x00b500a9, 0xfe0c3a98, 0x2bb2014c, 0x7e38cc90, 0xb300b65b, 0x020c00ad, - 0xb40be0b4, 0xef980e90, 0xd899c703, 0x1bf59fa6, 0x3a98008e, 0x0c2bb20d, 0xa2ed7e01, 0x014cfe00, - 0x2bb23ab2, 0x7e30cc90, 0xb300a593, 0x981306a4, 0x2bb20c3a, 0x727efd0c, 0x5c3e00b6, 0xadb300b4, - 0x7401cb00, 0x93f01c90, 0x9099bc00, 0x7f0069bc, 0xff19e401, 0x091bf4ff, 0x5c3e0260, 0x3a9800b4, - 0x014cfe0c, 0xffff1be4, 0x7e34cc90, 0xb300b65b, 0x019800ad, 0x343af034, 0xf9263690, 0x60100df4, - 0xff1be402, 0x0c3a98ff, 0x00b4513e, 0xb20c3a98, 0x7efd0c2b, 0xb300b672, 0x017000ad, 0x98012290, - 0x2aa6033a, 0xff3708f5, 0x6eb264b2, 0xd43db43d, 0xc4bdf4bd, 0x00b4933e, 0x9473e97f, 0x010d0a00, - 0x00b48d3e, 0x0600d033, 0xcc90010b, 0x01ff9001, 0xa602ee90, 0xe308f4fa, 0x0b00c4b3, 0x3e547cb5, - 0x3300b5cf, 0x00a600b9, 0xb0013998, 0x0cf40296, 0xb2030930, 0x5479b56d, 0xf4bde4bd, 0x00b4d23e, - 0x9073d97f, 0x697c0a00, 0x01ee90e9, 0x9001ff90, 0x399802dd, 0xf4f9a603, 0x493ee908, 0x94bd00b5, - 0x79b5f101, 0xb224bd54, 0xb5233e1b, 0xe4407f00, 0xf4ffff09, 0xf10f260b, 0x1bf4bfa6, 0xff0be40b, - 0xb51b3eff, 0x0c3a9800, 0xffff0ce4, 0x00b6727e, 0xb900adb3, 0xff0be400, 0x9019b2ff, 0x44900122, - 0x9891b202, 0x29a60339, 0x09c508f4, 0xf5b9a6f1, 0x9800a00b, 0x3c980c3a, 0xb6727e0a, 0x00adb300, - 0x31b5008c, 0xb5cf3e0a, 0xbd6f7f00, 0x01c19294, 0xf05179b5, 0x04bd00f3, 0x3e527fb5, 0x7f00b587, - 0x014c584b, 0x900c3a98, 0xb3f00100, 0x00c3f000, 0x7e024490, 0xb300b672, 0xb45200a4, 0xe9980be0, - 0x70999001, 0xa601e9b5, 0xd608f401, 0x9808607c, 0xf00c0c3a, 0xffff0be4, 0x00b6727e, 0x2d00a4b3, - 0xe4014cfe, 0xb2ffff0b, 0x40cc903a, 0x00a5787e, 0x1900a4b3, 0x98469034, 0x94f0517f, 0xf0f9bcff, - 0x3e517fb5, 0x0a00b5cf, 0x3ea5b203, 0x9000b5da, 0x77900188, 0x148db318, 0x49fefd90, 0x3c999001, - 0x457e9abf, 0xf03e00b7, 0x030500b5, 0x00b5f23e, 0x0bb204bd, 0x0b7e3ab2, 0x50b300a6, 0x3a981a00, - 0x7e04bd0c, 0x9800b6c4, 0x30b50d3a, 0xb7457e0c, 0x0d30b500, 0x900149fe, 0x9fbf5099, 0x0005dcd9, - 0xb299bf00, 0xf4f9a65a, 0x343e110b, 0x010500b6, 0x00b5f03e, 0x003a317e, 0xf93085fb, 0x7ea0b202, - 0x9800a5e7, 0xc47e0c0a, 0x0a9800b6, 0xb7457e0d, 0x7e0ab200, 0xbd00b745, 0xbf01fba4, 0x0aafb2a9, - 0xf4b9a602, 0xb9900d18, 0x98f9bc01, 0xc9a0a4bd, 0xa9bf00f8, 0x020aafb2, 0x18f4b9a6, 0x01b9900b, - 0xfcbca4bd, 0xbf00f899, 0xb2afb2b9, 0xf4c9a6ca, 0xf10a0708, 0xfbb500f8, 0xb5fca002, 0x00f801fc, - 0xaf98a9bf, 0x90b9bc02, 0xfbbfa9a0, 0x08f49ba6, 0x029bbb08, 0xa998a9a0, 0xa6aabf01, 0x051bf4a9, - 0x00f8f10a, 0x0800a0b3, 0x00b7457e, 0x30f400f8, 0x05dcdff8, 0x32f90000, 0x49feffbf, 0x14999001, - 0x9fa0a0b2, 0xa0b3b3b2, 0xfd024200, 0x0cf4a2a6, 0x01ab903a, 0xb60141fe, 0x119002b4, 0x7e1ab210, - 0xb300b7b1, 0xbf2700a4, 0xb21db219, 0xa0e4bd2c, 0x90dfbf90, 0x9eb201e9, 0xa699fcbc, 0xf408f490, - 0x3da0ddbf, 0x00b72a3e, 0x49fe020a, 0x14999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, - 0x35fb003a, 0xda00f808, 0x00002944, 0x0041c77e, 0xf000a630, 0xa6f00bac, 0x01aab901, 0x44da00f8, - 0x7e000029, 0x30004142, 0xacf000a6, 0x01a6f00b, 0xf801aab9, 0x2944da00, 0xd77e0000, 0xa6300042, - 0x0bacf000, 0xb901a6f0, 0x00f801aa, 0x7effb4f0, 0xf8000b94, 0x0b7e7e00, 0xf900f800, 0x3da0b202, - 0x384c7ea4, 0x00a6b000, 0xa00b9cf0, 0xfb9ab20a, 0xb202f901, 0x7ea43da0, 0xb000382a, 0x9cf000a6, - 0xb20aa00b, 0xf401fb9a, 0xdcdfe430, 0xf9000005, 0xfeffbf82, 0x45fe0149, 0x3c999001, 0xa00147fe, - 0x2455909f, 0xd9347790, 0x0000141c, 0x4bfe9abf, 0x90080c01, 0xff0d2cbb, 0x0000c17e, 0xeb00a433, - 0x3f0c30b4, 0x0c943339, 0x043118e2, 0x0f001033, 0xb0011933, 0x3e043d00, 0x9800b96d, 0x2cd9023f, - 0x98000014, 0x34580431, 0x3f5fa00a, 0x0339989f, 0xb5183690, 0xff090159, 0xf43379a0, 0xf77e1800, - 0xa0320032, 0x2900ad33, 0xdf010901, 0x0000142c, 0x1272f920, 0xbd0043f0, 0xb8ad3e14, 0x0241bc00, - 0x010006b1, 0x40060df4, 0x947e0100, 0x24d9000b, 0xbf000014, 0xff2ce49a, 0xb26bb2ff, 0x1300de0d, - 0x117e0000, 0x7aa000af, 0xd400adb3, 0x985bbf00, 0x1d90015c, 0x7c0eb204, 0x10bc2020, 0x1300da10, - 0x367e0000, 0xa0320021, 0xc500ad33, 0x4cb4bd00, 0x00da0100, 0xa6000013, 0xa408f414, 0x00b95c3e, - 0xd9023f98, 0x0000142c, 0x58043498, 0x5fa00a32, 0x39989f3f, 0x18389003, 0x090159b5, 0x3379a0ff, - 0x7e1600f4, 0x320032f7, 0x00ad33a0, 0x2cdf0084, 0x20000014, 0xff26e4f1, 0x3e24bdff, 0xbc00b94d, - 0x16b11262, 0x0df40100, 0x01004106, 0x000b947e, 0x5c985bbf, 0x042d9001, 0x00da1eb2, 0x7e000013, - 0xe40020d0, 0xbcffff4c, 0xa0322021, 0x1db28bb2, 0x001300de, 0x40417c00, 0x3500a433, 0x001424d9, - 0x7e9abf00, 0xa000ac3b, 0x00a4b37a, 0x4cb4bd13, 0x00da0100, 0xa6000013, 0xa608f426, 0x5c985bbf, - 0xbd7ab201, 0x7e040ed4, 0x32002136, 0x2db034a0, 0x817e3ab2, 0x0d33000f, 0x30fe7100, 0x020f3a01, - 0x1838f130, 0x04090333, 0x30014afe, 0x31303991, 0x90b4bd3b, 0x717e38aa, 0xe73e000f, 0x02f900b7, - 0x002930d9, 0xbfa0b200, 0x7e640b9a, 0x090000de, 0x00a43310, 0xa6008961, 0x009fcf02, 0x1000f5f1, - 0x8a009ff6, 0x4b02a600, 0xc4bd1000, 0xbd27104d, 0x198b7ee4, 0x00a43300, 0x2930d915, 0x9abf0000, - 0x00009b7e, 0x123e0409, 0x0ab200ba, 0x7e03e84b, 0x890016fc, 0xb802a400, 0x000200aa, 0x920aa5b6, - 0x9af601aa, 0x01114f00, 0x020099b8, 0x009ff600, 0x9a32943d, 0x000001fb, 0x00000000, 0x00000000, + 0xff09023a, 0x1bf4a9a6, 0x3e04bd09, 0xb600b5ed, 0x3b9007a5, 0x033ab530, 0x00b6d17e, 0xadb3a5b2, + 0x9803f500, 0xc009033b, 0x90343a90, 0xb9fd3fbb, 0x03b5b604, 0x00b79e7e, 0xadb3a5b2, 0xfe03d900, + 0x48fe0147, 0x40779001, 0x799044bd, 0x3c889001, 0x3e0991b0, 0xbd00b347, 0xb38ea0e4, 0x980f0044, + 0xb4bd0c3a, 0x6a3efe0c, 0x3ab200b2, 0x7cb24bb2, 0x00a5787e, 0xadb3a5b2, 0x3f039d00, 0x0194f079, + 0x98120bf4, 0x4bb20c3a, 0x757eff0c, 0x443e00b6, 0x7ab200b3, 0x00a32f7e, 0x0f00a0b3, 0xb20c3a98, + 0x3efd0c4b, 0x3f00b26a, 0x0294f079, 0x980e1bf4, 0x4bb20c3a, 0x393efd0c, 0xb0b400b3, 0x0c3ab209, + 0x7e8db201, 0xb300a63f, 0x3f5d00a0, 0xbd3fb279, 0x0299c724, 0xb0019990, 0xf5980a91, 0x0054b354, + 0x09b0b439, 0x0c0022bc, 0x0002bc03, 0xb80304b6, 0x00014001, 0xb21031bc, 0xb7987e1a, 0x0030bc00, + 0x014309b8, 0xb5952000, 0xf0b45302, 0x540fb50a, 0x043e81a0, 0x229000b3, 0x18ff9001, 0xbe1424b3, + 0x00b6313e, 0x793f8ebf, 0x18027f58, 0xee98077d, 0x0d3a9803, 0xf00299c7, 0xffcc00f3, 0x1f96cb70, + 0xe6cb4bb2, 0xcb010cd8, 0xf6ebf0d6, 0xe57e01e0, 0x3a9800a2, 0xb24bb20c, 0xb6757e6c, 0xb3a5b200, + 0x02b400ad, 0x98014490, 0x4ba6033b, 0xfeeb08f5, 0xbbbc94bd, 0xb289a0b0, 0xb7b47e8a, 0xb3a5b200, + 0x029400ad, 0x84bd37b2, 0xbc547f98, 0x98bc9088, 0x0394b690, 0x014099b8, 0x9039bc00, 0xb30b91b0, + 0x025300f9, 0xb4033c98, 0xb43d0fa0, 0xccbc24bd, 0x7e44bdc0, 0xb400b78f, 0x623e0f60, 0x3a9800b4, + 0xb02bb20d, 0xf57e0c41, 0xa93300a2, 0x9800b500, 0x4cfe0c3a, 0x902bb201, 0x5e7e38cc, 0xadb300b6, + 0xb4020c00, 0x90b40be0, 0x03ef980e, 0xa6d899c7, 0x8e1bf59f, 0x0d3a9800, 0x010c2bb2, 0x00a2ed7e, + 0xb2014cfe, 0x902bb23a, 0x937e30cc, 0xa4b300a5, 0x3a981306, 0x0c2bb20c, 0xb6757efd, 0xb45f3e00, + 0x00adb300, 0x907401cb, 0x0093f01c, 0xbc9099bc, 0x017f0069, 0xffff19e4, 0x60091bf4, 0xb45f3e02, + 0x0c3a9800, 0xe4014cfe, 0x90ffff1b, 0x5e7e34cc, 0xadb300b6, 0x34019800, 0x90343af0, 0xf4f92636, + 0x0260100d, 0xffff1be4, 0x3e0c3a98, 0x9800b454, 0x2bb20c3a, 0x757efd0c, 0xadb300b6, 0x90017000, + 0x3a980122, 0xf52aa603, 0xb2ff3708, 0x3d6eb264, 0xbdd43db4, 0x3ec4bdf4, 0x7f00b496, 0x009473e9, + 0x3e010d0a, 0x3300b490, 0x0b0600d0, 0x01cc9001, 0x9001ff90, 0xfaa602ee, 0xb3e308f4, 0xb50b00c4, + 0xd23e547c, 0xb93300b5, 0x9800a600, 0x96b00139, 0x300cf402, 0x6db20309, 0xbd5479b5, 0x3ef4bde4, + 0x7f00b4d5, 0x009073d9, 0xe9697c0a, 0x9001ee90, 0xdd9001ff, 0x03399802, 0x08f4f9a6, 0xb54c3ee9, + 0x0194bd00, 0x5479b5f1, 0x1bb224bd, 0x00b5263e, 0x09e4407f, 0x0bf4ffff, 0xa6f10f26, 0x0b1bf4bf, + 0xffff0be4, 0x00b51e3e, 0xe40c3a98, 0x7effff0c, 0xb300b675, 0x00b900ad, 0xffff0be4, 0x229019b2, + 0x02449001, 0x399891b2, 0xf429a603, 0xf109c508, 0x0bf5b9a6, 0x3a9800a0, 0x0a3c980c, 0x00b6757e, + 0x8c00adb3, 0x0a31b500, 0x00b5d23e, 0x94bd6f7f, 0xb501c192, 0xf3f05179, 0xb504bd00, 0x8a3e527f, + 0x4b7f00b5, 0x98014c58, 0x00900c3a, 0x00b3f001, 0x9000c3f0, 0x757e0244, 0xa4b300b6, 0xe0b45200, + 0x01e9980b, 0xb5709990, 0x01a601e9, 0x7cd608f4, 0x3a980860, 0xe4f00c0c, 0x7effff0b, 0xb300b675, + 0xfe2d00a4, 0x0be4014c, 0x3ab2ffff, 0x7e40cc90, 0xb300a578, 0x341900a4, 0x7f984690, 0xff94f051, + 0xb5f0f9bc, 0xd23e517f, 0x030a00b5, 0xdd3ea5b2, 0x889000b5, 0x18779001, 0x90148db3, 0x0149fefd, + 0xbf3c9990, 0xb7487e9a, 0xb5f33e00, 0x3e030500, 0xbd00b5f5, 0xb20bb204, 0xa60b7e3a, 0x0050b300, + 0x0c3a981a, 0xc77e04bd, 0x3a9800b6, 0x0c30b50d, 0x00b7487e, 0xfe0d30b5, 0x99900149, 0xd99fbf50, + 0x000005dc, 0x5ab299bf, 0x0bf4f9a6, 0xb6373e11, 0x3e010500, 0x7e00b5f3, 0xfb003a31, 0x02f93085, + 0xe77ea0b2, 0x0a9800a5, 0xb6c77e0c, 0x0d0a9800, 0x00b7487e, 0x487e0ab2, 0xa4bd00b7, 0xa9bf01fb, + 0x020aafb2, 0x18f4b9a6, 0x01b9900d, 0xbd98f9bc, 0xf8c9a0a4, 0xb2a9bf00, 0xa6020aaf, 0x0b18f4b9, + 0xbd01b990, 0x99fcbca4, 0xb9bf00f8, 0xcab2afb2, 0x08f4c9a6, 0xf8f10a07, 0x02fbb500, 0xfcb5fca0, + 0xbf00f801, 0x02af98a9, 0xa090b9bc, 0xa6fbbfa9, 0x0808f49b, 0xa0029bbb, 0x01a998a9, 0xa9a6aabf, + 0x0a051bf4, 0xb300f8f1, 0x7e0800a0, 0xf800b748, 0xf830f400, 0x0005dcdf, 0xbf32f900, 0x0149feff, + 0xb2149990, 0xb29fa0a0, 0x00a0b3b3, 0xa6fd0242, 0x3a0cf4a2, 0xfe01ab90, 0xb4b60141, 0x10119002, + 0xb47e1ab2, 0xa4b300b7, 0x19bf2700, 0x2cb21db2, 0x90a0e4bd, 0xe990dfbf, 0xbc9eb201, 0x90a699fc, + 0xbff408f4, 0x3e3da0dd, 0x0a00b72d, 0x0149fe02, 0xbf149990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, + 0x3a317e07, 0x0835fb00, 0x44da00f8, 0x7e000029, 0x300041c7, 0xacf000a6, 0x01a6f00b, 0xf801aab9, + 0x2944da00, 0x427e0000, 0xa6300041, 0x0bacf000, 0xb901a6f0, 0x00f801aa, 0x002944da, 0x42d77e00, + 0x00a63000, 0xf00bacf0, 0xaab901a6, 0xf000f801, 0x947effb4, 0x00f8000b, 0x000b7e7e, 0x02f900f8, + 0xa43da0b2, 0x00384c7e, 0xf000a6b0, 0x0aa00b9c, 0x01fb9ab2, 0xa0b202f9, 0x2a7ea43d, 0xa6b00038, + 0x0b9cf000, 0x9ab20aa0, 0x30f401fb, 0x05dcdfe4, 0x82f90000, 0x49feffbf, 0x0145fe01, 0xfe3c9990, + 0x9fa00147, 0x90245590, 0x1cd93477, 0xbf000014, 0x014bfe9a, 0xbb90080c, 0x7eff0d2c, 0x330000c1, + 0xb4eb00a4, 0x393f0c30, 0xe20c9433, 0x33043118, 0x330f0010, 0x00b00119, 0x703e043d, 0x3f9800b9, + 0x142cd902, 0x31980000, 0x0a345804, 0x9f3f5fa0, 0x90033998, 0x59b51836, 0xa0ff0901, 0x00f43379, + 0x32f77e18, 0x33a03200, 0x012900ad, 0x2cdf0109, 0x20000014, 0xf01272f9, 0x14bd0043, 0x00b8b03e, + 0xb10241bc, 0xf4010006, 0x0040060d, 0x0b947e01, 0x1424d900, 0x9abf0000, 0xffff2ce4, 0x0db26bb2, + 0x001300de, 0xaf117e00, 0xb37aa000, 0x00d400ad, 0x5c985bbf, 0x041d9001, 0x207c0eb2, 0x1010bc20, + 0x001300da, 0x21367e00, 0x33a03200, 0x00c500ad, 0x004cb4bd, 0x1300da01, 0x14a60000, 0x3ea408f4, + 0x9800b95f, 0x2cd9023f, 0x98000014, 0x32580434, 0x3f5fa00a, 0x0339989f, 0xb5183890, 0xff090159, + 0xf43379a0, 0xf77e1600, 0xa0320032, 0x8400ad33, 0x142cdf00, 0xf1200000, 0xffff26e4, 0x503e24bd, + 0x62bc00b9, 0x0016b112, 0x060df401, 0x7e010041, 0xbf000b94, 0x015c985b, 0xb2042d90, 0x1300da1e, + 0xd07e0000, 0x4ce40020, 0x21bcffff, 0xb2a03220, 0xde1db28b, 0x00001300, 0x3340417c, 0xd93500a4, + 0x00001424, 0x3b7e9abf, 0x7aa000ac, 0x1300a4b3, 0x004cb4bd, 0x1300da01, 0x26a60000, 0xbfa608f4, + 0x015c985b, 0xd4bd7ab2, 0x367e040e, 0xa0320021, 0xb22db034, 0x0f817e3a, 0x000d3300, 0x0130fe71, + 0x30020f3a, 0x331838f1, 0xfe040903, 0x9130014a, 0x3b313039, 0xaa90b4bd, 0x0f717e38, 0xb7ea3e00, + 0xd902f900, 0x00002930, 0x9abfa0b2, 0xde7e640b, 0x10090000, 0x6100a433, 0x02a60089, 0xf1009fcf, + 0xf61000f5, 0x008a009f, 0x004b02a6, 0x4dc4bd10, 0xe4bd2710, 0x00198b7e, 0x1500a433, 0x002930d9, + 0x7e9abf00, 0x0900009b, 0xba153e04, 0x4b0ab200, 0xfc7e03e8, 0x00890016, 0xaab802a4, 0xb6000200, + 0xaa920aa5, 0x009af601, 0xb801114f, 0x00020099, 0x3d009ff6, 0xfb9a3294, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0xb22438cf, 0xcfd90bc8, 0xf23ebc55, 0x2e5c0e40, - 0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0x0d4a5d7d, 0x9c31ffb3, 0x95bc604f, 0x40cc834d, + 0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0x1289f13d, 0xdc6acca2, 0x50be285c, 0xd086f67e, + 0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0xc901a2e3, 0xd0a96e16, 0x4a0da134, 0xc2405c59, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, diff --git a/src/common/nvswitch/kernel/inforom/ifrnvlink_nvswitch.c b/src/common/nvswitch/kernel/inforom/ifrnvlink_nvswitch.c index caea578a2..eea3c144d 100644 --- a/src/common/nvswitch/kernel/inforom/ifrnvlink_nvswitch.c +++ b/src/common/nvswitch/kernel/inforom/ifrnvlink_nvswitch.c @@ -32,7 +32,188 @@ nvswitch_inforom_nvlink_flush struct nvswitch_device *device ) { - return -NVL_ERR_NOT_SUPPORTED; + NvlStatus status = NVL_SUCCESS; + struct inforom *pInforom = device->pInforom; + PINFOROM_NVLINK_STATE pNvlinkState; + + if (pInforom == NULL) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + pNvlinkState = pInforom->pNvlinkState; + + if (pNvlinkState != NULL && pNvlinkState->bDirty) + { + status = nvswitch_inforom_write_object(device, "NVL", + pNvlinkState->pFmt, pNvlinkState->pNvl, + pNvlinkState->pPackedObject); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "Failed to flush NVL object to InfoROM, rc: %d\n", status); + } + else + { + pNvlinkState->bDirty = NV_FALSE; + } + } + + return status; +} + +static void +_inforom_nvlink_get_correctable_error_counts +( + nvswitch_device *device, + NvU32 linkId, + INFOROM_NVLINK_CORRECTABLE_ERROR_COUNTS *pErrorCounts +) +{ + NvlStatus status; + NvU32 lane, idx; + NVSWITCH_NVLINK_GET_COUNTERS_PARAMS p = { 0 }; + + ct_assert(NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE__SIZE <= + INFOROM_NVL_OBJECT_MAX_SUBLINK_WIDTH); + + nvswitch_os_memset(pErrorCounts, 0, sizeof(*pErrorCounts)); + + p.linkId = linkId; + p.counterMask = NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_FLIT + | NVSWITCH_NVLINK_COUNTER_DL_TX_ERR_REPLAY + | NVSWITCH_NVLINK_COUNTER_DL_TX_ERR_RECOVERY + | NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_REPLAY + | NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L0 + | NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L1 + | NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L2 + | NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L3 + | NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L4 + | NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L5 + | NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L6 + | NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L7 + | NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L7; + + status = device->hal.nvswitch_ctrl_get_counters(device, &p); + if (status != NVL_SUCCESS) + { + return; + } + + pErrorCounts->flitCrc = + p.nvlinkCounters[BIT_IDX_32(NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_FLIT)]; + + pErrorCounts->txLinkReplay = + p.nvlinkCounters[BIT_IDX_32(NVSWITCH_NVLINK_COUNTER_DL_TX_ERR_REPLAY)]; + + pErrorCounts->rxLinkReplay = + p.nvlinkCounters[BIT_IDX_32(NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_REPLAY)]; + + pErrorCounts->linkRecovery = + p.nvlinkCounters[BIT_IDX_32(NVSWITCH_NVLINK_COUNTER_DL_TX_ERR_RECOVERY)]; + + for (lane = 0; lane < NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE__SIZE; lane++) + { + idx = BIT_IDX_32(NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L(lane)); + pErrorCounts->laneCrc[lane] = p.nvlinkCounters[idx]; + } +} + +static void +_inforom_nvlink_update_correctable_error_rates +( + nvswitch_device *device, + struct inforom *pInforom + +) +{ + PINFOROM_NVLINK_STATE pNvlinkState = pInforom->pNvlinkState; + NvU64 enabledLinkMask; + NvU32 linkId, publicId, localLinkIdx; + NvBool bDirty = NV_FALSE; + NvBool bDirtyTemp; + INFOROM_NVLINK_CORRECTABLE_ERROR_COUNTS errorCounts = { 0 }; + + if (pNvlinkState == NULL) + { + return; + } + + enabledLinkMask = nvswitch_get_enabled_link_mask(device); + + FOR_EACH_INDEX_IN_MASK(64, linkId, enabledLinkMask) + { + if (device->hal.nvswitch_get_link_public_id(device, linkId, &publicId) != NVL_SUCCESS) + { + continue; + } + + if (device->hal.nvswitch_get_link_local_idx(device, linkId, &localLinkIdx) != NVL_SUCCESS) + { + continue; + } + + _inforom_nvlink_get_correctable_error_counts(device, linkId, &errorCounts); + + if (device->hal.nvswitch_inforom_nvl_update_link_correctable_error_info(device, + pNvlinkState->pNvl, &pNvlinkState->correctableErrorRateState, linkId, + publicId, localLinkIdx, &errorCounts, &bDirtyTemp) != NVL_SUCCESS) + { + continue; + } + + bDirty |= bDirtyTemp; + } + FOR_EACH_INDEX_IN_MASK_END; + + pNvlinkState->bDirty |= bDirty; +} + +static void _nvswitch_nvlink_1hz_callback +( + nvswitch_device *device +) +{ + struct inforom *pInforom = device->pInforom; + + if ((pInforom == NULL) || (pInforom->pNvlinkState == NULL) || + pInforom->pNvlinkState->bCallbackPending) + { + return; + } + + pInforom->pNvlinkState->bCallbackPending = NV_TRUE; + _inforom_nvlink_update_correctable_error_rates(device, pInforom); + pInforom->pNvlinkState->bCallbackPending = NV_FALSE; +} + +static void +_inforom_nvlink_start_correctable_error_recording +( + nvswitch_device *device, + struct inforom *pInforom +) +{ + PINFOROM_NVLINK_STATE pNvlinkState = pInforom->pNvlinkState; + + if (pNvlinkState == NULL) + { + return; + } + + if (pNvlinkState->bDisableCorrectableErrorLogging) + { + + NVSWITCH_PRINT(device, INFO, + "%s: Correctable error recording disabled by regkey or unsupported\n", + __FUNCTION__); + return; + } + + pNvlinkState->bCallbackPending = NV_FALSE; + + nvswitch_task_create(device, &_nvswitch_nvlink_1hz_callback, + NVSWITCH_INTERVAL_1SEC_IN_NS, 0); } NvlStatus @@ -41,7 +222,82 @@ nvswitch_inforom_nvlink_load nvswitch_device *device ) { - return -NVL_ERR_NOT_SUPPORTED; + NvlStatus status; + NvU8 version = 0; + NvU8 subversion = 0; + INFOROM_NVLINK_STATE *pNvlinkState = NULL; + struct inforom *pInforom = device->pInforom; + + if (pInforom == NULL) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + status = nvswitch_inforom_get_object_version_info(device, "NVL", &version, + &subversion); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, WARN, "no NVL object found, rc:%d\n", status); + return NVL_SUCCESS; + } + + if (!INFOROM_OBJECT_SUBVERSION_SUPPORTS_NVSWITCH(subversion)) + { + NVSWITCH_PRINT(device, WARN, "NVL v%u.%u not supported\n", + version, subversion); + return -NVL_ERR_NOT_SUPPORTED; + } + + NVSWITCH_PRINT(device, INFO, "NVL v%u.%u found\n", version, subversion); + + pNvlinkState = nvswitch_os_malloc(sizeof(INFOROM_NVLINK_STATE)); + if (pNvlinkState == NULL) + { + return -NVL_NO_MEM; + } + nvswitch_os_memset(pNvlinkState, 0, sizeof(INFOROM_NVLINK_STATE)); + + pNvlinkState->bDirty = NV_FALSE; + pNvlinkState->bDisableFatalErrorLogging = NV_FALSE; + pNvlinkState->bDisableCorrectableErrorLogging = NV_TRUE; + + status = device->hal.nvswitch_inforom_nvl_setup_nvlink_state(device, pNvlinkState, version); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "Failed to set up NVL object, rc:%d\n", status); + goto nvswitch_inforom_nvlink_version_fail; + } + + status = nvswitch_inforom_read_object(device, "NVL", pNvlinkState->pFmt, + pNvlinkState->pPackedObject, + pNvlinkState->pNvl); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "Failed to read NVL object, rc:%d\n", status); + goto nvswitch_inforom_read_fail; + } + + status = nvswitch_inforom_add_object(pInforom, &pNvlinkState->pNvl->header); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "Failed to cache NVL object header, rc:%d\n", + status); + goto nvswitch_inforom_read_fail; + } + + pInforom->pNvlinkState = pNvlinkState; + + _inforom_nvlink_start_correctable_error_recording(device, pInforom); + + return NVL_SUCCESS; + +nvswitch_inforom_read_fail: + nvswitch_os_free(pNvlinkState->pPackedObject); + nvswitch_os_free(pNvlinkState->pNvl); +nvswitch_inforom_nvlink_version_fail: + nvswitch_os_free(pNvlinkState); + + return status; } void @@ -50,30 +306,29 @@ nvswitch_inforom_nvlink_unload nvswitch_device *device ) { - return; -} + INFOROM_NVLINK_STATE *pNvlinkState; + struct inforom *pInforom = device->pInforom; -NvlStatus -nvswitch_inforom_nvlink_get_minion_data -( - nvswitch_device *device, - NvU8 linkId, - NvU32 *seedData -) -{ - return -NVL_ERR_NOT_SUPPORTED; -} + if (pInforom == NULL) + { + return; + } -NvlStatus -nvswitch_inforom_nvlink_set_minion_data -( - nvswitch_device *device, - NvU8 linkId, - NvU32 *seedData, - NvU32 size -) -{ - return -NVL_ERR_NOT_SUPPORTED; + pNvlinkState = pInforom->pNvlinkState; + if (pNvlinkState == NULL) + { + return; + } + + if (nvswitch_inforom_nvlink_flush(device) != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "Failed to flush NVL object on object unload\n"); + } + + nvswitch_os_free(pNvlinkState->pPackedObject); + nvswitch_os_free(pNvlinkState->pNvl); + nvswitch_os_free(pNvlinkState); + pInforom->pNvlinkState = NULL; } NvlStatus @@ -83,7 +338,35 @@ nvswitch_inforom_nvlink_log_error_event void *error_event ) { - return -NVL_ERR_NOT_SUPPORTED; + NvlStatus status; + NvBool bDirty = NV_FALSE; + struct inforom *pInforom = device->pInforom; + INFOROM_NVLINK_STATE *pNvlinkState; + + if (pInforom == NULL) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + pNvlinkState = pInforom->pNvlinkState; + if (pNvlinkState == NULL) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + status = device->hal.nvswitch_inforom_nvl_log_error_event(device, + pNvlinkState->pNvl, + (INFOROM_NVLINK_ERROR_EVENT *)error_event, + &bDirty); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "Failed to log error to inforom, rc:%d\n", + status); + } + + pNvlinkState->bDirty |= bDirty; + + return status; } NvlStatus @@ -93,7 +376,14 @@ nvswitch_inforom_nvlink_get_max_correctable_error_rate NVSWITCH_GET_NVLINK_MAX_CORRECTABLE_ERROR_RATES_PARAMS *params ) { - return -NVL_ERR_NOT_SUPPORTED; + struct inforom *pInforom = device->pInforom; + + if ((pInforom == NULL) || (pInforom->pNvlinkState == NULL)) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + return device->hal.nvswitch_inforom_nvl_get_max_correctable_error_rate(device, params); } NvlStatus @@ -103,5 +393,67 @@ nvswitch_inforom_nvlink_get_errors NVSWITCH_GET_NVLINK_ERROR_COUNTS_PARAMS *params ) { - return -NVL_ERR_NOT_SUPPORTED; + struct inforom *pInforom = device->pInforom; + + if ((pInforom == NULL) || (pInforom->pNvlinkState == NULL)) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + return device->hal.nvswitch_inforom_nvl_get_errors(device, params); } + +NvlStatus nvswitch_inforom_nvlink_setL1Threshold +( + nvswitch_device *device, + NvU32 word1, + NvU32 word2 +) +{ + struct inforom *pInforom = device->pInforom; + INFOROM_NVLINK_STATE *pNvlinkState; + + if (pInforom == NULL) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + pNvlinkState = pInforom->pNvlinkState; + if (pNvlinkState == NULL) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + return device->hal.nvswitch_inforom_nvl_setL1Threshold(device, + pNvlinkState->pNvl, + word1, + word2); +} + +NvlStatus nvswitch_inforom_nvlink_getL1Threshold +( + nvswitch_device *device, + NvU32 *word1, + NvU32 *word2 +) +{ + struct inforom *pInforom = device->pInforom; + INFOROM_NVLINK_STATE *pNvlinkState; + + if (pInforom == NULL) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + pNvlinkState = pInforom->pNvlinkState; + if (pNvlinkState == NULL) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + return device->hal.nvswitch_inforom_nvl_getL1Threshold(device, + pNvlinkState->pNvl, + word1, + word2); +} + diff --git a/src/common/nvswitch/kernel/inforom/inforom_nvl_v3_nvswitch.c b/src/common/nvswitch/kernel/inforom/inforom_nvl_v3_nvswitch.c new file mode 100644 index 000000000..5311d0870 --- /dev/null +++ b/src/common/nvswitch/kernel/inforom/inforom_nvl_v3_nvswitch.c @@ -0,0 +1,619 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "common_nvswitch.h" +#include "inforom/inforom_nvswitch.h" +#include "inforom/inforom_nvl_v3_nvswitch.h" +#include "lr10/lr10.h" + +NvlStatus inforom_nvl_v3_map_error +( + INFOROM_NVLINK_ERROR_TYPES error, + NvU8 *pHeader, + NvU16 *pMetadata, + NvU8 *pErrorSubtype, + INFOROM_NVL_ERROR_BLOCK_TYPE *pBlockType +) +{ + static const struct + { NvU8 header; + NvU16 metadata; + NvU8 errorSubtype; + INFOROM_NVL_ERROR_BLOCK_TYPE blockType; + } lut[] = + { + LUT_ELEMENT(DL, _RX, _FAULT_DL_PROTOCOL_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(DL, _RX, _FAULT_SUBLINK_CHANGE_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(DL, _RX, _FLIT_CRC_CORR, _ACCUM, _CORRECTABLE), + LUT_ELEMENT(DL, _RX, _LANE0_CRC_CORR, _ACCUM, _CORRECTABLE), + LUT_ELEMENT(DL, _RX, _LANE1_CRC_CORR, _ACCUM, _CORRECTABLE), + LUT_ELEMENT(DL, _RX, _LANE2_CRC_CORR, _ACCUM, _CORRECTABLE), + LUT_ELEMENT(DL, _RX, _LANE3_CRC_CORR, _ACCUM, _CORRECTABLE), + LUT_ELEMENT(DL, _RX, _LINK_REPLAY_EVENTS_CORR, _ACCUM, _CORRECTABLE), + LUT_ELEMENT(DL, _TX, _FAULT_RAM_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(DL, _TX, _FAULT_INTERFACE_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(DL, _TX, _FAULT_SUBLINK_CHANGE_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(DL, _TX, _LINK_REPLAY_EVENTS_CORR, _ACCUM, _CORRECTABLE), + LUT_ELEMENT(DL, _NA, _LTSSM_FAULT_UP_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(DL, _NA, _LTSSM_FAULT_DOWN_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(DL, _NA, _LINK_RECOVERY_EVENTS_CORR, _ACCUM, _CORRECTABLE), + LUT_ELEMENT(TLC, _RX, _DL_HDR_PARITY_ERR_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(TLC, _RX, _DL_DATA_PARITY_ERR_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(TLC, _RX, _DL_CTRL_PARITY_ERR_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(TLC, _RX, _INVALID_AE_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(TLC, _RX, _INVALID_BE_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(TLC, _RX, _INVALID_ADDR_ALIGN_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(TLC, _RX, _PKTLEN_ERR_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(TLC, _RX, _RSVD_PACKET_STATUS_ERR_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(TLC, _RX, _RSVD_CACHE_ATTR_PROBE_REQ_ERR_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(TLC, _RX, _RSVD_CACHE_ATTR_PROBE_RSP_ERR_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(TLC, _RX, _DATLEN_GT_RMW_REQ_MAX_ERR_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(TLC, _RX, _DATLEN_LT_ATR_RSP_MIN_ERR_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(TLC, _RX, _INVALID_CR_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(TLC, _RX, _INVALID_COLLAPSED_RESPONSE_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(TLC, _RX, _HDR_OVERFLOW_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(TLC, _RX, _DATA_OVERFLOW_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(TLC, _RX, _STOMP_DETECTED_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(TLC, _RX, _RSVD_CMD_ENC_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(TLC, _RX, _RSVD_DAT_LEN_ENC_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(TLC, _RX, _INVALID_PO_FOR_CACHE_ATTR_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(TLC, _RX, _RSP_STATUS_HW_ERR_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL), + LUT_ELEMENT(TLC, _RX, _RSP_STATUS_UR_ERR_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL), + LUT_ELEMENT(TLC, _RX, _RSP_STATUS_PRIV_ERR_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL), + LUT_ELEMENT(TLC, _RX, _POISON_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL), + LUT_ELEMENT(TLC, _RX, _AN1_HEARTBEAT_TIMEOUT_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL), + LUT_ELEMENT(TLC, _RX, _ILLEGAL_PRI_WRITE_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL), + LUT_ELEMENT(TLC, _TX, _DL_CREDIT_PARITY_ERR_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(TLC, _TX, _NCISOC_HDR_ECC_DBE_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(TLC, _TX, _NCISOC_PARITY_ERR_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(TLC, _TX, _ILLEGAL_PRI_WRITE_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL), + LUT_ELEMENT(TLC, _TX, _AN1_TIMEOUT_VC0_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL), + LUT_ELEMENT(TLC, _TX, _AN1_TIMEOUT_VC1_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL), + LUT_ELEMENT(TLC, _TX, _AN1_TIMEOUT_VC2_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL), + LUT_ELEMENT(TLC, _TX, _AN1_TIMEOUT_VC3_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL), + LUT_ELEMENT(TLC, _TX, _AN1_TIMEOUT_VC4_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL), + LUT_ELEMENT(TLC, _TX, _AN1_TIMEOUT_VC5_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL), + LUT_ELEMENT(TLC, _TX, _AN1_TIMEOUT_VC6_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL), + LUT_ELEMENT(TLC, _TX, _AN1_TIMEOUT_VC7_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL), + LUT_ELEMENT(TLC, _TX, _POISON_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL), + LUT_ELEMENT(TLC, _TX, _RSP_STATUS_HW_ERR_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL), + LUT_ELEMENT(TLC, _TX, _RSP_STATUS_UR_ERR_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL), + LUT_ELEMENT(TLC, _TX, _RSP_STATUS_PRIV_ERR_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL), + LUT_ELEMENT(NVLIPT, _NA, _SLEEP_WHILE_ACTIVE_LINK_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(NVLIPT, _NA, _RSTSEQ_PHYCTL_TIMEOUT_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(NVLIPT, _NA, _RSTSEQ_CLKCTL_TIMEOUT_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(NVLIPT, _NA, _CLKCTL_ILLEGAL_REQUEST_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(NVLIPT, _NA, _RSTSEQ_PLL_TIMEOUT_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(NVLIPT, _NA, _RSTSEQ_PHYARB_TIMEOUT_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(NVLIPT, _NA, _ILLEGAL_LINK_STATE_REQUEST_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL), + LUT_ELEMENT(NVLIPT, _NA, _FAILED_MINION_REQUEST_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL), + LUT_ELEMENT(NVLIPT, _NA, _RESERVED_REQUEST_VALUE_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL), + LUT_ELEMENT(NVLIPT, _NA, _LINK_STATE_WRITE_WHILE_BUSY_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL), + LUT_ELEMENT(NVLIPT, _NA, _WRITE_TO_LOCKED_SYSTEM_REG_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL), + LUT_ELEMENT(NVLIPT, _NA, _LINK_STATE_REQUEST_TIMEOUT_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL), + // TODO 3014908 log these in the NVL object until we have ECC object support + LUT_ELEMENT(TLC, _RX, _HDR_RAM_ECC_DBE_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(TLC, _RX, _DAT0_RAM_ECC_DBE_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(TLC, _RX, _DAT1_RAM_ECC_DBE_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(TLC, _TX, _CREQ_DAT_RAM_ECC_DBE_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL), + LUT_ELEMENT(TLC, _TX, _RSP_DAT_RAM_ECC_DBE_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL), + LUT_ELEMENT(TLC, _TX, _COM_DAT_RAM_ECC_DBE_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL), + LUT_ELEMENT(TLC, _TX, _RSP1_DAT_RAM_ECC_DBE_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(DL, _NA, _PHY_A_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(DL, _RX, _CRC_COUNTER_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(DL, _TX, _PL_ERROR_FATAL, _COUNT, _UNCORRECTABLE_FATAL), + LUT_ELEMENT(DL, _RX, _PL_ERROR_FATAL, _COUNT, _UNCORRECTABLE_FATAL) + }; + + ct_assert(INFOROM_NVLINK_DL_RX_FAULT_DL_PROTOCOL_FATAL == 0); + ct_assert(INFOROM_NVLINK_DL_RX_FAULT_SUBLINK_CHANGE_FATAL == 1); + ct_assert(INFOROM_NVLINK_DL_RX_FLIT_CRC_CORR == 2); + ct_assert(INFOROM_NVLINK_DL_RX_LANE0_CRC_CORR == 3); + ct_assert(INFOROM_NVLINK_DL_RX_LANE1_CRC_CORR == 4); + ct_assert(INFOROM_NVLINK_DL_RX_LANE2_CRC_CORR == 5); + ct_assert(INFOROM_NVLINK_DL_RX_LANE3_CRC_CORR == 6); + ct_assert(INFOROM_NVLINK_DL_RX_LINK_REPLAY_EVENTS_CORR == 7); + ct_assert(INFOROM_NVLINK_DL_TX_FAULT_RAM_FATAL == 8); + ct_assert(INFOROM_NVLINK_DL_TX_FAULT_INTERFACE_FATAL == 9); + ct_assert(INFOROM_NVLINK_DL_TX_FAULT_SUBLINK_CHANGE_FATAL == 10); + ct_assert(INFOROM_NVLINK_DL_TX_LINK_REPLAY_EVENTS_CORR == 11); + ct_assert(INFOROM_NVLINK_DL_LTSSM_FAULT_UP_FATAL == 12); + ct_assert(INFOROM_NVLINK_DL_LTSSM_FAULT_DOWN_FATAL == 13); + ct_assert(INFOROM_NVLINK_DL_LINK_RECOVERY_EVENTS_CORR == 14); + ct_assert(INFOROM_NVLINK_TLC_RX_DL_HDR_PARITY_ERR_FATAL == 15); + ct_assert(INFOROM_NVLINK_TLC_RX_DL_DATA_PARITY_ERR_FATAL == 16); + ct_assert(INFOROM_NVLINK_TLC_RX_DL_CTRL_PARITY_ERR_FATAL == 17); + ct_assert(INFOROM_NVLINK_TLC_RX_INVALID_AE_FATAL == 18); + ct_assert(INFOROM_NVLINK_TLC_RX_INVALID_BE_FATAL == 19); + ct_assert(INFOROM_NVLINK_TLC_RX_INVALID_ADDR_ALIGN_FATAL == 20); + ct_assert(INFOROM_NVLINK_TLC_RX_PKTLEN_ERR_FATAL == 21); + ct_assert(INFOROM_NVLINK_TLC_RX_RSVD_PACKET_STATUS_ERR_FATAL == 22); + ct_assert(INFOROM_NVLINK_TLC_RX_RSVD_CACHE_ATTR_PROBE_REQ_ERR_FATAL == 23); + ct_assert(INFOROM_NVLINK_TLC_RX_RSVD_CACHE_ATTR_PROBE_RSP_ERR_FATAL == 24); + ct_assert(INFOROM_NVLINK_TLC_RX_DATLEN_GT_RMW_REQ_MAX_ERR_FATAL == 25); + ct_assert(INFOROM_NVLINK_TLC_RX_DATLEN_LT_ATR_RSP_MIN_ERR_FATAL == 26); + ct_assert(INFOROM_NVLINK_TLC_RX_INVALID_CR_FATAL == 27); + ct_assert(INFOROM_NVLINK_TLC_RX_INVALID_COLLAPSED_RESPONSE_FATAL == 28); + ct_assert(INFOROM_NVLINK_TLC_RX_HDR_OVERFLOW_FATAL == 29); + ct_assert(INFOROM_NVLINK_TLC_RX_DATA_OVERFLOW_FATAL == 30); + ct_assert(INFOROM_NVLINK_TLC_RX_STOMP_DETECTED_FATAL == 31); + ct_assert(INFOROM_NVLINK_TLC_RX_RSVD_CMD_ENC_FATAL == 32); + ct_assert(INFOROM_NVLINK_TLC_RX_RSVD_DAT_LEN_ENC_FATAL == 33); + ct_assert(INFOROM_NVLINK_TLC_RX_INVALID_PO_FOR_CACHE_ATTR_FATAL == 34); + ct_assert(INFOROM_NVLINK_TLC_RX_RSP_STATUS_HW_ERR_NONFATAL == 35); + ct_assert(INFOROM_NVLINK_TLC_RX_RSP_STATUS_UR_ERR_NONFATAL == 36); + ct_assert(INFOROM_NVLINK_TLC_RX_RSP_STATUS_PRIV_ERR_NONFATAL == 37); + ct_assert(INFOROM_NVLINK_TLC_RX_POISON_NONFATAL == 38); + ct_assert(INFOROM_NVLINK_TLC_RX_AN1_HEARTBEAT_TIMEOUT_NONFATAL == 39); + ct_assert(INFOROM_NVLINK_TLC_RX_ILLEGAL_PRI_WRITE_NONFATAL == 40); + ct_assert(INFOROM_NVLINK_TLC_TX_DL_CREDIT_PARITY_ERR_FATAL == 41); + ct_assert(INFOROM_NVLINK_TLC_TX_NCISOC_HDR_ECC_DBE_FATAL == 42); + ct_assert(INFOROM_NVLINK_TLC_TX_NCISOC_PARITY_ERR_FATAL == 43); + ct_assert(INFOROM_NVLINK_TLC_TX_ILLEGAL_PRI_WRITE_NONFATAL == 44); + ct_assert(INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC0_NONFATAL == 45); + ct_assert(INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC1_NONFATAL == 46); + ct_assert(INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC2_NONFATAL == 47); + ct_assert(INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC3_NONFATAL == 48); + ct_assert(INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC4_NONFATAL == 49); + ct_assert(INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC5_NONFATAL == 50); + ct_assert(INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC6_NONFATAL == 51); + ct_assert(INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC7_NONFATAL == 52); + ct_assert(INFOROM_NVLINK_TLC_TX_POISON_NONFATAL == 53); + ct_assert(INFOROM_NVLINK_TLC_TX_RSP_STATUS_HW_ERR_NONFATAL == 54); + ct_assert(INFOROM_NVLINK_TLC_TX_RSP_STATUS_UR_ERR_NONFATAL == 55); + ct_assert(INFOROM_NVLINK_TLC_TX_RSP_STATUS_PRIV_ERR_NONFATAL == 56); + ct_assert(INFOROM_NVLINK_NVLIPT_SLEEP_WHILE_ACTIVE_LINK_FATAL == 57); + ct_assert(INFOROM_NVLINK_NVLIPT_RSTSEQ_PHYCTL_TIMEOUT_FATAL == 58); + ct_assert(INFOROM_NVLINK_NVLIPT_RSTSEQ_CLKCTL_TIMEOUT_FATAL == 59); + ct_assert(INFOROM_NVLINK_NVLIPT_CLKCTL_ILLEGAL_REQUEST_FATAL == 60); + ct_assert(INFOROM_NVLINK_NVLIPT_RSTSEQ_PLL_TIMEOUT_FATAL == 61); + ct_assert(INFOROM_NVLINK_NVLIPT_RSTSEQ_PHYARB_TIMEOUT_FATAL == 62); + ct_assert(INFOROM_NVLINK_NVLIPT_ILLEGAL_LINK_STATE_REQUEST_NONFATAL == 63); + ct_assert(INFOROM_NVLINK_NVLIPT_FAILED_MINION_REQUEST_NONFATAL == 64); + ct_assert(INFOROM_NVLINK_NVLIPT_RESERVED_REQUEST_VALUE_NONFATAL == 65); + ct_assert(INFOROM_NVLINK_NVLIPT_LINK_STATE_WRITE_WHILE_BUSY_NONFATAL == 66); + ct_assert(INFOROM_NVLINK_NVLIPT_WRITE_TO_LOCKED_SYSTEM_REG_NONFATAL == 67); + ct_assert(INFOROM_NVLINK_NVLIPT_LINK_STATE_REQUEST_TIMEOUT_NONFATAL == 68); + ct_assert(INFOROM_NVLINK_TLC_RX_HDR_RAM_ECC_DBE_FATAL == 69); + ct_assert(INFOROM_NVLINK_TLC_RX_DAT0_RAM_ECC_DBE_FATAL == 70); + ct_assert(INFOROM_NVLINK_TLC_RX_DAT1_RAM_ECC_DBE_FATAL == 71); + ct_assert(INFOROM_NVLINK_TLC_TX_CREQ_DAT_RAM_ECC_DBE_NONFATAL == 72); + ct_assert(INFOROM_NVLINK_TLC_TX_RSP_DAT_RAM_ECC_DBE_NONFATAL == 73); + ct_assert(INFOROM_NVLINK_TLC_TX_COM_DAT_RAM_ECC_DBE_NONFATAL == 74); + ct_assert(INFOROM_NVLINK_TLC_TX_RSP1_DAT_RAM_ECC_DBE_FATAL == 75); + ct_assert(INFOROM_NVLINK_DL_PHY_A_FATAL == 76); + ct_assert(INFOROM_NVLINK_DL_RX_CRC_COUNTER_FATAL == 77); + ct_assert(INFOROM_NVLINK_DL_TX_PL_ERROR_FATAL == 78); + ct_assert(INFOROM_NVLINK_DL_RX_PL_ERROR_FATAL == 79); + + ct_assert(NV_ARRAY_ELEMENTS(lut) == INFOROM_NVLINK_MAX_ERROR_TYPE); + + if (error >= NV_ARRAY_ELEMENTS(lut)) + { + return -NVL_BAD_ARGS; + } + + *pHeader = lut[error].header; + *pMetadata = lut[error].metadata; + *pErrorSubtype = lut[error].errorSubtype; + *pBlockType = lut[error].blockType; + return NVL_SUCCESS; +} + +NvlStatus +inforom_nvl_v3_encode_nvlipt_error_subtype +( + NvU8 localLinkIdx, + NvU8 *pSubtype +) +{ + static const NvBool linkIdxValidLut[] = + { + NV_TRUE, + NV_TRUE, + NV_TRUE, + NV_FALSE, + NV_FALSE, + NV_FALSE, + NV_TRUE, + NV_TRUE, + NV_TRUE, + NV_TRUE, + NV_TRUE, + NV_TRUE + }; + + ct_assert(NVLIPT_NA_SLEEP_WHILE_ACTIVE_LINK_FATAL_COUNT == 0); + ct_assert(NVLIPT_NA_RSTSEQ_PHYCTL_TIMEOUT_FATAL_COUNT == 1); + ct_assert(NVLIPT_NA_RSTSEQ_CLKCTL_TIMEOUT_FATAL_COUNT == 2); + ct_assert(NVLIPT_NA_CLKCTL_ILLEGAL_REQUEST_FATAL_COUNT == 3); + ct_assert(NVLIPT_NA_RSTSEQ_PLL_TIMEOUT_FATAL_COUNT == 4); + ct_assert(NVLIPT_NA_RSTSEQ_PHYARB_TIMEOUT_FATAL_COUNT == 5); + ct_assert(NVLIPT_NA_ILLEGAL_LINK_STATE_REQUEST_NONFATAL_COUNT == 6); + ct_assert(NVLIPT_NA_FAILED_MINION_REQUEST_NONFATAL_COUNT == 7); + ct_assert(NVLIPT_NA_RESERVED_REQUEST_VALUE_NONFATAL_COUNT == 8); + ct_assert(NVLIPT_NA_LINK_STATE_WRITE_WHILE_BUSY_NONFATAL_COUNT == 9); + ct_assert(NVLIPT_NA_WRITE_TO_LOCKED_SYSTEM_REG_NONFATAL_COUNT == 10); + ct_assert(NVLIPT_NA_LINK_STATE_REQUEST_TIMEOUT_NONFATAL_COUNT == 11); + + if ((localLinkIdx >= NV_INFOROM_NVL_OBJECT_V3_NVLIPT_ERROR_LINK_ID_COMMON) || + (*pSubtype >= NV_ARRAY_ELEMENTS(linkIdxValidLut))) + { + return -NVL_BAD_ARGS; + } + + if (linkIdxValidLut[*pSubtype]) + { + *pSubtype = FLD_SET_DRF_NUM(_INFOROM_NVL_OBJECT_V3, _NVLIPT_ERROR, + _LINK_ID, localLinkIdx, *pSubtype); + } + else + { + *pSubtype = FLD_SET_DRF(_INFOROM_NVL_OBJECT_V3, _NVLIPT_ERROR, _LINK_ID, + _COMMON, *pSubtype); + } + + return NVL_SUCCESS; +} + +NvBool +inforom_nvl_v3_should_replace_error_rate_entry +( + INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE *pErrorRate, + NvU32 flitCrcRate, + NvU32 *pLaneCrcRates +) +{ + NvU32 i; + NvU64 currentLaneCrcRateSum = 0; + NvU64 maxLaneCrcRateSum = 0; + + for (i = 0; i < NV_ARRAY_ELEMENTS(pErrorRate->laneCrcErrorsPerMinute); i++) + { + currentLaneCrcRateSum += pLaneCrcRates[i]; + maxLaneCrcRateSum += pErrorRate->laneCrcErrorsPerMinute[i]; + } + + return (flitCrcRate > pErrorRate->flitCrcErrorsPerMinute) || + (currentLaneCrcRateSum > maxLaneCrcRateSum); +} + +void +inforom_nvl_v3_seconds_to_day_and_month +( + NvU32 sec, + NvU32 *pDay, + NvU32 *pMonth +) +{ + *pDay = sec / (60 * 60 * 24); + *pMonth = *pDay / 30; +} + +void +inforom_nvl_v3_update_error_rate_entry +( + INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE *pErrorRate, + NvU32 newSec, + NvU32 newFlitCrcRate, + NvU32 *pNewLaneCrcRates +) +{ + pErrorRate->lastUpdated = newSec; + pErrorRate->flitCrcErrorsPerMinute = newFlitCrcRate; + nvswitch_os_memcpy(pErrorRate->laneCrcErrorsPerMinute, pNewLaneCrcRates, + sizeof(pErrorRate->laneCrcErrorsPerMinute)); +} + +NvlStatus +inforom_nvl_v3_map_error_to_userspace_error +( + nvswitch_device *device, + INFOROM_NVL_OBJECT_V3_ERROR_ENTRY *pErrorLog, + NVSWITCH_NVLINK_ERROR_ENTRY *pNvlError +) +{ + static const NvU32 DL_RX_ERRORS[] = + { + NVSWITCH_NVLINK_ERR_DL_RX_FAULT_DL_PROTOCOL_FATAL, + NVSWITCH_NVLINK_ERR_DL_RX_FAULT_SUBLINK_CHANGE_FATAL, + NVSWITCH_NVLINK_ERR_DL_RX_FLIT_CRC_CORR, + NVSWITCH_NVLINK_ERR_DL_RX_LANE0_CRC_CORR, + NVSWITCH_NVLINK_ERR_DL_RX_LANE1_CRC_CORR, + NVSWITCH_NVLINK_ERR_DL_RX_LANE2_CRC_CORR, + NVSWITCH_NVLINK_ERR_DL_RX_LANE3_CRC_CORR, + NVSWITCH_NVLINK_ERR_DL_RX_LINK_REPLAY_EVENTS_CORR + }; + + static const NvU32 DL_TX_ERRORS[] = + { + NVSWITCH_NVLINK_ERR_DL_TX_FAULT_RAM_FATAL, + NVSWITCH_NVLINK_ERR_DL_TX_FAULT_INTERFACE_FATAL, + NVSWITCH_NVLINK_ERR_DL_TX_FAULT_SUBLINK_CHANGE_FATAL, + NVSWITCH_NVLINK_ERR_DL_TX_LINK_REPLAY_EVENTS_CORR + }; + + static const NvU32 DL_NA_ERRORS[] = + { + NVSWITCH_NVLINK_ERR_DL_LTSSM_FAULT_UP_FATAL, + NVSWITCH_NVLINK_ERR_DL_LTSSM_FAULT_DOWN_FATAL, + NVSWITCH_NVLINK_ERR_DL_LINK_RECOVERY_EVENTS_CORR + }; + + static const NvU32 TLC_RX_ERRORS[] = + { + NVSWITCH_NVLINK_ERR_TLC_RX_DL_HDR_PARITY_ERR_FATAL, + NVSWITCH_NVLINK_ERR_TLC_RX_DL_DATA_PARITY_ERR_FATAL, + NVSWITCH_NVLINK_ERR_TLC_RX_DL_CTRL_PARITY_ERR_FATAL, + NVSWITCH_NVLINK_ERR_TLC_RX_INVALID_AE_FATAL, + NVSWITCH_NVLINK_ERR_TLC_RX_INVALID_BE_FATAL, + NVSWITCH_NVLINK_ERR_TLC_RX_INVALID_ADDR_ALIGN_FATAL, + NVSWITCH_NVLINK_ERR_TLC_RX_PKTLEN_ERR_FATAL, + NVSWITCH_NVLINK_ERR_TLC_RX_RSVD_PACKET_STATUS_ERR_FATAL, + NVSWITCH_NVLINK_ERR_TLC_RX_RSVD_CACHE_ATTR_PROBE_REQ_ERR_FATAL, + NVSWITCH_NVLINK_ERR_TLC_RX_RSVD_CACHE_ATTR_PROBE_RSP_ERR_FATAL, + NVSWITCH_NVLINK_ERR_TLC_RX_DATLEN_GT_RMW_REQ_MAX_ERR_FATAL, + NVSWITCH_NVLINK_ERR_TLC_RX_DATLEN_LT_ATR_RSP_MIN_ERR_FATAL, + NVSWITCH_NVLINK_ERR_TLC_RX_INVALID_CR_FATAL, + NVSWITCH_NVLINK_ERR_TLC_RX_INVALID_COLLAPSED_RESPONSE_FATAL, + NVSWITCH_NVLINK_ERR_TLC_RX_HDR_OVERFLOW_FATAL, + NVSWITCH_NVLINK_ERR_TLC_RX_DATA_OVERFLOW_FATAL, + NVSWITCH_NVLINK_ERR_TLC_RX_STOMP_DETECTED_FATAL, + NVSWITCH_NVLINK_ERR_TLC_RX_RSVD_CMD_ENC_FATAL, + NVSWITCH_NVLINK_ERR_TLC_RX_RSVD_DAT_LEN_ENC_FATAL, + NVSWITCH_NVLINK_ERR_TLC_RX_INVALID_PO_FOR_CACHE_ATTR_FATAL, + NVSWITCH_NVLINK_ERR_TLC_RX_RSP_STATUS_HW_ERR_NONFATAL, + NVSWITCH_NVLINK_ERR_TLC_RX_RSP_STATUS_UR_ERR_NONFATAL, + NVSWITCH_NVLINK_ERR_TLC_RX_RSP_STATUS_PRIV_ERR_NONFATAL, + NVSWITCH_NVLINK_ERR_TLC_RX_POISON_NONFATAL, + NVSWITCH_NVLINK_ERR_TLC_RX_AN1_HEARTBEAT_TIMEOUT_NONFATAL, + NVSWITCH_NVLINK_ERR_TLC_RX_ILLEGAL_PRI_WRITE_NONFATAL, + NVSWITCH_NVLINK_ERR_TLC_RX_HDR_RAM_ECC_DBE_FATAL, + NVSWITCH_NVLINK_ERR_TLC_RX_DAT0_RAM_ECC_DBE_FATAL, + NVSWITCH_NVLINK_ERR_TLC_RX_DAT1_RAM_ECC_DBE_FATAL + }; + + static const NvU32 TLC_TX_ERRORS[] = + { + NVSWITCH_NVLINK_ERR_TLC_TX_DL_CREDIT_PARITY_ERR_FATAL, + NVSWITCH_NVLINK_ERR_TLC_TX_NCISOC_HDR_ECC_DBE_FATAL, + NVSWITCH_NVLINK_ERR_TLC_TX_NCISOC_PARITY_ERR_FATAL, + NVSWITCH_NVLINK_ERR_TLC_TX_ILLEGAL_PRI_WRITE_NONFATAL, + NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC0_NONFATAL, + NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC1_NONFATAL, + NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC2_NONFATAL, + NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC3_NONFATAL, + NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC4_NONFATAL, + NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC5_NONFATAL, + NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC6_NONFATAL, + NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC7_NONFATAL, + NVSWITCH_NVLINK_ERR_TLC_TX_POISON_NONFATAL, + NVSWITCH_NVLINK_ERR_TLC_TX_RSP_STATUS_HW_ERR_NONFATAL, + NVSWITCH_NVLINK_ERR_TLC_TX_RSP_STATUS_UR_ERR_NONFATAL, + NVSWITCH_NVLINK_ERR_TLC_TX_RSP_STATUS_PRIV_ERR_NONFATAL, + NVSWITCH_NVLINK_ERR_TLC_TX_CREQ_DAT_RAM_ECC_DBE_NONFATAL, + NVSWITCH_NVLINK_ERR_TLC_TX_RSP_DAT_RAM_ECC_DBE_NONFATAL, + NVSWITCH_NVLINK_ERR_TLC_TX_COM_DAT_RAM_ECC_DBE_NONFATAL, + NVSWITCH_NVLINK_ERR_TLC_TX_RSP1_DAT_RAM_ECC_DBE_FATAL + }; + + static const NvU32 LIPT_ERRORS[] = + { + NVSWITCH_NVLINK_ERR_NVLIPT_SLEEP_WHILE_ACTIVE_LINK_FATAL, + NVSWITCH_NVLINK_ERR_NVLIPT_RSTSEQ_PHYCTL_TIMEOUT_FATAL, + NVSWITCH_NVLINK_ERR_NVLIPT_RSTSEQ_CLKCTL_TIMEOUT_FATAL, + NVSWITCH_NVLINK_ERR_NVLIPT_CLKCTL_ILLEGAL_REQUEST_FATAL, + NVSWITCH_NVLINK_ERR_NVLIPT_RSTSEQ_PLL_TIMEOUT_FATAL, + NVSWITCH_NVLINK_ERR_NVLIPT_RSTSEQ_PHYARB_TIMEOUT_FATAL, + NVSWITCH_NVLINK_ERR_NVLIPT_ILLEGAL_LINK_STATE_REQUEST_NONFATAL, + NVSWITCH_NVLINK_ERR_NVLIPT_FAILED_MINION_REQUEST_NONFATAL, + NVSWITCH_NVLINK_ERR_NVLIPT_RESERVED_REQUEST_VALUE_NONFATAL, + NVSWITCH_NVLINK_ERR_NVLIPT_LINK_STATE_WRITE_WHILE_BUSY_NONFATAL, + NVSWITCH_NVLINK_ERR_NVLIPT_WRITE_TO_LOCKED_SYSTEM_REG_NONFATAL, + NVSWITCH_NVLINK_ERR_NVLIPT_LINK_STATE_REQUEST_TIMEOUT_NONFATAL + }; + + NvU32 subType = 0; + NvU8 nvliptInstance = 0, localLinkIdx = 0; + NvU8 numLinksPerNvlipt = device->hal.nvswitch_get_num_links_per_nvlipt(device);; + + if ((pErrorLog == NULL) || (pNvlError == NULL)) + { + return -NVL_BAD_ARGS; + } + + subType = DRF_VAL(_INFOROM_NVL_OBJECT_V3, _NVLIPT_ERROR, _SUBTYPE, pErrorLog->errorSubtype); + nvliptInstance = DRF_VAL(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _NVLIPT_INSTANCE_ID, pErrorLog->metadata); + pNvlError->timeStamp = pErrorLog->data.event.lastError; + + if (pErrorLog->header == INFOROM_NVL_ERROR_TYPE_COUNT) + { + pNvlError->count = (NvU64)pErrorLog->data.event.totalCount; + } + else if (pErrorLog->header == INFOROM_NVL_ERROR_TYPE_ACCUM) + { + pNvlError->count = pErrorLog->data.accum.totalCount.hi; + pNvlError->count = (pNvlError->count << 32) | pErrorLog->data.accum.totalCount.lo; + } + else + { + return -NVL_ERR_NOT_SUPPORTED; + } + + if (FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, _DL0, pErrorLog->metadata) || + FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, _DL1, pErrorLog->metadata) || + FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, _DL2, pErrorLog->metadata) || + FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, _DL3, pErrorLog->metadata) || + FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, _DL4, pErrorLog->metadata) || + FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, _DL5, pErrorLog->metadata)) + { + localLinkIdx = DRF_VAL(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, pErrorLog->metadata); + pNvlError->instance = nvliptInstance * numLinksPerNvlipt + localLinkIdx; + + if (FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _DIRECTION, _NA, pErrorLog->metadata) && + (subType < (sizeof(DL_NA_ERRORS) / sizeof(DL_NA_ERRORS[0])))) + { + pNvlError->error = DL_NA_ERRORS[subType]; + return NVL_SUCCESS; + } + else if (FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _DIRECTION, _RX, pErrorLog->metadata) && + (subType < (sizeof(DL_RX_ERRORS) / sizeof(DL_RX_ERRORS[0])))) + { + pNvlError->error = DL_RX_ERRORS[subType]; + return NVL_SUCCESS; + } + else if (FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _DIRECTION, _TX, pErrorLog->metadata) && + (subType < (sizeof(DL_TX_ERRORS) / sizeof(DL_TX_ERRORS[0])))) + { + pNvlError->error = DL_TX_ERRORS[subType]; + return NVL_SUCCESS; + } + } + + else if (FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, _TLC0, pErrorLog->metadata) || + FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, _TLC1, pErrorLog->metadata) || + FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, _TLC2, pErrorLog->metadata) || + FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, _TLC3, pErrorLog->metadata) || + FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, _TLC4, pErrorLog->metadata) || + FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, _TLC5, pErrorLog->metadata)) + { + localLinkIdx = DRF_VAL(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, pErrorLog->metadata) + - NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_TLC0; + pNvlError->instance = nvliptInstance * numLinksPerNvlipt + localLinkIdx; + + if (FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _DIRECTION, _RX, pErrorLog->metadata) && + (subType < (sizeof(TLC_RX_ERRORS) / sizeof(TLC_RX_ERRORS[0])))) + { + pNvlError->error = TLC_RX_ERRORS[subType]; + return NVL_SUCCESS; + } + else if (FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _DIRECTION, _TX, pErrorLog->metadata) && + (subType < (sizeof(TLC_TX_ERRORS) / sizeof(TLC_TX_ERRORS[0])))) + { + pNvlError->error = TLC_TX_ERRORS[subType]; + return NVL_SUCCESS; + } + } + else if (FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, _NVLIPT, pErrorLog->metadata)) + { + if (subType < (sizeof(LIPT_ERRORS) / sizeof(LIPT_ERRORS[0]))) + { + if (FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _NVLIPT_ERROR, _LINK_ID, _COMMON, pErrorLog->errorSubtype)) + { + localLinkIdx = 0; //common nvlipt error + } + else + { + localLinkIdx = DRF_VAL(_INFOROM_NVL_OBJECT_V3, _NVLIPT_ERROR, _LINK_ID, pErrorLog->errorSubtype); + } + + pNvlError->instance = nvliptInstance * numLinksPerNvlipt + localLinkIdx; + pNvlError->error = LIPT_ERRORS[subType]; + return NVL_SUCCESS; + } + } + + return -NVL_ERR_NOT_SUPPORTED; +} + +void +inforom_nvl_v3_update_correctable_error_rates +( + INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V3S *pState, + NvU8 link, + INFOROM_NVLINK_CORRECTABLE_ERROR_COUNTS *pCounts +) +{ + NvU32 i; + NvU32 tempFlitCrc, tempRxLinkReplay, tempTxLinkReplay, tempLinkRecovery; + NvU32 tempLaneCrc[4]; + + // + // If the registers have decreased from last reported, then + // they must have been reset or have overflowed. Set the last + // register value to 0. + // + if (pCounts->flitCrc < pState->lastRead[link].flitCrc) + { + pState->lastRead[link].flitCrc = 0; + } + + for (i = 0; i < NV_ARRAY_ELEMENTS(pState->lastRead[link].laneCrc); i++) + { + if (pCounts->laneCrc[i] < pState->lastRead[link].laneCrc[i]) + { + pState->lastRead[link].laneCrc[i] = 0; + } + } + + // Get number of new errors since the last register read + tempFlitCrc = pCounts->flitCrc; + pCounts->flitCrc -= pState->lastRead[link].flitCrc; + + // Update errors per minute with error delta + m_inforom_nvl_get_new_errors_per_minute(pCounts->flitCrc, + &pState->errorsPerMinute[link].flitCrc); + + // Save the current register value for the next callback + pState->lastRead[link].flitCrc = tempFlitCrc; + + for (i = 0; i < NV_ARRAY_ELEMENTS(pState->lastRead[link].laneCrc); i++) + { + tempLaneCrc[i] = pCounts->laneCrc[i]; + pCounts->laneCrc[i] -= pState->lastRead[link].laneCrc[i]; + m_inforom_nvl_get_new_errors_per_minute(pCounts->laneCrc[i], + &pState->errorsPerMinute[link].laneCrc[i]); + + pState->lastRead[link].laneCrc[i] = tempLaneCrc[i]; + } + + // + // We don't track rates for the following errors. We just need to stash + // the current register value and update pCounts with the delta since + // the last register read. + // + if (pCounts->rxLinkReplay < pState->lastRead[link].rxLinkReplay) + { + pState->lastRead[link].rxLinkReplay = 0; + } + tempRxLinkReplay = pCounts->rxLinkReplay; + pCounts->rxLinkReplay -= pState->lastRead[link].rxLinkReplay; + pState->lastRead[link].rxLinkReplay = tempRxLinkReplay; + + if (pCounts->txLinkReplay < pState->lastRead[link].txLinkReplay) + { + pState->lastRead[link].txLinkReplay = 0; + } + tempTxLinkReplay = pCounts->txLinkReplay; + pCounts->txLinkReplay -= pState->lastRead[link].txLinkReplay; + pState->lastRead[link].txLinkReplay = tempTxLinkReplay; + + if (pCounts->linkRecovery < pState->lastRead[link].linkRecovery) + { + pState->lastRead[link].linkRecovery = 0; + } + tempLinkRecovery = pCounts->linkRecovery; + pCounts->linkRecovery -= pState->lastRead[link].linkRecovery; + pState->lastRead[link].linkRecovery = tempLinkRecovery; +} + diff --git a/src/common/nvswitch/kernel/inforom/inforom_nvl_v4_nvswitch.c b/src/common/nvswitch/kernel/inforom/inforom_nvl_v4_nvswitch.c new file mode 100644 index 000000000..311607aec --- /dev/null +++ b/src/common/nvswitch/kernel/inforom/inforom_nvl_v4_nvswitch.c @@ -0,0 +1,108 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "common_nvswitch.h" +#include "inforom/inforom_nvswitch.h" +#include "inforom/inforom_nvl_v4_nvswitch.h" +#include "ls10/ls10.h" + +void +inforom_nvl_v4_update_correctable_error_rates +( + INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V4S *pState, + NvU8 link, + INFOROM_NVLINK_CORRECTABLE_ERROR_COUNTS *pCounts +) +{ + NvU32 i; + NvU32 tempFlitCrc, tempRxLinkReplay, tempTxLinkReplay, tempLinkRecovery; + NvU32 tempLaneCrc[4]; + + // + // If the registers have decreased from last reported, then + // they must have been reset or have overflowed. Set the last + // register value to 0. + // + if (pCounts->flitCrc < pState->lastRead[link].flitCrc) + { + pState->lastRead[link].flitCrc = 0; + } + + for (i = 0; i < NV_ARRAY_ELEMENTS(pState->lastRead[link].laneCrc); i++) + { + if (pCounts->laneCrc[i] < pState->lastRead[link].laneCrc[i]) + { + pState->lastRead[link].laneCrc[i] = 0; + } + } + + // Get number of new errors since the last register read + tempFlitCrc = pCounts->flitCrc; + pCounts->flitCrc -= pState->lastRead[link].flitCrc; + + // Update errors per minute with error delta + m_inforom_nvl_get_new_errors_per_minute(pCounts->flitCrc, + &pState->errorsPerMinute[link].flitCrc); + + // Save the current register value for the next callback + pState->lastRead[link].flitCrc = tempFlitCrc; + + for (i = 0; i < NV_ARRAY_ELEMENTS(pState->lastRead[link].laneCrc); i++) + { + tempLaneCrc[i] = pCounts->laneCrc[i]; + pCounts->laneCrc[i] -= pState->lastRead[link].laneCrc[i]; + m_inforom_nvl_get_new_errors_per_minute(pCounts->laneCrc[i], + &pState->errorsPerMinute[link].laneCrc[i]); + + pState->lastRead[link].laneCrc[i] = tempLaneCrc[i]; + } + + // + // We don't track rates for the following errors. We just need to stash + // the current register value and update pCounts with the delta since + // the last register read. + // + if (pCounts->rxLinkReplay < pState->lastRead[link].rxLinkReplay) + { + pState->lastRead[link].rxLinkReplay = 0; + } + tempRxLinkReplay = pCounts->rxLinkReplay; + pCounts->rxLinkReplay -= pState->lastRead[link].rxLinkReplay; + pState->lastRead[link].rxLinkReplay = tempRxLinkReplay; + + if (pCounts->txLinkReplay < pState->lastRead[link].txLinkReplay) + { + pState->lastRead[link].txLinkReplay = 0; + } + tempTxLinkReplay = pCounts->txLinkReplay; + pCounts->txLinkReplay -= pState->lastRead[link].txLinkReplay; + pState->lastRead[link].txLinkReplay = tempTxLinkReplay; + + if (pCounts->linkRecovery < pState->lastRead[link].linkRecovery) + { + pState->lastRead[link].linkRecovery = 0; + } + tempLinkRecovery = pCounts->linkRecovery; + pCounts->linkRecovery -= pState->lastRead[link].linkRecovery; + pState->lastRead[link].linkRecovery = tempLinkRecovery; +} diff --git a/src/common/nvswitch/kernel/inforom/inforom_nvswitch.c b/src/common/nvswitch/kernel/inforom/inforom_nvswitch.c index a144a7516..ca98eb6ee 100644 --- a/src/common/nvswitch/kernel/inforom/inforom_nvswitch.c +++ b/src/common/nvswitch/kernel/inforom/inforom_nvswitch.c @@ -516,6 +516,7 @@ _nvswitch_inforom_read_file fsRet = *(NvU32*)pDmaBuf; if (fsRet != NV_OK) { + status = -NVL_IO_ERROR; NVSWITCH_PRINT(device, ERROR, "%s: FS error %x. Filename: %3s\n", __FUNCTION__, fsRet, pParams->fileName); } @@ -613,6 +614,7 @@ _nvswitch_inforom_write_file fsRet = *(NvU32*)pDmaBuf; if (fsRet != NV_OK) { + status = -NVL_IO_ERROR; NVSWITCH_PRINT(device, ERROR, "%s: FS returned %x. Filename: %3s\n", __FUNCTION__, fsRet, pParams->fileName); } @@ -623,11 +625,6 @@ ifr_dma_unmap_and_exit: ifr_dma_free_and_exit: nvswitch_os_free_contig_memory(device->os_handle, pDmaBuf, transferSize); - if (status != NV_OK) - { - return status; - } - return status; } diff --git a/src/common/nvswitch/kernel/lr10/inforom_lr10.c b/src/common/nvswitch/kernel/lr10/inforom_lr10.c index d19c12e44..c7d3c0e29 100644 --- a/src/common/nvswitch/kernel/lr10/inforom_lr10.c +++ b/src/common/nvswitch/kernel/lr10/inforom_lr10.c @@ -31,12 +31,14 @@ #include "nvswitch/lr10/dev_pmgr.h" #include "nvVer.h" #include "regkey_nvswitch.h" +#include "inforom/inforom_nvl_v3_nvswitch.h" // // TODO: Split individual object hals to their own respective files // static void _oms_parse(nvswitch_device *device, INFOROM_OMS_STATE *pOmsState); static void _oms_refresh(nvswitch_device *device, INFOROM_OMS_STATE *pOmsState); + NvlStatus nvswitch_inforom_nvl_log_error_event_lr10 ( @@ -46,7 +48,147 @@ nvswitch_inforom_nvl_log_error_event_lr10 NvBool *bDirty ) { - return -NVL_ERR_NOT_SUPPORTED; + NvlStatus status; + INFOROM_NVL_OBJECT_V3S *pNvlObject = &((PINFOROM_NVL_OBJECT)pNvlGeneric)->v3s; + INFOROM_NVLINK_ERROR_EVENT *pErrorEvent = (INFOROM_NVLINK_ERROR_EVENT *)pNvlErrorEvent; + INFOROM_NVL_OBJECT_V3_ERROR_ENTRY *pErrorEntry; + NvU32 i; + NvU32 sec; + NvU8 header = 0; + NvU16 metadata = 0; + NvU8 errorSubtype; + NvU64 accumTotalCount; + INFOROM_NVL_ERROR_BLOCK_TYPE blockType; + + if (pErrorEvent->nvliptInstance > INFOROM_NVL_OBJECT_V3_NVLIPT_INSTANCE_MAX) + { + NVSWITCH_PRINT(device, ERROR, + "object cannot log data for more than %u NVLIPTs (NVLIPT = %u requested)\n", + INFOROM_NVL_OBJECT_V3_NVLIPT_INSTANCE_MAX, pErrorEvent->nvliptInstance); + return -NVL_BAD_ARGS; + } + + if (pErrorEvent->localLinkIdx > INFOROM_NVL_OBJECT_V3_BLOCK_ID_MAX) + { + NVSWITCH_PRINT(device, ERROR, + "object cannot log data for more than %u internal links (internal link = %u requested)\n", + INFOROM_NVL_OBJECT_V3_BLOCK_ID_MAX, pErrorEvent->localLinkIdx); + return -NVL_BAD_ARGS; + } + + sec = (NvU32) (nvswitch_os_get_platform_time_epoch() / NVSWITCH_INTERVAL_1SEC_IN_NS); + + status = inforom_nvl_v3_map_error(pErrorEvent->error, &header, &metadata, + &errorSubtype, &blockType); + if (status != NVL_SUCCESS) + { + return status; + } + + metadata = FLD_SET_DRF_NUM(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, + _NVLIPT_INSTANCE_ID, pErrorEvent->nvliptInstance, metadata); + if (blockType == INFOROM_NVL_ERROR_BLOCK_TYPE_DL) + { + metadata = FLD_SET_DRF_NUM(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, + NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_DL(pErrorEvent->localLinkIdx), + metadata); + } + else if (blockType == INFOROM_NVL_ERROR_BLOCK_TYPE_TLC) + { + metadata = FLD_SET_DRF_NUM(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, + NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_TLC(pErrorEvent->localLinkIdx), + metadata); + } + else if (blockType == INFOROM_NVL_ERROR_BLOCK_TYPE_NVLIPT) + { + metadata = FLD_SET_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, + _BLOCK_ID, _NVLIPT, metadata); + status = inforom_nvl_v3_encode_nvlipt_error_subtype(pErrorEvent->localLinkIdx, + &errorSubtype); + if (status != NVL_SUCCESS) + { + return status; + } + } + + for (i = 0; i < INFOROM_NVL_OBJECT_V3S_NUM_ERROR_ENTRIES; i++) + { + pErrorEntry = &pNvlObject->errorLog[i]; + + if ((pErrorEntry->header == INFOROM_NVL_ERROR_TYPE_INVALID) || + ((pErrorEntry->metadata == metadata) && + (pErrorEntry->errorSubtype == errorSubtype))) + { + break; + } + } + + if (i >= INFOROM_NVL_OBJECT_V3S_NUM_ERROR_ENTRIES) + { + NVSWITCH_PRINT(device, ERROR, "%s: NVL error log is full -- unable to log error\n", + __FUNCTION__); + return -NVL_ERR_INVALID_STATE; + } + + if (pErrorEntry->header == INFOROM_NVL_ERROR_TYPE_INVALID) + { + pErrorEntry->header = header; + pErrorEntry->metadata = metadata; + pErrorEntry->errorSubtype = errorSubtype; + } + + if (pErrorEntry->header == INFOROM_NVL_ERROR_TYPE_ACCUM) + { + accumTotalCount = NvU64_ALIGN32_VAL(&pErrorEntry->data.accum.totalCount); + if (accumTotalCount != NV_U64_MAX) + { + if (pErrorEvent->count > NV_U64_MAX - accumTotalCount) + { + accumTotalCount = NV_U64_MAX; + } + else + { + accumTotalCount += pErrorEvent->count; + } + + NvU64_ALIGN32_PACK(&pErrorEntry->data.accum.totalCount, &accumTotalCount); + if (sec < pErrorEntry->data.accum.lastUpdated) + { + NVSWITCH_PRINT(device, ERROR, + "%s: System clock reporting earlier time than error timestamp\n", + __FUNCTION__); + } + pErrorEntry->data.accum.lastUpdated = sec; + *bDirty = NV_TRUE; + } + } + else if (pErrorEntry->header == INFOROM_NVL_ERROR_TYPE_COUNT) + { + if (pErrorEntry->data.event.totalCount != NV_U32_MAX) + { + pErrorEntry->data.event.totalCount++; + if (sec < pErrorEntry->data.event.lastError) + { + NVSWITCH_PRINT(device, ERROR, + "%s: System clock reporting earlier time than error timestamp\n", + __FUNCTION__); + } + else + { + pErrorEntry->data.event.avgEventDelta = + (pErrorEntry->data.event.avgEventDelta + sec - + pErrorEntry->data.event.lastError) >> 1; + } + pErrorEntry->data.event.lastError = sec; + *bDirty = NV_TRUE; + } + } + else + { + return -NVL_ERR_INVALID_STATE; + } + + return NVL_SUCCESS; } NvlStatus @@ -56,7 +198,37 @@ nvswitch_inforom_nvl_get_max_correctable_error_rate_lr10 NVSWITCH_GET_NVLINK_MAX_CORRECTABLE_ERROR_RATES_PARAMS *params ) { - return -NVL_ERR_NOT_SUPPORTED; + + struct inforom *pInforom = device->pInforom; + INFOROM_NVLINK_STATE *pNvlinkState; + NvU8 linkID = params->linkId; + + if (linkID >= NVSWITCH_NUM_LINKS_LR10) + { + return -NVL_BAD_ARGS; + } + + if (pInforom == NULL) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + pNvlinkState = pInforom->pNvlinkState; + if (pNvlinkState == NULL) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + nvswitch_os_memset(params, 0, sizeof(NVSWITCH_GET_NVLINK_MAX_CORRECTABLE_ERROR_RATES_PARAMS)); + params->linkId = linkID; + + nvswitch_os_memcpy(¶ms->dailyMaxCorrectableErrorRates, &pNvlinkState->pNvl->v3s.maxCorrectableErrorRates.dailyMaxCorrectableErrorRates[0][linkID], + sizeof(params->dailyMaxCorrectableErrorRates)); + + nvswitch_os_memcpy(¶ms->monthlyMaxCorrectableErrorRates, &pNvlinkState->pNvl->v3s.maxCorrectableErrorRates.monthlyMaxCorrectableErrorRates[0][linkID], + sizeof(params->monthlyMaxCorrectableErrorRates)); + + return NVL_SUCCESS; } NvlStatus @@ -66,8 +238,64 @@ nvswitch_inforom_nvl_get_errors_lr10 NVSWITCH_GET_NVLINK_ERROR_COUNTS_PARAMS *params ) { - return -NVL_ERR_NOT_SUPPORTED; + struct inforom *pInforom = device->pInforom; + INFOROM_NVLINK_STATE *pNvlinkState; + NvU32 maxReadSize = sizeof(params->errorLog)/sizeof(NVSWITCH_NVLINK_ERROR_ENTRY); + NvU32 errorLeftCount = 0, errorReadCount = 0, errIndx = 0; + NvU32 errorStart = params->errorIndex; + + if (pInforom == NULL) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + pNvlinkState = pInforom->pNvlinkState; + if (pNvlinkState == NULL) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + if (errorStart >= INFOROM_NVL_OBJECT_V3S_NUM_ERROR_ENTRIES) + { + return -NVL_BAD_ARGS; + } + + nvswitch_os_memset(params->errorLog, 0, sizeof(params->errorLog)); + + while (((errorStart + errorLeftCount) < INFOROM_NVL_OBJECT_V3S_NUM_ERROR_ENTRIES) && + (pNvlinkState->pNvl->v3s.errorLog[errorStart + errorLeftCount].header != INFOROM_NVL_ERROR_TYPE_INVALID)) + { + errorLeftCount++; + } + + if (errorLeftCount > maxReadSize) + { + errorReadCount = maxReadSize; + } + else + { + errorReadCount = errorLeftCount; + } + + params->errorIndex = errorStart + errorReadCount; + params->errorCount = errorReadCount; + + if (errorReadCount > 0) + { + for (errIndx = 0; errIndx < errorReadCount; errIndx++) + { + if (inforom_nvl_v3_map_error_to_userspace_error(device, + &pNvlinkState->pNvl->v3s.errorLog[errorStart+errIndx], + ¶ms->errorLog[errIndx]) != NVL_SUCCESS) + { + return -NVL_ERR_NOT_SUPPORTED; + } + } + } + + return NVL_SUCCESS; } + NvlStatus nvswitch_inforom_nvl_update_link_correctable_error_info_lr10 ( nvswitch_device *device, @@ -79,9 +307,251 @@ NvlStatus nvswitch_inforom_nvl_update_link_correctable_error_info_lr10 void *pNvlErrorCounts, NvBool *bDirty ) +{ + INFOROM_NVL_OBJECT_V3S *pNvlObject = &((PINFOROM_NVL_OBJECT)pNvlGeneric)->v3s; + INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V3S *pState = + &((INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE *)pData)->v3s; + INFOROM_NVLINK_CORRECTABLE_ERROR_COUNTS *pErrorCounts = + (INFOROM_NVLINK_CORRECTABLE_ERROR_COUNTS *)pNvlErrorCounts; + + NvU32 i; + NvU32 sec; + NvU32 day, month, currentEntryDay, currentEntryMonth; + INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE *pErrorRate; + INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE *pOldestErrorRate = NULL; + INFOROM_NVL_OBJECT_V3S_MAX_CORRECTABLE_ERROR_RATES *pCorrErrorRates; + NvBool bUpdated = NV_FALSE; + INFOROM_NVLINK_ERROR_EVENT errorEvent; + NvU32 currentFlitCrcRate; + NvU32 *pCurrentLaneCrcRates; + + if (bDirty == NULL) + { + return -NVL_BAD_ARGS; + } + + *bDirty = NV_FALSE; + + if (linkId >= INFOROM_NVL_OBJECT_V3S_NUM_LINKS) + { + NVSWITCH_PRINT(device, ERROR, + "object does not store data for more than %u links (linkId = %u requested)\n", + INFOROM_NVL_OBJECT_V3S_NUM_LINKS, linkId); + return -NVL_BAD_ARGS; + } + + if (nvliptInstance > INFOROM_NVL_OBJECT_V3_NVLIPT_INSTANCE_MAX) + { + NVSWITCH_PRINT(device, ERROR, + "object cannot log data for more than %u NVLIPTs (NVLIPT = %u requested)\n", + INFOROM_NVL_OBJECT_V3_NVLIPT_INSTANCE_MAX, nvliptInstance); + return -NVL_BAD_ARGS; + } + + if (localLinkIdx > INFOROM_NVL_OBJECT_V3_BLOCK_ID_MAX) + { + NVSWITCH_PRINT(device, ERROR, + "object cannot log data for more than %u internal links (internal link = %u requested)\n", + INFOROM_NVL_OBJECT_V3_BLOCK_ID_MAX, localLinkIdx); + return -NVL_BAD_ARGS; + } + + sec = (NvU32) (nvswitch_os_get_platform_time_epoch() / NVSWITCH_INTERVAL_1SEC_IN_NS); + inforom_nvl_v3_seconds_to_day_and_month(sec, &day, &month); + + inforom_nvl_v3_update_correctable_error_rates(pState, linkId, pErrorCounts); + currentFlitCrcRate = pState->errorsPerMinute[linkId].flitCrc; + pCurrentLaneCrcRates = pState->errorsPerMinute[linkId].laneCrc; + pCorrErrorRates = &pNvlObject->maxCorrectableErrorRates; + + for (i = 0; i < NV_ARRAY_ELEMENTS(pCorrErrorRates->dailyMaxCorrectableErrorRates); i++) + { + pErrorRate = &pCorrErrorRates->dailyMaxCorrectableErrorRates[i][linkId]; + inforom_nvl_v3_seconds_to_day_and_month(pErrorRate->lastUpdated, ¤tEntryDay, + ¤tEntryMonth); + + if ((pErrorRate->lastUpdated == 0) || (currentEntryDay == day)) + { + if (inforom_nvl_v3_should_replace_error_rate_entry(pErrorRate, + currentFlitCrcRate, + pCurrentLaneCrcRates)) + { + inforom_nvl_v3_update_error_rate_entry(pErrorRate, sec, + currentFlitCrcRate, + pCurrentLaneCrcRates); + bUpdated = NV_TRUE; + } + pOldestErrorRate = NULL; + break; + } + else if ((pOldestErrorRate == NULL) || + (pErrorRate->lastUpdated < pOldestErrorRate->lastUpdated)) + { + pOldestErrorRate = pErrorRate; + } + } + + if (pOldestErrorRate != NULL) + { + inforom_nvl_v3_update_error_rate_entry(pOldestErrorRate, sec, + currentFlitCrcRate, + pCurrentLaneCrcRates); + bUpdated = NV_TRUE; + } + + for (i = 0; i < NV_ARRAY_ELEMENTS(pCorrErrorRates->monthlyMaxCorrectableErrorRates); i++) + { + pErrorRate = &pCorrErrorRates->monthlyMaxCorrectableErrorRates[i][linkId]; + inforom_nvl_v3_seconds_to_day_and_month(pErrorRate->lastUpdated, ¤tEntryDay, + ¤tEntryMonth); + + if ((pErrorRate->lastUpdated == 0) || (currentEntryMonth == month)) + { + if (inforom_nvl_v3_should_replace_error_rate_entry(pErrorRate, + currentFlitCrcRate, + pCurrentLaneCrcRates)) + { + inforom_nvl_v3_update_error_rate_entry(pErrorRate, sec, + currentFlitCrcRate, + pCurrentLaneCrcRates); + bUpdated = NV_TRUE; + } + pOldestErrorRate = NULL; + break; + } + else if ((pOldestErrorRate == NULL) || + (pErrorRate->lastUpdated < pOldestErrorRate->lastUpdated)) + { + pOldestErrorRate = pErrorRate; + } + } + + if (pOldestErrorRate != NULL) + { + inforom_nvl_v3_update_error_rate_entry(pOldestErrorRate, sec, + currentFlitCrcRate, + pCurrentLaneCrcRates); + bUpdated = NV_TRUE; + } + + *bDirty = bUpdated; + + // Update aggregate error counts for each correctable error + + errorEvent.nvliptInstance = nvliptInstance; + errorEvent.localLinkIdx = localLinkIdx; + + if (pErrorCounts->flitCrc > 0) + { + errorEvent.error = INFOROM_NVLINK_DL_RX_FLIT_CRC_CORR; + errorEvent.count = pErrorCounts->flitCrc; + nvswitch_inforom_nvl_log_error_event_lr10(device, + pNvlGeneric, &errorEvent, &bUpdated); + *bDirty |= bUpdated; + } + + if (pErrorCounts->rxLinkReplay > 0) + { + errorEvent.error = INFOROM_NVLINK_DL_RX_LINK_REPLAY_EVENTS_CORR; + errorEvent.count = pErrorCounts->rxLinkReplay; + bUpdated = NV_FALSE; + nvswitch_inforom_nvl_log_error_event_lr10(device, + pNvlGeneric, &errorEvent, &bUpdated); + *bDirty |= bUpdated; + } + + if (pErrorCounts->txLinkReplay > 0) + { + errorEvent.error = INFOROM_NVLINK_DL_TX_LINK_REPLAY_EVENTS_CORR; + errorEvent.count = pErrorCounts->txLinkReplay; + bUpdated = NV_FALSE; + nvswitch_inforom_nvl_log_error_event_lr10(device, + pNvlGeneric, &errorEvent, &bUpdated); + *bDirty |= bUpdated; + } + + if (pErrorCounts->linkRecovery > 0) + { + errorEvent.error = INFOROM_NVLINK_DL_LINK_RECOVERY_EVENTS_CORR; + errorEvent.count = pErrorCounts->linkRecovery; + bUpdated = NV_FALSE; + nvswitch_inforom_nvl_log_error_event_lr10(device, + pNvlGeneric, &errorEvent, &bUpdated); + *bDirty |= bUpdated; + } + + for (i = 0; i < 4; i++) + { + if (pErrorCounts->laneCrc[i] == 0) + { + continue; + } + + errorEvent.error = INFOROM_NVLINK_DL_RX_LANE0_CRC_CORR + i; + errorEvent.count = pErrorCounts->laneCrc[i]; + bUpdated = NV_FALSE; + nvswitch_inforom_nvl_log_error_event_lr10(device, + pNvlGeneric, &errorEvent, &bUpdated); + *bDirty |= bUpdated; + } + + return NVL_SUCCESS; +} + +NvlStatus nvswitch_inforom_nvl_setL1Threshold_lr10 +( + nvswitch_device *device, + void *pNvlGeneric, + NvU32 word1, + NvU32 word2 +) { return -NVL_ERR_NOT_SUPPORTED; } + +NvlStatus nvswitch_inforom_nvl_getL1Threshold_lr10 +( + nvswitch_device *device, + void *pNvlGeneric, + NvU32 *word1, + NvU32 *word2 +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus nvswitch_inforom_nvl_setup_nvlink_state_lr10 +( + nvswitch_device *device, + INFOROM_NVLINK_STATE *pNvlinkState, + NvU8 version +) +{ + if (version != 3) + { + NVSWITCH_PRINT(device, WARN, "NVL v%u not supported\n", version); + return -NVL_ERR_NOT_SUPPORTED; + } + + pNvlinkState->pFmt = INFOROM_NVL_OBJECT_V3S_FMT; + pNvlinkState->pPackedObject = nvswitch_os_malloc(INFOROM_NVL_OBJECT_V3S_PACKED_SIZE); + if (pNvlinkState->pPackedObject == NULL) + { + return -NVL_NO_MEM; + } + + pNvlinkState->pNvl = nvswitch_os_malloc(sizeof(INFOROM_NVL_OBJECT)); + if (pNvlinkState->pNvl == NULL) + { + nvswitch_os_free(pNvlinkState->pPackedObject); + return -NVL_NO_MEM; + } + + pNvlinkState->bDisableCorrectableErrorLogging = NV_FALSE; + + return NVL_SUCCESS; +} + static NvlStatus _inforom_ecc_find_useable_entry_index diff --git a/src/common/nvswitch/kernel/lr10/intr_lr10.c b/src/common/nvswitch/kernel/lr10/intr_lr10.c index 29d9fae35..bbb606e0f 100644 --- a/src/common/nvswitch/kernel/lr10/intr_lr10.c +++ b/src/common/nvswitch/kernel/lr10/intr_lr10.c @@ -3492,11 +3492,16 @@ _nvswitch_service_nvltlc_rx_lnk_nonfatal_0_lr10 { NvU32 pending, bit, unhandled; NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + INFOROM_NVLINK_ERROR_EVENT error_event; + NvU32 injected; report.raw_pending = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_STATUS_0); report.raw_enable = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_NON_FATAL_REPORT_EN_0); report.mask = report.raw_enable; + error_event.nvliptInstance = (NvU8) nvlipt_instance; + error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LR10(link); + pending = report.raw_pending & report.mask; if (pending == 0) { @@ -3505,6 +3510,7 @@ _nvswitch_service_nvltlc_rx_lnk_nonfatal_0_lr10 unhandled = pending; report.raw_first = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_FIRST_0); + injected = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_REPORT_INJECT_0); bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXRSPSTATUS_PRIV_ERR, 1); if (nvswitch_test_flags(pending, bit)) @@ -3512,6 +3518,11 @@ _nvswitch_service_nvltlc_rx_lnk_nonfatal_0_lr10 NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_RX_LNK_RXRSPSTATUS_PRIV_ERR, "RX Rsp Status PRIV Error"); nvswitch_clear_flags(&unhandled, bit); + if (FLD_TEST_DRF_NUM(_NVLTLC_RX_LNK, _ERR_REPORT_INJECT_0, _RXRSPSTATUS_PRIV_ERR, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_RX_RSP_STATUS_PRIV_ERR_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } NVSWITCH_UNHANDLED_CHECK(device, unhandled); @@ -3544,12 +3555,17 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_0_lr10 { NvU32 pending, bit, unhandled; NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + INFOROM_NVLINK_ERROR_EVENT error_event; + NvU32 injected; report.raw_pending = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_STATUS_0); report.raw_enable = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_NON_FATAL_REPORT_EN_0); report.mask = report.raw_enable; pending = report.raw_pending & report.mask; + error_event.nvliptInstance = (NvU8) nvlipt_instance; + error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LR10(link); + if (pending == 0) { return -NVL_NOT_FOUND; @@ -3557,12 +3573,20 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_0_lr10 unhandled = pending; report.raw_first = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_FIRST_0); + injected = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_REPORT_INJECT_0); bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_0, _CREQ_RAM_DAT_ECC_DBE_ERR, 1); if (nvswitch_test_flags(pending, bit)) { NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_CREQ_RAM_DAT_ECC_DBE_ERR, "CREQ RAM DAT ECC DBE Error"); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC_TX_LNK, _ERR_REPORT_INJECT_0, _CREQ_RAM_DAT_ECC_DBE_ERR, 0x0, injected)) + { + // TODO 3014908 log these in the NVL object until we have ECC object support + error_event.error = INFOROM_NVLINK_TLC_TX_CREQ_DAT_RAM_ECC_DBE_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_0, _CREQ_RAM_ECC_LIMIT_ERR, 1); @@ -3591,6 +3615,13 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_0_lr10 { NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_COM_RAM_DAT_ECC_DBE_ERR, "COM RAM DAT ECC DBE Error"); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC_TX_LNK, _ERR_REPORT_INJECT_0, _COM_RAM_DAT_ECC_DBE_ERR, 0x0, injected)) + { + // TODO 3014908 log these in the NVL object until we have ECC object support + error_event.error = INFOROM_NVLINK_TLC_TX_COM_DAT_RAM_ECC_DBE_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_0, _COM_RAM_ECC_LIMIT_ERR, 1); @@ -3642,14 +3673,19 @@ _nvswitch_service_nvltlc_rx_lnk_nonfatal_1_lr10 NvU32 link ) { - NvU32 pending, bit, unhandled, injected; + NvU32 pending, bit, unhandled; NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + INFOROM_NVLINK_ERROR_EVENT error_event; + NvU32 injected; report.raw_pending = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_STATUS_1); report.raw_enable = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_NON_FATAL_REPORT_EN_1); report.mask = report.raw_enable; pending = report.raw_pending & report.mask; + error_event.nvliptInstance = (NvU8) nvlipt_instance; + error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LR10(link); + if (pending == 0) { return -NVL_NOT_FOUND; @@ -3667,6 +3703,8 @@ _nvswitch_service_nvltlc_rx_lnk_nonfatal_1_lr10 if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_1, _AN1_HEARTBEAT_TIMEOUT_ERR, 0x0, injected)) { + error_event.error = INFOROM_NVLINK_TLC_RX_AN1_HEARTBEAT_TIMEOUT_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); // // WAR Bug 200627368: Mask off HBTO to avoid a storm // During the start of reset_and_drain, all links on the GPU @@ -3719,12 +3757,17 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_1_lr10 { NvU32 pending, bit, unhandled; NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + INFOROM_NVLINK_ERROR_EVENT error_event = { 0 }; + NvU32 injected; report.raw_pending = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_STATUS_1); report.raw_enable = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_NON_FATAL_REPORT_EN_1); report.mask = report.raw_enable; pending = report.raw_pending & report.mask; + error_event.nvliptInstance = (NvU8) nvlipt_instance; + error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LR10(link); + if (pending == 0) { return -NVL_NOT_FOUND; @@ -3732,12 +3775,19 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_1_lr10 unhandled = pending; report.raw_first = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_FIRST_1); + injected = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_REPORT_INJECT_1); bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _AN1_TIMEOUT_VC0, 1); if (nvswitch_test_flags(pending, bit)) { NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC0, "AN1 Timeout VC0"); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _TX_LNK_ERR_REPORT_INJECT_1, _AN1_TIMEOUT_VC0, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC0_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _AN1_TIMEOUT_VC1, 1); @@ -3745,6 +3795,12 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_1_lr10 { NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC1, "AN1 Timeout VC1"); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _TX_LNK_ERR_REPORT_INJECT_1, _AN1_TIMEOUT_VC1, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC1_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _AN1_TIMEOUT_VC2, 1); @@ -3752,6 +3808,12 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_1_lr10 { NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC2, "AN1 Timeout VC2"); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _TX_LNK_ERR_REPORT_INJECT_1, _AN1_TIMEOUT_VC2, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC2_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _AN1_TIMEOUT_VC3, 1); @@ -3760,6 +3822,11 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_1_lr10 NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC3, "AN1 Timeout VC3"); nvswitch_clear_flags(&unhandled, bit); + if (FLD_TEST_DRF_NUM(_NVLTLC, _TX_LNK_ERR_REPORT_INJECT_1, _AN1_TIMEOUT_VC3, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC3_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _AN1_TIMEOUT_VC4, 1); @@ -3768,6 +3835,11 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_1_lr10 NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC4, "AN1 Timeout VC4"); nvswitch_clear_flags(&unhandled, bit); + if (FLD_TEST_DRF_NUM(_NVLTLC, _TX_LNK_ERR_REPORT_INJECT_1, _AN1_TIMEOUT_VC4, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC4_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _AN1_TIMEOUT_VC5, 1); @@ -3775,6 +3847,12 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_1_lr10 { NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC5, "AN1 Timeout VC5"); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _TX_LNK_ERR_REPORT_INJECT_1, _AN1_TIMEOUT_VC5, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC5_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _AN1_TIMEOUT_VC6, 1); @@ -3782,6 +3860,12 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_1_lr10 { NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC6, "AN1 Timeout VC6"); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _TX_LNK_ERR_REPORT_INJECT_1, _AN1_TIMEOUT_VC6, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC6_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _AN1_TIMEOUT_VC7, 1); @@ -3789,6 +3873,12 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_1_lr10 { NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC7, "AN1 Timeout VC7"); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _TX_LNK_ERR_REPORT_INJECT_1, _AN1_TIMEOUT_VC7, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC7_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } NVSWITCH_UNHANDLED_CHECK(device, unhandled); @@ -3890,11 +3980,16 @@ _nvswitch_service_nvlipt_lnk_nonfatal_lr10 { NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; NvU32 pending, bit, unhandled; + INFOROM_NVLINK_ERROR_EVENT error_event = { 0 }; + NvU32 injected; report.raw_pending = NVSWITCH_LINK_RD32_LR10(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_STATUS_0); report.raw_enable = NVSWITCH_LINK_RD32_LR10(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_NON_FATAL_REPORT_EN_0); report.mask = report.raw_enable; + error_event.nvliptInstance = (NvU8) nvlipt_instance; + error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LR10(link); + pending = report.raw_pending & report.mask; if (pending == 0) { @@ -3903,12 +3998,19 @@ _nvswitch_service_nvlipt_lnk_nonfatal_lr10 unhandled = pending; report.raw_first = NVSWITCH_LINK_RD32_LR10(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_FIRST_0); + injected = NVSWITCH_LINK_RD32_LR10(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_REPORT_INJECT_0); bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _ILLEGALLINKSTATEREQUEST, 1); if (nvswitch_test_flags(pending, bit)) { NVSWITCH_REPORT_NONFATAL(_HW_NVLIPT_LNK_ILLEGALLINKSTATEREQUEST, "_HW_NVLIPT_LNK_ILLEGALLINKSTATEREQUEST"); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLIPT_LNK, _ERR_REPORT_INJECT_0, _ILLEGALLINKSTATEREQUEST, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_NVLIPT_ILLEGAL_LINK_STATE_REQUEST_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _FAILEDMINIONREQUEST, 1); @@ -3916,6 +4018,12 @@ _nvswitch_service_nvlipt_lnk_nonfatal_lr10 { NVSWITCH_REPORT_NONFATAL(_HW_NVLIPT_LNK_FAILEDMINIONREQUEST, "_FAILEDMINIONREQUEST"); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLIPT_LNK, _ERR_REPORT_INJECT_0, _FAILEDMINIONREQUEST, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_NVLIPT_FAILED_MINION_REQUEST_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _RESERVEDREQUESTVALUE, 1); @@ -3923,6 +4031,12 @@ _nvswitch_service_nvlipt_lnk_nonfatal_lr10 { NVSWITCH_REPORT_NONFATAL(_HW_NVLIPT_LNK_RESERVEDREQUESTVALUE, "_RESERVEDREQUESTVALUE"); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLIPT_LNK, _ERR_REPORT_INJECT_0, _RESERVEDREQUESTVALUE, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_NVLIPT_RESERVED_REQUEST_VALUE_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _LINKSTATEWRITEWHILEBUSY, 1); @@ -3930,6 +4044,12 @@ _nvswitch_service_nvlipt_lnk_nonfatal_lr10 { NVSWITCH_REPORT_NONFATAL(_HW_NVLIPT_LNK_LINKSTATEWRITEWHILEBUSY, "_LINKSTATEWRITEWHILEBUSY"); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLIPT_LNK, _ERR_REPORT_INJECT_0, _LINKSTATEWRITEWHILEBUSY, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_NVLIPT_LINK_STATE_WRITE_WHILE_BUSY_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _LINK_STATE_REQUEST_TIMEOUT, 1); @@ -3937,6 +4057,12 @@ _nvswitch_service_nvlipt_lnk_nonfatal_lr10 { NVSWITCH_REPORT_NONFATAL(_HW_NVLIPT_LNK_LINK_STATE_REQUEST_TIMEOUT, "_LINK_STATE_REQUEST_TIMEOUT"); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLIPT_LNK, _ERR_REPORT_INJECT_0, _LINK_STATE_REQUEST_TIMEOUT, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_NVLIPT_LINK_STATE_REQUEST_TIMEOUT_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _WRITE_TO_LOCKED_SYSTEM_REG_ERR, 1); @@ -3944,6 +4070,12 @@ _nvswitch_service_nvlipt_lnk_nonfatal_lr10 { NVSWITCH_REPORT_NONFATAL(_HW_NVLIPT_LNK_WRITE_TO_LOCKED_SYSTEM_REG_ERR, "_WRITE_TO_LOCKED_SYSTEM_REG_ERR"); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLIPT_LNK, _ERR_REPORT_INJECT_0, _WRITE_TO_LOCKED_SYSTEM_REG_ERR, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_NVLIPT_WRITE_TO_LOCKED_SYSTEM_REG_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } NVSWITCH_UNHANDLED_CHECK(device, unhandled); @@ -4456,12 +4588,16 @@ nvswitch_service_nvldl_fatal_link_lr10 { NvU32 pending, bit, unhandled; NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + INFOROM_NVLINK_ERROR_EVENT error_event; report.raw_pending = NVSWITCH_LINK_RD32_LR10(device, link, NVLDL, _NVLDL_TOP, _INTR); report.raw_enable = NVSWITCH_LINK_RD32_LR10(device, link, NVLDL, _NVLDL_TOP, _INTR_STALL_EN); report.mask = report.raw_enable; pending = report.raw_pending & report.mask; + error_event.nvliptInstance = (NvU8) nvlipt_instance; + error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LR10(link); + if (pending == 0) { return -NVL_NOT_FOUND; @@ -4474,6 +4610,8 @@ nvswitch_service_nvldl_fatal_link_lr10 { NVSWITCH_REPORT_FATAL(_HW_DLPL_TX_FAULT_RAM, "TX Fault Ram", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + error_event.error = INFOROM_NVLINK_DL_TX_FAULT_RAM_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); } bit = DRF_NUM(_NVLDL_TOP, _INTR, _TX_FAULT_INTERFACE, 1); @@ -4481,6 +4619,8 @@ nvswitch_service_nvldl_fatal_link_lr10 { NVSWITCH_REPORT_FATAL(_HW_DLPL_TX_FAULT_INTERFACE, "TX Fault Interface", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + error_event.error = INFOROM_NVLINK_DL_TX_FAULT_INTERFACE_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); } bit = DRF_NUM(_NVLDL_TOP, _INTR, _TX_FAULT_SUBLINK_CHANGE, 1); @@ -4488,6 +4628,8 @@ nvswitch_service_nvldl_fatal_link_lr10 { NVSWITCH_REPORT_FATAL(_HW_DLPL_TX_FAULT_SUBLINK_CHANGE, "TX Fault Sublink Change", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + error_event.error = INFOROM_NVLINK_DL_TX_FAULT_SUBLINK_CHANGE_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); } bit = DRF_NUM(_NVLDL_TOP, _INTR, _RX_FAULT_SUBLINK_CHANGE, 1); @@ -4495,6 +4637,8 @@ nvswitch_service_nvldl_fatal_link_lr10 { NVSWITCH_REPORT_FATAL(_HW_DLPL_RX_FAULT_SUBLINK_CHANGE, "RX Fault Sublink Change", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + error_event.error = INFOROM_NVLINK_DL_RX_FAULT_SUBLINK_CHANGE_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); } bit = DRF_NUM(_NVLDL_TOP, _INTR, _RX_FAULT_DL_PROTOCOL, 1); @@ -4502,6 +4646,8 @@ nvswitch_service_nvldl_fatal_link_lr10 { NVSWITCH_REPORT_FATAL(_HW_DLPL_RX_FAULT_DL_PROTOCOL, "RX Fault DL Protocol", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + error_event.error = INFOROM_NVLINK_DL_RX_FAULT_DL_PROTOCOL_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); } bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_DOWN, 1); @@ -4509,6 +4655,8 @@ nvswitch_service_nvldl_fatal_link_lr10 { NVSWITCH_REPORT_FATAL(_HW_DLPL_LTSSM_FAULT_DOWN, "LTSSM Fault Down", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + error_event.error = INFOROM_NVLINK_DL_LTSSM_FAULT_DOWN_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); } bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_UP, 1); @@ -4516,6 +4664,8 @@ nvswitch_service_nvldl_fatal_link_lr10 { NVSWITCH_REPORT_FATAL(_HW_DLPL_LTSSM_FAULT_UP, "LTSSM Fault Up", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + error_event.error = INFOROM_NVLINK_DL_LTSSM_FAULT_UP_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); } bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_PROTOCOL, 1); @@ -4621,12 +4771,17 @@ _nvswitch_service_nvltlc_tx_sys_fatal_lr10 { NvU32 pending, bit, unhandled; NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + INFOROM_NVLINK_ERROR_EVENT error_event = { 0 }; + NvU32 injected; report.raw_pending = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_SYS, _ERR_STATUS_0); report.raw_enable = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_SYS, _ERR_FATAL_REPORT_EN_0); report.mask = report.raw_enable; pending = report.raw_pending & report.mask; + error_event.nvliptInstance = (NvU8) nvlipt_instance; + error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LR10(link); + if (pending == 0) { return -NVL_NOT_FOUND; @@ -4634,12 +4789,19 @@ _nvswitch_service_nvltlc_tx_sys_fatal_lr10 unhandled = pending; report.raw_first = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_SYS, _ERR_FIRST_0); + injected = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_SYS, _ERR_REPORT_INJECT_0); bit = DRF_NUM(_NVLTLC_TX_SYS, _ERR_STATUS_0, _NCISOC_PARITY_ERR, 1); if (nvswitch_test_flags(pending, bit)) { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_TX_SYS_NCISOC_PARITY_ERR, "NCISOC Parity Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _TX_SYS_ERR_REPORT_INJECT_0, _NCISOC_PARITY_ERR, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_TX_NCISOC_PARITY_ERR_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_TX_SYS, _ERR_STATUS_0, _NCISOC_HDR_ECC_DBE_ERR, 1); @@ -4647,6 +4809,12 @@ _nvswitch_service_nvltlc_tx_sys_fatal_lr10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_TX_SYS_NCISOC_HDR_ECC_DBE_ERR, "NCISOC HDR ECC DBE Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _TX_SYS_ERR_REPORT_INJECT_0, _NCISOC_HDR_ECC_DBE_ERR, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_TX_NCISOC_HDR_ECC_DBE_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_TX_SYS, _ERR_STATUS_0, _NCISOC_DAT_ECC_DBE_ERR, 1); @@ -4729,12 +4897,17 @@ _nvswitch_service_nvltlc_rx_sys_fatal_lr10 { NvU32 pending, bit, unhandled; NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + INFOROM_NVLINK_ERROR_EVENT error_event = { 0 }; + NvU32 injected; report.raw_pending = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_SYS, _ERR_STATUS_0); report.raw_enable = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_SYS, _ERR_FATAL_REPORT_EN_0); report.mask = report.raw_enable; pending = report.raw_pending & report.mask; + error_event.nvliptInstance = (NvU8) nvlipt_instance; + error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LR10(link); + if (pending == 0) { return -NVL_NOT_FOUND; @@ -4742,6 +4915,7 @@ _nvswitch_service_nvltlc_rx_sys_fatal_lr10 unhandled = pending; report.raw_first = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_SYS, _ERR_FIRST_0); + injected = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_SYS, _ERR_REPORT_INJECT_0); bit = DRF_NUM(_NVLTLC_RX_SYS, _ERR_STATUS_0, _NCISOC_PARITY_ERR, 1); if (nvswitch_test_flags(pending, bit)) @@ -4755,6 +4929,13 @@ _nvswitch_service_nvltlc_rx_sys_fatal_lr10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_SYS_HDR_RAM_ECC_DBE_ERR, "HDR RAM ECC DBE Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC_RX_SYS, _ERR_REPORT_INJECT_0, _HDR_RAM_ECC_DBE_ERR, 0x0, injected)) + { + // TODO 3014908 log these in the NVL object until we have ECC object support + error_event.error = INFOROM_NVLINK_TLC_RX_HDR_RAM_ECC_DBE_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_SYS, _ERR_STATUS_0, _HDR_RAM_ECC_LIMIT_ERR, 1); @@ -4769,6 +4950,13 @@ _nvswitch_service_nvltlc_rx_sys_fatal_lr10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_SYS_DAT0_RAM_ECC_DBE_ERR, "DAT0 RAM ECC DBE Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC_RX_SYS, _ERR_REPORT_INJECT_0, _DAT0_RAM_ECC_DBE_ERR, 0x0, injected)) + { + // TODO 3014908 log these in the NVL object until we have ECC object support + error_event.error = INFOROM_NVLINK_TLC_RX_DAT0_RAM_ECC_DBE_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_SYS, _ERR_STATUS_0, _DAT0_RAM_ECC_LIMIT_ERR, 1); @@ -4783,6 +4971,13 @@ _nvswitch_service_nvltlc_rx_sys_fatal_lr10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_SYS_DAT1_RAM_ECC_DBE_ERR, "DAT1 RAM ECC DBE Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC_RX_SYS, _ERR_REPORT_INJECT_0, _DAT1_RAM_ECC_DBE_ERR, 0x0, injected)) + { + // TODO 3014908 log these in the NVL object until we have ECC object support + error_event.error = INFOROM_NVLINK_TLC_RX_DAT1_RAM_ECC_DBE_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_SYS, _ERR_STATUS_0, _DAT1_RAM_ECC_LIMIT_ERR, 1); @@ -4830,12 +5025,17 @@ _nvswitch_service_nvltlc_tx_lnk_fatal_0_lr10 { NvU32 pending, bit, unhandled; NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + INFOROM_NVLINK_ERROR_EVENT error_event = { 0 }; + NvU32 injected; report.raw_pending = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_STATUS_0); report.raw_enable = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_FATAL_REPORT_EN_0); report.mask = report.raw_enable; pending = report.raw_pending & report.mask; + error_event.nvliptInstance = (NvU8) nvlipt_instance; + error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LR10(link); + if (pending == 0) { return -NVL_NOT_FOUND; @@ -4843,12 +5043,19 @@ _nvswitch_service_nvltlc_tx_lnk_fatal_0_lr10 unhandled = pending; report.raw_first = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_FIRST_0); + injected = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_REPORT_INJECT_0); bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_0, _TXDLCREDITPARITYERR, 1); if (nvswitch_test_flags(pending, bit)) { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_TXDLCREDITPARITYERR, "TX DL Credit Parity Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _TX_LNK_ERR_REPORT_INJECT_0, _TXDLCREDITPARITYERR, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_TX_DL_CREDIT_PARITY_ERR_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_0, _CREQ_RAM_HDR_ECC_DBE_ERR, 1); @@ -4884,6 +5091,13 @@ _nvswitch_service_nvltlc_tx_lnk_fatal_0_lr10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_TX_LNK_RSP1_RAM_DAT_ECC_DBE_ERR, "RSP1 RAM DAT ECC DBE Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC_TX_LNK, _ERR_REPORT_INJECT_0, _RSP1_RAM_DAT_ECC_DBE_ERR, 0x0, injected)) + { + // TODO 3014908 log these in the NVL object until we have ECC object support + error_event.error = INFOROM_NVLINK_TLC_TX_RSP1_DAT_RAM_ECC_DBE_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } NVSWITCH_UNHANDLED_CHECK(device, unhandled); @@ -4923,11 +5137,17 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10 { NvU32 pending, bit, unhandled; NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + INFOROM_NVLINK_ERROR_EVENT error_event = { 0 }; + NvU32 injected; report.raw_pending = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_STATUS_0); report.raw_enable = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_FATAL_REPORT_EN_0); report.mask = report.raw_enable; pending = report.raw_pending & report.mask; + + error_event.nvliptInstance = (NvU8) nvlipt_instance; + error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LR10(link); + if (pending == 0) { return -NVL_NOT_FOUND; @@ -4935,12 +5155,19 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10 unhandled = pending; report.raw_first = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_FIRST_0); + injected = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_REPORT_INJECT_0); bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXDLHDRPARITYERR, 1); if (nvswitch_test_flags(pending, bit)) { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXDLHDRPARITYERR, "RX DL HDR Parity Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _RXDLHDRPARITYERR, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_RX_DL_HDR_PARITY_ERR_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXDLDATAPARITYERR, 1); @@ -4948,6 +5175,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXDLDATAPARITYERR, "RX DL Data Parity Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _RXDLDATAPARITYERR, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_RX_DL_DATA_PARITY_ERR_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXDLCTRLPARITYERR, 1); @@ -4955,6 +5188,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXDLCTRLPARITYERR, "RX DL Ctrl Parity Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _RXDLCTRLPARITYERR, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_RX_DL_CTRL_PARITY_ERR_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXINVALIDAEERR, 1); @@ -4962,6 +5201,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXINVALIDAEERR, "RX Invalid DAE Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _RXINVALIDAEERR, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_RX_INVALID_AE_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXINVALIDBEERR, 1); @@ -4969,6 +5214,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXINVALIDBEERR, "RX Invalid BE Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _RXINVALIDBEERR, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_RX_INVALID_BE_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXINVALIDADDRALIGNERR, 1); @@ -4976,6 +5227,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXINVALIDADDRALIGNERR, "RX Invalid Addr Align Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _RXINVALIDADDRALIGNERR, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_RX_INVALID_ADDR_ALIGN_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXPKTLENERR, 1); @@ -4983,6 +5240,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXPKTLENERR, "RX Packet Length Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _RXPKTLENERR, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_RX_PKTLEN_ERR_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RSVCMDENCERR, 1); @@ -4990,6 +5253,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RSVCMDENCERR, "RSV Cmd Encoding Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _RSVCMDENCERR, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_RX_RSVD_CMD_ENC_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RSVDATLENENCERR, 1); @@ -4997,6 +5266,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RSVDATLENENCERR, "RSV Data Length Encoding Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _RSVDATLENENCERR, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_RX_RSVD_DAT_LEN_ENC_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RSVPKTSTATUSERR, 1); @@ -5004,6 +5279,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RSVPKTSTATUSERR, "RSV Packet Status Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _RSVPKTSTATUSERR, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_RX_RSVD_PACKET_STATUS_ERR_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RSVCACHEATTRPROBEREQERR, 1); @@ -5011,6 +5292,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RSVCACHEATTRPROBEREQERR, "RSV Packet Status Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _RSVCACHEATTRPROBEREQERR, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_RX_RSVD_CACHE_ATTR_PROBE_REQ_ERR_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RSVCACHEATTRPROBERSPERR, 1); @@ -5018,6 +5305,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RSVCACHEATTRPROBERSPERR, "RSV CacheAttr Probe Rsp Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _RSVCACHEATTRPROBERSPERR, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_RX_RSVD_CACHE_ATTR_PROBE_RSP_ERR_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _DATLENGTRMWREQMAXERR, 1); @@ -5025,6 +5318,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_DATLENGTRMWREQMAXERR, "Data Length RMW Req Max Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _DATLENGTRMWREQMAXERR, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_RX_DATLEN_GT_RMW_REQ_MAX_ERR_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _DATLENLTATRRSPMINERR, 1); @@ -5032,6 +5331,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_DATLENLTATRRSPMINERR, "Data Len Lt ATR RSP Min Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _DATLENLTATRRSPMINERR, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_RX_DATLEN_LT_ATR_RSP_MIN_ERR_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _INVALIDCACHEATTRPOERR, 1); @@ -5039,6 +5344,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_INVALIDCACHEATTRPOERR, "Invalid Cache Attr PO Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _INVALIDCACHEATTRPOERR, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_RX_INVALID_PO_FOR_CACHE_ATTR_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _INVALIDCRERR, 1); @@ -5046,6 +5357,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_INVALIDCRERR, "Invalid CR Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _INVALIDCRERR, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_RX_INVALID_CR_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXRSPSTATUS_HW_ERR, 1); @@ -5053,6 +5370,13 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_LNK_RXRSPSTATUS_HW_ERR, "RX Rsp Status HW Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + // TODO 200564153 _RX_RSPSTATUS_HW_ERR should be reported as non-fatal + if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _RXRSPSTATUS_HW_ERR, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_RX_RSP_STATUS_HW_ERR_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXRSPSTATUS_UR_ERR, 1); @@ -5060,6 +5384,13 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_LNK_RXRSPSTATUS_UR_ERR, "RX Rsp Status UR Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + // TODO 200564153 _RX_RSPSTATUS_UR_ERR should be reported as non-fatal + if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _RXRSPSTATUS_UR_ERR, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_RX_RSP_STATUS_UR_ERR_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _INVALID_COLLAPSED_RESPONSE_ERR, 1); @@ -5067,6 +5398,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_LNK_INVALID_COLLAPSED_RESPONSE_ERR, "Invalid Collapsed Response Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _INVALID_COLLAPSED_RESPONSE_ERR, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_RX_INVALID_COLLAPSED_RESPONSE_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } NVSWITCH_UNHANDLED_CHECK(device, unhandled); @@ -5106,12 +5443,17 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_1_lr10 { NvU32 pending, bit, unhandled; NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + INFOROM_NVLINK_ERROR_EVENT error_event = { 0 }; + NvU32 injected; report.raw_pending = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_STATUS_1); report.raw_enable = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_FATAL_REPORT_EN_1); report.mask = report.raw_enable; pending = report.raw_pending & report.mask; + error_event.nvliptInstance = (NvU8) nvlipt_instance; + error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LR10(link); + if (pending == 0) { return -NVL_NOT_FOUND; @@ -5119,12 +5461,19 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_1_lr10 unhandled = pending; report.raw_first = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_FIRST_1); + injected = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_REPORT_INJECT_1); bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_1, _RXHDROVFERR, 1); if (nvswitch_test_flags(pending, bit)) { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXHDROVFERR, "RX HDR OVF Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_1, _RXHDROVFERR, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_RX_HDR_OVERFLOW_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_1, _RXDATAOVFERR, 1); @@ -5132,6 +5481,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_1_lr10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXDATAOVFERR, "RX Data OVF Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_1, _RXDATAOVFERR, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_RX_DATA_OVERFLOW_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_1, _STOMPDETERR, 1); @@ -5139,6 +5494,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_1_lr10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_STOMPDETERR, "Stomp Det Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_1, _STOMPDETERR, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_RX_STOMP_DETECTED_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_1, _RXPOISONERR, 1); @@ -5253,6 +5614,8 @@ _nvswitch_service_nvlipt_common_fatal_lr10 NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; NvU32 pending, bit, contain, unhandled; NvU32 link, local_link_idx; + INFOROM_NVLINK_ERROR_EVENT error_event = { 0 }; + NvU32 injected; report.raw_pending = NVSWITCH_NVLIPT_RD32_LR10(device, instance, _NVLIPT_COMMON, _ERR_STATUS_0); report.raw_enable = NVSWITCH_NVLIPT_RD32_LR10(device, instance, _NVLIPT_COMMON, _ERR_FATAL_REPORT_EN_0); @@ -5267,9 +5630,12 @@ _nvswitch_service_nvlipt_common_fatal_lr10 return -NVL_NOT_FOUND; } + error_event.nvliptInstance = (NvU8) instance; + unhandled = pending; report.raw_first = NVSWITCH_NVLIPT_RD32_LR10(device, instance, _NVLIPT_COMMON, _ERR_FIRST_0); contain = NVSWITCH_NVLIPT_RD32_LR10(device, instance, _NVLIPT_COMMON, _ERR_CONTAIN_EN_0); + injected = NVSWITCH_NVLIPT_RD32_LR10(device, instance, _NVLIPT_COMMON, _ERR_REPORT_INJECT_0); bit = DRF_NUM(_NVLIPT_COMMON, _ERR_STATUS_0, _CLKCTL_ILLEGAL_REQUEST, 1); if (nvswitch_test_flags(pending, bit)) @@ -5284,6 +5650,12 @@ _nvswitch_service_nvlipt_common_fatal_lr10 } nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLIPT_COMMON, _ERR_REPORT_INJECT_0, _CLKCTL_ILLEGAL_REQUEST, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_NVLIPT_CLKCTL_ILLEGAL_REQUEST_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLIPT_COMMON, _ERR_STATUS_0, _RSTSEQ_PLL_TIMEOUT, 1); @@ -5299,6 +5671,12 @@ _nvswitch_service_nvlipt_common_fatal_lr10 } nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLIPT_COMMON, _ERR_REPORT_INJECT_0, _RSTSEQ_PLL_TIMEOUT, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_NVLIPT_RSTSEQ_PLL_TIMEOUT_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLIPT_COMMON, _ERR_STATUS_0, _RSTSEQ_PHYARB_TIMEOUT, 1); @@ -5314,6 +5692,12 @@ _nvswitch_service_nvlipt_common_fatal_lr10 } nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLIPT_COMMON, _ERR_REPORT_INJECT_0, _RSTSEQ_PHYARB_TIMEOUT, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_NVLIPT_RSTSEQ_PHYARB_TIMEOUT_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } NVSWITCH_UNHANDLED_CHECK(device, unhandled); @@ -5360,6 +5744,8 @@ _nvswitch_service_nvlipt_lnk_fatal_lr10 { NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; NvU32 pending, bit, unhandled; + INFOROM_NVLINK_ERROR_EVENT error_event = { 0 }; + NvU32 injected; report.raw_pending = NVSWITCH_LINK_RD32_LR10(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_STATUS_0); report.raw_enable = NVSWITCH_LINK_RD32_LR10(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_FATAL_REPORT_EN_0); @@ -5371,14 +5757,24 @@ _nvswitch_service_nvlipt_lnk_fatal_lr10 return -NVL_NOT_FOUND; } + error_event.nvliptInstance = (NvU8) nvlipt_instance; + error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LR10(link); + unhandled = pending; report.raw_first = NVSWITCH_LINK_RD32_LR10(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_FIRST_0); + injected = NVSWITCH_LINK_RD32_LR10(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_REPORT_INJECT_0); bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _SLEEPWHILEACTIVELINK, 1); if (nvswitch_test_flags(pending, bit)) { NVSWITCH_REPORT_FATAL(_HW_NVLIPT_LNK_SLEEPWHILEACTIVELINK, "No non-empty link is detected", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLIPT_LNK, _ERR_REPORT_INJECT_0, _SLEEPWHILEACTIVELINK, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_NVLIPT_SLEEP_WHILE_ACTIVE_LINK_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _RSTSEQ_PHYCTL_TIMEOUT, 1); @@ -5386,6 +5782,12 @@ _nvswitch_service_nvlipt_lnk_fatal_lr10 { NVSWITCH_REPORT_FATAL(_HW_NVLIPT_LNK_RSTSEQ_PHYCTL_TIMEOUT, "Reset sequencer timed out waiting for a handshake from PHYCTL", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLIPT_LNK, _ERR_REPORT_INJECT_0, _RSTSEQ_PHYCTL_TIMEOUT, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_NVLIPT_RSTSEQ_PHYCTL_TIMEOUT_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _RSTSEQ_CLKCTL_TIMEOUT, 1); @@ -5393,6 +5795,12 @@ _nvswitch_service_nvlipt_lnk_fatal_lr10 { NVSWITCH_REPORT_FATAL(_HW_NVLIPT_LNK_RSTSEQ_CLKCTL_TIMEOUT, "Reset sequencer timed out waiting for a handshake from CLKCTL", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLIPT_LNK, _ERR_REPORT_INJECT_0, _RSTSEQ_CLKCTL_TIMEOUT, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_NVLIPT_RSTSEQ_CLKCTL_TIMEOUT_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } NVSWITCH_UNHANDLED_CHECK(device, unhandled); diff --git a/src/common/nvswitch/kernel/lr10/link_lr10.c b/src/common/nvswitch/kernel/lr10/link_lr10.c index bc06d2fa0..f0c053cad 100644 --- a/src/common/nvswitch/kernel/lr10/link_lr10.c +++ b/src/common/nvswitch/kernel/lr10/link_lr10.c @@ -872,7 +872,7 @@ nvswitch_corelib_set_dl_link_mode_lr10 NVSWITCH_PRINT(device, ERROR, "%s: link #%d is still in reset, cannot change link state\n", __FUNCTION__, link->linkNumber); - return -NVL_ERR_INVALID_STATE; + return NVL_ERR_INVALID_STATE; } val = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, NVLDL, _NVLDL_TOP, _LINK_STATE); diff --git a/src/common/nvswitch/kernel/lr10/lr10.c b/src/common/nvswitch/kernel/lr10/lr10.c index 0dc9ae9c9..4349f7185 100644 --- a/src/common/nvswitch/kernel/lr10/lr10.c +++ b/src/common/nvswitch/kernel/lr10/lr10.c @@ -6380,6 +6380,15 @@ nvswitch_get_num_links_lr10 return num_links; } +static NvU8 +nvswitch_get_num_links_per_nvlipt_lr10 +( + nvswitch_device *device +) +{ + return NVSWITCH_LINKS_PER_NVLIPT; +} + NvBool nvswitch_is_link_valid_lr10 ( @@ -6403,22 +6412,8 @@ nvswitch_ctrl_get_fom_values_lr10 { NvlStatus status; NvU32 statData; - nvlink_link *link; - link = nvswitch_get_link(device, p->linkId); - if (link == NULL) - { - NVSWITCH_PRINT(device, ERROR, "%s: link #%d invalid\n", - __FUNCTION__, p->linkId); - return -NVL_BAD_ARGS; - } - - if (nvswitch_is_link_in_reset(device, link)) - { - NVSWITCH_PRINT(device, ERROR, "%s: link #%d is in reset\n", - __FUNCTION__, p->linkId); - return -NVL_ERR_INVALID_STATE; - } + NVSWITCH_ASSERT(p->linkId < nvswitch_get_num_links(device)); status = nvswitch_minion_get_dl_status(device, p->linkId, NV_NVLSTAT_TR16, 0, &statData); diff --git a/src/common/nvswitch/kernel/ls10/inforom_ls10.c b/src/common/nvswitch/kernel/ls10/inforom_ls10.c index b23bde0c3..588500af2 100644 --- a/src/common/nvswitch/kernel/ls10/inforom_ls10.c +++ b/src/common/nvswitch/kernel/ls10/inforom_ls10.c @@ -30,6 +30,8 @@ #include "rmsoecmdif.h" #include "flcn/flcn_nvswitch.h" #include "rmflcncmdif_nvswitch.h" +#include "inforom/inforom_nvl_v3_nvswitch.h" +#include "inforom/inforom_nvl_v4_nvswitch.h" NvlStatus nvswitch_inforom_nvl_log_error_event_ls10 @@ -40,7 +42,252 @@ nvswitch_inforom_nvl_log_error_event_ls10 NvBool *bDirty ) { - return -NVL_ERR_NOT_IMPLEMENTED; + NvlStatus status; + INFOROM_NVL_OBJECT_V4S *pNvlObject = &((PINFOROM_NVL_OBJECT)pNvlGeneric)->v4s; + INFOROM_NVLINK_ERROR_EVENT *pErrorEvent = (INFOROM_NVLINK_ERROR_EVENT *)pNvlErrorEvent; + INFOROM_NVL_OBJECT_V3_ERROR_ENTRY *pErrorEntry; + NvU32 i; + NvU32 sec; + NvU8 header = 0; + NvU16 metadata = 0; + NvU8 errorSubtype; + NvU64 accumTotalCount; + INFOROM_NVL_ERROR_BLOCK_TYPE blockType; + + if (pErrorEvent->nvliptInstance > INFOROM_NVL_OBJECT_V3_NVLIPT_INSTANCE_MAX) + { + NVSWITCH_PRINT(device, ERROR, + "object cannot log data for more than %u NVLIPTs (NVLIPT = %u requested)\n", + INFOROM_NVL_OBJECT_V3_NVLIPT_INSTANCE_MAX, pErrorEvent->nvliptInstance); + return -NVL_BAD_ARGS; + } + + if (pErrorEvent->localLinkIdx > INFOROM_NVL_OBJECT_V3_BLOCK_ID_MAX) + { + NVSWITCH_PRINT(device, ERROR, + "object cannot log data for more than %u internal links (internal link = %u requested)\n", + INFOROM_NVL_OBJECT_V3_BLOCK_ID_MAX, pErrorEvent->localLinkIdx); + return -NVL_BAD_ARGS; + } + + sec = (NvU32) (nvswitch_os_get_platform_time_epoch() / NVSWITCH_INTERVAL_1SEC_IN_NS); + + status = inforom_nvl_v3_map_error(pErrorEvent->error, &header, &metadata, + &errorSubtype, &blockType); + if (status != NVL_SUCCESS) + { + return status; + } + + metadata = FLD_SET_DRF_NUM(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, + _NVLIPT_INSTANCE_ID, pErrorEvent->nvliptInstance, metadata); + if (blockType == INFOROM_NVL_ERROR_BLOCK_TYPE_DL) + { + metadata = FLD_SET_DRF_NUM(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, + NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_DL(pErrorEvent->localLinkIdx), + metadata); + } + else if (blockType == INFOROM_NVL_ERROR_BLOCK_TYPE_TLC) + { + metadata = FLD_SET_DRF_NUM(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, + NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_TLC(pErrorEvent->localLinkIdx), + metadata); + } + else if (blockType == INFOROM_NVL_ERROR_BLOCK_TYPE_NVLIPT) + { + metadata = FLD_SET_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, + _BLOCK_ID, _NVLIPT, metadata); + status = inforom_nvl_v3_encode_nvlipt_error_subtype(pErrorEvent->localLinkIdx, + &errorSubtype); + if (status != NVL_SUCCESS) + { + return status; + } + } + + for (i = 0; i < INFOROM_NVL_OBJECT_V4S_NUM_ERROR_ENTRIES; i++) + { + pErrorEntry = &pNvlObject->errorLog[i]; + + if ((pErrorEntry->header == INFOROM_NVL_ERROR_TYPE_INVALID) || + ((pErrorEntry->metadata == metadata) && + (pErrorEntry->errorSubtype == errorSubtype))) + { + break; + } + } + + if (i >= INFOROM_NVL_OBJECT_V4S_NUM_ERROR_ENTRIES) + { + NVSWITCH_PRINT(device, ERROR, "%s: NVL error log is full -- unable to log error\n", + __FUNCTION__); + return -NVL_ERR_INVALID_STATE; + } + + if (pErrorEntry->header == INFOROM_NVL_ERROR_TYPE_INVALID) + { + pErrorEntry->header = header; + pErrorEntry->metadata = metadata; + pErrorEntry->errorSubtype = errorSubtype; + } + + if (pErrorEntry->header == INFOROM_NVL_ERROR_TYPE_ACCUM) + { + accumTotalCount = NvU64_ALIGN32_VAL(&pErrorEntry->data.accum.totalCount); + if (accumTotalCount != NV_U64_MAX) + { + if (pErrorEvent->count > NV_U64_MAX - accumTotalCount) + { + accumTotalCount = NV_U64_MAX; + } + else + { + accumTotalCount += pErrorEvent->count; + } + + NvU64_ALIGN32_PACK(&pErrorEntry->data.accum.totalCount, &accumTotalCount); + if (sec < pErrorEntry->data.accum.lastUpdated) + { + NVSWITCH_PRINT(device, ERROR, + "%s: System clock reporting earlier time than error timestamp\n", + __FUNCTION__); + } + pErrorEntry->data.accum.lastUpdated = sec; + *bDirty = NV_TRUE; + } + } + else if (pErrorEntry->header == INFOROM_NVL_ERROR_TYPE_COUNT) + { + if (pErrorEntry->data.event.totalCount != NV_U32_MAX) + { + pErrorEntry->data.event.totalCount++; + if (sec < pErrorEntry->data.event.lastError) + { + NVSWITCH_PRINT(device, ERROR, + "%s: System clock reporting earlier time than error timestamp\n", + __FUNCTION__); + } + else + { + pErrorEntry->data.event.avgEventDelta = + (pErrorEntry->data.event.avgEventDelta + sec - + pErrorEntry->data.event.lastError) >> 1; + } + pErrorEntry->data.event.lastError = sec; + *bDirty = NV_TRUE; + } + } + else + { + return -NVL_ERR_INVALID_STATE; + } + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_inforom_nvl_get_max_correctable_error_rate_ls10 +( + nvswitch_device *device, + NVSWITCH_GET_NVLINK_MAX_CORRECTABLE_ERROR_RATES_PARAMS *params +) +{ + + struct inforom *pInforom = device->pInforom; + INFOROM_NVLINK_STATE *pNvlinkState; + NvU8 linkID = params->linkId; + + if (linkID >= NVSWITCH_NUM_LINKS_LS10) + { + return -NVL_BAD_ARGS; + } + + if (pInforom == NULL) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + pNvlinkState = pInforom->pNvlinkState; + if (pNvlinkState == NULL) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + nvswitch_os_memset(params, 0, sizeof(NVSWITCH_GET_NVLINK_MAX_CORRECTABLE_ERROR_RATES_PARAMS)); + params->linkId = linkID; + + nvswitch_os_memcpy(¶ms->dailyMaxCorrectableErrorRates, &pNvlinkState->pNvl->v4s.maxCorrectableErrorRates.dailyMaxCorrectableErrorRates[0][linkID], + sizeof(params->dailyMaxCorrectableErrorRates)); + + nvswitch_os_memcpy(¶ms->monthlyMaxCorrectableErrorRates, &pNvlinkState->pNvl->v4s.maxCorrectableErrorRates.monthlyMaxCorrectableErrorRates[0][linkID], + sizeof(params->monthlyMaxCorrectableErrorRates)); + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_inforom_nvl_get_errors_ls10 +( + nvswitch_device *device, + NVSWITCH_GET_NVLINK_ERROR_COUNTS_PARAMS *params +) +{ + struct inforom *pInforom = device->pInforom; + INFOROM_NVLINK_STATE *pNvlinkState; + NvU32 maxReadSize = sizeof(params->errorLog)/sizeof(NVSWITCH_NVLINK_ERROR_ENTRY); + NvU32 errorLeftCount = 0, errorReadCount = 0, errIndx = 0; + NvU32 errorStart = params->errorIndex; + + if (pInforom == NULL) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + pNvlinkState = pInforom->pNvlinkState; + if (pNvlinkState == NULL) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + if (errorStart >= INFOROM_NVL_OBJECT_V4S_NUM_ERROR_ENTRIES) + { + return -NVL_BAD_ARGS; + } + + nvswitch_os_memset(params->errorLog, 0, sizeof(params->errorLog)); + + while (((errorStart + errorLeftCount) < INFOROM_NVL_OBJECT_V4S_NUM_ERROR_ENTRIES) && + (pNvlinkState->pNvl->v4s.errorLog[errorStart + errorLeftCount].header != INFOROM_NVL_ERROR_TYPE_INVALID)) + { + errorLeftCount++; + } + + if (errorLeftCount > maxReadSize) + { + errorReadCount = maxReadSize; + } + else + { + errorReadCount = errorLeftCount; + } + + params->errorIndex = errorStart + errorReadCount; + params->errorCount = errorReadCount; + + if (errorReadCount > 0) + { + for (errIndx = 0; errIndx < errorReadCount; errIndx++) + { + if (inforom_nvl_v3_map_error_to_userspace_error(device, + &pNvlinkState->pNvl->v4s.errorLog[errorStart+errIndx], + ¶ms->errorLog[errIndx]) != NVL_SUCCESS) + { + return -NVL_ERR_NOT_SUPPORTED; + } + } + } + + return NVL_SUCCESS; } NvlStatus nvswitch_inforom_nvl_update_link_correctable_error_info_ls10 @@ -55,7 +302,258 @@ NvlStatus nvswitch_inforom_nvl_update_link_correctable_error_info_ls10 NvBool *bDirty ) { - return -NVL_ERR_NOT_IMPLEMENTED; + INFOROM_NVL_OBJECT_V4S *pNvlObject = &((PINFOROM_NVL_OBJECT)pNvlGeneric)->v4s; + INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V4S *pState = + &((INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE *)pData)->v4s; + INFOROM_NVLINK_CORRECTABLE_ERROR_COUNTS *pErrorCounts = + (INFOROM_NVLINK_CORRECTABLE_ERROR_COUNTS *)pNvlErrorCounts; + + NvU32 i; + NvU32 sec; + NvU32 day, month, currentEntryDay, currentEntryMonth; + INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE *pErrorRate; + INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE *pOldestErrorRate = NULL; + INFOROM_NVL_OBJECT_V4S_MAX_CORRECTABLE_ERROR_RATES *pCorrErrorRates; + NvBool bUpdated = NV_FALSE; + INFOROM_NVLINK_ERROR_EVENT errorEvent; + NvU32 currentFlitCrcRate; + NvU32 *pCurrentLaneCrcRates; + + if (bDirty == NULL) + { + return -NVL_BAD_ARGS; + } + + *bDirty = NV_FALSE; + + if (linkId >= INFOROM_NVL_OBJECT_V4S_NUM_LINKS) + { + NVSWITCH_PRINT(device, ERROR, + "object does not store data for more than %u links (linkId = %u requested)\n", + INFOROM_NVL_OBJECT_V4S_NUM_LINKS, linkId); + return -NVL_BAD_ARGS; + } + + if (nvliptInstance > INFOROM_NVL_OBJECT_V3_NVLIPT_INSTANCE_MAX) + { + NVSWITCH_PRINT(device, ERROR, + "object cannot log data for more than %u NVLIPTs (NVLIPT = %u requested)\n", + INFOROM_NVL_OBJECT_V3_NVLIPT_INSTANCE_MAX, nvliptInstance); + return -NVL_BAD_ARGS; + } + + if (localLinkIdx > INFOROM_NVL_OBJECT_V3_BLOCK_ID_MAX) + { + NVSWITCH_PRINT(device, ERROR, + "object cannot log data for more than %u internal links (internal link = %u requested)\n", + INFOROM_NVL_OBJECT_V3_BLOCK_ID_MAX, localLinkIdx); + return -NVL_BAD_ARGS; + } + + sec = (NvU32) (nvswitch_os_get_platform_time_epoch() / NVSWITCH_INTERVAL_1SEC_IN_NS); + inforom_nvl_v3_seconds_to_day_and_month(sec, &day, &month); + + inforom_nvl_v4_update_correctable_error_rates(pState, linkId, pErrorCounts); + currentFlitCrcRate = pState->errorsPerMinute[linkId].flitCrc; + pCurrentLaneCrcRates = pState->errorsPerMinute[linkId].laneCrc; + pCorrErrorRates = &pNvlObject->maxCorrectableErrorRates; + + for (i = 0; i < NV_ARRAY_ELEMENTS(pCorrErrorRates->dailyMaxCorrectableErrorRates); i++) + { + pErrorRate = &pCorrErrorRates->dailyMaxCorrectableErrorRates[i][linkId]; + inforom_nvl_v3_seconds_to_day_and_month(pErrorRate->lastUpdated, ¤tEntryDay, + ¤tEntryMonth); + + if ((pErrorRate->lastUpdated == 0) || (currentEntryDay == day)) + { + if (inforom_nvl_v3_should_replace_error_rate_entry(pErrorRate, + currentFlitCrcRate, + pCurrentLaneCrcRates)) + { + inforom_nvl_v3_update_error_rate_entry(pErrorRate, sec, + currentFlitCrcRate, + pCurrentLaneCrcRates); + bUpdated = NV_TRUE; + } + pOldestErrorRate = NULL; + break; + } + else if ((pOldestErrorRate == NULL) || + (pErrorRate->lastUpdated < pOldestErrorRate->lastUpdated)) + { + pOldestErrorRate = pErrorRate; + } + } + + if (pOldestErrorRate != NULL) + { + inforom_nvl_v3_update_error_rate_entry(pOldestErrorRate, sec, + currentFlitCrcRate, + pCurrentLaneCrcRates); + bUpdated = NV_TRUE; + } + + for (i = 0; i < NV_ARRAY_ELEMENTS(pCorrErrorRates->monthlyMaxCorrectableErrorRates); i++) + { + pErrorRate = &pCorrErrorRates->monthlyMaxCorrectableErrorRates[i][linkId]; + inforom_nvl_v3_seconds_to_day_and_month(pErrorRate->lastUpdated, ¤tEntryDay, + ¤tEntryMonth); + + if ((pErrorRate->lastUpdated == 0) || (currentEntryMonth == month)) + { + if (inforom_nvl_v3_should_replace_error_rate_entry(pErrorRate, + currentFlitCrcRate, + pCurrentLaneCrcRates)) + { + inforom_nvl_v3_update_error_rate_entry(pErrorRate, sec, + currentFlitCrcRate, + pCurrentLaneCrcRates); + bUpdated = NV_TRUE; + } + pOldestErrorRate = NULL; + break; + } + else if ((pOldestErrorRate == NULL) || + (pErrorRate->lastUpdated < pOldestErrorRate->lastUpdated)) + { + pOldestErrorRate = pErrorRate; + } + } + + if (pOldestErrorRate != NULL) + { + inforom_nvl_v3_update_error_rate_entry(pOldestErrorRate, sec, + currentFlitCrcRate, + pCurrentLaneCrcRates); + bUpdated = NV_TRUE; + } + + *bDirty = bUpdated; + + // Update aggregate error counts for each correctable error + + errorEvent.nvliptInstance = nvliptInstance; + errorEvent.localLinkIdx = localLinkIdx; + + if (pErrorCounts->flitCrc > 0) + { + errorEvent.error = INFOROM_NVLINK_DL_RX_FLIT_CRC_CORR; + errorEvent.count = pErrorCounts->flitCrc; + nvswitch_inforom_nvl_log_error_event_ls10(device, + pNvlGeneric, &errorEvent, &bUpdated); + *bDirty |= bUpdated; + } + + if (pErrorCounts->rxLinkReplay > 0) + { + errorEvent.error = INFOROM_NVLINK_DL_RX_LINK_REPLAY_EVENTS_CORR; + errorEvent.count = pErrorCounts->rxLinkReplay; + bUpdated = NV_FALSE; + nvswitch_inforom_nvl_log_error_event_ls10(device, + pNvlGeneric, &errorEvent, &bUpdated); + *bDirty |= bUpdated; + } + + if (pErrorCounts->txLinkReplay > 0) + { + errorEvent.error = INFOROM_NVLINK_DL_TX_LINK_REPLAY_EVENTS_CORR; + errorEvent.count = pErrorCounts->txLinkReplay; + bUpdated = NV_FALSE; + nvswitch_inforom_nvl_log_error_event_ls10(device, + pNvlGeneric, &errorEvent, &bUpdated); + *bDirty |= bUpdated; + } + + if (pErrorCounts->linkRecovery > 0) + { + errorEvent.error = INFOROM_NVLINK_DL_LINK_RECOVERY_EVENTS_CORR; + errorEvent.count = pErrorCounts->linkRecovery; + bUpdated = NV_FALSE; + nvswitch_inforom_nvl_log_error_event_ls10(device, + pNvlGeneric, &errorEvent, &bUpdated); + *bDirty |= bUpdated; + } + + for (i = 0; i < 4; i++) + { + if (pErrorCounts->laneCrc[i] == 0) + { + continue; + } + + errorEvent.error = INFOROM_NVLINK_DL_RX_LANE0_CRC_CORR + i; + errorEvent.count = pErrorCounts->laneCrc[i]; + bUpdated = NV_FALSE; + nvswitch_inforom_nvl_log_error_event_ls10(device, + pNvlGeneric, &errorEvent, &bUpdated); + *bDirty |= bUpdated; + } + + return NVL_SUCCESS; +} + +NvlStatus nvswitch_inforom_nvl_setL1Threshold_ls10 +( + nvswitch_device *device, + void *pNvlGeneric, + NvU32 word1, + NvU32 word2 +) +{ + INFOROM_NVL_OBJECT_V4S *pNvlObject = &((PINFOROM_NVL_OBJECT)pNvlGeneric)->v4s; + + pNvlObject->l1ThresholdData.word1 = word1; + pNvlObject->l1ThresholdData.word2 = word2; + + return NVL_SUCCESS; +} + +NvlStatus nvswitch_inforom_nvl_getL1Threshold_ls10 +( + nvswitch_device *device, + void *pNvlGeneric, + NvU32 *word1, + NvU32 *word2 +) +{ + INFOROM_NVL_OBJECT_V4S *pNvlObject = &((PINFOROM_NVL_OBJECT)pNvlGeneric)->v4s; + + *word1 = pNvlObject->l1ThresholdData.word1; + *word2 = pNvlObject->l1ThresholdData.word2; + + return NVL_SUCCESS; +} + +NvlStatus nvswitch_inforom_nvl_setup_nvlink_state_ls10 +( + nvswitch_device *device, + INFOROM_NVLINK_STATE *pNvlinkState, + NvU8 version +) +{ + if (version != 4) + { + NVSWITCH_PRINT(device, WARN, "NVL v%u not supported\n", version); + return -NVL_ERR_NOT_SUPPORTED; + } + + pNvlinkState->pFmt = INFOROM_NVL_OBJECT_V4S_FMT; + pNvlinkState->pPackedObject = nvswitch_os_malloc(INFOROM_NVL_OBJECT_V4S_PACKED_SIZE); + if (pNvlinkState->pPackedObject == NULL) + { + return -NVL_NO_MEM; + } + + pNvlinkState->pNvl = nvswitch_os_malloc(sizeof(INFOROM_NVL_OBJECT)); + if (pNvlinkState->pNvl == NULL) + { + nvswitch_os_free(pNvlinkState->pPackedObject); + return -NVL_NO_MEM; + } + + pNvlinkState->bDisableCorrectableErrorLogging = NV_FALSE; + + return NVL_SUCCESS; } NvlStatus @@ -271,5 +769,97 @@ nvswitch_bbx_get_sxid_ls10 NVSWITCH_GET_SXIDS_PARAMS *params ) { - return -NVL_ERR_NOT_SUPPORTED; + NvlStatus status; + void *pDmaBuf; + NvU64 dmaHandle; + FLCN *pFlcn; + RM_FLCN_CMD_SOE bbxCmd; + NvU32 cmdSeqDesc; + NVSWITCH_TIMEOUT timeout; + NvU32 transferSize; + RM_SOE_BBX_GET_SXID_DATA bbxSxidData; + NvU32 sxidIdx; + + if (!nvswitch_is_inforom_supported_ls10(device)) + { + NVSWITCH_PRINT(device, INFO, "%s: InfoROM is not supported\n", __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + if (params == NULL) + { + return -NVL_BAD_ARGS; + } + + transferSize = sizeof(bbxSxidData); + status = nvswitch_os_alloc_contig_memory(device->os_handle, &pDmaBuf, transferSize, + (device->dma_addr_width == 32)); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to allocate contig memory. rc:%d\n", __FUNCTION__, status); + return status; + } + + status = nvswitch_os_map_dma_region(device->os_handle, pDmaBuf, &dmaHandle, + transferSize, NVSWITCH_DMA_DIR_TO_SYSMEM); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to map DMA region. rc:%d\n", __FUNCTION__, status); + goto nvswitch_bbx_get_sxid_ls10_free_and_exit; + } + + nvswitch_os_memset(pDmaBuf, 0, transferSize); + + pFlcn = device->pSoe->pFlcn; + nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout); + + nvswitch_os_memset(&bbxCmd, 0, sizeof(bbxCmd)); + bbxCmd.hdr.unitId = RM_SOE_UNIT_IFR; + bbxCmd.hdr.size = sizeof(bbxCmd); + bbxCmd.cmd.ifr.cmdType = RM_SOE_IFR_BBX_SXID_GET; + bbxCmd.cmd.ifr.bbxSxidGet.sizeInBytes = transferSize; + RM_FLCN_U64_PACK(&bbxCmd.cmd.ifr.bbxSxidGet.dmaHandle, &dmaHandle); + + status = flcnQueueCmdPostBlocking(device, pFlcn, + (PRM_FLCN_CMD)&bbxCmd, + NULL, // pMsg + NULL, // pPayload + SOE_RM_CMDQ_LOG_ID, + &cmdSeqDesc, + &timeout); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, "%s: BBX cmd %d failed. rc:%d\n", + __FUNCTION__, bbxCmd.cmd.ifr.cmdType, status); + goto nvswitch_bbx_get_sxid_ls10_unmap_and_exit; + } + + status = nvswitch_os_sync_dma_region_for_cpu(device->os_handle, dmaHandle, + transferSize, + NVSWITCH_DMA_DIR_TO_SYSMEM); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to sync DMA region. rc:%d\n", __FUNCTION__, status); + goto nvswitch_bbx_get_sxid_ls10_unmap_and_exit; + } + + nvswitch_os_memcpy((NvU8 *)&bbxSxidData, (NvU8 *)pDmaBuf, sizeof(bbxSxidData)); + + // Copy out SXIDs + params->sxidCount = bbxSxidData.sxidCount; + for (sxidIdx = 0; sxidIdx < INFOROM_BBX_OBJ_XID_ENTRIES; sxidIdx++) + { + params->sxidFirst[sxidIdx].sxid = bbxSxidData.sxidFirst[sxidIdx].sxid; + params->sxidFirst[sxidIdx].timestamp = bbxSxidData.sxidFirst[sxidIdx].timestamp; + params->sxidLast[sxidIdx].sxid = bbxSxidData.sxidLast[sxidIdx].sxid; + params->sxidLast[sxidIdx].timestamp = bbxSxidData.sxidLast[sxidIdx].timestamp; + } + +nvswitch_bbx_get_sxid_ls10_unmap_and_exit: + nvswitch_os_unmap_dma_region(device->os_handle, pDmaBuf, dmaHandle, + transferSize, NVSWITCH_DMA_DIR_FROM_SYSMEM); +nvswitch_bbx_get_sxid_ls10_free_and_exit: + nvswitch_os_free_contig_memory(device->os_handle, pDmaBuf, transferSize); + + return status; } diff --git a/src/common/nvswitch/kernel/ls10/intr_ls10.c b/src/common/nvswitch/kernel/ls10/intr_ls10.c index b9480c851..3f99ba5f6 100644 --- a/src/common/nvswitch/kernel/ls10/intr_ls10.c +++ b/src/common/nvswitch/kernel/ls10/intr_ls10.c @@ -113,7 +113,7 @@ _nvswitch_initialize_minion_interrupts intrEn = FLD_SET_DRF_NUM(_MINION, _MINION_INTR_STALL_EN, _LINK, localDiscoveredLinks, intrEn); - { + { // Disable interrupts only if explicitly requested to. Default to enable. if (device->regkeys.minion_intr != NV_SWITCH_REGKEY_MINION_INTERRUPTS_DISABLE) { @@ -358,11 +358,11 @@ _nvswitch_initialize_egress_interrupts DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_1, _MCRSP_RAM_HDR_ECC_DBE_ERR, _ENABLE); chip_device->intr_mask.egress[1].nonfatal = - DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR, _ENABLE) | - DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCRSPCTRLSTORE_ECC_LIMIT_ERR, _ENABLE) | - DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _RBCTRLSTORE_ECC_LIMIT_ERR, _ENABLE) | - DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREDSGT_ECC_LIMIT_ERR, _ENABLE) | - DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREDBUF_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCRSPCTRLSTORE_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _RBCTRLSTORE_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREDSGT_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREDBUF_ECC_LIMIT_ERR, _ENABLE) | DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCRSP_RAM_HDR_ECC_LIMIT_ERR, _ENABLE) | DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _NXBAR_REDUCTION_HDR_ECC_DBE_ERR, _ENABLE) | DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _NXBAR_REDUCTION_HDR_PARITY_ERR, _ENABLE) | @@ -4360,12 +4360,16 @@ _nvswitch_service_nvltlc_tx_sys_fatal_ls10 { NvU32 pending, bit, unhandled; NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + INFOROM_NVLINK_ERROR_EVENT error_event = { 0 }; report.raw_pending = NVSWITCH_LINK_RD32_LS10(device, link, NVLTLC, _NVLTLC_TX_SYS, _ERR_STATUS_0); report.raw_enable = NVSWITCH_LINK_RD32_LS10(device, link, NVLTLC, _NVLTLC_TX_SYS, _ERR_FATAL_REPORT_EN_0); report.mask = report.raw_enable; pending = report.raw_pending & report.mask; + error_event.nvliptInstance = (NvU8) nvlipt_instance; + error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LS10(link); + if (pending == 0) { return -NVL_NOT_FOUND; @@ -4379,6 +4383,10 @@ _nvswitch_service_nvltlc_tx_sys_fatal_ls10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_TX_SYS_NCISOC_PARITY_ERR, "NCISOC Parity Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_TLC_TX_NCISOC_PARITY_ERR_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_TX_SYS, _ERR_STATUS_0, _NCISOC_HDR_ECC_DBE_ERR, 1); @@ -4386,6 +4394,10 @@ _nvswitch_service_nvltlc_tx_sys_fatal_ls10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_TX_SYS_NCISOC_HDR_ECC_DBE_ERR, "NCISOC HDR ECC DBE Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_TLC_TX_NCISOC_HDR_ECC_DBE_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_TX_SYS, _ERR_STATUS_0, _NCISOC_DAT_ECC_DBE_ERR, 1); @@ -4468,12 +4480,16 @@ _nvswitch_service_nvltlc_rx_sys_fatal_ls10 { NvU32 pending, bit, unhandled; NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + INFOROM_NVLINK_ERROR_EVENT error_event = { 0 }; report.raw_pending = NVSWITCH_LINK_RD32_LS10(device, link, NVLTLC, _NVLTLC_RX_SYS, _ERR_STATUS_0); report.raw_enable = NVSWITCH_LINK_RD32_LS10(device, link, NVLTLC, _NVLTLC_RX_SYS, _ERR_FATAL_REPORT_EN_0); report.mask = report.raw_enable; pending = report.raw_pending & report.mask; + error_event.nvliptInstance = (NvU8) nvlipt_instance; + error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LS10(link); + if (pending == 0) { return -NVL_NOT_FOUND; @@ -4494,6 +4510,11 @@ _nvswitch_service_nvltlc_rx_sys_fatal_ls10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_SYS_HDR_RAM_ECC_DBE_ERR, "HDR RAM ECC DBE Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + { + // TODO 3014908 log these in the NVL object until we have ECC object support + error_event.error = INFOROM_NVLINK_TLC_RX_HDR_RAM_ECC_DBE_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_SYS, _ERR_STATUS_0, _HDR_RAM_ECC_LIMIT_ERR, 1); @@ -4508,6 +4529,11 @@ _nvswitch_service_nvltlc_rx_sys_fatal_ls10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_SYS_DAT0_RAM_ECC_DBE_ERR, "DAT0 RAM ECC DBE Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + { + // TODO 3014908 log these in the NVL object until we have ECC object support + error_event.error = INFOROM_NVLINK_TLC_RX_DAT0_RAM_ECC_DBE_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_SYS, _ERR_STATUS_0, _DAT0_RAM_ECC_LIMIT_ERR, 1); @@ -4522,6 +4548,11 @@ _nvswitch_service_nvltlc_rx_sys_fatal_ls10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_SYS_DAT1_RAM_ECC_DBE_ERR, "DAT1 RAM ECC DBE Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + { + // TODO 3014908 log these in the NVL object until we have ECC object support + error_event.error = INFOROM_NVLINK_TLC_RX_DAT1_RAM_ECC_DBE_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_SYS, _ERR_STATUS_0, _DAT1_RAM_ECC_LIMIT_ERR, 1); @@ -4569,12 +4600,16 @@ _nvswitch_service_nvltlc_tx_lnk_fatal_0_ls10 { NvU32 pending, bit, unhandled; NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + INFOROM_NVLINK_ERROR_EVENT error_event = { 0 }; report.raw_pending = NVSWITCH_LINK_RD32_LS10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_STATUS_0); report.raw_enable = NVSWITCH_LINK_RD32_LS10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_FATAL_REPORT_EN_0); report.mask = report.raw_enable; pending = report.raw_pending & report.mask; + error_event.nvliptInstance = (NvU8) nvlipt_instance; + error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LS10(link); + if (pending == 0) { return -NVL_NOT_FOUND; @@ -4588,6 +4623,10 @@ _nvswitch_service_nvltlc_tx_lnk_fatal_0_ls10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_TXDLCREDITPARITYERR, "TX DL Credit Parity Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_TLC_TX_DL_CREDIT_PARITY_ERR_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_0, _CREQ_RAM_HDR_ECC_DBE_ERR, 1); @@ -4623,6 +4662,11 @@ _nvswitch_service_nvltlc_tx_lnk_fatal_0_ls10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_TX_LNK_RSP1_RAM_DAT_ECC_DBE_ERR, "RSP1 RAM DAT ECC DBE Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + { + // TODO 3014908 log these in the NVL object until we have ECC object support + error_event.error = INFOROM_NVLINK_TLC_TX_RSP1_DAT_RAM_ECC_DBE_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } NVSWITCH_UNHANDLED_CHECK(device, unhandled); @@ -4662,11 +4706,16 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_ls10 { NvU32 pending, bit, unhandled; NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + INFOROM_NVLINK_ERROR_EVENT error_event = { 0 }; report.raw_pending = NVSWITCH_LINK_RD32_LS10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_STATUS_0); report.raw_enable = NVSWITCH_LINK_RD32_LS10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_FATAL_REPORT_EN_0); report.mask = report.raw_enable; pending = report.raw_pending & report.mask; + + error_event.nvliptInstance = (NvU8) nvlipt_instance; + error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LS10(link); + if (pending == 0) { return -NVL_NOT_FOUND; @@ -4680,6 +4729,10 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_ls10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXDLHDRPARITYERR, "RX DL HDR Parity Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_TLC_RX_DL_HDR_PARITY_ERR_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXDLDATAPARITYERR, 1); @@ -4687,6 +4740,10 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_ls10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXDLDATAPARITYERR, "RX DL Data Parity Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_TLC_RX_DL_DATA_PARITY_ERR_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXDLCTRLPARITYERR, 1); @@ -4694,6 +4751,10 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_ls10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXDLCTRLPARITYERR, "RX DL Ctrl Parity Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_TLC_RX_DL_CTRL_PARITY_ERR_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXPKTLENERR, 1); @@ -4701,6 +4762,10 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_ls10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXPKTLENERR, "RX Packet Length Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_TLC_RX_PKTLEN_ERR_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RSVCACHEATTRPROBEREQERR, 1); @@ -4708,6 +4773,10 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_ls10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RSVCACHEATTRPROBEREQERR, "RSV Packet Status Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_TLC_RX_RSVD_CACHE_ATTR_PROBE_REQ_ERR_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RSVCACHEATTRPROBERSPERR, 1); @@ -4715,6 +4784,10 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_ls10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RSVCACHEATTRPROBERSPERR, "RSV CacheAttr Probe Rsp Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_TLC_RX_RSVD_CACHE_ATTR_PROBE_RSP_ERR_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _DATLENGTRMWREQMAXERR, 1); @@ -4722,6 +4795,10 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_ls10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_DATLENGTRMWREQMAXERR, "Data Length RMW Req Max Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_TLC_RX_DATLEN_GT_RMW_REQ_MAX_ERR_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _DATLENLTATRRSPMINERR, 1); @@ -4729,6 +4806,10 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_ls10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_DATLENLTATRRSPMINERR, "Data Len Lt ATR RSP Min Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_TLC_RX_DATLEN_LT_ATR_RSP_MIN_ERR_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _INVALIDCACHEATTRPOERR, 1); @@ -4736,6 +4817,10 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_ls10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_INVALIDCACHEATTRPOERR, "Invalid Cache Attr PO Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_TLC_RX_INVALID_PO_FOR_CACHE_ATTR_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXRSPSTATUS_HW_ERR, 1); @@ -4743,6 +4828,10 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_ls10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_LNK_RXRSPSTATUS_HW_ERR, "RX Rsp Status HW Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_TLC_RX_RSP_STATUS_HW_ERR_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXRSPSTATUS_UR_ERR, 1); @@ -4750,6 +4839,10 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_ls10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_LNK_RXRSPSTATUS_UR_ERR, "RX Rsp Status UR Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_TLC_RX_RSP_STATUS_UR_ERR_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _INVALID_COLLAPSED_RESPONSE_ERR, 1); @@ -4757,6 +4850,10 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_ls10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_LNK_INVALID_COLLAPSED_RESPONSE_ERR, "Invalid Collapsed Response Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_TLC_RX_INVALID_COLLAPSED_RESPONSE_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } NVSWITCH_UNHANDLED_CHECK(device, unhandled); @@ -4796,12 +4893,17 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_1_ls10 { NvU32 pending, bit, unhandled; NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + INFOROM_NVLINK_ERROR_EVENT error_event = { 0 }; + NvU32 injected; report.raw_pending = NVSWITCH_LINK_RD32_LS10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_STATUS_1); report.raw_enable = NVSWITCH_LINK_RD32_LS10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_FATAL_REPORT_EN_1); report.mask = report.raw_enable; pending = report.raw_pending & report.mask; + error_event.nvliptInstance = (NvU8) nvlipt_instance; + error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LS10(link); + if (pending == 0) { return -NVL_NOT_FOUND; @@ -4809,12 +4911,19 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_1_ls10 unhandled = pending; report.raw_first = NVSWITCH_LINK_RD32_LS10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_FIRST_1); + injected = NVSWITCH_LINK_RD32_LS10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_REPORT_INJECT_1); bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_1, _RXHDROVFERR, 1); if (nvswitch_test_flags(pending, bit)) { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXHDROVFERR, "RX HDR OVF Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_1, _RXHDROVFERR, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_RX_HDR_OVERFLOW_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_1, _RXDATAOVFERR, 1); @@ -4822,6 +4931,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_1_ls10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXDATAOVFERR, "RX Data OVF Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_1, _RXDATAOVFERR, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_RX_DATA_OVERFLOW_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_1, _STOMPDETERR, 1); @@ -4829,6 +4944,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_1_ls10 { NVSWITCH_REPORT_FATAL(_HW_NVLTLC_STOMPDETERR, "Stomp Det Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_1, _STOMPDETERR, 0x0, injected)) + { + error_event.error = INFOROM_NVLINK_TLC_RX_STOMP_DETECTED_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_1, _RXPOISONERR, 1); @@ -4948,6 +5069,7 @@ _nvswitch_service_nvlipt_common_fatal_ls10 NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; NvU32 pending, bit, contain, unhandled; NvU32 link, local_link_idx; + INFOROM_NVLINK_ERROR_EVENT error_event = { 0 }; report.raw_pending = NVSWITCH_ENG_RD32(device, NVLIPT, , instance, _NVLIPT_COMMON, _ERR_STATUS_0); report.raw_enable = NVSWITCH_ENG_RD32(device, NVLIPT, , instance, _NVLIPT_COMMON, _ERR_FATAL_REPORT_EN_0); @@ -4959,6 +5081,8 @@ _nvswitch_service_nvlipt_common_fatal_ls10 return -NVL_NOT_FOUND; } + error_event.nvliptInstance = (NvU8) instance; + unhandled = pending; report.raw_first = NVSWITCH_ENG_RD32(device, NVLIPT, , instance, _NVLIPT_COMMON, _ERR_FIRST_0); contain = NVSWITCH_ENG_RD32(device, NVLIPT, , instance, _NVLIPT_COMMON, _ERR_CONTAIN_EN_0); @@ -4976,6 +5100,10 @@ _nvswitch_service_nvlipt_common_fatal_ls10 } nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_NVLIPT_CLKCTL_ILLEGAL_REQUEST_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } NVSWITCH_UNHANDLED_CHECK(device, unhandled); @@ -5302,6 +5430,7 @@ _nvswitch_emit_link_errors_nvldl_fatal_link_ls10 ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; NvU32 pending, bit; + INFOROM_NVLINK_ERROR_EVENT error_event; // Only enabled link errors are deffered pending = chip_device->deferredLinkErrors[link].fatalIntrMask.dl; @@ -5309,10 +5438,15 @@ _nvswitch_emit_link_errors_nvldl_fatal_link_ls10 report.raw_enable = pending; report.mask = report.raw_enable; + error_event.nvliptInstance = (NvU8) nvlipt_instance; + error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LS10(link); + bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_UP, 1); if (nvswitch_test_flags(pending, bit)) { NVSWITCH_REPORT_FATAL(_HW_DLPL_LTSSM_FAULT_UP, "LTSSM Fault Up", NV_FALSE); + error_event.error = INFOROM_NVLINK_DL_LTSSM_FAULT_UP_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); } } @@ -5336,10 +5470,6 @@ _nvswitch_emit_link_errors_nvldl_nonfatal_link_ls10 bit = DRF_NUM(_NVLDL_TOP, _INTR, _RX_SHORT_ERROR_RATE, 1); if (nvswitch_test_flags(pending, bit)) { - // Disable further interrupts - nvlink_link *nvlink = nvswitch_get_link(device, link); - nvlink->errorThreshold.bInterruptTrigerred = NV_TRUE; - nvswitch_configure_error_rate_threshold_interrupt_ls10(nvlink, NV_FALSE); NVSWITCH_REPORT_NONFATAL(_HW_DLPL_RX_SHORT_ERROR_RATE, "RX Short Error Rate"); } } @@ -5354,7 +5484,9 @@ _nvswitch_emit_link_errors_nvltlc_rx_lnk_nonfatal_1_ls10 { ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; - NvU32 pending, bit, injected; + NvU32 pending, bit; + INFOROM_NVLINK_ERROR_EVENT error_event; + NvU32 injected; // Only enabled link errors are deffered pending = chip_device->deferredLinkErrors[link].nonFatalIntrMask.tlcRx1; @@ -5363,6 +5495,9 @@ _nvswitch_emit_link_errors_nvltlc_rx_lnk_nonfatal_1_ls10 report.raw_enable = pending; report.mask = report.raw_enable; + error_event.nvliptInstance = (NvU8) nvlipt_instance; + error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LS10(link); + bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_1, _HEARTBEAT_TIMEOUT_ERR, 1); if (nvswitch_test_flags(pending, bit)) @@ -5371,6 +5506,8 @@ _nvswitch_emit_link_errors_nvltlc_rx_lnk_nonfatal_1_ls10 if (FLD_TEST_DRF_NUM(_NVLTLC_RX_LNK, _ERR_REPORT_INJECT_1, _HEARTBEAT_TIMEOUT_ERR, 0x0, injected)) { + error_event.error = INFOROM_NVLINK_TLC_RX_AN1_HEARTBEAT_TIMEOUT_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); } } } @@ -5386,6 +5523,7 @@ _nvswitch_emit_link_errors_nvlipt_lnk_nonfatal_ls10 ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; NvU32 pending, bit; + INFOROM_NVLINK_ERROR_EVENT error_event; // Only enabled link errors are deffered pending = chip_device->deferredLinkErrors[link].nonFatalIntrMask.liptLnk; @@ -5393,11 +5531,18 @@ _nvswitch_emit_link_errors_nvlipt_lnk_nonfatal_ls10 report.raw_enable = pending; report.mask = report.raw_enable; + error_event.nvliptInstance = (NvU8) nvlipt_instance; + error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LS10(link); + bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _FAILEDMINIONREQUEST, 1); if (nvswitch_test_flags(pending, bit)) { NVSWITCH_REPORT_NONFATAL(_HW_NVLIPT_LNK_FAILEDMINIONREQUEST, "_FAILEDMINIONREQUEST"); + { + error_event.error = INFOROM_NVLINK_NVLIPT_FAILED_MINION_REQUEST_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } } @@ -5754,11 +5899,15 @@ _nvswitch_service_nvltlc_rx_lnk_nonfatal_0_ls10 { NvU32 pending, bit, unhandled; NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + INFOROM_NVLINK_ERROR_EVENT error_event; report.raw_pending = NVSWITCH_LINK_RD32(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_STATUS_0); report.raw_enable = NVSWITCH_LINK_RD32(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_NON_FATAL_REPORT_EN_0); report.mask = report.raw_enable; + error_event.nvliptInstance = (NvU8) nvlipt_instance; + error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LS10(link); + pending = report.raw_pending & report.mask; if (pending == 0) { @@ -5773,6 +5922,10 @@ _nvswitch_service_nvltlc_rx_lnk_nonfatal_0_ls10 { NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_RX_LNK_RXRSPSTATUS_PRIV_ERR, "RX Rsp Status PRIV Error"); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_TLC_RX_RSP_STATUS_PRIV_ERR_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } NVSWITCH_UNHANDLED_CHECK(device, unhandled); @@ -5805,12 +5958,16 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_0_ls10 { NvU32 pending, bit, unhandled; NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + INFOROM_NVLINK_ERROR_EVENT error_event; report.raw_pending = NVSWITCH_LINK_RD32(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_STATUS_0); report.raw_enable = NVSWITCH_LINK_RD32(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_NON_FATAL_REPORT_EN_0); report.mask = report.raw_enable; pending = report.raw_pending & report.mask; + error_event.nvliptInstance = (NvU8) nvlipt_instance; + error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LS10(link); + if (pending == 0) { return -NVL_NOT_FOUND; @@ -5824,6 +5981,11 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_0_ls10 { NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_CREQ_RAM_DAT_ECC_DBE_ERR, "CREQ RAM DAT ECC DBE Error"); nvswitch_clear_flags(&unhandled, bit); + { + // TODO 3014908 log these in the NVL object until we have ECC object support + error_event.error = INFOROM_NVLINK_TLC_TX_CREQ_DAT_RAM_ECC_DBE_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_0, _CREQ_RAM_ECC_LIMIT_ERR, 1); @@ -5852,6 +6014,11 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_0_ls10 { NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_COM_RAM_DAT_ECC_DBE_ERR, "COM RAM DAT ECC DBE Error"); nvswitch_clear_flags(&unhandled, bit); + { + // TODO 3014908 log these in the NVL object until we have ECC object support + error_event.error = INFOROM_NVLINK_TLC_TX_COM_DAT_RAM_ECC_DBE_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_0, _COM_RAM_ECC_LIMIT_ERR, 1); @@ -5904,8 +6071,9 @@ _nvswitch_service_nvltlc_rx_lnk_nonfatal_1_ls10 ) { ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); - NvU32 pending, bit, unhandled, injected; + NvU32 pending, bit, unhandled; NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + NvU32 injected; report.raw_pending = NVSWITCH_LINK_RD32(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_STATUS_1); report.raw_enable = NVSWITCH_LINK_RD32(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_NON_FATAL_REPORT_EN_1); @@ -5983,12 +6151,16 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_1_ls10 { NvU32 pending, bit, unhandled; NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + INFOROM_NVLINK_ERROR_EVENT error_event = { 0 }; report.raw_pending = NVSWITCH_LINK_RD32(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_STATUS_1); report.raw_enable = NVSWITCH_LINK_RD32(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_NON_FATAL_REPORT_EN_1); report.mask = report.raw_enable; pending = report.raw_pending & report.mask; + error_event.nvliptInstance = (NvU8) nvlipt_instance; + error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LS10(link); + if (pending == 0) { return -NVL_NOT_FOUND; @@ -6002,6 +6174,10 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_1_ls10 { NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC0, "AN1 Timeout VC0"); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC0_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _TIMEOUT_VC1, 1); @@ -6009,6 +6185,10 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_1_ls10 { NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC1, "AN1 Timeout VC1"); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC1_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _TIMEOUT_VC2, 1); @@ -6016,13 +6196,21 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_1_ls10 { NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC2, "AN1 Timeout VC2"); nvswitch_clear_flags(&unhandled, bit); - } + { + error_event.error = INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC2_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } + } bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _TIMEOUT_VC3, 1); if (nvswitch_test_flags(pending, bit)) { NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC3, "AN1 Timeout VC3"); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC3_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _TIMEOUT_VC4, 1); @@ -6030,6 +6218,10 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_1_ls10 { NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC4, "AN1 Timeout VC4"); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC4_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _TIMEOUT_VC5, 1); @@ -6037,6 +6229,10 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_1_ls10 { NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC5, "AN1 Timeout VC5"); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC5_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _TIMEOUT_VC6, 1); @@ -6044,6 +6240,10 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_1_ls10 { NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC6, "AN1 Timeout VC6"); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC6_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _TIMEOUT_VC7, 1); @@ -6051,6 +6251,10 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_1_ls10 { NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC7, "AN1 Timeout VC7"); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC7_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } NVSWITCH_UNHANDLED_CHECK(device, unhandled); @@ -6228,11 +6432,15 @@ _nvswitch_service_nvlipt_lnk_nonfatal_ls10 NvU32 lnkStateRequest, lnkStateStatus; NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; NvU32 pending, bit, unhandled; + INFOROM_NVLINK_ERROR_EVENT error_event = { 0 }; report.raw_pending = NVSWITCH_LINK_RD32(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_STATUS_0); report.raw_enable = NVSWITCH_LINK_RD32(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_NON_FATAL_REPORT_EN_0); report.mask = report.raw_enable; + error_event.nvliptInstance = (NvU8) nvlipt_instance; + error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LS10(link); + pending = report.raw_pending & report.mask; if (pending == 0) { @@ -6247,6 +6455,10 @@ _nvswitch_service_nvlipt_lnk_nonfatal_ls10 { NVSWITCH_REPORT_NONFATAL(_HW_NVLIPT_LNK_ILLEGALLINKSTATEREQUEST, "_HW_NVLIPT_LNK_ILLEGALLINKSTATEREQUEST"); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_NVLIPT_ILLEGAL_LINK_STATE_REQUEST_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _FAILEDMINIONREQUEST, 1); @@ -6288,6 +6500,10 @@ _nvswitch_service_nvlipt_lnk_nonfatal_ls10 { NVSWITCH_REPORT_NONFATAL(_HW_NVLIPT_LNK_RESERVEDREQUESTVALUE, "_RESERVEDREQUESTVALUE"); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_NVLIPT_RESERVED_REQUEST_VALUE_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _LINKSTATEWRITEWHILEBUSY, 1); @@ -6295,6 +6511,10 @@ _nvswitch_service_nvlipt_lnk_nonfatal_ls10 { NVSWITCH_REPORT_NONFATAL(_HW_NVLIPT_LNK_LINKSTATEWRITEWHILEBUSY, "_LINKSTATEWRITEWHILEBUSY"); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_NVLIPT_LINK_STATE_WRITE_WHILE_BUSY_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _LINK_STATE_REQUEST_TIMEOUT, 1); @@ -6302,6 +6522,10 @@ _nvswitch_service_nvlipt_lnk_nonfatal_ls10 { NVSWITCH_REPORT_NONFATAL(_HW_NVLIPT_LNK_LINK_STATE_REQUEST_TIMEOUT, "_LINK_STATE_REQUEST_TIMEOUT"); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_NVLIPT_LINK_STATE_REQUEST_TIMEOUT_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _WRITE_TO_LOCKED_SYSTEM_REG_ERR, 1); @@ -6309,6 +6533,10 @@ _nvswitch_service_nvlipt_lnk_nonfatal_ls10 { NVSWITCH_REPORT_NONFATAL(_HW_NVLIPT_LNK_WRITE_TO_LOCKED_SYSTEM_REG_ERR, "_WRITE_TO_LOCKED_SYSTEM_REG_ERR"); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_NVLIPT_WRITE_TO_LOCKED_SYSTEM_REG_NONFATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } NVSWITCH_UNHANDLED_CHECK(device, unhandled); @@ -6521,6 +6749,7 @@ _nvswitch_service_nvlipt_lnk_fatal_ls10 { NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; NvU32 pending, bit, unhandled; + INFOROM_NVLINK_ERROR_EVENT error_event = { 0 }; report.raw_pending = NVSWITCH_LINK_RD32(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_STATUS_0); report.raw_enable = NVSWITCH_LINK_RD32(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_FATAL_REPORT_EN_0); @@ -6532,6 +6761,9 @@ _nvswitch_service_nvlipt_lnk_fatal_ls10 return -NVL_NOT_FOUND; } + error_event.nvliptInstance = (NvU8) nvlipt_instance; + error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LS10(link); + unhandled = pending; report.raw_first = NVSWITCH_LINK_RD32(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_FIRST_0); @@ -6540,6 +6772,10 @@ _nvswitch_service_nvlipt_lnk_fatal_ls10 { NVSWITCH_REPORT_FATAL(_HW_NVLIPT_LNK_SLEEPWHILEACTIVELINK, "No non-empty link is detected", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_NVLIPT_SLEEP_WHILE_ACTIVE_LINK_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _RSTSEQ_PHYCTL_TIMEOUT, 1); @@ -6547,6 +6783,10 @@ _nvswitch_service_nvlipt_lnk_fatal_ls10 { NVSWITCH_REPORT_FATAL(_HW_NVLIPT_LNK_RSTSEQ_PHYCTL_TIMEOUT, "Reset sequencer timed out waiting for a handshake from PHYCTL", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_NVLIPT_RSTSEQ_PHYCTL_TIMEOUT_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _RSTSEQ_CLKCTL_TIMEOUT, 1); @@ -6554,6 +6794,10 @@ _nvswitch_service_nvlipt_lnk_fatal_ls10 { NVSWITCH_REPORT_FATAL(_HW_NVLIPT_LNK_RSTSEQ_CLKCTL_TIMEOUT, "Reset sequencer timed out waiting for a handshake from CLKCTL", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + { + error_event.error = INFOROM_NVLINK_NVLIPT_RSTSEQ_CLKCTL_TIMEOUT_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); + } } NVSWITCH_UNHANDLED_CHECK(device, unhandled); @@ -6646,12 +6890,12 @@ _nvswitch_service_nvlw_fatal_ls10 status[5] = _nvswitch_service_nvlipt_link_fatal_ls10(device, instance); - if (status[0] != NVL_SUCCESS && status[0] != -NVL_NOT_FOUND && - status[1] != NVL_SUCCESS && status[1] != -NVL_NOT_FOUND && - status[2] != NVL_SUCCESS && status[2] != -NVL_NOT_FOUND && - status[3] != NVL_SUCCESS && status[3] != -NVL_NOT_FOUND && - status[4] != NVL_SUCCESS && status[4] != -NVL_NOT_FOUND && - status[5] != NVL_SUCCESS && status[5] != -NVL_NOT_FOUND) + if (status[0] != NVL_SUCCESS && + status[1] != NVL_SUCCESS && + status[2] != NVL_SUCCESS && + status[3] != NVL_SUCCESS && + status[4] != NVL_SUCCESS && + status[5] != NVL_SUCCESS) { return -NVL_MORE_PROCESSING_REQUIRED; } @@ -7071,12 +7315,16 @@ nvswitch_service_nvldl_fatal_link_ls10 NvBool bSkipIntrClear = NV_FALSE; NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + INFOROM_NVLINK_ERROR_EVENT error_event; report.raw_pending = NVSWITCH_LINK_RD32(device, link, NVLDL, _NVLDL_TOP, _INTR); report.raw_enable = NVSWITCH_LINK_RD32(device, link, NVLDL, _NVLDL_TOP, _INTR_STALL_EN); report.mask = report.raw_enable; pending = report.raw_pending & report.mask; + error_event.nvliptInstance = (NvU8) nvlipt_instance; + error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LS10(link); + if (pending == 0) { return -NVL_NOT_FOUND; @@ -7089,6 +7337,8 @@ nvswitch_service_nvldl_fatal_link_ls10 { NVSWITCH_REPORT_FATAL(_HW_DLPL_TX_FAULT_RAM, "TX Fault Ram", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + error_event.error = INFOROM_NVLINK_DL_TX_FAULT_RAM_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); } bit = DRF_NUM(_NVLDL_TOP, _INTR, _TX_FAULT_INTERFACE, 1); @@ -7096,6 +7346,8 @@ nvswitch_service_nvldl_fatal_link_ls10 { NVSWITCH_REPORT_FATAL(_HW_DLPL_TX_FAULT_INTERFACE, "TX Fault Interface", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + error_event.error = INFOROM_NVLINK_DL_TX_FAULT_INTERFACE_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); } bit = DRF_NUM(_NVLDL_TOP, _INTR, _TX_FAULT_SUBLINK_CHANGE, 1); @@ -7103,6 +7355,8 @@ nvswitch_service_nvldl_fatal_link_ls10 { NVSWITCH_REPORT_FATAL(_HW_DLPL_TX_FAULT_SUBLINK_CHANGE, "TX Fault Sublink Change", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + error_event.error = INFOROM_NVLINK_DL_TX_FAULT_SUBLINK_CHANGE_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); } bit = DRF_NUM(_NVLDL_TOP, _INTR, _RX_FAULT_SUBLINK_CHANGE, 1); @@ -7110,6 +7364,8 @@ nvswitch_service_nvldl_fatal_link_ls10 { NVSWITCH_REPORT_FATAL(_HW_DLPL_RX_FAULT_SUBLINK_CHANGE, "RX Fault Sublink Change", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + error_event.error = INFOROM_NVLINK_DL_RX_FAULT_SUBLINK_CHANGE_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); } bit = DRF_NUM(_NVLDL_TOP, _INTR, _RX_FAULT_DL_PROTOCOL, 1); @@ -7117,6 +7373,8 @@ nvswitch_service_nvldl_fatal_link_ls10 { NVSWITCH_REPORT_FATAL(_HW_DLPL_RX_FAULT_DL_PROTOCOL, "RX Fault DL Protocol", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + error_event.error = INFOROM_NVLINK_DL_RX_FAULT_DL_PROTOCOL_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); } bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_DOWN, 1); @@ -7124,6 +7382,8 @@ nvswitch_service_nvldl_fatal_link_ls10 { NVSWITCH_REPORT_FATAL(_HW_DLPL_LTSSM_FAULT_DOWN, "LTSSM Fault Down", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + error_event.error = INFOROM_NVLINK_DL_LTSSM_FAULT_DOWN_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); } bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_PROTOCOL, 1); @@ -7131,6 +7391,8 @@ nvswitch_service_nvldl_fatal_link_ls10 { NVSWITCH_REPORT_FATAL(_HW_DLPL_LTSSM_PROTOCOL, "LTSSM Protocol Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + + // TODO 2827793 this should be logged to the InfoROM as fatal } bit = DRF_NUM(_NVLDL_TOP, _INTR, _PHY_A, 1); @@ -7138,6 +7400,8 @@ nvswitch_service_nvldl_fatal_link_ls10 { NVSWITCH_REPORT_FATAL(_HW_DLPL_PHY_A, "PHY_A Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + error_event.error = INFOROM_NVLINK_DL_PHY_A_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); } bit = DRF_NUM(_NVLDL_TOP, _INTR, _TX_PL_ERROR, 1); @@ -7145,6 +7409,8 @@ nvswitch_service_nvldl_fatal_link_ls10 { NVSWITCH_REPORT_FATAL(_HW_DLPL_TX_PL_ERROR, "TX_PL Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + error_event.error = INFOROM_NVLINK_DL_TX_PL_ERROR_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); } bit = DRF_NUM(_NVLDL_TOP, _INTR, _RX_PL_ERROR, 1); @@ -7152,6 +7418,8 @@ nvswitch_service_nvldl_fatal_link_ls10 { NVSWITCH_REPORT_FATAL(_HW_DLPL_RX_PL_ERROR, "RX_PL Error", NV_FALSE); nvswitch_clear_flags(&unhandled, bit); + error_event.error = INFOROM_NVLINK_DL_RX_PL_ERROR_FATAL; + nvswitch_inforom_nvlink_log_error_event(device, &error_event); } // @@ -7192,7 +7460,7 @@ nvswitch_service_nvldl_fatal_link_ls10 if (!bSkipIntrClear) { - NVSWITCH_LINK_WR32(device, link, NVLDL, _NVLDL_TOP, _INTR, pending); + NVSWITCH_LINK_WR32(device, link, NVLDL, _NVLDL_TOP, _INTR, pending); } if (unhandled != 0) diff --git a/src/common/nvswitch/kernel/ls10/link_ls10.c b/src/common/nvswitch/kernel/ls10/link_ls10.c index 237d4113a..f98306b95 100644 --- a/src/common/nvswitch/kernel/ls10/link_ls10.c +++ b/src/common/nvswitch/kernel/ls10/link_ls10.c @@ -137,10 +137,9 @@ nvswitch_init_lpwr_regs_ls10 bLpEnable = NV_TRUE; softwareDesired = (bLpEnable) ? 0x1 : 0x0; - // TO-DO: The write to the AN1 register is not working. The logic here needs to be re-visited. - tempRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, _CTRL_SYSTEM_LINK_AN1_CTRL); - tempRegVal = FLD_SET_DRF_NUM(_NVLIPT, _LNK_CTRL_SYSTEM_LINK_AN1_CTRL, _PWRM_L1_ENABLE, softwareDesired, tempRegVal); - NVSWITCH_LINK_WR32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, _CTRL_SYSTEM_LINK_AN1_CTRL, tempRegVal); + tempRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, _PWRM_CTRL); + tempRegVal = FLD_SET_DRF_NUM(_NVLIPT, _LNK_PWRM_CTRL, _L1_SOFTWARE_DESIRED, softwareDesired, tempRegVal); + NVSWITCH_LINK_WR32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, _PWRM_CTRL, tempRegVal); } void @@ -1079,6 +1078,29 @@ nvswitch_store_topology_information_ls10 } } +void +nvswitch_get_error_rate_threshold_ls10 +( + nvlink_link *link +) +{ + nvswitch_device *device = link->dev->pDevInfo; + NvU32 linkNumber = link->linkNumber; + NvU32 crcRegVal; + + crcRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL, + _NVLDL_RX, _ERROR_RATE_CTRL); + + link->errorThreshold.thresholdMan = DRF_VAL(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_THRESHOLD_MAN, + crcRegVal); + link->errorThreshold.thresholdExp = DRF_VAL(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_THRESHOLD_EXP, + crcRegVal); + link->errorThreshold.timescaleMan = DRF_VAL(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_TIMESCALE_MAN, + crcRegVal); + link->errorThreshold.timescaleExp = DRF_VAL(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_TIMESCALE_EXP, + crcRegVal); +} + void nvswitch_set_error_rate_threshold_ls10 ( @@ -1132,7 +1154,6 @@ nvswitch_set_error_rate_threshold_ls10 crcRegVal &= ~shortRateMask; crcRegVal |= crcShortRegkeyVal; - link->errorThreshold.bUserConfig = NV_FALSE; link->errorThreshold.bInterruptTrigerred = NV_FALSE; } @@ -1204,13 +1225,11 @@ nvswitch_configure_error_rate_threshold_interrupt_ls10 if (bEnable) { link->errorThreshold.bInterruptTrigerred = NV_FALSE; - intrRegVal = FLD_SET_DRF_NUM(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, 1, - intrRegVal); + intrRegVal |= DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, _ENABLE); } else { - intrRegVal = FLD_SET_DRF_NUM(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, 0, - intrRegVal); + intrRegVal |= DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, _DISABLE); } NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, @@ -1414,7 +1433,7 @@ nvswitch_execute_unilateral_link_shutdown_ls10 NvU32 link_state_request; NvU32 link_state; NvU32 stat_data = 0; - NvU32 link_intr_subcode = 0; + NvU32 link_intr_subcode; if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLDL, link->linkNumber)) { diff --git a/src/common/nvswitch/kernel/ls10/ls10.c b/src/common/nvswitch/kernel/ls10/ls10.c index 8a33730eb..159592615 100644 --- a/src/common/nvswitch/kernel/ls10/ls10.c +++ b/src/common/nvswitch/kernel/ls10/ls10.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -65,7 +65,7 @@ #include "ls10/minion_nvlink_defines_public_ls10.h" #define NVSWITCH_IFR_MIN_BIOS_VER_LS10 0x9610170000ull -#define NVSWITCH_SMBPBI_MIN_BIOS_VER_LS10 0x9610220000ull +#define NVSWITCH_SMBPBI_MIN_BIOS_VER_LS10 0x9610170000ull void * nvswitch_alloc_chipdevice_ls10 @@ -113,7 +113,7 @@ nvswitch_pri_ring_init_ls10 { keepPolling = (nvswitch_timeout_check(&timeout)) ? NV_FALSE : NV_TRUE; - command = NVSWITCH_REG_RD32(device, _GFW_GLOBAL, _BOOT_PARTITION_PROGRESS); + command = NVSWITCH_REG_RD32(device, _GFW_GLOBAL, _BOOT_PARTITION_PROGRESS); if (FLD_TEST_DRF(_GFW_GLOBAL, _BOOT_PARTITION_PROGRESS, _VALUE, _SUCCESS, command)) { break; @@ -1353,10 +1353,10 @@ nvswitch_reset_and_drain_links_ls10 NvU32 link; NvU32 data32; NvU32 retry_count = 3; - NvU32 link_state_request; - NvU32 link_state; - NvU32 stat_data; - NvU32 link_intr_subcode; + NvU32 link_state_request; + NvU32 link_state; + NvU32 stat_data; + NvU32 link_intr_subcode; if (link_mask == 0) { @@ -1575,7 +1575,6 @@ nvswitch_set_nport_port_config_ls10 ) { NvU32 val; - NvlStatus status = NVL_SUCCESS; if (p->requesterLinkID >= NVBIT( DRF_SIZE(NV_NPORT_REQLINKID_REQROUTINGID) + @@ -1625,162 +1624,156 @@ nvswitch_set_nport_port_config_ls10 if (p->type == CONNECT_TRUNK_SWITCH) { - if (!nvswitch_is_soe_supported(device)) + if (IS_RTLSIM(device) || IS_EMULATION(device) || IS_FMODEL(device)) { // Set trunk specific settings (TPROD) on PRE-SILION - // NPORT - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _NPORT, _CTRL); - val = FLD_SET_DRF(_NPORT, _CTRL, _EGDRAINENB, _DISABLE, val); - val = FLD_SET_DRF(_NPORT, _CTRL, _ENEGRESSDBI, _ENABLE, val); - val = FLD_SET_DRF(_NPORT, _CTRL, _ENROUTEDBI, _ENABLE, val); - val = FLD_SET_DRF(_NPORT, _CTRL, _RTDRAINENB, _DISABLE, val); - val = FLD_SET_DRF(_NPORT, _CTRL, _SPARE, _INIT, val); - val = FLD_SET_DRF(_NPORT, _CTRL, _TRUNKLINKENB, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _NPORT, _CTRL, val); + // NPORT + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _NPORT, _CTRL); + val = FLD_SET_DRF(_NPORT, _CTRL, _EGDRAINENB, _DISABLE, val); + val = FLD_SET_DRF(_NPORT, _CTRL, _ENEGRESSDBI, _ENABLE, val); + val = FLD_SET_DRF(_NPORT, _CTRL, _ENROUTEDBI, _ENABLE, val); + val = FLD_SET_DRF(_NPORT, _CTRL, _RTDRAINENB, _DISABLE, val); + val = FLD_SET_DRF(_NPORT, _CTRL, _SPARE, _INIT, val); + val = FLD_SET_DRF(_NPORT, _CTRL, _TRUNKLINKENB, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _NPORT, _CTRL, val); - // EGRESS - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _EGRESS, _CTRL); - val = FLD_SET_DRF(_EGRESS, _CTRL, _CTO_ENB, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _EGRESS, _CTRL, val); + // EGRESS + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _EGRESS, _CTRL); + val = FLD_SET_DRF(_EGRESS, _CTRL, _CTO_ENB, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _EGRESS, _CTRL, val); - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _EGRESS, _ERR_CONTAIN_EN_0); - val = FLD_SET_DRF(_EGRESS, _ERR_CONTAIN_EN_0, _CREDIT_TIME_OUT_ERR, __TPROD, val); - val = FLD_SET_DRF(_EGRESS, _ERR_CONTAIN_EN_0, _HWRSPERR, __TPROD, val); - val = FLD_SET_DRF(_EGRESS, _ERR_CONTAIN_EN_0, _INVALIDVCSET_ERR, __TPROD, val); - val = FLD_SET_DRF(_EGRESS, _ERR_CONTAIN_EN_0, _REQTGTIDMISMATCHERR, __TPROD, val); - val = FLD_SET_DRF(_EGRESS, _ERR_CONTAIN_EN_0, _RSPREQIDMISMATCHERR, __TPROD, val); - val = FLD_SET_DRF(_EGRESS, _ERR_CONTAIN_EN_0, _URRSPERR, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _EGRESS, _ERR_CONTAIN_EN_0, val); + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _EGRESS, _ERR_CONTAIN_EN_0); + val = FLD_SET_DRF(_EGRESS, _ERR_CONTAIN_EN_0, _CREDIT_TIME_OUT_ERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_CONTAIN_EN_0, _HWRSPERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_CONTAIN_EN_0, _INVALIDVCSET_ERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_CONTAIN_EN_0, _REQTGTIDMISMATCHERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_CONTAIN_EN_0, _RSPREQIDMISMATCHERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_CONTAIN_EN_0, _URRSPERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _EGRESS, _ERR_CONTAIN_EN_0, val); - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _EGRESS, _ERR_FATAL_REPORT_EN_0); - val = FLD_SET_DRF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _CREDIT_TIME_OUT_ERR, __TPROD, val); - val = FLD_SET_DRF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _HWRSPERR, __TPROD, val); - val = FLD_SET_DRF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _INVALIDVCSET_ERR, __TPROD, val); - val = FLD_SET_DRF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _REQTGTIDMISMATCHERR, __TPROD, val); - val = FLD_SET_DRF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _RSPREQIDMISMATCHERR, __TPROD, val); - val = FLD_SET_DRF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _URRSPERR, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _EGRESS, _ERR_FATAL_REPORT_EN_0, val); + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _EGRESS, _ERR_FATAL_REPORT_EN_0); + val = FLD_SET_DRF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _CREDIT_TIME_OUT_ERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _HWRSPERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _INVALIDVCSET_ERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _REQTGTIDMISMATCHERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _RSPREQIDMISMATCHERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _URRSPERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _EGRESS, _ERR_FATAL_REPORT_EN_0, val); - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _EGRESS, _ERR_LOG_EN_0); - val = FLD_SET_DRF(_EGRESS, _ERR_LOG_EN_0, _CREDIT_TIME_OUT_ERR, __TPROD, val); - val = FLD_SET_DRF(_EGRESS, _ERR_LOG_EN_0, _HWRSPERR, __TPROD, val); - val = FLD_SET_DRF(_EGRESS, _ERR_LOG_EN_0, _INVALIDVCSET_ERR, __TPROD, val); - val = FLD_SET_DRF(_EGRESS, _ERR_LOG_EN_0, _REQTGTIDMISMATCHERR, __TPROD, val); - val = FLD_SET_DRF(_EGRESS, _ERR_LOG_EN_0, _RSPREQIDMISMATCHERR, __TPROD, val); - val = FLD_SET_DRF(_EGRESS, _ERR_LOG_EN_0, _URRSPERR, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _EGRESS, _ERR_LOG_EN_0, val); + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _EGRESS, _ERR_LOG_EN_0); + val = FLD_SET_DRF(_EGRESS, _ERR_LOG_EN_0, _CREDIT_TIME_OUT_ERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_LOG_EN_0, _HWRSPERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_LOG_EN_0, _INVALIDVCSET_ERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_LOG_EN_0, _REQTGTIDMISMATCHERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_LOG_EN_0, _RSPREQIDMISMATCHERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_LOG_EN_0, _URRSPERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _EGRESS, _ERR_LOG_EN_0, val); - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _EGRESS, _ERR_NON_FATAL_REPORT_EN_0); - val = FLD_SET_DRF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _PRIVRSPERR, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _EGRESS, _ERR_NON_FATAL_REPORT_EN_0, val); + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _EGRESS, _ERR_NON_FATAL_REPORT_EN_0); + val = FLD_SET_DRF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _PRIVRSPERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _EGRESS, _ERR_NON_FATAL_REPORT_EN_0, val); - // INGRESS - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _INGRESS, _ERR_CONTAIN_EN_0); - val = FLD_SET_DRF(_INGRESS, _ERR_CONTAIN_EN_0, _EXTAREMAPTAB_ECC_DBE_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_CONTAIN_EN_0, _EXTBREMAPTAB_ECC_DBE_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_CONTAIN_EN_0, _INVALIDVCSET, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_CONTAIN_EN_0, _MCREMAPTAB_ECC_DBE_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_CONTAIN_EN_0, _REMAPTAB_ECC_DBE_ERR, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _INGRESS, _ERR_CONTAIN_EN_0, val); + // INGRESS + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _INGRESS, _ERR_CONTAIN_EN_0); + val = FLD_SET_DRF(_INGRESS, _ERR_CONTAIN_EN_0, _EXTAREMAPTAB_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_CONTAIN_EN_0, _EXTBREMAPTAB_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_CONTAIN_EN_0, _INVALIDVCSET, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_CONTAIN_EN_0, _MCREMAPTAB_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_CONTAIN_EN_0, _REMAPTAB_ECC_DBE_ERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _INGRESS, _ERR_CONTAIN_EN_0, val); - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _INGRESS, _ERR_FATAL_REPORT_EN_0); - val = FLD_SET_DRF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTAREMAPTAB_ECC_DBE_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTBREMAPTAB_ECC_DBE_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _INVALIDVCSET, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _MCREMAPTAB_ECC_DBE_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _REMAPTAB_ECC_DBE_ERR, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _INGRESS, _ERR_FATAL_REPORT_EN_0, val); + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _INGRESS, _ERR_FATAL_REPORT_EN_0); + val = FLD_SET_DRF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTAREMAPTAB_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTBREMAPTAB_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _INVALIDVCSET, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _MCREMAPTAB_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _REMAPTAB_ECC_DBE_ERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _INGRESS, _ERR_FATAL_REPORT_EN_0, val); - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _INGRESS, _ERR_LOG_EN_0); - val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_0, _EXTAREMAPTAB_ECC_DBE_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_0, _EXTBREMAPTAB_ECC_DBE_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_0, _INVALIDVCSET, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_0, _MCREMAPTAB_ECC_DBE_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_0, _REMAPTAB_ECC_DBE_ERR, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _INGRESS, _ERR_LOG_EN_0, val); + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _INGRESS, _ERR_LOG_EN_0); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_0, _EXTAREMAPTAB_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_0, _EXTBREMAPTAB_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_0, _INVALIDVCSET, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_0, _MCREMAPTAB_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_0, _REMAPTAB_ECC_DBE_ERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _INGRESS, _ERR_LOG_EN_0, val); - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _INGRESS, _ERR_LOG_EN_1); - val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _EXTAREMAPTAB_ADDRTYPEERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _EXTAREMAPTAB_ECC_LIMIT_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _EXTBREMAPTAB_ADDRTYPEERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _EXTBREMAPTAB_ECC_LIMIT_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _MCCMDTOUCADDRERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _MCREMAPTAB_ADDRTYPEERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _MCREMAPTAB_ECC_LIMIT_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _READMCREFLECTMEMERR, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _INGRESS, _ERR_LOG_EN_1, val); + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _INGRESS, _ERR_LOG_EN_1); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _EXTAREMAPTAB_ADDRTYPEERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _EXTAREMAPTAB_ECC_LIMIT_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _EXTBREMAPTAB_ADDRTYPEERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _EXTBREMAPTAB_ECC_LIMIT_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _MCCMDTOUCADDRERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _MCREMAPTAB_ADDRTYPEERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _MCREMAPTAB_ECC_LIMIT_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _READMCREFLECTMEMERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _INGRESS, _ERR_LOG_EN_1, val); - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _INGRESS, _ERR_NON_FATAL_REPORT_EN_0); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _ACLFAIL, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _ADDRBOUNDSERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _ADDRTYPEERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_ACLFAIL, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_ADDRBOUNDSERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_INDEX_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_REQCONTEXTMISMATCHERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_ACLFAIL, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_ADDRBOUNDSERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_INDEX_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_REQCONTEXTMISMATCHERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_ACLFAIL, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_ADDRBOUNDSERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_INDEX_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_REQCONTEXTMISMATCHERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _REMAPTAB_ECC_LIMIT_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _REQCONTEXTMISMATCHERR, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _INGRESS, _ERR_NON_FATAL_REPORT_EN_0, val); + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _INGRESS, _ERR_NON_FATAL_REPORT_EN_0); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _ACLFAIL, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _ADDRBOUNDSERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _ADDRTYPEERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_ACLFAIL, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_ADDRBOUNDSERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_INDEX_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_REQCONTEXTMISMATCHERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_ACLFAIL, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_ADDRBOUNDSERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_INDEX_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_REQCONTEXTMISMATCHERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_ACLFAIL, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_ADDRBOUNDSERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_INDEX_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_REQCONTEXTMISMATCHERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _REMAPTAB_ECC_LIMIT_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _REQCONTEXTMISMATCHERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _INGRESS, _ERR_NON_FATAL_REPORT_EN_0, val); - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _INGRESS, _ERR_NON_FATAL_REPORT_EN_1); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTAREMAPTAB_ADDRTYPEERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTAREMAPTAB_ECC_LIMIT_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTBREMAPTAB_ADDRTYPEERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTBREMAPTAB_ECC_LIMIT_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCCMDTOUCADDRERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREMAPTAB_ADDRTYPEERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREMAPTAB_ECC_LIMIT_ERR, __TPROD, val); - val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _READMCREFLECTMEMERR, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _INGRESS, _ERR_NON_FATAL_REPORT_EN_1, val); + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _INGRESS, _ERR_NON_FATAL_REPORT_EN_1); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTAREMAPTAB_ADDRTYPEERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTAREMAPTAB_ECC_LIMIT_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTBREMAPTAB_ADDRTYPEERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTBREMAPTAB_ECC_LIMIT_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCCMDTOUCADDRERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREMAPTAB_ADDRTYPEERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREMAPTAB_ECC_LIMIT_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _READMCREFLECTMEMERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _INGRESS, _ERR_NON_FATAL_REPORT_EN_1, val); - // SOURCETRACK - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_CONTAIN_EN_0); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR, __TPROD, val); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _DUP_CREQ_TCEN0_TAG_ERR, __TPROD, val); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _INVALID_TCEN0_RSP_ERR, __TPROD, val); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _INVALID_TCEN1_RSP_ERR, __TPROD, val); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _SOURCETRACK_TIME_OUT_ERR, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_CONTAIN_EN_0, val); + // SOURCETRACK + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_CONTAIN_EN_0); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _DUP_CREQ_TCEN0_TAG_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _INVALID_TCEN0_RSP_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _INVALID_TCEN1_RSP_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _SOURCETRACK_TIME_OUT_ERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_CONTAIN_EN_0, val); - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_FATAL_REPORT_EN_0); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR, __TPROD, val); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _DUP_CREQ_TCEN0_TAG_ERR, __TPROD, val); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _INVALID_TCEN0_RSP_ERR, __TPROD, val); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _INVALID_TCEN1_RSP_ERR, __TPROD, val); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _SOURCETRACK_TIME_OUT_ERR, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_FATAL_REPORT_EN_0, val); + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_FATAL_REPORT_EN_0); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _DUP_CREQ_TCEN0_TAG_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _INVALID_TCEN0_RSP_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _INVALID_TCEN1_RSP_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _SOURCETRACK_TIME_OUT_ERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_FATAL_REPORT_EN_0, val); - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_LOG_EN_0); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_LOG_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR, __TPROD, val); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_LOG_EN_0, _DUP_CREQ_TCEN0_TAG_ERR, __TPROD, val); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_LOG_EN_0, _INVALID_TCEN0_RSP_ERR, __TPROD, val); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_LOG_EN_0, _INVALID_TCEN1_RSP_ERR, __TPROD, val); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_LOG_EN_0, _SOURCETRACK_TIME_OUT_ERR, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_LOG_EN_0, val); + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_LOG_EN_0); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_LOG_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_LOG_EN_0, _DUP_CREQ_TCEN0_TAG_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_LOG_EN_0, _INVALID_TCEN0_RSP_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_LOG_EN_0, _INVALID_TCEN1_RSP_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_LOG_EN_0, _SOURCETRACK_TIME_OUT_ERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_LOG_EN_0, val); - val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0); - val = FLD_SET_DRF(_SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR, __TPROD, val); - NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0, val); - } - else - { + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0, val); + } + else + { // Set trunk specific settings (TPROD) in SOE - status = nvswitch_set_nport_tprod_state_ls10(device, p->portNum); - if (status != NVL_SUCCESS) - { - NVSWITCH_PRINT(device, ERROR, - "%s: Failed to set NPORT TPROD state\n", - __FUNCTION__); - } + // nvswitch_set_nport_tprod_state_ls10(device, p->portNum); } } else @@ -1791,7 +1784,7 @@ nvswitch_set_nport_port_config_ls10 NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _NPORT, _SRC_PORT_TYPE0, NvU64_LO32(p->trunkSrcMask)); NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _NPORT, _SRC_PORT_TYPE1, NvU64_HI32(p->trunkSrcMask)); - return status; + return NVL_SUCCESS; } /* @@ -2647,6 +2640,14 @@ nvswitch_get_num_links_ls10 return NVSWITCH_NUM_LINKS_LS10; } +static NvU8 +nvswitch_get_num_links_per_nvlipt_ls10 +( + nvswitch_device *device +) +{ + return NVSWITCH_LINKS_PER_NVLIPT_LS10; +} void nvswitch_set_fatal_error_ls10 @@ -2797,7 +2798,7 @@ nvswitch_is_inforom_supported_ls10 { NVSWITCH_PRINT(device, INFO, "INFOROM is not supported since SOE is not supported\n"); - return NV_FALSE; + return NV_FALSE; } status = _nvswitch_get_bios_version(device, &version); @@ -2805,8 +2806,8 @@ nvswitch_is_inforom_supported_ls10 { NVSWITCH_PRINT(device, ERROR, "%s: Error getting BIOS version\n", __FUNCTION__); - return NV_FALSE; - } + return NV_FALSE; +} if (version >= NVSWITCH_IFR_MIN_BIOS_VER_LS10) { @@ -2848,14 +2849,21 @@ nvswitch_is_smbpbi_supported_ls10 nvswitch_device *device ) { - NvU64 version; - NvlStatus status; - if (!nvswitch_is_smbpbi_supported_lr10(device)) { return NV_FALSE; } + // + // Temporary driver WAR to disable SMBPBI on the LS10 NVSwitch driver. + // This should be removed once 3875091 is resolved. + // + return NV_FALSE; + +#if 0 + NvU64 version; + NvlStatus status; + status = _nvswitch_get_bios_version(device, &version); if (status != NVL_SUCCESS) { @@ -2874,6 +2882,7 @@ nvswitch_is_smbpbi_supported_ls10 "SMBPBI is not supported on NVSwitch BIOS version %llx.\n", version); return NV_FALSE; } +#endif } /* @@ -2906,8 +2915,17 @@ NvlStatus nvswitch_get_link_public_id_ls10 NvU32 *publicId ) { - NVSWITCH_PRINT(device, WARN, "%s: Function not implemented\n", __FUNCTION__); - return -NVL_ERR_NOT_IMPLEMENTED; + if (!device->hal.nvswitch_is_link_valid(device, linkId) || + (publicId == NULL)) + { + return -NVL_BAD_ARGS; + } + + *publicId = NVSWITCH_NVLIPT_GET_PUBLIC_ID_LS10(linkId); + + + return (NVSWITCH_ENG_VALID_LS10(device, NVLIPT, *publicId)) ? + NVL_SUCCESS : -NVL_BAD_ARGS; } /* @@ -4920,7 +4938,7 @@ nvswitch_launch_ALI_ls10 } nvswitch_launch_ALI_link_training(device, link, NV_FALSE); - } + } FOR_EACH_INDEX_IN_MASK_END; return NVL_SUCCESS; @@ -5047,29 +5065,29 @@ nvswitch_set_training_mode_ls10 { regVal = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, NVLIPT_LNK, _NVLIPT_LNK, - _CTRL_CAP_LOCAL_LINK_CHANNEL); + _CTRL_CAP_LOCAL_LINK_CHANNEL); - if (!FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_CAP_LOCAL_LINK_CHANNEL, _ALI_SUPPORT, _SUPPORTED, regVal)) - { - NVSWITCH_PRINT(device, ERROR, - "%s: ALI training not supported! Non-ALI will be used as the default.\n",__FUNCTION__); + if (!FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_CAP_LOCAL_LINK_CHANNEL, _ALI_SUPPORT, _SUPPORTED, regVal)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: ALI training not supported! Non-ALI will be used as the default.\n",__FUNCTION__); #ifdef INCLUDE_NVLINK_LIB device->nvlink_device->enableALI = NV_FALSE; #endif - return NVL_SUCCESS; - } + return NVL_SUCCESS; + } #ifdef INCLUDE_NVLINK_LIB device->nvlink_device->enableALI = NV_TRUE; #endif - } + } else { - NVSWITCH_PRINT(device, ERROR, + NVSWITCH_PRINT(device, ERROR, "%s: ALI training not enabled! Non-ALI will be used as the default.\n",__FUNCTION__); #ifdef INCLUDE_NVLINK_LIB - device->nvlink_device->enableALI = NV_FALSE; + device->nvlink_device->enableALI = NV_FALSE; #endif - return NVL_SUCCESS; + return NVL_SUCCESS; } } FOR_EACH_INDEX_IN_MASK_END; @@ -5567,7 +5585,7 @@ nvswitch_ctrl_set_nvlink_error_threshold_ls10 // Configure the interrupt nvswitch_configure_error_rate_threshold_interrupt_ls10(link, - link->errorThreshold.bInterruptEn); + pParams->errorThreshold[link->linkNumber].bInterruptEn); } } FOR_EACH_INDEX_IN_MASK_END; @@ -5593,6 +5611,9 @@ nvswitch_ctrl_get_nvlink_error_threshold_ls10 continue; } + // Get the Error threshold + nvswitch_get_error_rate_threshold_ls10(link); + pParams->errorThreshold[link->linkNumber].thresholdMan = link->errorThreshold.thresholdMan; pParams->errorThreshold[link->linkNumber].thresholdExp = diff --git a/src/common/nvswitch/kernel/ls10/soe_ls10.c b/src/common/nvswitch/kernel/ls10/soe_ls10.c index 8a4b50047..6e43c21a2 100644 --- a/src/common/nvswitch/kernel/ls10/soe_ls10.c +++ b/src/common/nvswitch/kernel/ls10/soe_ls10.c @@ -31,6 +31,7 @@ #include "common_nvswitch.h" #include "ls10/ls10.h" #include "ls10/soe_ls10.h" +#include "lr10/soe_lr10.h" #include "nvswitch/ls10/dev_soe_ip.h" #include "nvswitch/ls10/dev_soe_ip_addendum.h" @@ -39,9 +40,6 @@ #include "nvswitch/ls10/dev_nvlsaw_ip_addendum.h" #include "nvswitch/ls10/dev_riscv_pri.h" -#include "nvswitch/ls10/dev_nport_ip.h" -#include "nvswitch/ls10/dev_npg_ip.h" - #include "flcn/flcnable_nvswitch.h" #include "flcn/flcn_nvswitch.h" #include "rmflcncmdif_nvswitch.h" @@ -182,7 +180,7 @@ dumpDebugRegisters NVSWITCH_PRINT(device, ERROR, "RESET_PLM : 0x%08x\n", regRESET_PLM); NVSWITCH_PRINT(device, ERROR, "EXE_PLM : 0x%08x\n", regEXE_PLM); } -#endif // defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS) +#endif // defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS) /* * @Brief : Attach or Detach driver to SOE Queues @@ -232,7 +230,12 @@ _nvswitch_is_soe_attached_ls10 return FLD_TEST_DRF(_NVLSAW, _SOE_ATTACH_DETACH, _STATUS, _ATTACHED, val); } -// BACK UP Nport state and reset NPORT +/* + * @Brief : Backup NPORT state and issue NPORT reset + * + * @param[in] device + * @param[in] nport + */ NvlStatus nvswitch_soe_issue_nport_reset_ls10 ( @@ -240,7 +243,7 @@ nvswitch_soe_issue_nport_reset_ls10 NvU32 nport ) { - FLCN *pFlcn = device->pSoe->pFlcn; + FLCN *pFlcn = device->pSoe->pFlcn; NvU32 cmdSeqDesc = 0; NV_STATUS status; RM_FLCN_CMD_SOE cmd; @@ -256,7 +259,7 @@ nvswitch_soe_issue_nport_reset_ls10 pNportReset->nport = nport; pNportReset->cmdType = RM_SOE_CORE_CMD_ISSUE_NPORT_RESET; - nvswitch_timeout_create(NVSWITCH_INTERVAL_1SEC_IN_NS * 5, &timeout); + nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout); status = flcnQueueCmdPostBlocking(device, pFlcn, (PRM_FLCN_CMD)&cmd, NULL, // pMsg @@ -274,7 +277,12 @@ nvswitch_soe_issue_nport_reset_ls10 return NVL_SUCCESS; } -// De-reset NPORT and restore NPORT state +/* + * @Brief : De-Assert NPORT reset and restore NPORT state + * + * @param[in] device + * @param[in] nport + */ NvlStatus nvswitch_soe_restore_nport_state_ls10 ( @@ -292,13 +300,13 @@ nvswitch_soe_restore_nport_state_ls10 nvswitch_os_memset(&cmd, 0, sizeof(cmd)); cmd.hdr.unitId = RM_SOE_UNIT_CORE; - cmd.hdr.size = sizeof(cmd); + cmd.hdr.size = RM_SOE_CMD_SIZE(CORE, NPORT_STATE); pNportState = &cmd.cmd.core.nportState; pNportState->nport = nport; pNportState->cmdType = RM_SOE_CORE_CMD_RESTORE_NPORT_STATE; - nvswitch_timeout_create(NVSWITCH_INTERVAL_1SEC_IN_NS * 5, &timeout); + nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout); status = flcnQueueCmdPostBlocking(device, pFlcn, (PRM_FLCN_CMD)&cmd, NULL, // pMsg @@ -336,17 +344,10 @@ nvswitch_set_nport_tprod_state_ls10 NVSWITCH_TIMEOUT timeout; RM_SOE_CORE_CMD_NPORT_TPROD_STATE *nportTprodState; - if (!NVSWITCH_ENG_IS_VALID(device, NPORT, nport)) - { - NVSWITCH_PRINT(device, ERROR, "%s: NPORT #%d invalid\n", - __FUNCTION__, nport); - return -NVL_BAD_ARGS; - } - nvswitch_os_memset(&cmd, 0, sizeof(cmd)); cmd.hdr.unitId = RM_SOE_UNIT_CORE; - cmd.hdr.size = RM_SOE_CMD_SIZE(CORE, NPORT_STATE); + cmd.hdr.size = sizeof(cmd); nportTprodState = &cmd.cmd.core.nportTprodState; nportTprodState->nport = nport; @@ -391,7 +392,7 @@ nvswitch_soe_init_l2_state_ls10 if (!nvswitch_is_soe_supported(device)) { - NVSWITCH_PRINT(device, INFO, "%s: SOE is not supported. skipping!\n", + NVSWITCH_PRINT(device, INFO, "%s: SOE is not supported\n", __FUNCTION__); return; } @@ -420,6 +421,7 @@ nvswitch_soe_init_l2_state_ls10 } } + /* * @Brief : Init sequence for SOE FSP RISCV image * @@ -529,7 +531,6 @@ nvswitch_unload_soe_ls10 // Detach driver from SOE Queues _nvswitch_soe_attach_detach_driver_ls10(device, NV_FALSE); - return NVL_SUCCESS; } @@ -554,7 +555,7 @@ nvswitch_soe_register_event_callbacks_ls10 device, pFlcn, RM_SOE_UNIT_THERM, NULL, - nvswitch_therm_soe_callback_ls10, + nvswitch_therm_soe_callback_lr10, NULL, &pSoe->thermEvtDesc); if (status != NV_OK) diff --git a/src/common/nvswitch/kernel/ls10/therm_ls10.c b/src/common/nvswitch/kernel/ls10/therm_ls10.c index e4081ca43..e2c546e20 100644 --- a/src/common/nvswitch/kernel/ls10/therm_ls10.c +++ b/src/common/nvswitch/kernel/ls10/therm_ls10.c @@ -28,7 +28,6 @@ #include "ls10/therm_ls10.h" #include "error_nvswitch.h" #include "soe/soeiftherm.h" -#include "rmflcncmdif_nvswitch.h" #include "flcn/flcnable_nvswitch.h" #include "flcn/flcn_nvswitch.h" @@ -362,103 +361,6 @@ nvswitch_monitor_thermal_alert_ls10 return; } -/* - * @brief Callback function to recieve thermal messages from SOE. - */ -void -nvswitch_therm_soe_callback_ls10 -( - nvswitch_device *device, - RM_FLCN_MSG *pGenMsg, - void *pParams, - NvU32 seqDesc, - NV_STATUS status -) -{ - RM_SOE_THERM_MSG_SLOWDOWN_STATUS slowdown_status; - RM_SOE_THERM_MSG_SHUTDOWN_STATUS shutdown_status; - RM_FLCN_MSG_SOE *pMsg = (RM_FLCN_MSG_SOE *)pGenMsg; - NvU32 temperature; - NvU32 threshold; - - switch (pMsg->msg.soeTherm.msgType) - { - case RM_SOE_THERM_MSG_ID_SLOWDOWN_STATUS: - { - slowdown_status = pMsg->msg.soeTherm.slowdown; - if (slowdown_status.bSlowdown) - { - if (slowdown_status.source.bTsense) // TSENSE_THERM_ALERT - { - temperature = RM_SOE_NV_TEMP_TO_CELSIUS_TRUNCED(slowdown_status.maxTemperature); - threshold = RM_SOE_NV_TEMP_TO_CELSIUS_TRUNCED(slowdown_status.warnThreshold); - - NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_THERMAL_EVENT_START, - "NVSWITCH Temperature %dC | TSENSE WARN Threshold %dC\n", - temperature, threshold); - - NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_THERMAL_EVENT_START, - "Thermal Slowdown Engaged | Temp higher than WARN Threshold\n"); - } - - NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_THERMAL_EVENT_START, - "Thermal Slowdown Engaged | Links Thermal Mode %s\n", (slowdown_status.bLinksL1Status ? "ON" : "OFF")); - - if (slowdown_status.source.bPmgr) // PMGR_THERM_ALERT - { - NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_THERMAL_EVENT_START, - "Thermal Slowdown Engaged | PMGR WARN Threshold reached\n"); - } - } - else // REVERT_SLOWDOWN - { - temperature = RM_SOE_NV_TEMP_TO_CELSIUS_TRUNCED(slowdown_status.maxTemperature); - threshold = RM_SOE_NV_TEMP_TO_CELSIUS_TRUNCED(slowdown_status.warnThreshold); - - NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_THERMAL_EVENT_END, - "NVSWITCH Temperature %dC | TSENSE WARN Threshold %dC\n", - temperature, threshold); - - NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_THERMAL_EVENT_END, - "Thermal Slowdown Disengaged | Links Thermal Mode %s\n", (slowdown_status.bLinksL1Status ? "ON" : "OFF")); - - NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_THERMAL_EVENT_END, - "Thermal slowdown Disengaged\n"); - } - break; - } - - case RM_SOE_THERM_MSG_ID_SHUTDOWN_STATUS: - { - shutdown_status = pMsg->msg.soeTherm.shutdown; - if (shutdown_status.source.bTsense) // TSENSE_THERM_SHUTDOWN - { - temperature = RM_SOE_NV_TEMP_TO_CELSIUS_TRUNCED(shutdown_status.maxTemperature); - threshold = RM_SOE_NV_TEMP_TO_CELSIUS_TRUNCED(shutdown_status.overtThreshold); - - NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_THERMAL_SHUTDOWN, - "NVSWITCH Temperature %dC | OVERT Threshold %dC\n", - temperature, threshold); - - NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_THERMAL_SHUTDOWN, - "TSENSE OVERT Threshold reached. Shutting Down\n"); - } - - if (shutdown_status.source.bPmgr) // PMGR_THERM_SHUTDOWN - { - NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_THERMAL_EVENT_START, - "PMGR OVERT Threshold reached. Shutting Down\n"); - } - break; - } - default: - { - NVSWITCH_PRINT(device, ERROR, "%s Unknown message Id\n", __FUNCTION__); - NVSWITCH_ASSERT(0); - } - } -} - // // nvswitch_therm_read_voltage // diff --git a/src/common/nvswitch/kernel/nvswitch.c b/src/common/nvswitch/kernel/nvswitch.c index 0d9d3f310..4b5856f12 100644 --- a/src/common/nvswitch/kernel/nvswitch.c +++ b/src/common/nvswitch/kernel/nvswitch.c @@ -5080,3 +5080,21 @@ nvswitch_lib_ctrl return retval; } + +#if defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS) +void nvswitch_assert_log +( + const char *function, + const char *file, + NvU32 line +) +{ + nvswitch_os_assert_log("NVSwitch: Assertion failed in %s() at %s:%d\n", + function, file, line); +} +#else +void nvswitch_assert_log(void) +{ + nvswitch_os_assert_log("NVSwitch: Assertion failed\n"); +} +#endif diff --git a/src/common/sdk/nvidia/inc/class/cl00c2.h b/src/common/sdk/nvidia/inc/class/cl00c2.h index ef2d16823..a5597c56e 100644 --- a/src/common/sdk/nvidia/inc/class/cl00c2.h +++ b/src/common/sdk/nvidia/inc/class/cl00c2.h @@ -34,8 +34,8 @@ #define NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS_MESSAGE_ID (0x00c2U) typedef struct NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS { - NV_DECLARE_ALIGNED(NvU64 memSize, 8); // [OUT] + NV_DECLARE_ALIGNED(NvU64 memSize, 8); // [OUT] NvU32 format; // [IN] - PTE format to use - NvU32 pageSize; // [IN] - Page size to use + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); // [IN] - Page size to use } NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS; diff --git a/src/common/sdk/nvidia/inc/class/cl00de.h b/src/common/sdk/nvidia/inc/class/cl00de.h index 8c772ef51..8d90d9d8a 100644 --- a/src/common/sdk/nvidia/inc/class/cl00de.h +++ b/src/common/sdk/nvidia/inc/class/cl00de.h @@ -35,6 +35,8 @@ typedef struct NV00DE_SHARED_DATA { NvU32 bar1Size; NvU32 bar1AvailSize; + + NvU32 gspAssertCount; // New data members always add to bottom } NV00DE_SHARED_DATA; diff --git a/src/common/sdk/nvidia/inc/class/cl2080_notification.h b/src/common/sdk/nvidia/inc/class/cl2080_notification.h index b06b5be35..81dff11b5 100644 --- a/src/common/sdk/nvidia/inc/class/cl2080_notification.h +++ b/src/common/sdk/nvidia/inc/class/cl2080_notification.h @@ -200,8 +200,9 @@ extern "C" { #define NV2080_NOTIFIERS_POSSIBLE_ERROR (164) #define NV2080_NOTIFIERS_NVLINK_INFO_LINK_UP (165) #define NV2080_NOTIFIERS_NVLINK_INFO_LINK_DOWN (176) -#define NV2080_NOTIFIERS_HDMI_FRL_RETRAINING_REQUEST (177) -#define NV2080_NOTIFIERS_MAXCOUNT (178) +#define NV2080_NOTIFIERS_NVPCF_EVENTS (177) +#define NV2080_NOTIFIERS_HDMI_FRL_RETRAINING_REQUEST (178) +#define NV2080_NOTIFIERS_MAXCOUNT (179) // Indexed GR notifier reference #define NV2080_NOTIFIERS_GR(x) ((x == 0) ? (NV2080_NOTIFIERS_GR0) : (NV2080_NOTIFIERS_GR1 + (x - 1))) diff --git a/src/common/sdk/nvidia/inc/class/clc763.h b/src/common/sdk/nvidia/inc/class/clc763.h new file mode 100644 index 000000000..eb70baa79 --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/clc763.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc763_h_ +#define _clc763_h_ + +#define MMU_VIDMEM_ACCESS_BIT_BUFFER (0xc763) + +#endif /* _clc763_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h index 3ce0f06f3..f62b504d6 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -90,6 +90,11 @@ typedef struct NV0000_CTRL_GPU_GET_ID_INFO_PARAMS { NvS32 numaId; } NV0000_CTRL_GPU_GET_ID_INFO_PARAMS; +#define NV0000_CTRL_SLI_STATUS_OK (0x00000000U) +#define NV0000_CTRL_SLI_STATUS_OS_NOT_SUPPORTED (0x00000002U) +#define NV0000_CTRL_SLI_STATUS_GPU_NOT_SUPPORTED (0x00000040U) +#define NV0000_CTRL_SLI_STATUS_INVALID_GPU_COUNT (0x00000001U) + /* * NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 * This command returns GPU instance information for the specified GPU. @@ -149,7 +154,7 @@ typedef struct NV0000_CTRL_GPU_GET_ID_INFO_PARAMS { -#define NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 (0x205U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 (0x205U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID (0x5U) @@ -436,6 +441,55 @@ typedef struct NV0000_CTRL_GPU_DETACH_IDS_PARAMS { +/* + * NV0000_CTRL_CMD_GPU_GET_VIDEO_LINKS + * + * This command returns information about video bridge connections + * detected between GPUs in the system, organized as a table + * with one row per attached GPU and none, one or more peer GPUs + * listed in the columns of each row, if connected to the row head + * GPU via a video bridge. + * + * gpuId + * For each row, this field holds the GPU ID of the GPU + * whose connections are listed in the row. + * + * connectedGpuIds + * For each row, this table holds the GPU IDs of the + * GPUs connected to the GPU identified via the 'gpuId' + * field. + * + * links + * This table holds information about the video bridges + * connected between GPUs in the system. Each row + * represents connections to a single GPU. + * + * Please note: the table only reports video links between already + * attached GPUs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_GPU_GET_VIDEO_LINKS (0x219U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_MAX_VIDEO_LINKS 8U + +typedef struct NV0000_CTRL_GPU_VIDEO_LINKS { + NvU32 gpuId; + NvU32 connectedGpuIds[NV0000_CTRL_GPU_MAX_VIDEO_LINKS]; +} NV0000_CTRL_GPU_VIDEO_LINKS; + +#define NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS { + NV0000_CTRL_GPU_VIDEO_LINKS links[NV0000_CTRL_GPU_MAX_ATTACHED_GPUS]; +} NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS; + + + /* * NV0000_CTRL_CMD_GPU_GET_SVM_SIZE * @@ -869,5 +923,60 @@ typedef struct NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS { NV_DECLARE_ALIGNED(NvU64 totalSize, 8); NV_DECLARE_ALIGNED(NvP64 pData, 8); } NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_SET_NVLINK_BW_MODE + * + * This command is used to set NVLINK bandwidth for power saving + * + * The setting must be applied before the GPU is attached. + * NVLINK_BW_MODE is an NOP for non-NVLink GPUs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_DEVICE + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_INVALID_STATE + * NV_ERR_IN_USE + */ + +#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_FULL (0x00U) +#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_OFF (0x01U) +#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_MIN (0x02U) +#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_HALF (0x03U) +#define NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_3QUARTER (0x04U) + +#define NV0000_CTRL_CMD_GPU_SET_NVLINK_BW_MODE (0x286U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID (0x86U) + +typedef struct NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS { + NvU8 mode; +} NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_GET_NVLINK_BW_MODE + * + * This command is used to get NVLINK bandwidth for power saving + * + * The setting must be applied before the GPU is attached. + * NVLINK_BW_MODE is an NOP for non-NVLink GPUs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_DEVICE + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_INVALID_STATE + * NV_ERR_IN_USE + */ + +#define NV0000_CTRL_CMD_GPU_GET_NVLINK_BW_MODE (0x287U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID (0x87U) + +typedef struct NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS { + NvU8 mode; +} NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS; + /* _ctrl0000gpu_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h index 7f35670e5..c98c725de 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h @@ -296,7 +296,8 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS { /* Generic types */ #define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC (0xA00FF000U) -#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV9A_GENERIC (0xA00FF001U) + + /* processor capabilities */ #define NV0000_CTRL_SYSTEM_CPU_CAP_MMX (0x00000001U) @@ -1583,9 +1584,17 @@ typedef struct NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS { NvU32 counterBlock[GPS_MAX_COUNTERS_PER_BLOCK]; } NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS; -#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_PERF_SENSORS (0x12cU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x2C" */ +#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_PERF_SENSORS (0x12cU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS_MESSAGE_ID" */ -#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS (0x12eU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x2E" */ +#define NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS_MESSAGE_ID (0x2CU) + +typedef NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS; + +#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS (0x12eU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID (0x2EU) + +typedef NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS; /* * NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI @@ -1621,7 +1630,7 @@ typedef struct NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS { * NV_ERR_INSUFFICIENT_PERMISSIONS * */ -#define GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE 288U +#define GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE 288U #define NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID (0x2DU) typedef struct NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS { @@ -2855,9 +2864,17 @@ typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS NvU32 counterBlock[PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK]; } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS; -#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS (0x146U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x46" */ +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS (0x146U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS_MESSAGE_ID" */ -#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS (0x147U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x47" */ +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS_MESSAGE_ID (0x46U) + +typedef NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS; + +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS (0x147U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID (0x47U) + +typedef NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS; /* * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI @@ -2893,7 +2910,7 @@ typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS * NV_ERR_INSUFFICIENT_PERMISSIONS * */ -#define PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE 288U +#define PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE 288U #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID (0x43U) typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS { diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0041.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0041.h index 322393d9b..8d9da81ff 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0041.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0041.h @@ -201,10 +201,7 @@ typedef struct NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS { * This index is used to request the surface address space type. * Returned values are described by NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE. */ -typedef struct NV0041_CTRL_SURFACE_INFO { - NvU32 index; - NvU32 data; -} NV0041_CTRL_SURFACE_INFO; +typedef NVXXXX_CTRL_XXX_INFO NV0041_CTRL_SURFACE_INFO; /* valid surface info index values */ #define NV0041_CTRL_SURFACE_INFO_INDEX_ATTRS (0x00000001) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073.h index fa7d8f7eb..6b2df39d2 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073.h @@ -43,3 +43,4 @@ #include "ctrl0073/ctrl0073svp.h" #include "ctrl0073/ctrl0073dpu.h" #include "ctrl0073/ctrl0073psr.h" +#include "ctrl0073/ctrl0073common.h" diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h index 970ea3b97..3712f9f9d 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h @@ -39,6 +39,7 @@ #define NV0073_CTRL_SPECIFIC (0x02U) #define NV0073_CTRL_EVENT (0x03U) #define NV0073_CTRL_INTERNAL (0x04U) +#define NV0073_CTRL_COMMON (0x05U) #define NV0073_CTRL_DFP (0x11U) #define NV0073_CTRL_DP (0x13U) #define NV0073_CTRL_SVP (0x14U) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073common.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073common.h new file mode 100644 index 000000000..374cbb5b3 --- /dev/null +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073common.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl0073/ctrl0073common.finn +// + + + +/* _ctrl0073common_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h index 347b478e7..207a85910 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h @@ -465,7 +465,7 @@ typedef struct NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS { /* * NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG * - * This enum defines default/primary/secondary sor sublinks to be configured. + * This variable specifies default/primary/secondary sor sublinks to be configured. * These access modes are: * * NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_NONE @@ -475,11 +475,11 @@ typedef struct NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS { * NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_SECONDARY_SOR_LINK * Secondary sor sublink to be configured */ -typedef enum NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG { - NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_NONE = 0, - NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_PRIMARY_SOR_LINK = 1, - NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_SECONDARY_SOR_LINK = 2, -} NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG; +typedef NvU32 NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG; + +#define NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_NONE (0x0U) +#define NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_PRIMARY_SOR_LINK (0x1U) +#define NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_SECONDARY_SOR_LINK (0x2U) /* * NV0073_CTRL_DFP_ASSIGN_SOR_INFO diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h index e593227b3..16da22d17 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h @@ -728,7 +728,11 @@ typedef struct NV0073_CTRL_DP_LANE_DATA_PARAMS { * */ -#define NV0073_CTRL_CMD_DP_GET_LANE_DATA (0x731345U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | 0x45" */ +#define NV0073_CTRL_CMD_DP_GET_LANE_DATA (0x731345U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_LANE_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_GET_LANE_DATA_PARAMS_MESSAGE_ID (0x45U) + +typedef NV0073_CTRL_DP_LANE_DATA_PARAMS NV0073_CTRL_DP_GET_LANE_DATA_PARAMS; /* @@ -755,7 +759,11 @@ typedef struct NV0073_CTRL_DP_LANE_DATA_PARAMS { * */ -#define NV0073_CTRL_CMD_DP_SET_LANE_DATA (0x731346U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | 0x46" */ +#define NV0073_CTRL_CMD_DP_SET_LANE_DATA (0x731346U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_LANE_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_SET_LANE_DATA_PARAMS_MESSAGE_ID (0x46U) + +typedef NV0073_CTRL_DP_LANE_DATA_PARAMS NV0073_CTRL_DP_SET_LANE_DATA_PARAMS; /* * NV0073_CTRL_DP_CSTM @@ -2764,4 +2772,45 @@ typedef struct NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS { NvBool bDebugValues; NV0073_CTRL_DP_MSA_PROPERTIES_VALUES featureDebugValues; } NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS; + +/* + * NV0073_CTRL_CMD_DP_EXECUTE_OVERDRIVE_POLICY + * + * This command is used to execute RM Over Drive policy and decide if TCON Overdrive needs to be enabled + * or not based on the panel Overdrive grade determined using the panel manufId and prodId. + * + * subDeviceInstance [in] + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * displayId [in] + * This parameter specifies the ID of the eDP display which owns + * the Main Link to be adjusted. The display ID must a eDP display + * as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command. + * If more than one displayId bit is set or the displayId is not an eDP, + * this call will return NV_ERR_INVALID_ARGUMENT. + * manfId [in] + * This parameter is an input to this command which tells the + * Internal panel's manufacturer ID. + * prodId [in] + * This parameter is an input to this command which tells the + * Internal panel's product ID. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_DP_EXECUTE_OVERDRIVE_POLICY (0x731382U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS_MESSAGE_ID (0x82U) + +typedef struct NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU16 manfId; + NvU16 prodId; +} NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS; /* _ctrl0073dp_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h index 2b4965d45..b4c3764f9 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h @@ -31,17 +31,10 @@ #include "ctrl/ctrl0073/ctrl0073base.h" #include "ctrl/ctrl0073/ctrl0073system.h" -#define NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE (0x730401U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_FINN_PARAMS_MESSAGE_ID" */ +#define NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE (0x730401U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_PARAMS_MESSAGE_ID" */ +#define NV0073_CTRL_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_PARAMS_MESSAGE_ID (0x1U) -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_FINN_PARAMS_MESSAGE_ID (0x1U) - -typedef struct NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_FINN_PARAMS { - NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS params; -} NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_FINN_PARAMS; - +typedef NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS NV0073_CTRL_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_PARAMS; /* ctrl0073internal_h */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073psr.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073psr.h index 7ac6f6e3f..6b34b2460 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073psr.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073psr.h @@ -30,3 +30,41 @@ // Source file: ctrl/ctrl0073/ctrl0073psr.finn // +#include "ctrl/ctrl0073/ctrl0073base.h" + + + +/* + * NV0073_CTRL_CMD_PSR_GET_SR_PANEL_INFO + * + * displayId + * Display ID on which this information is being requested. + * frameLockPin + * Returns the frame lock pin of the panel. + * i2cAddress + * Returns the i2c address on which the SR panel is attached. + * NOTE: applies only to LVDS panels, otherwise this field + * should be ignored. + * bSelfRefreshEnabled + * Returns whether SR is enabled in RM. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0073_CTRL_CMD_PSR_GET_SR_PANEL_INFO (0x731602U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_PSR_INTERFACE_ID << 8) | NV0073_CTRL_PSR_GET_SR_PANEL_INFO_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_PSR_GET_SR_PANEL_INFO_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0073_CTRL_PSR_GET_SR_PANEL_INFO_PARAMS { + NvU32 displayId; + NvU32 frameLockPin; + NvU8 i2cAddress; + NvBool bSelfRefreshEnabled; +} NV0073_CTRL_PSR_GET_SR_PANEL_INFO_PARAMS; + + + +/* _ctrl0073psr_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h index 74ace22cc..6b7d8433a 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h @@ -546,6 +546,44 @@ typedef struct NV0073_CTRL_SPECIFIC_CTRL_HDMI_PARAMS { #define NV0073_CTRL_SPECIFIC_CTRL_HDMI_DISABLE (0x00000000U) #define NV0073_CTRL_SPECIFIC_CTRL_HDMI_ENABLE (0x00000001U) +/* + * NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM + * + * This command is used to signal the resource manager that the audio stream + * is to be mute off or on. + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which operation should be directed. + * This parameter must specify a value between zero and the total number + * of subdevices within the parent device. This parameter should be set + * to zero for default behavior. + * displayId + * This parameter specifies the displayId of HDMI resource to configure. + * This comes as input to this command. + * mute + * This field specifies the legal values: + * NV0073_CTRL_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_TRUE + * NV0073_CTRL_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_FALSE + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM (0x730275U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID (0x75U) + +typedef struct NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS { + NvU8 subDeviceInstance; + NvU32 displayId; + NvU8 mute; +} NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS; + +#define NV0073_CTRL_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_FALSE (0x00000000U) +#define NV0073_CTRL_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_TRUE (0x00000001U) + /* @@ -1132,19 +1170,28 @@ typedef struct NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV0073_CTRL_CMD_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS (0x730291U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | 0x91" */ - -#define NV0073_CTRL_CMD_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS (0x730292U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | 0x92" */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS (0x730291U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS_PARAMS_MESSAGE_ID" */ #define NV0073_CTRL_BACKLIGHT_BRIGHTNESS_MIN_VALUE 0U #define NV0073_CTRL_BACKLIGHT_BRIGHTNESS_MAX_VALUE 100U typedef struct NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS { - NvU32 subDeviceInstance; - NvU32 displayId; - NvU32 brightness; + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 brightness; + NvBool bUncalibrated; } NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS; +#define NV0073_CTRL_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS_PARAMS_MESSAGE_ID (0x91U) + +typedef NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS NV0073_CTRL_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS_PARAMS; + +#define NV0073_CTRL_CMD_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS (0x730292U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS_PARAMS_MESSAGE_ID (0x92U) + +typedef NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS NV0073_CTRL_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS_PARAMS; + /* * NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS * @@ -1329,7 +1376,7 @@ typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_FRL_LINK_CONFIG_PARAMS { -#define NV0073_CTRL_SPECIFIC_MAX_CRC_REGIONS 9U +#define NV0073_CTRL_SPECIFIC_MAX_CRC_REGIONS 9U #define NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS_PARAMS_MESSAGE_ID (0xA0U) @@ -1906,4 +1953,30 @@ typedef struct NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS { NvU8 windowHeadMask[NV0073_CTRL_SPECIFIC_MAX_WINDOWS]; } NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS; +/* + * NV0073_CTRL_CMD_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY + * + * This command is used to query whether the specified monitor should default + * to adaptive sync. + * + * [in]manufacturerID + * This parameter specifies the 16-bit EDID Manufacturer ID. + * [in]productID + * This parameter specifies the 16-bit EDID Product ID. + * [out]bDefaultAdaptivesync; + * This indicates whether the monitor should default to adaptive sync. + * Possible return values: + * NV_OK + */ + +#define NV0073_CTRL_CMD_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY (0x7302aeU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS_MESSAGE_ID (0xAEU) + +typedef struct NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS { + NvU16 manufacturerID; + NvU16 productID; + NvBool bDefaultAdaptivesync; +} NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS; + /* _ctrl0073specific_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h index 9a585aa57..d1bfd271e 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h @@ -34,6 +34,41 @@ +/* + * NV0073_CTRL_CMD_STEREO_DONGLE_SUPPORTED + * + * This command returns the support status of the NV stereo emitter + * (also known as the stereo dongle). It reports if the stereo dongle + * is present in terms of the USB interface initialized in Resman. + * This provides a RmControl interface to the STEREO_DONGLE_SUPPORTED + * command in stereoDongleControl. + * + * Parameters: + * [IN] subDeviceInstance - This parameter specifies the subdevice instance + * within the NV04_DISPLAY_COMMON parent device to which the operation + * should be directed. This parameter must specify a value between + * zero and the total number of subdevices within the parent device. + * This parameter should be set to zero for default behavior. + * [IN] head - head to be passed to stereoDongleControl + * [IN] bI2cEmitter - I2C driven DT embedded emitter + * [IN] bForcedSupported - GPIO23 driven emitter + * [OUT] support - the control word returned by stereoDongleControl + * + * Possible status values returned are: + * NV_ERR_NOT_SUPPORTED - stereo is not initialized on the GPU + */ +#define NV0073_CTRL_CMD_STEREO_DONGLE_SUPPORTED (0x731702U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID << 8) | NV0073_CTRL_STEREO_DONGLE_SUPPORTED_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_STEREO_DONGLE_SUPPORTED_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0073_CTRL_STEREO_DONGLE_SUPPORTED_PARAMS { + NvU32 subDeviceInstance; + NvU32 head; + NvBool bI2cEmitter; + NvBool bForcedSupported; + NvU32 support; +} NV0073_CTRL_STEREO_DONGLE_SUPPORTED_PARAMS; + /* * NV0073_CTRL_CMD_STEREO_DONGLE_SET_TIMINGS * diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h index d25501a34..a011bb4f8 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h @@ -468,8 +468,62 @@ typedef struct NV0073_CTRL_SYSTEM_GET_SET_HOTPLUG_CONFIG_PARAMS { NvU32 hotplugAlwaysAttached; } NV0073_CTRL_SYSTEM_GET_SET_HOTPLUG_CONFIG_PARAMS; +/* + * NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_STATE + * + * This command can be used to retrieve dynamic hotplug state information that + * are currently recorded by the RM. This information can be used by the client + * to determine which displays to detect after a hotplug event occurs. Or if + * the client knows that this device generates a hot plug/unplug signal on all + * connectors, then this can be used to cull displays from detection. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * flags + * This parameter specifies optional flags to be used while retrieving + * the hotplug state information. + * Here are the current defined fields: + * NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID + * A client uses this field to determine the lid state. + * Possible values are: + * NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID_OPEN + * The lid is open. + * NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID_CLOSED + * The lid is closed. The client should remove devices as + * reported inside the + * NV0073_CTRL_SYSTEM_GET_CONNECT_POLICY_PARAMS.lidClosedMask. + * hotplugAfterEdidMask + * This display mask specifies an NV0073_DISPLAY_MASK value describing + * the set of displays that have seen a hotplug or hotunplug event + * sometime after the last valid EDID read. If the device never has + * a valid EDID read, then it will always be listed here. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_STATE (0x730124U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS_MESSAGE_ID (0x24U) + +typedef struct NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS { + NvU32 subDeviceInstance; + NvU32 flags; + NvU32 hotplugAfterEdidMask; +} NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS; + +/* valid get hoplug state flags */ +#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID 0:0 +#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID_OPEN (0x00000000U) +#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_FLAGS_LID_CLOSED (0x00000001U) + /* * NV0073_CTRL_CMD_SYSTEM_GET_HEAD_ROUTING_MAP * @@ -756,6 +810,136 @@ typedef struct NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS { } NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS; +/* + * NV0073_CTRL_SYSTEM_CONNECTOR_INFO + * + * This structure describes a single connector table entry. + * + * type + * This field specifies the connector type. + * displayMask + * This field specifies the the displayMask to which the connector belongs. + * location + * This field specifies the placement of the connector on the platform. + * hotplug + * This field specifies hotplug capabilities (if any) for the connector. + */ +typedef struct NV0073_CTRL_SYSTEM_CONNECTOR_INFO { + NvU32 type; + NvU32 displayMask; + NvU32 location; + NvU32 hotplug; +} NV0073_CTRL_SYSTEM_CONNECTOR_INFO; + +/* valid type values */ +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_VGA_15_PIN (0x00000000U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_A (0x00000001U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_POD_VGA_15_PIN (0x00000002U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TV_COMPOSITE (0x00000010U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TV_SVIDEO (0x00000011U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TV_SVIDEO_BO_COMPOSITE (0x00000012U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TV_COMPONENT (0x00000013U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TV_SCART (0x00000014U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TV_SCART_EIAJ4120 (0x00000014U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TV_EIAJ4120 (0x00000017U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_PC_POD_HDTV_YPRPB (0x00000018U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_PC_POD_SVIDEO (0x00000019U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_PC_POD_COMPOSITE (0x0000001AU) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_I_TV_SVIDEO (0x00000020U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_I_TV_COMPOSITE (0x00000021U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_I_TV_SV_BO_COMPOSITE (0x00000022U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_I (0x00000030U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_D (0x00000031U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_ADC (0x00000032U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LFH_DVI_I_1 (0x00000038U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LFH_DVI_I_2 (0x00000039U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LFH_SVIDEO (0x0000003AU) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_BNC (0x0000003CU) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LVDS_SPWG (0x00000040U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LVDS_OEM (0x00000041U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LVDS_SPWG_DET (0x00000042U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LVDS_OEM_DET (0x00000043U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_TVDS_OEM_ATT (0x00000045U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_VGA_15_PIN_UNDOCKED (0x00000050U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_VGA_15_PIN_DOCKED (0x00000051U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_I_UNDOCKED (0x00000052U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_I_DOCKED (0x00000053U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_D_UNDOCKED (0x00000052U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DVI_D_DOCKED (0x00000053U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DP_EXT (0x00000056U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DP_INT (0x00000057U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DP_EXT_UNDOCKED (0x00000058U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_DP_EXT_DOCKED (0x00000059U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_3PIN_DIN_STEREO (0x00000060U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_HDMI_A (0x00000061U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_AUDIO_SPDIF (0x00000062U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_HDMI_C_MINI (0x00000063U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LFH_DP_1 (0x00000064U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_LFH_DP_2 (0x00000065U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_TYPE_VIRTUAL_WFD (0x00000070U) + +/* valid hotplug values */ +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_HOTPLUG_A_SUPPORTED (0x00000001U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_HOTPLUG_B_SUPPORTED (0x00000002U) + +/* + * Nv0073_CTRL_CMD_SYSTEM_GET_CONNECTOR_TABLE + * + * This command can be used to retrieve display connector information. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * version + * This parameter returns the version of the connector table. + * platform + * This parameter returns the type of platform of the associated subdevice. + * connectorTableEntries + * This parameter returns the number of valid entries in the connector + * table. + * connectorTable + * This parameter returns the connector information in the form of an + * array of NV0073_CTRL_SYSTEM_CONNECTOR_INFO structures. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * + */ +#define NV0073_CTRL_CMD_SYSTEM_GET_CONNECTOR_TABLE (0x730165U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS_MESSAGE_ID" */ + +/* maximum number of connector table entries */ +#define NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_MAX_ENTRIES (16U) + +#define NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS_MESSAGE_ID (0x65U) + +typedef struct NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS { + NvU32 subDeviceInstance; + NvU32 version; + NvU32 platform; + NvU32 connectorTableEntries; + /* + * C form: + * NV0073_CTRL_SYSTEM_CONNECTOR_INFO connectorTable[NV0073_CTRL_SYSTEM_CONNECTOR_TABLE_MAX_ENTRIES]; + */ + NV0073_CTRL_SYSTEM_CONNECTOR_INFO connectorTable[NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_MAX_ENTRIES]; +} NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS; + +/* valid version values */ +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_VERSION_30 (0x00000030U) + +/* valid platform values */ +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_DEFAULT_ADD_IN_CARD (0x00000000U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_TWO_PLATE_ADD_IN_CARD (0x00000001U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_MOBILE_ADD_IN_CARD (0x00000008U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_MXM_MODULE (0x00000009U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_MOBILE_BACK (0x00000010U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_MOBILE_BACK_LEFT (0x00000011U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_MOBILE_BACK_DOCK (0x00000018U) +#define NV0073_CTRL_SYSTEM_CONNECTOR_INFO_PLATFORM_CRUSH_DEFAULT (0x00000020U) /* * NV0073_CTRL_CMD_SYSTEM_GET_BOOT_DISPLAYS @@ -1090,7 +1274,9 @@ typedef struct NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS { * NV_ERR_INVALID_ARGUMENT */ -#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_UNPLUG_STATE (0x73017bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | 0x7B" */ +#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_UNPLUG_STATE (0x73017bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS_MESSAGE_ID (0x7BU) typedef struct NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS { NvU32 subDeviceInstance; @@ -1367,7 +1553,11 @@ typedef struct NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS { * the parameters. */ -#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_EVENT_CONFIG (0x730197U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | 0x97" */ +#define NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_EVENT_CONFIG (0x730197U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_HOTPLUG_EVENT_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_GET_HOTPLUG_EVENT_CONFIG_PARAMS_MESSAGE_ID (0x97U) + +typedef NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS NV0073_CTRL_SYSTEM_GET_HOTPLUG_EVENT_CONFIG_PARAMS; /* * NV0073_CTRL_CMD_SYSTEM_SET_HOTPLUG_EVENT_CONFIG @@ -1378,7 +1568,11 @@ typedef struct NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS { * the parameters. */ -#define NV0073_CTRL_CMD_SYSTEM_SET_HOTPLUG_EVENT_CONFIG (0x730198U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | 0x98" */ +#define NV0073_CTRL_CMD_SYSTEM_SET_HOTPLUG_EVENT_CONFIG (0x730198U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_SET_HOTPLUG_EVENT_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_SET_HOTPLUG_EVENT_CONFIG_PARAMS_MESSAGE_ID (0x98U) + +typedef NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS NV0073_CTRL_SYSTEM_SET_HOTPLUG_EVENT_CONFIG_PARAMS; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h index 05a18bf76..2bac0d9a7 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h @@ -62,10 +62,13 @@ typedef struct NV0080_CTRL_BIF_RESET_PARAMS { NvU32 flags; } NV0080_CTRL_BIF_RESET_PARAMS; -#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE 2:0 -#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SW_RESET (0x00000001) -#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SBR (0x00000002) -#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_FUNDAMENTAL (0x00000003) +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE 3:0 +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SW_RESET 0x1 +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SBR 0x2 +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_FUNDAMENTAL 0x3 +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE_FUSE 0x4 +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE 0x5 +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_PEX 0x6 /* * NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR @@ -81,7 +84,7 @@ typedef struct NV0080_CTRL_BIF_RESET_PARAMS { * NV_ERR_INVALID_OBJECT_PARENT */ -#define NV0080_CTRL_CMD_BIF_GET_DMA_BASE_SYSMEM_ADDR (0x800103) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS_MESSAGE_ID" */ +#define NV0080_CTRL_CMD_BIF_GET_DMA_BASE_SYSMEM_ADDR (0x800103) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS_MESSAGE_ID" */ #define NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS_MESSAGE_ID (0x3U) @@ -134,5 +137,27 @@ typedef struct NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS { NvBool bL1Enable; } NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS; +/* + * NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK + * + * pciePowerControlMask + * pciePowerControlIdentifiedKeyOrder + * pciePowerControlIdentifiedKeyLocation + * ASPM and RTD3 enable/disable information + * + * Possible status values returned are: + * NV_OK + */ + +#define NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK (0x800106) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS { + NvU32 pciePowerControlMask; + NvU32 pciePowerControlIdentifiedKeyOrder; + NvU32 pciePowerControlIdentifiedKeyLocation; +} NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS; + /* _ctrl0080bif_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h index b209ca25f..dfc7ef9cc 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h @@ -87,7 +87,7 @@ */ typedef struct NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK { - NvU32 pageSize; + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); NV_DECLARE_ALIGNED(NvU64 pteEntrySize, 8); NvU32 comptagLine; NvU32 kind; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h index 2592559fd..71205d6cf 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h @@ -95,10 +95,7 @@ typedef struct NV0080_CTRL_GR_GET_CAPS_PARAMS { * indicates that there is no minimum and the bug is not present on this * system. */ -typedef struct NV0080_CTRL_GR_INFO { - NvU32 index; - NvU32 data; -} NV0080_CTRL_GR_INFO; +typedef NVXXXX_CTRL_XXX_INFO NV0080_CTRL_GR_INFO; /* valid graphics info index values */ #define NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS (0x00000000) @@ -151,13 +148,14 @@ typedef struct NV0080_CTRL_GR_INFO { #define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC (0x00000032) +#define NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES (0x00000033) /* When adding a new INDEX, please update MAX_SIZE accordingly * NOTE: 0080 functionality is merged with 2080 functionality, so this max size * reflects that. */ -#define NV0080_CTRL_GR_INFO_INDEX_MAX (0x00000032) -#define NV0080_CTRL_GR_INFO_MAX_SIZE (0x33) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */ +#define NV0080_CTRL_GR_INFO_INDEX_MAX (0x00000033) +#define NV0080_CTRL_GR_INFO_MAX_SIZE (0x34) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */ /* * NV0080_CTRL_CMD_GR_GET_INFO @@ -210,9 +208,9 @@ typedef struct NV0080_CTRL_GR_GET_INFO_PARAMS { * disambiguate the target GR engine. * */ -#define NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE (0x801107) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | 0x7" */ +#define NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE (0x801107) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID" */ -#define NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE (0x801108) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | 0x8" */ +#define NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE (0x801108) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID" */ /* Enum for listing TPC partitioning modes */ typedef enum NV0080_CTRL_GR_TPC_PARTITION_MODE { @@ -228,6 +226,14 @@ typedef struct NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS { NV_DECLARE_ALIGNED(NV0080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); // [in] } NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS; +#define NV0080_CTRL_GR_GET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID (0x7U) + +typedef NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS NV0080_CTRL_GR_GET_TPC_PARTITION_MODE_PARAMS; + +#define NV0080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID (0x8U) + +typedef NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS NV0080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS; + /** * NV0080_CTRL_CMD_GR_GET_CAPS_V2 * diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h index 096c451bf..2a47543ec 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h @@ -88,7 +88,6 @@ typedef struct NV0080_CTRL_HOST_GET_CAPS_PARAMS { #define NV0080_CTRL_HOST_CAPS_P2P_4_WAY 1:0x08 // Deprecated #define NV0080_CTRL_HOST_CAPS_P2P_8_WAY 1:0x10 // Deprecated #define NV0080_CTRL_HOST_CAPS_P2P_DEADLOCK_BUG_203825 1:0x20 // Deprecated -#define NV0080_CTRL_HOST_CAPS_VIRTUAL_P2P 1:0x40 #define NV0080_CTRL_HOST_CAPS_BUG_254580 1:0x80 #define NV0080_CTRL_HOST_CAPS_COMPRESSED_BL_P2P_BUG_257072 2:0x02 // Deprecated #define NV0080_CTRL_HOST_CAPS_CROSS_BLITS_BUG_270260 2:0x04 // Deprecated diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h index 8607cc2f5..1fc34f410 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h @@ -32,6 +32,7 @@ #include "nvlimits.h" #include "ctrl0080gr.h" +#include "ctrl0080fifo.h" #include "ctrl/ctrl0080/ctrl0080base.h" #include "ctrl/ctrl0080/ctrl0080perf.h" @@ -91,7 +92,7 @@ typedef struct NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS { /*! * @ref NV0080_CTRL_CMD_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT */ -#define NV0080_CTRL_CMD_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT (0x802006) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS_MESSAGE_ID" */ +#define NV0080_CTRL_CMD_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT (0x802006) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS_MESSAGE_ID" */ #define NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS_MESSAGE_ID (0x6U) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h b/src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h index 595b021a3..cb751908e 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h @@ -127,18 +127,18 @@ typedef struct NV00F8_CTRL_DESCRIBE_PARAMS { } NV00F8_CTRL_DESCRIBE_PARAMS; /* - * hMemory [IN] + * hMemory * Physical memory handle to be attached. * - * offset [IN] + * offset * Offset into the fabric object. * Must be physical memory pagesize aligned (at least). * - * mapOffSet [IN] + * mapOffSet * Offset into the physical memory descriptor. * Must be physical memory pagesize aligned. * - * mapLength [IN] + * mapLength * Length of physical memory handle to be mapped. * Must be physical memory pagesize aligned and less than or equal to * fabric alloc size. @@ -215,4 +215,57 @@ typedef struct NV00F8_CTRL_DETACH_MEM_PARAMS { NvU16 numDetached; } NV00F8_CTRL_DETACH_MEM_PARAMS; +/* + * NV00F8_CTRL_CMD_GET_NUM_ATTACHED_MEM + * + * Returns number of attached physical memory info to the fabric object in + * a given offset range. + * + * offsetStart [IN] + * Offsets at which memory was attached. + * + * offsetEnd [IN] + * Offsets at which memory was attached. + * + * numMemInfos [OUT] + * Number of memory infos. + */ +#define NV00F8_CTRL_CMD_GET_NUM_ATTACHED_MEM (0xf80105) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_GET_NUM_ATTACHED_MEM_PARAMS_MESSAGE_ID" */ + +#define NV00F8_CTRL_GET_NUM_ATTACHED_MEM_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV00F8_CTRL_GET_NUM_ATTACHED_MEM_PARAMS { + NV_DECLARE_ALIGNED(NvU64 offsetStart, 8); + NV_DECLARE_ALIGNED(NvU64 offsetEnd, 8); + NvU16 numMemInfos; +} NV00F8_CTRL_GET_NUM_ATTACHED_MEM_PARAMS; + +/* + * NV00F8_CTRL_CMD_GET_ATTACHED_MEM + * + * Queries attached physical memory info to the fabric object. + * + * offsetStart [IN] + * Offsets at which memory was attached. + * + * numMemInfos [IN] + * Number of memory infos to be filled. + * + * memInfos [IN/OUT] + * Attached memory infos. + * Use must populate a non-zero `hMemory` handle. This handle will be used by + * RM for duping physical memory. + */ +#define NV00F8_CTRL_CMD_GET_ATTACHED_MEM (0xf80106) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS_MESSAGE_ID" */ + +#define NV00F8_MAX_ATTACHED_MEM_INFOS 64 + +#define NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS { + NV_DECLARE_ALIGNED(NvU64 offsetStart, 8); + NvU16 numMemInfos; + NV_DECLARE_ALIGNED(NV00F8_CTRL_ATTACH_MEM_INFO memInfos[NV00F8_MAX_ATTACHED_MEM_INFOS], 8); +} NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS; + /* _ctrl00f8_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl00fd.h b/src/common/sdk/nvidia/inc/ctrl/ctrl00fd.h index 7ba86f861..316aa6e93 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl00fd.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl00fd.h @@ -97,8 +97,7 @@ typedef struct NV00FD_CTRL_GET_INFO_PARAMS { * Physical memory handle to be attached. * * offset [IN] - * Offset into the MCFLA object. (Must be zero for now, maybe used in future) - * Must be MCFLA pagesize aligned. + * Offset into the MCFLA object. Must be at least physical pagesize aligned. * * mapOffSet [IN] * Offset into the physical memory descriptor. @@ -112,15 +111,10 @@ typedef struct NV00FD_CTRL_GET_INFO_PARAMS { * flags [IN] * For future use only. Must be zero for now. * - * devDescriptor [IN] - * devDescriptor is a file descriptor for unix RM clients, but a void - * pointer for windows RM clients. It is transparent to RM clients i.e. RM's - * user-mode shim populates this field on behalf of clients. - * * Restrictions: * a. Memory belonging to only NVSwitch P2P supported GPUs * which can do multicast can be attached - * b. Physical memory with 2MB pagesize is allowed + * b. Physical memory with 2MB or 512MB pagesize is allowed * c. Memory of an already attached GPU should not be attached * d. Only vidmem physical memory handle can be attached * @@ -136,7 +130,6 @@ typedef struct NV00FD_CTRL_ATTACH_MEM_PARAMS { NV_DECLARE_ALIGNED(NvU64 mapOffset, 8); NV_DECLARE_ALIGNED(NvU64 mapLength, 8); NvU32 flags; - NV_DECLARE_ALIGNED(NvU64 devDescriptor, 8); } NV00FD_CTRL_ATTACH_MEM_PARAMS; /* @@ -157,4 +150,56 @@ typedef struct NV00FD_CTRL_REGISTER_EVENT_PARAMS { NV_DECLARE_ALIGNED(NvP64 pOsEvent, 8); } NV00FD_CTRL_REGISTER_EVENT_PARAMS; +/* + * NV00FD_CTRL_CMD_ATTACH_GPU + * + * Attaches GPU to the Multicast FLA object. This step must be done before + * attaching memory to the Multicast FLA object. + * + * hSubdevice [IN] + * Subdevice handle of the owner GPU + * + * flags [IN] + * For future use only. Must be zero for now. + * + * devDescriptor [IN] + * devDescriptor is a file descriptor for unix RM clients, but a void + * pointer for windows RM clients. It is transparent to RM clients i.e. RM's + * user-mode shim populates this field on behalf of clients. + */ +#define NV00FD_CTRL_CMD_ATTACH_GPU (0xfd0104) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00FD_CTRL_ATTACH_GPU_PARAMS_MESSAGE_ID" */ + +#define NV00FD_CTRL_ATTACH_GPU_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV00FD_CTRL_ATTACH_GPU_PARAMS { + NvHandle hSubdevice; + NvU32 flags; + NV_DECLARE_ALIGNED(NvU64 devDescriptor, 8); +} NV00FD_CTRL_ATTACH_GPU_PARAMS; + +/* + * NV00FD_CTRL_CMD_DETACH_MEM + * + * Detaches the physical memory handle for a given GPU. + * + * hSubdevice [IN] + * Subdevice handle of the GPU for which memory to be detached. + * + * offset [IN] + * Offset into the MCFLA object at which memory to be detached. Same as + * NV00FD_CTRL_CMD_ATTACH_MEM. + * + * flags [IN] + * For future use only. Must be zero for now. + */ +#define NV00FD_CTRL_CMD_DETACH_MEM (0xfd0105) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00FD_CTRL_DETACH_MEM_PARAMS_MESSAGE_ID" */ + +#define NV00FD_CTRL_DETACH_MEM_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV00FD_CTRL_DETACH_MEM_PARAMS { + NvHandle hSubdevice; + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NvU32 flags; +} NV00FD_CTRL_DETACH_MEM_PARAMS; + /* _ctrl00fd_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h index 7df6a6d84..43a396eae 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h @@ -88,6 +88,7 @@ #define NV2080_CTRL_FLA (0x35) #define NV2080_CTRL_GSP (0x36) #define NV2080_CTRL_NNE (0x37) +#define NV2080_CTRL_NNE_LEGACY_NON_PRIVILEGED (0xb7) /* finn: Evaluated from "(NV2080_CTRL_NNE | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */ #define NV2080_CTRL_GRMGR (0x38) #define NV2080_CTRL_UCODE_FUZZER (0x39) #define NV2080_CTRL_DMABUF (0x3A) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h index cf5835047..15ee62c27 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h @@ -36,10 +36,7 @@ -typedef struct NV2080_CTRL_BIOS_INFO { - NvU32 index; - NvU32 data; -} NV2080_CTRL_BIOS_INFO; +typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_BIOS_INFO; /* Maximum number of bios infos that can be queried at once */ #define NV2080_CTRL_BIOS_INFO_MAX_SIZE (0x0000000F) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h index eb8d97954..4da86e10e 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h @@ -244,10 +244,7 @@ typedef struct NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS { * */ -typedef struct NV2080_CTRL_BUS_INFO { - NvU32 index; - NvU32 data; -} NV2080_CTRL_BUS_INFO; +typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_BUS_INFO; /* valid bus info index values */ @@ -1397,10 +1394,14 @@ typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS { * NV_OK and bIsLinkUp is NV_TRUE. * nrLinks[OUT] * Total number of C2C links that are up. + * maxNrLinks[OUT] + * Maximum number of C2C links that are supported. * linkMask[OUT] * Bitmask of the C2C links present and up. * perLinkBwMBps[OUT] * Theoretical per link bandwidth in MBps. + * perLinkLaneWidth[OUT] + * Lane width per link. * remoteType[OUT] * Type of the device connected to the remote end of the C2C link. * Valid values are : @@ -1427,8 +1428,10 @@ typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS { typedef struct NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS { NvBool bIsLinkUp; NvU32 nrLinks; + NvU32 maxNrLinks; NvU32 linkMask; NvU32 perLinkBwMBps; + NvU32 perLinkLaneWidth; NvU32 remoteType; } NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h index d2f5424a3..b45627ed5 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h @@ -228,6 +228,8 @@ typedef struct NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS { * NV_ERR_GENERIC */ + + #define NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS (0x20802a05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID (0x5U) @@ -269,7 +271,11 @@ typedef struct NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS { * */ -#define NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS (0x20802a07) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | 0x7" */ +#define NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS (0x20802a07) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS_MESSAGE_ID (0x7U) + +typedef NV2080_CTRL_CE_GET_CAPS_V2_PARAMS NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS; #define NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x8U) @@ -324,6 +330,12 @@ typedef struct NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS { NvU32 present; } NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS; -#define NV2080_CTRL_CMD_CE_GET_ALL_PHYSICAL_CAPS (0x20802a0b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | 0xb" */ +#define NV2080_CTRL_CMD_CE_GET_ALL_PHYSICAL_CAPS (0x20802a0b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS_MESSAGE_ID (0xbU) + +typedef NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS; + + /* _ctrl2080ce_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h index e72e63c38..cd4517f4d 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h @@ -114,10 +114,7 @@ typedef struct NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS { * NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE * This index can be used to request the system address size in bits. */ -typedef struct NV2080_CTRL_DMA_INFO { - NvU32 index; - NvU32 data; -} NV2080_CTRL_DMA_INFO; +typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_DMA_INFO; /* valid dma info index values */ #define NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE (0x000000000) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h index e71eb810b..324de6503 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h @@ -267,40 +267,6 @@ typedef struct NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS { } NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS; -/* - * NV2080_CTRL_CMD_EVENT_SET_VMBUS_CHANNEL - * - * hSemMemory - * This parameter specifies the handle of the memory object that - * identifies the semaphore memory associated with this subdevice - * event notification. Once this is set RM will generate an event - * only when there is a change in the semaphore value. It is - * expected that the semaphore memory value will be updated by - * the GPU indicating that there is an event pending. This - * command is used by VGX plugin to determine which virtual - * machine has generated a particular event. - * - * vmIdType - * This parameter specifies the type of guest virtual machine identifier - * - * guestVmId - * This parameter specifies the guest virtual machine identifier - * - * Possible status values returned are: - * NV_OK - * NV_ERR_INVALID_ARGUMENT - */ -#define NV2080_CTRL_CMD_EVENT_SET_VMBUS_CHANNEL (0x20800307) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS_MESSAGE_ID" */ - -#define NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS_MESSAGE_ID (0x7U) - -typedef struct NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS { - NvHandle hSemMemory; - VM_ID_TYPE vmIdType; - NV_DECLARE_ALIGNED(VM_ID guestVmId, 8); -} NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS; - - /* * NV2080_CTRL_CMD_EVENT_SET_TRIGGER_FIFO * diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h index a88332650..76982a19c 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h @@ -267,10 +267,7 @@ * Returns the ECC status size (corresponds to subpartitions or channels * depending on architecture/memory type). */ -typedef struct NV2080_CTRL_FB_INFO { - NvU32 index; - NvU32 data; -} NV2080_CTRL_FB_INFO; +typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FB_INFO; /* valid fb info index values */ #define NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_COUNT (0x00000000U) // Deprecated @@ -686,11 +683,11 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS { /* valid values for allocPolicy */ #define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS 0:0 -#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS_NO (0x00000000U) -#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS_YES (0x00000001U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS_NO (0x00000000U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS_YES (0x00000001U) #define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES 1:1 -#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES_NO (0x00000000U) -#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES_YES (0x00000001U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES_NO (0x00000000U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES_YES (0x00000001U) /* @@ -707,7 +704,11 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS { * NV_ERR_NOT_SUPPORTED * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY (0x2080130fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0xF" */ +#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY (0x2080130fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_PARAMS_MESSAGE_ID (0xFU) + +typedef NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_PARAMS; /* * NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAM @@ -773,7 +774,11 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS { * NV_ERR_NOT_SUPPORTED * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY_V2 (0x20801318U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x18" */ +#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY_V2 (0x20801318U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS_MESSAGE_ID (0x18U) + +typedef NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS; /* * NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY (deprecated; use NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2 instead) @@ -786,7 +791,11 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS { * NV_ERR_NOT_SUPPORTED * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY (0x20801312U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x12" */ +#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY (0x20801312U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_PARAMS_MESSAGE_ID (0x12U) + +typedef NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_PARAMS; /* * NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2 @@ -799,7 +808,11 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS { * NV_ERR_NOT_SUPPORTED * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2 (0x20801319U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x19" */ +#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2 (0x20801319U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS_MESSAGE_ID (0x19U) + +typedef NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS; /* @@ -875,7 +888,7 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS { * NV_OK * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_FB_IS_KIND (0x20801313U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_IS_KIND (0x20801313U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID (0x13U) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h index b8341aa47..8f80e72d6 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h @@ -213,10 +213,7 @@ typedef struct NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS { * This index can be used too get channel groups currently in use per engine/runlist. * */ -typedef struct NV2080_CTRL_FIFO_INFO { - NvU32 index; - NvU32 data; -} NV2080_CTRL_FIFO_INFO; +typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FIFO_INFO; /* valid fifo info index values */ #define NV2080_CTRL_FIFO_INFO_INDEX_INSTANCE_TOTAL (0x000000000) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h index 474f91622..3d743b3a1 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h @@ -332,9 +332,9 @@ typedef struct NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS { * * Get/set the event bitmask for the default queue. */ -#define NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_GET (0x20803122) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x22" */ +#define NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_GET (0x20803122) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_SET (0x20803123) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x23" */ +#define NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_SET (0x20803123) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS_MESSAGE_ID" */ typedef struct NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS { //! The engine type, from NV2080_ENGINE_TYPE_* @@ -353,6 +353,14 @@ typedef struct NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS { NvU8 queueId; } NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS; +#define NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS_MESSAGE_ID (0x22U) + +typedef NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS; + +#define NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS_MESSAGE_ID (0x23U) + +typedef NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS; + /* * NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_INFO * diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h index 41f9767af..d40e8b6c1 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2007-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -23,14 +23,52 @@ #pragma once +#include + // // This file was generated with FINN, an NVIDIA coding tool. // Source file: ctrl/ctrl2080/ctrl2080gpio.finn // +#include "ctrl/ctrl2080/ctrl2080base.h" + +#define NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_DIRECTION (0x20802300) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPIO_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS_MESSAGE_ID (0x00U) + +typedef struct NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS { + NvU32 gpioPin; // in + NvBool bInput; // in +} NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_OUTPUT (0x20802301) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPIO_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS_MESSAGE_ID (0x01U) + +typedef struct NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS { + NvU32 gpioPin; // in + NvU32 value; // in +} NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_GPIO_READ_INPUT (0x20802302) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPIO_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS_MESSAGE_ID (0x02U) + +typedef struct NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS { + NvU32 gpioPin; // in + NvU32 value; // out +} NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION (0x20802303) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPIO_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS_MESSAGE_ID (0x03U) + +typedef struct NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS { + NvU32 function; // in + NvU32 pin; // in +} NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS; + /* _ctrl2080gpio_h_ */ -#include "ctrl/ctrl2080/ctrl2080base.h" - diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h index 0b975697a..e31cd000b 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h @@ -61,10 +61,7 @@ -typedef struct NV2080_CTRL_GPU_INFO { - NvU32 index; - NvU32 data; -} NV2080_CTRL_GPU_INFO; +typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO; /* valid gpu info index values */ @@ -108,7 +105,9 @@ typedef struct NV2080_CTRL_GPU_INFO { #define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU (0x0000003cU) #define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY (0x0000003dU) -#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x0000003eU) + + +#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x0000003fU) /* valid minor revision extended values */ #define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_NONE (0x00000000U) @@ -241,7 +240,9 @@ typedef struct NV2080_CTRL_GPU_GET_INFO_PARAMS { NV_DECLARE_ALIGNED(NvP64 gpuInfoList, 8); } NV2080_CTRL_GPU_GET_INFO_PARAMS; -#define NV2080_CTRL_CMD_GPU_GET_INFO_V2 (0x20800102U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x2" */ +#define NV2080_CTRL_CMD_GPU_GET_INFO_V2 (0x20800102U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_MESSAGE_ID (0x2U) typedef struct NV2080_CTRL_GPU_GET_INFO_V2_PARAMS { NvU32 gpuInfoListSize; @@ -687,7 +688,9 @@ typedef struct NV2080_CTRL_GPU_REG_OP { * NV_ERR_INVALID_ARGUMENT * NV_ERR_INVALID_PARAM_STRUCT */ -#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS (0x20800122U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x22" */ +#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS (0x20800122U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_MESSAGE_ID (0x22U) typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS { NvHandle hClientTarget; @@ -1516,6 +1519,10 @@ typedef struct NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS { * The board's 699 product part number (LSB justified ASCII field with 0x00 * denoting empty space e.g. "699-21228-0208-200"). * + * board965PartNumber + * The board's 965 product part number (LSB justified ASCII field with 0x00 + * denoting empty space e.g. "965-21228-0208-200"). + * * Possible status return values are: * NV_OK * NV_ERR_NOT_SUPPORTED @@ -1541,6 +1548,7 @@ typedef struct NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS { NvU8 boardRevision[3]; NvU8 boardType; NvU8 board699PartNumber[NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH]; + NvU8 board965PartNumber[NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH]; } NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS; @@ -1867,13 +1875,17 @@ typedef struct NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_GPU_GET_ILLUM (0x20800154U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x54" */ +#define NV2080_CTRL_CMD_GPU_GET_ILLUM (0x20800154U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ILLUM_PARAMS_MESSAGE_ID" */ typedef struct NV2080_CTRL_CMD_GPU_ILLUM_PARAMS { NvU32 attribute; NvU32 value; } NV2080_CTRL_CMD_GPU_ILLUM_PARAMS; +#define NV2080_CTRL_GPU_GET_ILLUM_PARAMS_MESSAGE_ID (0x54U) + +typedef NV2080_CTRL_CMD_GPU_ILLUM_PARAMS NV2080_CTRL_GPU_GET_ILLUM_PARAMS; + /* * NV2080_CTRL_CMD_GPU_SET_ID_ILLUM * @@ -1883,7 +1895,11 @@ typedef struct NV2080_CTRL_CMD_GPU_ILLUM_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_GPU_SET_ILLUM (0x20800155U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x55" */ +#define NV2080_CTRL_CMD_GPU_SET_ILLUM (0x20800155U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID (0x55U) + +typedef NV2080_CTRL_CMD_GPU_ILLUM_PARAMS NV2080_CTRL_GPU_SET_ILLUM_PARAMS; /* * NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION @@ -2817,7 +2833,11 @@ typedef struct NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS { * See confluence page "vGPU UMED Security" for details. * */ -#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU (0x20800178U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x78" */ +#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU (0x20800178U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS_MESSAGE_ID (0x78U) + +typedef NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS; /* * NV2080_CTRL_CMD_GPU_GET_ENGINE_RUNLIST_PRI_BASE @@ -3120,12 +3140,11 @@ typedef struct NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS { * NV_ERR_NOT_SUPPORTED * NV_ERR_OPERATING_SYSTEM */ -#define NV2080_CTRL_CMD_GPU_GET_CACHED_INFO (0x20800182U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x82" */ +#define NV2080_CTRL_CMD_GPU_GET_CACHED_INFO (0x20800182U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS_MESSAGE_ID" */ -typedef struct NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS { - NvU32 gpuInfoListSize; - NV2080_CTRL_GPU_INFO gpuInfoList[NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE]; -} NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS; +#define NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS_MESSAGE_ID (0x82U) + +typedef NV2080_CTRL_GPU_GET_INFO_V2_PARAMS NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS; /* * NV2080_CTRL_GPU_SET_PARTITIONING_MODE @@ -3963,7 +3982,7 @@ typedef struct NV2080_CTRL_GPU_COMPUTE_PROFILE { * - Total Number of profiles filled * * profiles[OUT] - * - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles + * - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles */ #define NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xA2U) @@ -4025,11 +4044,11 @@ typedef struct NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS { /* * NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS - * + * * This command retrieves and constructs the GPU partnumber from the VBIOS. - * + * * The following data are currently supported: - * + * * pciDevId * The PCI device ID * @@ -4045,8 +4064,8 @@ typedef struct NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS { */ #define NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS (0x208001a4U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS_MESSAGE_ID" */ -/* - * The string format for a GPU part number +/* + * The string format for a GPU part number * The GPU part number is formatted with 4 hexadecimal digits for the PCI device ID, the chip SKU string, * the chip major number, and then the chip minor number. * Ordering of the fields for the string format must be synced with the NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS @@ -4112,4 +4131,116 @@ typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS #define NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS_MESSAGE_ID (0xA8U) typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_RESET + * + * INTERNAL DEBUG/TESTING USE ONLY + * + * Marks the device for reset. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_RESET (0x208001a9U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xA9" */ + +/* + * NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_RESET + * + * INTERNAL DEBUG/TESTING USE ONLY + * + * Unmarks the device for reset. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_RESET (0x208001aaU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xAA" */ + +/* + * NV2080_CTRL_CMD_GPU_GET_RESET_STATUS + * + * Gets the current reset status of the device. + * + * bResetNeeded + * Set to NV_TRUE if the device needs to be reset. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_RESET_STATUS (0x208001abU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS_MESSAGE_ID (0xABU) + +typedef struct NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS { + NvBool bResetRequired; +} NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_DRAIN_AND_RESET + * + * INTERNAL DEBUG/TESTING USE ONLY + * + * Marks the device for drain and reset. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_DRAIN_AND_RESET (0x208001acU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xAC" */ + +/* + * NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_DRAIN_AND_RESET + * + * INTERNAL DEBUG/TESTING USE ONLY + * + * Unmarks the device for drain and reset. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_DRAIN_AND_RESET (0x208001adU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xAD" */ + +/* + * NV2080_CTRL_CMD_GPU_GET_DRAIN_AND_RESET_STATUS + * + * Gets the current drain and reset status of the device. Drain and reset is used only SMC configs. + * + * bDrainRecommended + * Set to NV_TRUE if a drain and reset is recommended for the device. + * + * Possible status return values are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_GET_DRAIN_AND_RESET_STATUS (0x208001aeU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS_MESSAGE_ID (0xAEU) + +typedef struct NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS { + NvBool bDrainRecommended; +} NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS; + +/* + * NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2 + * + * This command returns NVENC software sessions information for the associate GPU. + * This command is similar to NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO but doesn't have + * embedded pointers. + * + * Check NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO for detailed information. + */ + +#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID (0xAFU) + +typedef struct NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS { + NvU32 sessionInfoTblEntry; + NV2080_CTRL_NVENC_SW_SESSION_INFO sessionInfoTbl[NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES]; +} NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS; + +#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2 (0x208001afU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID" */ + /* _ctrl2080gpu_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h index dde6eed98..2b4077586 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h @@ -147,6 +147,9 @@ typedef NV0080_CTRL_GR_ROUTE_INFO NV2080_CTRL_GR_ROUTE_INFO; * NV2080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT * This index is used to return the number of "Tensor Cores" * supported by the graphics pipeline + * NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES + * This index is used to return the Graphics capabilities + * supported by the graphics pipeline */ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO; @@ -253,6 +256,7 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO; #define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS #define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC #define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC +#define NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES /* When adding a new INDEX, please update INDEX_MAX and MAX_SIZE accordingly * NOTE: 0080 functionality is merged with 2080 functionality, so this max size @@ -320,6 +324,19 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO; +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D 0:0 +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_FALSE 0x0U +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_TRUE 0x1U +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D 1:1 +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_FALSE 0x0U +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_TRUE 0x1U +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE 2:2 +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_FALSE 0x0U +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_TRUE 0x1U +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M 3:3 +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_FALSE 0x0U +#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_TRUE 0x1U + /** * NV2080_CTRL_CMD_GR_GET_INFO * @@ -389,7 +406,9 @@ typedef struct NV2080_CTRL_GR_GET_INFO_PARAMS { * ID is given (shareChID), then the 2 channels will share * the zcull context buffers. */ -#define NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE (0x20801205U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x5" */ +#define NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE (0x20801205U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS_MESSAGE_ID (0x5U) typedef struct NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS { NvHandle hChannel; @@ -494,7 +513,9 @@ typedef struct NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS { * This parameter specifies the routing information used to * disambiguate the target GR engine. */ -#define NV2080_CTRL_CMD_GR_CTXSW_PM_MODE (0x20801207U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x7" */ +#define NV2080_CTRL_CMD_GR_CTXSW_PM_MODE (0x20801207U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS_MESSAGE_ID (0x7U) typedef struct NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS { NvHandle hChannel; @@ -542,7 +563,9 @@ typedef struct NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS { * ID is given (shareChID), then the 2 channels will share * the zcull context buffers. */ -#define NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND (0x20801208U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x8" */ +#define NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND (0x20801208U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_MESSAGE_ID (0x8U) typedef struct NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS { NvHandle hClient; @@ -580,7 +603,9 @@ typedef struct NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS { * This parameter specifies the routing information used to * disambiguate the target GR engine. */ -#define NV2080_CTRL_CMD_GR_CTXSW_PM_BIND (0x20801209U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x9" */ +#define NV2080_CTRL_CMD_GR_CTXSW_PM_BIND (0x20801209U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS_MESSAGE_ID (0x9U) typedef struct NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS { NvHandle hClient; @@ -607,7 +632,9 @@ typedef struct NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS { * disambiguate the target GR engine. */ #define NV2080_CTRL_GR_SET_GPC_TILE_MAP_MAX_VALUES 128U -#define NV2080_CTRL_CMD_GR_SET_GPC_TILE_MAP (0x2080120aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0xA" */ +#define NV2080_CTRL_CMD_GR_SET_GPC_TILE_MAP (0x2080120aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS_MESSAGE_ID (0xAU) typedef struct NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS { NvU32 mapValueCount; @@ -645,7 +672,9 @@ typedef struct NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS { * This parameter specifies the routing information used to * disambiguate the target GR engine. */ -#define NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE (0x2080120eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0xE" */ +#define NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE (0x2080120eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS_MESSAGE_ID (0xEU) typedef struct NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS { NvHandle hChannel; @@ -724,7 +753,9 @@ typedef struct NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS { * This parameter specifies the routing information used to * disambiguate the target GR engine. */ -#define NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE (0x20801210U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x10" */ +#define NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE (0x20801210U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_MESSAGE_ID (0x10U) typedef struct NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS { NvU32 flags; @@ -809,7 +840,9 @@ typedef enum NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS { * This parameter specifies the routing information used to * disambiguate the target GR engine. */ -#define NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND (0x20801211U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x11" */ +#define NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND (0x20801211U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_MESSAGE_ID (0x11U) typedef struct NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS { NvU32 flags; @@ -842,7 +875,9 @@ typedef struct NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS { * This parameter specifies the routing information used to * disambiguate the target GR engine. */ -#define NV2080_CTRL_CMD_GR_PC_SAMPLING_MODE (0x20801212U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x12" */ +#define NV2080_CTRL_CMD_GR_PC_SAMPLING_MODE (0x20801212U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_MESSAGE_ID (0x12U) typedef struct NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS { NvHandle hChannel; @@ -904,7 +939,9 @@ typedef struct NV2080_CTRL_GR_GET_ROP_INFO_PARAMS { * gfxpSaveCnt * This parameter returns the number of GfxP saves on the channel. */ -#define NV2080_CTRL_CMD_GR_GET_CTXSW_STATS (0x20801215U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x15" */ +#define NV2080_CTRL_CMD_GR_GET_CTXSW_STATS (0x20801215U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS_MESSAGE_ID (0x15U) typedef struct NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS { NvHandle hChannel; @@ -1120,12 +1157,14 @@ typedef struct NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS { * This parameter specifies the routing information used to * disambiguate the target GR engine. */ -#define NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL (0x2080121cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x1C" */ +#define NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL (0x2080121cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS_MESSAGE_ID" */ -typedef struct NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS { +#define NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS_MESSAGE_ID (0x1CU) + +typedef struct NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS { NvU32 chID; NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); -} NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS; +} NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS; /* * NV2080_CTRL_CMD_GR_GET_VAT_ALARM_DATA @@ -1144,7 +1183,7 @@ typedef struct NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS { #define NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_GPC_COUNT 10U #define NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_TPC_PER_GPC_COUNT 10U -#define NV2080_CTRL_CMD_GR_GET_VAT_ALARM_DATA (0x2080121dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x1D" */ +#define NV2080_CTRL_CMD_GR_GET_VAT_ALARM_DATA (0x2080121dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS_MESSAGE_ID" */ typedef struct NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC { NV_DECLARE_ALIGNED(NvU64 errorCounter, 8); @@ -1161,6 +1200,8 @@ typedef struct NV2080_CTRL_GR_VAT_ALARM_DATA { NV_DECLARE_ALIGNED(NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC gpc[NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_GPC_COUNT], 8); } NV2080_CTRL_GR_VAT_ALARM_DATA; +#define NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS_MESSAGE_ID (0x1DU) + typedef struct NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS { NV_DECLARE_ALIGNED(NV2080_CTRL_GR_VAT_ALARM_DATA smVatAlarm, 8); NvU32 maxGpcCount; @@ -1209,7 +1250,9 @@ typedef struct NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS { * The number of bytes in each slot, i * slotStride gives the offset from the * base of the pool to a given slot */ -#define NV2080_CTRL_CMD_GR_GFX_POOL_QUERY_SIZE (0x2080121fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x1F" */ +#define NV2080_CTRL_CMD_GR_GFX_POOL_QUERY_SIZE (0x2080121fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS_MESSAGE_ID (0x1FU) typedef struct NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS { NvU32 maxSlots; @@ -1233,7 +1276,9 @@ typedef struct NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS { * pControlStructure * This input is the kernel CPU pointer to the control structure. */ -#define NV2080_CTRL_CMD_GR_GFX_POOL_INITIALIZE (0x20801220U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x20" */ +#define NV2080_CTRL_CMD_GR_GFX_POOL_INITIALIZE (0x20801220U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS_MESSAGE_ID (0x20U) typedef struct NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS { NV_DECLARE_ALIGNED(NvP64 pControlStructure, 8); @@ -1260,7 +1305,9 @@ typedef struct NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS { * slots * This input contains an array of the slots to be added to the control structure */ -#define NV2080_CTRL_CMD_GR_GFX_POOL_ADD_SLOTS (0x20801221U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x21" */ +#define NV2080_CTRL_CMD_GR_GFX_POOL_ADD_SLOTS (0x20801221U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS_MESSAGE_ID (0x21U) typedef struct NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS { NV_DECLARE_ALIGNED(NvP64 pControlStructure, 8); @@ -1299,7 +1346,9 @@ typedef struct NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS { * many. If there are not enough slots on the freelist to remove the * requested amount, RM will return the number it was able to remove. */ -#define NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS (0x20801222U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x22" */ +#define NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS (0x20801222U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS_MESSAGE_ID (0x22U) typedef struct NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS { NV_DECLARE_ALIGNED(NvP64 pControlStructure, 8); @@ -1375,21 +1424,12 @@ typedef struct NV2080_CTRL_GR_GET_TPC_MASK_PARAMS { NvU32 tpcMask; } NV2080_CTRL_GR_GET_TPC_MASK_PARAMS; -#define NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE (0x2080122cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x2C" */ +#define NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE (0x2080122cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID (0x2CU) typedef NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID (0x2CU) - -typedef struct NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS { - NV_DECLARE_ALIGNED(NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS params, 8); -} NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS; - - - /* * NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES * @@ -1701,21 +1741,12 @@ typedef struct NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS { * This parameter specifies the routing information used to * disambiguate the target GR engine. */ -#define NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP (0x20801236U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x36" */ +#define NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP (0x20801236U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS_MESSAGE_ID (0x36U) typedef NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP_FINN_PARAMS_MESSAGE_ID (0x36U) - -typedef struct NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP_FINN_PARAMS { - NV_DECLARE_ALIGNED(NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS params, 8); -} NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP_FINN_PARAMS; - - - /* * NV2080_CTRL_CMD_GR_GET_ZCULL_MASK * diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h index b3314d902..b5123cc8c 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h @@ -228,11 +228,18 @@ typedef struct NV2080_CTRL_I2C_RW_REG_PARAMS { NvU8 buffer[(NV2080_CTRL_I2C_MAX_ENTRIES - 1)]; } NV2080_CTRL_I2C_RW_REG_PARAMS; -// provide NV2080_CTRL_I2C_READ_REG_PARAMS as the historical name -typedef NV2080_CTRL_I2C_RW_REG_PARAMS NV2080_CTRL_I2C_READ_REG_PARAMS; -#define NV2080_CTRL_CMD_I2C_READ_REG (0x20800603) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | 0x3" */ +#define NV2080_CTRL_CMD_I2C_READ_REG (0x20800603) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_READ_REG_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_CMD_I2C_WRITE_REG (0x20800604) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | 0x4" */ +// provide NV2080_CTRL_I2C_READ_REG_PARAMS as the historical name +#define NV2080_CTRL_I2C_READ_REG_PARAMS_MESSAGE_ID (0x3U) + +typedef NV2080_CTRL_I2C_RW_REG_PARAMS NV2080_CTRL_I2C_READ_REG_PARAMS; + +#define NV2080_CTRL_CMD_I2C_WRITE_REG (0x20800604) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_WRITE_REG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_I2C_WRITE_REG_PARAMS_MESSAGE_ID (0x4U) + +typedef NV2080_CTRL_I2C_RW_REG_PARAMS NV2080_CTRL_I2C_WRITE_REG_PARAMS; /* * NV006F_CTRL_CMD_SYSTEM_I2C_ACCESS @@ -273,7 +280,7 @@ typedef NV2080_CTRL_I2C_RW_REG_PARAMS NV2080_CTRL_I2C_READ_REG_PARAMS; * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_I2C_ACCESS (0x20800610) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_I2C_ACCESS (0x20800610) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID (0x10U) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h index 5307f5d05..2115816a4 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h @@ -41,6 +41,7 @@ #include "ctrl/ctrl0000/ctrl0000system.h" #include "ctrl/ctrl90f1.h" #include "ctrl/ctrl30f1.h" +#include "nvcfg_sdk.h" /*! * NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO @@ -206,31 +207,38 @@ typedef struct NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS { NvU32 bufferSize; } NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS; -#define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES 8 +#define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES 8 /*! * @ref NV2080_CTRL_CMD_GR_GET_CAPS_V2 */ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CAPS (0x20800a1f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x1F" */ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CAPS { NvU8 capsTbl[NV0080_CTRL_GR_CAPS_TBL_SIZE]; } NV2080_CTRL_INTERNAL_STATIC_GR_CAPS; + +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS_MESSAGE_ID (0x20U) + typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS { NV2080_CTRL_INTERNAL_STATIC_GR_CAPS engineCaps[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; } NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CAPS (0x20800a1f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS_MESSAGE_ID (0x1FU) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS; + /*! * @ref NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER * @ref NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS */ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER (0x20800a22) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x22" */ -#define NV2080_CTRL_INTERNAL_GR_MAX_SM 240 +#define NV2080_CTRL_INTERNAL_GR_MAX_SM 240 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER { struct { @@ -246,10 +254,17 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER { NvU16 numTpc; } NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER; +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID (0x23U) + typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS { NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER globalSmOrder[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; } NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER (0x20800a22) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID (0x22U) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS; /*! * Retrieve BSP Static data. @@ -288,15 +303,14 @@ typedef struct NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS { } NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS; -#define NV2080_CTRL_INTERNAL_GR_MAX_GPC 12 -#define NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT 10 +#define NV2080_CTRL_INTERNAL_GR_MAX_GPC 12 +#define NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT 10 /*! * @ref NV2080_CTRL_CMD_GR_GET_GPC_MASK * @ref NV2080_CTRL_CMD_GR_GET_TPC_MASK * @ref NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK */ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS (0x20800a26) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x26" */ @@ -328,6 +342,8 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS { NvU32 numGfxTpc; } NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS; +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID (0x27U) + typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS { /*! * floorsweeping masks which are indexed via local GR index @@ -335,6 +351,12 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS { NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS floorsweepingMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS (0x20800a26) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID (0x26U) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS; + /* * NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES * @@ -382,7 +404,6 @@ typedef struct NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS { * @ref NV2080_CTRL_CMD_GR_GET_INFO * @ref NV2080_CTRL_CMD_GR_GET_INFO_V2 */ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_INFO (0x20800a2a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x2A" */ @@ -397,14 +418,21 @@ typedef struct NV2080_CTRL_INTERNAL_GR_INFO { typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_INFO { NV2080_CTRL_INTERNAL_GR_INFO infoList[NV0080_CTRL_GR_INFO_MAX_SIZE]; } NV2080_CTRL_INTERNAL_STATIC_GR_INFO; +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_MESSAGE_ID (0x2BU) + typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS { NV2080_CTRL_INTERNAL_STATIC_GR_INFO engineInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; } NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_INFO (0x20800a2a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS_MESSAGE_ID (0x2AU) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS; + /*! * @ref NV2080_CTRL_CMD_GR_GET_ZCULL_INFO */ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ZCULL_INFO (0x20800a2c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x2C" */ @@ -421,14 +449,21 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO { NvU32 subregionHeightAlignPixels; } NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO; +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID (0x2DU) + typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS { NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO engineZcullInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; } NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ZCULL_INFO (0x20800a2c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID (0x2CU) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS; + /*! * @ref NV2080_CTRL_CMD_GR_GET_ROP_INFO */ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ROP_INFO (0x20800a2e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x2E" */ @@ -438,14 +473,21 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO { NvU32 ropOperationsCount; } NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO; +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID (0x2FU) + typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS { NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO engineRopInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; } NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ROP_INFO (0x20800a2e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS_MESSAGE_ID (0x2EU) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS; + /*! * @ref NV2080_CTRL_CMD_GR_GET_PPC_MASK */ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PPC_MASKS (0x20800a30) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x30" */ @@ -453,15 +495,22 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS { NvU32 mask[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; } NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS; +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_MESSAGE_ID (0x31U) + typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS { NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS enginePpcMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; } NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PPC_MASKS (0x20800a30) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS_MESSAGE_ID (0x30U) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS; + /*! * @ref NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES * @ref NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE */ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO (0x20800a32) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x32" */ @@ -476,14 +525,21 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO { NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO engine[NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT]; } NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO; +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID (0x33U) + typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS { NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO engineContextBuffersInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; } NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO (0x20800a32) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID (0x32U) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS; + /*! * @ref NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER */ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER (0x20800a34) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x34" */ @@ -499,10 +555,18 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER { NvU8 imla4; } NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER; +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID (0x35U) + typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS { NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER smIssueRateModifier[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; } NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER (0x20800a34) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID (0x34U) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS; + /* * NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS * @@ -554,9 +618,11 @@ typedef struct NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS { NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); NvBool bEnable; } NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS; + #define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID (0x37U) typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS; + #define NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID (0x38U) typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS; @@ -600,9 +666,11 @@ typedef struct NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS { #define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID (0x39U) typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS; + #define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID (0x3AU) typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS; + #define NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID (0x3BU) typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS; @@ -629,6 +697,7 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE { typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS { NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE fecsRecordSize[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS; + #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID (0x3DU) typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS; @@ -656,8 +725,6 @@ typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS NV2080_CTRL_C -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES (0x20800a3f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x3F" */ - typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES { NvU32 fecsRecordSize; NvU32 timestampHiTagMask; @@ -666,10 +733,18 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES { NvU8 numLowerBitsZeroShift; } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES; +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID (0x3EU) + typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS { NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES fecsTraceDefines[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES], 8); } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES (0x20800a3f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID (0x3FU) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS; + /** * NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE * @@ -739,16 +814,22 @@ typedef struct NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS { -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES (0x20800a48) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x48" */ - typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES { NvBool bPerSubCtxheaderSupported; } NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES; +#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID (0x47U) + typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS { NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES pdbTable[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; } NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES (0x20800a48) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID (0x48U) + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS; + /*! * NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM * @@ -933,6 +1014,8 @@ typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO { * table [OUT] * Supported profiles. */ +#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID (0x4FU) + typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS { NvU32 count; NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO table[NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES], 8); @@ -973,6 +1056,8 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS { +#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID (0x52U) + typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS { NV_DECLARE_ALIGNED(NvU64 engineMask, 8); } NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS; @@ -1280,7 +1365,11 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS { /*! * @ref NV2080_CTRL_CMD_GR_GET_CTXSW_MODES */ -#define NV2080_CTRL_CMD_INTERNAL_GR_GET_CTXSW_MODES (0x20800a5a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x5A" */ +#define NV2080_CTRL_CMD_INTERNAL_GR_GET_CTXSW_MODES (0x20800a5a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID (0x5AU) + +typedef NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS; /*! * NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE @@ -1299,16 +1388,43 @@ typedef struct NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS { /*! * NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE * - * tableLen [OUT] + * tableLen [OUT] * Number of valid records in table field. * - * table [OUT] + * table [OUT] * Interrupt table for Kernel RM. + * + * subtreeMap [OUT] + * Subtree range for each NV2080_INTR_CATEGORY. */ #define NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE (0x20800a5c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE 128 +/*! + * Categories of interrupts. + * + * Each of these categories get a separate range of interrupt subtrees (top + * level bits). + */ +typedef enum NV2080_INTR_CATEGORY { + NV2080_INTR_CATEGORY_DEFAULT = 0, + NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE = 1, + NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION = 2, + NV2080_INTR_CATEGORY_RUNLIST = 3, + NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION = 4, + NV2080_INTR_CATEGORY_UVM_OWNED = 5, + NV2080_INTR_CATEGORY_UVM_SHARED = 6, + NV2080_INTR_CATEGORY_ENUM_COUNT = 7, +} NV2080_INTR_CATEGORY; + +#define NV2080_INTR_INVALID_SUBTREE NV_U8_MAX + +typedef struct NV2080_INTR_CATEGORY_SUBTREE_MAP { + NvU8 subtreeStart; + NvU8 subtreeEnd; +} NV2080_INTR_CATEGORY_SUBTREE_MAP; + typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY { NvU16 engineIdx; NvU32 pmcIntrMask; @@ -1321,6 +1437,7 @@ typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY { typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS { NvU32 tableLen; NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY table[NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE]; + NV2080_INTR_CATEGORY_SUBTREE_MAP subtreeMap[NV2080_INTR_CATEGORY_ENUM_COUNT]; } NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS; /* Index to retrieve the needed heap space for specific module */ @@ -1438,29 +1555,41 @@ typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS { * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PROFILES */ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES (0x20800a63) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x63" */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES (0x20800a63) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID (0x63U) + +typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS; /*! * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_VALID_SWIZZID_MASK */ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK (0x20800a64) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x64" */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK (0x20800a64) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x64" */ /*! * NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES * NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES */ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES (0x20800a65) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x65" */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES (0x20800a65) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID (0x65U) + +typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS; /*! * NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES * NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES */ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES (0x20800a66) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x66" */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES (0x20800a66) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID (0x66U) + +typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS; /*! - * NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG * NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG + * NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG * * This command retrieves memory config from HW * @@ -1479,8 +1608,9 @@ typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS { * memBoundaryCfgValInit [OUT] * Memory boundary config initial value (64KB aligned) */ -#define NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a67) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x67" */ -#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a68) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x68" */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a68) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID (0x68U) typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS { NV_DECLARE_ALIGNED(NvU64 memBoundaryCfgA, 8); @@ -1490,6 +1620,12 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS { NvU32 memBoundaryCfgValInit; } NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a67) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID (0x67U) + +typedef NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS; + #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE (0x20800a6b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE 8 @@ -1679,6 +1815,10 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS { */ #define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER (0x20800a9c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x9C" */ +// Valid fault buffer types +#define NV2080_CTRL_FAULT_BUFFER_NON_REPLAYABLE (0x00000000) +#define NV2080_CTRL_FAULT_BUFFER_REPLAYABLE (0x00000001) + /* * NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER * @@ -1694,6 +1834,12 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS { * shadowFaultBufferPteArray * Pages of client shadow fault buffer. * + * shadowFaultBufferType + * Replayable or non-replayable fault buffer + * + * faultBufferSharedMemoryPhysAddr + * Fault buffer shared memory address. Used only by the Replayable fault buffer. + * * Possible status values returned are: * NV_OK */ @@ -1706,8 +1852,29 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PAR NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferQueuePhysAddr, 8); NvU32 shadowFaultBufferSize; NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferPteArray[NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES], 8); + NvU32 shadowFaultBufferType; + NV_DECLARE_ALIGNED(NvU64 faultBufferSharedMemoryPhysAddr, 8); } NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS; +/* + * NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER + * + * This command requests physical RM to disable the client shadow fault buffer. + * + * shadowFaultBufferType + * Replayable or non-replayable fault buffer + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9EU) + +typedef struct NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS { + NvU32 shadowFaultBufferType; +} NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS; + /* * NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER * @@ -1725,16 +1892,6 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SE NV_DECLARE_ALIGNED(NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS PdeCopyParams, 8); } NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS; -/* - * NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER - * - * This command requests physical RM to disable the client shadow fault buffer. - * - * Possible status values returned are: - * NV_OK - */ -#define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x9E" */ - /*! * NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X * @@ -1764,7 +1921,7 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SE * NV_ERR_INVALID_PARAM_STRUCT * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X (0x20800aa0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X (0x20800aa0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID" */ #define NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID (0xA0U) @@ -1850,22 +2007,38 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS { /*! * @ref NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE */ -#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_PARTITIONING_MODE (0x20800aa3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA3" */ +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_PARTITIONING_MODE (0x20800aa3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID (0xA3U) + +typedef NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS; /*! * @ref NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION */ -#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE (0x20800aa4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA4" */ +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE (0x20800aa4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA4U) + +typedef NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS; /*! * @ref NV2080_CTRL_CMD_GPU_SET_PARTITIONS */ -#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_GPU_INSTANCES (0x20800aa5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA5" */ +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_GPU_INSTANCES (0x20800aa5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS_MESSAGE_ID (0xA5U) + +typedef NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS; /*! * @ref NV2080_CTRL_CMD_GPU_GET_PARTITIONS */ -#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_GET_GPU_INSTANCES (0x20800aa6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA6" */ +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_GET_GPU_INSTANCES (0x20800aa6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS_MESSAGE_ID (0xA6U) + +typedef NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS; /*! * NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED @@ -1877,7 +2050,7 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS { * NV_TRUE -> ZBC-kind (and no _SKIP_ZBCREFCOUNT flag) are allocated in Kernel RM * */ -#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED (0x20800a69) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED (0x20800a69) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID (0x69U) @@ -1896,8 +2069,9 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS { * gpu instance should behave identically with respect to fragmentation and * placement / span positioning. */ -#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE (0x20800aa7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA7" */ -#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE (0x20800aa8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA8" */ +#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE (0x20800aa7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE (0x20800aa8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ /*! * NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE @@ -1908,8 +2082,9 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS { * as the exported gpu instance, but the imported gpu instance should behave * identically with respect to fragmentation and placement / span positioning. */ -#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE (0x20800aa9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA9" */ -#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE (0x20800aaa) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xAA" */ +#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE (0x20800aa9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE (0x20800aaa) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE 4 typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO { @@ -1926,6 +2101,22 @@ typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS { NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO info, 8); } NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS; +#define NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA7U) + +typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS; + +#define NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA8U) + +typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS; + +#define NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA9U) + +typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS; + +#define NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xAAU) + +typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS; + /*! * NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT * @@ -2094,6 +2285,8 @@ typedef struct NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS { NvU8 hshubId; } NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS; + + /* * NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR * @@ -2335,7 +2528,7 @@ typedef struct NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS { * P2P Capability is disabled by a regkey. * NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED * P2P Capability is not supported. - * + * * Possible status values returned are: * NV_OK * NV_ERR_INVALID_ARGUMENT @@ -2369,7 +2562,7 @@ typedef struct NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS { /* * NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE * - * An internal call to invoke the sequence VGA register reads & writes to + * An internal call to invoke the sequence VGA register reads & writes to * perform save and restore of VGA * * [in] saveOrRestore @@ -2417,10 +2610,9 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS { } NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS; /*! - * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES + * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES */ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES (0x20800aba) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xba" */ /*! * NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE @@ -2460,7 +2652,7 @@ typedef struct NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE { * - Total Number of profiles filled * * profiles[OUT] - * - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles + * - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles */ #define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xBBU) @@ -2469,6 +2661,12 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS { NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE profiles[NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE]; } NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES (0x20800aba) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xBAU) + +typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS; + /* @@ -2637,7 +2835,7 @@ typedef struct NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS { /*! * NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC * - * Disable the raster sync gpio on the other P2060 GPU + * Disable the raster sync gpio on the other P2060 GPU * that's connected to master over Video bridge. * * [in] bEnableMaster @@ -2647,7 +2845,7 @@ typedef struct NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS { * If raster sync GPIO direction is saved or not. * * [in/out] bRasterSyncGpioDirection - * During save it gets the direction. + * During save it gets the direction. * In restores it sets the direction. * * Possible status values returned are: @@ -2714,7 +2912,7 @@ typedef struct NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS { * [in] sysOffset * Offset in SYSMEM region to save to/restore from * [in] size - * Size of region being saved/restored + * Size of region being saved/restored */ #define NV2080_CTRL_CMD_INTERNAL_FBSR_SEND_REGION_INFO (0x20800ac3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS_MESSAGE_ID" */ @@ -2805,7 +3003,7 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS /*! * NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE * - * Update the system control capability + * Update the system control capability * * bIsSysCtrlSupported [IN] If the system control is supported @@ -2843,7 +3041,7 @@ typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI { NvU32 sensorId; /*! - * PFM sensor limit value if required + * PFM sensor limit value if required */ NvU32 limit; } NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI; @@ -2900,7 +3098,11 @@ typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS { * Sync payload data * */ -#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC (0x20800acc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xCC" */ +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC (0x20800acc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS_MESSAGE_ID (0xCCU) + +typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS; /*! * NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC @@ -2914,7 +3116,11 @@ typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS { * Sync payload data * */ -#define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC (0x20800acd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xCD" */ +#define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC (0x20800acd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS_MESSAGE_ID (0xCDU) + +typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS; /*! * NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE @@ -2922,7 +3128,7 @@ typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS { * Query Coherent FB Aperture Size. * */ -#define NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE (0x20800ada) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE (0x20800ada) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID (0xDAU) @@ -3168,9 +3374,94 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS { NvU32 vPstateIdx; } NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS; +/* + * NV2080_CTRL_CMD_INTERNAL_GC6_ENTRY_PREREQUISITE + * + * This command gets if GPU is in a proper state (P8 and engine idle) to be ready to enter RTD3 + * + * Possible status return values are: + * NV_OK Success + */ +#define NV2080_CTRL_CMD_INTERNAL_GC6_ENTRY_PREREQUISITE (0x2080a7d7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID (0xD7U) + +typedef struct NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS { + NvBool bIsSatisfied; +} NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS; + /* * This command unsets Dynamic Boost limit when nvidia-powerd is terminated unexpectedly. */ #define NV2080_CTRL_CMD_INTERNAL_PMGR_UNSET_DYNAMIC_BOOST_LIMIT (0x20800a7b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7B" */ +/*! + * NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS + * + * This command is an internal command sent from Kernel RM to Physical RM + * to get number of secure channels supported on SEC2 and CE + * + * maxSec2SecureChannels [OUT] + * maxCeSecureChannels [OUT] + */ +#define NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS (0x20800ad8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID (0xD8U) + +typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS { + NvU32 maxSec2SecureChannels; + NvU32 maxCeSecureChannels; +} NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS + * + * This command is an internal command sent from Kernel RM to Physical RM + * to disable the GPU system memory access after quiescing the GPU or + * re-enable sysmem access. + * + * bDisable [IN] + * If NV_TRUE the GPU is quiesced and system memory access is disabled . + * If NV_FALSE the GPU system memory access is re-enabled and the GPU is resumed. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS (0x20800adb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID (0xDBU) + +typedef struct NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS { + NvBool bDisable; +} NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_DISP_PINSETS_TO_LOCKPINS (0x20800adc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS_MESSAGE_ID (0xDCU) + +typedef struct NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS { + NvU32 pinSetIn; // in + NvU32 pinSetOut; // in + NvBool bMasterScanLock; // out + NvU32 masterScanLockPin; // out + NvBool bSlaveScanLock; // out + NvU32 slaveScanLockPin; // out +} NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_DETECT_HS_VIDEO_BRIDGE (0x20800add) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xDD" */ + +#define NV2080_CTRL_CMD_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL (0x20800ade) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS_MESSAGE_ID (0xDEU) + +typedef struct NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS { + NvU32 pinSet; // in + NvU32 gpioFunction; // out + NvU32 gpioPin; // out + NvBool gpioDirection; // out +} NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS; + /* ctrl2080internal_h */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h index b12521dfd..f87a34f0a 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h @@ -347,23 +347,7 @@ typedef struct NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_PERF_RATED_TDP_GET_CONTROL (0x2080206e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | 0x6E" */ - -/*! - * NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL - * - * This command sets the requested RATED_TDP action corresponding to the - * specified client. @Note, however, that this command is unable to set @ref - * NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM. - * - * See @ref NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS for documentation of - * parameters. - * - * Possible status values returned are - * NV_OK - * NV_ERR_NOT_SUPPORTED - */ -#define NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL (0x2080206f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | 0x6F" */ +#define NV2080_CTRL_CMD_PERF_RATED_TDP_GET_CONTROL (0x2080206e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS_MESSAGE_ID" */ /*! * Structure containing the requested action for a RATED_TDP client (@ref @@ -380,6 +364,30 @@ typedef struct NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS { NV2080_CTRL_PERF_RATED_TDP_ACTION input; } NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS; +#define NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS_MESSAGE_ID (0x6EU) + +typedef NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS; + +/*! + * NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL + * + * This command sets the requested RATED_TDP action corresponding to the + * specified client. @Note, however, that this command is unable to set @ref + * NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM. + * + * See @ref NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS for documentation of + * parameters. + * + * Possible status values returned are + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL (0x2080206f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS_MESSAGE_ID (0x6FU) + +typedef NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS; + /*! * This struct represents the GPU monitoring perfmon sample for an engine. */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h index e2471c302..ed4dd89a3 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h @@ -252,9 +252,17 @@ typedef struct NV2080_CTRL_CMD_RC_RECOVERY_PARAMS { NvU32 rcEnable; } NV2080_CTRL_CMD_RC_RECOVERY_PARAMS; -#define NV2080_CTRL_CMD_SET_RC_RECOVERY (0x2080220d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xD" */ +#define NV2080_CTRL_CMD_SET_RC_RECOVERY (0x2080220d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_SET_RC_RECOVERY_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_CMD_GET_RC_RECOVERY (0x2080220e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xE" */ +#define NV2080_CTRL_SET_RC_RECOVERY_PARAMS_MESSAGE_ID (0xDU) + +typedef NV2080_CTRL_CMD_RC_RECOVERY_PARAMS NV2080_CTRL_SET_RC_RECOVERY_PARAMS; + +#define NV2080_CTRL_CMD_GET_RC_RECOVERY (0x2080220e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_GET_RC_RECOVERY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GET_RC_RECOVERY_PARAMS_MESSAGE_ID (0xEU) + +typedef NV2080_CTRL_CMD_RC_RECOVERY_PARAMS NV2080_CTRL_GET_RC_RECOVERY_PARAMS; /* valid values for rcEnable */ #define NV2080_CTRL_CMD_RC_RECOVERY_DISABLED (0x00000000) @@ -353,9 +361,17 @@ typedef struct NV2080_CTRL_CMD_RC_INFO_PARAMS { NvU32 rcBreak; } NV2080_CTRL_CMD_RC_INFO_PARAMS; -#define NV2080_CTRL_CMD_SET_RC_INFO (0x20802211) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x11" */ +#define NV2080_CTRL_CMD_SET_RC_INFO (0x20802211) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_SET_RC_INFO_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_CMD_GET_RC_INFO (0x20802212) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x12" */ +#define NV2080_CTRL_SET_RC_INFO_PARAMS_MESSAGE_ID (0x11U) + +typedef NV2080_CTRL_CMD_RC_INFO_PARAMS NV2080_CTRL_SET_RC_INFO_PARAMS; + +#define NV2080_CTRL_CMD_GET_RC_INFO (0x20802212) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_GET_RC_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GET_RC_INFO_PARAMS_MESSAGE_ID (0x12U) + +typedef NV2080_CTRL_CMD_RC_INFO_PARAMS NV2080_CTRL_GET_RC_INFO_PARAMS; /* valid rcMode values */ #define NV2080_CTRL_CMD_RC_INFO_MODE_DISABLE (0x00000000) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h index d473f1137..dda35bf0b 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h @@ -53,7 +53,7 @@ * NV_ERR_INVALID_ARGUMENT */ -#define NV208F_CTRL_CMD_GPU_GET_RAM_SVOP_VALUES (0x208f1101) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID << 8) | 0x1" */ +#define NV208F_CTRL_CMD_GPU_GET_RAM_SVOP_VALUES (0x208f1101) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID << 8) | NV208F_CTRL_GPU_GET_RAM_SVOP_VALUES_PARAMS_MESSAGE_ID" */ typedef struct NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS { NvU32 sp; @@ -62,6 +62,10 @@ typedef struct NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS { NvU32 dp; } NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS; +#define NV208F_CTRL_GPU_GET_RAM_SVOP_VALUES_PARAMS_MESSAGE_ID (0x1U) + +typedef NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS NV208F_CTRL_GPU_GET_RAM_SVOP_VALUES_PARAMS; + /* * NV208F_CTRL_CMD_GPU_SET_RAM_SVOP_VALUES * @@ -82,7 +86,11 @@ typedef struct NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS { * NV_ERR_INVALID_ARGUMENT */ -#define NV208F_CTRL_CMD_GPU_SET_RAM_SVOP_VALUES (0x208f1102) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID << 8) | 0x2" */ +#define NV208F_CTRL_CMD_GPU_SET_RAM_SVOP_VALUES (0x208f1102) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID << 8) | NV208F_CTRL_GPU_SET_RAM_SVOP_VALUES_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_GPU_SET_RAM_SVOP_VALUES_PARAMS_MESSAGE_ID (0x2U) + +typedef NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS NV208F_CTRL_GPU_SET_RAM_SVOP_VALUES_PARAMS; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl30f1.h b/src/common/sdk/nvidia/inc/ctrl/ctrl30f1.h index fdfa8fb0a..07f0ae988 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl30f1.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl30f1.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2006-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -199,6 +199,12 @@ typedef struct NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS { * useHouseSync * When a house sync signal is detected, this parameter indicates that it * should be used as the reference to generate the frame sync signal. + * syncMulDiv + * Enables multiply/divide of the frequency of the house sync signal by an + * integer. Only supported if the + * NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_MULTIPLY_DIVIDE_SYNC bit is set. The + * maximum value of multiplyDivideValue is given by + * NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS.maxMulDivValue. * * Possible status values returned are: * NV_OK @@ -210,48 +216,60 @@ typedef struct NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS { #define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_PARAMS (0x30f10104) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS_MESSAGE_ID" */ +typedef struct NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS { + NvU8 multiplyDivideValue; + NvU8 multiplyDivideMode; + NvU16 rsvd; +} NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS; + +typedef struct NV30F1_CTRL_GSYNC_CONTROL_PARAMS_PARAMS { + NvU32 which; + NvU32 syncPolarity; + NvU32 syncVideoMode; + NvU32 nSync; + NvU32 syncSkew; + NvU32 syncStartDelay; + NvU32 useHouseSync; + NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS syncMulDiv; +} NV30F1_CTRL_GSYNC_CONTROL_PARAMS_PARAMS; + #define NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS_MESSAGE_ID (0x3U) -typedef struct NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS { - NvU32 which; - NvU32 syncPolarity; - NvU32 syncVideoMode; - NvU32 nSync; - NvU32 syncSkew; - NvU32 syncStartDelay; - NvU32 useHouseSync; -} NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS; +typedef NV30F1_CTRL_GSYNC_CONTROL_PARAMS_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS; + #define NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS_MESSAGE_ID (0x4U) -typedef NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS; +typedef NV30F1_CTRL_GSYNC_CONTROL_PARAMS_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS; /* * which values * */ -#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY 0x0001 -#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE 0x0002 -#define NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC 0x0004 -#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW 0x0008 -#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY 0x0010 -#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE 0x0020 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY 0x0001 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE 0x0002 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC 0x0004 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW 0x0008 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY 0x0010 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE 0x0020 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_MULTIPLY_DIVIDE 0x0040 -#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_POLARITY NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY -#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE -#define NV30F1_CTRL_GSYNC_GET_CONTROL_NSYNC NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC -#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_SKEW NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW -#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_START_DELAY NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY -#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_USE_HOUSE NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_POLARITY NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY +#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE +#define NV30F1_CTRL_GSYNC_GET_CONTROL_NSYNC NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_SKEW NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_START_DELAY NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_USE_HOUSE NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_MULTIPLY_DIVIDE NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_MULTIPLY_DIVIDE /* * syncPolarity values * */ -#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_RISING_EDGE 0 -#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_FALLING_EDGE 1 -#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_BOTH_EDGES 2 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_RISING_EDGE 0 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_FALLING_EDGE 1 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_BOTH_EDGES 2 /* * syncVideoMode values @@ -259,16 +277,23 @@ typedef NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS NV30F1_CTRL_GSYNC_SET_CONTRO * */ -#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE 0 -#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL 1 -#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM 2 -#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV 3 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE 0 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL 1 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM 2 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV 3 -#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_NONE NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE -#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_TTL NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL -#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_NTSCPALSECAM NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM -#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_HDTV NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV -#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_COMPOSITE 4 +#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_NONE NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE +#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_TTL NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL +#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_NTSCPALSECAM NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM +#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_HDTV NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV +#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_COMPOSITE 4 + +/* + * multiplyDivide values + * + */ +#define NV30F1_CTRL_GSYNC_SET_CONTROL_MULTIPLY_DIVIDE_MODE_MULTIPLY 0 +#define NV30F1_CTRL_GSYNC_SET_CONTROL_MULTIPLY_DIVIDE_MODE_DIVIDE 1 /* * NV30F1_CTRL_CMD_GSYNC_GET_CAPS @@ -330,13 +355,18 @@ typedef NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS NV30F1_CTRL_GSYNC_SET_CONTRO * programmed into the board has to be between 0 and maxSyncInterval, * inclusive. * + * maxMulDivValue + * This parameter returns the maximum possible value that can be + * programmed for multiplying / dividing house sync. Only valid if + * NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_MULTIPLY_DIVIDE_SYNC is set. + * * Possible status values returned are: * NV_OK * NV_ERR_GENERIC * NV_ERR_INVALID_ARGUMENT */ -#define NV30F1_CTRL_CMD_GSYNC_GET_CAPS (0x30f10105) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS_MESSAGE_ID" */ +#define NV30F1_CTRL_CMD_GSYNC_GET_CAPS (0x30f10105) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS_MESSAGE_ID" */ #define NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS_MESSAGE_ID (0x5U) @@ -353,6 +383,7 @@ typedef struct NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS { NvU32 maxStartDelay; NvU32 startDelayResolution; NvU32 maxSyncInterval; + NvU32 maxMulDivValue; } NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS; #define NV30F1_CTRL_GSYNC_GET_CAPS_BOARD_ID_P2060 (0x00002060) @@ -363,6 +394,7 @@ typedef struct NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS { #define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_FREQ_ACCURACY_4DPS (0x00000004) #define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_NEED_MASTER_BARRIER_WAR (0x00000010) +#define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_MULTIPLY_DIVIDE_SYNC (0x00000020) #define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_SYNC_LOCK_EVENT (0x10000000) #define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_HOUSE_SYNC_EVENT (0x20000000) @@ -482,19 +514,22 @@ typedef struct NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PARAMS { // If set the swapbarrier is not enable automatically when enablign a framelock master on fpga revs <= 5. #define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_CONFIG_FLAGS_KEEP_MASTER_SWAPBARRIER_DISABLED (0x00000001) -#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS_MESSAGE_ID (0x10U) - -typedef struct NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS { +typedef struct NV30F1_CTRL_GSYNC_CONTROL_SYNC_PARAMS { NvU32 gpuId; NvU32 master; NvU32 displays; NvU32 validateExternal; NvU32 refresh; NvU32 configFlags; -} NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS; +} NV30F1_CTRL_GSYNC_CONTROL_SYNC_PARAMS; + +#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS_MESSAGE_ID (0x10U) + +typedef NV30F1_CTRL_GSYNC_CONTROL_SYNC_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS; + #define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS_MESSAGE_ID (0x11U) -typedef NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS; +typedef NV30F1_CTRL_GSYNC_CONTROL_SYNC_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS; /* * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_UNSYNC @@ -705,14 +740,17 @@ typedef struct NV30F1_CTRL_GSYNC_GET_STATUS_PARAMS { #define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_TESTING (0x30f10121) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS_MESSAGE_ID" */ -#define NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS_MESSAGE_ID (0x21U) - -typedef struct NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS { +typedef struct NV30F1_CTRL_GSYNC_CONTROL_TESTING_PARAMS { NvU32 bEmitTestSignal; -} NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS; +} NV30F1_CTRL_GSYNC_CONTROL_TESTING_PARAMS; + #define NV30F1_CTRL_GSYNC_GET_CONTROL_TESTING_PARAMS_MESSAGE_ID (0x20U) -typedef NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_TESTING_PARAMS; +typedef NV30F1_CTRL_GSYNC_CONTROL_TESTING_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_TESTING_PARAMS; + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS_MESSAGE_ID (0x21U) + +typedef NV30F1_CTRL_GSYNC_CONTROL_TESTING_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS; /* * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_WATCHDOG @@ -756,14 +794,17 @@ typedef struct NV30F1_CTRL_GSYNC_SET_CONTROL_WATCHDOG_PARAMS { #define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_INTERLACE_MODE (0x30f10141) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID" */ -#define NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID (0x41U) - -typedef struct NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS { +typedef struct NV30F1_CTRL_GSYNC_CONTROL_INTERLACE_MODE_PARAMS { NvU32 enable; -} NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS; +} NV30F1_CTRL_GSYNC_CONTROL_INTERLACE_MODE_PARAMS; + #define NV30F1_CTRL_GSYNC_GET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID (0x40U) -typedef NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_INTERLACE_MODE_PARAMS; +typedef NV30F1_CTRL_GSYNC_CONTROL_INTERLACE_MODE_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_INTERLACE_MODE_PARAMS; + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID (0x41U) + +typedef NV30F1_CTRL_GSYNC_CONTROL_INTERLACE_MODE_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS; /* * @@ -795,15 +836,18 @@ typedef NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS NV30F1_CTRL_GSYNC_GE #define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_SWAP_BARRIER (0x30f10151) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID" */ -#define NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID (0x51U) - -typedef struct NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS { +typedef struct NV30F1_CTRL_GSYNC_CONTROL_SWAP_BARRIER_PARAMS { NvU32 gpuId; NvBool enable; -} NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS; +} NV30F1_CTRL_GSYNC_CONTROL_SWAP_BARRIER_PARAMS; + #define NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID (0x50U) -typedef NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS; +typedef NV30F1_CTRL_GSYNC_CONTROL_SWAP_BARRIER_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS; + +#define NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID (0x51U) + +typedef NV30F1_CTRL_GSYNC_CONTROL_SWAP_BARRIER_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS; /* * NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW @@ -1285,15 +1329,18 @@ typedef struct NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_PARAMS { #define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE (0x30f10173) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID" */ -#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID (0x72U) - -typedef struct NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS { +typedef struct NV30F1_CTRL_CMD_GSYNC_CONTROL_STEREO_LOCK_MODE_PARAMS { NvU32 gpuId; NvU32 enable; -} NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS; +} NV30F1_CTRL_CMD_GSYNC_CONTROL_STEREO_LOCK_MODE_PARAMS; + +#define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID (0x72U) + +typedef NV30F1_CTRL_CMD_GSYNC_CONTROL_STEREO_LOCK_MODE_PARAMS NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS; + #define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID (0x73U) -typedef NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS; +typedef NV30F1_CTRL_CMD_GSYNC_CONTROL_STEREO_LOCK_MODE_PARAMS NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS; /* * NV30F1_CTRL_CMD_GSYNC_READ_REGISTER @@ -1478,14 +1525,21 @@ typedef struct NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH_PARAMS { * NV_ERR_INVALID_STATE * */ -#define NV30F1_CTRL_CMD_GSYNC_GET_HOUSE_SYNC_MODE (0x30f10187) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | 0x87" */ - -#define NV30F1_CTRL_CMD_GSYNC_SET_HOUSE_SYNC_MODE (0x30f10188) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | 0x88" */ +#define NV30F1_CTRL_CMD_GSYNC_GET_HOUSE_SYNC_MODE (0x30f10187) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_HOUSE_SYNC_MODE_PARAMS_MESSAGE_ID" */ typedef struct NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS { NvU8 houseSyncMode; } NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS; +#define NV30F1_CTRL_GSYNC_GET_HOUSE_SYNC_MODE_PARAMS_MESSAGE_ID (0x87U) + +typedef NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS NV30F1_CTRL_GSYNC_GET_HOUSE_SYNC_MODE_PARAMS; + +#define NV30F1_CTRL_CMD_GSYNC_SET_HOUSE_SYNC_MODE (0x30f10188) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_HOUSE_SYNC_MODE_PARAMS_MESSAGE_ID" */ + +#define NV30F1_CTRL_GSYNC_SET_HOUSE_SYNC_MODE_PARAMS_MESSAGE_ID (0x88U) + +typedef NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS NV30F1_CTRL_GSYNC_SET_HOUSE_SYNC_MODE_PARAMS; #define NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_INPUT (0x00) #define NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_OUTPUT (0x01) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h index 64269d8c1..a9ce465a0 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h @@ -256,65 +256,6 @@ typedef struct NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_PARAMS { NvU32 swapLockoutStart; } NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_PARAMS; -/* - * NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN - * - * This command returns which lockpin has been connected for the specified - * subdevice in the current SLI and/or framelock configuration. - * - * head - * The head for which the locking is associated with - * - * masterScanLock - * Indicate the connection status and pin number of master scanlock - * - * slaveScanLock - * Indicate the connection status and pin number of slave scanlock - * - * flipLock - * Indicate the connection status and pin number of fliplock - * - * stereoLock - * Indicate the connection status and pin number of stereo lock - * - * Possible status values returned are: - * NV_OK - * NV_ERR_INVALID_ARGUMENT - */ -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN (0x50700207) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS_MESSAGE_ID" */ - -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_MASTER_SCAN_LOCK_CONNECTED 0:0 -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_MASTER_SCAN_LOCK_CONNECTED_NO (0x00000000) -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_MASTER_SCAN_LOCK_CONNECTED_YES (0x00000001) -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_MASTER_SCAN_LOCK_PIN 3:1 - -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_SLAVE_SCAN_LOCK_CONNECTED 0:0 -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_SLAVE_SCAN_LOCK_CONNECTED_NO (0x00000000) -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_SLAVE_SCAN_LOCK_CONNECTED_YES (0x00000001) -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_SLAVE_SCAN_LOCK_PIN 3:1 - -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_FLIP_LOCK_CONNECTED 0:0 -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_FLIP_LOCK_CONNECTED_NO (0x00000000) -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_FLIP_LOCK_CONNECTED_YES (0x00000001) -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_FLIP_LOCK_PIN 3:1 - -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STEREO_LOCK_CONNECTED 0:0 -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STEREO_LOCK_CONNECTED_NO (0x00000000) -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STEREO_LOCK_CONNECTED_YES (0x00000001) -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STEREO_LOCK_PIN 3:1 - -#define NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS_MESSAGE_ID (0x7U) - -typedef struct NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS { - NV5070_CTRL_CMD_BASE_PARAMS base; - NvU32 head; - - NvU32 masterScanLock; - NvU32 slaveScanLock; - NvU32 flipLock; - NvU32 stereoLock; -} NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS; - /* * NV5070_CTRL_CMD_SET_VIDEO_STATUS * diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl9067.h b/src/common/sdk/nvidia/inc/ctrl/ctrl9067.h index 62cb94861..117b8dda6 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl9067.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl9067.h @@ -134,9 +134,7 @@ typedef struct NV9067_CTRL_TPC_PARTITION_TABLE_PARAMS { * */ -#define NV9067_CTRL_CMD_GET_CWD_WATERMARK (0x90670201) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK_INTERFACE_ID << 8) | 0x1" */ - -#define NV9067_CTRL_CMD_SET_CWD_WATERMARK (0x90670202) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK_INTERFACE_ID << 8) | 0x2" */ +#define NV9067_CTRL_CMD_GET_CWD_WATERMARK (0x90670201) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK_INTERFACE_ID << 8) | NV9067_CTRL_GET_CWD_WATERMARK_PARAMS_MESSAGE_ID" */ #define NV9067_CTRL_CWD_WATERMARK_VALUE_MIN 1 #define NV9067_CTRL_CWD_WATERMARK_VALUE_DEFAULT 2 @@ -146,5 +144,14 @@ typedef struct NV9067_CTRL_CWD_WATERMARK_PARAMS { NvU32 watermarkValue; } NV9067_CTRL_CWD_WATERMARK_PARAMS; +#define NV9067_CTRL_GET_CWD_WATERMARK_PARAMS_MESSAGE_ID (0x1U) + +typedef NV9067_CTRL_CWD_WATERMARK_PARAMS NV9067_CTRL_GET_CWD_WATERMARK_PARAMS; + +#define NV9067_CTRL_CMD_SET_CWD_WATERMARK (0x90670202) /* finn: Evaluated from "(FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK_INTERFACE_ID << 8) | NV9067_CTRL_SET_CWD_WATERMARK_PARAMS_MESSAGE_ID" */ + +#define NV9067_CTRL_SET_CWD_WATERMARK_PARAMS_MESSAGE_ID (0x2U) + +typedef NV9067_CTRL_CWD_WATERMARK_PARAMS NV9067_CTRL_SET_CWD_WATERMARK_PARAMS; /* _ctrl9067_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h b/src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h index 20d94dd1e..7bd3b5f20 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h @@ -81,7 +81,9 @@ typedef struct NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS { /*! * Get VAS page level information. */ -#define NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO (0x90f10102U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | 0x2" */ +#define NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO (0x90f10102U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID" */ + +#define NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID (0x2U) typedef struct NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS { /*! @@ -232,7 +234,11 @@ typedef struct NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS { * Get VAS page level information without kernel priviledge. This will internally call * NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO. */ -#define NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO_VERIF (0x90f10105U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | 0x5" */ +#define NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO_VERIF (0x90f10105U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS_MESSAGE_ID" */ + +#define NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS_MESSAGE_ID (0x5U) + +typedef NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS; /*! * Pin PDEs for a given VA range on the server RM and then mirror the client's page diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla06c.h b/src/common/sdk/nvidia/inc/ctrl/ctrla06c.h index 775ce948b..a77df66c2 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrla06c.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla06c.h @@ -94,21 +94,12 @@ * NV_ERR_INVALID_OPERATION * */ -#define NVA06C_CTRL_CMD_GPFIFO_SCHEDULE (0xa06c0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */ +#define NVA06C_CTRL_CMD_GPFIFO_SCHEDULE (0xa06c0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */ + +#define NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x1U) + typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA06C_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x1U) - -typedef struct NVA06C_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS { - NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS params; -} NVA06C_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS; - - - - /* * NVA06C_CTRL_CMD_BIND * @@ -152,7 +143,15 @@ typedef NVA06F_CTRL_BIND_PARAMS NVA06C_CTRL_BIND_PARAMS; * NV_ERR_INVALID_ARGUMENT * NV_ERR_INVALID_STATE */ -#define NVA06C_CTRL_CMD_SET_TIMESLICE (0xa06c0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | 0x3" */ +#define NVA06C_CTRL_CMD_SET_TIMESLICE (0xa06c0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_SET_TIMESLICE_PARAMS_MESSAGE_ID" */ + +typedef struct NVA06C_CTRL_TIMESLICE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 timesliceUs, 8); +} NVA06C_CTRL_TIMESLICE_PARAMS; + +#define NVA06C_CTRL_SET_TIMESLICE_PARAMS_MESSAGE_ID (0x3U) + +typedef NVA06C_CTRL_TIMESLICE_PARAMS NVA06C_CTRL_SET_TIMESLICE_PARAMS; /* * NVA06C_CTRL_CMD_GET_TIMESLICE @@ -170,11 +169,11 @@ typedef NVA06F_CTRL_BIND_PARAMS NVA06C_CTRL_BIND_PARAMS; * NV_ERR_INVALID_ARGUMENT * NV_ERR_INVALID_STATE */ -#define NVA06C_CTRL_CMD_GET_TIMESLICE (0xa06c0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | 0x4" */ +#define NVA06C_CTRL_CMD_GET_TIMESLICE (0xa06c0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_GET_TIMESLICE_PARAMS_MESSAGE_ID" */ -typedef struct NVA06C_CTRL_TIMESLICE_PARAMS { - NV_DECLARE_ALIGNED(NvU64 timesliceUs, 8); -} NVA06C_CTRL_TIMESLICE_PARAMS; +#define NVA06C_CTRL_GET_TIMESLICE_PARAMS_MESSAGE_ID (0x4U) + +typedef NVA06C_CTRL_TIMESLICE_PARAMS NVA06C_CTRL_GET_TIMESLICE_PARAMS; /* * NVA06C_CTRL_CMD_PREEMPT @@ -266,7 +265,19 @@ typedef struct NVA06C_CTRL_GET_INFO_PARAMS { * NV_ERR_INVALID_STATE * NV_ERR_INSUFFICIENT_PERMISSIONS */ -#define NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL (0xa06c0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */ +#define NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL (0xa06c0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_SET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID" */ + +typedef struct NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS { + NvU32 tsgInterleaveLevel; +} NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS; + +#define NVA06C_CTRL_INTERLEAVE_LEVEL_LOW (0x00000000) +#define NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM (0x00000001) +#define NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH (0x00000002) + +#define NVA06C_CTRL_SET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID (0x7U) + +typedef NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS NVA06C_CTRL_SET_INTERLEAVE_LEVEL_PARAMS; /* * NVA06C_CTRL_CMD_GET_INTERLEAVE_LEVEL @@ -284,15 +295,11 @@ typedef struct NVA06C_CTRL_GET_INFO_PARAMS { * NV_ERR_INVALID_ARGUMENT * NV_ERR_INVALID_STATE */ -#define NVA06C_CTRL_CMD_GET_INTERLEAVE_LEVEL (0xa06c0108) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | 0x8" */ +#define NVA06C_CTRL_CMD_GET_INTERLEAVE_LEVEL (0xa06c0108) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO_INTERFACE_ID << 8) | NVA06C_CTRL_GET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID" */ -typedef struct NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS { - NvU32 tsgInterleaveLevel; -} NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS; +#define NVA06C_CTRL_GET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID (0x8U) -#define NVA06C_CTRL_INTERLEAVE_LEVEL_LOW (0x00000000) -#define NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM (0x00000001) -#define NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH (0x00000002) +typedef NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS NVA06C_CTRL_GET_INTERLEAVE_LEVEL_PARAMS; /* * NVA06C_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE @@ -404,7 +411,11 @@ typedef struct NVA06C_CTRL_MAKE_REALTIME_PARAMS { * Please see description of NVA06C_CTRL_CMD_GPFIFO_SCHEDULE for more information. * */ -#define NVA06C_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE (0xa06c0201) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL_INTERFACE_ID << 8) | 0x1" */ +#define NVA06C_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE (0xa06c0201) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL_INTERFACE_ID << 8) | NVA06C_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */ + +#define NVA06C_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x1U) + +typedef NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS NVA06C_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS; /* * NVA06C_CTRL_CMD_INTERNAL_SET_TIMESLICE @@ -415,7 +426,11 @@ typedef struct NVA06C_CTRL_MAKE_REALTIME_PARAMS { * Please see description of NVA06C_CTRL_CMD_SET_TIMESLICE for more information. * */ -#define NVA06C_CTRL_CMD_INTERNAL_SET_TIMESLICE (0xa06c0202) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL_INTERFACE_ID << 8) | 0x2" */ +#define NVA06C_CTRL_CMD_INTERNAL_SET_TIMESLICE (0xa06c0202) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL_INTERFACE_ID << 8) | NVA06C_CTRL_INTERNAL_SET_TIMESLICE_PARAMS_MESSAGE_ID" */ + +#define NVA06C_CTRL_INTERNAL_SET_TIMESLICE_PARAMS_MESSAGE_ID (0x2U) + +typedef NVA06C_CTRL_TIMESLICE_PARAMS NVA06C_CTRL_INTERNAL_SET_TIMESLICE_PARAMS; /* _ctrla06c.h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h b/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h index 699e6c68f..32b179170 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h @@ -38,41 +38,23 @@ * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information. * */ -#define NVA06F_CTRL_GET_CLASS_ENGINEID (0xa06f0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */ +#define NVA06F_CTRL_GET_CLASS_ENGINEID (0xa06f0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID" */ + +#define NVA06F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID (0x1U) typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVA06F_CTRL_GET_CLASS_ENGINEID_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U) - -typedef struct NVA06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS { - NVA06F_CTRL_GET_CLASS_ENGINEID_PARAMS params; -} NVA06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS; - - - /* * NVA06F_CTRL_RESET_CHANNEL * * Please see description of NV906F_CTRL_RESET_CHANNEL for more information. */ -#define NVA06F_CTRL_CMD_RESET_CHANNEL (0xa06f0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x2" */ +#define NVA06F_CTRL_CMD_RESET_CHANNEL (0xa06f0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U) typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U) - -typedef struct NVA06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS { - NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS params; -} NVA06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS; - - - /* * NVA06F_CTRL_CMD_GPFIFO_SCHEDULE * @@ -137,21 +119,12 @@ typedef struct NVA06F_CTRL_BIND_PARAMS { * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. * */ -#define NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xa06f0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */ +#define NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xa06f0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */ + +#define NVA06F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x7U) typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVA06F_CTRL_GET_MMU_FAULT_INFO_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U) - -typedef struct NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS { - NV_DECLARE_ALIGNED(NVA06F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8); -} NVA06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS; - - - /* * NVA06F_CTRL_CMD_SET_ERROR_NOTIFIER * @@ -192,7 +165,15 @@ typedef struct NVA06F_CTRL_SET_ERROR_NOTIFIER_PARAMS { * NV_ERR_INVALID_STATE * NV_ERR_INSUFFICIENT_PERMISSIONS */ -#define NVA06F_CTRL_CMD_SET_INTERLEAVE_LEVEL (0xa06f0109) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x9" */ +#define NVA06F_CTRL_CMD_SET_INTERLEAVE_LEVEL (0xa06f0109) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_SET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID" */ + +typedef struct NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS { + NvU32 channelInterleaveLevel; +} NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS; + +#define NVA06F_CTRL_SET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID (0x9U) + +typedef NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS NVA06F_CTRL_SET_INTERLEAVE_LEVEL_PARAMS; /* * NVA06F_CTRL_CMD_GET_INTERLEAVE_LEVEL @@ -210,11 +191,11 @@ typedef struct NVA06F_CTRL_SET_ERROR_NOTIFIER_PARAMS { * NV_ERR_INVALID_ARGUMENT * NV_ERR_INVALID_STATE */ -#define NVA06F_CTRL_CMD_GET_INTERLEAVE_LEVEL (0xa06f0110) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x10" */ +#define NVA06F_CTRL_CMD_GET_INTERLEAVE_LEVEL (0xa06f0110) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_GET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID" */ -typedef struct NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS { - NvU32 channelInterleaveLevel; -} NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS; +#define NVA06F_CTRL_GET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID (0x10U) + +typedef NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS NVA06F_CTRL_GET_INTERLEAVE_LEVEL_PARAMS; /* * NVA06F_CTRL_CMD_RESTART_RUNLIST diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06finternal.h b/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06finternal.h index 7a37815a5..83e064dcf 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06finternal.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06finternal.h @@ -40,7 +40,11 @@ * Please see description of NVA06F_CTRL_CMD_STOP_CHANNEL for more information. * */ -#define NVA06F_CTRL_CMD_INTERNAL_STOP_CHANNEL (0xa06f0301) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | 0x1" */ +#define NVA06F_CTRL_CMD_INTERNAL_STOP_CHANNEL (0xa06f0301) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | NVA06F_CTRL_INTERNAL_STOP_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NVA06F_CTRL_INTERNAL_STOP_CHANNEL_PARAMS_MESSAGE_ID (0x1U) + +typedef NVA06F_CTRL_STOP_CHANNEL_PARAMS NVA06F_CTRL_INTERNAL_STOP_CHANNEL_PARAMS; /* * NVA06F_CTRL_CMD_INTERNAL_RESET_CHANNEL @@ -51,7 +55,11 @@ * Please see description of NV906F_CTRL_CMD_RESET_CHANNEL for more information. * */ -#define NVA06F_CTRL_CMD_INTERNAL_RESET_CHANNEL (0xa06f0302) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | 0x2" */ +#define NVA06F_CTRL_CMD_INTERNAL_RESET_CHANNEL (0xa06f0302) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | NVA06F_CTRL_INTERNAL_RESET_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NVA06F_CTRL_INTERNAL_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U) + +typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVA06F_CTRL_INTERNAL_RESET_CHANNEL_PARAMS; /* * NVA06F_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE @@ -62,6 +70,10 @@ * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. * */ -#define NVA06F_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE (0xa06f0303) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | 0x3" */ +#define NVA06F_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE (0xa06f0303) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID << 8) | NVA06F_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */ + +#define NVA06F_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x3U) + +typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVA06F_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS; /* ctrla06finternal_h */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla080.h b/src/common/sdk/nvidia/inc/ctrl/ctrla080.h index 3cd06b09c..29ad3ef53 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrla080.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla080.h @@ -280,15 +280,19 @@ typedef struct NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS { * */ -#define NVA080_CTRL_CMD_MAP_SEMA_MEM (0xa0800202) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | 0x2" */ +#define NVA080_CTRL_CMD_MAP_SEMA_MEM (0xa0800202) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_MAP_SEMA_MEM_PARAMS_MESSAGE_ID" */ -typedef struct NVA080_CTRL_MAP_SEMA_MEM_PARAMS { +typedef struct NVA080_CTRL_SEMA_MEM_PARAMS { NvHandle hClient; NvHandle hDevice; NvHandle hMemory; NvHandle hCtxDma; NV_DECLARE_ALIGNED(NvU64 semaAddress, 8); -} NVA080_CTRL_MAP_SEMA_MEM_PARAMS; +} NVA080_CTRL_SEMA_MEM_PARAMS; + +#define NVA080_CTRL_MAP_SEMA_MEM_PARAMS_MESSAGE_ID (0x2U) + +typedef NVA080_CTRL_SEMA_MEM_PARAMS NVA080_CTRL_MAP_SEMA_MEM_PARAMS; /* * NVA080_CTRL_CMD_UNMAP_SEMA_MEM @@ -308,7 +312,11 @@ typedef struct NVA080_CTRL_MAP_SEMA_MEM_PARAMS { * */ -#define NVA080_CTRL_CMD_UNMAP_SEMA_MEM (0xa0800203) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | 0x3" */ +#define NVA080_CTRL_CMD_UNMAP_SEMA_MEM (0xa0800203) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_UNMAP_SEMA_MEM_PARAMS_MESSAGE_ID" */ + +#define NVA080_CTRL_UNMAP_SEMA_MEM_PARAMS_MESSAGE_ID (0x3U) + +typedef NVA080_CTRL_SEMA_MEM_PARAMS NVA080_CTRL_UNMAP_SEMA_MEM_PARAMS; /*! * NVA080_CTRL_CMD_SET_FB_USAGE @@ -322,7 +330,7 @@ typedef struct NVA080_CTRL_MAP_SEMA_MEM_PARAMS { * Possible status values returned are: * NV_OK */ -#define NVA080_CTRL_CMD_SET_FB_USAGE (0xa0800204) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_SET_FB_USAGE_PARAMS_MESSAGE_ID" */ +#define NVA080_CTRL_CMD_SET_FB_USAGE (0xa0800204) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_SET_FB_USAGE_PARAMS_MESSAGE_ID" */ #define NVA080_CTRL_SET_FB_USAGE_PARAMS_MESSAGE_ID (0x4U) @@ -364,16 +372,18 @@ typedef struct NVA080_CTRL_SET_FB_USAGE_PARAMS { #define NVA080_CTRL_CMD_MAP_PER_ENGINE_SEMA_MEM (0xa0800205) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID" */ -#define NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID (0x5U) - -typedef struct NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS { +typedef struct NVA080_CTRL_PER_ENGINE_SEMA_MEM_PARAMS { NvU32 hClient; NvU32 hDevice; NvHandle hMemory; NvU32 hCtxDma; NV_DECLARE_ALIGNED(NvU64 semaAddress, 8); NvU32 semaStride; -} NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS; +} NVA080_CTRL_PER_ENGINE_SEMA_MEM_PARAMS; + +#define NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID (0x5U) + +typedef NVA080_CTRL_PER_ENGINE_SEMA_MEM_PARAMS NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS; /*! * NVA080_CTRL_CMD_UNMAP_PER_ENGINE_SEMA_MEM @@ -392,7 +402,7 @@ typedef struct NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS { #define NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID (0x6U) -typedef NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS; +typedef NVA080_CTRL_PER_ENGINE_SEMA_MEM_PARAMS NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS; /* * NVA080_CTRL_CMD_UPDATE_SYSMEM_BITMAP diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla081.h b/src/common/sdk/nvidia/inc/ctrl/ctrla081.h index 35876db4f..e85964d5f 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrla081.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla081.h @@ -349,7 +349,11 @@ typedef struct NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS { * NV_ERR_NOT_SUPPORTED */ -#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES (0xa0810104) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | 0x4" */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES (0xa0810104) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES_PARAMS_MESSAGE_ID (0x4U) + +typedef NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS NVA081_CTRL_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES_PARAMS; /* * NVA081_CTRL_CMD_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES @@ -370,7 +374,11 @@ typedef struct NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS { * NV_ERR_NOT_SUPPORTED */ -#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES (0xa0810105) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | 0x5" */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES (0xa0810105) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES_PARAMS_MESSAGE_ID (0x5U) + +typedef NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES_PARAMS; /* * NVA081_CTRL_CMD_VGPU_CONFIG_EVENT_SET_NOTIFICATION @@ -403,7 +411,7 @@ typedef struct NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS { * NV_ERR_INVALID_ARGUMENT * NV_ERR_INVALID_STATE */ -#define NVA081_CTRL_CMD_VGPU_CONFIG_EVENT_SET_NOTIFICATION (0xa0810106) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_EVENT_SET_NOTIFICATION (0xa0810106) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ #define NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x6U) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla084.h b/src/common/sdk/nvidia/inc/ctrl/ctrla084.h index f5a514684..8145c27b1 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrla084.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla084.h @@ -63,8 +63,7 @@ #define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS_MESSAGE_ID (0x1U) typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS { - NvU8 vgpuUuid[NV2080_GPU_MAX_GID_LENGTH]; - NvU32 vgpuDeviceInstanceId; + NvU8 vgpuUuid[NV2080_GPU_MAX_GID_LENGTH]; } NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS; /* NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE @@ -296,7 +295,42 @@ typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS { NV_DECLARE_ALIGNED(VM_ID guestVmId, 8); } NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS; -#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_ACTION_SET (0x00000000) -#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_ACTION_UNSET (0x00000001) +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_ACTION_SET (0x00000000) +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_ACTION_UNSET (0x00000001) + +/* NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_GER_BAR_MAPPING_RANGES + * + * This command is used to get Bar mapping ranges in RM. + * + * Parameters: + * offsets [OUT] + * Offsets of the ranges + * sizes [OUT] + * Sizes of the ranges + * mitigated [OUT] + * Specifies whether it's mitigated range + * numRanges [OUT] + * Number of ranges + * + * osPageSize [IN] + * Page size. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES (0xa084010a) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_MAX_BAR_MAPPING_RANGES 10 + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS { + NV_DECLARE_ALIGNED(NvU64 offsets[NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_MAX_BAR_MAPPING_RANGES], 8); + NV_DECLARE_ALIGNED(NvU64 sizes[NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_MAX_BAR_MAPPING_RANGES], 8); + NvU32 numRanges; + NvU32 osPageSize; + NvBool mitigated[NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_MAX_BAR_MAPPING_RANGES]; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS; /* _ctrla084_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla16f.h b/src/common/sdk/nvidia/inc/ctrl/ctrla16f.h index 7cf7069eb..eceee332d 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrla16f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla16f.h @@ -65,101 +65,58 @@ * Please see description of NVA06F_CTRL_GET_CLASS_ENGINEID for more information. * */ -#define NVA16F_CTRL_GET_CLASS_ENGINEID (0xa16f0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | 0x1" */ +#define NVA16F_CTRL_GET_CLASS_ENGINEID (0xa16f0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | NVA16F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID" */ + +#define NVA16F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID (0x1U) typedef NVA06F_CTRL_GET_CLASS_ENGINEID_PARAMS NVA16F_CTRL_GET_CLASS_ENGINEID_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA16F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U) - -typedef struct NVA16F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS { - NVA16F_CTRL_GET_CLASS_ENGINEID_PARAMS params; -} NVA16F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS; - - - /* * NVA16F_CTRL_RESET_CHANNEL * * Please see description of NVA06F_CTRL_RESET_CHANNEL for more information. * */ -#define NVA16F_CTRL_CMD_RESET_CHANNEL (0xa16f0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | 0x2" */ +#define NVA16F_CTRL_CMD_RESET_CHANNEL (0xa16f0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | NVA16F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NVA16F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U) + typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVA16F_CTRL_CMD_RESET_CHANNEL_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA16F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U) - -typedef struct NVA16F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS { - NVA16F_CTRL_CMD_RESET_CHANNEL_PARAMS params; -} NVA16F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS; - - - /* * NVA16F_CTRL_CMD_GPFIFO_SCHEDULE * * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. * */ -#define NVA16F_CTRL_CMD_GPFIFO_SCHEDULE (0xa16f0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | 0x3" */ +#define NVA16F_CTRL_CMD_GPFIFO_SCHEDULE (0xa16f0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | NVA16F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */ + +#define NVA16F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x3U) + typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVA16F_CTRL_GPFIFO_SCHEDULE_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA16F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x3U) - -typedef struct NVA16F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS { - NVA16F_CTRL_GPFIFO_SCHEDULE_PARAMS params; -} NVA16F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS; - - - /* * NVA16F_CTRL_CMD_BIND * * Please see description of NVA06F_CTRL_CMD_BIND for more information. */ -#define NVA16F_CTRL_CMD_BIND (0xa16f0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | 0x4" */ +#define NVA16F_CTRL_CMD_BIND (0xa16f0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | NVA16F_CTRL_BIND_PARAMS_MESSAGE_ID" */ + +#define NVA16F_CTRL_BIND_PARAMS_MESSAGE_ID (0x4U) typedef NVA06F_CTRL_BIND_PARAMS NVA16F_CTRL_BIND_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA16F_CTRL_CMD_BIND_FINN_PARAMS_MESSAGE_ID (0x4U) - -typedef struct NVA16F_CTRL_CMD_BIND_FINN_PARAMS { - NVA16F_CTRL_BIND_PARAMS params; -} NVA16F_CTRL_CMD_BIND_FINN_PARAMS; - - - /* * NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION * * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. */ -#define NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xa16f0205) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT_INTERFACE_ID << 8) | 0x5" */ +#define NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xa16f0205) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT_INTERFACE_ID << 8) | NVA16F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NVA16F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x5U) typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVA16F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS_MESSAGE_ID (0x5U) - -typedef struct NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS { - NVA16F_CTRL_EVENT_SET_NOTIFICATION_PARAMS params; -} NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS; - - - /* valid action values */ #define NVA16F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE #define NVA16F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE @@ -182,19 +139,10 @@ typedef struct NVA16F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS { * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. * */ -#define NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO (0xa16f0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | 0x7" */ +#define NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO (0xa16f0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_GPFIFO_INTERFACE_ID << 8) | NVA16F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */ + +#define NVA16F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x7U) typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVA16F_CTRL_GET_MMU_FAULT_INFO_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U) - -typedef struct NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS { - NV_DECLARE_ALIGNED(NVA16F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8); -} NVA16F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS; - - - /* _ctrla16f.h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla26f.h b/src/common/sdk/nvidia/inc/ctrl/ctrla26f.h index 6dcf9306a..5e222a48d 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrla26f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla26f.h @@ -65,101 +65,58 @@ * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information. * */ -#define NVA26F_CTRL_GET_CLASS_ENGINEID (0xa26f0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | 0x1" */ +#define NVA26F_CTRL_GET_CLASS_ENGINEID (0xa26f0101) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | NVA26F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID" */ + +#define NVA26F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID (0x1U) typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVA26F_CTRL_GET_CLASS_ENGINEID_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA26F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U) - -typedef struct NVA26F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS { - NVA26F_CTRL_GET_CLASS_ENGINEID_PARAMS params; -} NVA26F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS; - - - /* * NVA26F_CTRL_RESET_CHANNEL * * Please see description of NVA06F_CTRL_CMD_RESET_CHANNEL for more information. * */ -#define NVA26F_CTRL_CMD_RESET_CHANNEL (0xa26f0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | 0x2" */ +#define NVA26F_CTRL_CMD_RESET_CHANNEL (0xa26f0102) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | NVA26F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NVA26F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U) + typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVA26F_CTRL_CMD_RESET_CHANNEL_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA26F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U) - -typedef struct NVA26F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS { - NVA26F_CTRL_CMD_RESET_CHANNEL_PARAMS params; -} NVA26F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS; - - - /* * NVA26F_CTRL_CMD_GPFIFO_SCHEDULE * * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. * */ -#define NVA26F_CTRL_CMD_GPFIFO_SCHEDULE (0xa26f0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | 0x3" */ +#define NVA26F_CTRL_CMD_GPFIFO_SCHEDULE (0xa26f0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | NVA26F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */ + +#define NVA26F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x3U) + typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVA26F_CTRL_GPFIFO_SCHEDULE_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA26F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x3U) - -typedef struct NVA26F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS { - NVA26F_CTRL_GPFIFO_SCHEDULE_PARAMS params; -} NVA26F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS; - - - /* * NVA26F_CTRL_CMD_BIND * * Please see description of NVA06F_CTRL_CMD_BIND for more information. */ -#define NVA26F_CTRL_CMD_BIND (0xa26f0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | 0x4" */ +#define NVA26F_CTRL_CMD_BIND (0xa26f0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | NVA26F_CTRL_BIND_PARAMS_MESSAGE_ID" */ + +#define NVA26F_CTRL_BIND_PARAMS_MESSAGE_ID (0x4U) typedef NVA06F_CTRL_BIND_PARAMS NVA26F_CTRL_BIND_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA26F_CTRL_CMD_BIND_FINN_PARAMS_MESSAGE_ID (0x4U) - -typedef struct NVA26F_CTRL_CMD_BIND_FINN_PARAMS { - NVA26F_CTRL_BIND_PARAMS params; -} NVA26F_CTRL_CMD_BIND_FINN_PARAMS; - - - /* * NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION * * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. */ -#define NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xa26f0205) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT_INTERFACE_ID << 8) | 0x5" */ +#define NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xa26f0205) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT_INTERFACE_ID << 8) | NVA26F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NVA26F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x5U) typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVA26F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS_MESSAGE_ID (0x5U) - -typedef struct NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS { - NVA26F_CTRL_EVENT_SET_NOTIFICATION_PARAMS params; -} NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS; - - - /* valid action values */ #define NVA26F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE #define NVA26F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE @@ -182,19 +139,10 @@ typedef struct NVA26F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS { * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. * */ -#define NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO (0xa26f0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | 0x7" */ +#define NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO (0xa26f0107) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_GPFIFO_INTERFACE_ID << 8) | NVA26F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */ + +#define NVA26F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x7U) typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVA26F_CTRL_GET_MMU_FAULT_INFO_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U) - -typedef struct NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS { - NV_DECLARE_ALIGNED(NVA26F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8); -} NVA26F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS; - - - /* _ctrla26f.h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlb069.h b/src/common/sdk/nvidia/inc/ctrl/ctrlb069.h index 66eb26d3a..ce7399107 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlb069.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlb069.h @@ -161,6 +161,8 @@ typedef struct NVB069_CTRL_FAULTBUFFER_GET_SIZE_PARAMS { * Mapping for PMC intr clear register - used to disable an intr (NV_PMC_INTR_EN_CLEAR(0)) * replayableFaultMask * Mask for the replayable fault bit(NV_PMC_INTR_REPLAYABLE_FAULT) + * faultBufferType + * This is an input param denoting replayable/non-replayable fault buffer */ #define NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS (0xb0690106) /* finn: Evaluated from "(FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID << 8) | NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS_MESSAGE_ID" */ @@ -175,6 +177,7 @@ typedef struct NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS { NV_DECLARE_ALIGNED(NvP64 pPmcIntrEnClear, 8); NvU32 replayableFaultMask; NV_DECLARE_ALIGNED(NvP64 pPrefetchCtrl, 8); + NvU32 faultBufferType; } NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS; /* _ctrlb069_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlb06f.h b/src/common/sdk/nvidia/inc/ctrl/ctrlb06f.h index 14a61997c..ddfac2b05 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlb06f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlb06f.h @@ -67,103 +67,58 @@ * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information. * */ -#define NVB06F_CTRL_GET_CLASS_ENGINEID (0xb06f0101) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */ +#define NVB06F_CTRL_GET_CLASS_ENGINEID (0xb06f0101) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID" */ + +#define NVB06F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID (0x1U) typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVB06F_CTRL_GET_CLASS_ENGINEID_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVB06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U) - -typedef struct NVB06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS { - NVB06F_CTRL_GET_CLASS_ENGINEID_PARAMS params; -} NVB06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS; - - - /* * NVB06F_CTRL_RESET_CHANNEL * * Please see description of NVA06F_CTRL_RESET_CHANNEL for more information. * */ -#define NVB06F_CTRL_CMD_RESET_CHANNEL (0xb06f0102) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x2" */ +#define NVB06F_CTRL_CMD_RESET_CHANNEL (0xb06f0102) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NVB06F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U) typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVB06F_CTRL_CMD_RESET_CHANNEL_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVB06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U) - -typedef struct NVB06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS { - NVB06F_CTRL_CMD_RESET_CHANNEL_PARAMS params; -} NVB06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS; - - - /* * NVB06F_CTRL_CMD_GPFIFO_SCHEDULE * * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. * */ -#define NVB06F_CTRL_CMD_GPFIFO_SCHEDULE (0xb06f0103) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x3" */ +#define NVB06F_CTRL_CMD_GPFIFO_SCHEDULE (0xb06f0103) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */ + +#define NVB06F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x3U) typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVB06F_CTRL_GPFIFO_SCHEDULE_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVB06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x3U) - -typedef struct NVB06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS { - NVB06F_CTRL_GPFIFO_SCHEDULE_PARAMS params; -} NVB06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS; - - - /* * NVB06F_CTRL_CMD_BIND * * Please see description of NVA06F_CTRL_CMD_BIND for more information. */ -#define NVB06F_CTRL_CMD_BIND (0xb06f0104) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x4" */ +#define NVB06F_CTRL_CMD_BIND (0xb06f0104) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_BIND_PARAMS_MESSAGE_ID" */ + +#define NVB06F_CTRL_BIND_PARAMS_MESSAGE_ID (0x4U) typedef NVA06F_CTRL_BIND_PARAMS NVB06F_CTRL_BIND_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVB06F_CTRL_CMD_BIND_FINN_PARAMS_MESSAGE_ID (0x4U) - -typedef struct NVB06F_CTRL_CMD_BIND_FINN_PARAMS { - NVB06F_CTRL_BIND_PARAMS params; -} NVB06F_CTRL_CMD_BIND_FINN_PARAMS; - - - /* * NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION * * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. */ -#define NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xb06f0205) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x5" */ +#define NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xb06f0205) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | NVB06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NVB06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x5U) typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVB06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS_MESSAGE_ID (0x5U) - -typedef struct NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS { - NVB06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS params; -} NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS; - - - /* valid action values */ #define NVB06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE #define NVB06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE @@ -186,21 +141,12 @@ typedef struct NVB06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS { * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. * */ -#define NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xb06f0107) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */ +#define NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xb06f0107) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */ + +#define NVB06F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x7U) typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVB06F_CTRL_GET_MMU_FAULT_INFO_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U) - -typedef struct NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS { - NV_DECLARE_ALIGNED(NVB06F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8); -} NVB06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS; - - - /* * NVB06F_CTRL_CMD_GET_ENGINE_CTX_SIZE * @@ -288,21 +234,12 @@ typedef struct NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS { * NV_ERR_INVALID_STATE */ -#define NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA (0xb06f010d) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS_MESSAGE_ID" */ +#define NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA (0xb06f010d) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_MIGRATE_ENGINE_CTX_DATA_PARAMS_MESSAGE_ID" */ + +#define NVB06F_CTRL_MIGRATE_ENGINE_CTX_DATA_PARAMS_MESSAGE_ID (0xDU) typedef NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS NVB06F_CTRL_MIGRATE_ENGINE_CTX_DATA_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS_MESSAGE_ID (0xDU) - -typedef struct NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS { - NV_DECLARE_ALIGNED(NVB06F_CTRL_MIGRATE_ENGINE_CTX_DATA_PARAMS params, 8); -} NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS; - - - /* * NVB06F_CTRL_CMD_GET_ENGINE_CTX_STATE * @@ -399,11 +336,13 @@ typedef struct NVB06F_CTRL_GET_ENGINE_CTX_STATE_PARAMS { #define NVB06F_CTRL_CMD_CHANNEL_HW_STATE_PBDMA_FAULTED 4:4 #define NVB06F_CTRL_CMD_CHANNEL_HW_STATE_ACQUIRE_FAIL 5:5 +typedef struct NVB06F_CTRL_CHANNEL_HW_STATE_PARAMS { + NvU32 state; +} NVB06F_CTRL_CHANNEL_HW_STATE_PARAMS; + #define NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS_MESSAGE_ID (0xFU) -typedef struct NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS { - NvU32 state; -} NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS; +typedef NVB06F_CTRL_CHANNEL_HW_STATE_PARAMS NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS; /* * NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE @@ -449,18 +388,11 @@ typedef struct NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS { * NV_OK * NV_ERR_INVALID_STATE */ -#define NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE (0xb06f0110) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x10" */ +#define NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE (0xb06f0110) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVB06F_CTRL_SET_CHANNEL_HW_STATE_PARAMS_MESSAGE_ID" */ -typedef NVB06F_CTRL_GET_CHANNEL_HW_STATE_PARAMS NVB06F_CTRL_SET_CHANNEL_HW_STATE_PARAMS; +#define NVB06F_CTRL_SET_CHANNEL_HW_STATE_PARAMS_MESSAGE_ID (0x10U) -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE_FINN_PARAMS_MESSAGE_ID (0x10U) - -typedef struct NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE_FINN_PARAMS { - NVB06F_CTRL_SET_CHANNEL_HW_STATE_PARAMS params; -} NVB06F_CTRL_CMD_SET_CHANNEL_HW_STATE_FINN_PARAMS; +typedef NVB06F_CTRL_CHANNEL_HW_STATE_PARAMS NVB06F_CTRL_SET_CHANNEL_HW_STATE_PARAMS; /* * NVB06F_CTRL_CMD_SAVE_ENGINE_CTX_DATA diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h b/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h index 54e2dbdc4..f98a32dda 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h @@ -36,7 +36,7 @@ /*! * @ref NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM */ -#define NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM (0xb0cc0200) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS_MESSAGE_ID" */ +#define NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM (0xb0cc0204) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID" */ // FINN PORT: The below type was generated by the FINN port to @@ -76,4 +76,123 @@ typedef struct NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS { NvBool bMemoryProfilingPermitted; } NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS; +#define NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS { + /*! + * [in] Memory handle (RW memory) for streaming records. + * Size of this must be >= @ref pmaBufferOffset + @ref pmaBufferSize. + */ + NvHandle hMemPmaBuffer; + + /*! + * [in] Start offset of PMA buffer (offset in @ref hMemPmaBuffer). + */ + NV_DECLARE_ALIGNED(NvU64 pmaBufferOffset, 8); + + /*! + * [in] size of the buffer. This must be <= NVB0CC_PMA_BUFFER_SIZE_MAX. + */ + NV_DECLARE_ALIGNED(NvU64 pmaBufferSize, 8); + + /*! + * [in] Memory handle (RO memory) for streaming number of bytes available. + * Size of this must be of at least @ref pmaBytesAvailableOffset + + * @ref NVB0CC_PMA_BYTES_AVAILABLE_SIZE. + */ + NvHandle hMemPmaBytesAvailable; + + /*! + * [in] Start offset of PMA bytes available buffer (offset in @ref hMemPmaBytesAvailable). + */ + NV_DECLARE_ALIGNED(NvU64 pmaBytesAvailableOffset, 8); + + /*! + * [in] Enable ctxsw for PMA stream. + */ + NvBool ctxsw; + + /*! + * [in/out] The PMA Channel Index associated with a given PMA stream. + * This parameter is input when bInputPmaChIdx is true, else it's output parameter. + */ + NvU32 pmaChannelIdx; + + /*! + * [out] PMA buffer VA. Note that this is a HWPM Virtual address. + */ + NV_DECLARE_ALIGNED(NvU64 pmaBufferVA, 8); + + /*! + * [In] This field must be specified by the client to indicate whether the + * pmaChannelIdx is input parameter or output parameter. + */ + NvBool bInputPmaChIdx; +} NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS; + + + +/*! + * NVB0CC_CTRL_CMD_INTERNAL_FREE_PMA_STREAM + * + * Internal logic for PMA Stream Free + */ +#define NVB0CC_CTRL_CMD_INTERNAL_FREE_PMA_STREAM (0xb0cc0206) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS { + /*! + * [in] The PMA channel index associated with a given PMA stream. + */ + NvU32 pmaChannelIdx; +} NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_INTERNAL_GET_MAX_PMAS + * + * Get the maximum number of PMA channels + */ +#define NVB0CC_CTRL_CMD_INTERNAL_GET_MAX_PMAS (0xb0cc0207) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS { + /*! + * [out] Max number of PMA channels + */ + NvU32 maxPmaChannels; +} NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_INTERNAL_BIND_PM_RESOURCES + * + * Internally bind PM resources. + */ +#define NVB0CC_CTRL_CMD_INTERNAL_BIND_PM_RESOURCES (0xb0cc0208) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | 0x8" */ + + +/*! + * NVB0CC_CTRL_CMD_INTERNAL_UNBIND_PM_RESOURCES + * + * Internally unbind PM resources. + */ +#define NVB0CC_CTRL_CMD_INTERNAL_UNBIND_PM_RESOURCES (0xb0cc0209) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | 0x9" */ + +/*! + * NVB0CC_CTRL_CMD_INTERNAL_RESERVE_HWPM_LEGACY + * + * Reserve legacy HWPM resources + */ +#define NVB0CC_CTRL_CMD_INTERNAL_RESERVE_HWPM_LEGACY (0xb0cc020a) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS_MESSAGE_ID (0xaU) + +typedef struct NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS { + /*! + * [in] Enable ctxsw for HWPM. + */ + NvBool ctxsw; +} NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS; + /* _ctrlb0ccinternal_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h b/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h index d456c63c1..0e2685fe0 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h @@ -109,7 +109,7 @@ typedef struct NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS { * for streaming the updated bytes available in the buffer. * */ -#define NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM (0xb0cc0105) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x5" */ +#define NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM (0xb0cc0105) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID" */ /*! * Defines the maximum size of PMA buffer for streamout. It can be up to 4GB minus one page @@ -118,6 +118,8 @@ typedef struct NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS { #define NVB0CC_PMA_BUFFER_SIZE_MAX (0xffe00000ULL) /* finn: Evaluated from "(4 * 1024 * 1024 * 1024 - 2 * 1024 * 1024)" */ #define NVB0CC_PMA_BYTES_AVAILABLE_SIZE (0x1000) /* finn: Evaluated from "(4 * 1024)" */ +#define NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID (0x5U) + typedef struct NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS { /*! * [in] Memory handle (RW memory) for streaming records. @@ -181,6 +183,8 @@ typedef struct NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS { NvU32 pmaChannelIdx; } NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS; + + /*! * NVB0CC_CTRL_CMD_BIND_PM_RESOURCES * @@ -258,6 +262,11 @@ typedef struct NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS { * [in] The PMA Channel Index associated with a given PMA stream. */ NvU32 pmaChannelIdx; + + /*! + * [out] Set to TRUE if PMA buffer has overflowed. + */ + NvBool bOverflowStatus; } NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS; /*! @@ -440,9 +449,7 @@ typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS { #define NVB0CC_MAX_CREDIT_INFO_ENTRIES (63) -#define NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_MESSAGE_ID (0xEU) - -typedef struct NVB0CC_CTRL_SET_HS_CREDITS_PARAMS { +typedef struct NVB0CC_CTRL_HS_CREDITS_PARAMS { /*! * [in] The PMA Channel Index associated with a given PMA stream. */ @@ -462,7 +469,11 @@ typedef struct NVB0CC_CTRL_SET_HS_CREDITS_PARAMS { * [in] Credit programming per chiplet */ NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO creditInfo[NVB0CC_MAX_CREDIT_INFO_ENTRIES]; -} NVB0CC_CTRL_SET_HS_CREDITS_PARAMS; +} NVB0CC_CTRL_HS_CREDITS_PARAMS; + +#define NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_MESSAGE_ID (0xEU) + +typedef NVB0CC_CTRL_HS_CREDITS_PARAMS NVB0CC_CTRL_SET_HS_CREDITS_PARAMS; /*! * NVB0CC_CTRL_CMD_GET_HS_CREDITS @@ -470,10 +481,79 @@ typedef struct NVB0CC_CTRL_SET_HS_CREDITS_PARAMS { * Gets per chiplet (pmm router) high speed streaming credits for a pma channel. * */ -#define NVB0CC_CTRL_CMD_GET_HS_CREDITS (0xb0cc010f) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0xF" */ +#define NVB0CC_CTRL_CMD_GET_HS_CREDITS (0xb0cc010f) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_MESSAGE_ID" */ -typedef NVB0CC_CTRL_SET_HS_CREDITS_PARAMS NVB0CC_CTRL_GET_HS_CREDITS_PARAMS; +#define NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_MESSAGE_ID (0xFU) + +typedef NVB0CC_CTRL_HS_CREDITS_PARAMS NVB0CC_CTRL_GET_HS_CREDITS_PARAMS; +typedef enum NVB0CC_CTRL_HES_TYPE { + NVB0CC_CTRL_HES_INVALID = 0, + NVB0CC_CTRL_HES_CWD = 1, +} NVB0CC_CTRL_HES_TYPE; + +typedef struct NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS { + /*! + * [in] Enable ctxsw for HES_CWD. + */ + NvBool ctxsw; +} NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS; + +/* + * NVB0CC_CTRL_HES_RESERVATION_UNION + * + * Union of all HES reservation params + * + */ +typedef union NVB0CC_CTRL_HES_RESERVATION_UNION { + NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS cwd; +} NVB0CC_CTRL_HES_RESERVATION_UNION; + +/*! + * NVB0CC_CTRL_CMD_RESERVE_HES + * + * Reserves HES for use by the calling client. + * This PM system will only be accessible if this reservation is + * taken. + * + * This reservation can be released with @ref NVB0CC_CTRL_CMD_RELEASE_HES. + * + * Reservation scope and rules are same as for @ref NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY. + * + */ +#define NVB0CC_CTRL_CMD_RESERVE_HES (0xb0cc0113) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_RESERVE_HES_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_RESERVE_HES_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NVB0CC_CTRL_RESERVE_HES_PARAMS { + /*! + * [in] Denotes the HES reservation type. Choose from @NVB0CC_CTRL_HES_TYPE. + */ + NvU32 type; + + /*! + * [in] Union of all possible reserve param structs. Initialize the reserveParams corresponding to the chosen type. + */ + NVB0CC_CTRL_HES_RESERVATION_UNION reserveParams; +} NVB0CC_CTRL_RESERVE_HES_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_RELEASE_HES + * + * Releases the reservation taken with @ref NVB0CC_CTRL_CMD_RESERVE_HES. + * + */ +#define NVB0CC_CTRL_CMD_RELEASE_HES (0xb0cc0114) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_RELEASE_HES_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_RELEASE_HES_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NVB0CC_CTRL_RELEASE_HES_PARAMS { + /*! + * [in] type of @NVB0CC_CTRL_HES_TYPE needs to be released. + */ + NVB0CC_CTRL_HES_TYPE type; +} NVB0CC_CTRL_RELEASE_HES_PARAMS; + /* _ctrlb0ccprofiler_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc06f.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc06f.h index 1b493c7c6..8e7aadb6e 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc06f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc06f.h @@ -65,101 +65,58 @@ * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information. * */ -#define NVC06F_CTRL_GET_CLASS_ENGINEID (0xc06f0101) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */ +#define NVC06F_CTRL_GET_CLASS_ENGINEID (0xc06f0101) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC06F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID" */ + +#define NVC06F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID (0x1U) typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVC06F_CTRL_GET_CLASS_ENGINEID_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVC06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U) - -typedef struct NVC06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS { - NVC06F_CTRL_GET_CLASS_ENGINEID_PARAMS params; -} NVC06F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS; - - - /* * NVC06F_CTRL_RESET_CHANNEL * * Please see description of NVA06F_CTRL_RESET_CHANNEL for more information. * */ -#define NVC06F_CTRL_CMD_RESET_CHANNEL (0xc06f0102) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x2" */ +#define NVC06F_CTRL_CMD_RESET_CHANNEL (0xc06f0102) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC06F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NVC06F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U) + typedef NVA06F_CTRL_CMD_RESET_CHANNEL_PARAMS NVC06F_CTRL_CMD_RESET_CHANNEL_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVC06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U) - -typedef struct NVC06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS { - NVC06F_CTRL_CMD_RESET_CHANNEL_PARAMS params; -} NVC06F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS; - - - /* * NVC06F_CTRL_CMD_GPFIFO_SCHEDULE * * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. * */ -#define NVC06F_CTRL_CMD_GPFIFO_SCHEDULE (0xc06f0103) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x3" */ +#define NVC06F_CTRL_CMD_GPFIFO_SCHEDULE (0xc06f0103) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC06F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */ + +#define NVC06F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x3U) + typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVC06F_CTRL_GPFIFO_SCHEDULE_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVC06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x3U) - -typedef struct NVC06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS { - NVC06F_CTRL_GPFIFO_SCHEDULE_PARAMS params; -} NVC06F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS; - - - /* * NVC06F_CTRL_CMD_BIND * * Please see description of NVA06F_CTRL_CMD_BIND for more information. */ -#define NVC06F_CTRL_CMD_BIND (0xc06f0104) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x4" */ +#define NVC06F_CTRL_CMD_BIND (0xc06f0104) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC06F_CTRL_BIND_PARAMS_MESSAGE_ID" */ + +#define NVC06F_CTRL_BIND_PARAMS_MESSAGE_ID (0x4U) typedef NVA06F_CTRL_BIND_PARAMS NVC06F_CTRL_BIND_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVC06F_CTRL_CMD_BIND_FINN_PARAMS_MESSAGE_ID (0x4U) - -typedef struct NVC06F_CTRL_CMD_BIND_FINN_PARAMS { - NVC06F_CTRL_BIND_PARAMS params; -} NVC06F_CTRL_CMD_BIND_FINN_PARAMS; - - - /* * NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION * * Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information. */ -#define NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xc06f0205) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x5" */ +#define NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xc06f0205) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | NVC06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NVC06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x5U) typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS_MESSAGE_ID (0x5U) - -typedef struct NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS { - NVC06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS params; -} NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS; - - - /* valid action values */ #define NVC06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE #define NVC06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE @@ -182,19 +139,10 @@ typedef struct NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION_FINN_PARAMS { * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. * */ -#define NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xc06f0107) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */ +#define NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xc06f0107) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC06F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */ + +#define NVC06F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x7U) typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVC06F_CTRL_GET_MMU_FAULT_INFO_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U) - -typedef struct NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS { - NV_DECLARE_ALIGNED(NVC06F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8); -} NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS; - - - /* _ctrlc06f.h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc369.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc369.h index 135de3380..731db4ad8 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc369.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc369.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -106,4 +106,50 @@ typedef struct NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUF_PARAMS { NV_DECLARE_ALIGNED(NvP64 pShadowBuffer, 8); } NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUF_PARAMS; +/* + * NVC369_CTRL_CMD_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUFFER + * + * This call creates and registers a client buffer for the replayable faults + * + * pShadowBuffer [OUT] + * This parameter represents the pointer to the shadow buffer + * + * bufferSize [OUT] + * Size in bytes of the shadow buffer for non replayable faults + * + * Possible status values returned are: + * NV_OK + */ + +#define NVC369_CTRL_CMD_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF (0xc3690103) /* finn: Evaluated from "(FINN_MMU_FAULT_BUFFER_MMU_FAULT_BUFFER_INTERFACE_ID << 8) | NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF_PARAMS_MESSAGE_ID" */ + +#define NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pShadowBuffer, 8); + NvU32 bufferSize; +} NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF_PARAMS; + +/* + * NVC369_CTRL_CMD_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUFFER + * + * This call unregisters and destroys a client buffer for the replayable + * faults + * + * pShadowBuffer [IN] + * This parameter represents the pointer to the shadow buffer + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVC369_CTRL_CMD_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF (0xc3690104) /* finn: Evaluated from "(FINN_MMU_FAULT_BUFFER_MMU_FAULT_BUFFER_INTERFACE_ID << 8) | NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF_PARAMS_MESSAGE_ID" */ + +#define NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pShadowBuffer, 8); +} NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF_PARAMS; + /* _ctrlc369_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc36f.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc36f.h index ddfce2014..c3c4209ce 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc36f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc36f.h @@ -67,83 +67,47 @@ * Please see description of NV906F_CTRL_GET_CLASS_ENGINEID for more information. * */ -#define NVC36F_CTRL_GET_CLASS_ENGINEID (0xc36f0101) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */ +#define NVC36F_CTRL_GET_CLASS_ENGINEID (0xc36f0101) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID" */ + +#define NVC36F_CTRL_GET_CLASS_ENGINEID_PARAMS_MESSAGE_ID (0x1U) typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS NVC36F_CTRL_GET_CLASS_ENGINEID_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVC36F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS_MESSAGE_ID (0x1U) - -typedef struct NVC36F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS { - NVC36F_CTRL_GET_CLASS_ENGINEID_PARAMS params; -} NVC36F_CTRL_GET_CLASS_ENGINEID_FINN_PARAMS; - - - /* * NVC36F_CTRL_RESET_CHANNEL * * Please see description of NV906F_CTRL_CMD_RESET_CHANNEL for more information. * */ -#define NVC36F_CTRL_CMD_RESET_CHANNEL (0xc36f0102) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x2" */ +#define NVC36F_CTRL_CMD_RESET_CHANNEL (0xc36f0102) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NVC36F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U) typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS NVC36F_CTRL_CMD_RESET_CHANNEL_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVC36F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS_MESSAGE_ID (0x2U) - -typedef struct NVC36F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS { - NVC36F_CTRL_CMD_RESET_CHANNEL_PARAMS params; -} NVC36F_CTRL_CMD_RESET_CHANNEL_FINN_PARAMS; - - - /* * NVC36F_CTRL_CMD_GPFIFO_SCHEDULE * * Please see description of NVA06F_CTRL_CMD_GPFIFO_SCHEDULE for more information. * */ -#define NVC36F_CTRL_CMD_GPFIFO_SCHEDULE (0xc36f0103) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x3" */ +#define NVC36F_CTRL_CMD_GPFIFO_SCHEDULE (0xc36f0103) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */ + +#define NVC36F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID (0x3U) typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS NVC36F_CTRL_GPFIFO_SCHEDULE_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVC36F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS_MESSAGE_ID (0x3U) - -typedef struct NVC36F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS { - NVC36F_CTRL_GPFIFO_SCHEDULE_PARAMS params; -} NVC36F_CTRL_CMD_GPFIFO_SCHEDULE_FINN_PARAMS; - - - /* * NVC36F_CTRL_CMD_BIND * * Please see description of NVA06F_CTRL_CMD_BIND for more information. */ -#define NVC36F_CTRL_CMD_BIND (0xc36f0104) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x4" */ +#define NVC36F_CTRL_CMD_BIND (0xc36f0104) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_BIND_PARAMS_MESSAGE_ID" */ + +#define NVC36F_CTRL_BIND_PARAMS_MESSAGE_ID (0x4U) typedef NVA06F_CTRL_BIND_PARAMS NVC36F_CTRL_BIND_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVC36F_CTRL_CMD_BIND_FINN_PARAMS_MESSAGE_ID (0x4U) - -typedef struct NVC36F_CTRL_CMD_BIND_FINN_PARAMS { - NVC36F_CTRL_BIND_PARAMS params; -} NVC36F_CTRL_CMD_BIND_FINN_PARAMS; - - - /* * NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION * @@ -175,21 +139,12 @@ typedef NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS NVC36F_CTRL_EVENT_SET_NOTIFICA * Please see description of NV906F_CTRL_CMD_GET_MMU_FAULT_INFO for more information. * */ -#define NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO (0xc36f0107) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */ +#define NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO (0xc36f0107) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVC36F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */ + +#define NVC36F_CTRL_GET_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x7U) typedef NV906F_CTRL_GET_MMU_FAULT_INFO_PARAMS NVC36F_CTRL_GET_MMU_FAULT_INFO_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS_MESSAGE_ID (0x7U) - -typedef struct NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS { - NV_DECLARE_ALIGNED(NVC36F_CTRL_GET_MMU_FAULT_INFO_PARAMS params, 8); -} NVC36F_CTRL_CMD_GET_MMU_FAULT_INFO_FINN_PARAMS; - - - /* * NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN * diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370chnc.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370chnc.h index a231232ef..16a263fd4 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370chnc.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370chnc.h @@ -185,7 +185,7 @@ typedef struct NVC370_CTRL_IDLE_CHANNEL_PARAMS { #define NVC370_CTRL_CMD_SET_ACCL (0xc3700102) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NVC370_CTRL_SET_ACCL_PARAMS_MESSAGE_ID" */ -#define NVC370_CTRL_CMD_GET_ACCL (0xc3700103) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID << 8) | 0x3" */ +#define NVC370_CTRL_CMD_GET_ACCL (0xc3700103) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_CHNCTL_INTERFACE_ID << 8) | NVC370_CTRL_GET_ACCL_PARAMS_MESSAGE_ID" */ #define NVC370_CTRL_ACCL_MAX_INSTANCE_CORE NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_CORE #define NVC370_CTRL_ACCL_MAX_INSTANCE_WINDOW NVC370_CTRL_CMD_MAX_CHANNEL_INSTANCE_WINDOW @@ -204,28 +204,21 @@ typedef struct NVC370_CTRL_IDLE_CHANNEL_PARAMS { #define NVC370_CTRL_ACCL_SKIP_SYNCPOINT NVC370_CTRL_IDLE_CHANNEL_ACCL_SKIP_SYNCPOINT #define NVC370_CTRL_ACCL_IGNORE_TIMESTAMP NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_TIMESTAMP #define NVC370_CTRL_ACCL_IGNORE_MGI NVC370_CTRL_IDLE_CHANNEL_ACCL_IGNORE_MGI -#define NVC370_CTRL_SET_ACCL_PARAMS_MESSAGE_ID (0x2U) - -typedef struct NVC370_CTRL_SET_ACCL_PARAMS { +typedef struct NVC370_CTRL_ACCL_PARAMS { NVC370_CTRL_CMD_BASE_PARAMS base; NvU32 channelClass; NvU32 channelInstance; NvU32 accelerators; NvU32 accelMask; -} NVC370_CTRL_SET_ACCL_PARAMS; -typedef NVC370_CTRL_SET_ACCL_PARAMS NVC370_CTRL_GET_ACCL_PARAMS; +} NVC370_CTRL_ACCL_PARAMS; -// FINN PORT: The below type was generated by the FINN port to -// ensure that all API's have a unique structure associated -// with them! -#define NVC370_CTRL_CMD_GET_ACCL_FINN_PARAMS_MESSAGE_ID (0x3U) - -typedef struct NVC370_CTRL_CMD_GET_ACCL_FINN_PARAMS { - NVC370_CTRL_GET_ACCL_PARAMS params; -} NVC370_CTRL_CMD_GET_ACCL_FINN_PARAMS; +#define NVC370_CTRL_SET_ACCL_PARAMS_MESSAGE_ID (0x2U) +typedef NVC370_CTRL_ACCL_PARAMS NVC370_CTRL_SET_ACCL_PARAMS; +#define NVC370_CTRL_GET_ACCL_PARAMS_MESSAGE_ID (0x3U) +typedef NVC370_CTRL_ACCL_PARAMS NVC370_CTRL_GET_ACCL_PARAMS; /* * NVC370_CTRL_CMD_GET_CHANNEL_INFO diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc637.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc637.h index 155d639ce..07adb74f2 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc637.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc637.h @@ -302,6 +302,7 @@ typedef struct NVC637_CTRL_EXEC_PARTITIONS_EXPORTED_INFO { NvU8 uuid[NVC637_UUID_LEN]; NvU32 sharedEngFlags; NvU32 gpcMask; + NvU32 gfxGpcCount; NvU32 veidOffset; NvU32 veidCount; NvU32 smCount; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc763.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc763.h new file mode 100644 index 000000000..68687b300 --- /dev/null +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc763.h @@ -0,0 +1,242 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc763.finn +// + +#include "ctrl/ctrlxxxx.h" +/* Vidmem Access bit buffer control commands and parameters */ + +#define NVC763_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xC763, NVC763_CTRL_##cat, idx) + +/* MMU_VIDMEM_ACCESS_BIT_BUFFER command categories (6bits) */ +#define NVC763_CTRL_RESERVED (0x00) +#define NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER (0x01) + +/* + * SW def for number of range checkers. Current value taken from + * NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO__SIZE_1 + * on GA102. Compile time assert to check that the below + * definition is consistent with HW manuals is included in + * each gmmu HAL where this is relevant. + */ +#define NV_VIDMEM_ACCESS_BIT_BUFFER_NUM_CHECKERS 8 + +/* + * NVC763_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NVC763_CTRL_CMD_NULL (0xc7630000) /* finn: Evaluated from "(FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_RESERVED_INTERFACE_ID << 8) | 0x0" */ + +#define NVC763_CTRL_CMD_VIDMEM_ACCESS_BIT_ENABLE_LOGGING (0xc7630101) /* finn: Evaluated from "(FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER_INTERFACE_ID << 8) | NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_ENABLE_LOGGING_PARAMS_MESSAGE_ID" */ + +// Supported granularities for the vidmem access bit buffer logging +typedef enum NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY { + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_64KB = 0, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_128KB = 1, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_256KB = 2, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_512KB = 3, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_1MB = 4, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_2MB = 5, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_4MB = 6, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_8MB = 7, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_16MB = 8, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_32MB = 9, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_64MB = 10, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_128MB = 11, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_256MB = 12, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_512MB = 13, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_1GB = 14, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY_2GB = 15, +} NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY; + +/** + * enum of disable mode to be used when the MMU enters protected mode + */ +typedef enum NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DISABLE_MODE { + /*! + * Disable mode will set all the access/dirty bits as '0' + */ + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DISABLE_MODE_CLEAR = 0, + /*! + * Disable mode will set all the access/dirty bits as '1' + */ + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DISABLE_MODE_SET = 1, +} NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DISABLE_MODE; + + +// +// If clients want to enable logging specifically for some MMU, clients need to +// do it in a loop +// +typedef enum NV_VIDMEM_ACCESS_BIT_BUFFER_MMU_TYPE { + /*! + * Read/Write Attrs only for HUBMMU registers + */ + NV_VIDMEM_ACCESS_BIT_BUFFER_HUBMMU = 0, + /*! + * Read/Write Attrs only for GPCMMU registers + */ + NV_VIDMEM_ACCESS_BIT_BUFFER_GPCMMU = 1, + /*! + * Read/Write Attrs only for HSHUBMMU registers + */ + NV_VIDMEM_ACCESS_BIT_BUFFER_HSHUBMMU = 2, + /*! + * Default will enable for all MMU possible + */ + NV_VIDMEM_ACCESS_BIT_BUFFER_DEFAULT = 3, +} NV_VIDMEM_ACCESS_BIT_BUFFER_MMU_TYPE; + +typedef enum NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_TRACK_MODE { + /*! + Mode to track access bits + */ + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_TRACK_MODE_ACCESS = 0, + /*! + Mode to track dirty bits + */ + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_TRACK_MODE_DIRTY = 1, +} NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_TRACK_MODE; + +/* + * NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_ENABLE_LOGGING_PARAMS + * + * This structure is used to enable logging of the VAB and specifies + * the requested configuration for the 8 independent range checkers. + * The tracking mode and disable mode are the same for all range checkers. + */ +#define NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_ENABLE_LOGGING_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_ENABLE_LOGGING_PARAMS { + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_GRANULARITY granularity[NV_VIDMEM_ACCESS_BIT_BUFFER_NUM_CHECKERS]; + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_TRACK_MODE trackMode; + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DISABLE_MODE disableMode; + NV_DECLARE_ALIGNED(NvU64 startAddress[NV_VIDMEM_ACCESS_BIT_BUFFER_NUM_CHECKERS], 8); + NvU8 rangeCount; + NV_VIDMEM_ACCESS_BIT_BUFFER_MMU_TYPE mmuType; +} NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_ENABLE_LOGGING_PARAMS; + + +#define NVC763_CTRL_CMD_VIDMEM_ACCESS_BIT_DISABLE_LOGGING (0xc7630102) /* finn: Evaluated from "(FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER_INTERFACE_ID << 8) | 0x2" */ + +/* + * NVC763_CTRL_CMD_VIDMEM_ACCESS_BIT_BUFFER_DUMP + * + * This call initiates the dump request with the properties set using enable + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVC763_CTRL_CMD_VIDMEM_ACCESS_BIT_DUMP (0xc7630103) /* finn: Evaluated from "(FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER_INTERFACE_ID << 8) | NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DUMP_PARAMS_MESSAGE_ID" */ + +/* + * NV_VAB_OP enumerates the types of dumps supported + * + * The options are: + * + * AGGREGATE + * Collects access buffer bits over multiple dumps using a bitwise OR. + * + * DIFF + * Sets a bit to 1 if it changed from 0 to 1 with this dump. If a bit was + * cleared since the last dump it will be 0. If a bit does not change + * with this dump it will be 0. + * + * CURRENT + * Copies the current access bit buffer state as is from HW. This operation + * clears any underlying aggregation from previous dumps with the other + * two operations. + * + * INVALID + * Should be unused and otherwise indicates error + */ +typedef enum NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP { + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP_AGGREGATE = 0, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP_DIFF = 1, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP_CURRENT = 2, + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP_INVALID = 3, +} NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP; + +/* + * NVC763_CTRL_VIDMEM_ACCESS_BIT_DUMP_PARAMS + * + * This structure records the dumped bits for the client + * masked by the client's access bit mask determined + * during VidmemAccessBitBuffer construction. + * + * bMetadata [IN] + * Whether or not clients want disable data. + * + * op_enum [IN] + * A member of NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP controlling the type of dump. + * + * accessBits [OUT] + * The client's access bits masked according to the client's access bit mask. + * + * gpcDisable [OUT] + * The GPC disable data from the VAB dump. See GPC_DISABLE in the Ampere-801 FD. + * + * hubDisable [OUT] + * The HUB disable data from the VAB dump. See HUB_DISABLE in the Ampere-801 FD. + * + * hsceDisable [OUT] + * The HSCE disable data from the VAB dump. See HSCE_DIS in the Ampere-801 FD. + * + * linkDisable [OUT] + * The LINK disable data from the VAB dump. See LINK_DIS in the Ampere-801 FD. + */ +#define NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DUMP_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DUMP_PARAMS { + NvBool bMetadata; + NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_OP op_enum; + NV_DECLARE_ALIGNED(NvU64 accessBits[64], 8); + NV_DECLARE_ALIGNED(NvU64 gpcDisable, 8); + NvU32 hubDisable; + NvU16 hsceDisable; + NvU8 linkDisable; +} NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DUMP_PARAMS; + + +#define NVC763_CTRL_CMD_VIDMEM_ACCESS_BIT_PUT_OFFSET (0xc7630104) /* finn: Evaluated from "(FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER_INTERFACE_ID << 8) | NVC763_CTRL_VIDMEM_ACCESS_BIT_PUT_OFFSET_PARAMS_MESSAGE_ID" */ + +#define NVC763_CTRL_VIDMEM_ACCESS_BIT_PUT_OFFSET_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVC763_CTRL_VIDMEM_ACCESS_BIT_PUT_OFFSET_PARAMS { + NvU32 vidmemAccessBitPutOffset; +} NVC763_CTRL_VIDMEM_ACCESS_BIT_PUT_OFFSET_PARAMS; +/* _ctrlc763_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlxxxx.h b/src/common/sdk/nvidia/inc/ctrl/ctrlxxxx.h index efe0c589d..3949b87a1 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlxxxx.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlxxxx.h @@ -23,6 +23,8 @@ #pragma once +#include + // // This file was generated with FINN, an NVIDIA coding tool. // Source file: ctrl/ctrlxxxx.finn @@ -65,3 +67,8 @@ #define NVxxxx_CTRL_LEGACY_PRIVILEGED (0xC0) #define NVxxxx_CTRL_LEGACY_NON_PRIVILEGED (0x80) + +typedef struct NVXXXX_CTRL_XXX_INFO { + NvU32 index; + NvU32 data; +} NVXXXX_CTRL_XXX_INFO; diff --git a/src/common/sdk/nvidia/inc/finn_rm_api.h b/src/common/sdk/nvidia/inc/g_finn_rm_api.h similarity index 94% rename from src/common/sdk/nvidia/inc/finn_rm_api.h rename to src/common/sdk/nvidia/inc/g_finn_rm_api.h index eac891a2f..bf74e359f 100644 --- a/src/common/sdk/nvidia/inc/finn_rm_api.h +++ b/src/common/sdk/nvidia/inc/g_finn_rm_api.h @@ -40,7 +40,7 @@ * FINN compiler version */ #define FINN_VERSION_MAJOR 1 -#define FINN_VERSION_MINOR 15 +#define FINN_VERSION_MINOR 17 #define FINN_VERSION_PATCH 0 typedef struct FINN_RM_API @@ -52,6 +52,17 @@ typedef struct FINN_RM_API } FINN_RM_API; + + +/*! + * @brief Private functions not to be called directly + */ +/**@{*/ +NV_STATUS finnSerializeInternal_FINN_RM_API(NvU64 interface, NvU64 message, const char *api, char **dst, NvLength dst_size, NvBool seri_up); +NV_STATUS finnDeserializeInternal_FINN_RM_API(const char **src, NvLength src_size, char *api, NvLength api_size, NvBool deser_up); +/**@}*/ + + /*! * @brief Serializes an RM API control params struct and copies it into the * serialization buffer as a FINN message. @@ -67,7 +78,7 @@ typedef struct FINN_RM_API * * @param[in] interface FINN interface ID of the param struct. * @param[in] message FINN message ID of the param struct. - * @param[in] src Pointer to the source param struct from which to + * @param[in] api Pointer to the source param struct from which to * copy the data. * @param[in, out] dst Double pointer to the destination buffer into * which to copy the data. *dst will be set to @@ -85,8 +96,14 @@ typedef struct FINN_RM_API * @retval NV_ERR_BUFFER_TOO_SMALL Destination buffer size too small. */ /**@{*/ -NV_STATUS FinnRmApiSerializeUp(NvU64 interface, NvU64 message, const void *src, NvU8 **dst, NvLength dst_size); -NV_STATUS FinnRmApiSerializeDown(NvU64 interface, NvU64 message, const void *src, NvU8 **dst, NvLength dst_size); +static NV_INLINE NV_STATUS FinnRmApiSerializeUp(NvU64 interface, NvU64 message, const void *api, NvU8 **dst, NvLength dst_size) +{ + return finnSerializeInternal_FINN_RM_API(interface, message, (const char *) api, (char **) dst, dst_size, NV_TRUE); +} +static NV_INLINE NV_STATUS FinnRmApiSerializeDown(NvU64 interface, NvU64 message, const void *api, NvU8 **dst, NvLength dst_size) +{ + return finnSerializeInternal_FINN_RM_API(interface, message, (const char *) api, (char **) dst, dst_size, NV_FALSE); +} /**@}*/ @@ -113,9 +130,9 @@ NV_STATUS FinnRmApiSerializeDown(NvU64 interface, NvU64 message, const void *src * deserialization on failure. * @param[in] src_size Maximum size of the source buffer measured in * `NvU8` units. - * @param[in, out] dst Pointer to the destination param struct into which + * @param[in, out] api Pointer to the destination param struct into which * to copy the data. - * @param[in] dst_size Size of the destination param struct measured in + * @param[in] api_size Size of the destination param struct measured in * `char` units per `sizeof` operator. * * @retval NV_OK Deserialization successful. @@ -129,10 +146,17 @@ NV_STATUS FinnRmApiSerializeDown(NvU64 interface, NvU64 message, const void *src * @retval NV_ERR_LIB_RM_VERSION_MISMATCH Version mismatch. */ /**@{*/ -NV_STATUS FinnRmApiDeserializeDown(NvU8 **src, NvLength src_size, void *dst, NvLength dst_size); -NV_STATUS FinnRmApiDeserializeUp(NvU8 **src, NvLength src_size, void *dst, NvLength dst_size); +static NV_INLINE NV_STATUS FinnRmApiDeserializeDown(NvU8 **src, NvLength src_size, void *api, NvLength api_size) +{ + return finnDeserializeInternal_FINN_RM_API((const char **) src, src_size / sizeof(NvU8), (char *) api, api_size, NV_FALSE); +} +static NV_INLINE NV_STATUS FinnRmApiDeserializeUp(NvU8 **src, NvLength src_size, void *api, NvLength api_size) +{ + return finnDeserializeInternal_FINN_RM_API((const char **) src, src_size / sizeof(NvU8), (char *) api, api_size, NV_TRUE); +} /**@}*/ + /*! * @brief Calculates the serialized size of an RM API param struct. * @@ -145,6 +169,7 @@ NV_STATUS FinnRmApiDeserializeUp(NvU8 **src, NvLength src_size, void *dst, NvLen */ NvU64 FinnRmApiGetSerializedSize(NvU64 interface, NvU64 message, const NvP64 src); + /*! * @brief Fetches the unserialized size of an API param struct. * @@ -158,6 +183,7 @@ NvU64 FinnRmApiGetSerializedSize(NvU64 interface, NvU64 message, const NvP64 src */ NvU64 FinnRmApiGetUnserializedSize(NvU64 interface, NvU64 message); + #define NV_RM_ALLOC_INTERFACE_INTERFACE_ID (0xA000U) typedef FINN_RM_API NV_RM_ALLOC_INTERFACE; #define FINN_NV01_ROOT_RESERVED_INTERFACE_ID (0x0U) @@ -217,6 +243,8 @@ typedef FINN_RM_API FINN_NV01_ROOT_USER_RESERVED; typedef FINN_RM_API FINN_NV01_ROOT_USER_MEMORY; #define FINN_NV04_DISPLAY_COMMON_RESERVED_INTERFACE_ID (0x7300U) typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_RESERVED; +#define FINN_NV04_DISPLAY_COMMON_COMMON_INTERFACE_ID (0x7305U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_COMMON; #define FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID (0x7311U) typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_DFP; #define FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID (0x7313U) @@ -224,7 +252,8 @@ typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_DP; #define FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID (0x7304U) typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_INTERNAL; - +#define FINN_NV04_DISPLAY_COMMON_PSR_INTERFACE_ID (0x7316U) +typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_PSR; #define FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID (0x7302U) typedef FINN_RM_API FINN_NV04_DISPLAY_COMMON_SPECIFIC; #define FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID (0x7317U) @@ -363,6 +392,8 @@ typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_LPWR; #define FINN_NV20_SUBDEVICE_0_MC_INTERFACE_ID (0x208017U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_MC; +#define FINN_NV20_SUBDEVICE_0_NNE_INTERFACE_ID (0x208037U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_NNE; #define FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID (0x208024U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_NVD; diff --git a/src/common/sdk/nvidia/inc/nv-hypervisor.h b/src/common/sdk/nvidia/inc/nv-hypervisor.h index 6ee37f76c..422f258b2 100644 --- a/src/common/sdk/nvidia/inc/nv-hypervisor.h +++ b/src/common/sdk/nvidia/inc/nv-hypervisor.h @@ -90,30 +90,6 @@ typedef enum VGPU_DEVICE_STATE_E NV_VGPU_DEV_IN_USE = 2 } VGPU_DEVICE_STATE; -typedef enum _VMBUS_CMD_TYPE -{ - VMBUS_CMD_TYPE_INVALID = 0, - VMBUS_CMD_TYPE_SETUP = 1, - VMBUS_CMD_TYPE_SENDPACKET = 2, - VMBUS_CMD_TYPE_CLEANUP = 3, -} VMBUS_CMD_TYPE; - -typedef struct -{ - NvU32 request_id; - NvU32 page_count; - NvU64 *pPfns; - void *buffer; - NvU32 bufferlen; -} vmbus_send_packet_cmd_params; - - -typedef struct -{ - NvU32 override_sint; - NvU8 *nv_guid; -} vmbus_setup_cmd_params; - /* * Function prototypes */ diff --git a/src/common/sdk/nvidia/inc/nverror.h b/src/common/sdk/nvidia/inc/nverror.h index a7fef7d5e..49e329668 100644 --- a/src/common/sdk/nvidia/inc/nverror.h +++ b/src/common/sdk/nvidia/inc/nverror.h @@ -119,7 +119,7 @@ #define INFOROM_FS_ERROR (125) #define ALI_TRAINING_FAIL (136) #define ROBUST_CHANNEL_LAST_ERROR (ALI_TRAINING_FAIL) - +#define NVLINK_FLA_PRIV_ERR (137) // Indexed CE reference diff --git a/src/common/sdk/nvidia/inc/nvos.h b/src/common/sdk/nvidia/inc/nvos.h index 27fe427de..8bb00416c 100644 --- a/src/common/sdk/nvidia/inc/nvos.h +++ b/src/common/sdk/nvidia/inc/nvos.h @@ -607,7 +607,6 @@ typedef void (*BindResultFunc)(void * pVoid, NvU32 gpuMask, NvU32 bState, NvU32 #define NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR 6 #define NVOS32_DESCRIPTOR_TYPE_KERNEL_VIRTUAL_ADDRESS 7 // NVOS32 function -#define NVOS32_FUNCTION_ALLOC_DEPTH_WIDTH_HEIGHT 1 #define NVOS32_FUNCTION_ALLOC_SIZE 2 #define NVOS32_FUNCTION_FREE 3 // #define NVOS32_FUNCTION_HEAP_PURGE 4 @@ -684,32 +683,6 @@ typedef struct union { - // NVOS32_FUNCTION_ALLOC_DEPTH_WIDTH_HEIGHT - struct - { - NvU32 owner; // [IN] - memory owner ID - NvHandle hMemory; // [IN/OUT] - unique memory handle - IN only if MEMORY_HANDLE_PROVIDED is set (otherwise generated) - NvU32 type; // [IN] - surface type, see below TYPE* defines - NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines - NvU32 depth; // [IN] - depth of surface in bits - NvU32 width; // [IN] - width of surface in pixels - NvU32 height; // [IN] - height of surface in pixels - NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated - NvU32 format; // [IN/OUT] - format requested, and format allocated - NvU32 comprCovg; // [IN/OUT] - compr covg requested, and allocated - NvU32 zcullCovg; // [OUT] - zcull covg allocated - NvU32 partitionStride; // [IN/OUT] - 0 means "RM" chooses - NvU64 size NV_ALIGN_BYTES(8); // [IN/OUT] - size of allocation - also returns the actual size allocated - NvU64 alignment NV_ALIGN_BYTES(8); // [IN] - requested alignment - NVOS32_ALLOC_FLAGS_ALIGNMENT* must be on - NvU64 offset NV_ALIGN_BYTES(8); // [IN/OUT] - desired offset if NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE is on AND returned offset - NvU64 limit NV_ALIGN_BYTES(8); // [OUT] - returned surface limit - NvP64 address NV_ALIGN_BYTES(8);// [OUT] - returned address - NvU64 rangeBegin NV_ALIGN_BYTES(8); // [IN] - allocated memory will be limited to the range - NvU64 rangeEnd NV_ALIGN_BYTES(8); // [IN] - from rangeBegin to rangeEnd, inclusive. - NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated - NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET) - } AllocDepthWidthHeight; - // NVOS32_FUNCTION_ALLOC_SIZE struct { @@ -1800,15 +1773,6 @@ typedef struct #define NVOS33_FLAGS_RESERVE_ON_UNMAP_DISABLE (0x00000000) #define NVOS33_FLAGS_RESERVE_ON_UNMAP_ENABLE (0x00000001) -// Systems with a coherent NVLINK2 connection between the CPU and GPU -// have the option of directly mapping video memory over that connection. -// During mapping you may specify a preference. -// -#define NVOS33_FLAGS_BUS 21:20 -#define NVOS33_FLAGS_BUS_ANY 0 -#define NVOS33_FLAGS_BUS_NVLINK_COHERENT 1 -#define NVOS33_FLAGS_BUS_PCIE 2 - // Internal use only #define NVOS33_FLAGS_OS_DESCRIPTOR 22:22 #define NVOS33_FLAGS_OS_DESCRIPTOR_DISABLE (0x00000000) @@ -2885,6 +2849,43 @@ typedef struct NvV32 status; // [OUT] status of call } NV_GSP_TEST_SEND_EVENT_NOTIFICATION_PARAMETERS; +/* + * NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_COH + * NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_DEFAULT + * Location is Coherent System memory (also the default option) + * NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_NCOH + * Location is Non-Coherent System memory + * NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_VID + * Location is FB + * + * Currently only used by MODS for the V1 VAB interface. To be deleted. + */ +typedef enum +{ + NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_DEFAULT = 0, + NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_COH, + NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_NCOH, + NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_VID +} NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE; + +/** + * @brief Multiclient vidmem access bit allocation params + */ +typedef struct +{ + /* [OUT] Dirty/Access tracking */ + NvBool bDirtyTracking; + /* [OUT] Current tracking granularity */ + NvU32 granularity; + /* [OUT] 512B Access bit mask with 1s set on + bits that are reserved for this client */ + NV_DECLARE_ALIGNED(NvU64 accessBitMask[64], 8); + /* Number of entries of vidmem access buffer. Used by VAB v1 - to be deleted */ + NvU32 noOfEntries; + /* Address space of the vidmem access bit buffer. Used by VAB v1 - to be deleted */ + NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE addrSpace; +} NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS; + /** * @brief HopperUsermodeAParams * This set of optionalparameters is passed in on allocation of diff --git a/src/nvidia/arch/nvalloc/common/inc/nvdevid.h b/src/common/shared/inc/nvdevid.h similarity index 97% rename from src/nvidia/arch/nvalloc/common/inc/nvdevid.h rename to src/common/shared/inc/nvdevid.h index a1cf28646..cce13d03b 100644 --- a/src/nvidia/arch/nvalloc/common/inc/nvdevid.h +++ b/src/common/shared/inc/nvdevid.h @@ -145,7 +145,6 @@ #define PCI_VENDOR_ID_CADENCE 0x17CD #define PCI_VENDOR_ID_ARM 0x13B5 #define PCI_VENDOR_ID_HYGON 0x1D94 -#define PCI_VENDOR_ID_ALIBABA 0x1DED #define NV_PCI_DEVID_DEVICE 31:16 /* RW--F */ #define NV_PCI_SUBID_DEVICE 31:16 /* RW--F */ @@ -400,9 +399,6 @@ #define PURLEY_P720_SSDEVID 0x1037 #define PURLEY_P520_SSDEVID 0x1036 -// Lenovo P520c -#define LENOVO_P520C_SSDEVID 0x103C - // Dell Purley(Matira) #define PURLEY_MATIRA3X_DEVID 0xA2D2 #define PURLEY_MATIRA3X_SSDEVID 0x08B1 @@ -410,9 +406,6 @@ #define PURLEY_MATIRA5_SSDEVID 0x0739 #define PURLEY_MATIRA7_SSDEVID 0x073A -//FTS Grantley -#define GRANTLEY_R940_SSDEVID 0x1201 - //FTS Purley #define PURLEY_R970_SSDEVID 0x1230 #define PURLEY_M770_SSDEVID 0x1231 @@ -430,14 +423,6 @@ #define SUPERMICRO_QUADRO_VCA_DEVID 0x8D44 #define SUPERMICRO_QUADRO_VCA_SSDEVID 0x7270 -// Supermicro SYS-4027GR-TRT -#define SUPERMICRO_SYS_4027GR_TRT_DEVID 0x1D41 -#define SUPERMICRO_SYS_4027GR_TRT_SSDEVID 0x0732 - -// Supermicro SYS-4029GP-TRT2 -#define SUPERMICRO_SYS_4029GP_TRT2_DEVID 0xA1C2 -#define SUPERMICRO_SYS_4029GP_TRT2_SSDEVID 0x7270 - // Asus Quadro BOXX definitions #define ASUS_QUADRO_BOXX_DEVID 0x8D44 #define ASUS_QUADRO_BOXX_SSDEVID 0x85F6 @@ -460,14 +445,6 @@ #define FOXCONN_EINSTEIN_64_DEVID 0xA1C1 #define FOXCONN_EINSTEIN_64_SSDEVID 0x7270 -// Tyan Workstation -#define TYAN_B7100_DEVID 0xA1C1 -#define TYAN_B7100_SSDEVID 0x7270 - -// ESC 4000 Series Workstation -#define ESC_4000_G4_DEVID 0xA1C1 -#define ESC_4000_G4_SSDEVID 0x871E - // NVIDIA C51 #define NVIDIA_C51_DEVICE_ID_MIN 0x2F0 @@ -643,7 +620,6 @@ enum { , CS_HYGON_C86 , CS_PHYTIUM_S2500 , CS_MELLANOX_BLUEFIELD2 -, CS_ALIBABA_YITIAN , CS_INTEL_1B81 , CS_INTEL_18DC , CS_INTEL_7A04 diff --git a/src/common/softfloat/source/f64_to_i64_r_minMag.c b/src/common/softfloat/source/f64_to_i64_r_minMag.c index 3822606db..6cca23f9d 100644 --- a/src/common/softfloat/source/f64_to_i64_r_minMag.c +++ b/src/common/softfloat/source/f64_to_i64_r_minMag.c @@ -90,7 +90,7 @@ int_fast64_t f64_to_i64_r_minMag( float64_t a, bool exact ) *--------------------------------------------------------------------*/ sig |= UINT64_C( 0x0010000000000000 ); absZ = sig>>shiftDist; - if ( exact && (absZ<pPushChannel; NvPushDevicePtr pPushDevice = pPushChannel->pDevice; const NvU32 classNumber = p3dChannel->p3dDevice->classNumber; + const NvU32 numChannels = + pPushDevice->clientSli ? pPushDevice->numSubDevices : 1; int sd; /* @@ -44,15 +46,13 @@ NvBool nv3dAllocChannelObject( nvAssert(p3dChannel->p3dDevice->pPushDevice == pParams->pPushChannel->pDevice); - for (sd = 0; - sd < ARRAY_LEN(pPushChannel->channelHandle) && - pPushChannel->channelHandle[sd] != 0; - sd++) { + for (sd = 0; sd < numChannels; sd++) { if (nvPushIsAModel(pPushDevice)) { nvAssert(sd == 0); } else { const NvPushImports *pImports = pPushDevice->pImports; + nvAssert(pPushChannel->channelHandle[sd] != 0); nvAssert(pParams->handle[sd] != 0); NvU32 ret = pImports->rmApiAlloc(pPushDevice, pPushChannel->channelHandle[sd], diff --git a/src/common/unix/nvidia-3d/src/nvidia-3d-kepler.c b/src/common/unix/nvidia-3d/src/nvidia-3d-kepler.c index 0dec5f43f..5ac99c3fc 100644 --- a/src/common/unix/nvidia-3d/src/nvidia-3d-kepler.c +++ b/src/common/unix/nvidia-3d/src/nvidia-3d-kepler.c @@ -102,10 +102,6 @@ void _nv3dUploadDataInlineKepler( nvPushSetMethodDataU64(p, gpuBaseAddress + offset + bytesSoFar); nvPushSetMethodData(p, bytesThisChunk); // NVA097_PITCH_OUT - nvPushMethod(p, NVA06F_SUBCHANNEL_3D, NVA097_SET_DST_WIDTH, 2); - nvPushSetMethodData(p, bytesThisChunk); - nvPushSetMethodData(p, 1); // NVA097_SET_DST_HEIGHT - nvPushMethodOneIncr(p, NVA06F_SUBCHANNEL_3D, NVA097_LAUNCH_DMA, 1 + dwordsThisChunk); nvPushSetMethodData(p, diff --git a/src/nvidia-modeset/include/dp/nvdp-connector.h b/src/nvidia-modeset/include/dp/nvdp-connector.h index 4e2823f5a..70aba5a76 100644 --- a/src/nvidia-modeset/include/dp/nvdp-connector.h +++ b/src/nvidia-modeset/include/dp/nvdp-connector.h @@ -47,6 +47,7 @@ NVDPLibModesetStatePtr nvDPLibCreateModesetState( const NvU32 displayId, const NVDpyIdList dpyIdList, const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, + const enum NvKmsDpyAttributeColorBpcValue colorBpc, NVHwModeTimingsEvo *pTimings); void nvDPLibFreeModesetState(NVDPLibModesetStatePtr pDpLibModesetState); @@ -59,6 +60,7 @@ NvBool nvDPLibValidateTimings( const NvU32 displayId, const NVDpyIdList dpyIdList, const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, + const enum NvKmsDpyAttributeColorBpcValue colorBpc, const struct NvKmsModeValidationParams *pModeValidationParams, NVHwModeTimingsEvo *pTimings); @@ -67,6 +69,7 @@ NvBool nvDPEndValidation(NVDispEvoPtr pDispEvo); NvBool nvDPValidateModeForDpyEvo( const NVDpyEvoRec *pDpyEvo, const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, + const enum NvKmsDpyAttributeColorBpcValue colorBpc, const struct NvKmsModeValidationParams *pModeValidationParams, NVHwModeTimingsEvo *pTimings); diff --git a/src/nvidia-modeset/include/nvkms-3dvision.h b/src/nvidia-modeset/include/nvkms-3dvision.h index 1dae05621..6387632ed 100644 --- a/src/nvidia-modeset/include/nvkms-3dvision.h +++ b/src/nvidia-modeset/include/nvkms-3dvision.h @@ -26,7 +26,7 @@ #include "nvkms-types.h" -void nv3DVisionAuthenticationEvo(NVDispEvoRec *pDispEvo, const NvU32 head); +void nv3DVisionAuthenticationEvo(NVDispEvoRec *pDispEvo, const NvU32 apiHead); void nvDpyCheck3DVisionCapsEvo(NVDpyEvoPtr pDpyEvo); NvBool @@ -34,6 +34,6 @@ nvPatch3DVisionModeTimingsEvo(NVT_TIMING *pTiming, NVDpyEvoPtr pDpyEvo, NVEvoInfoStringPtr pInfoString); void nvDisable3DVisionAegis(const NVDpyEvoRec *pDpyEvo); void nvSendHwModeTimingsToAegisEvo(const NVDispEvoRec *pDispEvo, - const NvU32 head); + const NvU32 apiHead); #endif /* __NVKMS_3DVISION_H__ */ diff --git a/src/nvidia-modeset/include/nvkms-cursor.h b/src/nvidia-modeset/include/nvkms-cursor.h index f8b235817..a20562ef8 100644 --- a/src/nvidia-modeset/include/nvkms-cursor.h +++ b/src/nvidia-modeset/include/nvkms-cursor.h @@ -36,14 +36,14 @@ NvBool nvSetCursorImage( NVDispEvoPtr pDispEvo, const struct NvKmsPerOpenDev *pOpenDevice, const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, - NvU32 head, + NvU32 apiHead, const struct NvKmsSetCursorImageCommonParams *pParams); void nvEvoMoveCursorInternal(NVDispEvoPtr pDispEvo, NvU32 head, NvS16 x, NvS16 y); -void nvEvoMoveCursor(NVDispEvoPtr pDispEvo, NvU32 head, - const struct NvKmsMoveCursorCommonParams *pParams); +void nvMoveCursor(NVDispEvoPtr pDispEvo, const NvU32 apiHead, + const struct NvKmsMoveCursorCommonParams *pParams); NvBool nvAllocCursorEvo(NVDevEvoPtr pDevEvo); void nvFreeCursorEvo(NVDevEvoPtr pDevEvo); diff --git a/src/nvidia-modeset/include/nvkms-dpy-override.h b/src/nvidia-modeset/include/nvkms-dpy-override.h new file mode 100644 index 000000000..22288395b --- /dev/null +++ b/src/nvidia-modeset/include/nvkms-dpy-override.h @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVKMS_DPY_OVERRIDE_H__ +#define __NVKMS_DPY_OVERRIDE_H__ + +#include "nvkms-types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct _DpyOverride { + NVListRec entry; + + NvU32 gpuId; + char name[NVKMS_DPY_NAME_SIZE]; + + NvBool connected; + NVEdidRec edid; +} NVDpyOverrideRec, *NVDpyOverridePtr; + +NVDpyOverrideRec *nvCreateDpyOverride(NvU32 gpuId, + const char *name, + NvBool connected, + const char *edid, + size_t edidSize); + +void nvDeleteDpyOverride(NvU32 gpuId, const char *name); + +void nvLogDpyOverrides(NvU32 gpuId, NVEvoInfoStringPtr pInfoStr); + +NVDpyOverridePtr nvDpyEvoGetOverride(const NVDpyEvoRec *pDpyEvo); +size_t nvReadDpyOverrideEdid(const NVDpyOverrideRec *pDpyOverride, NvU8 *buff, + size_t len); + +void nvClearDpyOverrides(void); + +#ifdef __cplusplus +}; +#endif + +#endif /* __NVKMS_DPY_OVERRIDE_H__ */ diff --git a/src/nvidia-modeset/include/nvkms-dpy.h b/src/nvidia-modeset/include/nvkms-dpy.h index 3ca7abb7e..715894f34 100644 --- a/src/nvidia-modeset/include/nvkms-dpy.h +++ b/src/nvidia-modeset/include/nvkms-dpy.h @@ -76,11 +76,13 @@ void nvDpyUpdateCurrentAttributes(NVDpyEvoRec *pDpyEvo); NvBool nvDpyIsAdaptiveSync(const NVDpyEvoRec *pDpyEvo); -NvBool nvDpyIsAdaptiveSyncDefaultlisted(const NVParsedEdidEvoRec *pParsedEdid); +NvBool nvDpyIsAdaptiveSyncDefaultlisted(const NVDpyEvoRec *pDpyEvo); enum NvKmsDpyAttributeDigitalSignalValue nvGetDefaultDpyAttributeDigitalSignalValue(const NVConnectorEvoRec *pConnectorEvo); +NVColorFormatInfoRec nvGetColorFormatInfo(const NVDpyEvoRec *pDpyEvo); + #ifdef __cplusplus }; #endif diff --git a/src/nvidia-modeset/include/nvkms-evo.h b/src/nvidia-modeset/include/nvkms-evo.h index 0e290013c..5d976f404 100644 --- a/src/nvidia-modeset/include/nvkms-evo.h +++ b/src/nvidia-modeset/include/nvkms-evo.h @@ -25,7 +25,6 @@ #define __NVKMS_H__ #include "nvkms-types.h" -#include "nvkms-modeset-types.h" #include "nvkms-api.h" #ifdef __cplusplus @@ -113,7 +112,7 @@ void nvEvoHeadSetControlOR(NVDispEvoPtr pDispEvo, void nvChooseDitheringEvo( const NVConnectorEvoRec *pConnectorEvo, - const enum nvKmsPixelDepth pixelDepth, + enum NvKmsDpyAttributeColorBpcValue bpc, const NVDpyAttributeRequestedDitheringConfig *pReqDithering, NVDpyAttributeCurrentDitheringConfig *pCurrDithering); @@ -161,14 +160,17 @@ NvBool nvConstructHwModeTimingsEvo(const NVDpyEvoRec *pDpyEvo, NvBool nvConstructHwModeTimingsImpCheckEvo( const NVConnectorEvoRec *pConnectorEvo, NVHwModeTimingsEvoPtr pTimings, + const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, + const enum NvKmsDpyAttributeColorBpcValue colorBpc, const struct NvKmsModeValidationParams *pParams, NVEvoInfoStringPtr pInfoString, const int head); -NvBool nvDowngradeHwModeTimingsDpPixelDepthEvo( - NVHwModeTimingsEvoPtr pTimings, - const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, - const enum NvKmsDpyAttributeColorRangeValue colorRange); +NvBool nvDowngradeColorSpaceAndBpc( + const NVColorFormatInfoRec *pSupportedColorFormats, + enum NvKmsDpyAttributeCurrentColorSpaceValue *pColorSpace, + enum NvKmsDpyAttributeColorBpcValue *pColorBpc, + enum NvKmsDpyAttributeColorRangeValue *pColorRange); NvBool nvDPValidateModeEvo(NVDpyEvoPtr pDpyEvo, NVHwModeTimingsEvoPtr pTimings, @@ -186,6 +188,7 @@ typedef struct _NVValidateImpOneDispHeadParamsRec const NVConnectorEvoRec *pConnectorEvo; const struct NvKmsUsageBounds *pUsage; NvU32 activeRmId; + enum nvKmsPixelDepth pixelDepth; NVHwModeTimingsEvoPtr pTimings; } NVValidateImpOneDispHeadParamsRec; @@ -212,19 +215,20 @@ NvBool nvValidateImpOneDispDowngrade( NvBool nvFrameLockServerPossibleEvo(const NVDpyEvoRec *pDpyEvo); NvBool nvFrameLockClientPossibleEvo(const NVDpyEvoRec *pDpyEvo); -void nvEvoSetLut(NVDispEvoPtr pDispEvo, NvU32 head, NvBool kickoff, +void nvEvoSetLut(NVDispEvoPtr pDispEvo, NvU32 apiHead, NvBool kickoff, const struct NvKmsSetLutCommonParams *pParams); NvBool nvValidateSetLutCommonParams( const NVDevEvoRec *pDevEvo, const struct NvKmsSetLutCommonParams *pParams); -void nvChooseCurrentColorSpaceAndRangeEvo( - enum nvKmsPixelDepth pixelDepth, +NvBool nvChooseCurrentColorSpaceAndRangeEvo( + const NVDpyEvoRec *pDpyEvo, enum NvYuv420Mode yuv420Mode, enum NvKmsOutputTf tf, const enum NvKmsDpyAttributeRequestedColorSpaceValue requestedColorSpace, const enum NvKmsDpyAttributeColorRangeValue requestedColorRange, enum NvKmsDpyAttributeCurrentColorSpaceValue *pCurrentColorSpace, + enum NvKmsDpyAttributeColorBpcValue *pCurrentColorBpc, enum NvKmsDpyAttributeColorRangeValue *pCurrentColorRange); void nvUpdateCurrentHardwareColorSpaceAndRangeEvo( @@ -253,8 +257,8 @@ NvBool nvUpdateFlipLockEvoOneHead(NVDispEvoPtr pDispEvo, const NvU32 head, NvBool *needsEarlyUpdate, NVEvoUpdateState *updateState); -void nvEvoUpdateCurrentPalette(NVDispEvoPtr pDispEvo, - NvU32 head, NvBool kickOff); +void nvEvoSetLUTContextDma(NVDispEvoPtr pDispEvo, + const NvU32 head, NVEvoUpdateState *pUpdateState); NvBool nvEvoPollForNoMethodPending(NVDevEvoPtr pDevEvo, const NvU32 sd, @@ -293,7 +297,7 @@ void nvDPSerializerPostSetMode(NVDispEvoPtr pDispEvo, NvBool nvFramelockSetControlUnsyncEvo(NVDispEvoPtr pDispEvo, const NvU32 headMask, NvBool server); -NvBool nvIsHDRCapableHead(NVDispEvoPtr pDispEvo, +NvBool nvIsHDRCapableHead(const NVDispEvoRec *pDispEvo, NvU32 apiHead); NvU32 nvGetHDRSrcMaxLum(const NVFlipChannelEvoHwState *pHwState); @@ -306,9 +310,18 @@ NvBool nvNeedsTmoLut(NVDevEvoPtr pDevEvo, NvBool nvIsCscMatrixIdentity(const struct NvKmsCscMatrix *matrix); +enum nvKmsPixelDepth nvEvoColorSpaceBpcToPixelDepth( + const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, + const enum NvKmsDpyAttributeColorBpcValue colorBpc); + void nvSuspendDevEvo(NVDevEvoRec *pDevEvo); NvBool nvResumeDevEvo(NVDevEvoRec *pDevEvo); +NvBool nvGetDefaultColorSpace( + const NVColorFormatInfoRec *pColorFormatsInfo, + enum NvKmsDpyAttributeCurrentColorSpaceValue *pColorSpace, + enum NvKmsDpyAttributeColorBpcValue *pColorBpc); + #ifdef __cplusplus }; #endif diff --git a/src/nvidia-modeset/include/nvkms-evo1.h b/src/nvidia-modeset/include/nvkms-evo1.h index 8b74629cb..eb9e225eb 100644 --- a/src/nvidia-modeset/include/nvkms-evo1.h +++ b/src/nvidia-modeset/include/nvkms-evo1.h @@ -38,7 +38,8 @@ void nvEvo1PrePostIMP(NVDispEvoPtr pDispEvo, NvBool isPre); void nvEvo1SetDscParams(const NVDispEvoRec *pDispEvo, const NvU32 head, - const NVHwModeTimingsEvo *pTimings); + const NVHwModeTimingsEvo *pTimings, + const enum nvKmsPixelDepth pixelDepth); NVEvoChannel* nvEvo1AllocateCoreChannel(NVDevEvoRec *pDevEvo); void nvEvo1FreeCoreChannel(NVDevEvoRec *pDevEvo, NVEvoChannel *pChannel); diff --git a/src/nvidia-modeset/include/nvkms-flip-workarea.h b/src/nvidia-modeset/include/nvkms-flip-workarea.h index 7d1b2d0c8..0319b2852 100644 --- a/src/nvidia-modeset/include/nvkms-flip-workarea.h +++ b/src/nvidia-modeset/include/nvkms-flip-workarea.h @@ -26,6 +26,22 @@ #include "nvkms-types.h" +typedef struct { + struct { + enum NvKmsOutputTf tf; + enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace; + enum NvKmsDpyAttributeColorBpcValue colorBpc; + enum NvKmsDpyAttributeColorRangeValue colorRange; + } hdr; + + struct NvKmsPoint viewPortPointIn; + + struct { + NvU32 viewPortPointIn : 1; + NvU32 hdr : 1; + } dirty; +} NVProposedFlipStateOneApiHead; + struct NvKmsFlipWorkArea { struct { NvBool changed; @@ -43,6 +59,12 @@ struct NvKmsFlipWorkArea { NVFlipEvoHwState oldState; } head[NVKMS_MAX_HEADS_PER_DISP]; } sd[NVKMS_MAX_SUBDEVICES]; + + struct { + struct { + NVProposedFlipStateOneApiHead proposedFlipState; + } apiHead[NVKMS_MAX_HEADS_PER_DISP]; + } disp[NVKMS_MAX_SUBDEVICES]; }; #endif /* __NVKMS_FLIP_WORKAREA_H__ */ diff --git a/src/nvidia-modeset/include/nvkms-flip.h b/src/nvidia-modeset/include/nvkms-flip.h index 1fb3686a7..85cb0d228 100644 --- a/src/nvidia-modeset/include/nvkms-flip.h +++ b/src/nvidia-modeset/include/nvkms-flip.h @@ -27,77 +27,19 @@ #include "nvkms-types.h" -void nvClearFlipEvoHwState( - NVFlipEvoHwState *pFlipState); - -void nvInitFlipEvoHwState( - const NVDevEvoRec *pDevEvo, - const NvU32 sd, - const NvU32 head, - NVFlipEvoHwState *pFlipState); - -NvBool nvAssignSurfaceArray( - const NVDevEvoRec *pDevEvo, - const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, - const NvKmsSurfaceHandle surfaceHandles[NVKMS_MAX_EYES], - const NvBool isUsedByCursorChannel, - const NvBool isUsedByLayerChannel, - NVSurfaceEvoPtr pSurfaceEvos[NVKMS_MAX_EYES]); - -NvBool -nvAssignCursorSurface(const struct NvKmsPerOpenDev *pOpenDev, - const NVDevEvoRec *pDevEvo, - const struct NvKmsSetCursorImageCommonParams *pImgParams, - NVSurfaceEvoPtr *pSurfaceEvo); - -NvBool nvUpdateFlipEvoHwState( +NvBool nvCheckFlipPermissions( const struct NvKmsPerOpenDev *pOpenDev, const NVDevEvoRec *pDevEvo, const NvU32 sd, - const NvU32 head, - const struct NvKmsFlipCommonParams *pParams, - NVFlipEvoHwState *pFlipState, - NvBool allowVrr); - -void -nvOverrideScalingUsageBounds(const NVDevEvoRec *pDevEvo, - NvU32 head, - NVFlipEvoHwState *pFlipState, - const struct NvKmsUsageBounds *pPossibleUsage); - -NvBool nvValidateFlipEvoHwState( - const NVDevEvoRec *pDevEvo, - const NvU32 head, - const NVHwModeTimingsEvo *pTimings, - const NVFlipEvoHwState *pFlipState); - -void -nvUpdateSurfacesFlipRefCount( - NVDevEvoPtr pDevEvo, - const NvU32 head, - NVFlipEvoHwState *pFlipState, - NvBool increase); - -void nvFlipEvoOneHead( - NVDevEvoPtr pDevEvo, - const NvU32 sd, - const NvU32 head, - const NVFlipEvoHwState *pFlipState, - NvBool allowFlipLock, - NVEvoUpdateState *updateState); - -void nvEvoCancelPostFlipIMPTimer( - NVDevEvoPtr pDevEvo); - -void nvFillPostSyncptReplyOneChannel( - NVEvoChannel *pChannel, - enum NvKmsSyncptType postType, - struct NvKmsSyncpt *postSyncpt, - const NVFlipSyncObjectEvoHwState *pHwSyncObject); + const NvU32 apiHead, + const struct NvKmsFlipCommonParams *pParams); NvBool nvFlipEvo(NVDevEvoPtr pDevEvo, const struct NvKmsPerOpenDev *pOpenDev, - const struct NvKmsFlipRequest *request, + const struct NvKmsFlipRequestOneHead *pFlipHead, + NvU32 numFlipHeads, + NvBool commit, + NvBool allowVrr, struct NvKmsFlipReply *reply, NvBool skipUpdate, NvBool allowFlipLock); @@ -117,4 +59,47 @@ void nvApiHeadSetViewportPointIn(const NVDispEvoRec *pDispEvo, const NvU16 x, const NvU16 y); +NvU32 nvApiHeadGetActiveViewportOffset(NVDispEvoRec *pDispEvo, + NvU32 apiHead); + +void nvApiHeadIdleMainLayerChannels(NVDevEvoRec *pDevEvo, + const NvU32 apiHeadMaskPerSd[NVKMS_MAX_SUBDEVICES]); + +void nvApiHeadUpdateFlipLock(NVDevEvoRec *pDevEvo, + const NvU32 apiHeadMaskPerSd[NVKMS_MAX_SUBDEVICES], + const NvBool enable); + +void nvCancelSDRTransitionTimer(NVDispApiHeadStateEvoRec *pApiHeadState); + +NvBool nvIdleMainLayerChannelCheckIdleOneApiHead(NVDispEvoPtr pDispEvo, + NvU32 apiHead); + +#define NV_SURFACE_USAGE_MASK_CURSOR 0:0 +#define NV_SURFACE_USAGE_MASK_CURSOR_DISABLE 0 +#define NV_SURFACE_USAGE_MASK_CURSOR_ENABLE 1 +#define NV_SURFACE_USAGE_MASK_LAYER(_n) (3+(3*(_n))):(1+(3*(_n))) + +#define NV_SURFACE_USAGE_MASK_LAYER_SEMAPHORE 1:1 +#define NV_SURFACE_USAGE_MASK_LAYER_SEMAPHORE_DISABLE 0 +#define NV_SURFACE_USAGE_MASK_LAYER_SEMAPHORE_ENABLE 1 +#define NV_SURFACE_USAGE_MASK_LAYER_NOTIFIER 2:2 +#define NV_SURFACE_USAGE_MASK_LAYER_NOTIFIER_DISABLE 0 +#define NV_SURFACE_USAGE_MASK_LAYER_NOTIFIER_ENABLE 1 +#define NV_SURFACE_USAGE_MASK_LAYER_SCANOUT 0:0 +#define NV_SURFACE_USAGE_MASK_LAYER_SCANOUT_DISABLE 0 +#define NV_SURFACE_USAGE_MASK_LAYER_SCANOUT_ENABLE 1 + +NvU32 nvCollectSurfaceUsageMaskOneApiHead(const NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + NVSurfaceEvoPtr pSurfaceEvo); + +void nvIdleLayerChannels(NVDevEvoRec *pDevEvo, + NvU32 layerMaskPerSdApiHead[NVKMS_MAX_SUBDEVICES][NVKMS_MAX_HEADS_PER_DISP]); + +void nvEvoClearSurfaceUsage(NVDevEvoRec *pDevEvo, + NVSurfaceEvoPtr pSurfaceEvo); + +NvBool nvIdleBaseChannelOneApiHead(NVDispEvoRec *pDispEvo, NvU32 apiHead, + NvBool *pStoppedBase); + #endif /* __NVKMS_FLIP_H__ */ diff --git a/src/nvidia-modeset/include/nvkms-headsurface-config.h b/src/nvidia-modeset/include/nvkms-headsurface-config.h index 9f1e167ee..54740cf9b 100644 --- a/src/nvidia-modeset/include/nvkms-headsurface-config.h +++ b/src/nvidia-modeset/include/nvkms-headsurface-config.h @@ -25,7 +25,6 @@ #define __NVKMS_HEADSURFACE_CONFIG_H__ #include "nvkms-types.h" -#include "nvkms-modeset-types.h" /* NVProposedModeSetHwState */ #include "nvkms-softfloat.h" /* NvKmsMatrixF32 */ #include "nvidia-headsurface-types.h" /* NvHsStaticWarpMesh */ #include "g_shader_names.h" /* ProgramName */ diff --git a/src/nvidia-modeset/include/nvkms-headsurface-ioctl.h b/src/nvidia-modeset/include/nvkms-headsurface-ioctl.h index 10e977ad9..1973c8036 100644 --- a/src/nvidia-modeset/include/nvkms-headsurface-ioctl.h +++ b/src/nvidia-modeset/include/nvkms-headsurface-ioctl.h @@ -42,7 +42,10 @@ NvBool nvHsIoctlSetCursorImage( NvBool nvHsIoctlFlip( NVDevEvoPtr pDevEvo, const struct NvKmsPerOpenDev *pOpenDev, - const struct NvKmsFlipRequest *pRequest, + const struct NvKmsFlipRequestOneHead *pFlipHead, + NvU32 numFlipHeads, + NvBool commit, + NvBool allowVrr, struct NvKmsFlipReply *pReply); #endif /* __NVKMS_HEADSURFACE_IOCTL_H__ */ diff --git a/src/nvidia-modeset/include/nvkms-headsurface-priv.h b/src/nvidia-modeset/include/nvkms-headsurface-priv.h index ca4a61a60..854c1d5aa 100644 --- a/src/nvidia-modeset/include/nvkms-headsurface-priv.h +++ b/src/nvidia-modeset/include/nvkms-headsurface-priv.h @@ -159,7 +159,7 @@ typedef struct _NVHsChannelStatisticsOneEyeRec { typedef struct _NVHsChannelFlipQueueEntry { NVListRec flipQueueEntry; - NVFlipChannelEvoHwState hwState; + NVHsLayerRequestedFlipState hwState; } NVHsChannelFlipQueueEntry; typedef struct _NVHsChannelEvoRec { @@ -184,11 +184,11 @@ typedef struct _NVHsChannelEvoRec { } nv2d; /* - * NvKmsFlipParams is too large to declare on the stack. We preallocate it - * here so that we don't have to allocate and free it on every headSurface - * flip. + * Flip request parameters are too large to declare on the stack. We + * preallocate them here so that we don't have to allocate and free them on + * every headSurface flip. */ - struct NvKmsFlipParams scratchParams; + struct NvKmsFlipRequestOneHead scratchParams; /* * The index into NVDevEvoRec::apiHeadSurfaceAllDisps[apiHead]::surface[] to use @@ -246,7 +246,7 @@ typedef struct _NVHsChannelEvoRec { */ struct { - NVFlipChannelEvoHwState current; + NVHsLayerRequestedFlipState current; NVListRec queue; } flipQueue[NVKMS_MAX_LAYERS_PER_HEAD]; @@ -272,10 +272,10 @@ typedef struct _NVHsChannelEvoRec { NvBool usingRgIntrForSwapGroups; /* - * Handle to the RG line interrupt callback object. This is needed to + * Pointer to the RG line interrupt callback object. This is needed to * enabled and disable the RG interrupt callback. */ - NvU32 rgIntrCallbackObjectHandle; + NVRgLine1CallbackPtr pRgIntrCallback; #if NVKMS_PROCFS_ENABLE @@ -494,7 +494,7 @@ static inline void HsChangeSurfaceFlipRefCount( } /*! - * Get the last NVFlipChannelEvoHwState entry in the pHsChannel's flip queue for + * Get the last NVHsLayerRequestedFlipState entry in the pHsChannel's flip queue for * the specified layer. * * If the flip queue is empty, return the 'current' entry. Otherwise, return @@ -502,7 +502,7 @@ static inline void HsChangeSurfaceFlipRefCount( * * This function cannot fail. */ -static inline const NVFlipChannelEvoHwState *HsGetLastFlipQueueEntry( +static inline const NVHsLayerRequestedFlipState *HsGetLastFlipQueueEntry( const NVHsChannelEvoRec *pHsChannel, const NvU8 layer) { diff --git a/src/nvidia-modeset/include/nvkms-headsurface.h b/src/nvidia-modeset/include/nvkms-headsurface.h index 0e7a05b75..7e9eeb762 100644 --- a/src/nvidia-modeset/include/nvkms-headsurface.h +++ b/src/nvidia-modeset/include/nvkms-headsurface.h @@ -26,6 +26,14 @@ #include "nvkms-types.h" +typedef struct _NVHsLayerRequestedFlipStateRec { + NVSurfaceEvoPtr pSurfaceEvo[NVKMS_MAX_EYES]; + NVFlipCompletionNotifierEvoHwState completionNotifier; + NVFlipSyncObjectEvoHwState syncObject; + NvBool perEyeStereoFlip; + NvU8 minPresentInterval; +} NVHsLayerRequestedFlipState; + NvU64 nvHsMapSurfaceToDevice( const NVDevEvoRec *pDevEvo, const NvU32 rmHandle, @@ -61,7 +69,7 @@ void nvHsFreeChannel(NVHsChannelEvoPtr pHsChannel); void nvHsPushFlipQueueEntry( NVHsChannelEvoPtr pHsChannel, const NvU8 layer, - const NVFlipChannelEvoHwState *pHwState); + const NVHsLayerRequestedFlipState *pHwState); void nvHsDrainFlipQueue( NVHsChannelEvoPtr pHsChannel); @@ -120,7 +128,7 @@ void nvHsProcFs( NVEvoInfoStringRec *pInfoString, NVDevEvoRec *pDevEvo, NvU32 dispIndex, - NvU32 head); + NvU32 apiHead); #endif #endif /* __NVKMS_HEADSURFACE_H__ */ diff --git a/src/nvidia-modeset/include/nvkms-hw-flip.h b/src/nvidia-modeset/include/nvkms-hw-flip.h new file mode 100644 index 000000000..02b7be937 --- /dev/null +++ b/src/nvidia-modeset/include/nvkms-hw-flip.h @@ -0,0 +1,127 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVKMS_HW_FLIP_H__ +#define __NVKMS_HW_FLIP_H__ + + +#include "nvkms-types.h" +#include "nvkms-flip-workarea.h" + +NvBool nvIsLayerDirty(const struct NvKmsFlipCommonParams *pParams, + const NvU32 layer); + +void nvClearFlipEvoHwState( + NVFlipEvoHwState *pFlipState); + +void nvInitFlipEvoHwState( + const NVDevEvoRec *pDevEvo, + const NvU32 sd, + const NvU32 head, + NVFlipEvoHwState *pFlipState); + +NvBool nvUpdateFlipEvoHwState( + const struct NvKmsPerOpenDev *pOpenDev, + const NVDevEvoRec *pDevEvo, + const NvU32 sd, + const NvU32 head, + const struct NvKmsFlipCommonParams *pParams, + const NVHwModeTimingsEvo *pTimings, + NVFlipEvoHwState *pFlipState, + NvBool allowVrr); + +void +nvOverrideScalingUsageBounds(const NVDevEvoRec *pDevEvo, + NvU32 head, + NVFlipEvoHwState *pFlipState, + const struct NvKmsUsageBounds *pPossibleUsage); + +NvBool nvValidateFlipEvoHwState( + const NVDevEvoRec *pDevEvo, + const NvU32 head, + const NVHwModeTimingsEvo *pTimings, + const NVFlipEvoHwState *pFlipState); + +void +nvUpdateSurfacesFlipRefCount( + NVDevEvoPtr pDevEvo, + const NvU32 head, + NVFlipEvoHwState *pFlipState, + NvBool increase); + +void nvFlipEvoOneHead( + NVDevEvoPtr pDevEvo, + const NvU32 sd, + const NvU32 head, + const NVT_HDR_STATIC_METADATA *pHdrInfo, + const NVFlipEvoHwState *pFlipState, + NvBool allowFlipLock, + NVEvoUpdateState *updateState); + +void nvEvoCancelPostFlipIMPTimer( + NVDevEvoPtr pDevEvo); + +void nvFillPostSyncptReplyOneChannel( + NVEvoChannel *pChannel, + enum NvKmsSyncptType postType, + struct NvKmsSyncpt *postSyncpt, + const NVFlipSyncObjectEvoHwState *pHwSyncObject); + +NvBool nvAllocatePreFlipBandwidth(NVDevEvoPtr pDevEvo, + struct NvKmsFlipWorkArea *pWorkArea); + +void nvPreFlip(NVDevEvoRec *pDevEvo, + struct NvKmsFlipWorkArea *pWorkArea, + const NvBool applyAllowVrr, + const NvBool allowVrr, + const NvBool skipUpdate); + +void nvPostFlip(NVDevEvoRec *pDevEvo, + struct NvKmsFlipWorkArea *pWorkArea, + const NvBool skipUpdate, + const NvBool applyAllowVrr, + NvS32 *pVrrSemaphoreIndex); + +NvBool nvPrepareToDoPreFlip(NVDevEvoRec *pDevEvo, + struct NvKmsFlipWorkArea *pWorkArea); + +NvBool nvAssignNVFlipEvoHwState(NVDevEvoRec *pDevEvo, + const struct NvKmsPerOpenDev *pOpenDev, + const NvU32 sd, + const NvU32 head, + const struct NvKmsFlipCommonParams *pParams, + const NvBool allowVrr, + NVFlipEvoHwState *pFlipHwState); + +void nvIdleMainLayerChannels( + NVDevEvoPtr pDevEvo, + const NVEvoChannelMask *idleChannelMaskPerSd, + NvBool allowStopBase); + +NvBool nvNeedToToggleFlipLock(const NVDispEvoRec *pDispEvo, + const NvU32 head, const NvBool enable); + +void nvToggleFlipLockPerDisp(NVDispEvoRec *pDispEvo, const NvU32 headMask, + const NvBool enable); + +#endif /* __NVKMS_HW_FLIP_H__ */ diff --git a/src/nvidia-modeset/include/nvkms-lut.h b/src/nvidia-modeset/include/nvkms-lut.h index 5500e0127..e3d4eafb8 100644 --- a/src/nvidia-modeset/include/nvkms-lut.h +++ b/src/nvidia-modeset/include/nvkms-lut.h @@ -50,11 +50,11 @@ void nvUploadDataToLutSurfaceEvo(NVLutSurfaceEvoPtr pSurfEvo, static inline void nvCancelLutUpdateEvo( const NVDispEvoRec *pDispEvo, - const NvU32 head) + const NvU32 apiHead) { NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; - nvkms_free_timer(pDevEvo->lut.head[head].disp[pDispEvo->displayOwner].updateTimer); - pDevEvo->lut.head[head].disp[pDispEvo->displayOwner].updateTimer = NULL; + nvkms_free_timer(pDevEvo->lut.apiHead[apiHead].disp[pDispEvo->displayOwner].updateTimer); + pDevEvo->lut.apiHead[apiHead].disp[pDispEvo->displayOwner].updateTimer = NULL; } #ifdef __cplusplus diff --git a/src/nvidia-modeset/include/nvkms-modeset-types.h b/src/nvidia-modeset/include/nvkms-modeset-types.h index cdee15e29..1c2710e41 100644 --- a/src/nvidia-modeset/include/nvkms-modeset-types.h +++ b/src/nvidia-modeset/include/nvkms-modeset-types.h @@ -38,14 +38,14 @@ typedef struct { NVAttributesSetEvoRec attributes; struct NvKmsModeValidationParams modeValidationParams; NvBool changed : 1; - NvBool allowGsync : 1; NvBool hs10bpcHint : 1; - enum NvKmsAllowAdaptiveSync allowAdaptiveSync; - NvU32 vrrOverrideMinRefreshRate; + NvBool colorSpaceSpecified : 1; + NvBool colorRangeSpecified : 1; NVDPLibModesetStatePtr pDpLibModesetState; NVDispHeadAudioStateEvoRec audio; NVDispHeadInfoFrameStateEvoRec infoFrame; enum NvKmsOutputTf tf; + NVDispStereoParamsEvoRec stereo; } NVProposedModeSetHwStateOneHead; typedef struct { @@ -64,12 +64,4 @@ typedef struct { NvBool allowHeadSurfaceInNvKms : 1; } NVProposedModeSetHwState; -struct _NVEvoModesetUpdateState { - NVEvoUpdateState updateState; - NVDpyIdList connectorIds; - const NVDPLibModesetStateRec - *pDpLibModesetState[NVKMS_MAX_HEADS_PER_DISP]; - NvBool windowMappingChanged; -}; - #endif /* __NVKMS_MODESET_TYPES_H__ */ diff --git a/src/nvidia-modeset/include/nvkms-modeset.h b/src/nvidia-modeset/include/nvkms-modeset.h index f3abffbb5..b2095c732 100644 --- a/src/nvidia-modeset/include/nvkms-modeset.h +++ b/src/nvidia-modeset/include/nvkms-modeset.h @@ -48,19 +48,12 @@ NvBool nvSetDispModeEvo(NVDevEvoPtr pDevEvo, NvBool bypassComposition, NvBool doRasterLock); -typedef NvBool (*NVShutDownHeadsTestFunc)( +typedef NvBool (*NVShutDownApiHeadsTestFunc)( const NVDispEvoRec *pDispEvo, - const NvU32 head); + const NvU32 apiHead); -void nvShutDownHeads(NVDevEvoPtr pDevEvo, NVShutDownHeadsTestFunc pTestFunc); - -NVVBlankCallbackPtr nvRegisterVBlankCallback(NVDispEvoPtr pDispEvo, - NvU32 head, - NVVBlankCallbackProc pCallback, - void *pUserData); -void nvUnregisterVBlankCallback(NVDispEvoPtr pDispEvo, - NvU32 head, - NVVBlankCallbackPtr pCallback); +void nvShutDownApiHeads(NVDevEvoPtr pDevEvo, + NVShutDownApiHeadsTestFunc pTestFunc); NVVBlankCallbackPtr nvApiHeadRegisterVBlankCallback(NVDispEvoPtr pDispEvo, @@ -69,13 +62,18 @@ nvApiHeadRegisterVBlankCallback(NVDispEvoPtr pDispEvo, void *pUserData); void nvApiHeadUnregisterVBlankCallback(NVDispEvoPtr pDispEvo, - const NvU32 apiHead, NVVBlankCallbackPtr pCallback); -NvU32 -nvApiHeadAddRgLine1Callback(const NVDispEvoRec *pDispEvo, +NVRgLine1CallbackPtr +nvApiHeadAddRgLine1Callback(NVDispEvoRec *pDispEvo, const NvU32 apiHead, - NV0092_REGISTER_RG_LINE_CALLBACK_FN pCallback); + NVRgLine1CallbackProc pCallbackProc, + void *pUserData); + +void nvApiHeadGetScanLine(const NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + NvU16 *pScanLine, + NvBool *pInBlankingPeriod); #ifdef __cplusplus }; diff --git a/src/nvidia-modeset/include/nvkms-private.h b/src/nvidia-modeset/include/nvkms-private.h index cfb5eb9e5..c337819e0 100644 --- a/src/nvidia-modeset/include/nvkms-private.h +++ b/src/nvidia-modeset/include/nvkms-private.h @@ -47,9 +47,8 @@ void nvSendFrameLockAttributeChangedEventEvo( const enum NvKmsFrameLockAttribute attribute, const NvS64 value); -void nvSendFlipOccurredEventEvo( - const NVDevEvoRec *pDevEvo, - NVEvoChannelMask channelMask); +void nvSendFlipOccurredEventEvo(const NVDispEvoRec *pDispEvo, + const NvU32 apiHead, const NvU32 layer); void nvSendUnicastEvent(struct NvKmsPerOpen *pOpen); diff --git a/src/nvidia-modeset/include/nvkms-rm.h b/src/nvidia-modeset/include/nvkms-rm.h index 3755d60e6..336c6a140 100644 --- a/src/nvidia-modeset/include/nvkms-rm.h +++ b/src/nvidia-modeset/include/nvkms-rm.h @@ -126,16 +126,19 @@ void nvRmFreeEvoDma(NVDevEvoPtr pDevEvo, NVEvoDmaPtr pDma); NvBool nvRmQueryDpAuxLog(NVDispEvoRec *pDispEvo, NvS64 *pValue); NvU64 nvRmGetGpuTime(NVDevEvoPtr pDevEvo); NvBool nvRmSetGc6Allowed(NVDevEvoPtr pDevEvo, NvBool allowed); -NvU32 nvRmAddRgLine1Callback( - const NVDispEvoRec *pDispEvo, - NvU32 head, - NV0092_REGISTER_RG_LINE_CALLBACK_FN pCallback); +NVRgLine1CallbackPtr +nvRmAddRgLine1Callback(NVDispEvoRec *pDispEvo, + NvU32 head, + NVRgLine1CallbackProc pCallbackProc, + void *pUserData); void nvRmRemoveRgLine1Callback(const NVDispEvoRec *pDispEvo, - NvU32 callbackObjectHandle); + NVRgLine1CallbackPtr pCallback); + NvU32 nvRmAddVBlankCallback( const NVDispEvoRec *pDispEvo, NvU32 head, - OSVBLANKCALLBACKPROC pCallback); + OSVBLANKCALLBACKPROC pCallback, + void *pParam2); void nvRmRemoveVBlankCallback(const NVDispEvoRec *pDispEvo, NvU32 callbackObjectHandle); void nvRmMuxInit(NVDevEvoPtr pDevEvo); @@ -147,6 +150,9 @@ NvMuxState nvRmMuxState(const NVDpyEvoRec *pDpyEvo); void nvRmRegisterBacklight(NVDispEvoRec *pDispEvo); void nvRmUnregisterBacklight(NVDispEvoRec *pDispEvo); +void nvRmAllocCoreRGSyncpts(NVDevEvoPtr pDevEvo); +void nvRmFreeCoreRGSyncpts(NVDevEvoPtr pDevEvo); + #ifdef __cplusplus }; #endif diff --git a/src/nvidia-modeset/include/nvkms-types.h b/src/nvidia-modeset/include/nvkms-types.h index 7feaad447..81bc9132f 100644 --- a/src/nvidia-modeset/include/nvkms-types.h +++ b/src/nvidia-modeset/include/nvkms-types.h @@ -141,6 +141,7 @@ typedef struct _NVDispHeadStateEvoRec *NVDispHeadStateEvoPtr; typedef struct _NVDispEvoRec *NVDispEvoPtr; typedef struct _NVParsedEdidEvoRec *NVParsedEdidEvoPtr; typedef struct _NVVBlankCallbackRec *NVVBlankCallbackPtr; +typedef struct _NVRgLine1CallbackRec *NVRgLine1CallbackPtr; typedef struct _NVDpyEvoRec *NVDpyEvoPtr; typedef struct _NVLutSurfaceEvo *NVLutSurfaceEvoPtr; typedef struct _NVFrameLockEvo *NVFrameLockEvoPtr; @@ -148,6 +149,7 @@ typedef struct _NVEvoInfoString *NVEvoInfoStringPtr; typedef struct _NVSurfaceEvoRec NVSurfaceEvoRec, *NVSurfaceEvoPtr; typedef struct _NVDeferredRequestFifoRec *NVDeferredRequestFifoPtr; typedef struct _NVSwapGroupRec *NVSwapGroupPtr; +typedef struct _NVEvoModesetUpdateState NVEvoModesetUpdateState; /* * _NVHs*EvoRec are defined in nvkms-headsurface-priv.h; they are intentionally @@ -165,9 +167,6 @@ typedef struct __nv_dplibmodesetstate NVDPLibModesetStateRec, *NVDPLibModesetSta /* _nv_dplibtimer is defined in nvdp-timer.hpp */ typedef struct _nv_dplibtimer NVDPLibTimerRec, *NVDPLibTimerPtr; -/* _NVEvoModesetUpdateState defined in nvkms-modeset-types.h */ -typedef struct _NVEvoModesetUpdateState NVEvoModesetUpdateState; - typedef struct _NVEvoApiHandlesRec { void **pointers; /* Dynamically allocated array of pointers. */ NvU32 numPointers; /* Number of elements in pointers array. */ @@ -385,6 +384,14 @@ typedef struct { } NVEvoUpdateState; +struct _NVEvoModesetUpdateState { + NVEvoUpdateState updateState; + NVDpyIdList connectorIds; + const NVDPLibModesetStateRec + *pDpLibModesetState[NVKMS_MAX_HEADS_PER_DISP]; + NvBool windowMappingChanged; +}; + typedef struct { struct { NVEvoChannelMask channelMask; @@ -393,7 +400,6 @@ typedef struct { typedef struct { NvU8 validTimeStampBits; - NvU8 legacyNotifierFormatSizeBytes; NvBool tearingFlips :1; NvBool vrrTearingFlips :1; NvBool perEyeStereoFlips :1; @@ -420,6 +426,8 @@ typedef struct _NVEvoSyncpt { NvU32 hCtxDma; /*! handle of syncpt object */ NvU32 hSyncpt; + /*! stores syncpt max value */ + NvU32 syncptMaxVal; } NVEvoSyncpt; /* Tracks internal state of a vblank sync object. */ @@ -456,7 +464,6 @@ typedef struct _NVEvoChannel { NVOS10_EVENT_KERNEL_CALLBACK_EX completionNotifierEventCallback; NvU32 completionNotifierEventHandle; - struct nvkms_ref_ptr *ref_ptr; /* * GV100 timestamped flips need a duplicate update which only changes @@ -644,6 +651,19 @@ typedef struct { } maxDownscaleFactors; } NVFlipChannelEvoHwState; +enum NvKmsDpyAttributeColorBpcValue { + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_UNKNOWN = 0, + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_10 = 10, + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8 = 8, + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_6 = 6, +}; + +typedef struct _NVColorFormatInfoRec { + struct { + enum NvKmsDpyAttributeColorBpcValue maxBpc; + } rgb444, yuv444, yuv422; +} NVColorFormatInfoRec; + typedef struct { struct NvKmsPoint viewPortPointIn; NVFlipCursorEvoHwState cursor; @@ -838,6 +858,9 @@ typedef struct { struct NvKmsCompositionCapabilities cursorCompositionCaps; NvU16 validLayerRRTransforms; struct NvKmsLayerCapabilities layerCaps[NVKMS_MAX_LAYERS_PER_HEAD]; + NvU8 legacyNotifierFormatSizeBytes[NVKMS_MAX_LAYERS_PER_HEAD]; + NvU8 dpYCbCr422MaxBpc; + NvU8 hdmiYCbCr422MaxBpc; } NVEvoCapsRec; typedef struct { @@ -1154,7 +1177,7 @@ typedef struct _NVEvoDevRec { NvU8 curLUTIndex; nvkms_timer_handle_t *updateTimer; } disp[NVKMS_MAX_SUBDEVICES]; - } head[NVKMS_MAX_HEADS_PER_DISP]; + } apiHead[NVKMS_MAX_HEADS_PER_DISP]; NVLutSurfaceEvoPtr defaultLut; enum NvKmsLUTState defaultBaseLUTState[NVKMS_MAX_SUBDEVICES]; enum NvKmsLUTState defaultOutputLUTState[NVKMS_MAX_SUBDEVICES]; @@ -1230,6 +1253,8 @@ enum nvKmsPixelDepth { NVKMS_PIXEL_DEPTH_18_444, NVKMS_PIXEL_DEPTH_24_444, NVKMS_PIXEL_DEPTH_30_444, + NVKMS_PIXEL_DEPTH_20_422, + NVKMS_PIXEL_DEPTH_16_422, }; enum nvKmsTimingsProtocol { @@ -1264,7 +1289,6 @@ typedef struct _NVHwModeTimingsEvo { NvU32 pixelClock; /* in kHz */ enum nvKmsTimingsProtocol protocol; - enum nvKmsPixelDepth pixelDepth; /* * yuv420Mode reflects whether this mode requires YUV 4:2:0 decimation into * a half-width output through headsurface (SW YUV420) or >=nvdisplay 4.0 HW @@ -1321,11 +1345,6 @@ typedef struct _NVHwModeTimingsEvo { HDMI_FRL_CONFIG hdmiFrlConfig; NVHwModeViewPortEvo viewPort; - - struct { - enum NvKmsStereoMode mode; - NvBool isAegis; - } stereo; } NVHwModeTimingsEvo; static inline NvU64 nvEvoFrametimeUsFromTimings(const NVHwModeTimingsEvo *pTimings) @@ -1469,6 +1488,13 @@ typedef struct _NVConnectorEvoRec { NvU32 physicalLocation; NvU32 validHeadMask; + /* + * [2Heads1OR] XXX Implement the dynamic api-head to hardware-heads mapping + * and remove NVConnectorEvoRec::validApiHeadMask and + * NvKmsQueryConnectorStaticDataReply::headMask. + */ + NvU32 validApiHeadMask; + NvU32 dfpInfo; /* DFP info query through NV0073_CTRL_CMD_DFP_GET_INFO */ NVDpyIdList ddcPartnerDpyIdsList; @@ -1485,12 +1511,9 @@ typedef struct _NVConnectorEvoRec { NvU32 mask; } or; - struct { - NvBool ycbcr422Capable; - NvBool ycbcr444Capable; - } colorSpaceCaps; - NvEldCase audioDevEldCase[NV_MAX_AUDIO_DEVICE_ENTRIES]; + + NvBool isHdmiEnabled; } NVConnectorEvoRec; static inline NvU32 nvConnectorGetAttachedHeadMaskEvo( @@ -1552,6 +1575,10 @@ typedef struct __NVAttributesSetEvoRec { * stored in NVDpyEvoRec::requestedColor(Space, Range}. The structure stores * the actual color space and color range in use. * + * nvChooseCurrentColorSpaceAndRangeEvo() chooses the actual color + * space, color bpc, and color range, for a dpy. It sets colorBpc + * to the max bpc supported by the given dpy. + * * Since YUV444 mode only allows limited color range, changes to the * current color space may trigger changes to the current color * range (see nvChooseCurrentColorSpaceAndRangeEvo()). @@ -1560,6 +1587,7 @@ typedef struct __NVAttributesSetEvoRec { * HEAD_SET_PROCAMP and applied in the headSurface composite shader. */ enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace; + enum NvKmsDpyAttributeColorBpcValue colorBpc; enum NvKmsDpyAttributeColorRangeValue colorRange; NVDpyAttributeCurrentDitheringConfig dithering; @@ -1657,29 +1685,23 @@ typedef struct _NVDispHeadStateEvoRec { NVHwModeTimingsEvo timings; NVConnectorEvoRec *pConnectorEvo; /* NULL if the head is not active */ - /* - * Each head can have up to NVKMS_MAX_VBLANK_SYNC_OBJECTS_PER_HEAD - * programmable Core semaphores. - * - * The numVblankSyncObjectsCreated will ideally always be equal to - * NVKMS_MAX_VBLANK_SYNC_OBJECTS_PER_HEAD, but could be lower if errors - * occured during syncpt allocation in nvRMSetupEvoCoreChannel(). - */ - NvU8 numVblankSyncObjectsCreated; - NVVblankSyncObjectRec vblankSyncObjects[NVKMS_MAX_VBLANK_SYNC_OBJECTS_PER_HEAD]; - NVDispHeadAudioStateEvoRec audio; + enum nvKmsPixelDepth pixelDepth; - NvU32 rmVBlankCallbackHandle; - NVListRec vblankCallbackList; + NVDispHeadAudioStateEvoRec audio; enum NvKmsOutputTf tf; struct { enum NvKmsHDROutputState outputState; struct NvKmsHDRStaticMetadata staticMetadata; - nvkms_timer_handle_t *sdrTransitionTimer; } hdr; + struct { + NVLutSurfaceEvoPtr pCurrSurface; + NvBool outputLutEnabled : 1; + NvBool baseLutEnabled : 1; + } lut; + /* * The api head can be mapped onto the N harware heads, a frame presented * by the api head gets split horizontally into N tiles, 'tilePosition' @@ -1688,6 +1710,17 @@ typedef struct _NVDispHeadStateEvoRec { NvU8 tilePosition; } NVDispHeadStateEvoRec; +typedef struct _NVDispStereoParamsEvoRec { + enum NvKmsStereoMode mode; + NvBool isAegis; +} NVDispStereoParamsEvoRec; + +typedef struct _NVDispFlipOccurredEventDataEvoRec { + NVDispEvoPtr pDispEvo; + NvU32 apiHead; + NvU32 layer; +} NVDispFlipOccurredEventDataEvoRec; + typedef struct _NVDispApiHeadStateEvoRec { /* * The mask of hardware heads mapped onto this api head, @@ -1698,6 +1731,9 @@ typedef struct _NVDispApiHeadStateEvoRec { NVDpyIdList activeDpys; /* Empty if the head is not active */ NVAttributesSetEvoRec attributes; + enum NvKmsOutputTf tf; + nvkms_timer_handle_t *hdrToSdrTransitionTimer; + /* * Hardware timings which are split across hardware heads. * @@ -1707,10 +1743,31 @@ typedef struct _NVDispApiHeadStateEvoRec { */ NVHwModeTimingsEvo timings; + NVDispStereoParamsEvoRec stereo; + struct NvKmsPoint viewPortPointIn; NVDispHeadInfoFrameStateEvoRec infoFrame; + /* + * Each head can have up to NVKMS_MAX_VBLANK_SYNC_OBJECTS_PER_HEAD + * programmable Core semaphores. + * + * The numVblankSyncObjectsCreated will ideally always be equal to + * NVKMS_MAX_VBLANK_SYNC_OBJECTS_PER_HEAD, but could be lower if errors + * occured during syncpt allocation in nvRMSetupEvoCoreChannel(). + */ + NvU8 numVblankSyncObjectsCreated; + NVVblankSyncObjectRec vblankSyncObjects[NVKMS_MAX_VBLANK_SYNC_OBJECTS_PER_HEAD]; + + struct { + struct nvkms_ref_ptr *ref_ptr; + NVDispFlipOccurredEventDataEvoRec data; + } flipOccurredEvent[NVKMS_MAX_LAYERS_PER_HEAD]; + + NvU32 rmVBlankCallbackHandle; + NVListRec vblankCallbackList; + NvBool hs10bpcHint : 1; } NVDispApiHeadStateEvoRec; @@ -1814,11 +1871,21 @@ typedef struct _NVDispEvoRec { * XXX[2Head1OR] Remove nvHardwareHeadToApiHead(), before implementing logic to * map multiple hardware heads onto the single api head. */ -static inline NvU32 nvHardwareHeadToApiHead(const NvU32 head) +static inline NvU32 nvHardwareHeadToApiHead(const NVDevEvoRec *pDevEvo, + const NvU32 head) { - return head; -} + /* + * Force a non-identity mapping between hardware heads and api heads, + * to identify bugs in api head handling. + */ + if (head < pDevEvo->numHeads) { + return (pDevEvo->numHeads - 1) - head; + } else { + nvAssert(head == NV_INVALID_HEAD); + return head; + } +} static inline NvU32 GetNextHwHead(NvU32 hwHeadsMask, const NvU32 prevHwHead) { @@ -1868,15 +1935,24 @@ typedef struct _NVParsedEdidEvoRec { } NVParsedEdidEvoRec; typedef void (*NVVBlankCallbackProc)(NVDispEvoRec *pDispEvo, - const NvU32 head, NVVBlankCallbackPtr pCallbackData); typedef struct _NVVBlankCallbackRec { NVListRec vblankCallbackListEntry; NVVBlankCallbackProc pCallback; void *pUserData; + NvU32 apiHead; } NVVBlankCallbackRec; +typedef void (*NVRgLine1CallbackProc)(NVDispEvoRec *pDispEvo, + const NvU32 head, + NVRgLine1CallbackPtr pCallbackData); + +typedef struct _NVRgLine1CallbackRec { + NVRgLine1CallbackProc pCallbackProc; + void *pUserData; +} NVRgLine1CallbackRec; + typedef struct _NVDpyAttributeRequestedDitheringConfigRec { enum NvKmsDpyAttributeRequestedDitheringValue state; enum NvKmsDpyAttributeRequestedDitheringDepthValue depth; @@ -2234,7 +2310,12 @@ typedef struct _NVLutSurfaceEvo { NvU32 allocRefCnt; /* Only used for dynamically allocated LUTs */ + NvU64 gpuAddress; void *subDeviceAddress[NVKMS_MAX_SUBDEVICES]; + + /* Keep track of prefetched surfaces. */ + NvU32 difrLastPrefetchPass; + } NVLutSurfaceEvoRec; typedef struct _NVFrameLockEvo { @@ -2553,6 +2634,7 @@ typedef struct { struct { /* pTimings == NULL => this head is disabled */ const NVHwModeTimingsEvo *pTimings; + enum nvKmsPixelDepth pixelDepth; const struct NvKmsUsageBounds *pUsage; NvU32 displayId; NvU32 orIndex; @@ -2637,6 +2719,7 @@ typedef const struct _nv_evo_hal { void (*HeadSetControlOR) (NVDevEvoPtr pDevEvo, const int head, const NVHwModeTimingsEvo *pTimings, + const enum nvKmsPixelDepth pixelDepth, const NvBool colorSpaceOverride, NVEvoUpdateState *updateState); void (*ORSetControl) (NVDevEvoPtr pDevEvo, @@ -2780,7 +2863,8 @@ typedef const struct _nv_evo_hal { void (*SetDscParams) (const NVDispEvoRec *pDispEvo, const NvU32 head, - const NVHwModeTimingsEvo *pTimings); + const NVHwModeTimingsEvo *pTimings, + const enum nvKmsPixelDepth pixelDepth); void (*EnableMidFrameAndDWCFWatermark)(NVDevEvoPtr pDevEvo, NvU32 sd, diff --git a/src/nvidia-modeset/include/nvkms-utils-flip.h b/src/nvidia-modeset/include/nvkms-utils-flip.h new file mode 100644 index 000000000..ac736d835 --- /dev/null +++ b/src/nvidia-modeset/include/nvkms-utils-flip.h @@ -0,0 +1,73 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVKMS_FLIP_UTILS_H__ +#define __NVKMS_FLIP_UTILS_H__ + + +#include "nvkms-types.h" + +NvBool nvAssignSurfaceArray( + const NVDevEvoRec *pDevEvo, + const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, + const NvKmsSurfaceHandle surfaceHandles[NVKMS_MAX_EYES], + const NvBool isUsedByCursorChannel, + const NvBool isUsedByLayerChannel, + NVSurfaceEvoPtr pSurfaceEvos[NVKMS_MAX_EYES]); + +NvBool nvAssignNIsoEvoHwState( + const NVDevEvoRec *pDevEvo, + const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, + const struct NvKmsNIsoSurface *pParamsNIso, + const NvBool notifier, /* TRUE=notifier; FALSE=semaphore */ + const NvU32 layer, + NVFlipNIsoSurfaceEvoHwState *pNIsoState); + +NvBool nvAssignCompletionNotifierEvoHwState( + const NVDevEvoRec *pDevEvo, + const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, + const struct NvKmsCompletionNotifierDescription *pParamsNotif, + const NvU32 layer, + NVFlipCompletionNotifierEvoHwState *pNotif); + +NvBool nvAssignSemaphoreEvoHwState( + const NVDevEvoRec *pDevEvo, + const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, + const NvU32 layer, + const NvU32 sd, + const struct NvKmsChannelSyncObjects *pChannelSyncObjects, + NVFlipSyncObjectEvoHwState *pFlipSyncObject); + +NvBool nvValidatePerLayerCompParams( + const struct NvKmsCompositionParams *pCompParams, + const struct NvKmsCompositionCapabilities *pCaps, + NVSurfaceEvoPtr pSurfaceEvo); + +NvBool +nvAssignCursorSurface(const struct NvKmsPerOpenDev *pOpenDev, + const NVDevEvoRec *pDevEvo, + const struct NvKmsSetCursorImageCommonParams *pImgParams, + NVSurfaceEvoPtr *pSurfaceEvo); + + +#endif /* __NVKMS_FLIP_UTILS_H__ */ diff --git a/src/nvidia-modeset/include/nvkms-vrr.h b/src/nvidia-modeset/include/nvkms-vrr.h index f90ee0301..bb1add984 100644 --- a/src/nvidia-modeset/include/nvkms-vrr.h +++ b/src/nvidia-modeset/include/nvkms-vrr.h @@ -25,7 +25,6 @@ #define __NVKMS_VRR_H__ #include "nvkms-types.h" -#include "nvkms-modeset-types.h" #ifdef __cplusplus extern "C" { @@ -34,8 +33,7 @@ extern "C" { void nvAllocVrrEvo(NVDevEvoPtr pDevEvo); void nvFreeVrrEvo(NVDevEvoPtr pDevEvo); void nvDisableVrr(NVDevEvoPtr pDevEvo); -void nvEnableVrr(NVDevEvoPtr pDevEvo, - const struct NvKmsSetModeRequest *pRequest); +void nvEnableVrr(NVDevEvoPtr pDevEvo); void nvCancelVrrFrameReleaseTimers(NVDevEvoPtr pDevEvo); void nvSetVrrActive(NVDevEvoPtr pDevEvo, NvBool active); void nvApplyVrrBaseFlipOverrides(const NVDispEvoRec *pDispEvo, NvU32 head, @@ -45,7 +43,7 @@ enum NvKmsVrrFlipType nvGetActiveVrrType(const NVDevEvoRec *pDevEvo); NvS32 nvIncVrrSemaphoreIndex(NVDevEvoPtr pDevEvo); void nvTriggerVrrUnstallMoveCursor(NVDispEvoPtr pDispEvo); void nvTriggerVrrUnstallSetCursorImage(NVDispEvoPtr pDispEvo, - NvBool ctxDmaChanged); + NvBool elvReleased); void nvGetDpyMinRefreshRateValidValues( const NVHwModeTimingsEvo *pTimings, const enum NvKmsDpyVRRType vrrType, diff --git a/src/nvidia-modeset/interface/nvkms-api.h b/src/nvidia-modeset/interface/nvkms-api.h index 1682ace4c..422555f3f 100644 --- a/src/nvidia-modeset/interface/nvkms-api.h +++ b/src/nvidia-modeset/interface/nvkms-api.h @@ -1930,13 +1930,7 @@ struct NvKmsSetModeOneHeadReply { */ enum NvKmsSetModeOneHeadStatus status; - /*! - * The identifier that we use to talk to RM about the display - * device(s) driven by this head. For DP MST, it is the identifier - * of the DisplayPort library group to which the MST device belongs. - * Otherwise, it is the identifier of the connector. - */ - NvU32 activeRmId; + NvU32 hwHead; /*! * The usage bounds that may be possible on this head based on the ISO @@ -2120,24 +2114,25 @@ struct NvKmsIdleBaseChannelParams { /*! * NVKMS_IOCTL_FLIP: Flip one or more heads on the subdevices of a device. * - * At least one head on one subdevice must be specified in a flip request. + * At least one head must be specified in a flip request, and at most + * NV_MAX_FLIP_REQUEST_HEADS may be specified. */ -struct NvKmsFlipRequestOneSubDevice { - /*! - * The bit mask of which head[] elements to look at on this disp. - */ - NvU32 requestedHeadsBitMask; - struct NvKmsFlipCommonParams head[NVKMS_MAX_HEADS_PER_DISP]; +struct NvKmsFlipRequestOneHead { + NvU32 sd; + NvU32 head; + struct NvKmsFlipCommonParams flip; }; +#define NV_MAX_FLIP_REQUEST_HEADS (NV_MAX_SUBDEVICES * NV_MAX_HEADS) + struct NvKmsFlipRequest { NvKmsDeviceHandle deviceHandle; - /* - * sd[n] corresponds to bit N in NvKmsAllocDeviceReply::subDeviceMask. - */ - struct NvKmsFlipRequestOneSubDevice sd[NVKMS_MAX_SUBDEVICES]; + /* Pointer to an array of length 'numFlipHeads'; each entry in the array is + * of type 'struct NvKmsFlipRequestOneHead'. */ + NvU64 pFlipHead NV_ALIGN_BYTES(8); + NvU32 numFlipHeads; /*! * When a flip request is made, NVKMS will first perform @@ -2166,10 +2161,6 @@ enum NvKmsVrrFlipType { NV_KMS_VRR_FLIP_ADAPTIVE_SYNC, }; -struct NvKmsFlipReplyOneSubDevice { - struct NvKmsFlipCommonReplyOneHead head[NVKMS_MAX_HEADS_PER_DISP]; -}; - struct NvKmsFlipReply { /*! * If vrrFlipType != NV_KMS_VRR_FLIP_NON_VRR, then VRR was used for the @@ -2189,9 +2180,10 @@ struct NvKmsFlipReply { enum NvKmsVrrFlipType vrrFlipType; /*! - * sd[n] corresponds to bit N in NvKmsAllocDeviceReply::subDeviceMask. + * Entries correspond to the heads specified in + * NvKmsFlipRequest::pFlipHead, in the same order. */ - struct NvKmsFlipReplyOneSubDevice sd[NVKMS_MAX_SUBDEVICES]; + struct NvKmsFlipCommonReplyOneHead flipHead[NV_MAX_FLIP_REQUEST_HEADS]; }; struct NvKmsFlipParams { @@ -2520,6 +2512,7 @@ enum NvKmsAttributeType { enum NvKmsDpyAttribute { NV_KMS_DPY_ATTRIBUTE_BACKLIGHT_BRIGHTNESS = 0, NV_KMS_DPY_ATTRIBUTE_SCANLINE, + NV_KMS_DPY_ATTRIBUTE_HW_HEAD, NV_KMS_DPY_ATTRIBUTE_HEAD, NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING, NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_MODE, @@ -2603,7 +2596,6 @@ enum NvKmsDpyAttributeCurrentColorSpaceValue { NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422 = 1, NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444 = 2, NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420 = 3, - NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_BT2020RGB = 4, }; /*! Values for the NV_KMS_DPY_ATTRIBUTE_DIGITAL_SIGNAL attribute. */ @@ -3243,14 +3235,11 @@ struct NvKmsReleaseOwnershipParams { * permissions. * * - The modeset owner can optionally revoke any previously granted - * permissions with NVKMS_IOCTL_REVOKE_PERMISSIONS. + * permissions with NVKMS_IOCTL_REVOKE_PERMISSIONS. This can be + * device-scope for all of a type, or just a set of permissions. * * Notes: * - * - NVKMS_IOCTL_REVOKE_PERMISSIONS has device-scope. It could be - * made finer-grained (e.g., take the file descriptor that was used - * to grant permissions) if that were needed. - * * - NvKmsPermissions::disp[n] corresponds to the disp named by * NvKmsAllocDeviceReply::dispHandles[n]. * @@ -3357,10 +3346,15 @@ struct NvKmsRevokePermissionsRequest { /* * A bitmask of permission types to be revoked for this device. - * It should be the bitwise 'or' of one or more + * It should be the bitwise 'or' of any number of * NVBIT(NV_KMS_PERMISSIONS_TYPE_*) values. */ NvU32 permissionsTypeBitmask; + + /* + * If permissionsTypeBitmask is 0, instead revoke only these permissions. + */ + struct NvKmsPermissions permissions; }; struct NvKmsRevokePermissionsReply { diff --git a/src/nvidia-modeset/kapi/interface/nvkms-kapi.h b/src/nvidia-modeset/kapi/interface/nvkms-kapi.h index 0ae71e170..c76493d74 100644 --- a/src/nvidia-modeset/kapi/interface/nvkms-kapi.h +++ b/src/nvidia-modeset/kapi/interface/nvkms-kapi.h @@ -520,14 +520,23 @@ struct NvKmsKapiFunctionsTable { ); /*! - * Revoke modeset permissions previously granted. This currently applies for all - * previous grant requests for this device. + * Revoke permissions previously granted. Only one (dispIndex, head, + * display) is currently supported. * - * \param [in] device A device returned by allocateDevice(). + * \param [in] device A device returned by allocateDevice(). + * + * \param [in] head head of display. + * + * \param [in] display The display to revoke. * * \return NV_TRUE on success, NV_FALSE on failure. */ - NvBool (*revokePermissions)(struct NvKmsKapiDevice *device); + NvBool (*revokePermissions) + ( + struct NvKmsKapiDevice *device, + NvU32 head, + NvKmsKapiDisplay display + ); /*! * Registers for notification, via diff --git a/src/nvidia-modeset/kapi/src/nvkms-kapi-channelevent.c b/src/nvidia-modeset/kapi/src/nvkms-kapi-sync.c similarity index 100% rename from src/nvidia-modeset/kapi/src/nvkms-kapi-channelevent.c rename to src/nvidia-modeset/kapi/src/nvkms-kapi-sync.c diff --git a/src/nvidia-modeset/kapi/src/nvkms-kapi.c b/src/nvidia-modeset/kapi/src/nvkms-kapi.c index 8f3a63de3..e521be1b3 100644 --- a/src/nvidia-modeset/kapi/src/nvkms-kapi.c +++ b/src/nvidia-modeset/kapi/src/nvkms-kapi.c @@ -851,11 +851,20 @@ static NvBool GrantPermissions sizeof(paramsGrant)); } -static NvBool RevokePermissions(struct NvKmsKapiDevice *device) +static NvBool RevokePermissions +( + struct NvKmsKapiDevice *device, + NvU32 head, + NvKmsKapiDisplay display +) { struct NvKmsRevokePermissionsParams paramsRevoke = { }; + struct NvKmsPermissions *perm = ¶msRevoke.request.permissions; + NvU32 dispIdx = device->dispIdx; - if (device == NULL) { + + if (dispIdx >= ARRAY_LEN(perm->modeset.disp) || + head >= ARRAY_LEN(perm->modeset.disp[0].head) || device == NULL) { return NV_FALSE; } @@ -863,8 +872,11 @@ static NvBool RevokePermissions(struct NvKmsKapiDevice *device) return NV_TRUE; } + perm->type = NV_KMS_PERMISSIONS_TYPE_MODESET; + perm->modeset.disp[dispIdx].head[head].dpyIdList = + nvAddDpyIdToEmptyDpyIdList(nvNvU32ToDpyId(display)); + paramsRevoke.request.deviceHandle = device->hKmsDevice; - paramsRevoke.request.permissionsTypeBitmask = NVBIT(NV_KMS_PERMISSIONS_TYPE_MODESET); return nvkms_ioctl_from_kapi(device->pKmsOpen, NVKMS_IOCTL_REVOKE_PERMISSIONS, ¶msRevoke, @@ -2315,10 +2327,9 @@ static NvBool ValidateDisplayMode static NvBool AssignSyncObjectConfig( struct NvKmsKapiDevice *device, const struct NvKmsKapiLayerConfig *pLayerConfig, - struct NvKmsChannelSyncObjects *pSyncObject, - NvBool bFromKmsSetMode) + struct NvKmsChannelSyncObjects *pSyncObject) { - if (!device->supportsSyncpts || bFromKmsSetMode) { + if (!device->supportsSyncpts) { if (pLayerConfig->syncptParams.preSyncptSpecified || pLayerConfig->syncptParams.postSyncptRequested) { return NV_FALSE; @@ -2468,8 +2479,7 @@ static NvBool NvKmsKapiOverlayLayerConfigToKms( ret = AssignSyncObjectConfig(device, layerConfig, - ¶ms->layer[layer].syncObjects.val, - bFromKmsSetMode); + ¶ms->layer[layer].syncObjects.val); if (ret == NV_FALSE) { return ret; } @@ -2569,8 +2579,7 @@ static NvBool NvKmsKapiPrimaryLayerConfigToKms( ret = AssignSyncObjectConfig(device, layerConfig, - ¶ms->layer[NVKMS_MAIN_LAYER].syncObjects.val, - bFromKmsSetMode); + ¶ms->layer[NVKMS_MAIN_LAYER].syncObjects.val); if (ret == NV_FALSE) { return ret; } @@ -2848,90 +2857,89 @@ static NvBool KmsFlip( struct NvKmsKapiModeSetReplyConfig *replyConfig, const NvBool commit) { - NvBool bChanged = NV_FALSE; struct NvKmsFlipParams *params = NULL; + struct NvKmsFlipRequestOneHead *pFlipHead = NULL; NvBool status = NV_TRUE; - NvU32 i; + NvU32 i, head; - params = nvKmsKapiCalloc(1, sizeof(*params)); + /* Allocate space for the params structure, plus space for each possible + * head. */ + params = nvKmsKapiCalloc(1, + sizeof(*params) + sizeof(pFlipHead[0]) * NVKMS_KAPI_MAX_HEADS); if (params == NULL) { return NV_FALSE; } + /* The flipHead array was allocated in the same block above. */ + pFlipHead = (struct NvKmsFlipRequestOneHead *)(params + 1); + params->request.deviceHandle = device->hKmsDevice; params->request.commit = commit; params->request.allowVrr = NV_FALSE; + params->request.pFlipHead = nvKmsPointerToNvU64(pFlipHead); + params->request.numFlipHeads = 0; + for (head = 0; + head < ARRAY_LEN(requestedConfig->headRequestedConfig); head++) { - for (i = 0; i < ARRAY_LEN(params->request.sd); i++) { - struct NvKmsFlipRequestOneSubDevice *sdParams = ¶ms->request.sd[i]; - NvU32 head; + const struct NvKmsKapiHeadRequestedConfig *headRequestedConfig = + &requestedConfig->headRequestedConfig[head]; + const struct NvKmsKapiHeadModeSetConfig *headModeSetConfig = + &headRequestedConfig->modeSetConfig; + enum NvKmsOutputTf tf; - if ((device->subDeviceMask & (1 << i)) == 0x0) { + struct NvKmsFlipCommonParams *flipParams = NULL; + + NvU32 layer; + + if (!IsHeadConfigValid(params, requestedConfig, headModeSetConfig, head)) { continue; } - for (head = 0; - head < ARRAY_LEN(requestedConfig->headRequestedConfig); head++) { + pFlipHead[params->request.numFlipHeads].sd = 0; + pFlipHead[params->request.numFlipHeads].head = head; + flipParams = &pFlipHead[params->request.numFlipHeads].flip; + params->request.numFlipHeads++; - const struct NvKmsKapiHeadRequestedConfig *headRequestedConfig = - &requestedConfig->headRequestedConfig[head]; - const struct NvKmsKapiHeadModeSetConfig *headModeSetConfig = - &headRequestedConfig->modeSetConfig; - enum NvKmsOutputTf tf; + NvKmsKapiCursorConfigToKms(&headRequestedConfig->cursorRequestedConfig, + flipParams, + NV_FALSE /* bFromKmsSetMode */); - struct NvKmsFlipCommonParams *flipParams = &sdParams->head[head]; + for (layer = 0; + layer < ARRAY_LEN(headRequestedConfig->layerRequestedConfig); + layer++) { - NvU32 layer; + const struct NvKmsKapiLayerRequestedConfig + *layerRequestedConfig = + &headRequestedConfig->layerRequestedConfig[layer]; - if (!IsHeadConfigValid(params, requestedConfig, headModeSetConfig, head)) { - continue; - } + status = NvKmsKapiLayerConfigToKms(device, + layerRequestedConfig, + layer, + head, + flipParams, + commit, + NV_FALSE /* bFromKmsSetMode */); - sdParams->requestedHeadsBitMask |= 1 << head; - - NvKmsKapiCursorConfigToKms(&headRequestedConfig->cursorRequestedConfig, - flipParams, - NV_FALSE /* bFromKmsSetMode */); - - for (layer = 0; - layer < ARRAY_LEN(headRequestedConfig->layerRequestedConfig); - layer++) { - - const struct NvKmsKapiLayerRequestedConfig - *layerRequestedConfig = - &headRequestedConfig->layerRequestedConfig[layer]; - - status = NvKmsKapiLayerConfigToKms(device, - layerRequestedConfig, - layer, - head, - flipParams, - commit, - NV_FALSE /* bFromKmsSetMode */); - - if (status != NV_TRUE) { - goto done; - } - - bChanged = NV_TRUE; - } - - status = GetOutputTransferFunction(headRequestedConfig, &tf); if (status != NV_TRUE) { goto done; } + } - flipParams->tf.val = tf; - flipParams->tf.specified = NV_TRUE; + status = GetOutputTransferFunction(headRequestedConfig, &tf); + if (status != NV_TRUE) { + goto done; + } - if (headModeSetConfig->vrrEnabled) { - params->request.allowVrr = NV_TRUE; - } + flipParams->tf.val = tf; + flipParams->tf.specified = NV_TRUE; + + if (headModeSetConfig->vrrEnabled) { + params->request.allowVrr = NV_TRUE; } } - if (!bChanged) { + if (params->request.numFlipHeads == 0) { goto done; } @@ -2946,58 +2954,44 @@ static NvBool KmsFlip( goto done; } - if (!bChanged || !commit) { + if (!commit) { goto done; } /*! fill back flip reply */ - for (i = 0; i < ARRAY_LEN(params->request.sd); i++) { + for (i = 0; i < params->request.numFlipHeads; i++) { + const struct NvKmsKapiHeadRequestedConfig *headRequestedConfig = + &requestedConfig->headRequestedConfig[pFlipHead[i].head]; - struct NvKmsFlipReplyOneSubDevice *sdReplyParams = ¶ms->reply.sd[i]; + struct NvKmsKapiHeadReplyConfig *headReplyConfig = + &replyConfig->headReplyConfig[pFlipHead[i].head]; - NvU32 head; + const struct NvKmsKapiHeadModeSetConfig *headModeSetConfig = + &headRequestedConfig->modeSetConfig; - if ((device->subDeviceMask & (1 << i)) == 0x0) { + struct NvKmsFlipCommonReplyOneHead *flipParams = ¶ms->reply.flipHead[i]; + + NvU32 layer; + + if (!IsHeadConfigValid(params, requestedConfig, headModeSetConfig, pFlipHead[i].head)) { continue; - } + } - for (head = 0; - head < ARRAY_LEN(requestedConfig->headRequestedConfig); - head++) { + for (layer = 0; + layer < ARRAY_LEN(headRequestedConfig->layerRequestedConfig); + layer++) { - const struct NvKmsKapiHeadRequestedConfig *headRequestedConfig = - &requestedConfig->headRequestedConfig[head]; + const struct NvKmsKapiLayerConfig *layerRequestedConfig = + &headRequestedConfig->layerRequestedConfig[layer].config; - struct NvKmsKapiHeadReplyConfig *headReplyConfig = - &replyConfig->headReplyConfig[head]; + struct NvKmsKapiLayerReplyConfig *layerReplyConfig = + &headReplyConfig->layerReplyConfig[layer]; - const struct NvKmsKapiHeadModeSetConfig *headModeSetConfig = - &headRequestedConfig->modeSetConfig; - - struct NvKmsFlipCommonReplyOneHead *flipParams = &sdReplyParams->head[head]; - - NvU32 layer; - - if (!IsHeadConfigValid(params, requestedConfig, headModeSetConfig, head)) { - continue; - } - - for (layer = 0; - layer < ARRAY_LEN(headRequestedConfig->layerRequestedConfig); - layer++) { - - const struct NvKmsKapiLayerConfig *layerRequestedConfig = - &headRequestedConfig->layerRequestedConfig[layer].config; - - struct NvKmsKapiLayerReplyConfig *layerReplyConfig = - &headReplyConfig->layerReplyConfig[layer]; - - /*! initialize explicitly to -1 as 0 is valid file descriptor */ - layerReplyConfig->postSyncptFd = -1; - if (layerRequestedConfig->syncptParams.postSyncptRequested) { - layerReplyConfig->postSyncptFd = - flipParams->layer[layer].postSyncpt.u.fd; - } + /*! initialize explicitly to -1 as 0 is valid file descriptor */ + layerReplyConfig->postSyncptFd = -1; + if (layerRequestedConfig->syncptParams.postSyncptRequested) { + layerReplyConfig->postSyncptFd = + flipParams->layer[layer].postSyncpt.u.fd; } } } @@ -3030,25 +3024,11 @@ static NvBool ApplyModeSetConfig( const struct NvKmsKapiHeadModeSetConfig *headModeSetConfig = &headRequestedConfig->modeSetConfig; - const struct NvKmsKapiLayerRequestedConfig *primaryLayerRequestedConfig = - &headRequestedConfig->layerRequestedConfig[NVKMS_KAPI_LAYER_PRIMARY_IDX]; - if ((requestedConfig->headsMask & (1 << head)) == 0x0) { continue; } - /* - * Source width/height of primary layer represents width/height of - * ViewPortIn. Destination X, Y, width and height of primary layer - * represents dimensions of ViewPortOut. To apply changes in - * width/height of ViewPortIn and/or changes dimensions of - * ViewPortOut requires full modeset. - */ - bRequiredModeset = - primaryLayerRequestedConfig->flags.srcWHChanged || - primaryLayerRequestedConfig->flags.dstXYChanged || - primaryLayerRequestedConfig->flags.dstWHChanged || headRequestedConfig->flags.activeChanged || headRequestedConfig->flags.displaysChanged || headRequestedConfig->flags.modeChanged; diff --git a/src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h b/src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h index 8036811f9..000600bde 100644 --- a/src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h +++ b/src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h @@ -43,14 +43,9 @@ enum NvKmsSyncPtOp { NVKMS_SYNCPT_OP_ALLOC, NVKMS_SYNCPT_OP_GET, NVKMS_SYNCPT_OP_PUT, - NVKMS_SYNCPT_OP_INCR_MAX, - NVKMS_SYNCPT_OP_CPU_INCR, NVKMS_SYNCPT_OP_FD_TO_ID_AND_THRESH, NVKMS_SYNCPT_OP_ID_AND_THRESH_TO_FD, NVKMS_SYNCPT_OP_READ_MINVAL, - NVKMS_SYNCPT_OP_READ_MAXVAL, - NVKMS_SYNCPT_OP_SET_MIN_EQ_MAX, - NVKMS_SYNCPT_OP_SET_MAXVAL, }; typedef struct { @@ -60,24 +55,10 @@ typedef struct { NvU32 id; /* out */ } alloc; - struct { - NvU32 id; /* in */ - } get; - struct { NvU32 id; /* in */ } put; - struct { - NvU32 id; /* in */ - NvU32 incr; /* in */ - NvU32 value; /* out */ - } incr_max; - - struct { - NvU32 id; /* in */ - } cpu_incr; - struct { NvS32 fd; /* in */ NvU32 id; /* out */ @@ -94,20 +75,6 @@ typedef struct { NvU32 id; /* in */ NvU32 minval; /* out */ } read_minval; - - struct { - NvU32 id; /* in */ - NvU32 maxval; /* out */ - } read_maxval; - - struct { - NvU32 id; /* in */ - } set_min_eq_max; - - struct { - NvU32 id; /* in */ - NvU32 val; /* in */ - } set_maxval; } NvKmsSyncPtOpParams; NvBool nvkms_output_rounding_fix(void); diff --git a/src/nvidia-modeset/os-interface/include/nvkms.h b/src/nvidia-modeset/os-interface/include/nvkms.h index 1276186ce..e770341b8 100644 --- a/src/nvidia-modeset/os-interface/include/nvkms.h +++ b/src/nvidia-modeset/os-interface/include/nvkms.h @@ -42,6 +42,20 @@ typedef void nvkms_procfs_proc_t(void *data, char *buffer, size_t size, nvkms_procfs_out_string_func_t *outString); +/* max number of loops to prevent hanging the kernel if an edge case is hit */ +#define NVKMS_READ_FILE_MAX_LOOPS 1000 +/* max size for any file read by the config system */ +#define NVKMS_READ_FILE_MAX_SIZE 8192 + +/* + * The read file callback should allocate a buffer pointed to by *buff, fill it + * with the contents of fname, and return the size of the buffer. Buffer is not + * guaranteed to be null-terminated. The caller is responsible for freeing the + * buffer with nvkms_free, not nvFree. + */ +typedef size_t nvkms_config_read_file_func_t(char *fname, + char ** const buff); + typedef struct { const char *name; nvkms_procfs_proc_t *func; @@ -74,6 +88,9 @@ void nvKmsResume(NvU32 gpuId); void nvKmsGetProcFiles(const nvkms_procfs_file_t **ppProcFiles); +NvBool nvKmsReadConf(const char *buff, size_t size, + nvkms_config_read_file_func_t readfile); + void nvKmsKapiHandleEventQueueChange ( struct NvKmsKapiDevice *device diff --git a/src/nvidia-modeset/src/dp/nvdp-connector.cpp b/src/nvidia-modeset/src/dp/nvdp-connector.cpp index ef6a55e80..31744bf93 100644 --- a/src/nvidia-modeset/src/dp/nvdp-connector.cpp +++ b/src/nvidia-modeset/src/dp/nvdp-connector.cpp @@ -30,7 +30,6 @@ #include "nvkms-evo.h" #include "nvkms-types.h" #include "nvkms-modeset.h" -#include "nvkms-modeset-types.h" #include "nvkms-utils.h" #include "nvkms-rmapi.h" @@ -199,67 +198,30 @@ static DisplayPort::Group* CreateGroup( return pGroup; } -/*! - * Returns the bits per pixel for the pixel depth value given - * - * \param[in] pixelDepth nvKmsPixelDepth value - * - * \return The pixel depth configured by this enum value - */ -static NvU32 GetSORBpp( - const enum nvKmsPixelDepth pixelDepth, - const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace) +static NvU32 GetColorDepth( + const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, + const enum NvKmsDpyAttributeColorBpcValue colorBpc) { - NvU32 bpc = nvPixelDepthToBitsPerComponent(pixelDepth); - if (bpc == 0) { - nvAssert(!"Unrecognized SOR pixel depth"); - /* XXX Assume lowest ? */ - bpc = 6; + switch (colorSpace) { + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420: + /* + * In YUV420, HW is programmed with RGB color space and full color + * range. The color space conversion and color range compression + * happen in a headSurface composite shader. + */ + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444: + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB: + /* + * For RGB/YCbCr444, each pixel is always 3 components. For + * YCbCr/YUV420, we currently always scan out from the headSurface + * as RGB. + */ + return colorBpc * 3; + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422: + return colorBpc * 2; } - /* - * In YUV420, HW is programmed with RGB color space and full color range. - * The color space conversion and color range compression happen in a - * headSurface composite shader. - * - * XXX Add support for - * NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422 over DP. - */ - nvAssert(colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420 || - colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444 || - colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB); - - /* For RGB/YCbCr444, each pixel is always 3 components. For YCbCr/YUV420, - * we currently always scan out from the headSurface as RGB. */ - return bpc * 3; -} - -/* XXX Instead of tracking pixelDepth, you should track bpc and calculate bpp - * from bpc + colorSpace. */ -static NvU32 GetBpc( - const enum nvKmsPixelDepth pixelDepth, - const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace) -{ - NvU32 bpc = nvPixelDepthToBitsPerComponent(pixelDepth); - if (bpc == 0) { - nvAssert(!"Unrecognized SOR pixel depth"); - /* XXX Assume lowest ? */ - return 6; - } - - /* - * In YUV420, HW is programmed with RGB color space and full color range. - * The color space conversion and color range compression happen in a - * headSurface composite shader. - * - * XXX Add support for - * NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422 over DP. - */ - nvAssert(colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420 || - colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444 || - colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB); - - return bpc; + return 0; } static void SetDPMSATiming(const NVDispEvoRec *pDispEvo, @@ -302,6 +264,7 @@ static void InitDpModesetParams( const NvU32 displayId, const NVHwModeTimingsEvo *pTimings, const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, + const enum NvKmsDpyAttributeColorBpcValue colorBpc, DisplayPort::DpModesetParams *pParams) { pParams->modesetInfo.pixelClockHz = pTimings->pixelClock * 1000; @@ -313,10 +276,8 @@ static void InitDpModesetParams( pParams->modesetInfo.surfaceHeight = nvEvoVisibleHeight(pTimings); pParams->modesetInfo.depth = - GetSORBpp(pTimings->pixelDepth, colorSpace); - - pParams->modesetInfo.bitsPerComponent = - GetBpc(pTimings->pixelDepth, colorSpace); + GetColorDepth(colorSpace, colorBpc); + pParams->modesetInfo.bitsPerComponent = colorBpc; pParams->colorFormat = dpColorFormat_Unknown; switch (colorSpace) { @@ -333,7 +294,6 @@ static void InitDpModesetParams( pParams->colorFormat = dpColorFormat_YCbCr422; break; case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB: - case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_BT2020RGB: pParams->colorFormat = dpColorFormat_RGB; break; } @@ -349,6 +309,7 @@ NVDPLibModesetStatePtr nvDPLibCreateModesetState( const NvU32 displayId, const NVDpyIdList dpyIdList, const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, + const enum NvKmsDpyAttributeColorBpcValue colorBpc, NVHwModeTimingsEvo *pTimings) { bool found = false; @@ -382,6 +343,7 @@ NVDPLibModesetStatePtr nvDPLibCreateModesetState( displayId, pTimings, colorSpace, + colorBpc, &pDpLibModesetState->modesetParams); if (pTimings->dpDsc.enable) { pDpLibModesetState->modesetParams.modesetInfo.bEnableDsc = true; @@ -421,6 +383,7 @@ NvBool nvDPLibValidateTimings( const NvU32 displayId, const NVDpyIdList dpyIdList, const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, + const enum NvKmsDpyAttributeColorBpcValue colorBpc, const struct NvKmsModeValidationParams *pModeValidationParams, NVHwModeTimingsEvo *pTimings) { @@ -474,6 +437,7 @@ NvBool nvDPLibValidateTimings( displayId, pTimings, colorSpace, + colorBpc, pModesetParams); dpDscParams.bCheckWithDsc = true; @@ -532,6 +496,7 @@ NvBool nvDPEndValidation(NVDispEvoPtr pDispEvo) NvBool nvDPValidateModeForDpyEvo( const NVDpyEvoRec *pDpyEvo, const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, + const enum NvKmsDpyAttributeColorBpcValue colorBpc, const struct NvKmsModeValidationParams *pModeValidationParams, NVHwModeTimingsEvo *pTimings) { @@ -548,6 +513,7 @@ NvBool nvDPValidateModeForDpyEvo( 0 /* displayId */, nvAddDpyIdToEmptyDpyIdList(pDpyEvo->id), colorSpace, + colorBpc, pModeValidationParams, pTimings); connector->endCompoundQuery(); @@ -913,13 +879,17 @@ void nvDPSetAllowMultiStreamingOneConnector( } static NvBool IsDpSinkMstCapableForceSst(const NVDispEvoRec *pDispEvo, - const NvU32 head) + const NvU32 apiHead) { - const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; - const NVConnectorEvoRec *pConnectorEvo = pHeadState->pConnectorEvo; + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); + const NVConnectorEvoRec *pConnectorEvo = (pDpyEvo != NULL) ? + pDpyEvo->pConnectorEvo : NULL; - if (pConnectorEvo == NULL || - pConnectorEvo->pDpLibConnector == NULL) { + if ((pConnectorEvo == NULL) || + (pConnectorEvo->pDpLibConnector == NULL)) { return FALSE; } @@ -931,11 +901,15 @@ static NvBool IsDpSinkMstCapableForceSst(const NVDispEvoRec *pDispEvo, static NvBool IsDpLinkTransitionWaitingForHeadShutDown( const NVDispEvoRec *pDispEvo, - const NvU32 head) + const NvU32 apiHead) { - const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; - return pHeadState->pConnectorEvo && - nvDPIsLinkAwaitingTransition(pHeadState->pConnectorEvo); + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); + + return (pDpyEvo != NULL) && + nvDPIsLinkAwaitingTransition(pDpyEvo->pConnectorEvo); } void nvDPSetAllowMultiStreaming(NVDevEvoPtr pDevEvo, NvBool allowMST) @@ -962,7 +936,7 @@ void nvDPSetAllowMultiStreaming(NVDevEvoPtr pDevEvo, NvBool allowMST) return; } - nvShutDownHeads(pDevEvo, IsDpSinkMstCapableForceSst); + nvShutDownApiHeads(pDevEvo, IsDpSinkMstCapableForceSst); /* * Heads driving MST capable sinks in force SST mode, are shut down. Now you @@ -987,8 +961,8 @@ void nvDPSetAllowMultiStreaming(NVDevEvoPtr pDevEvo, NvBool allowMST) } /* Shut down all DisplayPort heads that need to transition to/from SST. */ - nvShutDownHeads(pDevEvo, - IsDpLinkTransitionWaitingForHeadShutDown); + nvShutDownApiHeads(pDevEvo, + IsDpLinkTransitionWaitingForHeadShutDown); /* * Handle any pending timers the DP library scheduled to notify us diff --git a/src/nvidia-modeset/src/nvkms-3dvision.c b/src/nvidia-modeset/src/nvkms-3dvision.c index d38a184b7..499148ecd 100644 --- a/src/nvidia-modeset/src/nvkms-3dvision.c +++ b/src/nvidia-modeset/src/nvkms-3dvision.c @@ -24,7 +24,7 @@ #include "nvkms-types.h" #include "nvkms-3dvision.h" -void nv3DVisionAuthenticationEvo(NVDispEvoRec *pDispEvo, const NvU32 head) +void nv3DVisionAuthenticationEvo(NVDispEvoRec *pDispEvo, const NvU32 apiHead) { return; } @@ -47,7 +47,7 @@ void nvDisable3DVisionAegis(const NVDpyEvoRec *pDpyEvo) } void nvSendHwModeTimingsToAegisEvo(const NVDispEvoRec *pDispEvo, - const NvU32 head) + const NvU32 apiHead) { return; } diff --git a/src/nvidia-modeset/src/nvkms-attributes.c b/src/nvidia-modeset/src/nvkms-attributes.c index 666fd9df8..827560348 100644 --- a/src/nvidia-modeset/src/nvkms-attributes.c +++ b/src/nvidia-modeset/src/nvkms-attributes.c @@ -31,6 +31,7 @@ #include "nvkms-rmapi.h" #include "nvos.h" #include "nvkms-stereo.h" +#include "nvkms-hdmi.h" #include // NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_* @@ -196,6 +197,14 @@ static NvBool GetHead(const NVDpyEvoRec *pDpyEvo, NvS64 *pHead) return TRUE; } +static NvBool GetHwHead(const NVDpyEvoRec *pDpyEvo, NvS64 *pHead) +{ + NvU32 primaryHwHead = + nvGetPrimaryHwHead(pDpyEvo->pDispEvo, pDpyEvo->apiHead); + *pHead = (NvS64)primaryHwHead; + return TRUE; +} + static NvBool DitherConfigurationAllowed(const NVDpyEvoRec *pDpyEvo) { NVDispEvoPtr pDispEvo = pDpyEvo->pDispEvo; @@ -210,7 +219,6 @@ static void SetDitheringCommon(NVDpyEvoPtr pDpyEvo) const NVConnectorEvoRec *pConnectorEvo = pDpyEvo->pConnectorEvo; NVDispEvoRec *pDispEvo = pConnectorEvo->pDispEvo; NVDispApiHeadStateEvoRec *pApiHeadState; - enum nvKmsPixelDepth pixelDepth; NvU32 head; if (pDpyEvo->apiHead == NV_INVALID_HEAD) { @@ -221,16 +229,8 @@ static void SetDitheringCommon(NVDpyEvoPtr pDpyEvo) nvAssert((pApiHeadState->hwHeadsMask) != 0x0 && (nvDpyIdIsInDpyIdList(pDpyEvo->id, pApiHeadState->activeDpys))); - head = nvGetPrimaryHwHead(pDispEvo, pDpyEvo->apiHead); - pixelDepth = pDispEvo->headState[head].timings.pixelDepth; -#if defined(DEBUG) - FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { - nvAssert(pixelDepth == pDispEvo->headState[head].timings.pixelDepth); - } -#endif - nvChooseDitheringEvo(pConnectorEvo, - pixelDepth, + pApiHeadState->attributes.colorBpc, &pDpyEvo->requestedDithering, &pApiHeadState->attributes.dithering); @@ -613,10 +613,12 @@ static NvBool ColorSpaceAndRangeAvailable(const NVDpyEvoRec *pDpyEvo) */ static void DpyPostColorSpaceOrRangeSetEvo(NVDpyEvoPtr pDpyEvo) { + enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace; + enum NvKmsDpyAttributeColorBpcValue colorBpc; + enum NvKmsDpyAttributeColorRangeValue colorRange; NVEvoUpdateState updateState = { }; NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo; NVDispApiHeadStateEvoRec *pApiHeadState; - enum nvKmsPixelDepth pixelDepth; enum NvYuv420Mode yuv420Mode; enum NvKmsOutputTf tf; NvU32 head; @@ -630,13 +632,12 @@ static void DpyPostColorSpaceOrRangeSetEvo(NVDpyEvoPtr pDpyEvo) (nvDpyIdIsInDpyIdList(pDpyEvo->id, pApiHeadState->activeDpys))); head = nvGetPrimaryHwHead(pDispEvo, pDpyEvo->apiHead); - pixelDepth = pDispEvo->headState[head].timings.pixelDepth; yuv420Mode = pDispEvo->headState[head].timings.yuv420Mode; tf = pDispEvo->headState[head].tf; #if defined(DEBUG) FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { - nvAssert(pixelDepth == pDispEvo->headState[head].timings.pixelDepth); nvAssert(yuv420Mode == pDispEvo->headState[head].timings.yuv420Mode); + nvAssert(tf == pDispEvo->headState[head].tf); } #endif @@ -644,21 +645,45 @@ static void DpyPostColorSpaceOrRangeSetEvo(NVDpyEvoPtr pDpyEvo) * Choose current colorSpace and colorRange based on the current mode * timings and the requested color space and range. */ - nvChooseCurrentColorSpaceAndRangeEvo(pixelDepth, - yuv420Mode, - tf, - pDpyEvo->requestedColorSpace, - pDpyEvo->requestedColorRange, - &pApiHeadState->attributes.colorSpace, - &pApiHeadState->attributes.colorRange); + if (!nvChooseCurrentColorSpaceAndRangeEvo(pDpyEvo, + yuv420Mode, + tf, + pDpyEvo->requestedColorSpace, + pDpyEvo->requestedColorRange, + &colorSpace, + &colorBpc, + &colorRange)) { + nvAssert(!"Failed to choose current color space and color range"); + return; + } + + /* For DP, neither color space nor bpc can be changed without a modeset */ + if (nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo) && + ((pApiHeadState->attributes.colorSpace != colorSpace) || + (pApiHeadState->attributes.colorBpc != colorBpc))) { + return; + } + + pApiHeadState->attributes.colorSpace = colorSpace; + pApiHeadState->attributes.colorRange = colorRange; + pApiHeadState->attributes.colorBpc = colorBpc; /* Update hardware's current colorSpace and colorRange */ FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + enum nvKmsPixelDepth newPixelDepth = + nvEvoColorSpaceBpcToPixelDepth(pApiHeadState->attributes.colorSpace, + pApiHeadState->attributes.colorBpc); + nvUpdateCurrentHardwareColorSpaceAndRangeEvo(pDispEvo, head, pApiHeadState->attributes.colorSpace, pApiHeadState->attributes.colorRange, &updateState); + + if (newPixelDepth != pDispEvo->headState[head].pixelDepth) { + pDispEvo->headState[head].pixelDepth = newPixelDepth; + nvEvoHeadSetControlOR(pDispEvo, head, &updateState); + } } /* Update InfoFrames as needed. */ @@ -672,15 +697,18 @@ static void DpyPostColorSpaceOrRangeSetEvo(NVDpyEvoPtr pDpyEvo) static NvU32 DpyGetValidColorSpaces(const NVDpyEvoRec *pDpyEvo) { + const NVDevEvoRec *pDevEvo = pDpyEvo->pDispEvo->pDevEvo; NvU32 val = (1 << NV_KMS_DPY_ATTRIBUTE_REQUESTED_COLOR_SPACE_RGB); - if (pDpyEvo->pConnectorEvo->colorSpaceCaps.ycbcr422Capable && - pDpyEvo->colorSpaceCaps.ycbcr422Capable) { + if ((nvDpyIsHdmiEvo(pDpyEvo) && + (pDevEvo->caps.hdmiYCbCr422MaxBpc != 0)) || + (nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo) && + (pDevEvo->caps.dpYCbCr422MaxBpc != 0))) { val |= (1 << NV_KMS_DPY_ATTRIBUTE_REQUESTED_COLOR_SPACE_YCbCr422); } - if (pDpyEvo->pConnectorEvo->colorSpaceCaps.ycbcr444Capable && - pDpyEvo->colorSpaceCaps.ycbcr444Capable) { + if (nvDpyIsHdmiEvo(pDpyEvo) || + nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo)) { val |= (1 << NV_KMS_DPY_ATTRIBUTE_REQUESTED_COLOR_SPACE_YCbCr444); } @@ -1093,6 +1121,12 @@ static const struct { .getValidValues = NULL, .type = NV_KMS_ATTRIBUTE_TYPE_INTEGER, }, + [NV_KMS_DPY_ATTRIBUTE_HW_HEAD] = { + .set = NULL, + .get = GetHwHead, + .getValidValues = NULL, + .type = NV_KMS_ATTRIBUTE_TYPE_INTEGER, + }, [NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING] = { .set = SetDithering, .get = GetDithering, diff --git a/src/nvidia-modeset/src/nvkms-conf.c b/src/nvidia-modeset/src/nvkms-conf.c new file mode 100644 index 000000000..c6117e88b --- /dev/null +++ b/src/nvidia-modeset/src/nvkms-conf.c @@ -0,0 +1,599 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvkms-utils.h" +#include "nvkms-dpy-override.h" + +static NvBool CharIsSpace(char c) +{ + return (c == ' ' || /* space */ + c == '\f' || /* form feed */ + c == '\n' || /* line feed */ + c == '\r' || /* carriage return */ + c == '\t' || /* horizontal tab */ + c == '\v'); /* vertical tab */ +} + +/* Display Override Conf File Initialization */ +static inline NvU8 AsciiHexCharToNibble(char hex) +{ + if (hex >= '0' && hex <= '9') { + return hex - '0'; + } else if (hex >= 'A' && hex <= 'F') { + return hex - 'A' + 0xA; + } else if (hex >= 'a' && hex <= 'f') { + return hex - 'a' + 0xA; + } else { + return 0xFF; + } +} + +/* bin should be able to hold at least (size / 2) bytes */ +static size_t AsciiHexToBin(char *bin, const char *hex, size_t size) +{ + size_t hi, bi; + NvBool highNibble = TRUE; + NvU8 upnib = 0; + + if (hex == NULL || bin == NULL) { + return 0; + } + if (bin >= hex && bin <= hex + size) { + /* + * Although, theoretically, decoding ascii hex in place should work + * fine - each set of 2 characters encodes 1 byte - it's best to avoid + * the complexity + */ + nvAssert(!"ASCII hex would be decoded in place."); + return 0; + } + + for(hi = 0, bi = 0; hi < size; hi++) { + NvU8 nibble; + + if (CharIsSpace(hex[hi])) { + continue; + } + + nibble = AsciiHexCharToNibble(hex[hi]); + if (nibble > 0xF) { + return 0; /* invalid character */ + } + + if (highNibble) { + upnib = nibble << 4; + } else { + bin[bi++] = upnib | nibble; + } + highNibble = !highNibble; + } + + if (!highNibble) { + return 0; /* odd number of hex chars */ + } + + return bi; +} + +#define SUBPARSER(name) static NvBool Subparser_ ## name( \ + const char *key, \ + const char *value, \ + nvkms_config_read_file_func_t readfile) + +SUBPARSER(override) +{ + size_t i; + size_t idLen = 0; + size_t valLen = nvkms_strlen(value); + + NvU32 gpuId = NV0000_CTRL_GPU_INVALID_ID; + const char *name = NULL; + + static nv_gpu_info_t devs[NV_MAX_GPUS]; + NvU32 numdevs = nvkms_enumerate_gpus(devs); + + if (key[0] == '[') { + while (key[idLen] != 0 && key[idLen] != ']') { + idLen++; + } + } + + while (key[idLen] != 0 && key[idLen] != '.') { + idLen++; + } + + /* Get the GPU ID */ + if (key[0] == '[') { + /* GPU PCI Address */ + NvU32 domain = 0xFFFFFFFF, temp = 0; + NvU8 bus = 0xFF, slot = 0xFF, function = 0xFF; + size_t j; + + for (i = 1, j = 0; (key[i] != 0) && (key[i] != ']') && (j < 4); i++) { + if (key[i] == ':') { + if (j == 0) { + domain = temp; + } else if (j == 1) { + bus = (NvU8)temp; + } else { + break; + } + j++; + temp = 0; + } else if (key[i] == '.') { + if (j == 2) { + slot = (NvU8)temp; + } else { + break; + } + j++; + temp = 0; + } else { + NvU8 nibble = AsciiHexCharToNibble(key[i]); + if (nibble > 0xF) { + break; + } + temp <<= 4; + temp |= nibble; + } + } + + if (j == 3) { + function = (NvU8)temp; + j++; + } + + if (j != 4) { + nvEvoLog(EVO_LOG_WARN, "Syntax error in override entry: " + "Error reading PCI Address: %.*s " + "(%zu fields read)", (int)idLen, key, j); + nvClearDpyOverrides(); + return FALSE; + } + + for (size_t i = 0; i < numdevs; i++) { + if (devs[i].pci_info.domain == domain && + devs[i].pci_info.bus == bus && + devs[i].pci_info.slot == slot && + devs[i].pci_info.function == function) { + + gpuId = devs[i].gpu_id; + break; + } + } + if (gpuId == NV0000_CTRL_GPU_INVALID_ID) { + nvEvoLog(EVO_LOG_WARN, "Error in override entry: " + "No GPU with PCI Address %04x:%02hhx:%02hhx.%hhx", + domain, bus, slot, function); + nvClearDpyOverrides(); + return FALSE; + } + } else if (idLen == 5 && nvkms_memcmp(key, "tegra", 5) == 0){ + gpuId = NVKMS_DEVICE_ID_TEGRA; + } else { + nvEvoLog(EVO_LOG_WARN, "Syntax error in override entry: " + "Unknown GPU designator: %.*s", (int)idLen, key); + return FALSE; + } + + /* Get the dpy name */ + if (key[idLen] != '.' || key[idLen + 1] == 0) { + nvEvoLog(EVO_LOG_WARN, "Syntax error in override entry: " + "Expected '.' followed by display name"); + return FALSE; + } + name = key + (idLen + 1); + + /* Get the edid */ + if (value[0] == '"' && value[valLen - 1] == '"') { + valLen -= 2; + value += 1; + } + + if (value[0] == '/') { + size_t bufflen = 0; + char *buff = NULL; + + if (readfile != NULL) { + char *fname = nvCalloc(valLen + 1, 1); + nvkms_memcpy(fname, value, valLen); + bufflen = readfile(fname, &buff); + nvFree(fname); + } + + if (bufflen == 0) { + nvEvoLog(EVO_LOG_WARN, "Error in override entry: " + "Error opening EDID file: %.*s", (int)valLen, value); + nvClearDpyOverrides(); + return FALSE; + } + + nvCreateDpyOverride(gpuId, name, TRUE, buff, bufflen); + nvkms_free(buff, bufflen); + } else if (valLen == 12 && nvkms_memcmp(value, "disconnected", 12) == 0) { + nvCreateDpyOverride(gpuId, name, FALSE, NULL, 0); + } else { + char *edidBuf = nvCalloc(valLen / 2, 1); + size_t decoded = AsciiHexToBin(edidBuf, value, valLen); + if (decoded == 0) { + nvEvoLog(EVO_LOG_WARN, "Error in override entry: " + "Error decoding ASCII hex: %.*s\n", (int)valLen, value); + nvFree(edidBuf); + nvClearDpyOverrides(); + return FALSE; + } + + nvCreateDpyOverride(gpuId, name, TRUE, edidBuf, decoded); + nvFree(edidBuf); + } + + return TRUE; +} + +#undef SUBPARSER + +static NvBool Subparse( + const char *keyhead, + const char *keytail, + const char *value, + nvkms_config_read_file_func_t readfile) +{ +#define SUBPARSE(name) if (nvkms_strcmp(keyhead, #name) == 0) { \ + return Subparser_ ## name(keytail, value, readfile); \ +} + SUBPARSE(override); + nvEvoLog(EVO_LOG_WARN, "Error reading configuration file: " + "Parser not found for key: %s.%s", keyhead, keytail); + return FALSE; +#undef SUBPARSE +} + +#define ST_KEYHEAD 0 /* read head of key */ +#define ST_KEYTAIL 1 /* read tail of key */ +#define ST_VALUE 2 /* read value of key */ +#define ST_EQUALS 3 /* expect '=' */ +#define ST_SEND 4 /* send values */ + +/* + * This function implements a state machine: + * KEYHEAD -> KEYTAIL : when a '.' is read + * KEYHEAD -> EQUALS : when whitespace is read + * KEYHEAD -> VALUE : when '=' is read + * KEYTAIL -> EQUALS : when whitespace is read + * KEYTAIL -> VALUE : when '=' is read + * EQUALS -> VALUE : when '=' is read + * VALUE -> SEND : when whitespace is read + * SEND -> KEYHEAD : consumes no input but sends strings to further parser functions + * + * Here, whitespace means any block of one or more whitespace characters, as + * determined by the CharIsSpace() helper function. Whitespace only causes state + * transitions if at least one non-whitespace character has been read in that + * state + * + * When a '#' is read, all input is consumed until a '\n' is read or the end of + * the buffer is reached. This input is treated as whitespace for the purposes + * of the above state transitions and is considered part of any surrounding + * whitespace + * + * When a '"', '(', '{', '[', or '<' is read while in KEYHEAD, KEYTAIL, or VALUE, + * a substate is entered which consumes all input until a corresponding '"', ')', + * '}', ']', or '>' is read. While in this substate, '.', whitespace, '=', and '#' + * do not cause state transitions. + * + * While in KEYHEAD, KEYTAIL, or VALUE, all consumed input which does not cause + * state transitions are added to the corresponding string to be passed to + * further parser functions. + * + * NOTE: buff is not guaranteed to be NULL-terminated + */ +NvBool nvKmsReadConf( + const char *buff, + size_t size, + nvkms_config_read_file_func_t readfile) +{ + size_t i; + NvBool ret = FALSE; /* set false until success noted */ + + int state = ST_KEYHEAD; /* state machine's current state */ + char watchfor = 0; /* marker for paired char blocks */ + const char *ptr = NULL; /* pointer into buffer */ + char *strs[3] = { NULL, NULL, NULL }; /* alloced strings to be copied to */ + size_t lens[3] = { 0, 0, 0 }; /* lengths of strings in strs */ + + /* named pointers into strs */ + char ** const keyhead = &strs[ST_KEYHEAD]; + char ** const keytail = &strs[ST_KEYTAIL]; + char ** const value = &strs[ST_VALUE]; + + /* verify that there's always a string allocated in each of the slots */ + for (i = 0; i < 3; ++i) { + strs[i] = nvCalloc(1, 1); + if (strs[i] == NULL) { + nvEvoLog(EVO_LOG_WARN, "Error reading configuration file: " + "Out of memory"); + goto teardown; + } + lens[i] = 1; + } + +#define COPYPTR() do { \ + size_t strlen; \ + nvAssert(ptr != NULL); \ + nvAssert(state == ST_KEYHEAD || state == ST_KEYTAIL || state == ST_VALUE); \ + strlen = (buff + i) - ptr; \ + if (lens[state] < strlen + 1) { \ + /* allocate strlen + 1 to ensure a null terminator */ \ + nvFree(strs[state]); \ + strs[state] = nvCalloc(strlen + 1, 1); \ + if (strs[state] == NULL) { \ + nvEvoLog(EVO_LOG_WARN, "Error reading configuration file: " \ + "Out of memory"); \ + goto teardown; \ + } \ + lens[state] = strlen + 1; \ + } \ + nvkms_memcpy(strs[state], ptr, strlen); \ + strs[state][strlen] = 0; \ + ptr = NULL; \ +} while (0) + + for (i = 0; i < size; i++) { + /* + * If watchfor is set, then either we're in a comment or we're in a + * paired block. If we're in a comment (watchfor == '\n'), then we + * want ptr to be NULL, so that the comment isn't included in content. + * If we're not in a comment (watchfor == '"', ')', '}', ']', or '>'), + * we want ptr to be non-NULL, so that the paired block is included in + * the content. + */ + nvAssert(watchfor == 0 || + (watchfor != '\n' && ptr != NULL) || + (watchfor == '\n' && ptr == NULL)); + + if (state == ST_KEYHEAD) { + if (watchfor == 0) { + if (buff[i] == '.') { + if (ptr == NULL) { + nvEvoLog(EVO_LOG_WARN, "Syntax error in configuration file: " + "'.' at start of key"); + goto teardown; + } + + COPYPTR(); + state = ST_KEYTAIL; + } else if (buff[i] == '=') { + if (ptr == NULL) { + nvEvoLog(EVO_LOG_WARN, "Syntax error in configuration file: " + "key expected before '='"); + goto teardown; + } + + COPYPTR(); + state = ST_VALUE; + } else if (buff[i] == '"') { + if (ptr == NULL) { + ptr = buff + i; + } + watchfor = '"'; + } else if (buff[i] == '(') { + if (ptr == NULL) { + ptr = buff + i; + } + watchfor = ')'; + } else if (buff[i] == '{') { + if (ptr == NULL) { + ptr = buff + i; + } + watchfor = '}'; + } else if (buff[i] == '[') { + if (ptr == NULL) { + ptr = buff + i; + } + watchfor = ']'; + } else if (buff[i] == '<') { + if (ptr == NULL) { + ptr = buff + i; + } + watchfor = '>'; + } else if (buff[i] == '#') { + if (ptr != NULL) { + COPYPTR(); + state = ST_EQUALS; + } + watchfor = '\n'; + } else if (CharIsSpace(buff[i])) { + if (ptr != NULL) { + COPYPTR(); + state = ST_EQUALS; + } + } else if (ptr == NULL) { + ptr = buff + i; + } + } else if (buff[i] == watchfor) { + watchfor = 0; + } + } else if (state == ST_KEYTAIL) { + if (watchfor == 0) { + if (buff[i] == '=') { + if (ptr == NULL) { + nvEvoLog(EVO_LOG_WARN, "Syntax error in configuration file: " + "identifier expected after '.' in \"%s\" key", + *keyhead); + goto teardown; + } + + COPYPTR(); + state = ST_VALUE; + } else if (buff[i] == '"') { + if (ptr == NULL) { + ptr = buff + i; + } + watchfor = '"'; + } else if (buff[i] == '(') { + if (ptr == NULL) { + ptr = buff + i; + } + watchfor = ')'; + } else if (buff[i] == '{') { + if (ptr == NULL) { + ptr = buff + i; + } + watchfor = '}'; + } else if (buff[i] == '[') { + if (ptr == NULL) { + ptr = buff + i; + } + watchfor = ']'; + } else if (buff[i] == '<') { + if (ptr == NULL) { + ptr = buff + i; + } + watchfor = '>'; + } else if (buff[i] == '#') { + if (ptr != NULL) { + COPYPTR(); + state = ST_EQUALS; + } + watchfor = '\n'; + } else if (CharIsSpace(buff[i])) { + if (ptr != NULL) { + COPYPTR(); + state = ST_EQUALS; + } + } else if (ptr == NULL) { + ptr = buff + i; + } + } else if (buff[i] == watchfor) { + watchfor = 0; + } + } else if (state == ST_EQUALS) { + nvAssert(ptr == NULL); + /* watchfor should only ever be set if we're in a comment */ + nvAssert(watchfor == 0 || watchfor == '\n'); + + if (watchfor == 0) { + if (buff[i] == '=') { + state = ST_VALUE; + } else if (buff[i] == '#') { + watchfor = '\n'; + } else if (!CharIsSpace(buff[i])) { + nvEvoLog(EVO_LOG_WARN, "Syntax error in configuration file: " + "expected '=' before value"); + goto teardown; + } + } else if (buff[i] == watchfor) { + watchfor = 0; + } + + } else if (state == ST_VALUE) { + if (watchfor == 0) { + if (buff[i] == '=') { + nvEvoLog(EVO_LOG_WARN, "Syntax error in configuration file: " + "unexpected '=' in value"); + goto teardown; + } else if (buff[i] == '"') { + if (ptr == NULL) { + ptr = buff + i; + } + watchfor = '"'; + } else if (buff[i] == '(') { + if (ptr == NULL) { + ptr = buff + i; + } + watchfor = ')'; + } else if (buff[i] == '{') { + if (ptr == NULL) { + ptr = buff + i; + } + watchfor = '}'; + } else if (buff[i] == '[') { + if (ptr == NULL) { + ptr = buff + i; + } + watchfor = ']'; + } else if (buff[i] == '<') { + if (ptr == NULL) { + ptr = buff + i; + } + watchfor = '>'; + } else if (buff[i] == '#') { + if (ptr != NULL) { + COPYPTR(); + state = ST_SEND; + } + watchfor = '\n'; + } else if (CharIsSpace(buff[i])) { + if (ptr != NULL) { + COPYPTR(); + state = ST_SEND; + } + } else if (ptr == NULL) { + ptr = buff + i; + } + } else if (buff[i] == watchfor) { + watchfor = 0; + } + } else if (state == ST_SEND) { + if (!Subparse(*keyhead, *keytail, *value, readfile)) { + goto teardown; + } + state = ST_KEYHEAD; + (*keyhead)[0] = 0; + (*keytail)[0] = 0; + (*value)[0] = 0; + i--; /* don't consume input */ + } else { + nvAssert(!"Invalid state!"); + } + } + + if (state == ST_SEND) { + if (!Subparse(*keyhead, *keytail, *value, readfile)) { + goto teardown; + } + } else if ((state != ST_KEYHEAD) || (ptr != NULL)) { + /* + * if state is KEYHEAD and ptr is NULL, then we've just got trailing + * whitespace or comments, which is valid syntax + */ + nvEvoLog(EVO_LOG_WARN, "Syntax error in configuration file: " + "trailing input after last key-value pair"); + goto teardown; + } + + ret = TRUE; + + /* fallthrough */ +teardown: + for (i = 0; i < 3; i++) { + nvFree(strs[i]); + } + return ret; +#undef COPYPTR +} + +#undef ST_KEYHEAD +#undef ST_KEYTAIL +#undef ST_VALUE +#undef ST_EQUALS +#undef ST_SEND diff --git a/src/nvidia-modeset/src/nvkms-console-restore.c b/src/nvidia-modeset/src/nvkms-console-restore.c index e49a1db9b..9d2069988 100644 --- a/src/nvidia-modeset/src/nvkms-console-restore.c +++ b/src/nvidia-modeset/src/nvkms-console-restore.c @@ -114,74 +114,93 @@ static NVDpyIdList UpdateConnectedDpys(NVDispEvoPtr pDispEvo) static void FlipBaseToNull(NVDevEvoPtr pDevEvo) { - struct NvKmsFlipParams *pParams = nvCalloc(1, sizeof(*pParams)); - struct NvKmsFlipRequest *pRequest; + struct NvKmsFlipRequestOneHead *pFlipApiHead = NULL; + NvU32 numFlipApiHeads = 0, i; NvU32 sd; NVDispEvoPtr pDispEvo; NvBool ret = TRUE; - if (!pParams) { + /* First count the number of active heads. */ + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + NvU32 apiHead; + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { + continue; + } + numFlipApiHeads++; + } + } + + if (numFlipApiHeads == 0) { + // If no heads require changes, there's nothing to do. + return; + } + + /* Allocate an array of head structures */ + pFlipApiHead = nvCalloc(numFlipApiHeads, sizeof(pFlipApiHead[0])); + + if (!pFlipApiHead) { nvEvoLogDevDebug(pDevEvo, EVO_LOG_WARN, "Failed to allocate flip parameters for console restore base flip " "to NULL"); return; } - pRequest = &pParams->request; - + i = 0; FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - struct NvKmsFlipRequestOneSubDevice *pRequestSd = - &pRequest->sd[sd]; - NvU32 head; - for (head = 0; head < pDevEvo->numHeads; head++) { - struct NvKmsFlipCommonParams *pRequestHead = - &pRequestSd->head[head]; + NvU32 apiHead; + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + struct NvKmsFlipCommonParams *pRequestApiHead = NULL; NvU32 layer; - if (!nvHeadIsActive(pDispEvo, head)) { + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { continue; } - pRequestSd->requestedHeadsBitMask |= NVBIT(head); + pFlipApiHead[i].sd = sd; + pFlipApiHead[i].head = apiHead; + pRequestApiHead = &pFlipApiHead[i].flip; + i++; + nvAssert(i <= numFlipApiHeads); - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - pRequestHead->layer[layer].surface.specified = TRUE; + for (layer = 0; layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { + pRequestApiHead->layer[layer].surface.specified = TRUE; // No need to specify sizeIn/sizeOut as we are flipping NULL surface. - pRequestHead->layer[layer].compositionParams.specified = TRUE; - pRequestHead->layer[layer].completionNotifier.specified = TRUE; - pRequestHead->layer[layer].syncObjects.specified = TRUE; + pRequestApiHead->layer[layer].compositionParams.specified = TRUE; + pRequestApiHead->layer[layer].completionNotifier.specified = TRUE; + pRequestApiHead->layer[layer].syncObjects.specified = TRUE; // Disable HDR - pRequestHead->tf.val = NVKMS_OUTPUT_TF_NONE; - pRequestHead->tf.specified = TRUE; - pRequestHead->layer[layer].hdr.enabled = FALSE; - pRequestHead->layer[layer].hdr.specified = TRUE; - pRequestHead->layer[layer].colorspace.val = + pRequestApiHead->tf.val = NVKMS_OUTPUT_TF_NONE; + pRequestApiHead->tf.specified = TRUE; + pRequestApiHead->layer[layer].hdr.enabled = FALSE; + pRequestApiHead->layer[layer].hdr.specified = TRUE; + pRequestApiHead->layer[layer].colorspace.val = NVKMS_INPUT_COLORSPACE_NONE; - pRequestHead->layer[layer].colorspace.specified = TRUE; + pRequestApiHead->layer[layer].colorspace.specified = TRUE; } - - pRequest->commit = TRUE; } } - // If no heads require changes, there's nothing to do. - if (pRequest->commit) { - ret = nvFlipEvo(pDevEvo, pDevEvo->pNvKmsOpenDev, pRequest, - &pParams->reply, FALSE /* skipUpdate */, - FALSE /* allowFlipLock */); - } - nvFree(pParams); + ret = nvFlipEvo(pDevEvo, pDevEvo->pNvKmsOpenDev, + pFlipApiHead, + numFlipApiHeads, + TRUE /* commit */, + FALSE /* allowVrr */, + NULL /* pReply */, + FALSE /* skipUpdate */, + FALSE /* allowFlipLock */); + nvFree(pFlipApiHead); if (!ret) { nvAssert(!"Console restore failed to flip base to NULL"); } FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - NvU32 head; - for (head = 0; head < pDevEvo->numHeads; head++) { + NvU32 apiHead; + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { NvBool stoppedBase; - ret = nvRMIdleBaseChannel(pDevEvo, head, sd, &stoppedBase); + ret = nvIdleBaseChannelOneApiHead(pDispEvo, apiHead, &stoppedBase); if (!ret) { nvAssert(!"Console restore failed to idle base"); } @@ -189,13 +208,55 @@ static void FlipBaseToNull(NVDevEvoPtr pDevEvo) } } +/*! + * Return the mask of active api heads on this pDispEvo. + */ +static NvU32 GetActiveApiHeadMask(NVDispEvoPtr pDispEvo) +{ + NvU32 apiHead; + NvU32 apiHeadMask = 0; + + for (apiHead = 0; apiHead < NVKMS_MAX_HEADS_PER_DISP; apiHead++) { + if (nvApiHeadIsActive(pDispEvo, apiHead)) { + apiHeadMask |= 1 << apiHead; + } + } + + return apiHeadMask; +} + +static NvU32 PickApiHead(const NVDpyEvoRec *pDpyEvo, + const NvU32 availableApiHeadsMask) +{ + const NvU32 possibleApiHeads = availableApiHeadsMask & + pDpyEvo->pConnectorEvo->validApiHeadMask; + const NvU32 activeApiHeadsMask = + GetActiveApiHeadMask(pDpyEvo->pDispEvo); + + if (possibleApiHeads == 0) { + return NV_INVALID_HEAD; + } + + if ((pDpyEvo->apiHead != NV_INVALID_HEAD) && + ((NVBIT(pDpyEvo->apiHead) & possibleApiHeads) != 0x0)) { + return pDpyEvo->apiHead; + } + + if ((possibleApiHeads & ~activeApiHeadsMask) != 0x0) { + return BIT_IDX_32(LOWESTBIT(possibleApiHeads & + ~activeApiHeadsMask)); + } + + return BIT_IDX_32(LOWESTBIT(possibleApiHeads)); +} + static NvBool InitModeOneHeadRequest( NVDpyEvoRec *pDpyEvo, NVSurfaceEvoPtr pSurfaceEvo, const struct NvKmsMode *pOverrideMode, const struct NvKmsSize *pOverrideViewPortSizeIn, const struct NvKmsPoint *pOverrideViewPortPointIn, - const NvU32 head, + const NvU32 apiHead, struct NvKmsSetModeOneHeadRequest *pRequestHead) { @@ -242,7 +303,7 @@ static NvBool InitModeOneHeadRequest( pFlip->layer[NVKMS_MAIN_LAYER].sizeIn.val; /* Disable other layers except Main */ - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + for (layer = 0; layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { if (layer == NVKMS_MAIN_LAYER) { pFlip->layer[layer].csc.matrix = NVKMS_IDENTITY_CSC_MATRIX; @@ -272,24 +333,21 @@ ConstructModeOneHeadRequestForOneDpy(NVDpyEvoRec *pDpyEvo, NVSurfaceEvoPtr pSurfaceEvo, struct NvKmsSetModeParams *pParams, const NvU32 dispIndex, - NvU32 *pAvailableHeadsMask) + NvU32 *pAvailableApiHeadsMask) { NvBool ret = FALSE; - const NvU32 possibleHeads = *pAvailableHeadsMask & - pDpyEvo->pConnectorEvo->validHeadMask; + const NvU32 apiHead = PickApiHead(pDpyEvo, *pAvailableApiHeadsMask); - if (possibleHeads == 0 || pDpyEvo->isVrHmd) { + if ((apiHead == NV_INVALID_HEAD) || pDpyEvo->isVrHmd) { goto done; } - const NvU32 head = BIT_IDX_32(LOWESTBIT(possibleHeads)); - NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo; struct NvKmsSetModeRequest *pRequest = &pParams->request; struct NvKmsSetModeOneDispRequest *pRequestDisp = &pRequest->disp[dispIndex]; struct NvKmsSetModeOneHeadRequest *pRequestHead = - &pRequestDisp->head[head]; + &pRequestDisp->head[apiHead]; NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; @@ -298,7 +356,7 @@ ConstructModeOneHeadRequestForOneDpy(NVDpyEvoRec *pDpyEvo, NULL /* Use default Mode */, NULL /* Use default ViewPortSizeIn */, NULL /* Use default ViewPortPointIn */, - head, + apiHead, pRequestHead)) { goto done; } @@ -331,7 +389,7 @@ ConstructModeOneHeadRequestForOneDpy(NVDpyEvoRec *pDpyEvo, pRequestHead->viewPortOutSpecified = TRUE; } - *pAvailableHeadsMask &= ~NVBIT(head); + *pAvailableApiHeadsMask &= ~NVBIT(apiHead); ret = TRUE; @@ -492,7 +550,7 @@ ConstructModeRequestForTiledDisplay(const NVDispEvoRec *pDispEvo, struct NvKmsSetModeParams *pParams, const NvU32 dispIndex, NVDpyIdList tiledDisplayDpysList, - NvU32 *pAvailableHeadsMask) + NvU32 *pAvailableApiHeadsMask) { NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; /* @@ -516,16 +574,16 @@ ConstructModeRequestForTiledDisplay(const NVDispEvoRec *pDispEvo, struct NvKmsSetModeRequest *pRequest = &pParams->request; struct NvKmsSetModeOneDispRequest *pRequestDisp = &pRequest->disp[dispIndex]; - NvU32 firstClaimedHead = NV_INVALID_HEAD; - NvU32 claimedHeadMask = 0x0; + NvU32 firstClaimedApiHead = NV_INVALID_HEAD; + NvU32 claimedApiHeadMask = 0x0; NVDpyEvoRec *pDpyEvo; - NvU32 head; + NvU32 apiHead; /* * Return failure if not enough number of heads available to construct * modeset request for Tiled-Display. */ - if (nvPopCount32(*pAvailableHeadsMask) < + if (nvPopCount32(*pAvailableApiHeadsMask) < nvCountDpyIdsInDpyIdList(tiledDisplayDpysList)) { return FALSE; } @@ -546,20 +604,20 @@ ConstructModeRequestForTiledDisplay(const NVDispEvoRec *pDispEvo, .x = pDpyDisplayIdInfo->tile_location.x * viewPortSizeIn.width, .y = pDpyDisplayIdInfo->tile_location.y * viewPortSizeIn.height }; - const NvU32 possibleHeads = *pAvailableHeadsMask & - pDpyEvo->pConnectorEvo->validHeadMask & - ~claimedHeadMask; + const NvU32 localAvailableApiHeadsMask = + *pAvailableApiHeadsMask & ~claimedApiHeadMask; + const NvU32 apiHead = PickApiHead(pDpyEvo, + localAvailableApiHeadsMask); - if (possibleHeads == 0 || pDpyEvo->isVrHmd) { + if ((apiHead == NV_INVALID_HEAD) || pDpyEvo->isVrHmd) { goto failed; } - const NvU32 head = BIT_IDX_32(LOWESTBIT(possibleHeads)); struct NvKmsSetModeOneHeadRequest *pRequestHead = - &pRequestDisp->head[head]; + &pRequestDisp->head[apiHead]; struct NvKmsMode mode; - if (firstClaimedHead == NV_INVALID_HEAD) { + if (firstClaimedApiHead == NV_INVALID_HEAD) { /* * Find mode of native dimensions reported in Tiled-Display * information. @@ -572,20 +630,20 @@ ConstructModeRequestForTiledDisplay(const NVDispEvoRec *pDispEvo, goto failed; } - firstClaimedHead = head; + firstClaimedApiHead = apiHead; } else { /* All tiles should support same set of modes */ - mode = pRequestDisp->head[firstClaimedHead].mode; + mode = pRequestDisp->head[firstClaimedApiHead].mode; } - claimedHeadMask |= NVBIT(head); + claimedApiHeadMask |= NVBIT(apiHead); if (!InitModeOneHeadRequest(pDpyEvo, pSurfaceEvo, &mode, &viewPortSizeIn, &viewPortPointIn, - head, + apiHead, pRequestHead)) { goto failed; } @@ -601,19 +659,19 @@ ConstructModeRequestForTiledDisplay(const NVDispEvoRec *pDispEvo, FALSE /* doRasterLock */)) { goto failed; } - *pAvailableHeadsMask &= ~claimedHeadMask; + *pAvailableApiHeadsMask &= ~claimedApiHeadMask; return TRUE; failed: - for (head = 0; head < ARRAY_LEN(pRequestDisp->head); head++) { - if ((NVBIT(head) & claimedHeadMask) == 0x0) { + for (apiHead = 0; apiHead < ARRAY_LEN(pRequestDisp->head); apiHead++) { + if ((NVBIT(apiHead) & claimedApiHeadMask) == 0x0) { continue; } - nvkms_memset(&pRequestDisp->head[head], + nvkms_memset(&pRequestDisp->head[apiHead], 0, - sizeof(pRequestDisp->head[head])); + sizeof(pRequestDisp->head[apiHead])); } return FALSE; @@ -625,12 +683,15 @@ static NvBool isDpMSTModeActiveOnAnyConnector(NVDevEvoPtr pDevEvo) NVDispEvoPtr pDispEvo; FOR_ALL_EVO_DISPLAYS(pDispEvo, i, pDevEvo) { - NvU32 head; + NvU32 apiHead; - for (head = 0; head < pDevEvo->numHeads; head++) { - const NVDispHeadStateEvoRec *pHeadState = - &pDispEvo->headState[head]; - const NVConnectorEvoRec *pConnectorEvo = pHeadState->pConnectorEvo; + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); + const NVConnectorEvoRec *pConnectorEvo = (pDpyEvo != NULL) ? + pDpyEvo->pConnectorEvo : NULL; if ((pConnectorEvo != NULL) && nvConnectorUsesDPLib(pConnectorEvo)) { @@ -655,12 +716,14 @@ static NvBool isDpMSTModeActiveOnAnyConnector(NVDevEvoPtr pDevEvo) * If a framebuffer console surface was successfully imported from RM, then use * the core channel to set a mode that displays it. * - * Enables as many heads as possible in a clone configuration. In first pass - * for connected boot dpys and in second pass for other remaining dpys: + * This enables as many heads as possible in a clone configuration. + * In the first pass we select connected active dpys, in the second pass + * any other connected boot dpys, and in a third pass any other + * remaining connected dpys: * - * 1. Populate modeset request to enable given dpy. + * 1. Populate modeset request to enable the given dpy. * - * 2. Do modeset request validation, if fails then disable scaling. If + * 2. Do modeset request validation, if it fails then disable scaling. If * modeset request validation fails even after disabling scaling then do not * enable that dpy. * @@ -724,13 +787,17 @@ NvBool nvEvoRestoreConsole(NVDevEvoPtr pDevEvo, const NvBool allowMST) // Construct the request. // // To start with, try to enable as many connected dpys as possible, - // preferring boot displays first. + // preferring the connected active displays first. struct NvKmsSetModeRequest *pRequest = ¶ms->request; NvBool foundDpysConfigForConsoleRestore = FALSE; FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - NvU32 availableHeadsMask = NVBIT(pDevEvo->numHeads) - 1; + NvU32 availableApiHeadsMask = NVBIT(pDevEvo->numApiHeads) - 1; NVDpyIdList connectedDpys = UpdateConnectedDpys(pDispEvo); + const NVDpyIdList activeDpys = nvActiveDpysOnDispEvo(pDispEvo); + const NVDpyIdList connectedActiveDpys = + nvIntersectDpyIdListAndDpyIdList(connectedDpys, + activeDpys); const NVDpyIdList connectedBootDpys = nvIntersectDpyIdListAndDpyIdList(connectedDpys, pDispEvo->bootDisplays); @@ -739,7 +806,7 @@ NvBool nvEvoRestoreConsole(NVDevEvoPtr pDevEvo, const NvBool allowMST) int pass; pRequest->requestedDispsBitMask |= NVBIT(dispIndex); - pRequestDisp->requestedHeadsBitMask = availableHeadsMask; + pRequestDisp->requestedHeadsBitMask = availableApiHeadsMask; // Only enable heads on the subdevice that actually contains the // console. @@ -749,19 +816,24 @@ NvBool nvEvoRestoreConsole(NVDevEvoPtr pDevEvo, const NvBool allowMST) NVDpyIdList handledDpysList = nvEmptyDpyIdList(); - for (pass = 0; pass < 2; pass++) { + for (pass = 0; pass < 3; pass++) { NVDpyIdList candidateDpys; NVDpyEvoPtr pDpyEvo; - if (availableHeadsMask == 0) { + if (availableApiHeadsMask == 0) { break; } if (pass == 0) { - candidateDpys = connectedBootDpys; - } else { + candidateDpys = connectedActiveDpys; + } else if (pass == 1) { + candidateDpys = nvDpyIdListMinusDpyIdList(connectedBootDpys, + connectedActiveDpys); + } else if (pass == 2) { candidateDpys = nvDpyIdListMinusDpyIdList(connectedDpys, connectedBootDpys); + candidateDpys = nvDpyIdListMinusDpyIdList(candidateDpys, + connectedActiveDpys); } FOR_ALL_EVO_DPYS(pDpyEvo, candidateDpys, pDispEvo) { @@ -773,7 +845,7 @@ NvBool nvEvoRestoreConsole(NVDevEvoPtr pDevEvo, const NvBool allowMST) &pDpyEvo->parsedEdid.info.ext_displayid : NULL; NvBool done = FALSE; - if (availableHeadsMask == 0) { + if (availableApiHeadsMask == 0) { break; } @@ -807,7 +879,7 @@ NvBool nvEvoRestoreConsole(NVDevEvoPtr pDevEvo, const NvBool allowMST) params, dispIndex, tiledDisplayInfo.detectedDpysList, - &availableHeadsMask); + &availableApiHeadsMask); isTiledDisplayEnable = done; } @@ -828,7 +900,7 @@ NvBool nvEvoRestoreConsole(NVDevEvoPtr pDevEvo, const NvBool allowMST) pSurfaceEvo, params, dispIndex, - &availableHeadsMask); + &availableApiHeadsMask); isTiledDisplayEnable = done && tiledDisplayInfo.isCapToScaleSingleTile; } @@ -875,7 +947,7 @@ done: /* If console restore failed then simply shut down all heads */ if (!ret) { - nvShutDownHeads(pDevEvo, NULL /* pTestFunc, shut down all heads */); + nvShutDownApiHeads(pDevEvo, NULL /* pTestFunc, shut down all heads */); } // If restoring the console from here succeeded, then skip triggering RM's diff --git a/src/nvidia-modeset/src/nvkms-cursor.c b/src/nvidia-modeset/src/nvkms-cursor.c index 30467d681..edc1f49da 100644 --- a/src/nvidia-modeset/src/nvkms-cursor.c +++ b/src/nvidia-modeset/src/nvkms-cursor.c @@ -89,13 +89,13 @@ NvBool nvGetCursorImageSurfaces( } static void -SetCursorImage(NVDispEvoPtr pDispEvo, - const NvU32 head, - NVSurfaceEvoRec *pSurfaceEvoNew, - const struct NvKmsCompositionParams *pCursorCompParams) +SetCursorImageOneHead(NVDispEvoPtr pDispEvo, + const NvU32 head, + NVSurfaceEvoRec *pSurfaceEvoNew, + const struct NvKmsCompositionParams *pCursorCompParams, + NVEvoUpdateState *pUpdateState) { NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - NVEvoUpdateState updateState = { }; const NvU32 sd = pDispEvo->displayOwner; NvBool changed = FALSE; @@ -131,51 +131,79 @@ SetCursorImage(NVDispEvoPtr pDispEvo, pDevEvo, head, pDevEvo->gpus[sd].headState[head].cursor.pSurfaceEvo, - &updateState, + pUpdateState, &pDevEvo->gpus[sd].headState[head].cursor.cursorCompParams); - nvEvoUpdateAndKickOff(pDispEvo, FALSE, &updateState, - TRUE /* releaseElv */); nvPopEvoSubDevMask(pDevEvo); } +} - if (pSurfaceEvoNew) { - nvTriggerVrrUnstallSetCursorImage(pDispEvo, changed); +static void +SetCursorImage(NVDispEvoPtr pDispEvo, + const NvU32 apiHead, + NVSurfaceEvoRec *pSurfaceEvoNew, + const struct NvKmsCompositionParams *pCursorCompParams) +{ + NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + NvU32 head; + NVEvoUpdateState updateState = { }; + NvBool changed = FALSE; + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + SetCursorImageOneHead(pDispEvo, + head, + pSurfaceEvoNew, + pCursorCompParams, + &updateState); } + + if (!nvIsUpdateStateEmpty(pDevEvo, &updateState)) { + nvEvoUpdateAndKickOff(pDispEvo, FALSE, &updateState, + TRUE /* releaseElv */); + changed = TRUE; + } + + /* + * Unconditionally trigger an unstall: even if the cursor image or + * composition didn't change, clients setting the cursor image would expect + * a VRR unstall. Also, if the cursor changed from an image to no image + * (i.e., hiding the cursor), that should trigger a VRR unstall, too. + */ + nvTriggerVrrUnstallSetCursorImage(pDispEvo, changed); } static NvBool FlipCursorImage(NVDispEvoPtr pDispEvo, const struct NvKmsPerOpenDev *pOpenDevice, - NvU32 head, + NvU32 apiHead, const struct NvKmsSetCursorImageCommonParams *pImageParams) { const NvU32 sd = pDispEvo->displayOwner; NvBool ret; - struct NvKmsFlipParams *pFlipParams; - struct NvKmsFlipRequest *pFlipRequest; + struct NvKmsFlipRequestOneHead *pFlipHead = + nvCalloc(1, sizeof(*pFlipHead)); - pFlipParams = nvCalloc(1, sizeof(*pFlipParams)); - if (pFlipParams == NULL) { + if (pFlipHead == NULL) { return FALSE; } - pFlipRequest = &pFlipParams->request; - - pFlipRequest->sd[sd].head[head].cursor.image = *pImageParams; - pFlipRequest->sd[sd].head[head].cursor.imageSpecified = TRUE; - - pFlipRequest->sd[sd].requestedHeadsBitMask = NVBIT(head); - - pFlipRequest->commit = TRUE; + pFlipHead->sd = sd; + pFlipHead->head = apiHead; + pFlipHead->flip.cursor.image = *pImageParams; + pFlipHead->flip.cursor.imageSpecified = TRUE; ret = nvFlipEvo(pDispEvo->pDevEvo, pOpenDevice, - pFlipRequest, - &pFlipParams->reply, + pFlipHead, + 1 /* numFlipHeads */, + TRUE /* commit */, + FALSE /* allowVrr */, + NULL /* pReply */, FALSE /* skipUpdate */, FALSE /* allowFlipLock */); - nvFree(pFlipParams); + nvFree(pFlipHead); return ret; } @@ -184,7 +212,7 @@ NvBool nvSetCursorImage( NVDispEvoPtr pDispEvo, const struct NvKmsPerOpenDev *pOpenDevice, const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, - NvU32 head, + NvU32 apiHead, const struct NvKmsSetCursorImageCommonParams *pParams) { NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; @@ -206,25 +234,32 @@ NvBool nvSetCursorImage( pDevEvo->capsBits, NV5070_CTRL_SYSTEM_CAPS_BUG_2052012_GLITCHY_MCLK_SWITCH)) { const NvU32 sd = pDispEvo->displayOwner; + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + NvU32 head; - NVSurfaceEvoPtr pSurfaceEvoOld = - pDevEvo->gpus[sd].headState[head].cursor.pSurfaceEvo; + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + NVSurfaceEvoPtr pSurfaceEvoOld = + pDevEvo->gpus[sd].headState[head].cursor.pSurfaceEvo; - if ((pSurfaceEvoOld != pSurfaceEvoNew) && - (pSurfaceEvoOld == NULL || pSurfaceEvoNew == NULL)) { - flipCursorImage = TRUE; + if ((pSurfaceEvoOld != pSurfaceEvoNew) && + (pSurfaceEvoOld == NULL || pSurfaceEvoNew == NULL)) { + flipCursorImage = TRUE; + break; + } } } if (flipCursorImage) { return FlipCursorImage(pDispEvo, - pOpenDevice, head, pParams); + pOpenDevice, apiHead, pParams); } SetCursorImage(pDispEvo, - head, + apiHead, pSurfaceEvoNew, &pParams->cursorCompParams); + return TRUE; } @@ -244,19 +279,27 @@ void nvEvoMoveCursorInternal(NVDispEvoPtr pDispEvo, } } -void nvEvoMoveCursor(NVDispEvoPtr pDispEvo, NvU32 head, - const struct NvKmsMoveCursorCommonParams *pParams) +void nvMoveCursor(NVDispEvoPtr pDispEvo, const NvU32 apiHead, + const struct NvKmsMoveCursorCommonParams *pParams) { NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - const NvU32 sd = pDispEvo->displayOwner; + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + NvU32 head; /* XXX NVKMS TODO: validate x,y against current viewport in? */ - pDevEvo->gpus[sd].headState[head].cursor.x = pParams->x; - pDevEvo->gpus[sd].headState[head].cursor.y = pParams->y; + nvAssert(apiHead != NV_INVALID_HEAD); - nvEvoMoveCursorInternal(pDispEvo, - head, pParams->x, pParams->y); + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + const NvU32 sd = pDispEvo->displayOwner; + + pDevEvo->gpus[sd].headState[head].cursor.x = pParams->x; + pDevEvo->gpus[sd].headState[head].cursor.y = pParams->y; + + nvEvoMoveCursorInternal(pDispEvo, + head, pParams->x, pParams->y); + } } // Allocate and map cursor position PIO channels diff --git a/src/nvidia-modeset/src/nvkms-difr.c b/src/nvidia-modeset/src/nvkms-difr.c index 216c05b38..100d0cc3b 100644 --- a/src/nvidia-modeset/src/nvkms-difr.c +++ b/src/nvidia-modeset/src/nvkms-difr.c @@ -145,13 +145,32 @@ typedef struct _NVDIFRStateEvoRec { NvU32 prefetchPass; } NVDIFRStateEvoRec; +/* + * Prefetch parameters for DMA copy. + */ +typedef struct { + NvUPtr surfGpuAddress; + size_t surfSizeBytes; + enum NvKmsSurfaceMemoryFormat surfFormat; + NvU32 surfPitchBytes; +} NVDIFRPrefetchParams; + static NvBool AllocDIFRPushChannel(NVDIFRStateEvoPtr pDifr); static void FreeDIFRPushChannel(NVDIFRStateEvoPtr pDifr); static NvBool AllocDIFRCopyEngine(NVDIFRStateEvoPtr pDifr); static void FreeDIFRCopyEngine(NVDIFRStateEvoPtr pDifr); + static NvU32 PrefetchSingleSurface(NVDIFRStateEvoPtr pDifr, - NVSurfaceEvoPtr pSurfaceEvo, + NVDIFRPrefetchParams *pParams, size_t *remainingCache); +static NvBool PrefetchHelperSurfaceEvo(NVDIFRStateEvoPtr pDifr, + size_t *cacheRemaining, + NVSurfaceEvoPtr pSurfaceEvo, + NvU32 *status); +static NvBool PrefetchHelperLutSurface(NVDIFRStateEvoPtr pDifr, + size_t *cacheRemaining, + NVLutSurfaceEvoPtr pLutSurface, + NvU32 *status); static NvBool SetDisabledState(NVDIFRStateEvoPtr pDifr, NvBool shouldDisable); @@ -247,11 +266,12 @@ NvU32 nvDIFRPrefetchSurfaces(NVDIFRStateEvoPtr pDifr, size_t l2CacheSize) NVDevEvoPtr pDevEvo = pDifr->pDevEvo; NVEvoSubDevPtr pSubDev; NVEvoSubDevHeadStatePtr pHeadState; - NVSurfaceEvoPtr pSurface; size_t cacheRemaining = l2CacheSize; NvU32 layer; NvU32 head; + NvU32 apiHead; NvU32 eye; + NvU32 i; NvU32 status; /* If DIFR is disabled it's because we know we were or will be flipping. */ @@ -266,45 +286,73 @@ NvU32 nvDIFRPrefetchSurfaces(NVDIFRStateEvoPtr pDifr, size_t l2CacheSize) /* Get new prefetch pass counter for this iteration. */ pDifr->prefetchPass++; + /* + * Start by prefetching the cursor surface and image surfaces from + * present layers. + */ for (head = 0; head < pDevEvo->numHeads; head++) { - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + pHeadState = &pSubDev->headState[head]; + + if (!PrefetchHelperSurfaceEvo(pDifr, + &cacheRemaining, + pHeadState->cursor.pSurfaceEvo, + &status)) { + goto out; + } + + for (layer = 0; layer <= pDevEvo->head[head].numLayers; layer++) { for (eye = 0; eye < NVKMS_MAX_EYES; eye++) { - NvU32 prefetchStatus; - pHeadState = &pSubDev->headState[head]; - pSurface = pHeadState->layer[layer].pSurfaceEvo[eye]; - - if (!pSurface) { - continue; + if (!PrefetchHelperSurfaceEvo(pDifr, + &cacheRemaining, + pHeadState->layer[layer].pSurfaceEvo[eye], + &status)) { + goto out; } + } - if (pSurface->noDisplayCaching) { - status = - NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_OS_FLIPS_ENABLED; - break; - } + /* + * Prefetch per-layer LUTs, if any, but skip null LUTs and + * duplicates already prefetched. + */ + if (!PrefetchHelperLutSurface(pDifr, + &cacheRemaining, + pHeadState->layer[layer].inputLut.pLutSurfaceEvo, + &status)) { + goto out; + } - /* - * If we see the same pSurface twice (UBB, multi-head X - * screens, etc) we only ever want to prefetch it once - * within a single nvDIFRPrefetchSurfaces() call. - */ - if (pSurface->difrLastPrefetchPass == pDifr->prefetchPass) { - continue; - } - - pSurface->difrLastPrefetchPass = pDifr->prefetchPass; - prefetchStatus = PrefetchSingleSurface(pDevEvo->pDifrState, - pSurface, - &cacheRemaining); - if (prefetchStatus != NV2080_CTRL_LPWR_DIFR_PREFETCH_SUCCESS) { - status = prefetchStatus; - break; - } + if (!PrefetchHelperLutSurface(pDifr, + &cacheRemaining, + pHeadState->layer[layer].tmoLut.pLutSurfaceEvo, + &status)) { + goto out; } } } + /* + * Finally prefetch the known main LUTs. + */ + if (!PrefetchHelperLutSurface(pDifr, + &cacheRemaining, + pDevEvo->lut.defaultLut, + &status)) { + goto out; + } + + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + for (i = 0; i < ARRAY_LEN(pDevEvo->lut.apiHead[apiHead].LUT); i++) { + if (!PrefetchHelperLutSurface(pDifr, + &cacheRemaining, + pDevEvo->lut.apiHead[apiHead].LUT[i], + &status)) { + goto out; + } + } + } + +out: return status; } @@ -429,7 +477,7 @@ static void FreeDIFRCopyEngine(NVDIFRStateEvoPtr pDifr) } static NvU32 PrefetchSingleSurface(NVDIFRStateEvoPtr pDifr, - NVSurfaceEvoPtr pSurfaceEvo, + NVDIFRPrefetchParams *pParams, size_t *cacheRemaining) { NvPushChannelPtr p = &pDifr->prefetchPushChannel; @@ -437,12 +485,10 @@ static NvU32 PrefetchSingleSurface(NVDIFRStateEvoPtr pDifr, NvGpuSemaphore *semaphore = (NvGpuSemaphore *) nvPushGetNotifierCpuAddress(p, 0, 0); const NvKmsSurfaceMemoryFormatInfo *finfo = - nvKmsGetSurfaceMemoryFormatInfo(pSurfaceEvo->format); + nvKmsGetSurfaceMemoryFormatInfo(pParams->surfFormat); NvU32 componentSizes; - NvU32 pitch; NvU32 line_length_in; NvU32 line_count; - size_t surfaceSize; NvU64 starttime; NvU64 endtime; @@ -487,37 +533,25 @@ static NvU32 PrefetchSingleSurface(NVDIFRStateEvoPtr pDifr, /* * Compute some dimensional values to obtain correct blob size for - * prefetching. + * prefetching. Use the given pitch and calculate the number of lines + * needed to cover the whole memory region. */ - pitch = pSurfaceEvo->planes[0].pitch; - line_length_in = pSurfaceEvo->widthInPixels; - line_count = pSurfaceEvo->heightInPixels; + nvAssert(pParams->surfPitchBytes % finfo->rgb.bytesPerPixel == 0); + line_length_in = pParams->surfPitchBytes / finfo->rgb.bytesPerPixel; - if (pSurfaceEvo->layout == NvKmsSurfaceMemoryLayoutBlockLinear) { - pitch *= NVKMS_BLOCK_LINEAR_GOB_WIDTH; - } - - surfaceSize = pitch * line_count; + nvAssert(pParams->surfSizeBytes % pParams->surfPitchBytes == 0); + line_count = pParams->surfSizeBytes / pParams->surfPitchBytes; /* * Greedy strategy: assume all surfaces will fit in the supplied L2 size but * the first one that doesn't will cause the prefetch request to fail. If we * run out of cache then DIFR will disable itself until the next modeset. */ - if (*cacheRemaining < surfaceSize) { + if (*cacheRemaining < pParams->surfSizeBytes) { return NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_INSUFFICIENT_L2_SIZE; } - /* - * TODO: we should probably round up to the nearest cacheline size or maybe - * up to pSurfaceEvo->planes[0].rmObjectSizeInBytes, if greater? - * - * Using the total size of the surface pixel data (in bytes) seems to work - * but surface allocations can be larger than that and I'm not sure if DIFR - * needs only surfaceSize bytes in the cache or if the h/w will end up - * reading some non-visible alignment/padding areas as well. - */ - *cacheRemaining -= surfaceSize; + *cacheRemaining -= pParams->surfSizeBytes; /* * Push buffer DMA copy and semaphore programming. @@ -534,18 +568,27 @@ static NvU32 PrefetchSingleSurface(NVDIFRStateEvoPtr pDifr, nvPushImmedVal(p, NVA06F_SUBCHANNEL_COPY_ENGINE, NVA0B5_SET_REMAP_CONST_A, 0); nvPushMethod(p, NVA06F_SUBCHANNEL_COPY_ENGINE, NVA0B5_OFFSET_IN_UPPER, 2); - nvPushSetMethodDataU64(p, pSurfaceEvo->gpuAddress); + nvPushSetMethodDataU64(p, pParams->surfGpuAddress); nvPushMethod(p, NVA06F_SUBCHANNEL_COPY_ENGINE, NVA0B5_OFFSET_OUT_UPPER, 2); - nvPushSetMethodDataU64(p, pSurfaceEvo->gpuAddress); + nvPushSetMethodDataU64(p, pParams->surfGpuAddress); + + /* + * We don't expect phenomally large pitches but the .mfs for DMA copy + * defines PitchIn/PitchOut to be of signed 32-bit type for all + * architectures so assert that the value will be what h/w understands. + */ + nvAssert(pParams->surfPitchBytes <= NV_S32_MAX); + nvPushMethod(p, NVA06F_SUBCHANNEL_COPY_ENGINE, NVA0B5_PITCH_IN, 1); - nvPushSetMethodData(p, pitch); + nvPushSetMethodData(p, pParams->surfPitchBytes); nvPushMethod(p, NVA06F_SUBCHANNEL_COPY_ENGINE, NVA0B5_PITCH_OUT, 1); - nvPushSetMethodData(p, pitch); + nvPushSetMethodData(p, pParams->surfPitchBytes); nvPushMethod(p, NVA06F_SUBCHANNEL_COPY_ENGINE, NVA0B5_LINE_LENGTH_IN, 1); nvPushSetMethodData(p, line_length_in); nvPushMethod(p, NVA06F_SUBCHANNEL_COPY_ENGINE, NVA0B5_LINE_COUNT, 1); nvPushSetMethodData(p, line_count); + nvAssert(pParams->surfPitchBytes * line_count == pParams->surfSizeBytes); nvPushMethod(p, NVA06F_SUBCHANNEL_COPY_ENGINE, NVA0B5_LAUNCH_DMA, 1); nvPushSetMethodData @@ -605,6 +648,88 @@ static NvU32 PrefetchSingleSurface(NVDIFRStateEvoPtr pDifr, return NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_CE_HW_ERROR; } +static NvBool PrefetchHelperSurfaceEvo(NVDIFRStateEvoPtr pDifr, + size_t *cacheRemaining, + NVSurfaceEvoPtr pSurfaceEvo, + NvU32 *status) +{ + NVDIFRPrefetchParams params; + + nvAssert(*status == NV2080_CTRL_LPWR_DIFR_PREFETCH_SUCCESS); + + if (!pSurfaceEvo) { + return TRUE; + } + + if (pSurfaceEvo->noDisplayCaching) { + *status = NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_OS_FLIPS_ENABLED; + return FALSE; + } + + /* + * If we see the same SurfaceEvo twice (UBB, multi-head X screens, etc) + * we only ever want to prefetch it once within a single + * nvDIFRPrefetchSurfaces() call. + */ + if (pSurfaceEvo->difrLastPrefetchPass == pDifr->prefetchPass) { + return TRUE; + } + + /* + * Update pass counter even if we fail later: we want to try each + * surface only once. + */ + pSurfaceEvo->difrLastPrefetchPass = pDifr->prefetchPass; + + /* Collect copy parameters and do the prefetch. */ + params.surfGpuAddress = pSurfaceEvo->gpuAddress; + params.surfSizeBytes = pSurfaceEvo->planes[0].rmObjectSizeInBytes; + params.surfPitchBytes = pSurfaceEvo->planes[0].pitch; + params.surfFormat = pSurfaceEvo->format; + + if (pSurfaceEvo->layout == NvKmsSurfaceMemoryLayoutBlockLinear) { + params.surfPitchBytes *= NVKMS_BLOCK_LINEAR_GOB_WIDTH; + } + + *status = PrefetchSingleSurface(pDifr, ¶ms, cacheRemaining); + + return *status == NV2080_CTRL_LPWR_DIFR_PREFETCH_SUCCESS; +} + +static NvBool PrefetchHelperLutSurface(NVDIFRStateEvoPtr pDifr, + size_t *cacheRemaining, + NVLutSurfaceEvoPtr pLutSurface, + NvU32 *status) +{ + NVDIFRPrefetchParams params; + + nvAssert(*status == NV2080_CTRL_LPWR_DIFR_PREFETCH_SUCCESS); + + if (!pLutSurface) { + return TRUE; + } + + /* + * LUTs are often shared so we only want to prefetch (or consider) each + * LUT at most once during the prefetch process. + */ + if (pLutSurface->difrLastPrefetchPass == pDifr->prefetchPass) { + return TRUE; + } + + pLutSurface->difrLastPrefetchPass = pDifr->prefetchPass; + + /* Collect copy parameters and do the prefetch. */ + params.surfGpuAddress = (NvUPtr)pLutSurface->gpuAddress; + params.surfSizeBytes = pLutSurface->size; + params.surfPitchBytes = pLutSurface->size; + params.surfFormat = NvKmsSurfaceMemoryFormatI8; + + *status = PrefetchSingleSurface(pDifr, ¶ms, cacheRemaining); + + return *status == NV2080_CTRL_LPWR_DIFR_PREFETCH_SUCCESS; +} + /* * Set DIFR disabled state in H/W. Return true if state was changed and it * was successfully signalled downstream. diff --git a/src/nvidia-modeset/src/nvkms-dpy-override.c b/src/nvidia-modeset/src/nvkms-dpy-override.c new file mode 100644 index 000000000..a98abf5b4 --- /dev/null +++ b/src/nvidia-modeset/src/nvkms-dpy-override.c @@ -0,0 +1,264 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "nvkms-utils.h" +#include "nvkms-dpy-override.h" + +#include "nv_list.h" + +static NVListRec dpyOverrideList = NV_LIST_INIT(&dpyOverrideList); + +#define FOR_ALL_DPY_OVERRIDES(_pDpyOverride) \ + nvListForEachEntry(_pDpyOverride, &dpyOverrideList, entry) +#define FOR_ALL_DPY_OVERRIDES_SAFE(_pDpyOverride, _next) \ + nvListForEachEntry_safe(_pDpyOverride, _next, &dpyOverrideList, entry) + +#define DPY_OVERRIDE_MATCHES(_pDpyOverride, _gpuId, _name) \ + ((_pDpyOverride->gpuId == _gpuId) && \ + !nvkms_strcmp(_pDpyOverride->name, _name)) + +static NvBool DpyOverrideReadEdid(NVDpyOverrideRec *dpy, + const char *buffer, + size_t size) +{ + if ((dpy->edid.length != size) || (dpy->edid.buffer == NULL)) { + NvU8 *newbuf = nvRealloc(dpy->edid.buffer, size); + if (newbuf == NULL) { + return FALSE; + } + dpy->edid.buffer = newbuf; + dpy->edid.length = size; + } + + nvkms_memcpy(dpy->edid.buffer, buffer, size); + return TRUE; +} + + +/* + * Creates a display override on the given GPU for the given display name. + * If the override already exists it will be overwritten. + * + * \param[in] gpuId The ID of the GPU on which to create the display + * override, as returned in nvkms_enumerate_gpus() + * \param[in] name The name of the display to override in + * PROTOCOL-Index format, e.g. HDMI-0. + * \param[in] edid A buffer containing EDID data for the override. + * \param[in] edidSize The size of the edid buffer. + * + * \return A pointer to the created or edited NVDpyOverrideRec, or NULL if + * creation failed. + */ +NVDpyOverrideRec *nvCreateDpyOverride(NvU32 gpuId, + const char *name, + NvBool connected, + const char *edid, + size_t edidSize) +{ + NVDpyOverridePtr pDpyOverride; + size_t namelen, cpsz; + NvBool found = FALSE; + + /* if such a display override already exists, let it be changed */ + FOR_ALL_DPY_OVERRIDES(pDpyOverride) { + if (DPY_OVERRIDE_MATCHES(pDpyOverride, gpuId, name)) { + + found = TRUE; + break; + } + } + + /* if such a display override doesn't exist, create a new one */ + if (!found) { + pDpyOverride = nvCalloc(1, sizeof(*pDpyOverride)); + if (pDpyOverride == NULL) { + nvEvoLog(EVO_LOG_WARN, "Failed allocating data for display override"); + return NULL; + } + + nvListAdd(&pDpyOverride->entry, &dpyOverrideList); + + namelen = nvkms_strlen(name); + cpsz = namelen > NVKMS_DPY_NAME_SIZE - 1 ? NVKMS_DPY_NAME_SIZE - 1 + : namelen; + + nvkms_memcpy(pDpyOverride->name, name, cpsz); + pDpyOverride->gpuId = gpuId; + } + + pDpyOverride->connected = connected; + if (connected && !DpyOverrideReadEdid(pDpyOverride, edid, edidSize)) { + nvEvoLog(EVO_LOG_WARN, "Failed reading EDID"); + nvListDel(&pDpyOverride->entry); + nvFree(pDpyOverride); + return NULL; + } + + return pDpyOverride; +} + +/* + * Deletes a display override on the given GPU for the given display name. + * + * \param[in] gpuId The ID of the GPU on which to delete the display + * override, as returned in nvkms_enumerate_gpus() + * \param[in] name The name of the display whose override to delete in + * PROTOCOL-Index format, e.g. HDMI-0. + */ +void nvDeleteDpyOverride(NvU32 gpuId, const char *name) +{ + NVDpyOverridePtr pDpyOverride; + + /* If such a display override already exists, delete it */ + FOR_ALL_DPY_OVERRIDES(pDpyOverride) { + if (DPY_OVERRIDE_MATCHES(pDpyOverride, gpuId, name)) { + + nvListDel(&pDpyOverride->entry); + nvFree(pDpyOverride); + return; /* This makes using nvListForEachEntry safe. */ + } + } +} + +/* + * Logs a list of currently active override names to pInfoStr for a given + * GPU. + * + * \param[in] gpuId The ID of the GPU whose overrides to print, as + * returned in nvkms_enumerate_gpus() + * \param[in] pInfoStr A pointer to the NVEvoInfoString to log to. + */ +void nvLogDpyOverrides(NvU32 gpuId, NVEvoInfoStringPtr pInfoStr) +{ + NVDpyOverridePtr pDpyOverride; + FOR_ALL_DPY_OVERRIDES(pDpyOverride) { + if (pDpyOverride->gpuId == gpuId) { + nvEvoLogInfoString(pInfoStr, "%s", pDpyOverride->name); + } + } +} + +/* + * Checks if there is a matching, valid, and enabled NVDpyOverrideRec for the + * pDpyEvo in the global display override list and returns it if it is found. + * O(N) in length of display override list + * + * \param[in] pDpyEvo The display to check for an override. + * + * \return The NVDpyOverrideRec override for the pDpyEvo, or NULL if it isn't + * found. + */ +NVDpyOverridePtr nvDpyEvoGetOverride(const NVDpyEvoRec *pDpyEvo) +{ + NVDevEvoPtr pDevEvo; + NVDispEvoPtr pDispEvo; + NVSubDeviceEvoPtr pSubDevice; + NVDpyOverridePtr it; + + if (pDpyEvo == NULL) { + return NULL; + } + + /* + * Don't override DP MST displays, because there could be multiple attached + * to the single connector, which would result in the number of displays + * this override creates being dependent on the number of plugged in + * displays, which seems incorrect for this feature + */ + if (nvDpyEvoIsDPMST(pDpyEvo)) { + return NULL; + } + pDispEvo = pDpyEvo->pDispEvo; + pDevEvo = pDispEvo->pDevEvo; + + pSubDevice = pDevEvo->pSubDevices[pDispEvo->displayOwner]; + + FOR_ALL_DPY_OVERRIDES(it) { + /* Ensure valid and enabled override */ + if ((it->edid.length == 0) || (it->edid.buffer == NULL)) { + continue; + } + + /* + * Both NVDpyOverrideRec.gpuId and NVSubDeviceEvoRec.gpuId ultimately + * derive from nvRmApiControl(NV2080_CTRL_CMD_GPU_GET_ID), so we can + * use them to match GPUs. Additionally, NVConnectorEvo.name is of the + * format TYPE-N, e.g. HDMI-0, but pDpyEvo.name may have additional + * qualifiers (e.g., an existing EDID-derived name). + */ + if (DPY_OVERRIDE_MATCHES(it, pSubDevice->gpuId, pDpyEvo->pConnectorEvo->name)) { + + nvEvoLogDebug(EVO_LOG_INFO, "NVDpyOverrideRec found: %s\n", + it->name); + return it; + } + } + + return NULL; +} + +/* + * Reads the EDID data from a given NVDpyOverrideRec into the buffer buff. + * Does not write to the buffer if the operation fails. + * + * \param[in] pDpyOverride The override from which to read the EDID data. + * \param[out] buff A pointer to a buffer into which to read + * the override's EDID data. + * \param[in] len The length of the buffer. + * + * \return The number of bytes written into the buffer, or 0 if the operation + * failed. + */ +size_t nvReadDpyOverrideEdid(const NVDpyOverrideRec *pDpyOverride, + NvU8 *buff, size_t len) +{ + if ((pDpyOverride == NULL) || + (buff == NULL) || + (pDpyOverride->edid.length == 0) || + (pDpyOverride->edid.length > len)) { + return 0; + } + + nvkms_memcpy(buff, pDpyOverride->edid.buffer, + pDpyOverride->edid.length); + return pDpyOverride->edid.length; +} + +/* + * Delete all display overrides. This should only ever be called during shutdown + * of NVKMS or to cleanup when display override initialization fails. + */ +void nvClearDpyOverrides(void) +{ + NVDpyOverridePtr pDpyOverride, tmp; + FOR_ALL_DPY_OVERRIDES_SAFE(pDpyOverride, tmp) { + nvListDel(&pDpyOverride->entry); + if (pDpyOverride->edid.buffer != NULL) { + nvFree(pDpyOverride->edid.buffer); + } + nvFree(pDpyOverride); + } + + nvAssert(nvListIsEmpty(&dpyOverrideList)); +} diff --git a/src/nvidia-modeset/src/nvkms-dpy.c b/src/nvidia-modeset/src/nvkms-dpy.c index f5ed6c704..e4f1b983d 100644 --- a/src/nvidia-modeset/src/nvkms-dpy.c +++ b/src/nvidia-modeset/src/nvkms-dpy.c @@ -26,6 +26,7 @@ #include "nvkms-evo.h" #include "nvkms-dpy.h" +#include "nvkms-dpy-override.h" #include "nvkms-hdmi.h" #include "nvkms-rm.h" #include "nvkms-rmapi.h" @@ -1379,6 +1380,12 @@ static void LogEdid(NVDpyEvoPtr pDpyEvo, NVEvoInfoStringPtr pInfoString) { NVT_TYPE_CUST_AUTO, "Customized Auto Timings" }, { NVT_TYPE_CUST_MANUAL, "Customized Manual Timings" }, { NVT_TYPE_CVT_RB_2,"Reduced Blanking Coordinated Video Timings, v2" }, + { NVT_TYPE_DMT_RB_2, "Display Monitor Timings, V2" }, + { NVT_TYPE_DISPLAYID_7, "DisplayID Type 7 Timings" }, + { NVT_TYPE_DISPLAYID_8, "DisplayID Type 8 Timings" }, + { NVT_TYPE_DISPLAYID_9, "DisplayID Type 9 Timings" }, + { NVT_TYPE_DISPLAYID_10, "DisplayID Type 10 Timings" }, + { NVT_TYPE_CVT_RB_3, "Reduced Blanking Coordinated Video Timings, v3" }, }; /* @@ -1425,7 +1432,12 @@ static void LogEdid(NVDpyEvoPtr pDpyEvo, NVEvoInfoStringPtr pInfoString) case NVT_TYPE_CUST_AUTO: case NVT_TYPE_CUST_MANUAL: case NVT_TYPE_CVT_RB_2: - default: + case NVT_TYPE_DMT_RB_2: + case NVT_TYPE_DISPLAYID_7: + case NVT_TYPE_DISPLAYID_8: + case NVT_TYPE_DISPLAYID_9: + case NVT_TYPE_DISPLAYID_10: + case NVT_TYPE_CVT_RB_3: break; } break; @@ -2415,7 +2427,6 @@ static void UpdateDpYUV420InfoFrame(const NVDispEvoRec *pDispEvo, { const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; - const NVHwModeTimingsEvo *pTimings = &pHeadState->timings; NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS params = { 0 }; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; NvU32 ret; @@ -2448,11 +2459,11 @@ static void UpdateDpYUV420InfoFrame(const NVDispEvoRec *pDispEvo, sdp->db.pixEncoding = SDP_VSC_PIX_ENC_YCBCR420; sdp->db.colorimetryFormat = SDP_VSC_COLOR_FMT_YCBCR_COLORIMETRY_ITU_R_BT709; - switch (pTimings->pixelDepth) { - case NVKMS_PIXEL_DEPTH_30_444: + switch (pAttributesSet->colorBpc) { + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_10: sdp->db.bitDepth = SDP_VSC_BIT_DEPTH_YCBCR_10BPC; break; - case NVKMS_PIXEL_DEPTH_24_444: + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8: sdp->db.bitDepth = SDP_VSC_BIT_DEPTH_YCBCR_8BPC; break; default: @@ -2547,10 +2558,13 @@ void nvUpdateInfoFrames(NVDpyEvoRec *pDpyEvo) NvBool nvDpyRequiresDualLinkEvo(const NVDpyEvoRec *pDpyEvo, const NVHwModeTimingsEvo *pTimings) { + const NvU32 pixelClock = (pTimings->yuv420Mode == NV_YUV420_MODE_HW) ? + (pTimings->pixelClock / 2) : pTimings->pixelClock; + // Dual link HDMI is not possible. nvAssert(!(nvDpyIsHdmiEvo(pDpyEvo) && - (pTimings->pixelClock > pDpyEvo->maxSingleLinkPixelClockKHz))); - return (pTimings->pixelClock > pDpyEvo->maxSingleLinkPixelClockKHz); + (pixelClock > pDpyEvo->maxSingleLinkPixelClockKHz))); + return (pixelClock > pDpyEvo->maxSingleLinkPixelClockKHz); } /*! @@ -2702,14 +2716,49 @@ NvBool nvDpyGetDynamicData( struct NvKmsQueryDpyDynamicDataParams *pParams) { NVDispEvoPtr pDispEvo = pDpyEvo->pDispEvo; - const struct NvKmsQueryDpyDynamicDataRequest *pRequest = &pParams->request; + struct NvKmsQueryDpyDynamicDataRequest *pRequest = &pParams->request; struct NvKmsQueryDpyDynamicDataReply *pReply = &pParams->reply; NVConnectorEvoPtr pConnectorEvo = pDpyEvo->pConnectorEvo; NVDpyIdList connectedList; NVDpyIdList oneDpyIdList = nvAddDpyIdToEmptyDpyIdList(pDpyEvo->id); + NVDpyOverridePtr pDpyOverride = nvDpyEvoGetOverride(pDpyEvo); nvkms_memset(pReply, 0, sizeof(*pReply)); + if (pDpyOverride != NULL) { + if (pDpyOverride->connected && !pRequest->forceDisconnected) { + /* + * If display is overridden as connected, treat the request as if it + * had both forceConnected and overrideEdid set, unless the request + * had forceDisconnected set. + * + * If the request already had an EDID override, honor that EDID instead + * of the display override EDID. + */ + NvBool old = pRequest->forceConnected; + pRequest->forceConnected = TRUE; + + if (!pRequest->overrideEdid) { + size_t len = nvReadDpyOverrideEdid(pDpyOverride, + pRequest->edid.buffer, + ARRAY_LEN(pRequest->edid.buffer)); + + if (len != 0) { + pRequest->overrideEdid = TRUE; + pRequest->edid.bufferSize = len; + } else { + pRequest->forceConnected = old; + } + } + } else if (!pDpyOverride->connected && !pRequest->forceConnected) { + /* + * If display is overriden as disconnected, treat the request as if it + * had forceDisconnected set, unless the request had forceConnected set. + */ + pRequest->forceDisconnected = TRUE; + } + } + /* * Check for the connection state of the dpy. * @@ -2912,8 +2961,119 @@ NvBool nvDpyIsAdaptiveSync(const NVDpyEvoRec *pDpyEvo) } // Returns TRUE if this display is in the Adaptive-Sync defaultlist -NvBool nvDpyIsAdaptiveSyncDefaultlisted(const NVParsedEdidEvoRec *pParsedEdid) +NvBool nvDpyIsAdaptiveSyncDefaultlisted(const NVDpyEvoRec *pDpyEvo) { return FALSE; } +static enum NvKmsDpyAttributeColorBpcValue GetYuv422MaxBpc( + const NVDpyEvoRec *pDpyEvo) +{ + const NVT_EDID_CEA861_INFO *p861Info = + &pDpyEvo->parsedEdid.info.ext861; + + nvAssert(nvDpyIsHdmiEvo(pDpyEvo) || + nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo)); + + if (!pDpyEvo->parsedEdid.valid || + !pDpyEvo->parsedEdid.info.input.isDigital) { + return NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_UNKNOWN; + } + + if (pDpyEvo->parsedEdid.info.version >= NVT_EDID_VER_1_4) { + if (pDpyEvo->parsedEdid.info.u.feature_ver_1_4_digital.support_ycrcb_422) { + if (pDpyEvo->parsedEdid.info.input.u.digital.bpc >= 10) { + return NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_10; + } else if (pDpyEvo->parsedEdid.info.input.u.digital.bpc >= 8) { + return NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; + } + } + } else { + nvAssert(!nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo)); + + if (p861Info->revision >= NVT_CEA861_REV_A && + !!(p861Info->basic_caps & NVT_CEA861_CAP_YCbCr_422)) { + return NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_10; + } + } + + return NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_UNKNOWN; +} + +NVColorFormatInfoRec nvGetColorFormatInfo(const NVDpyEvoRec *pDpyEvo) +{ + const NVConnectorEvoRec *pConnectorEvo = + pDpyEvo->pConnectorEvo; + NVColorFormatInfoRec colorFormatsInfo = { }; + + if (pConnectorEvo->legacyType == + NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_CRT) { + + colorFormatsInfo.rgb444.maxBpc = + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_10; + } else if (pConnectorEvo->legacyType == + NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_DFP) { + + if (pConnectorEvo->signalFormat == + NVKMS_CONNECTOR_SIGNAL_FORMAT_DSI) { + + if (pDpyEvo->parsedEdid.valid) { + switch (pDpyEvo->parsedEdid.info.input.u.digital.bpc) { + case 10: + colorFormatsInfo.rgb444.maxBpc = + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_10; + break; + case 6: + colorFormatsInfo.rgb444.maxBpc = + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_6; + break; + default: + nvAssert(!"Unsupported bpc for DSI"); + // fall through + case 8: + colorFormatsInfo.rgb444.maxBpc = + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; + break; + } + } else { + colorFormatsInfo.rgb444.maxBpc = + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; + } + } else if (nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo)) { + + if (pDpyEvo->parsedEdid.valid && + pDpyEvo->parsedEdid.info.input.isDigital && + pDpyEvo->parsedEdid.info.version >= NVT_EDID_VER_1_4) { + if (pDpyEvo->parsedEdid.info.input.u.digital.bpc >= 10) { + colorFormatsInfo.rgb444.maxBpc = + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_10; + } else if (pDpyEvo->parsedEdid.info.input.u.digital.bpc < 8) { + colorFormatsInfo.rgb444.maxBpc = + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_6; + } else { + colorFormatsInfo.rgb444.maxBpc = + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; + colorFormatsInfo.yuv444.maxBpc = + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; + } + + colorFormatsInfo.yuv422.maxBpc = GetYuv422MaxBpc(pDpyEvo); + } else { + colorFormatsInfo.rgb444.maxBpc = + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; + } + } else { + + colorFormatsInfo.rgb444.maxBpc = + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; + if (nvDpyIsHdmiEvo(pDpyEvo)) { + colorFormatsInfo.yuv444.maxBpc = + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; + colorFormatsInfo.yuv422.maxBpc = + GetYuv422MaxBpc(pDpyEvo); + } + } + } + + return colorFormatsInfo; +} diff --git a/src/nvidia-modeset/src/nvkms-evo.c b/src/nvidia-modeset/src/nvkms-evo.c index 738a7318d..8720446c2 100644 --- a/src/nvidia-modeset/src/nvkms-evo.c +++ b/src/nvidia-modeset/src/nvkms-evo.c @@ -34,6 +34,7 @@ #include "nvkms-modepool.h" #include "nvkms-evo.h" #include "nvkms-flip.h" +#include "nvkms-hw-flip.h" #include "nvkms-dma.h" #include "nvkms-framelock.h" #include "nvkms-utils.h" @@ -111,7 +112,7 @@ static void SyncEvoLockState(void); static void UpdateEvoLockState(void); static void ScheduleLutUpdate(NVDispEvoRec *pDispEvo, - const NvU32 head, const NvU32 data, + const NvU32 apiHead, const NvU32 data, const NvU64 usec); NVEvoGlobal nvEvoGlobal = { @@ -792,6 +793,7 @@ void nvEvoSetTimings(NVDispEvoPtr pDispEvo, NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; const NVHwModeTimingsEvo *pTimings = &pHeadState->timings; + const enum nvKmsPixelDepth pixelDepth = pHeadState->pixelDepth; NVEvoColorRec overscanColor; nvPushEvoSubDevMaskDisp(pDispEvo); @@ -823,7 +825,7 @@ void nvEvoSetTimings(NVDispEvoPtr pDispEvo, EvoUpdateHeadParams(pDispEvo, head, updateState); - pDevEvo->hal->SetDscParams(pDispEvo, head, pTimings); + pDevEvo->hal->SetDscParams(pDispEvo, head, pTimings, pixelDepth); nvPopEvoSubDevMask(pDevEvo); } @@ -1640,54 +1642,99 @@ void nvEnableMidFrameAndDWCFWatermark(NVDevEvoPtr pDevEvo, pUpdateState); } +NvBool nvGetDefaultColorSpace( + const NVColorFormatInfoRec *pColorFormatsInfo, + enum NvKmsDpyAttributeCurrentColorSpaceValue *pColorSpace, + enum NvKmsDpyAttributeColorBpcValue *pColorBpc) +{ + if (pColorFormatsInfo->rgb444.maxBpc != + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_UNKNOWN) { + *pColorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB; + *pColorBpc = pColorFormatsInfo->rgb444.maxBpc; + return TRUE; + } + + if (pColorFormatsInfo->yuv444.maxBpc != + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_UNKNOWN) { + *pColorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444; + *pColorBpc = pColorFormatsInfo->yuv444.maxBpc; + return TRUE; + } + + if (pColorFormatsInfo->yuv422.maxBpc != + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_UNKNOWN) { + *pColorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422; + *pColorBpc = pColorFormatsInfo->yuv422.maxBpc; + return TRUE; + } + + return FALSE; +} /*! - * Choose current colorSpace and colorRange based on the current mode timings - * and the requested color space and range, and notify clients of any changes. + * Choose current colorSpace and colorRange for the given dpy based on + * the dpy's color format capailities, the given modeset parameters (YUV420 + * mode and output transfer function) and the requested color space and range. * - * This needs to be called during a modeset when YUV420 mode may have been - * enabled or disabled, as well as when the requested color space or range have - * changed. - * - * RGB/YUV would be selected for DFP, only RGB would be selected for CRT and - * only YUV would be selected for TV. + * This needs to be called during a modeset as well as when the requested color + * space or range have changed. * * If SW YUV420 mode is enabled, EVO HW is programmed with default (RGB color * space, FULL color range) values, and the real values are used in a * headSurface composite shader. */ -void nvChooseCurrentColorSpaceAndRangeEvo( - enum nvKmsPixelDepth pixelDepth, +NvBool nvChooseCurrentColorSpaceAndRangeEvo( + const NVDpyEvoRec *pDpyEvo, enum NvYuv420Mode yuv420Mode, enum NvKmsOutputTf tf, const enum NvKmsDpyAttributeRequestedColorSpaceValue requestedColorSpace, const enum NvKmsDpyAttributeColorRangeValue requestedColorRange, enum NvKmsDpyAttributeCurrentColorSpaceValue *pCurrentColorSpace, + enum NvKmsDpyAttributeColorBpcValue *pCurrentColorBpc, enum NvKmsDpyAttributeColorRangeValue *pCurrentColorRange) { enum NvKmsDpyAttributeCurrentColorSpaceValue newColorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB; + enum NvKmsDpyAttributeColorBpcValue newColorBpc = + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_10; enum NvKmsDpyAttributeColorRangeValue newColorRange = NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_FULL; + const NVColorFormatInfoRec colorFormatsInfo = + nvGetColorFormatInfo(pDpyEvo); - /* At depth 18 only RGB and full range are allowed */ - if (pixelDepth == NVKMS_PIXEL_DEPTH_18_444) { - goto done; - } + // XXX HDR TODO: Handle other transfer functions + // XXX HDR TODO: Handle YUV + if (tf == NVKMS_OUTPUT_TF_PQ) { + /* + * If the head is currently in PQ output mode, we override the + * requested color space with RGB. We cannot support yuv420Mode in + * that configuration, so fail in that case. + */ + if (yuv420Mode != NV_YUV420_MODE_NONE) { + return FALSE; + } - /* - * If the current mode timing requires YUV420 compression, we override the - * requested color space with YUV420. - * - * If the head is currently in PQ output mode, we override the requested - * color space with BT2020. - */ - if (yuv420Mode != NV_YUV420_MODE_NONE) { + /* + * At depth 18 only RGB and full range are allowed. Also, + * NVKMS_OUTPUT_TF_PQ requires limited range, which we can't do at + * depth 18; fail in that case. + */ + if (colorFormatsInfo.rgb444.maxBpc == + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_6) { + return FALSE; + } + newColorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB; + newColorBpc = colorFormatsInfo.rgb444.maxBpc; + } else if (yuv420Mode != NV_YUV420_MODE_NONE) { + /* + * If the current mode timing requires YUV420 compression, we override the + * requested color space with YUV420. + */ newColorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420; - } else if (tf == NVKMS_OUTPUT_TF_PQ) { - // XXX HDR TODO: Handle other transfer functions - // XXX HDR TODO: Handle YUV - newColorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_BT2020RGB; + newColorBpc = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; + + nvAssert(colorFormatsInfo.rgb444.maxBpc >= + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8); } else { /* * Note this is an assignment between different enum types. Checking the @@ -1697,31 +1744,52 @@ void nvChooseCurrentColorSpaceAndRangeEvo( switch (requestedColorSpace) { case NV_KMS_DPY_ATTRIBUTE_REQUESTED_COLOR_SPACE_RGB: newColorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB; + newColorBpc = colorFormatsInfo.rgb444.maxBpc; break; case NV_KMS_DPY_ATTRIBUTE_REQUESTED_COLOR_SPACE_YCbCr422: newColorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422; + newColorBpc = colorFormatsInfo.yuv422.maxBpc; break; case NV_KMS_DPY_ATTRIBUTE_REQUESTED_COLOR_SPACE_YCbCr444: newColorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444; + newColorBpc = colorFormatsInfo.yuv444.maxBpc; break; default: nvAssert(!"Invalid Requested ColorSpace"); } + + if ((newColorBpc == + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_UNKNOWN) && + !nvGetDefaultColorSpace(&colorFormatsInfo, &newColorSpace, + &newColorBpc)) { + return FALSE; + } } - /* Only limited color range is allowed in YUV and BT2020 colorimetry. */ + /* Hardware supports BPC_6 only for RGB */ + nvAssert((newColorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB) || + (newColorBpc != NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_6)); + /* + * Both YUV and NVKMS_OUTPUT_TF_PQ requires limited color range. + */ if ((newColorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444) || (newColorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422) || (newColorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420) || - (newColorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_BT2020RGB)) { + (tf == NVKMS_OUTPUT_TF_PQ)) { newColorRange = NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_LIMITED; + } else if ((newColorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB) && + (newColorBpc == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_6)) { + /* At depth 18 only RGB and full range are allowed */ + newColorRange = NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_FULL; } else { newColorRange = requestedColorRange; } -done: *pCurrentColorSpace = newColorSpace; *pCurrentColorRange = newColorRange; + *pCurrentColorBpc = newColorBpc; + + return TRUE; } void nvUpdateCurrentHardwareColorSpaceAndRangeEvo( @@ -1737,11 +1805,21 @@ void nvUpdateCurrentHardwareColorSpaceAndRangeEvo( nvAssert(pConnectorEvo != NULL); - // In SW YUV420 mode, HW is programmed with RGB color space and full color - // range. The color space conversion and color range compression happen - // in a headSurface composite shader. - if ((pHeadState->timings.yuv420Mode == NV_YUV420_MODE_SW) && + if (pHeadState->tf == NVKMS_OUTPUT_TF_PQ) { + nvAssert(pHeadState->timings.yuv420Mode == NV_YUV420_MODE_NONE); + nvAssert(colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB); + nvAssert(colorRange == NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_LIMITED); + + pHeadState->procAmp.colorimetry = NVT_COLORIMETRY_BT2020RGB; + pHeadState->procAmp.colorRange = NVT_COLOR_RANGE_LIMITED; + pHeadState->procAmp.colorFormat = NVT_COLOR_FORMAT_RGB; + } else if ((pHeadState->timings.yuv420Mode == NV_YUV420_MODE_SW) && (colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420)) { + /* + * In SW YUV420 mode, HW is programmed with RGB color space and full + * color range. The color space conversion and color range compression + * happen in a headSurface composite shader. + */ pHeadState->procAmp.colorimetry = NVT_COLORIMETRY_RGB; pHeadState->procAmp.colorRange = NVT_COLOR_RANGE_FULL; pHeadState->procAmp.colorFormat = NVT_COLOR_FORMAT_RGB; @@ -1754,7 +1832,6 @@ void nvUpdateCurrentHardwareColorSpaceAndRangeEvo( // Set color format switch (colorSpace) { case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB: - case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_BT2020RGB: pHeadState->procAmp.colorFormat = NVT_COLOR_FORMAT_RGB; break; case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444: @@ -1777,9 +1854,6 @@ void nvUpdateCurrentHardwareColorSpaceAndRangeEvo( case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB: pHeadState->procAmp.colorimetry = NVT_COLORIMETRY_RGB; break; - case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_BT2020RGB: - pHeadState->procAmp.colorimetry = NVT_COLORIMETRY_BT2020RGB; - break; case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444: case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422: case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420: @@ -1806,17 +1880,17 @@ void nvUpdateCurrentHardwareColorSpaceAndRangeEvo( nvAssert(!"ERROR: invalid pDpyEvo->type"); } - // Only advertise YCbCr444 or YCbCr422 when the corresponding - // colorSpaceCaps is TRUE. - if ((colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444) && - !pConnectorEvo->colorSpaceCaps.ycbcr444Capable) { - nvAssert(!"!pConnectorEvo->colorSpaceCaps.ycbcr444Capable"); - } + /* YCbCr444 should be advertise only for DisplayPort and HDMI */ + nvAssert((colorSpace != NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444) || + nvConnectorUsesDPLib(pConnectorEvo) || + pConnectorEvo->isHdmiEnabled); - if ((colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422) && - !pConnectorEvo->colorSpaceCaps.ycbcr422Capable) { - nvAssert(!"!pConnectorEvo->colorSpaceCaps.ycbcr422Capable"); - } + /* YcbCr422 should be advertised only for HDMI and DP on supported GPUs */ + nvAssert((colorSpace != NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422) || + (((pDevEvo->caps.hdmiYCbCr422MaxBpc != 0) && + pConnectorEvo->isHdmiEnabled)) || + ((pDevEvo->caps.dpYCbCr422MaxBpc != 0) && + nvConnectorUsesDPLib(pConnectorEvo))); switch (colorRange) { case NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_FULL: @@ -1836,7 +1910,7 @@ void nvUpdateCurrentHardwareColorSpaceAndRangeEvo( (pHeadState->procAmp.colorRange != NVT_COLOR_RANGE_LIMITED))); // Limited color range is not allowed with 18bpp mode - nvAssert(!((pHeadState->timings.pixelDepth == NVKMS_PIXEL_DEPTH_18_444) && + nvAssert(!((pHeadState->pixelDepth == NVKMS_PIXEL_DEPTH_18_444) && (pHeadState->procAmp.colorRange == NVT_COLOR_RANGE_LIMITED))); nvPushEvoSubDevMaskDisp(pDispEvo); @@ -1854,6 +1928,7 @@ void nvEvoHeadSetControlOR(NVDispEvoPtr pDispEvo, NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; const NVDispHeadStateEvoPtr pHeadState = &pDispEvo->headState[head]; const NVHwModeTimingsEvo *pTimings = &pHeadState->timings; + const enum nvKmsPixelDepth pixelDepth = pHeadState->pixelDepth; NvBool colorSpaceOverride = FALSE; /* @@ -1874,7 +1949,7 @@ void nvEvoHeadSetControlOR(NVDispEvoPtr pDispEvo, // Only set up the actual output for SLI primary. nvPushEvoSubDevMask(pDevEvo, 1 << pDispEvo->displayOwner); - pDevEvo->hal->HeadSetControlOR(pDevEvo, head, pTimings, + pDevEvo->hal->HeadSetControlOR(pDevEvo, head, pTimings, pixelDepth, colorSpaceOverride, pUpdateState); @@ -1913,7 +1988,7 @@ static const struct { */ void nvChooseDitheringEvo( const NVConnectorEvoRec *pConnectorEvo, - const enum nvKmsPixelDepth pixelDepth, + enum NvKmsDpyAttributeColorBpcValue bpc, const NVDpyAttributeRequestedDitheringConfig *pReqDithering, NVDpyAttributeCurrentDitheringConfig *pCurrDithering) { @@ -1989,10 +2064,9 @@ void nvChooseDitheringEvo( * which lowers the color depth, consider that while applying * dithering effects. */ - NvU32 dpBits = nvPixelDepthToBitsPerComponent(pixelDepth); - if (dpBits == 0) { + if (bpc == 0) { nvAssert(!"Unknown dpBits"); - dpBits = 8; + bpc = 8; } /* @@ -2002,7 +2076,7 @@ void nvChooseDitheringEvo( * * XXX TODO: nvdisplay can dither to 10 bpc. */ - if ((dpBits <= 8) && (lutBits > dpBits)) { + if ((bpc <= 8) && (lutBits > bpc)) { if (pReqDithering->state == NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_AUTO) { currDithering.enabled = TRUE; @@ -2011,10 +2085,10 @@ void nvChooseDitheringEvo( if (pReqDithering->depth == NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_DEPTH_AUTO) { - if (dpBits <= 6) { + if (bpc <= 6) { currDithering.depth = NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_DEPTH_6_BITS; - } else if (dpBits <= 8) { + } else if (bpc <= 8) { currDithering.depth = NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_DEPTH_8_BITS; } @@ -2992,13 +3066,21 @@ NvBool nvQueryRasterLockEvo(const NVDpyEvoRec *pDpyEvo, NvS64 *val) NVDispEvoPtr pDispEvo = pDpyEvo->pDispEvo; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; NVEvoSubDevPtr pEvoSubDev; - /* - * XXX[2Heads1OR] Loop over hardware heads to determine if this api-head - * is rasterlocked with any other api-head. - */ - const NvU32 head = pDpyEvo->apiHead; + const NvU32 apiHead = pDpyEvo->apiHead; + const NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); NVEvoHeadControlPtr pHC; + /* + * XXX[2Heads1OR] The EVO lock state machine is not currently supported with + * 2Heads1OR, the api head is expected to be mapped onto a single + * hardware head (which is the primary hardware head) if 2Heads1OR is not + * active and the EVO lock state machine is in use. + */ + if ((apiHead == NV_INVALID_HEAD) || + (nvPopCount32(pDispEvo->apiHeadState[apiHead].hwHeadsMask) != 1)) { + return FALSE; + } + if ((head == NV_INVALID_HEAD) || (pDevEvo->gpus == NULL)) { return FALSE; } @@ -3158,15 +3240,22 @@ static NvBool UpdateFlipLock50(const NVDpyEvoRec *pDpyEvo, NvU32 *val, NvBool set) { NVDispEvoPtr pDispEvo = pDpyEvo->pDispEvo; - /* - * XXX[2Heads1OR] Loop over hardware heads to determine is this api-head - * is rasterlocked with any other api-head and flip lock is not prohibited - * on its corresponding hardware heads. - */ - const NvU32 head = pDpyEvo->apiHead; + const NvU32 apiHead = pDpyEvo->apiHead; + const NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); NVEvoUpdateState updateState = { }; NvBool ret; + /* + * XXX[2Heads1OR] The EVO lock state machine is not currently supported with + * 2Heads1OR, the api head is expected to be mapped onto a single + * hardware head (which is the primary hardware head) if 2Heads1OR is not + * active and the EVO lock state machine is in use. + */ + if ((apiHead == NV_INVALID_HEAD) || + (nvPopCount32(pDispEvo->apiHeadState[apiHead].hwHeadsMask) != 1)) { + return FALSE; + } + if (head == NV_INVALID_HEAD) { return FALSE; } @@ -3412,47 +3501,46 @@ static void EvoSetViewportPointIn(NVDispEvoPtr pDispEvo, const NvU32 head, nvPopEvoSubDevMask(pDevEvo); } -static inline NvU32 LUTNotifierForHead(const NvU32 head) +static inline NvU32 LUTNotifierForApiHead(const NvU32 apiHead) { - nvAssert(head != NV_INVALID_HEAD); - return 1 + head; + nvAssert(apiHead != NV_INVALID_HEAD); + return 1 + apiHead; } -//****************************************************************************** -// -// Function: EvoUpdateCurrentPalette -// -// Description: Setting the palette -// -// Arguments: -// -// Return Value: None. -// -//****************************************************************************** -void nvEvoUpdateCurrentPalette(NVDispEvoPtr pDispEvo, - NvU32 head, NvBool kickOff) +void nvEvoSetLUTContextDma(NVDispEvoPtr pDispEvo, + const NvU32 head, NVEvoUpdateState *pUpdateState) { NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + + pDevEvo->hal->SetLUTContextDma(pDispEvo, + head, + pHeadState->lut.pCurrSurface, + pHeadState->lut.baseLutEnabled, + pHeadState->lut.outputLutEnabled, + pUpdateState, + pHeadState->bypassComposition); +} + +static void EvoUpdateCurrentPalette(NVDispEvoPtr pDispEvo, const NvU32 apiHead) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; const int dispIndex = pDispEvo->displayOwner; - NvU8 lutIndex = pDevEvo->lut.head[head].disp[dispIndex].curLUTIndex; + NvU32 head; NVEvoUpdateState updateState = { }; - pDevEvo->hal->SetLUTContextDma( - pDispEvo, - head, - pDevEvo->lut.head[head].LUT[lutIndex], - pDevEvo->lut.head[head].disp[dispIndex].curBaseLutEnabled, - pDevEvo->lut.head[head].disp[dispIndex].curOutputLutEnabled, - &updateState, - pHeadState->bypassComposition); + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + nvEvoSetLUTContextDma(pDispEvo, head, &updateState); + } /* * EVO2 does not set LUT context DMA if the core channel * doesn't have a scanout surface set, in that case there is no update * state to kickoff. */ - if (kickOff && !nvIsUpdateStateEmpty(pDevEvo, &updateState)) { + if (!nvIsUpdateStateEmpty(pDevEvo, &updateState)) { // Clear the completion notifier and kick off an update. Wait for it // here if NV_CTRL_SYNCHRONOUS_PALETTE_UPDATES is enabled. Otherwise, // don't wait for the notifier -- it'll be checked the next time a LUT @@ -3460,10 +3548,10 @@ void nvEvoUpdateCurrentPalette(NVDispEvoPtr pDispEvo, EvoUpdateAndKickOffWithNotifier(pDispEvo, TRUE, /* notify */ FALSE, /* sync */ - LUTNotifierForHead(head), + LUTNotifierForApiHead(apiHead), &updateState, TRUE /* releaseElv */); - pDevEvo->lut.head[head].disp[dispIndex].waitForPreviousUpdate = TRUE; + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].waitForPreviousUpdate = TRUE; } } @@ -3568,7 +3656,233 @@ static NvBool ValidateConnectorTypes(const NVDevEvoRec *pDevEvo) return TRUE; } -static void InitApiHeadState(NVDevEvoRec *pDevEvo) +static void ClearApiHeadStateOneDisp(NVDispEvoRec *pDispEvo) +{ + NvU32 apiHead; + NVConnectorEvoRec *pConnectorEvo; + + FOR_ALL_EVO_CONNECTORS(pConnectorEvo, pDispEvo) { + pConnectorEvo->validApiHeadMask = 0x0; + } + + for (apiHead = 0; apiHead < ARRAY_LEN(pDispEvo->apiHeadState); apiHead++) { + NvU32 layer; + NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + nvAssert(nvListIsEmpty(&pApiHeadState->vblankCallbackList)); + for (layer = 0; layer < ARRAY_LEN(pApiHeadState->flipOccurredEvent); layer++) { + if (pApiHeadState->flipOccurredEvent[layer].ref_ptr != NULL) { + nvkms_free_ref_ptr(pApiHeadState->flipOccurredEvent[layer].ref_ptr); + pApiHeadState->flipOccurredEvent[layer].ref_ptr = NULL; + } + } + } + + nvkms_memset(pDispEvo->apiHeadState, 0, sizeof(pDispEvo->apiHeadState)); +} + +static void UnRegisterFlipOccurredEventOneApiHead(NVDevEvoRec *pDevEvo, + const NvU32 apiHead) +{ + const NvU32 dispIndex = 0; /* XXX NVKMS TODO: need disp-scope in event */ + NVDispEvoRec *pDispEvo = pDevEvo->pDispEvo[dispIndex]; + NvU32 layer; + NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); + + if (head == NV_INVALID_HEAD) { + /* This can happen if nvAllocCoreChannelEvo() fails and leaves things + * in a partially-initialized state and nvFreeCoreChannelEvo() is + * called to clean up. */ + return; + } + + /* + * pDevEvo->apiHead[apiHead].numLayers is the number of layer which is + * visible to nvkms clients, and that number should be less than equal to + * pDevEvo->head[head].numLayers. + * + * If (pDevEvo->head[head].numLayers > pDevEvo->apiHead[apiHead].numLayers) + * then the extra per hardware-head layers remains unused and there is no + * need to register the completion notifier callback for those extra per + * hardware-head layers. + */ + nvAssert(pDevEvo->head[head].numLayers >= + pDevEvo->apiHead[apiHead].numLayers); + + for (layer = 0; layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { + NVEvoChannelPtr pChannel = pDevEvo->head[head].layer[layer]; + + if (pChannel->completionNotifierEventHandle != 0) { + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, + pChannel->completionNotifierEventHandle); + pChannel->completionNotifierEventHandle = 0; + } + } +} + +static void ClearApiHeadState(NVDevEvoRec *pDevEvo) +{ + NvU32 apiHead; + NvU32 dispIndex; + NVDispEvoRec *pDispEvo; + + nvRmFreeCoreRGSyncpts(pDevEvo); + + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + UnRegisterFlipOccurredEventOneApiHead(pDevEvo, apiHead); + } + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + ClearApiHeadStateOneDisp(pDispEvo); + } + + nvkms_memset(pDevEvo->apiHead, 0, sizeof(pDevEvo->apiHead)); +} + +static NvBool InitApiHeadStateOnceDisp(NVDispEvoRec *pDispEvo) +{ + NvU32 apiHead; + NVConnectorEvoRec *pConnectorEvo; + + for (apiHead = 0; apiHead < ARRAY_LEN(pDispEvo->apiHeadState); apiHead++) { + NvU32 layer; + NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + + nvListInit(&pApiHeadState->vblankCallbackList); + + for (layer = 0; layer < ARRAY_LEN(pApiHeadState->flipOccurredEvent); layer++) { + pApiHeadState->flipOccurredEvent[layer].ref_ptr = + nvkms_alloc_ref_ptr(&pApiHeadState->flipOccurredEvent[layer].data); + if (pApiHeadState->flipOccurredEvent[layer].ref_ptr == NULL) { + goto failed; + } + + pApiHeadState->flipOccurredEvent[layer].data = + (NVDispFlipOccurredEventDataEvoRec) { + .pDispEvo = pDispEvo, + .apiHead = apiHead, + .layer = layer, + }; + } + } + + for (NvU32 head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { + NvU32 apiHead = nvHardwareHeadToApiHead(pDispEvo->pDevEvo, head); + + pDispEvo->apiHeadState[apiHead].hwHeadsMask = NVBIT(head); + pDispEvo->apiHeadState[apiHead].attributes = + NV_EVO_DEFAULT_ATTRIBUTES_SET; + + if (pDispEvo->headState[head].pConnectorEvo != NULL) { + const NVConnectorEvoRec *pConnectorEvo = + pDispEvo->headState[head].pConnectorEvo; + + /* + * Use the pDpyEvo for the connector, since we may not have one + * for display id if it's a dynamic one. + */ + NVDpyEvoRec *pDpyEvo = nvGetDpyEvoFromDispEvo(pDispEvo, + pConnectorEvo->displayId); + + nvAssert(pDpyEvo->apiHead == NV_INVALID_HEAD); + + pDpyEvo->apiHead = apiHead; + pDispEvo->apiHeadState[apiHead].activeDpys = + nvAddDpyIdToEmptyDpyIdList(pConnectorEvo->displayId); + } else { + pDispEvo->apiHeadState[apiHead].activeDpys = nvEmptyDpyIdList(); + } + } + + FOR_ALL_EVO_CONNECTORS(pConnectorEvo, pDispEvo) { + NvU32 head; + pConnectorEvo->validApiHeadMask = 0x0; + FOR_EACH_EVO_HW_HEAD_IN_MASK(pConnectorEvo->validHeadMask, head) { + NvU32 apiHead = nvHardwareHeadToApiHead(pDispEvo->pDevEvo, head); + pConnectorEvo->validApiHeadMask |= NVBIT(apiHead); + } + } + + return TRUE; + +failed: + ClearApiHeadStateOneDisp(pDispEvo); + + return FALSE; +} + +static void +CompletionNotifierEventDeferredWork(void *dataPtr, NvU32 dataU32) +{ + NVDispFlipOccurredEventDataEvoRec *pEventData = dataPtr; + + nvSendFlipOccurredEventEvo(pEventData->pDispEvo, pEventData->apiHead, + pEventData->layer); +} + +static void CompletionNotifierEvent(void *arg, void *pEventDataVoid, + NvU32 hEvent, NvU32 Data, NV_STATUS Status) +{ + (void) nvkms_alloc_timer_with_ref_ptr( + CompletionNotifierEventDeferredWork, /* callback */ + arg, /* argument (this is a ref_ptr to NVDispFlipOccurredEventDataEvoRec) */ + 0, /* dataU32 */ + 0); /* timeout: schedule the work immediately */ +} + +static NvBool RegisterFlipOccurredEventOneApiHead(NVDevEvoRec *pDevEvo, + const NvU32 apiHead) +{ + const NvU32 dispIndex = 0; /* XXX NVKMS TODO: need disp-scope in event */ + NVDispEvoRec *pDispEvo = pDevEvo->pDispEvo[dispIndex]; + NvU32 layer; + NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); + + nvAssert(head != NV_INVALID_HEAD); + /* + * pDevEvo->apiHead[apiHead].numLayers is the number of layer which is + * visible to nvkms clients, and that number should be less than equal to + * pDevEvo->head[head].numLayers. + * + * If (pDevEvo->head[head].numLayers > pDevEvo->apiHead[apiHead].numLayers) + * then the extra per hardware-head layers remains unused and there is no + * need to register the completion notifier callback for those extra per + * hardware-head layers. + */ + nvAssert(pDevEvo->head[head].numLayers >= + pDevEvo->apiHead[apiHead].numLayers); + + for (layer = 0; layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { + NVEvoChannelPtr pChannel = pDevEvo->head[head].layer[layer]; + + pChannel->completionNotifierEventHandle = + nvGenerateUnixRmHandle(&pDevEvo->handleAllocator); + + if (!nvRmRegisterCallback(pDevEvo, + &pChannel->completionNotifierEventCallback, + pDispEvo->apiHeadState[apiHead]. + flipOccurredEvent[layer].ref_ptr, + pChannel->pb.channel_handle, + pChannel->completionNotifierEventHandle, + CompletionNotifierEvent, + 0)) { + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, + pChannel->completionNotifierEventHandle); + pChannel->completionNotifierEventHandle = 0; + goto failed; + } + } + + return TRUE; + +failed: + UnRegisterFlipOccurredEventOneApiHead(pDevEvo, apiHead); + + return FALSE; +} + +static NvBool InitApiHeadState(NVDevEvoRec *pDevEvo) { NVDispEvoRec *pDispEvo; NvU32 dispIndex; @@ -3577,40 +3891,29 @@ static void InitApiHeadState(NVDevEvoRec *pDevEvo) nvAssert(pDevEvo->numApiHeads == pDevEvo->numHeads); for (head = 0; head < pDevEvo->numHeads; head++) { - NvU32 apiHead = nvHardwareHeadToApiHead(head); + NvU32 apiHead = nvHardwareHeadToApiHead(pDevEvo, head); pDevEvo->apiHead[apiHead].numLayers = pDevEvo->head[head].numLayers; } FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - for (head = 0; head < pDevEvo->numHeads; head++) { - NvU32 apiHead = nvHardwareHeadToApiHead(head); - - pDispEvo->apiHeadState[apiHead].hwHeadsMask = NVBIT(head); - pDispEvo->apiHeadState[apiHead].attributes = - NV_EVO_DEFAULT_ATTRIBUTES_SET; - - if (pDispEvo->headState[head].pConnectorEvo != NULL) { - const NVConnectorEvoRec *pConnectorEvo = - pDispEvo->headState[head].pConnectorEvo; - - /* - * Use the pDpyEvo for the connector, since we may not have one - * for display id if it's a dynamic one. - */ - NVDpyEvoRec *pDpyEvo = nvGetDpyEvoFromDispEvo(pDispEvo, - pConnectorEvo->displayId); - - nvAssert(pDpyEvo->apiHead == NV_INVALID_HEAD); - - pDpyEvo->apiHead = apiHead; - pDispEvo->apiHeadState[apiHead].activeDpys = - nvAddDpyIdToEmptyDpyIdList(pConnectorEvo->displayId); - } else { - pDispEvo->apiHeadState[apiHead].activeDpys = nvEmptyDpyIdList(); - } + if (!InitApiHeadStateOnceDisp(pDispEvo)) { + goto failed; } } + + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + RegisterFlipOccurredEventOneApiHead(pDevEvo, apiHead); + } + + nvRmAllocCoreRGSyncpts(pDevEvo); + + return TRUE; + +failed: + ClearApiHeadState(pDevEvo); + + return FALSE; } /*! @@ -3778,6 +4081,12 @@ NvBool nvAllocCoreChannelEvo(NVDevEvoPtr pDevEvo) goto failed; } + if (!InitApiHeadState(pDevEvo)) { + nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, + "Failed to initialize the api heads."); + goto failed; + } + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { nvRmRegisterBacklight(pDispEvo); } @@ -3790,8 +4099,6 @@ NvBool nvAllocCoreChannelEvo(NVDevEvoPtr pDevEvo) } } - InitApiHeadState(pDevEvo); - return TRUE; failed: @@ -4037,7 +4344,7 @@ NvBool nvResumeDevEvo(NVDevEvoRec *pDevEvo) * restore the assignment, might be in use by the boot display setup * by vbios/gop driver. */ - nvShutDownHeads(pDevEvo, NULL /* pTestFunc, shut down all heads */); + nvShutDownApiHeads(pDevEvo, NULL /* pTestFunc, shut down all heads */); FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { RestoreSorAssignList(pDispEvo, disp[dispIndex].sorAssignList); @@ -4052,18 +4359,6 @@ void nvSuspendDevEvo(NVDevEvoRec *pDevEvo) nvFreeCoreChannelEvo(pDevEvo); } -static void ClearApiHeadState(NVDevEvoRec *pDevEvo) -{ - NvU32 dispIndex; - NVDispEvoRec *pDispEvo; - - nvkms_memset(pDevEvo->apiHead, 0, sizeof(pDevEvo->apiHead)); - - FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - nvkms_memset(pDispEvo->apiHeadState, 0, sizeof(pDispEvo->apiHeadState)); - } -} - /*! * Free the EVO core channel. * @@ -4301,6 +4596,37 @@ void nvSetImageSharpeningEvo(NVDispEvoRec *pDispEvo, const NvU32 head, nvPopEvoSubDevMask(pDevEvo); } +static void LayerSetPositionOneApiHead(NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + const NvU32 layer, + const NvS16 x, + const NvS16 y, + NVEvoUpdateState *pUpdateState) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + const NvU32 sd = pDispEvo->displayOwner; + NvU32 head; + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + NVEvoSubDevHeadStateRec *pSdHeadState = + &pDevEvo->gpus[sd].headState[head]; + + if ((pSdHeadState->layer[layer].outputPosition.x != x) || + (pSdHeadState->layer[layer].outputPosition.y != y)) { + NVEvoChannelPtr pChannel = + pDevEvo->head[head].layer[layer]; + + pSdHeadState->layer[layer].outputPosition.x = x; + pSdHeadState->layer[layer].outputPosition.y = y; + + pDevEvo->hal->SetImmPointOut(pDevEvo, pChannel, sd, pUpdateState, + x, y); + } + } +} + NvBool nvLayerSetPositionEvo( NVDevEvoPtr pDevEvo, const struct NvKmsSetLayerPositionRequest *pRequest) @@ -4315,29 +4641,29 @@ NvBool nvLayerSetPositionEvo( * state. */ FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - NvU32 head; + NvU32 apiHead; if ((pRequest->requestedDispsBitMask & NVBIT(sd)) == 0) { continue; } - for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { + for (apiHead = 0; apiHead < NVKMS_MAX_HEADS_PER_DISP; apiHead++) { NvU32 layer; if ((pRequest->disp[sd].requestedHeadsBitMask & - NVBIT(head)) == 0) { + NVBIT(apiHead)) == 0) { continue; } - if (!nvHeadIsActive(pDispEvo, head)) { + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { continue; } - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - const NvS16 x = pRequest->disp[sd].head[head].layerPosition[layer].x; - const NvS16 y = pRequest->disp[sd].head[head].layerPosition[layer].y; + for (layer = 0; layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { + const NvS16 x = pRequest->disp[sd].head[apiHead].layerPosition[layer].x; + const NvS16 y = pRequest->disp[sd].head[apiHead].layerPosition[layer].y; - if ((pRequest->disp[sd].head[head].requestedLayerBitMask & + if ((pRequest->disp[sd].head[apiHead].requestedLayerBitMask & NVBIT(layer)) == 0x0) { continue; } @@ -4358,47 +4684,36 @@ NvBool nvLayerSetPositionEvo( /* Checks in above block passed, so make the requested changes. */ FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - NvU32 head; + NvU32 apiHead; if ((pRequest->requestedDispsBitMask & NVBIT(sd)) == 0) { continue; } - for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { + for (apiHead = 0; apiHead < NVKMS_MAX_HEADS_PER_DISP; apiHead++) { NVEvoUpdateState updateState = { }; - NVEvoSubDevHeadStateRec *pSdHeadState = - &pDevEvo->gpus[sd].headState[head]; NvU32 layer; if ((pRequest->disp[sd].requestedHeadsBitMask & - NVBIT(head)) == 0) { + NVBIT(apiHead)) == 0) { continue; } - if (!nvHeadIsActive(pDispEvo, head)) { + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { continue; } - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - const NvS16 x = pRequest->disp[sd].head[head].layerPosition[layer].x; - const NvS16 y = pRequest->disp[sd].head[head].layerPosition[layer].y; + for (layer = 0; layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { + const NvS16 x = pRequest->disp[sd].head[apiHead].layerPosition[layer].x; + const NvS16 y = pRequest->disp[sd].head[apiHead].layerPosition[layer].y; - if ((pRequest->disp[sd].head[head].requestedLayerBitMask & + if ((pRequest->disp[sd].head[apiHead].requestedLayerBitMask & NVBIT(layer)) == 0x0) { continue; } - if ((pSdHeadState->layer[layer].outputPosition.x != x) || - (pSdHeadState->layer[layer].outputPosition.y != y)) { - - NVEvoChannelPtr pChannel = pDevEvo->head[head].layer[layer]; - - pSdHeadState->layer[layer].outputPosition.x = x; - pSdHeadState->layer[layer].outputPosition.y = y; - - pDevEvo->hal->SetImmPointOut(pDevEvo, pChannel, sd, - &updateState, x, y); - } + LayerSetPositionOneApiHead(pDispEvo, apiHead, layer, x, y, + &updateState); } pDevEvo->hal->Update(pDevEvo, &updateState, TRUE /* releaseElv */); @@ -4420,6 +4735,8 @@ NvBool nvLayerSetPositionEvo( NvBool nvConstructHwModeTimingsImpCheckEvo( const NVConnectorEvoRec *pConnectorEvo, NVHwModeTimingsEvoPtr pTimings, + const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, + const enum NvKmsDpyAttributeColorBpcValue colorBpc, const struct NvKmsModeValidationParams *pParams, NVEvoInfoStringPtr pInfoString, const int head) @@ -4446,6 +4763,8 @@ NvBool nvConstructHwModeTimingsImpCheckEvo( if (timingsParams[head].activeRmId == 0x0) { return FALSE; } + timingsParams[head].pixelDepth = + nvEvoColorSpaceBpcToPixelDepth(colorSpace, colorBpc); timingsParams[head].pTimings = pTimings; timingsParams[head].pUsage = &pTimings->viewPort.guaranteedUsage; @@ -5307,44 +5626,61 @@ static NvBool ConstructHwModeTimingsEvoDfp(const NVDpyEvoRec *pDpyEvo, pViewPortOut); } -NvBool nvDowngradeHwModeTimingsDpPixelDepthEvo( - NVHwModeTimingsEvoPtr pTimings, +static NvBool DowngradeColorBpc( const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, - const enum NvKmsDpyAttributeColorRangeValue colorRange) + enum NvKmsDpyAttributeColorBpcValue *pColorBpc, + enum NvKmsDpyAttributeColorRangeValue *pColorRange) { - /* - * In YUV420, HW is programmed with RGB color space and full color range. - * The color space conversion and color range compression happen in a - * headSurface composite shader. - * - * XXX Add support for - * NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422 over DP. - */ - nvAssert(colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420 || - colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444 || - colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB); - - switch (pTimings->pixelDepth) { - case NVKMS_PIXEL_DEPTH_18_444: - /* Cannot downgrade pixelDepth further. */ - return FALSE; - - case NVKMS_PIXEL_DEPTH_24_444: - /* At depth 18 only RGB and full range are allowed */ - if ((colorSpace != NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB) || - (colorRange != NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_FULL)) { + switch (*pColorBpc) { + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_10: + *pColorBpc = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; + break; + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8: + /* At depth 18 only RGB and full range are allowed */ + if (colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB) { + *pColorBpc = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_6; + *pColorRange = NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_FULL; + } else { + return FALSE; + } + break; + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_UNKNOWN: + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_6: return FALSE; - } - pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_18_444; - break; - case NVKMS_PIXEL_DEPTH_30_444: - pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_24_444; - break; } return TRUE; } +NvBool nvDowngradeColorSpaceAndBpc( + const NVColorFormatInfoRec *pSupportedColorFormats, + enum NvKmsDpyAttributeCurrentColorSpaceValue *pColorSpace, + enum NvKmsDpyAttributeColorBpcValue *pColorBpc, + enum NvKmsDpyAttributeColorRangeValue *pColorRange) +{ + if (DowngradeColorBpc(*pColorSpace, pColorBpc, pColorRange)) { + return TRUE; + } + + switch (*pColorSpace) { + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB: /* fallthrough */ + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444: + if (pSupportedColorFormats->yuv422.maxBpc != + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_UNKNOWN) { + *pColorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422; + *pColorBpc = pSupportedColorFormats->yuv422.maxBpc; + *pColorRange = NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_LIMITED; + return TRUE; + } + break; + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422: /* fallthrough */ + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420: + break; + } + + return FALSE; +} + /* * nvDPValidateModeEvo() - For DP devices handled by the DP lib, check DP * bandwidth and pick the best possible/supported pixel depth to use for @@ -5356,16 +5692,11 @@ NvBool nvDPValidateModeEvo(NVDpyEvoPtr pDpyEvo, const struct NvKmsModeValidationParams *pParams) { NVConnectorEvoPtr pConnectorEvo = pDpyEvo->pConnectorEvo; - /* XXX Add support for - * NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422 over DP. */ - const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace = - (pTimings->yuv420Mode != NV_YUV420_MODE_NONE) ? - NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420 : - NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB; - const enum NvKmsDpyAttributeColorRangeValue colorRange = - (colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB) ? - NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_FULL : - NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_LIMITED; + enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace; + enum NvKmsDpyAttributeColorBpcValue colorBpc; + enum NvKmsDpyAttributeColorRangeValue colorRange; + const NVColorFormatInfoRec supportedColorFormats = + nvGetColorFormatInfo(pDpyEvo); /* Only do this for DP devices. */ if (!nvConnectorUsesDPLib(pConnectorEvo)) { @@ -5377,18 +5708,29 @@ NvBool nvDPValidateModeEvo(NVDpyEvoPtr pDpyEvo, return TRUE; } + if (pTimings->yuv420Mode != NV_YUV420_MODE_NONE) { + colorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420; + colorBpc = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; + } else if (!nvGetDefaultColorSpace(&supportedColorFormats, &colorSpace, + &colorBpc)) { + return FALSE; + } + + if (colorSpace != NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB) { + colorRange = NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_LIMITED; + } else { + colorRange = NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_FULL; + } + nvAssert(nvDpyUsesDPLib(pDpyEvo)); nvAssert(pConnectorEvo->or.type == NV0073_CTRL_SPECIFIC_OR_TYPE_SOR); - nvAssert(pTimings->pixelDepth == NVKMS_PIXEL_DEPTH_30_444 || - pTimings->pixelDepth == NVKMS_PIXEL_DEPTH_24_444 || - pTimings->pixelDepth == NVKMS_PIXEL_DEPTH_18_444); - tryAgain: - if (!nvDPValidateModeForDpyEvo(pDpyEvo, colorSpace, pParams, pTimings)) { - if (nvDowngradeHwModeTimingsDpPixelDepthEvo(pTimings, - colorSpace, colorRange)) { + if (!nvDPValidateModeForDpyEvo(pDpyEvo, colorSpace, colorBpc, pParams, + pTimings)) { + if (nvDowngradeColorSpaceAndBpc(&supportedColorFormats, &colorSpace, + &colorBpc, &colorRange)) { goto tryAgain; } /* @@ -5402,8 +5744,6 @@ NvBool nvDPValidateModeEvo(NVDpyEvoPtr pDpyEvo, return TRUE; } - - /* * Construct the hardware values to program EVO for the specified * NVModeTimings @@ -5450,52 +5790,6 @@ NvBool nvConstructHwModeTimingsEvo(const NVDpyEvoRec *pDpyEvo, TweakTimingsForGsync(pDpyEvo, pTimings, pInfoString, pParams->stereoMode); } - /* Defaults, should match EVO displayClass_02.mfs values for _DEFAULT */ - if (pConnectorEvo->legacyType == NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_CRT) { - pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_30_444; - } else if (pConnectorEvo->legacyType == - NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_DFP) { - - if (pConnectorEvo->signalFormat == NVKMS_CONNECTOR_SIGNAL_FORMAT_DSI) { - switch (pDpyEvo->parsedEdid.info.input.u.digital.bpc) { - case 10: - pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_30_444; - break; - case 6: - pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_18_444; - break; - default: - nvAssert(!"Invalid Pixel Depth for DSI"); - // fall through - case 8: - pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_24_444; - break; - } - } else if (nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo)) { - // Pick displayport pixel depths for raster timings. - // Start off picking best possible depth based on monitor caps - // If the monitor doesn't have an EDID version 1.4 or higher, assume - // it's 8. - if (pDpyEvo->parsedEdid.valid && - pDpyEvo->parsedEdid.info.input.isDigital && - pDpyEvo->parsedEdid.info.version >= NVT_EDID_VER_1_4) { - if (pDpyEvo->parsedEdid.info.input.u.digital.bpc >= 10) { - pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_30_444; - } else if (pDpyEvo->parsedEdid.info.input.u.digital.bpc < 8) { - pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_18_444; - } else { - pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_24_444; - } - } - } else { - /* TMDS default */ - pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_24_444; - } - } - - pTimings->stereo.mode = pParams->stereoMode; - pTimings->stereo.isAegis = pDpyEvo->stereo3DVision.isAegis; - return TRUE; } @@ -6059,6 +6353,7 @@ static void AssignNVEvoIsModePossibleDispInput( } pImpInput->head[head].pTimings = timingsParams[head].pTimings; + pImpInput->head[head].pixelDepth = timingsParams[head].pixelDepth; pImpInput->head[head].displayId = timingsParams[head].activeRmId; pImpInput->head[head].orType = pConnectorEvo->or.type; pImpInput->head[head].pUsage = timingsParams[head].pUsage; @@ -6439,16 +6734,47 @@ static void GetRasterLockPin(NVDispEvoPtr pDispEvo0, NvU32 head0, } } /* GetRasterLockPin */ -static NvU32 -UpdateLUTTimer(NVDispEvoPtr pDispEvo, const NvU32 head, NvBool baseLutEnabled, - NvBool outputLutEnabled) +static void EvoIncrementCurrentLutIndex(NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + const NvBool baseLutEnabled, + const NvBool outputLutEnabled) +{ + NvU32 head; + const int dispIndex = pDispEvo->displayOwner; + NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + const int numLUTs = ARRAY_LEN(pDevEvo->lut.apiHead[apiHead].LUT); + NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].curLUTIndex++; + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].curLUTIndex %= numLUTs; + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].curBaseLutEnabled = baseLutEnabled; + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].curOutputLutEnabled = outputLutEnabled; + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + const NvU32 curLutIndex = + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].curLUTIndex; + NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + + pHeadState->lut.outputLutEnabled = + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].curOutputLutEnabled; + pHeadState->lut.baseLutEnabled = + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].curBaseLutEnabled; + pHeadState->lut.pCurrSurface = + pDevEvo->lut.apiHead[apiHead].LUT[curLutIndex]; + + } +} + +static NvU32 UpdateLUTTimer(NVDispEvoPtr pDispEvo, + const NvU32 apiHead, + const NvBool baseLutEnabled, + const NvBool outputLutEnabled) { NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - const int dispIndex = pDispEvo->displayOwner; - const int numLUTs = ARRAY_LEN(pDevEvo->lut.head[head].LUT); if (!pDevEvo->hal->IsCompNotifierComplete(pDispEvo, - LUTNotifierForHead(head))) { + LUTNotifierForApiHead(apiHead))) { // If the notifier is still pending, then the previous update is still // pending and further LUT changes should continue to go into the third // buffer. Reschedule the timer for another 10 ms. @@ -6456,12 +6782,10 @@ UpdateLUTTimer(NVDispEvoPtr pDispEvo, const NvU32 head, NvBool baseLutEnabled, } // Update the current LUT index and kick off an update. - pDevEvo->lut.head[head].disp[dispIndex].curLUTIndex++; - pDevEvo->lut.head[head].disp[dispIndex].curLUTIndex %= numLUTs; - pDevEvo->lut.head[head].disp[dispIndex].curBaseLutEnabled = baseLutEnabled; - pDevEvo->lut.head[head].disp[dispIndex].curOutputLutEnabled = outputLutEnabled; + EvoIncrementCurrentLutIndex(pDispEvo, apiHead, baseLutEnabled, + outputLutEnabled); - nvEvoUpdateCurrentPalette(pDispEvo, head, TRUE); + EvoUpdateCurrentPalette(pDispEvo, apiHead); // Return 0 to cancel the timer. return 0; @@ -6470,31 +6794,31 @@ UpdateLUTTimer(NVDispEvoPtr pDispEvo, const NvU32 head, NvBool baseLutEnabled, static void UpdateLUTTimerNVKMS(void *dataPtr, NvU32 dataU32) { NVDispEvoPtr pDispEvo = dataPtr; - const NvU32 head = DRF_VAL(UPDATE_LUT_TIMER_NVKMS, _DATAU32, _HEAD, + const NvU32 apiHead = DRF_VAL(UPDATE_LUT_TIMER_NVKMS, _DATAU32, _HEAD, dataU32); const NvBool baseLutEnabled = FLD_TEST_DRF(UPDATE_LUT_TIMER_NVKMS, _DATAU32, _BASE_LUT, _ENABLE, dataU32); const NvBool outputLutEnabled = FLD_TEST_DRF(UPDATE_LUT_TIMER_NVKMS, _DATAU32, _OUTPUT_LUT, _ENABLE, dataU32); - NvU32 ret = UpdateLUTTimer(pDispEvo, head, baseLutEnabled, + NvU32 ret = UpdateLUTTimer(pDispEvo, apiHead, baseLutEnabled, outputLutEnabled); if (ret != 0) { - ScheduleLutUpdate(pDispEvo, head, dataU32, ret * 1000); + ScheduleLutUpdate(pDispEvo, apiHead, dataU32, ret * 1000); } } static void ScheduleLutUpdate(NVDispEvoRec *pDispEvo, - const NvU32 head, const NvU32 data, + const NvU32 apiHead, const NvU32 data, const NvU64 usec) { NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; /* Cancel previous update */ - nvCancelLutUpdateEvo(pDispEvo, head); + nvCancelLutUpdateEvo(pDispEvo, apiHead); /* schedule a new timer */ - pDevEvo->lut.head[head].disp[pDispEvo->displayOwner].updateTimer = + pDevEvo->lut.apiHead[apiHead].disp[pDispEvo->displayOwner].updateTimer = nvkms_alloc_timer(UpdateLUTTimerNVKMS, pDispEvo, data, usec); @@ -6511,7 +6835,6 @@ static inline NvU16 GammaToEvo(NvU16 gamma) static NVEvoLutDataRec *GetNewLutBuffer( const NVDispEvoRec *pDispEvo, - NvU32 head, const struct NvKmsSetLutCommonParams *pParams) { const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; @@ -6588,7 +6911,7 @@ done: /* - * Update the head's LUT with the given colors. + * Update the api head's LUT with the given colors. * * The color LUT is triple-buffered. * @@ -6609,21 +6932,21 @@ done: * kick off an update. No new timer needs to be scheduled. */ -void nvEvoSetLut(NVDispEvoPtr pDispEvo, NvU32 head, NvBool kickoff, +void nvEvoSetLut(NVDispEvoPtr pDispEvo, NvU32 apiHead, NvBool kickoff, const struct NvKmsSetLutCommonParams *pParams) { NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; const int dispIndex = pDispEvo->displayOwner; - const int curLUT = pDevEvo->lut.head[head].disp[dispIndex].curLUTIndex; + const int curLUT = pDevEvo->lut.apiHead[apiHead].disp[dispIndex].curLUTIndex; const NvBool waitForPreviousUpdate = - pDevEvo->lut.head[head].disp[dispIndex].waitForPreviousUpdate; - const int numLUTs = ARRAY_LEN(pDevEvo->lut.head[head].LUT); + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].waitForPreviousUpdate; + const int numLUTs = ARRAY_LEN(pDevEvo->lut.apiHead[apiHead].LUT); const int lutToFill = (curLUT + 1) % numLUTs; - NVLutSurfaceEvoPtr pSurfEvo = pDevEvo->lut.head[head].LUT[lutToFill]; + NVLutSurfaceEvoPtr pSurfEvo = pDevEvo->lut.apiHead[apiHead].LUT[lutToFill]; NvBool baseLutEnabled = - pDevEvo->lut.head[head].disp[dispIndex].curBaseLutEnabled ; + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].curBaseLutEnabled ; NvBool outputLutEnabled = - pDevEvo->lut.head[head].disp[dispIndex].curOutputLutEnabled; + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].curOutputLutEnabled; if (!pParams->input.specified && !pParams->output.specified) { return; @@ -6641,7 +6964,7 @@ void nvEvoSetLut(NVDispEvoPtr pDispEvo, NvU32 head, NvBool kickoff, if ((pParams->input.specified && pParams->input.end != 0) || (pParams->output.specified && pParams->output.enabled)) { - NVEvoLutDataRec *pLUTBuffer = GetNewLutBuffer(pDispEvo, head, pParams); + NVEvoLutDataRec *pLUTBuffer = GetNewLutBuffer(pDispEvo, pParams); if (pLUTBuffer == NULL) { nvEvoLogDev(pDevEvo, EVO_LOG_WARN, @@ -6656,12 +6979,11 @@ void nvEvoSetLut(NVDispEvoPtr pDispEvo, NvU32 head, NvBool kickoff, } /* Kill a pending timer */ - nvCancelLutUpdateEvo(pDispEvo, head); + nvCancelLutUpdateEvo(pDispEvo, apiHead); if (!kickoff) { - pDevEvo->lut.head[head].disp[dispIndex].curBaseLutEnabled = baseLutEnabled; - pDevEvo->lut.head[head].disp[dispIndex].curOutputLutEnabled = outputLutEnabled; - pDevEvo->lut.head[head].disp[dispIndex].curLUTIndex = lutToFill; + EvoIncrementCurrentLutIndex(pDispEvo, apiHead, baseLutEnabled, + outputLutEnabled); return; } @@ -6671,31 +6993,30 @@ void nvEvoSetLut(NVDispEvoPtr pDispEvo, NvU32 head, NvBool kickoff, // is synchronous. NvBool previousUpdateComplete = pDevEvo->hal->IsCompNotifierComplete(pDispEvo, - LUTNotifierForHead(head)); + LUTNotifierForApiHead(apiHead)); if (!waitForPreviousUpdate || previousUpdateComplete || pParams->synchronous) { // Kick off an update now. - pDevEvo->lut.head[head].disp[dispIndex].curLUTIndex = lutToFill; - pDevEvo->lut.head[head].disp[dispIndex].curBaseLutEnabled = baseLutEnabled; - pDevEvo->lut.head[head].disp[dispIndex].curOutputLutEnabled = outputLutEnabled; - nvEvoUpdateCurrentPalette(pDispEvo, head, TRUE); + EvoIncrementCurrentLutIndex(pDispEvo, apiHead, baseLutEnabled, + outputLutEnabled); + EvoUpdateCurrentPalette(pDispEvo, apiHead); // If this LUT update is synchronous, then sync before returning. if (pParams->synchronous && - pDevEvo->lut.head[head].disp[dispIndex].waitForPreviousUpdate) { + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].waitForPreviousUpdate) { pDevEvo->hal->WaitForCompNotifier(pDispEvo, - LUTNotifierForHead(head)); - pDevEvo->lut.head[head].disp[dispIndex].waitForPreviousUpdate = + LUTNotifierForApiHead(apiHead)); + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].waitForPreviousUpdate = FALSE; } } else { // Schedule a timer to kick off an update later. // XXX 5 ms is a guess. We could probably look at this pDpy's refresh // rate to come up with a more reasonable estimate. - NvU32 dataU32 = DRF_NUM(UPDATE_LUT_TIMER_NVKMS, _DATAU32, _HEAD, head); + NvU32 dataU32 = DRF_NUM(UPDATE_LUT_TIMER_NVKMS, _DATAU32, _HEAD, apiHead); - nvAssert((head & ~0xff) == 0); + nvAssert((apiHead & ~0xff) == 0); if (baseLutEnabled) { dataU32 |= DRF_DEF(UPDATE_LUT_TIMER_NVKMS, _DATAU32, _BASE_LUT, @@ -6707,7 +7028,7 @@ void nvEvoSetLut(NVDispEvoPtr pDispEvo, NvU32 head, NvBool kickoff, _ENABLE); } - ScheduleLutUpdate(pDispEvo, head, dataU32, 5 * 1000); + ScheduleLutUpdate(pDispEvo, apiHead, dataU32, 5 * 1000); } } @@ -7546,7 +7867,7 @@ void nvDPSerializerPostSetMode(NVDispEvoPtr pDispEvo, } } -NvBool nvIsHDRCapableHead(NVDispEvoPtr pDispEvo, +NvBool nvIsHDRCapableHead(const NVDispEvoRec *pDispEvo, NvU32 apiHead) { const NVDpyEvoRec *pDpyEvo; @@ -7680,3 +8001,37 @@ NvBool nvIsCscMatrixIdentity(const struct NvKmsCscMatrix *matrix) return TRUE; } + +enum nvKmsPixelDepth nvEvoColorSpaceBpcToPixelDepth( + const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, + const enum NvKmsDpyAttributeColorBpcValue colorBpc) +{ + switch (colorSpace) { + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB: + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444: + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420: + switch (colorBpc) { + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_10: + return NVKMS_PIXEL_DEPTH_30_444; + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8: + return NVKMS_PIXEL_DEPTH_24_444; + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_UNKNOWN: /* fallthrough */ + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_6: + return NVKMS_PIXEL_DEPTH_18_444; + } + break; + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422: + nvAssert(colorBpc != NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_6); + switch (colorBpc) { + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_10: + return NVKMS_PIXEL_DEPTH_20_422; + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_6: /* fallthrough */ + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_UNKNOWN: /* fallthrough */ + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8: + return NVKMS_PIXEL_DEPTH_16_422; + } + break; + } + + return NVKMS_PIXEL_DEPTH_18_444; +} diff --git a/src/nvidia-modeset/src/nvkms-evo1.c b/src/nvidia-modeset/src/nvkms-evo1.c index 3037e5494..01a1bd01d 100644 --- a/src/nvidia-modeset/src/nvkms-evo1.c +++ b/src/nvidia-modeset/src/nvkms-evo1.c @@ -94,6 +94,7 @@ static void InitImpParams(NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS *pImp) static void AssignPerHeadImpParams(const NVDevEvoRec *pDevEvo, NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS *pImp, const NVHwModeTimingsEvo *pTimings, + const enum nvKmsPixelDepth pixelDepth, const struct NvKmsUsageBounds *pUsage, const int head, const int orNumber, @@ -312,7 +313,7 @@ static void AssignPerHeadImpParams(const NVDevEvoRec *pDevEvo, /* pixel depth */ - switch (pTimings->pixelDepth) { + switch (pixelDepth) { case NVKMS_PIXEL_DEPTH_18_444: pImp->Head[head].outputResourcePixelDepthBPP = NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444; @@ -325,6 +326,14 @@ static void AssignPerHeadImpParams(const NVDevEvoRec *pDevEvo, pImp->Head[head].outputResourcePixelDepthBPP = NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444; break; + case NVKMS_PIXEL_DEPTH_16_422: + pImp->Head[head].outputResourcePixelDepthBPP = + NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422; + break; + case NVKMS_PIXEL_DEPTH_20_422: + pImp->Head[head].outputResourcePixelDepthBPP = + NV5070_CTRL_IS_MODE_POSSIBLE_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422; + break; } } @@ -351,6 +360,7 @@ void nvEvo1IsModePossible(NVDispEvoPtr pDispEvo, AssignPerHeadImpParams(pDevEvo, pImp, pInput->head[head].pTimings, + pInput->head[head].pixelDepth, pInput->head[head].pUsage, head, pInput->head[head].orIndex, @@ -533,7 +543,8 @@ NvBool nvEvo1IsChannelMethodPending(NVDevEvoPtr pDevEvo, void nvEvo1SetDscParams(const NVDispEvoRec *pDispEvo, const NvU32 head, - const NVHwModeTimingsEvo *pTimings) + const NVHwModeTimingsEvo *pTimings, + const enum nvKmsPixelDepth pixelDepth) { nvAssert(!pTimings->dpDsc.enable); } diff --git a/src/nvidia-modeset/src/nvkms-evo2.c b/src/nvidia-modeset/src/nvkms-evo2.c index e5f63e421..5761f4202 100644 --- a/src/nvidia-modeset/src/nvkms-evo2.c +++ b/src/nvidia-modeset/src/nvkms-evo2.c @@ -40,8 +40,6 @@ #include // NV917C_BASE_CHANNEL_DMA #include // GK104DispOverlayImmControlPio -#include // NV917C_SET_PRESENT_CONTROL_STEREO_FLIP_MODE -#include // NV917D_HEAD_SET_HDMI_CTRL #include // NV917E_OVERLAY_CHANNEL_DMA #include // NV917C_SET_SPARE_{PRE,POST}_UPDATE_TRAP @@ -108,8 +106,6 @@ static void InitChannelCaps90(NVDevEvoPtr pDevEvo, * that it doesn't exceed 61 bits. */ .validTimeStampBits = 61, - /* The size of the legacy overlay notifier format. */ - .legacyNotifierFormatSizeBytes = NV_DISP_NOTIFICATION_2_SIZEOF, /* Overlay does not support tearing/immediate flips. */ .tearingFlips = FALSE, .vrrTearingFlips = FALSE, @@ -126,22 +122,15 @@ static void InitChannelCaps90(NVDevEvoPtr pDevEvo, * that it doesn't exceed 61 bits. */ .validTimeStampBits = 61, - /* The size of the legacy base format. */ - .legacyNotifierFormatSizeBytes = NV_DISP_BASE_NOTIFIER_1_SIZEOF, /* Base supports tearing/immediate flips. */ .tearingFlips = TRUE, - /* Some 9x7c classes support VRR; may be overridden at runtime. */ - .vrrTearingFlips = FALSE, + /* Base supports VRR tearing flips. */ + .vrrTearingFlips = TRUE, /* Base supports per-eye stereo flips. */ .perEyeStereoFlips = TRUE, }; pChannel->caps = BaseCaps; - - /* Base supports VRR tearing flips for class 917c and up. */ - if (pChannel->hwclass >= NV917C_BASE_CHANNEL_DMA) { - pChannel->caps.vrrTearingFlips = TRUE; - } } } @@ -707,6 +696,10 @@ static NvU32 EvoGetPixelDepth90(const enum nvKmsPixelDepth pixelDepth) return NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444; case NVKMS_PIXEL_DEPTH_30_444: return NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444; + case NVKMS_PIXEL_DEPTH_16_422: + return NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422; + case NVKMS_PIXEL_DEPTH_20_422: + return NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422; } nvAssert(!"Unexpected pixel depth"); return NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444; @@ -715,10 +708,11 @@ static NvU32 EvoGetPixelDepth90(const enum nvKmsPixelDepth pixelDepth) static void EvoHeadSetControlOR90(NVDevEvoPtr pDevEvo, const int head, const NVHwModeTimingsEvo *pTimings, + const enum nvKmsPixelDepth pixelDepth, const NvBool colorSpaceOverride, NVEvoUpdateState *updateState) { - const NvU32 hwPixelDepth = EvoGetPixelDepth90(pTimings->pixelDepth); + const NvU32 hwPixelDepth = EvoGetPixelDepth90(pixelDepth); const NvU16 colorSpaceFlag = nvEvo1GetColorSpaceFlag(pDevEvo, colorSpaceOverride); NVEvoChannelPtr pChannel = pDevEvo->core; @@ -1376,16 +1370,12 @@ EvoPushSetCoreSurfaceMethodsForOneSd(NVDevEvoRec *pDevEvo, const NVFlipCursorEvoHwState *pSdCursorState = &pSdHeadState->cursor; const NVDispEvoRec *pDispEvo = pDevEvo->gpus[sd].pDispEvo; - const int dispIndex = pDispEvo->displayOwner; - NvU8 curLutIndex = pDevEvo->lut.head[head].disp[dispIndex].curLUTIndex; + const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; - NvBool enableOutputLut = - pDevEvo->lut.head[head].disp[dispIndex].curOutputLutEnabled; - NvBool enableBaseLut = - pDevEvo->lut.head[head].disp[dispIndex].curBaseLutEnabled; + NvBool enableOutputLut = pHeadState->lut.outputLutEnabled; + NvBool enableBaseLut = pHeadState->lut.baseLutEnabled; - NVLutSurfaceEvoPtr pCurLutSurfEvo = - pDevEvo->lut.head[head].LUT[curLutIndex]; + NVLutSurfaceEvoPtr pCurLutSurfEvo = pHeadState->lut.pCurrSurface; NvU32 lutCtxdma = pCurLutSurfEvo != NULL ? pCurLutSurfEvo->dispCtxDma : 0x0; @@ -1845,9 +1835,8 @@ needToReprogramCoreSurface(NVDevEvoPtr pDevEvo, const NVSurfaceEvoRec *pNewSurfaceEvo) { const NVDispEvoRec *pDispEvo = pDevEvo->gpus[sd].pDispEvo; - const int dispIndex = pDispEvo->displayOwner; - NvBool enableBaseLut = - pDevEvo->lut.head[head].disp[dispIndex].curBaseLutEnabled; + const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + NvBool enableBaseLut = pHeadState->lut.baseLutEnabled; const NVSurfaceEvoRec *pCurrCoreSurfaceEvo = pDevEvo->pSubDevices[sd]->pCoreChannelSurface[head]; @@ -2613,8 +2602,15 @@ static NvBool EvoGetCapabilities90(NVDevEvoPtr pDevEvo) for (layer = 0; layer < ARRAY_LEN(pDevEvo->caps.layerCaps); layer++) { - pDevEvo->caps.layerCaps[layer].supportsWindowMode = - (layer != NVKMS_MAIN_LAYER); + if (layer != NVKMS_MAIN_LAYER) { + pDevEvo->caps.layerCaps[layer].supportsWindowMode = TRUE; + pDevEvo->caps.legacyNotifierFormatSizeBytes[layer] = + NV_DISP_NOTIFICATION_2_SIZEOF; + } else { + pDevEvo->caps.layerCaps[layer].supportsWindowMode = FALSE; + pDevEvo->caps.legacyNotifierFormatSizeBytes[layer] = + NV_DISP_BASE_NOTIFIER_1_SIZEOF; + } } pDevEvo->caps.cursorCompositionCaps = diff --git a/src/nvidia-modeset/src/nvkms-evo3.c b/src/nvidia-modeset/src/nvkms-evo3.c index 335d5d3a9..f4c9f9d14 100644 --- a/src/nvidia-modeset/src/nvkms-evo3.c +++ b/src/nvidia-modeset/src/nvkms-evo3.c @@ -33,7 +33,6 @@ #include "nvkms-softfloat.h" #include "nvkms-evo.h" #include "nvkms-evo1.h" -#include "nvkms-modeset-types.h" #include "nvkms-prealloc.h" #include "nv-float.h" #include "nvkms-dpy.h" @@ -2078,6 +2077,11 @@ static NvU32 EvoGetPixelDepthC3(const enum nvKmsPixelDepth pixelDepth) return NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444; case NVKMS_PIXEL_DEPTH_30_444: return NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444; + case NVKMS_PIXEL_DEPTH_16_422: + return NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422; + case NVKMS_PIXEL_DEPTH_20_422: + return NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422; + } nvAssert(!"Unexpected pixel depth"); return NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444; @@ -2189,11 +2193,12 @@ static void EvoORSetControlC6(NVDevEvoPtr pDevEvo, static void EvoHeadSetControlORC3(NVDevEvoPtr pDevEvo, const int head, const NVHwModeTimingsEvo *pTimings, + const enum nvKmsPixelDepth pixelDepth, const NvBool colorSpaceOverride, NVEvoUpdateState *updateState) { NVEvoChannelPtr pChannel = pDevEvo->core; - const NvU32 hwPixelDepth = EvoGetPixelDepthC3(pTimings->pixelDepth); + const NvU32 hwPixelDepth = EvoGetPixelDepthC3(pixelDepth); const NvU16 colorSpaceFlag = nvEvo1GetColorSpaceFlag(pDevEvo, colorSpaceOverride); @@ -2216,11 +2221,12 @@ static void EvoHeadSetControlORC3(NVDevEvoPtr pDevEvo, static void EvoHeadSetControlORC5(NVDevEvoPtr pDevEvo, const int head, const NVHwModeTimingsEvo *pTimings, + const enum nvKmsPixelDepth pixelDepth, const NvBool colorSpaceOverride, NVEvoUpdateState *updateState) { NVEvoChannelPtr pChannel = pDevEvo->core; - const NvU32 hwPixelDepth = EvoGetPixelDepthC3(pTimings->pixelDepth); + const NvU32 hwPixelDepth = EvoGetPixelDepthC3(pixelDepth); const NvU16 colorSpaceFlag = nvEvo1GetColorSpaceFlag(pDevEvo, colorSpaceOverride); @@ -2961,6 +2967,9 @@ static NvBool AssignPerHeadImpParams(NVC372_CTRL_IMP_HEAD *pImpHead, pImpHead->bEnableDsc = pTimings->hdmiFrlConfig.dscInfo.bEnableDSC || pTimings->dpDsc.enable; + pImpHead->bYUV420Format = + (pTimings->yuv420Mode == NV_YUV420_MODE_HW); + return TRUE; } @@ -3437,12 +3446,9 @@ EvoProgramSemaphore6(NVDevEvoPtr pDevEvo, acqMode = DRF_DEF(C67E, _SET_SEMAPHORE_CONTROL, _SKIP_ACQ, _TRUE); relMode = DRF_DEF(C67E, _SET_SEMAPHORE_CONTROL, _REL_MODE, _WRITE); value = pHwState->syncObject.u.syncpts.postValue; - /*! increase value in host1x hardware as well */ + /*! increase local max val as well */ if (hCtxDma != 0) { - NvKmsSyncPtOpParams params = { }; - params.incr_max.id = pChannel->postSyncpt.id; - params.incr_max.incr = 1; - nvkms_syncpt_op(NVKMS_SYNCPT_OP_INCR_MAX, ¶ms); + pChannel->postSyncpt.syncptMaxVal++; } } else { if (pHwState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo != NULL) { @@ -3945,7 +3951,7 @@ NVLutSurfaceEvoPtr EvoGetLutSurface3(NVDevEvoPtr pDevEvo, NvU32 win = NV_EVO_CHANNEL_MASK_WINDOW_NUMBER(pChannel->channelMask); NvU32 head = pDevEvo->headForWindow[win]; NvBool found = FALSE; - NvU32 dispIndex = 0; + const NVDispEvoRec *pDispEvo = NULL; NvU32 sd; if ((pHwState->pSurfaceEvo[NVKMS_LEFT] == NULL) || @@ -3977,9 +3983,9 @@ NVLutSurfaceEvoPtr EvoGetLutSurface3(NVDevEvoPtr pDevEvo, for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { if (nvPeekEvoSubDevMask(pDevEvo) & (1 << sd)) { if (found) { - nvAssert(dispIndex == pDevEvo->gpus[sd].pDispEvo->displayOwner); + nvAssert(pDispEvo == pDevEvo->gpus[sd].pDispEvo); } else { - dispIndex = pDevEvo->gpus[sd].pDispEvo->displayOwner; + pDispEvo = pDevEvo->gpus[sd].pDispEvo; found = TRUE; } } @@ -3993,10 +3999,7 @@ NVLutSurfaceEvoPtr EvoGetLutSurface3(NVDevEvoPtr pDevEvo, * in the surface format and curLUTIndex does not change until next * EvoSetLUTContextDma3() call which also makes sure to disable tearing. */ - const NvU32 lutIndex = - pDevEvo->lut.head[head].disp[dispIndex].curLUTIndex; - - return pDevEvo->lut.head[head].LUT[lutIndex]; + return pDispEvo->headState[head].lut.pCurrSurface; } static void @@ -7221,7 +7224,8 @@ EvoConfigureVblankSyncObjectC6(const NVDevEvoPtr pDevEvo, static void EvoSetHdmiFrlDscParams(const NVDispEvoRec *pDispEvo, const NvU32 head, - const NVHwModeTimingsEvo *pTimings) + const NVHwModeTimingsEvo *pTimings, + const enum nvKmsPixelDepth pixelDepth) { NVEvoChannelPtr pChannel = pDispEvo->pDevEvo->core; const HDMI_FRL_CONFIG *pFrl = &pTimings->hdmiFrlConfig; @@ -7232,7 +7236,7 @@ static void EvoSetHdmiFrlDscParams(const NVDispEvoRec *pDispEvo, pFrl->frlRate != HDMI_FRL_DATA_RATE_NONE && pFrl->dscInfo.bEnableDSC); - bpc = nvPixelDepthToBitsPerComponent(pTimings->pixelDepth); + bpc = nvPixelDepthToBitsPerComponent(pixelDepth); if (bpc < 8) { nvAssert(bpc >= 8); bpc = 8; @@ -7338,12 +7342,13 @@ static void EvoSetDpDscParams(const NVDispEvoRec *pDispEvo, static void EvoSetDscParamsC5(const NVDispEvoRec *pDispEvo, const NvU32 head, - const NVHwModeTimingsEvo *pTimings) + const NVHwModeTimingsEvo *pTimings, + const enum nvKmsPixelDepth pixelDepth) { if (pTimings->hdmiFrlConfig.frlRate != HDMI_FRL_DATA_RATE_NONE) { if (pTimings->hdmiFrlConfig.dscInfo.bEnableDSC) { - EvoSetHdmiFrlDscParams(pDispEvo, head, pTimings); + EvoSetHdmiFrlDscParams(pDispEvo, head, pTimings, pixelDepth); } } else if (pTimings->dpDsc.enable) { EvoSetDpDscParams(pDispEvo, head, pTimings); diff --git a/src/nvidia-modeset/src/nvkms-flip.c b/src/nvidia-modeset/src/nvkms-flip.c index 14e38b078..579792455 100644 --- a/src/nvidia-modeset/src/nvkms-flip.c +++ b/src/nvidia-modeset/src/nvkms-flip.c @@ -24,636 +24,23 @@ #include "nvkms-dma.h" #include "nvkms-evo.h" #include "nvkms-flip.h" -#include "nvkms-flip-workarea.h" -#include "nvkms-surface.h" +#include "nvkms-hw-flip.h" +#include "nvkms-utils-flip.h" #include "nvkms-prealloc.h" #include "nvkms-private.h" -#include "nvkms-rm.h" #include "nvkms-vrr.h" -#include "nvkms-cursor.h" -#include "nvkms-types.h" #include "nvkms-dpy.h" -#include "nvkms-lut.h" -#include "nvkms-softfloat.h" - -#include "nvkms-sync.h" - -#include "nvkms-difr.h" - -static void SchedulePostFlipIMPTimer(NVDevEvoPtr pDevEvo); - -// The EVO .mfs file defines the maximum minPresentInterval to be 8. -#define NV_MAX_SWAP_INTERVAL 8 - -/*! - * Assign the elements in an NVSurfaceEvoPtr[NVKMS_MAX_EYES] array. - * - * Use NVEvoApiHandlesRec to translate an - * NvKmsSurfaceHandle[NVKMS_MAX_EYES] array into an an - * NVSurfaceEvoPtr[NVKMS_MAX_EYES] array. - * - * \param[in] pOpenDevSurfaceHandles The client's surfaces. - * \param[in] surfaceHandles The handles naming surfaces. - * \param[out] pSurfaceEvos The surface pointers. - * - * \return Return TRUE if all surfaceHandles could be successfully - * translated into pSurfaceEvos. Otherwise, return FALSE. - */ -NvBool nvAssignSurfaceArray( - const NVDevEvoRec *pDevEvo, - const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, - const NvKmsSurfaceHandle surfaceHandles[NVKMS_MAX_EYES], - const NvBool isUsedByCursorChannel, - const NvBool isUsedByLayerChannel, - NVSurfaceEvoPtr pSurfaceEvos[NVKMS_MAX_EYES]) -{ - NvU32 eye; - - nvkms_memset(pSurfaceEvos, 0, sizeof(NVSurfaceEvoRec *) * NVKMS_MAX_EYES); - - for (eye = 0; eye < NVKMS_MAX_EYES; eye++) { - if (surfaceHandles[eye] != 0) { - pSurfaceEvos[eye] = - nvEvoGetSurfaceFromHandle(pDevEvo, - pOpenDevSurfaceHandles, - surfaceHandles[eye], - isUsedByCursorChannel, - isUsedByLayerChannel); - if ((pSurfaceEvos[eye] == NULL) || - (pSurfaceEvos[eye]->isoType != NVKMS_MEMORY_ISO)) { - return FALSE; - } - } - } - return TRUE; -} - - -/*! - * Assign the NVFlipNIsoSurfaceEvoHwState. - * - * Use the given NvKmsNIsoSurface to populate the - * NVFlipNIsoSurfaceEvoHwState. Validate that NvKmsNIsoSurface - * description is legitimate. - * - * \param[in] pDevEvo The device where the surface will be used. - * \param[in] pOpenDevSurfaceHandles The client's surfaces. - * \param[in] pParamsNIso The client's description of the NISO surface. - * \param[in] notifier Whether the NISO surface is a notifier. - * \param[in] pChannel The channel where the surface will be used. - * \param[out] pNIsoState The NVKMS presentation of the NISO surface. - * - * \return Return TRUE if the NVFlipNIsoSurfaceEvoHwState could be - * assigned and validated. Otherwise, return FALSE and leave - * the NVFlipNIsoSurfaceEvoHwState untouched. - */ -static NvBool AssignNIsoEvoHwState( - const NVDevEvoRec *pDevEvo, - const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, - const struct NvKmsNIsoSurface *pParamsNIso, - const NvBool notifier, /* TRUE=notifier; FALSE=semaphore */ - const NVEvoChannel *pChannel, - NVFlipNIsoSurfaceEvoHwState *pNIsoState) -{ - NVSurfaceEvoPtr pSurfaceEvo; - NvU32 elementSizeInBytes = 0, offsetInBytes, maxBytes; - - nvAssert(pParamsNIso->surfaceHandle != 0); - - pSurfaceEvo = - nvEvoGetSurfaceFromHandle(pDevEvo, - pOpenDevSurfaceHandles, - pParamsNIso->surfaceHandle, - FALSE /* isUsedByCursorChannel */, - TRUE /* isUsedByLayerChannel */); - if (pSurfaceEvo == NULL) { - return FALSE; - } - - /* Attempt to validate the surface: */ - - /* Only pitch surfaces can be used */ - if (pSurfaceEvo->layout != NvKmsSurfaceMemoryLayoutPitch) { - return FALSE; - } - - if (pSurfaceEvo->isoType != NVKMS_MEMORY_NISO) { - return FALSE; - } - - if ((pParamsNIso->format != NVKMS_NISO_FORMAT_FOUR_WORD) && - (pParamsNIso->format != NVKMS_NISO_FORMAT_FOUR_WORD_NVDISPLAY) && - (pParamsNIso->format != NVKMS_NISO_FORMAT_LEGACY)) { - return FALSE; - } - - if ((pDevEvo->caps.validNIsoFormatMask & - (1 << pParamsNIso->format)) == 0) { - return FALSE; - } - - /* Check that the item fits within the surface. */ - switch (pParamsNIso->format) { - case NVKMS_NISO_FORMAT_FOUR_WORD: - case NVKMS_NISO_FORMAT_FOUR_WORD_NVDISPLAY: - elementSizeInBytes = 16; - break; - case NVKMS_NISO_FORMAT_LEGACY: - if (notifier) { - /* Legacy notifier size depends on the channel. */ - elementSizeInBytes = pChannel->caps.legacyNotifierFormatSizeBytes; - } else { - /* Legacy semaphores are always 4 bytes. */ - elementSizeInBytes = 4; - } - break; - } - -#if defined(DEBUG) - /* Assert that the size calculated by nvkms-sync library is the same as the - * one we derived from channel caps above. */ - if (notifier) { - NvBool overlay = !!(pChannel->channelMask & - NV_EVO_CHANNEL_MASK_OVERLAY_ALL); - NvU32 libSize = nvKmsSizeOfNotifier(pParamsNIso->format, overlay); - nvAssert(libSize == elementSizeInBytes); - } else { - nvAssert(nvKmsSizeOfSemaphore(pParamsNIso->format) == elementSizeInBytes); - } -#endif - /* - * offsetInWords is an NvU16 and offsetInBytes is an NvU32, so - * neither of the expressions: - * offsetInWords * 4 - * offsetInBytes + elementSizeInBytes - * should ever overflow. - */ - - ct_assert(sizeof(pParamsNIso->offsetInWords) == 2); - - offsetInBytes = ((NvU32)pParamsNIso->offsetInWords) * 4; - - /* - * Compute the upper extent of the NISO element within the surface. - */ - - maxBytes = offsetInBytes + elementSizeInBytes; - - if (maxBytes > pSurfaceEvo->planes[0].rmObjectSizeInBytes) { - return FALSE; - } - - /* EVO expects the NISO element to fit within a 4k page. */ - - if (maxBytes > 4096) { - return FALSE; - } - - /* - * XXX NVKMS TODO: Check that the surface is in vidmem if - * NV5070_CTRL_SYSTEM_CAPS_BUG_644815_DNISO_VIDMEM_ONLY - */ - - pNIsoState->pSurfaceEvo = pSurfaceEvo; - pNIsoState->format = pParamsNIso->format; - pNIsoState->offsetInWords = pParamsNIso->offsetInWords; - - return TRUE; -} - - -static NvBool AssignCompletionNotifierEvoHwState( - const NVDevEvoRec *pDevEvo, - const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, - const struct NvKmsCompletionNotifierDescription *pParamsNotif, - const NVEvoChannel *pChannel, - NVFlipCompletionNotifierEvoHwState *pNotif) -{ - NvBool ret; - - nvkms_memset(pNotif, 0, sizeof(*pNotif)); - - /* If no surface is specified, we should not use a notifier. */ - if (pParamsNotif->surface.surfaceHandle == 0) { - return TRUE; - } - - ret = AssignNIsoEvoHwState(pDevEvo, - pOpenDevSurfaceHandles, - &pParamsNotif->surface, - TRUE, /* notifier */ - pChannel, - &pNotif->surface); - if (ret) { - pNotif->awaken = pParamsNotif->awaken; - } - - return ret; -} - -static NvBool AssignSemaphoreEvoHwState( - const NVDevEvoRec *pDevEvo, - const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, - const NVEvoChannel *pChannel, - const NvU32 sd, - const struct NvKmsChannelSyncObjects *pChannelSyncObjects, - NVFlipSyncObjectEvoHwState *pFlipSyncObject) -{ - NvBool ret; - - nvAssert(!pChannelSyncObjects->useSyncpt); - - nvkms_memset(pFlipSyncObject, 0, sizeof(*pFlipSyncObject)); - - if (!pDevEvo->hal->caps.supportsIndependentAcqRelSemaphore) { - /*! acquire and release sema surface needs to be same */ - if (pChannelSyncObjects->u.semaphores.acquire.surface.surfaceHandle != - pChannelSyncObjects->u.semaphores.release.surface.surfaceHandle) { - return FALSE; - } - if (pChannelSyncObjects->u.semaphores.acquire.surface.format != - pChannelSyncObjects->u.semaphores.release.surface.format) { - return FALSE; - } - if (pChannelSyncObjects->u.semaphores.acquire.surface.offsetInWords != - pChannelSyncObjects->u.semaphores.release.surface.offsetInWords) { - return FALSE; - } - } - - /*! If no surface is specified, we should not use a semaphore.*/ - if (pChannelSyncObjects->u.semaphores.acquire.surface.surfaceHandle != 0) { - - ret = AssignNIsoEvoHwState( - pDevEvo, - pOpenDevSurfaceHandles, - &pChannelSyncObjects->u.semaphores.acquire.surface, - FALSE, /* notifier */ - pChannel, - &pFlipSyncObject->u.semaphores.acquireSurface); - if (ret) { - pFlipSyncObject->u.semaphores.acquireValue = - pChannelSyncObjects->u.semaphores.acquire.value; - } else { - return ret; - } - } - - /*! If no surface is specified, we should not use a semaphore.*/ - if (pChannelSyncObjects->u.semaphores.release.surface.surfaceHandle != 0) { - - ret = AssignNIsoEvoHwState( - pDevEvo, - pOpenDevSurfaceHandles, - &pChannelSyncObjects->u.semaphores.release.surface, - FALSE, /* notifier */ - pChannel, - &pFlipSyncObject->u.semaphores.releaseSurface); - if (ret) { - pFlipSyncObject->u.semaphores.releaseValue = - pChannelSyncObjects->u.semaphores.release.value; - } else { - return ret; - } - } - - return TRUE; -} - -static NvBool AssignPreSyncptEvoHwState( - const NVDevEvoRec *pDevEvo, - const struct NvKmsChannelSyncObjects *pChannelSyncObjects, - NVFlipSyncObjectEvoHwState *pFlipSyncObject) -{ - NvBool ret; - NvU32 id = 0; - NvU32 value; - enum NvKmsSyncptType preType; - - nvAssert(pChannelSyncObjects->useSyncpt); - - preType = pChannelSyncObjects->u.syncpts.pre.type; - - if (preType == NVKMS_SYNCPT_TYPE_NONE) { - return TRUE; - } - - if (preType == NVKMS_SYNCPT_TYPE_FD) { - /*! Get id from fd using nvhost API */ - NvKmsSyncPtOpParams params = { }; - params.fd_to_id_and_thresh.fd = - pChannelSyncObjects->u.syncpts.pre.u.fd; - ret = nvkms_syncpt_op(NVKMS_SYNCPT_OP_FD_TO_ID_AND_THRESH, - ¶ms); - if (!ret) { - return FALSE; - } - id = params.fd_to_id_and_thresh.id; - value = params.fd_to_id_and_thresh.thresh; - } else { - id = pChannelSyncObjects->u.syncpts.pre.u.raw.id; - value = pChannelSyncObjects->u.syncpts.pre.u.raw.value; - } - if (id >= NV_SYNCPT_GLOBAL_TABLE_LENGTH) { - return FALSE; - } - /*! Fill pre-syncpt related information in hardware state */ - pFlipSyncObject->u.syncpts.preSyncpt = id; - pFlipSyncObject->u.syncpts.preValue = value; - pFlipSyncObject->u.syncpts.isPreSyncptSpecified = TRUE; - pFlipSyncObject->usingSyncpt = TRUE; - - return TRUE; -} - -static NvBool AssignPostSyncptEvoHwState( - const NVDevEvoRec *pDevEvo, - NVEvoChannel *pChannel, - const struct NvKmsChannelSyncObjects *pChannelSyncObjects, - NVFlipSyncObjectEvoHwState *pFlipSyncObject) -{ - enum NvKmsSyncptType postType; - NvU32 threshold; - NvKmsSyncPtOpParams params = { }; - NvBool ret = TRUE; - - nvAssert(pChannelSyncObjects->useSyncpt); - - postType = pChannelSyncObjects->u.syncpts.requestedPostType; - - /*! - * It is possible that syncpt is mentioned but post-syncpt - * is not specified (case where only pre-syncpt used) - */ - if (postType == NVKMS_SYNCPT_TYPE_NONE) { - return TRUE; - } - - - /*! read max value of current syncpt id */ - params.read_maxval.id = pChannel->postSyncpt.id; - ret = nvkms_syncpt_op(NVKMS_SYNCPT_OP_READ_MAXVAL, ¶ms); - if (!ret) { - nvAssert(!"Failed syncpt op READ_MAXVAL"); - return FALSE; - } - - /*! return threshold to caller but increase only when programming hw */ - threshold = params.read_maxval.maxval + 1; - - /*! each channel associated with one post-syncpt */ - pFlipSyncObject->u.syncpts.postCtxDma = pChannel->postSyncpt.hCtxDma; - pFlipSyncObject->u.syncpts.postValue = threshold; - - pFlipSyncObject->usingSyncpt = TRUE; - - return TRUE; -} - -void nvFillPostSyncptReplyOneChannel( - NVEvoChannel *pChannel, - enum NvKmsSyncptType postType, - struct NvKmsSyncpt *postSyncpt, - const NVFlipSyncObjectEvoHwState *pHwSyncObject) -{ - if (postType == NVKMS_SYNCPT_TYPE_RAW) { - postSyncpt->u.raw.id = pChannel->postSyncpt.id; - postSyncpt->u.raw.value = pHwSyncObject->u.syncpts.postValue; - postSyncpt->type = NVKMS_SYNCPT_TYPE_RAW; - } else if (postType == NVKMS_SYNCPT_TYPE_FD) { - NvBool ret = TRUE; - NvKmsSyncPtOpParams params = { }; - params.id_and_thresh_to_fd.id = pChannel->postSyncpt.id; - params.id_and_thresh_to_fd.thresh = - pHwSyncObject->u.syncpts.postValue; - - ret = nvkms_syncpt_op(NVKMS_SYNCPT_OP_ID_AND_THRESH_TO_FD, ¶ms); - if (!ret) { - nvAssert(!"Failed syncpt op ID_AND_THRESH_TO_FD"); - return; - } - postSyncpt->u.fd = params.id_and_thresh_to_fd.fd; - postSyncpt->type = NVKMS_SYNCPT_TYPE_FD; - } -} - -static void FillPostSyncptReply( - NVDevEvoRec *pDevEvo, - NvU32 sd, - const struct NvKmsFlipRequestOneSubDevice *pRequestOneSubDevice, - struct NvKmsFlipReplyOneSubDevice *pReplyOneSubDevice, - const struct NvKmsFlipWorkArea *pWorkArea) -{ - NvU32 head; - - /*! check for valid config */ - if (!pDevEvo->supportsSyncpts) { - return; - } - - for (head = 0; head < ARRAY_LEN(pRequestOneSubDevice->head); head++) { - const struct NvKmsFlipCommonParams *pRequestParams = - &pRequestOneSubDevice->head[head]; - struct NvKmsFlipCommonReplyOneHead *pReplyParams = - &pReplyOneSubDevice->head[head]; - const NVFlipEvoHwState *pFlipState = - &pWorkArea->sd[sd].head[head].newState; - NvU32 layer; - - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if (!pRequestParams->layer[layer].syncObjects.specified || - !pRequestParams->layer[layer].syncObjects.val.useSyncpt) { - continue; - } - - nvFillPostSyncptReplyOneChannel( - pDevEvo->head[head].layer[layer], - pRequestParams->layer[layer].syncObjects.val.u.syncpts.requestedPostType, - &pReplyParams->layer[layer].postSyncpt, - &pFlipState->layer[layer].syncObject); - } - } -} - -static NvBool GetPreSyncptCtxDma(NVDevEvoRec *pDevEvo, - NVEvoChannel *pChannel, const NvU32 id) -{ - NvU32 hSyncptCtxDma, hSyncpt; - - /*! use id value to check the global table */ - if (pDevEvo->preSyncptTable[id].hCtxDma == 0) { - /*! Register - allocate and bind ctxdma to syncpt*/ - if (!nvRmEvoAllocAndBindSyncpt(pDevEvo, - pChannel, - id, - &hSyncpt, - &hSyncptCtxDma)) { - nvAssert(!"Failed to register pre-syncpt"); - return FALSE; - } - - /*! Fill the Entry in Global Table */ - pDevEvo->preSyncptTable[id].hCtxDma = hSyncptCtxDma; - pDevEvo->preSyncptTable[id].hSyncpt = hSyncpt; - pDevEvo->preSyncptTable[id].channelMask |= pChannel->channelMask; - pDevEvo->preSyncptTable[id].id = id; - } else { - /*! - * syncpt found, just bind the context dma of this syncpt - * to the window if it is not already. - */ - if ((pDevEvo->preSyncptTable[id].channelMask & - pChannel->channelMask) == 0) { - - NvU32 ret = - nvRmEvoBindDispContextDMA(pDevEvo, - pChannel, - pDevEvo->preSyncptTable[id].hCtxDma); - if (ret != NVOS_STATUS_SUCCESS) { - nvAssert(!"Failed to bind pre-syncpt with ctxdma"); - } - pDevEvo->preSyncptTable[id].channelMask |= pChannel->channelMask; - /*! hSyncpt already allocated for id*/ - } - } - - return TRUE; -} - -static NvBool RegisterPreSyncpt(NVDevEvoRec *pDevEvo, - struct NvKmsFlipWorkArea *pWorkArea) -{ - NvU32 sd; - NvU32 ret = TRUE; - const NVDispEvoRec *pDispEvo; - - pDevEvo->pAllSyncptUsedInCurrentFlip = - nvCalloc(1, sizeof(NvBool) * NV_SYNCPT_GLOBAL_TABLE_LENGTH); - if (pDevEvo->pAllSyncptUsedInCurrentFlip == NULL) { - ret = FALSE; - goto done; - } - - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - NvU32 head; - for (head = 0; head < ARRAY_LEN(pWorkArea->sd[sd].head); head++) { - NVFlipEvoHwState *pFlipState = - &pWorkArea->sd[sd].head[head].newState; - NvU32 layer; - - for (layer = 0; layer < ARRAY_LEN(pFlipState->layer); layer++) { - NVFlipSyncObjectEvoHwState *pFlipSyncObject = - &pFlipState->layer[layer].syncObject; - NvU32 preSyncpt = pFlipSyncObject->u.syncpts.preSyncpt; - - if (!pFlipState->dirty.layerSyncObjects[layer] || - !pFlipSyncObject->usingSyncpt || - !pFlipSyncObject->u.syncpts.isPreSyncptSpecified) { - continue; - } - - if (!GetPreSyncptCtxDma(pDevEvo, - pDevEvo->head[head].layer[layer], - preSyncpt)) { - ret = FALSE; - goto done; - } - - pDevEvo->pAllSyncptUsedInCurrentFlip[preSyncpt] = NV_TRUE; - } - } - } - -done: - nvFree(pDevEvo->pAllSyncptUsedInCurrentFlip); - pDevEvo->pAllSyncptUsedInCurrentFlip = NULL; - - return ret; -} - -void nvClearFlipEvoHwState( - NVFlipEvoHwState *pFlipState) -{ - NvU32 i; - - nvkms_memset(pFlipState, 0, sizeof(*pFlipState)); - - for (i = 0; i < ARRAY_LEN(pFlipState->layer); i++) { - pFlipState->layer[i].cscMatrix = NVKMS_IDENTITY_CSC_MATRIX; - } -} - -/*! - * Initialize NVFlipEvoHwState with a current snapshot from headState. - */ -void nvInitFlipEvoHwState( - const NVDevEvoRec *pDevEvo, - const NvU32 sd, - const NvU32 head, - NVFlipEvoHwState *pFlipState) -{ - NVDispEvoRec *pDispEvo = pDevEvo->gpus[sd].pDispEvo; - const NVEvoSubDevHeadStateRec *pSdHeadState; - NvU32 i; - - nvClearFlipEvoHwState(pFlipState); - - if (!nvHeadIsActive(pDispEvo, head)) { - return; - } - - pSdHeadState = &pDevEvo->gpus[sd].headState[head]; - - pFlipState->viewPortPointIn = pSdHeadState->viewPortPointIn; - pFlipState->cursor = pSdHeadState->cursor; - - ct_assert(ARRAY_LEN(pFlipState->layer) == ARRAY_LEN(pSdHeadState->layer)); - - for (i = 0; i < ARRAY_LEN(pFlipState->layer); i++) { - pFlipState->layer[i] = pSdHeadState->layer[i]; - } - - // pFlipState->usage describes the usage bounds that will be necessary after - // this flip is complete. Initialize it using pSdHeadState->targetUsage, - // which describes the usage bounds that will be required just before this - // flip occurs, rather than pSdHeadState->usage, which describes the usage - // bounds currently programmed into the hardware. - // - // pSdHeadState->usage may have higher bounds than pSdHeadState->targetUsage - // if TryLoweringUsageBounds has not yet noticed that a satellite channel is - // no longer in use, or a flip to NULL in a satellite channel is pending but - // has not yet occurred. - pFlipState->usage = pSdHeadState->targetUsage; - - pFlipState->disableMidFrameAndDWCFWatermark = - pSdHeadState->targetDisableMidFrameAndDWCFWatermark; -} - - -static NvBool IsLayerDirty(const struct NvKmsFlipCommonParams *pParams, - const NvU32 layer) -{ - return pParams->layer[layer].surface.specified || - pParams->layer[layer].sizeIn.specified || - pParams->layer[layer].sizeOut.specified || - pParams->layer[layer].outputPosition.specified || - pParams->layer[layer].completionNotifier.specified || - pParams->layer[layer].syncObjects.specified || - pParams->layer[layer].compositionParams.specified || - pParams->layer[layer].csc.specified || - pParams->layer[layer].hdr.specified || - pParams->layer[layer].colorspace.specified; -} +#include "nvkms-rm.h" /*! * Check whether the flipPermissions for pOpenDev allow the flipping * requested by NvKmsFlipCommonParams. */ -static NvBool CheckFlipPermissions( +NvBool nvCheckFlipPermissions( const struct NvKmsPerOpenDev *pOpenDev, const NVDevEvoRec *pDevEvo, const NvU32 sd, - const NvU32 head, + const NvU32 apiHead, const struct NvKmsFlipCommonParams *pParams) { const int dispIndex = pDevEvo->gpus[sd].pDispEvo->displayOwner; @@ -661,7 +48,7 @@ static NvBool CheckFlipPermissions( nvGetFlipPermissionsFromOpenDev(pOpenDev); const struct NvKmsModesetPermissions *pModesetPermissions = nvGetModesetPermissionsFromOpenDev(pOpenDev); - const NvU8 allLayersMask = NVBIT(pDevEvo->head[head].numLayers) - 1; + const NvU8 allLayersMask = NVBIT(pDevEvo->apiHead[apiHead].numLayers) - 1; NvU8 layerMask = 0; NvU32 layer; @@ -669,14 +56,14 @@ static NvBool CheckFlipPermissions( nvAssert(pFlipPermissions != NULL); nvAssert(pModesetPermissions != NULL); - layerMask = pFlipPermissions->disp[dispIndex].head[head].layerMask; + layerMask = pFlipPermissions->disp[dispIndex].head[apiHead].layerMask; /* * If the client has modeset permissions for this disp+head, allow * the client to also perform flips on any layer. */ if (!nvDpyIdListIsEmpty(pModesetPermissions->disp[dispIndex]. - head[head].dpyIdList)) { + head[apiHead].dpyIdList)) { layerMask = allLayersMask; } @@ -686,8 +73,8 @@ static NvBool CheckFlipPermissions( return FALSE; } - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if (IsLayerDirty(pParams, layer) && ((layerMask & NVBIT(layer)) == 0)) { + for (layer = 0; layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { + if (nvIsLayerDirty(pParams, layer) && ((layerMask & NVBIT(layer)) == 0)) { return FALSE; } } @@ -695,2322 +82,183 @@ static NvBool CheckFlipPermissions( return TRUE; } -/*! - * Determine whether a base channel flip requires a non-tearing present mode. - * - * EVO requires a non-tearing flip when certain parameters are changing. See - * NV_DISP_BASE_STATE_ERROR_052 in dispClass024XBaseUpdateErrorChecks.mfs. - */ -static NvBool FlipRequiresNonTearingMode( - const NVDevEvoRec *pDevEvo, - const NvU32 head, - const NVFlipChannelEvoHwState *pOld, - const NVFlipChannelEvoHwState *pNew) -{ - // TODO: Do we need to care about the right eye here? The error check - // doesn't. - const NVSurfaceEvoRec *pOldSurf = pOld->pSurfaceEvo[NVKMS_LEFT]; - const NVSurfaceEvoRec *pNewSurf = pNew->pSurfaceEvo[NVKMS_LEFT]; - NvU32 oldHwFormat = 0, newHwFormat = 0; - - if (pOldSurf == NULL || pNewSurf == NULL) { - return TRUE; - } - - // If these functions actually return FALSE at this point, then something is - // really wrong... - if (!pDevEvo->hal->ValidateWindowFormat( - pOldSurf->format, NULL, &oldHwFormat)) { - nvAssert(FALSE); - } - - if (!pDevEvo->hal->ValidateWindowFormat( - pNewSurf->format, NULL, &newHwFormat)) { - nvAssert(FALSE); - } - - // Commented entries are things checked in the .mfs that are not yet - // supported in NVKMS. - return // SuperSample - oldHwFormat != newHwFormat || - // Gamma - // Layout (i.e. frame, field1, or field2) - pOldSurf->widthInPixels != pNewSurf->widthInPixels || - pOldSurf->heightInPixels != pNewSurf->heightInPixels || - pOldSurf->layout != pNewSurf->layout; - // UseGainOfs - // NewBaseLut -- USE_CORE_LUT is programmed in InitChannel* - // NewOutputLut -} - - -/*! - * Apply flip overrides if necessary. - * - * 1. Override swap intervals for VRR. - * 2. If the flip is changing certain parameters, override the tearing mode. - */ -static NvBool ApplyBaseFlipOverrides( - const NVDevEvoRec *pDevEvo, +static void FillPostSyncptReplyOneApiHead( + NVDevEvoRec *pDevEvo, const NvU32 sd, - const NvU32 head, - NVFlipChannelEvoHwState *pNew, - NvBool allowVrr) + const NvU32 apiHead, + const struct NvKmsFlipCommonParams *pRequestParams, + struct NvKmsFlipCommonReplyOneHead *pReplyParams, + const struct NvKmsFlipWorkArea *pWorkArea) { - const NVDispEvoRec *pDispEvo = pDevEvo->gpus[sd].pDispEvo; - const NVFlipChannelEvoHwState *pOld = - &pDevEvo->gpus[sd].headState[head].layer[NVKMS_MAIN_LAYER]; + /* XXX[2Heads1OR] Return per hardware-head post syncpt */ + const NvU32 head = nvGetPrimaryHwHead(pDevEvo->gpus[sd].pDispEvo, apiHead); + NvU32 layer; - // Apply VRR swap interval overrides. - // - // Note that this applies the overrides whenever the client requests VRR and - // VRR is enabled, regardless of whether actually activating it later - // succeeds. - if (allowVrr) { - if (!nvHeadIsActive(pDispEvo, head)) { - // - // XXX If VRR is allowed then modeset should have happened before - // base channel flip, currently we don't know how to do modeset - // and program base channel for VRR at same time. This should be - // revisited as part of bug 1731279. - // - return FALSE; - } - nvApplyVrrBaseFlipOverrides(pDevEvo->gpus[sd].pDispEvo, head, - pOld, pNew); + /*! check for valid config */ + if ((head == NV_INVALID_HEAD) || !pDevEvo->supportsSyncpts) { + return; } - if (!nvHeadIsActive(pDispEvo, head)) { - // - // This is possible when modeset and base flip happening at same time, - // tearing parameter does not make sense in that case, - // it should is disabled. - // - pNew->tearing = FALSE; - } else { - // Force non-tearing mode if EVO requires it. - if (FlipRequiresNonTearingMode(pDevEvo, head, pOld, pNew)) { - pNew->tearing = FALSE; - } - } + for (layer = 0; layer < ARRAY_LEN(pRequestParams->layer); layer++) { + const NVFlipEvoHwState *pFlipState = + &pWorkArea->sd[sd].head[head].newState; - return TRUE; -} - -static NvBool ValidateScalingUsageBounds( - const struct NvKmsScalingUsageBounds *pS, - const struct NvKmsScalingUsageBounds *pMaxS) -{ - return (pS->maxVDownscaleFactor <= pMaxS->maxVDownscaleFactor) && - (pS->maxHDownscaleFactor <= pMaxS->maxHDownscaleFactor) && - (pS->vTaps <= pMaxS->vTaps) && - (!pS->vUpscalingAllowed || pMaxS->vUpscalingAllowed); -} - -/*! - * Validate the requested usage bounds against the specified maximums. - */ -static NvBool ValidateUsageBounds( - const NVDevEvoRec *pDevEvo, - const NvU32 head, - const struct NvKmsUsageBounds *pUsage, - const struct NvKmsUsageBounds *pGuaranteedUsage) -{ - NvU32 i; - - for (i = 0; i < pDevEvo->head[head].numLayers; i++) { - const NvU64 supportedSurfaceFormatsUnion = - pUsage->layer[i].supportedSurfaceMemoryFormats | - pGuaranteedUsage->layer[i].supportedSurfaceMemoryFormats; - - if ((pUsage->layer[i].usable && !pGuaranteedUsage->layer[i].usable) || - (supportedSurfaceFormatsUnion != - pGuaranteedUsage->layer[i].supportedSurfaceMemoryFormats) || - !ValidateScalingUsageBounds(&pUsage->layer[i].scaling, - &pGuaranteedUsage->layer[i].scaling)) { - return FALSE; - } - } - - return TRUE; -} - -/*! - * Assign pFlipState->usage. - */ -static NvBool AssignUsageBounds( - const NVDevEvoRec *pDevEvo, - const NvU32 head, - NVFlipEvoHwState *pFlipState) -{ - struct NvKmsUsageBounds *pUsage = &pFlipState->usage; - int i; - - for (i = 0; i < pDevEvo->head[head].numLayers; i++) { - const NVFlipChannelEvoHwState *pLayerFlipState = &pFlipState->layer[i]; - - nvInitScalingUsageBounds(pDevEvo, &pUsage->layer[i].scaling); - - if (pLayerFlipState->pSurfaceEvo[NVKMS_LEFT]) { - pUsage->layer[i].usable = TRUE; - pUsage->layer[i].supportedSurfaceMemoryFormats = - nvEvoGetFormatsWithEqualOrLowerUsageBound( - pLayerFlipState->pSurfaceEvo[NVKMS_LEFT]->format, - pDevEvo->caps.layerCaps[i].supportedSurfaceMemoryFormats); - - if (pDevEvo->hal->GetWindowScalingCaps) { - const NVEvoScalerCaps *pScalerCaps = - pDevEvo->hal->GetWindowScalingCaps(pDevEvo); - - if (!nvComputeScalingUsageBounds(pScalerCaps, - pLayerFlipState->sizeIn.width, - pLayerFlipState->sizeIn.height, - pLayerFlipState->sizeOut.width, - pLayerFlipState->sizeOut.height, - pLayerFlipState->hTaps, - pLayerFlipState->vTaps, - &pUsage->layer[i].scaling)) { - return FALSE; - } - } - - if (pLayerFlipState->maxDownscaleFactors.specified) { - struct NvKmsScalingUsageBounds *pTargetScaling = - &pFlipState->usage.layer[i].scaling; - - if ((pLayerFlipState->maxDownscaleFactors.vertical < - pTargetScaling->maxVDownscaleFactor) || - (pLayerFlipState->maxDownscaleFactors.horizontal < - pTargetScaling->maxHDownscaleFactor)) { - return FALSE; - } - - pTargetScaling->maxVDownscaleFactor = - pLayerFlipState->maxDownscaleFactors.vertical; - pTargetScaling->maxHDownscaleFactor = - pLayerFlipState->maxDownscaleFactors.horizontal; - } - - } else { - pUsage->layer[i].usable = FALSE; - pUsage->layer[i].supportedSurfaceMemoryFormats = 0; - } - } - - return TRUE; -} - -void -nvOverrideScalingUsageBounds(const NVDevEvoRec *pDevEvo, - NvU32 head, - NVFlipEvoHwState *pFlipState, - const struct NvKmsUsageBounds *pPossibleUsage) -{ - NvU32 i; - - for (i = 0; i < pDevEvo->head[head].numLayers; i++) { - const NVFlipChannelEvoHwState *pLayerFlipState = &pFlipState->layer[i]; - const struct NvKmsScalingUsageBounds *pPossibleScaling = - &pPossibleUsage->layer[i].scaling; - struct NvKmsScalingUsageBounds *pTargetScaling = - &pFlipState->usage.layer[i].scaling; - - if (!pFlipState->usage.layer[i].usable) { + if (!pRequestParams->layer[layer].syncObjects.specified || + !pRequestParams->layer[layer].syncObjects.val.useSyncpt) { continue; } - if (!pLayerFlipState->maxDownscaleFactors.specified) { - const NvU16 possibleV = pPossibleScaling->maxVDownscaleFactor; - const NvU16 possibleH = pPossibleScaling->maxHDownscaleFactor; - NvU16 targetV = pTargetScaling->maxVDownscaleFactor; - NvU16 targetH = pTargetScaling->maxHDownscaleFactor; - - /* - * Calculate max H/V downscale factor by quantizing the range. - * - * E.g., - * max H/V downscale factor supported by HW is 4x for 5-tap and 2x - * for 2-tap mode. If 5-tap mode is required, the target usage bound - * that nvkms will attempt to program will either allow up to 2x - * downscaling, or up to 4x downscaling. If 2-tap mode is required, - * the target usage bound that NVKMS will attempt to program will - * allow up to 2x downscaling. Example: to downscale from 4096x2160 - * -> 2731x864 in 5-tap mode, NVKMS would specify up to 2x for the - * H downscale bound (required is 1.5x), and up to 4x for the V - * downscale bound (required is 2.5x). - */ - if (targetV > NV_EVO_SCALE_FACTOR_1X) { - const NvU16 possibleMid = - NV_EVO_SCALE_FACTOR_1X + ((possibleV - NV_EVO_SCALE_FACTOR_1X) / 2); - - if (targetV <= possibleMid) { - pTargetScaling->maxVDownscaleFactor = possibleMid; - } else { - pTargetScaling->maxVDownscaleFactor = possibleV; - } - } - - if (targetH > NV_EVO_SCALE_FACTOR_1X) { - const NvU16 possibleMid = - NV_EVO_SCALE_FACTOR_1X + ((possibleH - NV_EVO_SCALE_FACTOR_1X) / 2); - - if (targetH <= possibleMid) { - pTargetScaling->maxHDownscaleFactor = possibleMid; - } else { - pTargetScaling->maxHDownscaleFactor = possibleH; - } - } - } - - pTargetScaling->vTaps = pPossibleScaling->vTaps; - pTargetScaling->vUpscalingAllowed = pPossibleScaling->vUpscalingAllowed; + nvFillPostSyncptReplyOneChannel( + pDevEvo->head[head].layer[layer], + pRequestParams->layer[layer].syncObjects.val.u.syncpts.requestedPostType, + &pReplyParams->layer[layer].postSyncpt, + &pFlipState->layer[layer].syncObject); } } -static NvBool FlipTimeStampValidForChannel( - const NVEvoChannel *pChannel, - NvU64 timeStamp) -{ - if (pChannel->caps.validTimeStampBits < 64) { - const NvU64 validTimeStampMask = - NVBIT64(pChannel->caps.validTimeStampBits) - 1; - if ((timeStamp & ~validTimeStampMask) != 0) { - return FALSE; - } - } - return TRUE; -} -static NvBool ValidatePerLayerCompParams( - const struct NvKmsCompositionParams *pCompParams, - const struct NvKmsCompositionCapabilities *pCaps, - NVSurfaceEvoPtr pSurfaceEvo) -{ - const NvKmsSurfaceMemoryFormatInfo *pFormatInfo = (pSurfaceEvo != NULL) ? - nvKmsGetSurfaceMemoryFormatInfo(pSurfaceEvo->format) : NULL; - const enum NvKmsCompositionColorKeySelect colorKeySelect = - pCompParams->colorKeySelect; - NvU32 match; - - if ((pCaps->supportedColorKeySelects & NVBIT(colorKeySelect)) == 0x0) { - return FALSE; - } - - NVKMS_COMPOSITION_FOR_MATCH_BITS(colorKeySelect, match) { - if ((pCaps->colorKeySelect[colorKeySelect].supportedBlendModes[match] & - NVBIT(pCompParams->blendingMode[match])) == 0x0) { - return FALSE; - } - - switch (pCompParams->blendingMode[match]) { - case NVKMS_COMPOSITION_BLENDING_MODE_NON_PREMULT_ALPHA: - case NVKMS_COMPOSITION_BLENDING_MODE_PREMULT_ALPHA: - if (pCompParams->surfaceAlpha != 0) { - return FALSE; - } - break; - default: - break; - } - } - - /* Match and nomatch pixels should not use alpha blending mode at once. */ - if ((colorKeySelect != NVKMS_COMPOSITION_COLOR_KEY_SELECT_DISABLE) && - (NvKmsIsCompositionModeUseAlpha(pCompParams->blendingMode[0])) && - (NvKmsIsCompositionModeUseAlpha(pCompParams->blendingMode[1]))) { - return FALSE; - } - - /* - * If surface is NULL, no further validation required. The composition - * parameters do not take effect if surface is NULL. - */ - if (pFormatInfo == NULL || pFormatInfo->isYUV) { - return TRUE; - } - - /* Disable color keying for 8 Bpp surfaces. */ - if ((colorKeySelect == NVKMS_COMPOSITION_COLOR_KEY_SELECT_SRC) || - (colorKeySelect == NVKMS_COMPOSITION_COLOR_KEY_SELECT_DST)) { - - if (pFormatInfo->rgb.bytesPerPixel > 4) { - return FALSE; - } - } - - return TRUE; -} - -static NvBool UpdateFlipEvoHwStateTf( - const NVDevEvoRec *pDevEvo, +static NvBool UpdateProposedFlipStateOneApiHead( + const NVDispEvoRec *pDispEvo, + const NvU32 apiHead, const struct NvKmsFlipCommonParams *pParams, - NVFlipEvoHwState *pFlipState, - const NvU32 sd, - const NvU32 head) + NVProposedFlipStateOneApiHead *pProposedApiHead) { - if (!pParams->tf.specified) { - return TRUE; - } + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; - // If enabling HDR... - // XXX HDR TODO: Handle other transfer functions - if (pParams->tf.val == NVKMS_OUTPUT_TF_PQ) { - NVDispEvoPtr pDispEvo = pDevEvo->pDispEvo[sd]; + if (pParams->tf.specified) { + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); - // Cannot be an SLI configuration. - // XXX HDR TODO: Test SLI Mosaic + HDR and remove this check - if (pDevEvo->numSubDevices > 1) { - return FALSE; - } + pProposedApiHead->dirty.hdr = TRUE; + pProposedApiHead->hdr.tf = pParams->tf.val; - // Sink must support HDR. - if (!nvIsHDRCapableHead(pDispEvo, nvHardwareHeadToApiHead(head))) { - return FALSE; - } - } - - pFlipState->dirty.tf = TRUE; - pFlipState->tf = pParams->tf.val; - - return TRUE; -} - -static NvBool UpdateFlipEvoHwStateHDRStaticMetadata( - const NVDevEvoRec *pDevEvo, - const struct NvKmsFlipCommonParams *pParams, - NVFlipEvoHwState *pFlipState, - NVFlipChannelEvoHwState *pHwState, - const NvU32 head, - const NvU32 layer) -{ - if (pParams->layer[layer].hdr.specified) { - if (pParams->layer[layer].hdr.enabled) { - // Don't allow enabling HDR on a layer that doesn't support it. - if (!pDevEvo->caps.layerCaps[layer].supportsHDR) { + // If enabling HDR... + // XXX HDR TODO: Handle other transfer functions + if (pParams->tf.val == NVKMS_OUTPUT_TF_PQ) { + // Cannot be an SLI configuration. + // XXX HDR TODO: Test SLI Mosaic + HDR and remove this check + if (pDispEvo->pDevEvo->numSubDevices > 1) { return FALSE; } - pHwState->hdrStaticMetadata.val = - pParams->layer[layer].hdr.staticMetadata; - } - pHwState->hdrStaticMetadata.enabled = pParams->layer[layer].hdr.enabled; - - // Only mark dirty if layer supports HDR, otherwise this is a no-op. - if (pDevEvo->caps.layerCaps[layer].supportsHDR) { - pFlipState->dirty.hdrStaticMetadata = TRUE; - } - } - - return TRUE; -} - -static NvBool UpdateLayerFlipEvoHwStateCommon( - const struct NvKmsPerOpenDev *pOpenDev, - const NVDevEvoRec *pDevEvo, - const NvU32 sd, - const NvU32 head, - const NvU32 layer, - const struct NvKmsFlipCommonParams *pParams, - NVFlipEvoHwState *pFlipState) -{ - const NVEvoChannel *pChannel = pDevEvo->head[head].layer[layer]; - NVFlipChannelEvoHwState *pHwState = &pFlipState->layer[layer]; - const NVEvoApiHandlesRec *pOpenDevSurfaceHandles = - nvGetSurfaceHandlesFromOpenDevConst(pOpenDev); - NvBool ret; - - if (pParams->layer[layer].surface.specified) { - ret = nvAssignSurfaceArray(pDevEvo, - pOpenDevSurfaceHandles, - pParams->layer[layer].surface.handle, - FALSE /* isUsedByCursorChannel */, - TRUE /* isUsedByLayerChannel */, - pHwState->pSurfaceEvo); - if (!ret) { - return FALSE; - } - - /* - * Verify the (rotation, reflectionX, reflectionY) is a - * combination currently supported. - */ - if ((NVBIT(NvKmsRRParamsToCapBit(&pParams->layer[layer].surface.rrParams)) & - pDevEvo->caps.validLayerRRTransforms) == 0) { - return FALSE; - } - pHwState->rrParams = pParams->layer[layer].surface.rrParams; - - } - - /* Verify the timestamp is in the valid range for this channel. */ - if (!FlipTimeStampValidForChannel(pChannel, - pParams->layer[layer].timeStamp)) { - return FALSE; - } - pHwState->timeStamp = pParams->layer[layer].timeStamp; - - if (pParams->layer[layer].syncObjects.specified) { - if (!pDevEvo->supportsSyncpts && - pParams->layer[layer].syncObjects.val.useSyncpt) { - return FALSE; - } - - nvkms_memset(&pFlipState->layer[layer].syncObject, - 0, - sizeof(pFlipState->layer[layer].syncObject)); - - if (pParams->layer[layer].syncObjects.val.useSyncpt) { - ret = AssignPreSyncptEvoHwState(pDevEvo, - &pParams->layer[layer].syncObjects.val, - &pHwState->syncObject); - if (!ret) { - return FALSE; - } - pFlipState->dirty.layerSyncObjects[layer] = TRUE; - - ret = AssignPostSyncptEvoHwState(pDevEvo, - pDevEvo->head[head].layer[layer], - &pParams->layer[layer].syncObjects.val, - &pHwState->syncObject); - if (!ret) { - return FALSE; - } - } else { - if (pParams->layer[layer].syncObjects.val.u.semaphores.acquire.surface.surfaceHandle != 0 || - pParams->layer[layer].syncObjects.val.u.semaphores.release.surface.surfaceHandle != 0) { - if (pParams->layer[layer].skipPendingFlips) { - return FALSE; - } - } - - ret = AssignSemaphoreEvoHwState(pDevEvo, - pOpenDevSurfaceHandles, - pChannel, - sd, - &pParams->layer[layer].syncObjects.val, - &pHwState->syncObject); - if (!ret) { + // Sink must support HDR. + if (!nvIsHDRCapableHead(pDispEvo, apiHead)) { return FALSE; } } - } - if (pHwState->pSurfaceEvo[NVKMS_LEFT]) { - pHwState->minPresentInterval = - pParams->layer[layer].minPresentInterval; - } else { - /* The hardware requires that MPI be 0 when disabled. */ - pHwState->minPresentInterval = 0; - } - - if (pParams->layer[layer].sizeIn.specified) { - pHwState->sizeIn = pParams->layer[layer].sizeIn.val; - } - - if (pParams->layer[layer].sizeOut.specified) { - pHwState->sizeOut = pParams->layer[layer].sizeOut.val; - } - - /* - * If supportsWindowMode = TRUE, the sizeIn/sizeOut dimensions can be - * any arbitrary (valid) values. - * - * If supportsWindowMode = FALSE (legacy EVO main layer), the sizeIn - * /sizeOut dimensions must match the size of the surface for that layer. - * - * Note that if sizeIn/Out dimensions are invalid i.e. with a width or - * height of zero, this will be rejected by a call to - * ValidateFlipChannelEvoHwState() later in the code path. - * - * Note that if scaling is unsupported, i.e. that sizeIn cannot differ - * from sizeOut, then any unsupported configurations will be caught by the - * ComputeWindowScalingTaps() call later on in this function. - */ - if (!pDevEvo->caps.layerCaps[layer].supportsWindowMode && - (pHwState->pSurfaceEvo[NVKMS_LEFT] != NULL)) { - const NVSurfaceEvoRec *pSurfaceEvo = - pHwState->pSurfaceEvo[NVKMS_LEFT]; - - if ((pHwState->sizeIn.width != pSurfaceEvo->widthInPixels) || - (pHwState->sizeIn.height != pSurfaceEvo->heightInPixels)) { - return FALSE; - } - - if ((pHwState->sizeOut.width != pSurfaceEvo->widthInPixels) || - (pHwState->sizeOut.height != pSurfaceEvo->heightInPixels)) { + if (!nvChooseCurrentColorSpaceAndRangeEvo(pDpyEvo, + pApiHeadState->timings.yuv420Mode, + pParams->tf.val, + pDpyEvo->requestedColorSpace, + pDpyEvo->requestedColorRange, + &pProposedApiHead->hdr.colorSpace, + &pProposedApiHead->hdr.colorBpc, + &pProposedApiHead->hdr.colorRange)) { return FALSE; } } /* - * Allow the client to specify non-origin outputPosition only if the - * layer supports window mode. - * - * If window mode is unsupported but the client specifies non-origin - * outputPosition, return FALSE. + * Change in colorSpace and colorBpc is not handled. For DisplayPort, + * colorSpace and colorBpc can not be changed without a modeset. */ - if (pDevEvo->caps.layerCaps[layer].supportsWindowMode) { - if (pParams->layer[layer].outputPosition.specified) { - const NvS16 x = pParams->layer[layer].outputPosition.val.x; - const NvS16 y = pParams->layer[layer].outputPosition.val.y; - if ((pHwState->outputPosition.x != x) || - (pHwState->outputPosition.y != y)) { - pHwState->outputPosition.x = x; - pHwState->outputPosition.y = y; - pFlipState->dirty.layerPosition[layer] = TRUE; - } - } - } else if (pParams->layer[layer].outputPosition.specified && - ((pParams->layer[layer].outputPosition.val.x != 0) || - (pParams->layer[layer].outputPosition.val.y != 0))) { - return FALSE; - } - - if (pParams->layer[layer].compositionParams.specified) { - pHwState->composition = - pParams->layer[layer].compositionParams.val; - } - - if (!UpdateFlipEvoHwStateHDRStaticMetadata( - pDevEvo, pParams, pFlipState, - pHwState, head, layer)) { - return FALSE; - } - - if (pParams->layer[layer].colorspace.specified) { - pHwState->colorspace = - pParams->layer[layer].colorspace.val; - } - - if (pHwState->composition.depth == 0) { - pHwState->composition.depth = - NVKMS_MAX_LAYERS_PER_HEAD - layer; - } - - /* XXX Move ValidatePerLayerCompParams() call to nvValidateFlipEvoHwState() */ - if (!ValidatePerLayerCompParams( - &pHwState->composition, - &pDevEvo->caps.layerCaps[layer].composition, - pHwState->pSurfaceEvo[NVKMS_LEFT])) { - return FALSE; - } - - if (!pDevEvo->hal->ComputeWindowScalingTaps(pDevEvo, - pChannel, - pHwState)) { - return FALSE; - } - - if (pParams->layer[layer].completionNotifier.specified) { - ret = AssignCompletionNotifierEvoHwState( - pDevEvo, - pOpenDevSurfaceHandles, - &pParams->layer[layer].completionNotifier.val, - pChannel, - &pFlipState->layer[layer].completionNotifier); - if (!ret) { - return FALSE; - } - } - - if (pParams->layer[layer].maxDownscaleFactors.specified) { - pFlipState->layer[layer].maxDownscaleFactors.vertical = - pParams->layer[layer].maxDownscaleFactors.vertical; - pFlipState->layer[layer].maxDownscaleFactors.horizontal = - pParams->layer[layer].maxDownscaleFactors.horizontal; - pFlipState->layer[layer].maxDownscaleFactors.specified = TRUE; - } else { - pFlipState->layer[layer].maxDownscaleFactors.vertical = 0; - pFlipState->layer[layer].maxDownscaleFactors.horizontal = 0; - pFlipState->layer[layer].maxDownscaleFactors.specified = FALSE; - } - - pFlipState->dirty.layer[layer] = TRUE; - - return TRUE; -} - -static NvBool UpdateMainLayerFlipEvoHwState( - const struct NvKmsPerOpenDev *pOpenDev, - const NVDevEvoRec *pDevEvo, - const NvU32 sd, - const NvU32 head, - const struct NvKmsFlipCommonParams *pParams, - NVFlipEvoHwState *pFlipState, - NvBool allowVrr) -{ - const NVEvoChannel *pChannel = - pDevEvo->head[head].layer[NVKMS_MAIN_LAYER]; - NVFlipChannelEvoHwState *pHwState = &pFlipState->layer[NVKMS_MAIN_LAYER]; - - if (!IsLayerDirty(pParams, NVKMS_MAIN_LAYER)) { - return TRUE; - } - - if (!UpdateLayerFlipEvoHwStateCommon(pOpenDev, pDevEvo, sd, head, - NVKMS_MAIN_LAYER, - pParams, pFlipState)) { - return FALSE; - } - - if (pParams->layer[NVKMS_MAIN_LAYER].csc.specified) { - if (pParams->layer[NVKMS_MAIN_LAYER].csc.useMain) { - return FALSE; - } else { - pHwState->cscMatrix = pParams->layer[NVKMS_MAIN_LAYER].csc.matrix; - } - } - - if (pParams->layer[NVKMS_MAIN_LAYER].surface.specified) { - if (pParams->layer[NVKMS_MAIN_LAYER].perEyeStereoFlip && - !pChannel->caps.perEyeStereoFlips) { - return FALSE; - } - - pHwState->perEyeStereoFlip = - pParams->layer[NVKMS_MAIN_LAYER].perEyeStereoFlip; - } - - if (pParams->layer[NVKMS_MAIN_LAYER].tearing && !pChannel->caps.tearingFlips) { - return FALSE; - } - - // EVO will throw an invalid argument exception if - // minPresentInterval is too large, or if tearing is enabled and - // it's not zero. - if (pParams->layer[NVKMS_MAIN_LAYER].minPresentInterval > NV_MAX_SWAP_INTERVAL || - (pParams->layer[NVKMS_MAIN_LAYER].tearing && - pParams->layer[NVKMS_MAIN_LAYER].minPresentInterval != 0)) { - return FALSE; - } - - pHwState->tearing = pParams->layer[NVKMS_MAIN_LAYER].tearing; - - if (!ApplyBaseFlipOverrides(pDevEvo, - sd, head, &pFlipState->layer[NVKMS_MAIN_LAYER], - allowVrr)) { - return FALSE; - } - - pFlipState->skipLayerPendingFlips[NVKMS_MAIN_LAYER] = - pParams->layer[NVKMS_MAIN_LAYER].skipPendingFlips; - - return TRUE; -} - -NvBool -nvAssignCursorSurface(const struct NvKmsPerOpenDev *pOpenDev, - const NVDevEvoRec *pDevEvo, - const struct NvKmsSetCursorImageCommonParams *pImgParams, - NVSurfaceEvoPtr *pSurfaceEvo) - -{ - const NVEvoApiHandlesRec *pOpenDevSurfaceHandles = - nvGetSurfaceHandlesFromOpenDevConst(pOpenDev); - NVSurfaceEvoPtr pSurfaceEvos[NVKMS_MAX_EYES] = { }; - - if (!nvGetCursorImageSurfaces(pDevEvo, - pOpenDevSurfaceHandles, - pImgParams, - pSurfaceEvos)) { - return FALSE; - } - - /* XXX NVKMS TODO: add support for stereo cursor */ - if (pSurfaceEvos[NVKMS_RIGHT] != NULL) { - return FALSE; - } - - if (pSurfaceEvos[NVKMS_LEFT] != NULL) { - if (!ValidatePerLayerCompParams(&pImgParams->cursorCompParams, - &pDevEvo->caps.cursorCompositionCaps, - pSurfaceEvos[NVKMS_LEFT])) { - return FALSE; - } - } - - *pSurfaceEvo = pSurfaceEvos[NVKMS_LEFT]; - - return TRUE; -} - -static NvBool UpdateCursorLayerFlipEvoHwState( - const struct NvKmsPerOpenDev *pOpenDev, - const NVDevEvoRec *pDevEvo, - const struct NvKmsFlipCommonParams *pParams, - NVFlipEvoHwState *pFlipState) -{ - if (pParams->cursor.imageSpecified) { - if (!nvAssignCursorSurface(pOpenDev, pDevEvo, &pParams->cursor.image, - &pFlipState->cursor.pSurfaceEvo)) { - return FALSE; - } - - if (pFlipState->cursor.pSurfaceEvo != NULL) { - pFlipState->cursor.cursorCompParams = - pParams->cursor.image.cursorCompParams; - } - - pFlipState->dirty.cursorSurface = TRUE; - } - - if (pParams->cursor.positionSpecified) { - pFlipState->cursor.x = pParams->cursor.position.x; - pFlipState->cursor.y = pParams->cursor.position.y; - - pFlipState->dirty.cursorPosition = TRUE; - } - - return TRUE; -} - -static NvBool UpdateOverlayLayerFlipEvoHwState( - const struct NvKmsPerOpenDev *pOpenDev, - const NVDevEvoRec *pDevEvo, - const NvU32 sd, - const NvU32 head, - const NvU32 layer, - const struct NvKmsFlipCommonParams *pParams, - NVFlipEvoHwState *pFlipState) -{ - NVFlipChannelEvoHwState *pHwState = &pFlipState->layer[layer]; - - nvAssert(layer != NVKMS_MAIN_LAYER); - - if (!IsLayerDirty(pParams, layer)) { - return TRUE; - } - - if (pParams->layer[layer].skipPendingFlips || - pParams->layer[layer].perEyeStereoFlip) { - return FALSE; - } - - if (!UpdateLayerFlipEvoHwStateCommon(pOpenDev, pDevEvo, sd, head, layer, - pParams, pFlipState)) { - return FALSE; - } - - if (pParams->layer[layer].csc.specified) { - if (pParams->layer[layer].csc.useMain) { - if (pFlipState->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[NVKMS_LEFT]) { - pHwState->cscMatrix = - pFlipState->layer[NVKMS_MAIN_LAYER].cscMatrix; - } - } else { - pHwState->cscMatrix = pParams->layer[layer].csc.matrix; - } - } - - return TRUE; -} - -/*! - * Update the NVFlipEvoHwState, using NvKmsFlipCommonParams. - * - * Propagate the requested configuration from NvKmsFlipCommonParams to - * NVFlipEvoHwState, performing steps such as translating from - * NvKmsSurfaceHandle to NVSurfaceEvoRecs. Validate the NvKmsFlipCommonParams - * parameters, but defer more general validation of the resulting - * NVFlipEvoHwState until nvValidateFlipEvoHwState(), which callers must call - * separately. - * - * The NVFlipEvoHwState should first be initialized by calling - * nvInitFlipEvoHwState(). - * - * No NVKMS hardware or software state should be altered here, because - * this function is used before we have decided to commit the proposed - * NVFlipEvoHwState to hardware. - * - * \param[in] pOpenDev The pOpenDev of the client doing the flip. - * \param[in] pDevEvo The device on which the surface image will be set. - * \param[in] sd The subdevice for the flip, as specified by the - * client. - * \param[in] head The head for the flip, as specified by the client. - * \param[in] pParams The requested flip, NvKmsFlipCommonParams. - * \param[in,out] pFlipState The resulting NVFlipEvoHwState. - * \param[in] allowVrr Whether VRR flipping should be allowed. - * \param[in] pPossibleUsage Possible usage. - * - * \return If pFlipState could be updated, return TRUE. - * Otherwise, return FALSE. - */ -NvBool nvUpdateFlipEvoHwState( - const struct NvKmsPerOpenDev *pOpenDev, - const NVDevEvoRec *pDevEvo, - const NvU32 sd, - const NvU32 head, - const struct NvKmsFlipCommonParams *pParams, - NVFlipEvoHwState *pFlipState, - NvBool allowVrr) -{ - NvU32 layer; - - if (!CheckFlipPermissions(pOpenDev, pDevEvo, sd, head, pParams)) { + if ((pProposedApiHead->hdr.colorSpace != + pApiHeadState->attributes.colorSpace) || + (pProposedApiHead->hdr.colorBpc != + pApiHeadState->attributes.colorBpc)) { return FALSE; } if (pParams->viewPortIn.specified) { - pFlipState->dirty.viewPortPointIn = TRUE; - pFlipState->viewPortPointIn = pParams->viewPortIn.point; - } - - if (!UpdateCursorLayerFlipEvoHwState(pOpenDev, pDevEvo, pParams, - pFlipState)) { - return FALSE; - } - - if (!UpdateFlipEvoHwStateTf(pDevEvo, pParams, pFlipState, sd, head)) { - return FALSE; - } - - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if (layer == NVKMS_MAIN_LAYER) { - if (!UpdateMainLayerFlipEvoHwState(pOpenDev, pDevEvo, sd, head, - pParams, pFlipState, allowVrr)) { - return FALSE; - } - continue; - } - - if (!UpdateOverlayLayerFlipEvoHwState(pOpenDev, pDevEvo, sd, head, - layer, pParams, pFlipState)) { - return FALSE; - } - } - - if (!AssignUsageBounds(pDevEvo, head, pFlipState)) { - return FALSE; - } - - /* - * If there is active cursor/cropped-window(overlay) without full screen - * window(base/core) then NVKMS is supposed to disable MidFrame/DWCF - * watermark. - */ - - pFlipState->disableMidFrameAndDWCFWatermark = FALSE; - - if (NV5070_CTRL_SYSTEM_GET_CAP( - pDevEvo->capsBits, - NV5070_CTRL_SYSTEM_CAPS_BUG_2052012_GLITCHY_MCLK_SWITCH) && - !pFlipState->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[NVKMS_LEFT]) { - - if (pFlipState->cursor.pSurfaceEvo != NULL) { - pFlipState->disableMidFrameAndDWCFWatermark = TRUE; - } else { - NvU32 layer; - - /* - * XXX TODO: Check the output size of the overlay in order - * to determine if it will be fullscreen or not. - */ - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if (layer != NVKMS_MAIN_LAYER && - pFlipState->layer[layer].pSurfaceEvo[NVKMS_LEFT] != NULL) { - pFlipState->disableMidFrameAndDWCFWatermark = TRUE; - break; - } - } - } + pProposedApiHead->dirty.viewPortPointIn = TRUE; + pProposedApiHead->viewPortPointIn = pParams->viewPortIn.point; } return TRUE; } -/* - * Checks that if the surface is NULL (i.e. no image will be shown), various - * other elements must be NULL as well. If the surface is not NULL, verifies - * that the sizeIn/Out have nonzero values. - */ -inline static NvBool ValidateFlipChannelEvoHwState( - const NVFlipChannelEvoHwState *pState) +void nvCancelSDRTransitionTimer(NVDispApiHeadStateEvoRec *pApiHeadState) { - if (pState->pSurfaceEvo[NVKMS_LEFT] != NULL) { - /* Verify sizes are valid. */ - if ((pState->sizeIn.width == 0) || (pState->sizeIn.height == 0) || - (pState->sizeOut.width == 0) || (pState->sizeOut.height == 0)) { - return FALSE; - } - - return TRUE; - } - - if (pState->completionNotifier.surface.pSurfaceEvo != NULL) { - return FALSE; - } - - if (!pState->syncObject.usingSyncpt) { - if (pState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo != NULL) { - return FALSE; - } - - if (pState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo != NULL) { - return FALSE; - } - } - - return TRUE; + nvkms_free_timer(pApiHeadState->hdrToSdrTransitionTimer); + pApiHeadState->hdrToSdrTransitionTimer = NULL; } -static NvBool ValidateSurfaceSize( - const NVDevEvoRec *pDevEvo, - const NVSurfaceEvoRec *pSurfaceEvo, - const struct NvKmsRect *sourceFetchRect) +static void SDRTransition(void *dataPtr, NvU32 apiHead) { - NvU8 planeIndex; + NvU32 head; + NVDispEvoRec *pDispEvo = dataPtr; + NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + NVDpyEvoPtr pDpyEvo = + nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); - if ((pSurfaceEvo->widthInPixels > pDevEvo->caps.maxWidthInPixels) || - (pSurfaceEvo->heightInPixels > pDevEvo->caps.maxHeight)) { - return FALSE; + nvCancelSDRTransitionTimer(pApiHeadState); + + if (pDpyEvo == NULL) { + return; } - FOR_ALL_VALID_PLANES(planeIndex, pSurfaceEvo) { + nvAssert(pApiHeadState->hwHeadsMask != 0); - NvU64 planePitch = pSurfaceEvo->planes[planeIndex].pitch; - - /* - * Convert planePitch to units of bytes if it's currently specified in - * units of blocks. Each block is 64-bytes wide. - */ - if (pSurfaceEvo->layout == NvKmsSurfaceMemoryLayoutBlockLinear) { - planePitch <<= NVKMS_BLOCK_LINEAR_LOG_GOB_WIDTH; - } - - if (planePitch > pDevEvo->caps.maxWidthInBytes) { - return FALSE; - } + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + NVDispHeadStateEvoRec *pHeadState = + &pDispEvo->headState[head]; + nvAssert(pHeadState->hdr.outputState == + NVKMS_HDR_OUTPUT_STATE_TRANSITIONING_TO_SDR); + pHeadState->hdr.outputState = NVKMS_HDR_OUTPUT_STATE_SDR; } - if (!pDevEvo->hal->ValidateWindowFormat(pSurfaceEvo->format, - sourceFetchRect, - NULL)) { - return FALSE; - } - - return TRUE; + nvUpdateInfoFrames(pDpyEvo); } -static NvBool -ValidateMainFlipChannelEvoHwState(const NVDevEvoRec *pDevEvo, - const NVFlipChannelEvoHwState *pHwState, - const NVHwModeTimingsEvo *pTimings, - struct NvKmsPoint viewPortPointIn) +static +void ScheduleSDRTransitionTimer(NVDispEvoRec *pDispEvo, const NvU32 apiHead) { - NvU32 eye; - const NVSurfaceEvoRec *pFirstSurfaceEvo = NULL; + NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; - /* - * This struct represents the source fetch rectangle for a given surface, - * and will be populated later as such. This function doesn't explicitly set - * sourceFetchRect.{x,y} because NVKMS currently doesn't support programming - * source fetch offsets, so the init value of 0 should be fine for both of - * these fields. - */ - struct NvKmsRect sourceFetchRect = {0}; + nvAssert(!pApiHeadState->hdrToSdrTransitionTimer); - if (!ValidateFlipChannelEvoHwState(pHwState)) { - return FALSE; - } - - for (eye = 0; eye < NVKMS_MAX_EYES; eye++) { - const NVSurfaceEvoRec *pSurfaceEvo = pHwState->pSurfaceEvo[eye]; - - if (pSurfaceEvo == NULL) { - continue; - } - - if (pFirstSurfaceEvo == NULL) { - pFirstSurfaceEvo = pSurfaceEvo; - } else if (pSurfaceEvo->widthInPixels != - pFirstSurfaceEvo->widthInPixels || - pSurfaceEvo->heightInPixels != - pFirstSurfaceEvo->heightInPixels) { - return FALSE; - } - - sourceFetchRect.width = pHwState->sizeIn.width; - sourceFetchRect.height = pHwState->sizeIn.height; - - if (!ValidateSurfaceSize(pDevEvo, pSurfaceEvo, &sourceFetchRect)) { - return FALSE; - } - - /* The use of A_plus_B_greater_than_C_U16 is only valid if these - * fit in a U16 */ - nvAssert(pSurfaceEvo->widthInPixels <= NV_U16_MAX); - nvAssert(pSurfaceEvo->heightInPixels <= NV_U16_MAX); - /* And the checks above in ValidateSurfaceSize should have - * guaranteed that. */ - nvAssert(pDevEvo->caps.maxWidthInPixels <= NV_U16_MAX); - nvAssert(pDevEvo->caps.maxHeight <= NV_U16_MAX); - - /* - * Validate that the requested viewport parameters fit within the - * specified surface, unless the main layer is allowed to be smaller - * than the viewport. - */ - if (!pDevEvo->caps.layerCaps[NVKMS_MAIN_LAYER].supportsWindowMode) { - if (A_plus_B_greater_than_C_U16(viewPortPointIn.x, - pTimings->viewPort.in.width, - pSurfaceEvo->widthInPixels)) { - return FALSE; - } - - if (A_plus_B_greater_than_C_U16(viewPortPointIn.y, - pTimings->viewPort.in.height, - pSurfaceEvo->heightInPixels)) { - return FALSE; - } - } - } - - return TRUE; -} - -static NvBool -ValidateOverlayFlipChannelEvoHwState(const NVDevEvoRec *pDevEvo, - const NVFlipChannelEvoHwState *pHwState) -{ - const NVSurfaceEvoRec *pSurfaceEvo = pHwState->pSurfaceEvo[NVKMS_LEFT]; - - /* - * This struct represents the source fetch rectangle for a given surface, - * and will be populated later as such. This function doesn't explicitly set - * sourceFetchRect.{x,y} because NVKMS currently doesn't support programming - * source fetch offsets, so the init value of 0 should be fine for both of - * these fields. - */ - struct NvKmsRect sourceFetchRect = {0}; - - if (!ValidateFlipChannelEvoHwState(pHwState)) { - return FALSE; - } - - if (pSurfaceEvo == NULL) { - return TRUE; - } - - sourceFetchRect.width = pHwState->sizeIn.width; - sourceFetchRect.height = pHwState->sizeIn.height; - - if (!ValidateSurfaceSize(pDevEvo, pSurfaceEvo, &sourceFetchRect)) { - return FALSE; - } - - /* Validate input size against surface size. */ - if (pHwState->sizeIn.width > pSurfaceEvo->widthInPixels || - pHwState->sizeIn.height > pSurfaceEvo->heightInPixels) { - return FALSE; - } - - return TRUE; -} - -static NvBool -ValidateHDR(const NVDevEvoRec *pDevEvo, - const NvU32 head, - const NVFlipEvoHwState *pFlipState) -{ - NvU32 staticMetadataCount = 0; - NvU32 layerSupportedCount = 0; - - NvU32 layer; - - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if (pDevEvo->caps.layerCaps[layer].supportsHDR) { - layerSupportedCount++; - } - - if (pFlipState->layer[layer].hdrStaticMetadata.enabled) { - staticMetadataCount++; - - /* - * If HDR static metadata is enabled, we may need TMO. CSC11 will be - * used by NVKMS to convert from linear FP16 LMS to linear FP16 RGB. - * As such, the user-supplied precomp CSC can't be programmed into - * CSC11 in this case. - */ - if (!nvIsCscMatrixIdentity(&pFlipState->layer[layer].cscMatrix)) { - return FALSE; - } - - // Already checked in UpdateFlipEvoHwStateHDRStaticMetadata() - nvAssert(pDevEvo->caps.layerCaps[layer].supportsHDR); - } - } - - // If enabling HDR... - // XXX HDR TODO: Handle other transfer functions - if (pFlipState->tf == NVKMS_OUTPUT_TF_PQ) { - // At least one layer must have static metadata. - if (staticMetadataCount == 0) { - return FALSE; - } - - // At least one layer must support HDR, implied above. - nvAssert(layerSupportedCount != 0); - } - - // Only one layer can specify HDR static metadata. - // XXX HDR TODO: Support multiple layers with HDR static metadata - if (staticMetadataCount > 1) { - return FALSE; - } - - return TRUE; -} - -static NvBool -ValidateColorspace(const NVDevEvoRec *pDevEvo, - const NvU32 head, - const NVFlipEvoHwState *pFlipState) -{ - NvU32 layer; - - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if ((pFlipState->layer[layer].colorspace != - NVKMS_INPUT_COLORSPACE_NONE)) { - - NVSurfaceEvoPtr pSurfaceEvo = - pFlipState->layer[layer].pSurfaceEvo[NVKMS_LEFT]; - const NvKmsSurfaceMemoryFormatInfo *pFormatInfo = - (pSurfaceEvo != NULL) ? - nvKmsGetSurfaceMemoryFormatInfo(pSurfaceEvo->format) : NULL; - - // XXX HDR TODO: Support YUV. - if ((pFormatInfo == NULL) || pFormatInfo->isYUV) { - return FALSE; - } - - // FP16 is only for use with scRGB. - if ((pFlipState->layer[layer].colorspace != - NVKMS_INPUT_COLORSPACE_SCRGB_LINEAR) && - ((pSurfaceEvo->format == - NvKmsSurfaceMemoryFormatRF16GF16BF16AF16) || - (pSurfaceEvo->format == - NvKmsSurfaceMemoryFormatRF16GF16BF16XF16))) { - return FALSE; - } - - // scRGB is only compatible with FP16. - if ((pFlipState->layer[layer].colorspace == - NVKMS_INPUT_COLORSPACE_SCRGB_LINEAR) && - !((pSurfaceEvo->format == - NvKmsSurfaceMemoryFormatRF16GF16BF16AF16) || - (pSurfaceEvo->format == - NvKmsSurfaceMemoryFormatRF16GF16BF16XF16))) { - return FALSE; - } - } - } - - return TRUE; -} - -static NvU32 ValidateCompositionDepth(const NVFlipEvoHwState *pFlipState, - const NvU32 layer) -{ - NvU32 tmpLayer; - - if (pFlipState->layer[layer].pSurfaceEvo[NVKMS_LEFT] == NULL) { - return TRUE; - } - - /* Depth should be different for each of the layers owned by the head */ - for (tmpLayer = 0; tmpLayer < ARRAY_LEN(pFlipState->layer); tmpLayer++) { - if (pFlipState->layer[tmpLayer].pSurfaceEvo[NVKMS_LEFT] == NULL) { - continue; - } - - if ((tmpLayer != layer) && - (pFlipState->layer[tmpLayer].composition.depth == - pFlipState->layer[layer].composition.depth)) { - return FALSE; - } - } - - /* Depth of the main layer should be the greatest one */ - if (pFlipState->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[NVKMS_LEFT] != NULL) { - if (pFlipState->layer[NVKMS_MAIN_LAYER].composition.depth < - pFlipState->layer[layer].composition.depth) { - return FALSE; - } - } - - return TRUE; -} - -/*! - * Perform validation of the the given NVFlipEvoHwState. - */ -NvBool nvValidateFlipEvoHwState( - const NVDevEvoRec *pDevEvo, - const NvU32 head, - const NVHwModeTimingsEvo *pTimings, - const NVFlipEvoHwState *pFlipState) -{ - NvU32 layer; - - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if (!ValidateCompositionDepth(pFlipState, layer)) { - return FALSE; - } - - if (layer == NVKMS_MAIN_LAYER) { - if (!ValidateMainFlipChannelEvoHwState(pDevEvo, - &pFlipState->layer[layer], - pTimings, - pFlipState->viewPortPointIn)) { - return FALSE; - } - } else { - const NVFlipChannelEvoHwState *pMainLayerState = - &pFlipState->layer[NVKMS_MAIN_LAYER]; - - /* - * No overlay layer should be enabled if the main - * layer is disabled. - */ - if ((pMainLayerState->pSurfaceEvo[NVKMS_LEFT] == NULL) && - (pFlipState->layer[layer].pSurfaceEvo[NVKMS_LEFT] != NULL)) { - return FALSE; - } - - if (!pFlipState->dirty.layer[layer]) { - continue; - } - - if (!ValidateOverlayFlipChannelEvoHwState(pDevEvo, - &pFlipState->layer[layer])) { - return FALSE; - } - } - } - - if (!ValidateHDR(pDevEvo, head, pFlipState)) { - return FALSE; - } - - if (!ValidateColorspace(pDevEvo, head, pFlipState)) { - return FALSE; - } - - /* XXX NVKMS TODO: validate cursor x,y against current viewport in? */ - - return ValidateUsageBounds(pDevEvo, - head, - &pFlipState->usage, - &pTimings->viewPort.possibleUsage); -} - -/* - * Record in the updateState that the given channel needs interlocked - * window immediate updates. - */ -static void UpdateWinImmInterlockState(NVDevEvoPtr pDevEvo, - NVEvoUpdateState *updateState, - const NVEvoChannel *pChannel) -{ - const NvU32 subDevMask = nvPeekEvoSubDevMask(pDevEvo); - NvU32 sd; - - for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { - if (subDevMask & (1 << sd)) { - updateState->subdev[sd].winImmInterlockMask |= - pChannel->channelMask; - } - } -} - -/*! - * Record in the updateState that the given channel's method are eligible for - * flip locking. - */ -static void UpdateUpdateFlipLockState(NVDevEvoPtr pDevEvo, - NVEvoUpdateState *updateState, - const NVEvoChannel *pChannel) -{ - const NvU32 subDevMask = nvPeekEvoSubDevMask(pDevEvo); - NvU32 sd; - - for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { - if (subDevMask & (1 << sd)) { - updateState->subdev[sd].flipLockQualifyingMask |= - pChannel->channelMask; - } - } -} - -static void CancelSDRTransitionTimer(NVDispHeadStateEvoRec *pHeadState) -{ - nvkms_free_timer(pHeadState->hdr.sdrTransitionTimer); - pHeadState->hdr.sdrTransitionTimer = NULL; -} - -static void SDRTransition(void *dataPtr, NvU32 head) -{ - NVDispHeadStateEvoRec *pHeadState = dataPtr; - - nvAssert(pHeadState->hdr.outputState == - NVKMS_HDR_OUTPUT_STATE_TRANSITIONING_TO_SDR); - pHeadState->hdr.outputState = NVKMS_HDR_OUTPUT_STATE_SDR; - - if (pHeadState->pConnectorEvo) { - NVConnectorEvoPtr pConnectorEvo = pHeadState->pConnectorEvo; - NVDispEvoPtr pDispEvo = pConnectorEvo->pDispEvo; - NvU32 apiHead = nvHardwareHeadToApiHead(head); - NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; - NVDpyEvoPtr pDpyEvo = - nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); - - nvUpdateInfoFrames(pDpyEvo); - } - - CancelSDRTransitionTimer(pHeadState); -} - -static void ScheduleSDRTransitionTimer(NVDispHeadStateEvoRec *pHeadState, - const NvU32 head) -{ - nvAssert(!pHeadState->hdr.sdrTransitionTimer); - - pHeadState->hdr.sdrTransitionTimer = + pApiHeadState->hdrToSdrTransitionTimer = nvkms_alloc_timer(SDRTransition, - pHeadState, - head, + pDispEvo, + apiHead, 2000000 /* 2 seconds */); } -// Adjust from EDID-encoded maxCLL/maxFALL to actual values in units of 1 cd/m2 -static inline NvU32 MaxCvToVal(NvU32 cv) -{ - // 50*2^(cv/32) - return f64_to_ui32( - f64_mul(ui32_to_f64(50), - nvKmsPow(ui32_to_f64(2), - f64_div(ui32_to_f64(cv), - ui32_to_f64(32)))), softfloat_round_near_even, FALSE); -} - -// Adjust from EDID-encoded minCLL to actual value in units of 0.0001 cd/m2 -static inline NvU32 MinCvToVal(NvU32 cv, NvU32 maxCLL) -{ - // 10,000 * (minCLL = (maxCLL * ((cv/255)^2 / 100))) - return f64_to_ui32( - f64_mul(ui32_to_f64(10000), - f64_mul(ui32_to_f64(maxCLL), - f64_div(nvKmsPow(f64_div(ui32_to_f64(cv), - ui32_to_f64(255)), - ui32_to_f64(2)), - ui32_to_f64(100)))), - softfloat_round_near_even, FALSE); -} - -static void UpdateHDR(NVDevEvoPtr pDevEvo, - const NVFlipEvoHwState *pFlipState, - const NvU32 sd, - const NvU32 head, - NVEvoUpdateState *updateState) -{ - NVDispEvoPtr pDispEvo = pDevEvo->gpus[sd].pDispEvo; - NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; - NvU32 apiHead = nvHardwareHeadToApiHead(head); - NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; - NVDpyEvoRec *pDpyEvo = - nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); - NvBool dirty = FALSE; - - if (pFlipState->dirty.tf) { - // XXX HDR TODO: Handle other transfer functions - if (pFlipState->tf == NVKMS_OUTPUT_TF_PQ) { - pHeadState->hdr.outputState = NVKMS_HDR_OUTPUT_STATE_HDR; - - CancelSDRTransitionTimer(pHeadState); - } else if (pHeadState->hdr.outputState == NVKMS_HDR_OUTPUT_STATE_HDR) { - pHeadState->hdr.outputState = - NVKMS_HDR_OUTPUT_STATE_TRANSITIONING_TO_SDR; - - ScheduleSDRTransitionTimer(pHeadState, head); - } - pHeadState->tf = pFlipState->tf; - - nvChooseCurrentColorSpaceAndRangeEvo( - pHeadState->timings.pixelDepth, - pHeadState->timings.yuv420Mode, - pHeadState->tf, - pDpyEvo->requestedColorSpace, - pDpyEvo->requestedColorRange, - &pApiHeadState->attributes.colorSpace, - &pApiHeadState->attributes.colorRange); - - /* Update hardware's current colorSpace and colorRange */ - nvUpdateCurrentHardwareColorSpaceAndRangeEvo( - pDispEvo, - head, - pApiHeadState->attributes.colorSpace, - pApiHeadState->attributes.colorRange, - updateState); - - dirty = TRUE; - } - - if (pFlipState->dirty.hdrStaticMetadata) { - NvU32 layer; - NvBool found = FALSE; - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - // Populate head with updated static metadata. - if (pFlipState->layer[layer].hdrStaticMetadata.enabled) { - const NVT_EDID_INFO *pInfo = &pDpyEvo->parsedEdid.info; - const NVT_HDR_STATIC_METADATA *pHdrInfo = - &pInfo->hdr_static_metadata_info; - - NvU32 targetMaxCLL = MaxCvToVal(pHdrInfo->max_cll); - - // Send this layer's metadata to the display. - pHeadState->hdr.staticMetadata = - pFlipState->layer[layer].hdrStaticMetadata.val; - - /* - * Prepare for tone mapping. If we expect to tone map and the - * EDID has valid lum values, mirror EDID lum values to prevent - * redundant tone mapping by the display. We will tone map to - * the specified maxCLL. - */ - if (nvNeedsTmoLut(pDevEvo, pDevEvo->head[head].layer[layer], - &pFlipState->layer[layer], - nvGetHDRSrcMaxLum( - &pFlipState->layer[layer]), - targetMaxCLL)) { - NvU32 targetMaxFALL = MaxCvToVal(pHdrInfo->max_fall); - if ((targetMaxCLL > 0) && - (targetMaxCLL <= 10000) && - (targetMaxCLL >= targetMaxFALL)) { - - NvU32 targetMinCLL = MinCvToVal(pHdrInfo->min_cll, - targetMaxCLL); - - pHeadState->hdr.staticMetadata. - maxDisplayMasteringLuminance = targetMaxCLL; - pHeadState->hdr.staticMetadata. - minDisplayMasteringLuminance = targetMinCLL; - pHeadState->hdr.staticMetadata.maxCLL = targetMaxCLL; - pHeadState->hdr.staticMetadata.maxFALL = targetMaxFALL; - } - } - - /* - * Only one layer can currently specify static metadata, - * verified by ValidateHDR(). - * - * XXX HDR TODO: Combine metadata from multiple layers. - */ - nvAssert(!found); - found = TRUE; - } - } - if (!found) { - nvkms_memset(&pHeadState->hdr.staticMetadata, 0, - sizeof(struct NvKmsHDRStaticMetadata)); - } - - dirty = TRUE; - } - - if (dirty) { - // Update OCSC / OLUT - nvEvoUpdateCurrentPalette(pDispEvo, head, FALSE); - - nvUpdateInfoFrames(pDpyEvo); - } -} - -/*! - * Program a flip on all requested layers on the specified head. - * - * This also updates pDispEvo->headState[head], caching what was programmed. - - * \param[in,out] pDispEvo The disp on which the flip should be performed. - * \param[in] head The head on which the flip should be performed. - * \param[in] pFlipState The description of how to update each layer. - * \param[in,out] updateState Indicates which channels require UPDATEs - */ -void nvFlipEvoOneHead( - NVDevEvoPtr pDevEvo, - const NvU32 sd, - const NvU32 head, - const NVFlipEvoHwState *pFlipState, - NvBool allowFlipLock, - NVEvoUpdateState *updateState) -{ - NVDispEvoRec *pDispEvo = pDevEvo->gpus[sd].pDispEvo; - const NvU32 apiHead = nvHardwareHeadToApiHead(head); - const NvU32 subDeviceMask = NVBIT(sd); - const NVDispHeadStateEvoRec *pHeadState = - &pDevEvo->gpus[sd].pDispEvo->headState[head]; - NvBool bypassComposition = pHeadState->bypassComposition; - NVEvoSubDevHeadStateRec *pSdHeadState = - &pDevEvo->gpus[sd].headState[head]; - NvU32 layer; - - /* - * Provide the pre-update hardware state (in pSdHeadState) and the new - * target state (pFlipState) to the HAL implementation so that it has the - * information it needs to implement the workaround for hardware bug - * 2193096, which requires special logic on transitions between NULL and - * non-NULL ctxdmas (and vice versa). - */ - pDevEvo->hal->FlipTransitionWAR(pDevEvo, sd, head, - pSdHeadState, pFlipState, - updateState); - - /* - * Promote the software state first, such that the hardware programming - * paths below see the new state atomically. - */ - if (pFlipState->dirty.viewPortPointIn) { - pSdHeadState->viewPortPointIn = pFlipState->viewPortPointIn; - } - - if (pFlipState->dirty.cursorSurface || pFlipState->dirty.cursorPosition) { - pSdHeadState->cursor = pFlipState->cursor; - } - - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if (pFlipState->dirty.layer[layer]) { - pSdHeadState->layer[layer] = pFlipState->layer[layer]; - } - } - - if (pFlipState->dirty.viewPortPointIn) { - nvSetViewPortPointInEvo(pDevEvo->gpus[sd].pDispEvo, - head, - pFlipState->viewPortPointIn.x, - pFlipState->viewPortPointIn.y, - updateState); - } - - if (pFlipState->dirty.cursorSurface) { - nvPushEvoSubDevMask(pDevEvo, NVBIT(sd)); - pDevEvo->hal->SetCursorImage(pDevEvo, - head, - pSdHeadState->cursor.pSurfaceEvo, - updateState, - &pSdHeadState->cursor.cursorCompParams); - nvPopEvoSubDevMask(pDevEvo); - } - - if (pFlipState->dirty.cursorPosition) { - nvEvoMoveCursorInternal(pDevEvo->gpus[sd].pDispEvo, - head, - pFlipState->cursor.x, - pFlipState->cursor.y); - } - - UpdateHDR(pDevEvo, pFlipState, sd, head, updateState); - - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if (!pFlipState->dirty.layer[layer]) { - continue; - } - - if (pFlipState->dirty.layerPosition[layer]) { - /* Ensure position updates are supported on this layer. */ - nvAssert(pDevEvo->caps.layerCaps[layer].supportsWindowMode); - - pDevEvo->hal->SetImmPointOut(pDevEvo, - pDevEvo->head[head].layer[layer], - sd, - updateState, - pFlipState->layer[layer].outputPosition.x, - pFlipState->layer[layer].outputPosition.y); - - if (pDevEvo->hal->caps.supportsSynchronizedOverlayPositionUpdate) { - UpdateWinImmInterlockState(pDevEvo, updateState, - pDevEvo->head[head].layer[layer]); - } - } - - nvPushEvoSubDevMask(pDevEvo, subDeviceMask); - - /* Inform DIFR about the upcoming flip. */ - if (pDevEvo->pDifrState) { - nvDIFRNotifyFlip(pDevEvo->pDifrState); - } - - pDevEvo->hal->Flip(pDevEvo, - pDevEvo->head[head].layer[layer], - &pFlipState->layer[layer], - updateState, - bypassComposition); - if (layer == NVKMS_MAIN_LAYER && allowFlipLock) { - UpdateUpdateFlipLockState(pDevEvo, updateState, - pDevEvo->head[head].layer[layer]); - } - nvPopEvoSubDevMask(pDevEvo); - } - - pSdHeadState->targetUsage = pFlipState->usage; - - pSdHeadState->targetDisableMidFrameAndDWCFWatermark = - pFlipState->disableMidFrameAndDWCFWatermark; - - pDispEvo->apiHeadState[apiHead].viewPortPointIn = - pSdHeadState->viewPortPointIn; -} - -static void ChangeSurfaceFlipRefCount( - NVDevEvoPtr pDevEvo, - NVSurfaceEvoPtr pSurfaceEvo, - NvBool increase) -{ - if (pSurfaceEvo != NULL) { - if (increase) { - nvEvoIncrementSurfaceRefCnts(pSurfaceEvo); - } else { - nvEvoDecrementSurfaceRefCnts(pSurfaceEvo); - } - } -} - -void nvUpdateSurfacesFlipRefCount( - NVDevEvoPtr pDevEvo, - const NvU32 head, - NVFlipEvoHwState *pFlipState, - NvBool increase) -{ - NvU32 i; - - ChangeSurfaceFlipRefCount( - pDevEvo, - pFlipState->cursor.pSurfaceEvo, - increase); - - for (i = 0; i < pDevEvo->head[head].numLayers; i++) { - NVFlipChannelEvoHwState *pLayerFlipState = &pFlipState->layer[i]; - - ChangeSurfaceFlipRefCount( - pDevEvo, - pLayerFlipState->pSurfaceEvo[NVKMS_LEFT], - increase); - ChangeSurfaceFlipRefCount( - pDevEvo, - pLayerFlipState->pSurfaceEvo[NVKMS_RIGHT], - increase); - ChangeSurfaceFlipRefCount( - pDevEvo, - pLayerFlipState->completionNotifier.surface.pSurfaceEvo, - increase); - - if (!pLayerFlipState->syncObject.usingSyncpt) { - ChangeSurfaceFlipRefCount( - pDevEvo, - pLayerFlipState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo, - increase); - ChangeSurfaceFlipRefCount( - pDevEvo, - pLayerFlipState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo, - increase); - } - } -} - -static void UnionScalingUsageBounds( - const struct NvKmsScalingUsageBounds *a, - const struct NvKmsScalingUsageBounds *b, - struct NvKmsScalingUsageBounds *ret) -{ - ret->maxVDownscaleFactor = NV_MAX(a->maxVDownscaleFactor, - b->maxVDownscaleFactor); - ret->maxHDownscaleFactor = NV_MAX(a->maxHDownscaleFactor, - b->maxHDownscaleFactor); - ret->vTaps = NV_MAX(a->vTaps, b->vTaps); - ret->vUpscalingAllowed = a->vUpscalingAllowed || b->vUpscalingAllowed; -} - -void nvUnionUsageBounds(const struct NvKmsUsageBounds *a, - const struct NvKmsUsageBounds *b, - struct NvKmsUsageBounds *ret) -{ - NvU32 i; - - nvkms_memset(ret, 0, sizeof(*ret)); - - for (i = 0; i < ARRAY_LEN(a->layer); i++) { - nvAssert(a->layer[i].usable == - !!a->layer[i].supportedSurfaceMemoryFormats); - nvAssert(b->layer[i].usable == - !!b->layer[i].supportedSurfaceMemoryFormats); - - ret->layer[i].usable = a->layer[i].usable || b->layer[i].usable; - - ret->layer[i].supportedSurfaceMemoryFormats = - a->layer[i].supportedSurfaceMemoryFormats | - b->layer[i].supportedSurfaceMemoryFormats; - - UnionScalingUsageBounds(&a->layer[i].scaling, - &b->layer[i].scaling, - &ret->layer[i].scaling); - } -} - -NvBool UsageBoundsEqual( - const struct NvKmsUsageBounds *a, - const struct NvKmsUsageBounds *b) -{ - NvU32 layer; - - for (layer = 0; layer < ARRAY_LEN(a->layer); layer++) { - if (!nvEvoLayerUsageBoundsEqual(a, b, layer)) { - return FALSE; - } - } - - return TRUE; -} - -static NvBool AllocatePreFlipBandwidth(NVDevEvoPtr pDevEvo, - struct NvKmsFlipWorkArea *pWorkArea) -{ - NVValidateImpOneDispHeadParamsRec *timingsParams = NULL; - struct NvKmsUsageBounds *currentAndNew = NULL; - struct NvKmsUsageBounds *guaranteedAndCurrent = NULL; - NVDispEvoPtr pDispEvo; - NvU32 head; - NvBool recheckIMP = FALSE; - NvBool ret = TRUE; - - if (!pDevEvo->isSOCDisplay) { - return TRUE; - } - - timingsParams = - nvCalloc(NVKMS_MAX_HEADS_PER_DISP, sizeof(*timingsParams)); - if (timingsParams == NULL) { - return FALSE; - } - - currentAndNew = - nvCalloc(NVKMS_MAX_HEADS_PER_DISP, sizeof(*currentAndNew)); - if (currentAndNew == NULL) { - nvFree(timingsParams); - return FALSE; - } - - guaranteedAndCurrent = - nvCalloc(NVKMS_MAX_HEADS_PER_DISP, sizeof(*guaranteedAndCurrent)); - if (guaranteedAndCurrent == NULL) { - nvFree(timingsParams); - nvFree(currentAndNew); - return FALSE; - } - - pDispEvo = pDevEvo->pDispEvo[0]; - - // SOC Display never has more than one disp - nvAssert(pDevEvo->nDispEvo == 1); - - for (head = 0; head < pDevEvo->numHeads; head++) { - NVDispHeadStateEvoRec *pHeadState = - &pDispEvo->headState[head]; - const struct NvKmsUsageBounds *pCurrent = - &pDevEvo->gpus[0].headState[head].preallocatedUsage; - const struct NvKmsUsageBounds *pNew = - &pWorkArea->sd[0].head[head].newState.usage; - - if (pHeadState->activeRmId == 0) { - continue; - } - - timingsParams[head].pConnectorEvo = pHeadState->pConnectorEvo; - timingsParams[head].activeRmId = pHeadState->activeRmId; - timingsParams[head].pTimings = &pHeadState->timings; - - nvUnionUsageBounds(pCurrent, pNew, ¤tAndNew[head]); - nvUnionUsageBounds(&pHeadState->timings.viewPort.guaranteedUsage, - pCurrent, &guaranteedAndCurrent[head]); - - if (!ValidateUsageBounds(pDevEvo, - head, - pNew, - &guaranteedAndCurrent[head])) { - recheckIMP = TRUE; - } - - nvUnionUsageBounds(&guaranteedAndCurrent[head], pNew, - &guaranteedAndCurrent[head]); - timingsParams[head].pUsage = &guaranteedAndCurrent[head]; - } - - if (recheckIMP) { - ret = nvValidateImpOneDisp(pDispEvo, timingsParams, - FALSE /* requireBootClocks */, - NV_EVO_REALLOCATE_BANDWIDTH_MODE_PRE, - NULL /* pMinIsoBandwidthKBPS */, - NULL /* pMinDramFloorKBPS */); - if (ret) { - for (head = 0; head < pDevEvo->numHeads; head++) { - pDevEvo->gpus[0].headState[head].preallocatedUsage = - currentAndNew[head]; - } - } - } - - nvFree(timingsParams); - nvFree(currentAndNew); - nvFree(guaranteedAndCurrent); - - if (ret) { - nvScheduleLowerDispBandwidthTimer(pDevEvo); - } - - return ret; -} - -/*! - * If the satellite channel is active then pre-NVDisplay hardware does not allow - * to change its usage bounds in non-interlock update. The nvSetUsageBoundsEvo() - * code path for pre-NVDisplay hardware, interlocks the satellite channels with - * the usage bounds update. This makes it essential to poll for - * NO_METHOD_PENDING state of the satellite channels, otherwise blocking - * pre-flip IMP update will also get stuck. - * - * It is not possible to interlock flip-locked satellite channels with the core - * channel usage bounds update; in that case, reject the flip. Do not allow - * client to make any change in surface usage bounds parameters without - * deactivating channel first, if channel is flip-locked. - */ -static NvBool PrepareToDoPreFlipIMP(NVDevEvoPtr pDevEvo, - struct NvKmsFlipWorkArea *pWorkArea) -{ - NvU64 startTime = 0; - NvU32 timeout = 2000000; /* 2 seconds */ - NvU32 sd; - - for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { - NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[sd]; - NvU32 head; - - for (head = 0; head < pDevEvo->numHeads; head++) { - NVEvoHeadControlPtr pHC = - &pEvoSubDev->headControl[head]; - const NVEvoSubDevHeadStateRec *pCurrentFlipState = - &pDevEvo->gpus[sd].headState[head]; - const NVSurfaceEvoRec *pCurrentBaseSurf = - pCurrentFlipState->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[NVKMS_LEFT]; - const struct NvKmsUsageBounds *pCurrentUsage = - &pCurrentFlipState->usage; - - NVFlipEvoHwState *pNewFlipState = - &pWorkArea->sd[sd].head[head].newState; - const NVSurfaceEvoRec *pNewBaseSurf = - pNewFlipState->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[NVKMS_LEFT]; - struct NvKmsUsageBounds *pNewUsage = - &pNewFlipState->usage; - - struct NvKmsUsageBounds *pPreFlipUsage = - &pWorkArea->sd[sd].head[head].preFlipUsage; - - NvU32 layer; - - nvUnionUsageBounds(pNewUsage, pCurrentUsage, pPreFlipUsage); - - if (pDevEvo->hal->caps.supportsNonInterlockedUsageBoundsUpdate) { - /* - * NVDisplay does not interlock the satellite channel - * with its usage bounds update. - */ - continue; - } - - /* - * If head is flip-locked then do not change usage - * bounds while base channel is active. - */ - if (pHC->flipLock && - /* If the base channel is active before and after flip then - * current and new base usage bounds should be same. */ - ((pNewBaseSurf != NULL && - pCurrentBaseSurf != NULL && - !nvEvoLayerUsageBoundsEqual(pCurrentUsage, - pNewUsage, NVKMS_MAIN_LAYER)) || - /* If the base channel is active before flip then current and - * preflip base usage bounds should be same. */ - (pCurrentBaseSurf != NULL && - !nvEvoLayerUsageBoundsEqual(pCurrentUsage, - pPreFlipUsage, NVKMS_MAIN_LAYER)))) { - return FALSE; - } - - /* - * Poll for NO_METHOD_PENDING state if usage - * bounds of the channel are changed. - */ - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if (!nvEvoLayerUsageBoundsEqual(pCurrentUsage, - pPreFlipUsage, layer) && - !nvEvoPollForNoMethodPending(pDevEvo, - sd, - pDevEvo->head[head].layer[layer], - &startTime, - timeout)) { - return FALSE; - } - } - } - } - - return TRUE; -} - -/*! - * Tasks need to perform before triggering flip, they all should be done here. - * - * If necessary, raise usage bounds and/or disable MidFrameAndDWCFWatermark - * (bug 200508242) in the core channel and do an IMP update. - * - * Note that this function only raises usage bounds and/or disables - * MidFrameAndDWCFWatermark, never lowers usage bounds and/or enables - * MidFrameAndDWCFWatermark. This allows it to run before queuing a flip even - * if there are still pending flips in a base channel. - */ -static void PreFlipIMP(NVDevEvoPtr pDevEvo, - const struct NvKmsFlipWorkArea *pWorkArea) -{ - NvU32 head, sd; - NVDispEvoPtr pDispEvo; - - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - NVEvoUpdateState updateState = { }; - NvBool update = FALSE; - - for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { - const NVFlipEvoHwState *pNewState = - &pWorkArea->sd[sd].head[head].newState; - const struct NvKmsUsageBounds *pPreFlipUsage = - &pWorkArea->sd[sd].head[head].preFlipUsage; - struct NvKmsUsageBounds *pCurrentUsage = - &pDevEvo->gpus[sd].headState[head].usage; - - if (!UsageBoundsEqual(pCurrentUsage, pPreFlipUsage)) { - update |= nvSetUsageBoundsEvo(pDevEvo, sd, head, - pPreFlipUsage, &updateState); - } - - if (!pDevEvo->gpus[sd]. - headState[head].disableMidFrameAndDWCFWatermark && - pNewState->disableMidFrameAndDWCFWatermark) { - - nvEnableMidFrameAndDWCFWatermark(pDevEvo, - sd, - head, - FALSE /* enable */, - &updateState); - update = TRUE; - } - } - - if (update) { - nvDoIMPUpdateEvo(pDispEvo, &updateState); - } - } -} - -static void LowerDispBandwidth(void *dataPtr, NvU32 dataU32) -{ - NVValidateImpOneDispHeadParamsRec timingsParams[NVKMS_MAX_HEADS_PER_DISP]; - struct NvKmsUsageBounds *guaranteedAndCurrent; - NVDevEvoPtr pDevEvo = dataPtr; - NVDispEvoPtr pDispEvo; - NvU32 head; - NvBool ret; - - guaranteedAndCurrent = - nvCalloc(1, sizeof(*guaranteedAndCurrent) * NVKMS_MAX_HEADS_PER_DISP); - if (guaranteedAndCurrent == NULL) { - nvAssert(guaranteedAndCurrent != NULL); - return; - } - - nvkms_memset(&timingsParams, 0, sizeof(timingsParams)); - - pDispEvo = pDevEvo->pDispEvo[0]; - - // SOC Display never has more than one disp - nvAssert(pDevEvo->nDispEvo == 1); - - for (head = 0; head < pDevEvo->numHeads; head++) { - NVDispHeadStateEvoRec *pHeadState = - &pDispEvo->headState[head]; - const struct NvKmsUsageBounds *pGuaranteed = - &pHeadState->timings.viewPort.guaranteedUsage; - const struct NvKmsUsageBounds *pCurrent = - &pDevEvo->gpus[0].headState[head].usage; - - if (pHeadState->activeRmId == 0) { - continue; - } - - timingsParams[head].pConnectorEvo = pHeadState->pConnectorEvo; - timingsParams[head].activeRmId = pHeadState->activeRmId; - timingsParams[head].pTimings = &pHeadState->timings; - - nvUnionUsageBounds(pGuaranteed, pCurrent, &guaranteedAndCurrent[head]); - timingsParams[head].pUsage = &guaranteedAndCurrent[head]; - } - - ret = nvValidateImpOneDisp(pDispEvo, timingsParams, - FALSE /* requireBootClocks */, - NV_EVO_REALLOCATE_BANDWIDTH_MODE_POST, - NULL /* pMinIsoBandwidthKBPS */, - NULL /* pMinDramFloorKBPS */); - if (ret) { - for (head = 0; head < pDevEvo->numHeads; head++) { - pDevEvo->gpus[0].headState[head].preallocatedUsage = - pDevEvo->gpus[0].headState[head].usage; - } - } - - nvAssert(ret); - - nvFree(guaranteedAndCurrent); -} - -void nvCancelLowerDispBandwidthTimer(NVDevEvoPtr pDevEvo) -{ - nvkms_free_timer(pDevEvo->lowerDispBandwidthTimer); - pDevEvo->lowerDispBandwidthTimer = NULL; -} - -void nvScheduleLowerDispBandwidthTimer(NVDevEvoPtr pDevEvo) -{ - nvAssert(pDevEvo->isSOCDisplay); - - nvCancelLowerDispBandwidthTimer(pDevEvo); - - pDevEvo->lowerDispBandwidthTimer = - nvkms_alloc_timer(LowerDispBandwidth, - pDevEvo, - 0, /* dataU32 */ - 30000000 /* 30 seconds */); -} - -/*! - * Check whether the core, base, and overlay channels are idle (i.e. no methods - * pending in the corresponding pushbuffer) and lower the usage bounds if - * possible. - */ -static NvBool TryLoweringUsageBoundsOneHead(NVDevEvoPtr pDevEvo, NvU32 sd, - NvU32 head, - NVEvoUpdateState *updateState) -{ - const NVEvoSubDevHeadStateRec *pHeadState = - &pDevEvo->gpus[sd].headState[head]; - const struct NvKmsUsageBounds *pCurrent = &pHeadState->usage; - const struct NvKmsUsageBounds *pTarget = &pHeadState->targetUsage; - struct NvKmsUsageBounds newUsage = *pCurrent; - NvBool changed = FALSE; - NvBool scheduleLater = FALSE; - int i; - - for (i = 0; i < pDevEvo->head[head].numLayers; i++) { - if (pCurrent->layer[i].usable && !pTarget->layer[i].usable) { - NvBool isMethodPending; - - if (pDevEvo->hal->IsChannelMethodPending( - pDevEvo, - pDevEvo->head[head].layer[i], - sd, - &isMethodPending) && !isMethodPending) { - newUsage.layer[i] = pTarget->layer[i]; - changed = TRUE; - } else { - scheduleLater = TRUE; - } - } else if ((pCurrent->layer[i].usable && pTarget->layer[i].usable) && - ((pCurrent->layer[i].supportedSurfaceMemoryFormats != - pTarget->layer[i].supportedSurfaceMemoryFormats) || - (!nvEvoScalingUsageBoundsEqual(&pCurrent->layer[i].scaling, - &pTarget->layer[i].scaling)))) { - NvBool isMethodPending; - - if (pDevEvo->hal->IsChannelMethodPending( - pDevEvo, - pDevEvo->head[head].layer[i], - sd, - &isMethodPending) && !isMethodPending) { - newUsage.layer[i] = pTarget->layer[i]; - changed = TRUE; - } else { - scheduleLater = TRUE; - } - } - } - - if (scheduleLater) { - SchedulePostFlipIMPTimer(pDevEvo); - } - - if (changed) { - changed = nvSetUsageBoundsEvo(pDevEvo, sd, head, &newUsage, - updateState); - } - - return changed; -} - -static NvBool -TryEnablingMidFrameAndDWCFWatermarkOneHead(NVDevEvoPtr pDevEvo, - NvU32 sd, - NvU32 head, - NVEvoUpdateState *updateState) -{ - const NVEvoSubDevHeadStateRec *pHeadState = - &pDevEvo->gpus[sd].headState[head]; - NvBool changed = FALSE; - - if (pHeadState->disableMidFrameAndDWCFWatermark && - !pHeadState->targetDisableMidFrameAndDWCFWatermark) { - - NvBool isIdle; - - if (pDevEvo->hal->IsChannelIdle(pDevEvo, - pDevEvo->head[head].layer[NVKMS_MAIN_LAYER], - sd, - &isIdle) && isIdle) { - nvEnableMidFrameAndDWCFWatermark(pDevEvo, - sd, - head, - TRUE /* enable */, - updateState); - changed = TRUE; - } else { - // Schedule another timer to try again later. - SchedulePostFlipIMPTimer(pDevEvo); - } - } - - return changed; -} - -static void -TryToDoPostFlipIMP(void *dataPtr, NvU32 dataU32) -{ - NVDevEvoPtr pDevEvo = dataPtr; - NvU32 head, sd; - NVDispEvoPtr pDispEvo; - - pDevEvo->postFlipIMPTimer = NULL; - - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - NVEvoUpdateState updateState = { }; - NvBool update = FALSE; - - for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { - if (TryLoweringUsageBoundsOneHead(pDevEvo, sd, head, - &updateState)) { - update = TRUE; - } - - if (TryEnablingMidFrameAndDWCFWatermarkOneHead( - pDevEvo, - sd, - head, - &updateState)) { - update = TRUE; - } - } - - if (update) { - nvDoIMPUpdateEvo(pDispEvo, &updateState); - } - } -} - -static void SchedulePostFlipIMPTimer(NVDevEvoPtr pDevEvo) -{ - if (!pDevEvo->postFlipIMPTimer) { - pDevEvo->postFlipIMPTimer = - nvkms_alloc_timer( - TryToDoPostFlipIMP, - pDevEvo, - 0, /* dataU32 */ - 10000000 /* 10 seconds */); - } -} - -void nvEvoCancelPostFlipIMPTimer(NVDevEvoPtr pDevEvo) -{ - nvkms_free_timer(pDevEvo->postFlipIMPTimer); - pDevEvo->postFlipIMPTimer = NULL; -} - -/*! - * If necessary, schedule a timer to see if usage bounds can be lowered. - */ -static void SchedulePostFlipIMP(NVDevEvoPtr pDevEvo) -{ - NvU32 head, sd; - NVDispEvoPtr pDispEvo; - - // If a timer is already scheduled, do nothing. - if (pDevEvo->postFlipIMPTimer) { - return; - } - - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { - const NVEvoSubDevHeadStateRec *pHeadState = - &pDevEvo->gpus[sd].headState[head]; - - if (!UsageBoundsEqual(&pHeadState->usage, - &pHeadState->targetUsage) || - (pHeadState->disableMidFrameAndDWCFWatermark != - pHeadState->targetDisableMidFrameAndDWCFWatermark)) { - - SchedulePostFlipIMPTimer(pDevEvo); - return; - } - } - } -} - static NvBool GetAllowVrr(const NVDevEvoRec *pDevEvo, - const struct NvKmsFlipRequest *request, + const struct NvKmsFlipRequestOneHead *pFlipHead, + NvU32 numFlipHeads, + NvBool allowVrr, NvBool *pApplyAllowVrr) { - NvU32 sd; + NvU32 sd, i; const NVDispEvoRec *pDispEvo; - NvU32 requestedHeadCount, activeHeadCount, dirtyMainLayerCount; - NvBool allowVrr = request->allowVrr; + const NvU32 requestedApiHeadCount = numFlipHeads; + NvU32 activeApiHeadCount, dirtyMainLayerCount; *pApplyAllowVrr = FALSE; /*! - * Count active and requested heads so we can make a decision about VRR + * Count active heads so we can make a decision about VRR * and register syncpts if specified. */ - requestedHeadCount = activeHeadCount = dirtyMainLayerCount = 0; + activeApiHeadCount = dirtyMainLayerCount = 0; FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - NvU32 head; - const struct NvKmsFlipRequestOneSubDevice *pRequestOneSubDevice = - &request->sd[sd]; - - for (head = 0; head < ARRAY_LEN(pRequestOneSubDevice->head); head++) { - if (nvHeadIsActive(pDispEvo, head)) { - activeHeadCount++; + NvU32 apiHead; + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + if (nvApiHeadIsActive(pDispEvo, apiHead)) { + activeApiHeadCount++; } + } + } - if ((NVBIT(head) & - pRequestOneSubDevice->requestedHeadsBitMask) != 0x0) { - requestedHeadCount++; - - if (IsLayerDirty(&pRequestOneSubDevice->head[head], - NVKMS_MAIN_LAYER)) { - dirtyMainLayerCount++; - } - } + for (i = 0; i < numFlipHeads; i++) { + if (nvIsLayerDirty(&pFlipHead[i].flip, NVKMS_MAIN_LAYER)) { + dirtyMainLayerCount++; } } @@ -3018,8 +266,8 @@ static NvBool GetAllowVrr(const NVDevEvoRec *pDevEvo, * Deactivate VRR if only a subset of the heads are requested or * only a subset of the heads are being flipped. */ - if ((activeHeadCount != requestedHeadCount) || - (activeHeadCount != dirtyMainLayerCount)) { + if ((activeApiHeadCount != requestedApiHeadCount) || + (activeApiHeadCount != dirtyMainLayerCount)) { allowVrr = FALSE; } @@ -3034,84 +282,80 @@ static NvBool GetAllowVrr(const NVDevEvoRec *pDevEvo, return allowVrr; } -static void SkipLayerPendingFlips(NVDevEvoRec *pDevEvo, - const NvBool trashPendingMethods, - const NvBool unblockMethodsInExecutation, - struct NvKmsFlipWorkArea *pWorkArea) +static void FillNvKmsFlipReply(NVDevEvoRec *pDevEvo, + struct NvKmsFlipWorkArea *pWorkArea, + const NvBool applyAllowVrr, + const NvS32 vrrSemaphoreIndex, + const struct NvKmsFlipRequestOneHead *pFlipHead, + NvU32 numFlipHeads, + struct NvKmsFlipReply *reply) { - NvU64 startTime = 0; - const NvU32 timeout = 2000000; /* 2 seconds */ - struct { - struct { - struct { - NvU32 oldAccelMask; - } head[NVKMS_MAX_HEADS_PER_DISP]; - } sd[NVKMS_MAX_SUBDEVICES]; - } accelState = { }; - NvU32 sd, head; + NvU32 i; - for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { - if (!pWorkArea->sd[sd].changed) { - continue; - } - - for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { - const NVFlipEvoHwState *pFlipState = - &pWorkArea->sd[sd].head[head].newState; - - if (!pFlipState->skipLayerPendingFlips[NVKMS_MAIN_LAYER]|| - !pFlipState->dirty.layer[NVKMS_MAIN_LAYER]) { - continue; - } - - pDevEvo->hal->AccelerateChannel( - pDevEvo, - pDevEvo->head[head].layer[NVKMS_MAIN_LAYER], - sd, - trashPendingMethods, - unblockMethodsInExecutation, - &accelState.sd[sd].head[head].oldAccelMask); - } + if (reply == NULL) { + return; } - for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { - if (!pWorkArea->sd[sd].changed) { - continue; + for (i = 0; i < numFlipHeads; i++) { + const NvU32 sd = pFlipHead[i].sd; + const NvU32 apiHead = pFlipHead[i].head; + + FillPostSyncptReplyOneApiHead(pDevEvo, + sd, + apiHead, + &pFlipHead[i].flip, + &reply->flipHead[i], + pWorkArea); + } + + if (applyAllowVrr) { + reply->vrrFlipType = nvGetActiveVrrType(pDevEvo); + reply->vrrSemaphoreIndex = vrrSemaphoreIndex; + } else { + reply->vrrFlipType = NV_KMS_VRR_FLIP_NON_VRR; + reply->vrrSemaphoreIndex = -1; + } +} + +static void InitNvKmsFlipWorkArea(const NVDevEvoRec *pDevEvo, + struct NvKmsFlipWorkArea *pWorkArea) +{ + const NVDispEvoRec *pDispEvo; + NvU32 sd, head, apiHead; + + nvkms_memset(pWorkArea, 0, sizeof(*pWorkArea)); + + /* + * Initialize the work area. Note we take two snapshots of the + * current headState: newState and oldState. newState will + * describe the new configuration. After that is applied, we will + * refer to oldState to identify any surfaces that are no longer + * in use. + */ + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + for (head = 0; head < ARRAY_LEN(pWorkArea->sd[sd].head); head++) { + nvInitFlipEvoHwState(pDevEvo, sd, head, + &pWorkArea->sd[sd].head[head].newState); + nvInitFlipEvoHwState(pDevEvo, sd, head, + &pWorkArea->sd[sd].head[head].oldState); } - for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { - const NVFlipEvoHwState *pFlipState = - &pWorkArea->sd[sd].head[head].newState; + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + NVProposedFlipStateOneApiHead *pProposedApiHead = + &pWorkArea->disp[sd].apiHead[apiHead].proposedFlipState; + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; - if (!pFlipState->skipLayerPendingFlips[NVKMS_MAIN_LAYER] || - !pFlipState->dirty.layer[NVKMS_MAIN_LAYER]) { - continue; - } + pProposedApiHead->hdr.tf = pApiHeadState->tf; + pProposedApiHead->hdr.colorSpace = + pApiHeadState->attributes.colorSpace; + pProposedApiHead->hdr.colorBpc = + pApiHeadState->attributes.colorBpc; + pProposedApiHead->hdr.colorRange = + pApiHeadState->attributes.colorRange; - if (unblockMethodsInExecutation) { - if (!nvEvoPollForNoMethodPending(pDevEvo, - sd, - pDevEvo->head[head].layer[NVKMS_MAIN_LAYER], - &startTime, - timeout)) { - nvAssert(!"Failed to idle the main layer channel"); - } - } else { - if (!nvEvoPollForEmptyChannel(pDevEvo->head[head].layer[NVKMS_MAIN_LAYER], - sd, - &startTime, - timeout)) { - nvAssert(!"Failed to empty the main layer channel"); - } - } - - pDevEvo->hal->ResetChannelAccelerators( - pDevEvo, - pDevEvo->head[head].layer[NVKMS_MAIN_LAYER], - sd, - trashPendingMethods, - unblockMethodsInExecutation, - accelState.sd[sd].head[head].oldAccelMask); + pProposedApiHead->viewPortPointIn = + pApiHeadState->viewPortPointIn; } } } @@ -3137,25 +381,27 @@ static void SkipLayerPendingFlips(NVDevEvoRec *pDevEvo, */ NvBool nvFlipEvo(NVDevEvoPtr pDevEvo, const struct NvKmsPerOpenDev *pOpenDev, - const struct NvKmsFlipRequest *request, + const struct NvKmsFlipRequestOneHead *pFlipHead, + NvU32 numFlipHeads, + NvBool commit, + NvBool requestAllowVrr, struct NvKmsFlipReply *reply, NvBool skipUpdate, NvBool allowFlipLock) { - enum NvKmsVrrFlipType vrrFlipType = NV_KMS_VRR_FLIP_NON_VRR; NvS32 vrrSemaphoreIndex = -1; - NvU32 head, sd; + NvU32 apiHead, sd; NvBool applyAllowVrr = FALSE; NvBool ret = FALSE; NvBool changed = FALSE; NVDispEvoPtr pDispEvo; const NvBool allowVrr = - GetAllowVrr(pDevEvo, request, &applyAllowVrr); + GetAllowVrr(pDevEvo, pFlipHead, numFlipHeads, + requestAllowVrr, &applyAllowVrr); struct NvKmsFlipWorkArea *pWorkArea = nvPreallocGet(pDevEvo, PREALLOC_TYPE_FLIP_WORK_AREA, sizeof(*pWorkArea)); - - nvkms_memset(pWorkArea, 0, sizeof(*pWorkArea)); + NvU32 i; /* * Do not execute NVKMS_IOCTL_FLIP if the display channel yet has not @@ -3169,78 +415,48 @@ NvBool nvFlipEvo(NVDevEvoPtr pDevEvo, goto done; } - /* - * Initialize the work area. Note we take two snapshots of the - * current headState: newState and oldState. newState will - * describe the new configuration. After that is applied, we will - * refer to oldState to identify any surfaces that are no longer - * in use. - */ - - for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { - for (head = 0; head < ARRAY_LEN(pWorkArea->sd[sd].head); head++) { - nvInitFlipEvoHwState(pDevEvo, sd, head, - &pWorkArea->sd[sd].head[head].newState); - nvInitFlipEvoHwState(pDevEvo, sd, head, - &pWorkArea->sd[sd].head[head].oldState); - } - } + InitNvKmsFlipWorkArea(pDevEvo, pWorkArea); /* Validate the flip parameters and update the work area. */ - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + for (i = 0; i < numFlipHeads; i++) { + const NvU32 apiHead = pFlipHead[i].head; + const NvU32 sd = pFlipHead[i].sd; + NVDispEvoPtr pDispEvo = pDevEvo->pDispEvo[sd]; + NvU32 head; + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; - const struct NvKmsFlipRequestOneSubDevice *pRequestOneSubDevice = - &request->sd[sd]; - - for (head = 0; head < ARRAY_LEN(pRequestOneSubDevice->head); head++) { - const NVDispHeadStateEvoRec *pHeadState; - const struct NvKmsUsageBounds *pPossibleUsage; - const NvBool headActive = nvHeadIsActive(pDispEvo, head); - - if (!(NVBIT(head) & pRequestOneSubDevice->requestedHeadsBitMask)) { - continue; - } - - if (!headActive) { - goto done; - } - - pHeadState = &pDispEvo->headState[head]; - pPossibleUsage = &pHeadState->timings.viewPort.possibleUsage; - - if (!nvUpdateFlipEvoHwState( - pOpenDev, - pDevEvo, - sd, - head, - &pRequestOneSubDevice->head[head], - &pWorkArea->sd[sd].head[head].newState, - allowVrr)) { - goto done; - } - - nvOverrideScalingUsageBounds(pDevEvo, - head, - &pWorkArea->sd[sd].head[head].newState, - pPossibleUsage); - - if (!nvValidateFlipEvoHwState( - pDevEvo, - head, - &pHeadState->timings, - &pWorkArea->sd[sd].head[head].newState)) { - goto done; - } - - if (!nvSetTmoLutSurfacesEvo(pDevEvo, - &pWorkArea->sd[sd].head[head].newState, - head)) { - goto done; - } - - pWorkArea->sd[sd].changed = TRUE; - changed = TRUE; + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { + goto done; } + + if (!nvCheckFlipPermissions(pOpenDev, pDevEvo, sd, apiHead, + &pFlipHead[i].flip)) { + goto done; + } + + if (!UpdateProposedFlipStateOneApiHead( + pDispEvo, + apiHead, + &pFlipHead[i].flip, + &pWorkArea->disp[sd].apiHead[apiHead].proposedFlipState)) { + goto done; + } + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + if (!nvAssignNVFlipEvoHwState(pDevEvo, + pOpenDev, + sd, + head, + &pFlipHead[i].flip, + allowVrr, + &pWorkArea->sd[sd].head[head].newState)) { + goto done; + } + } + + pWorkArea->sd[sd].changed = TRUE; + changed = TRUE; } /* If nothing changed, fail. */ @@ -3249,21 +465,17 @@ NvBool nvFlipEvo(NVDevEvoPtr pDevEvo, goto done; } - ret = AllocatePreFlipBandwidth(pDevEvo, pWorkArea); + ret = nvAllocatePreFlipBandwidth(pDevEvo, pWorkArea); if (!ret) { goto done; } - if (!request->commit) { + if (!commit) { ret = NV_TRUE; goto done; } - if (!RegisterPreSyncpt(pDevEvo, pWorkArea)) { - goto done; - } - - if (!PrepareToDoPreFlipIMP(pDevEvo, pWorkArea)) { + if (!nvPrepareToDoPreFlip(pDevEvo, pWorkArea)) { goto done; } @@ -3276,39 +488,7 @@ NvBool nvFlipEvo(NVDevEvoPtr pDevEvo, ret = TRUE; - for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { - - if (!pWorkArea->sd[sd].changed) { - continue; - } - - for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { - // Increase refCnt of surfaces used AFTER flip - nvUpdateSurfacesFlipRefCount( - pDevEvo, - head, - &pWorkArea->sd[sd].head[head].newState, - NV_TRUE); - - nvRefTmoLutSurfacesEvo( - pDevEvo, - &pWorkArea->sd[sd].head[head].newState, - head); - } - } - - PreFlipIMP(pDevEvo, pWorkArea); - - if (!skipUpdate) { - /* Trash flips pending in channel which are not yet in execution */ - SkipLayerPendingFlips(pDevEvo, TRUE /* trashPendingMethods */, - FALSE /* unblockMethodsInExecutation */, - pWorkArea); - } - - if (applyAllowVrr) { - nvSetVrrActive(pDevEvo, allowVrr); - } + nvPreFlip(pDevEvo, pWorkArea, applyAllowVrr, allowVrr, skipUpdate); for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { NVEvoUpdateState updateState = { }; @@ -3319,66 +499,71 @@ NvBool nvFlipEvo(NVDevEvoPtr pDevEvo, pDispEvo = pDevEvo->gpus[sd].pDispEvo; - for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { - nvFlipEvoOneHead(pDevEvo, sd, head, - &pWorkArea->sd[sd].head[head].newState, - allowFlipLock, - &updateState); + for (apiHead = 0; apiHead < NVKMS_MAX_HEADS_PER_DISP; apiHead++) { + NvU32 head; + const NVProposedFlipStateOneApiHead *pProposedApiHead = + &pWorkArea->disp[sd].apiHead[apiHead].proposedFlipState; + NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); + const NVT_EDID_INFO *pInfo = &pDpyEvo->parsedEdid.info; + const NVT_HDR_STATIC_METADATA *pHdrInfo = + &pInfo->hdr_static_metadata_info; + + + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + nvFlipEvoOneHead(pDevEvo, sd, head, pHdrInfo, + &pWorkArea->sd[sd].head[head].newState, + allowFlipLock, + &updateState); + + if (pProposedApiHead->dirty.hdr) { + /* Update hardware's current colorSpace and colorRange */ + nvUpdateCurrentHardwareColorSpaceAndRangeEvo( + pDispEvo, + head, + pProposedApiHead->hdr.colorSpace, + pProposedApiHead->hdr.colorRange, + &updateState); + } + } + + if (pProposedApiHead->dirty.hdr) { + pApiHeadState->attributes.colorSpace = + pProposedApiHead->hdr.colorSpace; + pApiHeadState->attributes.colorBpc = + pProposedApiHead->hdr.colorBpc; + pApiHeadState->attributes.colorRange = + pProposedApiHead->hdr.colorRange; + + if (pProposedApiHead->hdr.tf == NVKMS_OUTPUT_TF_PQ) { + nvCancelSDRTransitionTimer(pApiHeadState); + } else if (pApiHeadState->tf == NVKMS_OUTPUT_TF_PQ) { + ScheduleSDRTransitionTimer(pDispEvo, apiHead); + } + + pApiHeadState->tf = pProposedApiHead->hdr.tf; + + nvUpdateInfoFrames(pDpyEvo); + } + + if (pProposedApiHead->dirty.viewPortPointIn) { + pApiHeadState->viewPortPointIn = + pProposedApiHead->viewPortPointIn; + } } if (!skipUpdate) { pDevEvo->hal->Update(pDevEvo, &updateState, TRUE /* releaseElv */); } - - for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { - // Decrease refCnt of surfaces used BEFORE the flip - nvUpdateSurfacesFlipRefCount( - pDevEvo, - head, - &pWorkArea->sd[sd].head[head].oldState, - NV_FALSE); - - nvUnrefTmoLutSurfacesEvo( - pDevEvo, - &pWorkArea->sd[sd].head[head].oldState, - head); - } - - FillPostSyncptReply(pDevEvo, - sd, - &request->sd[sd], - &reply->sd[sd], - pWorkArea); - } - if (!skipUpdate) { - /* Unblock flips which are stuck in execution */ - SkipLayerPendingFlips(pDevEvo, FALSE /* trashPendingMethods */, - TRUE /* unblockMethodsInExecutation */, - pWorkArea); - } + nvPostFlip(pDevEvo, pWorkArea, skipUpdate, applyAllowVrr, &vrrSemaphoreIndex); - if (applyAllowVrr) { - vrrFlipType = nvGetActiveVrrType(pDevEvo); - vrrSemaphoreIndex = nvIncVrrSemaphoreIndex(pDevEvo); - } else { - // TODO Schedule vrr unstall; per-disp/per-device? - } - - if (reply != NULL) { - reply->vrrFlipType = vrrFlipType; - reply->vrrSemaphoreIndex = vrrSemaphoreIndex; - } - - if (!skipUpdate) { - // Note that usage bounds are not lowered here, because the flip - // queued by this function may not occur until later. Instead, schedule - // a timer for later to check if the usage bounds can be lowered. - SchedulePostFlipIMP(pDevEvo); - - pDevEvo->skipConsoleRestore = FALSE; - } + FillNvKmsFlipReply(pDevEvo, pWorkArea, applyAllowVrr, vrrSemaphoreIndex, + pFlipHead, numFlipHeads, reply); /* fall through */ @@ -3497,3 +682,392 @@ void nvApiHeadSetViewportPointIn(const NVDispEvoRec *pDispEvo, TRUE /* releaseElv */); } } + +NvU32 nvApiHeadGetActiveViewportOffset(NVDispEvoRec *pDispEvo, + NvU32 apiHead) +{ + NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + NvU32 head, headCount; + NvU32 offset = 0; + + nvAssert(apiHead != NV_INVALID_HEAD); + + headCount = 0; + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + if (headCount == 0) { + offset = pDevEvo->hal->GetActiveViewportOffset(pDispEvo, head); + } else { + nvAssert(offset == pDevEvo->hal->GetActiveViewportOffset(pDispEvo, head)); + } + headCount++; + } + + return offset; +} + +void nvApiHeadIdleMainLayerChannels(NVDevEvoRec *pDevEvo, + const NvU32 apiHeadMaskPerSd[NVKMS_MAX_SUBDEVICES]) +{ + NVEvoChannelMask idleChannelMaskPerSd[NVKMS_MAX_SUBDEVICES] = { }; + const NVDispEvoRec *pDispEvo; + NvU32 dispIndex, apiHead; + NvBool found = FALSE; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + NvU32 head; + + if ((apiHeadMaskPerSd[pDispEvo->displayOwner] & + NVBIT(apiHead)) == 0x0) { + continue; + } + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + NVEvoChannelPtr pMainLayerChannel = + pDevEvo->head[head].layer[NVKMS_MAIN_LAYER]; + idleChannelMaskPerSd[pDispEvo->displayOwner] |= + pMainLayerChannel->channelMask; + found = TRUE; + } + } + } + + if (!found) { + return; + } + + nvIdleMainLayerChannels(pDevEvo, idleChannelMaskPerSd, + FALSE /* allowForceIdle */); +} + +void nvApiHeadUpdateFlipLock(NVDevEvoRec *pDevEvo, + const NvU32 apiHeadMaskPerSd[NVKMS_MAX_SUBDEVICES], + const NvBool enable) +{ + NvU32 dispIndex; + NVDispEvoPtr pDispEvo; + NvU32 headMaskPerSd[NVKMS_MAX_SUBDEVICES] = { }; + NVEvoChannelMask channelMaskPerSd[NVKMS_MAX_SUBDEVICES] = { }; + NvBool found = FALSE; + + /* Determine which channels need to enable or disable fliplock. */ + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + NvU32 apiHead; + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + NvU32 head; + + if ((apiHeadMaskPerSd[pDispEvo->displayOwner] & + NVBIT(apiHead)) == 0x0) { + continue; + } + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + NVEvoChannelPtr pMainLayerChannel = + pDevEvo->head[head].layer[NVKMS_MAIN_LAYER]; + + if (!nvNeedToToggleFlipLock(pDispEvo, head, enable)) { + continue; + } + + if (enable) { + /* + * Override the prohibition of fliplock on pDispEvos with + * headsurface enabled (calculated earlier in + * HsConfigAllowFlipLock) to allow enabling fliplock for + * headSurface swapgroups. + */ + nvAllowFlipLockEvo(pDispEvo, TRUE /* allowFlipLock */); + } + + headMaskPerSd[pDispEvo->displayOwner] |= NVBIT(head); + channelMaskPerSd[pDispEvo->displayOwner] |= + pMainLayerChannel->channelMask; + found = TRUE; + } + } + } + + if (!found) { + return; + } + + /* + * Wait for all base channels that are enabling/disabling fliplock to be + * idle. This shouldn't timeout if we're enabling fliplock while bringing + * up swapgroups on a new head. + */ + nvIdleMainLayerChannels(pDevEvo, channelMaskPerSd, !enable /* forceIdle */); + + /* Now that all channels are idle, update fliplock. */ + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + nvToggleFlipLockPerDisp(pDispEvo, + headMaskPerSd[pDispEvo->displayOwner], + enable); + } +} + +NvBool nvIdleMainLayerChannelCheckIdleOneApiHead(NVDispEvoPtr pDispEvo, + NvU32 apiHead) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + NvU32 head; + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + NVEvoChannelPtr pMainLayerChannel = + pDevEvo->head[head].layer[NVKMS_MAIN_LAYER]; + NvBool isMethodPending = FALSE; + NvBool ret; + + ret = pDevEvo->hal->IsChannelMethodPending(pDevEvo, pMainLayerChannel, + pDispEvo->displayOwner, &isMethodPending); + + if (ret && isMethodPending) { + return FALSE; + } + } + + return TRUE; +} + +NvU32 nvCollectSurfaceUsageMaskOneApiHead(const NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + NVSurfaceEvoPtr pSurfaceEvo) +{ + NvU32 usageMaskOneHead = 0x0; + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + const NvU32 sd = pDispEvo->displayOwner; + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + NvU32 head; + + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { + return 0; + } + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + const NVEvoSubDevHeadStateRec *pSdHeadState = + &pDevEvo->gpus[sd].headState[head]; + NvU32 layer; + + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + const NVFlipChannelEvoHwState *pLayerFlipState = + &pSdHeadState->layer[layer]; + const NVFlipSyncObjectEvoHwState *pSyncObject = + &pLayerFlipState->syncObject; + NvU32 usageMaskOneLayer = 0x0; + + if ((pSurfaceEvo == pLayerFlipState->pSurfaceEvo[NVKMS_LEFT]) || + (pSurfaceEvo == pLayerFlipState->pSurfaceEvo[NVKMS_RIGHT])) { + usageMaskOneLayer = FLD_SET_DRF(_SURFACE, _USAGE_MASK_LAYER, + _SCANOUT, _ENABLE, usageMaskOneLayer); + } + + if(pSurfaceEvo == + pLayerFlipState->completionNotifier.surface.pSurfaceEvo) { + usageMaskOneLayer = FLD_SET_DRF(_SURFACE, _USAGE_MASK_LAYER, + _NOTIFIER, _ENABLE, usageMaskOneLayer); + } + + if ((!pLayerFlipState->syncObject.usingSyncpt) && + (pSurfaceEvo == + pSyncObject->u.semaphores.acquireSurface.pSurfaceEvo) && + (pSurfaceEvo == + pSyncObject->u.semaphores.releaseSurface.pSurfaceEvo)) { + usageMaskOneLayer = FLD_SET_DRF(_SURFACE, _USAGE_MASK_LAYER, + _SEMAPHORE, _ENABLE, usageMaskOneLayer); + } + + usageMaskOneHead = FLD_IDX_SET_DRF_NUM(_SURFACE, _USAGE_MASK, + _LAYER, layer, usageMaskOneLayer, usageMaskOneHead); + } + + if (pSurfaceEvo == pSdHeadState->cursor.pSurfaceEvo) { + usageMaskOneHead = FLD_SET_DRF(_SURFACE, _USAGE_MASK, + _CURSOR, _ENABLE, usageMaskOneHead); + } + } + + return usageMaskOneHead; +} + +void nvIdleLayerChannels(NVDevEvoRec *pDevEvo, + NvU32 layerMaskPerSdApiHead[NVKMS_MAX_SUBDEVICES][NVKMS_MAX_HEADS_PER_DISP]) +{ + NVEvoChannelMask channelMaskPerSd[NVKMS_MAX_SUBDEVICES] = { }; + const NVDispEvoRec *pDispEvo; + NvU32 sd; + NvU64 startTime = 0; + const NvU32 timeout = 500000; // .5 seconds + NvBool allIdle; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + NvU32 head; + + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { + continue; + } + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + for (NvU32 layer = 0; + layer < pDevEvo->head[head].numLayers; layer++) { + if ((NVBIT(layer) & + layerMaskPerSdApiHead[sd][apiHead]) != 0x0) { + channelMaskPerSd[sd] |= + pDevEvo->head[head].layer[layer]->channelMask; + } + } + } + } + } + + do { + allIdle = TRUE; + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + + for (NvU32 head = 0; head < pDevEvo->numHeads; head++) { + NvU32 layer; + + if (!nvHeadIsActive(pDispEvo, head)) { + continue; + } + + for (layer = 0; + layer < pDevEvo->head[head].numLayers; layer++) { + NVEvoChannelPtr pLayerChannel = + pDevEvo->head[head].layer[layer]; + NvBool isMethodPending; + + if ((pLayerChannel->channelMask & + channelMaskPerSd[sd]) == 0x0) { + continue; + } + + if (pDevEvo->hal->IsChannelMethodPending(pDevEvo, + pLayerChannel, sd, &isMethodPending) && + isMethodPending) { + + allIdle = FALSE; + } else { + /* This has been completed, no need to keep trying */ + channelMaskPerSd[sd] &= ~pLayerChannel->channelMask; + } + } + } + } + + if (!allIdle) { + if (nvExceedsTimeoutUSec(&startTime, timeout)) { + break; + } + nvkms_yield(); + } + } while (!allIdle); + + /* If we timed out above, force things to be idle. */ + if (!allIdle) { + NVEvoIdleChannelState idleChannelState = { }; + NvBool tryToForceIdle = FALSE; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + + for (NvU32 head = 0; head < pDevEvo->numHeads; head++) { + NvU32 layer; + + if (!nvHeadIsActive(pDispEvo, head)) { + continue; + } + + for (layer = 0; + layer < pDevEvo->head[head].numLayers; layer++) { + NVEvoChannelPtr pLayerChannel = + pDevEvo->head[head].layer[layer]; + + if ((pLayerChannel->channelMask & + channelMaskPerSd[sd]) != 0x0) { + idleChannelState.subdev[sd].channelMask |= + pLayerChannel->channelMask; + tryToForceIdle = TRUE; + } + } + } + } + + if (tryToForceIdle) { + NvBool ret = pDevEvo->hal->ForceIdleSatelliteChannel(pDevEvo, + &idleChannelState); + if (!ret) { + nvAssert(ret); + } + } + } +} + +/* + * XXX NVKMS TODO + * Make the sync more efficient: we only need to sync if the + * in-flight methods flip away from this surface. + */ +void nvEvoClearSurfaceUsage(NVDevEvoRec *pDevEvo, + NVSurfaceEvoPtr pSurfaceEvo) +{ + NvU32 head; + + /* + * If the core channel is no longer allocated, we don't need to + * sync. This assumes the channels are allocated/deallocated + * together. + */ + if (pDevEvo->core) { + + if (pDevEvo->hal->ClearSurfaceUsage != NULL) { + pDevEvo->hal->ClearSurfaceUsage(pDevEvo, pSurfaceEvo); + } + + nvRMSyncEvoChannel(pDevEvo, pDevEvo->core, __LINE__); + + for (head = 0; head < pDevEvo->numHeads; head++) { + NvU32 layer; + + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + NVEvoChannelPtr pChannel = + pDevEvo->head[head].layer[layer]; + + nvRMSyncEvoChannel(pDevEvo, pChannel, __LINE__); + } + } + } +} + +NvBool nvIdleBaseChannelOneApiHead(NVDispEvoRec *pDispEvo, NvU32 apiHead, + NvBool *pStoppedBase) +{ + NvBool ret = TRUE; + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + NvU32 head; + + *pStoppedBase = FALSE; + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + NvBool stoppedBase = FALSE; + if (!nvRMIdleBaseChannel(pDevEvo, head, + pDispEvo->displayOwner, &stoppedBase)) { + ret = FALSE; + } else if (stoppedBase) { + *pStoppedBase = TRUE; + } + } + + return ret; +} diff --git a/src/nvidia-modeset/src/nvkms-framelock.c b/src/nvidia-modeset/src/nvkms-framelock.c index 58a13af98..7e3a27b94 100644 --- a/src/nvidia-modeset/src/nvkms-framelock.c +++ b/src/nvidia-modeset/src/nvkms-framelock.c @@ -1129,8 +1129,7 @@ static NvBool FrameLockDpyCanBeServer(const NVDpyEvoRec *pDpyEvo) NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS gsyncGetControlSyncParams = { 0 }; NVDispEvoPtr pDispEvo = pDpyEvo->pDispEvo; NVFrameLockEvoPtr pFrameLockEvo = pDispEvo->pFrameLockEvo; - /* XXX[2Heads1OR] Get the primary hardware head. */ - const NvU32 head = pDpyEvo->apiHead; + const NvU32 head = nvGetPrimaryHwHead(pDispEvo, pDpyEvo->apiHead); const NVDispHeadStateEvoRec *pHeadState; NvU32 ret; @@ -2172,25 +2171,43 @@ NvU32 nvGetFramelockServerHead(const NVDispEvoRec *pDispEvo) { const NVDpyEvoRec *pDpyEvo = nvGetDpyEvoFromDispEvo(pDispEvo, pDispEvo->framelock.server); - /* XXX[2Heads1OR] Get the primary hardware head. */ - return (pDpyEvo != NULL) ? pDpyEvo->apiHead : NV_INVALID_HEAD; + return (pDpyEvo != NULL) ? nvGetPrimaryHwHead(pDispEvo, pDpyEvo->apiHead) : + NV_INVALID_HEAD; } NvU32 nvGetFramelockClientHeadsMask(const NVDispEvoRec *pDispEvo) { NvU32 headsMask = 0x0; - const NVDpyEvoRec *pDpyEvo; + const NVDpyEvoRec *pServerDpyEvo, *pClientDpyEvo; - /* - * XXX[2Heads1OR] Translate api-head -> hardware-heads, and make sure to - * include the secondary hardware-head of the server dpy. - */ - FOR_ALL_EVO_DPYS(pDpyEvo, pDispEvo->framelock.clients, pDispEvo) { - if (pDpyEvo->apiHead == NV_INVALID_HEAD) { + pServerDpyEvo = nvGetDpyEvoFromDispEvo(pDispEvo, + pDispEvo->framelock.server); + if ((pServerDpyEvo != NULL) && + (pServerDpyEvo->apiHead != NV_INVALID_HEAD)) { + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[pServerDpyEvo->apiHead]; + NvU32 primaryHead = nvGetPrimaryHwHead(pDispEvo, + pServerDpyEvo->apiHead); + + nvAssert(primaryHead != NV_INVALID_HEAD); + + /* + * The secondary hardware-head of the server dpy are client of the + * primary head. + */ + headsMask |= pApiHeadState->hwHeadsMask; + headsMask &= ~NVBIT(primaryHead); + } + + FOR_ALL_EVO_DPYS(pClientDpyEvo, pDispEvo->framelock.clients, pDispEvo) { + if (pClientDpyEvo->apiHead == NV_INVALID_HEAD) { continue; } - headsMask |= NVBIT(pDpyEvo->apiHead); + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[pClientDpyEvo->apiHead]; + headsMask |= pApiHeadState->hwHeadsMask; } + return headsMask; } @@ -2205,8 +2222,13 @@ void nvUpdateGLSFramelock(const NVDispEvoRec *pDispEvo, const NvU32 head, * apiHead -> pDpyEvo mapping will get implemented. */ FOR_ALL_EVO_DPYS(pDpyEvo, pDispEvo->validDisplays, pDispEvo) { - /* XXX[2Heads1OR] Get the primary hardware head. */ - if (pDpyEvo->apiHead != head) { + /* + * XXX[2Heads1OR] Framelock is currently not supported with + * 2Heads1OR, the api head is expected to be mapped onto a single + * hardware head which is the primary hardware head. + */ + if ((pDpyEvo->apiHead == NV_INVALID_HEAD) || + (nvGetPrimaryHwHead(pDispEvo, pDpyEvo->apiHead) != head)) { continue; } diff --git a/src/nvidia-modeset/src/nvkms-hal.c b/src/nvidia-modeset/src/nvkms-hal.c index 1d8177068..d7bf0e56d 100644 --- a/src/nvidia-modeset/src/nvkms-hal.c +++ b/src/nvidia-modeset/src/nvkms-hal.c @@ -62,6 +62,8 @@ enum NvKmsAllocDeviceStatus nvAssignEvoCaps(NVDevEvoPtr pDevEvo) _supportsHDMI20, \ _inputLutAppliesToBase, \ _genericPageKind, \ + _dpYCbCr422MaxBpc, \ + _hdmiYCbCr422MaxBpc, \ _validNIsoFormatMask, \ _maxPitch, \ _maxWidthInBytes, \ @@ -91,6 +93,8 @@ enum NvKmsAllocDeviceStatus nvAssignEvoCaps(NVDevEvoPtr pDevEvo) .genericPageKind = _genericPageKind, \ .maxRasterWidth = DRF_MASK(NV ## _classPrefix ## 7D_HEAD_SET_RASTER_SIZE_WIDTH), \ .maxRasterHeight = DRF_MASK(NV ## _classPrefix ## 7D_HEAD_SET_RASTER_SIZE_HEIGHT),\ + .dpYCbCr422MaxBpc = _dpYCbCr422MaxBpc, \ + .hdmiYCbCr422MaxBpc = _hdmiYCbCr422MaxBpc, \ } \ } @@ -173,23 +177,25 @@ enum NvKmsAllocDeviceStatus nvAssignEvoCaps(NVDevEvoPtr pDevEvo) const NVEvoCapsRec evoCaps; } dispTable[] = { /* - * genericPageKind---------------------+ - * inputLutAppliesToBase ---------+ | - * supportsHDMI20 -------------+ | | - * supportsDP13 ------------+ | | | - * pEvoHal --------------+ | | | | - * windowClassPrefix | | | | | - * classPrefix | | | | | | - * | | | | | | | + * hdmiYCbCr422MaxBpc-----------------------------------------+ + * dpYCbCr422MaxBpc---------------------------------------+ | + * genericPageKind---------------------+ | | + * inputLutAppliesToBase ---------+ | | | + * supportsHDMI20 -------------+ | | | | + * supportsDP13 ------------+ | | | | | + * pEvoHal --------------+ | | | | | | + * windowClassPrefix | | | | | | | + * classPrefix | | | | | | | | + * | | | | | | | | | */ - ENTRY_NVD(C7, C6, &nvEvoC6, 1, 1, 0, TURING_GENERIC_KIND), - ENTRY_NVD(C6, C6, &nvEvoC6, 1, 1, 0, TURING_GENERIC_KIND), - ENTRY_NVD(C5, C5, &nvEvoC5, 1, 1, 0, TURING_GENERIC_KIND), - ENTRY_NVD(C3, C3, &nvEvoC3, 1, 1, 0, FERMI_GENERIC_KIND), - ENTRY_EVO(98, &nvEvo94, 1, 1, 1, FERMI_GENERIC_KIND), - ENTRY_EVO(97, &nvEvo94, 1, 1, 1, FERMI_GENERIC_KIND), - ENTRY_EVO(95, &nvEvo94, 0, 1, 1, FERMI_GENERIC_KIND), - ENTRY_EVO(94, &nvEvo94, 0, 0, 1, FERMI_GENERIC_KIND), + ENTRY_NVD(C7, C6, &nvEvoC6, 1, 1, 0, TURING_GENERIC_KIND, 12, 12), + ENTRY_NVD(C6, C6, &nvEvoC6, 1, 1, 0, TURING_GENERIC_KIND, 12, 12), + ENTRY_NVD(C5, C5, &nvEvoC5, 1, 1, 0, TURING_GENERIC_KIND, 12, 12), + ENTRY_NVD(C3, C3, &nvEvoC3, 1, 1, 0, FERMI_GENERIC_KIND, 12, 12), + ENTRY_EVO(98, &nvEvo94, 1, 1, 1, FERMI_GENERIC_KIND, 12, 12), + ENTRY_EVO(97, &nvEvo94, 1, 1, 1, FERMI_GENERIC_KIND, 12, 12), + ENTRY_EVO(95, &nvEvo94, 0, 1, 1, FERMI_GENERIC_KIND, 8, 0), + ENTRY_EVO(94, &nvEvo94, 0, 0, 1, FERMI_GENERIC_KIND, 8, 0), }; int i; diff --git a/src/nvidia-modeset/src/nvkms-hdmi.c b/src/nvidia-modeset/src/nvkms-hdmi.c index b844f7426..0a359387b 100644 --- a/src/nvidia-modeset/src/nvkms-hdmi.c +++ b/src/nvidia-modeset/src/nvkms-hdmi.c @@ -65,13 +65,21 @@ static inline const NVT_EDID_CEA861_INFO *GetExt861(const NVParsedEdidEvoRec *pP */ static void CalculateVideoInfoFrameColorFormat( const NVAttributesSetEvoRec *pAttributesSet, + enum NvKmsOutputTf tf, const NvU32 hdTimings, NVT_VIDEO_INFOFRAME_CTRL *pCtrl) { + /* + * If NVKMS_OUTPUT_TF_PQ is enabled, we expect the colorSpace is RGB. This + * is enforced when the colorSpace is selected. + */ + nvAssert((tf != NVKMS_OUTPUT_TF_PQ) || + (pAttributesSet->colorSpace == + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB)); + // sets video infoframe colorspace (RGB/YUV). switch (pAttributesSet->colorSpace) { case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB: - case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_BT2020RGB: pCtrl->color_space = NVT_VIDEO_INFOFRAME_BYTE1_Y1Y0_RGB; break; case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422: @@ -91,10 +99,11 @@ static void CalculateVideoInfoFrameColorFormat( // sets video infoframe colorimetry. switch (pAttributesSet->colorSpace) { case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB: - pCtrl->colorimetry = NVT_COLORIMETRY_RGB; - break; - case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_BT2020RGB: - pCtrl->colorimetry = NVT_COLORIMETRY_BT2020RGB; + if (tf == NVKMS_OUTPUT_TF_PQ) { + pCtrl->colorimetry = NVT_COLORIMETRY_BT2020RGB; + } else { + pCtrl->colorimetry = NVT_COLORIMETRY_RGB; + } break; case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422: case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444: @@ -322,6 +331,41 @@ static void DisableVendorSpecificInfoFrame( } } +/*! + * Sends General Control Packet to the HDMI sink. + */ +static void SendHdmiGcp(const NVDispEvoRec *pDispEvo, + const NvU32 head, NvBool avmute) +{ + const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NVHDMIPKT_RESULT ret; + + NvU8 sb0 = avmute ? HDMI_GENCTRL_PACKET_MUTE_ENABLE : + HDMI_GENCTRL_PACKET_MUTE_DISABLE; + + NvU8 sb1 = 0; + + NvU8 sb2 = NVT_HDMI_RESET_DEFAULT_PIXELPACKING_PHASE; + + NvU8 gcp[] = { + pktType_GeneralControl, 0, 0, sb0, sb1, sb2, 0, 0, 0, 0 + }; + + ret = NvHdmiPkt_PacketWrite(pDevEvo->hdmiLib.handle, + pDispEvo->displayOwner, + pHeadState->activeRmId, + head, + NVHDMIPKT_TYPE_GENERAL_CONTROL, + NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_EVERY_FRAME, + sizeof(gcp), + gcp); + + if (ret != NVHDMIPKT_SUCCESS) { + nvAssert(ret == NVHDMIPKT_SUCCESS); + } +} + /* * SendInfoFrame() - Send infoframe to the hardware through the hdmipkt * library. @@ -451,7 +495,10 @@ static void SendVideoInfoFrame(const NVDispEvoRec *pDispEvo, NVT_STATUS status; - CalculateVideoInfoFrameColorFormat(pAttributesSet, hdTimings, &videoCtrl); + CalculateVideoInfoFrameColorFormat(pAttributesSet, + pDispEvo->headState[head].tf, + hdTimings, + &videoCtrl); status = NvTiming_ConstructVideoInfoframe(pEdidInfo, &videoCtrl, @@ -614,6 +661,33 @@ static void SetDpAudioEnable(const NVDispEvoRec *pDispEvo, } } +/* + * Uses RM control to mute HDMI audio stream at source side. + */ +static void SetHdmiAudioMute(const NVDispEvoRec *pDispEvo, + const NvU32 head, const NvBool mute) +{ + NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS params = { }; + const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NvU32 ret; + + params.subDeviceInstance = pDispEvo->displayOwner; + params.displayId = pHeadState->activeRmId; + params.mute = (mute ? NV0073_CTRL_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_TRUE : + NV0073_CTRL_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_FALSE); + + ret = nvRmApiControl(nvEvoGlobal.clientHandle, + pDevEvo->displayCommonHandle, + NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM, + ¶ms, + sizeof(params)); + + if (ret != NVOS_STATUS_SUCCESS) { + nvAssert(!"NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM failed"); + } +} + static void EnableHdmiAudio(const NVDispEvoRec *pDispEvo, const NvU32 head, const NvBool enable) { @@ -1158,6 +1232,8 @@ void nvHdmiDpEnableDisableAudio(const NVDispEvoRec *pDispEvo, if (pHeadState->audio.isAudioOverHdmi) { EnableHdmiAudio(pDispEvo, head, enable); + SetHdmiAudioMute(pDispEvo, head, !enable /* mute */); + SendHdmiGcp(pDispEvo, head, !enable /* avmute */); } /* Populate ELD buffer after enabling audio */ @@ -1178,10 +1254,12 @@ void nvHdmiDpEnableDisableAudio(const NVDispEvoRec *pDispEvo, void nvDpyUpdateHdmiPreModesetEvo(NVDpyEvoPtr pDpyEvo) { if (!nvDpyIsHdmiEvo(pDpyEvo)) { + pDpyEvo->pConnectorEvo->isHdmiEnabled = FALSE; return; } HdmiSendEnable(pDpyEvo, TRUE); + pDpyEvo->pConnectorEvo->isHdmiEnabled = TRUE; } /* @@ -1925,8 +2003,11 @@ NvBool nvHdmiDpySupportsFrl(const NVDpyEvoRec *pDpyEvo) * Returns TRUE if FRL is needed, or FALSE otherwise. * */ static NvBool HdmiTimingsNeedFrl(const NVDpyEvoRec *pDpyEvo, - const NvU32 pixelClock) + const NVHwModeTimingsEvo *pHwTimings) { + const NvU32 pixelClock = (pHwTimings->yuv420Mode == NV_YUV420_MODE_HW) ? + (pHwTimings->pixelClock / 2) : pHwTimings->pixelClock; + nvAssert(nvDpyIsHdmiEvo(pDpyEvo)); /* @@ -1951,7 +2032,7 @@ NvBool nvHdmiFrlQueryConfig( NVHDMIPKT_RESULT ret; if (!nvDpyIsHdmiEvo(pDpyEvo) || - !HdmiTimingsNeedFrl(pDpyEvo, pHwTimings->pixelClock)) { + !HdmiTimingsNeedFrl(pDpyEvo, pHwTimings)) { return TRUE; } diff --git a/src/nvidia-modeset/src/nvkms-headsurface-config.c b/src/nvidia-modeset/src/nvkms-headsurface-config.c index b6dfaeb5b..6238a503f 100644 --- a/src/nvidia-modeset/src/nvkms-headsurface-config.c +++ b/src/nvidia-modeset/src/nvkms-headsurface-config.c @@ -27,12 +27,14 @@ #include "nvkms-headsurface-3d.h" #include "nvkms-headsurface-matrix.h" #include "nvkms-headsurface-swapgroup.h" +#include "nvkms-utils-flip.h" #include "nvkms-flip.h" #include "nvkms-utils.h" #include "nvkms-surface.h" #include "nvkms-private.h" #include "nvkms-evo.h" #include "nvkms-modeset.h" +#include "nvkms-stereo.h" #include "nvkms-prealloc.h" #include "nvidia-push-utils.h" /* nvPushIdleChannel() */ @@ -698,16 +700,16 @@ static void HsConfigCopyHsChannelToHsConfig( for (layer = 0; layer < ARRAY_LEN(pHsConfigOneHead->layer); layer++) { - const NVFlipChannelEvoHwState *pHwState = + const NVHsLayerRequestedFlipState *pFlipState = HsGetLastFlipQueueEntry(pHsChannel, layer); /* both structures have the same number of eyes */ ct_assert(ARRAY_LEN(pHsConfigOneHead->layer[layer].pSurfaceEvo) == - ARRAY_LEN(pHwState->pSurfaceEvo)); + ARRAY_LEN(pFlipState->pSurfaceEvo)); for (eye = NVKMS_LEFT; eye < NVKMS_MAX_EYES; eye++) { pHsConfigOneHead->layer[layer].pSurfaceEvo[eye] = - pHwState->pSurfaceEvo[eye]; + pFlipState->pSurfaceEvo[eye]; } } } @@ -1010,7 +1012,7 @@ static void HsConfigInitSwapGroupOneHead( pChannelConfig->eyeMask = NVBIT(NVKMS_LEFT); - if (pTimings->stereo.mode != NVKMS_STEREO_DISABLED) { + if (pApiHeadState->stereo.mode != NVKMS_STEREO_DISABLED) { pChannelConfig->eyeMask |= NVBIT(NVKMS_RIGHT); } @@ -1818,7 +1820,7 @@ static void HsConfigInitFlipQueue( */ for (layer = 0; layer < ARRAY_LEN(pHsConfigOneHead->layer); layer++) { - NVFlipChannelEvoHwState hwState = { }; + NVHsLayerRequestedFlipState hwState = { }; nvkms_memset(&pHsChannel->flipQueue[layer], 0, sizeof(pHsChannel->flipQueue[layer])); @@ -1879,26 +1881,22 @@ static void HsMainLayerFlip( const NVDispEvoRec *pDispEvo = pHsChannel->pDispEvo; NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; const NvU32 apiHead = pHsChannel->apiHead; - struct NvKmsFlipRequest *pRequest; - struct NvKmsFlipParams *pFlipParams; const NvU32 sd = pDispEvo->displayOwner; NvBool ret; NvU8 eye; struct NvKmsFlipCommonParams *pParamsOneHead; /* - * Use a preallocated NvKmsFlipRequest, so that we don't have to allocate + * Use preallocated memory, so that we don't have to allocate * memory here (and deal with allocation failure). */ - pFlipParams = &pHsChannel->scratchParams; + struct NvKmsFlipRequestOneHead *pFlipHead = &pHsChannel->scratchParams; - nvkms_memset(pFlipParams, 0, sizeof(*pFlipParams)); + nvkms_memset(pFlipHead, 0, sizeof(*pFlipHead)); - pRequest = &pFlipParams->request; - - pRequest->commit = NV_TRUE; - - pParamsOneHead = &pRequest->sd[sd].head[apiHead]; + pFlipHead->sd = sd; + pFlipHead->head = apiHead; + pParamsOneHead = &pFlipHead->flip; pParamsOneHead->layer[NVKMS_MAIN_LAYER].surface.specified = TRUE; @@ -1936,12 +1934,13 @@ static void HsMainLayerFlip( pParamsOneHead->cursor.position = cursorPosition; pParamsOneHead->cursor.positionSpecified = TRUE; - pRequest->sd[sd].requestedHeadsBitMask = NVBIT(apiHead); - ret = nvFlipEvo(pDevEvo, pDevEvo->pNvKmsOpenDev, - pRequest, - &pFlipParams->reply, + pFlipHead, + 1 /* numFlipHeads */, + TRUE /* commit */, + FALSE /* allowVrr */, + NULL /* pReply */, FALSE /* skipUpdate */, FALSE /* allowFlipLock */); @@ -2053,112 +2052,6 @@ static void HsConfigRestoreMainLayerSurface( } } - -/*! - * Wait for idle on a set of base channels. - * - * \param[in,out] pDevEvo The device. - * \param[in] idleChannelMaskPerSd The channel masks per subdevice that - * we should wait to be idle. - * \param[in] allowStopBase Whether we should stop base or just - * assert if the idle times out. - */ -static void HsConfigIdleBaseChannels( - NVDevEvoPtr pDevEvo, - const NVEvoChannelMask *idleChannelMaskPerSd, - NvBool allowStopBase) -{ - NvU64 startTime = 0; - NvBool allChannelsIdle = FALSE; - NVDispEvoPtr pDispEvo; - NvU32 dispIndex, head; - NVEvoChannelMask busyChannelMaskPerSd[NVKMS_MAX_SUBDEVICES] = { }; - - /* - * Wait up to 2 seconds for all channels to be idle, and gather a list of - * all busy channels. - */ - while (!allChannelsIdle) { - - const NvU32 timeout = 2000000; /* 2 seconds */ - NvBool anyChannelBusy = FALSE; - - FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - for (head = 0; head < pDevEvo->numHeads; head++) { - NVEvoChannelPtr pMainLayerChannel = - pDevEvo->head[head].layer[NVKMS_MAIN_LAYER]; - if (idleChannelMaskPerSd[pDispEvo->displayOwner] & - pMainLayerChannel->channelMask) { - - NvBool isMethodPending = FALSE; - if (!pDevEvo->hal->IsChannelMethodPending( - pDevEvo, - pMainLayerChannel, - pDispEvo->displayOwner, - &isMethodPending) - || isMethodPending) { - - /* Mark this channel as busy. */ - busyChannelMaskPerSd[pDispEvo->displayOwner] |= - pMainLayerChannel->channelMask; - anyChannelBusy = TRUE; - } else { - /* - * Mark this channel as no longer busy, in case its - * flip completed while we were waiting on another - * channel. - */ - busyChannelMaskPerSd[pDispEvo->displayOwner] &= - ~pMainLayerChannel->channelMask; - } - } - } - } - - if (!anyChannelBusy) { - allChannelsIdle = TRUE; - break; - } - - /* Break out of the loop if we exceed the timeout. */ - if (nvExceedsTimeoutUSec(&startTime, timeout)) { - break; - } - - nvkms_yield(); - } - - if (!allChannelsIdle) { - /* - * At least one channel was still idle after the 2 second timeout - * above. - */ - if (!allowStopBase) { - /* - * The caller of this function expected this wait for idle not to - * time out. - */ - nvEvoLogDev(pDevEvo, EVO_LOG_WARN, - "Timeout while waiting for idle."); - } else { - /* - * Idle all base channels that were still busy when the wait above - * timed out. - */ - NVEvoIdleChannelState idleChannelState = { }; - - FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - idleChannelState.subdev[pDispEvo->displayOwner].channelMask = - busyChannelMaskPerSd[pDispEvo->displayOwner]; - } - - pDevEvo->hal->ForceIdleSatelliteChannelIgnoreLock( - pDevEvo, &idleChannelState); - } - } -} - - /*! * Enable or disable fliplock on all channels using headsurface for swapgroups, * waiting for idle if necessary. @@ -2166,27 +2059,19 @@ static void HsConfigIdleBaseChannels( static void HsConfigUpdateFlipLockForSwapGroups(NVDevEvoPtr pDevEvo, NvBool enable) { - NvU32 dispIndex, head; + NvU32 dispIndex, apiHead; NVDispEvoPtr pDispEvo; - NVEvoChannelMask flipLockToggleChannelMaskPerSd[NVKMS_MAX_SUBDEVICES] = { }; + NvU32 flipLockToggleApiHeadMaskPerSd[NVKMS_MAX_SUBDEVICES] = { }; + NvBool found = FALSE; - /* Determine which channels need to enable or disable fliplock. */ FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - - for (head = 0; head < pDevEvo->numHeads; head++) { - const NvU32 apiHead = nvHardwareHeadToApiHead(head); + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { NVHsChannelEvoPtr pHsChannel = pDispEvo->pHsChannel[apiHead]; if (pHsChannel == NULL) { continue; } - NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[pDispEvo->displayOwner]; - NVEvoHeadControlPtr pHC = &pEvoSubDev->headControl[head]; - NVEvoChannelPtr pMainLayerChannel = - pDevEvo->head[head].layer[NVKMS_MAIN_LAYER]; - NvBool setFlipLock = FALSE; - /* * This function is called in two cases, when disabling fliplock for * the pHsChannels in the previous config, and when enabling @@ -2199,82 +2084,17 @@ static void HsConfigUpdateFlipLockForSwapGroups(NVDevEvoPtr pDevEvo, continue; } - if (!enable && pHC->flipLock) { - /* - * This channel is currently using fliplock in the config that - * is being torn down; idle its base channel and disable - * fliplock. - */ - setFlipLock = TRUE; - } - - if (enable && ((pHC->serverLock != NV_EVO_NO_LOCK) || - (pHC->clientLock != NV_EVO_NO_LOCK))) { - /* - * This channel will be using fliplock for swap groups in the - * new config; idle its base channel and enable fliplock. - */ - - /* - * Override the prohibition of fliplock on pDispEvos with - * headsurface enabled (calculated earlier in - * HsConfigAllowFlipLock) to allow enabling fliplock for - * headSurface swapgroups. - */ - nvAllowFlipLockEvo(pDispEvo, TRUE /* allowFlipLock */); - - nvAssert(!HEAD_MASK_QUERY(pEvoSubDev->flipLockProhibitedHeadMask, - head)); - setFlipLock = TRUE; - } - - if (!setFlipLock) { - continue; - } - - flipLockToggleChannelMaskPerSd[pDispEvo->displayOwner] |= - pMainLayerChannel->channelMask; + flipLockToggleApiHeadMaskPerSd[pDispEvo->displayOwner] |= + NVBIT(apiHead); + found = TRUE; } } - /* - * Wait for all base channels that are enabling/disabling fliplock to be - * idle. This shouldn't timeout if we're enabling fliplock while bringing - * up swapgroups on a new head. - */ - HsConfigIdleBaseChannels(pDevEvo, - flipLockToggleChannelMaskPerSd, - !enable /* allowStopBase */); - - /* Now that all channels are idle, update fliplock. */ - FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - NVEvoUpdateState updateState = { }; - - if (!flipLockToggleChannelMaskPerSd[pDispEvo->displayOwner]) { - continue; - } - - for (head = 0; head < pDevEvo->numHeads; head++) { - NVEvoChannelPtr pMainLayerChannel = - pDevEvo->head[head].layer[NVKMS_MAIN_LAYER]; - if (flipLockToggleChannelMaskPerSd[pDispEvo->displayOwner] & - pMainLayerChannel->channelMask) { - - NvU32 setEnable = enable; - - if (!nvUpdateFlipLockEvoOneHead(pDispEvo, head, &setEnable, - TRUE /* set */, - NULL /* needsEarlyUpdate */, - &updateState)) { - nvEvoLogDev(pDevEvo, EVO_LOG_WARN, - "Failed to toggle fliplock for swapgroups."); - } - } - } - - nvEvoUpdateAndKickOff(pDispEvo, TRUE, &updateState, - TRUE /* releaseElv */); + if (!found) { + return; } + + nvApiHeadUpdateFlipLock(pDevEvo, flipLockToggleApiHeadMaskPerSd, enable); } /*! @@ -2298,7 +2118,7 @@ void nvHsConfigStop( NvU32 dispIndex, apiHead; NVDispEvoPtr pDispEvo; NVHsDeviceEvoPtr pHsDevice = pDevEvo->pHsDevice; - NVEvoChannelMask hsDisableChannelMaskPerSd[NVKMS_MAX_SUBDEVICES] = { }; + NvU32 hsDisableApiHeadMaskPerSd[NVKMS_MAX_SUBDEVICES] = { }; /* * We should only get here if this configuration is going to be committed. @@ -2314,19 +2134,15 @@ void nvHsConfigStop( /* Flip all headSurface heads to NULL. */ FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - NvU32 head; - for (head = 0; head < pDevEvo->numHeads; head++) { - const NvU32 apiHead = nvHardwareHeadToApiHead(head); + NvU32 apiHead; + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { NVHsChannelEvoPtr pHsChannel = pDispEvo->pHsChannel[apiHead]; if (pHsChannel != NULL) { - NVEvoChannelPtr pMainLayerChannel = - pDevEvo->head[head].layer[NVKMS_MAIN_LAYER]; - hsDisableChannelMaskPerSd[pDispEvo->displayOwner] |= - pMainLayerChannel->channelMask; + hsDisableApiHeadMaskPerSd[pDispEvo->displayOwner] |= NVBIT(apiHead); if (pHsChannel->config.pixelShift == NVKMS_PIXEL_SHIFT_8K) { - nvSetStereoEvo(pDispEvo, head, FALSE); + nvSetStereo(pDispEvo, apiHead, FALSE); } if (pHsChannel->config.neededForSwapGroup) { @@ -2348,14 +2164,13 @@ void nvHsConfigStop( } /* - * Wait for base to be idle on all channels that previously had headSurface - * enabled in order to allow semaphore releases from previous headSurface - * flips to complete. This wait should not timeout, so if it does, just - * assert instead of forcing the channels idle. + * Wait for main layer channels to be idle on all channels that previously + * had headSurface enabled in order to allow semaphore releases from + * previous headSurface flips to complete. This wait should not timeout, + * so if it does, just assert instead of forcing the channels idle. */ - HsConfigIdleBaseChannels(pDevEvo, - hsDisableChannelMaskPerSd, - FALSE /* allowStopBase */); + nvApiHeadIdleMainLayerChannels(pDevEvo, + hsDisableApiHeadMaskPerSd); /* Update bookkeeping and restore the original surface in main layer. */ FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { @@ -2419,7 +2234,7 @@ void nvHsConfigStart( NVDevEvoPtr pDevEvo, NVHsConfig *pHsConfig) { - NvU32 dispIndex, head; + NvU32 dispIndex, apiHead; NVDispEvoPtr pDispEvo; NVHsDeviceEvoPtr pHsDevice = pDevEvo->pHsDevice; NvBool allowFlipLock; @@ -2433,8 +2248,7 @@ void nvHsConfigStart( FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - for (head = 0; head < pDevEvo->numHeads; head++) { - const NvU32 apiHead = nvHardwareHeadToApiHead(head); + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { NVHsConfigOneHead *pHsConfigOneHead = &pHsConfig->apiHead[dispIndex][apiHead]; @@ -2496,9 +2310,8 @@ void nvHsConfigStart( /* Update surfaces. */ - for (head = 0; head < pDevEvo->numHeads; head++) { + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { - const NvU32 apiHead = nvHardwareHeadToApiHead(head); NVHsStateOneHeadAllDisps *pDevEvoHsConfig = &pDevEvo->apiHeadSurfaceAllDisps[apiHead]; NVHsStateOneHeadAllDisps *pHsOneHeadAllDisps = @@ -2573,8 +2386,7 @@ void nvHsConfigStart( FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - for (head = 0; head < pDevEvo->numHeads; head++) { - const NvU32 apiHead = nvHardwareHeadToApiHead(head); + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { NVHsChannelEvoPtr pHsChannel = pDispEvo->pHsChannel[apiHead]; const NVHsConfigOneHead *pHsConfigOneHead = &pHsConfig->apiHead[dispIndex][apiHead]; @@ -2629,7 +2441,7 @@ void nvHsConfigStart( NV_HS_NEXT_FRAME_REQUEST_TYPE_FIRST_FRAME); if (pHsChannel->config.pixelShift == NVKMS_PIXEL_SHIFT_8K) { - nvSetStereoEvo(pDispEvo, head, TRUE); + nvSetStereo(pDispEvo, apiHead, TRUE); } } } diff --git a/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c b/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c index f75c9fb17..c3a843cde 100644 --- a/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c +++ b/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c @@ -22,11 +22,14 @@ */ #include "nvkms-types.h" +#include "nvkms-private.h" #include "nvkms-headsurface.h" #include "nvkms-headsurface-ioctl.h" #include "nvkms-headsurface-priv.h" +#include "nvkms-ioctl.h" #include "nvkms-cursor.h" #include "nvkms-utils.h" +#include "nvkms-utils-flip.h" #include "nvkms-flip.h" /* @@ -51,50 +54,20 @@ * - Apply the request to the headSurface-ful heads. */ -/*! - * Assign headSurface bitmasks. - * - * Given requestedHeadsBitMask and a disp, assign a head bitmasks of the - * headSurface-ful heads and headSurface-less heads. - * - * Fail if requestedHeadsBitMask contains invalid heads. - */ -static NvBool HsIoctlGetBitMasks( - const NVDispEvoRec *pDispEvo, - const NvU32 requestedHeadsBitMask, - NvU32 *pHsMask, - NvU32 *pNonHsMask) -{ - NvU32 hsMask = 0; - NvU32 nonHsMask = 0; - NvU32 head; +typedef struct _NVHsRequestedFlipState { + struct NvKmsPoint viewPortPointIn; + NVFlipCursorEvoHwState cursor; + NVHsLayerRequestedFlipState layer[NVKMS_MAX_LAYERS_PER_HEAD]; - if (nvHasBitAboveMax(requestedHeadsBitMask, pDispEvo->pDevEvo->numHeads)) { - return FALSE; - } + struct { + NvBool viewPortPointIn : 1; + NvBool cursorSurface : 1; + NvBool cursorPosition : 1; - FOR_EACH_INDEX_IN_MASK(32, head, requestedHeadsBitMask) { - const NvU32 apiHead = nvHardwareHeadToApiHead(head); - if (pDispEvo->pHsChannel[apiHead] == NULL) { - nonHsMask |= NVBIT(head); - } else { - hsMask |= NVBIT(head); - } + NvBool layer[NVKMS_MAX_LAYERS_PER_HEAD]; + } dirty; - } FOR_EACH_INDEX_IN_MASK_END; - - /* - * Each bit from the original mask should be in exactly one of hsMask or - * nonHsMask. - */ - nvAssert((hsMask | nonHsMask) == requestedHeadsBitMask); - nvAssert((hsMask & nonHsMask) == 0); - - *pHsMask = hsMask; - *pNonHsMask = nonHsMask; - - return TRUE; -} +} NVHsRequestedFlipState; /*! * Validate the NvKmsMoveCursorCommonParams for headSurface. @@ -132,10 +105,9 @@ static void HsIoctlMoveCursor( */ NvBool nvHsIoctlMoveCursor( NVDispEvoPtr pDispEvo, - NvU32 head, + NvU32 apiHead, const struct NvKmsMoveCursorCommonParams *pParams) { - const NvU32 apiHead = nvHardwareHeadToApiHead(head); NVHsChannelEvoRec *pHsChannel; if (apiHead > ARRAY_LEN(pDispEvo->pHsChannel)) { @@ -147,7 +119,7 @@ NvBool nvHsIoctlMoveCursor( /* If headSurface is not used on this head, call down. */ if (pHsChannel == NULL) { - nvEvoMoveCursor(pDispEvo, head, pParams); + nvMoveCursor(pDispEvo, apiHead, pParams); return TRUE; } @@ -226,10 +198,9 @@ NvBool nvHsIoctlSetCursorImage( NVDispEvoPtr pDispEvo, const struct NvKmsPerOpenDev *pOpenDevice, const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, - NvU32 head, + NvU32 apiHead, const struct NvKmsSetCursorImageCommonParams *pParams) { - const NvU32 apiHead = nvHardwareHeadToApiHead(head); NVHsChannelEvoRec *pHsChannel; NVSurfaceEvoRec *pSurfaceEvo = NULL; @@ -245,7 +216,7 @@ NvBool nvHsIoctlSetCursorImage( return nvSetCursorImage(pDispEvo, pOpenDevice, pOpenDevSurfaceHandles, - head, + apiHead, pParams); } @@ -278,36 +249,34 @@ static void HsIoctlPan( } /*! - * Create a copy of NvKmsFlipRequest with the headSurface-ful heads removed. + * Create a copy of pFlipHead[] array with the headSurface-ful heads removed. */ -static struct NvKmsFlipRequest *HsIoctlRemoveHsHeadsFromNvKmsFlipRequest( +static struct NvKmsFlipRequestOneHead *HsIoctlRemoveHsHeadsFromNvKmsFlipHead( NVDevEvoPtr pDevEvo, - const struct NvKmsFlipRequest *pRequestOriginal, - const NvU32 hsMask[NVKMS_MAX_SUBDEVICES]) + const struct NvKmsFlipRequestOneHead *pFlipHeadOriginal, + const NvU32 numFlipHeadsOriginal, + const NvU32 numFlipHeads, + const NvU8 hsMask[NVKMS_MAX_SUBDEVICES]) { - NVDispEvoPtr pDispEvo; - NvU32 head, sd; + struct NvKmsFlipRequestOneHead *pFlipHead = NULL; + NvU32 i, j; - struct NvKmsFlipRequest *pRequest = nvAlloc(sizeof(*pRequest)); - - if (pRequest == NULL) { - return FALSE; + pFlipHead = nvAlloc(sizeof(*pFlipHead) * numFlipHeads); + if (pFlipHead == NULL) { + return NULL; } - *pRequest = *pRequestOriginal; - - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - FOR_EACH_INDEX_IN_MASK(32, head, hsMask[sd]) { - - nvkms_memset(&pRequest->sd[sd].head[head], 0, - sizeof(pRequest->sd[sd].head[head])); - - pRequest->sd[sd].requestedHeadsBitMask &= ~NVBIT(head); - - } FOR_EACH_INDEX_IN_MASK_END; + j = 0; + for (i = 0; i < numFlipHeadsOriginal; i++) { + const NvU32 apiHead = pFlipHeadOriginal[i].head; + const NvU32 sd = pFlipHeadOriginal[i].sd; + if ((hsMask[sd] & NVBIT(apiHead)) == 0) { + pFlipHead[j++] = pFlipHeadOriginal[i]; + } } + nvAssert(j == numFlipHeads); - return pRequest; + return pFlipHead; } static void HsIoctlAssignSurfacesMaxEyes( @@ -322,7 +291,7 @@ static void HsIoctlAssignSurfacesMaxEyes( } static NvBool HsIoctlFlipValidateOneHwState( - const NVFlipChannelEvoHwState *pHwState, + const NVHsLayerRequestedFlipState *pHwState, const NvU32 sd) { /* The semaphore surface must have a CPU mapping. */ @@ -341,74 +310,152 @@ static NvBool HsIoctlFlipValidateOneHwState( } } - /* HeadSurface does not support timeStamp flips, yet. */ - - if (pHwState->timeStamp != 0) { - return FALSE; - } - return TRUE; } /*! - * Assign NVFlipEvoHwState. + * Assign NVHsRequestedFlipState. * - * Return TRUE if the NVFlipEvoHwState could be assigned and is valid for use by + * Return TRUE if the NVHsRequestedFlipState could be assigned and is valid for use by * headSurface. */ static NvBool HsIoctlFlipAssignHwStateOneHead( NVHsChannelEvoRec *pHsChannel, NVDevEvoPtr pDevEvo, const NvU32 sd, - const NvU32 head, + const NvU32 apiHead, const struct NvKmsPerOpenDev *pOpenDev, - const struct NvKmsFlipCommonParams *pRequestOneHead, - NVFlipEvoHwState *pFlipState) + const struct NvKmsFlipCommonParams *pParams, + NVHsRequestedFlipState *pFlipState) { + const NVEvoApiHandlesRec *pOpenDevSurfaceHandles = + nvGetSurfaceHandlesFromOpenDevConst(pOpenDev); NvU32 layer; - const struct NvKmsUsageBounds *pPossibleUsage = - &pDevEvo->gpus[sd].pDispEvo->headState[head].timings.viewPort.possibleUsage; nvAssert(pHsChannel != NULL); /* Init pFlipState using current pHsChannel state. */ - nvClearFlipEvoHwState(pFlipState); + nvkms_memset(pFlipState, 0, sizeof(*pFlipState)); pFlipState->cursor = pHsChannel->config.cursor; pFlipState->viewPortPointIn.x = pHsChannel->config.viewPortIn.x; pFlipState->viewPortPointIn.y = pHsChannel->config.viewPortIn.y; - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + for (layer = 0; layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { pFlipState->layer[layer] = *HsGetLastFlipQueueEntry(pHsChannel, layer); } - /* Apply pRequestOneHead to pFlipState. */ - - if (!nvUpdateFlipEvoHwState(pOpenDev, pDevEvo, sd, head, pRequestOneHead, - pFlipState, FALSE /* allowVrr */)) { + /* Apply pParams to pFlipState. */ + if (!nvCheckFlipPermissions(pOpenDev, pDevEvo, sd, apiHead, pParams)) { return FALSE; } - nvOverrideScalingUsageBounds(pDevEvo, head, pFlipState, pPossibleUsage); + if (pParams->viewPortIn.specified) { + pFlipState->dirty.viewPortPointIn = TRUE; + pFlipState->viewPortPointIn = pParams->viewPortIn.point; + } - /* Validate that the requested changes can be performed by headSurface. */ - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if (!pFlipState->dirty.layer[layer]) { - continue; + if (pParams->cursor.imageSpecified) { + if (!nvAssignCursorSurface(pOpenDev, pDevEvo, &pParams->cursor.image, + &pFlipState->cursor.pSurfaceEvo)) { + return FALSE; } - /* - * HeadSurface only supports client notifiers when running in - * swapgroup mode where each flip IOCTL will result in a real - * flip in HW. - */ - if (((pFlipState->layer[layer].completionNotifier.surface.pSurfaceEvo != NULL) || - pFlipState->layer[layer].completionNotifier.awaken) && - !pHsChannel->config.neededForSwapGroup) { + if (pFlipState->cursor.pSurfaceEvo != NULL) { + pFlipState->cursor.cursorCompParams = + pParams->cursor.image.cursorCompParams; + } + + pFlipState->dirty.cursorSurface = TRUE; + } + + if (pParams->cursor.positionSpecified) { + pFlipState->cursor.x = pParams->cursor.position.x; + pFlipState->cursor.y = pParams->cursor.position.y; + + pFlipState->dirty.cursorPosition = TRUE; + } + + for (layer = 0; layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { + if (pParams->layer[layer].surface.specified) { + NvBool ret = + nvAssignSurfaceArray(pDevEvo, + pOpenDevSurfaceHandles, + pParams->layer[layer].surface.handle, + FALSE /* isUsedByCursorChannel */, + TRUE /* isUsedByLayerChannel */, + pFlipState->layer[layer].pSurfaceEvo); + if (!ret) { + return FALSE; + } + + pFlipState->dirty.layer[layer] = TRUE; + } + + if (pParams->layer[layer].syncObjects.specified) { + NvBool ret; + + if (pParams->layer[layer].syncObjects.val.useSyncpt) { + return FALSE; + } + + nvkms_memset(&pFlipState->layer[layer].syncObject, + 0, + sizeof(pFlipState->layer[layer].syncObject)); + + ret = nvAssignSemaphoreEvoHwState(pDevEvo, + pOpenDevSurfaceHandles, + layer, + sd, + &pParams->layer[layer].syncObjects.val, + &pFlipState->layer[layer].syncObject); + if (!ret) { + return FALSE; + } + + pFlipState->dirty.layer[layer] = TRUE; + } + + if (pParams->layer[layer].completionNotifier.specified && + (pParams->layer[layer].completionNotifier.val.surface.surfaceHandle != 0)) { + + /* + * HeadSurface only supports client notifiers when running in + * swapgroup mode where each flip IOCTL will result in a real + * flip in HW. + */ + if (!pHsChannel->config.neededForSwapGroup) { + return FALSE; + } + + NvBool ret = nvAssignCompletionNotifierEvoHwState( + pDevEvo, + pOpenDevSurfaceHandles, + &pParams->layer[layer].completionNotifier.val, + layer, + &pFlipState->layer[layer].completionNotifier); + if (!ret) { + return FALSE; + } + + pFlipState->dirty.layer[layer] = TRUE; + } + + /* HeadSurface does not support timeStamp flips, yet. */ + if (pParams->layer[layer].timeStamp != 0) { return FALSE; } + } + + /* XXX Reject all unhandled flip parameters */ + + /* Validate that the requested changes can be performed by headSurface. */ + for (layer = 0; layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { + if (!pFlipState->dirty.layer[layer]) { + continue; + } if (!HsIoctlFlipValidateOneHwState(&pFlipState->layer[layer], sd)) { return FALSE; @@ -427,76 +474,86 @@ static NvBool HsIoctlFlipAssignHwStateOneHead( NvBool nvHsIoctlFlip( NVDevEvoPtr pDevEvo, const struct NvKmsPerOpenDev *pOpenDev, - const struct NvKmsFlipRequest *pRequest, + const struct NvKmsFlipRequestOneHead *pFlipHead, + NvU32 numFlipHeads, + NvBool commit, + NvBool allowVrr, struct NvKmsFlipReply *pReply) { - NvU32 head, sd; - NVDispEvoPtr pDispEvo; - NvU32 nHsHeads = 0; - NvU32 nNonHsHeads = 0; + NvU32 i; + ct_assert(NVKMS_MAX_HEADS_PER_DISP <= 8); + NvU8 hsMask[NVKMS_MAX_SUBDEVICES] = { }; + NvU8 nonHsMask[NVKMS_MAX_SUBDEVICES] = { }; + NvU32 nHsApiHeads = 0; + NvU32 nNonHsApiHeads = 0; NvBool ret = FALSE; struct { - NvU32 hsMask[NVKMS_MAX_SUBDEVICES]; - NvU32 nonHsMask[NVKMS_MAX_SUBDEVICES]; - NVFlipEvoHwState flipState + NVHsRequestedFlipState flipState [NVKMS_MAX_SUBDEVICES][NVKMS_MAX_HEADS_PER_DISP]; - } *pWorkArea = nvCalloc(1, sizeof(*pWorkArea)); - - if (pWorkArea == NULL) { - goto done; - } + } *pWorkArea = NULL; /* Take inventory of which heads are touched by the request. */ - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + for (i = 0; i < numFlipHeads; i++) { + const NvU32 apiHead = pFlipHead[i].head; + const NvU32 sd = pFlipHead[i].sd; + NVDispEvoPtr pDispEvo = pDevEvo->pDispEvo[sd]; - if (!HsIoctlGetBitMasks(pDispEvo, - pRequest->sd[sd].requestedHeadsBitMask, - &pWorkArea->hsMask[sd], - &pWorkArea->nonHsMask[sd])) { - goto done; + if (pDispEvo->pHsChannel[apiHead] == NULL) { + nonHsMask[sd] |= NVBIT(apiHead); + nNonHsApiHeads++; + } else { + hsMask[sd] |= NVBIT(apiHead); + nHsApiHeads++; } - - nHsHeads += nvPopCount32(pWorkArea->hsMask[sd]); - nNonHsHeads += nvPopCount32(pWorkArea->nonHsMask[sd]); } + nvAssert(numFlipHeads == nNonHsApiHeads + nHsApiHeads); /* * Handle the common case: if there are no headSurface-ful heads touched by * the request, call down and return. */ - if (nHsHeads == 0) { + if (nHsApiHeads == 0) { ret = nvFlipEvo(pDevEvo, pOpenDev, - pRequest, + pFlipHead, numFlipHeads, commit, allowVrr, pReply, FALSE /* skipUpdate */, TRUE /* allowFlipLock */); goto done; } + pWorkArea = nvCalloc(1, sizeof(*pWorkArea)); + if (pWorkArea == NULL) { + goto done; + } + /* * Assign and validate flipState for any headSurface heads in the * request. */ - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - FOR_EACH_INDEX_IN_MASK(32, head, pWorkArea->hsMask[sd]) { - const NvU32 apiHead = nvHardwareHeadToApiHead(head); - if (!HsIoctlFlipAssignHwStateOneHead( - pDispEvo->pHsChannel[apiHead], - pDevEvo, - sd, - head, - pOpenDev, - &pRequest->sd[sd].head[head], - &pWorkArea->flipState[sd][head])) { - goto done; - } + for (i = 0; i < numFlipHeads; i++) { + const NvU32 apiHead = pFlipHead[i].head; + const NvU32 sd = pFlipHead[i].sd; + NVDispEvoPtr pDispEvo = pDevEvo->pDispEvo[sd]; - } FOR_EACH_INDEX_IN_MASK_END; + if ((hsMask[sd] & NVBIT(apiHead)) == 0) { + continue; + } + + if (!HsIoctlFlipAssignHwStateOneHead( + pDispEvo->pHsChannel[apiHead], + pDevEvo, + sd, + apiHead, + pOpenDev, + &pFlipHead[i].flip, + &pWorkArea->flipState[sd][apiHead])) { + goto done; + } } /* @@ -505,25 +562,59 @@ NvBool nvHsIoctlFlip( * headSurface-ful heads removed and call down. */ - if (nNonHsHeads != 0) { + if (nNonHsApiHeads != 0) { NvBool tmp; - struct NvKmsFlipRequest *pRequestLocal = - HsIoctlRemoveHsHeadsFromNvKmsFlipRequest( - pDevEvo, pRequest, pWorkArea->hsMask); + struct NvKmsFlipRequestOneHead *pFlipHeadLocal = + HsIoctlRemoveHsHeadsFromNvKmsFlipHead( + pDevEvo, pFlipHead, numFlipHeads, nNonHsApiHeads, hsMask); - if (pRequestLocal == NULL) { + if (pFlipHeadLocal == NULL) { goto done; } tmp = nvFlipEvo(pDevEvo, pOpenDev, - pRequestLocal, + pFlipHeadLocal, nNonHsApiHeads, commit, allowVrr, pReply, FALSE /* skipUpdate */, TRUE /* allowFlipLock */); - nvFree(pRequestLocal); + // nvFlipEvo filled in pReply for the heads in pFlipHeadLocal. + // Move those replies to the right location for pFlipHead. + // + // Due to how HsIoctlRemoveHsHeadsFromNvKmsFlipHead() created + // pFlipHeadLocal, the entries will be in the same order as the + // original pFlipHead request, but some of the entries have been + // removed so the original array is longer. + // + // Iterate backwards through the local array (headLocal), which points + // to where the reply data was filled in by nvFlipEvo(). + // Keep an index into the original array (headOriginal) which points to + // the entry where the reply *should* be. This should always be >= + // headLocal. + // If the expected location for the reply is not the same as the local + // index, copy the reply to the right location and clear the local data + // (which was in the wrong place). + { + NvS32 headOriginal = numFlipHeads - 1; + NvS32 headLocal; + for (headLocal = nNonHsApiHeads - 1; headLocal >= 0; headLocal--) { + while (pFlipHead[headOriginal].sd != pFlipHeadLocal[headLocal].sd || + pFlipHead[headOriginal].head != pFlipHeadLocal[headLocal].head) { + headOriginal--; + nvAssert(headOriginal >= 0); + } + if (headOriginal != headLocal) { + nvAssert(headOriginal > headLocal); + pReply->flipHead[headOriginal] = pReply->flipHead[headLocal]; + nvkms_memset(&pReply->flipHead[headLocal], 0, + sizeof(pReply->flipHead[headLocal])); + } + } + } + + nvFree(pFlipHeadLocal); if (!tmp) { goto done; @@ -537,85 +628,95 @@ NvBool nvHsIoctlFlip( /* If this is a validation-only request, we are done. */ - if (!pRequest->commit) { + if (!commit) { goto done; } - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - FOR_EACH_INDEX_IN_MASK(32, head, pWorkArea->hsMask[sd]) { - const NvU32 apiHead = nvHardwareHeadToApiHead(head); - NVHsChannelEvoRec *pHsChannel = pDispEvo->pHsChannel[apiHead]; - const struct NvKmsFlipCommonParams *pParams = - &pRequest->sd[sd].head[head]; - NVFlipEvoHwState *pFlipState = - &pWorkArea->flipState[sd][head]; + for (i = 0; i < numFlipHeads; i++) { + const NvU32 apiHead = pFlipHead[i].head; + const NvU32 sd = pFlipHead[i].sd; + NVDispEvoPtr pDispEvo = pDevEvo->pDispEvo[sd]; - if (!nvHeadIsActive(pDispEvo, head)) { - continue; - } + if ((hsMask[sd] & NVBIT(apiHead)) == 0) { + continue; + } - if (pParams->layer[NVKMS_MAIN_LAYER].skipPendingFlips && - pFlipState->dirty.layer[NVKMS_MAIN_LAYER]) { - nvHsIdleFlipQueue(pHsChannel, TRUE /* force */); - } - } FOR_EACH_INDEX_IN_MASK_END; + NVHsChannelEvoRec *pHsChannel = pDispEvo->pHsChannel[apiHead]; + const struct NvKmsFlipCommonParams *pParams = + &pFlipHead[i].flip; + NVHsRequestedFlipState *pFlipState = + &pWorkArea->flipState[sd][apiHead]; + + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { + continue; + } + + if (pParams->layer[NVKMS_MAIN_LAYER].skipPendingFlips && + pFlipState->dirty.layer[NVKMS_MAIN_LAYER]) { + nvHsIdleFlipQueue(pHsChannel, TRUE /* force */); + } } /* Finally, update the headSurface-ful heads in the request. */ - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - FOR_EACH_INDEX_IN_MASK(32, head, pWorkArea->hsMask[sd]) { - const NvU32 apiHead = nvHardwareHeadToApiHead(head); - const NVFlipEvoHwState *pFlipState = - &pWorkArea->flipState[sd][head]; + for (i = 0; i < numFlipHeads; i++) { + const NvU32 apiHead = pFlipHead[i].head; + const NvU32 sd = pFlipHead[i].sd; + NVDispEvoPtr pDispEvo = pDevEvo->pDispEvo[sd]; - NVHsChannelEvoRec *pHsChannel = pDispEvo->pHsChannel[apiHead]; - NvU32 layer; + if ((hsMask[sd] & NVBIT(apiHead)) == 0) { + continue; + } - nvAssert(pHsChannel != NULL); + const NVHsRequestedFlipState *pFlipState = + &pWorkArea->flipState[sd][apiHead]; - if (pFlipState->dirty.cursorPosition) { - HsIoctlMoveCursor( - pHsChannel, - pFlipState->cursor.x, - pFlipState->cursor.y); + NVHsChannelEvoRec *pHsChannel = pDispEvo->pHsChannel[apiHead]; + NvU32 layer; + + nvAssert(pHsChannel != NULL); + + if (pFlipState->dirty.cursorPosition) { + HsIoctlMoveCursor( + pHsChannel, + pFlipState->cursor.x, + pFlipState->cursor.y); + } + + if (pFlipState->dirty.cursorSurface) { + HsIoctlSetCursorImage( + pHsChannel, + pFlipState->cursor.pSurfaceEvo); + } + + if (pFlipState->dirty.viewPortPointIn) { + HsIoctlPan(pHsChannel, &pFlipState->viewPortPointIn); + } + + /* + * XXX NVKMS HEADSURFACE TODO: Layers that are specified as part + * of the same NVKMS_IOCTL_FLIP request should be flipped + * atomically. But, layers that are specified separately should + * be allowed to flip separately. Update the headSurface flip + * queue handling to coordinate multi-layer atomic flips. + */ + for (layer = 0; layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { + if (!pFlipState->dirty.layer[layer]) { + continue; } - if (pFlipState->dirty.cursorSurface) { - HsIoctlSetCursorImage( - pHsChannel, - pFlipState->cursor.pSurfaceEvo); + if (layer == NVKMS_MAIN_LAYER) { + HsIoctlAssignSurfacesMaxEyes( + pHsChannel->flipQueueMainLayerState.pSurfaceEvo, + pFlipState->layer[layer].pSurfaceEvo); } - if (pFlipState->dirty.viewPortPointIn) { - HsIoctlPan(pHsChannel, &pFlipState->viewPortPointIn); + nvHsPushFlipQueueEntry(pHsChannel, layer, &pFlipState->layer[layer]); + + if (pHsChannel->config.neededForSwapGroup) { + pHsChannel->swapGroupFlipping = NV_TRUE; } - - /* - * XXX NVKMS HEADSURFACE TODO: Layers that are specified as part - * of the same NVKMS_IOCTL_FLIP request should be flipped - * atomically. But, layers that are specified separately should - * be allowed to flip separately. Update the headSurface flip - * queue handling to coordinate multi-layer atomic flips. - */ - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if (!pFlipState->dirty.layer[layer]) { - continue; - } - - if (layer == NVKMS_MAIN_LAYER) { - HsIoctlAssignSurfacesMaxEyes( - pHsChannel->flipQueueMainLayerState.pSurfaceEvo, - pFlipState->layer[layer].pSurfaceEvo); - } - - nvHsPushFlipQueueEntry(pHsChannel, layer, &pFlipState->layer[layer]); - - if (pHsChannel->config.neededForSwapGroup) { - pHsChannel->swapGroupFlipping = NV_TRUE; - } - } - } FOR_EACH_INDEX_IN_MASK_END; + } } done: diff --git a/src/nvidia-modeset/src/nvkms-headsurface-swapgroup.c b/src/nvidia-modeset/src/nvkms-headsurface-swapgroup.c index d216cdec7..6f3229004 100644 --- a/src/nvidia-modeset/src/nvkms-headsurface-swapgroup.c +++ b/src/nvidia-modeset/src/nvkms-headsurface-swapgroup.c @@ -414,7 +414,7 @@ static NvBool HsSwapGroupValidateConfig( const NVDevEvoRec *pDevEvo, const struct NvKmsSwapGroupConfig *pConfig) { - const NvU32 validHeadMask = NVBIT(pDevEvo->numHeads) - 1; + const NvU32 validHeadMask = NVBIT(pDevEvo->numApiHeads) - 1; NvU32 dispIndex; for (dispIndex = 0; dispIndex < ARRAY_LEN(pConfig->disp); dispIndex++) { @@ -460,9 +460,8 @@ NVSwapGroupRec* nvHsAllocSwapGroup( /* Are there heads requested that already belong to another SwapGroup? */ FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - NvU32 head; - FOR_ALL_HEADS(head, pRequest->config.disp[dispIndex].headMask) { - const NvU32 apiHead = nvHardwareHeadToApiHead(head); + NvU32 apiHead; + FOR_ALL_HEADS(apiHead, pRequest->config.disp[dispIndex].headMask) { if (pDispEvo->pSwapGroup[apiHead] != NULL) { return NULL; } @@ -483,9 +482,8 @@ NVSwapGroupRec* nvHsAllocSwapGroup( nvListInit(&pSwapGroup->deferredRequestFifoList); FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - NvU32 head; - FOR_ALL_HEADS(head, pRequest->config.disp[dispIndex].headMask) { - const NvU32 apiHead = nvHardwareHeadToApiHead(head); + NvU32 apiHead; + FOR_ALL_HEADS(apiHead, pRequest->config.disp[dispIndex].headMask) { pDispEvo->pSwapGroup[apiHead] = pSwapGroup; } } diff --git a/src/nvidia-modeset/src/nvkms-headsurface.c b/src/nvidia-modeset/src/nvkms-headsurface.c index 42777c097..968b934d4 100644 --- a/src/nvidia-modeset/src/nvkms-headsurface.c +++ b/src/nvidia-modeset/src/nvkms-headsurface.c @@ -475,7 +475,7 @@ static NvU32 HsGetSemaphoreIndex( } /*! - * Read the payload of the semaphore described in the pHwState. + * Read the payload of the semaphore described in the pSemaSurface. */ static NvU32 HsFlipQueueReadSemaphore( const NVHsChannelEvoRec *pHsChannel, @@ -503,16 +503,16 @@ static NvU32 HsFlipQueueReadSemaphore( } /*! - * Return whether the specified pHwState is ready to flip. + * Return whether the specified pFlipState is ready to flip. */ static NvBool HsFlipQueueEntryIsReady( const NVHsChannelEvoRec *pHsChannel, - const NVFlipChannelEvoHwState *pHwState) + const NVHsLayerRequestedFlipState *pFlipState) { const NVFlipNIsoSurfaceEvoHwState *pSemaSurface = - &pHwState->syncObject.u.semaphores.acquireSurface; + &pFlipState->syncObject.u.semaphores.acquireSurface; - if (pHwState->syncObject.usingSyncpt) { + if (pFlipState->syncObject.usingSyncpt) { return TRUE; } @@ -527,9 +527,9 @@ static NvBool HsFlipQueueEntryIsReady( if (pHsChannel->swapGroupFlipping) { // With swap group flipping, the client semaphore should be // written before the non-stall interrupt kicking off the flip. - nvAssert(semaphoreValue == pHwState->syncObject.u.semaphores.acquireValue); + nvAssert(semaphoreValue == pFlipState->syncObject.u.semaphores.acquireValue); } else { - if (semaphoreValue != pHwState->syncObject.u.semaphores.acquireValue) { + if (semaphoreValue != pFlipState->syncObject.u.semaphores.acquireValue) { return FALSE; } } @@ -546,43 +546,40 @@ static NvBool HsFlipQueueEntryIsReady( } /*! - * Update the reference count of all the surfaces described in the pHwState. + * Update the reference count of all the surfaces described in the pFlipState. */ static void HsUpdateFlipQueueEntrySurfaceRefCount( - const NVFlipChannelEvoHwState *pHwState, + const NVHsLayerRequestedFlipState *pFlipState, NvBool increase) { HsChangeSurfaceFlipRefCount( - pHwState->pSurfaceEvo[NVKMS_LEFT], increase); + pFlipState->pSurfaceEvo[NVKMS_LEFT], increase); HsChangeSurfaceFlipRefCount( - pHwState->pSurfaceEvo[NVKMS_RIGHT], increase); + pFlipState->pSurfaceEvo[NVKMS_RIGHT], increase); - HsChangeSurfaceFlipRefCount( - pHwState->completionNotifier.surface.pSurfaceEvo, increase); - - if (!pHwState->syncObject.usingSyncpt) { + if (!pFlipState->syncObject.usingSyncpt) { HsChangeSurfaceFlipRefCount( - pHwState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo, increase); + pFlipState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo, increase); HsChangeSurfaceFlipRefCount( - pHwState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo, increase); + pFlipState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo, increase); } } /*! - * Update bookkeeping for "flipping away" from a pHwState. + * Update bookkeeping for "flipping away" from a pFlipState. */ static void HsReleaseFlipQueueEntry( NVDevEvoPtr pDevEvo, NVHsChannelEvoPtr pHsChannel, - const NVFlipChannelEvoHwState *pHwState) + const NVHsLayerRequestedFlipState *pFlipState) { /* * If a semaphore surface was specified, we can now write its release value. */ - if (!pHwState->syncObject.usingSyncpt && - pHwState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo != NULL) { + if (!pFlipState->syncObject.usingSyncpt && + pFlipState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo != NULL) { /* * XXX NVKMS HEADSURFACE TODO: write the timestamp in the EVO/NVDisplay @@ -594,18 +591,18 @@ static void HsReleaseFlipQueueEntry( */ nvHs3dReleaseSemaphore(pHsChannel, - pHwState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo, - pHwState->syncObject.u.semaphores.releaseSurface.format, - pHwState->syncObject.u.semaphores.releaseSurface.offsetInWords, - pHwState->syncObject.u.semaphores.releaseValue, + pFlipState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo, + pFlipState->syncObject.u.semaphores.releaseSurface.format, + pFlipState->syncObject.u.semaphores.releaseSurface.offsetInWords, + pFlipState->syncObject.u.semaphores.releaseValue, TRUE /* allPreceedingReads */); } /* - * HeadSurface no longer needs to read from the surfaces in pHwState; + * HeadSurface no longer needs to read from the surfaces in pFlipState; * decrement their reference counts. */ - HsUpdateFlipQueueEntrySurfaceRefCount(pHwState, FALSE); + HsUpdateFlipQueueEntrySurfaceRefCount(pFlipState, FALSE); } /*! @@ -680,12 +677,12 @@ static void HsFastForwardFlipQueue( * * \param[in,out] pHsChannel The headSurface channel. * \param[in] layer The layer of the flip queue. - * \param[in] pHwState The hwState to be pushed on the flip queue. + * \param[in] pFlipState The hwState to be pushed on the flip queue. */ void nvHsPushFlipQueueEntry( NVHsChannelEvoPtr pHsChannel, const NvU8 layer, - const NVFlipChannelEvoHwState *pHwState) + const NVHsLayerRequestedFlipState *pFlipState) { NVListRec *pFlipQueue = &pHsChannel->flipQueue[layer].queue; NVHsChannelFlipQueueEntry *pEntry = nvCalloc(1, sizeof(*pEntry)); @@ -699,7 +696,7 @@ void nvHsPushFlipQueueEntry( return; } - pEntry->hwState = *pHwState; + pEntry->hwState = *pFlipState; /* Increment the ref counts on the surfaces in the flip queue entry. */ @@ -720,26 +717,26 @@ void nvHsPushFlipQueueEntry( * Remove the first entry in the flip queue and return it. * * If the first entry in the flipQueue is ready to be consumed by headSurface, - * remove it from the list and return it in the 'pHwState' argument. + * remove it from the list and return it in the 'pFlipState' argument. * * If this function returns TRUE, it is the caller's responsibility to * eventually call * - * HsUpdateFlipQueueEntrySurfaceRefCount(pHwState, FALSE) + * HsUpdateFlipQueueEntrySurfaceRefCount(pFlipState, FALSE) * - * for the returned pHwState. + * for the returned pFlipState. * * \param[in,out] pHsChannel The headSurface channel. * \param[in] layer The layer of the flip queue. - * \param[out] pHwState The hwState that was popped off the flip queue. + * \param[out] pFlipState The hwState that was popped off the flip queue. * * \return Return TRUE if a flip queue entry was popped off the queue and - * copied into pHwState. + * copied into pFlipState. */ static NvBool HsPopFlipQueueEntry( NVHsChannelEvoPtr pHsChannel, const NvU8 layer, - NVFlipChannelEvoHwState *pHwState) + NVHsLayerRequestedFlipState *pFlipState) { NVListRec *pFlipQueue = &pHsChannel->flipQueue[layer].queue; NVHsChannelFlipQueueEntry *pEntry; @@ -756,7 +753,7 @@ static NvBool HsPopFlipQueueEntry( return FALSE; } - *pHwState = pEntry->hwState; + *pFlipState = pEntry->hwState; nvListDel(&pEntry->flipQueueEntry); nvFree(pEntry); @@ -779,7 +776,7 @@ static void HsUpdateFlipQueueCurrent( for (layer = 0; layer < ARRAY_LEN(pHsChannel->flipQueue); layer++) { - NVFlipChannelEvoHwState newCurrent = { }; + NVHsLayerRequestedFlipState newCurrent = { }; /* * XXX NVKMS HEADSURFACE TODO: fast forward to the last ready flip queue @@ -1204,8 +1201,6 @@ static void HsFlipHelper( const NvBool allowFlipLock) { NVDevEvoRec *pDevEvo = pHsDevice->pDevEvo; - struct NvKmsFlipRequest *pRequest; - struct NvKmsFlipParams *pFlipParams; struct NvKmsFlipCommonParams *pParamsOneHead; NVHsNotifiersRec *pHsNotifiers = &pHsDevice->notifiers; const NvU32 sd = pHsChannel->pDispEvo->displayOwner; @@ -1213,18 +1208,16 @@ static void HsFlipHelper( NvBool ret; /* - * Use a preallocated NvKmsFlipParams, so that we don't have to allocate + * Use preallocated memory, so that we don't have to allocate * memory here (and deal with allocation failure). */ - pFlipParams = &pHsChannel->scratchParams; + struct NvKmsFlipRequestOneHead *pFlipHead = &pHsChannel->scratchParams; - nvkms_memset(pFlipParams, 0, sizeof(*pFlipParams)); + nvkms_memset(pFlipHead, 0, sizeof(*pFlipHead)); - pRequest = &pFlipParams->request; - - pParamsOneHead = &pRequest->sd[sd].head[apiHead]; - - pRequest->commit = NV_TRUE; + pFlipHead->sd = sd; + pFlipHead->head = apiHead; + pParamsOneHead = &pFlipHead->flip; if (isFirstFlip) { /* @@ -1264,8 +1257,6 @@ static void HsFlipHelper( pParamsOneHead->layer[NVKMS_MAIN_LAYER].completionNotifier.specified = TRUE; - pRequest->sd[sd].requestedHeadsBitMask = NVBIT(apiHead); - if (surfaceHandles[NVKMS_LEFT] != 0) { NVEvoApiHandlesRec *pOpenDevSurfaceHandles = nvGetSurfaceHandlesFromOpenDev(pDevEvo->pNvKmsOpenDev); @@ -1309,8 +1300,11 @@ static void HsFlipHelper( ret = nvFlipEvo(pDevEvo, pDevEvo->pNvKmsOpenDev, - pRequest, - &pFlipParams->reply, + pFlipHead, + 1 /* numFlipHeads */, + TRUE /* commit */, + FALSE /* allowVrr */, + NULL /* pReply */, FALSE /* skipUpdate */, allowFlipLock); @@ -1818,11 +1812,9 @@ void nvHsProcessPendingViewportFlips(NVDevEvoPtr pDevEvo) */ static void HsProcFsRecordScanline( const NVDispEvoRec *pDispEvo, - const NvU32 head) + const NvU32 apiHead) { #if NVKMS_PROCFS_ENABLE - const NvU32 apiHead = nvHardwareHeadToApiHead(head); - const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; NVHsChannelEvoRec *pHsChannel = pDispEvo->pHsChannel[apiHead]; NvU16 scanLine = 0; NvBool inBlankingPeriod = FALSE; @@ -1831,7 +1823,7 @@ static void HsProcFsRecordScanline( return; } - pDevEvo->hal->GetScanLine(pDispEvo, head, &scanLine, &inBlankingPeriod); + nvApiHeadGetScanLine(pDispEvo, apiHead, &scanLine, &inBlankingPeriod); if (inBlankingPeriod) { pHsChannel->statistics.scanLine.nInBlankingPeriod++; @@ -2124,11 +2116,12 @@ static NvBool HsCanOmitNonSgHsUpdate(NVHsChannelEvoPtr pHsChannel) /*! * Receive RG line 1 callback, in process context with nvkms_lock held. */ -static void HsServiceRGLineInterrupt(void *dataPtr, NvU32 dataU32) +static void HsRgLine1CallbackProc(NVDispEvoRec *pDispEvo, + const NvU32 head, + NVRgLine1CallbackPtr pCallback) { - NVDispEvoRec *pDispEvo = (NVDispEvoRec *)dataPtr; - NvU32 head = dataU32; - const NvU32 apiHead = nvHardwareHeadToApiHead(head); + const NvU32 apiHead = + (NvU32)(NvUPtr)pCallback->pUserData; NVHsChannelEvoPtr pHsChannel = pDispEvo->pHsChannel[apiHead]; /* @@ -2156,7 +2149,7 @@ static void HsServiceRGLineInterrupt(void *dataPtr, NvU32 dataU32) * flip to the render offset. */ NvU32 activeViewportOffset = - pDispEvo->pDevEvo->hal->GetActiveViewportOffset(pDispEvo, head); + nvApiHeadGetActiveViewportOffset(pDispEvo, apiHead); nvAssert((activeViewportOffset == 0) || (activeViewportOffset == pHsChannel->config.frameSize.height)); @@ -2178,7 +2171,7 @@ static void HsServiceRGLineInterrupt(void *dataPtr, NvU32 dataU32) } else { NVHsDeviceEvoRec *pHsDevice = pDispEvo->pDevEvo->pHsDevice; - HsProcFsRecordScanline(pDispEvo, head); + HsProcFsRecordScanline(pDispEvo, apiHead); if (HsCanOmitNonSgHsUpdate(pHsChannel)) { HsProcFsRecordOmittedNonSgHsUpdate(pHsChannel); @@ -2203,10 +2196,9 @@ static void HsServiceRGLineInterrupt(void *dataPtr, NvU32 dataU32) * */ static void HsVBlankCallback(NVDispEvoRec *pDispEvo, - const NvU32 head, NVVBlankCallbackPtr pCallbackData) { - const NvU32 apiHead = nvHardwareHeadToApiHead(head); + const NvU32 apiHead = pCallbackData->apiHead; NVHsChannelEvoPtr pHsChannel = pDispEvo->pHsChannel[apiHead]; NVHsDeviceEvoRec *pHsDevice = pDispEvo->pDevEvo->pHsDevice; @@ -2238,7 +2230,7 @@ static void HsVBlankCallback(NVDispEvoRec *pDispEvo, return; } - HsProcFsRecordScanline(pDispEvo, head); + HsProcFsRecordScanline(pDispEvo, apiHead); /* * XXX NVKMS HEADSURFACE TODO: evaluate whether there has been @@ -2260,29 +2252,6 @@ static void HsVBlankCallback(NVDispEvoRec *pDispEvo, } } -/*! - * Receive RG line 1 interrupt notification from resman. - * - * This function is registered as the kernel callback function from resman when - * the RG line 1 interrupt is generated. - * - * This function is called within resman's context, so we schedule a zero timer - * callback to process the swapgroup check and release without holding the - * resman lock. - */ -static void HsRGLineInterruptCallback(NvU32 rgIntrLine, void *param1, - NvBool bIsIrqlIsr /* unused */) -{ - void *pDispEvoRefPtr = (void *)((NvUPtr)param1 & - ~(NVKMS_MAX_HEADS_PER_DISP-1)); - NvU32 head = (NvUPtr)param1 & (NVKMS_MAX_HEADS_PER_DISP-1); - (void) nvkms_alloc_timer_with_ref_ptr( - HsServiceRGLineInterrupt, /* callback */ - pDispEvoRefPtr, /* ref_ptr */ - head, /* dataU32 */ - 0); /* usec */ -} - /*! * Schedule vblank callbacks from resman on a specific head and subdevice. */ @@ -2309,7 +2278,7 @@ void nvHsAddVBlankCallback(NVHsChannelEvoPtr pHsChannel) */ void nvHsAddRgLine1Callback(NVHsChannelEvoPtr pHsChannel) { - const NVDispEvoRec *pDispEvo = pHsChannel->pDispEvo; + NVDispEvoRec *pDispEvo = pHsChannel->pDispEvo; NvBool found; NvU32 val; @@ -2325,12 +2294,13 @@ void nvHsAddRgLine1Callback(NVHsChannelEvoPtr pHsChannel) return; } - pHsChannel->rgIntrCallbackObjectHandle = + pHsChannel->pRgIntrCallback = nvApiHeadAddRgLine1Callback(pDispEvo, pHsChannel->apiHead, - HsRGLineInterruptCallback); + HsRgLine1CallbackProc, + (void*)(NvUPtr)pHsChannel->apiHead); - if (pHsChannel->rgIntrCallbackObjectHandle == 0) { + if (pHsChannel->pRgIntrCallback == NULL) { nvAssert(!"Failed to register headSurface RG line 1 interrupt"); } else { pHsChannel->usingRgIntrForSwapGroups = TRUE; @@ -2349,8 +2319,8 @@ void nvHsRemoveRgLine1Callback(NVHsChannelEvoPtr pHsChannel) if (pHsChannel->usingRgIntrForSwapGroups) { nvRmRemoveRgLine1Callback(pDispEvo, - pHsChannel->rgIntrCallbackObjectHandle); - pHsChannel->rgIntrCallbackObjectHandle = 0; + pHsChannel->pRgIntrCallback); + pHsChannel->pRgIntrCallback = NULL; } } @@ -2372,7 +2342,6 @@ void nvHsRemoveVBlankCallback(NVHsChannelEvoPtr pHsChannel) NVDispEvoRec *pDispEvo = pHsChannel->pDispEvo; nvApiHeadUnregisterVBlankCallback(pDispEvo, - pHsChannel->apiHead, pHsChannel->vBlankCallback); pHsChannel->vBlankCallback = NULL; } @@ -2630,7 +2599,7 @@ static void HsProcFsScanLine( static void HsProcFsFlipQueueOneEntry( NVEvoInfoStringRec *pInfoString, - const NVFlipChannelEvoHwState *pFlipState) + const NVHsLayerRequestedFlipState *pFlipState) { /* * Print the pointers by casting to NvUPtr and formatting with NvUPtr_fmtx, @@ -2831,24 +2800,23 @@ void nvHsProcFs( NVEvoInfoStringRec *pInfoString, NVDevEvoRec *pDevEvo, NvU32 dispIndex, - NvU32 head) + NvU32 apiHead) { NVDispEvoPtr pDispEvo = pDevEvo->pDispEvo[dispIndex]; - const NvU32 apiHead = nvHardwareHeadToApiHead(head); const NVHsChannelEvoRec *pHsChannel = pDispEvo->pHsChannel[apiHead]; const NVHsStateOneHeadAllDisps *pHsOneHeadAllDisps = &pDevEvo->apiHeadSurfaceAllDisps[apiHead]; if (pHsChannel == NULL) { nvEvoLogInfoString(pInfoString, - " headSurface[head:%02d] : disabled", head); + " headSurface[head:%02d] : disabled", apiHead); return; } nvEvoLogInfoString(pInfoString, " headSurface[head:%02d] : " "enabled (needed for: %s)", - head, HsProcFsGetNeededForString(pHsChannel)); + apiHead, HsProcFsGetNeededForString(pHsChannel)); HsProcFsFrameStatistics(pInfoString, pHsChannel); diff --git a/src/nvidia-modeset/src/nvkms-hw-flip.c b/src/nvidia-modeset/src/nvkms-hw-flip.c new file mode 100644 index 000000000..a20f0a087 --- /dev/null +++ b/src/nvidia-modeset/src/nvkms-hw-flip.c @@ -0,0 +1,2785 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvkms-dma.h" +#include "nvkms-evo.h" +#include "nvkms-hw-flip.h" +#include "nvkms-utils-flip.h" +#include "nvkms-flip-workarea.h" +#include "nvkms-surface.h" +#include "nvkms-prealloc.h" +#include "nvkms-private.h" +#include "nvkms-rm.h" +#include "nvkms-vrr.h" +#include "nvkms-cursor.h" +#include "nvkms-types.h" +#include "nvkms-dpy.h" +#include "nvkms-lut.h" +#include "nvkms-softfloat.h" + +#include "nvkms-sync.h" + +#include "nvkms-difr.h" + +static void SchedulePostFlipIMPTimer(NVDevEvoPtr pDevEvo); + +// The EVO .mfs file defines the maximum minPresentInterval to be 8. +#define NV_MAX_SWAP_INTERVAL 8 + +static NvBool AssignPreSyncptEvoHwState( + const NVDevEvoRec *pDevEvo, + const struct NvKmsChannelSyncObjects *pChannelSyncObjects, + NVFlipSyncObjectEvoHwState *pFlipSyncObject) +{ + NvBool ret; + NvU32 id = 0; + NvU32 value; + enum NvKmsSyncptType preType; + + nvAssert(pChannelSyncObjects->useSyncpt); + + preType = pChannelSyncObjects->u.syncpts.pre.type; + + if (preType == NVKMS_SYNCPT_TYPE_NONE) { + return TRUE; + } + + if (preType == NVKMS_SYNCPT_TYPE_FD) { + /*! Get id from fd using nvhost API */ + NvKmsSyncPtOpParams params = { }; + params.fd_to_id_and_thresh.fd = + pChannelSyncObjects->u.syncpts.pre.u.fd; + ret = nvkms_syncpt_op(NVKMS_SYNCPT_OP_FD_TO_ID_AND_THRESH, + ¶ms); + if (!ret) { + return FALSE; + } + id = params.fd_to_id_and_thresh.id; + value = params.fd_to_id_and_thresh.thresh; + } else { + id = pChannelSyncObjects->u.syncpts.pre.u.raw.id; + value = pChannelSyncObjects->u.syncpts.pre.u.raw.value; + } + if (id >= NV_SYNCPT_GLOBAL_TABLE_LENGTH) { + return FALSE; + } + /*! Fill pre-syncpt related information in hardware state */ + pFlipSyncObject->u.syncpts.preSyncpt = id; + pFlipSyncObject->u.syncpts.preValue = value; + pFlipSyncObject->u.syncpts.isPreSyncptSpecified = TRUE; + pFlipSyncObject->usingSyncpt = TRUE; + + return TRUE; +} + +static NvBool AssignPostSyncptEvoHwState( + const NVDevEvoRec *pDevEvo, + NVEvoChannel *pChannel, + const struct NvKmsChannelSyncObjects *pChannelSyncObjects, + NVFlipSyncObjectEvoHwState *pFlipSyncObject) +{ + enum NvKmsSyncptType postType; + NvU32 threshold; + + nvAssert(pChannelSyncObjects->useSyncpt); + + postType = pChannelSyncObjects->u.syncpts.requestedPostType; + + /*! + * It is possible that syncpt is mentioned but post-syncpt + * is not specified (case where only pre-syncpt used) + */ + if (postType == NVKMS_SYNCPT_TYPE_NONE) { + return TRUE; + } + + /*! return threshold to caller but increase only when programming hw */ + threshold = pChannel->postSyncpt.syncptMaxVal + 1; + + /*! each channel associated with one post-syncpt */ + pFlipSyncObject->u.syncpts.postCtxDma = pChannel->postSyncpt.hCtxDma; + pFlipSyncObject->u.syncpts.postValue = threshold; + + pFlipSyncObject->usingSyncpt = TRUE; + + return TRUE; +} + +void nvFillPostSyncptReplyOneChannel( + NVEvoChannel *pChannel, + enum NvKmsSyncptType postType, + struct NvKmsSyncpt *postSyncpt, + const NVFlipSyncObjectEvoHwState *pHwSyncObject) +{ + if (postType == NVKMS_SYNCPT_TYPE_RAW) { + postSyncpt->u.raw.id = pChannel->postSyncpt.id; + postSyncpt->u.raw.value = pHwSyncObject->u.syncpts.postValue; + postSyncpt->type = NVKMS_SYNCPT_TYPE_RAW; + } else if (postType == NVKMS_SYNCPT_TYPE_FD) { + NvBool ret = TRUE; + NvKmsSyncPtOpParams params = { }; + params.id_and_thresh_to_fd.id = pChannel->postSyncpt.id; + params.id_and_thresh_to_fd.thresh = + pHwSyncObject->u.syncpts.postValue; + + ret = nvkms_syncpt_op(NVKMS_SYNCPT_OP_ID_AND_THRESH_TO_FD, ¶ms); + if (!ret) { + nvAssert(!"Failed syncpt op ID_AND_THRESH_TO_FD"); + return; + } + postSyncpt->u.fd = params.id_and_thresh_to_fd.fd; + postSyncpt->type = NVKMS_SYNCPT_TYPE_FD; + } +} + +static NvBool GetPreSyncptCtxDma(NVDevEvoRec *pDevEvo, + NVEvoChannel *pChannel, const NvU32 id) +{ + NvU32 hSyncptCtxDma, hSyncpt; + + /*! use id value to check the global table */ + if (pDevEvo->preSyncptTable[id].hCtxDma == 0) { + /*! Register - allocate and bind ctxdma to syncpt*/ + if (!nvRmEvoAllocAndBindSyncpt(pDevEvo, + pChannel, + id, + &hSyncpt, + &hSyncptCtxDma)) { + nvAssert(!"Failed to register pre-syncpt"); + return FALSE; + } + + /*! Fill the Entry in Global Table */ + pDevEvo->preSyncptTable[id].hCtxDma = hSyncptCtxDma; + pDevEvo->preSyncptTable[id].hSyncpt = hSyncpt; + pDevEvo->preSyncptTable[id].channelMask |= pChannel->channelMask; + pDevEvo->preSyncptTable[id].id = id; + } else { + /*! + * syncpt found, just bind the context dma of this syncpt + * to the window if it is not already. + */ + if ((pDevEvo->preSyncptTable[id].channelMask & + pChannel->channelMask) == 0) { + + NvU32 ret = + nvRmEvoBindDispContextDMA(pDevEvo, + pChannel, + pDevEvo->preSyncptTable[id].hCtxDma); + if (ret != NVOS_STATUS_SUCCESS) { + nvAssert(!"Failed to bind pre-syncpt with ctxdma"); + } + pDevEvo->preSyncptTable[id].channelMask |= pChannel->channelMask; + /*! hSyncpt already allocated for id*/ + } + } + + return TRUE; +} + +static NvBool RegisterPreSyncpt(NVDevEvoRec *pDevEvo, + struct NvKmsFlipWorkArea *pWorkArea) +{ + NvU32 sd; + NvU32 ret = TRUE; + const NVDispEvoRec *pDispEvo; + + pDevEvo->pAllSyncptUsedInCurrentFlip = + nvCalloc(1, sizeof(NvBool) * NV_SYNCPT_GLOBAL_TABLE_LENGTH); + if (pDevEvo->pAllSyncptUsedInCurrentFlip == NULL) { + ret = FALSE; + goto done; + } + + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + NvU32 head; + for (head = 0; head < ARRAY_LEN(pWorkArea->sd[sd].head); head++) { + NVFlipEvoHwState *pFlipState = + &pWorkArea->sd[sd].head[head].newState; + NvU32 layer; + + for (layer = 0; layer < ARRAY_LEN(pFlipState->layer); layer++) { + NVFlipSyncObjectEvoHwState *pFlipSyncObject = + &pFlipState->layer[layer].syncObject; + NvU32 preSyncpt = pFlipSyncObject->u.syncpts.preSyncpt; + + if (!pFlipState->dirty.layerSyncObjects[layer] || + !pFlipSyncObject->usingSyncpt || + !pFlipSyncObject->u.syncpts.isPreSyncptSpecified) { + continue; + } + + if (!GetPreSyncptCtxDma(pDevEvo, + pDevEvo->head[head].layer[layer], + preSyncpt)) { + ret = FALSE; + goto done; + } + + pDevEvo->pAllSyncptUsedInCurrentFlip[preSyncpt] = NV_TRUE; + } + } + } + +done: + nvFree(pDevEvo->pAllSyncptUsedInCurrentFlip); + pDevEvo->pAllSyncptUsedInCurrentFlip = NULL; + + return ret; +} + +void nvClearFlipEvoHwState( + NVFlipEvoHwState *pFlipState) +{ + NvU32 i; + + nvkms_memset(pFlipState, 0, sizeof(*pFlipState)); + + for (i = 0; i < ARRAY_LEN(pFlipState->layer); i++) { + pFlipState->layer[i].cscMatrix = NVKMS_IDENTITY_CSC_MATRIX; + } +} + +/*! + * Initialize NVFlipEvoHwState with a current snapshot from headState. + */ +void nvInitFlipEvoHwState( + const NVDevEvoRec *pDevEvo, + const NvU32 sd, + const NvU32 head, + NVFlipEvoHwState *pFlipState) +{ + NVDispEvoRec *pDispEvo = pDevEvo->gpus[sd].pDispEvo; + const NVEvoSubDevHeadStateRec *pSdHeadState; + NvU32 i; + + nvClearFlipEvoHwState(pFlipState); + + if (!nvHeadIsActive(pDispEvo, head)) { + return; + } + + pSdHeadState = &pDevEvo->gpus[sd].headState[head]; + + pFlipState->viewPortPointIn = pSdHeadState->viewPortPointIn; + pFlipState->cursor = pSdHeadState->cursor; + + ct_assert(ARRAY_LEN(pFlipState->layer) == ARRAY_LEN(pSdHeadState->layer)); + + for (i = 0; i < ARRAY_LEN(pFlipState->layer); i++) { + pFlipState->layer[i] = pSdHeadState->layer[i]; + } + + // pFlipState->usage describes the usage bounds that will be necessary after + // this flip is complete. Initialize it using pSdHeadState->targetUsage, + // which describes the usage bounds that will be required just before this + // flip occurs, rather than pSdHeadState->usage, which describes the usage + // bounds currently programmed into the hardware. + // + // pSdHeadState->usage may have higher bounds than pSdHeadState->targetUsage + // if TryLoweringUsageBounds has not yet noticed that a satellite channel is + // no longer in use, or a flip to NULL in a satellite channel is pending but + // has not yet occurred. + pFlipState->usage = pSdHeadState->targetUsage; + + pFlipState->disableMidFrameAndDWCFWatermark = + pSdHeadState->targetDisableMidFrameAndDWCFWatermark; +} + + +NvBool nvIsLayerDirty(const struct NvKmsFlipCommonParams *pParams, + const NvU32 layer) +{ + return pParams->layer[layer].surface.specified || + pParams->layer[layer].sizeIn.specified || + pParams->layer[layer].sizeOut.specified || + pParams->layer[layer].outputPosition.specified || + pParams->layer[layer].completionNotifier.specified || + pParams->layer[layer].syncObjects.specified || + pParams->layer[layer].compositionParams.specified || + pParams->layer[layer].csc.specified || + pParams->layer[layer].hdr.specified || + pParams->layer[layer].colorspace.specified; +} + +/*! + * Determine whether a base channel flip requires a non-tearing present mode. + * + * EVO requires a non-tearing flip when certain parameters are changing. See + * NV_DISP_BASE_STATE_ERROR_052 in dispClass024XBaseUpdateErrorChecks.mfs. + */ +static NvBool FlipRequiresNonTearingMode( + const NVDevEvoRec *pDevEvo, + const NvU32 head, + const NVFlipChannelEvoHwState *pOld, + const NVFlipChannelEvoHwState *pNew) +{ + // TODO: Do we need to care about the right eye here? The error check + // doesn't. + const NVSurfaceEvoRec *pOldSurf = pOld->pSurfaceEvo[NVKMS_LEFT]; + const NVSurfaceEvoRec *pNewSurf = pNew->pSurfaceEvo[NVKMS_LEFT]; + NvU32 oldHwFormat = 0, newHwFormat = 0; + + if (pOldSurf == NULL || pNewSurf == NULL) { + return TRUE; + } + + // If these functions actually return FALSE at this point, then something is + // really wrong... + if (!pDevEvo->hal->ValidateWindowFormat( + pOldSurf->format, NULL, &oldHwFormat)) { + nvAssert(FALSE); + } + + if (!pDevEvo->hal->ValidateWindowFormat( + pNewSurf->format, NULL, &newHwFormat)) { + nvAssert(FALSE); + } + + // Commented entries are things checked in the .mfs that are not yet + // supported in NVKMS. + return // SuperSample + oldHwFormat != newHwFormat || + // Gamma + // Layout (i.e. frame, field1, or field2) + pOldSurf->widthInPixels != pNewSurf->widthInPixels || + pOldSurf->heightInPixels != pNewSurf->heightInPixels || + pOldSurf->layout != pNewSurf->layout; + // UseGainOfs + // NewBaseLut -- USE_CORE_LUT is programmed in InitChannel* + // NewOutputLut +} + + +/*! + * Apply flip overrides if necessary. + * + * 1. Override swap intervals for VRR. + * 2. If the flip is changing certain parameters, override the tearing mode. + */ +static NvBool ApplyBaseFlipOverrides( + const NVDevEvoRec *pDevEvo, + const NvU32 sd, + const NvU32 head, + NVFlipChannelEvoHwState *pNew, + NvBool allowVrr) +{ + const NVDispEvoRec *pDispEvo = pDevEvo->gpus[sd].pDispEvo; + const NVFlipChannelEvoHwState *pOld = + &pDevEvo->gpus[sd].headState[head].layer[NVKMS_MAIN_LAYER]; + + // Apply VRR swap interval overrides. + // + // Note that this applies the overrides whenever the client requests VRR and + // VRR is enabled, regardless of whether actually activating it later + // succeeds. + if (allowVrr) { + if (!nvHeadIsActive(pDispEvo, head)) { + // + // XXX If VRR is allowed then modeset should have happened before + // base channel flip, currently we don't know how to do modeset + // and program base channel for VRR at same time. This should be + // revisited as part of bug 1731279. + // + return FALSE; + } + nvApplyVrrBaseFlipOverrides(pDevEvo->gpus[sd].pDispEvo, head, + pOld, pNew); + } + + if (!nvHeadIsActive(pDispEvo, head)) { + // + // This is possible when modeset and base flip happening at same time, + // tearing parameter does not make sense in that case, + // it should is disabled. + // + pNew->tearing = FALSE; + } else { + // Force non-tearing mode if EVO requires it. + if (FlipRequiresNonTearingMode(pDevEvo, head, pOld, pNew)) { + pNew->tearing = FALSE; + } + } + + return TRUE; +} + +static NvBool ValidateScalingUsageBounds( + const struct NvKmsScalingUsageBounds *pS, + const struct NvKmsScalingUsageBounds *pMaxS) +{ + return (pS->maxVDownscaleFactor <= pMaxS->maxVDownscaleFactor) && + (pS->maxHDownscaleFactor <= pMaxS->maxHDownscaleFactor) && + (pS->vTaps <= pMaxS->vTaps) && + (!pS->vUpscalingAllowed || pMaxS->vUpscalingAllowed); +} + +/*! + * Validate the requested usage bounds against the specified maximums. + */ +static NvBool ValidateUsageBounds( + const NVDevEvoRec *pDevEvo, + const NvU32 head, + const struct NvKmsUsageBounds *pUsage, + const struct NvKmsUsageBounds *pGuaranteedUsage) +{ + NvU32 i; + + for (i = 0; i < pDevEvo->head[head].numLayers; i++) { + const NvU64 supportedSurfaceFormatsUnion = + pUsage->layer[i].supportedSurfaceMemoryFormats | + pGuaranteedUsage->layer[i].supportedSurfaceMemoryFormats; + + if ((pUsage->layer[i].usable && !pGuaranteedUsage->layer[i].usable) || + (supportedSurfaceFormatsUnion != + pGuaranteedUsage->layer[i].supportedSurfaceMemoryFormats) || + !ValidateScalingUsageBounds(&pUsage->layer[i].scaling, + &pGuaranteedUsage->layer[i].scaling)) { + return FALSE; + } + } + + return TRUE; +} + +/*! + * Assign pFlipState->usage. + */ +static NvBool AssignUsageBounds( + const NVDevEvoRec *pDevEvo, + const NvU32 head, + NVFlipEvoHwState *pFlipState) +{ + struct NvKmsUsageBounds *pUsage = &pFlipState->usage; + int i; + + for (i = 0; i < pDevEvo->head[head].numLayers; i++) { + const NVFlipChannelEvoHwState *pLayerFlipState = &pFlipState->layer[i]; + + nvInitScalingUsageBounds(pDevEvo, &pUsage->layer[i].scaling); + + if (pLayerFlipState->pSurfaceEvo[NVKMS_LEFT]) { + pUsage->layer[i].usable = TRUE; + pUsage->layer[i].supportedSurfaceMemoryFormats = + nvEvoGetFormatsWithEqualOrLowerUsageBound( + pLayerFlipState->pSurfaceEvo[NVKMS_LEFT]->format, + pDevEvo->caps.layerCaps[i].supportedSurfaceMemoryFormats); + + if (pDevEvo->hal->GetWindowScalingCaps) { + const NVEvoScalerCaps *pScalerCaps = + pDevEvo->hal->GetWindowScalingCaps(pDevEvo); + + if (!nvComputeScalingUsageBounds(pScalerCaps, + pLayerFlipState->sizeIn.width, + pLayerFlipState->sizeIn.height, + pLayerFlipState->sizeOut.width, + pLayerFlipState->sizeOut.height, + pLayerFlipState->hTaps, + pLayerFlipState->vTaps, + &pUsage->layer[i].scaling)) { + return FALSE; + } + } + + if (pLayerFlipState->maxDownscaleFactors.specified) { + struct NvKmsScalingUsageBounds *pTargetScaling = + &pFlipState->usage.layer[i].scaling; + + if ((pLayerFlipState->maxDownscaleFactors.vertical < + pTargetScaling->maxVDownscaleFactor) || + (pLayerFlipState->maxDownscaleFactors.horizontal < + pTargetScaling->maxHDownscaleFactor)) { + return FALSE; + } + + pTargetScaling->maxVDownscaleFactor = + pLayerFlipState->maxDownscaleFactors.vertical; + pTargetScaling->maxHDownscaleFactor = + pLayerFlipState->maxDownscaleFactors.horizontal; + } + + } else { + pUsage->layer[i].usable = FALSE; + pUsage->layer[i].supportedSurfaceMemoryFormats = 0; + } + } + + return TRUE; +} + +void +nvOverrideScalingUsageBounds(const NVDevEvoRec *pDevEvo, + NvU32 head, + NVFlipEvoHwState *pFlipState, + const struct NvKmsUsageBounds *pPossibleUsage) +{ + NvU32 i; + + for (i = 0; i < pDevEvo->head[head].numLayers; i++) { + const NVFlipChannelEvoHwState *pLayerFlipState = &pFlipState->layer[i]; + const struct NvKmsScalingUsageBounds *pPossibleScaling = + &pPossibleUsage->layer[i].scaling; + struct NvKmsScalingUsageBounds *pTargetScaling = + &pFlipState->usage.layer[i].scaling; + + if (!pFlipState->usage.layer[i].usable) { + continue; + } + + if (!pLayerFlipState->maxDownscaleFactors.specified) { + const NvU16 possibleV = pPossibleScaling->maxVDownscaleFactor; + const NvU16 possibleH = pPossibleScaling->maxHDownscaleFactor; + NvU16 targetV = pTargetScaling->maxVDownscaleFactor; + NvU16 targetH = pTargetScaling->maxHDownscaleFactor; + + /* + * Calculate max H/V downscale factor by quantizing the range. + * + * E.g., + * max H/V downscale factor supported by HW is 4x for 5-tap and 2x + * for 2-tap mode. If 5-tap mode is required, the target usage bound + * that nvkms will attempt to program will either allow up to 2x + * downscaling, or up to 4x downscaling. If 2-tap mode is required, + * the target usage bound that NVKMS will attempt to program will + * allow up to 2x downscaling. Example: to downscale from 4096x2160 + * -> 2731x864 in 5-tap mode, NVKMS would specify up to 2x for the + * H downscale bound (required is 1.5x), and up to 4x for the V + * downscale bound (required is 2.5x). + */ + if (targetV > NV_EVO_SCALE_FACTOR_1X) { + const NvU16 possibleMid = + NV_EVO_SCALE_FACTOR_1X + ((possibleV - NV_EVO_SCALE_FACTOR_1X) / 2); + + if (targetV <= possibleMid) { + pTargetScaling->maxVDownscaleFactor = possibleMid; + } else { + pTargetScaling->maxVDownscaleFactor = possibleV; + } + } + + if (targetH > NV_EVO_SCALE_FACTOR_1X) { + const NvU16 possibleMid = + NV_EVO_SCALE_FACTOR_1X + ((possibleH - NV_EVO_SCALE_FACTOR_1X) / 2); + + if (targetH <= possibleMid) { + pTargetScaling->maxHDownscaleFactor = possibleMid; + } else { + pTargetScaling->maxHDownscaleFactor = possibleH; + } + } + } + + pTargetScaling->vTaps = pPossibleScaling->vTaps; + pTargetScaling->vUpscalingAllowed = pPossibleScaling->vUpscalingAllowed; + } +} + +static NvBool FlipTimeStampValidForChannel( + const NVEvoChannel *pChannel, + NvU64 timeStamp) +{ + if (pChannel->caps.validTimeStampBits < 64) { + const NvU64 validTimeStampMask = + NVBIT64(pChannel->caps.validTimeStampBits) - 1; + if ((timeStamp & ~validTimeStampMask) != 0) { + return FALSE; + } + } + return TRUE; +} + +static NvBool UpdateFlipEvoHwStateHDRStaticMetadata( + const NVDevEvoRec *pDevEvo, + const struct NvKmsFlipCommonParams *pParams, + NVFlipEvoHwState *pFlipState, + NVFlipChannelEvoHwState *pHwState, + const NvU32 head, + const NvU32 layer) +{ + if (pParams->layer[layer].hdr.specified) { + if (pParams->layer[layer].hdr.enabled) { + // Don't allow enabling HDR on a layer that doesn't support it. + if (!pDevEvo->caps.layerCaps[layer].supportsHDR) { + return FALSE; + } + + pHwState->hdrStaticMetadata.val = + pParams->layer[layer].hdr.staticMetadata; + } + pHwState->hdrStaticMetadata.enabled = pParams->layer[layer].hdr.enabled; + + // Only mark dirty if layer supports HDR, otherwise this is a no-op. + if (pDevEvo->caps.layerCaps[layer].supportsHDR) { + pFlipState->dirty.hdrStaticMetadata = TRUE; + } + } + + return TRUE; +} + +static NvBool UpdateLayerFlipEvoHwStateCommon( + const struct NvKmsPerOpenDev *pOpenDev, + const NVDevEvoRec *pDevEvo, + const NvU32 sd, + const NvU32 head, + const NvU32 layer, + const struct NvKmsFlipCommonParams *pParams, + NVFlipEvoHwState *pFlipState) +{ + const NVEvoChannel *pChannel = pDevEvo->head[head].layer[layer]; + NVFlipChannelEvoHwState *pHwState = &pFlipState->layer[layer]; + const NVEvoApiHandlesRec *pOpenDevSurfaceHandles = + nvGetSurfaceHandlesFromOpenDevConst(pOpenDev); + NvBool ret; + + if (pParams->layer[layer].surface.specified) { + ret = nvAssignSurfaceArray(pDevEvo, + pOpenDevSurfaceHandles, + pParams->layer[layer].surface.handle, + FALSE /* isUsedByCursorChannel */, + TRUE /* isUsedByLayerChannel */, + pHwState->pSurfaceEvo); + if (!ret) { + return FALSE; + } + + /* + * Verify the (rotation, reflectionX, reflectionY) is a + * combination currently supported. + */ + if ((NVBIT(NvKmsRRParamsToCapBit(&pParams->layer[layer].surface.rrParams)) & + pDevEvo->caps.validLayerRRTransforms) == 0) { + return FALSE; + } + pHwState->rrParams = pParams->layer[layer].surface.rrParams; + + } + + /* Verify the timestamp is in the valid range for this channel. */ + if (!FlipTimeStampValidForChannel(pChannel, + pParams->layer[layer].timeStamp)) { + return FALSE; + } + pHwState->timeStamp = pParams->layer[layer].timeStamp; + + if (pParams->layer[layer].syncObjects.specified) { + if (!pDevEvo->supportsSyncpts && + pParams->layer[layer].syncObjects.val.useSyncpt) { + return FALSE; + } + + nvkms_memset(&pFlipState->layer[layer].syncObject, + 0, + sizeof(pFlipState->layer[layer].syncObject)); + + if (pParams->layer[layer].syncObjects.val.useSyncpt) { + ret = AssignPreSyncptEvoHwState(pDevEvo, + &pParams->layer[layer].syncObjects.val, + &pHwState->syncObject); + if (!ret) { + return FALSE; + } + pFlipState->dirty.layerSyncObjects[layer] = TRUE; + + ret = AssignPostSyncptEvoHwState(pDevEvo, + pDevEvo->head[head].layer[layer], + &pParams->layer[layer].syncObjects.val, + &pHwState->syncObject); + if (!ret) { + return FALSE; + } + } else { + if (pParams->layer[layer].syncObjects.val.u.semaphores.acquire.surface.surfaceHandle != 0 || + pParams->layer[layer].syncObjects.val.u.semaphores.release.surface.surfaceHandle != 0) { + if (pParams->layer[layer].skipPendingFlips) { + return FALSE; + } + } + + ret = nvAssignSemaphoreEvoHwState(pDevEvo, + pOpenDevSurfaceHandles, + layer, + sd, + &pParams->layer[layer].syncObjects.val, + &pHwState->syncObject); + if (!ret) { + return FALSE; + } + } + } + + if (pHwState->pSurfaceEvo[NVKMS_LEFT]) { + pHwState->minPresentInterval = + pParams->layer[layer].minPresentInterval; + } else { + /* The hardware requires that MPI be 0 when disabled. */ + pHwState->minPresentInterval = 0; + } + + if (pParams->layer[layer].sizeIn.specified) { + pHwState->sizeIn = pParams->layer[layer].sizeIn.val; + } + + if (pParams->layer[layer].sizeOut.specified) { + pHwState->sizeOut = pParams->layer[layer].sizeOut.val; + } + + /* + * If supportsWindowMode = TRUE, the sizeIn/sizeOut dimensions can be + * any arbitrary (valid) values. + * + * If supportsWindowMode = FALSE (legacy EVO main layer), the sizeIn + * /sizeOut dimensions must match the size of the surface for that layer. + * + * Note that if sizeIn/Out dimensions are invalid i.e. with a width or + * height of zero, this will be rejected by a call to + * ValidateFlipChannelEvoHwState() later in the code path. + * + * Note that if scaling is unsupported, i.e. that sizeIn cannot differ + * from sizeOut, then any unsupported configurations will be caught by the + * ComputeWindowScalingTaps() call later on in this function. + */ + if (!pDevEvo->caps.layerCaps[layer].supportsWindowMode && + (pHwState->pSurfaceEvo[NVKMS_LEFT] != NULL)) { + const NVSurfaceEvoRec *pSurfaceEvo = + pHwState->pSurfaceEvo[NVKMS_LEFT]; + + if ((pHwState->sizeIn.width != pSurfaceEvo->widthInPixels) || + (pHwState->sizeIn.height != pSurfaceEvo->heightInPixels)) { + return FALSE; + } + + if ((pHwState->sizeOut.width != pSurfaceEvo->widthInPixels) || + (pHwState->sizeOut.height != pSurfaceEvo->heightInPixels)) { + return FALSE; + } + } + + /* + * Allow the client to specify non-origin outputPosition only if the + * layer supports window mode. + * + * If window mode is unsupported but the client specifies non-origin + * outputPosition, return FALSE. + */ + if (pDevEvo->caps.layerCaps[layer].supportsWindowMode) { + if (pParams->layer[layer].outputPosition.specified) { + const NvS16 x = pParams->layer[layer].outputPosition.val.x; + const NvS16 y = pParams->layer[layer].outputPosition.val.y; + if ((pHwState->outputPosition.x != x) || + (pHwState->outputPosition.y != y)) { + pHwState->outputPosition.x = x; + pHwState->outputPosition.y = y; + pFlipState->dirty.layerPosition[layer] = TRUE; + } + } + } else if (pParams->layer[layer].outputPosition.specified && + ((pParams->layer[layer].outputPosition.val.x != 0) || + (pParams->layer[layer].outputPosition.val.y != 0))) { + return FALSE; + } + + if (pParams->layer[layer].compositionParams.specified) { + pHwState->composition = + pParams->layer[layer].compositionParams.val; + } + + if (!UpdateFlipEvoHwStateHDRStaticMetadata( + pDevEvo, pParams, pFlipState, + pHwState, head, layer)) { + return FALSE; + } + + if (pParams->layer[layer].colorspace.specified) { + pHwState->colorspace = + pParams->layer[layer].colorspace.val; + } + + if (pHwState->composition.depth == 0) { + pHwState->composition.depth = + NVKMS_MAX_LAYERS_PER_HEAD - layer; + } + + /* XXX Move ValidatePerLayerCompParams() call to nvValidateFlipEvoHwState() */ + if (!nvValidatePerLayerCompParams( + &pHwState->composition, + &pDevEvo->caps.layerCaps[layer].composition, + pHwState->pSurfaceEvo[NVKMS_LEFT])) { + return FALSE; + } + + if (!pDevEvo->hal->ComputeWindowScalingTaps(pDevEvo, + pChannel, + pHwState)) { + return FALSE; + } + + if (pParams->layer[layer].completionNotifier.specified) { + ret = nvAssignCompletionNotifierEvoHwState( + pDevEvo, + pOpenDevSurfaceHandles, + &pParams->layer[layer].completionNotifier.val, + layer, + &pFlipState->layer[layer].completionNotifier); + if (!ret) { + return FALSE; + } + } + + if (pParams->layer[layer].maxDownscaleFactors.specified) { + pFlipState->layer[layer].maxDownscaleFactors.vertical = + pParams->layer[layer].maxDownscaleFactors.vertical; + pFlipState->layer[layer].maxDownscaleFactors.horizontal = + pParams->layer[layer].maxDownscaleFactors.horizontal; + pFlipState->layer[layer].maxDownscaleFactors.specified = TRUE; + } else { + pFlipState->layer[layer].maxDownscaleFactors.vertical = 0; + pFlipState->layer[layer].maxDownscaleFactors.horizontal = 0; + pFlipState->layer[layer].maxDownscaleFactors.specified = FALSE; + } + + pFlipState->dirty.layer[layer] = TRUE; + + return TRUE; +} + +static NvBool UpdateMainLayerFlipEvoHwState( + const struct NvKmsPerOpenDev *pOpenDev, + const NVDevEvoRec *pDevEvo, + const NvU32 sd, + const NvU32 head, + const struct NvKmsFlipCommonParams *pParams, + NVFlipEvoHwState *pFlipState, + NvBool allowVrr) +{ + const NVEvoChannel *pChannel = + pDevEvo->head[head].layer[NVKMS_MAIN_LAYER]; + NVFlipChannelEvoHwState *pHwState = &pFlipState->layer[NVKMS_MAIN_LAYER]; + + if (!nvIsLayerDirty(pParams, NVKMS_MAIN_LAYER)) { + return TRUE; + } + + if (!UpdateLayerFlipEvoHwStateCommon(pOpenDev, pDevEvo, sd, head, + NVKMS_MAIN_LAYER, + pParams, pFlipState)) { + return FALSE; + } + + if (pParams->layer[NVKMS_MAIN_LAYER].csc.specified) { + if (pParams->layer[NVKMS_MAIN_LAYER].csc.useMain) { + return FALSE; + } else { + pHwState->cscMatrix = pParams->layer[NVKMS_MAIN_LAYER].csc.matrix; + } + } + + if (pParams->layer[NVKMS_MAIN_LAYER].surface.specified) { + if (pParams->layer[NVKMS_MAIN_LAYER].perEyeStereoFlip && + !pChannel->caps.perEyeStereoFlips) { + return FALSE; + } + + pHwState->perEyeStereoFlip = + pParams->layer[NVKMS_MAIN_LAYER].perEyeStereoFlip; + } + + if (pParams->layer[NVKMS_MAIN_LAYER].tearing && !pChannel->caps.tearingFlips) { + return FALSE; + } + + // EVO will throw an invalid argument exception if + // minPresentInterval is too large, or if tearing is enabled and + // it's not zero. + if (pParams->layer[NVKMS_MAIN_LAYER].minPresentInterval > NV_MAX_SWAP_INTERVAL || + (pParams->layer[NVKMS_MAIN_LAYER].tearing && + pParams->layer[NVKMS_MAIN_LAYER].minPresentInterval != 0)) { + return FALSE; + } + + pHwState->tearing = pParams->layer[NVKMS_MAIN_LAYER].tearing; + + if (!ApplyBaseFlipOverrides(pDevEvo, + sd, head, &pFlipState->layer[NVKMS_MAIN_LAYER], + allowVrr)) { + return FALSE; + } + + pFlipState->skipLayerPendingFlips[NVKMS_MAIN_LAYER] = + pParams->layer[NVKMS_MAIN_LAYER].skipPendingFlips; + + return TRUE; +} + +static NvBool UpdateCursorLayerFlipEvoHwState( + const struct NvKmsPerOpenDev *pOpenDev, + const NVDevEvoRec *pDevEvo, + const struct NvKmsFlipCommonParams *pParams, + NVFlipEvoHwState *pFlipState) +{ + if (pParams->cursor.imageSpecified) { + if (!nvAssignCursorSurface(pOpenDev, pDevEvo, &pParams->cursor.image, + &pFlipState->cursor.pSurfaceEvo)) { + return FALSE; + } + + if (pFlipState->cursor.pSurfaceEvo != NULL) { + pFlipState->cursor.cursorCompParams = + pParams->cursor.image.cursorCompParams; + } + + pFlipState->dirty.cursorSurface = TRUE; + } + + if (pParams->cursor.positionSpecified) { + pFlipState->cursor.x = pParams->cursor.position.x; + pFlipState->cursor.y = pParams->cursor.position.y; + + pFlipState->dirty.cursorPosition = TRUE; + } + + return TRUE; +} + +static NvBool UpdateOverlayLayerFlipEvoHwState( + const struct NvKmsPerOpenDev *pOpenDev, + const NVDevEvoRec *pDevEvo, + const NvU32 sd, + const NvU32 head, + const NvU32 layer, + const struct NvKmsFlipCommonParams *pParams, + NVFlipEvoHwState *pFlipState) +{ + NVFlipChannelEvoHwState *pHwState = &pFlipState->layer[layer]; + + nvAssert(layer != NVKMS_MAIN_LAYER); + + if (!nvIsLayerDirty(pParams, layer)) { + return TRUE; + } + + if (pParams->layer[layer].skipPendingFlips || + pParams->layer[layer].perEyeStereoFlip) { + return FALSE; + } + + if (!UpdateLayerFlipEvoHwStateCommon(pOpenDev, pDevEvo, sd, head, layer, + pParams, pFlipState)) { + return FALSE; + } + + if (pParams->layer[layer].csc.specified) { + if (pParams->layer[layer].csc.useMain) { + if (pFlipState->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[NVKMS_LEFT]) { + pHwState->cscMatrix = + pFlipState->layer[NVKMS_MAIN_LAYER].cscMatrix; + } + } else { + pHwState->cscMatrix = pParams->layer[layer].csc.matrix; + } + } + + return TRUE; +} + +/*! + * Update the NVFlipEvoHwState, using NvKmsFlipCommonParams. + * + * Propagate the requested configuration from NvKmsFlipCommonParams to + * NVFlipEvoHwState, performing steps such as translating from + * NvKmsSurfaceHandle to NVSurfaceEvoRecs. Validate the NvKmsFlipCommonParams + * parameters, but defer more general validation of the resulting + * NVFlipEvoHwState until nvValidateFlipEvoHwState(), which callers must call + * separately. + * + * The NVFlipEvoHwState should first be initialized by calling + * nvInitFlipEvoHwState(). + * + * No NVKMS hardware or software state should be altered here, because + * this function is used before we have decided to commit the proposed + * NVFlipEvoHwState to hardware. + * + * \param[in] pOpenDev The pOpenDev of the client doing the flip. + * \param[in] pDevEvo The device on which the surface image will be set. + * \param[in] sd The subdevice for the flip, as specified by the + * client. + * \param[in] head The head for the flip, as specified by the client. + * \param[in] pParams The requested flip, NvKmsFlipCommonParams. + * \param[in] pTimings The mode timings for the flip. + * \param[in,out] pFlipState The resulting NVFlipEvoHwState. + * \param[in] allowVrr Whether VRR flipping should be allowed. + * \param[in] pPossibleUsage Possible usage. + * + * \return If pFlipState could be updated, return TRUE. + * Otherwise, return FALSE. + */ +NvBool nvUpdateFlipEvoHwState( + const struct NvKmsPerOpenDev *pOpenDev, + const NVDevEvoRec *pDevEvo, + const NvU32 sd, + const NvU32 head, + const struct NvKmsFlipCommonParams *pParams, + const NVHwModeTimingsEvo *pTimings, + NVFlipEvoHwState *pFlipState, + NvBool allowVrr) +{ + NvU32 layer; + + if (pParams->viewPortIn.specified) { + pFlipState->dirty.viewPortPointIn = TRUE; + pFlipState->viewPortPointIn = pParams->viewPortIn.point; + } + + if (!UpdateCursorLayerFlipEvoHwState(pOpenDev, pDevEvo, pParams, + pFlipState)) { + return FALSE; + } + + if (pParams->tf.specified) { + pFlipState->dirty.tf = TRUE; + pFlipState->tf = pParams->tf.val; + } + + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + if (layer == NVKMS_MAIN_LAYER) { + if (!UpdateMainLayerFlipEvoHwState(pOpenDev, pDevEvo, sd, head, + pParams, pFlipState, allowVrr)) { + return FALSE; + } + continue; + } + + if (!UpdateOverlayLayerFlipEvoHwState(pOpenDev, pDevEvo, sd, head, + layer, pParams, pFlipState)) { + return FALSE; + } + } + + if (!AssignUsageBounds(pDevEvo, head, pFlipState)) { + return FALSE; + } + + /* + * If there is active cursor/cropped-window(overlay) without full screen + * window(base/core) then NVKMS is supposed to disable MidFrame/DWCF + * watermark. + */ + + pFlipState->disableMidFrameAndDWCFWatermark = FALSE; + + if (NV5070_CTRL_SYSTEM_GET_CAP( + pDevEvo->capsBits, + NV5070_CTRL_SYSTEM_CAPS_BUG_2052012_GLITCHY_MCLK_SWITCH) && + !pFlipState->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[NVKMS_LEFT]) { + + if (pFlipState->cursor.pSurfaceEvo != NULL) { + pFlipState->disableMidFrameAndDWCFWatermark = TRUE; + } else { + NvU32 layer; + + /* + * XXX TODO: Check the output size of the overlay in order + * to determine if it will be fullscreen or not. + */ + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + if (layer != NVKMS_MAIN_LAYER && + pFlipState->layer[layer].pSurfaceEvo[NVKMS_LEFT] != NULL) { + pFlipState->disableMidFrameAndDWCFWatermark = TRUE; + break; + } + } + } + } + + return TRUE; +} + +/* + * Checks that if the surface is NULL (i.e. no image will be shown), various + * other elements must be NULL as well. If the surface is not NULL, verifies + * that the sizeIn/Out have nonzero values. + */ +inline static NvBool ValidateFlipChannelEvoHwState( + const NVFlipChannelEvoHwState *pState) +{ + if (pState->pSurfaceEvo[NVKMS_LEFT] != NULL) { + /* Verify sizes are valid. */ + if ((pState->sizeIn.width == 0) || (pState->sizeIn.height == 0) || + (pState->sizeOut.width == 0) || (pState->sizeOut.height == 0)) { + return FALSE; + } + + return TRUE; + } + + if (pState->completionNotifier.surface.pSurfaceEvo != NULL) { + return FALSE; + } + + if (!pState->syncObject.usingSyncpt) { + if (pState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo != NULL) { + return FALSE; + } + + if (pState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo != NULL) { + return FALSE; + } + } + + return TRUE; +} + +static NvBool ValidateSurfaceSize( + const NVDevEvoRec *pDevEvo, + const NVSurfaceEvoRec *pSurfaceEvo, + const struct NvKmsRect *sourceFetchRect) +{ + NvU8 planeIndex; + + if ((pSurfaceEvo->widthInPixels > pDevEvo->caps.maxWidthInPixels) || + (pSurfaceEvo->heightInPixels > pDevEvo->caps.maxHeight)) { + return FALSE; + } + + FOR_ALL_VALID_PLANES(planeIndex, pSurfaceEvo) { + + NvU64 planePitch = pSurfaceEvo->planes[planeIndex].pitch; + + /* + * Convert planePitch to units of bytes if it's currently specified in + * units of blocks. Each block is 64-bytes wide. + */ + if (pSurfaceEvo->layout == NvKmsSurfaceMemoryLayoutBlockLinear) { + planePitch <<= NVKMS_BLOCK_LINEAR_LOG_GOB_WIDTH; + } + + if (planePitch > pDevEvo->caps.maxWidthInBytes) { + return FALSE; + } + } + + if (!pDevEvo->hal->ValidateWindowFormat(pSurfaceEvo->format, + sourceFetchRect, + NULL)) { + return FALSE; + } + + return TRUE; +} + +static NvBool +ValidateMainFlipChannelEvoHwState(const NVDevEvoRec *pDevEvo, + const NVFlipChannelEvoHwState *pHwState, + const NVHwModeTimingsEvo *pTimings, + struct NvKmsPoint viewPortPointIn) +{ + NvU32 eye; + const NVSurfaceEvoRec *pFirstSurfaceEvo = NULL; + + /* + * This struct represents the source fetch rectangle for a given surface, + * and will be populated later as such. This function doesn't explicitly set + * sourceFetchRect.{x,y} because NVKMS currently doesn't support programming + * source fetch offsets, so the init value of 0 should be fine for both of + * these fields. + */ + struct NvKmsRect sourceFetchRect = {0}; + + if (!ValidateFlipChannelEvoHwState(pHwState)) { + return FALSE; + } + + for (eye = 0; eye < NVKMS_MAX_EYES; eye++) { + const NVSurfaceEvoRec *pSurfaceEvo = pHwState->pSurfaceEvo[eye]; + + if (pSurfaceEvo == NULL) { + continue; + } + + if (pFirstSurfaceEvo == NULL) { + pFirstSurfaceEvo = pSurfaceEvo; + } else if (pSurfaceEvo->widthInPixels != + pFirstSurfaceEvo->widthInPixels || + pSurfaceEvo->heightInPixels != + pFirstSurfaceEvo->heightInPixels) { + return FALSE; + } + + sourceFetchRect.width = pHwState->sizeIn.width; + sourceFetchRect.height = pHwState->sizeIn.height; + + if (!ValidateSurfaceSize(pDevEvo, pSurfaceEvo, &sourceFetchRect)) { + return FALSE; + } + + /* The use of A_plus_B_greater_than_C_U16 is only valid if these + * fit in a U16 */ + nvAssert(pSurfaceEvo->widthInPixels <= NV_U16_MAX); + nvAssert(pSurfaceEvo->heightInPixels <= NV_U16_MAX); + /* And the checks above in ValidateSurfaceSize should have + * guaranteed that. */ + nvAssert(pDevEvo->caps.maxWidthInPixels <= NV_U16_MAX); + nvAssert(pDevEvo->caps.maxHeight <= NV_U16_MAX); + + /* + * Validate that the requested viewport parameters fit within the + * specified surface, unless the main layer is allowed to be smaller + * than the viewport. + */ + if (!pDevEvo->caps.layerCaps[NVKMS_MAIN_LAYER].supportsWindowMode) { + if (A_plus_B_greater_than_C_U16(viewPortPointIn.x, + pTimings->viewPort.in.width, + pSurfaceEvo->widthInPixels)) { + return FALSE; + } + + if (A_plus_B_greater_than_C_U16(viewPortPointIn.y, + pTimings->viewPort.in.height, + pSurfaceEvo->heightInPixels)) { + return FALSE; + } + } + } + + return TRUE; +} + +static NvBool +ValidateOverlayFlipChannelEvoHwState(const NVDevEvoRec *pDevEvo, + const NVFlipChannelEvoHwState *pHwState) +{ + const NVSurfaceEvoRec *pSurfaceEvo = pHwState->pSurfaceEvo[NVKMS_LEFT]; + + /* + * This struct represents the source fetch rectangle for a given surface, + * and will be populated later as such. This function doesn't explicitly set + * sourceFetchRect.{x,y} because NVKMS currently doesn't support programming + * source fetch offsets, so the init value of 0 should be fine for both of + * these fields. + */ + struct NvKmsRect sourceFetchRect = {0}; + + if (!ValidateFlipChannelEvoHwState(pHwState)) { + return FALSE; + } + + if (pSurfaceEvo == NULL) { + return TRUE; + } + + sourceFetchRect.width = pHwState->sizeIn.width; + sourceFetchRect.height = pHwState->sizeIn.height; + + if (!ValidateSurfaceSize(pDevEvo, pSurfaceEvo, &sourceFetchRect)) { + return FALSE; + } + + /* Validate input size against surface size. */ + if (pHwState->sizeIn.width > pSurfaceEvo->widthInPixels || + pHwState->sizeIn.height > pSurfaceEvo->heightInPixels) { + return FALSE; + } + + return TRUE; +} + +static NvBool +ValidateHDR(const NVDevEvoRec *pDevEvo, + const NvU32 head, + const NVFlipEvoHwState *pFlipState) +{ + NvU32 staticMetadataCount = 0; + NvU32 layerSupportedCount = 0; + + NvU32 layer; + + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + if (pDevEvo->caps.layerCaps[layer].supportsHDR) { + layerSupportedCount++; + } + + if (pFlipState->layer[layer].hdrStaticMetadata.enabled) { + staticMetadataCount++; + + /* + * If HDR static metadata is enabled, we may need TMO. CSC11 will be + * used by NVKMS to convert from linear FP16 LMS to linear FP16 RGB. + * As such, the user-supplied precomp CSC can't be programmed into + * CSC11 in this case. + */ + if (!nvIsCscMatrixIdentity(&pFlipState->layer[layer].cscMatrix)) { + return FALSE; + } + + // Already checked in UpdateFlipEvoHwStateHDRStaticMetadata() + nvAssert(pDevEvo->caps.layerCaps[layer].supportsHDR); + } + } + + // If enabling HDR... + // XXX HDR TODO: Handle other transfer functions + if (pFlipState->tf == NVKMS_OUTPUT_TF_PQ) { + // At least one layer must have static metadata. + if (staticMetadataCount == 0) { + return FALSE; + } + + // At least one layer must support HDR, implied above. + nvAssert(layerSupportedCount != 0); + } + + // Only one layer can specify HDR static metadata. + // XXX HDR TODO: Support multiple layers with HDR static metadata + if (staticMetadataCount > 1) { + return FALSE; + } + + return TRUE; +} + +static NvBool +ValidateColorspace(const NVDevEvoRec *pDevEvo, + const NvU32 head, + const NVFlipEvoHwState *pFlipState) +{ + NvU32 layer; + + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + if ((pFlipState->layer[layer].colorspace != + NVKMS_INPUT_COLORSPACE_NONE)) { + + NVSurfaceEvoPtr pSurfaceEvo = + pFlipState->layer[layer].pSurfaceEvo[NVKMS_LEFT]; + const NvKmsSurfaceMemoryFormatInfo *pFormatInfo = + (pSurfaceEvo != NULL) ? + nvKmsGetSurfaceMemoryFormatInfo(pSurfaceEvo->format) : NULL; + + // XXX HDR TODO: Support YUV. + if ((pFormatInfo == NULL) || pFormatInfo->isYUV) { + return FALSE; + } + + // FP16 is only for use with scRGB. + if ((pFlipState->layer[layer].colorspace != + NVKMS_INPUT_COLORSPACE_SCRGB_LINEAR) && + ((pSurfaceEvo->format == + NvKmsSurfaceMemoryFormatRF16GF16BF16AF16) || + (pSurfaceEvo->format == + NvKmsSurfaceMemoryFormatRF16GF16BF16XF16))) { + return FALSE; + } + + // scRGB is only compatible with FP16. + if ((pFlipState->layer[layer].colorspace == + NVKMS_INPUT_COLORSPACE_SCRGB_LINEAR) && + !((pSurfaceEvo->format == + NvKmsSurfaceMemoryFormatRF16GF16BF16AF16) || + (pSurfaceEvo->format == + NvKmsSurfaceMemoryFormatRF16GF16BF16XF16))) { + return FALSE; + } + } + } + + return TRUE; +} + +static NvU32 ValidateCompositionDepth(const NVFlipEvoHwState *pFlipState, + const NvU32 layer) +{ + NvU32 tmpLayer; + + if (pFlipState->layer[layer].pSurfaceEvo[NVKMS_LEFT] == NULL) { + return TRUE; + } + + /* Depth should be different for each of the layers owned by the head */ + for (tmpLayer = 0; tmpLayer < ARRAY_LEN(pFlipState->layer); tmpLayer++) { + if (pFlipState->layer[tmpLayer].pSurfaceEvo[NVKMS_LEFT] == NULL) { + continue; + } + + if ((tmpLayer != layer) && + (pFlipState->layer[tmpLayer].composition.depth == + pFlipState->layer[layer].composition.depth)) { + return FALSE; + } + } + + /* Depth of the main layer should be the greatest one */ + if (pFlipState->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[NVKMS_LEFT] != NULL) { + if (pFlipState->layer[NVKMS_MAIN_LAYER].composition.depth < + pFlipState->layer[layer].composition.depth) { + return FALSE; + } + } + + return TRUE; +} + +/*! + * Perform validation of the the given NVFlipEvoHwState. + */ +NvBool nvValidateFlipEvoHwState( + const NVDevEvoRec *pDevEvo, + const NvU32 head, + const NVHwModeTimingsEvo *pTimings, + const NVFlipEvoHwState *pFlipState) +{ + NvU32 layer; + + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + if (!ValidateCompositionDepth(pFlipState, layer)) { + return FALSE; + } + + if (layer == NVKMS_MAIN_LAYER) { + if (!ValidateMainFlipChannelEvoHwState(pDevEvo, + &pFlipState->layer[layer], + pTimings, + pFlipState->viewPortPointIn)) { + return FALSE; + } + } else { + const NVFlipChannelEvoHwState *pMainLayerState = + &pFlipState->layer[NVKMS_MAIN_LAYER]; + + /* + * No overlay layer should be enabled if the main + * layer is disabled. + */ + if ((pMainLayerState->pSurfaceEvo[NVKMS_LEFT] == NULL) && + (pFlipState->layer[layer].pSurfaceEvo[NVKMS_LEFT] != NULL)) { + return FALSE; + } + + if (!pFlipState->dirty.layer[layer]) { + continue; + } + + if (!ValidateOverlayFlipChannelEvoHwState(pDevEvo, + &pFlipState->layer[layer])) { + return FALSE; + } + } + } + + if (!ValidateHDR(pDevEvo, head, pFlipState)) { + return FALSE; + } + + if (!ValidateColorspace(pDevEvo, head, pFlipState)) { + return FALSE; + } + + /* XXX NVKMS TODO: validate cursor x,y against current viewport in? */ + + return ValidateUsageBounds(pDevEvo, + head, + &pFlipState->usage, + &pTimings->viewPort.possibleUsage); +} + +/* + * Record in the updateState that the given channel needs interlocked + * window immediate updates. + */ +static void UpdateWinImmInterlockState(NVDevEvoPtr pDevEvo, + NVEvoUpdateState *updateState, + const NVEvoChannel *pChannel) +{ + const NvU32 subDevMask = nvPeekEvoSubDevMask(pDevEvo); + NvU32 sd; + + for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { + if (subDevMask & (1 << sd)) { + updateState->subdev[sd].winImmInterlockMask |= + pChannel->channelMask; + } + } +} + +/*! + * Record in the updateState that the given channel's method are eligible for + * flip locking. + */ +static void UpdateUpdateFlipLockState(NVDevEvoPtr pDevEvo, + NVEvoUpdateState *updateState, + const NVEvoChannel *pChannel) +{ + const NvU32 subDevMask = nvPeekEvoSubDevMask(pDevEvo); + NvU32 sd; + + for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { + if (subDevMask & (1 << sd)) { + updateState->subdev[sd].flipLockQualifyingMask |= + pChannel->channelMask; + } + } +} + +// Adjust from EDID-encoded maxCLL/maxFALL to actual values in units of 1 cd/m2 +static inline NvU32 MaxCvToVal(NvU32 cv) +{ + // 50*2^(cv/32) + return f64_to_ui32( + f64_mul(ui32_to_f64(50), + nvKmsPow(ui32_to_f64(2), + f64_div(ui32_to_f64(cv), + ui32_to_f64(32)))), softfloat_round_near_even, FALSE); +} + +// Adjust from EDID-encoded minCLL to actual value in units of 0.0001 cd/m2 +static inline NvU32 MinCvToVal(NvU32 cv, NvU32 maxCLL) +{ + // 10,000 * (minCLL = (maxCLL * ((cv/255)^2 / 100))) + return f64_to_ui32( + f64_mul(ui32_to_f64(10000), + f64_mul(ui32_to_f64(maxCLL), + f64_div(nvKmsPow(f64_div(ui32_to_f64(cv), + ui32_to_f64(255)), + ui32_to_f64(2)), + ui32_to_f64(100)))), + softfloat_round_near_even, FALSE); +} + +static void UpdateHDR(NVDevEvoPtr pDevEvo, + const NVFlipEvoHwState *pFlipState, + const NvU32 sd, + const NvU32 head, + const NVT_HDR_STATIC_METADATA *pHdrInfo, + NVEvoUpdateState *updateState) +{ + NVDispEvoPtr pDispEvo = pDevEvo->gpus[sd].pDispEvo; + NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + NvBool dirty = FALSE; + + if (pFlipState->dirty.tf) { + // XXX HDR TODO: Handle other transfer functions + if (pFlipState->tf == NVKMS_OUTPUT_TF_PQ) { + pHeadState->hdr.outputState = NVKMS_HDR_OUTPUT_STATE_HDR; + } else if (pHeadState->hdr.outputState == NVKMS_HDR_OUTPUT_STATE_HDR) { + pHeadState->hdr.outputState = + NVKMS_HDR_OUTPUT_STATE_TRANSITIONING_TO_SDR; + } + pHeadState->tf = pFlipState->tf; + + dirty = TRUE; + } + + if (pFlipState->dirty.hdrStaticMetadata) { + NvU32 layer; + NvBool found = FALSE; + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + // Populate head with updated static metadata. + if (pFlipState->layer[layer].hdrStaticMetadata.enabled) { + NvU32 targetMaxCLL = MaxCvToVal(pHdrInfo->max_cll); + + // Send this layer's metadata to the display. + pHeadState->hdr.staticMetadata = + pFlipState->layer[layer].hdrStaticMetadata.val; + + /* + * Prepare for tone mapping. If we expect to tone map and the + * EDID has valid lum values, mirror EDID lum values to prevent + * redundant tone mapping by the display. We will tone map to + * the specified maxCLL. + */ + if (nvNeedsTmoLut(pDevEvo, pDevEvo->head[head].layer[layer], + &pFlipState->layer[layer], + nvGetHDRSrcMaxLum( + &pFlipState->layer[layer]), + targetMaxCLL)) { + NvU32 targetMaxFALL = MaxCvToVal(pHdrInfo->max_fall); + if ((targetMaxCLL > 0) && + (targetMaxCLL <= 10000) && + (targetMaxCLL >= targetMaxFALL)) { + + NvU32 targetMinCLL = MinCvToVal(pHdrInfo->min_cll, + targetMaxCLL); + + pHeadState->hdr.staticMetadata. + maxDisplayMasteringLuminance = targetMaxCLL; + pHeadState->hdr.staticMetadata. + minDisplayMasteringLuminance = targetMinCLL; + pHeadState->hdr.staticMetadata.maxCLL = targetMaxCLL; + pHeadState->hdr.staticMetadata.maxFALL = targetMaxFALL; + } + } + + /* + * Only one layer can currently specify static metadata, + * verified by ValidateHDR(). + * + * XXX HDR TODO: Combine metadata from multiple layers. + */ + nvAssert(!found); + found = TRUE; + } + } + if (!found) { + nvkms_memset(&pHeadState->hdr.staticMetadata, 0, + sizeof(struct NvKmsHDRStaticMetadata)); + } + + dirty = TRUE; + } + + if (dirty) { + // Update OCSC / OLUT + nvEvoSetLUTContextDma(pDispEvo, head, updateState); + } +} + +/*! + * Program a flip on all requested layers on the specified head. + * + * This also updates pDispEvo->headState[head], caching what was programmed. + + * \param[in,out] pDispEvo The disp on which the flip should be performed. + * \param[in] head The head on which the flip should be performed. + * \param[in] pFlipState The description of how to update each layer. + * \param[in,out] updateState Indicates which channels require UPDATEs + */ +void nvFlipEvoOneHead( + NVDevEvoPtr pDevEvo, + const NvU32 sd, + const NvU32 head, + const NVT_HDR_STATIC_METADATA *pHdrInfo, + const NVFlipEvoHwState *pFlipState, + NvBool allowFlipLock, + NVEvoUpdateState *updateState) +{ + const NvU32 subDeviceMask = NVBIT(sd); + const NVDispHeadStateEvoRec *pHeadState = + &pDevEvo->gpus[sd].pDispEvo->headState[head]; + NvBool bypassComposition = pHeadState->bypassComposition; + NVEvoSubDevHeadStateRec *pSdHeadState = + &pDevEvo->gpus[sd].headState[head]; + NvU32 layer; + + /* + * Provide the pre-update hardware state (in pSdHeadState) and the new + * target state (pFlipState) to the HAL implementation so that it has the + * information it needs to implement the workaround for hardware bug + * 2193096, which requires special logic on transitions between NULL and + * non-NULL ctxdmas (and vice versa). + */ + pDevEvo->hal->FlipTransitionWAR(pDevEvo, sd, head, + pSdHeadState, pFlipState, + updateState); + + /* + * Promote the software state first, such that the hardware programming + * paths below see the new state atomically. + */ + if (pFlipState->dirty.viewPortPointIn) { + pSdHeadState->viewPortPointIn = pFlipState->viewPortPointIn; + } + + if (pFlipState->dirty.cursorSurface || pFlipState->dirty.cursorPosition) { + pSdHeadState->cursor = pFlipState->cursor; + } + + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + if (pFlipState->dirty.layer[layer]) { + pSdHeadState->layer[layer] = pFlipState->layer[layer]; + } + } + + if (pFlipState->dirty.viewPortPointIn) { + nvSetViewPortPointInEvo(pDevEvo->gpus[sd].pDispEvo, + head, + pFlipState->viewPortPointIn.x, + pFlipState->viewPortPointIn.y, + updateState); + } + + if (pFlipState->dirty.cursorSurface) { + nvPushEvoSubDevMask(pDevEvo, NVBIT(sd)); + pDevEvo->hal->SetCursorImage(pDevEvo, + head, + pSdHeadState->cursor.pSurfaceEvo, + updateState, + &pSdHeadState->cursor.cursorCompParams); + nvPopEvoSubDevMask(pDevEvo); + } + + if (pFlipState->dirty.cursorPosition) { + nvEvoMoveCursorInternal(pDevEvo->gpus[sd].pDispEvo, + head, + pFlipState->cursor.x, + pFlipState->cursor.y); + } + + UpdateHDR(pDevEvo, pFlipState, sd, head, pHdrInfo, updateState); + + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + if (!pFlipState->dirty.layer[layer]) { + continue; + } + + if (pFlipState->dirty.layerPosition[layer]) { + /* Ensure position updates are supported on this layer. */ + nvAssert(pDevEvo->caps.layerCaps[layer].supportsWindowMode); + + pDevEvo->hal->SetImmPointOut(pDevEvo, + pDevEvo->head[head].layer[layer], + sd, + updateState, + pFlipState->layer[layer].outputPosition.x, + pFlipState->layer[layer].outputPosition.y); + + if (pDevEvo->hal->caps.supportsSynchronizedOverlayPositionUpdate) { + UpdateWinImmInterlockState(pDevEvo, updateState, + pDevEvo->head[head].layer[layer]); + } + } + + nvPushEvoSubDevMask(pDevEvo, subDeviceMask); + + /* Inform DIFR about the upcoming flip. */ + if (pDevEvo->pDifrState) { + nvDIFRNotifyFlip(pDevEvo->pDifrState); + } + + pDevEvo->hal->Flip(pDevEvo, + pDevEvo->head[head].layer[layer], + &pFlipState->layer[layer], + updateState, + bypassComposition); + if (layer == NVKMS_MAIN_LAYER && allowFlipLock) { + UpdateUpdateFlipLockState(pDevEvo, updateState, + pDevEvo->head[head].layer[layer]); + } + nvPopEvoSubDevMask(pDevEvo); + } + + pSdHeadState->targetUsage = pFlipState->usage; + + pSdHeadState->targetDisableMidFrameAndDWCFWatermark = + pFlipState->disableMidFrameAndDWCFWatermark; +} + +static void ChangeSurfaceFlipRefCount( + NVDevEvoPtr pDevEvo, + NVSurfaceEvoPtr pSurfaceEvo, + NvBool increase) +{ + if (pSurfaceEvo != NULL) { + if (increase) { + nvEvoIncrementSurfaceRefCnts(pSurfaceEvo); + } else { + nvEvoDecrementSurfaceRefCnts(pSurfaceEvo); + } + } +} + +void nvUpdateSurfacesFlipRefCount( + NVDevEvoPtr pDevEvo, + const NvU32 head, + NVFlipEvoHwState *pFlipState, + NvBool increase) +{ + NvU32 i; + + ChangeSurfaceFlipRefCount( + pDevEvo, + pFlipState->cursor.pSurfaceEvo, + increase); + + for (i = 0; i < pDevEvo->head[head].numLayers; i++) { + NVFlipChannelEvoHwState *pLayerFlipState = &pFlipState->layer[i]; + + ChangeSurfaceFlipRefCount( + pDevEvo, + pLayerFlipState->pSurfaceEvo[NVKMS_LEFT], + increase); + ChangeSurfaceFlipRefCount( + pDevEvo, + pLayerFlipState->pSurfaceEvo[NVKMS_RIGHT], + increase); + ChangeSurfaceFlipRefCount( + pDevEvo, + pLayerFlipState->completionNotifier.surface.pSurfaceEvo, + increase); + + if (!pLayerFlipState->syncObject.usingSyncpt) { + ChangeSurfaceFlipRefCount( + pDevEvo, + pLayerFlipState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo, + increase); + ChangeSurfaceFlipRefCount( + pDevEvo, + pLayerFlipState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo, + increase); + } + } +} + +static void UnionScalingUsageBounds( + const struct NvKmsScalingUsageBounds *a, + const struct NvKmsScalingUsageBounds *b, + struct NvKmsScalingUsageBounds *ret) +{ + ret->maxVDownscaleFactor = NV_MAX(a->maxVDownscaleFactor, + b->maxVDownscaleFactor); + ret->maxHDownscaleFactor = NV_MAX(a->maxHDownscaleFactor, + b->maxHDownscaleFactor); + ret->vTaps = NV_MAX(a->vTaps, b->vTaps); + ret->vUpscalingAllowed = a->vUpscalingAllowed || b->vUpscalingAllowed; +} + +void nvUnionUsageBounds(const struct NvKmsUsageBounds *a, + const struct NvKmsUsageBounds *b, + struct NvKmsUsageBounds *ret) +{ + NvU32 i; + + nvkms_memset(ret, 0, sizeof(*ret)); + + for (i = 0; i < ARRAY_LEN(a->layer); i++) { + nvAssert(a->layer[i].usable == + !!a->layer[i].supportedSurfaceMemoryFormats); + nvAssert(b->layer[i].usable == + !!b->layer[i].supportedSurfaceMemoryFormats); + + ret->layer[i].usable = a->layer[i].usable || b->layer[i].usable; + + ret->layer[i].supportedSurfaceMemoryFormats = + a->layer[i].supportedSurfaceMemoryFormats | + b->layer[i].supportedSurfaceMemoryFormats; + + UnionScalingUsageBounds(&a->layer[i].scaling, + &b->layer[i].scaling, + &ret->layer[i].scaling); + } +} + +NvBool UsageBoundsEqual( + const struct NvKmsUsageBounds *a, + const struct NvKmsUsageBounds *b) +{ + NvU32 layer; + + for (layer = 0; layer < ARRAY_LEN(a->layer); layer++) { + if (!nvEvoLayerUsageBoundsEqual(a, b, layer)) { + return FALSE; + } + } + + return TRUE; +} + +NvBool nvAllocatePreFlipBandwidth(NVDevEvoPtr pDevEvo, + struct NvKmsFlipWorkArea *pWorkArea) +{ + NVValidateImpOneDispHeadParamsRec *timingsParams = NULL; + struct NvKmsUsageBounds *currentAndNew = NULL; + struct NvKmsUsageBounds *guaranteedAndCurrent = NULL; + NVDispEvoPtr pDispEvo; + NvU32 head; + NvBool recheckIMP = FALSE; + NvBool ret = TRUE; + + if (!pDevEvo->isSOCDisplay) { + return TRUE; + } + + timingsParams = + nvCalloc(NVKMS_MAX_HEADS_PER_DISP, sizeof(*timingsParams)); + if (timingsParams == NULL) { + return FALSE; + } + + currentAndNew = + nvCalloc(NVKMS_MAX_HEADS_PER_DISP, sizeof(*currentAndNew)); + if (currentAndNew == NULL) { + nvFree(timingsParams); + return FALSE; + } + + guaranteedAndCurrent = + nvCalloc(NVKMS_MAX_HEADS_PER_DISP, sizeof(*guaranteedAndCurrent)); + if (guaranteedAndCurrent == NULL) { + nvFree(timingsParams); + nvFree(currentAndNew); + return FALSE; + } + + pDispEvo = pDevEvo->pDispEvo[0]; + + // SOC Display never has more than one disp + nvAssert(pDevEvo->nDispEvo == 1); + + for (head = 0; head < pDevEvo->numHeads; head++) { + NVDispHeadStateEvoRec *pHeadState = + &pDispEvo->headState[head]; + const struct NvKmsUsageBounds *pCurrent = + &pDevEvo->gpus[0].headState[head].preallocatedUsage; + const struct NvKmsUsageBounds *pNew = + &pWorkArea->sd[0].head[head].newState.usage; + + if (pHeadState->activeRmId == 0) { + continue; + } + + timingsParams[head].pConnectorEvo = pHeadState->pConnectorEvo; + timingsParams[head].activeRmId = pHeadState->activeRmId; + timingsParams[head].pixelDepth = pHeadState->pixelDepth; + timingsParams[head].pTimings = &pHeadState->timings; + + nvUnionUsageBounds(pCurrent, pNew, ¤tAndNew[head]); + nvUnionUsageBounds(&pHeadState->timings.viewPort.guaranteedUsage, + pCurrent, &guaranteedAndCurrent[head]); + + if (!ValidateUsageBounds(pDevEvo, + head, + pNew, + &guaranteedAndCurrent[head])) { + recheckIMP = TRUE; + } + + nvUnionUsageBounds(&guaranteedAndCurrent[head], pNew, + &guaranteedAndCurrent[head]); + timingsParams[head].pUsage = &guaranteedAndCurrent[head]; + } + + if (recheckIMP) { + ret = nvValidateImpOneDisp(pDispEvo, timingsParams, + FALSE /* requireBootClocks */, + NV_EVO_REALLOCATE_BANDWIDTH_MODE_PRE, + NULL /* pMinIsoBandwidthKBPS */, + NULL /* pMinDramFloorKBPS */); + if (ret) { + for (head = 0; head < pDevEvo->numHeads; head++) { + pDevEvo->gpus[0].headState[head].preallocatedUsage = + currentAndNew[head]; + } + } + } + + nvFree(timingsParams); + nvFree(currentAndNew); + nvFree(guaranteedAndCurrent); + + if (ret) { + nvScheduleLowerDispBandwidthTimer(pDevEvo); + } + + return ret; +} + +/*! + * If the satellite channel is active then pre-NVDisplay hardware does not allow + * to change its usage bounds in non-interlock update. The nvSetUsageBoundsEvo() + * code path for pre-NVDisplay hardware, interlocks the satellite channels with + * the usage bounds update. This makes it essential to poll for + * NO_METHOD_PENDING state of the satellite channels, otherwise blocking + * pre-flip IMP update will also get stuck. + * + * It is not possible to interlock flip-locked satellite channels with the core + * channel usage bounds update; in that case, reject the flip. Do not allow + * client to make any change in surface usage bounds parameters without + * deactivating channel first, if channel is flip-locked. + */ +static NvBool PrepareToDoPreFlipIMP(NVDevEvoPtr pDevEvo, + struct NvKmsFlipWorkArea *pWorkArea) +{ + NvU64 startTime = 0; + NvU32 timeout = 2000000; /* 2 seconds */ + NvU32 sd; + + for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { + NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[sd]; + NvU32 head; + + for (head = 0; head < pDevEvo->numHeads; head++) { + NVEvoHeadControlPtr pHC = + &pEvoSubDev->headControl[head]; + const NVEvoSubDevHeadStateRec *pCurrentFlipState = + &pDevEvo->gpus[sd].headState[head]; + const NVSurfaceEvoRec *pCurrentBaseSurf = + pCurrentFlipState->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[NVKMS_LEFT]; + const struct NvKmsUsageBounds *pCurrentUsage = + &pCurrentFlipState->usage; + + NVFlipEvoHwState *pNewFlipState = + &pWorkArea->sd[sd].head[head].newState; + const NVSurfaceEvoRec *pNewBaseSurf = + pNewFlipState->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[NVKMS_LEFT]; + struct NvKmsUsageBounds *pNewUsage = + &pNewFlipState->usage; + + struct NvKmsUsageBounds *pPreFlipUsage = + &pWorkArea->sd[sd].head[head].preFlipUsage; + + NvU32 layer; + + nvUnionUsageBounds(pNewUsage, pCurrentUsage, pPreFlipUsage); + + if (pDevEvo->hal->caps.supportsNonInterlockedUsageBoundsUpdate) { + /* + * NVDisplay does not interlock the satellite channel + * with its usage bounds update. + */ + continue; + } + + /* + * If head is flip-locked then do not change usage + * bounds while base channel is active. + */ + if (pHC->flipLock && + /* If the base channel is active before and after flip then + * current and new base usage bounds should be same. */ + ((pNewBaseSurf != NULL && + pCurrentBaseSurf != NULL && + !nvEvoLayerUsageBoundsEqual(pCurrentUsage, + pNewUsage, NVKMS_MAIN_LAYER)) || + /* If the base channel is active before flip then current and + * preflip base usage bounds should be same. */ + (pCurrentBaseSurf != NULL && + !nvEvoLayerUsageBoundsEqual(pCurrentUsage, + pPreFlipUsage, NVKMS_MAIN_LAYER)))) { + return FALSE; + } + + /* + * Poll for NO_METHOD_PENDING state if usage + * bounds of the channel are changed. + */ + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + if (!nvEvoLayerUsageBoundsEqual(pCurrentUsage, + pPreFlipUsage, layer) && + !nvEvoPollForNoMethodPending(pDevEvo, + sd, + pDevEvo->head[head].layer[layer], + &startTime, + timeout)) { + return FALSE; + } + } + } + } + + return TRUE; +} + +/*! + * Tasks need to perform before triggering flip, they all should be done here. + * + * If necessary, raise usage bounds and/or disable MidFrameAndDWCFWatermark + * (bug 200508242) in the core channel and do an IMP update. + * + * Note that this function only raises usage bounds and/or disables + * MidFrameAndDWCFWatermark, never lowers usage bounds and/or enables + * MidFrameAndDWCFWatermark. This allows it to run before queuing a flip even + * if there are still pending flips in a base channel. + */ +static void PreFlipIMP(NVDevEvoPtr pDevEvo, + const struct NvKmsFlipWorkArea *pWorkArea) +{ + NvU32 head, sd; + NVDispEvoPtr pDispEvo; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + NVEvoUpdateState updateState = { }; + NvBool update = FALSE; + + for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { + const NVFlipEvoHwState *pNewState = + &pWorkArea->sd[sd].head[head].newState; + const struct NvKmsUsageBounds *pPreFlipUsage = + &pWorkArea->sd[sd].head[head].preFlipUsage; + struct NvKmsUsageBounds *pCurrentUsage = + &pDevEvo->gpus[sd].headState[head].usage; + + if (!UsageBoundsEqual(pCurrentUsage, pPreFlipUsage)) { + update |= nvSetUsageBoundsEvo(pDevEvo, sd, head, + pPreFlipUsage, &updateState); + } + + if (!pDevEvo->gpus[sd]. + headState[head].disableMidFrameAndDWCFWatermark && + pNewState->disableMidFrameAndDWCFWatermark) { + + nvEnableMidFrameAndDWCFWatermark(pDevEvo, + sd, + head, + FALSE /* enable */, + &updateState); + update = TRUE; + } + } + + if (update) { + nvDoIMPUpdateEvo(pDispEvo, &updateState); + } + } +} + +static void LowerDispBandwidth(void *dataPtr, NvU32 dataU32) +{ + NVValidateImpOneDispHeadParamsRec timingsParams[NVKMS_MAX_HEADS_PER_DISP]; + struct NvKmsUsageBounds *guaranteedAndCurrent; + NVDevEvoPtr pDevEvo = dataPtr; + NVDispEvoPtr pDispEvo; + NvU32 head; + NvBool ret; + + guaranteedAndCurrent = + nvCalloc(1, sizeof(*guaranteedAndCurrent) * NVKMS_MAX_HEADS_PER_DISP); + if (guaranteedAndCurrent == NULL) { + nvAssert(guaranteedAndCurrent != NULL); + return; + } + + nvkms_memset(&timingsParams, 0, sizeof(timingsParams)); + + pDispEvo = pDevEvo->pDispEvo[0]; + + // SOC Display never has more than one disp + nvAssert(pDevEvo->nDispEvo == 1); + + for (head = 0; head < pDevEvo->numHeads; head++) { + NVDispHeadStateEvoRec *pHeadState = + &pDispEvo->headState[head]; + const struct NvKmsUsageBounds *pGuaranteed = + &pHeadState->timings.viewPort.guaranteedUsage; + const struct NvKmsUsageBounds *pCurrent = + &pDevEvo->gpus[0].headState[head].usage; + + if (pHeadState->activeRmId == 0) { + continue; + } + + timingsParams[head].pConnectorEvo = pHeadState->pConnectorEvo; + timingsParams[head].activeRmId = pHeadState->activeRmId; + timingsParams[head].pixelDepth = pHeadState->pixelDepth; + timingsParams[head].pTimings = &pHeadState->timings; + + nvUnionUsageBounds(pGuaranteed, pCurrent, &guaranteedAndCurrent[head]); + timingsParams[head].pUsage = &guaranteedAndCurrent[head]; + } + + ret = nvValidateImpOneDisp(pDispEvo, timingsParams, + FALSE /* requireBootClocks */, + NV_EVO_REALLOCATE_BANDWIDTH_MODE_POST, + NULL /* pMinIsoBandwidthKBPS */, + NULL /* pMinDramFloorKBPS */); + if (ret) { + for (head = 0; head < pDevEvo->numHeads; head++) { + pDevEvo->gpus[0].headState[head].preallocatedUsage = + pDevEvo->gpus[0].headState[head].usage; + } + } + + nvAssert(ret); + + nvFree(guaranteedAndCurrent); +} + +void nvCancelLowerDispBandwidthTimer(NVDevEvoPtr pDevEvo) +{ + nvkms_free_timer(pDevEvo->lowerDispBandwidthTimer); + pDevEvo->lowerDispBandwidthTimer = NULL; +} + +void nvScheduleLowerDispBandwidthTimer(NVDevEvoPtr pDevEvo) +{ + nvAssert(pDevEvo->isSOCDisplay); + + nvCancelLowerDispBandwidthTimer(pDevEvo); + + pDevEvo->lowerDispBandwidthTimer = + nvkms_alloc_timer(LowerDispBandwidth, + pDevEvo, + 0, /* dataU32 */ + 30000000 /* 30 seconds */); +} + +/*! + * Check whether the core, base, and overlay channels are idle (i.e. no methods + * pending in the corresponding pushbuffer) and lower the usage bounds if + * possible. + */ +static NvBool TryLoweringUsageBoundsOneHead(NVDevEvoPtr pDevEvo, NvU32 sd, + NvU32 head, + NVEvoUpdateState *updateState) +{ + const NVEvoSubDevHeadStateRec *pHeadState = + &pDevEvo->gpus[sd].headState[head]; + const struct NvKmsUsageBounds *pCurrent = &pHeadState->usage; + const struct NvKmsUsageBounds *pTarget = &pHeadState->targetUsage; + struct NvKmsUsageBounds newUsage = *pCurrent; + NvBool changed = FALSE; + NvBool scheduleLater = FALSE; + int i; + + for (i = 0; i < pDevEvo->head[head].numLayers; i++) { + if (pCurrent->layer[i].usable && !pTarget->layer[i].usable) { + NvBool isMethodPending; + + if (pDevEvo->hal->IsChannelMethodPending( + pDevEvo, + pDevEvo->head[head].layer[i], + sd, + &isMethodPending) && !isMethodPending) { + newUsage.layer[i] = pTarget->layer[i]; + changed = TRUE; + } else { + scheduleLater = TRUE; + } + } else if ((pCurrent->layer[i].usable && pTarget->layer[i].usable) && + ((pCurrent->layer[i].supportedSurfaceMemoryFormats != + pTarget->layer[i].supportedSurfaceMemoryFormats) || + (!nvEvoScalingUsageBoundsEqual(&pCurrent->layer[i].scaling, + &pTarget->layer[i].scaling)))) { + NvBool isMethodPending; + + if (pDevEvo->hal->IsChannelMethodPending( + pDevEvo, + pDevEvo->head[head].layer[i], + sd, + &isMethodPending) && !isMethodPending) { + newUsage.layer[i] = pTarget->layer[i]; + changed = TRUE; + } else { + scheduleLater = TRUE; + } + } + } + + if (scheduleLater) { + SchedulePostFlipIMPTimer(pDevEvo); + } + + if (changed) { + changed = nvSetUsageBoundsEvo(pDevEvo, sd, head, &newUsage, + updateState); + } + + return changed; +} + +static NvBool +TryEnablingMidFrameAndDWCFWatermarkOneHead(NVDevEvoPtr pDevEvo, + NvU32 sd, + NvU32 head, + NVEvoUpdateState *updateState) +{ + const NVEvoSubDevHeadStateRec *pHeadState = + &pDevEvo->gpus[sd].headState[head]; + NvBool changed = FALSE; + + if (pHeadState->disableMidFrameAndDWCFWatermark && + !pHeadState->targetDisableMidFrameAndDWCFWatermark) { + + NvBool isIdle; + + if (pDevEvo->hal->IsChannelIdle(pDevEvo, + pDevEvo->head[head].layer[NVKMS_MAIN_LAYER], + sd, + &isIdle) && isIdle) { + nvEnableMidFrameAndDWCFWatermark(pDevEvo, + sd, + head, + TRUE /* enable */, + updateState); + changed = TRUE; + } else { + // Schedule another timer to try again later. + SchedulePostFlipIMPTimer(pDevEvo); + } + } + + return changed; +} + +static void +TryToDoPostFlipIMP(void *dataPtr, NvU32 dataU32) +{ + NVDevEvoPtr pDevEvo = dataPtr; + NvU32 head, sd; + NVDispEvoPtr pDispEvo; + + pDevEvo->postFlipIMPTimer = NULL; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + NVEvoUpdateState updateState = { }; + NvBool update = FALSE; + + for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { + if (TryLoweringUsageBoundsOneHead(pDevEvo, sd, head, + &updateState)) { + update = TRUE; + } + + if (TryEnablingMidFrameAndDWCFWatermarkOneHead( + pDevEvo, + sd, + head, + &updateState)) { + update = TRUE; + } + } + + if (update) { + nvDoIMPUpdateEvo(pDispEvo, &updateState); + } + } +} + +static void SchedulePostFlipIMPTimer(NVDevEvoPtr pDevEvo) +{ + if (!pDevEvo->postFlipIMPTimer) { + pDevEvo->postFlipIMPTimer = + nvkms_alloc_timer( + TryToDoPostFlipIMP, + pDevEvo, + 0, /* dataU32 */ + 10000000 /* 10 seconds */); + } +} + +void nvEvoCancelPostFlipIMPTimer(NVDevEvoPtr pDevEvo) +{ + nvkms_free_timer(pDevEvo->postFlipIMPTimer); + pDevEvo->postFlipIMPTimer = NULL; +} + +/*! + * If necessary, schedule a timer to see if usage bounds can be lowered. + */ +static void SchedulePostFlipIMP(NVDevEvoPtr pDevEvo) +{ + NvU32 head, sd; + NVDispEvoPtr pDispEvo; + + // If a timer is already scheduled, do nothing. + if (pDevEvo->postFlipIMPTimer) { + return; + } + + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { + const NVEvoSubDevHeadStateRec *pHeadState = + &pDevEvo->gpus[sd].headState[head]; + + if (!UsageBoundsEqual(&pHeadState->usage, + &pHeadState->targetUsage) || + (pHeadState->disableMidFrameAndDWCFWatermark != + pHeadState->targetDisableMidFrameAndDWCFWatermark)) { + + SchedulePostFlipIMPTimer(pDevEvo); + return; + } + } + } +} + +static void SkipLayerPendingFlips(NVDevEvoRec *pDevEvo, + const NvBool trashPendingMethods, + const NvBool unblockMethodsInExecutation, + struct NvKmsFlipWorkArea *pWorkArea) +{ + NvU64 startTime = 0; + const NvU32 timeout = 2000000; /* 2 seconds */ + struct { + struct { + struct { + NvU32 oldAccelMask; + } head[NVKMS_MAX_HEADS_PER_DISP]; + } sd[NVKMS_MAX_SUBDEVICES]; + } accelState = { }; + NvU32 sd, head; + + for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { + if (!pWorkArea->sd[sd].changed) { + continue; + } + + for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { + const NVFlipEvoHwState *pFlipState = + &pWorkArea->sd[sd].head[head].newState; + + if (!pFlipState->skipLayerPendingFlips[NVKMS_MAIN_LAYER]|| + !pFlipState->dirty.layer[NVKMS_MAIN_LAYER]) { + continue; + } + + pDevEvo->hal->AccelerateChannel( + pDevEvo, + pDevEvo->head[head].layer[NVKMS_MAIN_LAYER], + sd, + trashPendingMethods, + unblockMethodsInExecutation, + &accelState.sd[sd].head[head].oldAccelMask); + } + } + + for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { + if (!pWorkArea->sd[sd].changed) { + continue; + } + + for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { + const NVFlipEvoHwState *pFlipState = + &pWorkArea->sd[sd].head[head].newState; + + if (!pFlipState->skipLayerPendingFlips[NVKMS_MAIN_LAYER] || + !pFlipState->dirty.layer[NVKMS_MAIN_LAYER]) { + continue; + } + + if (unblockMethodsInExecutation) { + if (!nvEvoPollForNoMethodPending(pDevEvo, + sd, + pDevEvo->head[head].layer[NVKMS_MAIN_LAYER], + &startTime, + timeout)) { + nvAssert(!"Failed to idle the main layer channel"); + } + } else { + if (!nvEvoPollForEmptyChannel(pDevEvo->head[head].layer[NVKMS_MAIN_LAYER], + sd, + &startTime, + timeout)) { + nvAssert(!"Failed to empty the main layer channel"); + } + } + + pDevEvo->hal->ResetChannelAccelerators( + pDevEvo, + pDevEvo->head[head].layer[NVKMS_MAIN_LAYER], + sd, + trashPendingMethods, + unblockMethodsInExecutation, + accelState.sd[sd].head[head].oldAccelMask); + } + } +} + +void nvPreFlip(NVDevEvoRec *pDevEvo, + struct NvKmsFlipWorkArea *pWorkArea, + const NvBool applyAllowVrr, + const NvBool allowVrr, + const NvBool skipUpdate) +{ + NvU32 sd, head; + + for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { + + if (!pWorkArea->sd[sd].changed) { + continue; + } + + for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { + // Increase refCnt of surfaces used AFTER flip + nvUpdateSurfacesFlipRefCount( + pDevEvo, + head, + &pWorkArea->sd[sd].head[head].newState, + NV_TRUE); + + nvRefTmoLutSurfacesEvo( + pDevEvo, + &pWorkArea->sd[sd].head[head].newState, + head); + } + } + + PreFlipIMP(pDevEvo, pWorkArea); + + if (!skipUpdate) { + /* Trash flips pending in channel which are not yet in execution */ + SkipLayerPendingFlips(pDevEvo, TRUE /* trashPendingMethods */, + FALSE /* unblockMethodsInExecutation */, + pWorkArea); + } + + if (applyAllowVrr) { + nvSetVrrActive(pDevEvo, allowVrr); + } + +} + +void nvPostFlip(NVDevEvoRec *pDevEvo, + struct NvKmsFlipWorkArea *pWorkArea, + const NvBool skipUpdate, + const NvBool applyAllowVrr, + NvS32 *pVrrSemaphoreIndex) +{ + NvU32 sd, head; + + if (!skipUpdate) { + /* Unblock flips which are stuck in execution */ + SkipLayerPendingFlips(pDevEvo, FALSE /* trashPendingMethods */, + TRUE /* unblockMethodsInExecutation */, + pWorkArea); + } + + if (applyAllowVrr) { + *pVrrSemaphoreIndex = nvIncVrrSemaphoreIndex(pDevEvo); + } else { + // TODO Schedule vrr unstall; per-disp/per-device? + } + + for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { + if (!pWorkArea->sd[sd].changed) { + continue; + } + + for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { + // Decrease refCnt of surfaces used BEFORE the flip + nvUpdateSurfacesFlipRefCount( + pDevEvo, + head, + &pWorkArea->sd[sd].head[head].oldState, + NV_FALSE); + + nvUnrefTmoLutSurfacesEvo( + pDevEvo, + &pWorkArea->sd[sd].head[head].oldState, + head); + } + } + + if (!skipUpdate) { + // Note that usage bounds are not lowered here, because the flip + // queued by this function may not occur until later. Instead, schedule + // a timer for later to check if the usage bounds can be lowered. + SchedulePostFlipIMP(pDevEvo); + + pDevEvo->skipConsoleRestore = FALSE; + } +} + +NvBool nvPrepareToDoPreFlip(NVDevEvoRec *pDevEvo, + struct NvKmsFlipWorkArea *pWorkArea) +{ + if (!RegisterPreSyncpt(pDevEvo, pWorkArea)) { + return FALSE; + } + + if (!PrepareToDoPreFlipIMP(pDevEvo, pWorkArea)) { + return FALSE; + } + + return TRUE; +} + +NvBool nvAssignNVFlipEvoHwState(NVDevEvoRec *pDevEvo, + const struct NvKmsPerOpenDev *pOpenDev, + const NvU32 sd, + const NvU32 head, + const struct NvKmsFlipCommonParams *pParams, + const NvBool allowVrr, + NVFlipEvoHwState *pFlipHwState) +{ + const NVDispEvoRec *pDispEvo = pDevEvo->gpus[sd].pDispEvo; + const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + const struct NvKmsUsageBounds *pPossibleUsage = + &pHeadState->timings.viewPort.possibleUsage; + + if (!nvUpdateFlipEvoHwState(pOpenDev, pDevEvo, sd, head, pParams, + &pHeadState->timings, pFlipHwState, allowVrr)) { + return FALSE; + } + + nvOverrideScalingUsageBounds(pDevEvo, head, pFlipHwState, pPossibleUsage); + + if (!nvValidateFlipEvoHwState(pDevEvo, head, &pHeadState->timings, + pFlipHwState)) { + return FALSE; + } + + if (!nvSetTmoLutSurfacesEvo(pDevEvo, pFlipHwState, head)) { + return FALSE; + } + + return TRUE; +} + +/*! + * Wait for idle on a set of the main layer channels. + * + * \param[in,out] pDevEvo The device. + * \param[in] idleChannelMaskPerSd The channel masks per subdevice that + * we should wait to be idle. + * \param[in] allowForceIdle Whether we should force idle a channel + * or just assert if the idle times out. + */ +void nvIdleMainLayerChannels( + NVDevEvoPtr pDevEvo, + const NVEvoChannelMask *idleChannelMaskPerSd, + NvBool allowStopBase) +{ + NvU64 startTime = 0; + NvBool allChannelsIdle = FALSE; + NVDispEvoPtr pDispEvo; + NvU32 dispIndex, head; + NVEvoChannelMask busyChannelMaskPerSd[NVKMS_MAX_SUBDEVICES] = { }; + + /* + * Wait up to 2 seconds for all channels to be idle, and gather a list of + * all busy channels. + */ + while (!allChannelsIdle) { + + const NvU32 timeout = 2000000; /* 2 seconds */ + NvBool anyChannelBusy = FALSE; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + for (head = 0; head < pDevEvo->numHeads; head++) { + NVEvoChannelPtr pMainLayerChannel = + pDevEvo->head[head].layer[NVKMS_MAIN_LAYER]; + if (idleChannelMaskPerSd[pDispEvo->displayOwner] & + pMainLayerChannel->channelMask) { + + NvBool isMethodPending = FALSE; + if (!pDevEvo->hal->IsChannelMethodPending( + pDevEvo, + pMainLayerChannel, + pDispEvo->displayOwner, + &isMethodPending) + || isMethodPending) { + + /* Mark this channel as busy. */ + busyChannelMaskPerSd[pDispEvo->displayOwner] |= + pMainLayerChannel->channelMask; + anyChannelBusy = TRUE; + } else { + /* + * Mark this channel as no longer busy, in case its + * flip completed while we were waiting on another + * channel. + */ + busyChannelMaskPerSd[pDispEvo->displayOwner] &= + ~pMainLayerChannel->channelMask; + } + } + } + } + + if (!anyChannelBusy) { + allChannelsIdle = TRUE; + break; + } + + /* Break out of the loop if we exceed the timeout. */ + if (nvExceedsTimeoutUSec(&startTime, timeout)) { + break; + } + + nvkms_yield(); + } + + if (!allChannelsIdle) { + /* + * At least one channel was still idle after the 2 second timeout + * above. + */ + if (!allowStopBase) { + /* + * The caller of this function expected this wait for idle not to + * time out. + */ + nvEvoLogDev(pDevEvo, EVO_LOG_WARN, + "Timeout while waiting for idle."); + } else { + /* + * Idle all base channels that were still busy when the wait above + * timed out. + */ + NVEvoIdleChannelState idleChannelState = { }; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + idleChannelState.subdev[pDispEvo->displayOwner].channelMask = + busyChannelMaskPerSd[pDispEvo->displayOwner]; + } + + pDevEvo->hal->ForceIdleSatelliteChannelIgnoreLock( + pDevEvo, &idleChannelState); + } + } +} + +NvBool nvNeedToToggleFlipLock(const NVDispEvoRec *pDispEvo, + const NvU32 head, const NvBool enable) +{ + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + const NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[pDispEvo->displayOwner]; + const NVEvoHeadControlPtr pHC = &pEvoSubDev->headControl[head]; + NvBool needToToggle = FALSE; + + if (!enable && pHC->flipLock) { + /* + * This channel is currently using fliplock in the config that + * is being torn down; idle its base channel and disable + * fliplock. + */ + needToToggle = TRUE; + } + + if (enable && ((pHC->serverLock != NV_EVO_NO_LOCK) || + (pHC->clientLock != NV_EVO_NO_LOCK))) { + /* + * This channel will be using fliplock for swap groups in the + * new config; idle its base channel and enable fliplock. + */ + nvAssert(!HEAD_MASK_QUERY(pEvoSubDev->flipLockProhibitedHeadMask, + head)); + needToToggle = TRUE; + } + + return needToToggle; +} + +void nvToggleFlipLockPerDisp(NVDispEvoRec *pDispEvo, const NvU32 headMask, + const NvBool enable) +{ + NvU32 head; + NVEvoUpdateState updateState = { }; + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + + for (head = 0; head < pDevEvo->numHeads; head++) { + if ((headMask & NVBIT(head)) != 0x0) { + NvU32 setEnable = enable; + + if (!nvUpdateFlipLockEvoOneHead(pDispEvo, head, &setEnable, + TRUE /* set */, + NULL /* needsEarlyUpdate */, + &updateState)) { + nvEvoLogDev(pDevEvo, EVO_LOG_WARN, + "Failed to toggle fliplock for swapgroups."); + } + } + } + + if (!nvIsUpdateStateEmpty(pDevEvo, &updateState)) { + nvEvoUpdateAndKickOff(pDispEvo, TRUE, &updateState, + TRUE /* releaseElv */); + } +} diff --git a/src/nvidia-modeset/src/nvkms-lut.c b/src/nvidia-modeset/src/nvkms-lut.c index fbe195ad0..944dcd2e0 100644 --- a/src/nvidia-modeset/src/nvkms-lut.c +++ b/src/nvidia-modeset/src/nvkms-lut.c @@ -40,6 +40,15 @@ static void FreeLutSurfaceEvoInVidmem(NVLutSurfaceEvoPtr pSurfEvo) pDevEvo = pSurfEvo->pDevEvo; + if (pSurfEvo->gpuAddress) { + nvRmApiUnmapMemoryDma(nvEvoGlobal.clientHandle, + pDevEvo->deviceHandle, + pDevEvo->nvkmsGpuVASpace, + pSurfEvo->handle, + 0, + (NvU64)pSurfEvo->gpuAddress); + } + nvRmEvoUnMapVideoMemory(pDevEvo, pSurfEvo->handle, pSurfEvo->subDeviceAddress); @@ -141,6 +150,24 @@ static NVLutSurfaceEvoPtr AllocLutSurfaceEvoInVidmem(NVDevEvoPtr pDevEvo) goto fail; } + /* + * The GPU mapping is only needed for prefetching LUT surfaces for DIFR. + * It isn't worth failing alone but we want to keep gpuAddress coherent. + */ + ret = nvRmApiMapMemoryDma(nvEvoGlobal.clientHandle, + pDevEvo->deviceHandle, + pDevEvo->nvkmsGpuVASpace, + pSurfEvo->handle, + 0, + pSurfEvo->size, + DRF_DEF(OS46, _FLAGS, _CACHE_SNOOP, _ENABLE) | + DRF_DEF(OS46, _FLAGS, _ACCESS, _READ_ONLY), + &pSurfEvo->gpuAddress); + + if (ret != NVOS_STATUS_SUCCESS) { + pSurfEvo->gpuAddress = 0ULL; + } + return pSurfEvo; fail: @@ -358,13 +385,13 @@ void nvUnrefTmoLutSurfacesEvo(NVDevEvoPtr pDevEvo, NvBool nvAllocLutSurfacesEvo(NVDevEvoPtr pDevEvo) { NVDispEvoPtr pDispEvo; - NvU32 head, dispIndex, i, sd; + NvU32 apiHead, dispIndex, i, sd; - for (head = 0; head < pDevEvo->numHeads; head++) { - for (i = 0; i < ARRAY_LEN(pDevEvo->lut.head[head].LUT); i++) { - pDevEvo->lut.head[head].LUT[i] = AllocLutSurfaceEvo(pDevEvo); + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + for (i = 0; i < ARRAY_LEN(pDevEvo->lut.apiHead[apiHead].LUT); i++) { + pDevEvo->lut.apiHead[apiHead].LUT[i] = AllocLutSurfaceEvo(pDevEvo); - if (pDevEvo->lut.head[head].LUT[i] == NULL) { + if (pDevEvo->lut.apiHead[apiHead].LUT[i] == NULL) { nvFreeLutSurfacesEvo(pDevEvo); return FALSE; } @@ -372,9 +399,9 @@ NvBool nvAllocLutSurfacesEvo(NVDevEvoPtr pDevEvo) FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { // No palette has been loaded yet, so disable the LUT. - pDevEvo->lut.head[head].disp[dispIndex].waitForPreviousUpdate = FALSE; - pDevEvo->lut.head[head].disp[dispIndex].curBaseLutEnabled = FALSE; - pDevEvo->lut.head[head].disp[dispIndex].curOutputLutEnabled = FALSE; + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].waitForPreviousUpdate = FALSE; + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].curBaseLutEnabled = FALSE; + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].curOutputLutEnabled = FALSE; } } @@ -399,13 +426,13 @@ NvBool nvAllocLutSurfacesEvo(NVDevEvoPtr pDevEvo) void nvFreeLutSurfacesEvo(NVDevEvoPtr pDevEvo) { - NvU32 head, i, dispIndex; + NvU32 head, i, dispIndex, apiHead; NVDispEvoPtr pDispEvo; /* Cancel any queued LUT update timers */ FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - for (head = 0; head < pDevEvo->numHeads; head++) { - nvCancelLutUpdateEvo(pDispEvo, head); + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + nvCancelLutUpdateEvo(pDispEvo, apiHead); } } @@ -414,16 +441,25 @@ void nvFreeLutSurfacesEvo(NVDevEvoPtr pDevEvo) nvRMSyncEvoChannel(pDevEvo, pDevEvo->core, __LINE__); } + /* Clear the current lut surface stored in the hardware head state */ + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + for (head = 0; head < pDevEvo->numHeads; head++) { + pDispEvo->headState[head].lut.pCurrSurface = NULL; + pDispEvo->headState[head].lut.baseLutEnabled = FALSE; + pDispEvo->headState[head].lut.outputLutEnabled = FALSE; + } + } + if (pDevEvo->lut.defaultLut != NULL) { FreeLutSurfaceEvo(pDevEvo->lut.defaultLut); pDevEvo->lut.defaultLut = NULL; } - for (head = 0; head < pDevEvo->numHeads; head++) { - for (i = 0; i < ARRAY_LEN(pDevEvo->lut.head[head].LUT); i++) { - if (pDevEvo->lut.head[head].LUT[i] != NULL) { - FreeLutSurfaceEvo(pDevEvo->lut.head[head].LUT[i]); - pDevEvo->lut.head[head].LUT[i] = NULL; + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + for (i = 0; i < ARRAY_LEN(pDevEvo->lut.apiHead[apiHead].LUT); i++) { + if (pDevEvo->lut.apiHead[apiHead].LUT[i] != NULL) { + FreeLutSurfaceEvo(pDevEvo->lut.apiHead[apiHead].LUT[i]); + pDevEvo->lut.apiHead[apiHead].LUT[i] = NULL; } } } diff --git a/src/nvidia-modeset/src/nvkms-modepool.c b/src/nvidia-modeset/src/nvkms-modepool.c index 136c6f605..0d4a251b7 100644 --- a/src/nvidia-modeset/src/nvkms-modepool.c +++ b/src/nvidia-modeset/src/nvkms-modepool.c @@ -1235,7 +1235,7 @@ static NvBool ValidateModeTimings( NvU32 maxPixelClockKHz = pDpyEvo->maxPixelClockKHz; NvU32 realPixelClock = HzToKHz(pModeTimings->pixelClockHz); - if (pModeTimings->yuv420Mode == NV_YUV420_MODE_SW) { + if (pModeTimings->yuv420Mode != NV_YUV420_MODE_NONE) { realPixelClock /= 2; } @@ -1275,7 +1275,7 @@ static NvBool ValidateModeTimings( if ((overrides & NVKMS_MODE_VALIDATION_NO_EDID_MAX_PCLK_CHECK) == 0) { NvU32 realPixelClock = HzToKHz(pModeTimings->pixelClockHz); - if (pModeTimings->yuv420Mode == NV_YUV420_MODE_SW) { + if (pModeTimings->yuv420Mode != NV_YUV420_MODE_NONE) { realPixelClock /= 2; } @@ -1677,13 +1677,24 @@ static NvBool ValidateMode(NVDpyEvoPtr pDpyEvo, /* Run the raster timings through IMP checking. */ + { + const NVColorFormatInfoRec colorFormats = + nvGetColorFormatInfo(pDpyEvo); + enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace; + enum NvKmsDpyAttributeColorBpcValue colorBpc; - if (!nvConstructHwModeTimingsImpCheckEvo(pDpyEvo->pConnectorEvo, - pTimingsEvo, pParams, pInfoString, - 0 /* head */)) { - LogModeValidationEnd(pDispEvo, pInfoString, - "GPU extended capability check failed"); - goto done; + if (!nvGetDefaultColorSpace(&colorFormats, &colorSpace, &colorBpc) || + !nvConstructHwModeTimingsImpCheckEvo(pDpyEvo->pConnectorEvo, + pTimingsEvo, + colorSpace, + colorBpc, + pParams, + pInfoString, + 0 /* head */)) { + LogModeValidationEnd(pDispEvo, pInfoString, + "GPU extended capability check failed"); + goto done; + } } /* Log modevalidation information about the viewport. */ diff --git a/src/nvidia-modeset/src/nvkms-modeset.c b/src/nvidia-modeset/src/nvkms-modeset.c index b950a8c44..566315e63 100644 --- a/src/nvidia-modeset/src/nvkms-modeset.c +++ b/src/nvidia-modeset/src/nvkms-modeset.c @@ -81,6 +81,7 @@ #include "nvkms-dpy.h" #include "nvkms-rm.h" #include "nvkms-hdmi.h" +#include "nvkms-hw-flip.h" #include "nvkms-flip.h" #include "nvkms-3dvision.h" #include "nvkms-modepool.h" @@ -307,13 +308,17 @@ GetColorSpaceAndColorRange( * Choose current colorSpace and colorRange based on the current mode * timings and the requested color space and range. */ - nvChooseCurrentColorSpaceAndRangeEvo(pProposedHead->timings.pixelDepth, - pProposedHead->timings.yuv420Mode, - pProposedHead->tf, - requestedColorSpace, - requestedColorRange, - &pProposedHead->attributes.colorSpace, - &pProposedHead->attributes.colorRange); + if (!nvChooseCurrentColorSpaceAndRangeEvo(pOneArbitraryDpyEvo, + pProposedHead->timings.yuv420Mode, + pProposedHead->tf, + requestedColorSpace, + requestedColorRange, + &pProposedHead->attributes.colorSpace, + &pProposedHead->attributes.colorBpc, + &pProposedHead->attributes.colorRange)) { + return FALSE; + } + /* * When colorspace is specified in modeset request, it should * match the proposed colorspace. @@ -350,6 +355,9 @@ GetColorSpaceAndColorRange( return FALSE; } + pProposedHead->colorSpaceSpecified = pRequestHead->colorSpaceSpecified; + pProposedHead->colorRangeSpecified = pRequestHead->colorRangeSpecified; + return TRUE; } @@ -369,6 +377,174 @@ NvBool nvGetAllowHeadSurfaceInNvKms(const NVDevEvoRec *pDevEvo, return pDevEvo->allowHeadSurfaceInNvKms; } +static void +InitProposedModeSetHwState(const NVDevEvoRec *pDevEvo, + const struct NvKmsPerOpenDev *pOpenDev, + NVProposedModeSetHwState *pProposed) +{ + NvU32 sd; + NVDispEvoPtr pDispEvo; + + nvkms_memset(pProposed, 0, sizeof(*pProposed)); + + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + NvU32 head; + for (head = 0; head < pDevEvo->numHeads; head++) { + const NVDispHeadStateEvoRec *pHeadState; + NVProposedModeSetHwStateOneHead *pProposedHead = + &pProposed->disp[sd].head[head]; + const NvU32 apiHead = nvHardwareHeadToApiHead(pDevEvo, head); + + /* + * If the previous modeset can not be inherited then initialize the + * proposed modeset state to shutdown all heads. + */ + if (!InheritPreviousModesetState(pDevEvo, pOpenDev)) { + NvU32 layer; + NVFlipEvoHwState *pFlip = &pProposed->sd[sd].head[head].flip; + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + pFlip->dirty.layer[layer] = TRUE; + } + pProposedHead->changed = TRUE; + continue; + } + + /* + * Case of invalid hardware head is handled inside + * nvInitFlipEvoHwState(). + */ + nvInitFlipEvoHwState(pDevEvo, sd, head, + &pProposed->sd[sd].head[head].flip); + + if (!nvHeadIsActive(pDispEvo, head)) { + continue; + } + + pHeadState = &pDispEvo->headState[head]; + + pProposedHead->timings = pHeadState->timings; + pProposedHead->dpyIdList = + pDispEvo->apiHeadState[apiHead].activeDpys; + pProposedHead->pConnectorEvo = pHeadState->pConnectorEvo; + pProposedHead->activeRmId = pHeadState->activeRmId; + pProposedHead->allowFlipLockGroup = pHeadState->allowFlipLockGroup; + pProposedHead->modeValidationParams = + pHeadState->modeValidationParams; + pProposedHead->attributes = + pDispEvo->apiHeadState[apiHead].attributes; + pProposedHead->changed = FALSE; + pProposedHead->hs10bpcHint = + pDispEvo->apiHeadState[apiHead].hs10bpcHint; + pProposedHead->audio = pHeadState->audio; + pProposedHead->infoFrame = + pDispEvo->apiHeadState[apiHead].infoFrame; + pProposedHead->tf = pHeadState->tf; + } + } +} + +static NvBool +AssignProposedModeSetNVFlipEvoHwState( + NVDevEvoRec *pDevEvo, + const struct NvKmsPerOpenDev *pOpenDev, + const NvU32 sd, + const NvU32 head, + const struct NvKmsSetModeRequest *pRequest, + NVFlipEvoHwState *pFlip, + NVProposedModeSetHwStateOneHead *pProposedHead) +{ + const NvU32 apiHead = nvHardwareHeadToApiHead(pDevEvo, head); + const struct NvKmsSetModeOneDispRequest *pRequestDisp = &pRequest->disp[sd]; + const struct NvKmsSetModeOneHeadRequest *pRequestHead = + &pRequestDisp->head[apiHead]; + + /* + * Clear the flipStates of all layers: + * + * The current flipState of main layer may still contain + * old surfaces (e.g., headSurface) that are no longer + * desirable or compatible with the new modeset + * configuration. + * + * Function ApplyProposedModeSetHwStateOneHeadShutDown() clears + * pSdHeadState and disables all layers. It is not possible to + * re-apply the existing flipstates because hardware releases + * sempahores when layers get disabled; this results in a stuck + * channel if you re-apply the existing flipstate which has + * the old semaphore values. + */ + + nvClearFlipEvoHwState(pFlip); + + if (pRequest->commit) { + NvU32 layer; + + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + pFlip->dirty.layer[layer] = TRUE; + } + } + + /*! + * Modeset path should not request pre-syncpt as it will + * not progress because this will update all of the Core and + * Window method state together, and wait for the Core + * completion notifier to signal. If any of the Window + * channels is waiting for a semaphore acquire, then this + * will stall the Core notifier as well since the Core and + * Window channels are interlocked. + */ + if (pDevEvo->supportsSyncpts && + IsPreSyncptSpecified( + pDevEvo, + head, + &pRequest->disp[sd].head[apiHead].flip)) { + return FALSE; + } + + if (!nvUpdateFlipEvoHwState(pOpenDev, + pDevEvo, + sd, + head, + &pRequestHead->flip, + &pProposedHead->timings, + pFlip, + FALSE /* allowVrr */)) { + return FALSE; + } + + /* + * If the modeset is flipping to a depth 30 surface, record this as + * a hint to headSurface, so it can also allocate its surfaces at + * depth 30. + */ + { + const NVSurfaceEvoRec *pSurfaceEvo = + pFlip->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[NVKMS_LEFT]; + + pProposedHead->hs10bpcHint = + (pSurfaceEvo != NULL) && + (pSurfaceEvo->format == NvKmsSurfaceMemoryFormatA2B10G10R10 || + pSurfaceEvo->format == NvKmsSurfaceMemoryFormatX2B10G10R10); + } + + /* + * EVO3 hal simulates USE_CORE_LUT behavior. + * NVDisplay window channel does allow to change the input LUT + * on immediate flips, therefore force disable tearing + * if LUT is specified. + * + * XXX NVKMS TODO: Implement separate input programming for + * base and overlay layers and remove code block. + */ + if ((pRequestHead->lut.input.specified || + pRequestHead->lut.output.specified) && + !pDevEvo->hal->caps.supportsCoreLut) { + pFlip->layer[NVKMS_MAIN_LAYER].tearing = FALSE; + } + + return TRUE; +} + /*! * Assign the NVProposedModeSetHwState structure. * @@ -403,48 +579,7 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, NvU8 allowFlipLockGroup = 0; /* Initialize pProposed with the current hardware configuration. */ - - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - NvU32 head; - for (head = 0; head < pDevEvo->numHeads; head++) { - - const NVDispHeadStateEvoRec *pHeadState; - NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposed->disp[sd].head[head]; - const NvU32 apiHead = nvHardwareHeadToApiHead(head); - - /* - * Case of invalid hardware head is handled inside - * nvInitFlipEvoHwState(). - */ - nvInitFlipEvoHwState(pDevEvo, sd, head, - &pProposed->sd[sd].head[head].flip); - - if (!nvHeadIsActive(pDispEvo, head)) { - continue; - } - - pHeadState = &pDispEvo->headState[head]; - - pProposedHead->timings = pHeadState->timings; - pProposedHead->dpyIdList = - pDispEvo->apiHeadState[apiHead].activeDpys; - pProposedHead->pConnectorEvo = pHeadState->pConnectorEvo; - pProposedHead->activeRmId = pHeadState->activeRmId; - pProposedHead->allowFlipLockGroup = pHeadState->allowFlipLockGroup; - pProposedHead->modeValidationParams = - pHeadState->modeValidationParams; - pProposedHead->attributes = - pDispEvo->apiHeadState[apiHead].attributes; - pProposedHead->changed = FALSE; - pProposedHead->hs10bpcHint = - pDispEvo->apiHeadState[apiHead].hs10bpcHint; - pProposedHead->audio = pHeadState->audio; - pProposedHead->infoFrame = - pDispEvo->apiHeadState[apiHead].infoFrame; - pProposedHead->tf = pHeadState->tf; - } - } + InitProposedModeSetHwState(pDevEvo, pOpenDev, pProposed); /* Update pProposed with the requested changes from the client. */ @@ -454,15 +589,10 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { const struct NvKmsSetModeOneDispRequest *pRequestDisp = &pRequest->disp[sd]; - NvBool shutDownAllHeads = FALSE; NvU32 head; if ((pRequest->requestedDispsBitMask & (1 << sd)) == 0) { - if (!InheritPreviousModesetState(pDevEvo, pOpenDev)) { - shutDownAllHeads = TRUE; - } else { - continue; - } + continue; } NVProposedModeSetHwStateOneDisp *pProposedDisp = @@ -471,65 +601,42 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, pDispEvo = pDevEvo->pDispEvo[sd]; for (head = 0; head < pDevEvo->numHeads; head++) { - + const NvU32 apiHead = nvHardwareHeadToApiHead(pDevEvo, head); const struct NvKmsSetModeOneHeadRequest *pRequestHead = - &pRequestDisp->head[head]; + &pRequestDisp->head[apiHead]; NVProposedModeSetHwStateOneHead *pProposedHead = &pProposedDisp->head[head]; - NVDpyIdList newDpyIdList; - NvBool clearAndContinue = FALSE; + const NVDpyEvoRec *pDpyEvo; - if ((pRequestDisp->requestedHeadsBitMask & (1 << head)) == 0 || - shutDownAllHeads) { - if (!InheritPreviousModesetState(pDevEvo, pOpenDev)) { - /* - * If the modeset owner is changing, implicitly shut down - * other heads not included in requestedHeadsBitMask. - */ - newDpyIdList = nvEmptyDpyIdList(); - } else { - /* - * Otherwise, just leave the head alone so it keeps its - * current configuration. - */ - continue; - } - } else { - newDpyIdList = pRequestHead->dpyIdList; + if ((pRequestDisp->requestedHeadsBitMask & (1 << apiHead)) == 0) { + /* + * Just leave the head alone so it keeps its current + * configuration. + */ + continue; } - /* - * If newDpyIdList is empty or do not find the valid dpy in - * newDpyIdList, then the head should be disabled. - * Clear the pProposedHead, so that no state leaks to the new - * configuration. - */ - if (nvDpyIdListIsEmpty(newDpyIdList)) { - clearAndContinue = TRUE; - } else { - const NVDpyEvoRec *pDpyEvo = - nvGetOneArbitraryDpyEvo(newDpyIdList, pDispEvo); - if (pDpyEvo != NULL) { - pProposedHead->pConnectorEvo = pDpyEvo->pConnectorEvo; - pProposedHead->changed = TRUE; - } else { - clearAndContinue = TRUE; - } - } - - - if (clearAndContinue) { + pDpyEvo = nvGetOneArbitraryDpyEvo(pRequestHead->dpyIdList, pDispEvo); + if (pDpyEvo == NULL) { + /* + * If newDpyIdList is empty or does not find a valid dpy in + * newDpyIdList, then the head should be disabled. + * Clear the pProposedHead, so that no state leaks to the new + * configuration. + */ nvkms_memset(pProposedHead, 0, sizeof(*pProposedHead)); pProposedHead->changed = TRUE; continue; } - pProposedHead->dpyIdList = newDpyIdList; + pProposedHead->changed = TRUE; + pProposedHead->dpyIdList = pRequestHead->dpyIdList; + pProposedHead->pConnectorEvo = pDpyEvo->pConnectorEvo; pProposedHead->activeRmId = nvRmAllocDisplayId(pDispEvo, pProposedHead->dpyIdList); if (pProposedHead->activeRmId == 0x0) { /* XXX Need separate error code? */ - pReply->disp[sd].head[head].status = + pReply->disp[sd].head[apiHead].status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_DPY; ret = FALSE; continue; @@ -537,7 +644,7 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, /* Verify that the requested dpys are valid on this head. */ if ((pProposedHead->pConnectorEvo->validHeadMask & NVBIT(head)) == 0) { - pReply->disp[sd].head[head].status = + pReply->disp[sd].head[apiHead].status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_DPY; ret = FALSE; continue; @@ -552,24 +659,24 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, */ if (!nvGetHwModeTimings(pDispEvo, pRequestHead, &pProposedHead->timings, &pProposedHead->infoFrame.ctrl)) { - pReply->disp[sd].head[head].status = + pReply->disp[sd].head[apiHead].status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_MODE; ret = FALSE; continue; } + + pProposedHead->stereo.mode = + pRequestHead->modeValidationParams.stereoMode; + pProposedHead->stereo.isAegis = pDpyEvo->stereo3DVision.isAegis; pProposedHead->infoFrame.hdTimings = nvEvoIsHDQualityVideoTimings(&pProposedHead->timings); pProposedHead->allowFlipLockGroup = 0; pProposedHead->modeValidationParams = pRequestHead->modeValidationParams; - pProposedHead->allowGsync = pRequestHead->allowGsync; - pProposedHead->allowAdaptiveSync = pRequestHead->allowAdaptiveSync; - pProposedHead->vrrOverrideMinRefreshRate = - pRequestHead->vrrOverrideMinRefreshRate; if (!GetColorSpaceAndColorRange(pDispEvo, pRequestHead, pProposedHead)) { - pReply->disp[sd].head[head].status = + pReply->disp[sd].head[apiHead].status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_MODE; ret = FALSE; continue; @@ -585,20 +692,14 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, NV_KMS_DPY_ATTRIBUTE_DIGITAL_SIGNAL_HDMI_FRL; } - { - NVDpyEvoRec *pDpyEvo = - nvGetOneArbitraryDpyEvo(pProposedHead->dpyIdList, - pDispEvo); + pProposedHead->attributes.dvc = + pDpyEvo->currentAttributes.dvc; - pProposedHead->attributes.dvc = - pDpyEvo->currentAttributes.dvc; - - /* Image sharpening is available when scaling is enabled. */ - pProposedHead->attributes.imageSharpening.available = - nvIsImageSharpeningAvailable(&pProposedHead->timings.viewPort); - pProposedHead->attributes.imageSharpening.value = - pDpyEvo->currentAttributes.imageSharpening.value; - } + /* Image sharpening is available when scaling is enabled. */ + pProposedHead->attributes.imageSharpening.available = + nvIsImageSharpeningAvailable(&pProposedHead->timings.viewPort); + pProposedHead->attributes.imageSharpening.value = + pDpyEvo->currentAttributes.imageSharpening.value; /* * If InheritPreviousModesetState() returns FALSE, it implies that @@ -624,106 +725,23 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, pProposedHead->lut.input.specified = FALSE; } - NVFlipEvoHwState *pFlip = - &pProposed->sd[sd].head[head].flip; - - /* - * Clear the flipStates of all layers: - * - * The current flipState of main layer may still contain - * old surfaces (e.g., headSurface) that are no longer - * desirable or compatible with the new modeset - * configuration. - * - * Function ApplyProposedModeSetHwStateOneHeadShutDown() clears - * pSdHeadState and disables all layers. It is not possible to - * re-apply the existing flipstates because hardware releases - * sempahores when layers get disabled; this results in a stuck - * channel if you re-apply the existing flipstate which has - * the old semaphore values. - */ - - nvClearFlipEvoHwState(pFlip); - - if (pRequest->commit) { - NvU32 layer; - - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - pFlip->dirty.layer[layer] = TRUE; - } - } - - /*! - * Modeset path should not request pre-syncpt as it will - * not progress because this will update all of the Core and - * Window method state together, and wait for the Core - * completion notifier to signal. If any of the Window - * channels is waiting for a semaphore acquire, then this - * will stall the Core notifier as well since the Core and - * Window channels are interlocked. - */ - if (pDevEvo->supportsSyncpts && - IsPreSyncptSpecified( + if (!AssignProposedModeSetNVFlipEvoHwState( pDevEvo, + pOpenDev, + sd, head, - &pRequest->disp[sd].head[head].flip)) { - pReply->disp[sd].head[head].status = + pRequest, + &pProposed->sd[sd].head[head].flip, + pProposedHead)) { + pReply->disp[sd].head[apiHead].status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_FLIP; ret = FALSE; continue; /* next head */ } - if (!nvUpdateFlipEvoHwState(pOpenDev, - pDevEvo, - sd, - head, - &pRequestHead->flip, - pFlip, - FALSE /* allowVrr */)) { - pReply->disp[sd].head[head].status = - NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_FLIP; - ret = FALSE; - continue; /* next head */ - } - - /* - * If the modeset is flipping to a depth 30 surface, record this as - * a hint to headSurface, so it can also allocate its surfaces at - * depth 30. - */ - { - const NVSurfaceEvoRec *pSurfaceEvo = - pFlip->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[NVKMS_LEFT]; - - pProposedHead->hs10bpcHint = - (pSurfaceEvo != NULL) && - (pSurfaceEvo->format == NvKmsSurfaceMemoryFormatA2B10G10R10 || - pSurfaceEvo->format == NvKmsSurfaceMemoryFormatX2B10G10R10); - } - - /* - * EVO3 hal simulates USE_CORE_LUT behavior. - * NVDisplay window channel does allow to change the input LUT - * on immediate flips, therefore force disable tearing - * if LUT is specified. - * - * XXX NVKMS TODO: Implement separate input programming for - * base and overlay layers and remove code block. - */ - if ((pRequestHead->lut.input.specified || - pRequestHead->lut.output.specified) && - !pDevEvo->hal->caps.supportsCoreLut) { - pFlip->layer[NVKMS_MAIN_LAYER].tearing = FALSE; - } /* Construct audio state */ - { - NVDpyEvoRec *pDpyEvo = - nvGetOneArbitraryDpyEvo(pProposedHead->dpyIdList, - pDispEvo); - - nvHdmiDpConstructHeadAudioState(pProposedHead->activeRmId, - pDpyEvo, &pProposedHead->audio); - } + nvHdmiDpConstructHeadAudioState(pProposedHead->activeRmId, + pDpyEvo, &pProposedHead->audio); } /* head */ } /* pDispEvo */ @@ -740,14 +758,14 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, } for (head = 0; head < pDevEvo->numHeads; head++) { - + const NvU32 apiHead = nvHardwareHeadToApiHead(pDevEvo, head); const struct NvKmsSetModeOneHeadRequest *pRequestHead = - &pRequest->disp[sd].head[head]; + &pRequest->disp[sd].head[apiHead]; NVProposedModeSetHwStateOneHead *pProposedHead = &pProposed->disp[sd].head[head]; if ((pRequest->disp[sd].requestedHeadsBitMask & - NVBIT(head)) == 0) { + NVBIT(apiHead)) == 0) { continue; } @@ -757,8 +775,7 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, } } - if (ret) { - } else { + if (!ret) { ClearProposedModeSetHwState(pDevEvo, pProposed, FALSE /* committed */); } @@ -828,6 +845,9 @@ ValidateProposedModeSetHwStateOneDispImp(NVDispEvoPtr pDispEvo, timingsParams[head].pConnectorEvo = pProposedHead->pConnectorEvo; timingsParams[head].activeRmId = pProposedHead->activeRmId; + timingsParams[head].pixelDepth = + nvEvoColorSpaceBpcToPixelDepth(pProposedHead->attributes.colorSpace, + pProposedHead->attributes.colorBpc); timingsParams[head].pTimings = &pProposedHead->timings; timingsParams[head].pUsage = &pProposedHead->timings.viewPort.guaranteedUsage; @@ -903,11 +923,50 @@ static NvBool SkipDisplayPortBandwidthCheck( NVKMS_MODE_VALIDATION_NO_DISPLAYPORT_BANDWIDTH_CHECK) != 0; } -static NvBool DowngradeDpPixelDepth( +static NvBool DowngradeColorSpaceAndBpcOneHead( + const NVDispEvoRec *pDispEvo, + NVProposedModeSetHwStateOneHead *pProposedHead) +{ + enum NvKmsDpyAttributeColorRangeValue colorRange = + pProposedHead->attributes.colorRange; + enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace = + pProposedHead->attributes.colorSpace; + enum NvKmsDpyAttributeColorBpcValue colorBpc = + pProposedHead->attributes.colorBpc; + NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pProposedHead->dpyIdList, + pDispEvo); + const NVColorFormatInfoRec supportedColorFormats = + nvGetColorFormatInfo(pDpyEvo); + + if (!nvDowngradeColorSpaceAndBpc(&supportedColorFormats, + &colorSpace, &colorBpc, &colorRange)) { + return FALSE; + } + + if (pProposedHead->colorRangeSpecified && + (colorRange != pProposedHead->attributes.colorRange)) { + return FALSE; + } + + if (pProposedHead->colorSpaceSpecified && + (colorSpace != pProposedHead->attributes.colorSpace)) { + return FALSE; + } + + pProposedHead->attributes.colorRange = colorRange; + pProposedHead->attributes.colorSpace = colorSpace; + pProposedHead->attributes.colorBpc = colorBpc; + + return TRUE; +} + +static NvBool DowngradeColorSpaceAndBpcOneDisp( NVDispEvoPtr pDispEvo, NVProposedModeSetHwStateOneDisp *pProposedDisp, const NVConnectorEvoRec *pConnectorEvo) { + NvBool ret = FALSE; NvU32 head; /* @@ -918,22 +977,19 @@ static NvBool DowngradeDpPixelDepth( for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { NVProposedModeSetHwStateOneHead *pProposedHead = &pProposedDisp->head[head]; - NVHwModeTimingsEvoPtr pTimings = &pProposedHead->timings; - if (SkipDisplayPortBandwidthCheck(pProposedHead)) { + if (!pProposedHead->changed || + SkipDisplayPortBandwidthCheck(pProposedHead)) { continue; } if ((pProposedHead->pConnectorEvo == pConnectorEvo) && - nvDowngradeHwModeTimingsDpPixelDepthEvo( - pTimings, - pProposedHead->attributes.colorSpace, - pProposedHead->attributes.colorRange)) { - return TRUE; + DowngradeColorSpaceAndBpcOneHead(pDispEvo, pProposedHead)) { + ret = TRUE; } } - return FALSE; + return ret; } /*! @@ -975,13 +1031,23 @@ tryAgain: pProposedHead->activeRmId, pProposedHead->dpyIdList, pProposedHead->attributes.colorSpace, + pProposedHead->attributes.colorBpc, &pProposedHead->modeValidationParams, pTimings); - if (!bResult) { - if (DowngradeDpPixelDepth(pDispEvo, - pProposedDisp, - pProposedHead->pConnectorEvo)) { + if (!bResult && pProposedHead->changed) { + + /* + * First, try to downgrade the pixel depth for this current head. + * If the pixel depth for this current head is not possible to + * downgrade further then try to downgrade the pixel depth of other + * changed heads which are sharing same connector and dp-bandwidth. + */ + + if (DowngradeColorSpaceAndBpcOneHead(pDispEvo, pProposedHead) || + DowngradeColorSpaceAndBpcOneDisp(pDispEvo, + pProposedDisp, + pProposedHead->pConnectorEvo)) { bTryAgain = TRUE; } @@ -990,6 +1056,14 @@ tryAgain: * This proposed mode-set is not possible on this DP link, so fail. */ + break; + } else if (!bResult) { + + /* + * The Dp link bandwidth check fails for an unchanged head -- + * This proposed mode-set is not possible on this DP link, so fail. + */ + break; } } @@ -1017,6 +1091,7 @@ tryAgain: pProposedHead->activeRmId, pProposedHead->dpyIdList, pProposedHead->attributes.colorSpace, + pProposedHead->attributes.colorBpc, &pProposedHead->timings); if (pProposedHead->pDpLibModesetState == NULL) { return FALSE; @@ -1032,28 +1107,28 @@ static void VBlankCallbackDeferredWork(void *dataPtr, NvU32 data32) NVVBlankCallbackPtr pVBlankCallbackTmp = NULL; NVVBlankCallbackPtr pVBlankCallback = NULL; NVDispEvoPtr pDispEvo = dataPtr; - NvU32 head = data32; + NvU32 apiHead = data32; - if (!nvHeadIsActive(pDispEvo, head)) { + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { return; } nvListForEachEntry_safe(pVBlankCallback, pVBlankCallbackTmp, - &pDispEvo->headState[head].vblankCallbackList, + &pDispEvo->apiHeadState[apiHead].vblankCallbackList, vblankCallbackListEntry) { - pVBlankCallback->pCallback(pDispEvo, head, pVBlankCallback); + pVBlankCallback->pCallback(pDispEvo, pVBlankCallback); } } static void VBlankCallback(void *pParam1, void *pParam2) { - const NvU32 head = (NvU32)(NvUPtr)pParam2; + const NvU32 apiHead = (NvU32)(NvUPtr)pParam2; (void) nvkms_alloc_timer_with_ref_ptr( VBlankCallbackDeferredWork, pParam1, /* ref_ptr to pDispEvo */ - head, /* dataU32 */ + apiHead, /* dataU32 */ 0); /* timeout: schedule the work immediately */ } @@ -1128,7 +1203,7 @@ ValidateProposedModeSetHwStateOneDisp( * Check ViewPortIn dimensions and ensure valid h/vTaps can be assigned. */ for (head = 0; head < pDevEvo->numHeads; head++) { - + const NvU32 apiHead = nvHardwareHeadToApiHead(pDevEvo, head); /* XXX assume the gpus have equal capabilities */ const NVEvoScalerCaps *pScalerCaps = &pDevEvo->gpus[0].capabilities.head[head].scalerCaps; @@ -1136,7 +1211,7 @@ ValidateProposedModeSetHwStateOneDisp( if (!nvValidateHwModeTimingsViewPort(pDevEvo, pScalerCaps, pTimings, &dummyInfoString)) { - pReplyDisp->head[head].status = + pReplyDisp->head[apiHead].status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_MODE; return FALSE; } @@ -1168,7 +1243,7 @@ ValidateProposedModeSetHwStateOneDisp( } nvChooseDitheringEvo(pDpyEvo->pConnectorEvo, - pProposedHead->timings.pixelDepth, + pProposedHead->attributes.colorBpc, &pDpyEvo->requestedDithering, &pProposedHead->attributes.dithering); } @@ -1207,6 +1282,8 @@ ValidateProposedFlipHwStateOneSubDev( NvU32 head; for (head = 0; head < pDevEvo->numHeads; head++) { + const NvU32 apiHead = nvHardwareHeadToApiHead(pDevEvo, head); + if (!pProposedDisp->head[head].changed || nvDpyIdListIsEmpty(pProposedDisp->head[head].dpyIdList)) { continue; @@ -1222,7 +1299,7 @@ ValidateProposedFlipHwStateOneSubDev( head, &pProposedDisp->head[head].timings, &pProposedSd->head[head].flip)) { - pReplyDisp->head[head].status = + pReplyDisp->head[apiHead].status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_FLIP; return FALSE; } @@ -1475,13 +1552,18 @@ IsProposedModeSetHwStateOneHeadIncompatible( return isIncompatible; } -static void DisableActiveCoreRGSyncObjects(NVDevEvoPtr pDevEvo, - NVDispHeadStateEvoPtr pHeadState, - NvU32 head, +static void DisableActiveCoreRGSyncObjects(NVDispEvoRec *pDispEvo, + const NvU32 apiHead, NVEvoUpdateState *pUpdateState) { - for (int i = 0; i < pHeadState->numVblankSyncObjectsCreated; i++) { - if (pHeadState->vblankSyncObjects[i].enabled) { + NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; + + for (int i = 0; i < pApiHeadState->numVblankSyncObjectsCreated; i++) { + if (pApiHeadState->vblankSyncObjects[i].enabled) { + NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); + nvAssert(head != NV_INVALID_HEAD); + /* hCtxDma of 0 indicates Disable. */ pDevEvo->hal->ConfigureVblankSyncObject( pDevEvo, @@ -1490,7 +1572,7 @@ static void DisableActiveCoreRGSyncObjects(NVDevEvoPtr pDevEvo, i, 0, /* hCtxDma */ pUpdateState); - pHeadState->vblankSyncObjects[i].enabled = FALSE; + pApiHeadState->vblankSyncObjects[i].enabled = FALSE; } } } @@ -1517,7 +1599,7 @@ ApplyProposedModeSetHwStateOneHeadShutDown( NVDispHeadStateEvoPtr pHeadState; NVDpyEvoPtr pDpyEvo; const NvU32 sd = pDispEvo->displayOwner; - NvU32 apiHead = nvHardwareHeadToApiHead(head); + NvU32 apiHead = nvHardwareHeadToApiHead(pDevEvo, head); NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; /* @@ -1543,6 +1625,8 @@ ApplyProposedModeSetHwStateOneHeadShutDown( pHeadState = &pDispEvo->headState[head]; pDpyEvo = nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); + nvCancelSDRTransitionTimer(pApiHeadState); + /* * Identify and disable any active core RG sync objects. * @@ -1552,15 +1636,21 @@ ApplyProposedModeSetHwStateOneHeadShutDown( * ApplyProposedModeSetHwStateOneHeadPreUpdate(), if the given head will be * active after the modeset. */ - DisableActiveCoreRGSyncObjects(pDevEvo, pHeadState, head, + DisableActiveCoreRGSyncObjects(pDispEvo, apiHead, &pWorkArea->modesetUpdateState.updateState); + if (pApiHeadState->rmVBlankCallbackHandle != 0) { + nvRmRemoveVBlankCallback(pDispEvo, + pApiHeadState->rmVBlankCallbackHandle); + pApiHeadState->rmVBlankCallbackHandle = 0; + } + nvDisable3DVisionAegis(pDpyEvo); nvHdmiDpEnableDisableAudio(pDispEvo, head, FALSE /* enable */); /* Cancel any pending LUT updates. */ - nvCancelLutUpdateEvo(pDispEvo, head); + nvCancelLutUpdateEvo(pDispEvo, apiHead); nvEvoDetachConnector(pHeadState->pConnectorEvo, head, &pWorkArea->modesetUpdateState); @@ -1572,6 +1662,7 @@ ApplyProposedModeSetHwStateOneHeadShutDown( pWorkArea->sd[pDispEvo->displayOwner].changedDpyIdList); pApiHeadState->activeDpys = nvEmptyDpyIdList(); nvkms_memset(&pApiHeadState->timings, 0, sizeof(pApiHeadState->timings)); + nvkms_memset(&pApiHeadState->stereo, 0, sizeof(pApiHeadState->stereo)); pHeadState->pConnectorEvo = NULL; pHeadState->bypassComposition = FALSE; @@ -1611,6 +1702,9 @@ ApplyProposedModeSetHwStateOneDispFlip( for (head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { const NVProposedModeSetHwStateOneHead *pProposedHead = &pProposedDisp->head[head]; + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pProposedHead->dpyIdList, pDispEvo); + NvU32 apiHead = nvHardwareHeadToApiHead(pDevEvo, head); const NvU32 sd = pDispEvo->displayOwner; /* @@ -1626,33 +1720,44 @@ ApplyProposedModeSetHwStateOneDispFlip( continue; } + nvAssert(pDpyEvo != NULL); + nvSetUsageBoundsEvo(pDevEvo, sd, head, &pProposed->sd[sd].head[head].flip.usage, pUpdateState); nvFlipEvoOneHead(pDevEvo, sd, head, + &pDpyEvo->parsedEdid.info.hdr_static_metadata_info, &pProposed->sd[sd].head[head].flip, FALSE /* allowFlipLock */, pUpdateState); + + pDispEvo->apiHeadState[apiHead].viewPortPointIn = + pProposed->sd[sd].head[head].flip.viewPortPointIn; } } -static void ReenableActiveCoreRGSyncObjects(NVDevEvoPtr pDevEvo, - NVDispHeadStateEvoPtr pHeadState, - NvU32 head, +static void ReEnableActiveCoreRGSyncObjects(NVDispEvoRec *pDispEvo, + const NvU32 apiHead, NVEvoUpdateState *pUpdateState) { - for (int i = 0; i < pHeadState->numVblankSyncObjectsCreated; i++) { - if (pHeadState->vblankSyncObjects[i].inUse) { + NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); + NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; + + nvAssert(head != NV_INVALID_HEAD); + + for (int i = 0; i < pApiHeadState->numVblankSyncObjectsCreated; i++) { + if (pApiHeadState->vblankSyncObjects[i].inUse) { pDevEvo->hal->ConfigureVblankSyncObject( pDevEvo, - pHeadState->timings.rasterBlankStart.y, + pDispEvo->headState[head].timings.rasterBlankStart.y, head, i, - pHeadState->vblankSyncObjects[i].evoSyncpt.hCtxDma, + pApiHeadState->vblankSyncObjects[i].evoSyncpt.hCtxDma, pUpdateState); - pHeadState->vblankSyncObjects[i].enabled = TRUE; + pApiHeadState->vblankSyncObjects[i].enabled = TRUE; } } } @@ -1687,7 +1792,7 @@ ApplyProposedModeSetHwStateOneHeadPreUpdate( NVDispHeadStateEvoPtr pHeadState; NVDpyEvoPtr pDpyEvo = nvGetOneArbitraryDpyEvo(pProposedHead->dpyIdList, pDispEvo); - NvU32 apiHead = nvHardwareHeadToApiHead(head); + NvU32 apiHead = nvHardwareHeadToApiHead(pDispEvo->pDevEvo, head); NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; /* @@ -1732,6 +1837,7 @@ ApplyProposedModeSetHwStateOneHeadPreUpdate( */ pApiHeadState->activeDpys = pProposedHead->dpyIdList; pApiHeadState->timings = pProposedHead->timings; + pApiHeadState->stereo = pProposedHead->stereo; pWorkArea->sd[pDispEvo->displayOwner].changedDpyIdList = nvAddDpyIdListToDpyIdList( pApiHeadState->activeDpys, @@ -1741,19 +1847,23 @@ ApplyProposedModeSetHwStateOneHeadPreUpdate( pHeadState->pConnectorEvo = pProposedHead->pConnectorEvo; pHeadState->timings = pProposedHead->timings; + pHeadState->pixelDepth = + nvEvoColorSpaceBpcToPixelDepth(pProposedHead->attributes.colorSpace, + pProposedHead->attributes.colorBpc); + pHeadState->audio = pProposedHead->audio; pApiHeadState->infoFrame = pProposedHead->infoFrame; AssignProposedUsageOneHead(pDispEvo->pDevEvo, pProposed, head); - nvSendHwModeTimingsToAegisEvo(pDispEvo, head); + nvSendHwModeTimingsToAegisEvo(pDispEvo, apiHead); /* Set LUT settings */ - nvEvoSetLut(pDispEvo, head, FALSE /* kickoff */, &pProposedHead->lut); + nvEvoSetLut(pDispEvo, apiHead, FALSE /* kickoff */, &pProposedHead->lut); /* Update current LUT to hardware */ - nvEvoUpdateCurrentPalette(pDispEvo, head, FALSE /* kickoff */); + nvEvoSetLUTContextDma(pDispEvo, head, updateState); nvEvoSetTimings(pDispEvo, head, updateState); @@ -1796,10 +1906,17 @@ ApplyProposedModeSetHwStateOneHeadPreUpdate( * Re-enable any active sync objects, configuring them in accordance with * the new timings. */ - ReenableActiveCoreRGSyncObjects(pDispEvo->pDevEvo, pHeadState, head, - updateState); + ReEnableActiveCoreRGSyncObjects(pDispEvo, apiHead, updateState); + + nvAssert(pApiHeadState->rmVBlankCallbackHandle == 0); + if (!nvListIsEmpty(&pApiHeadState->vblankCallbackList)) { + pApiHeadState->rmVBlankCallbackHandle = + nvRmAddVBlankCallback(pDispEvo, head, VBlankCallback, + (void *)(NvUPtr)apiHead); + } pApiHeadState->attributes = pProposedHead->attributes; + pApiHeadState->tf = pProposedHead->tf; } @@ -1822,7 +1939,7 @@ ApplyProposedModeSetHwStateOneHeadPostUpdate(NVDispEvoPtr pDispEvo, { NVDispHeadStateEvoRec *pHeadState; NVDpyEvoRec *pDpyEvo; - NvU32 apiHead = nvHardwareHeadToApiHead(head); + NvU32 apiHead = nvHardwareHeadToApiHead(pDispEvo->pDevEvo, head); NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; /* @@ -1854,7 +1971,7 @@ ApplyProposedModeSetHwStateOneHeadPostUpdate(NVDispEvoPtr pDispEvo, nvUpdateInfoFrames(pDpyEvo); /* Perform 3D vision authentication */ - nv3DVisionAuthenticationEvo(pDispEvo, head); + nv3DVisionAuthenticationEvo(pDispEvo, apiHead); nvHdmiDpEnableDisableAudio(pDispEvo, head, TRUE /* enable */); } @@ -2261,14 +2378,14 @@ InitializeReply(const NVDevEvoRec *pDevEvo, FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - NvU32 head; + NvU32 apiHead; pReply->disp[dispIndex].status = NVKMS_SET_MODE_ONE_DISP_STATUS_SUCCESS; - for (head = 0; head < pDevEvo->numHeads; head++) { + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { - pReply->disp[dispIndex].head[head].status = + pReply->disp[dispIndex].head[apiHead].status = NVKMS_SET_MODE_ONE_HEAD_STATUS_SUCCESS; } } @@ -2299,7 +2416,7 @@ ValidateRequest(const NVDevEvoRec *pDevEvo, const struct NvKmsSetModeRequest *pRequest, struct NvKmsSetModeReply *pReply) { - NvU32 dispIndex, head; + NvU32 dispIndex, apiHead; NvBool ret = TRUE; const struct NvKmsModesetPermissions *pPermissions = @@ -2339,13 +2456,13 @@ ValidateRequest(const NVDevEvoRec *pDevEvo, ret = FALSE; } - for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { + for (apiHead = 0; apiHead < NVKMS_MAX_HEADS_PER_DISP; apiHead++) { - if ((pRequestDisp->requestedHeadsBitMask & (1 << head)) == 0) { + if ((pRequestDisp->requestedHeadsBitMask & (1 << apiHead)) == 0) { continue; } - if (head >= pDevEvo->numHeads) { + if (apiHead >= pDevEvo->numApiHeads) { pReply->disp[dispIndex].status = NVKMS_SET_MODE_ONE_DISP_STATUS_INVALID_REQUESTED_HEADS_BITMASK; ret = FALSE; @@ -2353,17 +2470,17 @@ ValidateRequest(const NVDevEvoRec *pDevEvo, } const NVDpyIdList permDpyIdList = - pPermissions->disp[dispIndex].head[head].dpyIdList; + pPermissions->disp[dispIndex].head[apiHead].dpyIdList; const struct NvKmsSetModeOneHeadRequest *pRequestHead = - &pRequestDisp->head[head]; + &pRequestDisp->head[apiHead]; /* * Does the client have permission to touch this head at * all? */ if (pRequest->commit && nvDpyIdListIsEmpty(permDpyIdList)) { - pReply->disp[dispIndex].head[head].status = + pReply->disp[dispIndex].head[apiHead].status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_PERMISSIONS; ret = FALSE; continue; @@ -2384,7 +2501,7 @@ ValidateRequest(const NVDevEvoRec *pDevEvo, if (pRequest->commit && !nvDpyIdListIsASubSetofDpyIdList(pRequestHead->dpyIdList, permDpyIdList)) { - pReply->disp[dispIndex].head[head].status = + pReply->disp[dispIndex].head[apiHead].status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_PERMISSIONS; ret = FALSE; continue; @@ -2396,14 +2513,14 @@ ValidateRequest(const NVDevEvoRec *pDevEvo, if (!nvDpyIdListIsASubSetofDpyIdList( pRequestHead->dpyIdList, pDevEvo->pDispEvo[dispIndex]->validDisplays)) { - pReply->disp[dispIndex].head[head].status = + pReply->disp[dispIndex].head[apiHead].status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_DPY; ret = FALSE; continue; } if (!nvValidateSetLutCommonParams(pDevEvo, &pRequestHead->lut)) { - pReply->disp[dispIndex].head[head].status = + pReply->disp[dispIndex].head[apiHead].status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_LUT; ret = FALSE; continue; @@ -2469,24 +2586,21 @@ AssignReplySuccess(const NVDevEvoRec *pDevEvo, } for (head = 0; head < pDevEvo->numHeads; head++) { - const NvU32 apiHead = nvHardwareHeadToApiHead(head); + const NvU32 apiHead = nvHardwareHeadToApiHead(pDevEvo, head); const struct NvKmsSetModeOneHeadRequest *pRequestHead = - &pRequestDisp->head[head]; + &pRequestDisp->head[apiHead]; struct NvKmsSetModeOneHeadReply *pReplyHead = - &pReply->disp[dispIndex].head[head]; + &pReply->disp[dispIndex].head[apiHead]; - if ((pRequestDisp->requestedHeadsBitMask & (1 << head)) == 0) { + if ((pRequestDisp->requestedHeadsBitMask & (1 << apiHead)) == 0) { continue; } pReplyHead->status = NVKMS_SET_MODE_ONE_HEAD_STATUS_SUCCESS; - if (nvDpyIdListIsEmpty(pRequestHead->dpyIdList)) { - pReplyHead->activeRmId = 0; - } else { + if (!nvDpyIdListIsEmpty(pRequestHead->dpyIdList)) { const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; - pReplyHead->activeRmId = pHeadState->activeRmId; pReplyHead->possibleUsage = pHeadState->timings.viewPort.possibleUsage; pReplyHead->guaranteedUsage = pHeadState->timings.viewPort.guaranteedUsage; pReplyHead->usingHeadSurface = @@ -2494,6 +2608,9 @@ AssignReplySuccess(const NVDevEvoRec *pDevEvo, pReplyHead->vrrEnabled = (pDispEvo->headState[head].timings.vrr.type != NVKMS_DPY_VRR_TYPE_NONE); + pReplyHead->hwHead = head; + } else { + pReplyHead->hwHead = NV_INVALID_HEAD; } FillPostSyncptReplyForModeset( pDevEvo, @@ -2802,7 +2919,7 @@ NvBool nvSetDispModeEvo(NVDevEvoPtr pDevEvo, bypassComposition); } - nvEnableVrr(pDevEvo, pRequest); + nvEnableVrr(pDevEvo); /* * Cache whether HS in NVKMS is allowed, so we can make consistent @@ -2878,7 +2995,7 @@ done: * Register a callback to activate when vblank is reached on a given head. * * \param[in,out] pDispEvo The display engine to register the callback on. - * \param[in] head The head to register the callback on. + * \param[in] apiHead The api head to register the callback on. * \param[in] pCallback The function to call when vblank is reached on the * provided pDispEvo+head combination. * \param[in] pUserData A pointer to caller-provided custom data. @@ -2886,35 +3003,6 @@ done: * \return Returns a pointer to a NVVBlankCallbackRec structure if the * registration was successful. Otherwise, return NULL. */ -NVVBlankCallbackPtr nvRegisterVBlankCallback(NVDispEvoPtr pDispEvo, - NvU32 head, - NVVBlankCallbackProc pCallback, - void *pUserData) -{ - NVVBlankCallbackPtr pVBlankCallback = NULL; - - pVBlankCallback = nvCalloc(1, sizeof(*pVBlankCallback)); - if (pVBlankCallback == NULL) { - return NULL; - } - - pVBlankCallback->pCallback = pCallback; - pVBlankCallback->pUserData = pUserData; - - nvListAppend(&pVBlankCallback->vblankCallbackListEntry, - &pDispEvo->headState[head].vblankCallbackList); - - // If this is the first entry in the list, register the vblank callback - if (pDispEvo->headState[head].rmVBlankCallbackHandle == 0) { - - pDispEvo->headState[head].rmVBlankCallbackHandle = - nvRmAddVBlankCallback(pDispEvo, - head, - VBlankCallback); - } - return pVBlankCallback; -} - NVVBlankCallbackPtr nvApiHeadRegisterVBlankCallback(NVDispEvoPtr pDispEvo, const NvU32 apiHead, @@ -2928,56 +3016,75 @@ nvApiHeadRegisterVBlankCallback(NVDispEvoPtr pDispEvo, * primary hardware head. */ const NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); - if (head == NV_INVALID_HEAD) { + NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; + NVVBlankCallbackPtr pVBlankCallback = NULL; + + pVBlankCallback = nvCalloc(1, sizeof(*pVBlankCallback)); + if (pVBlankCallback == NULL) { return NULL; } - return nvRegisterVBlankCallback(pDispEvo, head, pCallback, pUserData); + + pVBlankCallback->pCallback = pCallback; + pVBlankCallback->pUserData = pUserData; + pVBlankCallback->apiHead = apiHead; + + nvListAppend(&pVBlankCallback->vblankCallbackListEntry, + &pApiHeadState->vblankCallbackList); + + nvAssert((head != NV_INVALID_HEAD) || + (pApiHeadState->rmVBlankCallbackHandle == 0)); + + // If this is the first entry in the list, register the vblank callback + if ((head != NV_INVALID_HEAD) && + (pApiHeadState->rmVBlankCallbackHandle == 0)) { + pApiHeadState->rmVBlankCallbackHandle = + nvRmAddVBlankCallback(pDispEvo, head, VBlankCallback, + (void *)(NvUPtr)apiHead); + } + + return pVBlankCallback; } /*! - * Un-register a vblank callback for a given head. + * Un-register a vblank callback for a given api head. * * \param[in,out] pDispEvo The display engine to register the callback on. - * \param[in] head The head to register the callback on. * \param[in] pCallback A pointer to the NVVBlankCallbackRec to un-register. * */ -void nvUnregisterVBlankCallback(NVDispEvoPtr pDispEvo, - NvU32 head, - NVVBlankCallbackPtr pCallback) +void nvApiHeadUnregisterVBlankCallback(NVDispEvoPtr pDispEvo, + NVVBlankCallbackPtr pCallback) { + const NvU32 apiHead = pCallback->apiHead; + NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; + const NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); + nvListDel(&pCallback->vblankCallbackListEntry); nvFree(pCallback); + nvAssert((head != NV_INVALID_HEAD) || + (pApiHeadState->rmVBlankCallbackHandle == 0)); + // If there are no more callbacks, disable the RM-level callback - if (nvListIsEmpty(&pDispEvo->headState[head].vblankCallbackList)) { + if (nvListIsEmpty(&pApiHeadState->vblankCallbackList) && + (head != NV_INVALID_HEAD) && + (pApiHeadState->rmVBlankCallbackHandle != 0)) { nvRmRemoveVBlankCallback(pDispEvo, - pDispEvo->headState[head].rmVBlankCallbackHandle); - - pDispEvo->headState[head].rmVBlankCallbackHandle = 0; + pApiHeadState->rmVBlankCallbackHandle); + pApiHeadState->rmVBlankCallbackHandle = 0; } } -void nvApiHeadUnregisterVBlankCallback(NVDispEvoPtr pDispEvo, - const NvU32 apiHead, - NVVBlankCallbackPtr pCallback) -{ - const NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); - if (head == NV_INVALID_HEAD) { - return; - } - nvUnregisterVBlankCallback(pDispEvo, head, pCallback); -} - /*! - * Perform a modeset that disables some or all heads. + * Perform a modeset that disables some or all api heads. * * \param[in] pDevEvo The device to shut down. * \param[in] pTestFunc The pointer to test function, identifying heads * targeted to shut down. If NULL then shut down * all heads. */ -void nvShutDownHeads(NVDevEvoPtr pDevEvo, NVShutDownHeadsTestFunc pTestFunc) +void nvShutDownApiHeads(NVDevEvoPtr pDevEvo, + NVShutDownApiHeadsTestFunc pTestFunc) { if (pDevEvo->displayHandle != 0) { struct NvKmsSetModeParams *params = @@ -2992,20 +3099,20 @@ void nvShutDownHeads(NVDevEvoPtr pDevEvo, NVShutDownHeadsTestFunc pTestFunc) req = ¶ms->request; FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - NvU32 head; + NvU32 apiHead; req->requestedDispsBitMask |= NVBIT(dispIndex); - for (head = 0; head < pDevEvo->numHeads; head++) { + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { /* * XXX pTestFunc isn't honored by nvSetDispModeEvo()'s * InheritPreviousModesetState() logic. */ - if (pTestFunc && !pTestFunc(pDispEvo, head)) { + if (pTestFunc && !pTestFunc(pDispEvo, apiHead)) { continue; } dirty = TRUE; - req->disp[dispIndex].requestedHeadsBitMask |= NVBIT(head); + req->disp[dispIndex].requestedHeadsBitMask |= NVBIT(apiHead); } } @@ -3029,7 +3136,7 @@ void nvShutDownHeads(NVDevEvoPtr pDevEvo, NVShutDownHeadsTestFunc pTestFunc) if (pDevEvo->coreInitMethodsPending) { FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { req->disp[dispIndex].requestedHeadsBitMask |= - NVBIT(pDevEvo->numHeads) - 1; + NVBIT(pDevEvo->numApiHeads) - 1; } } @@ -3046,10 +3153,11 @@ void nvShutDownHeads(NVDevEvoPtr pDevEvo, NVShutDownHeadsTestFunc pTestFunc) } } -NvU32 -nvApiHeadAddRgLine1Callback(const NVDispEvoRec *pDispEvo, +NVRgLine1CallbackPtr +nvApiHeadAddRgLine1Callback(NVDispEvoRec *pDispEvo, const NvU32 apiHead, - NV0092_REGISTER_RG_LINE_CALLBACK_FN pCallback) + NVRgLine1CallbackProc pCallbackProc, + void *pUserData) { /* * All the hardware heads mapped on the input api head should be @@ -3061,5 +3169,23 @@ nvApiHeadAddRgLine1Callback(const NVDispEvoRec *pDispEvo, if (head == NV_INVALID_HEAD) { return FALSE; } - return nvRmAddRgLine1Callback(pDispEvo, head, pCallback); + return nvRmAddRgLine1Callback(pDispEvo, head, pCallbackProc, pUserData); +} + + +void nvApiHeadGetScanLine(const NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + NvU16 *pScanLine, + NvBool *pInBlankingPeriod) +{ + /* + * All the hardware heads mapped on the input api head should be + * rasterlocked; therefore it is sufficient to get scanline only for the + * primary hardware head. + */ + const NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); + + nvAssert(head != NV_INVALID_HEAD); + pDispEvo->pDevEvo->hal->GetScanLine(pDispEvo, head, pScanLine, + pInBlankingPeriod); } diff --git a/src/nvidia-modeset/src/nvkms-rm.c b/src/nvidia-modeset/src/nvkms-rm.c index 90ee5ce6e..4f0a498e0 100644 --- a/src/nvidia-modeset/src/nvkms-rm.c +++ b/src/nvidia-modeset/src/nvkms-rm.c @@ -88,6 +88,8 @@ #include "displayport/dpcd.h" +#define NVKMS_SYNCPT_ID_INVALID (0xFFFFFFFF) + static NvU32 GetLegacyConnectorType(NVDispEvoPtr pDispEvo, NVDpyId dpyId); static void RmFreeEvoChannel(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel); @@ -276,19 +278,16 @@ static NvBool QueryGpuCapabilities(NVDevEvoPtr pDevEvo) static void FreeDisplay(NVDispEvoPtr pDispEvo) { - NvU32 head; - if (pDispEvo == NULL) { return; } - for (head = 0; head < ARRAY_LEN(pDispEvo->pSwapGroup); head++) { #if defined(DEBUG) - const NvU32 apiHead = nvHardwareHeadToApiHead(head); + for (NvU32 apiHead = 0; + apiHead < ARRAY_LEN(pDispEvo->pSwapGroup); apiHead++) { nvAssert(pDispEvo->pSwapGroup[apiHead] == NULL); -#endif - nvAssert(nvListIsEmpty(&pDispEvo->headState[head].vblankCallbackList)); } +#endif nvAssert(nvListIsEmpty(&pDispEvo->dpyList)); @@ -300,7 +299,6 @@ static void FreeDisplay(NVDispEvoPtr pDispEvo) static inline NVDispEvoPtr AllocDisplay(NVDevEvoPtr pDevEvo) { - NvU32 head; NVDispEvoPtr pDispEvo = nvCalloc(1, sizeof(NVDispEvoRec)); if (pDispEvo == NULL) { @@ -316,10 +314,6 @@ static inline NVDispEvoPtr AllocDisplay(NVDevEvoPtr pDevEvo) pDispEvo->framelock.clients = nvEmptyDpyIdList(); pDispEvo->framelock.currentServerHead = NV_INVALID_HEAD; - for (head = 0; head < ARRAY_LEN(pDispEvo->headState); head++) { - nvListInit(&pDispEvo->headState[head].vblankCallbackList); - } - pDispEvo->ref_ptr = nvkms_alloc_ref_ptr(pDispEvo); if (!pDispEvo->ref_ptr) { goto fail; @@ -737,32 +731,6 @@ static NvBool AllocConnector( pConnectorEvo->dfpInfo = GetDfpInfo(pConnectorEvo); - /* - * Change-list 6909651 has disabled YCbCr* color space for DisplayPort, it - * says - - * "Disable anything other than RGB for DisplayPort; on FERMI at least, - * there are problems YCbCr* on DP (but not HDMI), since the limited range - * must be implemented by EVO HW, and not the LUT (per EVO error checks)." - * - * TODO Investigate if YCbCr* color space for DisplayPort allowed on Kepler - * onward (also take DP-MST into consideration). - */ - if (!nvConnectorUsesDPLib(pConnectorEvo)) { - /* check for color space (YCbCr422, YCbCr444) capability of GPU */ - if (FLD_TEST_DRF(0073, _CTRL_DFP_FLAGS_FORMAT, _YCBCR422_CAPABLE, _TRUE, - pConnectorEvo->dfpInfo)) { - pConnectorEvo->colorSpaceCaps.ycbcr422Capable = TRUE; - } - - if (FLD_TEST_DRF(0073, _CTRL_DFP_FLAGS_FORMAT, _YCBCR444_CAPABLE, _TRUE, - pConnectorEvo->dfpInfo)) { - pConnectorEvo->colorSpaceCaps.ycbcr444Capable = TRUE; - } - } else { - pConnectorEvo->colorSpaceCaps.ycbcr422Capable = FALSE; - pConnectorEvo->colorSpaceCaps.ycbcr444Capable = FALSE; - } - if (pConnectorEvo->signalFormat == NVKMS_CONNECTOR_SIGNAL_FORMAT_DSI) { nvAssert(pDevEvo->numHeads >= 1); // DSI supports only HEAD0 assignment @@ -2622,24 +2590,6 @@ void nvRmFreeEvoDma(NVDevEvoPtr pDevEvo, NVEvoDmaPtr pDma) } } -static void -CompletionNotifierEventDeferredWork(void *dataPtr, NvU32 dataU32) -{ - NVEvoChannelPtr pChannel = dataPtr; - - nvSendFlipOccurredEventEvo(pChannel->pb.pDevEvo, pChannel->channelMask); -} - -static void CompletionNotifierEvent(void *arg, void *pEventDataVoid, - NvU32 hEvent, NvU32 Data, NV_STATUS Status) -{ - (void) nvkms_alloc_timer_with_ref_ptr( - CompletionNotifierEventDeferredWork, /* callback */ - arg, /* argument (this is a ref_ptr to a pChannel) */ - 0, /* dataU32 */ - 0); /* timeout: schedule the work immediately */ -} - /*****************************************************************************/ /* RmAllocEvoChannel () * Allocates the EVO channel and associated notifier surfaces and ctxdmas. @@ -2793,30 +2743,6 @@ RmAllocEvoChannel(NVDevEvoPtr pDevEvo, buffer->pDevEvo = pDevEvo; buffer->currentSubDevMask = SUBDEVICE_MASK_ALL; - if (!FLD_TEST_DRF64(_EVO, _CHANNEL_MASK, _CORE, _ENABLE, channelMask)) { - pChannel->ref_ptr = nvkms_alloc_ref_ptr(pChannel); - - if (pChannel->ref_ptr == NULL) { - goto fail; - } - - pChannel->completionNotifierEventHandle = - nvGenerateUnixRmHandle(&pDevEvo->handleAllocator); - - if (!nvRmRegisterCallback(pDevEvo, - &pChannel->completionNotifierEventCallback, - pChannel->ref_ptr, - pChannel->pb.channel_handle, - pChannel->completionNotifierEventHandle, - CompletionNotifierEvent, - 0)) { - nvFreeUnixRmHandle(&pDevEvo->handleAllocator, - pChannel->completionNotifierEventHandle); - pChannel->completionNotifierEventHandle = 0; - goto fail; - } - } - pChannel->imm.type = NV_EVO_IMM_CHANNEL_NONE; pDevEvo->hal->InitChannel(pDevEvo, pChannel); @@ -2918,8 +2844,6 @@ static void RmFreeEvoChannel(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel) pChannel->completionNotifierEventHandle = 0; } - nvkms_free_ref_ptr(pChannel->ref_ptr); - for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { if (pChannel->pb.control[sd]) { if (nvRmApiUnmapMemory(nvEvoGlobal.clientHandle, @@ -3176,6 +3100,9 @@ static NvBool AllocSyncpt(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel, return FALSE; } + /*! Set syncpt id to invalid to avoid un-intended Free */ + pEvoSyncptOut->id = NVKMS_SYNCPT_ID_INVALID; + /* * HW engine on Orin is called HOST1X, all syncpts are in internal RAM of * HOST1X. @@ -3187,13 +3114,18 @@ static NvBool AllocSyncpt(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel, return FALSE; } id = params.alloc.id; - result = nvRmEvoAllocAndBindSyncpt( - pDevEvo, pChannel, id, &hSyncpt, &hSyncptCtxDma); + + /* Post syncpt max val is tracked locally. Init the value here. */ + params.read_minval.id = id; + result = nvkms_syncpt_op(NVKMS_SYNCPT_OP_READ_MINVAL, ¶ms); if (!result) { - /*! put back syncpt as register failed */ - params.put.id = id; - nvkms_syncpt_op(NVKMS_SYNCPT_OP_PUT, ¶ms); - return FALSE; + goto failed; + } + + result = nvRmEvoAllocAndBindSyncpt(pDevEvo, pChannel, id, + &hSyncpt, &hSyncptCtxDma); + if (!result) { + goto failed; } /*! Populate syncpt values to return. */ @@ -3201,7 +3133,15 @@ static NvBool AllocSyncpt(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel, pEvoSyncptOut->hCtxDma = hSyncptCtxDma; pEvoSyncptOut->hSyncpt = hSyncpt; pEvoSyncptOut->channelMask = pChannel->channelMask; + pEvoSyncptOut->syncptMaxVal = params.read_minval.minval; + return TRUE; + +failed: + /*! put back syncpt as operation failed */ + params.put.id = id; + nvkms_syncpt_op(NVKMS_SYNCPT_OP_PUT, ¶ms); + return FALSE; } static NvBool AllocPostSyncptPerChannel(NVDevEvoPtr pDevEvo, @@ -3345,7 +3285,7 @@ failed: } /* Pre-allocate the vblank syncpts, store in NVDispHeadStateEvoRec. */ -static void AllocCoreRGSyncpts(NVDevEvoPtr pDevEvo) +void nvRmAllocCoreRGSyncpts(NVDevEvoPtr pDevEvo) { NVDispEvoPtr pDispEvo = NULL; @@ -3361,21 +3301,22 @@ static void AllocCoreRGSyncpts(NVDevEvoPtr pDevEvo) pDispEvo = pDevEvo->pDispEvo[0]; /* Initialize all heads' vblank sync object counts to zero. */ - for (int i = 0; i < pDevEvo->numHeads; i++) { - pDispEvo->headState[i].numVblankSyncObjectsCreated = 0; + for (int i = 0; i < pDevEvo->numApiHeads; i++) { + pDispEvo->apiHeadState[i].numVblankSyncObjectsCreated = 0; } /* For each core RG syncpt index: */ for (syncptIdx = 0; syncptIdx < NVKMS_MAX_VBLANK_SYNC_OBJECTS_PER_HEAD; syncptIdx++) { /* For each Head: */ - for (int i = 0; i < pDevEvo->numHeads; i++) { + for (int i = 0; i < pDevEvo->numApiHeads; i++) { NvBool result = FALSE; - NVDispHeadStateEvoPtr pHeadState = &pDispEvo->headState[i]; + NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[i]; result = AllocSyncpt(pDevEvo, pDevEvo->core, - &pHeadState->vblankSyncObjects[syncptIdx].evoSyncpt); + &pApiHeadState->vblankSyncObjects[syncptIdx].evoSyncpt); if (!result) { /* * Stop trying to allocate more syncpts if none are @@ -3388,9 +3329,9 @@ static void AllocCoreRGSyncpts(NVDevEvoPtr pDevEvo) } /* Populate the index of the syncpt in the NVVblankSyncObjectRec. */ - pHeadState->vblankSyncObjects[syncptIdx].index = syncptIdx; + pApiHeadState->vblankSyncObjects[syncptIdx].index = syncptIdx; /* Update the count. */ - pHeadState->numVblankSyncObjectsCreated = syncptIdx + 1; + pApiHeadState->numVblankSyncObjectsCreated = syncptIdx + 1; } } } @@ -3418,8 +3359,6 @@ NvBool nvRMSetupEvoCoreChannel(NVDevEvoPtr pDevEvo) } } - AllocCoreRGSyncpts(pDevEvo); - nvInitEvoSubDevMask(pDevEvo); /* @@ -3468,7 +3407,7 @@ void nvRMFreeWindowChannels(NVDevEvoPtr pDevEvo) } /* Frees the Core RG Syncpts. */ -static void FreeCoreRGSyncpts(NVDevEvoPtr pDevEvo) +void nvRmFreeCoreRGSyncpts(NVDevEvoPtr pDevEvo) { NVDispEvoPtr pDispEvo = NULL; @@ -3488,21 +3427,19 @@ static void FreeCoreRGSyncpts(NVDevEvoPtr pDevEvo) pDispEvo = pDevEvo->pDispEvo[0]; /* For each Head: */ - for (int i = 0; i < pDevEvo->numHeads; i++) { + for (int i = 0; i < pDevEvo->numApiHeads; i++) { /* Free all core RG syncpts. */ - NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[i]; - for (int j = 0; j < pHeadState->numVblankSyncObjectsCreated; j++) { + NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[i]; + for (int j = 0; j < pApiHeadState->numVblankSyncObjectsCreated; j++) { nvRmEvoFreeSyncpt(pDevEvo, - &pHeadState->vblankSyncObjects[j].evoSyncpt); + &pApiHeadState->vblankSyncObjects[j].evoSyncpt); } - pHeadState->numVblankSyncObjectsCreated = 0; + pApiHeadState->numVblankSyncObjectsCreated = 0; } } void nvRMFreeEvoCoreChannel(NVDevEvoPtr pDevEvo) { - FreeCoreRGSyncpts(pDevEvo); - if (pDevEvo->core != NULL) { EvoFreeCoreChannel(pDevEvo, pDevEvo->core); pDevEvo->core = NULL; @@ -3794,7 +3731,8 @@ void nvRmEvoFreeSyncpt( NVDevEvoRec *pDevEvo, NVEvoSyncpt *pEvoSyncpt) { - if ((pEvoSyncpt == NULL) || !pDevEvo->supportsSyncpts) { + if ((pEvoSyncpt == NULL) || !pDevEvo->supportsSyncpts || + (pEvoSyncpt->id == NVKMS_SYNCPT_ID_INVALID)) { return; } @@ -5237,6 +5175,41 @@ NvBool nvRmSetGc6Allowed(NVDevEvoPtr pDevEvo, NvBool allowed) return TRUE; } +typedef struct _NVRmRgLine1CallbackRec { + NVRgLine1CallbackRec base; + struct nvkms_ref_ptr *ref_ptr; + NvU32 rmHandle; + NVDispEvoRec *pDispEvo; + NvU32 head; +} NVRmRgLine1CallbackRec; + +static void RGLine1ServiceInterrupt(void *dataPtr, NvU32 dataU32) +{ + NVRmRgLine1CallbackRec *pRmCallback = (NVRmRgLine1CallbackRec*)dataPtr; + pRmCallback->base.pCallbackProc(pRmCallback->pDispEvo, pRmCallback->head, + &pRmCallback->base); +} + +/*! + * Receive RG line 1 interrupt notification from resman. + * + * This function is registered as the kernel callback function from resman when + * the RG line 1 interrupt is generated. + * + * This function is called within resman's context, so we schedule a zero timer + * callback to process the swapgroup check and release without holding the + * resman lock. + */ +static void RGLine1InterruptCallback(NvU32 rgIntrLine, void *param1, + NvBool bIsIrqlIsr /* unused */) +{ + (void) nvkms_alloc_timer_with_ref_ptr( + RGLine1ServiceInterrupt, /* callback */ + param1, /* argument (this is a ref_ptr to a NVRmRgLine1CallbackRec*) */ + 0, /* dataU32 */ + 0); /* usec */ +} + /*! * Register an RM callback function for the RG line 1 interrupt. * @@ -5246,38 +5219,40 @@ NvBool nvRmSetGc6Allowed(NVDevEvoPtr pDevEvo, NvBool allowed) * * \param[in] pCallback The callback function pointer to be registered * - * \return Handle to callback object on success, 0 on failure. This same - * handle must be used to unregister the callback. + * \return Pointer to callback object on success, NULL on failure. This same + * pointer must be used to unregister the callback. */ -NvU32 nvRmAddRgLine1Callback( - const NVDispEvoRec *pDispEvo, - NvU32 head, - NV0092_REGISTER_RG_LINE_CALLBACK_FN pCallback) +NVRgLine1CallbackPtr +nvRmAddRgLine1Callback(NVDispEvoRec *pDispEvo, + NvU32 head, + NVRgLine1CallbackProc pCallbackProc, + void *pUserData) { NV0092_RG_LINE_CALLBACK_ALLOCATION_PARAMETERS rgLineParams = { 0 }; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; NvU32 handle = nvGenerateUnixRmHandle(&pDevEvo->handleAllocator); NvU32 ret; + NVRmRgLine1CallbackRec *pRmCallback = nvCalloc(1, sizeof(*pRmCallback)); + + if (pRmCallback == NULL) { + goto failed; + } + + pRmCallback->ref_ptr = nvkms_alloc_ref_ptr(pRmCallback); + if (pRmCallback->ref_ptr == NULL) { + goto failed; + } + pRmCallback->base.pCallbackProc = pCallbackProc; + pRmCallback->base.pUserData = pUserData; + pRmCallback->rmHandle = handle; + pRmCallback->pDispEvo = pDispEvo; + pRmCallback->head = head; rgLineParams.subDeviceInstance = pDispEvo->displayOwner; rgLineParams.head = head; rgLineParams.rgLineNum = 1; - rgLineParams.pCallbkFn = pCallback; - - /* - * This object only takes a single pointer, but we want it to operate - * on a {pDispEvo,head} tuple, but we want to allocate the callback - * in NVKMS using a ref_ptr to allow for the pDispEvo being freed while - * callbacks are outstanding, so we bundle pDispEvo->ref_ptr and head - * into a single value here before passing it to RM, then decouple them - * in the RM callback function before allocating the NVKMS timer callback. - * - * This works because pDispEvo->ref_ptr will never have the lowest 2 - * bits set, and RM doesn't do anything with pCallbkParams aside from - * passing it back to the callback function. - */ - nvAssert(!((NvUPtr)pDispEvo->ref_ptr & head)); - rgLineParams.pCallbkParams = (void*)((NvUPtr)pDispEvo->ref_ptr | head); + rgLineParams.pCallbkFn = RGLine1InterruptCallback; + rgLineParams.pCallbkParams = pRmCallback->ref_ptr; ret = nvRmApiAlloc(nvEvoGlobal.clientHandle, pDevEvo->displayCommonHandle, @@ -5286,47 +5261,60 @@ NvU32 nvRmAddRgLine1Callback( &rgLineParams); if (ret == NVOS_STATUS_SUCCESS) { - return handle; - } else { - nvEvoLogDevDebug(pDevEvo, EVO_LOG_ERROR, - "Failed to enable RG line interrupt, ret: %d", ret); - nvFreeUnixRmHandle(&pDevEvo->handleAllocator, handle); - return 0; + return &pRmCallback->base; } + + nvEvoLogDevDebug(pDevEvo, EVO_LOG_ERROR, + "Failed to enable RG line interrupt, ret: %d", ret); + /* fall through */ + +failed: + if (pRmCallback != NULL) { + nvkms_free_ref_ptr(pRmCallback->ref_ptr); + nvFree(pRmCallback); + } + + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, handle); + + return NULL; } /*! * Unregister an RM callback function previously registered with * nvRmAddRgLine1Callback. * - * \param[in] pDispEvo The display on which to unregister the - * callback + * \param[in] pDispEvo The display on which to unregister the + * callback * - * \param[in] callbackObjectHandle Handle to the previously allocated - * callback object + * \param[in] pCallback Pointer to the previously allocated + * callback object */ void nvRmRemoveRgLine1Callback(const NVDispEvoRec *pDispEvo, - NvU32 callbackObjectHandle) + NVRgLine1CallbackPtr pCallback) { + NVRmRgLine1CallbackRec *pRmCallback; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; NvU32 ret; - if (callbackObjectHandle == 0) { + if (pCallback == NULL) { nvEvoLogDevDebug(pDevEvo, EVO_LOG_ERROR, - "Failed to disable RG line interrupt, obj handle 0"); + "Failed to disable RG line interrupt, obj pointer NULL"); return; } + pRmCallback = nv_container_of(pCallback, NVRmRgLine1CallbackRec, base); ret = nvRmApiFree(nvEvoGlobal.clientHandle, pDevEvo->displayCommonHandle, - callbackObjectHandle); + pRmCallback->rmHandle); if (ret != NVOS_STATUS_SUCCESS) { nvEvoLogDevDebug(pDevEvo, EVO_LOG_ERROR, "Failed to disable RG line interrupt, ret: %d", ret); } - nvFreeUnixRmHandle(&pDevEvo->handleAllocator, callbackObjectHandle); + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, pRmCallback->rmHandle); + nvkms_free_ref_ptr(pRmCallback->ref_ptr); + nvFree(pRmCallback); } /*! @@ -5344,7 +5332,8 @@ void nvRmRemoveRgLine1Callback(const NVDispEvoRec *pDispEvo, NvU32 nvRmAddVBlankCallback( const NVDispEvoRec *pDispEvo, NvU32 head, - OSVBLANKCALLBACKPROC pCallback) + OSVBLANKCALLBACKPROC pCallback, + void *pParam2) { NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; const NvU32 sd = pDispEvo->displayOwner; @@ -5355,12 +5344,7 @@ NvU32 nvRmAddVBlankCallback( .pProc = pCallback, .LogicalHead = head, .pParm1 = pDispEvo->ref_ptr, - - /* - * The callback's second argument is a pointer, which is large enough to - * store the head number. - */ - .pParm2 = (void *)(NvUPtr)head, + .pParm2 = pParam2, }; ret = nvRmApiAlloc(nvEvoGlobal.clientHandle, diff --git a/src/nvidia-modeset/src/nvkms-surface.c b/src/nvidia-modeset/src/nvkms-surface.c index ce2f95a2c..38298a327 100644 --- a/src/nvidia-modeset/src/nvkms-surface.c +++ b/src/nvidia-modeset/src/nvkms-surface.c @@ -594,7 +594,7 @@ struct ClearSurfaceUsageCache { } layer[NVKMS_MAX_LAYERS_PER_HEAD]; NvBool flipCursorToNull : 1; - } head[NVKMS_MAX_SUBDEVICES][NVKMS_MAX_HEADS_PER_DISP]; + } apiHead[NVKMS_MAX_SUBDEVICES][NVKMS_MAX_HEADS_PER_DISP]; }; /* @@ -607,69 +607,67 @@ ClearSurfaceUsageCollect(NVDevEvoPtr pDevEvo, struct ClearSurfaceUsageCache *pCache) { NVDispEvoPtr pDispEvo; - NvU32 head, sd; + NvU32 apiHead, sd; FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - for (head = 0; head < pDevEvo->numHeads; head++) { - - const NVEvoSubDevHeadStateRec *pSdHeadState = - &pDevEvo->gpus[sd].headState[head]; - const NVFlipChannelEvoHwState *pMainFlipState = - &pSdHeadState->layer[NVKMS_MAIN_LAYER]; + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + NvU32 usageMaskOneHead = nvCollectSurfaceUsageMaskOneApiHead(pDispEvo, + apiHead, pSurfaceEvo); + NvU32 usageMaskMainLayer = DRF_IDX_VAL(_SURFACE, + _USAGE_MASK, _LAYER, NVKMS_MAIN_LAYER, usageMaskOneHead); NvU32 layer; - if (!nvHeadIsActive(pDispEvo, head)) { - continue; - } - /* * XXX NVKMS TODO: flip across heads/subdevices for all scenarios * that are flip locked. */ - if (!pMainFlipState->syncObject.usingSyncpt && - (pSurfaceEvo == pMainFlipState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo || - pSurfaceEvo == pMainFlipState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo)) { - pCache->head[sd][head].layer[NVKMS_MAIN_LAYER].flipSemaphoreToNull = TRUE; + if (FLD_TEST_DRF(_SURFACE, _USAGE_MASK_LAYER, _SEMAPHORE, + _ENABLE, usageMaskMainLayer)) { + pCache->apiHead[sd][apiHead].layer[NVKMS_MAIN_LAYER]. + flipSemaphoreToNull = TRUE; } - if (pSurfaceEvo == pMainFlipState->pSurfaceEvo[NVKMS_LEFT] || - pSurfaceEvo == pMainFlipState->pSurfaceEvo[NVKMS_RIGHT] || - pSurfaceEvo == pMainFlipState->completionNotifier.surface.pSurfaceEvo) { - pCache->head[sd][head].layer[NVKMS_MAIN_LAYER].flipToNull = TRUE; + if (FLD_TEST_DRF(_SURFACE, _USAGE_MASK_LAYER, _NOTIFIER, + _ENABLE, usageMaskMainLayer) || + FLD_TEST_DRF(_SURFACE, _USAGE_MASK_LAYER, _SCANOUT, + _ENABLE, usageMaskMainLayer)) { + pCache->apiHead[sd][apiHead].layer[NVKMS_MAIN_LAYER]. + flipToNull = TRUE; } - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - const NVFlipChannelEvoHwState *pLayerFlipState = - &pSdHeadState->layer[layer]; + for (layer = 0; + layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { + NvU32 usageMaskOneLayer = DRF_IDX_VAL(_SURFACE, + _USAGE_MASK, _LAYER, layer, usageMaskOneHead); if (layer == NVKMS_MAIN_LAYER) { continue; } - if (pSurfaceEvo == pLayerFlipState->pSurfaceEvo[NVKMS_LEFT] || - pSurfaceEvo == pLayerFlipState->pSurfaceEvo[NVKMS_RIGHT] || - pSurfaceEvo == pLayerFlipState->completionNotifier.surface.pSurfaceEvo || - (!pLayerFlipState->syncObject.usingSyncpt && - (pSurfaceEvo == pLayerFlipState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo || - pSurfaceEvo == pLayerFlipState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo))) { - pCache->head[sd][head].layer[layer].flipToNull = TRUE; - } - - /* - * EVO requires that, when flipping the base channel (aka main layer) to - * NULL, overlay channel is also flipped to NULL. - */ - if (pCache->head[sd][head].layer[NVKMS_MAIN_LAYER].flipToNull && - (pLayerFlipState->pSurfaceEvo[NVKMS_LEFT] != NULL || - pLayerFlipState->pSurfaceEvo[NVKMS_RIGHT] != NULL)) { - pCache->head[sd][head].layer[layer].flipToNull = TRUE; + if (usageMaskOneLayer != 0x0) { + pCache->apiHead[sd][apiHead].layer[layer]. + flipToNull = TRUE; + } if (pCache->apiHead[sd][apiHead].layer[NVKMS_MAIN_LAYER]. + flipToNull) { + NVSurfaceEvoPtr pSurfaceEvos[NVKMS_MAX_EYES] = { }; + /* + * EVO requires that, when flipping the base channel + * (aka main layer) to NULL, overlay channel is also + * flipped to NULL. + */ + if ((pSurfaceEvos[NVKMS_LEFT] != NULL) || + (pSurfaceEvos[NVKMS_RIGHT] != NULL)) { + pCache->apiHead[sd][apiHead].layer[layer]. + flipToNull = TRUE; + } } } - if (pSurfaceEvo == pSdHeadState->cursor.pSurfaceEvo) { - pCache->head[sd][head].flipCursorToNull = TRUE; + if (FLD_TEST_DRF(_SURFACE, _USAGE_MASK, _CURSOR, + _ENABLE, usageMaskOneHead) != 0x0) { + pCache->apiHead[sd][apiHead].flipCursorToNull = TRUE; } } } @@ -700,11 +698,13 @@ ClearSurfaceUsageApply(NVDevEvoPtr pDevEvo, NvBool skipUpdate) { NVDispEvoPtr pDispEvo; - NvU32 head, sd; - NvBool found = FALSE; - struct NvKmsFlipRequest *request = nvCalloc(1, sizeof(*request)); + NvU32 apiHead, sd; + const NvU32 maxApiHeads = pDevEvo->numApiHeads * pDevEvo->numSubDevices; + struct NvKmsFlipRequestOneHead *pFlipApiHead = + nvCalloc(1, sizeof(*pFlipApiHead) * maxApiHeads); + NvU32 numFlipApiHeads = 0; - if (request == NULL) { + if (pFlipApiHead == NULL) { nvAssert(!"Failed to allocate memory"); return; } @@ -712,46 +712,59 @@ ClearSurfaceUsageApply(NVDevEvoPtr pDevEvo, /* 1. Issue a flip of any overlay layer to NULL */ FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - for (head = 0; head < pDevEvo->numHeads; head++) { + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { - struct NvKmsFlipCommonParams *pRequestOneHead = - &request->sd[sd].head[head]; + struct NvKmsFlipCommonParams *pRequestOneApiHead = + &pFlipApiHead[numFlipApiHeads].flip; NvU32 layer; + NvBool found = FALSE; - if (!nvHeadIsActive(pDispEvo, head)) { + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { continue; } - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + for (layer = 0; + layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { if (layer == NVKMS_MAIN_LAYER) { continue; } - if (pCache->head[sd][head].layer[layer].flipToNull) { - pRequestOneHead->layer[layer].surface.specified = TRUE; + if (pCache->apiHead[sd][apiHead].layer[layer].flipToNull) { + pRequestOneApiHead->layer[layer].surface.specified = TRUE; // No need to specify sizeIn/sizeOut as we are flipping NULL surface. - pRequestOneHead->layer[layer].compositionParams.specified = TRUE; - pRequestOneHead->layer[layer].syncObjects.specified = TRUE; - pRequestOneHead->layer[layer].completionNotifier.specified = TRUE; + pRequestOneApiHead->layer[layer].compositionParams.specified = TRUE; + pRequestOneApiHead->layer[layer].syncObjects.specified = TRUE; + pRequestOneApiHead->layer[layer].completionNotifier.specified = TRUE; - request->sd[sd].requestedHeadsBitMask |= NVBIT(head); found = TRUE; - pCache->head[sd][head].layer[layer].needToIdle = TRUE; + pCache->apiHead[sd][apiHead].layer[layer].needToIdle = TRUE; } } + + if (found) { + pFlipApiHead[numFlipApiHeads].sd = sd; + pFlipApiHead[numFlipApiHeads].head = apiHead; + numFlipApiHeads++; + nvAssert(numFlipApiHeads <= maxApiHeads); + } } } - if (found) { - request->commit = NV_TRUE; - - nvFlipEvo(pDevEvo, pDevEvo->pNvKmsOpenDev, request, NULL, skipUpdate, + if (numFlipApiHeads > 0) { + nvFlipEvo(pDevEvo, pDevEvo->pNvKmsOpenDev, + pFlipApiHead, + numFlipApiHeads, + TRUE /* commit */, + FALSE /* allowVrr */, + NULL /* pReply */, + skipUpdate, FALSE /* allowFlipLock */); - nvkms_memset(request, 0, sizeof(*request)); - found = FALSE; + nvkms_memset(pFlipApiHead, 0, + sizeof(pFlipApiHead[0]) * numFlipApiHeads); + numFlipApiHeads = 0; } /* @@ -766,46 +779,58 @@ ClearSurfaceUsageApply(NVDevEvoPtr pDevEvo, /* 2. Issue a flip of any main layer to NULL */ FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - for (head = 0; head < pDevEvo->numHeads; head++) { + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { - struct NvKmsFlipCommonParams *pRequestOneHead = - &request->sd[sd].head[head]; + struct NvKmsFlipCommonParams *pRequestOneApiHead = + &pFlipApiHead[numFlipApiHeads].flip; + NvBool found = FALSE; - if (!nvHeadIsActive(pDispEvo, head)) { + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { continue; } - if (pCache->head[sd][head].layer[NVKMS_MAIN_LAYER].flipToNull || - pCache->head[sd][head].layer[NVKMS_MAIN_LAYER].flipSemaphoreToNull) { + if (pCache->apiHead[sd][apiHead].layer[NVKMS_MAIN_LAYER].flipToNull || + pCache->apiHead[sd][apiHead].layer[NVKMS_MAIN_LAYER].flipSemaphoreToNull) { - if (pCache->head[sd][head].layer[NVKMS_MAIN_LAYER].flipToNull) { - pRequestOneHead->layer[NVKMS_MAIN_LAYER].surface.specified = TRUE; + if (pCache->apiHead[sd][apiHead].layer[NVKMS_MAIN_LAYER].flipToNull) { + pRequestOneApiHead->layer[NVKMS_MAIN_LAYER].surface.specified = TRUE; // No need to specify sizeIn/sizeOut as we are flipping NULL surface. - pRequestOneHead->layer[NVKMS_MAIN_LAYER].completionNotifier.specified = TRUE; + pRequestOneApiHead->layer[NVKMS_MAIN_LAYER].completionNotifier.specified = TRUE; - pCache->head[sd][head].layer[NVKMS_MAIN_LAYER].needToIdle = TRUE; + pCache->apiHead[sd][apiHead].layer[NVKMS_MAIN_LAYER].needToIdle = TRUE; } /* XXX arguably we should also idle for this case, but we * don't currently have a way to do so without also * clearing the ISO surface */ - pRequestOneHead->layer[NVKMS_MAIN_LAYER].syncObjects.val.useSyncpt = FALSE; - pRequestOneHead->layer[NVKMS_MAIN_LAYER].syncObjects.specified = TRUE; + pRequestOneApiHead->layer[NVKMS_MAIN_LAYER].syncObjects.val.useSyncpt = FALSE; + pRequestOneApiHead->layer[NVKMS_MAIN_LAYER].syncObjects.specified = TRUE; - request->sd[sd].requestedHeadsBitMask |= NVBIT(head); found = TRUE; } + + if (found) { + pFlipApiHead[numFlipApiHeads].sd = sd; + pFlipApiHead[numFlipApiHeads].head = apiHead; + numFlipApiHeads++; + nvAssert(numFlipApiHeads <= maxApiHeads); + } } } - if (found) { - request->commit = NV_TRUE; - - nvFlipEvo(pDevEvo, pDevEvo->pNvKmsOpenDev, request, NULL, skipUpdate, + if (numFlipApiHeads > 0) { + nvFlipEvo(pDevEvo, pDevEvo->pNvKmsOpenDev, + pFlipApiHead, + numFlipApiHeads, + TRUE /* commit */, + FALSE /* allowVrr */, + NULL /* pReply */, + skipUpdate, FALSE /* allowFlipLock */); - nvkms_memset(request, 0, sizeof(*request)); - found = FALSE; + nvkms_memset(pFlipApiHead, 0, + sizeof(pFlipApiHead[0]) * numFlipApiHeads); + numFlipApiHeads = 0; } /* @@ -814,111 +839,52 @@ ClearSurfaceUsageApply(NVDevEvoPtr pDevEvo, * forcibly idle any problematic channels. */ if (!skipUpdate) { - NvU64 startTime = 0; - const NvU32 timeout = 500000; // .5 seconds - NvBool allIdle; - - do { - allIdle = TRUE; - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - - for (head = 0; head < pDevEvo->numHeads; head++) { - NvU32 layer; - - if (!nvHeadIsActive(pDispEvo, head)) { - continue; + NvU32 layerMaskPerSdApiHead[NVKMS_MAX_SUBDEVICES] + [NVKMS_MAX_HEADS_PER_DISP] = { }; + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + for (NvU32 layer = 0; + layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { + if (pCache->apiHead[sd][apiHead].layer[layer].needToIdle) { + layerMaskPerSdApiHead[sd][apiHead] |= NVBIT(layer); } - - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - NvBool isMethodPending; - - if (!pCache->head[sd][head].layer[layer].needToIdle) { - continue; - } - - if (pDevEvo->hal->IsChannelMethodPending( - pDevEvo, pDevEvo->head[head].layer[layer], sd, - &isMethodPending) && - isMethodPending) { - - allIdle = FALSE; - } else { - /* This has been completed, no need to keep trying */ - pCache->head[sd][head].layer[layer].needToIdle = FALSE; - } - } - } - } - - if (!allIdle) { - if (nvExceedsTimeoutUSec(&startTime, timeout)) { - break; - } - nvkms_yield(); - } - } while (!allIdle); - - /* If we timed out above, force things to be idle. */ - if (!allIdle) { - NVEvoIdleChannelState idleChannelState = { }; - NvBool tryToForceIdle = FALSE; - - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - - for (head = 0; head < pDevEvo->numHeads; head++) { - NvU32 layer; - - if (!nvHeadIsActive(pDispEvo, head)) { - continue; - } - - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if (pCache->head[sd][head].layer[layer].needToIdle) { - idleChannelState.subdev[sd].channelMask |= - pDevEvo->head[head].layer[layer]->channelMask; - tryToForceIdle = TRUE; - } - } - } - } - - if (tryToForceIdle) { - NvBool ret = pDevEvo->hal->ForceIdleSatelliteChannel(pDevEvo, &idleChannelState); - if (!ret) { - nvAssert(ret); } } } + nvIdleLayerChannels(pDevEvo, layerMaskPerSdApiHead); } /* 4. Issue a flip of any core channels to NULL */ FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - for (head = 0; head < pDevEvo->numHeads; head++) { + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { - struct NvKmsFlipCommonParams *pRequestOneHead = - &request->sd[sd].head[head]; - - if (!nvHeadIsActive(pDispEvo, head)) { + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { continue; } - if (pCache->head[sd][head].flipCursorToNull) { - pRequestOneHead->cursor.imageSpecified = TRUE; - request->sd[sd].requestedHeadsBitMask |= NVBIT(head); - found = TRUE; + if (pCache->apiHead[sd][apiHead].flipCursorToNull) { + pFlipApiHead[numFlipApiHeads].flip.cursor.imageSpecified = TRUE; + pFlipApiHead[numFlipApiHeads].sd = sd; + pFlipApiHead[numFlipApiHeads].head = apiHead; + numFlipApiHeads++; + nvAssert(numFlipApiHeads <= maxApiHeads); } } } - if (found) { - request->commit = NV_TRUE; - - nvFlipEvo(pDevEvo, pDevEvo->pNvKmsOpenDev, request, NULL, skipUpdate, + if (numFlipApiHeads > 0) { + nvFlipEvo(pDevEvo, pDevEvo->pNvKmsOpenDev, + pFlipApiHead, + numFlipApiHeads, + TRUE /* commit */, + FALSE /* allowVrr */, + NULL /* pReply */, + skipUpdate, FALSE /* allowFlipLock */); } - nvFree(request); + nvFree(pFlipApiHead); } /* @@ -1092,37 +1058,7 @@ void nvEvoDecrementSurfaceRefCnts(NVSurfaceEvoPtr pSurfaceEvo) * flips. (Bug 2050970) */ if (pSurfaceEvo->requireCtxDma) { - /* - * XXX NVKMS TODO - * Make the sync more efficient: we only need to sync if the - * in-flight methods flip away from this surface. - */ - NvU32 head; - - /* - * If the core channel is no longer allocated, we don't need to - * sync. This assumes the channels are allocated/deallocated - * together. - */ - if (pDevEvo->core) { - - if (pDevEvo->hal->ClearSurfaceUsage != NULL) { - pDevEvo->hal->ClearSurfaceUsage(pDevEvo, pSurfaceEvo); - } - - nvRMSyncEvoChannel(pDevEvo, pDevEvo->core, __LINE__); - - for (head = 0; head < pDevEvo->numHeads; head++) { - NvU32 layer; - - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - NVEvoChannelPtr pChannel = - pDevEvo->head[head].layer[layer]; - - nvRMSyncEvoChannel(pDevEvo, pChannel, __LINE__); - } - } - } + nvEvoClearSurfaceUsage(pDevEvo, pSurfaceEvo); } FreeSurfaceEvoRm(pDevEvo, pSurfaceEvo); diff --git a/src/nvidia-modeset/src/nvkms-utils-flip.c b/src/nvidia-modeset/src/nvkms-utils-flip.c new file mode 100644 index 000000000..8338dd689 --- /dev/null +++ b/src/nvidia-modeset/src/nvkms-utils-flip.c @@ -0,0 +1,399 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvkms-utils-flip.h" +#include "nvkms-private.h" +#include "nvkms-surface.h" +#include "nvkms-cursor.h" +#include "nvkms-sync.h" + +/*! + * Assign the elements in an NVSurfaceEvoPtr[NVKMS_MAX_EYES] array. + * + * Use NVEvoApiHandlesRec to translate an + * NvKmsSurfaceHandle[NVKMS_MAX_EYES] array into an an + * NVSurfaceEvoPtr[NVKMS_MAX_EYES] array. + * + * \param[in] pOpenDevSurfaceHandles The client's surfaces. + * \param[in] surfaceHandles The handles naming surfaces. + * \param[out] pSurfaceEvos The surface pointers. + * + * \return Return TRUE if all surfaceHandles could be successfully + * translated into pSurfaceEvos. Otherwise, return FALSE. + */ +NvBool nvAssignSurfaceArray( + const NVDevEvoRec *pDevEvo, + const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, + const NvKmsSurfaceHandle surfaceHandles[NVKMS_MAX_EYES], + const NvBool isUsedByCursorChannel, + const NvBool isUsedByLayerChannel, + NVSurfaceEvoPtr pSurfaceEvos[NVKMS_MAX_EYES]) +{ + NvU32 eye; + + nvkms_memset(pSurfaceEvos, 0, sizeof(NVSurfaceEvoRec *) * NVKMS_MAX_EYES); + + for (eye = 0; eye < NVKMS_MAX_EYES; eye++) { + if (surfaceHandles[eye] != 0) { + pSurfaceEvos[eye] = + nvEvoGetSurfaceFromHandle(pDevEvo, + pOpenDevSurfaceHandles, + surfaceHandles[eye], + isUsedByCursorChannel, + isUsedByLayerChannel); + if ((pSurfaceEvos[eye] == NULL) || + (pSurfaceEvos[eye]->isoType != NVKMS_MEMORY_ISO)) { + return FALSE; + } + } + } + return TRUE; +} + + +/*! + * Assign the NVFlipNIsoSurfaceEvoHwState. + * + * Use the given NvKmsNIsoSurface to populate the + * NVFlipNIsoSurfaceEvoHwState. Validate that NvKmsNIsoSurface + * description is legitimate. + * + * \param[in] pDevEvo The device where the surface will be used. + * \param[in] pOpenDevSurfaceHandles The client's surfaces. + * \param[in] pParamsNIso The client's description of the NISO surface. + * \param[in] notifier Whether the NISO surface is a notifier. + * \param[in] pChannel The channel where the surface will be used. + * \param[out] pNIsoState The NVKMS presentation of the NISO surface. + * + * \return Return TRUE if the NVFlipNIsoSurfaceEvoHwState could be + * assigned and validated. Otherwise, return FALSE and leave + * the NVFlipNIsoSurfaceEvoHwState untouched. + */ +NvBool nvAssignNIsoEvoHwState( + const NVDevEvoRec *pDevEvo, + const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, + const struct NvKmsNIsoSurface *pParamsNIso, + const NvBool notifier, /* TRUE=notifier; FALSE=semaphore */ + const NvU32 layer, + NVFlipNIsoSurfaceEvoHwState *pNIsoState) +{ + NVSurfaceEvoPtr pSurfaceEvo; + NvU32 elementSizeInBytes = 0, offsetInBytes, maxBytes; + + nvAssert(pParamsNIso->surfaceHandle != 0); + + pSurfaceEvo = + nvEvoGetSurfaceFromHandle(pDevEvo, + pOpenDevSurfaceHandles, + pParamsNIso->surfaceHandle, + FALSE /* isUsedByCursorChannel */, + TRUE /* isUsedByLayerChannel */); + if (pSurfaceEvo == NULL) { + return FALSE; + } + + /* Attempt to validate the surface: */ + + /* Only pitch surfaces can be used */ + if (pSurfaceEvo->layout != NvKmsSurfaceMemoryLayoutPitch) { + return FALSE; + } + + if (pSurfaceEvo->isoType != NVKMS_MEMORY_NISO) { + return FALSE; + } + + if ((pParamsNIso->format != NVKMS_NISO_FORMAT_FOUR_WORD) && + (pParamsNIso->format != NVKMS_NISO_FORMAT_FOUR_WORD_NVDISPLAY) && + (pParamsNIso->format != NVKMS_NISO_FORMAT_LEGACY)) { + return FALSE; + } + + if ((pDevEvo->caps.validNIsoFormatMask & + (1 << pParamsNIso->format)) == 0) { + return FALSE; + } + + /* Check that the item fits within the surface. */ + switch (pParamsNIso->format) { + case NVKMS_NISO_FORMAT_FOUR_WORD: + case NVKMS_NISO_FORMAT_FOUR_WORD_NVDISPLAY: + elementSizeInBytes = 16; + break; + case NVKMS_NISO_FORMAT_LEGACY: + if (notifier) { + /* Legacy notifier size depends on the layer. */ + elementSizeInBytes = + pDevEvo->caps.legacyNotifierFormatSizeBytes[layer]; + } else { + /* Legacy semaphores are always 4 bytes. */ + elementSizeInBytes = 4; + } + break; + } + +#if defined(DEBUG) + /* Assert that the size calculated by nvkms-sync library is the same as the + * one we derived from channel caps above. */ + if (notifier) { + NvBool overlay = (layer != NVKMS_MAIN_LAYER); + NvU32 libSize = nvKmsSizeOfNotifier(pParamsNIso->format, overlay); + nvAssert(libSize == elementSizeInBytes); + } else { + nvAssert(nvKmsSizeOfSemaphore(pParamsNIso->format) == elementSizeInBytes); + } +#endif + /* + * offsetInWords is an NvU16 and offsetInBytes is an NvU32, so + * neither of the expressions: + * offsetInWords * 4 + * offsetInBytes + elementSizeInBytes + * should ever overflow. + */ + + ct_assert(sizeof(pParamsNIso->offsetInWords) == 2); + + offsetInBytes = ((NvU32)pParamsNIso->offsetInWords) * 4; + + /* + * Compute the upper extent of the NISO element within the surface. + */ + + maxBytes = offsetInBytes + elementSizeInBytes; + + if (maxBytes > pSurfaceEvo->planes[0].rmObjectSizeInBytes) { + return FALSE; + } + + /* EVO expects the NISO element to fit within a 4k page. */ + + if (maxBytes > 4096) { + return FALSE; + } + + /* + * XXX NVKMS TODO: Check that the surface is in vidmem if + * NV5070_CTRL_SYSTEM_CAPS_BUG_644815_DNISO_VIDMEM_ONLY + */ + + pNIsoState->pSurfaceEvo = pSurfaceEvo; + pNIsoState->format = pParamsNIso->format; + pNIsoState->offsetInWords = pParamsNIso->offsetInWords; + + return TRUE; +} + +NvBool nvAssignCompletionNotifierEvoHwState( + const NVDevEvoRec *pDevEvo, + const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, + const struct NvKmsCompletionNotifierDescription *pParamsNotif, + const NvU32 layer, + NVFlipCompletionNotifierEvoHwState *pNotif) +{ + NvBool ret; + + nvkms_memset(pNotif, 0, sizeof(*pNotif)); + + /* If no surface is specified, we should not use a notifier. */ + if (pParamsNotif->surface.surfaceHandle == 0) { + return TRUE; + } + + ret = nvAssignNIsoEvoHwState(pDevEvo, + pOpenDevSurfaceHandles, + &pParamsNotif->surface, + TRUE, /* notifier */ + layer, + &pNotif->surface); + if (ret) { + pNotif->awaken = pParamsNotif->awaken; + } + + return ret; +} + +NvBool nvAssignSemaphoreEvoHwState( + const NVDevEvoRec *pDevEvo, + const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, + const NvU32 layer, + const NvU32 sd, + const struct NvKmsChannelSyncObjects *pChannelSyncObjects, + NVFlipSyncObjectEvoHwState *pFlipSyncObject) +{ + NvBool ret; + + nvAssert(!pChannelSyncObjects->useSyncpt); + + nvkms_memset(pFlipSyncObject, 0, sizeof(*pFlipSyncObject)); + + if (!pDevEvo->hal->caps.supportsIndependentAcqRelSemaphore) { + /*! acquire and release sema surface needs to be same */ + if (pChannelSyncObjects->u.semaphores.acquire.surface.surfaceHandle != + pChannelSyncObjects->u.semaphores.release.surface.surfaceHandle) { + return FALSE; + } + if (pChannelSyncObjects->u.semaphores.acquire.surface.format != + pChannelSyncObjects->u.semaphores.release.surface.format) { + return FALSE; + } + if (pChannelSyncObjects->u.semaphores.acquire.surface.offsetInWords != + pChannelSyncObjects->u.semaphores.release.surface.offsetInWords) { + return FALSE; + } + } + + /*! If no surface is specified, we should not use a semaphore.*/ + if (pChannelSyncObjects->u.semaphores.acquire.surface.surfaceHandle != 0) { + + ret = nvAssignNIsoEvoHwState( + pDevEvo, + pOpenDevSurfaceHandles, + &pChannelSyncObjects->u.semaphores.acquire.surface, + FALSE, /* notifier */ + layer, + &pFlipSyncObject->u.semaphores.acquireSurface); + if (ret) { + pFlipSyncObject->u.semaphores.acquireValue = + pChannelSyncObjects->u.semaphores.acquire.value; + } else { + return ret; + } + } + + /*! If no surface is specified, we should not use a semaphore.*/ + if (pChannelSyncObjects->u.semaphores.release.surface.surfaceHandle != 0) { + + ret = nvAssignNIsoEvoHwState( + pDevEvo, + pOpenDevSurfaceHandles, + &pChannelSyncObjects->u.semaphores.release.surface, + FALSE, /* notifier */ + layer, + &pFlipSyncObject->u.semaphores.releaseSurface); + if (ret) { + pFlipSyncObject->u.semaphores.releaseValue = + pChannelSyncObjects->u.semaphores.release.value; + } else { + return ret; + } + } + + return TRUE; +} + +NvBool nvValidatePerLayerCompParams( + const struct NvKmsCompositionParams *pCompParams, + const struct NvKmsCompositionCapabilities *pCaps, + NVSurfaceEvoPtr pSurfaceEvo) +{ + const NvKmsSurfaceMemoryFormatInfo *pFormatInfo = (pSurfaceEvo != NULL) ? + nvKmsGetSurfaceMemoryFormatInfo(pSurfaceEvo->format) : NULL; + const enum NvKmsCompositionColorKeySelect colorKeySelect = + pCompParams->colorKeySelect; + NvU32 match; + + if ((pCaps->supportedColorKeySelects & NVBIT(colorKeySelect)) == 0x0) { + return FALSE; + } + + NVKMS_COMPOSITION_FOR_MATCH_BITS(colorKeySelect, match) { + if ((pCaps->colorKeySelect[colorKeySelect].supportedBlendModes[match] & + NVBIT(pCompParams->blendingMode[match])) == 0x0) { + return FALSE; + } + + switch (pCompParams->blendingMode[match]) { + case NVKMS_COMPOSITION_BLENDING_MODE_NON_PREMULT_ALPHA: + case NVKMS_COMPOSITION_BLENDING_MODE_PREMULT_ALPHA: + if (pCompParams->surfaceAlpha != 0) { + return FALSE; + } + break; + default: + break; + } + } + + /* Match and nomatch pixels should not use alpha blending mode at once. */ + if ((colorKeySelect != NVKMS_COMPOSITION_COLOR_KEY_SELECT_DISABLE) && + (NvKmsIsCompositionModeUseAlpha(pCompParams->blendingMode[0])) && + (NvKmsIsCompositionModeUseAlpha(pCompParams->blendingMode[1]))) { + return FALSE; + } + + /* + * If surface is NULL, no further validation required. The composition + * parameters do not take effect if surface is NULL. + */ + if (pFormatInfo == NULL || pFormatInfo->isYUV) { + return TRUE; + } + + /* Disable color keying for 8 Bpp surfaces. */ + if ((colorKeySelect == NVKMS_COMPOSITION_COLOR_KEY_SELECT_SRC) || + (colorKeySelect == NVKMS_COMPOSITION_COLOR_KEY_SELECT_DST)) { + + if (pFormatInfo->rgb.bytesPerPixel > 4) { + return FALSE; + } + } + + return TRUE; +} + +NvBool +nvAssignCursorSurface(const struct NvKmsPerOpenDev *pOpenDev, + const NVDevEvoRec *pDevEvo, + const struct NvKmsSetCursorImageCommonParams *pImgParams, + NVSurfaceEvoPtr *pSurfaceEvo) + +{ + const NVEvoApiHandlesRec *pOpenDevSurfaceHandles = + nvGetSurfaceHandlesFromOpenDevConst(pOpenDev); + NVSurfaceEvoPtr pSurfaceEvos[NVKMS_MAX_EYES] = { }; + + if (!nvGetCursorImageSurfaces(pDevEvo, + pOpenDevSurfaceHandles, + pImgParams, + pSurfaceEvos)) { + return FALSE; + } + + /* XXX NVKMS TODO: add support for stereo cursor */ + if (pSurfaceEvos[NVKMS_RIGHT] != NULL) { + return FALSE; + } + + if (pSurfaceEvos[NVKMS_LEFT] != NULL) { + if (!nvValidatePerLayerCompParams(&pImgParams->cursorCompParams, + &pDevEvo->caps.cursorCompositionCaps, + pSurfaceEvos[NVKMS_LEFT])) { + return FALSE; + } + } + + *pSurfaceEvo = pSurfaceEvos[NVKMS_LEFT]; + + return TRUE; +} + diff --git a/src/nvidia-modeset/src/nvkms-utils.c b/src/nvidia-modeset/src/nvkms-utils.c index 648af0c8b..6fd823560 100644 --- a/src/nvidia-modeset/src/nvkms-utils.c +++ b/src/nvidia-modeset/src/nvkms-utils.c @@ -489,12 +489,19 @@ void nvEvoDestroyApiHandles(NVEvoApiHandlesPtr pEvoApiHandles) NvU8 nvPixelDepthToBitsPerComponent(enum nvKmsPixelDepth pixelDepth) { + /* + * Note: The 444 formats have three components per pixel, thus we compute + * bpc as depth/3. The 422 formats effectively store two components per + * pixel, so we compute bpc for those as depth/2. + */ switch (pixelDepth) { case NVKMS_PIXEL_DEPTH_18_444: return 6; case NVKMS_PIXEL_DEPTH_24_444: + case NVKMS_PIXEL_DEPTH_16_422: return 8; case NVKMS_PIXEL_DEPTH_30_444: + case NVKMS_PIXEL_DEPTH_20_422: return 10; } nvAssert(!"Unknown NVKMS_PIXEL_DEPTH"); diff --git a/src/nvidia-modeset/src/nvkms-vrr.c b/src/nvidia-modeset/src/nvkms-vrr.c index 5467876e5..4b1a7c705 100644 --- a/src/nvidia-modeset/src/nvkms-vrr.c +++ b/src/nvidia-modeset/src/nvkms-vrr.c @@ -126,9 +126,7 @@ void nvGetDpyMinRefreshRateValidValues( return; } -void nvEnableVrr( - NVDevEvoPtr pDevEvo, - const struct NvKmsSetModeRequest *pRequest) +void nvEnableVrr(NVDevEvoPtr pDevEvo) { return; } @@ -173,7 +171,7 @@ void nvTriggerVrrUnstallMoveCursor( void nvTriggerVrrUnstallSetCursorImage( NVDispEvoPtr pDispEvo, - NvBool ctxDmaChanged) + NvBool elvReleased) { return; } diff --git a/src/nvidia-modeset/src/nvkms.c b/src/nvidia-modeset/src/nvkms.c index 3a660f097..ee7d37444 100644 --- a/src/nvidia-modeset/src/nvkms.c +++ b/src/nvidia-modeset/src/nvkms.c @@ -36,6 +36,7 @@ #include "nvkms-modepool.h" #include "nvkms-modeset.h" #include "nvkms-attributes.h" +#include "nvkms-dpy-override.h" #include "nvkms-framelock.h" #include "nvkms-surface.h" #include "nvkms-3dvision.h" @@ -43,6 +44,7 @@ #include "nvkms-headsurface.h" #include "nvkms-headsurface-ioctl.h" #include "nvkms-headsurface-swapgroup.h" +#include "nvkms-flip.h" /* nvFlipEvo */ #include "nvkms-vrr.h" #include "dp/nvdp-connector.h" @@ -209,7 +211,7 @@ struct NvKmsPerOpen { struct { NvKmsGenericHandle hCallback; struct NvKmsPerOpenDisp *pOpenDisp; - NvU32 head; + NvU32 apiHead; } vblankNotification; } e; } unicastEvent; @@ -818,7 +820,7 @@ static NvBool ValidateNvKmsPermissions( continue; } - if (nvHasBitAboveMax(layerMask, pDevEvo->head[h].numLayers)) { + if (nvHasBitAboveMax(layerMask, pDevEvo->apiHead[h].numLayers)) { return FALSE; } @@ -832,7 +834,7 @@ static NvBool ValidateNvKmsPermissions( return FALSE; } - if (h >= pDevEvo->numHeads) { + if (h >= pDevEvo->numApiHeads) { return FALSE; } } @@ -860,7 +862,7 @@ static NvBool ValidateNvKmsPermissions( return FALSE; } - if (h >= pDevEvo->numHeads) { + if (h >= pDevEvo->numApiHeads) { return FALSE; } } @@ -880,14 +882,14 @@ static void AssignFullNvKmsFlipPermissions( const NVDevEvoRec *pDevEvo, struct NvKmsFlipPermissions *pPermissions) { - NvU32 dispIndex, head; + NvU32 dispIndex, apiHead; nvkms_memset(pPermissions, 0, sizeof(*pPermissions)); for (dispIndex = 0; dispIndex < pDevEvo->nDispEvo; dispIndex++) { - for (head = 0; head < pDevEvo->numHeads; head++) { - pPermissions->disp[dispIndex].head[head].layerMask = - NVBIT(pDevEvo->head[head].numLayers) - 1; + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + pPermissions->disp[dispIndex].head[apiHead].layerMask = + NVBIT(pDevEvo->apiHead[apiHead].numLayers) - 1; } } } @@ -896,13 +898,13 @@ static void AssignFullNvKmsModesetPermissions( const NVDevEvoRec *pDevEvo, struct NvKmsModesetPermissions *pPermissions) { - NvU32 dispIndex, head; + NvU32 dispIndex, apiHead; nvkms_memset(pPermissions, 0, sizeof(*pPermissions)); for (dispIndex = 0; dispIndex < pDevEvo->nDispEvo; dispIndex++) { - for (head = 0; head < pDevEvo->numHeads; head++) { - pPermissions->disp[dispIndex].head[head].dpyIdList = + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + pPermissions->disp[dispIndex].head[apiHead].dpyIdList = nvAllDpyIdList(); } } @@ -943,6 +945,61 @@ static NvBool GrabModesetOwnership(struct NvKmsPerOpenDev *pOpenDev) return TRUE; } +/* + * If not NULL, remove pRemoveFlip from pFlip. Returns true if there are still + * some remaining permissions. + */ +static NvBool RemoveFlipPermissions(struct NvKmsFlipPermissions *pFlip, + const struct NvKmsFlipPermissions *pRemoveFlip) +{ + NvU32 d, h, dLen, hLen; + NvBool remainingPermissions = FALSE; + + dLen = ARRAY_LEN(pFlip->disp); + for (d = 0; d < dLen; d++) { + hLen = ARRAY_LEN(pFlip->disp[d].head); + for (h = 0; h < hLen; h++) { + + if (pRemoveFlip) { + pFlip->disp[d].head[h].layerMask &= + ~pRemoveFlip->disp[d].head[h].layerMask; + } + + remainingPermissions |= (pFlip->disp[d].head[h].layerMask != 0); + } + } + + return remainingPermissions; +} + +/* + * If not NULL, remove pRemoveModeset from pModeset. Returns true if there are + * still some remaining permissions. + */ +static NvBool RemoveModesetPermissions(struct NvKmsModesetPermissions *pModeset, + const struct NvKmsModesetPermissions *pRemoveModeset) +{ + NvU32 d, h, dLen, hLen; + NvBool remainingPermissions = FALSE; + + dLen = ARRAY_LEN(pModeset->disp); + for (d = 0; d < dLen; d++) { + hLen = ARRAY_LEN(pModeset->disp[d].head); + for (h = 0; h < hLen; h++) { + + if (pRemoveModeset) { + pModeset->disp[d].head[h].dpyIdList = nvDpyIdListMinusDpyIdList( + pModeset->disp[d].head[h].dpyIdList, + pRemoveModeset->disp[d].head[h].dpyIdList); + } + + remainingPermissions |= + !nvDpyIdListIsEmpty(pModeset->disp[d].head[h].dpyIdList); + } + } + + return remainingPermissions; +} /*! * Clear permissions on the specified device for all NvKmsPerOpens. @@ -1254,7 +1311,7 @@ static NvBool AllocDevice(struct NvKmsPerOpen *pOpen, struct NvKmsAllocDeviceParams *pParams = pParamsVoid; NVDevEvoPtr pDevEvo; struct NvKmsPerOpenDev *pOpenDev; - NvU32 disp, head; + NvU32 disp, apiHead; NvU8 layer; nvkms_memset(&pParams->reply, 0, sizeof(pParams->reply)); @@ -1312,7 +1369,7 @@ static NvBool AllocDevice(struct NvKmsPerOpen *pOpen, pParams->reply.deviceHandle = pOpenDev->nvKmsApiHandle; pParams->reply.subDeviceMask = NV_TWO_N_MINUS_ONE(pDevEvo->numSubDevices); - pParams->reply.numHeads = pDevEvo->numHeads; + pParams->reply.numHeads = pDevEvo->numApiHeads; pParams->reply.numDisps = pDevEvo->nDispEvo; ct_assert(ARRAY_LEN(pParams->reply.dispHandles) == @@ -1327,8 +1384,8 @@ static NvBool AllocDevice(struct NvKmsPerOpen *pOpen, ct_assert(ARRAY_LEN(pParams->reply.layerCaps) == ARRAY_LEN(pDevEvo->caps.layerCaps)); - for (head = 0; head < pDevEvo->numHeads; head++) { - pParams->reply.numLayers[head] = pDevEvo->head[head].numLayers; + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + pParams->reply.numLayers[apiHead] = pDevEvo->apiHead[apiHead].numLayers; } for (layer = 0; @@ -1406,7 +1463,7 @@ static void UnregisterDeferredRequestFifos(struct NvKmsPerOpenDev *pOpenDev) * DisableRemainingVblankSyncObjects(). */ static void DisableAndCleanVblankSyncObject(struct NvKmsPerOpenDisp *pOpenDisp, - NvU32 head, + NvU32 apiHead, NVVblankSyncObjectRec *pVblankSyncObject, NVEvoUpdateState *pUpdateState, NvKmsVblankSyncObjectHandle handle); @@ -1418,7 +1475,7 @@ static void DisableRemainingVblankSyncObjects(struct NvKmsPerOpen *pOpen, NvKmsGenericHandle disp; NVVblankSyncObjectRec *pVblankSyncObject; NvKmsVblankSyncObjectHandle handle; - NvU32 head = 0; + NvU32 apiHead = 0; nvAssert(pOpen->type == NvKmsPerOpenTypeIoctl); @@ -1436,14 +1493,14 @@ static void DisableRemainingVblankSyncObjects(struct NvKmsPerOpen *pOpen, NVEvoUpdateState updateState = { }; /* For each head: */ - for (head = 0; head < ARRAY_LEN(pOpenDisp->vblankSyncObjectHandles); head++) { + for (apiHead = 0; apiHead < ARRAY_LEN(pOpenDisp->vblankSyncObjectHandles); apiHead++) { NVEvoApiHandlesRec *pHandles = - &pOpenDisp->vblankSyncObjectHandles[head]; + &pOpenDisp->vblankSyncObjectHandles[apiHead]; /* For each still-active vblank sync object: */ FOR_ALL_POINTERS_IN_EVO_API_HANDLES(pHandles, pVblankSyncObject, handle) { - DisableAndCleanVblankSyncObject(pOpenDisp, head, + DisableAndCleanVblankSyncObject(pOpenDisp, apiHead, pVblankSyncObject, &updateState, handle); @@ -1599,7 +1656,7 @@ static NvBool QueryConnectorStaticData(struct NvKmsPerOpen *pOpen, pParams->reply.signalFormat = pConnectorEvo->signalFormat; pParams->reply.physicalIndex = pConnectorEvo->physicalIndex; pParams->reply.physicalLocation = pConnectorEvo->physicalLocation; - pParams->reply.headMask = pConnectorEvo->validHeadMask; + pParams->reply.headMask = pConnectorEvo->validApiHeadMask; pParams->reply.isLvds = (pConnectorEvo->or.type == NV0073_CTRL_SPECIFIC_OR_TYPE_SOR) && @@ -1996,20 +2053,20 @@ static NvBool SetModePrepUser( { struct NvKmsSetModeParams *pParams = pParamsVoid; struct NvKmsSetModeRequest *pReq = &pParams->request; - NvU32 disp, head, dispFailed, headFailed; + NvU32 disp, apiHead, dispFailed, apiHeadFailed; /* Iterate over all of the common LUT ramp pointers embedded in the SetMode * request, and copy in each one. */ for (disp = 0; disp < ARRAY_LEN(pReq->disp); disp++) { - for (head = 0; head < ARRAY_LEN(pReq->disp[disp].head); head++) { + for (apiHead = 0; apiHead < ARRAY_LEN(pReq->disp[disp].head); apiHead++) { struct NvKmsSetLutCommonParams *pCommonLutParams = - &pReq->disp[disp].head[head].lut; + &pReq->disp[disp].head[apiHead].lut; if (!CopyInLutParams(pCommonLutParams)) { /* Remember how far we got through these loops before we * failed, so that we can undo everything up to this point. */ dispFailed = disp; - headFailed = head; + apiHeadFailed = apiHead; goto fail; } } @@ -2019,12 +2076,12 @@ static NvBool SetModePrepUser( fail: for (disp = 0; disp < ARRAY_LEN(pReq->disp); disp++) { - for (head = 0; head < ARRAY_LEN(pReq->disp[disp].head); head++) { + for (apiHead = 0; apiHead < ARRAY_LEN(pReq->disp[disp].head); apiHead++) { struct NvKmsSetLutCommonParams *pCommonLutParams = - &pReq->disp[disp].head[head].lut; + &pReq->disp[disp].head[apiHead].lut; if (disp > dispFailed || - (disp == dispFailed && head >= headFailed)) { + (disp == dispFailed && apiHead >= apiHeadFailed)) { break; } @@ -2044,12 +2101,12 @@ static NvBool SetModeDoneUser( { struct NvKmsSetModeParams *pParams = pParamsVoid; struct NvKmsSetModeRequest *pReq = &pParams->request; - NvU32 disp, head; + NvU32 disp, apiHead; for (disp = 0; disp < ARRAY_LEN(pReq->disp); disp++) { - for (head = 0; head < ARRAY_LEN(pReq->disp[disp].head); head++) { + for (apiHead = 0; apiHead < ARRAY_LEN(pReq->disp[disp].head); apiHead++) { struct NvKmsSetLutCommonParams *pCommonLutParams = - &pReq->disp[disp].head[head].lut; + &pReq->disp[disp].head[apiHead].lut; FreeCopiedInLutParams(pCommonLutParams); } @@ -2100,7 +2157,7 @@ static NvBool SetCursorImage(struct NvKmsPerOpen *pOpen, pDispEvo = pOpenDisp->pDispEvo; - if (!nvHeadIsActive(pDispEvo, pParams->request.head)) { + if (!nvApiHeadIsActive(pDispEvo, pParams->request.head)) { return FALSE; } @@ -2130,7 +2187,7 @@ static NvBool MoveCursor(struct NvKmsPerOpen *pOpen, pDispEvo = pOpenDisp->pDispEvo; - if (!nvHeadIsActive(pDispEvo, pParams->request.head)) { + if (!nvApiHeadIsActive(pDispEvo, pParams->request.head)) { return FALSE; } @@ -2194,7 +2251,7 @@ static NvBool SetLut(struct NvKmsPerOpen *pOpen, pDispEvo = pOpenDisp->pDispEvo; - if (!nvHeadIsActive(pDispEvo, pParams->request.head)) { + if (!nvApiHeadIsActive(pDispEvo, pParams->request.head)) { return FALSE; } @@ -2214,28 +2271,15 @@ static NvBool SetLut(struct NvKmsPerOpen *pOpen, /*! * Return whether the specified head is idle. */ -static NvBool IdleBaseChannelCheckIdleOneHead( +static NvBool IdleMainLayerChannelCheckIdleOneApiHead( NVDispEvoPtr pDispEvo, - NvU32 head) + NvU32 apiHead) { - NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - - const NvU32 apiHead = nvHardwareHeadToApiHead(head); - NVHsChannelEvoPtr pHsChannel = pDispEvo->pHsChannel[apiHead]; - - if (pHsChannel != NULL) { - return nvHsIdleFlipQueue(pHsChannel, FALSE /* force */); - } else - { - NVEvoChannelPtr pMainLayerChannel = - pDevEvo->head[head].layer[NVKMS_MAIN_LAYER]; - NvBool isMethodPending = FALSE; - NvBool ret; - - ret = pDevEvo->hal->IsChannelMethodPending(pDevEvo, pMainLayerChannel, - pDispEvo->displayOwner, &isMethodPending); - return !ret || !isMethodPending; + if (pDispEvo->pHsChannel[apiHead] != NULL) { + return nvHsIdleFlipQueue(pDispEvo->pHsChannel[apiHead], + FALSE /* force */); } + return nvIdleMainLayerChannelCheckIdleOneApiHead(pDispEvo, apiHead); } /*! @@ -2251,28 +2295,28 @@ static NvBool IdleBaseChannelCheckIdle( const struct NvKmsIdleBaseChannelRequest *pRequest, struct NvKmsIdleBaseChannelReply *pReply) { - NvU32 head, sd; + NvU32 apiHead, sd; NVDispEvoPtr pDispEvo; NvBool allIdle = TRUE; FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - for (head = 0; head < pDevEvo->numHeads; head++) { + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { NvBool idle; - if (!nvHeadIsActive(pDispEvo, head)) { + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { continue; } - if ((pRequest->subDevicesPerHead[head] & NVBIT(sd)) == 0) { + if ((pRequest->subDevicesPerHead[apiHead] & NVBIT(sd)) == 0) { continue; } - idle = IdleBaseChannelCheckIdleOneHead(pDispEvo, head); + idle = IdleMainLayerChannelCheckIdleOneApiHead(pDispEvo, apiHead); if (!idle) { - pReply->stopSubDevicesPerHead[head] |= NVBIT(sd); + pReply->stopSubDevicesPerHead[apiHead] |= NVBIT(sd); } allIdle = allIdle && idle; } @@ -2358,6 +2402,96 @@ static NvBool IdleBaseChannel(struct NvKmsPerOpen *pOpen, } +struct NvKmsFlipExtraUserState +{ + // Nothing needed. +}; + +static NvBool FlipPrepUser( + void *pParamsVoid, + void *pExtraUserStateVoid) +{ + struct NvKmsFlipParams *pParams = pParamsVoid; + struct NvKmsFlipRequest *pRequest = &pParams->request; + struct NvKmsFlipRequestOneHead *pFlipHeadKernel = NULL; + NvU64 pFlipHeadUser = pRequest->pFlipHead; + size_t size; + int status; + + if (!nvKmsNvU64AddressIsSafe(pFlipHeadUser)) { + return FALSE; + } + + if (pRequest->numFlipHeads <= 0 || + pRequest->numFlipHeads > NV_MAX_FLIP_REQUEST_HEADS) { + return FALSE; + } + + size = sizeof(*pFlipHeadKernel) * pRequest->numFlipHeads; + pFlipHeadKernel = nvAlloc(size); + if (!pFlipHeadKernel) { + return FALSE; + } + + status = nvkms_copyin((char *)pFlipHeadKernel, pFlipHeadUser, size); + if (status != 0) { + nvFree(pFlipHeadKernel); + return FALSE; + } + + pRequest->pFlipHead = nvKmsPointerToNvU64(pFlipHeadKernel); + + return TRUE; +} + +static NvBool FlipDoneUser( + void *pParamsVoid, + void *pExtraUserStateVoid) +{ + struct NvKmsFlipParams *pParams = pParamsVoid; + struct NvKmsFlipRequest *pRequest = &pParams->request; + + nvFree(nvKmsNvU64ToPointer(pRequest->pFlipHead)); + /* The request is not copied back out to userspace (only the reply is), so + * we don't need to worry about restoring the user pointer */ + pRequest->pFlipHead = 0; + + return TRUE; +} + +/*! + * For each entry in the array pointed to by 'pFlipHead', of length + * 'numFlipHeads', verify that the sd and head values specified are within + * bounds and that there are no duplicates. + */ +static NvBool ValidateFlipHeads( + NVDevEvoPtr pDevEvo, + const struct NvKmsFlipRequestOneHead *pFlipHead, + NvU32 numFlipHeads) +{ + NvU32 i; + ct_assert(NVKMS_MAX_HEADS_PER_DISP <= 8); + NvU8 apiHeadsUsed[NVKMS_MAX_SUBDEVICES] = { }; + + for (i = 0; i < numFlipHeads; i++) { + const NvU32 sd = pFlipHead[i].sd; + const NvU32 apiHead = pFlipHead[i].head; + + if (sd >= pDevEvo->numSubDevices) { + return FALSE; + } + if (apiHead >= pDevEvo->numApiHeads) { + return FALSE; + } + if ((apiHeadsUsed[sd] & (1 << apiHead)) != 0) { + return FALSE; + } + apiHeadsUsed[sd] |= (1 << apiHead); + } + + return TRUE; +} + /*! * Flip the specified head. */ @@ -2366,6 +2500,11 @@ static NvBool Flip(struct NvKmsPerOpen *pOpen, { struct NvKmsFlipParams *pParams = pParamsVoid; struct NvKmsPerOpenDev *pOpenDev; + NVDevEvoPtr pDevEvo = NULL; + const struct NvKmsFlipRequest *pRequest = &pParams->request; + const struct NvKmsFlipRequestOneHead *pFlipHead = + nvKmsNvU64ToPointer(pRequest->pFlipHead); + const NvU32 numFlipHeads = pRequest->numFlipHeads; pOpenDev = GetPerOpenDev(pOpen, pParams->request.deviceHandle); @@ -2373,8 +2512,16 @@ static NvBool Flip(struct NvKmsPerOpen *pOpen, return FALSE; } - return nvHsIoctlFlip(pOpenDev->pDevEvo, pOpenDev, - &pParams->request, &pParams->reply); + pDevEvo = pOpenDev->pDevEvo; + + if (!ValidateFlipHeads(pDevEvo, pFlipHead, numFlipHeads)) { + return FALSE; + } + + return nvHsIoctlFlip(pDevEvo, pOpenDev, + pFlipHead, numFlipHeads, + pRequest->commit, pRequest->allowVrr, + &pParams->reply); } @@ -3191,6 +3338,86 @@ static NvBool AcquirePermissions(struct NvKmsPerOpen *pOpen, void *pParamsVoid) return TRUE; } +/*! + * Clear the set of permissions from pRevokingOpenDev. + * + * For NvKmsPerOpen::type==Ioctl, clear from permissions. It doesn't clear + * itself or privileged. + * + * For NvKmsPerOpen::type==GrantPermissions, clear from + * NvKmsPerOpen::grantPermissions, and reset NvKmsPerOpen::type to Undefined + * if it is empty. + */ +static NvBool RevokePermissionsSet( + struct NvKmsPerOpenDev *pRevokingOpenDev, + const struct NvKmsPermissions *pRevokingPermissions) +{ + const NVDevEvoRec *pDevEvo; + struct NvKmsPerOpen *pOpen; + const struct NvKmsFlipPermissions *pRemoveFlip; + const struct NvKmsModesetPermissions *pRemoveModeset; + + // Only process valid permissions. + if (pRevokingPermissions->type != NV_KMS_PERMISSIONS_TYPE_FLIPPING && + pRevokingPermissions->type != NV_KMS_PERMISSIONS_TYPE_MODESET) { + return FALSE; + } + + pDevEvo = pRevokingOpenDev->pDevEvo; + pRemoveFlip = + (pRevokingPermissions->type == NV_KMS_PERMISSIONS_TYPE_FLIPPING) + ? &pRevokingPermissions->flip + : NULL; + pRemoveModeset = + (pRevokingPermissions->type == NV_KMS_PERMISSIONS_TYPE_MODESET) + ? &pRevokingPermissions->modeset + : NULL; + + nvListForEachEntry(pOpen, &perOpenList, perOpenListEntry) { + if ((pOpen->type == NvKmsPerOpenTypeGrantPermissions) && + (pOpen->grantPermissions.pDevEvo == pDevEvo)) { + NvBool remainingPermissions = FALSE; + struct NvKmsPermissions *pFdPermissions = + &pOpen->grantPermissions.permissions; + + if (pFdPermissions->type == NV_KMS_PERMISSIONS_TYPE_FLIPPING) { + remainingPermissions = + RemoveFlipPermissions(&pFdPermissions->flip, pRemoveFlip); + } else { + remainingPermissions = RemoveModesetPermissions( + &pFdPermissions->modeset, pRemoveModeset); + } + + // Reset if it is empty. + if (!remainingPermissions) { + nvkms_memset(&pOpen->grantPermissions, 0, + sizeof(pOpen->grantPermissions)); + pOpen->type = NvKmsPerOpenTypeUndefined; + } + + } else if (pOpen->type == NvKmsPerOpenTypeIoctl) { + + struct NvKmsPerOpenDev *pOpenDev = DevEvoToOpenDev(pOpen, pDevEvo); + if (pOpenDev == NULL) { + continue; + } + + if (pOpenDev == pRevokingOpenDev || pOpenDev->isPrivileged) { + continue; + } + + if (pRevokingPermissions->type == NV_KMS_PERMISSIONS_TYPE_FLIPPING) { + RemoveFlipPermissions(&pOpenDev->flipPermissions, pRemoveFlip); + } else { + RemoveModesetPermissions(&pOpenDev->modesetPermissions, + pRemoveModeset); + } + } + } + + return TRUE; +} + static NvBool RevokePermissions(struct NvKmsPerOpen *pOpen, void *pParamsVoid) { struct NvKmsRevokePermissionsParams *pParams = pParamsVoid; @@ -3215,11 +3442,18 @@ static NvBool RevokePermissions(struct NvKmsPerOpen *pOpen, void *pParamsVoid) return FALSE; } - /* Revoke permissions for everyone except the caller. */ + if (pParams->request.permissionsTypeBitmask > 0) { + // Old behavior, revoke all permissions of a type. + + /* Revoke permissions for everyone except the caller. */ + RevokePermissionsInternal(pParams->request.permissionsTypeBitmask, + pOpenDev->pDevEvo, + pOpenDev /* pOpenDevExclude */); + } else { + /* If not using bitmask, revoke using the set. */ + return RevokePermissionsSet(pOpenDev, &pParams->request.permissions); + } - RevokePermissionsInternal(pParams->request.permissionsTypeBitmask, - pOpenDev->pDevEvo, - pOpenDev /* pOpenDevExclude */); return TRUE; } @@ -3341,7 +3575,7 @@ static NvBool QueryDpyCRC32(struct NvKmsPerOpen *pOpen, pDispEvo = pOpenDisp->pDispEvo; - if (!nvHeadIsActive(pDispEvo, pParams->request.head)) { + if (!nvApiHeadIsActive(pDispEvo, pParams->request.head)) { return FALSE; } @@ -3352,8 +3586,18 @@ static NvBool QueryDpyCRC32(struct NvKmsPerOpen *pOpen, crcOut.compositorCrc32 = &(pParams->reply.compositorCrc32); crcOut.outputCrc32 = &(pParams->reply.outputCrc32); - if (!nvReadCRC32Evo(pDispEvo, pParams->request.head, &crcOut)) { - return FALSE; + { + /* + * XXX[2Heads1OR] Is it sufficient to query CRC only for the primary + * hardware head? + */ + NvU32 head = nvGetPrimaryHwHead(pDispEvo, pParams->request.head); + + nvAssert(head != NV_INVALID_HEAD); + + if (!nvReadCRC32Evo(pDispEvo, head, &crcOut)) { + return FALSE; + } } return TRUE; @@ -3818,11 +4062,11 @@ static NvBool EnableVblankSyncObject( { struct NvKmsEnableVblankSyncObjectParams *pParams = pParamsVoid; struct NvKmsPerOpenDisp* pOpenDisp = NULL; - NVDispHeadStateEvoRec *pHeadState = NULL; + NVDispApiHeadStateEvoRec *pApiHeadState = NULL; NVDevEvoPtr pDevEvo = NULL; NvKmsVblankSyncObjectHandle vblankHandle = 0; int freeVblankSyncObjectIdx = 0; - NvU32 head = pParams->request.head; + NvU32 apiHead = pParams->request.head; NVVblankSyncObjectRec *vblankSyncObjects = NULL; NVDispEvoPtr pDispEvo = NULL; NVEvoUpdateState updateState = { }; @@ -3847,12 +4091,12 @@ static NvBool EnableVblankSyncObject( } /* Validate requested head because it comes from user input. */ - if (head >= ARRAY_LEN(pDispEvo->headState)) { - nvEvoLogDebug(EVO_LOG_ERROR, "Invalid head requested, head=%d.", head); + if (apiHead >= ARRAY_LEN(pDispEvo->apiHeadState)) { + nvEvoLogDebug(EVO_LOG_ERROR, "Invalid head requested, head=%d.", apiHead); return FALSE; } - pHeadState = &pDispEvo->headState[head]; - vblankSyncObjects = pHeadState->vblankSyncObjects; + pApiHeadState = &pDispEvo->apiHeadState[apiHead]; + vblankSyncObjects = pApiHeadState->vblankSyncObjects; pDevEvo = pDispEvo->pDevEvo; /* @@ -3860,33 +4104,37 @@ static NvBool EnableVblankSyncObject( * use. */ for (freeVblankSyncObjectIdx = 0; - freeVblankSyncObjectIdx < pHeadState->numVblankSyncObjectsCreated; + freeVblankSyncObjectIdx < pApiHeadState->numVblankSyncObjectsCreated; freeVblankSyncObjectIdx++) { if (!vblankSyncObjects[freeVblankSyncObjectIdx].inUse) { break; } } - if (freeVblankSyncObjectIdx == pHeadState->numVblankSyncObjectsCreated) { + if (freeVblankSyncObjectIdx == pApiHeadState->numVblankSyncObjectsCreated) { return FALSE; } /* Save the created vblank handle if it is valid. */ vblankHandle = - nvEvoCreateApiHandle(&pOpenDisp->vblankSyncObjectHandles[head], + nvEvoCreateApiHandle(&pOpenDisp->vblankSyncObjectHandles[apiHead], &vblankSyncObjects[freeVblankSyncObjectIdx]); if (vblankHandle == 0) { nvEvoLogDebug(EVO_LOG_ERROR, "Unable to create vblank handle."); return FALSE; } - if (nvHeadIsActive(pDispEvo, head)) { + if (nvApiHeadIsActive(pDispEvo, apiHead)) { + NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); + + nvAssert(head != NV_INVALID_HEAD); + /* * Instruct the hardware to enable a semaphore corresponding to this * syncpt. The Update State will be populated. */ pDevEvo->hal->ConfigureVblankSyncObject( pDevEvo, - pHeadState->timings.rasterBlankStart.y, + pDispEvo->headState[head].timings.rasterBlankStart.y, head, freeVblankSyncObjectIdx, vblankSyncObjects[freeVblankSyncObjectIdx].evoSyncpt.hCtxDma, @@ -3909,20 +4157,24 @@ static NvBool EnableVblankSyncObject( pParams->reply.vblankHandle = vblankHandle; /* Note: the syncpt ID is NOT the same as the vblank handle. */ pParams->reply.syncptId = - pHeadState->vblankSyncObjects[freeVblankSyncObjectIdx].evoSyncpt.id; + pApiHeadState->vblankSyncObjects[freeVblankSyncObjectIdx].evoSyncpt.id; return TRUE; } static void DisableAndCleanVblankSyncObject(struct NvKmsPerOpenDisp *pOpenDisp, - NvU32 head, + NvU32 apiHead, NVVblankSyncObjectRec *pVblankSyncObject, NVEvoUpdateState *pUpdateState, NvKmsVblankSyncObjectHandle handle) { NVDispEvoPtr pDispEvo = pOpenDisp->pDispEvo; - if (nvHeadIsActive(pDispEvo, head)) { + if (nvApiHeadIsActive(pDispEvo, apiHead)) { + NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); + + nvAssert(head != NV_INVALID_HEAD); + /* * Instruct the hardware to disable the semaphore corresponding to this * syncpt. The Update State will be populated. @@ -3946,7 +4198,7 @@ static void DisableAndCleanVblankSyncObject(struct NvKmsPerOpenDisp *pOpenDisp, pVblankSyncObject->enabled = FALSE; /* Remove the handle from the map. */ - nvEvoDestroyApiHandle(&pOpenDisp->vblankSyncObjectHandles[head], handle); + nvEvoDestroyApiHandle(&pOpenDisp->vblankSyncObjectHandles[apiHead], handle); } static NvBool DisableVblankSyncObject( @@ -3958,7 +4210,7 @@ static NvBool DisableVblankSyncObject( GetPerOpenDisp(pOpen, pParams->request.deviceHandle, pParams->request.dispHandle); NVVblankSyncObjectRec *pVblankSyncObject = NULL; - NvU32 head = pParams->request.head; + NvU32 apiHead = pParams->request.head; NVDevEvoPtr pDevEvo = NULL; NVEvoUpdateState updateState = { }; @@ -3978,14 +4230,14 @@ static NvBool DisableVblankSyncObject( } /* Validate requested head because it comes from user input. */ - if (head >= ARRAY_LEN(pOpenDisp->pDispEvo->headState)) { - nvEvoLogDebug(EVO_LOG_ERROR, "Invalid head requested, head=%d.", head); + if (apiHead >= ARRAY_LEN(pOpenDisp->pDispEvo->apiHeadState)) { + nvEvoLogDebug(EVO_LOG_ERROR, "Invalid head requested, head=%d.", apiHead); return FALSE; } /* Mark the indicated object as free. */ pVblankSyncObject = - nvEvoGetPointerFromApiHandle(&pOpenDisp->vblankSyncObjectHandles[head], + nvEvoGetPointerFromApiHandle(&pOpenDisp->vblankSyncObjectHandles[apiHead], pParams->request.vblankHandle); if (pVblankSyncObject == NULL) { nvEvoLogDebug(EVO_LOG_ERROR, "unable to find object with provided " @@ -3993,7 +4245,7 @@ static NvBool DisableVblankSyncObject( return FALSE; } - DisableAndCleanVblankSyncObject(pOpenDisp, head, pVblankSyncObject, + DisableAndCleanVblankSyncObject(pOpenDisp, apiHead, pVblankSyncObject, &updateState, pParams->request.vblankHandle); if (!nvIsUpdateStateEmpty(pOpenDisp->pDispEvo->pDevEvo, &updateState)) { @@ -4010,7 +4262,6 @@ static NvBool DisableVblankSyncObject( } static void NotifyVblankCallback(NVDispEvoRec *pDispEvo, - const NvU32 head, NVVBlankCallbackPtr pCallbackData) { struct NvKmsPerOpen *pEventOpenFd = pCallbackData->pUserData; @@ -4034,7 +4285,7 @@ static NvBool NotifyVblank( struct NvKmsPerOpenDisp* pOpenDisp = GetPerOpenDisp(pOpen, pParams->request.deviceHandle, pParams->request.dispHandle); - NvU32 head = pParams->request.head; + const NvU32 apiHead = pParams->request.head; pEventOpenFd = nvkms_get_per_open_data(pParams->request.unicastEvent.fd); @@ -4048,25 +4299,23 @@ static NvBool NotifyVblank( pEventOpenFd->type = NvKmsPerOpenTypeUnicastEvent; - pCallbackData = nvRegisterVBlankCallback(pOpenDisp->pDispEvo, - head, - NotifyVblankCallback, - pEventOpenFd); + pCallbackData = nvApiHeadRegisterVBlankCallback(pOpenDisp->pDispEvo, + apiHead, + NotifyVblankCallback, + pEventOpenFd); if (pCallbackData == NULL) { return NV_FALSE; } pEventOpenFd->unicastEvent.type = NvKmsUnicastEventTypeVblankNotification; pEventOpenFd->unicastEvent.e.vblankNotification.pOpenDisp = pOpenDisp; - pEventOpenFd->unicastEvent.e.vblankNotification.head = head; + pEventOpenFd->unicastEvent.e.vblankNotification.apiHead = apiHead; pEventOpenFd->unicastEvent.e.vblankNotification.hCallback - = nvEvoCreateApiHandle(&pOpenDisp->vblankCallbackHandles[head], + = nvEvoCreateApiHandle(&pOpenDisp->vblankCallbackHandles[apiHead], pCallbackData); if (pEventOpenFd->unicastEvent.e.vblankNotification.hCallback == 0) { - nvUnregisterVBlankCallback(pOpenDisp->pDispEvo, - head, - pCallbackData); + nvApiHeadUnregisterVBlankCallback(pOpenDisp->pDispEvo, pCallbackData); return NV_FALSE; } @@ -4145,7 +4394,7 @@ NvBool nvKmsIoctl( ENTRY(NVKMS_IOCTL_MOVE_CURSOR, MoveCursor), ENTRY_CUSTOM_USER(NVKMS_IOCTL_SET_LUT, SetLut), ENTRY(NVKMS_IOCTL_IDLE_BASE_CHANNEL, IdleBaseChannel), - ENTRY(NVKMS_IOCTL_FLIP, Flip), + ENTRY_CUSTOM_USER(NVKMS_IOCTL_FLIP, Flip), ENTRY(NVKMS_IOCTL_DECLARE_DYNAMIC_DPY_INTEREST, DeclareDynamicDpyInterest), ENTRY(NVKMS_IOCTL_REGISTER_SURFACE, RegisterSurface), @@ -4568,7 +4817,7 @@ ProcFsPrintClients( case NvKmsUnicastEventTypeVblankNotification: nvEvoLogInfoString(&infoString, " head : %x", - pOpen->unicastEvent.e.vblankNotification.head); + pOpen->unicastEvent.e.vblankNotification.apiHead); break; default: break; @@ -4753,7 +5002,7 @@ ProcFsPrintHeadSurface( { NVDevEvoPtr pDevEvo; NVDispEvoPtr pDispEvo; - NvU32 dispIndex, head; + NvU32 dispIndex, apiHead; NVEvoInfoStringRec infoString; FOR_ALL_EVO_DEVS(pDevEvo) { @@ -4772,9 +5021,9 @@ ProcFsPrintHeadSurface( dispIndex, pDispEvo); outString(data, buffer); - for (head = 0; head < pDevEvo->numHeads; head++) { + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { nvInitInfoString(&infoString, buffer, size); - nvHsProcFs(&infoString, pDevEvo, dispIndex, head); + nvHsProcFs(&infoString, pDevEvo, dispIndex, apiHead); nvEvoLogInfoString(&infoString, ""); outString(data, buffer); } @@ -5086,6 +5335,8 @@ static void FreeGlobalState(void) nvEvoGlobal.clientHandle); nvEvoGlobal.clientHandle = 0; } + + nvClearDpyOverrides(); } NvBool nvKmsModuleLoad(void) @@ -5295,34 +5546,11 @@ void nvSendFrameLockAttributeChangedEventEvo( } -void nvSendFlipOccurredEventEvo( - const NVDevEvoRec *pDevEvo, - NVEvoChannelMask channelMask) +void nvSendFlipOccurredEventEvo(const NVDispEvoRec *pDispEvo, + const NvU32 apiHead, const NvU32 layer) { struct NvKmsPerOpen *pOpen; const NvU32 eventType = NVKMS_EVENT_TYPE_FLIP_OCCURRED; - const NvU32 dispIndex = 0; /* XXX NVKMS TODO: need disp-scope in event */ - const NVDispEvoRec *pDispEvo = pDevEvo->pDispEvo[dispIndex]; - NvU32 head, layer; - - nvAssert(NV_EVO_CHANNEL_MASK_POPCOUNT(channelMask) == 1); - - for (head = 0; head < pDevEvo->numHeads; head++) { - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if (pDevEvo->head[head].layer[layer]->channelMask == channelMask) { - break; - } - } - - if (layer < pDevEvo->head[head].numLayers) { - break; - } - } - - if (head >= pDevEvo->numHeads) { - nvAssert(!"Bad channelMask"); - return; - } nvListForEachEntry(pOpen, &perOpenIoctlList, perOpenIoctlListEntry) { @@ -5333,7 +5561,7 @@ void nvSendFlipOccurredEventEvo( struct NvKmsPerOpenDev *pOpenDev; const struct NvKmsFlipPermissions *pFlipPermissions; - pOpenDev = DevEvoToOpenDev(pOpen, pDevEvo); + pOpenDev = DevEvoToOpenDev(pOpen, pDispEvo->pDevEvo); if (pOpenDev == NULL) { continue; @@ -5345,8 +5573,8 @@ void nvSendFlipOccurredEventEvo( pFlipPermissions = &pOpenDev->flipPermissions; - if ((pFlipPermissions->disp[dispIndex].head[head].layerMask & - NVBIT(layer)) == 0x0) { + if ((pFlipPermissions->disp[pDispEvo->displayOwner]. + head[apiHead].layerMask & NVBIT(layer)) == 0x0) { continue; } @@ -5358,7 +5586,7 @@ void nvSendFlipOccurredEventEvo( event.eventType = eventType; event.u.flipOccurred.deviceHandle = deviceHandle; event.u.flipOccurred.dispHandle = dispHandle; - event.u.flipOccurred.head = head; + event.u.flipOccurred.head = apiHead; event.u.flipOccurred.layer = layer; SendEvent(pOpen, &event); @@ -5383,7 +5611,7 @@ void nvRemoveUnicastEvent(struct NvKmsPerOpen *pOpen) NvKmsGenericHandle callbackHandle; NVVBlankCallbackPtr pCallbackData; struct NvKmsPerOpenDisp *pOpenDisp; - NvU32 head; + NvU32 apiHead; if (pOpen == NULL) { return; @@ -5406,24 +5634,23 @@ void nvRemoveUnicastEvent(struct NvKmsPerOpen *pOpen) pOpen->unicastEvent.e.vblankNotification.hCallback; pOpenDisp = pOpen->unicastEvent.e.vblankNotification.pOpenDisp; - head = pOpen->unicastEvent.e.vblankNotification.head; + apiHead = pOpen->unicastEvent.e.vblankNotification.apiHead; /* Unregister the vblank callback */ pCallbackData = - nvEvoGetPointerFromApiHandle(&pOpenDisp->vblankCallbackHandles[head], + nvEvoGetPointerFromApiHandle(&pOpenDisp->vblankCallbackHandles[apiHead], callbackHandle); - nvUnregisterVBlankCallback(pOpenDisp->pDispEvo, - head, - pCallbackData); + nvApiHeadUnregisterVBlankCallback(pOpenDisp->pDispEvo, + pCallbackData); - nvEvoDestroyApiHandle(&pOpenDisp->vblankCallbackHandles[head], + nvEvoDestroyApiHandle(&pOpenDisp->vblankCallbackHandles[apiHead], callbackHandle); /* invalidate the pOpen data */ pOpen->unicastEvent.e.vblankNotification.hCallback = 0; pOpen->unicastEvent.e.vblankNotification.pOpenDisp = NULL; - pOpen->unicastEvent.e.vblankNotification.head = NV_INVALID_HEAD; + pOpen->unicastEvent.e.vblankNotification.apiHead = NV_INVALID_HEAD; break; default: nvAssert("Invalid Unicast Event Type!"); @@ -5638,8 +5865,8 @@ void nvKmsSuspend(NvU32 gpuId) * that becomes stale after suspend. Shutting the heads down here * clears the relevant state explicitly. */ - nvShutDownHeads(pDevEvo, - NULL /* pTestFunc, shut down all heads */); + nvShutDownApiHeads(pDevEvo, + NULL /* pTestFunc, shut down all heads */); pDevEvo->skipConsoleRestore = TRUE; FreeSurfaceCtxDmasForAllOpens(pDevEvo); diff --git a/src/nvidia-modeset/src/shaders/g_ampere_shader_info.h b/src/nvidia-modeset/src/shaders/g_ampere_shader_info.h index fa9617b38..d08079068 100644 --- a/src/nvidia-modeset/src/shaders/g_ampere_shader_info.h +++ b/src/nvidia-modeset/src/shaders/g_ampere_shader_info.h @@ -1,4 +1,4 @@ -// Generated using 'Offline GLSL Shader Compiler Version 13.0.0.0.465.00.dev/gpu_drv/dev_a-14542' +// Generated using 'Offline GLSL Shader Compiler Version 13.0.0.0.530.00.dev/gpu_drv/dev_a-15624' // WARNING: This file is auto-generated! Do not hand-edit! // Instead, edit the GLSL shaders and run 'unix-build nvmake @generate'. @@ -9,7 +9,7 @@ ct_assert(NUM_PROGRAMS == 34); static const Nv3dProgramInfo AmpereProgramInfo[NUM_PROGRAMS] = { // nvidia_headsurface_vertex { .offset = 0x00000000, - .registerCount = 16, + .registerCount = 15, .type = NV3D_SHADER_TYPE_VERTEX, .constIndex = -1, .stage = NV3D_HW_SHADER_STAGE_VERTEX_B, diff --git a/src/nvidia-modeset/src/shaders/g_ampere_shaders b/src/nvidia-modeset/src/shaders/g_ampere_shaders index 2d26d21b6416edb23fdb6f16cb3bd01ad499a1d2..3ae838d516012fb2ca08d46b4a54d9cbbd6789ca 100644 GIT binary patch delta 8124 zcmeHMU2Ggz6}~_FSc+6BmeL+Bsk@8TG8)p5G zDpA%#yzs&x4eC@P$gm)#iGW5~qD2VBu5hcUst7MU(c-dNHGM#FpZb6h%Q@%H&Wv5Z zAOv+oMv9}e_s;z}_xsK{_nWm3Gix7ae(;^?P|jG`KZ0>2nHjr(fDs#^u92I1$8xVLA>Uj7oWc=FIV`C*PLncnRb6> zJ;gO|{qX(f`3xIsFjmAFvheQ)+Ja3E>~02DFjbmB8&?P}8)}qUdC(3nGabeXgZ7>c zwkEXDcEO$~=LYs0784F<)DC~Vu_KFB7-P1PBbRTn47qu>p^^PM+Fftuh+X^n9E_A3 zrI9vaB|SRk+~XdDBZ}=Uf8o$8mzji>oETUx#*7NSw{_Sx9y`V8ejHq zf7Uodn@%zs8l3=}t~=x7==MT@lc7dhjfw5B;JPz1495x^;kXpA^GQGo)5&%{>x98A z&pz?B`@tdXv=PIpSa9*nB?~_;uP>;W6N7PX?)}T4EtU) zr7`*B7(?G2)xaLkg?0@fd?7vbWq5%+vjvE_FqA}_X6U(D^HMsk#$6o3rPnSbQ|AW# zdm8sXI5{H>*3Nz|BLFhSQwW*$rwB3&&)hyk8`9M9A!K%Y&vYcQgdhV;Fr9=Jf|wwZ zOyaB5{)XGOzp(Ksm`Zydr*faCsjP1Y=oF057fvN3Uv>$7oX{JhGXaMHPjFDC!-XO| zVFs2WqNVi^orOe*UO?yKi*TUytV!>Rqc`CkW*bv`&{>M16B#2Zz|ow9(2#XUJD7Hf@GX=H#o_h{@=yaW;;=!1EzrDKqjFAEy&Q-@WB}T5HDp>b);{ zYpslK0ps)Id3+mNd$zaU3K*{|kc5oSA=*R6@3fHd+Rupbmv4rQCk)~r08-u2bBIx5 zFon5v6c%A)b*D6rw3!GQKShkE2+?!BotwybtsOAF!te-bmvEw{Gc0K`L@6=8NJmTr z=-Tb|_V@Q={QRwe@yUG1aAN#OA+&4A_*5DhPM#sgrxR!su8Hxf)NaNnlE`@KkBr~E zMT~#<7BPOOgEV~MH_eoPyDdyFv$3H_pI}5{+z5rtyc!{JAdo(V$uCCwM3^@e>GL5I zf%L}a-RT1f<$Us!NL86Qgt z6+yuh@l5HnEU4f_o6_f05L~P56c%GZEqY&N1ucm=pW}e|0u<@#Mk%ORs|1DW>NKWb z%C8WO{TH6#1~)qH6TCThFnx`c2w(Pp^-XS7TjVwnZ zSdPg`Ireb_>_k+j)aJl%Cf*(30Y7cwX;-;&B-oG_I!oW;nIi`#Mk^p=vEl#YNBqB0 zZTRjL*zLn|;{hx;I_tmX2dLhNWBFbF@f93G6&(KW{>mR#9GLF@-^=pOc3)K-?qPuy zhc+vy;&}B@5voO`EQGg!U1cu1Fr(^R$RSj5$UXP*!XC9KpAGddx{t@Cg9p9h&@9n^ z3@VNT=x;P>Y(Cux$b&iuY`(f$MjbKGIc$I17l!V#s-u^n zfL$UrQpY9Y@d;+ zBaq~A$M)~SI51t^DW_2rpCo0(^7~gsAc9P@Y4|-7L5jsl5U}7VN+oKi^3(3PuZaD0 zPk-jR7|0-{Q1(#5XC#Z%A{m61tYnZvD2w1xU)o;=q5e?r`aiiYPzUL3UKju5K+BC^ zPzYT3r3!)DZ4s!S|Gp3sN{k;BLOMIY7CU>DkpC^_|19SBmpo$E3X(kF_;yJidKBA9 z@`!PQB##17B9c6c6XE>=E^;7w6pDf5af&@H6H6Dz3PmVMvY>&04Qx?2OC!`^;%vct zPmE19%|H9LI9>0ZMr2iD{6R&e5-B2Z(tmtgJf;XWslIhYgu= z>R2y}v!4teEpTr6cdv>0kA6mY;OS)jU96*Ia@UYpz}Tjw0%m7c1_ew^fTkcAlTaWC zn$DroLm0I%Dp3%ONh%NoO{X#*N-D(WDUNCa^{0eVjwBQ+V5kxPtV#bXM`a+H7?e%+ zPXh?-T9kcAGO0(|2SOcwv!e&AFv>m#Gw_En`vh51Wgkc!ld2uQFa(lGjnxJ(^iVRX zv--d$$)p&4l7I<8GQms}N+#AL5+xJ+5lNECf%Nr~M9pMnNd}q;d=!N({KuL}4Zg|X z1Mt{F&7{6tGcms|>tD=KiL4-Dq)d_4g#X-CdAb&SyM}kWRw8*p0f+S=-{QAkF*zpv z*RRU?oKC79&e1axrYPyzPT>`q;m5T=$cM@C1x>@Rj%p$eGVyp0i*J&B;A^xg@?%N= ixodKMdMuRY>Gy&jO7UGS;orC>>p~yt{OOuJrvD4x@mziY delta 7659 zcmeHMTZ|iL75*FwaVH5dd~lS=jN4<^_7qH^FOE$_4|x7`YfHrpAn43))-5d7<pQqVjA{OS*x#zxSbvB~ z*2gt}GhqTumi`2|P^Bv55DW>tWXE9^%umMr`L}J7McS9Uc%cMiaaf-#G4_N`(`Fpdf~bylxb8Ba3&;DFanTEKGA4dXDjrWU}3%GHE`BUaRWb%8`FI$vWf z0rT+!Cv{e;#$qE3zlUIdr9kYAf1!@?08EI-Q^5pvf%xfQ0vxC@*m5O$ptchabU)!Y zuFB;puDkV_I@eqMnbkNq-PK(miha7b@e?s~3{)&tCyQf)1Ku=QvNpjcP)@^tpi!yH zSbi|xwLvz75y%e6V-wkde8Y76vkPTdHe1V*Ro9tLiq6&yl3zo)=`QVdtS4q*adw0j zuYvkqI|iGN(B>pN?#AvpYoE>%HJz@*j+SY&@|jEqj+`f@Zje3Bdm1-(A4FAmIOOl=mwWqIVr8+zWkIxJo2R$p*oQ7|kA=z>5gC-cy zIrz;3aG@k<7i@kKjWm%ShspGeT@&OH85m{VZfzV~=I(dDwQEVsGWqx@LnB<$*^laR zgULfmzK!w_jQg@>Fzak0`3=~VOtKD-e>SP1Oj~!Ibm?3ofp>;ulXz$AtQLO~B%0rC zF!!S`%?N|H(hukYU|>FoFj#$%U@-sawPU1-p{Ao5?qIf3RZ2wwcp?z#bY$8GunfQ<#G3*Ac0bbpfh1fU4`%9B#B$YtF8_ z%+9BOzHp4ppghQ0z)ntP_#?3s&5&Z`bpkUeF*E~Dk#W&1Z#b^eoXOC(xzL&?-NVhJ z85202OXUV8>)P&W)8}+Xp&{UO7GWK5y4OTb8^0hT{Y9 zd@I@iO%&~4(hmJ2vcoF0bpD5v8I0Ovoip$K#th9n+B0G#@#=_9}7u-B*dz zy*3i<>EG4SwfC;Qqc|O7#8JFHaXP1#qYP#PPRAig!3UZtPRD`}KrUX(1w;c*n`^hG z?>0`~TTpaWINh-Yr_(6Egb4$vG>F$9ZNcs78NhKmbn?w-L31C+q&d==rwPX>zu~Y& zNIcWn;iVh_(I*lj6@4UxZ1?~LQNEpf`b@Ohp&1e?r4V8N_6%%3Jg*9w=ItwlU|2W8)byI=e2&POOx zO$f^45UUiaCVlr-9^`e9%)>`mZUC0K-~;(}gL~&s@oCvLW8Rfh+-m>$etvFld)f?R zJGZ=Fe}~)N*N^c0s31#`kNCh_KEfZJDPfKbADChtAE3;Y?jVCpZ7-hU`tG~y;k@2Y z`F|r6dyNbHUMxobQhxnei^c8L-}Ad2jJ@8w{C^jXg^I@BAO6bkg<~ucKXZ`Y=&Nwt z*d;I=8?%DK@hhJbemM3E+8~>a=5!ct3wqEYp>Qm>l#Tf<4UAkmXt_|?7^!eSE#Ww8 zi@)Co;dmR`>^~5WpA^em!?D+YZU6_tsMQj{q3BoK5Z@s&+SIQiIBe}_Mf+D+0*rlh+RtL5s=$I>67SUWV!x`NGn8Y5^>cybuzns3TOCw5WX7nKfyovnXN56J0a3o` zc)jO^S>oy0nyR0}q%Yc?@a8;mG=o(~aV+RTbRDnZi8%}M)I`k(I#$$RiSn5VG?ZUa z+unvJ%!~sa!%PwC+!bn`bHuGzvvFSRsULaw|l=4y{%REHX*@Z#Qr-M z=aIyligS3+O~rX8bj(zoM@T}&d7e0;(sX2IVJt|~p@MYo0^-d+V||Og-xV4}RI7h*fL?+%hF*9ZpG7 z*3p}le%2A`fRZ=@aB?hD-$dBaGP0K8$TI+Y5V1VryiPK{!mPhn;vYzk1; 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Do not hand-edit! // Instead, edit the GLSL shaders and run 'unix-build nvmake @generate'. @@ -9,7 +9,7 @@ ct_assert(NUM_PROGRAMS == 34); static const Nv3dProgramInfo HopperProgramInfo[NUM_PROGRAMS] = { // nvidia_headsurface_vertex { .offset = 0x00000000, - .registerCount = 13, + .registerCount = 14, .type = NV3D_SHADER_TYPE_VERTEX, .constIndex = -1, .stage = NV3D_HW_SHADER_STAGE_VERTEX_B, diff --git a/src/nvidia-modeset/src/shaders/g_hopper_shaders b/src/nvidia-modeset/src/shaders/g_hopper_shaders index eb4e721e9de977c0e992c5a3efb7839aa5fd668e..449ddc9e2bb5f52043979e5f5319188bb7b0f794 100644 GIT binary patch delta 16345 zcmeHOYm8h~az5vt+mGqTz5RYn&-CqwZJZdUJ+KQbVCI2wST=YJ{D>4Oo))V_*#vCU zV}kKu_bl2xRtau9z01``WbHL82+9U~89}pAf@cTELI}przi1x@Mo6Ii03&S_MajBT zRp;JwZx45Q@3k(bxCL;e0& z;Q#S=pTTb5FQ9FSu|$QjcTAu)#x#dsHCc5o((f-Y`8$sNVIuCdQ~v<8IW+Z;_WLpT z9{yGhR&Q}WL0Qz8PiLp$D=-M3XhoQBP3#N8hU~oybS6V?m z1Wk-hF?PDaus=(9{VT0dAmX;K&ai4Lz+p=Zuxgs`&T31C>AgST1i`%wW`W;(CQTT9 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zUEoRtHMJkUNV~CgoPH&$_s6Ni=<%NtWuus&1bU5nok#}T3;5a@SOr0X9l%=ge@p|F z1ZBH(UC!;|c+s-7gOd4VQYrryDJ1R(GI)!?DFL2N5otLw6lmm7jE@^?HrGF(CQ;be|033jwQq$p&r?D_|9)c4i8Xuki&BeRj1EzIgF|k1J}noxTKDe zrS!nVxH-o5{+jBGA~fX9vTp7a}LRnc+HGl8TIryciefWI|kULv9{iU2~Ul*y}?v;tGuOFUtV1C&#{kf89zlP}d2NEFv z)O&>3+6qU^xKlRcmzE!RBGtMrW1hOLCU+kL95tSXziWd3vqMyvqo-GsB=eYI& diff --git a/src/nvidia-modeset/src/shaders/g_pascal_shader_info.h b/src/nvidia-modeset/src/shaders/g_pascal_shader_info.h index 3d62a718f..744126408 100644 --- a/src/nvidia-modeset/src/shaders/g_pascal_shader_info.h +++ b/src/nvidia-modeset/src/shaders/g_pascal_shader_info.h @@ -1,4 +1,4 @@ -// Generated using 'Offline GLSL Shader Compiler Version 13.0.0.0.465.00.dev/gpu_drv/dev_a-14542' +// Generated using 'Offline GLSL Shader Compiler Version 13.0.0.0.530.00.dev/gpu_drv/dev_a-15624' // WARNING: This file is auto-generated! Do not hand-edit! // Instead, edit the GLSL shaders and run 'unix-build nvmake @generate'. @@ -9,7 +9,7 @@ ct_assert(NUM_PROGRAMS == 34); static const Nv3dProgramInfo PascalProgramInfo[NUM_PROGRAMS] = { // nvidia_headsurface_vertex { .offset = 0x00000030, - .registerCount = 11, + .registerCount = 13, .type = NV3D_SHADER_TYPE_VERTEX, .constIndex = -1, .stage = NV3D_HW_SHADER_STAGE_VERTEX_B, @@ -322,9 +322,9 @@ static const NvU32 PascalConstantBuf0[] = { 0x000012f8, // 6.80471e-42 0x00001478, // 7.3428e-42 0x00001630, // 7.95938e-42 - 0x00001a40, // 9.41673e-42 - 0x00001de0, // 1.07171e-41 - 0x000022e0, // 1.25108e-41 + 0x00001a38, // 9.40552e-42 + 0x00001df0, // 1.07396e-41 + 0x000022f0, // 1.25332e-41 0x00002880, // 1.45287e-41 0x00002a00, // 1.50668e-41 0x00002bb8, // 1.56833e-41 @@ -346,9 +346,9 @@ static const NvU32 PascalConstantBuf2[] = { 0x000012f8, // 6.80471e-42 0x00001478, // 7.3428e-42 0x00001630, // 7.95938e-42 - 0x00001a70, // 9.48399e-42 - 0x00001e10, // 1.07844e-41 - 0x00002310, // 1.25781e-41 + 0x00001a60, // 9.46157e-42 + 0x00001e18, // 1.07956e-41 + 0x00002318, // 1.25893e-41 0x000028b0, // 1.45959e-41 0x00002a30, // 1.5134e-41 0x00002be0, // 1.57394e-41 @@ -361,9 +361,9 @@ static const NvU32 PascalConstantBuf3[] = { 0x000012f8, // 6.80471e-42 0x00001478, // 7.3428e-42 0x00001630, // 7.95938e-42 - 0x00001ab0, // 9.57367e-42 - 0x00001e50, // 1.08741e-41 - 0x00002350, // 1.26677e-41 + 0x00001aa0, // 9.55125e-42 + 0x00001e58, // 1.08853e-41 + 0x00002358, // 1.26789e-41 0x000028f0, // 1.46856e-41 0x00002a70, // 1.52237e-41 0x00002c20, // 1.58291e-41 @@ -376,9 +376,9 @@ static const NvU32 PascalConstantBuf4[] = { 0x00001300, // 6.81592e-42 0x00001480, // 7.35401e-42 0x00001638, // 7.97059e-42 - 0x00001a90, // 9.52883e-42 - 0x00001e30, // 1.08292e-41 - 0x00002330, // 1.26229e-41 + 0x00001a80, // 9.50641e-42 + 0x00001e38, // 1.08404e-41 + 0x00002338, // 1.26341e-41 0x000028d0, // 1.46408e-41 0x00002a50, // 1.51789e-41 0x00002c00, // 1.57842e-41 @@ -391,9 +391,9 @@ static const NvU32 PascalConstantBuf5[] = { 0x00001300, // 6.81592e-42 0x00001480, // 7.35401e-42 0x00001638, // 7.97059e-42 - 0x00001ad0, // 9.61851e-42 - 0x00001e70, // 1.09189e-41 - 0x00002370, // 1.27126e-41 + 0x00001ac0, // 9.59609e-42 + 0x00001e78, // 1.09301e-41 + 0x00002378, // 1.27238e-41 0x00002910, // 1.47304e-41 0x00002a90, // 1.52685e-41 0x00002c40, // 1.58739e-41 diff --git a/src/nvidia-modeset/src/shaders/g_pascal_shaders b/src/nvidia-modeset/src/shaders/g_pascal_shaders index b32308032b26abe864c22a4573c179641e9c90b6..5c9de8a51f3b2548be8484a17973f58fe4e96b80 100644 GIT binary patch delta 18270 zcmeHPU2GiJb-uH^oY@`j%-r3Xo!K8QmrQD_b%IhNY;hA5;5N3QKIDOJg4zr>wNkW= z+9$(l>jF-(>qscums;_rSf?l;T1i7h{jpW0VG#r&tuT&@yd+MLxP2%r##VqLg-A!1 zlUCyNoOAElABrl1KDFui!AJLJ&OP_ubI$#C=DX~E#qNH^K6|>eFCLf@+1QfZ_|WZuQo&Pz`lcd-KsSwSHFlN!RbK^;rtKZXkaq#+_(P<<$V zLiLgOv2GW%#AQ<%Sk?x5!g?B(c;|+-1uoYRQvM*0V{b~zBe2yoO_UuWex=#4)?#A| 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b/src/nvidia-modeset/srcs.mk index fbcca3ccc..7d63b079d 100644 --- a/src/nvidia-modeset/srcs.mk +++ b/src/nvidia-modeset/srcs.mk @@ -153,8 +153,8 @@ SRCS += ../common/unix/nvidia-3d/src/nvidia-3d-vertex-arrays.c SRCS += ../common/unix/nvidia-3d/src/nvidia-3d-volta.c SRCS += ../common/unix/nvidia-push/src/nvidia-push-init.c SRCS += ../common/unix/nvidia-push/src/nvidia-push.c -SRCS += kapi/src/nvkms-kapi-channelevent.c SRCS += kapi/src/nvkms-kapi-notifiers.c +SRCS += kapi/src/nvkms-kapi-sync.c SRCS += kapi/src/nvkms-kapi.c SRCS += lib/nvkms-format.c SRCS += lib/nvkms-sync.c @@ -167,12 +167,14 @@ SRCS_CXX += src/dp/nvdp-timer.cpp SRCS += src/g_nvkms-evo-states.c SRCS += src/nvkms-3dvision.c SRCS += src/nvkms-attributes.c +SRCS += src/nvkms-conf.c SRCS += src/nvkms-console-restore.c SRCS += src/nvkms-cursor.c SRCS += src/nvkms-cursor2.c SRCS += src/nvkms-cursor3.c SRCS += src/nvkms-difr.c SRCS += src/nvkms-dma.c +SRCS += src/nvkms-dpy-override.c SRCS += src/nvkms-dpy.c SRCS += src/nvkms-event.c SRCS += src/nvkms-evo.c @@ -183,6 +185,7 @@ SRCS += src/nvkms-flip.c SRCS += src/nvkms-framelock.c SRCS += src/nvkms-hal.c SRCS += src/nvkms-hdmi.c +SRCS += src/nvkms-hw-flip.c SRCS += src/nvkms-headsurface-3d.c SRCS += src/nvkms-headsurface-config.c SRCS += src/nvkms-headsurface-ioctl.c @@ -200,6 +203,7 @@ SRCS += src/nvkms-rm.c SRCS += src/nvkms-rmapi-dgpu.c SRCS += src/nvkms-stereo.c SRCS += src/nvkms-surface.c +SRCS += src/nvkms-utils-flip.c SRCS += src/nvkms-utils.c SRCS += src/nvkms-vrr.c SRCS += src/nvkms.c diff --git a/src/nvidia/arch/nvalloc/common/inc/dev_ctrl_defines.h b/src/nvidia/arch/nvalloc/common/inc/dev_ctrl_defines.h index 351aebe8f..ea5dad1a3 100644 --- a/src/nvidia/arch/nvalloc/common/inc/dev_ctrl_defines.h +++ b/src/nvidia/arch/nvalloc/common/inc/dev_ctrl_defines.h @@ -36,53 +36,49 @@ // giving us a total of 128 LEAF registers. // GPU vector: The 128 LEAF registers give us a total of (128*32) GPU vectors // giving us a total of 4096 GPU vectors -// +// // // Given a subtree index, the below macros give us the index of the TOP level // register and the bit within the TOP level register to program for that // subtree. // -#define NV_CTRL_INTR_SUBTREE_TO_TOP_IDX(i) ((i) / 32) -#define NV_CTRL_INTR_SUBTREE_TO_TOP_BIT(i) ((i) % 32) +#define NV_CTRL_INTR_SUBTREE_TO_TOP_IDX(i) (((NvU32)(i)) / 32) +#define NV_CTRL_INTR_SUBTREE_TO_TOP_BIT(i) (((NvU32)(i)) % 32) // // Given a subtree index, the below macros give us the two LEAF register indices // that correspond to that subtree. // -#define NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(i) ((i)*2) -#define NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(i) (((i)*2) + 1) +#define NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(i) (((NvU32)(i)) * 2) +#define NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(i) ((((NvU32)(i)) * 2) + 1) -#define NV_CTRL_INTR_LEAF_IDX_TO_SUBTREE(i) ((i)/2) +#define NV_CTRL_INTR_LEAF_IDX_TO_SUBTREE(i) (((NvU32)(i)) / 2) // // Given a LEAF register index, the below macros give us the range of GPU // interrupt vectors that correspond to those leafs. // -#define NV_CTRL_INTR_LEAF_IDX_TO_GPU_VECTOR_START(i) ((i)*32) -#define NV_CTRL_INTR_LEAF_IDX_TO_GPU_VECTOR_END(i) (((i)*32) + 31) +#define NV_CTRL_INTR_LEAF_IDX_TO_GPU_VECTOR_START(i) (((NvU32)(i)) * 32) +#define NV_CTRL_INTR_LEAF_IDX_TO_GPU_VECTOR_END(i) ((((NvU32)(i)) * 32) + 31) // // Given a GPU interrupt vector, the below macros give us the index of the // LEAF register and the bit within the LEAF register to program for that // GPU interrupt vector. // -#define NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(i) ((i) / 32) -#define NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(i) ((i) % 32) +#define NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(i) (((NvU32)(i)) / 32) +#define NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(i) (((NvU32)(i)) % 32) // // Given a GPU interrupt vector, the below macro gives us the subtree in which // it belongs. // -#define NV_CTRL_INTR_GPU_VECTOR_TO_SUBTREE(i) ((NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(i)) / 2) +#define NV_CTRL_INTR_GPU_VECTOR_TO_SUBTREE(i) \ + ((NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(i)) / 2) -// // The max number of leaf registers we expect -// This is enforced to be greater than or equal to -// (NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(NV_CPU_INTR_STALL_SUBTREE_LAST) + 1) -// for the largest NV_CPU_INTR_STALL_SUBTREE_LAST -// -#define NV_MAX_INTR_LEAVES 12 +#define NV_MAX_INTR_LEAVES 16 // In SW, this specifies an invalid interrupt vector #define NV_INTR_VECTOR_INVALID (NV_U32_MAX) diff --git a/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_emem_channels.h b/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_emem_channels.h index c4b9949e2..912eeaea5 100644 --- a/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_emem_channels.h +++ b/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_emem_channels.h @@ -33,15 +33,7 @@ // RM uses channel 0 for FSP EMEM. #define FSP_EMEM_CHANNEL_RM 0x0 -// PMU/SOE use channel 4 for FSP EMEM. -#define FSP_EMEM_CHANNEL_PMU_SOE 0x4 -#define FSP_EMEM_CHANNEL_MAX 0x8 - // EMEM channel 0 (RM) is allocated 1K bytes. #define FSP_EMEM_CHANNEL_RM_SIZE 1024 -// EMEM channel 4 (PMU/SOE) is allocated 1K bytes. -#define FSP_EMEM_CHANNEL_PMU_SOE_SIZE 1024 -#define FSP_EMEM_CHANNEL_PMU_SOE_OFFSET 4096 - #endif // _FSP_EMEM_CHANNELS_H_ diff --git a/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_nvdm_format.h b/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_nvdm_format.h index dc389f14d..40f28b31c 100644 --- a/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_nvdm_format.h +++ b/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_nvdm_format.h @@ -39,5 +39,6 @@ #define NVDM_TYPE_FSP_RESPONSE 0x15 #define NVDM_TYPE_INFOROM 0x17 #define NVDM_TYPE_SMBPBI 0x18 +#define NVDM_TYPE_UEFI_RM 0x1C #endif // _FSP_NVDM_FORMAT_H_ diff --git a/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_sr_meta.h b/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_sr_meta.h new file mode 100644 index 000000000..731c0fc13 --- /dev/null +++ b/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_sr_meta.h @@ -0,0 +1,83 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#ifndef GSP_FW_SR_META_H_ +#define GSP_FW_SR_META_H_ + +/*! + * GSP firmware SR metadata + * + * Initialized by CPU-RM and kept in Sysmem. + * Verified by Booter. + * + */ +typedef struct +{ + // + // Magic + // Use for verification by Booter + // + NvU64 magic; // = GSP_FW_SR_META_MAGIC; + + // + // Revision number + // Bumped up when we change this interface so it is not backward compatible. + // Bumped up when we revoke GSP-RM ucode + // + NvU64 revision; // = GSP_FW_SR_META_MAGIC_REVISION; + + // + // ---- Members regarding data in SYSMEM ---------------------------- + // Consumed by Booter for DMA + // + NvU64 sysmemAddrOfSuspendResumeData; + NvU64 sizeOfSuspendResumeData; + + // ---- Members for crypto ops across S/R --------------------------- + + // + // IV used for encryption of the Suspend/Resume data + // + NvU8 IV[32]; + + // + // Hash generated of the Suspend/Resume data + // + NvU8 hash[64]; + + // ---- Unused members ---------------------------------------------- + + // + // Pad structure to exactly 256 bytes (1 DMA chunk). Can replace padding with additional + // fields without incrementing revision. Padding initialized to 0. + // + NvU32 padding[32]; + +} GspFwSRMeta; + +#define GSP_FW_SR_META_REVISION 1 +#define GSP_FW_SR_META_MAGIC 0x8a3bb9e6c6c39d93ULL + +#endif // GSP_FW_SR_META_H_ diff --git a/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h b/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h index ac88094fb..9b88eb89c 100644 --- a/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h +++ b/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h @@ -139,12 +139,16 @@ typedef struct NvU32 elfCodeSize; NvU32 elfDataSize; - // Bit 0 is used to check if [VGPU-GSP] mode is active in init partition - NvU8 driverModel; + // Used during GSP-RM resume to check for revocation + NvU32 lsUcodeVersion; + + // Number of VF partitions allocating sub-heaps from the WPR heap + // Used during boot to ensure the heap is adequately sized + NvU8 gspFwHeapVfPartitionCount; // Pad structure to exactly 256 bytes. Can replace padding with additional // fields without incrementing revision. Padding initialized to 0. - NvU8 padding[11]; + NvU8 padding[7]; // BL to use for verification (i.e. Booter says OK to boot) NvU64 verified; // 0x0 -> unverified, 0xa0a0a0a0a0a0a0a0 -> verified @@ -154,7 +158,4 @@ typedef struct #define GSP_FW_WPR_META_REVISION 1 #define GSP_FW_WPR_META_MAGIC 0xdc3aae21371a60b3ULL -// Bit 0 is used to check if [VGPU-GSP] mode is active in init partition -#define DRIVERMODEL_VGPU 0 - #endif // GSP_FW_WPR_META_H_ diff --git a/src/nvidia/arch/nvalloc/common/inc/gsp/gspifpub.h b/src/nvidia/arch/nvalloc/common/inc/gsp/gspifpub.h index 46733a60e..7aba29a1d 100644 --- a/src/nvidia/arch/nvalloc/common/inc/gsp/gspifpub.h +++ b/src/nvidia/arch/nvalloc/common/inc/gsp/gspifpub.h @@ -77,9 +77,9 @@ typedef struct GSP_ACR_BOOT_GSP_RM_PARAMS */ typedef struct GSP_RM_PARAMS { - // Physical memory aperture through which bootArgsPa is accessed + // Physical memory aperture through which bootArgsOffset is accessed GSP_DMA_TARGET target; - // Physical address that will be stuffed in NV_PGSP_FALCON_MAILBOX(0|1) + // Physical offset in the memory aperture that will be passed to GSP-RM NvU64 bootArgsOffset; } GSP_RM_PARAMS; diff --git a/src/nvidia/arch/nvalloc/common/inc/inforom/ifrnvl.h b/src/nvidia/arch/nvalloc/common/inc/inforom/ifrnvl.h new file mode 100644 index 000000000..5aa462beb --- /dev/null +++ b/src/nvidia/arch/nvalloc/common/inc/inforom/ifrnvl.h @@ -0,0 +1,1271 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _IFRNVL_H_ +#define _IFRNVL_H_ + +// +// NVL - NVLINK Configuration and Error Data +// + +// Link Remote Endpoint Type +typedef enum +{ + INFOROM_NVLINK_REMOTE_TYPE_UNSUPPORTED = -1, + INFOROM_NVLINK_REMOTE_TYPE_NONE = 0, + INFOROM_NVLINK_REMOTE_TYPE_PEER = 1, + INFOROM_NVLINK_REMOTE_TYPE_SYSTEM = 2, + INFOROM_NVLINK_REMOTE_TYPE_SWITCH = 3, + INFOROM_NVLINK_REMOTE_TYPE_MAX = 3, + INFOROM_NVLINK_NUM_REMOTE_TYPES = 4 +} INFOROM_NVLINK_REMOTE_TYPE; + +// Fatal Errors +typedef enum +{ + INFOROM_NVLINK_FATAL_ERR_TYPE_UNSUPPORTED = -1, + + // + // NVLink 1.0 + // + INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_DL_DATA_PARITY = 0, + INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_DL_CTRL_PARITY = 1, + INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_PROTOCOL = 2, + INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_OVERFLOW = 3, + INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_RAM_DATA_PARITY = 4, + INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_RAM_HDR_PARITY = 5, + INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_RESP = 6, + INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_POISON = 7, + INFOROM_NVLINK_FATAL_ERR_TYPE_TL_TX_RAM_DATA_PARITY = 8, + INFOROM_NVLINK_FATAL_ERR_TYPE_TL_TX_RAM_HDR_PARITY = 9, + INFOROM_NVLINK_FATAL_ERR_TYPE_TL_TX_CREDIT = 10, + INFOROM_NVLINK_FATAL_ERR_TYPE_TL_DL_FLOW_CTRL_PARITY = 11, + INFOROM_NVLINK_FATAL_ERR_TYPE_TL_DL_HDR_PARITY = 12, + INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_RECOVERY_LONG = 13, + INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_FAULT_RAM = 14, + INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_FAULT_INTERFACE = 15, + INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_FAULT_SUBLINK_CHANGE = 16, + INFOROM_NVLINK_FATAL_ERR_TYPE_DL_RX_FAULT_SUBLINK_CHANGE = 17, + INFOROM_NVLINK_FATAL_ERR_TYPE_DL_RX_FAULT_DL_PROTOCOL = 18, + INFOROM_NVLINK_FATAL_ERR_TYPE_DL_LTSSM_FAULT = 19, + INFOROM_NVLINK_FATAL_ERR_TYPE_MAX_V1 = 19, + INFOROM_NVLINK_NUM_V1_FATAL_ERR_TYPES = 20, + + // + // NVLink 2.0 + // + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DL_DATA_PARITY = 0, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DL_CTRL_PARITY = 1, + // No direct equivalent to: _TL_RX_PROTOCOL = 2, + // No direct equivalent to: _TL_RX_OVERFLOW = 3, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RAM_DATA_PARITY = 4, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RAM_HDR_PARITY = 5, + // No direct equivalent to: _TL_RX_RESP = 6, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DATA_POISONED_PKT_RCVD = 7, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_RAM_DATA_PARITY = 8, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_RAM_HDR_PARITY = 9, + // No direct equivalent to: _TL_TX_CREDIT = 10, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_DL_FLOW_CONTROL_PARITY = 11, + // No direct equivalent to: _TL_DL_HDR_PARITY = 12, + // Identical to NVLink 1.0: _DL_TX_RECOVERY_LONG = 13, + // Identical to NVLink 1.0: _DL_TX_FAULT_RAM = 14, + // Identical to NVLink 1.0: _DL_TX_FAULT_INTERFACE = 15, + // Identical to NVLink 1.0: _DL_TX_FAULT_SUBLINK_CHANGE = 16, + // Identical to NVLink 1.0: _DL_RX_FAULT_SUBLINK_CHANGE = 17, + // Identical to NVLink 1.0: _DL_RX_FAULT_DL_PROTOCOL = 18, + // Identical to NVLink 1.0: _DL_LTSSM_FAULT = 19, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DL_HDR_PARITY = 20, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_AE_FLIT_RCVD = 21, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_BE_FLIT_RCVD = 22, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_ADDR_ALIGN = 23, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_PKT_LEN = 24, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_CMD_ENC = 25, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_DAT_LEN_ENC = 26, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_ADDR_TYPE = 27, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_RSP_STATUS = 28, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_PKT_STATUS = 29, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ = 30, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP = 31, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DAT_LEN_GT_ATOMIC_REQ_MAX_SIZE = 32, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE = 33, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE = 34, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_PO_FOR_CACHE_ATTR = 35, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_COMPRESSED_RESP = 36, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RESP_STATUS_TARGET = 37, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RESP_STATUS_UNSUPPORTED_REQUEST = 38, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_HDR_OVERFLOW = 39, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DATA_OVERFLOW = 40, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_STOMPED_PKT_RCVD = 41, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_CORRECTABLE_INTERNAL = 42, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_UNSUPPORTED_VC_OVERFLOW = 43, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_UNSUPPORTED_NVLINK_CREDIT_RELEASE = 44, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_UNSUPPORTED_NCISOC_CREDIT_RELEASE = 45, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_HDR_CREDIT_OVERFLOW = 46, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_DATA_CREDIT_OVERFLOW = 47, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_DL_REPLAY_CREDIT_OVERFLOW = 48, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_UNSUPPORTED_VC_OVERFLOW = 49, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_STOMPED_PKT_SENT = 50, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_DATA_POISONED_PKT_SENT = 51, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_RESP_STATUS_TARGET = 52, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_RESP_STATUS_UNSUPPORTED_REQUEST = 53, + INFOROM_NVLINK_FATAL_ERR_TYPE_MIF_RX_RAM_DATA_PARITY = 54, + INFOROM_NVLINK_FATAL_ERR_TYPE_MIF_RX_RAM_HDR_PARITY = 55, + INFOROM_NVLINK_FATAL_ERR_TYPE_MIF_TX_RAM_DATA_PARITY = 56, + INFOROM_NVLINK_FATAL_ERR_TYPE_MIF_TX_RAM_HDR_PARITY = 57, + INFOROM_NVLINK_FATAL_ERR_TYPE_MAX_V2 = 57, + INFOROM_NVLINK_NUM_V2_FATAL_ERR_TYPES = 58, + + // NVLink 3.0 + + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_COLLAPSED_RESPONSE = 58, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_NCISOC_HDR_ECC_DBE = 59, + INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_NCISOC_PARITY = 60, + INFOROM_NVLINK_FATAL_ERR_TYPE_DL_LTSSM_FAULT_UP = 61, + INFOROM_NVLINK_FATAL_ERR_TYPE_DL_LTSSM_FAULT_DOWN = 62, + INFOROM_NVLINK_FATAL_ERR_TYPE_MAX_V3 = 62, + INFOROM_NVLINK_NUM_V3_FATAL_ERR_TYPES = 63, + + INFOROM_NVLINK_FATAL_ERR_TYPE_MAX = 62, + INFOROM_NVLINK_NUM_FATAL_ERR_TYPES = 63, +} INFOROM_NVLINK_FATAL_ERR_TYPE; + +typedef enum +{ + // DL RX ----------------------------------------- + // Fatal Counts + INFOROM_NVLINK_DL_RX_FAULT_DL_PROTOCOL_FATAL = 0, + INFOROM_NVLINK_DL_RX_FAULT_SUBLINK_CHANGE_FATAL, + + // Correctable Accumulated Counts + INFOROM_NVLINK_DL_RX_FLIT_CRC_CORR, + INFOROM_NVLINK_DL_RX_LANE0_CRC_CORR, + INFOROM_NVLINK_DL_RX_LANE1_CRC_CORR, + INFOROM_NVLINK_DL_RX_LANE2_CRC_CORR, + INFOROM_NVLINK_DL_RX_LANE3_CRC_CORR, + INFOROM_NVLINK_DL_RX_LINK_REPLAY_EVENTS_CORR, + + // DL TX ----------------------------------------- + // Fatal Counts + INFOROM_NVLINK_DL_TX_FAULT_RAM_FATAL, + INFOROM_NVLINK_DL_TX_FAULT_INTERFACE_FATAL, + INFOROM_NVLINK_DL_TX_FAULT_SUBLINK_CHANGE_FATAL, + + // Correctable Accumulated Counts + INFOROM_NVLINK_DL_TX_LINK_REPLAY_EVENTS_CORR, + + // DL Disassociated ------------------------------ + // Fatal Counts + INFOROM_NVLINK_DL_LTSSM_FAULT_UP_FATAL, + INFOROM_NVLINK_DL_LTSSM_FAULT_DOWN_FATAL, + + // Correctable Accumulated Counts + INFOROM_NVLINK_DL_LINK_RECOVERY_EVENTS_CORR, + + // TLC RX ---------------------------------------- + // Fatal Counts + INFOROM_NVLINK_TLC_RX_DL_HDR_PARITY_ERR_FATAL, + INFOROM_NVLINK_TLC_RX_DL_DATA_PARITY_ERR_FATAL, + INFOROM_NVLINK_TLC_RX_DL_CTRL_PARITY_ERR_FATAL, + INFOROM_NVLINK_TLC_RX_INVALID_AE_FATAL, + INFOROM_NVLINK_TLC_RX_INVALID_BE_FATAL, + INFOROM_NVLINK_TLC_RX_INVALID_ADDR_ALIGN_FATAL, + INFOROM_NVLINK_TLC_RX_PKTLEN_ERR_FATAL, + INFOROM_NVLINK_TLC_RX_RSVD_PACKET_STATUS_ERR_FATAL, + INFOROM_NVLINK_TLC_RX_RSVD_CACHE_ATTR_PROBE_REQ_ERR_FATAL, + INFOROM_NVLINK_TLC_RX_RSVD_CACHE_ATTR_PROBE_RSP_ERR_FATAL, + INFOROM_NVLINK_TLC_RX_DATLEN_GT_RMW_REQ_MAX_ERR_FATAL, + INFOROM_NVLINK_TLC_RX_DATLEN_LT_ATR_RSP_MIN_ERR_FATAL, + INFOROM_NVLINK_TLC_RX_INVALID_CR_FATAL, + INFOROM_NVLINK_TLC_RX_INVALID_COLLAPSED_RESPONSE_FATAL, + INFOROM_NVLINK_TLC_RX_HDR_OVERFLOW_FATAL, + INFOROM_NVLINK_TLC_RX_DATA_OVERFLOW_FATAL, + INFOROM_NVLINK_TLC_RX_STOMP_DETECTED_FATAL, + INFOROM_NVLINK_TLC_RX_RSVD_CMD_ENC_FATAL, + INFOROM_NVLINK_TLC_RX_RSVD_DAT_LEN_ENC_FATAL, + INFOROM_NVLINK_TLC_RX_INVALID_PO_FOR_CACHE_ATTR_FATAL, + // This is only needed for NCISOC support (not used outside SoC?) + // TLC_RX_NCISOC_CREDIT_PARITY_ERR_FATAL_COUNT, + + // Non-Fatal Counts + INFOROM_NVLINK_TLC_RX_RSP_STATUS_HW_ERR_NONFATAL, + INFOROM_NVLINK_TLC_RX_RSP_STATUS_UR_ERR_NONFATAL, + INFOROM_NVLINK_TLC_RX_RSP_STATUS_PRIV_ERR_NONFATAL, + INFOROM_NVLINK_TLC_RX_POISON_NONFATAL, + INFOROM_NVLINK_TLC_RX_AN1_HEARTBEAT_TIMEOUT_NONFATAL, + INFOROM_NVLINK_TLC_RX_ILLEGAL_PRI_WRITE_NONFATAL, + + // Correctable Accumulated Counts + // These should be logged in the ECC object instead + // TLC_RX_HDR_RAM_ECC_SBE_ACCUM, + // TLC_RX_DAT0_RAM_ECC_SBE_ACCUM, + // TLC_RX_DAT1_RAM_ECC_SBE_ACCUM, + + // TLC TX ---------------------------------------- + // Fatal Counts + INFOROM_NVLINK_TLC_TX_DL_CREDIT_PARITY_ERR_FATAL, + // These should be logged in the ECC object instead + // TLC_TX_CREQ_HDR_RAM_ECC_DBE_FATAL_COUNT, + // TLC_TX_RSP_HDR_RAM_ECC_DBE_FATAL_COUNT, + // TLC_TX_RSP1_HDR_RAM_ECC_DBE_FATAL_COUNT, + // TLC_TX_COM_HDR_RAM_ECC_DBE_FATAL_COUNT, + INFOROM_NVLINK_TLC_TX_NCISOC_HDR_ECC_DBE_FATAL, + INFOROM_NVLINK_TLC_TX_NCISOC_PARITY_ERR_FATAL, + + // Non-Fatal Counts + // This is only needed for NCISOC support (not used outside SoC?) + // TLC_TX_NCISOC_DAT_ECC_DBE_NONFATAL_COUNT, + INFOROM_NVLINK_TLC_TX_ILLEGAL_PRI_WRITE_NONFATAL, + INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC0_NONFATAL, + INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC1_NONFATAL, + INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC2_NONFATAL, + INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC3_NONFATAL, + INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC4_NONFATAL, + INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC5_NONFATAL, + INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC6_NONFATAL, + INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC7_NONFATAL, + INFOROM_NVLINK_TLC_TX_POISON_NONFATAL, + INFOROM_NVLINK_TLC_TX_RSP_STATUS_HW_ERR_NONFATAL, + INFOROM_NVLINK_TLC_TX_RSP_STATUS_UR_ERR_NONFATAL, + INFOROM_NVLINK_TLC_TX_RSP_STATUS_PRIV_ERR_NONFATAL, + + // Correctable Counts + // These should be logged in the ECC object instead + // TLC_TX_CREQ_RAMS_ECC_SBE_CORR_ACCUM, + // TLC_TX_RSP_RAMS_ECC_SBE_CORR_ACCUM, + // TLC_TX_RSP1_RAMS_ECC_SBE_CORR_ACCUM, + // TLC_TX_COM_RAMS_ECC_SBE_CORR_ACCUM, + // This is only needed for NCISOC support (not used outside SoC?) + // TLC_TX_NCISOC_ECC_LIMIT_ERR_CORR_ACCUM, + + // NVLIPT Disassociated -------------------------- + // Fatal Counts + INFOROM_NVLINK_NVLIPT_SLEEP_WHILE_ACTIVE_LINK_FATAL, + INFOROM_NVLINK_NVLIPT_RSTSEQ_PHYCTL_TIMEOUT_FATAL, + INFOROM_NVLINK_NVLIPT_RSTSEQ_CLKCTL_TIMEOUT_FATAL, + INFOROM_NVLINK_NVLIPT_CLKCTL_ILLEGAL_REQUEST_FATAL, + INFOROM_NVLINK_NVLIPT_RSTSEQ_PLL_TIMEOUT_FATAL, + INFOROM_NVLINK_NVLIPT_RSTSEQ_PHYARB_TIMEOUT_FATAL, + + // Non-Fatal Counts + INFOROM_NVLINK_NVLIPT_ILLEGAL_LINK_STATE_REQUEST_NONFATAL, + INFOROM_NVLINK_NVLIPT_FAILED_MINION_REQUEST_NONFATAL, + INFOROM_NVLINK_NVLIPT_RESERVED_REQUEST_VALUE_NONFATAL, + INFOROM_NVLINK_NVLIPT_LINK_STATE_WRITE_WHILE_BUSY_NONFATAL, + INFOROM_NVLINK_NVLIPT_WRITE_TO_LOCKED_SYSTEM_REG_NONFATAL, + INFOROM_NVLINK_NVLIPT_LINK_STATE_REQUEST_TIMEOUT_NONFATAL, + + // TODO 3014908 log these in the NVL object until we have ECC object support + INFOROM_NVLINK_TLC_RX_HDR_RAM_ECC_DBE_FATAL, + INFOROM_NVLINK_TLC_RX_DAT0_RAM_ECC_DBE_FATAL, + INFOROM_NVLINK_TLC_RX_DAT1_RAM_ECC_DBE_FATAL, + INFOROM_NVLINK_TLC_TX_CREQ_DAT_RAM_ECC_DBE_NONFATAL, + INFOROM_NVLINK_TLC_TX_RSP_DAT_RAM_ECC_DBE_NONFATAL, + INFOROM_NVLINK_TLC_TX_COM_DAT_RAM_ECC_DBE_NONFATAL, + INFOROM_NVLINK_TLC_TX_RSP1_DAT_RAM_ECC_DBE_FATAL, + + // DL Interrupts ----------------------------------------- + // Fatal Counts + INFOROM_NVLINK_DL_PHY_A_FATAL, + INFOROM_NVLINK_DL_RX_CRC_COUNTER_FATAL, + INFOROM_NVLINK_DL_TX_PL_ERROR_FATAL, + INFOROM_NVLINK_DL_RX_PL_ERROR_FATAL, + + INFOROM_NVLINK_MAX_ERROR_TYPE +} INFOROM_NVLINK_ERROR_TYPES; + +#define INFOROM_NVLINK_V1_FATAL_ERR_TYPES \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_DL_DATA_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_DL_CTRL_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_PROTOCOL) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_OVERFLOW) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_RAM_DATA_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_RAM_HDR_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_RESP) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TL_RX_POISON) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TL_TX_RAM_DATA_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TL_TX_RAM_HDR_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TL_TX_CREDIT) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TL_DL_FLOW_CTRL_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TL_DL_HDR_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_RECOVERY_LONG) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_FAULT_RAM) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_FAULT_INTERFACE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_FAULT_SUBLINK_CHANGE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_RX_FAULT_SUBLINK_CHANGE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_RX_FAULT_DL_PROTOCOL) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_LTSSM_FAULT) + +#define INFOROM_NVLINK_V2_FATAL_ERR_TYPES \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DL_DATA_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DL_CTRL_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RAM_DATA_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RAM_HDR_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DATA_POISONED_PKT_RCVD) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_RAM_DATA_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_RAM_HDR_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_DL_FLOW_CONTROL_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_RECOVERY_LONG) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_FAULT_RAM) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_FAULT_INTERFACE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_FAULT_SUBLINK_CHANGE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_RX_FAULT_SUBLINK_CHANGE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_RX_FAULT_DL_PROTOCOL) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_LTSSM_FAULT) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DL_HDR_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_AE_FLIT_RCVD) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_BE_FLIT_RCVD) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_ADDR_ALIGN) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_PKT_LEN) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_CMD_ENC) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_DAT_LEN_ENC) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_ADDR_TYPE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_RSP_STATUS) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_PKT_STATUS) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DAT_LEN_GT_ATOMIC_REQ_MAX_SIZE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_PO_FOR_CACHE_ATTR) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_COMPRESSED_RESP) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RESP_STATUS_TARGET) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RESP_STATUS_UNSUPPORTED_REQUEST) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_HDR_OVERFLOW) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DATA_OVERFLOW) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_STOMPED_PKT_RCVD) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_CORRECTABLE_INTERNAL) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_UNSUPPORTED_VC_OVERFLOW) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_UNSUPPORTED_NVLINK_CREDIT_RELEASE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_UNSUPPORTED_NCISOC_CREDIT_RELEASE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_HDR_CREDIT_OVERFLOW) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_DATA_CREDIT_OVERFLOW) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_DL_REPLAY_CREDIT_OVERFLOW) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_UNSUPPORTED_VC_OVERFLOW) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_STOMPED_PKT_SENT) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_DATA_POISONED_PKT_SENT) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_RESP_STATUS_TARGET) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_RESP_STATUS_UNSUPPORTED_REQUEST) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_MIF_RX_RAM_DATA_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_MIF_RX_RAM_HDR_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_MIF_TX_RAM_DATA_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_MIF_TX_RAM_HDR_PARITY) + +#define INFOROM_NVLINK_V3_FATAL_ERR_TYPES \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DL_DATA_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DL_CTRL_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_DL_FLOW_CONTROL_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_FAULT_RAM) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_FAULT_INTERFACE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_FAULT_SUBLINK_CHANGE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_RX_FAULT_SUBLINK_CHANGE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_RX_FAULT_DL_PROTOCOL) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DL_HDR_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_AE_FLIT_RCVD) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_BE_FLIT_RCVD) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_ADDR_ALIGN) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_PKT_LEN) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_CMD_ENC) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_DAT_LEN_ENC) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_PKT_STATUS) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_PO_FOR_CACHE_ATTR) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_COMPRESSED_RESP) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_HDR_OVERFLOW) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_DATA_OVERFLOW) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_STOMPED_PKT_RCVD) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_RX_INVALID_COLLAPSED_RESPONSE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_NCISOC_HDR_ECC_DBE) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_TLC_TX_NCISOC_PARITY) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_LTSSM_FAULT_UP) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_LTSSM_FAULT_DOWN) + +#define INFOROM_NVLINK_V4_FATAL_ERR_TYPES \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_PHY_A) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_RX_CRC_COUNTER) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_TX_PL_ERROR) | \ + NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_DL_RX_PL_ERROR) + +#define INFOROM_ADD_NVLINK_FATAL_ERR_TYPE(mask, type) \ + mask |= NVBIT64(INFOROM_NVLINK_FATAL_ERR_TYPE_##type) + +typedef struct +{ + NvU32 errorsPerMinute; + NvU32 timestamp; +} INFOROM_NVLINK_ERROR_RATE; + +#define INFOROM_NVLINK_NUM_LINKS 6 + +typedef union INFOROM_NVL_OBJECT INFOROM_NVL_OBJECT, *PINFOROM_NVL_OBJECT; + +// Version 1.0 ---------------------------------------------------------------- + +// Link Remote Endpoint Type +typedef enum +{ + INFOROM_NVL_OBJECT_V1_REMOTE_TYPE_UNSUPPORTED = -1, + INFOROM_NVL_OBJECT_V1_REMOTE_TYPE_NONE = 0, + INFOROM_NVL_OBJECT_V1_REMOTE_TYPE_PEER = 1, + INFOROM_NVL_OBJECT_V1_REMOTE_TYPE_SYSTEM = 2, + INFOROM_NVL_OBJECT_V1_REMOTE_TYPE_SWITCH = 3, + INFOROM_NVL_OBJECT_V1_REMOTE_TYPE_MAX = 3, + INFOROM_NVL_OBJECT_V1_NUM_REMOTE_TYPES = 4, +} INFOROM_NVL_OBJECT_V1_REMOTE_TYPE; + +// Fatal Errors +typedef enum +{ + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_UNSUPPORTED = -1, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_TL_RX_DL_DATA_PARITY = 0, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_TL_RX_DL_CTRL_PARITY = 1, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_TL_RX_PROTOCOL = 2, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_TL_RX_OVERFLOW = 3, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_TL_RX_RAM_DATA_PARITY = 4, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_TL_RX_RAM_HDR_PARITY = 5, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_TL_RX_RESP = 6, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_TL_RX_POISON = 7, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_TL_TX_RAM_DATA_PARITY = 8, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_TL_TX_RAM_HDR_PARITY = 9, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_TL_TX_CREDIT = 10, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_TL_DL_FLOW_CTRL_PARITY = 11, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_TL_DL_HDR_PARITY = 12, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_DL_TX_RECOVERY_LONG = 13, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_DL_TX_FAULT_RAM = 14, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_DL_TX_FAULT_INTERFACE = 15, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_DL_TX_FAULT_SUBLINK_CHANGE = 16, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_DL_RX_FAULT_SUBLINK_CHANGE = 17, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_DL_RX_FAULT_DL_PROTOCOL = 18, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_DL_LTSSM_FAULT = 19, + INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX_MAX = 19, + INFOROM_NVL_OBJECT_V1_NUM_FATAL_ERR_INDICES = 20, +} INFOROM_NVL_OBJECT_V1_FATAL_ERR_INDEX; + +typedef struct INFOROM_NVL_OBJECT_V1_FATAL_ERR_DATA +{ + inforom_U008 counts[INFOROM_NVL_OBJECT_V1_NUM_FATAL_ERR_INDICES]; + inforom_U008 reserved[25]; +} INFOROM_NVL_OBJECT_V1_FATAL_ERR_DATA; + +#define INFOROM_NVL_OBJECT_V1_FATAL_ERR_DATA_FMT "45b" + +// Non-Fatal Errors +typedef struct INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_ENTRY +{ + inforom_U024 errRate; + inforom_U032 timestamp; +} INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_ENTRY; + +#define INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_FMT "td" + +#define INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_DAY_ENTRIES 5 +#define INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_DAY_INTERVAL (60*60*24) +#define INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_MONTH_ENTRIES 3 +#define INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_MONTH_INTERVAL (60*60*24*30) + +typedef struct INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_DATA +{ + INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_ENTRY maxNDaysAgo[ + INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_DAY_ENTRIES]; + INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_ENTRY maxNMonthsAgo[ + INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_MONTH_ENTRIES]; +} INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_DATA; + +#define INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_DATA_FMT \ + INFOROM_FMT_REP08(INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_FMT) + +typedef struct INFOROM_NVL_OBJECT_V1_ERR_DATA +{ + INFOROM_NVL_OBJECT_V1_FATAL_ERR_DATA fatal; + INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_DATA nonfatal; +} INFOROM_NVL_OBJECT_V1_ERR_DATA; + +#define INFOROM_NVL_OBJECT_V1_ERR_DATA_FMT \ + INFOROM_NVL_OBJECT_V1_FATAL_ERR_DATA_FMT \ + INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_DATA_FMT + +#define INFOROM_NVL_OBJECT_V1_NUM_LINKS 6 + +typedef struct INFOROM_NVL_OBJECT_V1 +{ + INFOROM_OBJECT_HEADER_V1_00 header; + inforom_U004 lastErrorRemoteType[ + INFOROM_NVL_OBJECT_V1_NUM_LINKS]; + inforom_U008 reserved1[1]; + INFOROM_NVL_OBJECT_V1_ERR_DATA errData[INFOROM_NVL_OBJECT_V1_NUM_LINKS]; + inforom_U016 padding[1]; + inforom_U032 reserved2[13]; +} INFOROM_NVL_OBJECT_V1; + +#define INFOROM_NVL_OBJECT_V1_FMT \ + INFOROM_OBJECT_HEADER_V1_00_FMT \ + "6n" /* lastRemoteType */ \ + "b" /* reserved1 */ \ + INFOROM_FMT_REP04(INFOROM_NVL_OBJECT_V1_ERR_DATA_FMT) \ + INFOROM_FMT_REP02(INFOROM_NVL_OBJECT_V1_ERR_DATA_FMT) \ + "w" /* padding */ \ + "13d" /* reserved2 */ + +#define INFOROM_NVL_OBJECT_V1_PACKED_SIZE 672 + +// Version 2.0 ---------------------------------------------------------------- + +// Link Remote Endpoint Type +typedef enum +{ + INFOROM_NVL_OBJECT_V2_REMOTE_TYPE_UNSUPPORTED = -1, + INFOROM_NVL_OBJECT_V2_REMOTE_TYPE_NONE = 0, + INFOROM_NVL_OBJECT_V2_REMOTE_TYPE_PEER = 1, + INFOROM_NVL_OBJECT_V2_REMOTE_TYPE_SYSTEM = 2, + INFOROM_NVL_OBJECT_V2_REMOTE_TYPE_SWITCH = 3, + INFOROM_NVL_OBJECT_V2_REMOTE_TYPE_MAX = 3, + INFOROM_NVL_OBJECT_V2_NUM_REMOTE_TYPES = 4, +} INFOROM_NVL_OBJECT_V2_REMOTE_TYPE; + +// Fatal Errors +typedef enum +{ + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_UNSUPPORTED = -1, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_DL_HDR_PARITY = 0, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_DL_DATA_PARITY = 1, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_DL_CTRL_PARITY = 2, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_RAM_DATA_PARITY = 3, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_RAM_HDR_PARITY = 4, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_INVALID_AE_FLIT_RCVD = 5, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_INVALID_BE_FLIT_RCVD = 6, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_INVALID_ADDR_ALIGN = 7, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_PKT_LEN = 8, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_RSVD_CMD_ENC = 9, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_RSVD_DAT_LEN_ENC = 10, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_RSVD_ADDR_TYPE = 11, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_RSVD_RSP_STATUS = 12, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_RSVD_PKT_STATUS = 13, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ = 14, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP = 15, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_DAT_LEN_GT_ATOMIC_REQ_MAX_SIZE = 16, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE = 17, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE = 18, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_INVALID_PO_FOR_CACHE_ATTR = 19, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_INVALID_COMPRESSED_RESP = 20, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_RESP_STATUS_TARGET = 21, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_RESP_STATUS_UNSUPPORTED_REQUEST = 22, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_HDR_OVERFLOW = 23, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_DATA_OVERFLOW = 24, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_STOMPED_PKT_RCVD = 25, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_DATA_POISONED_PKT_RCVD = 26, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_CORRECTABLE_INTERNAL = 27, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_UNSUPPORTED_VC_OVERFLOW = 28, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_UNSUPPORTED_NVLINK_CREDIT_RELEASE = 29, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_RX_UNSUPPORTED_NCISOC_CREDIT_RELEASE = 30, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_TX_HDR_CREDIT_OVERFLOW = 31, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_TX_DATA_CREDIT_OVERFLOW = 32, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_TX_DL_REPLAY_CREDIT_OVERFLOW = 33, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_TX_DL_FLOW_CONTROL_PARITY = 34, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_TX_RAM_HDR_PARITY = 35, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_TX_RAM_DATA_PARITY = 36, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_TX_UNSUPPORTED_VC_OVERFLOW = 37, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_TX_STOMPED_PKT_SENT = 38, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_TX_DATA_POISONED_PKT_SENT = 39, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_TX_RESP_STATUS_TARGET = 40, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_TLC_TX_RESP_STATUS_UNSUPPORTED_REQUEST = 41, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_MIF_RX_RAM_DATA_PARITY = 42, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_MIF_RX_RAM_HDR_PARITY = 43, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_MIF_TX_RAM_DATA_PARITY = 44, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_MIF_TX_RAM_HDR_PARITY = 45, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_DL_TX_RECOVERY_LONG = 46, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_DL_TX_FAULT_RAM = 47, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_DL_TX_FAULT_INTERFACE = 48, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_DL_TX_FAULT_SUBLINK_CHANGE = 49, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_DL_RX_FAULT_SUBLINK_CHANGE = 50, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_DL_RX_FAULT_DL_PROTOCOL = 51, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_DL_LTSSM_FAULT = 52, + INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX_MAX = 52, + INFOROM_NVL_OBJECT_V2_NUM_FATAL_ERR_INDICES = 53, +} INFOROM_NVL_OBJECT_V2_FATAL_ERR_INDEX; + +typedef struct INFOROM_NVL_OBJECT_V2_FATAL_ERR_DATA +{ + inforom_U008 counts[INFOROM_NVL_OBJECT_V2_NUM_FATAL_ERR_INDICES]; +} INFOROM_NVL_OBJECT_V2_FATAL_ERR_DATA; + +#define INFOROM_NVL_OBJECT_V2_FATAL_ERR_DATA_FMT "53b" + +// Non-Fatal Errors +typedef INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_ENTRY + INFOROM_NVL_OBJECT_V2_NONFATAL_ERR_RATE_ENTRY; + +#define INFOROM_NVL_OBJECT_V2_NONFATAL_ERR_RATE_FMT \ + INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_FMT + +#define INFOROM_NVL_OBJECT_V2_NONFATAL_ERR_RATE_DAY_ENTRIES \ + INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_DAY_ENTRIES +#define INFOROM_NVL_OBJECT_V2_NONFATAL_ERR_RATE_DAY_INTERVAL \ + INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_DAY_INTERVAL +#define INFOROM_NVL_OBJECT_V2_NONFATAL_ERR_RATE_MONTH_ENTRIES \ + INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_MONTH_ENTRIES +#define INFOROM_NVL_OBJECT_V2_NONFATAL_ERR_RATE_MONTH_INTERVAL \ + INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_RATE_MONTH_INTERVAL + +typedef INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_DATA + INFOROM_NVL_OBJECT_V2_NONFATAL_ERR_DATA; + +#define INFOROM_NVL_OBJECT_V2_NONFATAL_ERR_DATA_FMT \ + INFOROM_NVL_OBJECT_V1_NONFATAL_ERR_DATA_FMT + +typedef struct INFOROM_NVL_OBJECT_V2_ERR_DATA +{ + INFOROM_NVL_OBJECT_V2_FATAL_ERR_DATA fatal; + INFOROM_NVL_OBJECT_V2_NONFATAL_ERR_DATA nonfatal; +} INFOROM_NVL_OBJECT_V2_ERR_DATA; + +#define INFOROM_NVL_OBJECT_V2_ERR_DATA_FMT \ + INFOROM_NVL_OBJECT_V2_FATAL_ERR_DATA_FMT \ + INFOROM_NVL_OBJECT_V2_NONFATAL_ERR_DATA_FMT + +#define INFOROM_NVL_OBJECT_V2_NUM_LINKS INFOROM_NVL_OBJECT_V1_NUM_LINKS + +typedef struct INFOROM_NVL_OBJECT_V2 +{ + INFOROM_OBJECT_HEADER_V1_00 header; + inforom_U004 lastErrorRemoteType[ + INFOROM_NVL_OBJECT_V2_NUM_LINKS]; + inforom_U008 reserved1[1]; + INFOROM_NVL_OBJECT_V2_ERR_DATA errData[INFOROM_NVL_OBJECT_V2_NUM_LINKS]; + inforom_U016 padding[1]; + inforom_U032 reserved2[1]; +} INFOROM_NVL_OBJECT_V2; + +#define INFOROM_NVL_OBJECT_V2_FMT \ + INFOROM_OBJECT_HEADER_V1_00_FMT \ + "6n" /* lastRemoteType */ \ + "b" /* reserved1 */ \ + INFOROM_FMT_REP04(INFOROM_NVL_OBJECT_V2_ERR_DATA_FMT) \ + INFOROM_FMT_REP02(INFOROM_NVL_OBJECT_V2_ERR_DATA_FMT) \ + "w" /* padding */ \ + "d" /* reserved2 */ + +#define INFOROM_NVL_OBJECT_V2_PACKED_SIZE 672 + +// Version 3.G0 --------------------------------------------------------------- + +#define INFOROM_NVL_OBJECT_V3G_NUM_LINKS 12 +#define INFOROM_NVL_OBJECT_V3G_MAX_SEED_BUFFER_SIZE 7 + +typedef INFOROM_NVL_OBJECT_V2_REMOTE_TYPE INFOROM_NVL_OBJECT_V3_REMOTE_TYPE; + +typedef struct INFOROM_NVL_OBJECT_V3_REMOTE_DEVICE_INFO +{ + inforom_U032 lastUpdated; + NvU64_ALIGN32 remoteDeviceSID; + inforom_U008 remoteDeviceType; + inforom_U008 remoteDeviceLink; +} INFOROM_NVL_OBJECT_V3_REMOTE_DEVICE_INFO; + +#define INFOROM_NVL_OBJECT_V3_REMOTE_DEVICE_INFO_FMT "dq2b" + +typedef struct INFOROM_NVL_OBJECT_V3_MINION_DATA +{ + inforom_U032 lastUpdated; + inforom_U032 data[INFOROM_NVL_OBJECT_V3G_MAX_SEED_BUFFER_SIZE]; +} INFOROM_NVL_OBJECT_V3_MINION_DATA; + +#define INFOROM_NVL_OBJECT_V3_MINION_DATA_FMT "8d" + +typedef struct INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE +{ + inforom_U032 lastUpdated; + inforom_U032 flitCrcErrorsPerMinute; + inforom_U016 laneCrcErrorsPerMinute[4]; +} INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE; + +#define INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE_FMT "2d4w" + +typedef INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE + INFOROM_NVL_OBJECT_V3G_CORRECTABLE_ERROR_RATE_ARRAY[INFOROM_NVL_OBJECT_V3G_NUM_LINKS]; + +#define INFOROM_NVL_OBJECT_V3G_CORRECTABLE_ERROR_RATE_ARRAY_FMT \ + INFOROM_FMT_REP08(INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE_FMT) \ + INFOROM_FMT_REP04(INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE_FMT) + +typedef struct INFOROM_NVL_OBJECT_V3G_MAX_CORRECTABLE_ERROR_RATES +{ + INFOROM_NVL_OBJECT_V3G_CORRECTABLE_ERROR_RATE_ARRAY dailyMaxCorrectableErrorRates[5]; + INFOROM_NVL_OBJECT_V3G_CORRECTABLE_ERROR_RATE_ARRAY monthlyMaxCorrectableErrorRates[3]; +} INFOROM_NVL_OBJECT_V3G_MAX_CORRECTABLE_ERROR_RATES; + +#define INFOROM_NVL_OBJECT_V3G_MAX_CORRECTABLE_ERROR_RATES_FMT \ + INFOROM_FMT_REP08(INFOROM_NVL_OBJECT_V3G_CORRECTABLE_ERROR_RATE_ARRAY_FMT) + +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_NVLIPT_INSTANCE_ID 3:0 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID 7:4 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_DL0 0 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_DL1 1 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_DL2 2 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_DL3 3 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_DL4 4 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_DL5 5 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_DL(n) \ + (NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_DL0+(n)) +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_TLC0 6 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_TLC1 7 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_TLC2 8 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_TLC3 9 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_TLC4 10 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_TLC5 11 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_TLC(n) \ + (NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_TLC0+(n)) +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_MINION 12 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_NVLIPT 13 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_DIRECTION 9:8 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_DIRECTION_NA 1 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_DIRECTION_RX 2 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_DIRECTION_TX 3 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_SEVERITY 11:10 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_SEVERITY_CORRECTABLE 1 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_SEVERITY_UNCORRECTABLE_NONFATAL 2 +#define NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_SEVERITY_UNCORRECTABLE_FATAL 3 + +#define INFOROM_NVL_OBJECT_V3_NVLIPT_INSTANCE_MAX 15 +#define INFOROM_NVL_OBJECT_V3_BLOCK_ID_MAX 15 + +#define NV_INFOROM_NVL_OBJECT_V3_NVLIPT_ERROR_SUBTYPE 4:0 +#define NV_INFOROM_NVL_OBJECT_V3_NVLIPT_ERROR_LINK_ID 7:5 +#define NV_INFOROM_NVL_OBJECT_V3_NVLIPT_ERROR_LINK_ID_COMMON 7 + +// Format is ____ +// Each _ has its own subtype space. +typedef enum +{ + // DL RX ----------------------------------------- + // Fatal Counts + DL_RX_FAULT_DL_PROTOCOL_FATAL_COUNT = 0, + DL_RX_FAULT_SUBLINK_CHANGE_FATAL_COUNT, + + // Correctable Accumulated Counts + DL_RX_FLIT_CRC_CORR_ACCUM, + DL_RX_LANE0_CRC_CORR_ACCUM, + DL_RX_LANE1_CRC_CORR_ACCUM, + DL_RX_LANE2_CRC_CORR_ACCUM, + DL_RX_LANE3_CRC_CORR_ACCUM, + DL_RX_LINK_REPLAY_EVENTS_CORR_ACCUM, + + // DL TX ----------------------------------------- + // Fatal Counts + DL_TX_FAULT_RAM_FATAL_COUNT = 0, + DL_TX_FAULT_INTERFACE_FATAL_COUNT, + DL_TX_FAULT_SUBLINK_CHANGE_FATAL_COUNT, + + // Correctable Accumulated Counts + DL_TX_LINK_REPLAY_EVENTS_CORR_ACCUM, + + // DL Disassociated ------------------------------ + // Fatal Counts + DL_NA_LTSSM_FAULT_UP_FATAL_COUNT = 0, + DL_NA_LTSSM_FAULT_DOWN_FATAL_COUNT, + + // Correctable Accumulated Counts + DL_NA_LINK_RECOVERY_EVENTS_CORR_ACCUM, + + DL_NA_PHY_A_FATAL_COUNT, + DL_RX_CRC_COUNTER_FATAL_COUNT, + DL_TX_PL_ERROR_FATAL_COUNT, + DL_RX_PL_ERROR_FATAL_COUNT, + + // TLC RX ---------------------------------------- + // Fatal Counts + TLC_RX_DL_HDR_PARITY_ERR_FATAL_COUNT = 0, + TLC_RX_DL_DATA_PARITY_ERR_FATAL_COUNT, + TLC_RX_DL_CTRL_PARITY_ERR_FATAL_COUNT, + TLC_RX_INVALID_AE_FATAL_COUNT, + TLC_RX_INVALID_BE_FATAL_COUNT, + TLC_RX_INVALID_ADDR_ALIGN_FATAL_COUNT, + TLC_RX_PKTLEN_ERR_FATAL_COUNT, + TLC_RX_RSVD_PACKET_STATUS_ERR_FATAL_COUNT, + TLC_RX_RSVD_CACHE_ATTR_PROBE_REQ_ERR_FATAL_COUNT, + TLC_RX_RSVD_CACHE_ATTR_PROBE_RSP_ERR_FATAL_COUNT, + TLC_RX_DATLEN_GT_RMW_REQ_MAX_ERR_FATAL_COUNT, + TLC_RX_DATLEN_LT_ATR_RSP_MIN_ERR_FATAL_COUNT, + TLC_RX_INVALID_CR_FATAL_COUNT, + TLC_RX_INVALID_COLLAPSED_RESPONSE_FATAL_COUNT, + TLC_RX_HDR_OVERFLOW_FATAL_COUNT, + TLC_RX_DATA_OVERFLOW_FATAL_COUNT, + TLC_RX_STOMP_DETECTED_FATAL_COUNT, + TLC_RX_RSVD_CMD_ENC_FATAL_COUNT, + TLC_RX_RSVD_DAT_LEN_ENC_FATAL_COUNT, + TLC_RX_INVALID_PO_FOR_CACHE_ATTR_FATAL_COUNT, + // This is only needed for NCISOC support (not used outside SoC?) + // TLC_RX_NCISOC_CREDIT_PARITY_ERR_FATAL_COUNT, + + // Non-Fatal Counts + TLC_RX_RSP_STATUS_HW_ERR_NONFATAL_COUNT, + TLC_RX_RSP_STATUS_UR_ERR_NONFATAL_COUNT, + TLC_RX_RSP_STATUS_PRIV_ERR_NONFATAL_COUNT, + TLC_RX_POISON_NONFATAL_COUNT, + TLC_RX_AN1_HEARTBEAT_TIMEOUT_NONFATAL_COUNT, + TLC_RX_ILLEGAL_PRI_WRITE_NONFATAL_COUNT, + + // Fatal Counts addendum + TLC_RX_HDR_RAM_ECC_DBE_FATAL_COUNT, + TLC_RX_DAT0_RAM_ECC_DBE_FATAL_COUNT, + TLC_RX_DAT1_RAM_ECC_DBE_FATAL_COUNT, + + // Correctable Accumulated Counts + // These should be logged in the ECC object instead + // TLC_RX_HDR_RAM_ECC_SBE_ACCUM, + // TLC_RX_DAT0_RAM_ECC_SBE_ACCUM, + // TLC_RX_DAT1_RAM_ECC_SBE_ACCUM, + + // TLC TX ---------------------------------------- + // Fatal Counts + TLC_TX_DL_CREDIT_PARITY_ERR_FATAL_COUNT = 0, + // These should be logged in the ECC object instead + // TLC_TX_CREQ_HDR_RAM_ECC_DBE_FATAL_COUNT, + // TLC_TX_RSP_HDR_RAM_ECC_DBE_FATAL_COUNT, + // TLC_TX_RSP1_HDR_RAM_ECC_DBE_FATAL_COUNT, + // TLC_TX_COM_HDR_RAM_ECC_DBE_FATAL_COUNT, + TLC_TX_NCISOC_HDR_ECC_DBE_FATAL_COUNT, + TLC_TX_NCISOC_PARITY_ERR_FATAL_COUNT, + + // Non-Fatal Counts + // This is only needed for NCISOC support (not used outside SoC?) + // TLC_TX_NCISOC_DAT_ECC_DBE_NONFATAL_COUNT, + TLC_TX_ILLEGAL_PRI_WRITE_NONFATAL_COUNT, + TLC_TX_AN1_TIMEOUT_VC0_NONFATAL_COUNT, + TLC_TX_AN1_TIMEOUT_VC1_NONFATAL_COUNT, + TLC_TX_AN1_TIMEOUT_VC2_NONFATAL_COUNT, + TLC_TX_AN1_TIMEOUT_VC3_NONFATAL_COUNT, + TLC_TX_AN1_TIMEOUT_VC4_NONFATAL_COUNT, + TLC_TX_AN1_TIMEOUT_VC5_NONFATAL_COUNT, + TLC_TX_AN1_TIMEOUT_VC6_NONFATAL_COUNT, + TLC_TX_AN1_TIMEOUT_VC7_NONFATAL_COUNT, + TLC_TX_POISON_NONFATAL_COUNT, + TLC_TX_RSP_STATUS_HW_ERR_NONFATAL_COUNT, + TLC_TX_RSP_STATUS_UR_ERR_NONFATAL_COUNT, + TLC_TX_RSP_STATUS_PRIV_ERR_NONFATAL_COUNT, + TLC_TX_CREQ_DAT_RAM_ECC_DBE_NONFATAL_COUNT, + TLC_TX_RSP_DAT_RAM_ECC_DBE_NONFATAL_COUNT, + TLC_TX_COM_DAT_RAM_ECC_DBE_NONFATAL_COUNT, + + // Correctable Counts + // These should be logged in the ECC object instead + // TLC_TX_CREQ_RAMS_ECC_SBE_CORR_ACCUM, + // TLC_TX_RSP_RAMS_ECC_SBE_CORR_ACCUM, + // TLC_TX_RSP1_RAMS_ECC_SBE_CORR_ACCUM, + // TLC_TX_COM_RAMS_ECC_SBE_CORR_ACCUM, + // This is only needed for NCISOC support (not used outside SoC?) + // TLC_TX_NCISOC_ECC_LIMIT_ERR_CORR_ACCUM, + + // TLC TX Fatal addendum + TLC_TX_RSP1_DAT_RAM_ECC_DBE_FATAL_COUNT, + + // NVLIPT Disassociated -------------------------- + // Fatal Counts + NVLIPT_NA_SLEEP_WHILE_ACTIVE_LINK_FATAL_COUNT = 0, + NVLIPT_NA_RSTSEQ_PHYCTL_TIMEOUT_FATAL_COUNT, + NVLIPT_NA_RSTSEQ_CLKCTL_TIMEOUT_FATAL_COUNT, + NVLIPT_NA_CLKCTL_ILLEGAL_REQUEST_FATAL_COUNT, + NVLIPT_NA_RSTSEQ_PLL_TIMEOUT_FATAL_COUNT, + NVLIPT_NA_RSTSEQ_PHYARB_TIMEOUT_FATAL_COUNT, + + // Non-Fatal Counts + NVLIPT_NA_ILLEGAL_LINK_STATE_REQUEST_NONFATAL_COUNT, + NVLIPT_NA_FAILED_MINION_REQUEST_NONFATAL_COUNT, + NVLIPT_NA_RESERVED_REQUEST_VALUE_NONFATAL_COUNT, + NVLIPT_NA_LINK_STATE_WRITE_WHILE_BUSY_NONFATAL_COUNT, + NVLIPT_NA_WRITE_TO_LOCKED_SYSTEM_REG_NONFATAL_COUNT, + NVLIPT_NA_LINK_STATE_REQUEST_TIMEOUT_NONFATAL_COUNT +} INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_SUBTYPE; + +#define INFOROM_NVL_OBJECT_V3_FATAL_ERR_INDEX_UNSUPPORTED ((NvU8) NV_U8_MAX) + +typedef enum +{ + INFOROM_NVL_ERROR_TYPE_INVALID = 0, + INFOROM_NVL_ERROR_TYPE_COUNT, + INFOROM_NVL_ERROR_TYPE_ACCUM +} INFOROM_NVL_OBJECT_V3_ERROR_TYPE; + +typedef enum +{ + INFOROM_NVL_ERROR_BLOCK_TYPE_DL = 0, + INFOROM_NVL_ERROR_BLOCK_TYPE_TLC, + INFOROM_NVL_ERROR_BLOCK_TYPE_NVLIPT +} INFOROM_NVL_ERROR_BLOCK_TYPE; + +typedef struct +{ + NvU8 nvliptInstance; + NvU8 localLinkIdx; + INFOROM_NVLINK_ERROR_TYPES error; + NvU32 count; // count is used only for correctable errors +} INFOROM_NVLINK_ERROR_EVENT; + +#define INFOROM_NVL_OBJECT_MAX_SUBLINK_WIDTH 8 +typedef struct +{ + NvU16 flitCrc; + NvU8 laneCrc[INFOROM_NVL_OBJECT_MAX_SUBLINK_WIDTH]; + NvU16 rxLinkReplay; + NvU16 txLinkReplay; + NvU16 linkRecovery; +} INFOROM_NVLINK_CORRECTABLE_ERROR_COUNTS; + +typedef struct INFOROM_NVL_OBJECT_V3_ERROR_ENTRY +{ + inforom_U008 header; + inforom_U016 metadata; + inforom_U008 errorSubtype; + union + { + struct + { + inforom_U032 lastError; + inforom_U032 avgEventDelta; + inforom_U032 totalCount; + } event; + struct + { + inforom_U032 lastUpdated; + NvU64_ALIGN32 totalCount; + } accum; + } data; +} INFOROM_NVL_OBJECT_V3_ERROR_ENTRY; + +#define INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT "bwb3d" + +#define INFOROM_NVL_OBJECT_V3G_NUM_ERROR_ENTRIES 240 + +typedef struct INFOROM_NVL_OBJECT_V3G +{ + INFOROM_OBJECT_HEADER_V1_00 header; + INFOROM_NVL_OBJECT_V3_REMOTE_DEVICE_INFO remoteDeviceInfo[INFOROM_NVL_OBJECT_V3G_NUM_LINKS]; + INFOROM_NVL_OBJECT_V3_MINION_DATA minionData[INFOROM_NVL_OBJECT_V3G_NUM_LINKS]; + INFOROM_NVL_OBJECT_V3G_MAX_CORRECTABLE_ERROR_RATES maxCorrectableErrorRates; + INFOROM_NVL_OBJECT_V3_ERROR_ENTRY errorLog[INFOROM_NVL_OBJECT_V3G_NUM_ERROR_ENTRIES]; +} INFOROM_NVL_OBJECT_V3G; + +#define INFOROM_NVL_OBJECT_V3G_REMOTE_DEVICE_INFO_ARRAY_FMT \ + INFOROM_FMT_REP08(INFOROM_NVL_OBJECT_V3_REMOTE_DEVICE_INFO_FMT) \ + INFOROM_FMT_REP04(INFOROM_NVL_OBJECT_V3_REMOTE_DEVICE_INFO_FMT) + +#define INFOROM_NVL_OBJECT_V3G_MINION_DATA_ARRAY_FMT \ + INFOROM_FMT_REP08(INFOROM_NVL_OBJECT_V3_MINION_DATA_FMT) \ + INFOROM_FMT_REP04(INFOROM_NVL_OBJECT_V3_MINION_DATA_FMT) + +#define INFOROM_NVL_OBJECT_V3G_ERROR_LOG_FMT \ + INFOROM_FMT_REP128(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_FMT_REP64(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_FMT_REP32(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_FMT_REP16(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) + +#define INFOROM_NVL_OBJECT_V3G_FMT \ + INFOROM_OBJECT_HEADER_V1_00_FMT \ + INFOROM_NVL_OBJECT_V3G_REMOTE_DEVICE_INFO_ARRAY_FMT \ + INFOROM_NVL_OBJECT_V3G_MINION_DATA_ARRAY_FMT \ + INFOROM_NVL_OBJECT_V3G_MAX_CORRECTABLE_ERROR_RATES_FMT \ + INFOROM_NVL_OBJECT_V3G_ERROR_LOG_FMT + +#define INFOROM_NVL_OBJECT_V3G_PACKED_SIZE 5936 + +// Version 3.S0 --------------------------------------------------------------- +#define INFOROM_NVL_OBJECT_V3S_NUM_LINKS 36 +#define INFOROM_NVL_OBJECT_V3S_NUM_ERROR_ENTRIES 721 + +typedef INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE + INFOROM_NVL_OBJECT_V3S_CORRECTABLE_ERROR_RATE_ARRAY[INFOROM_NVL_OBJECT_V3S_NUM_LINKS]; + +#define INFOROM_NVL_OBJECT_V3S_CORRECTABLE_ERROR_RATE_ARRAY_FMT \ + INFOROM_FMT_REP32(INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE_FMT) \ + INFOROM_FMT_REP04(INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE_FMT) + +typedef struct INFOROM_NVL_OBJECT_V3S_MAX_CORRECTABLE_ERROR_RATES +{ + INFOROM_NVL_OBJECT_V3S_CORRECTABLE_ERROR_RATE_ARRAY dailyMaxCorrectableErrorRates[5]; + INFOROM_NVL_OBJECT_V3S_CORRECTABLE_ERROR_RATE_ARRAY monthlyMaxCorrectableErrorRates[3]; +} INFOROM_NVL_OBJECT_V3S_MAX_CORRECTABLE_ERROR_RATES; + +#define INFOROM_NVL_OBJECT_V3S_MAX_CORRECTABLE_ERROR_RATES_FMT \ + INFOROM_FMT_REP08(INFOROM_NVL_OBJECT_V3S_CORRECTABLE_ERROR_RATE_ARRAY_FMT) + +typedef struct INFOROM_NVL_OBJECT_V3S +{ + INFOROM_OBJECT_HEADER_V1_00 header; + INFOROM_NVL_OBJECT_V3_REMOTE_DEVICE_INFO remoteDeviceInfo[INFOROM_NVL_OBJECT_V3S_NUM_LINKS]; + INFOROM_NVL_OBJECT_V3_MINION_DATA minionData[INFOROM_NVL_OBJECT_V3S_NUM_LINKS]; + INFOROM_NVL_OBJECT_V3S_MAX_CORRECTABLE_ERROR_RATES maxCorrectableErrorRates; + INFOROM_NVL_OBJECT_V3_ERROR_ENTRY errorLog[INFOROM_NVL_OBJECT_V3S_NUM_ERROR_ENTRIES]; +} INFOROM_NVL_OBJECT_V3S; + +#define INFOROM_NVL_OBJECT_V3S_REMOTE_DEVICE_INFO_ARRAY_FMT \ + INFOROM_FMT_REP32(INFOROM_NVL_OBJECT_V3_REMOTE_DEVICE_INFO_FMT) \ + INFOROM_FMT_REP04(INFOROM_NVL_OBJECT_V3_REMOTE_DEVICE_INFO_FMT) + +#define INFOROM_NVL_OBJECT_V3S_MINION_DATA_ARRAY_FMT \ + INFOROM_FMT_REP32(INFOROM_NVL_OBJECT_V3_MINION_DATA_FMT) \ + INFOROM_FMT_REP04(INFOROM_NVL_OBJECT_V3_MINION_DATA_FMT) + +#define INFOROM_NVL_OBJECT_V3S_ERROR_LOG_FMT \ + INFOROM_FMT_REP512(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_FMT_REP128(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_FMT_REP64(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_FMT_REP16(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT + +#define INFOROM_NVL_OBJECT_V3S_FMT \ + INFOROM_OBJECT_HEADER_V1_00_FMT \ + INFOROM_NVL_OBJECT_V3S_REMOTE_DEVICE_INFO_ARRAY_FMT \ + INFOROM_NVL_OBJECT_V3S_MINION_DATA_ARRAY_FMT \ + INFOROM_NVL_OBJECT_V3S_MAX_CORRECTABLE_ERROR_RATES_FMT \ + INFOROM_NVL_OBJECT_V3S_ERROR_LOG_FMT + +#define INFOROM_NVL_OBJECT_V3S_PACKED_SIZE 17808 + +// Version 4.G0 --------------------------------------------------------------- + +#define INFOROM_NVL_OBJECT_V4G_NUM_LINKS 18 + +typedef struct INFOROM_NVL_OBJECT_V4_L1_THRESHOLD_DATA +{ + inforom_U032 word1; + inforom_U032 word2; +} INFOROM_NVL_OBJECT_V4_L1_THRESHOLD_DATA; + +#define INFOROM_NVL_OBJECT_V4_L1_THRESHOLD_DATA_FMT "2d" + +typedef INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE + INFOROM_NVL_OBJECT_V4G_CORRECTABLE_ERROR_RATE_ARRAY[INFOROM_NVL_OBJECT_V4G_NUM_LINKS]; + +#define INFOROM_NVL_OBJECT_V4G_CORRECTABLE_ERROR_RATE_ARRAY_FMT \ + INFOROM_FMT_REP16(INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE_FMT) \ + INFOROM_FMT_REP02(INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE_FMT) + +typedef struct INFOROM_NVL_OBJECT_V4G_MAX_CORRECTABLE_ERROR_RATES +{ + INFOROM_NVL_OBJECT_V4G_CORRECTABLE_ERROR_RATE_ARRAY dailyMaxCorrectableErrorRates[5]; + INFOROM_NVL_OBJECT_V4G_CORRECTABLE_ERROR_RATE_ARRAY monthlyMaxCorrectableErrorRates[3]; +} INFOROM_NVL_OBJECT_V4G_MAX_CORRECTABLE_ERROR_RATES; + +#define INFOROM_NVL_OBJECT_V4G_MAX_CORRECTABLE_ERROR_RATES_FMT \ + INFOROM_FMT_REP08(INFOROM_NVL_OBJECT_V4G_CORRECTABLE_ERROR_RATE_ARRAY_FMT) + +typedef struct INFOROM_NVL_OBJECT_V4G_RESERVED +{ + inforom_U032 reserved; +} INFOROM_NVL_OBJECT_V4G_RESERVED; + +#define INFOROM_NVL_OBJECT_V4G_RESERVED_FMT "d" + +#define INFOROM_NVL_OBJECT_V4G_NUM_ERROR_ENTRIES 364 + +typedef struct INFOROM_NVL_OBJECT_V4G +{ + INFOROM_OBJECT_HEADER_V1_00 header; + INFOROM_NVL_OBJECT_V4_L1_THRESHOLD_DATA l1ThresholdData; + INFOROM_NVL_OBJECT_V3_REMOTE_DEVICE_INFO remoteDeviceInfo[INFOROM_NVL_OBJECT_V4G_NUM_LINKS]; + INFOROM_NVL_OBJECT_V4G_MAX_CORRECTABLE_ERROR_RATES maxCorrectableErrorRates; + INFOROM_NVL_OBJECT_V3_ERROR_ENTRY errorLog[INFOROM_NVL_OBJECT_V4G_NUM_ERROR_ENTRIES]; + INFOROM_NVL_OBJECT_V4G_RESERVED reserved; +} INFOROM_NVL_OBJECT_V4G; + +#define INFOROM_NVL_OBJECT_V4G_REMOTE_DEVICE_INFO_ARRAY_FMT \ + INFOROM_FMT_REP16(INFOROM_NVL_OBJECT_V3_REMOTE_DEVICE_INFO_FMT) \ + INFOROM_FMT_REP02(INFOROM_NVL_OBJECT_V3_REMOTE_DEVICE_INFO_FMT) + +#define INFOROM_NVL_OBJECT_V4G_ERROR_LOG_FMT \ + INFOROM_FMT_REP128(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_FMT_REP128(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_FMT_REP64(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_FMT_REP32(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_FMT_REP08(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_FMT_REP04(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) + +#define INFOROM_NVL_OBJECT_V4G_FMT \ + INFOROM_OBJECT_HEADER_V1_00_FMT \ + INFOROM_NVL_OBJECT_V4G_REMOTE_DEVICE_INFO_ARRAY_FMT \ + INFOROM_NVL_OBJECT_V4_L1_THRESHOLD_DATA_FMT \ + INFOROM_NVL_OBJECT_V4G_MAX_CORRECTABLE_ERROR_RATES_FMT \ + INFOROM_NVL_OBJECT_V4G_ERROR_LOG_FMT \ + INFOROM_NVL_OBJECT_V4G_RESERVED_FMT + +#define INFOROM_NVL_OBJECT_V4G_PACKED_SIZE 8400 + +// Version 4.S0 --------------------------------------------------------------- +#define INFOROM_NVL_OBJECT_V4S_NUM_LINKS 64 +#define INFOROM_NVL_OBJECT_V4S_NUM_ERROR_ENTRIES 1286 + +typedef INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE + INFOROM_NVL_OBJECT_V4S_CORRECTABLE_ERROR_RATE_ARRAY[INFOROM_NVL_OBJECT_V4S_NUM_LINKS]; + +#define INFOROM_NVL_OBJECT_V4S_CORRECTABLE_ERROR_RATE_ARRAY_FMT \ + INFOROM_FMT_REP64(INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE_FMT) + +typedef struct INFOROM_NVL_OBJECT_V4S_MAX_CORRECTABLE_ERROR_RATES +{ + INFOROM_NVL_OBJECT_V4S_CORRECTABLE_ERROR_RATE_ARRAY dailyMaxCorrectableErrorRates[5]; + INFOROM_NVL_OBJECT_V4S_CORRECTABLE_ERROR_RATE_ARRAY monthlyMaxCorrectableErrorRates[3]; +} INFOROM_NVL_OBJECT_V4S_MAX_CORRECTABLE_ERROR_RATES; + +#define INFOROM_NVL_OBJECT_V4S_MAX_CORRECTABLE_ERROR_RATES_FMT \ + INFOROM_FMT_REP08(INFOROM_NVL_OBJECT_V4S_CORRECTABLE_ERROR_RATE_ARRAY_FMT) + +typedef struct INFOROM_NVL_OBJECT_V4S +{ + INFOROM_OBJECT_HEADER_V1_00 header; + INFOROM_NVL_OBJECT_V4_L1_THRESHOLD_DATA l1ThresholdData; + INFOROM_NVL_OBJECT_V3_REMOTE_DEVICE_INFO remoteDeviceInfo[INFOROM_NVL_OBJECT_V4S_NUM_LINKS]; + INFOROM_NVL_OBJECT_V4S_MAX_CORRECTABLE_ERROR_RATES maxCorrectableErrorRates; + INFOROM_NVL_OBJECT_V3_ERROR_ENTRY errorLog[INFOROM_NVL_OBJECT_V4S_NUM_ERROR_ENTRIES]; +} INFOROM_NVL_OBJECT_V4S; + +#define INFOROM_NVL_OBJECT_V4S_REMOTE_DEVICE_INFO_ARRAY_FMT \ + INFOROM_FMT_REP64(INFOROM_NVL_OBJECT_V3_REMOTE_DEVICE_INFO_FMT) + +#define INFOROM_NVL_OBJECT_V4S_ERROR_LOG_FMT \ + INFOROM_FMT_REP512(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_FMT_REP512(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_FMT_REP256(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_FMT_REP04(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) \ + INFOROM_FMT_REP02(INFOROM_NVL_OBJECT_V3_ERROR_ENTRY_FMT) + +#define INFOROM_NVL_OBJECT_V4S_FMT \ + INFOROM_OBJECT_HEADER_V1_00_FMT \ + INFOROM_NVL_OBJECT_V4S_REMOTE_DEVICE_INFO_ARRAY_FMT \ + INFOROM_NVL_OBJECT_V4_L1_THRESHOLD_DATA_FMT \ + INFOROM_NVL_OBJECT_V4S_MAX_CORRECTABLE_ERROR_RATES_FMT \ + INFOROM_NVL_OBJECT_V4S_ERROR_LOG_FMT + +#define INFOROM_NVL_OBJECT_V4S_PACKED_SIZE 29680 + +union INFOROM_NVL_OBJECT +{ + INFOROM_OBJECT_HEADER_V1_00 header; + INFOROM_NVL_OBJECT_V1 v1; + INFOROM_NVL_OBJECT_V2 v2; + INFOROM_NVL_OBJECT_V3G v3g; + INFOROM_NVL_OBJECT_V3S v3s; + INFOROM_NVL_OBJECT_V4G v4g; + INFOROM_NVL_OBJECT_V4S v4s; +}; + +#define INFOROM_NVL_OBJECT_FLUSH_INTERVAL (60 * 10) + +typedef struct +{ + struct + { + NvU32 flitCrc; + NvU32 laneCrc[4]; + } errorsPerMinute[INFOROM_NVL_OBJECT_V3G_NUM_LINKS]; + + struct + { + NvU32 flitCrc; + NvU32 laneCrc[4]; + NvU32 rxLinkReplay; + NvU32 txLinkReplay; + NvU32 linkRecovery; + } lastRead[INFOROM_NVL_OBJECT_V3G_NUM_LINKS]; +} INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V3G; + +typedef struct +{ + struct + { + NvU32 flitCrc; + NvU32 laneCrc[4]; + } errorsPerMinute[INFOROM_NVL_OBJECT_V3S_NUM_LINKS]; + + struct + { + NvU32 flitCrc; + NvU32 laneCrc[4]; + NvU32 rxLinkReplay; + NvU32 txLinkReplay; + NvU32 linkRecovery; + } lastRead[INFOROM_NVL_OBJECT_V3S_NUM_LINKS]; +} INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V3S; + +typedef struct +{ + struct + { + NvU32 flitCrc; + NvU32 laneCrc[4]; + } errorsPerMinute[INFOROM_NVL_OBJECT_V4G_NUM_LINKS]; + + struct + { + NvU32 flitCrc; + NvU32 laneCrc[4]; + NvU32 rxLinkReplay; + NvU32 txLinkReplay; + NvU32 linkRecovery; + } lastRead[INFOROM_NVL_OBJECT_V4G_NUM_LINKS]; +} INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V4G; + +typedef struct +{ + struct + { + NvU32 flitCrc; + NvU32 laneCrc[4]; + } errorsPerMinute[INFOROM_NVL_OBJECT_V4S_NUM_LINKS]; + + struct + { + NvU32 flitCrc; + NvU32 laneCrc[4]; + NvU32 rxLinkReplay; + NvU32 txLinkReplay; + NvU32 linkRecovery; + } lastRead[INFOROM_NVL_OBJECT_V4S_NUM_LINKS]; +} INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V4S; + + +typedef union +{ + INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V3G v3g; + INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V3S v3s; + INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V4G v4g; + INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V4S v4s; +} INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE; + +typedef struct +{ + const char *pFmt; + NvU8 *pPackedObject; + INFOROM_NVL_OBJECT *pNvl; + + NvBool bDirty; + NvBool bDisableFatalErrorLogging; + NvBool bDisableCorrectableErrorLogging; + NvBool bCallbackPending; + + NvU32 timeSinceLastFlush; + + INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE correctableErrorRateState; +} INFOROM_NVLINK_STATE, *PINFOROM_NVLINK_STATE; + +#endif /* _IFRNVL_H_ */ diff --git a/src/nvidia/arch/nvalloc/common/inc/inforom/ifrstruct.h b/src/nvidia/arch/nvalloc/common/inc/inforom/ifrstruct.h index ea174e989..f8d90fc8d 100644 --- a/src/nvidia/arch/nvalloc/common/inc/inforom/ifrstruct.h +++ b/src/nvidia/arch/nvalloc/common/inc/inforom/ifrstruct.h @@ -26,6 +26,7 @@ #include "inforom/types.h" +#include "inforom/ifrnvl.h" #include "inforom/ifrecc.h" #include "inforom/ifrdem.h" #include "inforom/omsdef.h" @@ -68,7 +69,9 @@ struct INFOROM_OBD_OBJECT_V2_XX inforom_U032 productLength; inforom_U032 productWidth; inforom_U032 productHeight; - inforom_U008 reserved[89]; + inforom_U008 vbiosFactoryVersion[5]; + inforom_U008 board965PartNumber[20]; + inforom_U008 reserved[64]; }; #define INFOROM_OBD_OBJECT_V2_XX_FMT INFOROM_OBJECT_HEADER_V1_00_FMT "d111b3d89b" typedef struct INFOROM_OBD_OBJECT_V2_XX INFOROM_OBD_OBJECT_V2_XX; diff --git a/src/nvidia/arch/nvalloc/common/inc/nv-firmware.h b/src/nvidia/arch/nvalloc/common/inc/nv-firmware.h index 3ddade5b7..d5f161bc3 100644 --- a/src/nvidia/arch/nvalloc/common/inc/nv-firmware.h +++ b/src/nvidia/arch/nvalloc/common/inc/nv-firmware.h @@ -81,12 +81,12 @@ static inline const char *nv_firmware_path( { switch (fw_chip_family) { - case NV_FIRMWARE_CHIP_FAMILY_AD10X: - return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_ad10x.bin"); + case NV_FIRMWARE_CHIP_FAMILY_AD10X: // fall through + case NV_FIRMWARE_CHIP_FAMILY_GA10X: + return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_ga10x.bin"); case NV_FIRMWARE_CHIP_FAMILY_GH100: // fall through case NV_FIRMWARE_CHIP_FAMILY_GA100: // fall through - case NV_FIRMWARE_CHIP_FAMILY_GA10X: // fall through case NV_FIRMWARE_CHIP_FAMILY_TU11X: // fall through case NV_FIRMWARE_CHIP_FAMILY_TU10X: return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_tu10x.bin"); @@ -100,12 +100,12 @@ static inline const char *nv_firmware_path( { switch (fw_chip_family) { - case NV_FIRMWARE_CHIP_FAMILY_AD10X: - return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_log_ad10x.bin"); + case NV_FIRMWARE_CHIP_FAMILY_AD10X: // fall through + case NV_FIRMWARE_CHIP_FAMILY_GA10X: + return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_log_ga10x.bin"); case NV_FIRMWARE_CHIP_FAMILY_GH100: // fall through case NV_FIRMWARE_CHIP_FAMILY_GA100: // fall through - case NV_FIRMWARE_CHIP_FAMILY_GA10X: // fall through case NV_FIRMWARE_CHIP_FAMILY_TU11X: // fall through case NV_FIRMWARE_CHIP_FAMILY_TU10X: return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_log_tu10x.bin"); @@ -125,7 +125,7 @@ static inline const char *nv_firmware_path( // which will then be invoked (at the top-level) for each // gsp_*.bin (but not gsp_log_*.bin) #if defined(NV_FIRMWARE_DECLARE_GSP_FILENAME) -NV_FIRMWARE_DECLARE_GSP_FILENAME("gsp_ad10x.bin") +NV_FIRMWARE_DECLARE_GSP_FILENAME("gsp_ga10x.bin") NV_FIRMWARE_DECLARE_GSP_FILENAME("gsp_tu10x.bin") #endif // defined(NV_FIRMWARE_DECLARE_GSP_FILENAME) diff --git a/src/nvidia/arch/nvalloc/common/inc/nvcst.h b/src/nvidia/arch/nvalloc/common/inc/nvcst.h index 92419de99..9a86d5e42 100644 --- a/src/nvidia/arch/nvalloc/common/inc/nvcst.h +++ b/src/nvidia/arch/nvalloc/common/inc/nvcst.h @@ -290,7 +290,6 @@ VENDORNAME vendorName[] = {PCI_VENDOR_ID_FUJITSU, "Fujitsu"}, {PCI_VENDOR_ID_CADENCE, "Cadence"}, {PCI_VENDOR_ID_ARM, "ARM"}, - {PCI_VENDOR_ID_ALIBABA, "Alibaba"}, {0, "Unknown"} // Indicates end of the table }; @@ -346,7 +345,6 @@ ARMCSALLOWLISTINFO armChipsetAllowListInfo[] = {PCI_VENDOR_ID_ARM, 0x0100, CS_ARM_NEOVERSEN1}, // Arm Neoverse N1 {PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN96XX}, // Marvell OCTEON CN96xx {PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN98XX}, // Marvell OCTEON CN98xx - {PCI_VENDOR_ID_ALIBABA, 0x8000, CS_ALIBABA_YITIAN}, // Alibaba Yitian // last element must have chipset CS_UNKNOWN (zero) {0, 0, CS_UNKNOWN} diff --git a/src/nvidia/arch/nvalloc/common/inc/nvpcie.h b/src/nvidia/arch/nvalloc/common/inc/nvpcie.h index 6b5c7ca75..c5c8217b9 100644 --- a/src/nvidia/arch/nvalloc/common/inc/nvpcie.h +++ b/src/nvidia/arch/nvalloc/common/inc/nvpcie.h @@ -24,6 +24,8 @@ #ifndef NVPCIE_H #define NVPCIE_H + + /**************** Resource Manager Defines and Structures ******************\ * * * Private PCI Express related defines and structures. * @@ -53,6 +55,8 @@ #define PCI_INVALID_SUBVENDORID 0xFFFF #define PCI_INVALID_SUBDEVICEID 0xFFFF +#define PCI_IS_VENDORID_VALID(id) (((id) != 0x0000) && ((id) != 0xFFFF)) + #define PCI_CLASS_BRIDGE_DEV 0x06 #define PCI_SUBCLASS_BR_HOST 0x00 #define PCI_MULTIFUNCTION 0x80 @@ -470,7 +474,8 @@ typedef struct CL_PCIE_DC_CAPABILITY_MAP_ENTRY entries[PCI_MAX_CAPS]; } CL_PCIE_DC_CAPABILITY_MAP; -struct OBJCL; +typedef struct OBJCL OBJCL; +typedef struct OBJGPU OBJGPU; // root port setup functions NV_STATUS Broadcom_HT2100_setupFunc(OBJGPU *, OBJCL*); @@ -494,6 +499,6 @@ NV_STATUS AMD_RP1630_setupFunc(OBJGPU *, OBJCL*); NV_STATUS AMD_RP1483_setupFunc(OBJGPU *, OBJCL*); // Determines if the GPU is in a multi-GPU board based on devid checks -NvBool gpuIsMultiGpuBoard(OBJGPU *, NvBool *); +NvBool gpuIsMultiGpuBoard(OBJGPU *); #endif // NVPCIE_H diff --git a/src/nvidia/arch/nvalloc/common/inc/rmlsfm.h b/src/nvidia/arch/nvalloc/common/inc/rmlsfm.h index 2e712609b..559a79a04 100644 --- a/src/nvidia/arch/nvalloc/common/inc/rmlsfm.h +++ b/src/nvidia/arch/nvalloc/common/inc/rmlsfm.h @@ -112,6 +112,10 @@ * Changes to the define needs to be reflected in path [1] * For new Falcon Id adding, we need to append to the end; * don't insert the new falcon Id in the middle. + * + * @note If a newly added Falcon has multiple instances sharing + * the same Falcon Id, the LSF_FALCON_USES_INSTANCE macro + * need to be updated. */ #define LSF_FALCON_ID_PMU (0U) #define LSF_FALCON_ID_DPU (1U) @@ -136,12 +140,15 @@ #define LSF_FALCON_ID_NVDEC_RISCV (18U) #define LSF_FALCON_ID_NVDEC_RISCV_EB (19U) #define LSF_FALCON_ID_NVJPG (20U) -#define LSF_FALCON_ID_END (21U) +#define LSF_FALCON_ID_FECS_RISCV (21U) +#define LSF_FALCON_ID_GPCCS_RISCV (22U) +#define LSF_FALCON_ID_NVJPG_RISCV_EB (23U) +#define LSF_FALCON_ID_END (24U) #define LSF_FALCON_ID_INVALID (0xFFFFFFFFU) // -// ************************ NOTIFICATION ********************************* +// ************************ NOTIFICATION ********************************* // In case anyone needs to add new LSF falconId, please must calculate // WPR header size per LSF_FALCON_ID_END. RM needs to call lsfmGetWprHeaderSizeMax_HAL // to align with acrReadSubWprHeader_HAL in ACR. Otherwise, ACR can't get correct @@ -162,7 +169,14 @@ #define LSF_FALCON_INSTANCE_INVALID (0xFFFFFFFFU) #define LSF_FALCON_INDEX_MASK_DEFAULT_0 (0x0) - +/*! + * Checks if the LSF Falcon specified by falconId uses a falconInstance to uniquely identify itself. + * Some Falcons (eg: NVENC) use separate FalconId for each instance while some (eg: NVJPG) + * shares the same falconId across all instances of that engine. Those engines require a falconInstance + * to uniquely identify it. + * @note this macro should be updated as needed whenever LSF_FALCON_ID* defines are added. See Bug: 3833461 + */ +#define LSF_FALCON_USES_INSTANCE(falconId) ((falconId == LSF_FALCON_ID_NVDEC_RISCV_EB) || (falconId == LSF_FALCON_ID_NVJPG) || (falconId == LSF_FALCON_ID_NVJPG_RISCV_EB)) /*! * Size in entries of the ucode descriptor's dependency map. @@ -358,8 +372,8 @@ typedef struct // The PMU supports the ACR task on GM20X_thru_VOLTA profiles only. // In order to prevent LSF_FALCON_ID_END changes to affect older / shipped PMU ucodes (increase of DMEM footprint) // adding PMU specific ***_END define capturing value covering all PMU profiles that this with the ACR task. -// -#define LSF_FALCON_ID_END_PMU (LSF_FALCON_ID_FBFALCON + 1) +// +#define LSF_FALCON_ID_END_PMU (LSF_FALCON_ID_FBFALCON + 1) #define LSF_WPR_HEADERS_TOTAL_SIZE_MAX_PMU (NV_ALIGN_UP((sizeof(LSF_WPR_HEADER) * LSF_FALCON_ID_END_PMU), LSF_WPR_HEADER_ALIGNMENT)) // Maximum SUB WPR header size diff --git a/src/nvidia/arch/nvalloc/unix/include/nv-ioctl.h b/src/nvidia/arch/nvalloc/unix/include/nv-ioctl.h index ffd1dee87..f2c1aab62 100644 --- a/src/nvidia/arch/nvalloc/unix/include/nv-ioctl.h +++ b/src/nvidia/arch/nvalloc/unix/include/nv-ioctl.h @@ -104,7 +104,7 @@ typedef struct nv_ioctl_rm_api_version #define NV_RM_API_VERSION_CMD_STRICT 0 #define NV_RM_API_VERSION_CMD_RELAXED '1' -#define NV_RM_API_VERSION_CMD_OVERRIDE '2' +#define NV_RM_API_VERSION_CMD_QUERY '2' #define NV_RM_API_VERSION_REPLY_UNRECOGNIZED 0 #define NV_RM_API_VERSION_REPLY_RECOGNIZED 1 diff --git a/src/nvidia/arch/nvalloc/unix/include/nv-reg.h b/src/nvidia/arch/nvalloc/unix/include/nv-reg.h index 31d3560f5..cdb51417f 100644 --- a/src/nvidia/arch/nvalloc/unix/include/nv-reg.h +++ b/src/nvidia/arch/nvalloc/unix/include/nv-reg.h @@ -699,6 +699,22 @@ #define NV_REG_ENABLE_PCIE_RELAXED_ORDERING_MODE \ NV_REG_STRING(__NV_ENABLE_PCIE_RELAXED_ORDERING_MODE) +/* + * Option: EnableResizableBar + * + * Description: + * + * When this option is enabled, the NVIDIA driver will attempt to resize + * BAR1 to match framebuffer size, or the next largest available size on + * supported machines. This is currently only implemented for Linux. + * + * Possible values: + * 0 - Do not enable PCI BAR resizing + * 1 - Enable PCI BAR resizing + */ +#define __NV_ENABLE_RESIZABLE_BAR EnableResizableBar +#define NV_REG_ENABLE_RESIZABLE_BAR NV_REG_STRING(__NV_ENABLE_RESIZABLE_BAR) + /* * Option: EnableGpuFirmware * @@ -825,6 +841,26 @@ #define NV_DMA_REMAP_PEER_MMIO_DISABLE 0x00000000 #define NV_DMA_REMAP_PEER_MMIO_ENABLE 0x00000001 +/* + * Option: NVreg_RmNvlinkBandwidth + * + * Description: + * + * This option allows user to reduce the NVLINK P2P bandwidth to save power. + * The option is in the string format. + * + * Possible string values: + * OFF: 0% bandwidth + * MIN: 15%-25% bandwidth depending on the system's NVLink topology + * HALF: 50% bandwidth + * 3QUARTER: 75% bandwidth + * FULL: 100% bandwidth (default) + * + * This option is only for Hopper+ GPU with NVLINK version 4.0. + */ +#define __NV_RM_NVLINK_BW RmNvlinkBandwidth +#define NV_RM_NVLINK_BW NV_REG_STRING(__NV_RM_NVLINK_BW) + #if defined(NV_DEFINE_REGISTRY_KEY_TABLE) /* @@ -861,6 +897,7 @@ NV_DEFINE_REG_ENTRY_GLOBAL(__NV_IGNORE_MMIO_CHECK, 0); NV_DEFINE_REG_ENTRY_GLOBAL(__NV_NVLINK_DISABLE, 0); NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_PCIE_RELAXED_ORDERING_MODE, 0); NV_DEFINE_REG_ENTRY_GLOBAL(__NV_REGISTER_PCI_DRIVER, 1); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_RESIZABLE_BAR, 0); NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_DBG_BREAKPOINT, 0); NV_DEFINE_REG_STRING_ENTRY(__NV_REGISTRY_DWORDS, NULL); @@ -870,6 +907,7 @@ NV_DEFINE_REG_STRING_ENTRY(__NV_GPU_BLACKLIST, NULL); NV_DEFINE_REG_STRING_ENTRY(__NV_TEMPORARY_FILE_PATH, NULL); NV_DEFINE_REG_STRING_ENTRY(__NV_EXCLUDED_GPUS, NULL); NV_DEFINE_REG_ENTRY(__NV_DMA_REMAP_PEER_MMIO, NV_DMA_REMAP_PEER_MMIO_ENABLE); +NV_DEFINE_REG_STRING_ENTRY(__NV_RM_NVLINK_BW, NULL); /* *----------------registry database definition---------------------- @@ -910,6 +948,7 @@ nv_parm_t nv_parms[] = { NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_REGISTER_PCI_DRIVER), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_PCIE_RELAXED_ORDERING_MODE), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_RESIZABLE_BAR), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_GPU_FIRMWARE), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_GPU_FIRMWARE_LOGS), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_DBG_BREAKPOINT), diff --git a/src/nvidia/arch/nvalloc/unix/include/nv.h b/src/nvidia/arch/nvalloc/unix/include/nv.h index c69aed13d..421204004 100644 --- a/src/nvidia/arch/nvalloc/unix/include/nv.h +++ b/src/nvidia/arch/nvalloc/unix/include/nv.h @@ -315,6 +315,7 @@ typedef enum NV_SOC_IRQ_DPAUX_TYPE, NV_SOC_IRQ_GPIO_TYPE, NV_SOC_IRQ_HDACODEC_TYPE, + NV_SOC_IRQ_TCPC2DISP_TYPE, NV_SOC_IRQ_INVALID_TYPE } nv_soc_irq_type_t; @@ -329,6 +330,7 @@ typedef struct nv_soc_irq_info_s { NvU32 gpio_num; NvU32 dpaux_instance; } irq_data; + NvS32 ref_count; } nv_soc_irq_info_t; #define NV_MAX_SOC_IRQS 6 @@ -384,9 +386,11 @@ typedef struct nv_state_t NvS32 current_soc_irq; NvU32 num_soc_irqs; NvU32 hdacodec_irq; + NvU32 tcpc2disp_irq; NvU8 *soc_dcb_blob; NvU32 soc_dcb_size; NvU32 disp_sw_soc_chip_id; + NvBool soc_is_dpalt_mode_supported; NvU32 igpu_stall_irq[NV_IGPU_MAX_STALL_IRQS]; NvU32 igpu_nonstall_irq; @@ -649,7 +653,8 @@ static inline NvBool IS_REG_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length) static inline NvBool IS_FB_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length) { - return ((nv->fb) && (offset >= nv->fb->cpu_address) && + return ((nv->fb) && (nv->fb->size != 0) && + (offset >= nv->fb->cpu_address) && ((offset + (length - 1)) >= offset) && ((offset + (length - 1)) <= (nv->fb->cpu_address + (nv->fb->size - 1)))); } @@ -739,7 +744,7 @@ nv_state_t* NV_API_CALL nv_get_ctl_state (void); void NV_API_CALL nv_set_dma_address_size (nv_state_t *, NvU32 ); NV_STATUS NV_API_CALL nv_alias_pages (nv_state_t *, NvU32, NvU32, NvU32, NvU64, NvU64 *, void **); -NV_STATUS NV_API_CALL nv_alloc_pages (nv_state_t *, NvU32, NvBool, NvU32, NvBool, NvBool, NvU64 *, void **); +NV_STATUS NV_API_CALL nv_alloc_pages (nv_state_t *, NvU32, NvBool, NvU32, NvBool, NvBool, NvS32, NvU64 *, void **); NV_STATUS NV_API_CALL nv_free_pages (nv_state_t *, NvU32, NvBool, NvU32, void *); NV_STATUS NV_API_CALL nv_register_user_pages (nv_state_t *, NvU64, NvU64 *, void *, void **); @@ -915,7 +920,6 @@ NV_STATUS NV_API_CALL rm_write_registry_string (nvidia_stack_t *, nv_state_t * void NV_API_CALL rm_parse_option_string (nvidia_stack_t *, const char *); char* NV_API_CALL rm_remove_spaces (const char *); char* NV_API_CALL rm_string_token (char **, const char); -void NV_API_CALL rm_vgpu_vfio_set_driver_vm(nvidia_stack_t *, NvBool); NV_STATUS NV_API_CALL rm_run_rc_callback (nvidia_stack_t *, nv_state_t *); void NV_API_CALL rm_execute_work_item (nvidia_stack_t *, void *); @@ -985,11 +989,12 @@ const char* NV_API_CALL rm_get_dynamic_power_management_status(nvidia_stack_t *, const char* NV_API_CALL rm_get_gpu_gcx_support(nvidia_stack_t *, nv_state_t *, NvBool); void NV_API_CALL rm_acpi_notify(nvidia_stack_t *, nv_state_t *, NvU32); +void NV_API_CALL rm_acpi_nvpcf_notify(nvidia_stack_t *); NvBool NV_API_CALL rm_is_altstack_in_use(void); /* vGPU VFIO specific functions */ -NV_STATUS NV_API_CALL nv_vgpu_create_request(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU32, NvU16 *, NvU32); +NV_STATUS NV_API_CALL nv_vgpu_create_request(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU32, NvU16 *, NvU32, NvBool *); NV_STATUS NV_API_CALL nv_vgpu_delete(nvidia_stack_t *, const NvU8 *, NvU16); NV_STATUS NV_API_CALL nv_vgpu_get_type_ids(nvidia_stack_t *, nv_state_t *, NvU32 *, NvU32 *, NvBool, NvU8, NvBool); NV_STATUS NV_API_CALL nv_vgpu_get_type_info(nvidia_stack_t *, nv_state_t *, NvU32, char *, int, NvU8); diff --git a/src/nvidia/arch/nvalloc/unix/include/os-interface.h b/src/nvidia/arch/nvalloc/unix/include/os-interface.h index 9ebeeed83..588092f61 100644 --- a/src/nvidia/arch/nvalloc/unix/include/os-interface.h +++ b/src/nvidia/arch/nvalloc/unix/include/os-interface.h @@ -181,7 +181,6 @@ NV_STATUS NV_API_CALL os_put_page (NvU64 address); NvU32 NV_API_CALL os_get_page_refcount (NvU64 address); NvU32 NV_API_CALL os_count_tail_pages (NvU64 address); void NV_API_CALL os_free_pages_phys (NvU64, NvU32); -NV_STATUS NV_API_CALL os_call_nv_vmbus (NvU32, void *); NV_STATUS NV_API_CALL os_open_temporary_file (void **); void NV_API_CALL os_close_file (void *); NV_STATUS NV_API_CALL os_write_file (void *, NvU8 *, NvU64, NvU64); diff --git a/src/nvidia/arch/nvalloc/unix/include/osfuncs.h b/src/nvidia/arch/nvalloc/unix/include/osfuncs.h index 7afbf6373..19f2fa28a 100644 --- a/src/nvidia/arch/nvalloc/unix/include/osfuncs.h +++ b/src/nvidia/arch/nvalloc/unix/include/osfuncs.h @@ -39,13 +39,6 @@ OSDbgBreakpointEnabled osDbgBreakpointEnabled; void* osGetStereoDongleInterface(void); -OSCallACPI_DSM osCallACPI_DSM; -OSCallACPI_DDC osCallACPI_DDC; -OSCallACPI_NVHG_ROM osCallACPI_NVHG_ROM; -OSCallACPI_DOD osCallACPI_DOD; -OSCallACPI_MXDS osCallACPI_MXDS; -OSCallACPI_MXDM osCallACPI_MXDM; - #if defined(NVCPU_X86_64) OSnv_rdcr4 nv_rdcr4; NvU64 nv_rdcr3(OBJOS *); diff --git a/src/nvidia/arch/nvalloc/unix/src/dynamic-power.c b/src/nvidia/arch/nvalloc/unix/src/dynamic-power.c new file mode 100644 index 000000000..ad8684ca2 --- /dev/null +++ b/src/nvidia/arch/nvalloc/unix/src/dynamic-power.c @@ -0,0 +1,210 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include + +#include +#include +#include +#include +#include + +#include + +#include +#include +#include "kernel/gpu/intr/intr.h" + +// +// Function to update fixed fbsr modes to support multiple vairants such as +// GCOFF and cuda S3/resume. +// +static void +RmUpdateFixedFbsrModes(OBJGPU *pGpu) +{ + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERING)) + { + pMemoryManager->fixedFbsrModesMask = NVBIT(FBSR_TYPE_DMA); + } + else if (nv->preserve_vidmem_allocations) + { + pMemoryManager->fixedFbsrModesMask = NVBIT(FBSR_TYPE_FILE); + } +} + +static NV_STATUS +RmPowerManagementInternal( + OBJGPU *pGpu, + nv_pm_action_t pmAction +) +{ + // default to NV_OK. there may cases where resman is loaded, but + // no devices are allocated (we're still at the console). in these + // cases, it's fine to let the system do whatever it wants. + NV_STATUS rmStatus = NV_OK; + + if (pGpu) + { + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvBool bcState = gpumgrGetBcEnabledStatus(pGpu); + Intr *pIntr = GPU_GET_INTR(pGpu); + + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + if ((pmAction == NV_PM_ACTION_HIBERNATE) || (pmAction == NV_PM_ACTION_STANDBY)) + { + // + // pFb object store the FBSR mode through which FB state unload has happened, + // so os layer doesn't need to set FBSR mode on resume. + // + RmUpdateFixedFbsrModes(pGpu); + } + + switch (pmAction) + { + case NV_PM_ACTION_HIBERNATE: + nvp->pm_state.InHibernate = NV_TRUE; + nvp->pm_state.IntrEn = intrGetIntrEn(pIntr); + intrSetIntrEn(pIntr, INTERRUPT_TYPE_DISABLED); + gpumgrSetBcEnabledStatus(pGpu, NV_FALSE); + + rmStatus = gpuEnterHibernate(pGpu); + gpumgrSetBcEnabledStatus(pGpu, bcState); + + break; + + case NV_PM_ACTION_STANDBY: + nvp->pm_state.InHibernate = NV_FALSE; + nvp->pm_state.IntrEn = intrGetIntrEn(pIntr); + intrSetIntrEn(pIntr, INTERRUPT_TYPE_DISABLED); + gpumgrSetBcEnabledStatus(pGpu, NV_FALSE); + + rmStatus = gpuEnterStandby(pGpu); + gpumgrSetBcEnabledStatus(pGpu, bcState); + + break; + + case NV_PM_ACTION_RESUME: + gpumgrSetBcEnabledStatus(pGpu, NV_FALSE); + + if (nvp->pm_state.InHibernate) + { + gpuResumeFromHibernate(pGpu); + } + else + { + gpuResumeFromStandby(pGpu); + } + intrSetIntrEn(pIntr, nvp->pm_state.IntrEn); + gpumgrSetBcEnabledStatus(pGpu, bcState); + NvU32 ac_plugged = 0; + + if (IsMobile(pGpu)) + { + if (nv_acpi_get_powersource(&ac_plugged) == NV_OK) + { + // + // As we have already acquired API and GPU lock here, we are + // directly calling RmPowerSourceChangeEvent. + // + RmPowerSourceChangeEvent(nv, !ac_plugged); + } + } + break; + + default: + rmStatus = NV_ERR_INVALID_ARGUMENT; + break; + } + pMemoryManager->fixedFbsrModesMask = 0; + } + + return rmStatus; +} + +static NV_STATUS +RmPowerManagement( + OBJGPU *pGpu, + nv_pm_action_t pmAction +) +{ + NV_STATUS rmStatus; + + rmStatus = RmPowerManagementInternal(pGpu, pmAction); + + return rmStatus; +} + +NV_STATUS NV_API_CALL rm_power_management( + nvidia_stack_t *sp, + nv_state_t *pNv, + nv_pm_action_t pmAction +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus = NV_OK; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + NV_ASSERT_OK(os_flush_work_queue(pNv->queue)); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER)) == NV_OK) + { + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv); + + if (pGpu != NULL) + { + if ((rmStatus = os_ref_dynamic_power(pNv, NV_DYNAMIC_PM_FINE)) == NV_OK) + { + // LOCK: acquire GPUs lock + if ((rmStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER)) == NV_OK) + { + { + rmStatus = RmPowerManagement(pGpu, pmAction); + } + + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + } + os_unref_dynamic_power(pNv, NV_DYNAMIC_PM_FINE); + } + } + // UNLOCK: release API lock + rmapiLockRelease(); + } + + NV_ASSERT_OK(os_flush_work_queue(pNv->queue)); + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + + diff --git a/src/nvidia/arch/nvalloc/unix/src/escape.c b/src/nvidia/arch/nvalloc/unix/src/escape.c index c7b451a46..3e70c449f 100644 --- a/src/nvidia/arch/nvalloc/unix/src/escape.c +++ b/src/nvidia/arch/nvalloc/unix/src/escape.c @@ -70,7 +70,7 @@ static NvBool RmIsDeviceRefNeeded(NVOS54_PARAMETERS *pApi) { switch(pApi->cmd) { - case NV00FD_CTRL_CMD_ATTACH_MEM: + case NV00FD_CTRL_CMD_ATTACH_GPU: return NV_TRUE; default: return NV_FALSE; @@ -88,8 +88,8 @@ static NV_STATUS RmGetDeviceFd(NVOS54_PARAMETERS *pApi, NvS32 *pFd) switch(pApi->cmd) { - case NV00FD_CTRL_CMD_ATTACH_MEM: - paramSize = sizeof(NV00FD_CTRL_ATTACH_MEM_PARAMS); + case NV00FD_CTRL_CMD_ATTACH_GPU: + paramSize = sizeof(NV00FD_CTRL_ATTACH_GPU_PARAMS); break; default: return NV_ERR_INVALID_ARGUMENT; @@ -103,8 +103,8 @@ static NV_STATUS RmGetDeviceFd(NVOS54_PARAMETERS *pApi, NvS32 *pFd) switch(pApi->cmd) { - case NV00FD_CTRL_CMD_ATTACH_MEM: - *pFd = (NvS32)((NV00FD_CTRL_ATTACH_MEM_PARAMS *)pKernelParams)->devDescriptor; + case NV00FD_CTRL_CMD_ATTACH_GPU: + *pFd = (NvS32)((NV00FD_CTRL_ATTACH_GPU_PARAMS *)pKernelParams)->devDescriptor; break; default: NV_ASSERT(0); diff --git a/src/nvidia/arch/nvalloc/unix/src/exports-stubs.c b/src/nvidia/arch/nvalloc/unix/src/exports-stubs.c index 4dac378a6..2ccc9c523 100644 --- a/src/nvidia/arch/nvalloc/unix/src/exports-stubs.c +++ b/src/nvidia/arch/nvalloc/unix/src/exports-stubs.c @@ -83,15 +83,6 @@ NV_STATUS NV_API_CALL rm_transition_dynamic_power( return NV_OK; } -NV_STATUS NV_API_CALL rm_power_management( - nvidia_stack_t *sp, - nv_state_t *pNv, - nv_pm_action_t pmAction -) -{ - return NV_OK; -} - const char* NV_API_CALL rm_get_vidmem_power_status( nvidia_stack_t *sp, nv_state_t *pNv diff --git a/src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c b/src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c index 980308d34..0ad10b898 100644 --- a/src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c +++ b/src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c @@ -447,11 +447,14 @@ NV_STATUS NV_API_CALL nv_vgpu_create_request( const NvU8 *pMdevUuid, NvU32 vgpuTypeId, NvU16 *vgpuId, - NvU32 gpuPciBdf + NvU32 gpuPciBdf, + NvBool *is_driver_vm ) { THREAD_STATE_NODE threadState; + OBJSYS *pSys = SYS_GET_INSTANCE(); void *fp = NULL; + OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); NV_STATUS rmStatus = NV_OK; NV_ENTER_RM_RUNTIME(sp,fp); @@ -463,6 +466,8 @@ NV_STATUS NV_API_CALL nv_vgpu_create_request( rmStatus = kvgpumgrCreateRequestVgpu(pNv->gpu_id, pMdevUuid, vgpuTypeId, vgpuId, gpuPciBdf); + *is_driver_vm = pHypervisor->getProperty(pHypervisor, PDB_PROP_HYPERVISOR_DRIVERVM_ENABLED); + // UNLOCK: release API lock rmapiLockRelease(); } @@ -979,6 +984,9 @@ NV_STATUS osIsVgpuVfioPresent(void) void initVGXSpecificRegistry(OBJGPU *pGpu) { NvU32 data32; + osWriteRegistryDword(pGpu, NV_REG_STR_RM_POWER_FEATURES, 0x55455555); + osWriteRegistryDword(pGpu, NV_REG_STR_RM_INFOROM_DISABLE_BBX, + NV_REG_STR_RM_INFOROM_DISABLE_BBX_YES); #if !defined(NVCPU_X86_64) osWriteRegistryDword(pGpu, NV_REG_STR_RM_BAR2_APERTURE_SIZE_MB, 4); #endif diff --git a/src/nvidia/arch/nvalloc/unix/src/os.c b/src/nvidia/arch/nvalloc/unix/src/os.c index 2bba0c0ae..881162a10 100644 --- a/src/nvidia/arch/nvalloc/unix/src/os.c +++ b/src/nvidia/arch/nvalloc/unix/src/os.c @@ -45,6 +45,7 @@ #include "mem_mgr/io_vaspace.h" #include #include "gpu/mem_mgr/mem_desc.h" +#include "gpu/mem_mgr/mem_mgr.h" #include "core/thread_state.h" #include #include @@ -299,7 +300,13 @@ void* osMapKernelSpace( offset = (Start & ~os_page_mask); Start &= os_page_mask; - Size = ((Size + offset + ~os_page_mask) & os_page_mask); + + if (!portSafeAddU64(Size, offset, &Size) || + !portSafeAddU64(Size, ~os_page_mask, &Size)) + { + return NULL; + } + Size &= os_page_mask; ptr = os_map_kernel_space(Start, Size, Mode); if (ptr != NULL) @@ -892,6 +899,7 @@ NV_STATUS osAllocPagesInternal( nv_state_t *nv = NV_GET_NV_STATE(pGpu); void *pMemData = NULL; NV_STATUS status; + NvS32 nodeId = -1; memdescSetAddress(pMemDesc, NvP64_NULL); memdescSetMemData(pMemDesc, NULL, NULL); @@ -923,16 +931,19 @@ NV_STATUS osAllocPagesInternal( if (nv && (memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_32BIT_ADDRESSABLE))) nv->force_dma32_alloc = NV_TRUE; - status = nv_alloc_pages( - NV_GET_NV_STATE(pGpu), - NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount), - memdescGetContiguity(pMemDesc, AT_CPU), - memdescGetCpuCacheAttrib(pMemDesc), - pSys->getProperty(pSys, - PDB_PROP_SYS_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS), - unencrypted, - memdescGetPteArray(pMemDesc, AT_CPU), - &pMemData); + { + status = nv_alloc_pages( + NV_GET_NV_STATE(pGpu), + NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount), + memdescGetContiguity(pMemDesc, AT_CPU), + memdescGetCpuCacheAttrib(pMemDesc), + pSys->getProperty(pSys, + PDB_PROP_SYS_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS), + unencrypted, + nodeId, + memdescGetPteArray(pMemDesc, AT_CPU), + &pMemData); + } if (nv && nv->force_dma32_alloc) nv->force_dma32_alloc = NV_FALSE; @@ -942,7 +953,7 @@ NV_STATUS osAllocPagesInternal( { return status; } - + // // If the OS layer doesn't think in RM page size, we need to inflate the // PTE array into RM pages. @@ -5240,3 +5251,4 @@ osDmabufIsSupported(void) { return os_dma_buf_enabled; } + diff --git a/src/nvidia/arch/nvalloc/unix/src/osapi.c b/src/nvidia/arch/nvalloc/unix/src/osapi.c index 83fec382c..b6705ac47 100644 --- a/src/nvidia/arch/nvalloc/unix/src/osapi.c +++ b/src/nvidia/arch/nvalloc/unix/src/osapi.c @@ -404,7 +404,7 @@ void RmFreeUnusedClients( NvU32 *pClientList; NvU32 numClients, i; NV_STATUS status; - RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + RM_API *pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); // // The 'nvfp' pointer uniquely identifies an open instance in kernel space @@ -427,7 +427,7 @@ void RmFreeUnusedClients( if (numClients != 0) { - pRmApi->FreeClientList(pRmApi, pClientList, numClients); + pRmApi->DisableClients(pRmApi, pClientList, numClients); portMemFree(pClientList); } @@ -1008,6 +1008,16 @@ static NV_STATUS RmPerformVersionCheck( NvBool relaxed = NV_FALSE; NvU32 i; + // + // rmStr (i.e., NV_VERSION_STRING) must be null-terminated and fit within + // NV_RM_API_VERSION_STRING_LENGTH, so that: + // + // (1) If the versions don't match, we can return rmStr in + // pParams->versionString. + // (2) The below loop is guaranteed to not overrun rmStr. + // + ct_assert(sizeof(NV_VERSION_STRING) <= NV_RM_API_VERSION_STRING_LENGTH); + if (dataSize != sizeof(nv_ioctl_rm_api_version_t)) return NV_ERR_INVALID_ARGUMENT; @@ -1020,11 +1030,11 @@ static NV_STATUS RmPerformVersionCheck( pParams->reply = NV_RM_API_VERSION_REPLY_RECOGNIZED; // - // the client requested to override the version check; just return - // success. + // the client is just querying the version, not verifying against expected. // - if (pParams->cmd == NV_RM_API_VERSION_CMD_OVERRIDE) + if (pParams->cmd == NV_RM_API_VERSION_CMD_QUERY) { + os_string_copy(pParams->versionString, rmStr); return NV_OK; } @@ -1037,19 +1047,6 @@ static NV_STATUS RmPerformVersionCheck( relaxed = NV_TRUE; } - // - // rmStr (i.e., NV_VERSION_STRING) must be null-terminated and fit within - // NV_RM_API_VERSION_STRING_LENGTH, so that: - // - // (1) If the versions don't match, we can return rmStr in - // pParams->versionString. - // (2) The below loop is guaranteed to not overrun rmStr. - // - if ((os_string_length(rmStr) + 1) > NV_RM_API_VERSION_STRING_LENGTH) - { - return NV_ERR_BUFFER_TOO_SMALL; - } - for (i = 0; i < NV_RM_API_VERSION_STRING_LENGTH; i++) { clientCh = pParams->versionString[i]; @@ -1353,6 +1350,24 @@ RmDmabufPutClientAndDevice( NV_ASSERT_OK(kmigmgrDecRefCount(pKernelMIGGpuInstance->pShare)); } +static void +RmHandleNvpcfEvents( + nv_state_t *pNv +) +{ + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv); + THREAD_STATE_NODE threadState; + + if (RmUnixRmApiPrologue(pNv, &threadState, RM_LOCK_MODULES_ACPI) == NULL) + { + return; + } + + gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_NVPCF_EVENTS, NULL, 0, 0, 0); + + RmUnixRmApiEpilogue(pNv, &threadState); +} + /* * --------------------------------------------------------------------------- * @@ -2446,6 +2461,27 @@ NV_STATUS NV_API_CALL rm_ioctl( return rmStatus; } +static void _deferredClientListFreeCallback(void *unused) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + NV_STATUS status = serverFreeDisabledClients(&g_resServ, 0, pSys->clientListDeferredFreeLimit); + // + // Possible return values: + // NV_WARN_MORE_PROCESSING_REQUIRED - Iteration limit reached, need to call again + // NV_ERR_IN_USE - Already running on another thread, try again later + // In both cases, schedule a worker to clean up anything that remains + // + if (status != NV_OK) + { + status = osQueueSystemWorkItem(_deferredClientListFreeCallback, unused); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_NOTICE, "Failed to schedule deferred free callback. Freeing immediately.\n"); + serverFreeDisabledClients(&g_resServ, 0, 0); + } + } +} + void NV_API_CALL rm_cleanup_file_private( nvidia_stack_t *sp, nv_state_t *pNv, @@ -2454,19 +2490,23 @@ void NV_API_CALL rm_cleanup_file_private( { THREAD_STATE_NODE threadState; void *fp; - RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL); + RM_API *pRmApi; RM_API_CONTEXT rmApiContext = {0}; NvU32 i; + OBJSYS *pSys = SYS_GET_INSTANCE(); NV_ENTER_RM_RUNTIME(sp,fp); + pRmApi = rmapiGetInterface(RMAPI_EXTERNAL); threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); threadStateSetTimeoutOverride(&threadState, 10 * 1000); - if (rmapiPrologue(pRmApi, &rmApiContext) != NV_OK) + if (rmapiPrologue(pRmApi, &rmApiContext) != NV_OK) { + NV_EXIT_RM_RUNTIME(sp,fp); return; + } - // LOCK: acquire API lock - if (rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI) == NV_OK) + // LOCK: acquire API lock. Low priority so cleanup doesn't block active threads + if (rmapiLockAcquire(RMAPI_LOCK_FLAGS_LOW_PRIORITY, RM_LOCK_MODULES_OSAPI) == NV_OK) { // Unref any object which was exported on this file. if (nvfp->handles != NULL) @@ -2487,13 +2527,21 @@ void NV_API_CALL rm_cleanup_file_private( nvfp->maxHandles = 0; } - // Free any RM clients associated with this file. + // Disable any RM clients associated with this file. RmFreeUnusedClients(pNv, nvfp); + // Unless configured otherwise, immediately free all disabled clients + if (!pSys->bUseDeferredClientListFree) + serverFreeDisabledClients(&g_resServ, RM_LOCK_STATES_API_LOCK_ACQUIRED, 0); + // UNLOCK: release API lock rmapiLockRelease(); } + // Start the deferred free callback if necessary + if (pSys->bUseDeferredClientListFree) + _deferredClientListFreeCallback(NULL); + rmapiEpilogue(pRmApi, &rmApiContext); threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); @@ -2929,7 +2977,7 @@ static NV_STATUS RmRunNanoTimerCallback( THREAD_STATE_FLAGS_IS_DEFERRED_INT_HANDLER); // Call timer event service - status = tmrEventServiceOSTimerCallback_HAL(pGpu, pTmr, (PTMR_EVENT)pTmrEvent); + status = tmrEventServiceTimer(pGpu, pTmr, (PTMR_EVENT)pTmrEvent); // Out of conflicting thread threadStateFreeISRAndDeferredIntHandler(&threadState, @@ -5318,25 +5366,6 @@ void NV_API_CALL rm_dma_buf_put_client_and_device( // NOTE: Used only on VMWware // -void NV_API_CALL rm_vgpu_vfio_set_driver_vm( - nvidia_stack_t *sp, - NvBool is_driver_vm -) -{ - OBJSYS *pSys; - POBJHYPERVISOR pHypervisor; - void *fp; - - NV_ENTER_RM_RUNTIME(sp,fp); - - pSys = SYS_GET_INSTANCE(); - pHypervisor = SYS_GET_HYPERVISOR(pSys); - - pHypervisor->setProperty(pHypervisor, PDB_PROP_HYPERVISOR_DRIVERVM_ENABLED, is_driver_vm); - - NV_EXIT_RM_RUNTIME(sp,fp); -} - NvBool NV_API_CALL rm_is_altstack_in_use(void) { #if defined(__use_altstack__) @@ -5345,3 +5374,21 @@ NvBool NV_API_CALL rm_is_altstack_in_use(void) return NV_FALSE; #endif } + +void NV_API_CALL rm_acpi_nvpcf_notify( + nvidia_stack_t *sp +) +{ + void *fp; + OBJGPU *pGpu = gpumgrGetGpu(0); + + NV_ENTER_RM_RUNTIME(sp,fp); + + if (pGpu != NULL) + { + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + RmHandleNvpcfEvents(nv); + } + + NV_EXIT_RM_RUNTIME(sp,fp); +} diff --git a/src/nvidia/arch/nvalloc/unix/src/osinit.c b/src/nvidia/arch/nvalloc/unix/src/osinit.c index a000b8148..7af025e8a 100644 --- a/src/nvidia/arch/nvalloc/unix/src/osinit.c +++ b/src/nvidia/arch/nvalloc/unix/src/osinit.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -665,14 +665,14 @@ osInitNvMapping( "NV fb using linear address : 0x%p\n", pGpu->registerAccess.gpuFbAddr); pGpu->setProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_ENABLED, NV_TRUE); - pGpu->setProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS, NV_FALSE); + pGpu->setProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS, NV_TRUE); if (osReadRegistryDword(pGpu, NV_REG_PROCESS_NONSTALL_INTR_IN_LOCKLESS_ISR, &data) == NV_OK) { - if (data == NV_REG_PROCESS_NONSTALL_INTR_IN_LOCKLESS_ISR_ENABLE) + if (data == NV_REG_PROCESS_NONSTALL_INTR_IN_LOCKLESS_ISR_DISABLE) { - pGpu->setProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS, NV_TRUE); + pGpu->setProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS, NV_FALSE); } } @@ -680,6 +680,12 @@ osInitNvMapping( { pGpu->setProperty(pGpu, PDB_PROP_GPU_ALLOW_PAGE_RETIREMENT, NV_TRUE); } + else + { + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_ALLOW_PAGE_RETIREMENT, NV_TRUE); + } + } if ((osReadRegistryDword(NULL, NV_REG_PRESERVE_VIDEO_MEMORY_ALLOCATIONS, @@ -766,6 +772,11 @@ RmSetConsolePreservationParams(OBJGPU *pGpu) if (os_is_vgx_hyper() || IS_VIRTUAL(pGpu)) return; + if (!gpuFuseSupportsDisplay_HAL(pGpu)) + { + return; + } + // // Check the OS layer for any video memory used by a console // driver that should be reserved. @@ -937,6 +948,9 @@ RmInitNvDevice( return; } + // Setup GPU scalability + (void) RmInitScalability(pGpu); + return; } diff --git a/src/nvidia/arch/nvalloc/unix/src/osunix.c b/src/nvidia/arch/nvalloc/unix/src/osunix.c index 7d70602de..cc4502224 100644 --- a/src/nvidia/arch/nvalloc/unix/src/osunix.c +++ b/src/nvidia/arch/nvalloc/unix/src/osunix.c @@ -66,13 +66,6 @@ initUnixOSFunctionPointers(OBJOS *pOS) pOS->osNv_cpuid = nv_cpuid; #endif - pOS->osCallACPI_DSM = osCallACPI_DSM; - pOS->osCallACPI_DDC = osCallACPI_DDC; - pOS->osCallACPI_NVHG_ROM = osCallACPI_NVHG_ROM; - pOS->osCallACPI_DOD = osCallACPI_DOD; - pOS->osCallACPI_MXDM = osCallACPI_MXDM; - pOS->osCallACPI_MXDS = osCallACPI_MXDS; - pOS->osDbgBreakpointEnabled = osDbgBreakpointEnabled; } diff --git a/src/nvidia/arch/nvalloc/unix/src/rm-gpu-ops.c b/src/nvidia/arch/nvalloc/unix/src/rm-gpu-ops.c index d542393dc..f198f9f15 100644 --- a/src/nvidia/arch/nvalloc/unix/src/rm-gpu-ops.c +++ b/src/nvidia/arch/nvalloc/unix/src/rm-gpu-ops.c @@ -570,6 +570,17 @@ NV_STATUS NV_API_CALL rm_gpu_ops_get_non_replayable_faults(nvidia_stack_t *sp, return rmStatus; } +NV_STATUS NV_API_CALL rm_gpu_ops_flush_replayable_fault_buffer(nvidia_stack_t *sp, + gpuDeviceHandle device) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsFlushReplayableFaultBuffer(device); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + NV_STATUS NV_API_CALL rm_gpu_ops_init_access_cntr_info(nvidia_stack_t *sp, gpuDeviceHandle device, gpuAccessCntrInfo *accessCntrInfo) diff --git a/src/nvidia/arch/nvalloc/unix/src/unix_intr.c b/src/nvidia/arch/nvalloc/unix/src/unix_intr.c index 6d562c7a1..09d022b24 100644 --- a/src/nvidia/arch/nvalloc/unix/src/unix_intr.c +++ b/src/nvidia/arch/nvalloc/unix/src/unix_intr.c @@ -303,9 +303,6 @@ NV_STATUS osIsr( */ NvBool osLockShouldToggleInterrupts(OBJGPU *pGpu) { - if (pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY)) - return NV_TRUE; - return (!pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_PM_CODEPATH) && gpuIsStateLoaded(pGpu) && !pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_SLI_LINK_CODEPATH)); @@ -591,10 +588,10 @@ NV_STATUS NV_API_CALL rm_gpu_copy_mmu_faults( goto done; } - // Non-replayable faults are copied to the client shadow buffer by GSP-RM. if (IS_GSP_CLIENT(pGpu)) { - status = NV_ERR_NOT_SUPPORTED; + // Non-replayable faults are copied to the client shadow buffer by GSP-RM. + status = NV_OK; goto done; } @@ -614,11 +611,6 @@ static NV_STATUS _rm_gpu_copy_mmu_faults_unlocked( THREAD_STATE_NODE *pThreadState ) { - // Non-replayable faults are copied to the client shadow buffer by GSP-RM. - if (IS_GSP_CLIENT(pGpu)) - { - return NV_ERR_NOT_SUPPORTED; - } return NV_OK; } @@ -643,6 +635,7 @@ NV_STATUS rm_gpu_handle_mmu_faults( if (pGpu == NULL) { + NV_EXIT_RM_RUNTIME(sp,fp); return NV_ERR_OBJECT_NOT_FOUND; } @@ -666,7 +659,7 @@ NV_STATUS rm_gpu_handle_mmu_faults( { // We have to clear the top level interrupt bit here since otherwise // the bottom half will attempt to service the interrupt on the CPU - // side before GSP recieves the notification and services it + // side before GSP receives the notification and services it kgmmuClearNonReplayableFaultIntr_HAL(pGpu, pKernelGmmu, &threadState); status = intrTriggerPrivDoorbell_HAL(pGpu, pIntr, NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_HANDLE); @@ -681,7 +674,15 @@ NV_STATUS rm_gpu_handle_mmu_faults( } else { - status = _rm_gpu_copy_mmu_faults_unlocked(pGpu, faultsCopied, &threadState); + if (IS_GSP_CLIENT(pGpu)) + { + // Non-replayable faults are copied to the client shadow buffer by GSP-RM. + status = NV_OK; + } + else + { + status = _rm_gpu_copy_mmu_faults_unlocked(pGpu, faultsCopied, &threadState); + } } threadStateFreeISRLockless(&threadState, pGpu, THREAD_STATE_FLAGS_IS_ISR_LOCKLESS); diff --git a/src/nvidia/exports_link_command.txt b/src/nvidia/exports_link_command.txt index 8664b4002..795858861 100644 --- a/src/nvidia/exports_link_command.txt +++ b/src/nvidia/exports_link_command.txt @@ -16,7 +16,6 @@ --undefined=rm_init_adapter --undefined=rm_init_private_state --undefined=rm_init_rm ---undefined=rm_vgpu_vfio_set_driver_vm --undefined=rm_ioctl --undefined=rm_is_supported_device --undefined=rm_is_supported_pci_device @@ -85,6 +84,7 @@ --undefined=rm_gpu_ops_destroy_fault_info --undefined=rm_gpu_ops_has_pending_non_replayable_faults --undefined=rm_gpu_ops_get_non_replayable_faults +--undefined=rm_gpu_ops_flush_replayable_fault_buffer --undefined=rm_gpu_ops_init_access_cntr_info --undefined=rm_gpu_ops_destroy_access_cntr_info --undefined=rm_gpu_ops_enable_access_cntr @@ -190,3 +190,4 @@ --undefined=rm_is_iommu_needed_for_sriov --undefined=rm_disable_iomap_wc --undefined=rm_is_altstack_in_use +--undefined=rm_acpi_nvpcf_notify diff --git a/src/nvidia/generated/g_access_cntr_buffer_nvoc.c b/src/nvidia/generated/g_access_cntr_buffer_nvoc.c index 1b57c336e..cda006097 100644 --- a/src/nvidia/generated/g_access_cntr_buffer_nvoc.c +++ b/src/nvidia/generated/g_access_cntr_buffer_nvoc.c @@ -127,16 +127,16 @@ static NvBool __nvoc_thunk_GpuResource_accesscntrShareCallback(struct AccessCoun return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_AccessCounterBuffer_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_RsResource_accesscntrMapTo(struct AccessCounterBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_AccessCounterBuffer_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_accesscntrCheckMemInterUnmap(struct AccessCounterBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_AccessCounterBuffer_RmResource.offset), bSubdeviceHandleProvided); } static NV_STATUS __nvoc_thunk_Notifier_accesscntrGetOrAllocNotifShare(struct AccessCounterBuffer *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_AccessCounterBuffer_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); } -static NV_STATUS __nvoc_thunk_RmResource_accesscntrCheckMemInterUnmap(struct AccessCounterBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_AccessCounterBuffer_RmResource.offset), bSubdeviceHandleProvided); +static NV_STATUS __nvoc_thunk_RsResource_accesscntrMapTo(struct AccessCounterBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_AccessCounterBuffer_RsResource.offset), pParams); } static void __nvoc_thunk_Notifier_accesscntrSetNotificationShare(struct AccessCounterBuffer *pNotifier, struct NotifShare *pNotifShare) { @@ -199,6 +199,10 @@ static NV_STATUS __nvoc_thunk_Notifier_accesscntrUnregisterEvent(struct AccessCo return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_AccessCounterBuffer_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_accesscntrControlSerialization_Prologue(struct AccessCounterBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_AccessCounterBuffer_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_accesscntrCanCopy(struct AccessCounterBuffer *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_AccessCounterBuffer_RsResource.offset)); } @@ -211,6 +215,10 @@ static NV_STATUS __nvoc_thunk_RsResource_accesscntrIsDuplicate(struct AccessCoun return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_AccessCounterBuffer_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_accesscntrControlSerialization_Epilogue(struct AccessCounterBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_AccessCounterBuffer_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_accesscntrGetNotificationListPtr(struct AccessCounterBuffer *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_AccessCounterBuffer_Notifier.offset)); } @@ -482,11 +490,11 @@ static void __nvoc_init_funcTable_AccessCounterBuffer_1(AccessCounterBuffer *pTh pThis->__accesscntrShareCallback__ = &__nvoc_thunk_GpuResource_accesscntrShareCallback; - pThis->__accesscntrMapTo__ = &__nvoc_thunk_RsResource_accesscntrMapTo; + pThis->__accesscntrCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_accesscntrCheckMemInterUnmap; pThis->__accesscntrGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_accesscntrGetOrAllocNotifShare; - pThis->__accesscntrCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_accesscntrCheckMemInterUnmap; + pThis->__accesscntrMapTo__ = &__nvoc_thunk_RsResource_accesscntrMapTo; pThis->__accesscntrSetNotificationShare__ = &__nvoc_thunk_Notifier_accesscntrSetNotificationShare; @@ -518,12 +526,16 @@ static void __nvoc_init_funcTable_AccessCounterBuffer_1(AccessCounterBuffer *pTh pThis->__accesscntrUnregisterEvent__ = &__nvoc_thunk_Notifier_accesscntrUnregisterEvent; + pThis->__accesscntrControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_accesscntrControlSerialization_Prologue; + pThis->__accesscntrCanCopy__ = &__nvoc_thunk_RsResource_accesscntrCanCopy; pThis->__accesscntrPreDestruct__ = &__nvoc_thunk_RsResource_accesscntrPreDestruct; pThis->__accesscntrIsDuplicate__ = &__nvoc_thunk_RsResource_accesscntrIsDuplicate; + pThis->__accesscntrControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_accesscntrControlSerialization_Epilogue; + pThis->__accesscntrGetNotificationListPtr__ = &__nvoc_thunk_Notifier_accesscntrGetNotificationListPtr; pThis->__accesscntrGetNotificationShare__ = &__nvoc_thunk_Notifier_accesscntrGetNotificationShare; @@ -556,13 +568,16 @@ NV_STATUS __nvoc_objCreate_AccessCounterBuffer(AccessCounterBuffer **ppThis, Dyn Object *pParentObj; AccessCounterBuffer *pThis; - pThis = portMemAllocNonPaged(sizeof(AccessCounterBuffer)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(AccessCounterBuffer), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(AccessCounterBuffer)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_AccessCounterBuffer); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -578,11 +593,17 @@ NV_STATUS __nvoc_objCreate_AccessCounterBuffer(AccessCounterBuffer **ppThis, Dyn if (status != NV_OK) goto __nvoc_objCreate_AccessCounterBuffer_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_AccessCounterBuffer_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(AccessCounterBuffer)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_access_cntr_buffer_nvoc.h b/src/nvidia/generated/g_access_cntr_buffer_nvoc.h index 997c0adb8..335cd9378 100644 --- a/src/nvidia/generated/g_access_cntr_buffer_nvoc.h +++ b/src/nvidia/generated/g_access_cntr_buffer_nvoc.h @@ -73,9 +73,9 @@ struct AccessCounterBuffer { NV_STATUS (*__accesscntrCtrlCmdAccessCntrSetConfig__)(struct AccessCounterBuffer *, NVC365_CTRL_ACCESS_CNTR_SET_CONFIG_PARAMS *); NV_STATUS (*__accesscntrCtrlCmdAccessCntrBufferEnableIntr__)(struct AccessCounterBuffer *, NVC365_CTRL_ACCESS_CNTR_BUFFER_ENABLE_INTR_PARAMS *); NvBool (*__accesscntrShareCallback__)(struct AccessCounterBuffer *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__accesscntrMapTo__)(struct AccessCounterBuffer *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__accesscntrGetOrAllocNotifShare__)(struct AccessCounterBuffer *, NvHandle, NvHandle, struct NotifShare **); NV_STATUS (*__accesscntrCheckMemInterUnmap__)(struct AccessCounterBuffer *, NvBool); + NV_STATUS (*__accesscntrGetOrAllocNotifShare__)(struct AccessCounterBuffer *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__accesscntrMapTo__)(struct AccessCounterBuffer *, RS_RES_MAP_TO_PARAMS *); void (*__accesscntrSetNotificationShare__)(struct AccessCounterBuffer *, struct NotifShare *); NvU32 (*__accesscntrGetRefCount__)(struct AccessCounterBuffer *); void (*__accesscntrAddAdditionalDependants__)(struct RsClient *, struct AccessCounterBuffer *, RsResourceRef *); @@ -91,9 +91,11 @@ struct AccessCounterBuffer { NV_STATUS (*__accesscntrGetMemoryMappingDescriptor__)(struct AccessCounterBuffer *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__accesscntrControlFilter__)(struct AccessCounterBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__accesscntrUnregisterEvent__)(struct AccessCounterBuffer *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__accesscntrControlSerialization_Prologue__)(struct AccessCounterBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__accesscntrCanCopy__)(struct AccessCounterBuffer *); void (*__accesscntrPreDestruct__)(struct AccessCounterBuffer *); NV_STATUS (*__accesscntrIsDuplicate__)(struct AccessCounterBuffer *, NvHandle, NvBool *); + void (*__accesscntrControlSerialization_Epilogue__)(struct AccessCounterBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__accesscntrGetNotificationListPtr__)(struct AccessCounterBuffer *); struct NotifShare *(*__accesscntrGetNotificationShare__)(struct AccessCounterBuffer *); NvBool (*__accesscntrAccessCallback__)(struct AccessCounterBuffer *, struct RsClient *, void *, RsAccessRight); @@ -141,9 +143,9 @@ NV_STATUS __nvoc_objCreate_AccessCounterBuffer(AccessCounterBuffer**, Dynamic*, #define accesscntrCtrlCmdAccessCntrSetConfig(pAccessCounterBuffer, pParams) accesscntrCtrlCmdAccessCntrSetConfig_DISPATCH(pAccessCounterBuffer, pParams) #define accesscntrCtrlCmdAccessCntrBufferEnableIntr(pAccessCounterBuffer, pGetParams) accesscntrCtrlCmdAccessCntrBufferEnableIntr_DISPATCH(pAccessCounterBuffer, pGetParams) #define accesscntrShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) accesscntrShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define accesscntrMapTo(pResource, pParams) accesscntrMapTo_DISPATCH(pResource, pParams) -#define accesscntrGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) accesscntrGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) #define accesscntrCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) accesscntrCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define accesscntrGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) accesscntrGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define accesscntrMapTo(pResource, pParams) accesscntrMapTo_DISPATCH(pResource, pParams) #define accesscntrSetNotificationShare(pNotifier, pNotifShare) accesscntrSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define accesscntrGetRefCount(pResource) accesscntrGetRefCount_DISPATCH(pResource) #define accesscntrAddAdditionalDependants(pClient, pResource, pReference) accesscntrAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) @@ -159,9 +161,11 @@ NV_STATUS __nvoc_objCreate_AccessCounterBuffer(AccessCounterBuffer**, Dynamic*, #define accesscntrGetMemoryMappingDescriptor(pRmResource, ppMemDesc) accesscntrGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define accesscntrControlFilter(pResource, pCallContext, pParams) accesscntrControlFilter_DISPATCH(pResource, pCallContext, pParams) #define accesscntrUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) accesscntrUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define accesscntrControlSerialization_Prologue(pResource, pCallContext, pParams) accesscntrControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define accesscntrCanCopy(pResource) accesscntrCanCopy_DISPATCH(pResource) #define accesscntrPreDestruct(pResource) accesscntrPreDestruct_DISPATCH(pResource) #define accesscntrIsDuplicate(pResource, hMemory, pDuplicate) accesscntrIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define accesscntrControlSerialization_Epilogue(pResource, pCallContext, pParams) accesscntrControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define accesscntrGetNotificationListPtr(pNotifier) accesscntrGetNotificationListPtr_DISPATCH(pNotifier) #define accesscntrGetNotificationShare(pNotifier) accesscntrGetNotificationShare_DISPATCH(pNotifier) #define accesscntrAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) accesscntrAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) @@ -247,16 +251,16 @@ static inline NvBool accesscntrShareCallback_DISPATCH(struct AccessCounterBuffer return pGpuResource->__accesscntrShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS accesscntrMapTo_DISPATCH(struct AccessCounterBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__accesscntrMapTo__(pResource, pParams); +static inline NV_STATUS accesscntrCheckMemInterUnmap_DISPATCH(struct AccessCounterBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__accesscntrCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } static inline NV_STATUS accesscntrGetOrAllocNotifShare_DISPATCH(struct AccessCounterBuffer *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return pNotifier->__accesscntrGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); } -static inline NV_STATUS accesscntrCheckMemInterUnmap_DISPATCH(struct AccessCounterBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__accesscntrCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline NV_STATUS accesscntrMapTo_DISPATCH(struct AccessCounterBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__accesscntrMapTo__(pResource, pParams); } static inline void accesscntrSetNotificationShare_DISPATCH(struct AccessCounterBuffer *pNotifier, struct NotifShare *pNotifShare) { @@ -319,6 +323,10 @@ static inline NV_STATUS accesscntrUnregisterEvent_DISPATCH(struct AccessCounterB return pNotifier->__accesscntrUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS accesscntrControlSerialization_Prologue_DISPATCH(struct AccessCounterBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__accesscntrControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool accesscntrCanCopy_DISPATCH(struct AccessCounterBuffer *pResource) { return pResource->__accesscntrCanCopy__(pResource); } @@ -331,6 +339,10 @@ static inline NV_STATUS accesscntrIsDuplicate_DISPATCH(struct AccessCounterBuffe return pResource->__accesscntrIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void accesscntrControlSerialization_Epilogue_DISPATCH(struct AccessCounterBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__accesscntrControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *accesscntrGetNotificationListPtr_DISPATCH(struct AccessCounterBuffer *pNotifier) { return pNotifier->__accesscntrGetNotificationListPtr__(pNotifier); } diff --git a/src/nvidia/generated/g_allclasses.h b/src/nvidia/generated/g_allclasses.h index 278c45728..9a1051694 100644 --- a/src/nvidia/generated/g_allclasses.h +++ b/src/nvidia/generated/g_allclasses.h @@ -151,6 +151,7 @@ #include // MAXWELL_DMA_COPY_A #include // ACCESS_COUNTER_NOTIFY_BUFFER #include // MMU_FAULT_BUFFER +#include // MMU_VIDMEM_ACCESS_BIT_BUFFER #include // TURING_A #include // TURING_COMPUTE_A #include // AMPERE_A @@ -719,6 +720,10 @@ #define MMU_FAULT_BUFFER (0x0000c369) #endif +#ifndef MMU_VIDMEM_ACCESS_BIT_BUFFER +#define MMU_VIDMEM_ACCESS_BIT_BUFFER (0x0000c763) +#endif + #ifndef TURING_A #define TURING_A (0x0000c597) #endif diff --git a/src/nvidia/generated/g_binary_api_nvoc.c b/src/nvidia/generated/g_binary_api_nvoc.c index a8690b074..2b5ab8bf1 100644 --- a/src/nvidia/generated/g_binary_api_nvoc.c +++ b/src/nvidia/generated/g_binary_api_nvoc.c @@ -101,6 +101,54 @@ static NvBool __nvoc_thunk_GpuResource_binapiShareCallback(struct BinaryApi *pGp return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } +static NV_STATUS __nvoc_thunk_RmResource_binapiCheckMemInterUnmap(struct BinaryApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_BinaryApi_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_binapiMapTo(struct BinaryApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_binapiGetMapAddrSpace(struct BinaryApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApi_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_binapiGetRefCount(struct BinaryApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_binapiAddAdditionalDependants(struct RsClient *pClient, struct BinaryApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_binapiControl_Prologue(struct BinaryApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_binapiGetRegBaseOffsetAndSize(struct BinaryApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApi_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_binapiInternalControlForward(struct BinaryApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApi_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_binapiUnmapFrom(struct BinaryApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_binapiControl_Epilogue(struct BinaryApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_binapiControlLookup(struct BinaryApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset), pParams, ppEntry); +} + +static NvHandle __nvoc_thunk_GpuResource_binapiGetInternalObjectHandle(struct BinaryApi *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApi_GpuResource.offset)); +} + static NV_STATUS __nvoc_thunk_GpuResource_binapiUnmap(struct BinaryApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApi_GpuResource.offset), pCallContext, pCpuMapping); } @@ -113,68 +161,28 @@ static NV_STATUS __nvoc_thunk_RmResource_binapiGetMemoryMappingDescriptor(struct return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_BinaryApi_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_GpuResource_binapiGetMapAddrSpace(struct BinaryApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApi_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvHandle __nvoc_thunk_GpuResource_binapiGetInternalObjectHandle(struct BinaryApi *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApi_GpuResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_binapiControlFilter(struct BinaryApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_binapiAddAdditionalDependants(struct RsClient *pClient, struct BinaryApi *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_binapiGetRefCount(struct BinaryApi *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RmResource_binapiCheckMemInterUnmap(struct BinaryApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_BinaryApi_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_binapiMapTo(struct BinaryApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_binapiControl_Prologue(struct BinaryApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_GpuResource_binapiGetRegBaseOffsetAndSize(struct BinaryApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApi_GpuResource.offset), pGpu, pOffset, pSize); +static NV_STATUS __nvoc_thunk_RmResource_binapiControlSerialization_Prologue(struct BinaryApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_binapiCanCopy(struct BinaryApi *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_binapiInternalControlForward(struct BinaryApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApi_GpuResource.offset), command, pParams, size); -} - static void __nvoc_thunk_RsResource_binapiPreDestruct(struct BinaryApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_binapiUnmapFrom(struct BinaryApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_binapiIsDuplicate(struct BinaryApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset), hMemory, pDuplicate); } -static void __nvoc_thunk_RmResource_binapiControl_Epilogue(struct BinaryApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_binapiControlLookup(struct BinaryApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_binapiControlSerialization_Epilogue(struct BinaryApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_binapiMap(struct BinaryApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -229,43 +237,47 @@ static void __nvoc_init_funcTable_BinaryApi_1(BinaryApi *pThis) { pThis->__binapiShareCallback__ = &__nvoc_thunk_GpuResource_binapiShareCallback; + pThis->__binapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_binapiCheckMemInterUnmap; + + pThis->__binapiMapTo__ = &__nvoc_thunk_RsResource_binapiMapTo; + + pThis->__binapiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_binapiGetMapAddrSpace; + + pThis->__binapiGetRefCount__ = &__nvoc_thunk_RsResource_binapiGetRefCount; + + pThis->__binapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_binapiAddAdditionalDependants; + + pThis->__binapiControl_Prologue__ = &__nvoc_thunk_RmResource_binapiControl_Prologue; + + pThis->__binapiGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_binapiGetRegBaseOffsetAndSize; + + pThis->__binapiInternalControlForward__ = &__nvoc_thunk_GpuResource_binapiInternalControlForward; + + pThis->__binapiUnmapFrom__ = &__nvoc_thunk_RsResource_binapiUnmapFrom; + + pThis->__binapiControl_Epilogue__ = &__nvoc_thunk_RmResource_binapiControl_Epilogue; + + pThis->__binapiControlLookup__ = &__nvoc_thunk_RsResource_binapiControlLookup; + + pThis->__binapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_binapiGetInternalObjectHandle; + pThis->__binapiUnmap__ = &__nvoc_thunk_GpuResource_binapiUnmap; pThis->__binapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_binapiGetMemInterMapParams; pThis->__binapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_binapiGetMemoryMappingDescriptor; - pThis->__binapiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_binapiGetMapAddrSpace; - - pThis->__binapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_binapiGetInternalObjectHandle; - pThis->__binapiControlFilter__ = &__nvoc_thunk_RsResource_binapiControlFilter; - pThis->__binapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_binapiAddAdditionalDependants; - - pThis->__binapiGetRefCount__ = &__nvoc_thunk_RsResource_binapiGetRefCount; - - pThis->__binapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_binapiCheckMemInterUnmap; - - pThis->__binapiMapTo__ = &__nvoc_thunk_RsResource_binapiMapTo; - - pThis->__binapiControl_Prologue__ = &__nvoc_thunk_RmResource_binapiControl_Prologue; - - pThis->__binapiGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_binapiGetRegBaseOffsetAndSize; + pThis->__binapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_binapiControlSerialization_Prologue; pThis->__binapiCanCopy__ = &__nvoc_thunk_RsResource_binapiCanCopy; - pThis->__binapiInternalControlForward__ = &__nvoc_thunk_GpuResource_binapiInternalControlForward; - pThis->__binapiPreDestruct__ = &__nvoc_thunk_RsResource_binapiPreDestruct; - pThis->__binapiUnmapFrom__ = &__nvoc_thunk_RsResource_binapiUnmapFrom; - pThis->__binapiIsDuplicate__ = &__nvoc_thunk_RsResource_binapiIsDuplicate; - pThis->__binapiControl_Epilogue__ = &__nvoc_thunk_RmResource_binapiControl_Epilogue; - - pThis->__binapiControlLookup__ = &__nvoc_thunk_RsResource_binapiControlLookup; + pThis->__binapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_binapiControlSerialization_Epilogue; pThis->__binapiMap__ = &__nvoc_thunk_GpuResource_binapiMap; @@ -293,13 +305,16 @@ NV_STATUS __nvoc_objCreate_BinaryApi(BinaryApi **ppThis, Dynamic *pParent, NvU32 Object *pParentObj; BinaryApi *pThis; - pThis = portMemAllocNonPaged(sizeof(BinaryApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(BinaryApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(BinaryApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_BinaryApi); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -315,11 +330,17 @@ NV_STATUS __nvoc_objCreate_BinaryApi(BinaryApi **ppThis, Dynamic *pParent, NvU32 if (status != NV_OK) goto __nvoc_objCreate_BinaryApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_BinaryApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(BinaryApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -436,6 +457,54 @@ static NvBool __nvoc_thunk_GpuResource_binapiprivShareCallback(struct BinaryApiP return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApiPrivileged_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } +static NV_STATUS __nvoc_thunk_RmResource_binapiprivCheckMemInterUnmap(struct BinaryApiPrivileged *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_BinaryApiPrivileged_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_binapiprivMapTo(struct BinaryApiPrivileged *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_binapiprivGetMapAddrSpace(struct BinaryApiPrivileged *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApiPrivileged_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_binapiprivGetRefCount(struct BinaryApiPrivileged *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_binapiprivAddAdditionalDependants(struct RsClient *pClient, struct BinaryApiPrivileged *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_binapiprivControl_Prologue(struct BinaryApiPrivileged *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_binapiprivGetRegBaseOffsetAndSize(struct BinaryApiPrivileged *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApiPrivileged_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_binapiprivInternalControlForward(struct BinaryApiPrivileged *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApiPrivileged_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_binapiprivUnmapFrom(struct BinaryApiPrivileged *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_binapiprivControl_Epilogue(struct BinaryApiPrivileged *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_binapiprivControlLookup(struct BinaryApiPrivileged *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset), pParams, ppEntry); +} + +static NvHandle __nvoc_thunk_GpuResource_binapiprivGetInternalObjectHandle(struct BinaryApiPrivileged *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApiPrivileged_GpuResource.offset)); +} + static NV_STATUS __nvoc_thunk_GpuResource_binapiprivUnmap(struct BinaryApiPrivileged *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApiPrivileged_GpuResource.offset), pCallContext, pCpuMapping); } @@ -448,68 +517,28 @@ static NV_STATUS __nvoc_thunk_RmResource_binapiprivGetMemoryMappingDescriptor(st return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_BinaryApiPrivileged_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_GpuResource_binapiprivGetMapAddrSpace(struct BinaryApiPrivileged *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApiPrivileged_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvHandle __nvoc_thunk_GpuResource_binapiprivGetInternalObjectHandle(struct BinaryApiPrivileged *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApiPrivileged_GpuResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_binapiprivControlFilter(struct BinaryApiPrivileged *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_binapiprivAddAdditionalDependants(struct RsClient *pClient, struct BinaryApiPrivileged *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_binapiprivGetRefCount(struct BinaryApiPrivileged *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RmResource_binapiprivCheckMemInterUnmap(struct BinaryApiPrivileged *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_BinaryApiPrivileged_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_binapiprivMapTo(struct BinaryApiPrivileged *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_binapiprivControl_Prologue(struct BinaryApiPrivileged *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_GpuResource_binapiprivGetRegBaseOffsetAndSize(struct BinaryApiPrivileged *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApiPrivileged_GpuResource.offset), pGpu, pOffset, pSize); +static NV_STATUS __nvoc_thunk_RmResource_binapiprivControlSerialization_Prologue(struct BinaryApiPrivileged *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_binapiprivCanCopy(struct BinaryApiPrivileged *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_binapiprivInternalControlForward(struct BinaryApiPrivileged *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApiPrivileged_GpuResource.offset), command, pParams, size); -} - static void __nvoc_thunk_RsResource_binapiprivPreDestruct(struct BinaryApiPrivileged *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_binapiprivUnmapFrom(struct BinaryApiPrivileged *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_binapiprivIsDuplicate(struct BinaryApiPrivileged *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset), hMemory, pDuplicate); } -static void __nvoc_thunk_RmResource_binapiprivControl_Epilogue(struct BinaryApiPrivileged *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_binapiprivControlLookup(struct BinaryApiPrivileged *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_binapiprivControlSerialization_Epilogue(struct BinaryApiPrivileged *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_binapiprivMap(struct BinaryApiPrivileged *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -564,43 +593,47 @@ static void __nvoc_init_funcTable_BinaryApiPrivileged_1(BinaryApiPrivileged *pTh pThis->__binapiprivShareCallback__ = &__nvoc_thunk_GpuResource_binapiprivShareCallback; + pThis->__binapiprivCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_binapiprivCheckMemInterUnmap; + + pThis->__binapiprivMapTo__ = &__nvoc_thunk_RsResource_binapiprivMapTo; + + pThis->__binapiprivGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_binapiprivGetMapAddrSpace; + + pThis->__binapiprivGetRefCount__ = &__nvoc_thunk_RsResource_binapiprivGetRefCount; + + pThis->__binapiprivAddAdditionalDependants__ = &__nvoc_thunk_RsResource_binapiprivAddAdditionalDependants; + + pThis->__binapiprivControl_Prologue__ = &__nvoc_thunk_RmResource_binapiprivControl_Prologue; + + pThis->__binapiprivGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_binapiprivGetRegBaseOffsetAndSize; + + pThis->__binapiprivInternalControlForward__ = &__nvoc_thunk_GpuResource_binapiprivInternalControlForward; + + pThis->__binapiprivUnmapFrom__ = &__nvoc_thunk_RsResource_binapiprivUnmapFrom; + + pThis->__binapiprivControl_Epilogue__ = &__nvoc_thunk_RmResource_binapiprivControl_Epilogue; + + pThis->__binapiprivControlLookup__ = &__nvoc_thunk_RsResource_binapiprivControlLookup; + + pThis->__binapiprivGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_binapiprivGetInternalObjectHandle; + pThis->__binapiprivUnmap__ = &__nvoc_thunk_GpuResource_binapiprivUnmap; pThis->__binapiprivGetMemInterMapParams__ = &__nvoc_thunk_RmResource_binapiprivGetMemInterMapParams; pThis->__binapiprivGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_binapiprivGetMemoryMappingDescriptor; - pThis->__binapiprivGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_binapiprivGetMapAddrSpace; - - pThis->__binapiprivGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_binapiprivGetInternalObjectHandle; - pThis->__binapiprivControlFilter__ = &__nvoc_thunk_RsResource_binapiprivControlFilter; - pThis->__binapiprivAddAdditionalDependants__ = &__nvoc_thunk_RsResource_binapiprivAddAdditionalDependants; - - pThis->__binapiprivGetRefCount__ = &__nvoc_thunk_RsResource_binapiprivGetRefCount; - - pThis->__binapiprivCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_binapiprivCheckMemInterUnmap; - - pThis->__binapiprivMapTo__ = &__nvoc_thunk_RsResource_binapiprivMapTo; - - pThis->__binapiprivControl_Prologue__ = &__nvoc_thunk_RmResource_binapiprivControl_Prologue; - - pThis->__binapiprivGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_binapiprivGetRegBaseOffsetAndSize; + pThis->__binapiprivControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_binapiprivControlSerialization_Prologue; pThis->__binapiprivCanCopy__ = &__nvoc_thunk_RsResource_binapiprivCanCopy; - pThis->__binapiprivInternalControlForward__ = &__nvoc_thunk_GpuResource_binapiprivInternalControlForward; - pThis->__binapiprivPreDestruct__ = &__nvoc_thunk_RsResource_binapiprivPreDestruct; - pThis->__binapiprivUnmapFrom__ = &__nvoc_thunk_RsResource_binapiprivUnmapFrom; - pThis->__binapiprivIsDuplicate__ = &__nvoc_thunk_RsResource_binapiprivIsDuplicate; - pThis->__binapiprivControl_Epilogue__ = &__nvoc_thunk_RmResource_binapiprivControl_Epilogue; - - pThis->__binapiprivControlLookup__ = &__nvoc_thunk_RsResource_binapiprivControlLookup; + pThis->__binapiprivControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_binapiprivControlSerialization_Epilogue; pThis->__binapiprivMap__ = &__nvoc_thunk_GpuResource_binapiprivMap; @@ -629,13 +662,16 @@ NV_STATUS __nvoc_objCreate_BinaryApiPrivileged(BinaryApiPrivileged **ppThis, Dyn Object *pParentObj; BinaryApiPrivileged *pThis; - pThis = portMemAllocNonPaged(sizeof(BinaryApiPrivileged)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(BinaryApiPrivileged), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(BinaryApiPrivileged)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_BinaryApiPrivileged); + pThis->__nvoc_base_BinaryApi.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -651,11 +687,17 @@ NV_STATUS __nvoc_objCreate_BinaryApiPrivileged(BinaryApiPrivileged **ppThis, Dyn if (status != NV_OK) goto __nvoc_objCreate_BinaryApiPrivileged_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_BinaryApiPrivileged_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(BinaryApiPrivileged)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_binary_api_nvoc.h b/src/nvidia/generated/g_binary_api_nvoc.h index eb767006b..44fa96982 100644 --- a/src/nvidia/generated/g_binary_api_nvoc.h +++ b/src/nvidia/generated/g_binary_api_nvoc.h @@ -56,25 +56,27 @@ struct BinaryApi { struct BinaryApi *__nvoc_pbase_BinaryApi; NV_STATUS (*__binapiControl__)(struct BinaryApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__binapiShareCallback__)(struct BinaryApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__binapiCheckMemInterUnmap__)(struct BinaryApi *, NvBool); + NV_STATUS (*__binapiMapTo__)(struct BinaryApi *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__binapiGetMapAddrSpace__)(struct BinaryApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__binapiGetRefCount__)(struct BinaryApi *); + void (*__binapiAddAdditionalDependants__)(struct RsClient *, struct BinaryApi *, RsResourceRef *); + NV_STATUS (*__binapiControl_Prologue__)(struct BinaryApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__binapiGetRegBaseOffsetAndSize__)(struct BinaryApi *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__binapiInternalControlForward__)(struct BinaryApi *, NvU32, void *, NvU32); + NV_STATUS (*__binapiUnmapFrom__)(struct BinaryApi *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__binapiControl_Epilogue__)(struct BinaryApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__binapiControlLookup__)(struct BinaryApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__binapiGetInternalObjectHandle__)(struct BinaryApi *); NV_STATUS (*__binapiUnmap__)(struct BinaryApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__binapiGetMemInterMapParams__)(struct BinaryApi *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__binapiGetMemoryMappingDescriptor__)(struct BinaryApi *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__binapiGetMapAddrSpace__)(struct BinaryApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__binapiGetInternalObjectHandle__)(struct BinaryApi *); NV_STATUS (*__binapiControlFilter__)(struct BinaryApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__binapiAddAdditionalDependants__)(struct RsClient *, struct BinaryApi *, RsResourceRef *); - NvU32 (*__binapiGetRefCount__)(struct BinaryApi *); - NV_STATUS (*__binapiCheckMemInterUnmap__)(struct BinaryApi *, NvBool); - NV_STATUS (*__binapiMapTo__)(struct BinaryApi *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__binapiControl_Prologue__)(struct BinaryApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__binapiGetRegBaseOffsetAndSize__)(struct BinaryApi *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__binapiControlSerialization_Prologue__)(struct BinaryApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__binapiCanCopy__)(struct BinaryApi *); - NV_STATUS (*__binapiInternalControlForward__)(struct BinaryApi *, NvU32, void *, NvU32); void (*__binapiPreDestruct__)(struct BinaryApi *); - NV_STATUS (*__binapiUnmapFrom__)(struct BinaryApi *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__binapiIsDuplicate__)(struct BinaryApi *, NvHandle, NvBool *); - void (*__binapiControl_Epilogue__)(struct BinaryApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__binapiControlLookup__)(struct BinaryApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__binapiControlSerialization_Epilogue__)(struct BinaryApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__binapiMap__)(struct BinaryApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__binapiAccessCallback__)(struct BinaryApi *, struct RsClient *, void *, RsAccessRight); }; @@ -109,25 +111,27 @@ NV_STATUS __nvoc_objCreate_BinaryApi(BinaryApi**, Dynamic*, NvU32, struct CALL_C #define binapiControl(pResource, pCallContext, pParams) binapiControl_DISPATCH(pResource, pCallContext, pParams) #define binapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) binapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define binapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) binapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define binapiMapTo(pResource, pParams) binapiMapTo_DISPATCH(pResource, pParams) +#define binapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) binapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define binapiGetRefCount(pResource) binapiGetRefCount_DISPATCH(pResource) +#define binapiAddAdditionalDependants(pClient, pResource, pReference) binapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define binapiControl_Prologue(pResource, pCallContext, pParams) binapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define binapiGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) binapiGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define binapiInternalControlForward(pGpuResource, command, pParams, size) binapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define binapiUnmapFrom(pResource, pParams) binapiUnmapFrom_DISPATCH(pResource, pParams) +#define binapiControl_Epilogue(pResource, pCallContext, pParams) binapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define binapiControlLookup(pResource, pParams, ppEntry) binapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define binapiGetInternalObjectHandle(pGpuResource) binapiGetInternalObjectHandle_DISPATCH(pGpuResource) #define binapiUnmap(pGpuResource, pCallContext, pCpuMapping) binapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define binapiGetMemInterMapParams(pRmResource, pParams) binapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define binapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) binapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define binapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) binapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define binapiGetInternalObjectHandle(pGpuResource) binapiGetInternalObjectHandle_DISPATCH(pGpuResource) #define binapiControlFilter(pResource, pCallContext, pParams) binapiControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define binapiAddAdditionalDependants(pClient, pResource, pReference) binapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define binapiGetRefCount(pResource) binapiGetRefCount_DISPATCH(pResource) -#define binapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) binapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define binapiMapTo(pResource, pParams) binapiMapTo_DISPATCH(pResource, pParams) -#define binapiControl_Prologue(pResource, pCallContext, pParams) binapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define binapiGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) binapiGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define binapiControlSerialization_Prologue(pResource, pCallContext, pParams) binapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define binapiCanCopy(pResource) binapiCanCopy_DISPATCH(pResource) -#define binapiInternalControlForward(pGpuResource, command, pParams, size) binapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define binapiPreDestruct(pResource) binapiPreDestruct_DISPATCH(pResource) -#define binapiUnmapFrom(pResource, pParams) binapiUnmapFrom_DISPATCH(pResource, pParams) #define binapiIsDuplicate(pResource, hMemory, pDuplicate) binapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) -#define binapiControl_Epilogue(pResource, pCallContext, pParams) binapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define binapiControlLookup(pResource, pParams, ppEntry) binapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define binapiControlSerialization_Epilogue(pResource, pCallContext, pParams) binapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define binapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) binapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define binapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) binapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS binapiControl_IMPL(struct BinaryApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); @@ -140,6 +144,54 @@ static inline NvBool binapiShareCallback_DISPATCH(struct BinaryApi *pGpuResource return pGpuResource->__binapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } +static inline NV_STATUS binapiCheckMemInterUnmap_DISPATCH(struct BinaryApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__binapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS binapiMapTo_DISPATCH(struct BinaryApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__binapiMapTo__(pResource, pParams); +} + +static inline NV_STATUS binapiGetMapAddrSpace_DISPATCH(struct BinaryApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__binapiGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 binapiGetRefCount_DISPATCH(struct BinaryApi *pResource) { + return pResource->__binapiGetRefCount__(pResource); +} + +static inline void binapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct BinaryApi *pResource, RsResourceRef *pReference) { + pResource->__binapiAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS binapiControl_Prologue_DISPATCH(struct BinaryApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__binapiControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS binapiGetRegBaseOffsetAndSize_DISPATCH(struct BinaryApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__binapiGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS binapiInternalControlForward_DISPATCH(struct BinaryApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__binapiInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS binapiUnmapFrom_DISPATCH(struct BinaryApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__binapiUnmapFrom__(pResource, pParams); +} + +static inline void binapiControl_Epilogue_DISPATCH(struct BinaryApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__binapiControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS binapiControlLookup_DISPATCH(struct BinaryApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__binapiControlLookup__(pResource, pParams, ppEntry); +} + +static inline NvHandle binapiGetInternalObjectHandle_DISPATCH(struct BinaryApi *pGpuResource) { + return pGpuResource->__binapiGetInternalObjectHandle__(pGpuResource); +} + static inline NV_STATUS binapiUnmap_DISPATCH(struct BinaryApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { return pGpuResource->__binapiUnmap__(pGpuResource, pCallContext, pCpuMapping); } @@ -152,68 +204,28 @@ static inline NV_STATUS binapiGetMemoryMappingDescriptor_DISPATCH(struct BinaryA return pRmResource->__binapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS binapiGetMapAddrSpace_DISPATCH(struct BinaryApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__binapiGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvHandle binapiGetInternalObjectHandle_DISPATCH(struct BinaryApi *pGpuResource) { - return pGpuResource->__binapiGetInternalObjectHandle__(pGpuResource); -} - static inline NV_STATUS binapiControlFilter_DISPATCH(struct BinaryApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__binapiControlFilter__(pResource, pCallContext, pParams); } -static inline void binapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct BinaryApi *pResource, RsResourceRef *pReference) { - pResource->__binapiAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 binapiGetRefCount_DISPATCH(struct BinaryApi *pResource) { - return pResource->__binapiGetRefCount__(pResource); -} - -static inline NV_STATUS binapiCheckMemInterUnmap_DISPATCH(struct BinaryApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__binapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS binapiMapTo_DISPATCH(struct BinaryApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__binapiMapTo__(pResource, pParams); -} - -static inline NV_STATUS binapiControl_Prologue_DISPATCH(struct BinaryApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__binapiControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS binapiGetRegBaseOffsetAndSize_DISPATCH(struct BinaryApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__binapiGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +static inline NV_STATUS binapiControlSerialization_Prologue_DISPATCH(struct BinaryApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__binapiControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool binapiCanCopy_DISPATCH(struct BinaryApi *pResource) { return pResource->__binapiCanCopy__(pResource); } -static inline NV_STATUS binapiInternalControlForward_DISPATCH(struct BinaryApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__binapiInternalControlForward__(pGpuResource, command, pParams, size); -} - static inline void binapiPreDestruct_DISPATCH(struct BinaryApi *pResource) { pResource->__binapiPreDestruct__(pResource); } -static inline NV_STATUS binapiUnmapFrom_DISPATCH(struct BinaryApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__binapiUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS binapiIsDuplicate_DISPATCH(struct BinaryApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__binapiIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline void binapiControl_Epilogue_DISPATCH(struct BinaryApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__binapiControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS binapiControlLookup_DISPATCH(struct BinaryApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__binapiControlLookup__(pResource, pParams, ppEntry); +static inline void binapiControlSerialization_Epilogue_DISPATCH(struct BinaryApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__binapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS binapiMap_DISPATCH(struct BinaryApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -247,25 +259,27 @@ struct BinaryApiPrivileged { struct BinaryApiPrivileged *__nvoc_pbase_BinaryApiPrivileged; NV_STATUS (*__binapiprivControl__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__binapiprivShareCallback__)(struct BinaryApiPrivileged *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__binapiprivCheckMemInterUnmap__)(struct BinaryApiPrivileged *, NvBool); + NV_STATUS (*__binapiprivMapTo__)(struct BinaryApiPrivileged *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__binapiprivGetMapAddrSpace__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__binapiprivGetRefCount__)(struct BinaryApiPrivileged *); + void (*__binapiprivAddAdditionalDependants__)(struct RsClient *, struct BinaryApiPrivileged *, RsResourceRef *); + NV_STATUS (*__binapiprivControl_Prologue__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__binapiprivGetRegBaseOffsetAndSize__)(struct BinaryApiPrivileged *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__binapiprivInternalControlForward__)(struct BinaryApiPrivileged *, NvU32, void *, NvU32); + NV_STATUS (*__binapiprivUnmapFrom__)(struct BinaryApiPrivileged *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__binapiprivControl_Epilogue__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__binapiprivControlLookup__)(struct BinaryApiPrivileged *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__binapiprivGetInternalObjectHandle__)(struct BinaryApiPrivileged *); NV_STATUS (*__binapiprivUnmap__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__binapiprivGetMemInterMapParams__)(struct BinaryApiPrivileged *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__binapiprivGetMemoryMappingDescriptor__)(struct BinaryApiPrivileged *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__binapiprivGetMapAddrSpace__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__binapiprivGetInternalObjectHandle__)(struct BinaryApiPrivileged *); NV_STATUS (*__binapiprivControlFilter__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__binapiprivAddAdditionalDependants__)(struct RsClient *, struct BinaryApiPrivileged *, RsResourceRef *); - NvU32 (*__binapiprivGetRefCount__)(struct BinaryApiPrivileged *); - NV_STATUS (*__binapiprivCheckMemInterUnmap__)(struct BinaryApiPrivileged *, NvBool); - NV_STATUS (*__binapiprivMapTo__)(struct BinaryApiPrivileged *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__binapiprivControl_Prologue__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__binapiprivGetRegBaseOffsetAndSize__)(struct BinaryApiPrivileged *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__binapiprivControlSerialization_Prologue__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__binapiprivCanCopy__)(struct BinaryApiPrivileged *); - NV_STATUS (*__binapiprivInternalControlForward__)(struct BinaryApiPrivileged *, NvU32, void *, NvU32); void (*__binapiprivPreDestruct__)(struct BinaryApiPrivileged *); - NV_STATUS (*__binapiprivUnmapFrom__)(struct BinaryApiPrivileged *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__binapiprivIsDuplicate__)(struct BinaryApiPrivileged *, NvHandle, NvBool *); - void (*__binapiprivControl_Epilogue__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__binapiprivControlLookup__)(struct BinaryApiPrivileged *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__binapiprivControlSerialization_Epilogue__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__binapiprivMap__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__binapiprivAccessCallback__)(struct BinaryApiPrivileged *, struct RsClient *, void *, RsAccessRight); }; @@ -300,25 +314,27 @@ NV_STATUS __nvoc_objCreate_BinaryApiPrivileged(BinaryApiPrivileged**, Dynamic*, #define binapiprivControl(pResource, pCallContext, pParams) binapiprivControl_DISPATCH(pResource, pCallContext, pParams) #define binapiprivShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) binapiprivShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define binapiprivCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) binapiprivCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define binapiprivMapTo(pResource, pParams) binapiprivMapTo_DISPATCH(pResource, pParams) +#define binapiprivGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) binapiprivGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define binapiprivGetRefCount(pResource) binapiprivGetRefCount_DISPATCH(pResource) +#define binapiprivAddAdditionalDependants(pClient, pResource, pReference) binapiprivAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define binapiprivControl_Prologue(pResource, pCallContext, pParams) binapiprivControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define binapiprivGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) binapiprivGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define binapiprivInternalControlForward(pGpuResource, command, pParams, size) binapiprivInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define binapiprivUnmapFrom(pResource, pParams) binapiprivUnmapFrom_DISPATCH(pResource, pParams) +#define binapiprivControl_Epilogue(pResource, pCallContext, pParams) binapiprivControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define binapiprivControlLookup(pResource, pParams, ppEntry) binapiprivControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define binapiprivGetInternalObjectHandle(pGpuResource) binapiprivGetInternalObjectHandle_DISPATCH(pGpuResource) #define binapiprivUnmap(pGpuResource, pCallContext, pCpuMapping) binapiprivUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define binapiprivGetMemInterMapParams(pRmResource, pParams) binapiprivGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define binapiprivGetMemoryMappingDescriptor(pRmResource, ppMemDesc) binapiprivGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define binapiprivGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) binapiprivGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define binapiprivGetInternalObjectHandle(pGpuResource) binapiprivGetInternalObjectHandle_DISPATCH(pGpuResource) #define binapiprivControlFilter(pResource, pCallContext, pParams) binapiprivControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define binapiprivAddAdditionalDependants(pClient, pResource, pReference) binapiprivAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define binapiprivGetRefCount(pResource) binapiprivGetRefCount_DISPATCH(pResource) -#define binapiprivCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) binapiprivCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define binapiprivMapTo(pResource, pParams) binapiprivMapTo_DISPATCH(pResource, pParams) -#define binapiprivControl_Prologue(pResource, pCallContext, pParams) binapiprivControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define binapiprivGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) binapiprivGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define binapiprivControlSerialization_Prologue(pResource, pCallContext, pParams) binapiprivControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define binapiprivCanCopy(pResource) binapiprivCanCopy_DISPATCH(pResource) -#define binapiprivInternalControlForward(pGpuResource, command, pParams, size) binapiprivInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define binapiprivPreDestruct(pResource) binapiprivPreDestruct_DISPATCH(pResource) -#define binapiprivUnmapFrom(pResource, pParams) binapiprivUnmapFrom_DISPATCH(pResource, pParams) #define binapiprivIsDuplicate(pResource, hMemory, pDuplicate) binapiprivIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) -#define binapiprivControl_Epilogue(pResource, pCallContext, pParams) binapiprivControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define binapiprivControlLookup(pResource, pParams, ppEntry) binapiprivControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define binapiprivControlSerialization_Epilogue(pResource, pCallContext, pParams) binapiprivControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define binapiprivMap(pGpuResource, pCallContext, pParams, pCpuMapping) binapiprivMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define binapiprivAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) binapiprivAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS binapiprivControl_IMPL(struct BinaryApiPrivileged *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); @@ -331,6 +347,54 @@ static inline NvBool binapiprivShareCallback_DISPATCH(struct BinaryApiPrivileged return pGpuResource->__binapiprivShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } +static inline NV_STATUS binapiprivCheckMemInterUnmap_DISPATCH(struct BinaryApiPrivileged *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__binapiprivCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS binapiprivMapTo_DISPATCH(struct BinaryApiPrivileged *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__binapiprivMapTo__(pResource, pParams); +} + +static inline NV_STATUS binapiprivGetMapAddrSpace_DISPATCH(struct BinaryApiPrivileged *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__binapiprivGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 binapiprivGetRefCount_DISPATCH(struct BinaryApiPrivileged *pResource) { + return pResource->__binapiprivGetRefCount__(pResource); +} + +static inline void binapiprivAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct BinaryApiPrivileged *pResource, RsResourceRef *pReference) { + pResource->__binapiprivAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS binapiprivControl_Prologue_DISPATCH(struct BinaryApiPrivileged *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__binapiprivControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS binapiprivGetRegBaseOffsetAndSize_DISPATCH(struct BinaryApiPrivileged *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__binapiprivGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS binapiprivInternalControlForward_DISPATCH(struct BinaryApiPrivileged *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__binapiprivInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS binapiprivUnmapFrom_DISPATCH(struct BinaryApiPrivileged *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__binapiprivUnmapFrom__(pResource, pParams); +} + +static inline void binapiprivControl_Epilogue_DISPATCH(struct BinaryApiPrivileged *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__binapiprivControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS binapiprivControlLookup_DISPATCH(struct BinaryApiPrivileged *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__binapiprivControlLookup__(pResource, pParams, ppEntry); +} + +static inline NvHandle binapiprivGetInternalObjectHandle_DISPATCH(struct BinaryApiPrivileged *pGpuResource) { + return pGpuResource->__binapiprivGetInternalObjectHandle__(pGpuResource); +} + static inline NV_STATUS binapiprivUnmap_DISPATCH(struct BinaryApiPrivileged *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { return pGpuResource->__binapiprivUnmap__(pGpuResource, pCallContext, pCpuMapping); } @@ -343,68 +407,28 @@ static inline NV_STATUS binapiprivGetMemoryMappingDescriptor_DISPATCH(struct Bin return pRmResource->__binapiprivGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS binapiprivGetMapAddrSpace_DISPATCH(struct BinaryApiPrivileged *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__binapiprivGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvHandle binapiprivGetInternalObjectHandle_DISPATCH(struct BinaryApiPrivileged *pGpuResource) { - return pGpuResource->__binapiprivGetInternalObjectHandle__(pGpuResource); -} - static inline NV_STATUS binapiprivControlFilter_DISPATCH(struct BinaryApiPrivileged *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__binapiprivControlFilter__(pResource, pCallContext, pParams); } -static inline void binapiprivAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct BinaryApiPrivileged *pResource, RsResourceRef *pReference) { - pResource->__binapiprivAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 binapiprivGetRefCount_DISPATCH(struct BinaryApiPrivileged *pResource) { - return pResource->__binapiprivGetRefCount__(pResource); -} - -static inline NV_STATUS binapiprivCheckMemInterUnmap_DISPATCH(struct BinaryApiPrivileged *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__binapiprivCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS binapiprivMapTo_DISPATCH(struct BinaryApiPrivileged *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__binapiprivMapTo__(pResource, pParams); -} - -static inline NV_STATUS binapiprivControl_Prologue_DISPATCH(struct BinaryApiPrivileged *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__binapiprivControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS binapiprivGetRegBaseOffsetAndSize_DISPATCH(struct BinaryApiPrivileged *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__binapiprivGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +static inline NV_STATUS binapiprivControlSerialization_Prologue_DISPATCH(struct BinaryApiPrivileged *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__binapiprivControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool binapiprivCanCopy_DISPATCH(struct BinaryApiPrivileged *pResource) { return pResource->__binapiprivCanCopy__(pResource); } -static inline NV_STATUS binapiprivInternalControlForward_DISPATCH(struct BinaryApiPrivileged *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__binapiprivInternalControlForward__(pGpuResource, command, pParams, size); -} - static inline void binapiprivPreDestruct_DISPATCH(struct BinaryApiPrivileged *pResource) { pResource->__binapiprivPreDestruct__(pResource); } -static inline NV_STATUS binapiprivUnmapFrom_DISPATCH(struct BinaryApiPrivileged *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__binapiprivUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS binapiprivIsDuplicate_DISPATCH(struct BinaryApiPrivileged *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__binapiprivIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline void binapiprivControl_Epilogue_DISPATCH(struct BinaryApiPrivileged *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__binapiprivControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS binapiprivControlLookup_DISPATCH(struct BinaryApiPrivileged *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__binapiprivControlLookup__(pResource, pParams, ppEntry); +static inline void binapiprivControlSerialization_Epilogue_DISPATCH(struct BinaryApiPrivileged *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__binapiprivControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS binapiprivMap_DISPATCH(struct BinaryApiPrivileged *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c index f00b3cb1a..ffead9b0b 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c @@ -34,1387 +34,1634 @@ // VAR NAME: booter_ucode_data_ad10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 33024 -// COMPRESSED SIZE (bytes): 22004 +// DATA SIZE (bytes): 37120 +// COMPRESSED SIZE (bytes): 25955 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_image_dbg_data[] = { - 0xed, 0xdc, 0x73, 0xac, 0xac, 0xcd, 0x03, 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0xf9, 0xbf, 0xb7, 0xfb, 0x7f, 0x97, 0x01, 0x90, 0xbc, 0xfe, 0xb7, 0x54, 0x4e, 0x4d, + 0x49, 0x4e, 0x9c, 0xc0, 0xd4, 0xce, 0xdc, 0xd2, 0xce, 0xf4, 0x3f, 0x05, 0x05, 0x69, 0xc1, 0xff, + 0x29, 0x10, 0x68, 0x2b, 0x29, 0x0b, 0x12, 0xd8, 0xda, 0x9b, 0x98, 0xea, 0xfe, 0x57, 0xbd, 0xa8, + 0xb0, 0xf0, 0xff, 0xd4, 0xff, 0x87, 0x06, 0x05, 0x00, 0x00, 0xc1, 0x7f, 0x82, 0xf1, 0x3f, 0x79, + 0x82, 0xff, 0x9b, 0x3f, 0x13, 0xcc, 0x7f, 0x02, 0xfd, 0x3f, 0x41, 0xf8, 0x9f, 0x30, 0xfd, 0x4f, + 0x1f, 0x0c, 0xff, 0x2b, 0xfe, 0x93, 0x07, 0x02, 0xfc, 0xff, 0xde, 0x9e, 0xea, 0xff, 0x42, 0x5f, + 0x68, 0x00, 0xff, 0xfb, 0xfb, 0xf7, 0xfd, 0x3f, 0xf4, 0x03, 0x02, 0xf1, 0x7f, 0xde, 0x3e, 0xfd, + 0xff, 0x90, 0xcf, 0xf8, 0x4f, 0x64, 0xfe, 0x27, 0xc4, 0xff, 0x13, 0x12, 0xff, 0x09, 0xc9, 0xff, + 0x84, 0xd4, 0xff, 0xbc, 0x26, 0xf3, 0x3f, 0xa9, 0xec, 0x7f, 0xf5, 0x23, 0xf0, 0x3f, 0xfd, 0xfc, + 0xaf, 0xb1, 0xfb, 0xdf, 0xbe, 0x03, 0x80, 0xff, 0x0c, 0x31, 0x80, 0xb2, 0x28, 0x03, 0x80, 0xf0, + 0x7f, 0x86, 0xd7, 0xd0, 0xc9, 0xd2, 0xc5, 0xc2, 0xd6, 0xd4, 0xc5, 0xd2, 0x98, 0xc0, 0xd4, 0xc9, + 0xc9, 0xde, 0x09, 0xea, 0xff, 0xa4, 0xf6, 0xff, 0x39, 0xfe, 0x5f, 0x5f, 0xc3, 0xce, 0xbd, 0x00, + 0x91, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1424,8 +1671,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 33024, // uncompressed data size (bytes) - 22004, // compressed data size (bytes) + 37120, // uncompressed data size (bytes) + 25955, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_AD102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1447,8 +1694,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x0e, 0x07, 0x62, 0x4d, 0x08, 0x13, 0x4c, 0x84, 0x41, 0x69, - 0x20, 0x00, 0x00, 0xd5, 0x45, 0x9c, 0x39, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x4e, 0x03, 0x62, 0x6d, 0x08, 0x13, 0x4c, 0xa4, 0x42, 0x69, + 0x20, 0x00, 0x00, 0x9f, 0x5d, 0x93, 0xe9, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1476,1386 +1723,1634 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_header_dbg_storage_pvt; // VAR NAME: booter_ucode_data_ad10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 33024 -// COMPRESSED SIZE (bytes): 22000 +// DATA SIZE (bytes): 37120 +// COMPRESSED SIZE (bytes): 25956 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_image_prod_data[] = { - 0xed, 0xfc, 0x73, 0xac, 0xec, 0x41, 0xc3, 0x07, 0x78, 0x1e, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0xcd, - 0x7b, 0x6c, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xf6, 0x3d, 0xb6, 0xe7, 0x99, 0x99, 0x77, - 0x32, 0x93, 0x67, 0x77, 0xfe, 0xd9, 0xdd, 0x64, 0x93, 0xdd, 0xfb, 0x49, 0xbe, 0x5d, 0xe8, 0x4a, - 0xaa, 0xbb, 0x3a, 0xbf, 0x4a, 0xba, 0xbb, 0xba, 0x01, 0x00, 0xfe, 0xff, 0x9b, 0xf0, 0xc5, 0x07, - 0x5c, 0x24, 0x76, 0xe4, 0xac, 0x50, 0x78, 0x29, 0x30, 0xa3, 0x4f, 0xe6, 0x5f, 0x91, 0x59, 0x6d, - 0xb3, 0xa6, 0xe7, 0x27, 0x21, 0x17, 0xa2, 0xd8, 0xb8, 0x9d, 0x78, 0xae, 0x0b, 0x5d, 0x33, 0xe2, - 0x76, 0x05, 0x5e, 0x3a, 0xf0, 0x9f, 0x1f, 0x11, 0x4e, 0x3d, 0x62, 0x19, 0xc9, 0xeb, 0x66, 0x9b, - 0xaa, 0xd9, 0xd7, 0xe1, 0xe1, 0x44, 0x85, 0xd8, 0x33, 0x9d, 0x1d, 0x65, 0x7f, 0x45, 0x62, 0x5a, - 0xd0, 0x29, 0x39, 0x25, 0x25, 0x83, 0x15, 0x93, 0xec, 0x4f, 0xbd, 0x89, 0xa5, 0x83, 0x90, 0x82, - 0x16, 0x49, 0xc8, 0x0d, 0xdd, 0x38, 0xf7, 0xa9, 0xd7, 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0xcf, 0x10, 0x03, 0x28, 0x8b, 0x32, 0x00, 0x08, + 0xff, 0x33, 0xbc, 0x86, 0x8e, 0x96, 0xce, 0x16, 0xb6, 0xa6, 0xce, 0x96, 0xc6, 0x04, 0xa6, 0x8e, + 0x8e, 0xf6, 0x8e, 0x50, 0xff, 0x8b, 0xda, 0xff, 0xff, 0xf8, 0xdf, 0x00, 0x3c, 0xf2, 0xf4, 0x13, + 0x00, 0x91, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2865,8 +3360,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 33024, // uncompressed data size (bytes) - 22000, // compressed data size (bytes) + 37120, // uncompressed data size (bytes) + 25956, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_AD102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -2888,8 +3383,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_image_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x0e, 0x07, 0x62, 0x4d, 0x08, 0x13, 0x4c, 0x84, 0x41, 0x69, - 0x20, 0x00, 0x00, 0xd5, 0x45, 0x9c, 0x39, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x4e, 0x03, 0x62, 0x6d, 0x08, 0x13, 0x4c, 0xa4, 0x42, 0x69, + 0x20, 0x00, 0x00, 0x9f, 0x5d, 0x93, 0xe9, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2922,55 +3417,55 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_header_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_sig_dbg_data[] = { - 0x01, 0x00, 0x03, 0xff, 0xfc, 0x6c, 0x0e, 0x43, 0x32, 0x75, 0x20, 0x86, 0x2c, 0x6c, 0xe5, 0x3a, - 0xeb, 0xc9, 0x91, 0x96, 0xd9, 0x07, 0x15, 0x0b, 0xd1, 0xea, 0xb6, 0xce, 0xa1, 0xf1, 0xb5, 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0xf9, 0xb3, 0x28, 0x69, + 0xfa, 0x9a, 0xef, 0x22, 0x98, 0xd1, 0x4a, 0x91, 0x2c, 0xb7, 0xd3, 0xad, 0x30, 0x84, 0x0a, 0x84, + 0x41, 0x80, 0x26, 0xd1, 0x26, 0x1b, 0x51, 0xf1, 0xc0, 0x00, 0x03, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3084,7 +3579,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_patch_loc_data[] = { - 0x10, 0x57, 0x00, 0x00, + 0x10, 0x66, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c index 9b221d6f8..25899e9d4 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c @@ -34,1501 +34,1794 @@ // VAR NAME: booter_ucode_data_ga100 // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 36352 -// COMPRESSED SIZE (bytes): 23832 +// DATA SIZE (bytes): 40704 +// COMPRESSED SIZE (bytes): 28516 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_image_dbg_data[] = { - 0xed, 0xfc, 0x43, 0x90, 0x28, 0x4d, 0xc3, 0x06, 0x6c, 0xb6, 0x6d, 0xdb, 0xb6, 0x4f, 0xdb, 0xc6, - 0x69, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0x76, 0xf7, 0xff, 0x7e, 0x13, - 0x31, 0x9b, 0x67, 0x37, 0xbb, 0x99, 0x89, 0x73, 0x6d, 0x12, 0x11, 0x95, 0x95, 0x8b, 0xaa, 0x8c, - 0x8a, 0xb8, 0x33, 0x4b, 0x02, 0x00, 0x61, 0x26, 0x1d, 0x20, 0x16, 0x00, 0x1c, 0xa0, 0xfb, 0x28, - 0xef, 0xbd, 0xf9, 0x07, 0x50, 0x02, 0x00, 0xf1, 0xff, 0x3a, 0x20, 0xc0, 0x01, 0xfe, 0x5f, 0xcd, - 0x70, 0x00, 0x00, 0xc0, 0x9f, 0x24, 0x00, 0x1f, 0x7a, 0x00, 0x80, 0x37, 0xa0, 0x37, 0x80, 0x77, - 0xa0, 0x68, 0x00, 0x20, 0x80, 0xde, 0x9d, 0xdd, 0xdf, 0xdf, 0x5f, 0xf8, 0x70, 0x00, 0x40, 0x80, - 0xdf, 0x5c, 0x90, 0xc6, 0x23, 0x00, 0xe6, 0xb4, 0x75, 0xc0, 0xc6, 0x24, 0x00, 0x9a, 0xb4, 0x75, - 0xa0, 0xff, 0x15, 0xa4, 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0xfc, 0xf3, 0xcf, 0x3f, + 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, + 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, + 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0xff, 0x0b, 0xfc, 0x7f, 0x00, 0x8d, 0x0d, 0xfe, 0xdd, + 0x00, 0x9f, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1538,8 +1831,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 36352, // uncompressed data size (bytes) - 23832, // compressed data size (bytes) + 40704, // uncompressed data size (bytes) + 28516, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA100_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1561,8 +1854,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x4e, 0x00, 0x62, 0x3d, 0x08, 0x13, 0x4c, 0xc4, 0x43, 0x69, - 0x20, 0x00, 0x00, 0x87, 0x58, 0x20, 0x04, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x2e, 0x00, 0x62, 0x7d, 0x08, 0x13, 0x4c, 0xe4, 0x43, 0x69, + 0x20, 0x00, 0x00, 0x1a, 0x52, 0x4d, 0xe9, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1590,1501 +1883,1794 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_header_dbg_storage_pvt; // VAR NAME: booter_ucode_data_ga100 // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 36352 -// COMPRESSED SIZE (bytes): 23828 +// DATA SIZE (bytes): 40704 +// COMPRESSED SIZE (bytes): 28514 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_image_prod_data[] = { - 0xed, 0xfc, 0x43, 0xb0, 0x68, 0x4d, 0xdb, 0x06, 0xe0, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, - 0xdb, 0xb6, 0x6d, 0xfb, 0x6c, 0xdb, 0xb6, 0xed, 0xb3, 0x6d, 0xdb, 0x36, 0xf3, 0xfd, 0xa9, 0xca, - 0xe4, 0xcd, 0x28, 0xb3, 0x24, 0x75, 0xae, 0x49, 0xa3, 0x6a, 0xad, 0xd5, 0x93, 0xee, 0xc9, 0xdd, - 0xcf, 0x92, 0x04, 0x40, 0x98, 0xcd, 0x04, 0x88, 0x07, 0x00, 0x07, 0xe8, 0x39, 0xca, 0x7f, 0x6f, - 0xf9, 0x01, 0x94, 0x04, 0x40, 0xfc, 0xbf, 0x09, 0x08, 0x70, 0x80, 0xff, 0xe7, 0x30, 0x12, 0x00, - 0x00, 0xf0, 0x27, 0x05, 0xc0, 0x8f, 0x1e, 0x00, 0xe0, 0x0d, 0xe8, 0x0d, 0xe0, 0x1d, 0x28, 0x16, - 0x00, 0x08, 0xa0, 0x6f, 0x67, 0xf7, 0xf7, 0xf7, 0x17, 0x3e, 0x12, 0x00, 0x10, 0xe0, 0x37, 0x0f, - 0xa4, 0xe9, 0x08, 0x80, 0x39, 0x63, 0x1d, 0xb0, 0x29, 0x05, 0x80, 0x26, 0x63, 0x1d, 0xe8, 0x7f, - 0x0d, 0x69, 0xc6, 0x3a, 0xf0, 0xff, 0x1a, 0xbc, 0xff, 0x3d, 0x0b, 0x90, 0x91, 0x07, 0xdc, 0xb2, - 0x0b, 0xdc, 0x97, 0x97, 0xbf, 0x9b, 0x91, 0x07, 0x98, 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0xa0, 0x75, 0x6a, 0xff, 0xbd, 0x3e, 0xec, 0x8e, 0xf2, 0xf1, 0x54, 0xe6, 0xf9, 0x6c, + 0x14, 0x62, 0x1b, 0x2b, 0xe6, 0x68, 0x39, 0xc3, 0x7f, 0xaf, 0xaf, 0x83, 0x7b, 0xfa, 0x9a, 0xef, + 0x45, 0x2d, 0xcd, 0x38, 0x45, 0xf2, 0xe6, 0xea, 0x4e, 0xd3, 0xb5, 0x0c, 0x27, 0x05, 0x0c, 0x70, + 0x30, 0x02, 0xb0, 0xca, 0x13, 0x3f, 0x4f, 0x30, 0x6c, 0xc1, 0xbe, 0xcc, 0xb8, 0xe8, 0x25, 0x70, + 0x8e, 0x74, 0xc4, 0x65, 0xa7, 0x74, 0x5a, 0xd5, 0x56, 0x34, 0xc4, 0xc8, 0xb5, 0x7f, 0x99, 0x34, + 0x83, 0xce, 0x3f, 0x40, 0x16, 0x80, 0x61, 0xc7, 0xad, 0x82, 0xb5, 0xb9, 0xed, 0x49, 0x02, 0xd2, + 0x37, 0xa5, 0x75, 0xb1, 0x5e, 0x9d, 0x08, 0xb0, 0xa8, 0x2c, 0x99, 0x5c, 0xc8, 0x74, 0xe1, 0xd8, + 0xde, 0x4c, 0x79, 0x6f, 0x01, 0xa6, 0x75, 0xd1, 0x1b, 0x95, 0x0f, 0xf0, 0xcf, 0x3f, 0xff, 0xfc, + 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, + 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, + 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, + 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0x1f, 0xf0, 0xff, 0x00, 0x56, 0x0b, 0xad, 0xbe, 0x00, 0x9f, + 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3094,8 +3680,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 36352, // uncompressed data size (bytes) - 23828, // compressed data size (bytes) + 40704, // uncompressed data size (bytes) + 28514, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA100_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -3117,8 +3703,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_image_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x4e, 0x00, 0x62, 0x3d, 0x08, 0x13, 0x4c, 0xc4, 0x43, 0x69, - 0x20, 0x00, 0x00, 0x87, 0x58, 0x20, 0x04, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x2e, 0x00, 0x62, 0x7d, 0x08, 0x13, 0x4c, 0xe4, 0x43, 0x69, + 0x20, 0x00, 0x00, 0x1a, 0x52, 0x4d, 0xe9, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3151,31 +3737,31 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_header_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_sig_dbg_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x40, 0x07, 0xac, 0x9b, 0x5d, 0xf4, 0x1d, 0xdd, 0x6b, 0xd5, 0x5a, - 0xf1, 0xef, 0x4c, 0x4b, 0x38, 0x51, 0x2c, 0x5e, 0x3e, 0xed, 0x96, 0x68, 0xad, 0xda, 0x7e, 0xf0, - 0x11, 0xa2, 0x77, 0x1a, 0xf0, 0xe6, 0x27, 0x8e, 0xaf, 0xd1, 0xa3, 0x5c, 0x1b, 0xbb, 0x3b, 0x7e, - 0xf7, 0xd7, 0x80, 0x80, 0x71, 0x9d, 0x4b, 0xa5, 0xdf, 0x9e, 0x82, 0x18, 0xa1, 0x1a, 0x5b, 0x6c, - 0xc8, 0x7c, 0x07, 0x09, 0xa8, 0xfd, 0xc6, 0x46, 0x6d, 0x00, 0xeb, 0xc3, 0x82, 0x94, 0xb5, 0x54, - 0x6f, 0xbc, 0x65, 0xbd, 0xb8, 0xcc, 0x4a, 0xde, 0xca, 0x33, 0xf9, 0xfd, 0x47, 0xb6, 0x77, 0x54, - 0xf4, 0xec, 0xfc, 0x3a, 0xa2, 0xf9, 0x2d, 0x9c, 0xd5, 0x89, 0x90, 0x79, 0xb7, 0x52, 0xc2, 0x61, - 0x8f, 0x07, 0x41, 0xc7, 0x1f, 0x2e, 0x5c, 0xf2, 0xe5, 0xd3, 0x80, 0x9d, 0x28, 0x89, 0x37, 0xab, - 0xdd, 0xc0, 0x63, 0xc6, 0x21, 0x29, 0x84, 0x7a, 0x71, 0x23, 0x82, 0x92, 0x81, 0xb2, 0x38, 0x36, - 0xa7, 0xe9, 0xef, 0xa9, 0x60, 0x09, 0x32, 0x8a, 0x68, 0xac, 0x5e, 0x20, 0x7d, 0x9c, 0xe8, 0x0c, - 0xea, 0xb9, 0x6c, 0x17, 0x10, 0xae, 0x75, 0x0f, 0x8e, 0xd1, 0x5c, 0xe4, 0x98, 0x34, 0xf5, 0x40, - 0xdb, 0x1c, 0x9e, 0xe7, 0x19, 0xd6, 0x2f, 0x8e, 0x88, 0xfc, 0x51, 0x12, 0x80, 0x57, 0x83, 0xca, - 0x56, 0x83, 0xc7, 0x68, 0xf5, 0xe4, 0x63, 0xcb, 0x98, 0xc3, 0x4d, 0x29, 0x56, 0x68, 0x7f, 0xad, - 0xa5, 0xe6, 0x01, 0x5a, 0x03, 0xdb, 0x95, 0xaa, 0xec, 0x32, 0x78, 0x3a, 0xeb, 0x24, 0x6d, 0x41, - 0x61, 0xd5, 0x3d, 0x7f, 0x56, 0xe6, 0x37, 0x8a, 0x00, 0x9e, 0x62, 0x18, 0x1d, 0xca, 0x0b, 0x7e, - 0x9a, 0x15, 0xcf, 0x6a, 0xf2, 0xb1, 0x6b, 0x4d, 0xf4, 0xdb, 0xf7, 0xe0, 0x96, 0xa6, 0xbf, 0x1d, - 0x31, 0x7d, 0x21, 0xdc, 0xbb, 0x1a, 0xe4, 0x45, 0xf8, 0xa1, 0xaa, 0x91, 0xfb, 0xc8, 0x07, 0x4d, - 0xb4, 0x36, 0x7d, 0xaa, 0x2a, 0x3e, 0x19, 0xdf, 0x59, 0x77, 0xab, 0xbc, 0xf7, 0x44, 0x89, 0xcc, - 0xe4, 0x4d, 0x3f, 0xc6, 0x5f, 0x82, 0xf0, 0xde, 0x6b, 0x83, 0xdd, 0x5b, 0xe9, 0x15, 0x89, 0x0d, - 0x56, 0x1f, 0x83, 0xc4, 0x10, 0xc5, 0xe6, 0xbe, 0xcb, 0x24, 0x6d, 0x66, 0x2b, 0xdd, 0xdf, 0xc5, - 0xa6, 0x03, 0x90, 0xe4, 0xb7, 0xc3, 0x33, 0x28, 0x59, 0xa6, 0x62, 0x45, 0xf3, 0x97, 0xbd, 0xd2, - 0x99, 0x3f, 0x82, 0x69, 0xa2, 0xcb, 0xe7, 0x2a, 0xe9, 0x51, 0xe7, 0x3d, 0x41, 0x52, 0x74, 0x7b, - 0xfd, 0x02, 0x0f, 0x74, 0xa0, 0xfe, 0xc5, 0x37, 0x51, 0x97, 0xe7, 0x1d, 0xd4, 0x9d, 0xe1, 0xe2, - 0x1e, 0xb1, 0x24, 0x88, 0xe1, 0xd6, 0x29, 0x14, 0xaf, 0xba, 0x9f, 0xd3, 0x93, 0x4a, 0x97, 0x79, - 0x82, 0xaf, 0x03, 0xa7, 0x12, 0xa2, 0x10, 0xd8, 0x8b, 0x80, 0x01, 0x00, 0x00, + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0xe5, 0x3a, 0x94, 0x96, 0x95, 0x55, 0x26, 0x8f, 0x19, 0x5f, 0x14, + 0xe5, 0x91, 0x1c, 0x16, 0x26, 0xca, 0xac, 0xc2, 0x66, 0x7f, 0x05, 0x1b, 0xed, 0x62, 0xb5, 0x6b, + 0xb2, 0xb0, 0x67, 0x10, 0x27, 0x56, 0xe5, 0xe7, 0x6f, 0x32, 0xba, 0xf1, 0x43, 0x78, 0x92, 0x48, + 0xe4, 0xc5, 0x51, 0xe6, 0xc9, 0x15, 0x05, 0xd5, 0xfd, 0x79, 0x42, 0x03, 0x15, 0xeb, 0x76, 0xee, + 0xb3, 0x9a, 0xae, 0x42, 0xec, 0x39, 0xb0, 0x28, 0x1d, 0xb7, 0xe3, 0xa2, 0x72, 0x0f, 0x34, 0xbd, + 0x57, 0xb8, 0x4f, 0x5b, 0x5c, 0x2b, 0x9e, 0x0f, 0x1a, 0x8b, 0x66, 0x98, 0x16, 0xd4, 0x4b, 0x10, + 0x3b, 0xdb, 0x6c, 0x1a, 0xea, 0xd5, 0xc2, 0xfd, 0x72, 0x79, 0x92, 0x22, 0x3a, 0xb9, 0xaa, 0x8c, + 0x6a, 0xe4, 0x05, 0x32, 0x47, 0x12, 0xf0, 0x78, 0xfa, 0xa8, 0xd6, 0x2d, 0x39, 0x33, 0x5b, 0x94, + 0x93, 0x91, 0x93, 0xb3, 0xbc, 0xd0, 0x44, 0x20, 0x5c, 0xe2, 0x8a, 0xd2, 0x41, 0xc2, 0xae, 0x45, + 0xaa, 0x96, 0xef, 0x4f, 0x73, 0x07, 0xaa, 0x6a, 0x79, 0xde, 0xb6, 0xbd, 0x6a, 0x6c, 0x98, 0xd7, + 0x07, 0x43, 0xa6, 0x6e, 0x62, 0xd6, 0x97, 0x5d, 0x01, 0xf0, 0xe0, 0x0f, 0xc2, 0x84, 0x51, 0x8f, + 0x23, 0x94, 0xb9, 0xf6, 0xa2, 0xbf, 0xde, 0x81, 0x84, 0xd4, 0xed, 0x03, 0xf1, 0x8c, 0xc7, 0xd0, + 0x6c, 0x93, 0x40, 0x91, 0xcc, 0x4c, 0x9f, 0x13, 0xd3, 0x10, 0x7a, 0x0e, 0xc1, 0x1b, 0x1b, 0x02, + 0x9b, 0xa4, 0x59, 0x06, 0x9a, 0x21, 0x66, 0x3c, 0xae, 0xda, 0xf5, 0xd3, 0x4a, 0xe7, 0x4c, 0xef, + 0x85, 0x88, 0x16, 0x04, 0x03, 0xf7, 0x02, 0x67, 0x0e, 0x7e, 0xdf, 0x8c, 0x4c, 0xca, 0xc1, 0x06, + 0x3a, 0x4c, 0xf8, 0xef, 0xe6, 0x1f, 0x9d, 0x95, 0x60, 0x0d, 0xf0, 0xb6, 0xe5, 0xe1, 0xe4, 0x80, + 0x24, 0xef, 0x9d, 0x22, 0x9c, 0x09, 0xa6, 0xae, 0x2a, 0xe9, 0xeb, 0xa3, 0x55, 0x2d, 0x1a, 0xd5, + 0x4a, 0x81, 0x3d, 0x03, 0xc6, 0x9d, 0xc3, 0x64, 0x8a, 0xe3, 0xc8, 0x23, 0x90, 0x93, 0x77, 0x8b, + 0xdc, 0xf7, 0xa4, 0xd3, 0xec, 0x3c, 0xa6, 0x9c, 0x41, 0xc6, 0xa1, 0xe4, 0xd5, 0xe4, 0xf2, 0x30, + 0xb9, 0x5d, 0x00, 0x4b, 0x3a, 0x0c, 0x3b, 0x67, 0xaf, 0x00, 0x34, 0x6d, 0x11, 0x05, 0xdb, 0x42, + 0x11, 0x3a, 0x08, 0xc6, 0x53, 0x5a, 0xda, 0xdf, 0x9f, 0x9d, 0xe7, 0x18, 0x59, 0xc6, 0x06, 0x70, + 0xae, 0xd6, 0x0c, 0xd7, 0xba, 0x43, 0xbd, 0x6c, 0x21, 0x13, 0x3f, 0xdd, 0x27, 0xaf, 0x68, 0x66, + 0x63, 0x99, 0x33, 0x12, 0x98, 0x80, 0x0b, 0x56, 0x42, 0x00, 0x76, 0xf0, 0x92, 0x5f, 0xd9, 0xac, + 0x73, 0x1a, 0x52, 0x02, 0x23, 0xca, 0x82, 0xf8, 0x15, 0x9a, 0x47, 0x9b, 0x78, 0x5b, 0xdf, 0xd9, + 0xcb, 0x81, 0xb0, 0x6e, 0x91, 0xd4, 0xcd, 0xa6, 0xbe, 0x80, 0x01, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3208,31 +3794,31 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_sig_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_sig_prod_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0xab, 0xf2, 0xff, 0xd7, 0x03, 0x58, 0xb3, 0xc7, 0xdb, 0xb5, 0xc8, - 0xcf, 0xde, 0xf4, 0x3d, 0xe1, 0x67, 0x8a, 0x76, 0x59, 0x3b, 0xa2, 0x10, 0x91, 0x47, 0xa6, 0x27, - 0x0c, 0xbb, 0xb3, 0x7f, 0x16, 0xc0, 0xa8, 0x89, 0x4b, 0x32, 0xdc, 0xe9, 0x85, 0x24, 0xde, 0x32, - 0x79, 0x68, 0x16, 0xf6, 0xb3, 0xbd, 0xbe, 0x9f, 0xc5, 0x2b, 0xd7, 0x57, 0xaf, 0x35, 0x5d, 0x37, - 0xda, 0x5a, 0xe1, 0x04, 0xa4, 0xac, 0x6c, 0x7b, 0x12, 0x09, 0x29, 0xaf, 0x70, 0x2f, 0xbb, 0x41, - 0x13, 0x91, 0xe3, 0xaf, 0x8c, 0xd5, 0xa3, 0x38, 0x0a, 0xb0, 0x7d, 0x15, 0x00, 0xd9, 0x07, 0x69, - 0x3c, 0xe9, 0x9d, 0xad, 0xc6, 0x34, 0x4b, 0x63, 0xfb, 0x91, 0x1d, 0x93, 0xd9, 0x6d, 0x44, 0x89, - 0xa1, 0xc5, 0x9c, 0x50, 0x0a, 0xdc, 0xd1, 0x02, 0xc3, 0x9a, 0x0a, 0x53, 0xf2, 0x2e, 0x40, 0xc8, - 0xdb, 0x75, 0xc8, 0xf4, 0xa9, 0x16, 0xee, 0x81, 0x03, 0x7f, 0x62, 0xfe, 0x98, 0x5f, 0x87, 0x0c, - 0xed, 0xa9, 0xd5, 0x04, 0x7e, 0xa7, 0x33, 0x28, 0x4c, 0xe4, 0xfc, 0x2d, 0x35, 0x76, 0x85, 0xc1, - 0xb2, 0x54, 0xb7, 0xbd, 0x5d, 0xde, 0x9c, 0xc0, 0x44, 0xc8, 0xbc, 0xa2, 0xb7, 0x6a, 0xa1, 0x42, - 0x71, 0x4a, 0x09, 0x9b, 0x19, 0x80, 0x44, 0xe3, 0x82, 0x38, 0xc0, 0xc8, 0x95, 0xd8, 0x80, 0xe5, - 0x47, 0xf2, 0xd4, 0x1b, 0xc7, 0x74, 0xb7, 0x67, 0xa5, 0x07, 0x19, 0x65, 0xb2, 0x2f, 0xaa, 0x62, - 0x99, 0xfc, 0x74, 0xc6, 0x83, 0x91, 0x9a, 0x49, 0x0a, 0x64, 0x84, 0xc7, 0x06, 0x5e, 0xe3, 0xde, - 0x32, 0xbe, 0xd4, 0x6d, 0x8e, 0x71, 0x0f, 0x57, 0xd8, 0x51, 0xda, 0xc0, 0x69, 0xa7, 0x90, 0x9e, - 0xfd, 0x32, 0xea, 0x85, 0x3d, 0x07, 0x60, 0xe3, 0x2a, 0x60, 0x0f, 0xe1, 0x77, 0x38, 0xa7, 0x45, - 0x05, 0x70, 0x23, 0x44, 0xae, 0x89, 0x02, 0x87, 0xd9, 0x54, 0x0b, 0xd6, 0x97, 0xb5, 0x0d, 0xc5, - 0x12, 0xd3, 0x91, 0x52, 0x9f, 0x37, 0xcf, 0xdf, 0x7e, 0x08, 0x79, 0x35, 0xad, 0x4a, 0xfa, 0xa5, - 0x2b, 0x34, 0xad, 0x87, 0x8a, 0xa8, 0x0b, 0x34, 0x47, 0x12, 0x1b, 0x78, 0xc3, 0x55, 0x91, 0x5a, - 0xb2, 0xdd, 0x9e, 0xc0, 0x25, 0xe7, 0x86, 0x93, 0x1a, 0xdb, 0x71, 0xea, 0xf6, 0xb8, 0xcf, 0x79, - 0x12, 0x1c, 0xf5, 0xbd, 0x5b, 0xa5, 0x0f, 0x84, 0x33, 0xba, 0x18, 0xa2, 0xdb, 0x74, 0xad, 0x3e, - 0x39, 0xe9, 0x89, 0xd7, 0xb9, 0xdf, 0x8c, 0xba, 0x3d, 0x55, 0xb6, 0x32, 0xb3, 0x8b, 0x23, 0x8c, - 0x52, 0x57, 0x66, 0x26, 0x56, 0xbf, 0x8f, 0xae, 0xf9, 0x90, 0xfd, 0xf4, 0xc3, 0x1a, 0x38, 0x77, - 0x6c, 0xf1, 0xc3, 0x61, 0xd5, 0x73, 0x11, 0x7d, 0x9c, 0x38, 0xdb, 0x75, 0x98, 0x37, 0x06, 0x99, - 0xee, 0x33, 0xfe, 0xd0, 0x9b, 0x7f, 0x80, 0x20, 0xcf, 0x80, 0x01, 0x00, 0x00, + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x05, 0x55, 0xf4, 0x0a, 0xf8, 0xa9, 0x87, 0xf9, 0x09, 0xd0, 0x64, + 0xcf, 0x89, 0x6d, 0x0f, 0xcc, 0xad, 0x20, 0x7a, 0x47, 0x37, 0xfa, 0x8c, 0x66, 0x25, 0x3b, 0x8e, + 0x71, 0x08, 0x30, 0x76, 0x3c, 0xd4, 0x0c, 0xf9, 0x83, 0x98, 0x41, 0xe2, 0x90, 0x62, 0x06, 0xe6, + 0xa3, 0x46, 0xcd, 0xc1, 0x35, 0x24, 0xa9, 0xfe, 0x2b, 0x4d, 0x1f, 0xb0, 0xfc, 0x36, 0x0b, 0x37, + 0x1b, 0x9e, 0x6c, 0x6d, 0x54, 0xdb, 0x62, 0xc0, 0x96, 0x81, 0x99, 0x3b, 0xfa, 0xc6, 0xae, 0xdb, + 0x31, 0xff, 0x34, 0xd4, 0x45, 0xa8, 0xee, 0x25, 0x36, 0xef, 0xa3, 0x6f, 0xe3, 0x33, 0x6d, 0x99, + 0x60, 0xc1, 0x43, 0xa7, 0x98, 0xc5, 0xe7, 0x8b, 0x0a, 0x72, 0xaf, 0xb3, 0x7f, 0x45, 0x0c, 0x31, + 0xd1, 0x69, 0x60, 0x88, 0x79, 0xb9, 0x77, 0x61, 0x3e, 0xf2, 0x4e, 0x23, 0x17, 0x12, 0x10, 0xa1, + 0x19, 0xfc, 0xd9, 0x26, 0xed, 0xb7, 0x5f, 0x63, 0xfe, 0xcf, 0x4c, 0x1d, 0xd7, 0xb0, 0xa4, 0xc0, + 0x53, 0x48, 0x87, 0x4d, 0x13, 0x11, 0x88, 0xfe, 0x89, 0x08, 0xc7, 0xa8, 0x36, 0x46, 0xda, 0x58, + 0x18, 0xd0, 0x6d, 0x36, 0xc2, 0x71, 0xf4, 0xa3, 0xa5, 0xcd, 0x7e, 0xf9, 0xdf, 0xd9, 0xa3, 0x66, + 0xaf, 0x2d, 0x34, 0xb7, 0xcb, 0x1e, 0x9a, 0xc0, 0xdb, 0xca, 0x15, 0xed, 0x95, 0x79, 0x07, 0x23, + 0xda, 0x75, 0x78, 0x15, 0x89, 0xc0, 0x71, 0x75, 0xc4, 0xf4, 0x65, 0x6a, 0xb0, 0xff, 0x82, 0x48, + 0x43, 0xa2, 0x96, 0xe4, 0x1b, 0xb5, 0xee, 0x37, 0x9f, 0x48, 0x6d, 0xcf, 0x7b, 0x5f, 0xe6, 0xbe, + 0x47, 0xb2, 0xa6, 0xdd, 0xa6, 0x84, 0x36, 0xd4, 0xde, 0x6e, 0x46, 0x1a, 0x65, 0x97, 0x8a, 0xe3, + 0xad, 0x07, 0x92, 0xe8, 0x84, 0x72, 0x35, 0xc3, 0xb5, 0x1d, 0x24, 0xb6, 0x3a, 0x14, 0x80, 0xef, + 0x2d, 0x70, 0x6d, 0x7b, 0x6a, 0x1b, 0x77, 0x07, 0xd2, 0xf9, 0xcd, 0x21, 0x9d, 0xd4, 0x56, 0x26, + 0x38, 0xbe, 0xcd, 0xab, 0x1c, 0xf2, 0x40, 0x15, 0xce, 0x11, 0xb1, 0x4a, 0x71, 0x51, 0x32, 0x12, + 0x94, 0x20, 0xc6, 0xa9, 0xe2, 0x88, 0xb6, 0xc5, 0x5d, 0xf7, 0x1d, 0x0a, 0x89, 0x5f, 0xd2, 0x61, + 0x16, 0xe6, 0xba, 0x48, 0x14, 0x54, 0xd0, 0x57, 0xdb, 0xe9, 0x8c, 0x82, 0x2d, 0xa1, 0x0c, 0xe2, + 0x6c, 0xba, 0xd8, 0x22, 0xfc, 0xee, 0xac, 0x51, 0xd1, 0x7e, 0x1c, 0x5f, 0x85, 0xa0, 0x59, 0xdf, + 0x6e, 0x31, 0x28, 0x26, 0x8f, 0xf6, 0x29, 0x03, 0x48, 0x5b, 0x09, 0x8b, 0xfd, 0xe7, 0x32, 0xb6, + 0xe5, 0x9f, 0x84, 0xba, 0xca, 0x42, 0x83, 0xdb, 0x39, 0x66, 0xa9, 0x81, 0xdf, 0x55, 0x7e, 0x52, + 0xec, 0x4f, 0x01, 0x18, 0x30, 0xa5, 0x58, 0xbe, 0x96, 0x9d, 0x04, 0x0d, 0x6e, 0x7e, 0x1c, 0x46, + 0xc8, 0xe8, 0x97, 0x78, 0x0f, 0x91, 0xa8, 0xbb, 0x8b, 0x80, 0x01, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3265,7 +3851,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_patch_loc_data[] = { - 0x00, 0x62, 0x00, 0x00, + 0x00, 0x72, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c index 84ae32666..527601813 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c @@ -34,1586 +34,1833 @@ // VAR NAME: booter_ucode_data_ga10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 36864 -// COMPRESSED SIZE (bytes): 25193 +// DATA SIZE (bytes): 41216 +// COMPRESSED SIZE (bytes): 29140 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_image_dbg_data[] = { - 0xed, 0xfd, 0x43, 0xb0, 0x30, 0x4b, 0xd7, 0x00, 0x6a, 0x6e, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, - 0xdb, 0xf6, 0xbb, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xbb, 0xff, 0xf1, 0x37, 0xe9, - 0x8e, 0xe8, 0xc1, 0x1d, 0xdc, 0xf3, 0xcc, 0x72, 0x54, 0x51, 0x59, 0x51, 0xab, 0x72, 0xad, 0x4a, - 0x00, 0x00, 0xfc, 0xbf, 0x9b, 0x0d, 0x06, 0xfb, 0x68, 0xd3, 0xb7, 0x60, 0xcb, 0x1a, 0x08, 0xff, - 0x16, 0x72, 0x67, 0xc8, 0x41, 0x2e, 0x1e, 0xab, 0xf0, 0xe9, 0xe3, 0xb6, 0x38, 0x56, 0xb1, 0x33, - 0x13, 0xe1, 0x96, 0xa4, 0x05, 0x37, 0x61, 0xce, 0x44, 0xad, 0xaf, 0x73, 0x74, 0x88, 0x5d, 0xb8, - 0x4a, 0xac, 0xd4, 0x7d, 0x87, 0x7f, 0xd1, 0xb3, 0x03, 0x5e, 0x97, 0x1f, 0xf5, 0xb5, 0xd1, 0xa0, - 0xf8, 0x7b, 0xd6, 0x47, 0xd7, 0x69, 0x57, 0xca, 0x58, 0x0c, 0x75, 0x48, 0x07, 0x64, 0xb5, 0x4f, - 0xaa, 0xcd, 0x0d, 0xc5, 0x66, 0xdb, 0xa6, 0xb0, 0x25, 0x76, 0x12, 0x4b, 0x00, 0x64, 0x7d, 0x28, - 0x5f, 0x43, 0x0d, 0xb6, 0xd7, 0x46, 0x59, 0xa1, 0xe2, 0xe5, 0x70, 0xf5, 0xe9, 0xd1, 0xb5, 0x8e, - 0x30, 0x77, 0x22, 0xba, 0xbe, 0xf5, 0x48, 0xd7, 0x29, 0xa4, 0xe6, 0xbd, 0x20, 0x18, 0xa7, 0xcc, - 0x60, 0xe4, 0xdc, 0x92, 0x9f, 0xdc, 0x21, 0x09, 0xbc, 0xa8, 0x1b, 0x14, 0x05, 0x8c, 0xe1, 0x2c, - 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0x84, 0x1f, 0x73, 0xf3, 0x17, 0xb6, 0x2a, 0x41, + 0x1d, 0x4e, 0x38, 0x95, 0xd7, 0x29, 0xb0, 0xbc, 0x81, 0x11, 0xff, 0x84, 0x0a, 0xc7, 0xa4, 0xe2, + 0xb2, 0xe3, 0x10, 0x2b, 0x82, 0xec, 0xb6, 0x74, 0x66, 0x93, 0x5e, 0xc7, 0xfc, 0x93, 0x30, 0x93, + 0x8a, 0xe6, 0xfe, 0xbb, 0x14, 0x26, 0x94, 0x9e, 0x47, 0x38, 0x23, 0xb3, 0x40, 0x7f, 0x7b, 0xd1, + 0x51, 0xfb, 0xfc, 0x5e, 0x7d, 0xb6, 0xe1, 0x1c, 0x90, 0x0e, 0x1f, 0xab, 0xb2, 0xf1, 0xba, 0x8f, + 0x1c, 0xd5, 0x07, 0x1c, 0xc8, 0xa4, 0x1f, 0x91, 0x7c, 0xbb, 0xf0, 0xe6, 0x2f, 0x35, 0x7a, 0x73, + 0x9d, 0x3d, 0x9d, 0x76, 0xf4, 0x45, 0x49, 0xb9, 0x9c, 0x62, 0xf4, 0x7f, 0x00, 0xc3, 0x54, 0xd2, + 0x68, 0x0e, 0x76, 0xff, 0xff, 0xfa, 0xf9, 0xff, 0xe3, 0xeb, 0x37, 0xff, 0xf3, 0x9f, 0xff, 0xfc, + 0xe7, 0x3f, 0xff, 0xf9, 0xcf, 0x7f, 0xfe, 0xf3, 0x9f, 0xff, 0xfc, 0xe7, 0x3f, 0xff, 0xf9, 0xcf, + 0x7f, 0xfe, 0xf3, 0x9f, 0xff, 0xfc, 0xe7, 0x3f, 0xff, 0xf9, 0xcf, 0x7f, 0xfe, 0xf3, 0x9f, 0xff, + 0xfc, 0xe7, 0x3f, 0xff, 0xf9, 0xcf, 0x7f, 0xfe, 0xf3, 0x9f, 0xff, 0xfc, 0xe7, 0x3f, 0xff, 0xf9, + 0xcf, 0x7f, 0xfe, 0xf3, 0x9f, 0xff, 0xfc, 0xe7, 0xff, 0xb5, 0xff, 0x07, 0x92, 0xb7, 0x96, 0x30, + 0x00, 0xa1, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1623,8 +1870,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 36864, // uncompressed data size (bytes) - 25193, // compressed data size (bytes) + 41216, // uncompressed data size (bytes) + 29140, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1646,8 +1893,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x4e, 0x01, 0x62, 0x6d, 0x08, 0x13, 0x4c, 0x24, 0x43, 0x69, - 0x20, 0x00, 0x00, 0x5e, 0xa1, 0x3e, 0xdc, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x2e, 0x01, 0x62, 0x5d, 0x08, 0x13, 0x4c, 0x14, 0x43, 0x69, + 0x20, 0x00, 0x00, 0xba, 0xbc, 0x76, 0xc1, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1675,1586 +1922,1833 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_header_dbg_storage_pvt; // VAR NAME: booter_ucode_data_ga10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 36864 -// COMPRESSED SIZE (bytes): 25188 +// DATA SIZE (bytes): 41216 +// COMPRESSED SIZE (bytes): 29139 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_image_prod_data[] = { - 0xed, 0xfd, 0x33, 0xb0, 0x30, 0xcc, 0x16, 0x30, 0xe8, 0x6e, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, - 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0x7b, 0xef, 0x77, 0xfe, 0xf8, 0xdc, 0xe0, - 0x4e, 0xd5, 0x04, 0x13, 0xcc, 0xf7, 0x64, 0x1d, 0x75, 0xd0, 0xa8, 0xd5, 0xab, 0x05, 0x00, 0xf0, - 0xff, 0x6d, 0x3a, 0xdd, 0xd7, 0xdd, 0x62, 0x2f, 0xdf, 0x7a, 0xf1, 0xf0, 0xd6, 0xb3, 0x5d, 0xfe, - 0x47, 0xe5, 0xb1, 0x30, 0x4b, 0x1d, 0x4a, 0x00, 0xf6, 0x48, 0x90, 0x7d, 0x1f, 0x17, 0xf6, 0xea, - 0x83, 0xd4, 0xdd, 0xcf, 0x06, 0xd5, 0x29, 0x84, 0x27, 0x6c, 0xc8, 0x8b, 0x86, 0xb6, 0x7f, 0x5a, - 0x84, 0xa3, 0x07, 0x4b, 0xf4, 0x90, 0xc1, 0x40, 0xc3, 0xce, 0x3a, 0x4a, 0xcb, 0xcb, 0x8d, 0xec, - 0x7d, 0x79, 0x87, 0x47, 0xa5, 0xb1, 0xc4, 0xd7, 0x5f, 0xcc, 0x39, 0xc5, 0x2b, 0x04, 0x17, 0xc5, - 0x2d, 0x2f, 0xed, 0xa7, 0x12, 0x0e, 0xc8, 0x47, 0x01, 0x84, 0x15, 0x30, 0xd8, 0xb9, 0xfd, 0x7b, - 0xcb, 0x01, 0xf9, 0x02, 0x74, 0x6d, 0x15, 0x34, 0xc9, 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0x31, 0xbd, - 0x00, 0x90, 0x00, 0x00, + 0xff, 0xfc, 0xe7, 0x3f, 0xff, 0xf9, 0xcf, 0xff, 0x5b, 0xff, 0x0f, 0x71, 0x57, 0x6c, 0x07, 0x00, + 0xa1, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3264,8 +3758,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 36864, // uncompressed data size (bytes) - 25188, // compressed data size (bytes) + 41216, // uncompressed data size (bytes) + 29139, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -3287,8 +3781,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_image_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x4e, 0x01, 0x62, 0x6d, 0x08, 0x13, 0x4c, 0x24, 0x43, 0x69, - 0x20, 0x00, 0x00, 0x5e, 0xa1, 0x3e, 0xdc, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x2e, 0x01, 0x62, 0x5d, 0x08, 0x13, 0x4c, 0x14, 0x43, 0x69, + 0x20, 0x00, 0x00, 0xba, 0xbc, 0x76, 0xc1, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3321,55 +3815,55 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_header_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_sig_dbg_data[] = { - 0x01, 0x00, 0x03, 0xff, 0xfc, 0x52, 0xe7, 0x80, 0x9b, 0x63, 0x0f, 0x4d, 0xf8, 0x07, 0x6a, 0x53, - 0x35, 0x16, 0xc8, 0x42, 0x3e, 0xd3, 0x9c, 0xca, 0xb5, 0xe2, 0x18, 0xc6, 0x1e, 0x1a, 0x66, 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0x0f, 0x90, 0xf2, 0xc0, 0xdd, 0x75, + 0x1a, 0xe2, 0xcb, 0x09, 0xb2, 0x8c, 0xa6, 0x05, 0xbe, 0xf9, 0x4d, 0x9a, 0x13, 0x75, 0xb9, 0x0e, + 0x50, 0xee, 0xde, 0x9e, 0xed, 0xa9, 0x97, 0x43, 0x3b, 0x40, 0x92, 0xc1, 0x0a, 0x75, 0x78, 0x9e, + 0x93, 0xb9, 0xf9, 0xf3, 0x8f, 0xde, 0x41, 0xf7, 0x73, 0x0f, 0xf3, 0xf8, 0xc9, 0x21, 0x19, 0xf2, + 0x25, 0x8f, 0xce, 0x89, 0x89, 0x05, 0x67, 0x45, 0x7f, 0x13, 0x4f, 0x2e, 0xab, 0xcf, 0xbc, 0x05, + 0xca, 0x6d, 0xdc, 0xa1, 0x63, 0x03, 0xb7, 0x06, 0x8a, 0xc4, 0x30, 0xa6, 0x4e, 0x6d, 0x4e, 0x11, + 0xe8, 0x48, 0x65, 0x92, 0xe4, 0x30, 0xed, 0xc7, 0xcf, 0x53, 0xee, 0xa0, 0xf2, 0x54, 0x20, 0xdc, + 0x0a, 0x3d, 0xfe, 0xc9, 0x5a, 0x82, 0x10, 0x08, 0x6f, 0x74, 0xda, 0x22, 0x0e, 0x02, 0x69, 0xa9, + 0x46, 0xc9, 0x0c, 0x86, 0x5f, 0x2a, 0x4b, 0x1f, 0x69, 0xc1, 0x34, 0x9d, 0xc3, 0x26, 0x77, 0xfa, + 0x79, 0xd8, 0xb7, 0xd8, 0xe8, 0x5b, 0x30, 0xa0, 0xd9, 0xd3, 0x47, 0xcc, 0x59, 0x91, 0x66, 0x90, + 0x78, 0xe3, 0x65, 0xfc, 0x48, 0x7b, 0xe7, 0x5a, 0x31, 0x50, 0x0e, 0xbf, 0xae, 0x35, 0xe7, 0x4b, + 0x01, 0xb8, 0x7a, 0x16, 0x8a, 0x23, 0xc6, 0x0b, 0x6e, 0x4b, 0xd5, 0x6c, 0x7f, 0x88, 0xd0, 0xcb, + 0x61, 0x32, 0x3a, 0x13, 0x21, 0x9c, 0xd0, 0x80, 0xe0, 0x18, 0xd4, 0x75, 0xb8, 0x8a, 0x5e, 0xf2, + 0x30, 0x9c, 0x01, 0x41, 0xe3, 0x45, 0x16, 0x67, 0xdb, 0x4b, 0x66, 0x53, 0x0e, 0x8e, 0x2a, 0xd8, + 0x0c, 0x37, 0xa6, 0x7a, 0xa6, 0x2a, 0xc4, 0x42, 0xbf, 0x00, 0x03, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3398,37 +3892,37 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_sig_dbg_storage_pvt; // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 768 -// COMPRESSED SIZE (bytes): 419 +// COMPRESSED SIZE (bytes): 420 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_sig_prod_data[] = { - 0xfb, 0xa7, 0x7c, 0xf3, 0xdb, 0xf4, 0xff, 0xcc, 0x0b, 0x6f, 0x7d, 0x9b, 0x6d, 0xcd, 0xb5, 0x6e, - 0x5b, 0xfe, 0xe5, 0xc0, 0xff, 0xd7, 0xea, 0xc2, 0xb7, 0x76, 0x88, 0x6d, 0xae, 0xcc, 0xda, 0xbe, - 0x77, 0xe9, 0xcb, 0xe5, 0xdf, 0x02, 0x05, 0xf7, 0xff, 0x9f, 0x11, 0x24, 0x19, 0x5a, 0xe5, 0xd8, - 0x37, 0x57, 0xc4, 0x53, 0xe9, 0xe2, 0x83, 0x44, 0xd1, 0x15, 0x8f, 0x0e, 0xeb, 0x4b, 0xbc, 0x28, - 0xde, 0xd1, 0x7f, 0x75, 0xab, 0x48, 0xae, 0x47, 0xc9, 0x2e, 0x01, 0x19, 0xaf, 0xd7, 0xf9, 0x47, - 0x14, 0x5e, 0x73, 0x9e, 0x59, 0xb6, 0xf9, 0xe2, 0xfc, 0x9f, 0x2e, 0x1a, 0x85, 0x6c, 0x6a, 0xdb, - 0xc4, 0xa7, 0x1b, 0xcf, 0xde, 0xfc, 0x6c, 0xde, 0x51, 0x2b, 0xfd, 0xe6, 0xc6, 0x92, 0xdf, 0xde, - 0x9e, 0xe9, 0x29, 0xba, 0x2c, 0x45, 0xd7, 0xbd, 0x5a, 0x8f, 0x5b, 0x3d, 0xf1, 0xb7, 0x34, 0x59, - 0x57, 0x2f, 0xd6, 0x74, 0xdf, 0x53, 0x52, 0x7c, 0xe1, 0x1c, 0xa6, 0xbb, 0x2c, 0xf9, 0xb9, 0x97, - 0x4f, 0xc4, 0xa6, 0x17, 0xcf, 0xca, 0xf9, 0x68, 0x9d, 0xeb, 0x37, 0xf1, 0xb0, 0xcf, 0xd5, 0x24, - 0xa9, 0xe2, 0x5b, 0xbc, 0x65, 0x57, 0x5f, 0xc6, 0x7d, 0xd8, 0x76, 0x6a, 0x33, 0xb7, 0x6a, 0xeb, - 0x8d, 0x14, 0xcf, 0xf4, 0x32, 0x5b, 0x81, 0xf0, 0xb8, 0xcc, 0xdc, 0xe3, 0x45, 0xd9, 0x4b, 0x6f, - 0xce, 0x9c, 0x7b, 0xcc, 0xb8, 0x68, 0x55, 0xd8, 0x1f, 0xab, 0xe3, 0x89, 0x7f, 0x83, 0xc4, 0xcd, - 0x77, 0xad, 0x72, 0x11, 0x91, 0xae, 0x0f, 0x3a, 0xac, 0x7d, 0x26, 0x61, 0xc5, 0xf7, 0xef, 0xda, - 0xfa, 0x57, 0xee, 0x99, 0xc4, 0x4e, 0x9a, 0xfa, 0x2c, 0x40, 0xad, 0xf1, 0xff, 0x64, 0x9b, 0xbd, - 0x85, 0xe6, 0xf6, 0xe6, 0x8b, 0x9e, 0x0b, 0xd4, 0xfc, 0x10, 0xe2, 0xd9, 0x5d, 0x10, 0x2b, 0x9e, - 0xb4, 0xe6, 0x94, 0xf3, 0x5c, 0x39, 0xbb, 0x6b, 0x3c, 0xc5, 0x91, 0xa5, 0xcf, 0xbf, 0xbc, 0x99, - 0x7f, 0x3a, 0xef, 0xfb, 0x71, 0x5f, 0x71, 0xe6, 0xf3, 0xd6, 0xac, 0x71, 0xbb, 0x5e, 0x5f, 0xfe, - 0xe8, 0x2f, 0xae, 0x24, 0xbb, 0xc8, 0x98, 0xbf, 0xb9, 0x40, 0x27, 0x70, 0xc5, 0x87, 0xfe, 0x63, - 0x1e, 0xa5, 0x0f, 0x3f, 0xd8, 0xec, 0xd6, 0x68, 0x4d, 0xce, 0x0d, 0x9f, 0x71, 0x85, 0x7b, 0xa2, - 0xc9, 0x05, 0x8d, 0xf6, 0xe4, 0x8b, 0x9d, 0x8d, 0xd1, 0x61, 0x42, 0x1f, 0xf5, 0xda, 0x83, 0x8f, - 0x36, 0x4c, 0xab, 0xab, 0x9b, 0xd5, 0xe0, 0xcc, 0xdb, 0x77, 0x3a, 0xe8, 0x6b, 0xb3, 0xa8, 0xe0, - 0x3b, 0x11, 0xcb, 0x3d, 0xb3, 0xd5, 0x1f, 0xf8, 0xcd, 0xf5, 0xf8, 0x1c, 0xc0, 0x76, 0xec, 0xca, - 0xcf, 0xbd, 0x6f, 0xaf, 0x64, 0xfd, 0x5c, 0xf9, 0xd7, 0xd1, 0x3c, 0xa3, 0xd4, 0x33, 0x39, 0x44, - 0x61, 0xfd, 0x15, 0xad, 0x1b, 0xca, 0x27, 0xeb, 0x82, 0x43, 0x2d, 0x2c, 0x9a, 0x32, 0x2e, 0xaf, - 0x76, 0xd0, 0x29, 0xd8, 0xce, 0x30, 0x0a, 0x06, 0x14, 0x00, 0x00, 0xaa, 0xd8, 0x3f, 0xfe, 0x00, - 0x03, 0x00, 0x00, + 0xf3, 0x6c, 0x32, 0x38, 0xa0, 0xb9, 0x37, 0xc4, 0x62, 0xcb, 0x75, 0x07, 0x81, 0xa4, 0x84, 0xda, + 0x4b, 0xeb, 0x96, 0x37, 0x08, 0x73, 0x89, 0xb4, 0x76, 0xfc, 0xda, 0xa0, 0xf5, 0x33, 0x75, 0xc1, + 0xba, 0x03, 0x33, 0x7a, 0xa5, 0x7f, 0x48, 0xf6, 0x1d, 0x29, 0x74, 0xbe, 0xfd, 0xa6, 0x88, 0xc9, + 0xfb, 0x8f, 0x7f, 0xc1, 0x29, 0x3b, 0xc1, 0x62, 0x0d, 0x4b, 0xfe, 0xe7, 0x27, 0x66, 0xf0, 0xe9, + 0x45, 0xe6, 0x76, 0x65, 0x31, 0xce, 0xbf, 0xb6, 0xef, 0x56, 0xf5, 0x32, 0xb5, 0x05, 0x93, 0x43, + 0x6f, 0x1e, 0x5f, 0x74, 0xd4, 0xcd, 0xc8, 0xd9, 0x20, 0x73, 0xe3, 0x8d, 0xbf, 0x96, 0xfb, 0xf7, + 0xba, 0x37, 0xa8, 0x3d, 0x99, 0xd0, 0x7e, 0x8c, 0xd7, 0x7c, 0x66, 0xa2, 0xf7, 0x7b, 0x5e, 0x79, + 0xbd, 0xc2, 0x89, 0x33, 0xbd, 0xe7, 0xae, 0x67, 0x98, 0x7b, 0xc2, 0xfe, 0xfd, 0x1e, 0xe7, 0x13, + 0x6a, 0xc5, 0x0b, 0x8c, 0xcf, 0x44, 0x2c, 0x92, 0x90, 0x15, 0xf8, 0xb0, 0x88, 0x31, 0xd2, 0xee, + 0x8a, 0xfe, 0x2d, 0x21, 0x76, 0xab, 0x62, 0xd7, 0x7b, 0x9e, 0x72, 0xb3, 0xe6, 0x37, 0xec, 0x31, + 0x2c, 0x98, 0xa7, 0xb8, 0x43, 0xe4, 0xfe, 0xe2, 0x25, 0x6f, 0xfa, 0xb5, 0x1b, 0x42, 0xe7, 0x1f, + 0xfc, 0xd0, 0x26, 0x22, 0x2e, 0xd7, 0xa1, 0xf3, 0x5e, 0x81, 0x33, 0x9e, 0xe9, 0x8b, 0x7f, 0xb2, + 0xa7, 0xbc, 0xea, 0xa5, 0x02, 0xb3, 0xdd, 0xba, 0x1b, 0x9c, 0xf6, 0xca, 0xe6, 0x70, 0x16, 0x86, + 0x49, 0xcf, 0x5d, 0x9f, 0x34, 0x29, 0x5d, 0x77, 0xfa, 0x91, 0xde, 0xfd, 0xce, 0xe7, 0xa6, 0xcc, + 0x5d, 0xff, 0x9d, 0x5b, 0xad, 0x77, 0xde, 0x9e, 0x55, 0x13, 0x78, 0x3b, 0x14, 0x97, 0x46, 0x26, + 0xb5, 0x75, 0xf8, 0xce, 0x09, 0x69, 0xfa, 0x3b, 0x75, 0x8d, 0xf6, 0xfe, 0xaa, 0xdf, 0xf3, 0x5f, + 0x35, 0xae, 0xfd, 0xb3, 0xa5, 0xf5, 0x68, 0xe4, 0xd6, 0x75, 0xad, 0xf9, 0x42, 0xa2, 0x6b, 0x62, + 0xe5, 0xdb, 0xe6, 0xce, 0x2a, 0x95, 0xba, 0xe0, 0xf2, 0xe7, 0xa4, 0x9d, 0xb7, 0x4f, 0x80, 0xaf, + 0xe9, 0xeb, 0x9a, 0xd7, 0xf7, 0xb9, 0x17, 0xda, 0x88, 0x2c, 0x5f, 0xb7, 0xb7, 0x44, 0xfb, 0x9b, + 0xfd, 0xe9, 0xc4, 0x89, 0xcc, 0xab, 0x8c, 0xfd, 0xe7, 0xfb, 0xcb, 0x36, 0xbf, 0x4a, 0x17, 0xab, + 0xb9, 0x73, 0x47, 0xc0, 0xd6, 0x27, 0xff, 0xf5, 0x1e, 0x1e, 0xfb, 0xc4, 0x09, 0xf1, 0x1c, 0x3a, + 0xcd, 0xfb, 0x0f, 0xcf, 0x98, 0x97, 0xd7, 0xbb, 0xf8, 0x5f, 0xfc, 0x5d, 0x6d, 0xff, 0x87, 0x8d, + 0xa1, 0xab, 0xe6, 0x5c, 0x70, 0xbb, 0xff, 0xf8, 0x27, 0xe3, 0xd4, 0x82, 0x69, 0x4c, 0xc7, 0xfe, + 0xcc, 0x71, 0x30, 0x4d, 0x59, 0xc8, 0xb4, 0xe4, 0xd8, 0x82, 0xfe, 0x3d, 0x5f, 0x3e, 0x1c, 0x73, + 0x79, 0x76, 0xf2, 0x75, 0xdd, 0xb4, 0xef, 0xab, 0x14, 0x1c, 0x0b, 0xea, 0x17, 0x2d, 0xda, 0x5d, + 0x26, 0xea, 0x53, 0xf7, 0xf5, 0x16, 0xc3, 0x28, 0x18, 0x50, 0x00, 0x00, 0xa5, 0x8b, 0x94, 0xf7, + 0x00, 0x03, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3439,7 +3933,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_sig_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 768, // uncompressed data size (bytes) - 419, // compressed data size (bytes) + 420, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA102_sig_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -3461,7 +3955,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_patch_loc_data[] = { - 0x10, 0x64, 0x00, 0x00, + 0x10, 0x74, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c index e8e8183ce..3de2c6a6b 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c @@ -34,1526 +34,1768 @@ // VAR NAME: booter_ucode_data_tu10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 35584 -// COMPRESSED SIZE (bytes): 24227 +// DATA SIZE (bytes): 39936 +// COMPRESSED SIZE (bytes): 28110 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_image_dbg_data[] = { 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0xfb, 0x84, 0xbc, + 0x83, 0x9b, 0xdd, 0x97, 0x5e, 0xa5, 0x01, 0xb5, 0xbe, 0x53, 0xc5, 0xc7, 0xd5, 0xb4, 0x14, 0x24, + 0xbe, 0xdc, 0x1f, 0xa4, 0x08, 0x84, 0xef, 0xa0, 0x56, 0xda, 0x10, 0x77, 0x6c, 0x81, 0xda, 0x89, + 0x3d, 0xf0, 0xd2, 0x93, 0x4d, 0xf3, 0xde, 0xd3, 0xcc, 0xb6, 0x07, 0x4a, 0x41, 0x58, 0x33, 0xc1, + 0x8a, 0xb2, 0x04, 0x48, 0x35, 0x95, 0x11, 0xd2, 0xf0, 0xfb, 0x30, 0x26, 0x87, 0x7a, 0x9c, 0x08, + 0x5c, 0x54, 0x5c, 0x5d, 0x21, 0xb2, 0x5a, 0xb5, 0x6e, 0x26, 0xb8, 0x8c, 0x8d, 0x90, 0xac, 0xbe, + 0x0d, 0xfb, 0x25, 0x82, 0x22, 0x9a, 0xe4, 0x2c, 0x11, 0x79, 0xab, 0x9b, 0x02, 0xaa, 0x14, 0x0b, + 0x1c, 0xfb, 0x3a, 0x56, 0xb9, 0xff, 0xff, 0xd7, 0x75, 0x80, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, + 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, + 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, + 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, + 0x9f, 0xff, 0x3f, 0xf1, 0x7f, 0x01, 0xd6, 0x2d, 0x6c, 0x6c, 0x00, 0x9c, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1563,8 +1805,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 35584, // uncompressed data size (bytes) - 24227, // compressed data size (bytes) + 39936, // uncompressed data size (bytes) + 28110, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_TU102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1586,8 +1828,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x8e, 0x07, 0x62, 0x1d, 0x08, 0x13, 0x4c, 0xc4, 0x41, 0x69, - 0x20, 0x00, 0x00, 0x5d, 0x39, 0xf2, 0xda, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xce, 0x07, 0x62, 0x5d, 0x08, 0x13, 0x4c, 0xe4, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x6a, 0x65, 0x76, 0x8b, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1615,1526 +1857,1769 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_header_dbg_storage_pvt; // VAR NAME: booter_ucode_data_tu10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 35584 -// COMPRESSED SIZE (bytes): 24227 +// DATA SIZE (bytes): 39936 +// COMPRESSED SIZE (bytes): 28113 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_image_prod_data[] = { - 0xed, 0xdc, 0x53, 0xaf, 0x28, 0xcd, 0xf7, 0x00, 0xe8, 0x6d, 0xdb, 0xb6, 0x6d, 0xe3, 0x6c, 0xdb, - 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xf3, 0x6c, 0xdb, 0x36, 0xe6, 0xf7, 0x9f, 0xbb, - 0x79, 0xbf, 0xc1, 0x24, 0xe7, 0xb9, 0xa9, 0xaa, 0x4e, 0xba, 0x57, 0x5d, 0x74, 0xaf, 0x64, 0x75, - 0xb2, 0x4a, 0x02, 0x00, 0x61, 0x36, 0x03, 0x20, 0x0e, 0x00, 0x14, 0xa0, 0xe7, 0x28, 0xff, 0xbd, - 0xe5, 0x07, 0x50, 0x02, 0x00, 0xf1, 0xff, 0x2e, 0x40, 0x80, 0x02, 0xfc, 0xbf, 0xcb, 0x08, 0x00, - 0x00, 0xc0, 0x9f, 0x64, 0x00, 0x5f, 0x7a, 0x00, 0x80, 0x37, 0xa0, 0x37, 0x80, 0x77, 0xa0, 0x18, - 0x00, 0x20, 0x80, 0xbe, 0x9d, 0xdd, 0xdf, 0xdf, 0x5f, 0xf8, 0x08, 0x00, 0x40, 0x80, 0xdf, 0x3c, - 0x90, 0xa6, 0x23, 0x00, 0xe6, 0xf4, 0x0d, 0xc0, 0xa6, 0x64, 0x00, 0x9a, 0xf4, 0x0d, 0xa0, 0xff, - 0x0d, 0xa4, 0xe9, 0x1b, 0xc0, 0xff, 0x1b, 0xf0, 0xfe, 0x77, 0x2f, 0x40, 0x7a, 0x1e, 0x70, 0xcb, - 0x2e, 0x70, 0x5f, 0x5e, 0xfe, 0x6e, 0x7a, 0x1e, 0x60, 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0xcf, 0x82, 0xb9, 0xf7, 0xe5, 0x63, 0x91, 0xa7, 0x45, 0x5d, 0xd7, 0xca, 0x4d, + 0xca, 0x88, 0x8d, 0x40, 0x21, 0xe6, 0x61, 0xf4, 0x48, 0xb5, 0x55, 0x6a, 0x98, 0x03, 0x2b, 0x78, + 0xc7, 0x4f, 0xcb, 0x1d, 0xb5, 0xe0, 0x20, 0x8c, 0x19, 0x0e, 0x0b, 0x28, 0x62, 0xc3, 0x15, 0x91, + 0x15, 0x39, 0x4d, 0x42, 0xdb, 0xe8, 0x7b, 0xcb, 0xfb, 0xbb, 0xa5, 0x6a, 0xfa, 0x09, 0x12, 0x55, + 0x4d, 0x05, 0x24, 0xed, 0xac, 0x5f, 0xe0, 0x60, 0xc0, 0x6f, 0xe9, 0x11, 0xaf, 0x61, 0x09, 0xb2, + 0x73, 0xb5, 0xf8, 0x45, 0x2f, 0x9f, 0x89, 0x44, 0xe4, 0x61, 0x1a, 0x27, 0xcc, 0x44, 0xfe, 0x05, + 0x00, 0x8c, 0xdf, 0x31, 0xb9, 0xf5, 0x17, 0x20, 0x43, 0x5b, 0x15, 0x35, 0xbf, 0xc5, 0xb9, 0xc2, + 0x11, 0x24, 0xb2, 0xfd, 0xea, 0xba, 0x82, 0x13, 0xdc, 0xff, 0xdb, 0x6d, 0x80, 0x7f, 0xfe, 0xf9, + 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, + 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, + 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, + 0xfe, 0xf9, 0xe7, 0x9f, 0xff, 0x8f, 0xf8, 0xbf, 0x00, 0x15, 0x32, 0x1b, 0xfa, 0x00, 0x9c, 0x00, + 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3144,8 +3629,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 35584, // uncompressed data size (bytes) - 24227, // compressed data size (bytes) + 39936, // uncompressed data size (bytes) + 28113, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_TU102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -3167,8 +3652,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_image_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x8e, 0x07, 0x62, 0x1d, 0x08, 0x13, 0x4c, 0xc4, 0x41, 0x69, - 0x20, 0x00, 0x00, 0x5d, 0x39, 0xf2, 0xda, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xce, 0x07, 0x62, 0x5d, 0x08, 0x13, 0x4c, 0xe4, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x6a, 0x65, 0x76, 0x8b, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3201,7 +3686,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_header_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_sig_dbg_data[] = { - 0xdc, 0x0b, 0xc1, 0x59, 0x91, 0xe1, 0x5d, 0xf2, 0x54, 0x06, 0x0d, 0xa3, 0x71, 0xb0, 0xc7, 0x52, + 0xbc, 0x1c, 0x6d, 0x20, 0xde, 0x55, 0x42, 0xd2, 0x0a, 0x80, 0x8b, 0xc0, 0xe1, 0xf3, 0x3c, 0x4b, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3234,7 +3719,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_sig_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_sig_prod_data[] = { - 0xcc, 0x26, 0x2d, 0xb0, 0xb0, 0x5c, 0x1f, 0xb1, 0x57, 0x5e, 0x05, 0x8a, 0xa1, 0x2d, 0x2b, 0x6c, + 0xd6, 0xa7, 0x37, 0x0d, 0x47, 0x15, 0x71, 0x56, 0x03, 0x40, 0x93, 0xbd, 0xf0, 0xfc, 0x3c, 0x93, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3267,7 +3752,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_patch_loc_data[] = { - 0x00, 0x61, 0x00, 0x00, + 0x00, 0x71, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c index 2752bd7d0..74baa0e09 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c @@ -34,1520 +34,1770 @@ // VAR NAME: booter_ucode_data_tu11x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 35584 -// COMPRESSED SIZE (bytes): 24132 +// DATA SIZE (bytes): 39936 +// COMPRESSED SIZE (bytes): 28132 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_image_dbg_data[] = { - 0xed, 0xdc, 0x53, 0x90, 0xe8, 0xce, 0x1b, 0x30, 0xe8, 0xb1, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xd6, - 0x19, 0xdb, 0xb6, 0x6d, 0xdb, 0x9e, 0x39, 0x63, 0xdb, 0xb6, 0x6d, 0xdb, 0xdc, 0xff, 0xb7, 0x77, - 0xfb, 0xbb, 0xd9, 0xda, 0xcb, 0xad, 0x3a, 0xcf, 0x4d, 0xa7, 0x53, 0x95, 0xbc, 0xa9, 0xa4, 0xd2, - 0xd5, 0x6f, 0xd2, 0xdd, 0x92, 0x00, 0x08, 0x33, 0x19, 0x00, 0x71, 0x00, 0xa0, 0x00, 0xdd, 0x47, - 0xf9, 0xef, 0xcd, 0x3f, 0x80, 0x92, 0x00, 0x88, 0xff, 0x67, 0x07, 0x04, 0x28, 0xc0, 0xff, 0x5d, - 0x8d, 0x00, 0x00, 0x00, 0xfc, 0x49, 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0xc3, + 0xa7, 0xad, 0x49, 0x12, 0xb8, 0x92, 0x44, 0x48, 0x21, 0x5b, 0xa5, 0x8b, 0xf0, 0x2b, 0x92, 0x70, + 0xd8, 0x2a, 0x18, 0x1b, 0x7f, 0x09, 0xe5, 0xf5, 0xb1, 0x8e, 0x0d, 0xba, 0x0b, 0x72, 0x95, 0x58, + 0xc7, 0x9f, 0xc5, 0xfd, 0xb4, 0xde, 0x3f, 0x87, 0x9f, 0x6a, 0x34, 0x5d, 0x13, 0x5f, 0x77, 0x75, + 0x0c, 0x8a, 0xb3, 0xd1, 0x76, 0x91, 0xe9, 0x91, 0x9b, 0x03, 0xd9, 0x52, 0xcb, 0x14, 0x04, 0x96, + 0xe7, 0x0b, 0xf5, 0x30, 0xe1, 0x2c, 0xdd, 0xe2, 0xf2, 0x06, 0x38, 0x51, 0x57, 0x86, 0x75, 0x19, + 0x35, 0x59, 0x9e, 0x5a, 0x63, 0x19, 0x5f, 0xc5, 0x95, 0x02, 0x7f, 0x01, 0x48, 0xce, 0x12, 0x91, + 0xb7, 0xba, 0x29, 0xa0, 0x4a, 0xb1, 0xc0, 0xb1, 0xaf, 0x63, 0x95, 0xfa, 0xff, 0xbf, 0x2e, 0x03, + 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, + 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, + 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, + 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xff, 0xc4, 0xff, 0x05, 0x5e, 0xd6, 0x73, 0x23, + 0x00, 0x9c, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1557,8 +1807,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 35584, // uncompressed data size (bytes) - 24132, // compressed data size (bytes) + 39936, // uncompressed data size (bytes) + 28132, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_TU116_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1580,8 +1830,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x8e, 0x07, 0x62, 0x1d, 0x08, 0x13, 0x4c, 0xc4, 0x41, 0x69, - 0x20, 0x00, 0x00, 0x5d, 0x39, 0xf2, 0xda, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xce, 0x07, 0x62, 0x5d, 0x08, 0x13, 0x4c, 0xe4, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x6a, 0x65, 0x76, 0x8b, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1609,1520 +1859,1770 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_header_dbg_storage_pvt; // VAR NAME: booter_ucode_data_tu11x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 35584 -// COMPRESSED SIZE (bytes): 24135 +// DATA SIZE (bytes): 39936 +// COMPRESSED SIZE (bytes): 28132 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_image_prod_data[] = { - 0xed, 0xfc, 0x53, 0x8c, 0x28, 0xcf, 0x1b, 0x38, 0x78, 0x8f, 0x6d, 0xdb, 0xf6, 0xcc, 0x19, 0xdb, - 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x71, 0xc6, 0xb6, 0x6d, 0xdb, 0xf6, 0xfe, 0xfe, 0xef, - 0xdd, 0xfb, 0xdd, 0x8b, 0xcd, 0x5e, 0x6e, 0x72, 0x3e, 0x37, 0xd5, 0xd5, 0x49, 0xf7, 0xd3, 0x49, - 0xa7, 0x2a, 0x55, 0xdd, 0xf5, 0x94, 0x04, 0x00, 0xc2, 0x4c, 0x06, 0x40, 0x1c, 0x00, 0x28, 0x40, - 0xf7, 0x51, 0xfe, 0x7b, 0xcb, 0x0f, 0xa0, 0x04, 0x00, 0xe2, 0xff, 0x39, 0x01, 0x01, 0x0a, 0xf0, - 0xff, 0xab, 0x46, 0x00, 0x00, 0x00, 0xfe, 0x24, 0x03, 0xf8, 0xd2, 0x03, 0x00, 0xbc, 0x01, 0xbd, - 0x01, 0xbc, 0x03, 0xc5, 0x00, 0x00, 0x01, 0xf4, 0xee, 0xec, 0xfe, 0xfe, 0xfe, 0xc2, 0x47, 0x00, - 0x00, 0x02, 0xfc, 0xe6, 0x81, 0x34, 0x1d, 0x01, 0xfc, 0x49, 0x5f, 0x07, 0x6c, 0x4a, 0x06, 0xa0, - 0x49, 0x5f, 0x07, 0xfa, 0x5f, 0x41, 0x9a, 0xbe, 0x0e, 0xfc, 0xbf, 0x02, 0xef, 0x7f, 0xd7, 0x02, - 0xa4, 0xe7, 0x01, 0xb7, 0xec, 0x02, 0xf7, 0xe6, 0xe5, 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0xe0, + 0x0d, 0x2c, 0x8e, 0x9e, 0x8c, 0x77, 0xd7, 0x43, 0xba, 0x3a, 0xe4, 0xe3, 0xd1, 0xa6, 0x6f, 0xbb, + 0xf5, 0x1a, 0x83, 0x20, 0x75, 0x88, 0x49, 0x0c, 0xb1, 0xdb, 0x9f, 0x8a, 0x74, 0x76, 0x23, 0x18, + 0xab, 0xb3, 0x69, 0x7c, 0x8a, 0x28, 0xf8, 0xff, 0x75, 0x1b, 0xe0, 0x3f, 0xff, 0xf9, 0xcf, 0x7f, + 0xfe, 0xf3, 0x9f, 0xff, 0xfc, 0xe7, 0x3f, 0xff, 0xf9, 0xcf, 0x7f, 0xfe, 0xf3, 0x9f, 0xff, 0xfc, + 0xe7, 0x3f, 0xff, 0xf9, 0xcf, 0x7f, 0xfe, 0xf3, 0x9f, 0xff, 0xfc, 0xe7, 0x3f, 0xff, 0xf9, 0xcf, + 0x7f, 0xfe, 0xf3, 0x9f, 0xff, 0xfc, 0xe7, 0x3f, 0xff, 0xf9, 0xcf, 0x7f, 0xfe, 0xf3, 0x9f, 0xff, + 0xfc, 0xe7, 0x3f, 0xff, 0xf9, 0xcf, 0x7f, 0xfe, 0xff, 0xc4, 0xff, 0x0b, 0x42, 0xc8, 0x0d, 0xcf, + 0x00, 0x9c, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3132,8 +3632,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 35584, // uncompressed data size (bytes) - 24135, // compressed data size (bytes) + 39936, // uncompressed data size (bytes) + 28132, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_TU116_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -3155,8 +3655,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_image_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x8e, 0x07, 0x62, 0x1d, 0x08, 0x13, 0x4c, 0xc4, 0x41, 0x69, - 0x20, 0x00, 0x00, 0x5d, 0x39, 0xf2, 0xda, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xce, 0x07, 0x62, 0x5d, 0x08, 0x13, 0x4c, 0xe4, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x6a, 0x65, 0x76, 0x8b, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3189,7 +3689,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_header_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_sig_dbg_data[] = { - 0xa0, 0x36, 0x85, 0x48, 0xdb, 0x21, 0x06, 0x83, 0x93, 0x8c, 0xb1, 0xa2, 0xe3, 0xef, 0x78, 0x7e, + 0x93, 0x0a, 0x99, 0x09, 0x4d, 0xaa, 0xeb, 0xac, 0x32, 0x20, 0x4c, 0xba, 0x57, 0xbf, 0xe3, 0xf2, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3222,7 +3722,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_sig_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_sig_prod_data[] = { - 0xec, 0x58, 0xd9, 0x1f, 0x66, 0x9d, 0xcc, 0xa0, 0x7d, 0xa7, 0xec, 0xee, 0x64, 0xab, 0xcd, 0xd9, + 0x98, 0xd3, 0xbe, 0x5a, 0x6f, 0x0e, 0xe7, 0x74, 0x73, 0x08, 0xa6, 0xf9, 0x16, 0x51, 0x4d, 0x26, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3255,7 +3755,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_patch_loc_data[] = { - 0x00, 0x61, 0x00, 0x00, + 0x00, 0x71, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c index 2dac85e84..6b9ff60b7 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c @@ -34,450 +34,911 @@ // VAR NAME: booter_ucode_data_ad10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 8960 -// COMPRESSED SIZE (bytes): 7012 +// DATA SIZE (bytes): 20992 +// COMPRESSED SIZE (bytes): 14399 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_image_dbg_data[] = { - 0xed, 0x99, 0x65, 0x50, 0x5d, 0xdd, 0x96, 0xae, 0x91, 0x04, 0x77, 0x77, 0x87, 0x8d, 0xbb, 0xbb, - 0xbb, 0x07, 0x77, 0xdf, 0xc1, 0x09, 0x6e, 0xc1, 0xdd, 0xdd, 0x82, 0xbb, 0xbb, 0x06, 0x0b, 0x12, - 0x3c, 0xb8, 0x67, 0xe3, 0xbe, 0x71, 0x87, 0x60, 0xcd, 0xe9, 0xfe, 0x6e, 0xdd, 0xae, 0xaf, 0xee, - 0xfd, 0xd3, 0xdd, 0x55, 0xe7, 0x47, 0x9f, 0xb7, 0xea, 0x59, 0x63, 0x8c, 0xb9, 0x46, 0xd5, 0xbb, - 0xe6, 0x9c, 0x7f, 0xd6, 0x5c, 0x0b, 0x02, 0xe2, 0x7f, 0xb7, 0x04, 0xc8, 0x73, 0x46, 0x6b, 0xbf, - 0xba, 0xc4, 0x84, 0x3a, 0x44, 0x68, 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defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 8960, // uncompressed data size (bytes) - 7012, // compressed data size (bytes) + 20992, // uncompressed data size (bytes) + 14399, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_AD102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -510,8 +971,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x01, 0x62, 0x76, 0x08, 0x13, 0x4c, 0x48, 0x43, 0x69, - 0x20, 0x00, 0x00, 0xa5, 0x7c, 0x63, 0x18, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xb6, 0x04, 0x62, 0x49, 0x08, 0x13, 0x4c, 0x58, 0x40, 0x69, + 0x20, 0x00, 0x00, 0xcd, 0x04, 0x38, 0x58, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -539,450 +1000,912 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_header_dbg_storage_pvt // VAR NAME: booter_ucode_data_ad10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 8960 -// COMPRESSED SIZE (bytes): 7010 +// DATA SIZE (bytes): 20992 +// COMPRESSED SIZE (bytes): 14401 // static BINDATA_CONST NvU8 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0xea, 0x7f, 0x88, + 0x03, 0x02, 0xf1, 0xff, 0xdc, 0x3e, 0xed, 0x7f, 0xb0, 0xd3, 0xff, 0x2a, 0xe3, 0xaf, 0xc4, 0xff, + 0x4a, 0xe2, 0xaf, 0x24, 0xff, 0x4a, 0xea, 0x3f, 0xd7, 0x64, 0xfe, 0x53, 0xca, 0xfe, 0x23, 0x4e, + 0xfd, 0x7f, 0xe2, 0xfc, 0xf7, 0xb1, 0xfb, 0xaf, 0x77, 0x00, 0xf0, 0x77, 0x88, 0x01, 0x94, 0x44, + 0x19, 0xfe, 0x27, 0xfa, 0xf0, 0xff, 0x25, 0xff, 0x0d, 0xed, 0x84, 0x93, 0xf3, 0x00, 0x52, 0x00, + 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -992,8 +1915,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_image_prod_storage_pvt #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 8960, // uncompressed data size (bytes) - 7010, // compressed data size (bytes) + 20992, // uncompressed data size (bytes) + 14401, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_AD102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1015,8 +1938,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_image_prod_storage_pvt // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x01, 0x62, 0x76, 0x08, 0x13, 0x4c, 0x48, 0x43, 0x69, - 0x20, 0x00, 0x00, 0xa5, 0x7c, 0x63, 0x18, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xb6, 0x04, 0x62, 0x49, 0x08, 0x13, 0x4c, 0x58, 0x40, 0x69, + 0x20, 0x00, 0x00, 0xcd, 0x04, 0x38, 0x58, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1049,55 +1972,55 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_header_prod_storage_pv // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_sig_dbg_data[] = { - 0x01, 0x00, 0x03, 0xff, 0xfc, 0x05, 0xc8, 0x8d, 0x0a, 0x2d, 0x7a, 0xb2, 0x85, 0x54, 0x06, 0xb2, - 0x6c, 0x83, 0x69, 0x50, 0x0e, 0xd3, 0xf1, 0x2a, 0xc6, 0x07, 0xfc, 0xae, 0x72, 0x6e, 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0x11, 0xa3, 0xdc, 0xac, 0xd4, 0x15, 0x68, 0x06, 0x1f, + 0x34, 0x9f, 0x66, 0xb2, 0xc2, 0xc9, 0x6c, 0x20, 0xb8, 0x1d, 0xaf, 0xfb, 0xe9, 0xae, 0x18, 0x18, + 0x21, 0xd1, 0x6d, 0x66, 0xf1, 0x18, 0x6f, 0x6d, 0xef, 0xfa, 0x97, 0x89, 0x04, 0x45, 0x01, 0x3f, + 0x65, 0xb0, 0xeb, 0x13, 0x56, 0x52, 0x82, 0x48, 0x20, 0xa3, 0xa0, 0x3a, 0xb3, 0xc3, 0x9b, 0xa4, + 0x10, 0xd7, 0xc9, 0xad, 0x60, 0x6c, 0xba, 0x17, 0x8b, 0xaf, 0xdc, 0x67, 0xb1, 0xc2, 0xc1, 0x89, + 0x96, 0x4c, 0x7b, 0x83, 0x70, 0x28, 0x48, 0xc1, 0xa8, 0x75, 0x92, 0xd1, 0x7a, 0x5a, 0x21, 0x89, + 0x61, 0xb6, 0x36, 0x9f, 0x06, 0xa0, 0x45, 0xe1, 0xed, 0x11, 0x54, 0x47, 0x3d, 0x46, 0x7e, 0x27, + 0x07, 0x22, 0xaf, 0x8f, 0x6f, 0x42, 0x7c, 0xa6, 0x9e, 0x99, 0x51, 0xdb, 0x71, 0x51, 0x5e, 0x3d, + 0x99, 0x14, 0xa3, 0x4f, 0xd9, 0x95, 0xc0, 0x53, 0x3d, 0x54, 0xe6, 0x9f, 0x53, 0x91, 0x0c, 0x09, + 0x25, 0x02, 0x1f, 0xb1, 0x67, 0x16, 0x73, 0xd5, 0x6d, 0x27, 0x25, 0x13, 0xf4, 0x90, 0xd0, 0x69, + 0x0a, 0x6a, 0xac, 0x30, 0x87, 0xc9, 0xa9, 0x0c, 0x0f, 0x18, 0xce, 0x0c, 0x82, 0xe7, 0x2a, 0xb6, + 0x31, 0x26, 0x89, 0xae, 0x66, 0x5a, 0x00, 0xff, 0x4e, 0xc1, 0x0a, 0xd5, 0x0e, 0x2d, 0xa4, 0x0b, + 0xc7, 0x9f, 0x05, 0x44, 0x1a, 0x38, 0x16, 0xb3, 0x38, 0x00, 0x03, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1211,7 +2134,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_patch_loc_data[] = { - 0x10, 0x1c, 0x00, 0x00, + 0x10, 0x39, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c index c7b34fba7..c976f8696 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c @@ -34,427 +34,884 @@ // VAR NAME: booter_ucode_data_ga100 // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 8704 -// COMPRESSED SIZE (bytes): 6655 +// DATA SIZE (bytes): 20480 +// COMPRESSED SIZE (bytes): 13953 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_image_dbg_data[] = { - 0xed, 0x99, 0x45, 0x50, 0x1c, 0x6a, 0xb3, 0x86, 0x87, 0x21, 0x58, 0x20, 0x38, 0x04, 0x87, 0xe0, - 0x12, 0xdc, 0xdd, 0xdd, 0x82, 0x43, 0x70, 0x77, 0x27, 0x38, 0x03, 0x83, 0xbb, 0x0e, 0x30, 0xb8, - 0xbb, 0x07, 0x0b, 0x41, 0x43, 0x70, 0x38, 0x40, 0x82, 0xeb, 0xe0, 0x04, 0x87, 0x00, 0x81, 0xc1, - 0xe6, 0xe6, 0x5f, 0xdc, 0xcd, 0xbf, 0xba, 0xeb, 0x5b, 0xe7, 0xd9, 0xbc, 0x6f, 0xf7, 0xa2, 0xab, - 0x7b, 0xd1, 0xd5, 0xf5, 0xd5, 0x17, 0x07, 0x00, 0x20, 0xbd, 0x40, 0x00, 0x20, 0x1c, 0x00, 0xe0, - 0x1e, 0x78, 0x0f, 0x80, 0x03, 0x93, 0x00, 0x40, 0x40, 0xff, 0x26, 0x0c, 0x81, 0x40, 0xe0, 0xc4, - 0x01, 0x90, 0x00, 0x88, 0xa2, 0x57, 0xad, 0x7b, 0x00, 0x5e, 0xe8, 0x0a, 0x52, 0x2b, 0x04, 0xf0, - 0x1e, 0xba, 0x02, 0xfc, 0x2b, 0x0c, 0xd0, 0x15, 0xe4, 0xbf, 0x42, 0x15, 0x07, 0x00, 0x00, 0xa0, - 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0x14, 0x77, 0xb8, 0x71, 0xc8, 0x32, 0x8a, 0x32, + 0x20, 0x3a, 0x9d, 0x03, 0x54, 0xb8, 0x8b, 0xdd, 0xeb, 0x01, 0x7f, 0x75, 0xe8, 0x26, 0xf8, 0xf9, + 0x8e, 0x05, 0x5a, 0xcf, 0xec, 0x1c, 0x65, 0xda, 0x87, 0x9c, 0xf4, 0xd8, 0xeb, 0x90, 0xf6, 0x99, + 0x03, 0xbf, 0x27, 0xf4, 0x05, 0x7b, 0x6f, 0x94, 0xa4, 0xf3, 0x09, 0x46, 0xdf, 0x3b, 0x70, 0x4c, + 0x05, 0xb5, 0xc6, 0x40, 0x57, 0xc0, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, + 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, + 0xff, 0xfc, 0xf3, 0xcf, 0xff, 0xcb, 0xfc, 0x7f, 0x00, 0x56, 0xc1, 0xe5, 0x39, 0x00, 0x50, 0x00, + 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -464,8 +921,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 8704, // uncompressed data size (bytes) - 6655, // compressed data size (bytes) + 20480, // uncompressed data size (bytes) + 13953, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA100_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -487,8 +944,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x02, 0x62, 0x0e, 0x08, 0x13, 0x4c, 0x48, 0x42, 0x69, - 0x20, 0x00, 0x00, 0x2b, 0x43, 0x56, 0x8a, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x36, 0x07, 0x62, 0x49, 0x08, 0x13, 0x4c, 0x98, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x86, 0xa4, 0x95, 0x74, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -516,427 +973,883 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_header_dbg_storage_pvt // VAR NAME: booter_ucode_data_ga100 // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 8704 -// COMPRESSED SIZE (bytes): 6649 +// DATA SIZE (bytes): 20480 +// COMPRESSED SIZE (bytes): 13951 // static BINDATA_CONST NvU8 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0xf1, 0xd2, 0xfe, 0x8b, 0xc0, 0x44, 0xa3, 0x9d, 0x24, + 0xd3, 0xa0, 0xeb, 0xe4, 0x42, 0xe6, 0x0b, 0xc7, 0xf6, 0x66, 0xaa, 0x7b, 0x0b, 0x30, 0xcd, 0x8b, + 0xde, 0xa8, 0x7c, 0x80, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, + 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, + 0xe7, 0x9f, 0xff, 0x97, 0xf9, 0xff, 0x00, 0x3a, 0xe2, 0x77, 0x76, 0x00, 0x50, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -946,8 +1859,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_image_prod_storage_pvt #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 8704, // uncompressed data size (bytes) - 6649, // compressed data size (bytes) + 20480, // uncompressed data size (bytes) + 13951, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA100_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -969,8 +1882,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_image_prod_storage_pvt // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x02, 0x62, 0x0e, 0x08, 0x13, 0x4c, 0x48, 0x42, 0x69, - 0x20, 0x00, 0x00, 0x2b, 0x43, 0x56, 0x8a, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x36, 0x07, 0x62, 0x49, 0x08, 0x13, 0x4c, 0x98, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x86, 0xa4, 0x95, 0x74, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1003,31 +1916,31 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_header_prod_storage_pv // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_sig_dbg_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x27, 0x14, 0x82, 0xed, 0x50, 0xb4, 0xad, 0x04, 0xb4, 0x65, 0xe6, - 0xa2, 0x91, 0x3f, 0x4a, 0xc1, 0x55, 0x7a, 0xb0, 0x08, 0x78, 0x5f, 0x32, 0xe9, 0x8f, 0x54, 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0xc3, 0x66, 0x1d, 0xfc, 0xec, 0x1c, 0xf7, 0x2f, 0x3b, 0xbc, 0xda, - 0xc2, 0x63, 0x68, 0x0d, 0xfc, 0xe1, 0x92, 0xbb, 0x56, 0xae, 0x8c, 0x14, 0xf9, 0x98, 0x30, 0x4f, - 0x03, 0x56, 0x61, 0xd5, 0x8b, 0x30, 0x5c, 0xb1, 0xb3, 0x80, 0x01, 0x00, 0x00, + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x3d, 0x8f, 0x43, 0x51, 0x1e, 0x76, 0xd8, 0x14, 0xef, 0x47, 0xfe, + 0x79, 0xa7, 0x4f, 0x2c, 0x63, 0x08, 0x1f, 0x93, 0x61, 0x90, 0x61, 0x8d, 0x14, 0x60, 0x06, 0x09, + 0xb0, 0x4c, 0x9b, 0x39, 0x35, 0xc5, 0xb8, 0xc4, 0x8b, 0x60, 0x4d, 0x50, 0xd0, 0x26, 0xf1, 0x91, + 0x11, 0xb0, 0x67, 0x95, 0x81, 0x01, 0x5c, 0x6c, 0xae, 0x28, 0x4c, 0x53, 0x58, 0x5f, 0x56, 0x42, + 0xc9, 0xa8, 0x74, 0x34, 0x75, 0x9e, 0x60, 0x2f, 0x89, 0xc0, 0x13, 0xaa, 0xb7, 0x1f, 0xad, 0x28, + 0x5b, 0xcf, 0xfd, 0x1d, 0x3f, 0x4a, 0xc8, 0xf7, 0x20, 0x7a, 0x0b, 0xae, 0x06, 0xef, 0xef, 0xb3, + 0xfb, 0x8d, 0xa0, 0xc4, 0xc2, 0x8b, 0x07, 0x98, 0x7d, 0x60, 0x1b, 0x48, 0xeb, 0x68, 0x94, 0xec, + 0x2e, 0x6a, 0x8e, 0x09, 0x70, 0x62, 0xe3, 0xd7, 0x73, 0x0b, 0x60, 0x19, 0x2c, 0x28, 0x03, 0xe4, + 0xd5, 0xe1, 0x0e, 0x5e, 0x1c, 0xcf, 0x1b, 0x97, 0xa9, 0xcd, 0x74, 0xc6, 0x1e, 0xec, 0xda, 0x90, + 0xa0, 0xb4, 0x46, 0xc0, 0x1e, 0x16, 0xa1, 0x51, 0x24, 0xeb, 0xb2, 0x09, 0x51, 0x7c, 0x75, 0x5a, + 0xa7, 0x4a, 0x00, 0x44, 0x3f, 0xf0, 0x27, 0x7b, 0xa3, 0xd1, 0xa0, 0x80, 0x34, 0xa2, 0xc2, 0x51, + 0xb3, 0xd0, 0x5f, 0x90, 0x87, 0x9d, 0xd3, 0x07, 0x12, 0x92, 0xc1, 0x38, 0x03, 0x0c, 0xcd, 0x90, + 0xf4, 0xe9, 0xe4, 0x8f, 0xa6, 0x51, 0xf6, 0x79, 0x5b, 0xb3, 0xf7, 0x05, 0x29, 0x8d, 0x65, 0xab, + 0x76, 0xe8, 0x8e, 0x5f, 0x7e, 0x1b, 0x72, 0x4b, 0x3b, 0x11, 0x66, 0x1f, 0x9b, 0x9d, 0xa0, 0x9a, + 0x41, 0x8d, 0xc8, 0x64, 0xdc, 0xae, 0x40, 0x91, 0x6a, 0x00, 0x48, 0x69, 0xa1, 0x00, 0xde, 0x56, + 0x77, 0x18, 0xeb, 0xc9, 0xbf, 0x39, 0x95, 0xaa, 0x16, 0x42, 0x15, 0x51, 0x94, 0xc9, 0xd1, 0x6f, + 0x75, 0x8a, 0xb3, 0xff, 0x73, 0xd5, 0xd5, 0x08, 0xe5, 0x59, 0xf1, 0x0a, 0x46, 0xf7, 0x39, 0x4d, + 0x78, 0xe2, 0x55, 0x6e, 0x69, 0x54, 0x7b, 0x21, 0x85, 0xcd, 0x99, 0x2a, 0x59, 0x3d, 0xf7, 0x43, + 0xec, 0x90, 0x4d, 0x82, 0xcb, 0xd0, 0xc4, 0xff, 0x4c, 0xfe, 0x72, 0x1b, 0x15, 0xfe, 0x60, 0x4a, + 0x74, 0x78, 0x18, 0x42, 0xcc, 0x49, 0x28, 0x63, 0x3a, 0xc6, 0x5a, 0x53, 0xd4, 0x3d, 0x5b, 0x2b, + 0xba, 0x4b, 0x52, 0xad, 0xfc, 0xc8, 0x09, 0xe1, 0x6c, 0xd4, 0xac, 0x72, 0x79, 0x62, 0xf8, 0x8f, + 0x05, 0x18, 0x2e, 0x86, 0x00, 0xf3, 0x0f, 0xa6, 0x75, 0xb8, 0x3c, 0x3a, 0x0a, 0x22, 0x90, 0xe8, + 0xc5, 0x93, 0x0b, 0x27, 0xa6, 0x45, 0xe3, 0xf7, 0x75, 0x8b, 0x4f, 0x28, 0x6f, 0xc4, 0xd6, 0x7f, + 0xd7, 0x5b, 0x26, 0xd1, 0xc8, 0x05, 0xd9, 0xbf, 0x18, 0x10, 0x52, 0x28, 0x88, 0x88, 0x77, 0x09, + 0x1d, 0x6b, 0x49, 0xd8, 0x74, 0x8f, 0x9a, 0xff, 0x6a, 0x80, 0x01, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1060,31 +1973,31 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_sig_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_sig_prod_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x99, 0x28, 0x07, 0xb5, 0xce, 0x8e, 0x09, 0x5c, 0x30, 0x2a, 0x9c, - 0xdc, 0x66, 0x84, 0xa4, 0x0d, 0x33, 0x44, 0x87, 0xa2, 0xd7, 0x17, 0xb5, 0x14, 0x15, 0x12, 0x82, - 0x3e, 0xd3, 0x74, 0xc9, 0xac, 0xb1, 0x92, 0xcc, 0x85, 0x88, 0xcb, 0x87, 0x9f, 0xdc, 0x1e, 0x72, - 0xf8, 0x0a, 0x44, 0xec, 0x86, 0x0d, 0x4b, 0xbf, 0x04, 0x19, 0x73, 0x45, 0x5e, 0x1b, 0x90, 0x90, - 0xb8, 0xad, 0x94, 0x67, 0x14, 0x60, 0xee, 0xc2, 0x86, 0x37, 0xd1, 0x02, 0x54, 0xbe, 0x7c, 0x01, - 0x7f, 0xae, 0x40, 0x03, 0x88, 0x0e, 0x45, 0x84, 0x5e, 0x52, 0x33, 0x2b, 0x2c, 0x5b, 0x00, 0x85, - 0xfe, 0x78, 0xb8, 0xf2, 0x5d, 0x43, 0xa1, 0xa0, 0xbb, 0xc0, 0x6b, 0xa7, 0x83, 0xa8, 0xbc, 0xf9, - 0xa3, 0x83, 0xd4, 0x0f, 0x9f, 0xc9, 0x88, 0x4f, 0x4c, 0x6a, 0xfa, 0x90, 0x39, 0x86, 0xc5, 0xe4, - 0x79, 0x20, 0xf3, 0x1e, 0x76, 0x6d, 0x59, 0x1d, 0x27, 0x1b, 0x47, 0x55, 0x3c, 0x49, 0xe6, 0xdf, - 0xa8, 0x63, 0xb4, 0xbd, 0x8c, 0x66, 0xc8, 0x9c, 0x43, 0x9d, 0x49, 0xc5, 0x20, 0xdc, 0x71, 0x0b, - 0xf6, 0xac, 0x49, 0x9a, 0xe0, 0x4f, 0xa9, 0x3a, 0x00, 0x0c, 0x01, 0x5e, 0xfd, 0xbc, 0xdc, 0xbc, - 0x3f, 0x4b, 0xd6, 0xf6, 0x59, 0x48, 0x57, 0xdd, 0xbe, 0xa3, 0xbf, 0x6e, 0x9c, 0x52, 0x3c, 0xa8, - 0xde, 0x49, 0x56, 0x9a, 0x69, 0x01, 0x86, 0xf5, 0x48, 0x2f, 0xe8, 0xe6, 0xf2, 0x16, 0xf0, 0xee, - 0xe3, 0xf9, 0xce, 0x42, 0x13, 0x7d, 0x8e, 0xa5, 0xb2, 0xb4, 0x04, 0xc2, 0x82, 0xe2, 0x1e, 0xaf, - 0xc9, 0xa0, 0x2c, 0x68, 0x01, 0xde, 0xbf, 0x4f, 0x56, 0x55, 0x3d, 0x8f, 0xf4, 0x6b, 0x77, 0x32, - 0x0c, 0xaf, 0x9b, 0x5c, 0x5e, 0x8f, 0x52, 0x6a, 0xcb, 0x91, 0xa2, 0xa3, 0x63, 0x36, 0x9f, 0xea, - 0x35, 0x75, 0x6f, 0x17, 0xcc, 0xd2, 0x24, 0x21, 0x74, 0xcc, 0x32, 0x72, 0x2e, 0x99, 0x8d, 0x01, - 0xcf, 0x96, 0xf7, 0xaa, 0xaa, 0xb7, 0x13, 0xd1, 0x2e, 0xf0, 0x7d, 0x8f, 0x7c, 0xa8, 0xfe, 0x42, - 0x18, 0x7a, 0x46, 0xec, 0x46, 0x2a, 0x1f, 0xf3, 0xef, 0x2e, 0xc7, 0x74, 0x7f, 0x60, 0x46, 0xf1, - 0x9b, 0xb8, 0x45, 0x6e, 0x88, 0x3f, 0x71, 0xd8, 0xea, 0x43, 0x9e, 0x4b, 0xd9, 0x7b, 0xa9, 0xac, - 0x86, 0xf8, 0x20, 0x71, 0xf4, 0x81, 0xfa, 0xed, 0x4a, 0x46, 0xb7, 0xe6, 0xdd, 0x62, 0x2c, 0xcf, - 0x92, 0xcc, 0xb4, 0x4f, 0x5e, 0x33, 0xa0, 0xfe, 0xea, 0xcd, 0x41, 0x68, 0x1f, 0x7e, 0xc4, 0xc3, - 0x38, 0x67, 0x65, 0x37, 0xad, 0xc5, 0x88, 0xac, 0x51, 0x71, 0xfa, 0xec, 0x5a, 0x6d, 0x6b, 0x20, - 0x64, 0x81, 0xbc, 0x75, 0x7c, 0x2e, 0xf4, 0xb3, 0xfb, 0x5e, 0x0c, 0xbf, 0x14, 0x0f, 0x7d, 0x94, - 0x1a, 0x20, 0x11, 0xd4, 0x25, 0x4f, 0x24, 0x10, 0xe0, 0x80, 0x01, 0x00, 0x00, + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x26, 0x87, 0xb7, 0xa1, 0xb9, 0xcd, 0xb0, 0xe8, 0x9f, 0x7d, 0x06, + 0xfc, 0xe3, 0x24, 0x48, 0x8d, 0xbf, 0x18, 0x7f, 0x07, 0x98, 0xda, 0xe7, 0x41, 0xb4, 0xde, 0x89, + 0xe8, 0x4f, 0xf1, 0xcb, 0xee, 0x09, 0xf9, 0x1b, 0xd2, 0x3a, 0x9f, 0x12, 0xce, 0x1a, 0xfa, 0xed, + 0x2d, 0x15, 0x23, 0xa6, 0x56, 0x88, 0x4f, 0xbc, 0xa5, 0x77, 0x35, 0x6a, 0x8e, 0xdb, 0x53, 0x6d, + 0x6b, 0x51, 0x58, 0xe9, 0x94, 0xed, 0x80, 0x5f, 0x6c, 0x71, 0x7a, 0x52, 0x47, 0x09, 0xbb, 0x15, + 0xa5, 0xd4, 0x2e, 0x68, 0x53, 0x26, 0xf7, 0xdb, 0x39, 0xc9, 0x52, 0xda, 0x99, 0xe1, 0xc8, 0x97, + 0x94, 0xfd, 0xa0, 0xf2, 0x95, 0x60, 0x69, 0x75, 0x83, 0x57, 0x46, 0x89, 0x13, 0xa0, 0x02, 0x21, + 0xca, 0xc2, 0x8a, 0x54, 0x46, 0xc6, 0x87, 0xf8, 0x8c, 0x54, 0x4d, 0xf8, 0xf5, 0x2f, 0xc3, 0x94, + 0x6f, 0x94, 0x5e, 0xa1, 0x89, 0xf5, 0xf4, 0x48, 0x49, 0x83, 0x9a, 0x07, 0x80, 0xe2, 0x12, 0x3e, + 0x6f, 0x2b, 0xb7, 0x05, 0xe8, 0x22, 0x0a, 0xb2, 0xc6, 0x21, 0x42, 0x03, 0x6d, 0x32, 0xf0, 0x30, + 0x32, 0x72, 0xc8, 0xb9, 0x81, 0xb4, 0xa1, 0x3d, 0x6c, 0xb9, 0xdd, 0xfc, 0xe6, 0x2a, 0x2f, 0xcb, + 0xe7, 0xe5, 0x57, 0x21, 0x3a, 0x7d, 0x29, 0x83, 0x9d, 0xc9, 0x86, 0x21, 0xbf, 0xf2, 0x8f, 0xab, + 0xa6, 0xe3, 0xe4, 0x2c, 0x36, 0xaa, 0x86, 0xd6, 0x07, 0x16, 0x90, 0x4d, 0x82, 0xdd, 0xf4, 0x6d, + 0x2d, 0x88, 0x2e, 0xa4, 0xbf, 0x35, 0x58, 0x8e, 0x1f, 0x9a, 0x52, 0xb7, 0x9d, 0x9e, 0x10, 0x95, + 0xe9, 0x7c, 0x61, 0x58, 0x76, 0xfe, 0x59, 0xf4, 0x9c, 0x83, 0x9c, 0x5e, 0xa1, 0x0c, 0x46, 0x94, + 0xac, 0xe9, 0x33, 0x01, 0x34, 0x5a, 0xca, 0x9b, 0x6e, 0x89, 0xe5, 0xc1, 0xf7, 0xc5, 0xc9, 0xb3, + 0x2b, 0x87, 0x00, 0xad, 0xa6, 0x8c, 0xa6, 0xbc, 0x81, 0xdb, 0x54, 0x2c, 0x71, 0xfe, 0xc4, 0x88, + 0x55, 0x76, 0x97, 0x9f, 0x53, 0xb3, 0xb4, 0xbe, 0x16, 0xf9, 0xf8, 0xc8, 0x2e, 0x85, 0x9a, 0x1b, + 0x14, 0x83, 0x80, 0x30, 0x99, 0x00, 0xf8, 0x34, 0xbc, 0xe4, 0xc4, 0x8c, 0xbf, 0x84, 0x9e, 0x5b, + 0xfd, 0xb3, 0x5a, 0x84, 0x4f, 0x3d, 0x59, 0xb7, 0xea, 0x5e, 0x02, 0xf3, 0xb6, 0x89, 0xdd, 0x50, + 0xa7, 0x35, 0x6e, 0xc8, 0x3f, 0x36, 0x3b, 0x67, 0xf2, 0xc0, 0x22, 0xb7, 0x0f, 0x13, 0x2d, 0x59, + 0xc8, 0x4e, 0xb3, 0x2f, 0x0e, 0xb9, 0x72, 0xe1, 0x82, 0x64, 0x0c, 0xb9, 0xe6, 0x54, 0xed, 0x99, + 0x59, 0x47, 0x77, 0xd3, 0x24, 0x38, 0xd8, 0x8c, 0xdc, 0x60, 0x4e, 0xa8, 0x25, 0x6a, 0x62, 0x3b, + 0x32, 0x39, 0xff, 0xef, 0x82, 0xb8, 0x1b, 0x78, 0x99, 0x38, 0x80, 0xef, 0x6a, 0xaf, 0xc5, 0x0d, + 0x9e, 0x9f, 0x9f, 0xae, 0x3e, 0xf6, 0x20, 0x8c, 0xc6, 0x80, 0x01, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1117,7 +2030,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_patch_loc_data[] = { - 0x00, 0x1c, 0x00, 0x00, + 0x00, 0x39, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c index 896b27640..448ac7c04 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c @@ -34,459 +34,917 @@ // VAR NAME: booter_ucode_data_ga10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 8960 -// COMPRESSED SIZE (bytes): 7153 +// DATA SIZE (bytes): 20736 +// COMPRESSED SIZE (bytes): 14495 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_image_dbg_data[] = { - 0xed, 0xd9, 0x43, 0x5c, 0x25, 0x80, 0xb7, 0xc0, 0xf1, 0x6c, 0xdb, 0xc6, 0x64, 0x4d, 0xb6, 0x8d, - 0x9b, 0xed, 0x9a, 0xdc, 0xe4, 0x26, 0xdb, 0x9a, 0xcc, 0xc9, 0x35, 0x75, 0xb3, 0x6e, 0xbe, 0xb9, - 0xc9, 0xf6, 0xcd, 0x36, 0xa6, 0xc9, 0x78, 0xfb, 0xff, 0xe6, 0x2d, 0xdf, 0xe2, 0xfd, 0xbf, 0xbb, - 0xb3, 0x3e, 0xe7, 0xf3, 0xdb, 0x1c, 0x28, 0xa8, 0xff, 0xdf, 0x84, 0xa9, 0x0b, 0xc6, 0xea, 0x02, - 0x3d, 0x12, 0x22, 0x5d, 0x62, 0xb4, 0x93, 0x94, 0x6e, 0x3a, 0x42, 0x4a, 0xef, 0xbf, 0x53, 0x74, - 0x05, 0xb1, 0x5c, 0x58, 0x0e, 0xc8, 0x3f, 0xe5, 0x3d, 0x77, 0x1d, 0x75, 0x65, 0x8c, 0x26, 0xb2, - 0x44, 0x76, 0x20, 0xd7, 0x04, 0x64, 0x3a, 0x5d, 0x7e, 0x59, 0x07, 0xad, 0x4b, 0xdb, 0x93, 0xa6, - 0x7d, 0x0d, 0x45, 0x6e, 0x88, 0x12, 0x6b, 0xac, 0x25, 0xf5, 0x5b, 0xab, 0x2c, 0x01, 0x9c, 0x0d, - 0xd5, 0x1c, 0xed, 0x5f, 0x18, 0x4b, 0x0b, 0xa7, 0x12, 0x9a, 0x39, 0x0e, 0x77, 0x1d, 0x21, 0x1b, - 0xdc, 0x48, 0x22, 0x08, 0xaa, 0x0c, 0xc4, 0xcd, 0x2c, 0x04, 0xa9, 0xed, 0xd1, 0x61, 0xca, 0x7a, - 0xa3, 0x7c, 0x41, 0xb3, 0x98, 0x16, 0x30, 0x20, 0x6a, 0x08, 0x6e, 0x36, 0x5e, 0xd3, 0x75, 0xa7, - 0xf6, 0x24, 0x81, 0x01, 0x20, 0x65, 0x10, 0x77, 0xa2, 0x89, 0xed, 0xb5, 0x56, 0xdc, 0xdd, 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0x1f, 0xad, 0x58, 0x54, 0x6d, 0xa8, 0xd0, 0xd4, 0x0e, + 0x93, 0xf4, 0x65, 0x12, 0x34, 0x5f, 0x72, 0x88, 0xda, 0x79, 0xe9, 0xb5, 0xcf, 0x1f, 0x6b, 0x54, + 0xb5, 0x7b, 0x8c, 0x75, 0x67, 0x58, 0x1e, 0x9e, 0x5f, 0x8c, 0xa2, 0x52, 0x28, 0xda, 0x14, 0x5f, + 0xfe, 0x29, 0x47, 0x3a, 0x07, 0x02, 0xbb, 0xf9, 0x4d, 0x17, 0xc0, 0x84, 0x65, 0xfb, 0x3e, 0x82, + 0xf9, 0x08, 0x07, 0xfc, 0x7f, 0xbd, 0x7f, 0xf9, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, + 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, + 0xf3, 0xcf, 0x3f, 0xff, 0x37, 0xfc, 0x0f, 0xe6, 0x9c, 0x24, 0xde, 0x00, 0x51, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -496,8 +954,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 8960, // uncompressed data size (bytes) - 7153, // compressed data size (bytes) + 20736, // uncompressed data size (bytes) + 14495, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -519,8 +977,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x05, 0x62, 0x56, 0x08, 0x13, 0x4c, 0xc8, 0x40, 0x69, - 0x20, 0x00, 0x00, 0x8e, 0xa1, 0x42, 0xb2, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xb6, 0x02, 0x62, 0x71, 0x08, 0x13, 0x4c, 0x58, 0x42, 0x69, + 0x20, 0x00, 0x00, 0x92, 0xc7, 0x51, 0xc7, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -548,458 +1006,918 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_header_dbg_storage_pvt // VAR NAME: booter_ucode_data_ga10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 8960 -// COMPRESSED SIZE (bytes): 7151 +// DATA SIZE (bytes): 20736 +// COMPRESSED SIZE (bytes): 14499 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_image_prod_data[] = { - 0xed, 0xd9, 0x43, 0x5c, 0x25, 0x80, 0xb7, 0xc0, 0xf1, 0xec, 0xc9, 0x9a, 0xcc, 0x9b, 0xad, 0xc9, - 0x9e, 0x78, 0xb3, 0xed, 0x9b, 0xed, 0x9a, 0xec, 0x09, 0x93, 0x75, 0xb3, 0xed, 0x6e, 0xb6, 0x6b, - 0xe2, 0x64, 0x7b, 0xb2, 0x27, 0xd7, 0xdb, 0xff, 0x37, 0x6f, 0xf9, 0x16, 0xef, 0xff, 0xdd, 0x9d, - 0xf5, 0x39, 0x9f, 0xdf, 0xe6, 0x40, 0x41, 0xfd, 0xff, 0xd6, 0x79, 0x67, 0x52, 0x95, 0x42, 0x79, - 0xc0, 0x8b, 0x33, 0x67, 0xea, 0xf0, 0xa1, 0x47, 0x39, 0xbc, 0x33, 0xcf, 0x86, 0x1c, 0x0a, 0x33, - 0xe8, 0x66, 0xa0, 0xb6, 0xb0, 0xd0, 0xc0, 0xd7, 0x93, 0xbb, 0xbb, 0x57, 0x12, 0x47, 0x7d, 0xf6, - 0xc2, 0x05, 0x2e, 0xfa, 0x43, 0xf1, 0xb7, 0xa8, 0xf9, 0x1e, 0x72, 0x28, 0xeb, 0x8c, 0xb3, 0x17, - 0x44, 0x59, 0x8e, 0x46, 0x9c, 0xd3, 0xbb, 0xb5, 0x10, 0x94, 0x27, 0xc6, 0xda, 0x5a, 0xce, 0x9c, - 0xfc, 0xf8, 0xcb, 0x6e, 0x16, 0xe7, 0x53, 0xa6, 0xd7, 0x17, 0x17, 0x09, 0xa0, 0xf5, 0x90, 0xa4, - 0x90, 0xb8, 0xd2, 0x41, 0x72, 0xa3, 0xd1, 0x11, 0x75, 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kgspBinArchiveBooterUnloadUcode_GA102_image_prod_storage_pvt #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 8960, // uncompressed data size (bytes) - 7151, // compressed data size (bytes) + 20736, // uncompressed data size (bytes) + 14499, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1032,8 +1950,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_image_prod_storage_pvt // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x05, 0x62, 0x56, 0x08, 0x13, 0x4c, 0xc8, 0x40, 0x69, - 0x20, 0x00, 0x00, 0x8e, 0xa1, 0x42, 0xb2, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xb6, 0x02, 0x62, 0x71, 0x08, 0x13, 0x4c, 0x58, 0x42, 0x69, + 0x20, 0x00, 0x00, 0x92, 0xc7, 0x51, 0xc7, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1066,55 +1984,55 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_header_prod_storage_pv // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_sig_dbg_data[] = { - 0x01, 0x00, 0x03, 0xff, 0xfc, 0x77, 0x3d, 0x96, 0x96, 0xa6, 0xde, 0x8a, 0x3f, 0xda, 0x60, 0x62, - 0x3b, 0xf6, 0x5f, 0x56, 0x8d, 0xe8, 0xda, 0x1e, 0xdb, 0x7a, 0x29, 0xd6, 0xfd, 0x83, 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0x96, 0x07, 0xc4, 0x24, + 0x42, 0x51, 0xaf, 0xe7, 0x3c, 0x00, 0xdc, 0xf5, 0xe5, 0x77, 0xb4, 0xfc, 0xc1, 0xc9, 0xca, 0x3c, + 0x9c, 0xc3, 0xf6, 0xa8, 0x54, 0x76, 0x30, 0xdf, 0x56, 0x5c, 0x8f, 0xfb, 0x8d, 0x36, 0x38, 0xab, + 0xcd, 0x95, 0x4c, 0x4b, 0x80, 0xa7, 0x27, 0xbd, 0xe0, 0x26, 0x31, 0x04, 0x76, 0x83, 0x50, 0xfa, + 0xec, 0x00, 0xba, 0xad, 0x15, 0xf4, 0xd2, 0xec, 0xcc, 0x00, 0x03, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1143,37 +2061,37 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_sig_dbg_storage_pvt; // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 768 -// COMPRESSED SIZE (bytes): 421 +// COMPRESSED SIZE (bytes): 418 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_sig_prod_data[] = { - 0xf3, 0x7a, 0x16, 0x2f, 0x7b, 0x64, 0xf9, 0xec, 0x6f, 0x41, 0xdb, 0x45, 0x3a, 0x1e, 0x37, 0x6d, - 0xbf, 0xbb, 0xf4, 0x9e, 0x44, 0x03, 0xab, 0xf2, 0x5d, 0xfd, 0x89, 0xec, 0x52, 0x97, 0xde, 0x5d, - 0x58, 0xc7, 0xd6, 0xb0, 0x7d, 0xd2, 0x97, 0x53, 0x49, 0xb9, 0x12, 0x76, 0x0f, 0x19, 0x7e, 0x7f, - 0xdb, 0xd6, 0x1b, 0xb2, 0x5a, 0xf4, 0xec, 0xc2, 0xf0, 0x27, 0x9e, 0xad, 0x82, 0xfb, 0x37, 0xcd, - 0x64, 0x50, 0x3e, 0xeb, 0xbd, 0x99, 0x93, 0x71, 0x7e, 0xd9, 0x19, 0xd7, 0xaf, 0xea, 0xcb, 0xac, - 0xf8, 0x1c, 0xfb, 0x36, 0x05, 0xcc, 0x92, 0x90, 0xb9, 0x9e, 0x55, 0x19, 0x3e, 0x73, 0xc2, 0x77, - 0xf7, 0xb3, 0xfb, 0xb2, 0x94, 0x3c, 0x55, 0xa7, 0xee, 0xc8, 0x64, 0x9b, 0x23, 0xac, 0x94, 0xba, - 0x4d, 0x5e, 0x63, 0xf7, 0xc4, 0x52, 0x87, 0xcb, 0xb7, 0xaf, 0x5b, 0x7e, 0x79, 0x70, 0xe5, 0xba, - 0xaf, 0xff, 0xdf, 0x9e, 0x47, 0x17, 0x45, 0x8f, 0x19, 0xfd, 0x5c, 0x98, 0x7d, 0xb5, 0x68, 0x8e, - 0xe3, 0x36, 0x35, 0x91, 0x50, 0x67, 0xdb, 0xcb, 0x36, 0x97, 0x19, 0x03, 0xb6, 0x6d, 0x4d, 0x16, - 0xb8, 0xa1, 0xea, 0x39, 0x4b, 0xe4, 0x46, 0x97, 0xa4, 0xc8, 0xe3, 0x37, 0x39, 0x61, 0x52, 0x9b, - 0x5d, 0xcf, 0xee, 0xd9, 0x11, 0xc9, 0xb4, 0x46, 0x42, 0x69, 0xd2, 0xfe, 0x04, 0x21, 0xd3, 0xdd, - 0xd9, 0xea, 0x1c, 0x67, 0xae, 0xe8, 0x38, 0xc4, 0x9d, 0x99, 0x7c, 0xa0, 0x6e, 0x4d, 0xa5, 0xd9, - 0x81, 0x7b, 0x9f, 0x3d, 0xf6, 0x44, 0x1b, 0x16, 0x65, 0xac, 0x7c, 0x96, 0x37, 0x4b, 0xf9, 0x52, - 0xc6, 0x2a, 0xeb, 0x05, 0x7e, 0xcf, 0x4f, 0xaf, 0x3f, 0xff, 0xc2, 0x98, 0x69, 0xf6, 0x4f, 0x1b, - 0xc6, 0x37, 0x25, 0xff, 0x04, 0x6a, 0xd8, 0x1b, 0x19, 0xb7, 0xdd, 0x3b, 0xdd, 0x32, 0x9f, 0x63, - 0xc7, 0xa3, 0x19, 0x9d, 0xd7, 0xbd, 0xd7, 0x1f, 0xba, 0xd4, 0x7a, 0x30, 0xbb, 0x6e, 0xd1, 0x45, - 0xe9, 0xda, 0xde, 0x94, 0x57, 0x27, 0x12, 0xad, 0xfe, 0x6b, 0x86, 0x7f, 0x0b, 0xb8, 0xb2, 0xe4, - 0x8c, 0x47, 0x4c, 0xe7, 0xc3, 0x1d, 0x96, 0xfa, 0x9e, 0x87, 0xaf, 0x4a, 0x97, 0xad, 0x4d, 0xf4, - 0xca, 0x3d, 0x79, 0xac, 0x55, 0x4e, 0xb1, 0xc7, 0x82, 0xd7, 0x2f, 0x8b, 0xf7, 0xcd, 0x97, 0xeb, - 0x3b, 0x66, 0x2b, 0x68, 0x65, 0x57, 0xfd, 0xef, 0x8d, 0x53, 0x78, 0xd3, 0xfd, 0xed, 0x49, 0xe6, - 0xa5, 0xb9, 0x86, 0xaf, 0x15, 0xae, 0x7f, 0x5b, 0x90, 0x3a, 0xdb, 0x52, 0xb5, 0x73, 0x57, 0x41, - 0xb9, 0xc7, 0xb3, 0xa2, 0x29, 0xf7, 0x2f, 0x27, 0x35, 0xa8, 0x15, 0x1c, 0x95, 0x5a, 0xeb, 0xf8, - 0xc4, 0x83, 0x4b, 0xfc, 0xc5, 0xf9, 0x75, 0xb9, 0x95, 0xe6, 0x9f, 0x14, 0x39, 0xf7, 0x6c, 0x5a, - 0xf5, 0xc9, 0xe8, 0x42, 0x8c, 0x97, 0xe8, 0x1a, 0xe6, 0x73, 0x05, 0xbb, 0xd2, 0x9a, 0xff, 0xdf, - 0xf4, 0x8c, 0xfa, 0xf8, 0x62, 0xa2, 0x33, 0xc3, 0x28, 0x18, 0x50, 0x00, 0x00, 0x6f, 0x81, 0x84, - 0xf3, 0x00, 0x03, 0x00, 0x00, + 0xb3, 0xfa, 0x7f, 0xa2, 0xf2, 0xa0, 0xc0, 0x7e, 0x73, 0x4e, 0x21, 0x83, 0xa7, 0xec, 0x5f, 0x42, + 0xb6, 0x78, 0x3e, 0x73, 0xae, 0x5c, 0x7f, 0x85, 0x49, 0xd6, 0x24, 0xb6, 0xea, 0x58, 0x21, 0xf7, + 0xf5, 0x9f, 0x39, 0x7d, 0xd3, 0x55, 0xbb, 0xad, 0x85, 0x34, 0x66, 0xb9, 0xf9, 0x4c, 0x4d, 0xfb, + 0xcd, 0xfa, 0x7e, 0xf7, 0x8e, 0xc3, 0xe5, 0xd3, 0xc5, 0xeb, 0x6d, 0x24, 0x3f, 0x39, 0xef, 0x60, + 0xd3, 0x33, 0xfa, 0xfb, 0x95, 0x33, 0x3a, 0x6f, 0x67, 0x65, 0x8d, 0x69, 0xe2, 0xb2, 0x0e, 0xef, + 0x4d, 0x75, 0x52, 0x75, 0xf6, 0x37, 0x96, 0xee, 0x95, 0xbc, 0xed, 0xa8, 0x69, 0x67, 0x6b, 0xde, + 0xbb, 0x6b, 0x69, 0x9b, 0x68, 0xe3, 0x86, 0x9b, 0xc7, 0xef, 0xa7, 0x84, 0x7e, 0xd5, 0x5d, 0x71, + 0x2b, 0x62, 0x83, 0xee, 0x01, 0x83, 0x25, 0x12, 0xed, 0xff, 0x2f, 0x85, 0xaa, 0x28, 0x04, 0x71, + 0x1b, 0x68, 0xab, 0x86, 0x79, 0xbf, 0xfb, 0x1d, 0x58, 0xf4, 0xc6, 0x52, 0xf3, 0x40, 0xbf, 0xc5, + 0x9d, 0x20, 0x83, 0x95, 0xdf, 0xfe, 0x2b, 0x6a, 0x4b, 0xfd, 0x31, 0x7a, 0x56, 0xd1, 0x16, 0xf4, + 0x7c, 0x79, 0xcc, 0xf7, 0x6d, 0x61, 0xb7, 0xda, 0x7f, 0xf4, 0xb9, 0x48, 0x3c, 0x32, 0x7b, 0xb0, + 0xe2, 0x92, 0xd0, 0xa5, 0xc0, 0x6d, 0x0e, 0x66, 0xfa, 0xea, 0x8e, 0x8e, 0xa7, 0x0f, 0xfa, 0x9e, + 0x8e, 0x2b, 0xee, 0xe0, 0xe8, 0x3b, 0x70, 0xdd, 0xd3, 0xc1, 0xa8, 0xfe, 0xdf, 0xb4, 0xbf, 0xa7, + 0x1a, 0x97, 0x77, 0xd8, 0xc4, 0x29, 0x1b, 0x2e, 0x29, 0xaa, 0x58, 0x3b, 0xef, 0xea, 0x86, 0x5e, + 0xd1, 0xed, 0x21, 0x53, 0xbf, 0x08, 0x4f, 0xb4, 0x5c, 0x31, 0x6f, 0x71, 0x75, 0x71, 0xdf, 0xb6, + 0x1d, 0x5f, 0x3c, 0xe7, 0xee, 0xfc, 0xb6, 0xc2, 0xdb, 0x87, 0x49, 0xc3, 0xce, 0x46, 0xa0, 0xd9, + 0xf2, 0x71, 0xcd, 0x92, 0x03, 0x76, 0xff, 0x7c, 0xfe, 0x7c, 0x71, 0x28, 0xf7, 0x35, 0xb1, 0x7a, + 0x1b, 0x33, 0x7f, 0xf5, 0xee, 0xbe, 0xd2, 0x19, 0x33, 0x3e, 0x39, 0x76, 0x2d, 0x57, 0x7b, 0x1e, + 0x6f, 0xda, 0x7e, 0x21, 0x9c, 0x3f, 0x96, 0x39, 0x8e, 0xaf, 0xbc, 0x44, 0xab, 0x45, 0x77, 0x11, + 0x73, 0xf2, 0xfa, 0x8f, 0xe1, 0x7d, 0xff, 0xcc, 0x2e, 0x5b, 0xca, 0x95, 0xdd, 0xfd, 0xf6, 0xc5, + 0xfe, 0xc7, 0xe3, 0x5f, 0xb1, 0x8e, 0x3b, 0xc5, 0xa7, 0x5e, 0x66, 0xe5, 0xf9, 0xb0, 0x49, 0x70, + 0x7d, 0x6c, 0xeb, 0xd5, 0x0c, 0x66, 0xf6, 0x06, 0xe7, 0x82, 0xdd, 0x35, 0x59, 0x7d, 0x5f, 0xef, + 0xfc, 0x7b, 0xb3, 0x5c, 0x3d, 0xfd, 0x93, 0x5f, 0xed, 0xc5, 0x55, 0xc1, 0xa7, 0x8b, 0xcf, 0xda, + 0x3f, 0xe9, 0x65, 0xfd, 0xc9, 0xc8, 0x5d, 0x38, 0x75, 0xb9, 0x62, 0x8b, 0xc3, 0x97, 0xad, 0x4a, + 0xd7, 0x8f, 0x34, 0x4c, 0x6e, 0x99, 0x1f, 0xd7, 0xff, 0xe8, 0x88, 0x41, 0xce, 0xba, 0xb6, 0x69, + 0x97, 0x45, 0x4b, 0xec, 0x19, 0x46, 0xc1, 0x80, 0x02, 0x00, 0x5a, 0x0e, 0xb9, 0xb4, 0x00, 0x03, + 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1184,7 +2102,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_sig_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 768, // uncompressed data size (bytes) - 421, // compressed data size (bytes) + 418, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA102_sig_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1206,7 +2124,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_patch_loc_data[] = { - 0x10, 0x1d, 0x00, 0x00, + 0x10, 0x3a, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c index 8d151f7bb..19a88d95a 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c @@ -34,424 +34,883 @@ // VAR NAME: booter_ucode_data_tu10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 8192 -// COMPRESSED SIZE (bytes): 6600 +// DATA SIZE (bytes): 19968 +// COMPRESSED SIZE (bytes): 13941 // static BINDATA_CONST NvU8 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0x3b, 0x7d, 0x42, 0xc6, 0x68, 0xf4, 0xee, 0x23, 0xfb, 0xf5, 0x3e, + 0xee, 0x1b, 0x85, 0xda, 0xc3, 0x18, 0x8b, 0x1e, 0x3a, 0x3b, 0x6f, 0x7b, 0x04, 0x5c, 0x15, 0xbd, + 0x93, 0x9d, 0x52, 0x35, 0x93, 0x3a, 0x7c, 0x25, 0x9b, 0x65, 0x73, 0x26, 0x5e, 0xcb, 0x63, 0x12, + 0xb3, 0x28, 0x1d, 0x65, 0x70, 0x90, 0xc6, 0xee, 0x1c, 0x01, 0xb9, 0x32, 0xe2, 0xf2, 0x88, 0x27, + 0xfa, 0x3b, 0x20, 0xd9, 0xe6, 0x28, 0xcf, 0xb2, 0xa3, 0x0a, 0xcb, 0xcc, 0x1a, 0xcf, 0x0b, 0xed, + 0xdc, 0xf0, 0x9f, 0xf9, 0x4b, 0xd0, 0x6f, 0x8b, 0xa0, 0x0f, 0xd8, 0xa3, 0x02, 0x3e, 0x34, 0xac, + 0x8a, 0xd4, 0x04, 0xa7, 0x3a, 0xcb, 0xed, 0x40, 0x2a, 0xf7, 0xaa, 0x3d, 0x39, 0x09, 0x20, 0xb5, + 0x0e, 0xcf, 0xda, 0x25, 0x58, 0x38, 0xc4, 0x97, 0x85, 0x49, 0x4f, 0x93, 0x50, 0x36, 0xbb, 0x29, + 0xa1, 0x4b, 0xb1, 0x21, 0x70, 0xae, 0xe2, 0x54, 0xfa, 0xff, 0x6f, 0x39, 0xe0, 0x9f, 0x7f, 0xfe, + 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, + 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0x3f, 0xe8, 0xff, 0x01, 0x56, 0x5d, 0xc1, + 0xba, 0x00, 0x4e, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -461,8 +920,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 8192, // uncompressed data size (bytes) - 6600, // compressed data size (bytes) + 19968, // uncompressed data size (bytes) + 13941, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_TU102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -484,8 +943,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x02, 0x62, 0x36, 0x08, 0x13, 0x4c, 0x48, 0x42, 0x69, - 0x20, 0x00, 0x00, 0x77, 0x72, 0x25, 0x67, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x36, 0x07, 0x62, 0x71, 0x08, 0x13, 0x4c, 0x98, 0x41, 0x69, + 0x20, 0x00, 0x00, 0xda, 0x95, 0xe6, 0x99, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -513,424 +972,883 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_header_dbg_storage_pvt // VAR NAME: booter_ucode_data_tu10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 8192 -// COMPRESSED SIZE (bytes): 6599 +// DATA SIZE (bytes): 19968 +// COMPRESSED SIZE (bytes): 13940 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_image_prod_data[] = { - 0xed, 0x99, 0x45, 0x54, 0x1c, 0x8c, 0xce, 0x86, 0x87, 0xc1, 0x07, 0xca, 0xe0, 0x5a, 0x8a, 0x15, - 0x8a, 0xbb, 0xbb, 0x6b, 0x29, 0x32, 0x1d, 0x1c, 0x0a, 0x14, 0x77, 0x2b, 0x52, 0xdc, 0x5d, 0x0a, - 0x83, 0xbb, 0xb4, 0xb8, 0xbb, 0xbb, 0xbb, 0x0f, 0xc5, 0x4a, 0x71, 0x8a, 0x17, 0x67, 0x80, 0xff, - 0xbb, 0xdb, 0xbb, 0xbb, 0xdb, 0xff, 0x7c, 0xcf, 0xe6, 0x4d, 0x36, 0x49, 0x16, 0x49, 0x4e, 0xce, - 0x49, 0x24, 0x00, 0x80, 0xf4, 0x0c, 0x03, 0xf8, 0x81, 0x01, 0x80, 0x3b, 0xe0, 0x1d, 0xe0, 0x1e, - 0x18, 0x0b, 0x00, 0x02, 0xba, 0x37, 0x36, 0x5f, 0x5e, 0x5e, 0xc0, 0x91, 0x00, 0x24, 0xc0, 0x4b, - 0x2e, 0x4a, 0xfd, 0x0e, 0x80, 0x27, 0x6d, 0x05, 0xa9, 0x1e, 0x06, 0x60, 0x4d, 0x5b, 0x01, 0xfe, - 0x23, 0xf4, 0x69, 0x2b, 0xc8, 0xff, 0xc8, 0x9b, 0x48, 0x00, 0x00, 0x90, 0x96, 0x8b, 0xdc, 0xb8, - 0x89, 0xdc, 0x9d, 0x9b, 0xb7, 0x99, 0x96, 0x8b, 0x94, 0x96, 0x0e, 0x6c, 0xdc, 0x44, 0x6a, 0x5c, - 0x01, 0xfa, 0x35, 0x01, 0x00, 0x60, 0x2e, 0x25, 0x00, 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0xbe, 0x64, 0x3c, 0xbc, 0xae, 0x12, 0x65, 0x32, 0xfc, 0x7e, + 0xfa, 0x38, 0xeb, 0x3f, 0x5e, 0xe1, 0x38, 0x1e, 0x9f, 0x22, 0x08, 0x49, 0x77, 0x1f, 0x10, 0x39, + 0xee, 0x3c, 0x06, 0xdd, 0x51, 0x9f, 0x99, 0x62, 0xd2, 0x50, 0xc5, 0x51, 0x68, 0x26, 0x6d, 0x9b, + 0xa5, 0x82, 0xb3, 0xac, 0xab, 0xe5, 0x2c, 0x2e, 0xbc, 0xbb, 0xdb, 0x22, 0xff, 0x13, 0x06, 0x9b, + 0x2a, 0xe2, 0x10, 0x13, 0x12, 0xff, 0x41, 0xa6, 0xfb, 0x5b, 0x83, 0x55, 0xca, 0xa9, 0xff, 0xa0, + 0x3b, 0xf6, 0x86, 0xe4, 0xd6, 0x46, 0x09, 0x72, 0x45, 0x31, 0xd2, 0x4b, 0xfa, 0x97, 0xe5, 0x3a, + 0x4a, 0xc6, 0x18, 0xff, 0xd2, 0xe2, 0xfd, 0x72, 0xf4, 0x31, 0x34, 0x07, 0xf6, 0x61, 0xef, 0x3c, + 0xc6, 0x05, 0xb5, 0x98, 0xbe, 0x14, 0xf1, 0x37, 0x6f, 0x5b, 0x15, 0x0d, 0xbf, 0xe5, 0xa9, 0xc2, + 0x01, 0x14, 0x8a, 0xc3, 0xca, 0x9a, 0x82, 0x13, 0xfc, 0xff, 0x2d, 0x07, 0xfc, 0xf3, 0xcf, 0x3f, + 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, + 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0xff, 0x07, 0xfd, 0x3f, 0xe8, 0xbe, 0xe0, 0x77, + 0x00, 0x4e, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -940,8 +1858,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_image_prod_storage_pvt #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 8192, // uncompressed data size (bytes) - 6599, // compressed data size (bytes) + 19968, // uncompressed data size (bytes) + 13940, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_TU102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -963,8 +1881,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_image_prod_storage_pvt // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x02, 0x62, 0x36, 0x08, 0x13, 0x4c, 0x48, 0x42, 0x69, - 0x20, 0x00, 0x00, 0x77, 0x72, 0x25, 0x67, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x36, 0x07, 0x62, 0x71, 0x08, 0x13, 0x4c, 0x98, 0x41, 0x69, + 0x20, 0x00, 0x00, 0xda, 0x95, 0xe6, 0x99, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -997,7 +1915,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_header_prod_storage_pv // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_sig_dbg_data[] = { - 0x8d, 0xf3, 0xbb, 0x29, 0x1d, 0x0d, 0xac, 0xa0, 0xce, 0x43, 0xd8, 0xc5, 0x51, 0xb0, 0xd0, 0x9d, + 0x10, 0xf0, 0x2c, 0x6d, 0xec, 0xb3, 0x69, 0x81, 0x7f, 0x52, 0x0a, 0x94, 0x5d, 0x50, 0x0b, 0xdf, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1030,7 +1948,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_sig_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_sig_prod_data[] = { - 0x5b, 0xe8, 0xcf, 0xaa, 0x40, 0x4a, 0x12, 0xff, 0xf0, 0xe8, 0x39, 0x5b, 0x2e, 0x44, 0x7a, 0x64, + 0xa3, 0xad, 0x00, 0x41, 0x0c, 0xf3, 0x83, 0x0d, 0x21, 0x82, 0x37, 0x80, 0xcd, 0x36, 0xa6, 0x4d, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1063,7 +1981,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_patch_loc_data[] = { - 0x00, 0x1c, 0x00, 0x00, + 0x00, 0x39, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c index 759da2dc6..ff78b68c5 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c @@ -34,424 +34,881 @@ // VAR NAME: booter_ucode_data_tu11x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 8192 -// COMPRESSED SIZE (bytes): 6602 +// DATA SIZE (bytes): 19968 +// COMPRESSED SIZE (bytes): 13907 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_image_dbg_data[] = { - 0xed, 0x99, 0x45, 0x54, 0x1c, 0xd0, 0xd2, 0xad, 0x1b, 0x97, 0xe0, 0x2e, 0xc1, 0x82, 0x5b, 0x63, - 0xc1, 0xdd, 0x25, 0xb8, 0xbb, 0x06, 0x08, 0xee, 0x12, 0x5c, 0x83, 0x76, 0x70, 0x77, 0x68, 0xbc, - 0x71, 0x77, 0x97, 0x20, 0x8d, 0x5b, 0x90, 0xe0, 0x16, 0xdc, 0x9d, 0x97, 0x7f, 0x7a, 0x67, 0x77, - 0xfa, 0xd6, 0xfd, 0x26, 0xbb, 0xf6, 0xe4, 0xd4, 0x19, 0x54, 0xad, 0xb5, 0xcf, 0x3a, 0x51, 0x00, - 0x00, 0xcc, 0x5b, 0x32, 0x20, 0x00, 0x13, 0x00, 0x78, 0x80, 0x7d, 0x00, 0x3c, 0xc2, 0x82, 0x00, - 0xb0, 0x80, 0x9e, 0x8d, 0x3f, 0xef, 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0xca, 0xc0, 0xff, 0xad, 0x0f, 0xf8, 0xcf, 0x7f, 0xfe, 0xf3, 0x9f, 0xff, 0xfc, + 0xe7, 0x3f, 0xff, 0xf9, 0xcf, 0x7f, 0xfe, 0xf3, 0x9f, 0xff, 0xfc, 0xe7, 0x3f, 0xff, 0xf9, 0xcf, + 0x7f, 0xfe, 0xf3, 0x9f, 0xff, 0xfc, 0xe7, 0xff, 0x43, 0xff, 0x0b, 0xee, 0x0e, 0x5c, 0x38, 0x00, + 0x4e, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -461,8 +918,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU116_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 8192, // uncompressed data size (bytes) - 6602, // compressed data size (bytes) + 19968, // uncompressed data size (bytes) + 13907, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_TU116_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -484,8 +941,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU116_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x02, 0x62, 0x36, 0x08, 0x13, 0x4c, 0x48, 0x42, 0x69, - 0x20, 0x00, 0x00, 0x77, 0x72, 0x25, 0x67, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x36, 0x07, 0x62, 0x71, 0x08, 0x13, 0x4c, 0x98, 0x41, 0x69, + 0x20, 0x00, 0x00, 0xda, 0x95, 0xe6, 0x99, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -513,423 +970,880 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU116_header_dbg_storage_pvt // VAR NAME: booter_ucode_data_tu11x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 8192 -// COMPRESSED SIZE (bytes): 6594 +// DATA SIZE (bytes): 19968 +// COMPRESSED SIZE (bytes): 13906 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_image_prod_data[] = { - 0xed, 0x99, 0x45, 0x50, 0x1e, 0x8a, 0xce, 0x86, 0x3f, 0x83, 0xe2, 0x56, 0xa0, 0xb8, 0x7e, 0xb8, - 0xbb, 0x6b, 0x81, 0x22, 0xc5, 0xdd, 0xdd, 0xdd, 0x29, 0xee, 0xee, 0xee, 0x0e, 0xc5, 0x29, 0x50, - 0xbc, 0xb8, 0xbb, 0x7b, 0x71, 0x97, 0xe2, 0xc5, 0xe5, 0x3f, 0x77, 0x7b, 0x77, 0x77, 0xfb, 0xcf, - 0x79, 0x36, 0x6f, 0xb2, 0x49, 0x32, 0x99, 0x64, 0x26, 0x33, 0x89, 0x00, 0x00, 0x80, 0x6f, 0xc9, - 0x00, 0x5f, 0x54, 0x00, 0xe0, 0x01, 0xf4, 0x00, 0x78, 0x04, 0xc5, 0x00, 0x40, 0x80, 0xae, 0x8d, - 0xcd, 0xf7, 0xf7, 0x77, 0xd4, 0x08, 0x00, 0x10, 0xf0, 0x9e, 0x07, 0x69, 0xd8, 0x03, 0xb0, 0xa5, - 0xaf, 0x00, 0x1b, 0x92, 0x01, 0xf4, 0xe9, 0x2b, 0xa0, 0x7f, 0x84, 0x22, 0x7d, 0x05, 0xfc, 0x8f, - 0x10, 0x45, 0x00, 0x00, 0x80, 0xf4, 0x3c, 0x70, 0xe3, 0x26, 0xb8, 0x2b, 0x2f, 0x7f, 0x33, 0x3d, - 0x0f, 0x98, 0x9e, 0x01, 0x6a, 0xdc, 0x04, 0x36, 0xae, 0x80, 0x7c, 0x9b, 0x00, 0x00, 0x54, 0x16, - 0x29, 0x00, 0xda, 0x7d, 0x1e, 0x00, 0x15, 0x18, 0x01, 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0x7b, 0x1c, 0x1e, + 0x5a, 0xe4, 0x55, 0x3b, 0x70, 0x0b, 0xe2, 0xa9, 0xe1, 0xfa, 0x59, 0x05, 0x4e, 0x04, 0xaa, 0xf4, + 0x64, 0xa0, 0xce, 0x82, 0x5f, 0xd4, 0xd3, 0xb7, 0xa2, 0x80, 0xf9, 0xb0, 0x70, 0x0e, 0xd0, 0xf5, + 0xc8, 0xeb, 0x8e, 0x7f, 0x33, 0x09, 0xcf, 0xde, 0xb4, 0xf4, 0xd1, 0xbe, 0x93, 0x0e, 0xf6, 0xeb, + 0xbf, 0xcf, 0x5f, 0x4f, 0x6e, 0x85, 0x3a, 0xd8, 0x33, 0xeb, 0xa6, 0x53, 0xe7, 0xdb, 0x6f, 0x52, + 0x10, 0x40, 0x04, 0x27, 0x87, 0x39, 0xec, 0x4d, 0x46, 0xbb, 0x7a, 0x10, 0x8d, 0xd6, 0xda, 0x35, + 0x3c, 0x46, 0xe5, 0xff, 0xdf, 0x62, 0xa0, 0xff, 0xfc, 0xe7, 0x3f, 0xff, 0xf9, 0xcf, 0x7f, 0xfe, + 0xf3, 0x9f, 0xff, 0xfc, 0xe7, 0x3f, 0xff, 0xf9, 0xcf, 0x7f, 0xfe, 0xf3, 0x9f, 0xff, 0xfc, 0xe7, + 0x3f, 0xff, 0xf9, 0xcf, 0x7f, 0xfe, 0x3f, 0xf4, 0xbf, 0x00, 0xd4, 0xd5, 0x08, 0x62, 0x00, 0x4e, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -940,8 +1854,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU116_image_prod_storage_pvt #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 8192, // uncompressed data size (bytes) - 6594, // compressed data size (bytes) + 19968, // uncompressed data size (bytes) + 13906, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_TU116_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -963,8 +1877,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU116_image_prod_storage_pvt // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x02, 0x62, 0x36, 0x08, 0x13, 0x4c, 0x48, 0x42, 0x69, - 0x20, 0x00, 0x00, 0x77, 0x72, 0x25, 0x67, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x36, 0x07, 0x62, 0x71, 0x08, 0x13, 0x4c, 0x98, 0x41, 0x69, + 0x20, 0x00, 0x00, 0xda, 0x95, 0xe6, 0x99, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -997,7 +1911,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU116_header_prod_storage_pv // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_sig_dbg_data[] = { - 0xd2, 0xd7, 0x61, 0x5d, 0x7e, 0x54, 0x57, 0xef, 0xa8, 0xba, 0xb0, 0x6c, 0x4b, 0xf1, 0x2b, 0xbc, + 0x0d, 0x0a, 0x86, 0x3d, 0x58, 0x5c, 0x19, 0x82, 0xfe, 0x07, 0x84, 0x4d, 0x20, 0xd0, 0xe8, 0xc8, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1030,7 +1944,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU116_sig_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_sig_prod_data[] = { - 0x6b, 0x77, 0x25, 0x37, 0xf0, 0xfe, 0x01, 0x30, 0x26, 0xef, 0xb5, 0x87, 0x87, 0xff, 0x2c, 0x57, + 0x23, 0x4b, 0x2a, 0xa1, 0x16, 0xcc, 0x7e, 0x43, 0x97, 0xfc, 0x16, 0x7f, 0x7c, 0x23, 0x80, 0x28, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1063,7 +1977,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU116_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_patch_loc_data[] = { - 0x00, 0x1c, 0x00, 0x00, + 0x00, 0x39, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c index 502af8dbf..fe13c21c4 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c @@ -29,476 +29,1098 @@ #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmBoot_GA102("ucode_image_dbg") -// FILE NAME: kernel/inc/gsprm/bin/g_gsprm_skbl_dbg_ga102_riscv_image.bin +// FILE NAME: kernel/inc/gsprm/bin/g_gsprm_skbl_dbg_libos3_ga102_riscv_image.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 12288 -// COMPRESSED SIZE (bytes): 7350 +// DATA SIZE (bytes): 20480 +// COMPRESSED SIZE (bytes): 17302 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GA102_ucode_image_dbg_data[] = { - 0xed, 0x97, 0x67, 0x54, 0x53, 0x5d, 0xb3, 0xc7, 0x13, 0x02, 0x24, 0x14, 0x21, 0x74, 0xa4, 0x28, - 0x84, 0x0e, 0x2a, 0xa8, 0xf4, 0x5e, 0xa4, 0x89, 0x34, 0x41, 0x40, 0x41, 0x5a, 0x68, 0x02, 0xd2, - 0x3b, 0x48, 0x0f, 0xa1, 0xb7, 0x00, 0x01, 0x69, 0x52, 0x05, 0xa4, 0xf7, 0x26, 0x2d, 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0xe3, 0xff, 0xda, 0x5f, 0xf0, 0xff, + 0xca, 0xea, 0x9f, 0x7a, 0xd6, 0x43, 0x82, 0x22, 0xfd, 0xf3, 0x58, 0x25, 0x60, 0x06, 0x0d, 0xf8, + 0x17, 0xea, 0xa1, 0xff, 0xb1, 0x9f, 0xfd, 0xfe, 0x20, 0x49, 0x29, 0xfe, 0xbf, 0x90, 0xe2, 0x2f, + 0xe6, 0xfe, 0x95, 0x06, 0x3d, 0x6c, 0x36, 0xc2, 0x6a, 0xce, 0x4d, 0x58, 0xa0, 0xbf, 0xf3, 0xc0, + 0xff, 0x20, 0xe8, 0x5f, 0x84, 0xfc, 0x8b, 0x88, 0x7f, 0xc7, 0x29, 0xfe, 0x22, 0xe6, 0x5f, 0x44, + 0xfd, 0x8b, 0xb8, 0x7f, 0x71, 0x07, 0xf8, 0x0f, 0x02, 0xc0, 0xfe, 0xfa, 0xf9, 0x8b, 0x34, 0xff, + 0xb6, 0xff, 0xee, 0xd3, 0x0e, 0xed, 0x0f, 0x3a, 0xfd, 0x45, 0xb7, 0xbf, 0xf8, 0x3f, 0x2f, 0x08, + 0x54, 0xcc, 0x7f, 0x41, 0x10, 0x00, 0xf1, 0x5f, 0xf8, 0xf9, 0x57, 0xfe, 0x67, 0x5c, 0xfe, 0xef, + 0xef, 0xb7, 0xd4, 0x42, 0xfd, 0xbf, 0x7c, 0xe9, 0xfc, 0x57, 0xfe, 0x2b, 0xff, 0x95, 0xff, 0xca, + 0x7f, 0xe5, 0xbf, 0xf2, 0x5f, 0xf9, 0xaf, 0xfc, 0x57, 0xfe, 0x3f, 0x93, 0xff, 0x0b, 0x8c, 0x30, + 0x8e, 0x1d, 0x00, 0x50, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -508,8 +1130,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GA102_ucode_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 12288, // uncompressed data size (bytes) - 7350, // compressed data size (bytes) + 20480, // uncompressed data size (bytes) + 17302, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GA102_ucode_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -521,19 +1143,19 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GA102_ucode_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmBoot_GA102("ucode_desc_dbg") -// FILE NAME: kernel/inc/gsprm/bin/g_gsprm_skbl_dbg_ga102_riscv_desc.bin +// FILE NAME: kernel/inc/gsprm/bin/g_gsprm_skbl_dbg_libos3_ga102_riscv_desc.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 76 -// COMPRESSED SIZE (bytes): 40 +// DATA SIZE (bytes): 84 +// COMPRESSED SIZE (bytes): 41 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GA102_ucode_desc_dbg_data[] = { - 0x63, 0x61, 0x00, 0x02, 0x05, 0x06, 0x86, 0x0d, 0xac, 0x40, 0xac, 0xca, 0xc0, 0x20, 0xc0, 0x80, - 0x05, 0x70, 0x40, 0x31, 0x33, 0x10, 0x73, 0x03, 0x31, 0x2f, 0x03, 0x03, 0x23, 0x16, 0x75, 0x00, - 0x8d, 0x26, 0xa8, 0x4f, 0x4c, 0x00, 0x00, 0x00, + 0x63, 0x65, 0x00, 0x02, 0x07, 0x20, 0x62, 0x03, 0x62, 0x37, 0x06, 0x06, 0x01, 0x06, 0x2c, 0x80, + 0x03, 0x8a, 0x41, 0x92, 0x12, 0x40, 0xac, 0xce, 0xc0, 0xc0, 0x88, 0x4d, 0x5d, 0x00, 0x44, 0x10, + 0x00, 0xf4, 0x78, 0x36, 0x05, 0x54, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -543,8 +1165,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GA102_ucode_desc_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 76, // uncompressed data size (bytes) - 40, // compressed data size (bytes) + 84, // uncompressed data size (bytes) + 41, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GA102_ucode_desc_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -556,475 +1178,1098 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GA102_ucode_desc_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmBoot_GA102("ucode_image_prod") -// FILE NAME: kernel/inc/gsprm/bin/g_gsprm_skbl_prod_ga102_riscv_image.bin +// FILE NAME: kernel/inc/gsprm/bin/g_gsprm_skbl_prod_libos3_ga102_riscv_image.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 12288 -// COMPRESSED SIZE (bytes): 7340 +// DATA SIZE (bytes): 20480 +// COMPRESSED SIZE (bytes): 17301 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GA102_ucode_image_prod_data[] = { - 0xed, 0x94, 0x75, 0x54, 0xd4, 0x5d, 0xb7, 0xc7, 0x27, 0x80, 0x01, 0xa4, 0xbb, 0x5b, 0x1a, 0xa4, - 0xbb, 0x5b, 0x1a, 0x41, 0x42, 0x9a, 0x01, 0x86, 0x52, 0x4a, 0xba, 0x73, 0xe8, 0x8e, 0x91, 0x50, - 0xba, 0x41, 0x1a, 0x29, 0x69, 0x09, 0x01, 0x25, 0xa4, 0xa4, 0x5b, 0x4a, 0x52, 0x42, 0x81, 0xab, - 0x0f, 0x3c, 0xef, 0x7d, 0xff, 0xbc, 0xff, 0x5f, 0xbf, 0x6b, 0xcd, 0xfa, 0xcc, 0xd9, 0x7b, 0xff, - 0xce, 0x3e, 0x7b, 0xaf, 0x7d, 0x8e, 0x12, 0xcd, 0x1b, 0xbf, 0xa8, 0x92, 0x66, 0x03, 0xcd, 0xf8, - 0x8a, 0x67, 0xc8, 0x5b, 0x74, 0xb8, 0xad, 0x3c, 0x82, 0xb9, 0xd4, 0x2b, 0x3c, 0xde, 0xd4, 0xfb, - 0xc2, 0x0b, 0x2d, 0x92, 0x07, 0x6f, 0x2a, 0xf3, 0x59, 0x91, 0xe8, 0x62, 0x9d, 0xf7, 0x7b, 0x6e, - 0x6f, 0xce, 0x21, 0xce, 0x2b, 0xfe, 0xe7, 0xb2, 0xd9, 0x2f, 0xc0, 0x53, 0x59, 0x61, 0x3d, 0x8c, - 0x97, 0x25, 0x0f, 0x20, 0x06, 0x4f, 0xa8, 0xd0, 0x08, 0x65, 0x2a, 0x9d, 0x78, 0xce, 0x15, 0x11, - 0x7b, 0x2a, 0x56, 0xc7, 0x0d, 0x27, 0xc0, 0x6e, 0x75, 0x92, 0x5a, 0x63, 0x1a, 0x59, 0xd5, 0x87, - 0xcd, 0x51, 0xf6, 0x0d, 0x2a, 0x79, 0xc8, 0xdb, 0x39, 0xda, 0x01, 0x18, 0x8a, 0x95, 0x21, 0x2c, - 0x30, 0xb8, 0x4a, 0x85, 0x1f, 0xcb, 0x3b, 0xaf, 0x51, 0xb5, 0x78, 0xa3, 0x97, 0x1a, 0xd0, 0xa3, - 0xcc, 0x89, 0x14, 0x74, 0x0a, 0x9d, 0x12, 0x52, 0xd4, 0xef, 0x92, 0x1f, 0x56, 0xd4, 0x50, 0xd8, - 0x0f, 0xd3, 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0x08, 0xe2, 0x3f, 0xaf, 0xd5, 0x6f, 0xcc, 0x20, 0x01, 0xff, 0x42, + 0x7d, 0xb4, 0x3f, 0xf6, 0xb3, 0xdf, 0x1f, 0x24, 0x2e, 0xc3, 0xff, 0x17, 0x92, 0xff, 0xc5, 0xbc, + 0xbf, 0xd2, 0xa0, 0x8f, 0xc5, 0x46, 0x50, 0xc3, 0xb9, 0x01, 0x03, 0xf8, 0xb7, 0x1f, 0xd8, 0x1f, + 0x04, 0xf9, 0x8b, 0x10, 0x7f, 0x11, 0xe1, 0x6f, 0x3b, 0xf9, 0x5f, 0xc4, 0xf8, 0x8b, 0x28, 0x7f, + 0x11, 0xe7, 0x2f, 0xee, 0x00, 0xfd, 0x41, 0x00, 0xd0, 0xbf, 0x71, 0xfe, 0x22, 0xf5, 0xbf, 0xed, + 0xbf, 0xe3, 0xb4, 0x47, 0xfd, 0x83, 0xce, 0x7f, 0xd1, 0xfd, 0x2f, 0xfe, 0xcf, 0x07, 0x02, 0x05, + 0xe3, 0x5f, 0x10, 0x04, 0x80, 0xf0, 0x2f, 0xfc, 0xfa, 0x2b, 0xff, 0xd3, 0x2e, 0xff, 0xf7, 0xfa, + 0x2d, 0x3f, 0x20, 0xff, 0x5f, 0x7e, 0x74, 0xfe, 0x2b, 0xff, 0x95, 0xff, 0xca, 0x7f, 0xe5, 0xbf, + 0xf2, 0x5f, 0xf9, 0xaf, 0xfc, 0x57, 0xfe, 0x2b, 0xff, 0x9f, 0xc9, 0xff, 0x05, 0xf2, 0x62, 0x1d, + 0x00, 0x00, 0x50, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1034,8 +2279,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GA102_ucode_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 12288, // uncompressed data size (bytes) - 7340, // compressed data size (bytes) + 20480, // uncompressed data size (bytes) + 17301, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GA102_ucode_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1047,19 +2292,19 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GA102_ucode_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmBoot_GA102("ucode_desc_prod") -// FILE NAME: kernel/inc/gsprm/bin/g_gsprm_skbl_prod_ga102_riscv_desc.bin +// FILE NAME: kernel/inc/gsprm/bin/g_gsprm_skbl_prod_libos3_ga102_riscv_desc.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 76 -// COMPRESSED SIZE (bytes): 40 +// DATA SIZE (bytes): 84 +// COMPRESSED SIZE (bytes): 41 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GA102_ucode_desc_prod_data[] = { - 0x63, 0x61, 0x00, 0x02, 0x05, 0x06, 0x86, 0x0d, 0xac, 0x40, 0xac, 0xca, 0xc0, 0x20, 0xc0, 0x80, - 0x05, 0x70, 0x40, 0x31, 0x33, 0x10, 0x73, 0x03, 0x31, 0x2f, 0x03, 0x03, 0x23, 0x16, 0x75, 0x00, - 0x8d, 0x26, 0xa8, 0x4f, 0x4c, 0x00, 0x00, 0x00, + 0x63, 0x65, 0x00, 0x02, 0x07, 0x20, 0x62, 0x03, 0x62, 0x37, 0x06, 0x06, 0x01, 0x06, 0x2c, 0x80, + 0x03, 0x8a, 0x41, 0x92, 0x12, 0x40, 0xac, 0xce, 0xc0, 0xc0, 0x88, 0x4d, 0x5d, 0x00, 0x44, 0x10, + 0x00, 0xf4, 0x78, 0x36, 0x05, 0x54, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1069,8 +2314,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GA102_ucode_desc_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 76, // uncompressed data size (bytes) - 40, // compressed data size (bytes) + 84, // uncompressed data size (bytes) + 41, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GA102_ucode_desc_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c index 286831e2c..2b0813db4 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c @@ -35,7749 +35,7892 @@ // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 126976 -// COMPRESSED SIZE (bytes): 123814 +// COMPRESSED SIZE (bytes): 126108 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GH100_ucode_image_dbg_data[] = { - 0xec, 0x97, 0xc3, 0x92, 0x28, 0x0a, 0x90, 0x6d, 0xcb, 0xb6, 0x6d, 0xd7, 0x29, 0xdb, 0xb6, 0x6d, - 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0x7d, 0xbf, 0xe0, 0x8d, 0x5e, 0x44, - 0x4f, 0x7a, 0x0f, 0x73, 0x96, 0xb1, 0x32, 0x22, 0xd7, 0x06, 0x00, 0xf8, 0xbf, 0xfc, 0x6f, 0x66, - 0x6d, 0x03, 0xc8, 0xfe, 0x61, 0x6d, 0x9c, 0x81, 0x7e, 0xb1, 0xb4, 0xd0, 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0x49, 0x78, 0x6b, 0x60, 0x10, 0x45, + 0x29, 0x54, 0x50, 0x20, 0xa7, 0x00, 0x5e, 0x6c, 0x3b, 0x59, 0x2c, 0xe1, 0xf9, 0x1a, 0x1e, 0x86, + 0x7b, 0x85, 0x1e, 0xb4, 0xf0, 0x33, 0x4d, 0x12, 0xc1, 0x85, 0x01, 0x66, 0xc3, 0x1e, 0xd4, 0x52, + 0x37, 0x83, 0x7a, 0x0b, 0xbc, 0x84, 0x44, 0xcc, 0x5b, 0x61, 0x0b, 0xd3, 0x15, 0xf3, 0xb7, 0x38, + 0x02, 0x09, 0x91, 0x7f, 0x7b, 0xe4, 0xe7, 0xec, 0xd0, 0xc2, 0x04, 0x70, 0xee, 0x7d, 0x04, 0x59, + 0xfe, 0x10, 0xbe, 0x81, 0x7f, 0x19, 0xfe, 0x0d, 0x01, 0x61, 0x53, 0xda, 0x45, 0x14, 0x61, 0x8e, + 0x92, 0xb7, 0xf3, 0x35, 0x61, 0x7e, 0x2c, 0x0c, 0x6d, 0xea, 0xd8, 0xb6, 0x05, 0xe5, 0xd9, 0xa7, + 0x9b, 0xeb, 0x7a, 0xc9, 0x37, 0x51, 0xc3, 0xae, 0xc5, 0x1d, 0xe6, 0xd1, 0xb9, 0xe6, 0x20, 0xed, + 0x5c, 0x0c, 0x4a, 0x21, 0x6b, 0x9c, 0xd6, 0xc0, 0x47, 0x80, 0x4d, 0x50, 0x28, 0xc0, 0xff, 0xf3, + 0x7f, 0x9a, 0xff, 0x01, 0xca, 0xc3, 0xb3, 0xc5, 0x00, 0xf0, 0x01, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -7788,7 +7931,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GH100_ucode_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 126976, // uncompressed data size (bytes) - 123814, // compressed data size (bytes) + 126108, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GH100_ucode_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -7810,8 +7953,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GH100_ucode_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GH100_ucode_desc_dbg_data[] = { - 0x63, 0x65, 0x20, 0x02, 0x70, 0x41, 0x71, 0x25, 0x10, 0x37, 0x03, 0x71, 0x12, 0x23, 0x03, 0x23, - 0x1e, 0x7d, 0x00, 0x9f, 0x32, 0x0c, 0x15, 0x54, 0x00, 0x00, 0x00, + 0x63, 0x65, 0x20, 0x02, 0x70, 0x41, 0x71, 0x25, 0x10, 0x37, 0x03, 0x71, 0x36, 0x23, 0x03, 0x23, + 0x1e, 0x7d, 0x00, 0xc6, 0x9c, 0xd4, 0x6c, 0x54, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -7840,7772 +7983,7916 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GH100_ucode_desc_dbg_storage_pvt; // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 126976 -// COMPRESSED SIZE (bytes): 124189 +// COMPRESSED SIZE (bytes): 126481 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GH100_ucode_image_prod_data[] = { - 0x9c, 0x97, 0xc3, 0x96, 0x28, 0x0a, 0x80, 0x24, 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126976, // uncompressed data size (bytes) - 124189, // compressed data size (bytes) + 126481, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GH100_ucode_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -15638,8 +15925,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GH100_ucode_image_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GH100_ucode_desc_prod_data[] = { - 0x63, 0x65, 0x20, 0x02, 0x70, 0x41, 0x71, 0x25, 0x10, 0x37, 0x03, 0x71, 0x12, 0x23, 0x03, 0x23, - 0x1e, 0x7d, 0x00, 0x9f, 0x32, 0x0c, 0x15, 0x54, 0x00, 0x00, 0x00, + 0x63, 0x65, 0x20, 0x02, 0x70, 0x41, 0x71, 0x25, 0x10, 0x37, 0x03, 0x71, 0x36, 0x23, 0x03, 0x23, + 0x1e, 0x7d, 0x00, 0xc6, 0x9c, 0xd4, 0x6c, 0x54, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c index 83f2ed55c..27f643234 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c @@ -34,7750 +34,7894 @@ // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 124232 -// COMPRESSED SIZE (bytes): 123818 +// DATA SIZE (bytes): 126536 +// COMPRESSED SIZE (bytes): 126124 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_image_data[] = { - 0x8c, 0x97, 0xc3, 0x96, 0x28, 0x0a, 0x90, 0x04, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, - 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xee, 0xdb, 0xb6, 0x6d, 0xdb, 0xf3, 0xce, 0x9c, 0xf9, 0x80, 0xc9, - 0x4d, 0xd5, 0x2e, 0x97, 0x19, 0x01, 0x0c, 0x22, 0x01, 0x00, 0x70, 0x02, 0x08, 0xf0, 0xbf, 0x31, - 0xfa, 0xbf, 0xeb, 0x09, 0x00, 0x00, 0xf2, 0x7f, 0x2f, 0x20, 0x05, 0xc0, 0xff, 0x2b, 0xe9, 0x0a, - 0xac, 0xdf, 0xfd, 0x3d, 0x65, 0x88, 0x6e, 0x7c, 0xf9, 0xd2, 0x72, 0xba, 0xc4, 0x92, 0x3b, 0xa8, - 0xd6, 0xc7, 0xa5, 0x56, 0xe3, 0x61, 0x3a, 0x87, 0xe9, 0x9e, 0xa9, 0xb6, 0xf5, 0x4a, 0x06, 0x6d, - 0x38, 0x3b, 0x7e, 0x3c, 0x2e, 0xc5, 0x37, 0xfb, 0xce, 0x17, 0x17, 0xb3, 0xf2, 0xdd, 0x27, 0xc9, - 0x0d, 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data size (bytes) + 126124, // compressed data size (bytes) kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_image_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -7810,10 +7954,10 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_image_stora // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_hash_data[] = { - 0x01, 0x30, 0x00, 0xcf, 0xff, 0x2b, 0x75, 0x8a, 0x60, 0x87, 0x0c, 0xd1, 0xbb, 0x32, 0x64, 0x8a, - 0xeb, 0x3f, 0xbe, 0xd4, 0x9f, 0xa8, 0xc9, 0x29, 0x0b, 0xdf, 0xb3, 0xc3, 0x97, 0x17, 0x8f, 0x35, - 0x37, 0x4d, 0x72, 0x6f, 0x0e, 0xff, 0x41, 0x07, 0x21, 0x37, 0x13, 0x19, 0x1d, 0x11, 0x09, 0xe4, - 0xda, 0x06, 0xc3, 0x6b, 0x3b, 0x91, 0x02, 0xde, 0xbd, 0x30, 0x00, 0x00, 0x00, + 0x01, 0x30, 0x00, 0xcf, 0xff, 0xc8, 0x81, 0x78, 0x61, 0x05, 0x0d, 0xf6, 0x5c, 0x2a, 0x7d, 0x76, + 0x7e, 0x0e, 0x15, 0xb9, 0xc0, 0x7b, 0x8c, 0x9c, 0xa3, 0xc9, 0x89, 0xd9, 0x93, 0x59, 0xed, 0xa0, + 0xb2, 0xa0, 0xe8, 0xa7, 0xd4, 0x9f, 0x0d, 0x42, 0x5c, 0x9e, 0x2b, 0x84, 0xba, 0x1c, 0x58, 0x6b, + 0x24, 0xd5, 0x18, 0x93, 0xbc, 0x3f, 0xe7, 0xe2, 0x4d, 0x30, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -7846,31 +7990,31 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_hash_storag // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_sig_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x5e, 0xf8, 0x92, 0xc4, 0x6a, 0x05, 0xe2, 0x40, 0xce, 0x41, 0x1e, - 0x9c, 0x35, 0xcd, 0x6b, 0xa0, 0xe1, 0x8c, 0x7c, 0xb9, 0x78, 0xbd, 0x3d, 0x47, 0x32, 0x1d, 0xa0, - 0x2a, 0xa7, 0x32, 0x0a, 0x69, 0x69, 0x91, 0xd4, 0x8c, 0xa6, 0xb3, 0x8f, 0x93, 0xcf, 0xd4, 0x54, - 0x23, 0x0a, 0xbe, 0xee, 0xa2, 0x61, 0x30, 0x2d, 0xc8, 0x1f, 0xf4, 0x6a, 0x39, 0xa1, 0xbe, 0x06, - 0x34, 0xeb, 0x64, 0x67, 0x7b, 0xe8, 0x04, 0xdd, 0x39, 0x13, 0xcb, 0xb9, 0x56, 0x6a, 0xaa, 0xd5, - 0xfc, 0xb7, 0x96, 0xf7, 0xbd, 0xf0, 0xd1, 0x4a, 0x5c, 0x0c, 0x0b, 0x7e, 0x77, 0x5c, 0x10, 0xc3, - 0x13, 0x85, 0x8f, 0x29, 0x77, 0x6c, 0xc3, 0x1d, 0x19, 0x14, 0xa6, 0x7b, 0x02, 0x29, 0xde, 0x55, - 0x92, 0x8d, 0x7e, 0x73, 0x63, 0x8f, 0x41, 0xc8, 0x9a, 0x36, 0xe0, 0x9d, 0xed, 0x5e, 0x47, 0x09, - 0xdc, 0x3e, 0x51, 0xad, 0xc0, 0x07, 0xef, 0x93, 0x16, 0xe9, 0x06, 0x1e, 0xac, 0xc7, 0xa9, 0xdb, - 0x08, 0xdd, 0x76, 0x7f, 0xb7, 0xdf, 0xc1, 0xc6, 0x19, 0xdf, 0x65, 0x0d, 0x9c, 0x38, 0x1e, 0xb7, - 0x76, 0xaa, 0x09, 0xbf, 0x32, 0xc5, 0x9b, 0xf1, 0x11, 0x22, 0x06, 0x4b, 0xdc, 0x5d, 0x02, 0x4a, - 0xb9, 0xb0, 0x7f, 0x88, 0x3d, 0x9a, 0xf8, 0x2c, 0xf8, 0xcc, 0xfd, 0x20, 0x95, 0x52, 0x09, 0x35, - 0xf5, 0x79, 0xcb, 0x2d, 0x1c, 0xd0, 0xa7, 0xa2, 0x91, 0x15, 0xeb, 0xbc, 0x9f, 0x9b, 0xc5, 0x5c, - 0x34, 0xc1, 0xa8, 0x75, 0x28, 0xb8, 0x71, 0x3d, 0x83, 0x74, 0x1b, 0x15, 0x3b, 0xce, 0x67, 0x45, - 0x0e, 0x43, 0xc0, 0xf0, 0xa8, 0x08, 0x7b, 0xa3, 0x7c, 0x1b, 0xc0, 0x18, 0xb7, 0xe3, 0xe4, 0xac, - 0x42, 0x9d, 0x23, 0x42, 0x5d, 0x8d, 0x9f, 0x0a, 0x10, 0x91, 0x83, 0x50, 0x5f, 0xf9, 0x05, 0x4d, - 0x6c, 0x4b, 0x7c, 0x3d, 0x40, 0x59, 0x04, 0x64, 0xca, 0x4f, 0x7e, 0xbc, 0xb6, 0x5a, 0xe9, 0xb0, - 0xbe, 0x8d, 0xf0, 0x2f, 0x59, 0xf1, 0xce, 0x59, 0x6c, 0xe8, 0x74, 0x3b, 0x52, 0xfa, 0x99, 0xb6, - 0xec, 0x83, 0x01, 0x3b, 0xaa, 0x98, 0x29, 0xe0, 0x37, 0x88, 0x19, 0xed, 0x92, 0xd4, 0xff, 0x86, - 0xaa, 0xa8, 0xf1, 0x3a, 0x24, 0x3e, 0x4e, 0x0b, 0xd7, 0xc5, 0xab, 0x0c, 0x35, 0xf7, 0x12, 0x85, - 0x18, 0xfd, 0x63, 0xb3, 0xa3, 0xe2, 0x00, 0xfe, 0xe9, 0xd3, 0x13, 0xe9, 0xff, 0x3e, 0xb0, 0xd8, - 0x2a, 0x32, 0xa9, 0x31, 0x7c, 0x89, 0x7a, 0xac, 0xf8, 0xac, 0xbe, 0x0c, 0xab, 0xec, 0x59, 0x70, - 0x67, 0x8d, 0xf6, 0x2c, 0x4e, 0x0c, 0x8d, 0x13, 0x19, 0xa9, 0xd0, 0xe4, 0xff, 0x2f, 0xb1, 0xbf, - 0x6e, 0xd6, 0xb2, 0x52, 0x9f, 0x5f, 0x3c, 0x2e, 0xd6, 0x11, 0xb0, 0x81, 0x1a, 0x5f, 0xd3, 0x11, - 0x2a, 0x82, 0x63, 0xe1, 0x16, 0xb3, 0x6f, 0xc1, 0xc9, 0x80, 0x01, 0x00, 0x00, + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x4d, 0x2e, 0xd9, 0x9d, 0xe6, 0x9c, 0x0e, 0xc3, 0xf6, 0x69, 0x89, + 0xb2, 0xd2, 0x7d, 0x0d, 0x86, 0x10, 0xfc, 0x28, 0x9f, 0x7b, 0x75, 0x88, 0x13, 0x67, 0xd0, 0xf6, + 0xed, 0x97, 0x6f, 0xf1, 0xd2, 0xf8, 0x39, 0xeb, 0xf1, 0xf1, 0xab, 0x6a, 0xe7, 0x8c, 0x9a, 0xa9, + 0x07, 0xbc, 0x31, 0xca, 0x17, 0xa4, 0x0f, 0x03, 0x20, 0xab, 0x72, 0xec, 0xff, 0x8a, 0x31, 0x52, + 0x90, 0x21, 0xe4, 0x35, 0x3f, 0x42, 0xbf, 0x36, 0x19, 0xb6, 0x90, 0xca, 0x89, 0xd5, 0x98, 0x7b, + 0x19, 0xcf, 0xd2, 0x48, 0x30, 0x70, 0xc4, 0xe1, 0x04, 0xe9, 0xa0, 0x3a, 0xb1, 0x83, 0xbe, 0x7f, + 0x4f, 0x00, 0xa2, 0x62, 0xf2, 0xd6, 0x2b, 0x89, 0xb8, 0x31, 0xd1, 0x1e, 0x54, 0xf5, 0xab, 0x5f, + 0xac, 0x86, 0xd1, 0x36, 0x85, 0xf7, 0x8f, 0xee, 0x8f, 0x57, 0xb0, 0x86, 0x96, 0x9f, 0x2c, 0x3e, + 0xac, 0xb7, 0xa0, 0x2e, 0xba, 0x83, 0x7c, 0x74, 0xa9, 0xfe, 0xca, 0xb4, 0xc2, 0xea, 0xfe, 0x39, + 0xe3, 0x33, 0x35, 0xaa, 0xb5, 0xf0, 0x03, 0x5e, 0x81, 0x21, 0x04, 0x17, 0x23, 0xef, 0xc7, 0xa9, + 0x3a, 0x42, 0xf8, 0xe2, 0xac, 0x07, 0xfb, 0x91, 0xff, 0xc8, 0x37, 0xfe, 0x21, 0x60, 0x71, 0x77, + 0x2e, 0x79, 0x95, 0xcd, 0xf1, 0x52, 0x1b, 0x4c, 0x7e, 0x95, 0x15, 0x2c, 0x04, 0xdb, 0xc7, 0xe3, + 0x95, 0x32, 0xb5, 0x78, 0x99, 0xae, 0x88, 0x43, 0x7e, 0x06, 0xe5, 0x86, 0x5c, 0x6e, 0x7e, 0x45, + 0xf8, 0x42, 0x49, 0x1c, 0x5a, 0xaa, 0x91, 0xa5, 0x1c, 0xc0, 0xad, 0x85, 0x48, 0x11, 0x4d, 0x42, + 0x50, 0x27, 0x31, 0xc6, 0x10, 0xec, 0x60, 0xd7, 0x7b, 0x47, 0xba, 0x6c, 0x86, 0xae, 0x94, 0xeb, + 0x31, 0x9c, 0x80, 0xca, 0xd7, 0xcf, 0x5e, 0x49, 0x7c, 0x6f, 0x28, 0xb8, 0x8a, 0x70, 0xcd, 0x0d, + 0x06, 0x05, 0x34, 0xf7, 0xa1, 0xa6, 0x30, 0x34, 0x90, 0xaf, 0xcd, 0x04, 0xfd, 0xba, 0xc0, 0x96, + 0x04, 0x0f, 0xa2, 0x27, 0xba, 0xa3, 0xb6, 0x3a, 0x1c, 0x9a, 0xb7, 0x9b, 0x83, 0x39, 0xe6, 0x97, + 0x8a, 0x0c, 0xce, 0x8d, 0xc1, 0x42, 0x15, 0xa3, 0xd9, 0x33, 0x31, 0x16, 0xeb, 0xe3, 0xd0, 0xfb, + 0x00, 0x7c, 0xa3, 0x73, 0x19, 0x02, 0x05, 0xb6, 0xed, 0xd4, 0xd5, 0x6c, 0x3a, 0xbc, 0x39, 0xa9, + 0xd6, 0x5d, 0xd1, 0x5c, 0x54, 0xde, 0x4e, 0xe8, 0x5f, 0xf6, 0xe7, 0xac, 0x94, 0x22, 0x21, 0xff, + 0xce, 0x22, 0xfb, 0x60, 0x08, 0x6a, 0x4d, 0xdf, 0xf3, 0x0a, 0x51, 0xfe, 0x02, 0x7b, 0x51, 0x13, + 0x14, 0xec, 0xea, 0x95, 0xa0, 0x6e, 0x24, 0x5e, 0x31, 0x1a, 0x85, 0xd9, 0x80, 0x4a, 0x9d, 0xca, + 0x1b, 0x5e, 0xa5, 0xfd, 0x9a, 0xf5, 0x51, 0x2d, 0x37, 0xfa, 0xdd, 0xce, 0xfa, 0x2c, 0xb3, 0x21, + 0xcb, 0x31, 0x93, 0x33, 0x97, 0xfa, 0x1d, 0xe8, 0x50, 0x80, 0x01, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c index a47fe4e80..3650c3f8a 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c @@ -34,7774 +34,7918 @@ // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 124232 -// COMPRESSED SIZE (bytes): 124201 +// DATA SIZE (bytes): 126536 +// COMPRESSED SIZE (bytes): 126502 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_image_data[] = { - 0x00, 0x4c, 0x80, 0xb3, 0x7f, 0x03, 0x04, 0x48, 0x00, 0x00, 0xe5, 0x01, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x62, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79, 0x00, 0x00, 0x04, 0x01, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa4, 0xed, 0x6f, - 0x66, 0x9c, 0x74, 0x5c, 0xac, 0xbb, 0xb9, 0xfb, 0x0a, 0x46, 0xe2, 0x3e, 0x88, 0x73, 0xa6, 0xc8, - 0x6a, 0x11, 0x66, 0x1f, 0xe5, 0x88, 0x0b, 0x40, 0x92, 0x29, 0x92, 0x0e, 0x18, 0xee, 0xc3, 0x8c, - 0xc6, 0xf8, 0xc6, 0xbd, 0xa3, 0x41, 0x72, 0x34, 0x62, 0x93, 0xc9, 0x40, 0xea, 0x0d, 0x03, 0x1a, - 0x04, 0x73, 0x3b, 0x68, 0x17, 0x33, 0x67, 0x75, 0xe6, 0xe5, 0x13, 0xc5, 0x7f, 0x55, 0x07, 0x08, - 0x5f, 0x38, 0x64, 0xd9, 0x77, 0xca, 0x66, 0xb3, 0x22, 0xd8, 0xdd, 0xd6, 0x6c, 0x03, 0x53, 0xe3, - 0x55, 0xf6, 0x0a, 0x07, 0xe3, 0xba, 0x03, 0x8e, 0x82, 0xf4, 0x7e, 0x9e, 0x0e, 0xa7, 0xd7, 0x51, - 0x74, 0x30, 0xea, 0x85, 0xd1, 0x7d, 0x24, 0xa9, 0x25, 0x96, 0x74, 0x91, 0x11, 0x91, 0x7c, 0xa2, - 0xe7, 0xf2, 0xa8, 0x67, 0xed, 0x7a, 0x4b, 0x18, 0xc7, 0x91, 0xba, 0xd1, 0x40, 0xac, 0xf3, 0xce, - 0xab, 0xa8, 0x7c, 0xec, 0x2f, 0x7a, 0xd5, 0xc6, 0x2d, 0x90, 0x0e, 0x35, 0x26, 0x58, 0xbf, 0x1d, - 0x2e, 0x62, 0x56, 0xf2, 0xa6, 0x43, 0xb6, 0xc6, 0xf5, 0x83, 0xe0, 0x24, 0x6e, 0xdb, 0x20, 0xc0, - 0xb3, 0xd0, 0xf7, 0x25, 0x2e, 0xdd, 0x0d, 0x8b, 0x15, 0x0f, 0xb1, 0x8a, 0x20, 0x5f, 0xc4, 0xd0, - 0x4a, 0x38, 0xed, 0x69, 0x29, 0xda, 0xb4, 0xfc, 0xd4, 0x55, 0xbb, 0x9c, 0x40, 0xf6, 0xb5, 0x27, - 0x29, 0x61, 0x6b, 0x19, 0xcc, 0xf6, 0x3f, 0x76, 0xb0, 0xdf, 0x3a, 0xf9, 0x56, 0x73, 0xd5, 0x7a, - 0x74, 0xe1, 0x12, 0x3f, 0xb8, 0x59, 0xb2, 0xbd, 0xf1, 0xd7, 0x6e, 0xa1, 0x51, 0x1d, 0x89, 0x67, - 0x03, 0x9b, 0x85, 0xc0, 0x4d, 0xec, 0x43, 0x8f, 0x24, 0xfb, 0xcf, 0x57, 0xe9, 0xa5, 0x73, 0xfa, - 0x6c, 0xa5, 0xc7, 0x58, 0xc8, 0xe4, 0x0f, 0xb5, 0x53, 0x13, 0xa1, 0x98, 0xd2, 0x3b, 0x90, 0xf7, - 0xce, 0xee, 0x10, 0xef, 0x30, 0xb5, 0xf4, 0xac, 0x5d, 0x99, 0x1d, 0xbb, 0x0d, 0x9c, 0x42, 0x63, - 0x64, 0x92, 0x23, 0x2e, 0x5c, 0x30, 0xbd, 0xb9, 0x90, 0xe4, 0x39, 0x90, 0x74, 0x0f, 0x31, 0xf0, - 0x7a, 0x3f, 0xf0, 0x79, 0x80, 0x37, 0x59, 0x1c, 0x93, 0xc6, 0x92, 0x96, 0xa0, 0x90, 0x0b, 0x5a, - 0x51, 0x3d, 0x71, 0xe9, 0xa4, 0x62, 0x1f, 0x33, 0xb3, 0x08, 0xa5, 0x8d, 0x91, 0x5f, 0xb8, 0xc5, - 0x0a, 0x67, 0x60, 0x0f, 0x71, 0x8d, 0xb7, 0x7b, 0xfc, 0x78, 0xc4, 0x7f, 0x4e, 0x5d, 0x9d, 0x1f, - 0xb0, 0x99, 0xfb, 0xf6, 0xcc, 0x28, 0xed, 0x5f, 0x90, 0xc3, 0x2b, 0x9f, 0xeb, 0xc3, 0x80, 0x9a, - 0x81, 0x16, 0xd6, 0x1f, 0xa9, 0x03, 0xb1, 0xd9, 0xf6, 0x29, 0x60, 0x27, 0xc7, 0x8c, 0xe6, 0x7e, - 0x44, 0xd7, 0x8f, 0xce, 0x79, 0x35, 0x12, 0xc3, 0x7f, 0xa9, 0x69, 0x30, 0x9e, 0xd7, 0x2e, 0x6e, - 0x21, 0x69, 0x02, 0xc2, 0xc1, 0x60, 0xb9, 0xea, 0xdf, 0x78, 0x39, 0x53, 0xf2, 0xcd, 0x19, 0x46, - 0x5c, 0xa7, 0x27, 0xc5, 0xb6, 0xd2, 0x5e, 0x27, 0x32, 0x45, 0xf7, 0x17, 0xf2, 0x5a, 0xdd, 0x1d, - 0xa8, 0x16, 0xd0, 0x09, 0x0a, 0x03, 0x6e, 0x41, 0xe1, 0x85, 0x7c, 0xaa, 0xfe, 0xcd, 0xf8, 0xf5, - 0xfa, 0xeb, 0xfa, 0xcf, 0x8d, 0x6c, 0x2f, 0x94, 0x2f, 0xb9, 0x0b, 0x83, 0xa0, 0xf9, 0xc4, 0x04, - 0xdc, 0xb6, 0x22, 0x88, 0x02, 0xd1, 0x3a, 0xae, 0xe4, 0xb5, 0xf3, 0x1c, 0x2f, 0xa0, 0x72, 0xcb, - 0x2b, 0x5e, 0xac, 0x62, 0x5e, 0xba, 0x63, 0xae, 0xf1, 0xac, 0xad, 0x28, 0x13, 0x1b, 0xe5, 0xed, - 0x3f, 0x31, 0x03, 0xbf, 0xb1, 0xcd, 0x52, 0xbe, 0x98, 0x17, 0x18, 0xa5, 0xd1, 0x39, 0x6e, 0x70, - 0xb8, 0x7d, 0xf0, 0x0c, 0x1d, 0x5d, 0x2c, 0x7e, 0x03, 0xe0, 0x6f, 0x78, 0xaf, 0xc1, 0x68, 0x6e, - 0xb2, 0x80, 0xc3, 0x81, 0xa6, 0x73, 0x91, 0xa4, 0xef, 0x57, 0xf5, 0x23, 0x94, 0x09, 0x4d, 0x3c, - 0xfb, 0xc6, 0xed, 0xe2, 0x4d, 0xb7, 0x90, 0x50, 0xbc, 0x21, 0x37, 0x7c, 0x50, 0x4d, 0x79, 0xdc, - 0x6c, 0xe2, 0xd3, 0x0a, 0x7e, 0x6b, 0x26, 0x3c, 0xe4, 0x8d, 0xcc, 0xd8, 0x93, 0x50, 0x40, 0x16, - 0x2c, 0x88, 0x3a, 0x74, 0x85, 0xb6, 0x32, 0xd1, 0x64, 0x76, 0xe0, 0x7e, 0x31, 0x3c, 0xb0, 0xbf, - 0x26, 0xed, 0xae, 0x1a, 0xb5, 0x90, 0x5c, 0x3b, 0xed, 0x1f, 0x9b, 0x2e, 0x8b, 0xd7, 0xe1, 0x39, - 0x8f, 0xcd, 0xd5, 0x5e, 0x97, 0x47, 0x75, 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0x32, 0x2e, 0xb0, 0x6d, 0xe7, 0x33, 0xa8, 0xb5, 0x42, 0xc1, 0x9d, 0x82, 0xd9, 0xbc, + 0xef, 0x3b, 0xe1, 0x6b, 0x94, 0x27, 0x7d, 0x12, 0x5e, 0x4a, 0xbe, 0xaa, 0x74, 0x11, 0x5d, 0x36, + 0x7f, 0x8a, 0xcc, 0x78, 0xd3, 0x09, 0x79, 0x7a, 0x05, 0xb1, 0xdf, 0x7e, 0x1f, 0x45, 0x41, 0x75, + 0xf9, 0xfc, 0xc0, 0xce, 0xd2, 0x1d, 0x33, 0x80, 0x7d, 0xcc, 0x7c, 0x89, 0xeb, 0x7f, 0x5f, 0xca, + 0x9c, 0x5d, 0x3a, 0x49, 0xf4, 0x61, 0xb5, 0xd3, 0x1b, 0x1d, 0x98, 0xc9, 0x0b, 0x1c, 0xdd, 0x1d, + 0x97, 0x0f, 0x84, 0x49, 0x2f, 0x0c, 0xe9, 0x0e, 0x25, 0x18, 0xa7, 0x71, 0x07, 0xdf, 0xfb, 0x24, + 0xaf, 0x9b, 0x1c, 0x50, 0xba, 0x8c, 0xdd, 0x34, 0x89, 0x2f, 0x83, 0x0a, 0x74, 0x01, 0xf0, 0x54, + 0xb4, 0x88, 0x70, 0xc4, 0xb2, 0x14, 0xbb, 0xe0, 0x9d, 0x37, 0x6d, 0x7d, 0xd6, 0x75, 0x92, 0xba, + 0x7b, 0x5f, 0x1e, 0x46, 0x4b, 0xe2, 0x23, 0xb4, 0xdb, 0x52, 0x54, 0x57, 0x10, 0x63, 0xde, 0x44, + 0xe3, 0x30, 0xd9, 0x87, 0x48, 0xf7, 0xaf, 0x3e, 0x27, 0x74, 0x6f, 0xba, 0x59, 0x8f, 0xbd, 0xf9, + 0x41, 0x83, 0x90, 0xb8, 0x07, 0x6f, 0xf0, 0xda, 0xbd, 0x74, 0x4e, 0x51, 0xbb, 0x99, 0xea, 0x33, + 0xba, 0x4d, 0xe7, 0x0a, 0x12, 0x26, 0x6f, 0xbd, 0x6b, 0xb7, 0x1c, 0x59, 0x74, 0xb0, 0x00, 0x02, + 0x1f, 0xb0, 0x43, 0xdb, 0x5d, 0x07, 0x8e, 0xb4, 0x5e, 0x48, 0x23, 0x01, 0x88, 0xaf, 0xeb, 0x76, + 0x8c, 0x1b, 0x9c, 0xc3, 0x94, 0x59, 0x20, 0xcf, 0x12, 0xc7, 0xf9, 0xb8, 0x8c, 0xc3, 0x58, 0xe4, + 0x76, 0x64, 0x02, 0x67, 0x9c, 0x62, 0xf7, 0xd4, 0x8e, 0xb5, 0xad, 0x25, 0xd1, 0xff, 0x89, 0x76, + 0x46, 0x60, 0xcf, 0xae, 0xeb, 0x3f, 0xaa, 0x3b, 0xa8, 0xd7, 0xb2, 0xc1, 0x06, 0x12, 0x5e, 0x43, + 0xef, 0x27, 0x72, 0x50, 0x43, 0x4f, 0xa2, 0xf2, 0x61, 0x80, 0x35, 0x81, 0xe3, 0xbd, 0x04, 0xf6, + 0x33, 0x59, 0x87, 0x95, 0xe0, 0xa3, 0xdc, 0x9a, 0x97, 0x48, 0xf3, 0xf4, 0xb4, 0xd7, 0xfb, 0x86, + 0x86, 0x04, 0x91, 0xc2, 0x6c, 0x23, 0x2a, 0x43, 0xb6, 0x70, 0x94, 0x7d, 0xfe, 0x0f, 0xd3, 0x3f, + 0xc0, 0x28, 0x48, 0xee, 0x01, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -7811,8 +7955,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_image_storag #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 124232, // uncompressed data size (bytes) - 124201, // compressed data size (bytes) + 126536, // uncompressed data size (bytes) + 126502, // compressed data size (bytes) kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_image_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -7834,10 +7978,10 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_image_storag // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_hash_data[] = { - 0x01, 0x30, 0x00, 0xcf, 0xff, 0x3a, 0x5c, 0x79, 0x51, 0x33, 0xff, 0xd2, 0xd0, 0xdf, 0xa9, 0x6f, - 0x62, 0x3e, 0xd3, 0xa9, 0x0c, 0x87, 0x97, 0x2e, 0x70, 0x62, 0x43, 0xb1, 0x89, 0xf5, 0x67, 0x58, - 0xaa, 0xa9, 0xc4, 0xd5, 0x68, 0x03, 0x39, 0xaa, 0xfb, 0x3c, 0xeb, 0x11, 0x81, 0xc6, 0xc8, 0xc7, - 0x34, 0xc4, 0x85, 0x59, 0xf0, 0x0f, 0xcb, 0x74, 0x60, 0x30, 0x00, 0x00, 0x00, + 0x01, 0x30, 0x00, 0xcf, 0xff, 0x95, 0xd7, 0x99, 0x29, 0xc6, 0xba, 0x9e, 0xf6, 0x5a, 0xf9, 0x11, + 0xd5, 0x07, 0x19, 0xae, 0x2c, 0xf5, 0x75, 0xae, 0xff, 0x71, 0xc1, 0x4f, 0x9e, 0xba, 0x3a, 0x0b, + 0xa5, 0xf0, 0x67, 0xf7, 0x9d, 0x28, 0x17, 0x6e, 0xea, 0xd6, 0x47, 0xaf, 0xd1, 0xe3, 0xa5, 0x79, + 0x48, 0x74, 0x6b, 0x39, 0xfe, 0x0b, 0xe4, 0x21, 0xf3, 0x30, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -7870,31 +8014,31 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_hash_storage // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_sig_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x2b, 0xe3, 0x35, 0xee, 0x18, 0xdf, 0xca, 0x3f, 0x66, 0x20, 0xb4, - 0x53, 0x84, 0x89, 0xed, 0xc2, 0x25, 0x72, 0x05, 0xb2, 0xd8, 0x19, 0x8e, 0xab, 0xe0, 0x90, 0xc8, - 0x7c, 0x2e, 0x9c, 0xbc, 0x6a, 0x37, 0x8b, 0xdc, 0x43, 0x37, 0xaf, 0x0c, 0x43, 0xc3, 0xd2, 0xbf, - 0xb2, 0xc7, 0xef, 0xea, 0x90, 0x17, 0x89, 0x2d, 0x3f, 0xca, 0x9f, 0xb8, 0xe8, 0xe7, 0xad, 0xf9, - 0x50, 0xe9, 0xa3, 0xc9, 0x92, 0x94, 0xd8, 0x2b, 0x21, 0x75, 0x67, 0xad, 0x34, 0xae, 0x5b, 0xbf, - 0x91, 0x5d, 0x15, 0x96, 0x15, 0x45, 0xf8, 0xfd, 0xf7, 0x2f, 0xcd, 0x0e, 0xb4, 0x18, 0x46, 0x82, - 0x08, 0x96, 0xa2, 0x6a, 0x2f, 0x1a, 0x6e, 0x6a, 0xfa, 0xcb, 0x56, 0x90, 0x29, 0x68, 0x9a, 0xff, - 0xec, 0x05, 0x60, 0x12, 0x6d, 0x0c, 0x0e, 0x87, 0xff, 0xb0, 0x3f, 0xd6, 0xdf, 0xaa, 0xf9, 0x5f, - 0x63, 0x32, 0xef, 0x76, 0x90, 0x18, 0x0a, 0xac, 0x36, 0x2a, 0xc9, 0xe1, 0x5a, 0x52, 0xe6, 0x00, - 0x2a, 0x41, 0x07, 0x9d, 0x7d, 0x62, 0x28, 0x90, 0x4f, 0x4a, 0x36, 0x8d, 0xec, 0xa4, 0x30, 0xeb, - 0x1f, 0x26, 0xe6, 0x28, 0xa7, 0x1d, 0xa9, 0x72, 0x30, 0xa9, 0x24, 0x05, 0x7c, 0x03, 0xd2, 0x6d, - 0x34, 0x1f, 0x4d, 0x1c, 0xdb, 0xb8, 0xd4, 0x61, 0x72, 0x05, 0xc9, 0xa5, 0xc2, 0xed, 0xda, 0xdc, - 0x37, 0xd1, 0x2f, 0x14, 0x34, 0xe9, 0x2a, 0xb5, 0xc1, 0x2d, 0xb4, 0x3d, 0x6e, 0xbf, 0x88, 0x8b, - 0x1a, 0x6f, 0xb2, 0xd2, 0xd7, 0x5d, 0xe3, 0x29, 0x32, 0xd8, 0xed, 0x38, 0x67, 0x2c, 0x58, 0x28, - 0x4f, 0x8a, 0x29, 0x82, 0xfb, 0x08, 0x7b, 0x4b, 0xa9, 0x45, 0xb8, 0x44, 0x00, 0x3a, 0x0e, 0xb2, - 0xc4, 0xca, 0x23, 0xea, 0x40, 0x8e, 0xe9, 0xb4, 0x28, 0xfb, 0x40, 0x91, 0x40, 0x51, 0xa2, 0xdd, - 0x16, 0xfb, 0x26, 0xd4, 0x92, 0x57, 0x17, 0xe9, 0xaf, 0x66, 0xc9, 0xfe, 0xd5, 0xc9, 0x7c, 0xf5, - 0x66, 0x4c, 0x54, 0x6f, 0x9d, 0x0b, 0x64, 0x55, 0x5c, 0x20, 0xc7, 0x83, 0x77, 0xd4, 0x01, 0x70, - 0x1c, 0xe1, 0x0b, 0xe2, 0xd8, 0x23, 0xfa, 0x31, 0x5a, 0xd1, 0xa5, 0x67, 0x50, 0x96, 0x8f, 0x02, - 0x83, 0xa8, 0x07, 0x8c, 0xef, 0xba, 0x3e, 0x4d, 0x88, 0xe4, 0x54, 0xeb, 0x0c, 0xca, 0x31, 0x8d, - 0xfd, 0x26, 0xcd, 0x31, 0x02, 0xbc, 0x81, 0x6b, 0x51, 0x21, 0x60, 0x11, 0x69, 0xeb, 0x35, 0x9f, - 0xa1, 0x1d, 0x8c, 0x10, 0xfa, 0xb8, 0xd6, 0x1f, 0xe8, 0x41, 0x32, 0xdc, 0x9e, 0xfb, 0x9e, 0xc4, - 0x3b, 0x80, 0xd9, 0x11, 0x71, 0x98, 0x39, 0x6c, 0xbb, 0x35, 0xa2, 0xbe, 0xab, 0xef, 0x57, 0xf8, - 0xd0, 0x1d, 0x47, 0x62, 0xdc, 0x0b, 0x54, 0xdd, 0x50, 0x12, 0x1a, 0x1f, 0x01, 0xba, 0x1d, 0xf0, - 0x30, 0x62, 0xd3, 0xa4, 0xd9, 0xf5, 0xdd, 0xce, 0x1d, 0x80, 0x01, 0x00, 0x00, + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x8b, 0xe3, 0x0f, 0xdd, 0x2d, 0x07, 0xaf, 0x06, 0x29, 0x5a, 0xee, + 0xc8, 0x8c, 0x39, 0x04, 0x6c, 0xf7, 0x0f, 0xcf, 0x4f, 0xdd, 0x37, 0x4c, 0xb7, 0x07, 0x0b, 0xfa, + 0x21, 0xaa, 0x22, 0x7b, 0xbe, 0x74, 0xca, 0xf2, 0x15, 0x16, 0x67, 0x23, 0x05, 0xed, 0x37, 0xd5, + 0xd5, 0x69, 0x78, 0xf8, 0xcb, 0x90, 0x39, 0x4d, 0x8b, 0x51, 0x00, 0x32, 0x6c, 0x8e, 0x88, 0xa4, + 0x94, 0xcc, 0xdb, 0x7d, 0xf0, 0x9e, 0x34, 0x91, 0x7e, 0xcc, 0x8f, 0xd0, 0xca, 0x74, 0xf0, 0x80, + 0x25, 0x4b, 0x6b, 0x3b, 0x2c, 0x07, 0xb6, 0x37, 0x43, 0xe6, 0x94, 0x79, 0x14, 0x56, 0x9a, 0xd0, + 0xd7, 0xe2, 0xbb, 0xc0, 0x40, 0xb2, 0x17, 0x4f, 0x62, 0x9d, 0x57, 0x4a, 0x8a, 0x0f, 0xd5, 0xdb, + 0x1b, 0xad, 0x28, 0x33, 0x47, 0x4a, 0x99, 0x18, 0x54, 0x85, 0x01, 0xeb, 0x62, 0x28, 0x0d, 0xf2, + 0x18, 0x87, 0x26, 0x4b, 0xd7, 0x8c, 0xe0, 0x6e, 0x98, 0x05, 0x30, 0x77, 0xc7, 0x43, 0x40, 0x6e, + 0x78, 0x97, 0x4c, 0x52, 0x86, 0xc9, 0xf3, 0x02, 0xc8, 0x9d, 0x3a, 0xc2, 0x09, 0x14, 0x0b, 0xde, + 0xb7, 0x1e, 0xee, 0xa7, 0xdd, 0xca, 0x60, 0x97, 0x5c, 0x42, 0x9e, 0x5c, 0x09, 0x12, 0x96, 0xba, + 0x49, 0x5e, 0xad, 0x2b, 0x69, 0xe2, 0xba, 0x60, 0x22, 0x31, 0x96, 0x2b, 0xf4, 0x09, 0xa4, 0xce, + 0x1b, 0x6e, 0x4a, 0x09, 0xb9, 0xbb, 0x36, 0xd6, 0x52, 0xb6, 0x08, 0xbd, 0x49, 0xc2, 0xba, 0xf5, + 0xe1, 0x62, 0x5d, 0x34, 0xf1, 0x72, 0x77, 0x90, 0xa1, 0x25, 0x79, 0x23, 0x24, 0x5a, 0xf6, 0xd0, + 0x37, 0xad, 0x58, 0x3e, 0x71, 0x22, 0x62, 0xa3, 0x91, 0x30, 0x6f, 0x9d, 0x7a, 0x5c, 0x06, 0x49, + 0x87, 0xf2, 0xdb, 0x22, 0x74, 0xf9, 0x50, 0xbc, 0x40, 0x8d, 0x6c, 0xd6, 0x02, 0x08, 0xa8, 0xb8, + 0xc8, 0xea, 0xd2, 0x99, 0x0c, 0x9b, 0x27, 0x09, 0xe7, 0x42, 0xe6, 0x39, 0x1c, 0xa7, 0x0c, 0xa9, + 0xfd, 0x4c, 0xfb, 0xbd, 0xd0, 0x3e, 0x64, 0xe8, 0x39, 0x4f, 0xcc, 0x90, 0x56, 0x80, 0xcf, 0x10, + 0x09, 0xc7, 0x12, 0xb0, 0xd6, 0xec, 0xee, 0x26, 0xa8, 0x86, 0x9e, 0x1f, 0x48, 0xc4, 0x29, 0x94, + 0xf3, 0x92, 0x5c, 0xd7, 0xc0, 0xea, 0x88, 0x67, 0x76, 0x14, 0x8f, 0xb1, 0x36, 0x47, 0x5b, 0x1d, + 0xb0, 0x7f, 0xcf, 0x86, 0x82, 0x00, 0xf5, 0xb5, 0xff, 0x4c, 0x73, 0xf7, 0x64, 0x25, 0x22, 0x97, + 0x88, 0x4b, 0x7d, 0x2d, 0x84, 0x95, 0xf6, 0xad, 0x22, 0x1b, 0x9a, 0xfa, 0xf1, 0x58, 0xcd, 0xa4, + 0x75, 0xf9, 0xea, 0x85, 0x74, 0x86, 0x9e, 0x94, 0x1d, 0xc1, 0xd6, 0xc7, 0xd1, 0xc9, 0x05, 0xe4, + 0x36, 0x77, 0x89, 0xe8, 0x27, 0x98, 0x83, 0xf9, 0x22, 0x37, 0x64, 0x3e, 0x0f, 0x5b, 0x4c, 0x22, + 0xcb, 0x76, 0x8c, 0x26, 0xba, 0x6d, 0x6e, 0xda, 0x49, 0x80, 0x01, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_channel_descendant_nvoc.c b/src/nvidia/generated/g_channel_descendant_nvoc.c index 5e19349cf..5a4f0db14 100644 --- a/src/nvidia/generated/g_channel_descendant_nvoc.c +++ b/src/nvidia/generated/g_channel_descendant_nvoc.c @@ -119,14 +119,14 @@ static NvBool __nvoc_thunk_GpuResource_chandesShareCallback(struct ChannelDescen return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ChannelDescendant_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_RsResource_chandesMapTo(struct ChannelDescendant *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ChannelDescendant_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_Notifier_chandesGetOrAllocNotifShare(struct ChannelDescendant *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_ChannelDescendant_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); } +static NV_STATUS __nvoc_thunk_RsResource_chandesMapTo(struct ChannelDescendant *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ChannelDescendant_RsResource.offset), pParams); +} + static NV_STATUS __nvoc_thunk_GpuResource_chandesGetMapAddrSpace(struct ChannelDescendant *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ChannelDescendant_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); } @@ -195,6 +195,10 @@ static NV_STATUS __nvoc_thunk_Notifier_chandesUnregisterEvent(struct ChannelDesc return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_ChannelDescendant_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_chandesControlSerialization_Prologue(struct ChannelDescendant *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ChannelDescendant_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_chandesCanCopy(struct ChannelDescendant *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ChannelDescendant_RsResource.offset)); } @@ -207,6 +211,10 @@ static NV_STATUS __nvoc_thunk_RsResource_chandesIsDuplicate(struct ChannelDescen return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ChannelDescendant_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_chandesControlSerialization_Epilogue(struct ChannelDescendant *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ChannelDescendant_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_chandesGetNotificationListPtr(struct ChannelDescendant *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_ChannelDescendant_Notifier.offset)); } @@ -289,10 +297,10 @@ static void __nvoc_init_funcTable_ChannelDescendant_1(ChannelDescendant *pThis, pThis->__chandesShareCallback__ = &__nvoc_thunk_GpuResource_chandesShareCallback; - pThis->__chandesMapTo__ = &__nvoc_thunk_RsResource_chandesMapTo; - pThis->__chandesGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_chandesGetOrAllocNotifShare; + pThis->__chandesMapTo__ = &__nvoc_thunk_RsResource_chandesMapTo; + pThis->__chandesGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_chandesGetMapAddrSpace; pThis->__chandesSetNotificationShare__ = &__nvoc_thunk_Notifier_chandesSetNotificationShare; @@ -327,12 +335,16 @@ static void __nvoc_init_funcTable_ChannelDescendant_1(ChannelDescendant *pThis, pThis->__chandesUnregisterEvent__ = &__nvoc_thunk_Notifier_chandesUnregisterEvent; + pThis->__chandesControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_chandesControlSerialization_Prologue; + pThis->__chandesCanCopy__ = &__nvoc_thunk_RsResource_chandesCanCopy; pThis->__chandesPreDestruct__ = &__nvoc_thunk_RsResource_chandesPreDestruct; pThis->__chandesIsDuplicate__ = &__nvoc_thunk_RsResource_chandesIsDuplicate; + pThis->__chandesControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_chandesControlSerialization_Epilogue; + pThis->__chandesGetNotificationListPtr__ = &__nvoc_thunk_Notifier_chandesGetNotificationListPtr; pThis->__chandesGetNotificationShare__ = &__nvoc_thunk_Notifier_chandesGetNotificationShare; @@ -368,13 +380,16 @@ NV_STATUS __nvoc_objCreate_ChannelDescendant(ChannelDescendant **ppThis, Dynamic ChannelDescendant *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(ChannelDescendant)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ChannelDescendant), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(ChannelDescendant)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ChannelDescendant); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -394,11 +409,17 @@ NV_STATUS __nvoc_objCreate_ChannelDescendant(ChannelDescendant **ppThis, Dynamic if (status != NV_OK) goto __nvoc_objCreate_ChannelDescendant_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_ChannelDescendant_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(ChannelDescendant)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_channel_descendant_nvoc.h b/src/nvidia/generated/g_channel_descendant_nvoc.h index 7980f95f2..d1abac8a4 100644 --- a/src/nvidia/generated/g_channel_descendant_nvoc.h +++ b/src/nvidia/generated/g_channel_descendant_nvoc.h @@ -85,7 +85,7 @@ typedef struct KernelChannel KernelChannel; */ typedef struct _METHOD METHOD, *PMETHOD; -typedef NV_STATUS (*METHODPROC)(OBJGPU *, struct ChannelDescendant *, PMETHOD, NvU32, NvV32); +typedef NV_STATUS (*METHODPROC)(OBJGPU *, struct ChannelDescendant *, NvU32, NvV32); struct _METHOD { @@ -122,12 +122,12 @@ struct ChannelDescendant { struct INotifier *__nvoc_pbase_INotifier; struct Notifier *__nvoc_pbase_Notifier; struct ChannelDescendant *__nvoc_pbase_ChannelDescendant; - NV_STATUS (*__chandesGetSwMethods__)(struct ChannelDescendant *, METHOD **, NvU32 *); + NV_STATUS (*__chandesGetSwMethods__)(struct ChannelDescendant *, const METHOD **, NvU32 *); NvBool (*__chandesIsSwMethodStalling__)(struct ChannelDescendant *, NvU32); NV_STATUS (*__chandesCheckMemInterUnmap__)(struct ChannelDescendant *, NvBool); NvBool (*__chandesShareCallback__)(struct ChannelDescendant *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__chandesMapTo__)(struct ChannelDescendant *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__chandesGetOrAllocNotifShare__)(struct ChannelDescendant *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__chandesMapTo__)(struct ChannelDescendant *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__chandesGetMapAddrSpace__)(struct ChannelDescendant *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); void (*__chandesSetNotificationShare__)(struct ChannelDescendant *, struct NotifShare *); NvU32 (*__chandesGetRefCount__)(struct ChannelDescendant *); @@ -145,9 +145,11 @@ struct ChannelDescendant { NV_STATUS (*__chandesGetMemoryMappingDescriptor__)(struct ChannelDescendant *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__chandesControlFilter__)(struct ChannelDescendant *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__chandesUnregisterEvent__)(struct ChannelDescendant *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__chandesControlSerialization_Prologue__)(struct ChannelDescendant *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__chandesCanCopy__)(struct ChannelDescendant *); void (*__chandesPreDestruct__)(struct ChannelDescendant *); NV_STATUS (*__chandesIsDuplicate__)(struct ChannelDescendant *, NvHandle, NvBool *); + void (*__chandesControlSerialization_Epilogue__)(struct ChannelDescendant *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__chandesGetNotificationListPtr__)(struct ChannelDescendant *); struct NotifShare *(*__chandesGetNotificationShare__)(struct ChannelDescendant *); NV_STATUS (*__chandesMap__)(struct ChannelDescendant *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -191,8 +193,8 @@ NV_STATUS __nvoc_objCreate_ChannelDescendant(ChannelDescendant**, Dynamic*, NvU3 #define chandesIsSwMethodStalling(pChannelDescendant, hHandle) chandesIsSwMethodStalling_DISPATCH(pChannelDescendant, hHandle) #define chandesCheckMemInterUnmap(pChannelDescendant, bSubdeviceHandleProvided) chandesCheckMemInterUnmap_DISPATCH(pChannelDescendant, bSubdeviceHandleProvided) #define chandesShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) chandesShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define chandesMapTo(pResource, pParams) chandesMapTo_DISPATCH(pResource, pParams) #define chandesGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) chandesGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define chandesMapTo(pResource, pParams) chandesMapTo_DISPATCH(pResource, pParams) #define chandesGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) chandesGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) #define chandesSetNotificationShare(pNotifier, pNotifShare) chandesSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define chandesGetRefCount(pResource) chandesGetRefCount_DISPATCH(pResource) @@ -210,9 +212,11 @@ NV_STATUS __nvoc_objCreate_ChannelDescendant(ChannelDescendant**, Dynamic*, NvU3 #define chandesGetMemoryMappingDescriptor(pRmResource, ppMemDesc) chandesGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define chandesControlFilter(pResource, pCallContext, pParams) chandesControlFilter_DISPATCH(pResource, pCallContext, pParams) #define chandesUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) chandesUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define chandesControlSerialization_Prologue(pResource, pCallContext, pParams) chandesControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define chandesCanCopy(pResource) chandesCanCopy_DISPATCH(pResource) #define chandesPreDestruct(pResource) chandesPreDestruct_DISPATCH(pResource) #define chandesIsDuplicate(pResource, hMemory, pDuplicate) chandesIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define chandesControlSerialization_Epilogue(pResource, pCallContext, pParams) chandesControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define chandesGetNotificationListPtr(pNotifier) chandesGetNotificationListPtr_DISPATCH(pNotifier) #define chandesGetNotificationShare(pNotifier) chandesGetNotificationShare_DISPATCH(pNotifier) #define chandesMap(pGpuResource, pCallContext, pParams, pCpuMapping) chandesMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -247,9 +251,9 @@ static inline void chandesDestroy(struct ChannelDescendant *pChannelDescendant) #define chandesDestroy_HAL(pChannelDescendant) chandesDestroy(pChannelDescendant) -NV_STATUS chandesGetSwMethods_IMPL(struct ChannelDescendant *pChannelDescendant, METHOD **ppMethods, NvU32 *pNumMethods); +NV_STATUS chandesGetSwMethods_IMPL(struct ChannelDescendant *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods); -static inline NV_STATUS chandesGetSwMethods_DISPATCH(struct ChannelDescendant *pChannelDescendant, METHOD **ppMethods, NvU32 *pNumMethods) { +static inline NV_STATUS chandesGetSwMethods_DISPATCH(struct ChannelDescendant *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return pChannelDescendant->__chandesGetSwMethods__(pChannelDescendant, ppMethods, pNumMethods); } @@ -269,14 +273,14 @@ static inline NvBool chandesShareCallback_DISPATCH(struct ChannelDescendant *pGp return pGpuResource->__chandesShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS chandesMapTo_DISPATCH(struct ChannelDescendant *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__chandesMapTo__(pResource, pParams); -} - static inline NV_STATUS chandesGetOrAllocNotifShare_DISPATCH(struct ChannelDescendant *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return pNotifier->__chandesGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); } +static inline NV_STATUS chandesMapTo_DISPATCH(struct ChannelDescendant *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__chandesMapTo__(pResource, pParams); +} + static inline NV_STATUS chandesGetMapAddrSpace_DISPATCH(struct ChannelDescendant *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return pGpuResource->__chandesGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); } @@ -345,6 +349,10 @@ static inline NV_STATUS chandesUnregisterEvent_DISPATCH(struct ChannelDescendant return pNotifier->__chandesUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS chandesControlSerialization_Prologue_DISPATCH(struct ChannelDescendant *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__chandesControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool chandesCanCopy_DISPATCH(struct ChannelDescendant *pResource) { return pResource->__chandesCanCopy__(pResource); } @@ -357,6 +365,10 @@ static inline NV_STATUS chandesIsDuplicate_DISPATCH(struct ChannelDescendant *pR return pResource->__chandesIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void chandesControlSerialization_Epilogue_DISPATCH(struct ChannelDescendant *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__chandesControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *chandesGetNotificationListPtr_DISPATCH(struct ChannelDescendant *pNotifier) { return pNotifier->__chandesGetNotificationListPtr__(pNotifier); } @@ -388,7 +400,7 @@ void chandesDestruct_IMPL(struct ChannelDescendant *pChannelDescendant); // //--------------------------------------------------------------------------- -NV_STATUS mthdNoOperation(OBJGPU *, struct ChannelDescendant *, PMETHOD, NvU32, NvU32); +NV_STATUS mthdNoOperation(OBJGPU *, struct ChannelDescendant *, NvU32, NvU32); #endif // _CHANNEL_DESCENDANT_H_ diff --git a/src/nvidia/generated/g_chipset_nvoc.c b/src/nvidia/generated/g_chipset_nvoc.c index 2d1ec5e32..a130ace4d 100644 --- a/src/nvidia/generated/g_chipset_nvoc.c +++ b/src/nvidia/generated/g_chipset_nvoc.c @@ -116,13 +116,16 @@ NV_STATUS __nvoc_objCreate_OBJCL(OBJCL **ppThis, Dynamic *pParent, NvU32 createF Object *pParentObj; OBJCL *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJCL)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJCL), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJCL)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJCL); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -138,11 +141,17 @@ NV_STATUS __nvoc_objCreate_OBJCL(OBJCL **ppThis, Dynamic *pParent, NvU32 createF if (status != NV_OK) goto __nvoc_objCreate_OBJCL_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJCL_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJCL)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_chipset_nvoc.h b/src/nvidia/generated/g_chipset_nvoc.h index a2c006934..9ef3faa47 100644 --- a/src/nvidia/generated/g_chipset_nvoc.h +++ b/src/nvidia/generated/g_chipset_nvoc.h @@ -266,6 +266,7 @@ struct OBJCL { NvBool PDB_PROP_CL_ASPM_L1_CHIPSET_DISABLED; NvBool PDB_PROP_CL_ASPM_L0S_CHIPSET_ENABLED_MOBILE_ONLY; NvBool PDB_PROP_CL_ASPM_L1_CHIPSET_ENABLED_MOBILE_ONLY; + NvBool PDB_PROP_CL_ASPM_UPSTREAM_PORT_L1_MASK_ENABLED; NvBool PDB_PROP_CL_PCIE_GEN1_GEN2_SWITCH_CHIPSET_DISABLED; NvBool PDB_PROP_CL_PCIE_GEN1_GEN2_SWITCH_CHIPSET_DISABLED_GEFORCE; NvBool PDB_PROP_CL_EXTENDED_TAG_FIELD_NOT_CAPABLE; @@ -347,10 +348,10 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJCL; #define PDB_PROP_CL_ASPM_L1_CHIPSET_DISABLED_BASE_NAME PDB_PROP_CL_ASPM_L1_CHIPSET_DISABLED #define PDB_PROP_CL_RELAXED_ORDERING_NOT_CAPABLE_BASE_CAST #define PDB_PROP_CL_RELAXED_ORDERING_NOT_CAPABLE_BASE_NAME PDB_PROP_CL_RELAXED_ORDERING_NOT_CAPABLE +#define PDB_PROP_CL_ASPM_UPSTREAM_PORT_L1_MASK_ENABLED_BASE_CAST +#define PDB_PROP_CL_ASPM_UPSTREAM_PORT_L1_MASK_ENABLED_BASE_NAME PDB_PROP_CL_ASPM_UPSTREAM_PORT_L1_MASK_ENABLED #define PDB_PROP_CL_PCIE_GEN2_AT_LESS_THAN_X16_DISABLED_BASE_CAST #define PDB_PROP_CL_PCIE_GEN2_AT_LESS_THAN_X16_DISABLED_BASE_NAME PDB_PROP_CL_PCIE_GEN2_AT_LESS_THAN_X16_DISABLED -#define PDB_PROP_CL_ALLOW_PCIE_GEN3_ON_PATSBURG_WITH_IVBE_CPU_BASE_CAST -#define PDB_PROP_CL_ALLOW_PCIE_GEN3_ON_PATSBURG_WITH_IVBE_CPU_BASE_NAME PDB_PROP_CL_ALLOW_PCIE_GEN3_ON_PATSBURG_WITH_IVBE_CPU #define PDB_PROP_CL_UNSUPPORTED_CHIPSET_BASE_CAST #define PDB_PROP_CL_UNSUPPORTED_CHIPSET_BASE_NAME PDB_PROP_CL_UNSUPPORTED_CHIPSET #define PDB_PROP_CL_ASLM_SUPPORTS_GEN2_LINK_UPGRADE_BASE_CAST @@ -361,6 +362,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJCL; #define PDB_PROP_CL_BUG_999673_P2P_ARBITRARY_SPLIT_WAR_BASE_NAME PDB_PROP_CL_BUG_999673_P2P_ARBITRARY_SPLIT_WAR #define PDB_PROP_CL_ASPM_L1_CHIPSET_ENABLED_MOBILE_ONLY_BASE_CAST #define PDB_PROP_CL_ASPM_L1_CHIPSET_ENABLED_MOBILE_ONLY_BASE_NAME PDB_PROP_CL_ASPM_L1_CHIPSET_ENABLED_MOBILE_ONLY +#define PDB_PROP_CL_ALLOW_PCIE_GEN3_ON_PATSBURG_WITH_IVBE_CPU_BASE_CAST +#define PDB_PROP_CL_ALLOW_PCIE_GEN3_ON_PATSBURG_WITH_IVBE_CPU_BASE_NAME PDB_PROP_CL_ALLOW_PCIE_GEN3_ON_PATSBURG_WITH_IVBE_CPU #define PDB_PROP_CL_PCIE_FORCE_GEN2_ENABLE_BASE_CAST #define PDB_PROP_CL_PCIE_FORCE_GEN2_ENABLE_BASE_NAME PDB_PROP_CL_PCIE_FORCE_GEN2_ENABLE #define PDB_PROP_CL_DISABLE_BR03_FLOW_CONTROL_BASE_CAST @@ -462,20 +465,6 @@ static inline void clInitPropertiesFromRegistry(struct OBJGPU *arg0, struct OBJC #define clInitPropertiesFromRegistry_HAL(arg0, pCl) clInitPropertiesFromRegistry(arg0, pCl) -NV_STATUS clGetFHBHandle_IMPL(struct OBJCL *arg0, void **arg1, NvU16 *arg2, NvU16 *arg3); - - -#ifdef __nvoc_chipset_h_disabled -static inline NV_STATUS clGetFHBHandle(struct OBJCL *arg0, void **arg1, NvU16 *arg2, NvU16 *arg3) { - NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_chipset_h_disabled -#define clGetFHBHandle(arg0, arg1, arg2, arg3) clGetFHBHandle_IMPL(arg0, arg1, arg2, arg3) -#endif //__nvoc_chipset_h_disabled - -#define clGetFHBHandle_HAL(arg0, arg1, arg2, arg3) clGetFHBHandle(arg0, arg1, arg2, arg3) - NvU32 clInitMappingPciBusDevice_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1); @@ -908,31 +897,31 @@ static inline NV_STATUS clInitDeviceInfo(struct OBJCL *arg0, struct OBJGPU *arg1 #define clInitDeviceInfo_HAL(arg0, arg1) clInitDeviceInfo(arg0, arg1) -void clCountBR_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, NvU8 *arg2, NvU8 *arg3, NvU8 *arg4); +void clCountBR_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, NvU8 *arg2); #ifdef __nvoc_chipset_h_disabled -static inline void clCountBR(struct OBJGPU *arg0, struct OBJCL *arg1, NvU8 *arg2, NvU8 *arg3, NvU8 *arg4) { +static inline void clCountBR(struct OBJGPU *arg0, struct OBJCL *arg1, NvU8 *arg2) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); } #else //__nvoc_chipset_h_disabled -#define clCountBR(arg0, arg1, arg2, arg3, arg4) clCountBR_IMPL(arg0, arg1, arg2, arg3, arg4) +#define clCountBR(arg0, arg1, arg2) clCountBR_IMPL(arg0, arg1, arg2) #endif //__nvoc_chipset_h_disabled -#define clCountBR_HAL(arg0, arg1, arg2, arg3, arg4) clCountBR(arg0, arg1, arg2, arg3, arg4) +#define clCountBR_HAL(arg0, arg1, arg2) clCountBR(arg0, arg1, arg2) -void clFindCommonBR_IMPL(struct OBJGPU *pGpu1, struct OBJGPU *pGpu2, struct OBJCL *pCl, NvU8 *pBR03Bus, NvU8 *pBR04Bus, NvU8 *pPLXBus, NvBool bScanAll); +void clFindCommonBR_IMPL(struct OBJGPU *pGpu1, struct OBJGPU *pGpu2, struct OBJCL *pCl, NvU8 *pBR04Bus, NvBool bScanAll); #ifdef __nvoc_chipset_h_disabled -static inline void clFindCommonBR(struct OBJGPU *pGpu1, struct OBJGPU *pGpu2, struct OBJCL *pCl, NvU8 *pBR03Bus, NvU8 *pBR04Bus, NvU8 *pPLXBus, NvBool bScanAll) { +static inline void clFindCommonBR(struct OBJGPU *pGpu1, struct OBJGPU *pGpu2, struct OBJCL *pCl, NvU8 *pBR04Bus, NvBool bScanAll) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); } #else //__nvoc_chipset_h_disabled -#define clFindCommonBR(pGpu1, pGpu2, pCl, pBR03Bus, pBR04Bus, pPLXBus, bScanAll) clFindCommonBR_IMPL(pGpu1, pGpu2, pCl, pBR03Bus, pBR04Bus, pPLXBus, bScanAll) +#define clFindCommonBR(pGpu1, pGpu2, pCl, pBR04Bus, bScanAll) clFindCommonBR_IMPL(pGpu1, pGpu2, pCl, pBR04Bus, bScanAll) #endif //__nvoc_chipset_h_disabled -#define clFindCommonBR_HAL(pGpu1, pGpu2, pCl, pBR03Bus, pBR04Bus, pPLXBus, bScanAll) clFindCommonBR(pGpu1, pGpu2, pCl, pBR03Bus, pBR04Bus, pPLXBus, bScanAll) +#define clFindCommonBR_HAL(pGpu1, pGpu2, pCl, pBR04Bus, bScanAll) clFindCommonBR(pGpu1, pGpu2, pCl, pBR04Bus, bScanAll) void clFindCommonDownstreamBR_IMPL(struct OBJGPU *pGpu1, struct OBJGPU *pGpu2, struct OBJCL *pCl, NvU8 *pPciSwitchBus); @@ -947,18 +936,18 @@ static inline void clFindCommonDownstreamBR(struct OBJGPU *pGpu1, struct OBJGPU #define clFindCommonDownstreamBR_HAL(pGpu1, pGpu2, pCl, pPciSwitchBus) clFindCommonDownstreamBR(pGpu1, pGpu2, pCl, pPciSwitchBus) -void clFindBR_IMPL(struct OBJGPU *pGpu, struct OBJCL *pCl, NvU8 *pBR03Bus, NvU8 *pBR04Bus, NvBool *pBRNotBR04A03, NvBool *pNoUnsupportedBRFound, NvBool *pNoOnboardBR04, NvU8 *pPLXBus); +void clFindBR_IMPL(struct OBJGPU *pGpu, struct OBJCL *pCl, NvU8 *pBR03Bus, NvU8 *pBR04Bus, NvBool *pBRNotBR04A03, NvBool *pNoUnsupportedBRFound, NvBool *pNoOnboardBR04); #ifdef __nvoc_chipset_h_disabled -static inline void clFindBR(struct OBJGPU *pGpu, struct OBJCL *pCl, NvU8 *pBR03Bus, NvU8 *pBR04Bus, NvBool *pBRNotBR04A03, NvBool *pNoUnsupportedBRFound, NvBool *pNoOnboardBR04, NvU8 *pPLXBus) { +static inline void clFindBR(struct OBJGPU *pGpu, struct OBJCL *pCl, NvU8 *pBR03Bus, NvU8 *pBR04Bus, NvBool *pBRNotBR04A03, NvBool *pNoUnsupportedBRFound, NvBool *pNoOnboardBR04) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); } #else //__nvoc_chipset_h_disabled -#define clFindBR(pGpu, pCl, pBR03Bus, pBR04Bus, pBRNotBR04A03, pNoUnsupportedBRFound, pNoOnboardBR04, pPLXBus) clFindBR_IMPL(pGpu, pCl, pBR03Bus, pBR04Bus, pBRNotBR04A03, pNoUnsupportedBRFound, pNoOnboardBR04, pPLXBus) +#define clFindBR(pGpu, pCl, pBR03Bus, pBR04Bus, pBRNotBR04A03, pNoUnsupportedBRFound, pNoOnboardBR04) clFindBR_IMPL(pGpu, pCl, pBR03Bus, pBR04Bus, pBRNotBR04A03, pNoUnsupportedBRFound, pNoOnboardBR04) #endif //__nvoc_chipset_h_disabled -#define clFindBR_HAL(pGpu, pCl, pBR03Bus, pBR04Bus, pBRNotBR04A03, pNoUnsupportedBRFound, pNoOnboardBR04, pPLXBus) clFindBR(pGpu, pCl, pBR03Bus, pBR04Bus, pBRNotBR04A03, pNoUnsupportedBRFound, pNoOnboardBR04, pPLXBus) +#define clFindBR_HAL(pGpu, pCl, pBR03Bus, pBR04Bus, pBRNotBR04A03, pNoUnsupportedBRFound, pNoOnboardBR04) clFindBR(pGpu, pCl, pBR03Bus, pBR04Bus, pBRNotBR04A03, pNoUnsupportedBRFound, pNoOnboardBR04) void clSearchBR04_IMPL(struct OBJCL *pCl, NvU8 *pBR04BusArray, NvU8 *pBR04RevArray, NvU8 *pBR04Count); @@ -1028,20 +1017,6 @@ static inline void clFreeBusTopologyCache(struct OBJCL *pCl) { #define clFreeBusTopologyCache_HAL(pCl) clFreeBusTopologyCache(pCl) -NvBool clAreGpusBehindSameBridge_IMPL(struct OBJCL *pCl, struct OBJGPU *pGpu1, struct OBJGPU *pGpu2); - - -#ifdef __nvoc_chipset_h_disabled -static inline NvBool clAreGpusBehindSameBridge(struct OBJCL *pCl, struct OBJGPU *pGpu1, struct OBJGPU *pGpu2) { - NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); - return NV_FALSE; -} -#else //__nvoc_chipset_h_disabled -#define clAreGpusBehindSameBridge(pCl, pGpu1, pGpu2) clAreGpusBehindSameBridge_IMPL(pCl, pGpu1, pGpu2) -#endif //__nvoc_chipset_h_disabled - -#define clAreGpusBehindSameBridge_HAL(pCl, pGpu1, pGpu2) clAreGpusBehindSameBridge(pCl, pGpu1, pGpu2) - NvBool clIsL1MaskEnabledForUpstreamPort_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1); diff --git a/src/nvidia/generated/g_client_nvoc.c b/src/nvidia/generated/g_client_nvoc.c index 7cd9f8a67..a3c457c5b 100644 --- a/src/nvidia/generated/g_client_nvoc.c +++ b/src/nvidia/generated/g_client_nvoc.c @@ -124,13 +124,16 @@ NV_STATUS __nvoc_objCreate_UserInfo(UserInfo **ppThis, Dynamic *pParent, NvU32 c Object *pParentObj; UserInfo *pThis; - pThis = portMemAllocNonPaged(sizeof(UserInfo)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(UserInfo), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(UserInfo)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_UserInfo); + pThis->__nvoc_base_RsShared.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -146,11 +149,17 @@ NV_STATUS __nvoc_objCreate_UserInfo(UserInfo **ppThis, Dynamic *pParent, NvU32 c if (status != NV_OK) goto __nvoc_objCreate_UserInfo_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_UserInfo_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(UserInfo)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -359,13 +368,16 @@ NV_STATUS __nvoc_objCreate_RmClient(RmClient **ppThis, Dynamic *pParent, NvU32 c Object *pParentObj; RmClient *pThis; - pThis = portMemAllocNonPaged(sizeof(RmClient)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RmClient), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(RmClient)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RmClient); + pThis->__nvoc_base_RsClient.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -381,11 +393,17 @@ NV_STATUS __nvoc_objCreate_RmClient(RmClient **ppThis, Dynamic *pParent, NvU32 c if (status != NV_OK) goto __nvoc_objCreate_RmClient_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_RmClient_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(RmClient)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_client_resource_nvoc.c b/src/nvidia/generated/g_client_resource_nvoc.c index e848b1901..7fe2e3414 100644 --- a/src/nvidia/generated/g_client_resource_nvoc.c +++ b/src/nvidia/generated/g_client_resource_nvoc.c @@ -110,6 +110,14 @@ static NvBool __nvoc_thunk_RmClientResource_resShareCallback(struct RsResource * return cliresShareCallback((struct RmClientResource *)(((unsigned char *)pRmCliRes) - __nvoc_rtti_RmClientResource_RsResource.offset), pInvokingClient, pParentRef, pSharePolicy); } +static NV_STATUS __nvoc_thunk_RmClientResource_resControl_Prologue(struct RsResource *pRmCliRes, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return cliresControl_Prologue((struct RmClientResource *)(((unsigned char *)pRmCliRes) - __nvoc_rtti_RmClientResource_RsResource.offset), pCallContext, pParams); +} + +static void __nvoc_thunk_RmClientResource_resControl_Epilogue(struct RsResource *pRmCliRes, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + cliresControl_Epilogue((struct RmClientResource *)(((unsigned char *)pRmCliRes) - __nvoc_rtti_RmClientResource_RsResource.offset), pCallContext, pParams); +} + static NV_STATUS __nvoc_thunk_RsResource_cliresControl(struct RmClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControl((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmClientResource_RsResource.offset), pCallContext, pParams); } @@ -142,12 +150,12 @@ static NV_STATUS __nvoc_thunk_Notifier_cliresUnregisterEvent(struct RmClientReso return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_RmClientResource_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static NvBool __nvoc_thunk_RsResource_cliresCanCopy(struct RmClientResource *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmClientResource_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RsResource_cliresControlSerialization_Prologue(struct RmClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlSerialization_Prologue((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmClientResource_RsResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_cliresControl_Prologue(struct RmClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControl_Prologue((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmClientResource_RsResource.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_RsResource_cliresCanCopy(struct RmClientResource *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmClientResource_RsResource.offset)); } static void __nvoc_thunk_RsResource_cliresPreDestruct(struct RmClientResource *pResource) { @@ -162,12 +170,12 @@ static NV_STATUS __nvoc_thunk_RsResource_cliresIsDuplicate(struct RmClientResour return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmClientResource_RsResource.offset), hMemory, pDuplicate); } -static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_cliresGetNotificationListPtr(struct RmClientResource *pNotifier) { - return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_RmClientResource_Notifier.offset)); +static void __nvoc_thunk_RsResource_cliresControlSerialization_Epilogue(struct RmClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + resControlSerialization_Epilogue((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmClientResource_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_cliresControl_Epilogue(struct RmClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - resControl_Epilogue((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmClientResource_RsResource.offset), pCallContext, pParams); +static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_cliresGetNotificationListPtr(struct RmClientResource *pNotifier) { + return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_RmClientResource_Notifier.offset)); } static struct NotifShare *__nvoc_thunk_Notifier_cliresGetNotificationShare(struct RmClientResource *pNotifier) { @@ -403,12 +411,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient #endif }, { /* [14] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGetPrivilegedStatus_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x135u, /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS), @@ -418,12 +426,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient #endif }, { /* [15] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGetFabricStatus_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) - /*flags=*/ 0x810u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x136u, /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS), @@ -463,12 +471,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient #endif }, { /* [18] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGetRmInstanceId_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) - /*flags=*/ 0x13u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*flags=*/ 0x813u, /*accessRight=*/0x0u, /*methodId=*/ 0x139u, /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS), @@ -478,12 +486,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient #endif }, { /* [19] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGetP2pCapsMatrix_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) - /*flags=*/ 0x11u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x13au, /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS), @@ -523,12 +531,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient #endif }, { /* [22] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x807u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGetClientDatabaseInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) - /*flags=*/ 0x7u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x807u) + /*flags=*/ 0x807u, /*accessRight=*/0x0u, /*methodId=*/ 0x13du, /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS), @@ -538,12 +546,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient #endif }, { /* [23] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGetBuildVersionV2_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) - /*flags=*/ 0x811u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) + /*flags=*/ 0x4811u, /*accessRight=*/0x0u, /*methodId=*/ 0x13eu, /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS), @@ -553,12 +561,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient #endif }, { /* [24] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x807u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemRmctrlCacheModeCtrl_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x807u) - /*flags=*/ 0x807u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) + /*flags=*/ 0x7u, /*accessRight=*/0x0u, /*methodId=*/ 0x13fu, /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS), @@ -628,12 +636,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient #endif }, { /* [29] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuGetIdInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) - /*flags=*/ 0x810u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x202u, /*paramSize=*/ sizeof(NV0000_CTRL_GPU_GET_ID_INFO_PARAMS), @@ -643,12 +651,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient #endif }, { /* [30] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuGetInitStatus_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) - /*flags=*/ 0x11u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x203u, /*paramSize=*/ sizeof(NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS), @@ -658,12 +666,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient #endif }, { /* [31] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuGetDeviceIds_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) - /*flags=*/ 0x13u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*flags=*/ 0x813u, /*accessRight=*/0x0u, /*methodId=*/ 0x204u, /*paramSize=*/ sizeof(NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS), @@ -673,12 +681,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient #endif }, { /* [32] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuGetIdInfoV2_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) - /*flags=*/ 0x810u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x205u, /*paramSize=*/ sizeof(NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS), @@ -703,12 +711,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient #endif }, { /* [34] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuAttachIds_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) - /*flags=*/ 0x11u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x215u, /*paramSize=*/ sizeof(NV0000_CTRL_GPU_ATTACH_IDS_PARAMS), @@ -718,12 +726,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient #endif }, { /* [35] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuDetachIds_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) - /*flags=*/ 0x11u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x216u, /*paramSize=*/ sizeof(NV0000_CTRL_GPU_DETACH_IDS_PARAMS), @@ -733,12 +741,27 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient #endif }, { /* [36] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuGetVideoLinks_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + /*flags=*/ 0x11u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x219u, + /*paramSize=*/ sizeof(NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdGpuGetVideoLinks" +#endif + }, + { /* [37] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuGetPciInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) - /*flags=*/ 0x810u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x21bu, /*paramSize=*/ sizeof(NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS), @@ -747,13 +770,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetPciInfo" #endif }, - { /* [37] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [38] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuGetSvmSize_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x240u, /*paramSize=*/ sizeof(NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS), @@ -762,7 +785,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetSvmSize" #endif }, - { /* [38] */ + { /* [39] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -777,13 +800,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetUuidInfo" #endif }, - { /* [39] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [40] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuGetUuidFromGpuId_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x275u, /*paramSize=*/ sizeof(NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS), @@ -792,7 +815,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetUuidFromGpuId" #endif }, - { /* [40] */ + { /* [41] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -807,13 +830,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuModifyGpuDrainState" #endif }, - { /* [41] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + { /* [42] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuQueryGpuDrainState_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) - /*flags=*/ 0x11u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x279u, /*paramSize=*/ sizeof(NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS), @@ -822,13 +845,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuQueryGpuDrainState" #endif }, - { /* [42] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + { /* [43] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuGetMemOpEnable_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) - /*flags=*/ 0x811u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) + /*flags=*/ 0x4811u, /*accessRight=*/0x0u, /*methodId=*/ 0x27bu, /*paramSize=*/ sizeof(NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS), @@ -837,7 +860,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetMemOpEnable" #endif }, - { /* [43] */ + { /* [44] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -852,7 +875,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuDisableNvlinkInit" #endif }, - { /* [44] */ + { /* [45] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -867,7 +890,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdLegacyConfig" #endif }, - { /* [45] */ + { /* [46] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -882,7 +905,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdIdleChannels" #endif }, - { /* [46] */ + { /* [47] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -897,7 +920,37 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdPushGspUcode" #endif }, - { /* [47] */ + { /* [48] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuSetNvlinkBwMode_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x286u, + /*paramSize=*/ sizeof(NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdGpuSetNvlinkBwMode" +#endif + }, + { /* [49] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuGetNvlinkBwMode_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*flags=*/ 0x813u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x287u, + /*paramSize=*/ sizeof(NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdGpuGetNvlinkBwMode" +#endif + }, + { /* [50] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -912,7 +965,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGsyncGetAttachedIds" #endif }, - { /* [48] */ + { /* [51] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -927,7 +980,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGsyncGetIdInfo" #endif }, - { /* [49] */ + { /* [52] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -942,7 +995,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdEventSetNotification" #endif }, - { /* [50] */ + { /* [53] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -957,7 +1010,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdEventGetSystemEventStatus" #endif }, - { /* [51] */ + { /* [54] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -972,13 +1025,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetDumpSize" #endif }, - { /* [52] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [55] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdNvdGetDump_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, /*accessRight=*/0x0u, /*methodId=*/ 0x602u, /*paramSize=*/ sizeof(NV0000_CTRL_NVD_GET_DUMP_PARAMS), @@ -987,7 +1040,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetDump" #endif }, - { /* [53] */ + { /* [56] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1002,7 +1055,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetTimestamp" #endif }, - { /* [54] */ + { /* [57] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1017,7 +1070,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetNvlogInfo" #endif }, - { /* [55] */ + { /* [58] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1032,7 +1085,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetNvlogBufferInfo" #endif }, - { /* [56] */ + { /* [59] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1047,7 +1100,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetNvlog" #endif }, - { /* [57] */ + { /* [60] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1062,13 +1115,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetRcerrRpt" #endif }, - { /* [58] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [61] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSetSubProcessID_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x901u, /*paramSize=*/ sizeof(NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS), @@ -1077,13 +1130,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSetSubProcessID" #endif }, - { /* [59] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [62] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdDisableSubProcessUserdIsolation_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x902u, /*paramSize=*/ sizeof(NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS), @@ -1092,7 +1145,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdDisableSubProcessUserdIsolation" #endif }, - { /* [60] */ + { /* [63] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1107,7 +1160,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSyncGpuBoostInfo" #endif }, - { /* [61] */ + { /* [64] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x5u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1122,7 +1175,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSyncGpuBoostGroupCreate" #endif }, - { /* [62] */ + { /* [65] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x5u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1137,7 +1190,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSyncGpuBoostGroupDestroy" #endif }, - { /* [63] */ + { /* [66] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1152,7 +1205,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSyncGpuBoostGroupInfo" #endif }, - { /* [64] */ + { /* [67] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1167,7 +1220,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuAcctSetAccountingState" #endif }, - { /* [65] */ + { /* [68] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1182,7 +1235,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuAcctGetAccountingState" #endif }, - { /* [66] */ + { /* [69] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1197,7 +1250,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuAcctGetProcAccountingInfo" #endif }, - { /* [67] */ + { /* [70] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1212,7 +1265,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuAcctGetAccountingPids" #endif }, - { /* [68] */ + { /* [71] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1227,7 +1280,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuAcctClearAccountingData" #endif }, - { /* [69] */ + { /* [72] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1242,13 +1295,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdVgpuGetStartData" #endif }, - { /* [70] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + { /* [73] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdClientGetAddrSpaceType_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) - /*flags=*/ 0x810u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0xd01u, /*paramSize=*/ sizeof(NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS), @@ -1257,13 +1310,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdClientGetAddrSpaceType" #endif }, - { /* [71] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + { /* [74] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdClientGetHandleInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) - /*flags=*/ 0x11u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0xd02u, /*paramSize=*/ sizeof(NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS), @@ -1272,7 +1325,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdClientGetHandleInfo" #endif }, - { /* [72] */ + { /* [75] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1287,7 +1340,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdClientGetAccessRights" #endif }, - { /* [73] */ + { /* [76] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1302,7 +1355,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdClientSetInheritedSharePolicy" #endif }, - { /* [74] */ + { /* [77] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1317,7 +1370,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdClientGetChildHandle" #endif }, - { /* [75] */ + { /* [78] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1332,7 +1385,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdClientShareObject" #endif }, - { /* [76] */ + { /* [79] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1347,7 +1400,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdObjectsAreDuplicates" #endif }, - { /* [77] */ + { /* [80] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1362,7 +1415,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdOsUnixFlushUserCache" #endif }, - { /* [78] */ + { /* [81] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1377,7 +1430,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdOsUnixExportObjectToFd" #endif }, - { /* [79] */ + { /* [82] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1392,7 +1445,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdOsUnixImportObjectFromFd" #endif }, - { /* [80] */ + { /* [83] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1407,7 +1460,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdOsUnixGetExportObjectInfo" #endif }, - { /* [81] */ + { /* [84] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1422,7 +1475,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdOsUnixCreateExportObjectFd" #endif }, - { /* [82] */ + { /* [85] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1437,7 +1490,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdOsUnixExportObjectsToFd" #endif }, - { /* [83] */ + { /* [86] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1457,7 +1510,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient const struct NVOC_EXPORT_INFO __nvoc_export_info_RmClientResource = { - /*numEntries=*/ 84, + /*numEntries=*/ 87, /*pExportEntries=*/ __nvoc_exported_method_def_RmClientResource }; @@ -1512,6 +1565,10 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresShareCallback__ = &cliresShareCallback_IMPL; + pThis->__cliresControl_Prologue__ = &cliresControl_Prologue_IMPL; + + pThis->__cliresControl_Epilogue__ = &cliresControl_Epilogue_IMPL; + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) pThis->__cliresCtrlCmdSystemGetCpuInfo__ = &cliresCtrlCmdSystemGetCpuInfo_IMPL; #endif @@ -1520,7 +1577,7 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdSystemGetFeatures__ = &cliresCtrlCmdSystemGetFeatures_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) pThis->__cliresCtrlCmdSystemGetBuildVersionV2__ = &cliresCtrlCmdSystemGetBuildVersionV2_IMPL; #endif @@ -1564,7 +1621,7 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdSystemGetP2pCapsV2__ = &cliresCtrlCmdSystemGetP2pCapsV2_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdSystemGetP2pCapsMatrix__ = &cliresCtrlCmdSystemGetP2pCapsMatrix_IMPL; #endif @@ -1580,23 +1637,23 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdSystemGetGpusPowerStatus__ = &cliresCtrlCmdSystemGetGpusPowerStatus_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdSystemGetPrivilegedStatus__ = &cliresCtrlCmdSystemGetPrivilegedStatus_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdSystemGetFabricStatus__ = &cliresCtrlCmdSystemGetFabricStatus_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) pThis->__cliresCtrlCmdSystemGetRmInstanceId__ = &cliresCtrlCmdSystemGetRmInstanceId_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x807u) pThis->__cliresCtrlCmdSystemGetClientDatabaseInfo__ = &cliresCtrlCmdSystemGetClientDatabaseInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x807u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) pThis->__cliresCtrlCmdSystemRmctrlCacheModeCtrl__ = &cliresCtrlCmdSystemRmctrlCacheModeCtrl_IMPL; #endif @@ -1604,7 +1661,7 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdNvdGetDumpSize__ = &cliresCtrlCmdNvdGetDumpSize_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) pThis->__cliresCtrlCmdNvdGetDump__ = &cliresCtrlCmdNvdGetDump_IMPL; #endif @@ -1628,11 +1685,11 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdNvdGetRcerrRpt__ = &cliresCtrlCmdNvdGetRcerrRpt_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdClientGetAddrSpaceType__ = &cliresCtrlCmdClientGetAddrSpaceType_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdClientGetHandleInfo__ = &cliresCtrlCmdClientGetHandleInfo_IMPL; #endif @@ -1660,19 +1717,19 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdGpuGetAttachedIds__ = &cliresCtrlCmdGpuGetAttachedIds_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdGpuGetIdInfo__ = &cliresCtrlCmdGpuGetIdInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdGpuGetIdInfoV2__ = &cliresCtrlCmdGpuGetIdInfoV2_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdGpuGetInitStatus__ = &cliresCtrlCmdGpuGetInitStatus_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) pThis->__cliresCtrlCmdGpuGetDeviceIds__ = &cliresCtrlCmdGpuGetDeviceIds_IMPL; #endif @@ -1680,19 +1737,19 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdGpuGetProbedIds__ = &cliresCtrlCmdGpuGetProbedIds_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdGpuAttachIds__ = &cliresCtrlCmdGpuAttachIds_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdGpuDetachIds__ = &cliresCtrlCmdGpuDetachIds_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdGpuGetSvmSize__ = &cliresCtrlCmdGpuGetSvmSize_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdGpuGetPciInfo__ = &cliresCtrlCmdGpuGetPciInfo_IMPL; #endif @@ -1700,7 +1757,7 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdGpuGetUuidInfo__ = &cliresCtrlCmdGpuGetUuidInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdGpuGetUuidFromGpuId__ = &cliresCtrlCmdGpuGetUuidFromGpuId_IMPL; #endif @@ -1708,11 +1765,11 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdGpuModifyGpuDrainState__ = &cliresCtrlCmdGpuModifyGpuDrainState_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdGpuQueryGpuDrainState__ = &cliresCtrlCmdGpuQueryGpuDrainState_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) pThis->__cliresCtrlCmdGpuGetMemOpEnable__ = &cliresCtrlCmdGpuGetMemOpEnable_IMPL; #endif @@ -1720,6 +1777,14 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdGpuDisableNvlinkInit__ = &cliresCtrlCmdGpuDisableNvlinkInit_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + pThis->__cliresCtrlCmdGpuSetNvlinkBwMode__ = &cliresCtrlCmdGpuSetNvlinkBwMode_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + pThis->__cliresCtrlCmdGpuGetNvlinkBwMode__ = &cliresCtrlCmdGpuGetNvlinkBwMode_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__cliresCtrlCmdLegacyConfig__ = &cliresCtrlCmdLegacyConfig_IMPL; #endif @@ -1732,6 +1797,10 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdPushGspUcode__ = &cliresCtrlCmdPushGspUcode_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + pThis->__cliresCtrlCmdGpuGetVideoLinks__ = &cliresCtrlCmdGpuGetVideoLinks_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__cliresCtrlCmdGsyncGetAttachedIds__ = &cliresCtrlCmdGsyncGetAttachedIds_IMPL; #endif @@ -1796,11 +1865,11 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdGpuAcctClearAccountingData__ = &cliresCtrlCmdGpuAcctClearAccountingData_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdSetSubProcessID__ = &cliresCtrlCmdSetSubProcessID_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdDisableSubProcessUserdIsolation__ = &cliresCtrlCmdDisableSubProcessUserdIsolation_IMPL; #endif @@ -1852,6 +1921,10 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__nvoc_base_RsClientResource.__nvoc_base_RsResource.__resShareCallback__ = &__nvoc_thunk_RmClientResource_resShareCallback; + pThis->__nvoc_base_RsClientResource.__nvoc_base_RsResource.__resControl_Prologue__ = &__nvoc_thunk_RmClientResource_resControl_Prologue; + + pThis->__nvoc_base_RsClientResource.__nvoc_base_RsResource.__resControl_Epilogue__ = &__nvoc_thunk_RmClientResource_resControl_Epilogue; + pThis->__cliresControl__ = &__nvoc_thunk_RsResource_cliresControl; pThis->__cliresUnmap__ = &__nvoc_thunk_RsResource_cliresUnmap; @@ -1868,9 +1941,9 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresUnregisterEvent__ = &__nvoc_thunk_Notifier_cliresUnregisterEvent; - pThis->__cliresCanCopy__ = &__nvoc_thunk_RsResource_cliresCanCopy; + pThis->__cliresControlSerialization_Prologue__ = &__nvoc_thunk_RsResource_cliresControlSerialization_Prologue; - pThis->__cliresControl_Prologue__ = &__nvoc_thunk_RsResource_cliresControl_Prologue; + pThis->__cliresCanCopy__ = &__nvoc_thunk_RsResource_cliresCanCopy; pThis->__cliresPreDestruct__ = &__nvoc_thunk_RsResource_cliresPreDestruct; @@ -1878,9 +1951,9 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresIsDuplicate__ = &__nvoc_thunk_RsResource_cliresIsDuplicate; - pThis->__cliresGetNotificationListPtr__ = &__nvoc_thunk_Notifier_cliresGetNotificationListPtr; + pThis->__cliresControlSerialization_Epilogue__ = &__nvoc_thunk_RsResource_cliresControlSerialization_Epilogue; - pThis->__cliresControl_Epilogue__ = &__nvoc_thunk_RsResource_cliresControl_Epilogue; + pThis->__cliresGetNotificationListPtr__ = &__nvoc_thunk_Notifier_cliresGetNotificationListPtr; pThis->__cliresGetNotificationShare__ = &__nvoc_thunk_Notifier_cliresGetNotificationShare; @@ -1917,13 +1990,16 @@ NV_STATUS __nvoc_objCreate_RmClientResource(RmClientResource **ppThis, Dynamic * Object *pParentObj; RmClientResource *pThis; - pThis = portMemAllocNonPaged(sizeof(RmClientResource)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RmClientResource), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(RmClientResource)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RmClientResource); + pThis->__nvoc_base_RsClientResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -1939,11 +2015,17 @@ NV_STATUS __nvoc_objCreate_RmClientResource(RmClientResource **ppThis, Dynamic * if (status != NV_OK) goto __nvoc_objCreate_RmClientResource_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_RmClientResource_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(RmClientResource)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_client_resource_nvoc.h b/src/nvidia/generated/g_client_resource_nvoc.h index 8ffd05074..13ac6c37b 100644 --- a/src/nvidia/generated/g_client_resource_nvoc.h +++ b/src/nvidia/generated/g_client_resource_nvoc.h @@ -30,6 +30,7 @@ extern "C" { */ #include "g_client_resource_nvoc.h" + #ifndef _CLIENT_RESOURCE_H_ #define _CLIENT_RESOURCE_H_ @@ -75,6 +76,8 @@ struct RmClientResource { struct RmClientResource *__nvoc_pbase_RmClientResource; NvBool (*__cliresAccessCallback__)(struct RmClientResource *, struct RsClient *, void *, RsAccessRight); NvBool (*__cliresShareCallback__)(struct RmClientResource *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__cliresControl_Prologue__)(struct RmClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__cliresControl_Epilogue__)(struct RmClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__cliresCtrlCmdSystemGetCpuInfo__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetFeatures__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetBuildVersionV2__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS *); @@ -127,9 +130,12 @@ struct RmClientResource { NV_STATUS (*__cliresCtrlCmdGpuQueryGpuDrainState__)(struct RmClientResource *, NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS *); NV_STATUS (*__cliresCtrlCmdGpuGetMemOpEnable__)(struct RmClientResource *, NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS *); NV_STATUS (*__cliresCtrlCmdGpuDisableNvlinkInit__)(struct RmClientResource *, NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS *); + NV_STATUS (*__cliresCtrlCmdGpuSetNvlinkBwMode__)(struct RmClientResource *, NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS *); + NV_STATUS (*__cliresCtrlCmdGpuGetNvlinkBwMode__)(struct RmClientResource *, NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS *); NV_STATUS (*__cliresCtrlCmdLegacyConfig__)(struct RmClientResource *, NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS *); NV_STATUS (*__cliresCtrlCmdIdleChannels__)(struct RmClientResource *, NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS *); NV_STATUS (*__cliresCtrlCmdPushGspUcode__)(struct RmClientResource *, NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS *); + NV_STATUS (*__cliresCtrlCmdGpuGetVideoLinks__)(struct RmClientResource *, NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS *); NV_STATUS (*__cliresCtrlCmdGsyncGetAttachedIds__)(struct RmClientResource *, NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS *); NV_STATUS (*__cliresCtrlCmdGsyncGetIdInfo__)(struct RmClientResource *, NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS *); NV_STATUS (*__cliresCtrlCmdEventSetNotification__)(struct RmClientResource *, NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS *); @@ -167,13 +173,13 @@ struct RmClientResource { void (*__cliresAddAdditionalDependants__)(struct RsClient *, struct RmClientResource *, RsResourceRef *); NvU32 (*__cliresGetRefCount__)(struct RmClientResource *); NV_STATUS (*__cliresUnregisterEvent__)(struct RmClientResource *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__cliresControlSerialization_Prologue__)(struct RmClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__cliresCanCopy__)(struct RmClientResource *); - NV_STATUS (*__cliresControl_Prologue__)(struct RmClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__cliresPreDestruct__)(struct RmClientResource *); NV_STATUS (*__cliresUnmapFrom__)(struct RmClientResource *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__cliresIsDuplicate__)(struct RmClientResource *, NvHandle, NvBool *); + void (*__cliresControlSerialization_Epilogue__)(struct RmClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__cliresGetNotificationListPtr__)(struct RmClientResource *); - void (*__cliresControl_Epilogue__)(struct RmClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); struct NotifShare *(*__cliresGetNotificationShare__)(struct RmClientResource *); NV_STATUS (*__cliresControlLookup__)(struct RmClientResource *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__cliresMap__)(struct RmClientResource *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -210,6 +216,8 @@ NV_STATUS __nvoc_objCreate_RmClientResource(RmClientResource**, Dynamic*, NvU32, #define cliresAccessCallback(pRmCliRes, pInvokingClient, pAllocParams, accessRight) cliresAccessCallback_DISPATCH(pRmCliRes, pInvokingClient, pAllocParams, accessRight) #define cliresShareCallback(pRmCliRes, pInvokingClient, pParentRef, pSharePolicy) cliresShareCallback_DISPATCH(pRmCliRes, pInvokingClient, pParentRef, pSharePolicy) +#define cliresControl_Prologue(pRmCliRes, pCallContext, pParams) cliresControl_Prologue_DISPATCH(pRmCliRes, pCallContext, pParams) +#define cliresControl_Epilogue(pRmCliRes, pCallContext, pParams) cliresControl_Epilogue_DISPATCH(pRmCliRes, pCallContext, pParams) #define cliresCtrlCmdSystemGetCpuInfo(pRmCliRes, pCpuInfoParams) cliresCtrlCmdSystemGetCpuInfo_DISPATCH(pRmCliRes, pCpuInfoParams) #define cliresCtrlCmdSystemGetFeatures(pRmCliRes, pParams) cliresCtrlCmdSystemGetFeatures_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemGetBuildVersionV2(pRmCliRes, pParams) cliresCtrlCmdSystemGetBuildVersionV2_DISPATCH(pRmCliRes, pParams) @@ -262,9 +270,12 @@ NV_STATUS __nvoc_objCreate_RmClientResource(RmClientResource**, Dynamic*, NvU32, #define cliresCtrlCmdGpuQueryGpuDrainState(pRmCliRes, pParams) cliresCtrlCmdGpuQueryGpuDrainState_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdGpuGetMemOpEnable(pRmCliRes, pMemOpEnableParams) cliresCtrlCmdGpuGetMemOpEnable_DISPATCH(pRmCliRes, pMemOpEnableParams) #define cliresCtrlCmdGpuDisableNvlinkInit(pRmCliRes, pParams) cliresCtrlCmdGpuDisableNvlinkInit_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdGpuSetNvlinkBwMode(pRmCliRes, pParams) cliresCtrlCmdGpuSetNvlinkBwMode_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdGpuGetNvlinkBwMode(pRmCliRes, pParams) cliresCtrlCmdGpuGetNvlinkBwMode_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdLegacyConfig(pRmCliRes, pParams) cliresCtrlCmdLegacyConfig_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdIdleChannels(pRmCliRes, pParams) cliresCtrlCmdIdleChannels_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdPushGspUcode(pRmCliRes, pParams) cliresCtrlCmdPushGspUcode_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdGpuGetVideoLinks(pRmCliRes, pParams) cliresCtrlCmdGpuGetVideoLinks_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdGsyncGetAttachedIds(pRmCliRes, pGsyncAttachedIds) cliresCtrlCmdGsyncGetAttachedIds_DISPATCH(pRmCliRes, pGsyncAttachedIds) #define cliresCtrlCmdGsyncGetIdInfo(pRmCliRes, pGsyncIdInfoParams) cliresCtrlCmdGsyncGetIdInfo_DISPATCH(pRmCliRes, pGsyncIdInfoParams) #define cliresCtrlCmdEventSetNotification(pRmCliRes, pEventSetNotificationParams) cliresCtrlCmdEventSetNotification_DISPATCH(pRmCliRes, pEventSetNotificationParams) @@ -302,13 +313,13 @@ NV_STATUS __nvoc_objCreate_RmClientResource(RmClientResource**, Dynamic*, NvU32, #define cliresAddAdditionalDependants(pClient, pResource, pReference) cliresAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define cliresGetRefCount(pResource) cliresGetRefCount_DISPATCH(pResource) #define cliresUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) cliresUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define cliresControlSerialization_Prologue(pResource, pCallContext, pParams) cliresControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define cliresCanCopy(pResource) cliresCanCopy_DISPATCH(pResource) -#define cliresControl_Prologue(pResource, pCallContext, pParams) cliresControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define cliresPreDestruct(pResource) cliresPreDestruct_DISPATCH(pResource) #define cliresUnmapFrom(pResource, pParams) cliresUnmapFrom_DISPATCH(pResource, pParams) #define cliresIsDuplicate(pResource, hMemory, pDuplicate) cliresIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define cliresControlSerialization_Epilogue(pResource, pCallContext, pParams) cliresControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define cliresGetNotificationListPtr(pNotifier) cliresGetNotificationListPtr_DISPATCH(pNotifier) -#define cliresControl_Epilogue(pResource, pCallContext, pParams) cliresControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define cliresGetNotificationShare(pNotifier) cliresGetNotificationShare_DISPATCH(pNotifier) #define cliresControlLookup(pResource, pParams, ppEntry) cliresControlLookup_DISPATCH(pResource, pParams, ppEntry) #define cliresMap(pResource, pCallContext, pParams, pCpuMapping) cliresMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -325,6 +336,18 @@ static inline NvBool cliresShareCallback_DISPATCH(struct RmClientResource *pRmCl return pRmCliRes->__cliresShareCallback__(pRmCliRes, pInvokingClient, pParentRef, pSharePolicy); } +NV_STATUS cliresControl_Prologue_IMPL(struct RmClientResource *pRmCliRes, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); + +static inline NV_STATUS cliresControl_Prologue_DISPATCH(struct RmClientResource *pRmCliRes, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pRmCliRes->__cliresControl_Prologue__(pRmCliRes, pCallContext, pParams); +} + +void cliresControl_Epilogue_IMPL(struct RmClientResource *pRmCliRes, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); + +static inline void cliresControl_Epilogue_DISPATCH(struct RmClientResource *pRmCliRes, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pRmCliRes->__cliresControl_Epilogue__(pRmCliRes, pCallContext, pParams); +} + NV_STATUS cliresCtrlCmdSystemGetCpuInfo_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS *pCpuInfoParams); static inline NV_STATUS cliresCtrlCmdSystemGetCpuInfo_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS *pCpuInfoParams) { @@ -637,6 +660,18 @@ static inline NV_STATUS cliresCtrlCmdGpuDisableNvlinkInit_DISPATCH(struct RmClie return pRmCliRes->__cliresCtrlCmdGpuDisableNvlinkInit__(pRmCliRes, pParams); } +NV_STATUS cliresCtrlCmdGpuSetNvlinkBwMode_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdGpuSetNvlinkBwMode_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdGpuSetNvlinkBwMode__(pRmCliRes, pParams); +} + +NV_STATUS cliresCtrlCmdGpuGetNvlinkBwMode_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdGpuGetNvlinkBwMode_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdGpuGetNvlinkBwMode__(pRmCliRes, pParams); +} + NV_STATUS cliresCtrlCmdLegacyConfig_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS *pParams); static inline NV_STATUS cliresCtrlCmdLegacyConfig_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS *pParams) { @@ -655,6 +690,12 @@ static inline NV_STATUS cliresCtrlCmdPushGspUcode_DISPATCH(struct RmClientResour return pRmCliRes->__cliresCtrlCmdPushGspUcode__(pRmCliRes, pParams); } +NV_STATUS cliresCtrlCmdGpuGetVideoLinks_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdGpuGetVideoLinks_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdGpuGetVideoLinks__(pRmCliRes, pParams); +} + NV_STATUS cliresCtrlCmdGsyncGetAttachedIds_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS *pGsyncAttachedIds); static inline NV_STATUS cliresCtrlCmdGsyncGetAttachedIds_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS *pGsyncAttachedIds) { @@ -861,12 +902,12 @@ static inline NV_STATUS cliresUnregisterEvent_DISPATCH(struct RmClientResource * return pNotifier->__cliresUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static inline NvBool cliresCanCopy_DISPATCH(struct RmClientResource *pResource) { - return pResource->__cliresCanCopy__(pResource); +static inline NV_STATUS cliresControlSerialization_Prologue_DISPATCH(struct RmClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__cliresControlSerialization_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS cliresControl_Prologue_DISPATCH(struct RmClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__cliresControl_Prologue__(pResource, pCallContext, pParams); +static inline NvBool cliresCanCopy_DISPATCH(struct RmClientResource *pResource) { + return pResource->__cliresCanCopy__(pResource); } static inline void cliresPreDestruct_DISPATCH(struct RmClientResource *pResource) { @@ -881,12 +922,12 @@ static inline NV_STATUS cliresIsDuplicate_DISPATCH(struct RmClientResource *pRes return pResource->__cliresIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline PEVENTNOTIFICATION *cliresGetNotificationListPtr_DISPATCH(struct RmClientResource *pNotifier) { - return pNotifier->__cliresGetNotificationListPtr__(pNotifier); +static inline void cliresControlSerialization_Epilogue_DISPATCH(struct RmClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__cliresControlSerialization_Epilogue__(pResource, pCallContext, pParams); } -static inline void cliresControl_Epilogue_DISPATCH(struct RmClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__cliresControl_Epilogue__(pResource, pCallContext, pParams); +static inline PEVENTNOTIFICATION *cliresGetNotificationListPtr_DISPATCH(struct RmClientResource *pNotifier) { + return pNotifier->__cliresGetNotificationListPtr__(pNotifier); } static inline struct NotifShare *cliresGetNotificationShare_DISPATCH(struct RmClientResource *pNotifier) { diff --git a/src/nvidia/generated/g_compute_instance_subscription_nvoc.c b/src/nvidia/generated/g_compute_instance_subscription_nvoc.c index 58e63e216..abf094f08 100644 --- a/src/nvidia/generated/g_compute_instance_subscription_nvoc.c +++ b/src/nvidia/generated/g_compute_instance_subscription_nvoc.c @@ -101,6 +101,54 @@ static NvBool __nvoc_thunk_GpuResource_cisubscriptionShareCallback(struct Comput return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ComputeInstanceSubscription_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } +static NV_STATUS __nvoc_thunk_RmResource_cisubscriptionCheckMemInterUnmap(struct ComputeInstanceSubscription *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ComputeInstanceSubscription_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_cisubscriptionMapTo(struct ComputeInstanceSubscription *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_cisubscriptionGetMapAddrSpace(struct ComputeInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ComputeInstanceSubscription_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_cisubscriptionGetRefCount(struct ComputeInstanceSubscription *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_cisubscriptionAddAdditionalDependants(struct RsClient *pClient, struct ComputeInstanceSubscription *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_cisubscriptionControl_Prologue(struct ComputeInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_cisubscriptionGetRegBaseOffsetAndSize(struct ComputeInstanceSubscription *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ComputeInstanceSubscription_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_cisubscriptionInternalControlForward(struct ComputeInstanceSubscription *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ComputeInstanceSubscription_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_cisubscriptionUnmapFrom(struct ComputeInstanceSubscription *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_cisubscriptionControl_Epilogue(struct ComputeInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_cisubscriptionControlLookup(struct ComputeInstanceSubscription *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset), pParams, ppEntry); +} + +static NvHandle __nvoc_thunk_GpuResource_cisubscriptionGetInternalObjectHandle(struct ComputeInstanceSubscription *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ComputeInstanceSubscription_GpuResource.offset)); +} + static NV_STATUS __nvoc_thunk_GpuResource_cisubscriptionControl(struct ComputeInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ComputeInstanceSubscription_GpuResource.offset), pCallContext, pParams); } @@ -117,64 +165,24 @@ static NV_STATUS __nvoc_thunk_RmResource_cisubscriptionGetMemoryMappingDescripto return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ComputeInstanceSubscription_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_GpuResource_cisubscriptionGetMapAddrSpace(struct ComputeInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ComputeInstanceSubscription_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvHandle __nvoc_thunk_GpuResource_cisubscriptionGetInternalObjectHandle(struct ComputeInstanceSubscription *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ComputeInstanceSubscription_GpuResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_cisubscriptionControlFilter(struct ComputeInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_cisubscriptionAddAdditionalDependants(struct RsClient *pClient, struct ComputeInstanceSubscription *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_cisubscriptionGetRefCount(struct ComputeInstanceSubscription *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RmResource_cisubscriptionCheckMemInterUnmap(struct ComputeInstanceSubscription *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ComputeInstanceSubscription_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_cisubscriptionMapTo(struct ComputeInstanceSubscription *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_cisubscriptionControl_Prologue(struct ComputeInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_GpuResource_cisubscriptionGetRegBaseOffsetAndSize(struct ComputeInstanceSubscription *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ComputeInstanceSubscription_GpuResource.offset), pGpu, pOffset, pSize); -} - -static NV_STATUS __nvoc_thunk_GpuResource_cisubscriptionInternalControlForward(struct ComputeInstanceSubscription *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ComputeInstanceSubscription_GpuResource.offset), command, pParams, size); +static NV_STATUS __nvoc_thunk_RmResource_cisubscriptionControlSerialization_Prologue(struct ComputeInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RmResource.offset), pCallContext, pParams); } static void __nvoc_thunk_RsResource_cisubscriptionPreDestruct(struct ComputeInstanceSubscription *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_cisubscriptionUnmapFrom(struct ComputeInstanceSubscription *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_cisubscriptionIsDuplicate(struct ComputeInstanceSubscription *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset), hMemory, pDuplicate); } -static void __nvoc_thunk_RmResource_cisubscriptionControl_Epilogue(struct ComputeInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_cisubscriptionControlLookup(struct ComputeInstanceSubscription *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_cisubscriptionControlSerialization_Epilogue(struct ComputeInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_cisubscriptionMap(struct ComputeInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -258,6 +266,30 @@ static void __nvoc_init_funcTable_ComputeInstanceSubscription_1(ComputeInstanceS pThis->__cisubscriptionShareCallback__ = &__nvoc_thunk_GpuResource_cisubscriptionShareCallback; + pThis->__cisubscriptionCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_cisubscriptionCheckMemInterUnmap; + + pThis->__cisubscriptionMapTo__ = &__nvoc_thunk_RsResource_cisubscriptionMapTo; + + pThis->__cisubscriptionGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_cisubscriptionGetMapAddrSpace; + + pThis->__cisubscriptionGetRefCount__ = &__nvoc_thunk_RsResource_cisubscriptionGetRefCount; + + pThis->__cisubscriptionAddAdditionalDependants__ = &__nvoc_thunk_RsResource_cisubscriptionAddAdditionalDependants; + + pThis->__cisubscriptionControl_Prologue__ = &__nvoc_thunk_RmResource_cisubscriptionControl_Prologue; + + pThis->__cisubscriptionGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_cisubscriptionGetRegBaseOffsetAndSize; + + pThis->__cisubscriptionInternalControlForward__ = &__nvoc_thunk_GpuResource_cisubscriptionInternalControlForward; + + pThis->__cisubscriptionUnmapFrom__ = &__nvoc_thunk_RsResource_cisubscriptionUnmapFrom; + + pThis->__cisubscriptionControl_Epilogue__ = &__nvoc_thunk_RmResource_cisubscriptionControl_Epilogue; + + pThis->__cisubscriptionControlLookup__ = &__nvoc_thunk_RsResource_cisubscriptionControlLookup; + + pThis->__cisubscriptionGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_cisubscriptionGetInternalObjectHandle; + pThis->__cisubscriptionControl__ = &__nvoc_thunk_GpuResource_cisubscriptionControl; pThis->__cisubscriptionUnmap__ = &__nvoc_thunk_GpuResource_cisubscriptionUnmap; @@ -266,35 +298,15 @@ static void __nvoc_init_funcTable_ComputeInstanceSubscription_1(ComputeInstanceS pThis->__cisubscriptionGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_cisubscriptionGetMemoryMappingDescriptor; - pThis->__cisubscriptionGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_cisubscriptionGetMapAddrSpace; - - pThis->__cisubscriptionGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_cisubscriptionGetInternalObjectHandle; - pThis->__cisubscriptionControlFilter__ = &__nvoc_thunk_RsResource_cisubscriptionControlFilter; - pThis->__cisubscriptionAddAdditionalDependants__ = &__nvoc_thunk_RsResource_cisubscriptionAddAdditionalDependants; - - pThis->__cisubscriptionGetRefCount__ = &__nvoc_thunk_RsResource_cisubscriptionGetRefCount; - - pThis->__cisubscriptionCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_cisubscriptionCheckMemInterUnmap; - - pThis->__cisubscriptionMapTo__ = &__nvoc_thunk_RsResource_cisubscriptionMapTo; - - pThis->__cisubscriptionControl_Prologue__ = &__nvoc_thunk_RmResource_cisubscriptionControl_Prologue; - - pThis->__cisubscriptionGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_cisubscriptionGetRegBaseOffsetAndSize; - - pThis->__cisubscriptionInternalControlForward__ = &__nvoc_thunk_GpuResource_cisubscriptionInternalControlForward; + pThis->__cisubscriptionControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_cisubscriptionControlSerialization_Prologue; pThis->__cisubscriptionPreDestruct__ = &__nvoc_thunk_RsResource_cisubscriptionPreDestruct; - pThis->__cisubscriptionUnmapFrom__ = &__nvoc_thunk_RsResource_cisubscriptionUnmapFrom; - pThis->__cisubscriptionIsDuplicate__ = &__nvoc_thunk_RsResource_cisubscriptionIsDuplicate; - pThis->__cisubscriptionControl_Epilogue__ = &__nvoc_thunk_RmResource_cisubscriptionControl_Epilogue; - - pThis->__cisubscriptionControlLookup__ = &__nvoc_thunk_RsResource_cisubscriptionControlLookup; + pThis->__cisubscriptionControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_cisubscriptionControlSerialization_Epilogue; pThis->__cisubscriptionMap__ = &__nvoc_thunk_GpuResource_cisubscriptionMap; @@ -322,13 +334,16 @@ NV_STATUS __nvoc_objCreate_ComputeInstanceSubscription(ComputeInstanceSubscripti Object *pParentObj; ComputeInstanceSubscription *pThis; - pThis = portMemAllocNonPaged(sizeof(ComputeInstanceSubscription)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ComputeInstanceSubscription), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(ComputeInstanceSubscription)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ComputeInstanceSubscription); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -344,11 +359,17 @@ NV_STATUS __nvoc_objCreate_ComputeInstanceSubscription(ComputeInstanceSubscripti if (status != NV_OK) goto __nvoc_objCreate_ComputeInstanceSubscription_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_ComputeInstanceSubscription_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(ComputeInstanceSubscription)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_compute_instance_subscription_nvoc.h b/src/nvidia/generated/g_compute_instance_subscription_nvoc.h index 61536b0ea..67baf2ed1 100644 --- a/src/nvidia/generated/g_compute_instance_subscription_nvoc.h +++ b/src/nvidia/generated/g_compute_instance_subscription_nvoc.h @@ -67,25 +67,27 @@ struct ComputeInstanceSubscription { NvBool (*__cisubscriptionCanCopy__)(struct ComputeInstanceSubscription *); NV_STATUS (*__cisubscriptionCtrlCmdGetUuid__)(struct ComputeInstanceSubscription *, NVC638_CTRL_GET_UUID_PARAMS *); NvBool (*__cisubscriptionShareCallback__)(struct ComputeInstanceSubscription *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__cisubscriptionCheckMemInterUnmap__)(struct ComputeInstanceSubscription *, NvBool); + NV_STATUS (*__cisubscriptionMapTo__)(struct ComputeInstanceSubscription *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__cisubscriptionGetMapAddrSpace__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__cisubscriptionGetRefCount__)(struct ComputeInstanceSubscription *); + void (*__cisubscriptionAddAdditionalDependants__)(struct RsClient *, struct ComputeInstanceSubscription *, RsResourceRef *); + NV_STATUS (*__cisubscriptionControl_Prologue__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__cisubscriptionGetRegBaseOffsetAndSize__)(struct ComputeInstanceSubscription *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__cisubscriptionInternalControlForward__)(struct ComputeInstanceSubscription *, NvU32, void *, NvU32); + NV_STATUS (*__cisubscriptionUnmapFrom__)(struct ComputeInstanceSubscription *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__cisubscriptionControl_Epilogue__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__cisubscriptionControlLookup__)(struct ComputeInstanceSubscription *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__cisubscriptionGetInternalObjectHandle__)(struct ComputeInstanceSubscription *); NV_STATUS (*__cisubscriptionControl__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__cisubscriptionUnmap__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__cisubscriptionGetMemInterMapParams__)(struct ComputeInstanceSubscription *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__cisubscriptionGetMemoryMappingDescriptor__)(struct ComputeInstanceSubscription *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__cisubscriptionGetMapAddrSpace__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__cisubscriptionGetInternalObjectHandle__)(struct ComputeInstanceSubscription *); NV_STATUS (*__cisubscriptionControlFilter__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__cisubscriptionAddAdditionalDependants__)(struct RsClient *, struct ComputeInstanceSubscription *, RsResourceRef *); - NvU32 (*__cisubscriptionGetRefCount__)(struct ComputeInstanceSubscription *); - NV_STATUS (*__cisubscriptionCheckMemInterUnmap__)(struct ComputeInstanceSubscription *, NvBool); - NV_STATUS (*__cisubscriptionMapTo__)(struct ComputeInstanceSubscription *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__cisubscriptionControl_Prologue__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__cisubscriptionGetRegBaseOffsetAndSize__)(struct ComputeInstanceSubscription *, struct OBJGPU *, NvU32 *, NvU32 *); - NV_STATUS (*__cisubscriptionInternalControlForward__)(struct ComputeInstanceSubscription *, NvU32, void *, NvU32); + NV_STATUS (*__cisubscriptionControlSerialization_Prologue__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__cisubscriptionPreDestruct__)(struct ComputeInstanceSubscription *); - NV_STATUS (*__cisubscriptionUnmapFrom__)(struct ComputeInstanceSubscription *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__cisubscriptionIsDuplicate__)(struct ComputeInstanceSubscription *, NvHandle, NvBool *); - void (*__cisubscriptionControl_Epilogue__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__cisubscriptionControlLookup__)(struct ComputeInstanceSubscription *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__cisubscriptionControlSerialization_Epilogue__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__cisubscriptionMap__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__cisubscriptionAccessCallback__)(struct ComputeInstanceSubscription *, struct RsClient *, void *, RsAccessRight); MIG_COMPUTE_INSTANCE *pMIGComputeInstance; @@ -123,25 +125,27 @@ NV_STATUS __nvoc_objCreate_ComputeInstanceSubscription(ComputeInstanceSubscripti #define cisubscriptionCanCopy(arg0) cisubscriptionCanCopy_DISPATCH(arg0) #define cisubscriptionCtrlCmdGetUuid(arg0, arg1) cisubscriptionCtrlCmdGetUuid_DISPATCH(arg0, arg1) #define cisubscriptionShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) cisubscriptionShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define cisubscriptionCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) cisubscriptionCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define cisubscriptionMapTo(pResource, pParams) cisubscriptionMapTo_DISPATCH(pResource, pParams) +#define cisubscriptionGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) cisubscriptionGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define cisubscriptionGetRefCount(pResource) cisubscriptionGetRefCount_DISPATCH(pResource) +#define cisubscriptionAddAdditionalDependants(pClient, pResource, pReference) cisubscriptionAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define cisubscriptionControl_Prologue(pResource, pCallContext, pParams) cisubscriptionControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define cisubscriptionGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) cisubscriptionGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define cisubscriptionInternalControlForward(pGpuResource, command, pParams, size) cisubscriptionInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define cisubscriptionUnmapFrom(pResource, pParams) cisubscriptionUnmapFrom_DISPATCH(pResource, pParams) +#define cisubscriptionControl_Epilogue(pResource, pCallContext, pParams) cisubscriptionControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define cisubscriptionControlLookup(pResource, pParams, ppEntry) cisubscriptionControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define cisubscriptionGetInternalObjectHandle(pGpuResource) cisubscriptionGetInternalObjectHandle_DISPATCH(pGpuResource) #define cisubscriptionControl(pGpuResource, pCallContext, pParams) cisubscriptionControl_DISPATCH(pGpuResource, pCallContext, pParams) #define cisubscriptionUnmap(pGpuResource, pCallContext, pCpuMapping) cisubscriptionUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define cisubscriptionGetMemInterMapParams(pRmResource, pParams) cisubscriptionGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define cisubscriptionGetMemoryMappingDescriptor(pRmResource, ppMemDesc) cisubscriptionGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define cisubscriptionGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) cisubscriptionGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define cisubscriptionGetInternalObjectHandle(pGpuResource) cisubscriptionGetInternalObjectHandle_DISPATCH(pGpuResource) #define cisubscriptionControlFilter(pResource, pCallContext, pParams) cisubscriptionControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define cisubscriptionAddAdditionalDependants(pClient, pResource, pReference) cisubscriptionAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define cisubscriptionGetRefCount(pResource) cisubscriptionGetRefCount_DISPATCH(pResource) -#define cisubscriptionCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) cisubscriptionCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define cisubscriptionMapTo(pResource, pParams) cisubscriptionMapTo_DISPATCH(pResource, pParams) -#define cisubscriptionControl_Prologue(pResource, pCallContext, pParams) cisubscriptionControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define cisubscriptionGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) cisubscriptionGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) -#define cisubscriptionInternalControlForward(pGpuResource, command, pParams, size) cisubscriptionInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define cisubscriptionControlSerialization_Prologue(pResource, pCallContext, pParams) cisubscriptionControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define cisubscriptionPreDestruct(pResource) cisubscriptionPreDestruct_DISPATCH(pResource) -#define cisubscriptionUnmapFrom(pResource, pParams) cisubscriptionUnmapFrom_DISPATCH(pResource, pParams) #define cisubscriptionIsDuplicate(pResource, hMemory, pDuplicate) cisubscriptionIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) -#define cisubscriptionControl_Epilogue(pResource, pCallContext, pParams) cisubscriptionControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define cisubscriptionControlLookup(pResource, pParams, ppEntry) cisubscriptionControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define cisubscriptionControlSerialization_Epilogue(pResource, pCallContext, pParams) cisubscriptionControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define cisubscriptionMap(pGpuResource, pCallContext, pParams, pCpuMapping) cisubscriptionMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define cisubscriptionAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) cisubscriptionAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool cisubscriptionCanCopy_IMPL(struct ComputeInstanceSubscription *arg0); @@ -160,6 +164,54 @@ static inline NvBool cisubscriptionShareCallback_DISPATCH(struct ComputeInstance return pGpuResource->__cisubscriptionShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } +static inline NV_STATUS cisubscriptionCheckMemInterUnmap_DISPATCH(struct ComputeInstanceSubscription *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__cisubscriptionCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS cisubscriptionMapTo_DISPATCH(struct ComputeInstanceSubscription *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__cisubscriptionMapTo__(pResource, pParams); +} + +static inline NV_STATUS cisubscriptionGetMapAddrSpace_DISPATCH(struct ComputeInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__cisubscriptionGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 cisubscriptionGetRefCount_DISPATCH(struct ComputeInstanceSubscription *pResource) { + return pResource->__cisubscriptionGetRefCount__(pResource); +} + +static inline void cisubscriptionAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ComputeInstanceSubscription *pResource, RsResourceRef *pReference) { + pResource->__cisubscriptionAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS cisubscriptionControl_Prologue_DISPATCH(struct ComputeInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__cisubscriptionControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS cisubscriptionGetRegBaseOffsetAndSize_DISPATCH(struct ComputeInstanceSubscription *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__cisubscriptionGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS cisubscriptionInternalControlForward_DISPATCH(struct ComputeInstanceSubscription *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__cisubscriptionInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS cisubscriptionUnmapFrom_DISPATCH(struct ComputeInstanceSubscription *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__cisubscriptionUnmapFrom__(pResource, pParams); +} + +static inline void cisubscriptionControl_Epilogue_DISPATCH(struct ComputeInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__cisubscriptionControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS cisubscriptionControlLookup_DISPATCH(struct ComputeInstanceSubscription *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__cisubscriptionControlLookup__(pResource, pParams, ppEntry); +} + +static inline NvHandle cisubscriptionGetInternalObjectHandle_DISPATCH(struct ComputeInstanceSubscription *pGpuResource) { + return pGpuResource->__cisubscriptionGetInternalObjectHandle__(pGpuResource); +} + static inline NV_STATUS cisubscriptionControl_DISPATCH(struct ComputeInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pGpuResource->__cisubscriptionControl__(pGpuResource, pCallContext, pParams); } @@ -176,64 +228,24 @@ static inline NV_STATUS cisubscriptionGetMemoryMappingDescriptor_DISPATCH(struct return pRmResource->__cisubscriptionGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS cisubscriptionGetMapAddrSpace_DISPATCH(struct ComputeInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__cisubscriptionGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvHandle cisubscriptionGetInternalObjectHandle_DISPATCH(struct ComputeInstanceSubscription *pGpuResource) { - return pGpuResource->__cisubscriptionGetInternalObjectHandle__(pGpuResource); -} - static inline NV_STATUS cisubscriptionControlFilter_DISPATCH(struct ComputeInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__cisubscriptionControlFilter__(pResource, pCallContext, pParams); } -static inline void cisubscriptionAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ComputeInstanceSubscription *pResource, RsResourceRef *pReference) { - pResource->__cisubscriptionAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 cisubscriptionGetRefCount_DISPATCH(struct ComputeInstanceSubscription *pResource) { - return pResource->__cisubscriptionGetRefCount__(pResource); -} - -static inline NV_STATUS cisubscriptionCheckMemInterUnmap_DISPATCH(struct ComputeInstanceSubscription *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__cisubscriptionCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS cisubscriptionMapTo_DISPATCH(struct ComputeInstanceSubscription *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__cisubscriptionMapTo__(pResource, pParams); -} - -static inline NV_STATUS cisubscriptionControl_Prologue_DISPATCH(struct ComputeInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__cisubscriptionControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS cisubscriptionGetRegBaseOffsetAndSize_DISPATCH(struct ComputeInstanceSubscription *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__cisubscriptionGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); -} - -static inline NV_STATUS cisubscriptionInternalControlForward_DISPATCH(struct ComputeInstanceSubscription *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__cisubscriptionInternalControlForward__(pGpuResource, command, pParams, size); +static inline NV_STATUS cisubscriptionControlSerialization_Prologue_DISPATCH(struct ComputeInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__cisubscriptionControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline void cisubscriptionPreDestruct_DISPATCH(struct ComputeInstanceSubscription *pResource) { pResource->__cisubscriptionPreDestruct__(pResource); } -static inline NV_STATUS cisubscriptionUnmapFrom_DISPATCH(struct ComputeInstanceSubscription *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__cisubscriptionUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS cisubscriptionIsDuplicate_DISPATCH(struct ComputeInstanceSubscription *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__cisubscriptionIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline void cisubscriptionControl_Epilogue_DISPATCH(struct ComputeInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__cisubscriptionControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS cisubscriptionControlLookup_DISPATCH(struct ComputeInstanceSubscription *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__cisubscriptionControlLookup__(pResource, pParams, ppEntry); +static inline void cisubscriptionControlSerialization_Epilogue_DISPATCH(struct ComputeInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__cisubscriptionControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS cisubscriptionMap_DISPATCH(struct ComputeInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_console_mem_nvoc.c b/src/nvidia/generated/g_console_mem_nvoc.c index 8f709ae93..5517d8693 100644 --- a/src/nvidia/generated/g_console_mem_nvoc.c +++ b/src/nvidia/generated/g_console_mem_nvoc.c @@ -101,6 +101,46 @@ static NV_STATUS __nvoc_thunk_Memory_conmemCheckMemInterUnmap(struct ConsoleMemo return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), bSubdeviceHandleProvided); } +static NvBool __nvoc_thunk_RmResource_conmemShareCallback(struct ConsoleMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RsResource_conmemMapTo(struct ConsoleMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_conmemGetMapAddrSpace(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_conmemGetRefCount(struct ConsoleMemory *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_conmemAddAdditionalDependants(struct RsClient *pClient, struct ConsoleMemory *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_conmemControl_Prologue(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_Memory_conmemIsGpuMapAllowed(struct ConsoleMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), pGpu); +} + +static NV_STATUS __nvoc_thunk_RsResource_conmemUnmapFrom(struct ConsoleMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_conmemControl_Epilogue(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_conmemControlLookup(struct ConsoleMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset), pParams, ppEntry); +} + static NV_STATUS __nvoc_thunk_Memory_conmemControl(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), pCallContext, pParams); } @@ -117,36 +157,12 @@ static NV_STATUS __nvoc_thunk_Memory_conmemGetMemoryMappingDescriptor(struct Con return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_Memory_conmemGetMapAddrSpace(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvBool __nvoc_thunk_RmResource_conmemShareCallback(struct ConsoleMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); -} - static NV_STATUS __nvoc_thunk_RsResource_conmemControlFilter(struct ConsoleMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_conmemAddAdditionalDependants(struct RsClient *pClient, struct ConsoleMemory *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_conmemGetRefCount(struct ConsoleMemory *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RsResource_conmemMapTo(struct ConsoleMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_conmemControl_Prologue(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RmResource.offset), pCallContext, pParams); -} - -static NvBool __nvoc_thunk_Memory_conmemIsGpuMapAllowed(struct ConsoleMemory *pMemory, struct OBJGPU *pGpu) { - return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), pGpu); +static NV_STATUS __nvoc_thunk_RmResource_conmemControlSerialization_Prologue(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_conmemIsReady(struct ConsoleMemory *pMemory, NvBool bCopyConstructorContext) { @@ -165,16 +181,8 @@ static NV_STATUS __nvoc_thunk_Memory_conmemIsDuplicate(struct ConsoleMemory *pMe return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), hMemory, pDuplicate); } -static NV_STATUS __nvoc_thunk_RsResource_conmemUnmapFrom(struct ConsoleMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RmResource_conmemControl_Epilogue(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_conmemControlLookup(struct ConsoleMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_conmemControlSerialization_Epilogue(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_conmemMap(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -229,6 +237,26 @@ static void __nvoc_init_funcTable_ConsoleMemory_1(ConsoleMemory *pThis) { pThis->__conmemCheckMemInterUnmap__ = &__nvoc_thunk_Memory_conmemCheckMemInterUnmap; + pThis->__conmemShareCallback__ = &__nvoc_thunk_RmResource_conmemShareCallback; + + pThis->__conmemMapTo__ = &__nvoc_thunk_RsResource_conmemMapTo; + + pThis->__conmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_conmemGetMapAddrSpace; + + pThis->__conmemGetRefCount__ = &__nvoc_thunk_RsResource_conmemGetRefCount; + + pThis->__conmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_conmemAddAdditionalDependants; + + pThis->__conmemControl_Prologue__ = &__nvoc_thunk_RmResource_conmemControl_Prologue; + + pThis->__conmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_conmemIsGpuMapAllowed; + + pThis->__conmemUnmapFrom__ = &__nvoc_thunk_RsResource_conmemUnmapFrom; + + pThis->__conmemControl_Epilogue__ = &__nvoc_thunk_RmResource_conmemControl_Epilogue; + + pThis->__conmemControlLookup__ = &__nvoc_thunk_RsResource_conmemControlLookup; + pThis->__conmemControl__ = &__nvoc_thunk_Memory_conmemControl; pThis->__conmemUnmap__ = &__nvoc_thunk_Memory_conmemUnmap; @@ -237,21 +265,9 @@ static void __nvoc_init_funcTable_ConsoleMemory_1(ConsoleMemory *pThis) { pThis->__conmemGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_conmemGetMemoryMappingDescriptor; - pThis->__conmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_conmemGetMapAddrSpace; - - pThis->__conmemShareCallback__ = &__nvoc_thunk_RmResource_conmemShareCallback; - pThis->__conmemControlFilter__ = &__nvoc_thunk_RsResource_conmemControlFilter; - pThis->__conmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_conmemAddAdditionalDependants; - - pThis->__conmemGetRefCount__ = &__nvoc_thunk_RsResource_conmemGetRefCount; - - pThis->__conmemMapTo__ = &__nvoc_thunk_RsResource_conmemMapTo; - - pThis->__conmemControl_Prologue__ = &__nvoc_thunk_RmResource_conmemControl_Prologue; - - pThis->__conmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_conmemIsGpuMapAllowed; + pThis->__conmemControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_conmemControlSerialization_Prologue; pThis->__conmemIsReady__ = &__nvoc_thunk_Memory_conmemIsReady; @@ -261,11 +277,7 @@ static void __nvoc_init_funcTable_ConsoleMemory_1(ConsoleMemory *pThis) { pThis->__conmemIsDuplicate__ = &__nvoc_thunk_Memory_conmemIsDuplicate; - pThis->__conmemUnmapFrom__ = &__nvoc_thunk_RsResource_conmemUnmapFrom; - - pThis->__conmemControl_Epilogue__ = &__nvoc_thunk_RmResource_conmemControl_Epilogue; - - pThis->__conmemControlLookup__ = &__nvoc_thunk_RsResource_conmemControlLookup; + pThis->__conmemControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_conmemControlSerialization_Epilogue; pThis->__conmemMap__ = &__nvoc_thunk_Memory_conmemMap; @@ -293,13 +305,16 @@ NV_STATUS __nvoc_objCreate_ConsoleMemory(ConsoleMemory **ppThis, Dynamic *pParen Object *pParentObj; ConsoleMemory *pThis; - pThis = portMemAllocNonPaged(sizeof(ConsoleMemory)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ConsoleMemory), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(ConsoleMemory)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ConsoleMemory); + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -315,11 +330,17 @@ NV_STATUS __nvoc_objCreate_ConsoleMemory(ConsoleMemory **ppThis, Dynamic *pParen if (status != NV_OK) goto __nvoc_objCreate_ConsoleMemory_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_ConsoleMemory_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(ConsoleMemory)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_console_mem_nvoc.h b/src/nvidia/generated/g_console_mem_nvoc.h index ef14876c9..b18331597 100644 --- a/src/nvidia/generated/g_console_mem_nvoc.h +++ b/src/nvidia/generated/g_console_mem_nvoc.h @@ -55,25 +55,27 @@ struct ConsoleMemory { struct ConsoleMemory *__nvoc_pbase_ConsoleMemory; NvBool (*__conmemCanCopy__)(struct ConsoleMemory *); NV_STATUS (*__conmemCheckMemInterUnmap__)(struct ConsoleMemory *, NvBool); + NvBool (*__conmemShareCallback__)(struct ConsoleMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__conmemMapTo__)(struct ConsoleMemory *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__conmemGetMapAddrSpace__)(struct ConsoleMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__conmemGetRefCount__)(struct ConsoleMemory *); + void (*__conmemAddAdditionalDependants__)(struct RsClient *, struct ConsoleMemory *, RsResourceRef *); + NV_STATUS (*__conmemControl_Prologue__)(struct ConsoleMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__conmemIsGpuMapAllowed__)(struct ConsoleMemory *, struct OBJGPU *); + NV_STATUS (*__conmemUnmapFrom__)(struct ConsoleMemory *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__conmemControl_Epilogue__)(struct ConsoleMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__conmemControlLookup__)(struct ConsoleMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__conmemControl__)(struct ConsoleMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__conmemUnmap__)(struct ConsoleMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__conmemGetMemInterMapParams__)(struct ConsoleMemory *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__conmemGetMemoryMappingDescriptor__)(struct ConsoleMemory *, MEMORY_DESCRIPTOR **); - NV_STATUS (*__conmemGetMapAddrSpace__)(struct ConsoleMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvBool (*__conmemShareCallback__)(struct ConsoleMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__conmemControlFilter__)(struct ConsoleMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__conmemAddAdditionalDependants__)(struct RsClient *, struct ConsoleMemory *, RsResourceRef *); - NvU32 (*__conmemGetRefCount__)(struct ConsoleMemory *); - NV_STATUS (*__conmemMapTo__)(struct ConsoleMemory *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__conmemControl_Prologue__)(struct ConsoleMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvBool (*__conmemIsGpuMapAllowed__)(struct ConsoleMemory *, struct OBJGPU *); + NV_STATUS (*__conmemControlSerialization_Prologue__)(struct ConsoleMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__conmemIsReady__)(struct ConsoleMemory *, NvBool); NV_STATUS (*__conmemCheckCopyPermissions__)(struct ConsoleMemory *, struct OBJGPU *, NvHandle); void (*__conmemPreDestruct__)(struct ConsoleMemory *); NV_STATUS (*__conmemIsDuplicate__)(struct ConsoleMemory *, NvHandle, NvBool *); - NV_STATUS (*__conmemUnmapFrom__)(struct ConsoleMemory *, RS_RES_UNMAP_FROM_PARAMS *); - void (*__conmemControl_Epilogue__)(struct ConsoleMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__conmemControlLookup__)(struct ConsoleMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__conmemControlSerialization_Epilogue__)(struct ConsoleMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__conmemMap__)(struct ConsoleMemory *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__conmemAccessCallback__)(struct ConsoleMemory *, struct RsClient *, void *, RsAccessRight); }; @@ -108,25 +110,27 @@ NV_STATUS __nvoc_objCreate_ConsoleMemory(ConsoleMemory**, Dynamic*, NvU32, CALL_ #define conmemCanCopy(pConsoleMemory) conmemCanCopy_DISPATCH(pConsoleMemory) #define conmemCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) conmemCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define conmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) conmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define conmemMapTo(pResource, pParams) conmemMapTo_DISPATCH(pResource, pParams) +#define conmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) conmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define conmemGetRefCount(pResource) conmemGetRefCount_DISPATCH(pResource) +#define conmemAddAdditionalDependants(pClient, pResource, pReference) conmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define conmemControl_Prologue(pResource, pCallContext, pParams) conmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define conmemIsGpuMapAllowed(pMemory, pGpu) conmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define conmemUnmapFrom(pResource, pParams) conmemUnmapFrom_DISPATCH(pResource, pParams) +#define conmemControl_Epilogue(pResource, pCallContext, pParams) conmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define conmemControlLookup(pResource, pParams, ppEntry) conmemControlLookup_DISPATCH(pResource, pParams, ppEntry) #define conmemControl(pMemory, pCallContext, pParams) conmemControl_DISPATCH(pMemory, pCallContext, pParams) #define conmemUnmap(pMemory, pCallContext, pCpuMapping) conmemUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define conmemGetMemInterMapParams(pMemory, pParams) conmemGetMemInterMapParams_DISPATCH(pMemory, pParams) #define conmemGetMemoryMappingDescriptor(pMemory, ppMemDesc) conmemGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define conmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) conmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) -#define conmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) conmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define conmemControlFilter(pResource, pCallContext, pParams) conmemControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define conmemAddAdditionalDependants(pClient, pResource, pReference) conmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define conmemGetRefCount(pResource) conmemGetRefCount_DISPATCH(pResource) -#define conmemMapTo(pResource, pParams) conmemMapTo_DISPATCH(pResource, pParams) -#define conmemControl_Prologue(pResource, pCallContext, pParams) conmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define conmemIsGpuMapAllowed(pMemory, pGpu) conmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define conmemControlSerialization_Prologue(pResource, pCallContext, pParams) conmemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define conmemIsReady(pMemory, bCopyConstructorContext) conmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define conmemCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) conmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) #define conmemPreDestruct(pResource) conmemPreDestruct_DISPATCH(pResource) #define conmemIsDuplicate(pMemory, hMemory, pDuplicate) conmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) -#define conmemUnmapFrom(pResource, pParams) conmemUnmapFrom_DISPATCH(pResource, pParams) -#define conmemControl_Epilogue(pResource, pCallContext, pParams) conmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define conmemControlLookup(pResource, pParams, ppEntry) conmemControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define conmemControlSerialization_Epilogue(pResource, pCallContext, pParams) conmemControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define conmemMap(pMemory, pCallContext, pParams, pCpuMapping) conmemMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define conmemAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) conmemAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool conmemCanCopy_IMPL(struct ConsoleMemory *pConsoleMemory); @@ -139,6 +143,46 @@ static inline NV_STATUS conmemCheckMemInterUnmap_DISPATCH(struct ConsoleMemory * return pMemory->__conmemCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } +static inline NvBool conmemShareCallback_DISPATCH(struct ConsoleMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__conmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS conmemMapTo_DISPATCH(struct ConsoleMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__conmemMapTo__(pResource, pParams); +} + +static inline NV_STATUS conmemGetMapAddrSpace_DISPATCH(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__conmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 conmemGetRefCount_DISPATCH(struct ConsoleMemory *pResource) { + return pResource->__conmemGetRefCount__(pResource); +} + +static inline void conmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ConsoleMemory *pResource, RsResourceRef *pReference) { + pResource->__conmemAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS conmemControl_Prologue_DISPATCH(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__conmemControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool conmemIsGpuMapAllowed_DISPATCH(struct ConsoleMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__conmemIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline NV_STATUS conmemUnmapFrom_DISPATCH(struct ConsoleMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__conmemUnmapFrom__(pResource, pParams); +} + +static inline void conmemControl_Epilogue_DISPATCH(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__conmemControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS conmemControlLookup_DISPATCH(struct ConsoleMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__conmemControlLookup__(pResource, pParams, ppEntry); +} + static inline NV_STATUS conmemControl_DISPATCH(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pMemory->__conmemControl__(pMemory, pCallContext, pParams); } @@ -155,36 +199,12 @@ static inline NV_STATUS conmemGetMemoryMappingDescriptor_DISPATCH(struct Console return pMemory->__conmemGetMemoryMappingDescriptor__(pMemory, ppMemDesc); } -static inline NV_STATUS conmemGetMapAddrSpace_DISPATCH(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pMemory->__conmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvBool conmemShareCallback_DISPATCH(struct ConsoleMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pResource->__conmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); -} - static inline NV_STATUS conmemControlFilter_DISPATCH(struct ConsoleMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__conmemControlFilter__(pResource, pCallContext, pParams); } -static inline void conmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ConsoleMemory *pResource, RsResourceRef *pReference) { - pResource->__conmemAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 conmemGetRefCount_DISPATCH(struct ConsoleMemory *pResource) { - return pResource->__conmemGetRefCount__(pResource); -} - -static inline NV_STATUS conmemMapTo_DISPATCH(struct ConsoleMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__conmemMapTo__(pResource, pParams); -} - -static inline NV_STATUS conmemControl_Prologue_DISPATCH(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__conmemControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NvBool conmemIsGpuMapAllowed_DISPATCH(struct ConsoleMemory *pMemory, struct OBJGPU *pGpu) { - return pMemory->__conmemIsGpuMapAllowed__(pMemory, pGpu); +static inline NV_STATUS conmemControlSerialization_Prologue_DISPATCH(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__conmemControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS conmemIsReady_DISPATCH(struct ConsoleMemory *pMemory, NvBool bCopyConstructorContext) { @@ -203,16 +223,8 @@ static inline NV_STATUS conmemIsDuplicate_DISPATCH(struct ConsoleMemory *pMemory return pMemory->__conmemIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline NV_STATUS conmemUnmapFrom_DISPATCH(struct ConsoleMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__conmemUnmapFrom__(pResource, pParams); -} - -static inline void conmemControl_Epilogue_DISPATCH(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__conmemControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS conmemControlLookup_DISPATCH(struct ConsoleMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__conmemControlLookup__(pResource, pParams, ppEntry); +static inline void conmemControlSerialization_Epilogue_DISPATCH(struct ConsoleMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__conmemControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS conmemMap_DISPATCH(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_context_dma_nvoc.c b/src/nvidia/generated/g_context_dma_nvoc.c index dde7cc317..6645d6ef5 100644 --- a/src/nvidia/generated/g_context_dma_nvoc.c +++ b/src/nvidia/generated/g_context_dma_nvoc.c @@ -122,6 +122,38 @@ static NvBool __nvoc_thunk_RmResource_ctxdmaAccessCallback(struct ContextDma *pR return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RmResource.offset), pInvokingClient, pAllocParams, accessRight); } +static void __nvoc_thunk_Notifier_ctxdmaSetNotificationShare(struct ContextDma *pNotifier, struct NotifShare *pNotifShare) { + notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_ContextDma_Notifier.offset), pNotifShare); +} + +static NvU32 __nvoc_thunk_RsResource_ctxdmaGetRefCount(struct ContextDma *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_ctxdmaAddAdditionalDependants(struct RsClient *pClient, struct ContextDma *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_ctxdmaControl_Prologue(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RmResource.offset), pCallContext, pParams); +} + +static void __nvoc_thunk_RmResource_ctxdmaControl_Epilogue(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_ctxdmaControlLookup(struct ContextDma *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset), pParams, ppEntry); +} + +static NV_STATUS __nvoc_thunk_RsResource_ctxdmaControl(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControl((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_ctxdmaUnmap(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset), pCallContext, pCpuMapping); +} + static NV_STATUS __nvoc_thunk_RmResource_ctxdmaGetMemInterMapParams(struct ContextDma *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ContextDma_RmResource.offset), pParams); } @@ -130,42 +162,22 @@ static NV_STATUS __nvoc_thunk_RmResource_ctxdmaGetMemoryMappingDescriptor(struct return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ContextDma_RmResource.offset), ppMemDesc); } -static void __nvoc_thunk_Notifier_ctxdmaSetNotificationShare(struct ContextDma *pNotifier, struct NotifShare *pNotifShare) { - notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_ContextDma_Notifier.offset), pNotifShare); -} - -static NV_STATUS __nvoc_thunk_RsResource_ctxdmaControl(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControl((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset), pCallContext, pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_ctxdmaControlFilter(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset), pCallContext, pParams); } -static NvU32 __nvoc_thunk_RsResource_ctxdmaGetRefCount(struct ContextDma *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_Notifier_ctxdmaUnregisterEvent(struct ContextDma *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_ContextDma_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static NV_STATUS __nvoc_thunk_RsResource_ctxdmaUnmap(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RmResource_ctxdmaControlSerialization_Prologue(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_ctxdmaCanCopy(struct ContextDma *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RmResource_ctxdmaControl_Prologue(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RmResource.offset), pCallContext, pParams); -} - -static void __nvoc_thunk_RsResource_ctxdmaAddAdditionalDependants(struct RsClient *pClient, struct ContextDma *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset), pReference); -} - static void __nvoc_thunk_RsResource_ctxdmaPreDestruct(struct ContextDma *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset)); } @@ -174,22 +186,18 @@ static NV_STATUS __nvoc_thunk_RsResource_ctxdmaIsDuplicate(struct ContextDma *pR return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_ctxdmaControlSerialization_Epilogue(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_ctxdmaGetNotificationListPtr(struct ContextDma *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_ContextDma_Notifier.offset)); } -static void __nvoc_thunk_RmResource_ctxdmaControl_Epilogue(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RmResource.offset), pCallContext, pParams); -} - static struct NotifShare *__nvoc_thunk_Notifier_ctxdmaGetNotificationShare(struct ContextDma *pNotifier) { return notifyGetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_ContextDma_Notifier.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_ctxdmaControlLookup(struct ContextDma *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_RsResource_ctxdmaMap(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return resMap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset), pCallContext, pParams, pCpuMapping); } @@ -328,40 +336,44 @@ static void __nvoc_init_funcTable_ContextDma_1(ContextDma *pThis) { pThis->__ctxdmaAccessCallback__ = &__nvoc_thunk_RmResource_ctxdmaAccessCallback; + pThis->__ctxdmaSetNotificationShare__ = &__nvoc_thunk_Notifier_ctxdmaSetNotificationShare; + + pThis->__ctxdmaGetRefCount__ = &__nvoc_thunk_RsResource_ctxdmaGetRefCount; + + pThis->__ctxdmaAddAdditionalDependants__ = &__nvoc_thunk_RsResource_ctxdmaAddAdditionalDependants; + + pThis->__ctxdmaControl_Prologue__ = &__nvoc_thunk_RmResource_ctxdmaControl_Prologue; + + pThis->__ctxdmaControl_Epilogue__ = &__nvoc_thunk_RmResource_ctxdmaControl_Epilogue; + + pThis->__ctxdmaControlLookup__ = &__nvoc_thunk_RsResource_ctxdmaControlLookup; + + pThis->__ctxdmaControl__ = &__nvoc_thunk_RsResource_ctxdmaControl; + + pThis->__ctxdmaUnmap__ = &__nvoc_thunk_RsResource_ctxdmaUnmap; + pThis->__ctxdmaGetMemInterMapParams__ = &__nvoc_thunk_RmResource_ctxdmaGetMemInterMapParams; pThis->__ctxdmaGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_ctxdmaGetMemoryMappingDescriptor; - pThis->__ctxdmaSetNotificationShare__ = &__nvoc_thunk_Notifier_ctxdmaSetNotificationShare; - - pThis->__ctxdmaControl__ = &__nvoc_thunk_RsResource_ctxdmaControl; - pThis->__ctxdmaControlFilter__ = &__nvoc_thunk_RsResource_ctxdmaControlFilter; - pThis->__ctxdmaGetRefCount__ = &__nvoc_thunk_RsResource_ctxdmaGetRefCount; - pThis->__ctxdmaUnregisterEvent__ = &__nvoc_thunk_Notifier_ctxdmaUnregisterEvent; - pThis->__ctxdmaUnmap__ = &__nvoc_thunk_RsResource_ctxdmaUnmap; + pThis->__ctxdmaControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_ctxdmaControlSerialization_Prologue; pThis->__ctxdmaCanCopy__ = &__nvoc_thunk_RsResource_ctxdmaCanCopy; - pThis->__ctxdmaControl_Prologue__ = &__nvoc_thunk_RmResource_ctxdmaControl_Prologue; - - pThis->__ctxdmaAddAdditionalDependants__ = &__nvoc_thunk_RsResource_ctxdmaAddAdditionalDependants; - pThis->__ctxdmaPreDestruct__ = &__nvoc_thunk_RsResource_ctxdmaPreDestruct; pThis->__ctxdmaIsDuplicate__ = &__nvoc_thunk_RsResource_ctxdmaIsDuplicate; + pThis->__ctxdmaControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_ctxdmaControlSerialization_Epilogue; + pThis->__ctxdmaGetNotificationListPtr__ = &__nvoc_thunk_Notifier_ctxdmaGetNotificationListPtr; - pThis->__ctxdmaControl_Epilogue__ = &__nvoc_thunk_RmResource_ctxdmaControl_Epilogue; - pThis->__ctxdmaGetNotificationShare__ = &__nvoc_thunk_Notifier_ctxdmaGetNotificationShare; - pThis->__ctxdmaControlLookup__ = &__nvoc_thunk_RsResource_ctxdmaControlLookup; - pThis->__ctxdmaMap__ = &__nvoc_thunk_RsResource_ctxdmaMap; pThis->__ctxdmaGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_ctxdmaGetOrAllocNotifShare; @@ -391,13 +403,16 @@ NV_STATUS __nvoc_objCreate_ContextDma(ContextDma **ppThis, Dynamic *pParent, NvU Object *pParentObj; ContextDma *pThis; - pThis = portMemAllocNonPaged(sizeof(ContextDma)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ContextDma), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(ContextDma)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ContextDma); + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -413,11 +428,17 @@ NV_STATUS __nvoc_objCreate_ContextDma(ContextDma **ppThis, Dynamic *pParent, NvU if (status != NV_OK) goto __nvoc_objCreate_ContextDma_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_ContextDma_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(ContextDma)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_context_dma_nvoc.h b/src/nvidia/generated/g_context_dma_nvoc.h index 8534d0410..01bafb779 100644 --- a/src/nvidia/generated/g_context_dma_nvoc.h +++ b/src/nvidia/generated/g_context_dma_nvoc.h @@ -96,23 +96,25 @@ struct ContextDma { NvBool (*__ctxdmaShareCallback__)(struct ContextDma *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__ctxdmaCheckMemInterUnmap__)(struct ContextDma *, NvBool); NvBool (*__ctxdmaAccessCallback__)(struct ContextDma *, struct RsClient *, void *, RsAccessRight); + void (*__ctxdmaSetNotificationShare__)(struct ContextDma *, struct NotifShare *); + NvU32 (*__ctxdmaGetRefCount__)(struct ContextDma *); + void (*__ctxdmaAddAdditionalDependants__)(struct RsClient *, struct ContextDma *, RsResourceRef *); + NV_STATUS (*__ctxdmaControl_Prologue__)(struct ContextDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__ctxdmaControl_Epilogue__)(struct ContextDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__ctxdmaControlLookup__)(struct ContextDma *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__ctxdmaControl__)(struct ContextDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__ctxdmaUnmap__)(struct ContextDma *, struct CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__ctxdmaGetMemInterMapParams__)(struct ContextDma *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__ctxdmaGetMemoryMappingDescriptor__)(struct ContextDma *, struct MEMORY_DESCRIPTOR **); - void (*__ctxdmaSetNotificationShare__)(struct ContextDma *, struct NotifShare *); - NV_STATUS (*__ctxdmaControl__)(struct ContextDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__ctxdmaControlFilter__)(struct ContextDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvU32 (*__ctxdmaGetRefCount__)(struct ContextDma *); NV_STATUS (*__ctxdmaUnregisterEvent__)(struct ContextDma *, NvHandle, NvHandle, NvHandle, NvHandle); - NV_STATUS (*__ctxdmaUnmap__)(struct ContextDma *, struct CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__ctxdmaControlSerialization_Prologue__)(struct ContextDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__ctxdmaCanCopy__)(struct ContextDma *); - NV_STATUS (*__ctxdmaControl_Prologue__)(struct ContextDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__ctxdmaAddAdditionalDependants__)(struct RsClient *, struct ContextDma *, RsResourceRef *); void (*__ctxdmaPreDestruct__)(struct ContextDma *); NV_STATUS (*__ctxdmaIsDuplicate__)(struct ContextDma *, NvHandle, NvBool *); + void (*__ctxdmaControlSerialization_Epilogue__)(struct ContextDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__ctxdmaGetNotificationListPtr__)(struct ContextDma *); - void (*__ctxdmaControl_Epilogue__)(struct ContextDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); struct NotifShare *(*__ctxdmaGetNotificationShare__)(struct ContextDma *); - NV_STATUS (*__ctxdmaControlLookup__)(struct ContextDma *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__ctxdmaMap__)(struct ContextDma *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NV_STATUS (*__ctxdmaGetOrAllocNotifShare__)(struct ContextDma *, NvHandle, NvHandle, struct NotifShare **); NvU32 Class; @@ -173,23 +175,25 @@ NV_STATUS __nvoc_objCreate_ContextDma(ContextDma**, Dynamic*, NvU32, struct CALL #define ctxdmaShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) ctxdmaShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define ctxdmaCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) ctxdmaCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define ctxdmaAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) ctxdmaAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +#define ctxdmaSetNotificationShare(pNotifier, pNotifShare) ctxdmaSetNotificationShare_DISPATCH(pNotifier, pNotifShare) +#define ctxdmaGetRefCount(pResource) ctxdmaGetRefCount_DISPATCH(pResource) +#define ctxdmaAddAdditionalDependants(pClient, pResource, pReference) ctxdmaAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define ctxdmaControl_Prologue(pResource, pCallContext, pParams) ctxdmaControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define ctxdmaControl_Epilogue(pResource, pCallContext, pParams) ctxdmaControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define ctxdmaControlLookup(pResource, pParams, ppEntry) ctxdmaControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define ctxdmaControl(pResource, pCallContext, pParams) ctxdmaControl_DISPATCH(pResource, pCallContext, pParams) +#define ctxdmaUnmap(pResource, pCallContext, pCpuMapping) ctxdmaUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define ctxdmaGetMemInterMapParams(pRmResource, pParams) ctxdmaGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define ctxdmaGetMemoryMappingDescriptor(pRmResource, ppMemDesc) ctxdmaGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define ctxdmaSetNotificationShare(pNotifier, pNotifShare) ctxdmaSetNotificationShare_DISPATCH(pNotifier, pNotifShare) -#define ctxdmaControl(pResource, pCallContext, pParams) ctxdmaControl_DISPATCH(pResource, pCallContext, pParams) #define ctxdmaControlFilter(pResource, pCallContext, pParams) ctxdmaControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define ctxdmaGetRefCount(pResource) ctxdmaGetRefCount_DISPATCH(pResource) #define ctxdmaUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) ctxdmaUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) -#define ctxdmaUnmap(pResource, pCallContext, pCpuMapping) ctxdmaUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define ctxdmaControlSerialization_Prologue(pResource, pCallContext, pParams) ctxdmaControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define ctxdmaCanCopy(pResource) ctxdmaCanCopy_DISPATCH(pResource) -#define ctxdmaControl_Prologue(pResource, pCallContext, pParams) ctxdmaControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define ctxdmaAddAdditionalDependants(pClient, pResource, pReference) ctxdmaAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define ctxdmaPreDestruct(pResource) ctxdmaPreDestruct_DISPATCH(pResource) #define ctxdmaIsDuplicate(pResource, hMemory, pDuplicate) ctxdmaIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define ctxdmaControlSerialization_Epilogue(pResource, pCallContext, pParams) ctxdmaControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define ctxdmaGetNotificationListPtr(pNotifier) ctxdmaGetNotificationListPtr_DISPATCH(pNotifier) -#define ctxdmaControl_Epilogue(pResource, pCallContext, pParams) ctxdmaControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define ctxdmaGetNotificationShare(pNotifier) ctxdmaGetNotificationShare_DISPATCH(pNotifier) -#define ctxdmaControlLookup(pResource, pParams, ppEntry) ctxdmaControlLookup_DISPATCH(pResource, pParams, ppEntry) #define ctxdmaMap(pResource, pCallContext, pParams, pCpuMapping) ctxdmaMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) #define ctxdmaGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) ctxdmaGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) NV_STATUS ctxdmaValidate_IMPL(struct ContextDma *pContextDma, NvU64 start, NvU64 len); @@ -246,6 +250,38 @@ static inline NvBool ctxdmaAccessCallback_DISPATCH(struct ContextDma *pResource, return pResource->__ctxdmaAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); } +static inline void ctxdmaSetNotificationShare_DISPATCH(struct ContextDma *pNotifier, struct NotifShare *pNotifShare) { + pNotifier->__ctxdmaSetNotificationShare__(pNotifier, pNotifShare); +} + +static inline NvU32 ctxdmaGetRefCount_DISPATCH(struct ContextDma *pResource) { + return pResource->__ctxdmaGetRefCount__(pResource); +} + +static inline void ctxdmaAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ContextDma *pResource, RsResourceRef *pReference) { + pResource->__ctxdmaAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS ctxdmaControl_Prologue_DISPATCH(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__ctxdmaControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline void ctxdmaControl_Epilogue_DISPATCH(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__ctxdmaControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS ctxdmaControlLookup_DISPATCH(struct ContextDma *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__ctxdmaControlLookup__(pResource, pParams, ppEntry); +} + +static inline NV_STATUS ctxdmaControl_DISPATCH(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__ctxdmaControl__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS ctxdmaUnmap_DISPATCH(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__ctxdmaUnmap__(pResource, pCallContext, pCpuMapping); +} + static inline NV_STATUS ctxdmaGetMemInterMapParams_DISPATCH(struct ContextDma *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { return pRmResource->__ctxdmaGetMemInterMapParams__(pRmResource, pParams); } @@ -254,42 +290,22 @@ static inline NV_STATUS ctxdmaGetMemoryMappingDescriptor_DISPATCH(struct Context return pRmResource->__ctxdmaGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline void ctxdmaSetNotificationShare_DISPATCH(struct ContextDma *pNotifier, struct NotifShare *pNotifShare) { - pNotifier->__ctxdmaSetNotificationShare__(pNotifier, pNotifShare); -} - -static inline NV_STATUS ctxdmaControl_DISPATCH(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__ctxdmaControl__(pResource, pCallContext, pParams); -} - static inline NV_STATUS ctxdmaControlFilter_DISPATCH(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__ctxdmaControlFilter__(pResource, pCallContext, pParams); } -static inline NvU32 ctxdmaGetRefCount_DISPATCH(struct ContextDma *pResource) { - return pResource->__ctxdmaGetRefCount__(pResource); -} - static inline NV_STATUS ctxdmaUnregisterEvent_DISPATCH(struct ContextDma *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { return pNotifier->__ctxdmaUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static inline NV_STATUS ctxdmaUnmap_DISPATCH(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pResource->__ctxdmaUnmap__(pResource, pCallContext, pCpuMapping); +static inline NV_STATUS ctxdmaControlSerialization_Prologue_DISPATCH(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__ctxdmaControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool ctxdmaCanCopy_DISPATCH(struct ContextDma *pResource) { return pResource->__ctxdmaCanCopy__(pResource); } -static inline NV_STATUS ctxdmaControl_Prologue_DISPATCH(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__ctxdmaControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline void ctxdmaAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ContextDma *pResource, RsResourceRef *pReference) { - pResource->__ctxdmaAddAdditionalDependants__(pClient, pResource, pReference); -} - static inline void ctxdmaPreDestruct_DISPATCH(struct ContextDma *pResource) { pResource->__ctxdmaPreDestruct__(pResource); } @@ -298,22 +314,18 @@ static inline NV_STATUS ctxdmaIsDuplicate_DISPATCH(struct ContextDma *pResource, return pResource->__ctxdmaIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void ctxdmaControlSerialization_Epilogue_DISPATCH(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__ctxdmaControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *ctxdmaGetNotificationListPtr_DISPATCH(struct ContextDma *pNotifier) { return pNotifier->__ctxdmaGetNotificationListPtr__(pNotifier); } -static inline void ctxdmaControl_Epilogue_DISPATCH(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__ctxdmaControl_Epilogue__(pResource, pCallContext, pParams); -} - static inline struct NotifShare *ctxdmaGetNotificationShare_DISPATCH(struct ContextDma *pNotifier) { return pNotifier->__ctxdmaGetNotificationShare__(pNotifier); } -static inline NV_STATUS ctxdmaControlLookup_DISPATCH(struct ContextDma *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__ctxdmaControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS ctxdmaMap_DISPATCH(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return pResource->__ctxdmaMap__(pResource, pCallContext, pParams, pCpuMapping); } diff --git a/src/nvidia/generated/g_dbgbuffer_nvoc.c b/src/nvidia/generated/g_dbgbuffer_nvoc.c index b216107ca..b67f44d78 100644 --- a/src/nvidia/generated/g_dbgbuffer_nvoc.c +++ b/src/nvidia/generated/g_dbgbuffer_nvoc.c @@ -113,30 +113,6 @@ static NvBool __nvoc_thunk_GpuResource_dbgbufShareCallback(struct DebugBufferApi return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DebugBufferApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuResource_dbgbufControl(struct DebugBufferApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DebugBufferApi_GpuResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_dbgbufGetMemInterMapParams(struct DebugBufferApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DebugBufferApi_RmResource.offset), pParams); -} - -static NvHandle __nvoc_thunk_GpuResource_dbgbufGetInternalObjectHandle(struct DebugBufferApi *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DebugBufferApi_GpuResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RsResource_dbgbufControlFilter(struct DebugBufferApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset), pCallContext, pParams); -} - -static void __nvoc_thunk_RsResource_dbgbufAddAdditionalDependants(struct RsClient *pClient, struct DebugBufferApi *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_dbgbufGetRefCount(struct DebugBufferApi *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_RmResource_dbgbufCheckMemInterUnmap(struct DebugBufferApi *pRmResource, NvBool bSubdeviceHandleProvided) { return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DebugBufferApi_RmResource.offset), bSubdeviceHandleProvided); } @@ -145,6 +121,14 @@ static NV_STATUS __nvoc_thunk_RsResource_dbgbufMapTo(struct DebugBufferApi *pRes return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset), pParams); } +static NvU32 __nvoc_thunk_RsResource_dbgbufGetRefCount(struct DebugBufferApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_dbgbufAddAdditionalDependants(struct RsClient *pClient, struct DebugBufferApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset), pReference); +} + static NV_STATUS __nvoc_thunk_RmResource_dbgbufControl_Prologue(struct DebugBufferApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RmResource.offset), pCallContext, pParams); } @@ -153,26 +137,14 @@ static NV_STATUS __nvoc_thunk_GpuResource_dbgbufGetRegBaseOffsetAndSize(struct D return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DebugBufferApi_GpuResource.offset), pGpu, pOffset, pSize); } -static NvBool __nvoc_thunk_RsResource_dbgbufCanCopy(struct DebugBufferApi *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_GpuResource_dbgbufInternalControlForward(struct DebugBufferApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DebugBufferApi_GpuResource.offset), command, pParams, size); } -static void __nvoc_thunk_RsResource_dbgbufPreDestruct(struct DebugBufferApi *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_dbgbufUnmapFrom(struct DebugBufferApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RsResource_dbgbufIsDuplicate(struct DebugBufferApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset), hMemory, pDuplicate); -} - static void __nvoc_thunk_RmResource_dbgbufControl_Epilogue(struct DebugBufferApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RmResource.offset), pCallContext, pParams); } @@ -181,6 +153,42 @@ static NV_STATUS __nvoc_thunk_RsResource_dbgbufControlLookup(struct DebugBufferA return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset), pParams, ppEntry); } +static NvHandle __nvoc_thunk_GpuResource_dbgbufGetInternalObjectHandle(struct DebugBufferApi *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DebugBufferApi_GpuResource.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_dbgbufControl(struct DebugBufferApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DebugBufferApi_GpuResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_dbgbufGetMemInterMapParams(struct DebugBufferApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DebugBufferApi_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_dbgbufControlFilter(struct DebugBufferApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_dbgbufControlSerialization_Prologue(struct DebugBufferApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_RsResource_dbgbufCanCopy(struct DebugBufferApi *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_dbgbufPreDestruct(struct DebugBufferApi *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_dbgbufIsDuplicate(struct DebugBufferApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_dbgbufControlSerialization_Epilogue(struct DebugBufferApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RmResource_dbgbufAccessCallback(struct DebugBufferApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RmResource.offset), pInvokingClient, pAllocParams, accessRight); } @@ -242,40 +250,44 @@ static void __nvoc_init_funcTable_DebugBufferApi_1(DebugBufferApi *pThis) { pThis->__dbgbufShareCallback__ = &__nvoc_thunk_GpuResource_dbgbufShareCallback; - pThis->__dbgbufControl__ = &__nvoc_thunk_GpuResource_dbgbufControl; - - pThis->__dbgbufGetMemInterMapParams__ = &__nvoc_thunk_RmResource_dbgbufGetMemInterMapParams; - - pThis->__dbgbufGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_dbgbufGetInternalObjectHandle; - - pThis->__dbgbufControlFilter__ = &__nvoc_thunk_RsResource_dbgbufControlFilter; - - pThis->__dbgbufAddAdditionalDependants__ = &__nvoc_thunk_RsResource_dbgbufAddAdditionalDependants; - - pThis->__dbgbufGetRefCount__ = &__nvoc_thunk_RsResource_dbgbufGetRefCount; - pThis->__dbgbufCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dbgbufCheckMemInterUnmap; pThis->__dbgbufMapTo__ = &__nvoc_thunk_RsResource_dbgbufMapTo; + pThis->__dbgbufGetRefCount__ = &__nvoc_thunk_RsResource_dbgbufGetRefCount; + + pThis->__dbgbufAddAdditionalDependants__ = &__nvoc_thunk_RsResource_dbgbufAddAdditionalDependants; + pThis->__dbgbufControl_Prologue__ = &__nvoc_thunk_RmResource_dbgbufControl_Prologue; pThis->__dbgbufGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_dbgbufGetRegBaseOffsetAndSize; - pThis->__dbgbufCanCopy__ = &__nvoc_thunk_RsResource_dbgbufCanCopy; - pThis->__dbgbufInternalControlForward__ = &__nvoc_thunk_GpuResource_dbgbufInternalControlForward; - pThis->__dbgbufPreDestruct__ = &__nvoc_thunk_RsResource_dbgbufPreDestruct; - pThis->__dbgbufUnmapFrom__ = &__nvoc_thunk_RsResource_dbgbufUnmapFrom; - pThis->__dbgbufIsDuplicate__ = &__nvoc_thunk_RsResource_dbgbufIsDuplicate; - pThis->__dbgbufControl_Epilogue__ = &__nvoc_thunk_RmResource_dbgbufControl_Epilogue; pThis->__dbgbufControlLookup__ = &__nvoc_thunk_RsResource_dbgbufControlLookup; + pThis->__dbgbufGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_dbgbufGetInternalObjectHandle; + + pThis->__dbgbufControl__ = &__nvoc_thunk_GpuResource_dbgbufControl; + + pThis->__dbgbufGetMemInterMapParams__ = &__nvoc_thunk_RmResource_dbgbufGetMemInterMapParams; + + pThis->__dbgbufControlFilter__ = &__nvoc_thunk_RsResource_dbgbufControlFilter; + + pThis->__dbgbufControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_dbgbufControlSerialization_Prologue; + + pThis->__dbgbufCanCopy__ = &__nvoc_thunk_RsResource_dbgbufCanCopy; + + pThis->__dbgbufPreDestruct__ = &__nvoc_thunk_RsResource_dbgbufPreDestruct; + + pThis->__dbgbufIsDuplicate__ = &__nvoc_thunk_RsResource_dbgbufIsDuplicate; + + pThis->__dbgbufControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_dbgbufControlSerialization_Epilogue; + pThis->__dbgbufAccessCallback__ = &__nvoc_thunk_RmResource_dbgbufAccessCallback; } @@ -300,13 +312,16 @@ NV_STATUS __nvoc_objCreate_DebugBufferApi(DebugBufferApi **ppThis, Dynamic *pPar Object *pParentObj; DebugBufferApi *pThis; - pThis = portMemAllocNonPaged(sizeof(DebugBufferApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DebugBufferApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(DebugBufferApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DebugBufferApi); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -322,11 +337,17 @@ NV_STATUS __nvoc_objCreate_DebugBufferApi(DebugBufferApi **ppThis, Dynamic *pPar if (status != NV_OK) goto __nvoc_objCreate_DebugBufferApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_DebugBufferApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(DebugBufferApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_dbgbuffer_nvoc.h b/src/nvidia/generated/g_dbgbuffer_nvoc.h index d15bd3c89..35af3c50d 100644 --- a/src/nvidia/generated/g_dbgbuffer_nvoc.h +++ b/src/nvidia/generated/g_dbgbuffer_nvoc.h @@ -66,23 +66,25 @@ struct DebugBufferApi { NV_STATUS (*__dbgbufGetMapAddrSpace__)(struct DebugBufferApi *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); NV_STATUS (*__dbgbufGetMemoryMappingDescriptor__)(struct DebugBufferApi *, MEMORY_DESCRIPTOR **); NvBool (*__dbgbufShareCallback__)(struct DebugBufferApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__dbgbufControl__)(struct DebugBufferApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__dbgbufGetMemInterMapParams__)(struct DebugBufferApi *, RMRES_MEM_INTER_MAP_PARAMS *); - NvHandle (*__dbgbufGetInternalObjectHandle__)(struct DebugBufferApi *); - NV_STATUS (*__dbgbufControlFilter__)(struct DebugBufferApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__dbgbufAddAdditionalDependants__)(struct RsClient *, struct DebugBufferApi *, RsResourceRef *); - NvU32 (*__dbgbufGetRefCount__)(struct DebugBufferApi *); NV_STATUS (*__dbgbufCheckMemInterUnmap__)(struct DebugBufferApi *, NvBool); NV_STATUS (*__dbgbufMapTo__)(struct DebugBufferApi *, RS_RES_MAP_TO_PARAMS *); + NvU32 (*__dbgbufGetRefCount__)(struct DebugBufferApi *); + void (*__dbgbufAddAdditionalDependants__)(struct RsClient *, struct DebugBufferApi *, RsResourceRef *); NV_STATUS (*__dbgbufControl_Prologue__)(struct DebugBufferApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dbgbufGetRegBaseOffsetAndSize__)(struct DebugBufferApi *, struct OBJGPU *, NvU32 *, NvU32 *); - NvBool (*__dbgbufCanCopy__)(struct DebugBufferApi *); NV_STATUS (*__dbgbufInternalControlForward__)(struct DebugBufferApi *, NvU32, void *, NvU32); - void (*__dbgbufPreDestruct__)(struct DebugBufferApi *); NV_STATUS (*__dbgbufUnmapFrom__)(struct DebugBufferApi *, RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__dbgbufIsDuplicate__)(struct DebugBufferApi *, NvHandle, NvBool *); void (*__dbgbufControl_Epilogue__)(struct DebugBufferApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dbgbufControlLookup__)(struct DebugBufferApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__dbgbufGetInternalObjectHandle__)(struct DebugBufferApi *); + NV_STATUS (*__dbgbufControl__)(struct DebugBufferApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dbgbufGetMemInterMapParams__)(struct DebugBufferApi *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__dbgbufControlFilter__)(struct DebugBufferApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dbgbufControlSerialization_Prologue__)(struct DebugBufferApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__dbgbufCanCopy__)(struct DebugBufferApi *); + void (*__dbgbufPreDestruct__)(struct DebugBufferApi *); + NV_STATUS (*__dbgbufIsDuplicate__)(struct DebugBufferApi *, NvHandle, NvBool *); + void (*__dbgbufControlSerialization_Epilogue__)(struct DebugBufferApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dbgbufAccessCallback__)(struct DebugBufferApi *, struct RsClient *, void *, RsAccessRight); MEMORY_DESCRIPTOR *pMemDesc; }; @@ -120,23 +122,25 @@ NV_STATUS __nvoc_objCreate_DebugBufferApi(DebugBufferApi**, Dynamic*, NvU32, CAL #define dbgbufGetMapAddrSpace(pDebugBufferApi, pCallContext, mapFlags, pAddrSpace) dbgbufGetMapAddrSpace_DISPATCH(pDebugBufferApi, pCallContext, mapFlags, pAddrSpace) #define dbgbufGetMemoryMappingDescriptor(pDebugBufferApi, ppMemDesc) dbgbufGetMemoryMappingDescriptor_DISPATCH(pDebugBufferApi, ppMemDesc) #define dbgbufShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) dbgbufShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define dbgbufControl(pGpuResource, pCallContext, pParams) dbgbufControl_DISPATCH(pGpuResource, pCallContext, pParams) -#define dbgbufGetMemInterMapParams(pRmResource, pParams) dbgbufGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define dbgbufGetInternalObjectHandle(pGpuResource) dbgbufGetInternalObjectHandle_DISPATCH(pGpuResource) -#define dbgbufControlFilter(pResource, pCallContext, pParams) dbgbufControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define dbgbufAddAdditionalDependants(pClient, pResource, pReference) dbgbufAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define dbgbufGetRefCount(pResource) dbgbufGetRefCount_DISPATCH(pResource) #define dbgbufCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) dbgbufCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define dbgbufMapTo(pResource, pParams) dbgbufMapTo_DISPATCH(pResource, pParams) +#define dbgbufGetRefCount(pResource) dbgbufGetRefCount_DISPATCH(pResource) +#define dbgbufAddAdditionalDependants(pClient, pResource, pReference) dbgbufAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define dbgbufControl_Prologue(pResource, pCallContext, pParams) dbgbufControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dbgbufGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) dbgbufGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) -#define dbgbufCanCopy(pResource) dbgbufCanCopy_DISPATCH(pResource) #define dbgbufInternalControlForward(pGpuResource, command, pParams, size) dbgbufInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) -#define dbgbufPreDestruct(pResource) dbgbufPreDestruct_DISPATCH(pResource) #define dbgbufUnmapFrom(pResource, pParams) dbgbufUnmapFrom_DISPATCH(pResource, pParams) -#define dbgbufIsDuplicate(pResource, hMemory, pDuplicate) dbgbufIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define dbgbufControl_Epilogue(pResource, pCallContext, pParams) dbgbufControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define dbgbufControlLookup(pResource, pParams, ppEntry) dbgbufControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define dbgbufGetInternalObjectHandle(pGpuResource) dbgbufGetInternalObjectHandle_DISPATCH(pGpuResource) +#define dbgbufControl(pGpuResource, pCallContext, pParams) dbgbufControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define dbgbufGetMemInterMapParams(pRmResource, pParams) dbgbufGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define dbgbufControlFilter(pResource, pCallContext, pParams) dbgbufControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define dbgbufControlSerialization_Prologue(pResource, pCallContext, pParams) dbgbufControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define dbgbufCanCopy(pResource) dbgbufCanCopy_DISPATCH(pResource) +#define dbgbufPreDestruct(pResource) dbgbufPreDestruct_DISPATCH(pResource) +#define dbgbufIsDuplicate(pResource, hMemory, pDuplicate) dbgbufIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define dbgbufControlSerialization_Epilogue(pResource, pCallContext, pParams) dbgbufControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define dbgbufAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) dbgbufAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS dbgbufMap_IMPL(struct DebugBufferApi *pDebugBufferApi, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping); @@ -166,30 +170,6 @@ static inline NvBool dbgbufShareCallback_DISPATCH(struct DebugBufferApi *pGpuRes return pGpuResource->__dbgbufShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS dbgbufControl_DISPATCH(struct DebugBufferApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pGpuResource->__dbgbufControl__(pGpuResource, pCallContext, pParams); -} - -static inline NV_STATUS dbgbufGetMemInterMapParams_DISPATCH(struct DebugBufferApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__dbgbufGetMemInterMapParams__(pRmResource, pParams); -} - -static inline NvHandle dbgbufGetInternalObjectHandle_DISPATCH(struct DebugBufferApi *pGpuResource) { - return pGpuResource->__dbgbufGetInternalObjectHandle__(pGpuResource); -} - -static inline NV_STATUS dbgbufControlFilter_DISPATCH(struct DebugBufferApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__dbgbufControlFilter__(pResource, pCallContext, pParams); -} - -static inline void dbgbufAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct DebugBufferApi *pResource, RsResourceRef *pReference) { - pResource->__dbgbufAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 dbgbufGetRefCount_DISPATCH(struct DebugBufferApi *pResource) { - return pResource->__dbgbufGetRefCount__(pResource); -} - static inline NV_STATUS dbgbufCheckMemInterUnmap_DISPATCH(struct DebugBufferApi *pRmResource, NvBool bSubdeviceHandleProvided) { return pRmResource->__dbgbufCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } @@ -198,6 +178,14 @@ static inline NV_STATUS dbgbufMapTo_DISPATCH(struct DebugBufferApi *pResource, R return pResource->__dbgbufMapTo__(pResource, pParams); } +static inline NvU32 dbgbufGetRefCount_DISPATCH(struct DebugBufferApi *pResource) { + return pResource->__dbgbufGetRefCount__(pResource); +} + +static inline void dbgbufAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct DebugBufferApi *pResource, RsResourceRef *pReference) { + pResource->__dbgbufAddAdditionalDependants__(pClient, pResource, pReference); +} + static inline NV_STATUS dbgbufControl_Prologue_DISPATCH(struct DebugBufferApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__dbgbufControl_Prologue__(pResource, pCallContext, pParams); } @@ -206,26 +194,14 @@ static inline NV_STATUS dbgbufGetRegBaseOffsetAndSize_DISPATCH(struct DebugBuffe return pGpuResource->__dbgbufGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); } -static inline NvBool dbgbufCanCopy_DISPATCH(struct DebugBufferApi *pResource) { - return pResource->__dbgbufCanCopy__(pResource); -} - static inline NV_STATUS dbgbufInternalControlForward_DISPATCH(struct DebugBufferApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { return pGpuResource->__dbgbufInternalControlForward__(pGpuResource, command, pParams, size); } -static inline void dbgbufPreDestruct_DISPATCH(struct DebugBufferApi *pResource) { - pResource->__dbgbufPreDestruct__(pResource); -} - static inline NV_STATUS dbgbufUnmapFrom_DISPATCH(struct DebugBufferApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__dbgbufUnmapFrom__(pResource, pParams); } -static inline NV_STATUS dbgbufIsDuplicate_DISPATCH(struct DebugBufferApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return pResource->__dbgbufIsDuplicate__(pResource, hMemory, pDuplicate); -} - static inline void dbgbufControl_Epilogue_DISPATCH(struct DebugBufferApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__dbgbufControl_Epilogue__(pResource, pCallContext, pParams); } @@ -234,6 +210,42 @@ static inline NV_STATUS dbgbufControlLookup_DISPATCH(struct DebugBufferApi *pRes return pResource->__dbgbufControlLookup__(pResource, pParams, ppEntry); } +static inline NvHandle dbgbufGetInternalObjectHandle_DISPATCH(struct DebugBufferApi *pGpuResource) { + return pGpuResource->__dbgbufGetInternalObjectHandle__(pGpuResource); +} + +static inline NV_STATUS dbgbufControl_DISPATCH(struct DebugBufferApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__dbgbufControl__(pGpuResource, pCallContext, pParams); +} + +static inline NV_STATUS dbgbufGetMemInterMapParams_DISPATCH(struct DebugBufferApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__dbgbufGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS dbgbufControlFilter_DISPATCH(struct DebugBufferApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dbgbufControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS dbgbufControlSerialization_Prologue_DISPATCH(struct DebugBufferApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dbgbufControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool dbgbufCanCopy_DISPATCH(struct DebugBufferApi *pResource) { + return pResource->__dbgbufCanCopy__(pResource); +} + +static inline void dbgbufPreDestruct_DISPATCH(struct DebugBufferApi *pResource) { + pResource->__dbgbufPreDestruct__(pResource); +} + +static inline NV_STATUS dbgbufIsDuplicate_DISPATCH(struct DebugBufferApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__dbgbufIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void dbgbufControlSerialization_Epilogue_DISPATCH(struct DebugBufferApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__dbgbufControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline NvBool dbgbufAccessCallback_DISPATCH(struct DebugBufferApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return pResource->__dbgbufAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); } diff --git a/src/nvidia/generated/g_dce_client_nvoc.h b/src/nvidia/generated/g_dce_client_nvoc.h index c5028b208..cba98be2e 100644 --- a/src/nvidia/generated/g_dce_client_nvoc.h +++ b/src/nvidia/generated/g_dce_client_nvoc.h @@ -66,7 +66,6 @@ struct OBJDCECLIENTRM { struct OBJDCECLIENTRM *__nvoc_pbase_OBJDCECLIENTRM; NV_STATUS (*__dceclientConstructEngine__)(struct OBJGPU *, struct OBJDCECLIENTRM *, ENGDESCRIPTOR); void (*__dceclientStateDestroy__)(struct OBJGPU *, struct OBJDCECLIENTRM *); - NV_STATUS (*__dceclientReconcileTunableState__)(POBJGPU, struct OBJDCECLIENTRM *, void *); NV_STATUS (*__dceclientStateLoad__)(POBJGPU, struct OBJDCECLIENTRM *, NvU32); NV_STATUS (*__dceclientStateUnload__)(POBJGPU, struct OBJDCECLIENTRM *, NvU32); NV_STATUS (*__dceclientStateInitLocked__)(POBJGPU, struct OBJDCECLIENTRM *); @@ -77,12 +76,7 @@ struct OBJDCECLIENTRM { void (*__dceclientInitMissing__)(POBJGPU, struct OBJDCECLIENTRM *); NV_STATUS (*__dceclientStatePreInitLocked__)(POBJGPU, struct OBJDCECLIENTRM *); NV_STATUS (*__dceclientStatePreInitUnlocked__)(POBJGPU, struct OBJDCECLIENTRM *); - NV_STATUS (*__dceclientGetTunableState__)(POBJGPU, struct OBJDCECLIENTRM *, void *); - NV_STATUS (*__dceclientCompareTunableState__)(POBJGPU, struct OBJDCECLIENTRM *, void *, void *); - void (*__dceclientFreeTunableState__)(POBJGPU, struct OBJDCECLIENTRM *, void *); NV_STATUS (*__dceclientStatePostLoad__)(POBJGPU, struct OBJDCECLIENTRM *, NvU32); - NV_STATUS (*__dceclientAllocTunableState__)(POBJGPU, struct OBJDCECLIENTRM *, void **); - NV_STATUS (*__dceclientSetTunableState__)(POBJGPU, struct OBJDCECLIENTRM *, void *); NvBool (*__dceclientIsPresent__)(POBJGPU, struct OBJDCECLIENTRM *); struct OBJRPC *pRpc; NvU32 clientId[2]; @@ -120,7 +114,6 @@ NV_STATUS __nvoc_objCreate_OBJDCECLIENTRM(OBJDCECLIENTRM**, Dynamic*, NvU32); #define dceclientConstructEngine(arg0, arg1, arg2) dceclientConstructEngine_DISPATCH(arg0, arg1, arg2) #define dceclientStateDestroy(arg0, arg1) dceclientStateDestroy_DISPATCH(arg0, arg1) -#define dceclientReconcileTunableState(pGpu, pEngstate, pTunableState) dceclientReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define dceclientStateLoad(pGpu, pEngstate, arg0) dceclientStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define dceclientStateUnload(pGpu, pEngstate, arg0) dceclientStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define dceclientStateInitLocked(pGpu, pEngstate) dceclientStateInitLocked_DISPATCH(pGpu, pEngstate) @@ -131,12 +124,7 @@ NV_STATUS __nvoc_objCreate_OBJDCECLIENTRM(OBJDCECLIENTRM**, Dynamic*, NvU32); #define dceclientInitMissing(pGpu, pEngstate) dceclientInitMissing_DISPATCH(pGpu, pEngstate) #define dceclientStatePreInitLocked(pGpu, pEngstate) dceclientStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define dceclientStatePreInitUnlocked(pGpu, pEngstate) dceclientStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define dceclientGetTunableState(pGpu, pEngstate, pTunableState) dceclientGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define dceclientCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) dceclientCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define dceclientFreeTunableState(pGpu, pEngstate, pTunableState) dceclientFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define dceclientStatePostLoad(pGpu, pEngstate, arg0) dceclientStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define dceclientAllocTunableState(pGpu, pEngstate, ppTunableState) dceclientAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define dceclientSetTunableState(pGpu, pEngstate, pTunableState) dceclientSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define dceclientIsPresent(pGpu, pEngstate) dceclientIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS dceclientConstructEngine_IMPL(struct OBJGPU *arg0, struct OBJDCECLIENTRM *arg1, ENGDESCRIPTOR arg2); @@ -150,10 +138,6 @@ static inline void dceclientStateDestroy_DISPATCH(struct OBJGPU *arg0, struct OB arg1->__dceclientStateDestroy__(arg0, arg1); } -static inline NV_STATUS dceclientReconcileTunableState_DISPATCH(POBJGPU pGpu, struct OBJDCECLIENTRM *pEngstate, void *pTunableState) { - return pEngstate->__dceclientReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS dceclientStateLoad_DISPATCH(POBJGPU pGpu, struct OBJDCECLIENTRM *pEngstate, NvU32 arg0) { return pEngstate->__dceclientStateLoad__(pGpu, pEngstate, arg0); } @@ -194,30 +178,10 @@ static inline NV_STATUS dceclientStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, str return pEngstate->__dceclientStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS dceclientGetTunableState_DISPATCH(POBJGPU pGpu, struct OBJDCECLIENTRM *pEngstate, void *pTunableState) { - return pEngstate->__dceclientGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS dceclientCompareTunableState_DISPATCH(POBJGPU pGpu, struct OBJDCECLIENTRM *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__dceclientCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void dceclientFreeTunableState_DISPATCH(POBJGPU pGpu, struct OBJDCECLIENTRM *pEngstate, void *pTunableState) { - pEngstate->__dceclientFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS dceclientStatePostLoad_DISPATCH(POBJGPU pGpu, struct OBJDCECLIENTRM *pEngstate, NvU32 arg0) { return pEngstate->__dceclientStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS dceclientAllocTunableState_DISPATCH(POBJGPU pGpu, struct OBJDCECLIENTRM *pEngstate, void **ppTunableState) { - return pEngstate->__dceclientAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS dceclientSetTunableState_DISPATCH(POBJGPU pGpu, struct OBJDCECLIENTRM *pEngstate, void *pTunableState) { - return pEngstate->__dceclientSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool dceclientIsPresent_DISPATCH(POBJGPU pGpu, struct OBJDCECLIENTRM *pEngstate) { return pEngstate->__dceclientIsPresent__(pGpu, pEngstate); } diff --git a/src/nvidia/generated/g_deferred_api_nvoc.c b/src/nvidia/generated/g_deferred_api_nvoc.c index 2ced6e1d6..65c7dc3af 100644 --- a/src/nvidia/generated/g_deferred_api_nvoc.c +++ b/src/nvidia/generated/g_deferred_api_nvoc.c @@ -120,7 +120,7 @@ const struct NVOC_CLASS_DEF __nvoc_class_def_DeferredApiObject = /*pExportInfo=*/ &__nvoc_export_info_DeferredApiObject }; -static NV_STATUS __nvoc_thunk_DeferredApiObject_chandesGetSwMethods(struct ChannelDescendant *pDeferredApi, METHOD **ppMethods, NvU32 *pNumMethods) { +static NV_STATUS __nvoc_thunk_DeferredApiObject_chandesGetSwMethods(struct ChannelDescendant *pDeferredApi, const METHOD **ppMethods, NvU32 *pNumMethods) { return defapiGetSwMethods((struct DeferredApiObject *)(((unsigned char *)pDeferredApi) - __nvoc_rtti_DeferredApiObject_ChannelDescendant.offset), ppMethods, pNumMethods); } @@ -212,6 +212,10 @@ static NV_STATUS __nvoc_thunk_Notifier_defapiUnregisterEvent(struct DeferredApiO return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DeferredApiObject_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_defapiControlSerialization_Prologue(struct DeferredApiObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DeferredApiObject_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_defapiCanCopy(struct DeferredApiObject *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DeferredApiObject_RsResource.offset)); } @@ -224,6 +228,10 @@ static NV_STATUS __nvoc_thunk_RsResource_defapiIsDuplicate(struct DeferredApiObj return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DeferredApiObject_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_defapiControlSerialization_Epilogue(struct DeferredApiObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DeferredApiObject_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_defapiGetNotificationListPtr(struct DeferredApiObject *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DeferredApiObject_Notifier.offset)); } @@ -395,12 +403,16 @@ static void __nvoc_init_funcTable_DeferredApiObject_1(DeferredApiObject *pThis) pThis->__defapiUnregisterEvent__ = &__nvoc_thunk_Notifier_defapiUnregisterEvent; + pThis->__defapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_defapiControlSerialization_Prologue; + pThis->__defapiCanCopy__ = &__nvoc_thunk_RsResource_defapiCanCopy; pThis->__defapiPreDestruct__ = &__nvoc_thunk_RsResource_defapiPreDestruct; pThis->__defapiIsDuplicate__ = &__nvoc_thunk_RsResource_defapiIsDuplicate; + pThis->__defapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_defapiControlSerialization_Epilogue; + pThis->__defapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_defapiGetNotificationListPtr; pThis->__defapiGetNotificationShare__ = &__nvoc_thunk_Notifier_defapiGetNotificationShare; @@ -435,13 +447,16 @@ NV_STATUS __nvoc_objCreate_DeferredApiObject(DeferredApiObject **ppThis, Dynamic DeferredApiObject *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(DeferredApiObject)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DeferredApiObject), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(DeferredApiObject)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DeferredApiObject); + pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -461,11 +476,17 @@ NV_STATUS __nvoc_objCreate_DeferredApiObject(DeferredApiObject **ppThis, Dynamic if (status != NV_OK) goto __nvoc_objCreate_DeferredApiObject_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_DeferredApiObject_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(DeferredApiObject)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_deferred_api_nvoc.h b/src/nvidia/generated/g_deferred_api_nvoc.h index e1dae0b98..6a5457317 100644 --- a/src/nvidia/generated/g_deferred_api_nvoc.h +++ b/src/nvidia/generated/g_deferred_api_nvoc.h @@ -75,7 +75,7 @@ struct DeferredApiObject { struct Notifier *__nvoc_pbase_Notifier; struct ChannelDescendant *__nvoc_pbase_ChannelDescendant; struct DeferredApiObject *__nvoc_pbase_DeferredApiObject; - NV_STATUS (*__defapiGetSwMethods__)(struct DeferredApiObject *, METHOD **, NvU32 *); + NV_STATUS (*__defapiGetSwMethods__)(struct DeferredApiObject *, const METHOD **, NvU32 *); NvBool (*__defapiIsSwMethodStalling__)(struct DeferredApiObject *, NvU32); NV_STATUS (*__defapiCtrlCmdDeferredApi__)(struct DeferredApiObject *, NV5080_CTRL_DEFERRED_API_PARAMS *); NV_STATUS (*__defapiCtrlCmdDeferredApiV2__)(struct DeferredApiObject *, NV5080_CTRL_DEFERRED_API_V2_PARAMS *); @@ -101,9 +101,11 @@ struct DeferredApiObject { NV_STATUS (*__defapiGetMemoryMappingDescriptor__)(struct DeferredApiObject *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__defapiControlFilter__)(struct DeferredApiObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__defapiUnregisterEvent__)(struct DeferredApiObject *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__defapiControlSerialization_Prologue__)(struct DeferredApiObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__defapiCanCopy__)(struct DeferredApiObject *); void (*__defapiPreDestruct__)(struct DeferredApiObject *); NV_STATUS (*__defapiIsDuplicate__)(struct DeferredApiObject *, NvHandle, NvBool *); + void (*__defapiControlSerialization_Epilogue__)(struct DeferredApiObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__defapiGetNotificationListPtr__)(struct DeferredApiObject *); struct NotifShare *(*__defapiGetNotificationShare__)(struct DeferredApiObject *); NV_STATUS (*__defapiMap__)(struct DeferredApiObject *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -166,16 +168,18 @@ NV_STATUS __nvoc_objCreate_DeferredApiObject(DeferredApiObject**, Dynamic*, NvU3 #define defapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) defapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define defapiControlFilter(pResource, pCallContext, pParams) defapiControlFilter_DISPATCH(pResource, pCallContext, pParams) #define defapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) defapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define defapiControlSerialization_Prologue(pResource, pCallContext, pParams) defapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define defapiCanCopy(pResource) defapiCanCopy_DISPATCH(pResource) #define defapiPreDestruct(pResource) defapiPreDestruct_DISPATCH(pResource) #define defapiIsDuplicate(pResource, hMemory, pDuplicate) defapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define defapiControlSerialization_Epilogue(pResource, pCallContext, pParams) defapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define defapiGetNotificationListPtr(pNotifier) defapiGetNotificationListPtr_DISPATCH(pNotifier) #define defapiGetNotificationShare(pNotifier) defapiGetNotificationShare_DISPATCH(pNotifier) #define defapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) defapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define defapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) defapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) -NV_STATUS defapiGetSwMethods_IMPL(struct DeferredApiObject *pDeferredApi, METHOD **ppMethods, NvU32 *pNumMethods); +NV_STATUS defapiGetSwMethods_IMPL(struct DeferredApiObject *pDeferredApi, const METHOD **ppMethods, NvU32 *pNumMethods); -static inline NV_STATUS defapiGetSwMethods_DISPATCH(struct DeferredApiObject *pDeferredApi, METHOD **ppMethods, NvU32 *pNumMethods) { +static inline NV_STATUS defapiGetSwMethods_DISPATCH(struct DeferredApiObject *pDeferredApi, const METHOD **ppMethods, NvU32 *pNumMethods) { return pDeferredApi->__defapiGetSwMethods__(pDeferredApi, ppMethods, pNumMethods); } @@ -287,6 +291,10 @@ static inline NV_STATUS defapiUnregisterEvent_DISPATCH(struct DeferredApiObject return pNotifier->__defapiUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS defapiControlSerialization_Prologue_DISPATCH(struct DeferredApiObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__defapiControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool defapiCanCopy_DISPATCH(struct DeferredApiObject *pResource) { return pResource->__defapiCanCopy__(pResource); } @@ -299,6 +307,10 @@ static inline NV_STATUS defapiIsDuplicate_DISPATCH(struct DeferredApiObject *pRe return pResource->__defapiIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void defapiControlSerialization_Epilogue_DISPATCH(struct DeferredApiObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__defapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *defapiGetNotificationListPtr_DISPATCH(struct DeferredApiObject *pNotifier) { return pNotifier->__defapiGetNotificationListPtr__(pNotifier); } diff --git a/src/nvidia/generated/g_device_nvoc.c b/src/nvidia/generated/g_device_nvoc.c index 28aab5673..acdcafe7f 100644 --- a/src/nvidia/generated/g_device_nvoc.c +++ b/src/nvidia/generated/g_device_nvoc.c @@ -105,6 +105,50 @@ static NvBool __nvoc_thunk_GpuResource_deviceShareCallback(struct Device *pGpuRe return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Device_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } +static NV_STATUS __nvoc_thunk_RmResource_deviceCheckMemInterUnmap(struct Device *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Device_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_deviceMapTo(struct Device *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_deviceGetMapAddrSpace(struct Device *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Device_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_deviceGetRefCount(struct Device *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_deviceAddAdditionalDependants(struct RsClient *pClient, struct Device *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_deviceControl_Prologue(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_deviceGetRegBaseOffsetAndSize(struct Device *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Device_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_RsResource_deviceUnmapFrom(struct Device *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_deviceControl_Epilogue(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_deviceControlLookup(struct Device *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset), pParams, ppEntry); +} + +static NvHandle __nvoc_thunk_GpuResource_deviceGetInternalObjectHandle(struct Device *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Device_GpuResource.offset)); +} + static NV_STATUS __nvoc_thunk_GpuResource_deviceUnmap(struct Device *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Device_GpuResource.offset), pCallContext, pCpuMapping); } @@ -117,40 +161,12 @@ static NV_STATUS __nvoc_thunk_RmResource_deviceGetMemoryMappingDescriptor(struct return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Device_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_GpuResource_deviceGetMapAddrSpace(struct Device *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Device_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvHandle __nvoc_thunk_GpuResource_deviceGetInternalObjectHandle(struct Device *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Device_GpuResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_deviceControlFilter(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_deviceAddAdditionalDependants(struct RsClient *pClient, struct Device *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_deviceGetRefCount(struct Device *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RmResource_deviceCheckMemInterUnmap(struct Device *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Device_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_deviceMapTo(struct Device *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_deviceControl_Prologue(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_GpuResource_deviceGetRegBaseOffsetAndSize(struct Device *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Device_GpuResource.offset), pGpu, pOffset, pSize); +static NV_STATUS __nvoc_thunk_RmResource_deviceControlSerialization_Prologue(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_deviceCanCopy(struct Device *pResource) { @@ -161,20 +177,12 @@ static void __nvoc_thunk_RsResource_devicePreDestruct(struct Device *pResource) resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_deviceUnmapFrom(struct Device *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_deviceIsDuplicate(struct Device *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset), hMemory, pDuplicate); } -static void __nvoc_thunk_RmResource_deviceControl_Epilogue(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_deviceControlLookup(struct Device *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_deviceControlSerialization_Epilogue(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_deviceMap(struct Device *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -192,6 +200,21 @@ static NvBool __nvoc_thunk_RmResource_deviceAccessCallback(struct Device *pResou static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] = { { /* [0] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) deviceCtrlCmdBifReset_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x800102u, + /*paramSize=*/ sizeof(NV0080_CTRL_BIF_RESET_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Device.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "deviceCtrlCmdBifReset" +#endif + }, + { /* [1] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -206,7 +229,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdBifGetDmaBaseSysmemAddr" #endif }, - { /* [1] */ + { /* [2] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -221,7 +244,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdBifAspmFeatureSupported" #endif }, - { /* [2] */ + { /* [3] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -236,7 +259,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdBifAspmCyaUpdate" #endif }, - { /* [3] */ + { /* [4] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) deviceCtrlCmdBifGetPciePowerControlMask_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*flags=*/ 0x200u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x800106u, + /*paramSize=*/ sizeof(NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Device.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "deviceCtrlCmdBifGetPciePowerControlMask" +#endif + }, + { /* [5] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -251,13 +289,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetClasslist" #endif }, - { /* [4] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + { /* [6] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) deviceCtrlCmdGpuGetNumSubdevices_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) - /*flags=*/ 0x811u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) + /*flags=*/ 0x4811u, /*accessRight=*/0x0u, /*methodId=*/ 0x800280u, /*paramSize=*/ sizeof(NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS), @@ -266,7 +304,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetNumSubdevices" #endif }, - { /* [5] */ + { /* [7] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x5u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -281,7 +319,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuModifyGpuSwStatePersistence" #endif }, - { /* [6] */ + { /* [8] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -296,13 +334,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuQueryGpuSwStatePersistence" #endif }, - { /* [7] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + { /* [9] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) deviceCtrlCmdGpuGetVirtualizationMode_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) - /*flags=*/ 0x810u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x800289u, /*paramSize=*/ sizeof(NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS), @@ -311,7 +349,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetVirtualizationMode" #endif }, - { /* [8] */ + { /* [10] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -326,7 +364,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetSparseTextureComputeMode" #endif }, - { /* [9] */ + { /* [11] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -341,7 +379,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuSetSparseTextureComputeMode" #endif }, - { /* [10] */ + { /* [12] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -356,7 +394,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetVgxCaps" #endif }, - { /* [11] */ + { /* [13] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -371,7 +409,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetSriovCaps" #endif }, - { /* [12] */ + { /* [14] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -386,7 +424,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetClasslistV2" #endif }, - { /* [13] */ + { /* [15] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -401,7 +439,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetFindSubDeviceHandle" #endif }, - { /* [14] */ + { /* [16] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x211u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -416,7 +454,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetBrandCaps" #endif }, - { /* [15] */ + { /* [17] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -431,7 +469,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuSetVgpuVfBar1Size" #endif }, - { /* [16] */ + { /* [18] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x812u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -446,7 +484,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdKGrGetCaps" #endif }, - { /* [17] */ + { /* [19] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -461,7 +499,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdKGrGetInfo" #endif }, - { /* [18] */ + { /* [20] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -476,7 +514,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdKGrGetTpcPartitionMode" #endif }, - { /* [19] */ + { /* [21] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -491,7 +529,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdKGrSetTpcPartitionMode" #endif }, - { /* [20] */ + { /* [22] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x812u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -506,7 +544,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdKGrGetCapsV2" #endif }, - { /* [21] */ + { /* [23] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -521,13 +559,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdKGrGetInfoV2" #endif }, - { /* [22] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + { /* [24] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) deviceCtrlCmdFbGetCaps_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) - /*flags=*/ 0x11u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x801301u, /*paramSize=*/ sizeof(NV0080_CTRL_FB_GET_CAPS_PARAMS), @@ -536,7 +574,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFbGetCaps" #endif }, - { /* [23] */ + { /* [25] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -551,13 +589,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFbGetCompbitStoreInfo" #endif }, - { /* [24] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + { /* [26] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) deviceCtrlCmdFbGetCapsV2_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) - /*flags=*/ 0x11u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x801307u, /*paramSize=*/ sizeof(NV0080_CTRL_FB_GET_CAPS_V2_PARAMS), @@ -566,13 +604,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFbGetCapsV2" #endif }, - { /* [25] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + { /* [27] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) deviceCtrlCmdHostGetCaps_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) - /*flags=*/ 0x810u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x801401u, /*paramSize=*/ sizeof(NV0080_CTRL_HOST_GET_CAPS_PARAMS), @@ -581,13 +619,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdHostGetCaps" #endif }, - { /* [26] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + { /* [28] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) deviceCtrlCmdHostGetCapsV2_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) - /*flags=*/ 0x810u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4850u) + /*flags=*/ 0x4850u, /*accessRight=*/0x0u, /*methodId=*/ 0x801402u, /*paramSize=*/ sizeof(NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS), @@ -596,7 +634,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdHostGetCapsV2" #endif }, - { /* [27] */ + { /* [29] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -611,7 +649,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoGetCaps" #endif }, - { /* [28] */ + { /* [30] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -626,7 +664,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoStartSelectedChannels" #endif }, - { /* [29] */ + { /* [31] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -641,13 +679,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoGetEngineContextProperties" #endif }, - { /* [30] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + { /* [32] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) deviceCtrlCmdFifoGetChannelList_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) - /*flags=*/ 0x810u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x80170du, /*paramSize=*/ sizeof(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS), @@ -656,7 +694,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoGetChannelList" #endif }, - { /* [31] */ + { /* [33] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2211u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -671,7 +709,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoGetLatencyBufferSize" #endif }, - { /* [32] */ + { /* [34] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -686,7 +724,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoSetChannelProperties" #endif }, - { /* [33] */ + { /* [35] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -701,7 +739,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoStopRunlist" #endif }, - { /* [34] */ + { /* [36] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -716,7 +754,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoStartRunlist" #endif }, - { /* [35] */ + { /* [37] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -731,7 +769,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoGetCapsV2" #endif }, - { /* [36] */ + { /* [38] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -746,7 +784,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoIdleChannels" #endif }, - { /* [37] */ + { /* [39] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -761,7 +799,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaGetPteInfo" #endif }, - { /* [38] */ + { /* [40] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -776,7 +814,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaFlush" #endif }, - { /* [39] */ + { /* [41] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -791,7 +829,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaAdvSchedGetVaCaps" #endif }, - { /* [40] */ + { /* [42] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -806,7 +844,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaGetPdeInfo" #endif }, - { /* [41] */ + { /* [43] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -821,7 +859,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaSetPteInfo" #endif }, - { /* [42] */ + { /* [44] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -836,7 +874,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaInvalidateTLB" #endif }, - { /* [43] */ + { /* [45] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -851,7 +889,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaGetCaps" #endif }, - { /* [44] */ + { /* [46] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -866,7 +904,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaSetVASpaceSize" #endif }, - { /* [45] */ + { /* [47] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -881,7 +919,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaUpdatePde2" #endif }, - { /* [46] */ + { /* [48] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -896,7 +934,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaEnablePrivilegedRange" #endif }, - { /* [47] */ + { /* [49] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c0000u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -911,7 +949,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaSetDefaultVASpace" #endif }, - { /* [48] */ + { /* [50] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -926,7 +964,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaSetPageDirectory" #endif }, - { /* [49] */ + { /* [51] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -941,7 +979,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaUnsetPageDirectory" #endif }, - { /* [50] */ + { /* [52] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -956,7 +994,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdMsencGetCaps" #endif }, - { /* [51] */ + { /* [53] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -971,7 +1009,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdBspGetCapsV2" #endif }, - { /* [52] */ + { /* [54] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -986,7 +1024,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdOsUnixVTSwitch" #endif }, - { /* [53] */ + { /* [55] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1001,7 +1039,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdOsUnixVTGetFBInfo" #endif }, - { /* [54] */ + { /* [56] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1016,7 +1054,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdNvjpgGetCapsV2" #endif }, - { /* [55] */ + { /* [57] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1031,7 +1069,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdInternalPerfCudaLimitDisable" #endif }, - { /* [56] */ + { /* [58] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1046,7 +1084,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdInternalPerfGetUnderpoweredGpuCount" #endif }, - { /* [57] */ + { /* [59] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1066,7 +1104,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] const struct NVOC_EXPORT_INFO __nvoc_export_info_Device = { - /*numEntries=*/ 58, + /*numEntries=*/ 60, /*pExportEntries=*/ __nvoc_exported_method_def_Device }; @@ -1107,6 +1145,10 @@ static void __nvoc_init_funcTable_Device_1(Device *pThis) { pThis->__deviceInternalControlForward__ = &deviceInternalControlForward_IMPL; +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + pThis->__deviceCtrlCmdBifReset__ = &deviceCtrlCmdBifReset_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) pThis->__deviceCtrlCmdBifGetDmaBaseSysmemAddr__ = &deviceCtrlCmdBifGetDmaBaseSysmemAddr_IMPL; #endif @@ -1119,6 +1161,10 @@ static void __nvoc_init_funcTable_Device_1(Device *pThis) { pThis->__deviceCtrlCmdBifAspmCyaUpdate__ = &deviceCtrlCmdBifAspmCyaUpdate_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + pThis->__deviceCtrlCmdBifGetPciePowerControlMask__ = &deviceCtrlCmdBifGetPciePowerControlMask_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__deviceCtrlCmdDmaGetPteInfo__ = &deviceCtrlCmdDmaGetPteInfo_IMPL; #endif @@ -1199,11 +1245,11 @@ static void __nvoc_init_funcTable_Device_1(Device *pThis) { pThis->__deviceCtrlCmdFbGetCompbitStoreInfo__ = &deviceCtrlCmdFbGetCompbitStoreInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__deviceCtrlCmdFbGetCaps__ = &deviceCtrlCmdFbGetCaps_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__deviceCtrlCmdFbGetCapsV2__ = &deviceCtrlCmdFbGetCapsV2_IMPL; #endif @@ -1231,7 +1277,7 @@ static void __nvoc_init_funcTable_Device_1(Device *pThis) { pThis->__deviceCtrlCmdFifoStartRunlist__ = &deviceCtrlCmdFifoStartRunlist_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__deviceCtrlCmdFifoGetChannelList__ = &deviceCtrlCmdFifoGetChannelList_IMPL; #endif @@ -1247,11 +1293,11 @@ static void __nvoc_init_funcTable_Device_1(Device *pThis) { pThis->__deviceCtrlCmdFifoIdleChannels__ = &deviceCtrlCmdFifoIdleChannels_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__deviceCtrlCmdHostGetCaps__ = &deviceCtrlCmdHostGetCaps_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4850u) pThis->__deviceCtrlCmdHostGetCapsV2__ = &deviceCtrlCmdHostGetCapsV2_IMPL; #endif @@ -1275,7 +1321,7 @@ static void __nvoc_init_funcTable_Device_1(Device *pThis) { pThis->__deviceCtrlCmdGpuGetClasslistV2__ = &deviceCtrlCmdGpuGetClasslistV2_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) pThis->__deviceCtrlCmdGpuGetNumSubdevices__ = &deviceCtrlCmdGpuGetNumSubdevices_IMPL; #endif @@ -1287,7 +1333,7 @@ static void __nvoc_init_funcTable_Device_1(Device *pThis) { pThis->__deviceCtrlCmdGpuQueryGpuSwStatePersistence__ = &deviceCtrlCmdGpuQueryGpuSwStatePersistence_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__deviceCtrlCmdGpuGetVirtualizationMode__ = &deviceCtrlCmdGpuGetVirtualizationMode_IMPL; #endif @@ -1345,41 +1391,45 @@ static void __nvoc_init_funcTable_Device_1(Device *pThis) { pThis->__deviceShareCallback__ = &__nvoc_thunk_GpuResource_deviceShareCallback; + pThis->__deviceCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_deviceCheckMemInterUnmap; + + pThis->__deviceMapTo__ = &__nvoc_thunk_RsResource_deviceMapTo; + + pThis->__deviceGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_deviceGetMapAddrSpace; + + pThis->__deviceGetRefCount__ = &__nvoc_thunk_RsResource_deviceGetRefCount; + + pThis->__deviceAddAdditionalDependants__ = &__nvoc_thunk_RsResource_deviceAddAdditionalDependants; + + pThis->__deviceControl_Prologue__ = &__nvoc_thunk_RmResource_deviceControl_Prologue; + + pThis->__deviceGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_deviceGetRegBaseOffsetAndSize; + + pThis->__deviceUnmapFrom__ = &__nvoc_thunk_RsResource_deviceUnmapFrom; + + pThis->__deviceControl_Epilogue__ = &__nvoc_thunk_RmResource_deviceControl_Epilogue; + + pThis->__deviceControlLookup__ = &__nvoc_thunk_RsResource_deviceControlLookup; + + pThis->__deviceGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_deviceGetInternalObjectHandle; + pThis->__deviceUnmap__ = &__nvoc_thunk_GpuResource_deviceUnmap; pThis->__deviceGetMemInterMapParams__ = &__nvoc_thunk_RmResource_deviceGetMemInterMapParams; pThis->__deviceGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_deviceGetMemoryMappingDescriptor; - pThis->__deviceGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_deviceGetMapAddrSpace; - - pThis->__deviceGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_deviceGetInternalObjectHandle; - pThis->__deviceControlFilter__ = &__nvoc_thunk_RsResource_deviceControlFilter; - pThis->__deviceAddAdditionalDependants__ = &__nvoc_thunk_RsResource_deviceAddAdditionalDependants; - - pThis->__deviceGetRefCount__ = &__nvoc_thunk_RsResource_deviceGetRefCount; - - pThis->__deviceCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_deviceCheckMemInterUnmap; - - pThis->__deviceMapTo__ = &__nvoc_thunk_RsResource_deviceMapTo; - - pThis->__deviceControl_Prologue__ = &__nvoc_thunk_RmResource_deviceControl_Prologue; - - pThis->__deviceGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_deviceGetRegBaseOffsetAndSize; + pThis->__deviceControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_deviceControlSerialization_Prologue; pThis->__deviceCanCopy__ = &__nvoc_thunk_RsResource_deviceCanCopy; pThis->__devicePreDestruct__ = &__nvoc_thunk_RsResource_devicePreDestruct; - pThis->__deviceUnmapFrom__ = &__nvoc_thunk_RsResource_deviceUnmapFrom; - pThis->__deviceIsDuplicate__ = &__nvoc_thunk_RsResource_deviceIsDuplicate; - pThis->__deviceControl_Epilogue__ = &__nvoc_thunk_RmResource_deviceControl_Epilogue; - - pThis->__deviceControlLookup__ = &__nvoc_thunk_RsResource_deviceControlLookup; + pThis->__deviceControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_deviceControlSerialization_Epilogue; pThis->__deviceMap__ = &__nvoc_thunk_GpuResource_deviceMap; @@ -1407,13 +1457,16 @@ NV_STATUS __nvoc_objCreate_Device(Device **ppThis, Dynamic *pParent, NvU32 creat Object *pParentObj; Device *pThis; - pThis = portMemAllocNonPaged(sizeof(Device)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Device), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(Device)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Device); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -1429,11 +1482,17 @@ NV_STATUS __nvoc_objCreate_Device(Device **ppThis, Dynamic *pParent, NvU32 creat if (status != NV_OK) goto __nvoc_objCreate_Device_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_Device_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(Device)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_device_nvoc.h b/src/nvidia/generated/g_device_nvoc.h index 6dd1b5a7f..99d7b0171 100644 --- a/src/nvidia/generated/g_device_nvoc.h +++ b/src/nvidia/generated/g_device_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -83,9 +83,11 @@ struct Device { struct Device *__nvoc_pbase_Device; NV_STATUS (*__deviceControl__)(struct Device *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__deviceInternalControlForward__)(struct Device *, NvU32, void *, NvU32); + NV_STATUS (*__deviceCtrlCmdBifReset__)(struct Device *, NV0080_CTRL_BIF_RESET_PARAMS *); NV_STATUS (*__deviceCtrlCmdBifGetDmaBaseSysmemAddr__)(struct Device *, NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS *); NV_STATUS (*__deviceCtrlCmdBifAspmFeatureSupported__)(struct Device *, NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS *); NV_STATUS (*__deviceCtrlCmdBifAspmCyaUpdate__)(struct Device *, NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS *); + NV_STATUS (*__deviceCtrlCmdBifGetPciePowerControlMask__)(struct Device *, NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS *); NV_STATUS (*__deviceCtrlCmdDmaGetPteInfo__)(struct Device *, NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS *); NV_STATUS (*__deviceCtrlCmdDmaUpdatePde2__)(struct Device *, NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *); NV_STATUS (*__deviceCtrlCmdDmaSetPageDirectory__)(struct Device *, NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS *); @@ -142,24 +144,26 @@ struct Device { NV_STATUS (*__deviceCtrlCmdOsUnixVTSwitch__)(struct Device *, NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS *); NV_STATUS (*__deviceCtrlCmdOsUnixVTGetFBInfo__)(struct Device *, NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS *); NvBool (*__deviceShareCallback__)(struct Device *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__deviceCheckMemInterUnmap__)(struct Device *, NvBool); + NV_STATUS (*__deviceMapTo__)(struct Device *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__deviceGetMapAddrSpace__)(struct Device *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__deviceGetRefCount__)(struct Device *); + void (*__deviceAddAdditionalDependants__)(struct RsClient *, struct Device *, RsResourceRef *); + NV_STATUS (*__deviceControl_Prologue__)(struct Device *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__deviceGetRegBaseOffsetAndSize__)(struct Device *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__deviceUnmapFrom__)(struct Device *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__deviceControl_Epilogue__)(struct Device *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__deviceControlLookup__)(struct Device *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__deviceGetInternalObjectHandle__)(struct Device *); NV_STATUS (*__deviceUnmap__)(struct Device *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__deviceGetMemInterMapParams__)(struct Device *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__deviceGetMemoryMappingDescriptor__)(struct Device *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__deviceGetMapAddrSpace__)(struct Device *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__deviceGetInternalObjectHandle__)(struct Device *); NV_STATUS (*__deviceControlFilter__)(struct Device *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__deviceAddAdditionalDependants__)(struct RsClient *, struct Device *, RsResourceRef *); - NvU32 (*__deviceGetRefCount__)(struct Device *); - NV_STATUS (*__deviceCheckMemInterUnmap__)(struct Device *, NvBool); - NV_STATUS (*__deviceMapTo__)(struct Device *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__deviceControl_Prologue__)(struct Device *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__deviceGetRegBaseOffsetAndSize__)(struct Device *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__deviceControlSerialization_Prologue__)(struct Device *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__deviceCanCopy__)(struct Device *); void (*__devicePreDestruct__)(struct Device *); - NV_STATUS (*__deviceUnmapFrom__)(struct Device *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__deviceIsDuplicate__)(struct Device *, NvHandle, NvBool *); - void (*__deviceControl_Epilogue__)(struct Device *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__deviceControlLookup__)(struct Device *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__deviceControlSerialization_Epilogue__)(struct Device *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__deviceMap__)(struct Device *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__deviceAccessCallback__)(struct Device *, struct RsClient *, void *, RsAccessRight); NvU32 deviceInst; @@ -212,9 +216,11 @@ NV_STATUS __nvoc_objCreate_Device(Device**, Dynamic*, NvU32, struct CALL_CONTEXT #define deviceControl(pResource, pCallContext, pParams) deviceControl_DISPATCH(pResource, pCallContext, pParams) #define deviceInternalControlForward(pDevice, command, pParams, size) deviceInternalControlForward_DISPATCH(pDevice, command, pParams, size) +#define deviceCtrlCmdBifReset(pDevice, pBifResetParams) deviceCtrlCmdBifReset_DISPATCH(pDevice, pBifResetParams) #define deviceCtrlCmdBifGetDmaBaseSysmemAddr(pDevice, pBifDmaBaseSysmemParams) deviceCtrlCmdBifGetDmaBaseSysmemAddr_DISPATCH(pDevice, pBifDmaBaseSysmemParams) #define deviceCtrlCmdBifAspmFeatureSupported(pDevice, pBifAspmParams) deviceCtrlCmdBifAspmFeatureSupported_DISPATCH(pDevice, pBifAspmParams) #define deviceCtrlCmdBifAspmCyaUpdate(pDevice, pBifAspmCyaParams) deviceCtrlCmdBifAspmCyaUpdate_DISPATCH(pDevice, pBifAspmCyaParams) +#define deviceCtrlCmdBifGetPciePowerControlMask(pDevice, pBifPciePowerControlParams) deviceCtrlCmdBifGetPciePowerControlMask_DISPATCH(pDevice, pBifPciePowerControlParams) #define deviceCtrlCmdDmaGetPteInfo(pDevice, pParams) deviceCtrlCmdDmaGetPteInfo_DISPATCH(pDevice, pParams) #define deviceCtrlCmdDmaUpdatePde2(pDevice, pParams) deviceCtrlCmdDmaUpdatePde2_DISPATCH(pDevice, pParams) #define deviceCtrlCmdDmaSetPageDirectory(pDevice, pParams) deviceCtrlCmdDmaSetPageDirectory_DISPATCH(pDevice, pParams) @@ -271,24 +277,26 @@ NV_STATUS __nvoc_objCreate_Device(Device**, Dynamic*, NvU32, struct CALL_CONTEXT #define deviceCtrlCmdOsUnixVTSwitch(pDevice, pParams) deviceCtrlCmdOsUnixVTSwitch_DISPATCH(pDevice, pParams) #define deviceCtrlCmdOsUnixVTGetFBInfo(pDevice, pParams) deviceCtrlCmdOsUnixVTGetFBInfo_DISPATCH(pDevice, pParams) #define deviceShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) deviceShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define deviceCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) deviceCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define deviceMapTo(pResource, pParams) deviceMapTo_DISPATCH(pResource, pParams) +#define deviceGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) deviceGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define deviceGetRefCount(pResource) deviceGetRefCount_DISPATCH(pResource) +#define deviceAddAdditionalDependants(pClient, pResource, pReference) deviceAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define deviceControl_Prologue(pResource, pCallContext, pParams) deviceControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define deviceGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) deviceGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define deviceUnmapFrom(pResource, pParams) deviceUnmapFrom_DISPATCH(pResource, pParams) +#define deviceControl_Epilogue(pResource, pCallContext, pParams) deviceControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define deviceControlLookup(pResource, pParams, ppEntry) deviceControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define deviceGetInternalObjectHandle(pGpuResource) deviceGetInternalObjectHandle_DISPATCH(pGpuResource) #define deviceUnmap(pGpuResource, pCallContext, pCpuMapping) deviceUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define deviceGetMemInterMapParams(pRmResource, pParams) deviceGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define deviceGetMemoryMappingDescriptor(pRmResource, ppMemDesc) deviceGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define deviceGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) deviceGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define deviceGetInternalObjectHandle(pGpuResource) deviceGetInternalObjectHandle_DISPATCH(pGpuResource) #define deviceControlFilter(pResource, pCallContext, pParams) deviceControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define deviceAddAdditionalDependants(pClient, pResource, pReference) deviceAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define deviceGetRefCount(pResource) deviceGetRefCount_DISPATCH(pResource) -#define deviceCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) deviceCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define deviceMapTo(pResource, pParams) deviceMapTo_DISPATCH(pResource, pParams) -#define deviceControl_Prologue(pResource, pCallContext, pParams) deviceControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define deviceGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) deviceGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define deviceControlSerialization_Prologue(pResource, pCallContext, pParams) deviceControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define deviceCanCopy(pResource) deviceCanCopy_DISPATCH(pResource) #define devicePreDestruct(pResource) devicePreDestruct_DISPATCH(pResource) -#define deviceUnmapFrom(pResource, pParams) deviceUnmapFrom_DISPATCH(pResource, pParams) #define deviceIsDuplicate(pResource, hMemory, pDuplicate) deviceIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) -#define deviceControl_Epilogue(pResource, pCallContext, pParams) deviceControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define deviceControlLookup(pResource, pParams, ppEntry) deviceControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define deviceControlSerialization_Epilogue(pResource, pCallContext, pParams) deviceControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define deviceMap(pGpuResource, pCallContext, pParams, pCpuMapping) deviceMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define deviceAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) deviceAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS deviceControl_IMPL(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); @@ -303,6 +311,12 @@ static inline NV_STATUS deviceInternalControlForward_DISPATCH(struct Device *pDe return pDevice->__deviceInternalControlForward__(pDevice, command, pParams, size); } +NV_STATUS deviceCtrlCmdBifReset_IMPL(struct Device *pDevice, NV0080_CTRL_BIF_RESET_PARAMS *pBifResetParams); + +static inline NV_STATUS deviceCtrlCmdBifReset_DISPATCH(struct Device *pDevice, NV0080_CTRL_BIF_RESET_PARAMS *pBifResetParams) { + return pDevice->__deviceCtrlCmdBifReset__(pDevice, pBifResetParams); +} + NV_STATUS deviceCtrlCmdBifGetDmaBaseSysmemAddr_IMPL(struct Device *pDevice, NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS *pBifDmaBaseSysmemParams); static inline NV_STATUS deviceCtrlCmdBifGetDmaBaseSysmemAddr_DISPATCH(struct Device *pDevice, NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR_PARAMS *pBifDmaBaseSysmemParams) { @@ -321,6 +335,12 @@ static inline NV_STATUS deviceCtrlCmdBifAspmCyaUpdate_DISPATCH(struct Device *pD return pDevice->__deviceCtrlCmdBifAspmCyaUpdate__(pDevice, pBifAspmCyaParams); } +NV_STATUS deviceCtrlCmdBifGetPciePowerControlMask_IMPL(struct Device *pDevice, NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS *pBifPciePowerControlParams); + +static inline NV_STATUS deviceCtrlCmdBifGetPciePowerControlMask_DISPATCH(struct Device *pDevice, NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS *pBifPciePowerControlParams) { + return pDevice->__deviceCtrlCmdBifGetPciePowerControlMask__(pDevice, pBifPciePowerControlParams); +} + NV_STATUS deviceCtrlCmdDmaGetPteInfo_IMPL(struct Device *pDevice, NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS *pParams); static inline NV_STATUS deviceCtrlCmdDmaGetPteInfo_DISPATCH(struct Device *pDevice, NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS *pParams) { @@ -655,6 +675,50 @@ static inline NvBool deviceShareCallback_DISPATCH(struct Device *pGpuResource, s return pGpuResource->__deviceShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } +static inline NV_STATUS deviceCheckMemInterUnmap_DISPATCH(struct Device *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__deviceCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS deviceMapTo_DISPATCH(struct Device *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__deviceMapTo__(pResource, pParams); +} + +static inline NV_STATUS deviceGetMapAddrSpace_DISPATCH(struct Device *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__deviceGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 deviceGetRefCount_DISPATCH(struct Device *pResource) { + return pResource->__deviceGetRefCount__(pResource); +} + +static inline void deviceAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct Device *pResource, RsResourceRef *pReference) { + pResource->__deviceAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS deviceControl_Prologue_DISPATCH(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__deviceControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS deviceGetRegBaseOffsetAndSize_DISPATCH(struct Device *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__deviceGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS deviceUnmapFrom_DISPATCH(struct Device *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__deviceUnmapFrom__(pResource, pParams); +} + +static inline void deviceControl_Epilogue_DISPATCH(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__deviceControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS deviceControlLookup_DISPATCH(struct Device *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__deviceControlLookup__(pResource, pParams, ppEntry); +} + +static inline NvHandle deviceGetInternalObjectHandle_DISPATCH(struct Device *pGpuResource) { + return pGpuResource->__deviceGetInternalObjectHandle__(pGpuResource); +} + static inline NV_STATUS deviceUnmap_DISPATCH(struct Device *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { return pGpuResource->__deviceUnmap__(pGpuResource, pCallContext, pCpuMapping); } @@ -667,40 +731,12 @@ static inline NV_STATUS deviceGetMemoryMappingDescriptor_DISPATCH(struct Device return pRmResource->__deviceGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS deviceGetMapAddrSpace_DISPATCH(struct Device *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__deviceGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvHandle deviceGetInternalObjectHandle_DISPATCH(struct Device *pGpuResource) { - return pGpuResource->__deviceGetInternalObjectHandle__(pGpuResource); -} - static inline NV_STATUS deviceControlFilter_DISPATCH(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__deviceControlFilter__(pResource, pCallContext, pParams); } -static inline void deviceAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct Device *pResource, RsResourceRef *pReference) { - pResource->__deviceAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 deviceGetRefCount_DISPATCH(struct Device *pResource) { - return pResource->__deviceGetRefCount__(pResource); -} - -static inline NV_STATUS deviceCheckMemInterUnmap_DISPATCH(struct Device *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__deviceCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS deviceMapTo_DISPATCH(struct Device *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__deviceMapTo__(pResource, pParams); -} - -static inline NV_STATUS deviceControl_Prologue_DISPATCH(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__deviceControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS deviceGetRegBaseOffsetAndSize_DISPATCH(struct Device *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__deviceGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +static inline NV_STATUS deviceControlSerialization_Prologue_DISPATCH(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__deviceControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool deviceCanCopy_DISPATCH(struct Device *pResource) { @@ -711,20 +747,12 @@ static inline void devicePreDestruct_DISPATCH(struct Device *pResource) { pResource->__devicePreDestruct__(pResource); } -static inline NV_STATUS deviceUnmapFrom_DISPATCH(struct Device *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__deviceUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS deviceIsDuplicate_DISPATCH(struct Device *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__deviceIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline void deviceControl_Epilogue_DISPATCH(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__deviceControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS deviceControlLookup_DISPATCH(struct Device *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__deviceControlLookup__(pResource, pParams, ppEntry); +static inline void deviceControlSerialization_Epilogue_DISPATCH(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__deviceControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS deviceMap_DISPATCH(struct Device *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_disp_capabilities_nvoc.c b/src/nvidia/generated/g_disp_capabilities_nvoc.c index 1255696f7..c5a8e6742 100644 --- a/src/nvidia/generated/g_disp_capabilities_nvoc.c +++ b/src/nvidia/generated/g_disp_capabilities_nvoc.c @@ -101,6 +101,50 @@ static NvBool __nvoc_thunk_GpuResource_dispcapShareCallback(struct DispCapabilit return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispCapabilities_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } +static NV_STATUS __nvoc_thunk_RmResource_dispcapCheckMemInterUnmap(struct DispCapabilities *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispCapabilities_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispcapMapTo(struct DispCapabilities *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_dispcapGetMapAddrSpace(struct DispCapabilities *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispCapabilities_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_dispcapGetRefCount(struct DispCapabilities *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_dispcapAddAdditionalDependants(struct RsClient *pClient, struct DispCapabilities *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_dispcapControl_Prologue(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_dispcapInternalControlForward(struct DispCapabilities *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispCapabilities_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispcapUnmapFrom(struct DispCapabilities *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_dispcapControl_Epilogue(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispcapControlLookup(struct DispCapabilities *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset), pParams, ppEntry); +} + +static NvHandle __nvoc_thunk_GpuResource_dispcapGetInternalObjectHandle(struct DispCapabilities *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispCapabilities_GpuResource.offset)); +} + static NV_STATUS __nvoc_thunk_GpuResource_dispcapControl(struct DispCapabilities *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispCapabilities_GpuResource.offset), pCallContext, pParams); } @@ -117,64 +161,28 @@ static NV_STATUS __nvoc_thunk_RmResource_dispcapGetMemoryMappingDescriptor(struc return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispCapabilities_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_GpuResource_dispcapGetMapAddrSpace(struct DispCapabilities *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispCapabilities_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvHandle __nvoc_thunk_GpuResource_dispcapGetInternalObjectHandle(struct DispCapabilities *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispCapabilities_GpuResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_dispcapControlFilter(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_dispcapAddAdditionalDependants(struct RsClient *pClient, struct DispCapabilities *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_dispcapGetRefCount(struct DispCapabilities *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RmResource_dispcapCheckMemInterUnmap(struct DispCapabilities *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispCapabilities_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_dispcapMapTo(struct DispCapabilities *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_dispcapControl_Prologue(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RmResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_dispcapControlSerialization_Prologue(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_dispcapCanCopy(struct DispCapabilities *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_dispcapInternalControlForward(struct DispCapabilities *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispCapabilities_GpuResource.offset), command, pParams, size); -} - static void __nvoc_thunk_RsResource_dispcapPreDestruct(struct DispCapabilities *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_dispcapUnmapFrom(struct DispCapabilities *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_dispcapIsDuplicate(struct DispCapabilities *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset), hMemory, pDuplicate); } -static void __nvoc_thunk_RmResource_dispcapControl_Epilogue(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_dispcapControlLookup(struct DispCapabilities *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_dispcapControlSerialization_Epilogue(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_dispcapMap(struct DispCapabilities *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -229,6 +237,28 @@ static void __nvoc_init_funcTable_DispCapabilities_1(DispCapabilities *pThis) { pThis->__dispcapShareCallback__ = &__nvoc_thunk_GpuResource_dispcapShareCallback; + pThis->__dispcapCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispcapCheckMemInterUnmap; + + pThis->__dispcapMapTo__ = &__nvoc_thunk_RsResource_dispcapMapTo; + + pThis->__dispcapGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_dispcapGetMapAddrSpace; + + pThis->__dispcapGetRefCount__ = &__nvoc_thunk_RsResource_dispcapGetRefCount; + + pThis->__dispcapAddAdditionalDependants__ = &__nvoc_thunk_RsResource_dispcapAddAdditionalDependants; + + pThis->__dispcapControl_Prologue__ = &__nvoc_thunk_RmResource_dispcapControl_Prologue; + + pThis->__dispcapInternalControlForward__ = &__nvoc_thunk_GpuResource_dispcapInternalControlForward; + + pThis->__dispcapUnmapFrom__ = &__nvoc_thunk_RsResource_dispcapUnmapFrom; + + pThis->__dispcapControl_Epilogue__ = &__nvoc_thunk_RmResource_dispcapControl_Epilogue; + + pThis->__dispcapControlLookup__ = &__nvoc_thunk_RsResource_dispcapControlLookup; + + pThis->__dispcapGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_dispcapGetInternalObjectHandle; + pThis->__dispcapControl__ = &__nvoc_thunk_GpuResource_dispcapControl; pThis->__dispcapUnmap__ = &__nvoc_thunk_GpuResource_dispcapUnmap; @@ -237,35 +267,17 @@ static void __nvoc_init_funcTable_DispCapabilities_1(DispCapabilities *pThis) { pThis->__dispcapGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_dispcapGetMemoryMappingDescriptor; - pThis->__dispcapGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_dispcapGetMapAddrSpace; - - pThis->__dispcapGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_dispcapGetInternalObjectHandle; - pThis->__dispcapControlFilter__ = &__nvoc_thunk_RsResource_dispcapControlFilter; - pThis->__dispcapAddAdditionalDependants__ = &__nvoc_thunk_RsResource_dispcapAddAdditionalDependants; - - pThis->__dispcapGetRefCount__ = &__nvoc_thunk_RsResource_dispcapGetRefCount; - - pThis->__dispcapCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispcapCheckMemInterUnmap; - - pThis->__dispcapMapTo__ = &__nvoc_thunk_RsResource_dispcapMapTo; - - pThis->__dispcapControl_Prologue__ = &__nvoc_thunk_RmResource_dispcapControl_Prologue; + pThis->__dispcapControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_dispcapControlSerialization_Prologue; pThis->__dispcapCanCopy__ = &__nvoc_thunk_RsResource_dispcapCanCopy; - pThis->__dispcapInternalControlForward__ = &__nvoc_thunk_GpuResource_dispcapInternalControlForward; - pThis->__dispcapPreDestruct__ = &__nvoc_thunk_RsResource_dispcapPreDestruct; - pThis->__dispcapUnmapFrom__ = &__nvoc_thunk_RsResource_dispcapUnmapFrom; - pThis->__dispcapIsDuplicate__ = &__nvoc_thunk_RsResource_dispcapIsDuplicate; - pThis->__dispcapControl_Epilogue__ = &__nvoc_thunk_RmResource_dispcapControl_Epilogue; - - pThis->__dispcapControlLookup__ = &__nvoc_thunk_RsResource_dispcapControlLookup; + pThis->__dispcapControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_dispcapControlSerialization_Epilogue; pThis->__dispcapMap__ = &__nvoc_thunk_GpuResource_dispcapMap; @@ -293,13 +305,16 @@ NV_STATUS __nvoc_objCreate_DispCapabilities(DispCapabilities **ppThis, Dynamic * Object *pParentObj; DispCapabilities *pThis; - pThis = portMemAllocNonPaged(sizeof(DispCapabilities)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DispCapabilities), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(DispCapabilities)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DispCapabilities); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -315,11 +330,17 @@ NV_STATUS __nvoc_objCreate_DispCapabilities(DispCapabilities **ppThis, Dynamic * if (status != NV_OK) goto __nvoc_objCreate_DispCapabilities_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_DispCapabilities_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(DispCapabilities)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_disp_capabilities_nvoc.h b/src/nvidia/generated/g_disp_capabilities_nvoc.h index a8884e085..4869f5490 100644 --- a/src/nvidia/generated/g_disp_capabilities_nvoc.h +++ b/src/nvidia/generated/g_disp_capabilities_nvoc.h @@ -62,25 +62,27 @@ struct DispCapabilities { struct DispCapabilities *__nvoc_pbase_DispCapabilities; NV_STATUS (*__dispcapGetRegBaseOffsetAndSize__)(struct DispCapabilities *, struct OBJGPU *, NvU32 *, NvU32 *); NvBool (*__dispcapShareCallback__)(struct DispCapabilities *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__dispcapCheckMemInterUnmap__)(struct DispCapabilities *, NvBool); + NV_STATUS (*__dispcapMapTo__)(struct DispCapabilities *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__dispcapGetMapAddrSpace__)(struct DispCapabilities *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__dispcapGetRefCount__)(struct DispCapabilities *); + void (*__dispcapAddAdditionalDependants__)(struct RsClient *, struct DispCapabilities *, RsResourceRef *); + NV_STATUS (*__dispcapControl_Prologue__)(struct DispCapabilities *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispcapInternalControlForward__)(struct DispCapabilities *, NvU32, void *, NvU32); + NV_STATUS (*__dispcapUnmapFrom__)(struct DispCapabilities *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__dispcapControl_Epilogue__)(struct DispCapabilities *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispcapControlLookup__)(struct DispCapabilities *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__dispcapGetInternalObjectHandle__)(struct DispCapabilities *); NV_STATUS (*__dispcapControl__)(struct DispCapabilities *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispcapUnmap__)(struct DispCapabilities *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__dispcapGetMemInterMapParams__)(struct DispCapabilities *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__dispcapGetMemoryMappingDescriptor__)(struct DispCapabilities *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__dispcapGetMapAddrSpace__)(struct DispCapabilities *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__dispcapGetInternalObjectHandle__)(struct DispCapabilities *); NV_STATUS (*__dispcapControlFilter__)(struct DispCapabilities *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__dispcapAddAdditionalDependants__)(struct RsClient *, struct DispCapabilities *, RsResourceRef *); - NvU32 (*__dispcapGetRefCount__)(struct DispCapabilities *); - NV_STATUS (*__dispcapCheckMemInterUnmap__)(struct DispCapabilities *, NvBool); - NV_STATUS (*__dispcapMapTo__)(struct DispCapabilities *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__dispcapControl_Prologue__)(struct DispCapabilities *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispcapControlSerialization_Prologue__)(struct DispCapabilities *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispcapCanCopy__)(struct DispCapabilities *); - NV_STATUS (*__dispcapInternalControlForward__)(struct DispCapabilities *, NvU32, void *, NvU32); void (*__dispcapPreDestruct__)(struct DispCapabilities *); - NV_STATUS (*__dispcapUnmapFrom__)(struct DispCapabilities *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__dispcapIsDuplicate__)(struct DispCapabilities *, NvHandle, NvBool *); - void (*__dispcapControl_Epilogue__)(struct DispCapabilities *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__dispcapControlLookup__)(struct DispCapabilities *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__dispcapControlSerialization_Epilogue__)(struct DispCapabilities *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispcapMap__)(struct DispCapabilities *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__dispcapAccessCallback__)(struct DispCapabilities *, struct RsClient *, void *, RsAccessRight); NvU32 ControlOffset; @@ -117,25 +119,27 @@ NV_STATUS __nvoc_objCreate_DispCapabilities(DispCapabilities**, Dynamic*, NvU32, #define dispcapGetRegBaseOffsetAndSize(pDispCapabilities, pGpu, pOffset, pSize) dispcapGetRegBaseOffsetAndSize_DISPATCH(pDispCapabilities, pGpu, pOffset, pSize) #define dispcapShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) dispcapShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define dispcapCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) dispcapCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define dispcapMapTo(pResource, pParams) dispcapMapTo_DISPATCH(pResource, pParams) +#define dispcapGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) dispcapGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define dispcapGetRefCount(pResource) dispcapGetRefCount_DISPATCH(pResource) +#define dispcapAddAdditionalDependants(pClient, pResource, pReference) dispcapAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define dispcapControl_Prologue(pResource, pCallContext, pParams) dispcapControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define dispcapInternalControlForward(pGpuResource, command, pParams, size) dispcapInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define dispcapUnmapFrom(pResource, pParams) dispcapUnmapFrom_DISPATCH(pResource, pParams) +#define dispcapControl_Epilogue(pResource, pCallContext, pParams) dispcapControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define dispcapControlLookup(pResource, pParams, ppEntry) dispcapControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define dispcapGetInternalObjectHandle(pGpuResource) dispcapGetInternalObjectHandle_DISPATCH(pGpuResource) #define dispcapControl(pGpuResource, pCallContext, pParams) dispcapControl_DISPATCH(pGpuResource, pCallContext, pParams) #define dispcapUnmap(pGpuResource, pCallContext, pCpuMapping) dispcapUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define dispcapGetMemInterMapParams(pRmResource, pParams) dispcapGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define dispcapGetMemoryMappingDescriptor(pRmResource, ppMemDesc) dispcapGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define dispcapGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) dispcapGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define dispcapGetInternalObjectHandle(pGpuResource) dispcapGetInternalObjectHandle_DISPATCH(pGpuResource) #define dispcapControlFilter(pResource, pCallContext, pParams) dispcapControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define dispcapAddAdditionalDependants(pClient, pResource, pReference) dispcapAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define dispcapGetRefCount(pResource) dispcapGetRefCount_DISPATCH(pResource) -#define dispcapCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) dispcapCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define dispcapMapTo(pResource, pParams) dispcapMapTo_DISPATCH(pResource, pParams) -#define dispcapControl_Prologue(pResource, pCallContext, pParams) dispcapControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define dispcapControlSerialization_Prologue(pResource, pCallContext, pParams) dispcapControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dispcapCanCopy(pResource) dispcapCanCopy_DISPATCH(pResource) -#define dispcapInternalControlForward(pGpuResource, command, pParams, size) dispcapInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define dispcapPreDestruct(pResource) dispcapPreDestruct_DISPATCH(pResource) -#define dispcapUnmapFrom(pResource, pParams) dispcapUnmapFrom_DISPATCH(pResource, pParams) #define dispcapIsDuplicate(pResource, hMemory, pDuplicate) dispcapIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) -#define dispcapControl_Epilogue(pResource, pCallContext, pParams) dispcapControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define dispcapControlLookup(pResource, pParams, ppEntry) dispcapControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define dispcapControlSerialization_Epilogue(pResource, pCallContext, pParams) dispcapControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define dispcapMap(pGpuResource, pCallContext, pParams, pCpuMapping) dispcapMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define dispcapAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) dispcapAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS dispcapGetRegBaseOffsetAndSize_IMPL(struct DispCapabilities *pDispCapabilities, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize); @@ -148,6 +152,50 @@ static inline NvBool dispcapShareCallback_DISPATCH(struct DispCapabilities *pGpu return pGpuResource->__dispcapShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } +static inline NV_STATUS dispcapCheckMemInterUnmap_DISPATCH(struct DispCapabilities *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__dispcapCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS dispcapMapTo_DISPATCH(struct DispCapabilities *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__dispcapMapTo__(pResource, pParams); +} + +static inline NV_STATUS dispcapGetMapAddrSpace_DISPATCH(struct DispCapabilities *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__dispcapGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 dispcapGetRefCount_DISPATCH(struct DispCapabilities *pResource) { + return pResource->__dispcapGetRefCount__(pResource); +} + +static inline void dispcapAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct DispCapabilities *pResource, RsResourceRef *pReference) { + pResource->__dispcapAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS dispcapControl_Prologue_DISPATCH(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dispcapControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS dispcapInternalControlForward_DISPATCH(struct DispCapabilities *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__dispcapInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS dispcapUnmapFrom_DISPATCH(struct DispCapabilities *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__dispcapUnmapFrom__(pResource, pParams); +} + +static inline void dispcapControl_Epilogue_DISPATCH(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__dispcapControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS dispcapControlLookup_DISPATCH(struct DispCapabilities *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__dispcapControlLookup__(pResource, pParams, ppEntry); +} + +static inline NvHandle dispcapGetInternalObjectHandle_DISPATCH(struct DispCapabilities *pGpuResource) { + return pGpuResource->__dispcapGetInternalObjectHandle__(pGpuResource); +} + static inline NV_STATUS dispcapControl_DISPATCH(struct DispCapabilities *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pGpuResource->__dispcapControl__(pGpuResource, pCallContext, pParams); } @@ -164,64 +212,28 @@ static inline NV_STATUS dispcapGetMemoryMappingDescriptor_DISPATCH(struct DispCa return pRmResource->__dispcapGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS dispcapGetMapAddrSpace_DISPATCH(struct DispCapabilities *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__dispcapGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvHandle dispcapGetInternalObjectHandle_DISPATCH(struct DispCapabilities *pGpuResource) { - return pGpuResource->__dispcapGetInternalObjectHandle__(pGpuResource); -} - static inline NV_STATUS dispcapControlFilter_DISPATCH(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__dispcapControlFilter__(pResource, pCallContext, pParams); } -static inline void dispcapAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct DispCapabilities *pResource, RsResourceRef *pReference) { - pResource->__dispcapAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 dispcapGetRefCount_DISPATCH(struct DispCapabilities *pResource) { - return pResource->__dispcapGetRefCount__(pResource); -} - -static inline NV_STATUS dispcapCheckMemInterUnmap_DISPATCH(struct DispCapabilities *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__dispcapCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS dispcapMapTo_DISPATCH(struct DispCapabilities *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__dispcapMapTo__(pResource, pParams); -} - -static inline NV_STATUS dispcapControl_Prologue_DISPATCH(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__dispcapControl_Prologue__(pResource, pCallContext, pParams); +static inline NV_STATUS dispcapControlSerialization_Prologue_DISPATCH(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dispcapControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool dispcapCanCopy_DISPATCH(struct DispCapabilities *pResource) { return pResource->__dispcapCanCopy__(pResource); } -static inline NV_STATUS dispcapInternalControlForward_DISPATCH(struct DispCapabilities *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__dispcapInternalControlForward__(pGpuResource, command, pParams, size); -} - static inline void dispcapPreDestruct_DISPATCH(struct DispCapabilities *pResource) { pResource->__dispcapPreDestruct__(pResource); } -static inline NV_STATUS dispcapUnmapFrom_DISPATCH(struct DispCapabilities *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__dispcapUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS dispcapIsDuplicate_DISPATCH(struct DispCapabilities *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__dispcapIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline void dispcapControl_Epilogue_DISPATCH(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__dispcapControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS dispcapControlLookup_DISPATCH(struct DispCapabilities *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__dispcapControlLookup__(pResource, pParams, ppEntry); +static inline void dispcapControlSerialization_Epilogue_DISPATCH(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__dispcapControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS dispcapMap_DISPATCH(struct DispCapabilities *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_disp_channel_nvoc.c b/src/nvidia/generated/g_disp_channel_nvoc.c index edd3ca5d6..e4d8c6c11 100644 --- a/src/nvidia/generated/g_disp_channel_nvoc.c +++ b/src/nvidia/generated/g_disp_channel_nvoc.c @@ -119,16 +119,16 @@ static NvBool __nvoc_thunk_GpuResource_dispchnShareCallback(struct DispChannel * return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispChannel_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_RsResource_dispchnMapTo(struct DispChannel *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannel_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_dispchnCheckMemInterUnmap(struct DispChannel *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispChannel_RmResource.offset), bSubdeviceHandleProvided); } static NV_STATUS __nvoc_thunk_Notifier_dispchnGetOrAllocNotifShare(struct DispChannel *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispChannel_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); } -static NV_STATUS __nvoc_thunk_RmResource_dispchnCheckMemInterUnmap(struct DispChannel *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispChannel_RmResource.offset), bSubdeviceHandleProvided); +static NV_STATUS __nvoc_thunk_RsResource_dispchnMapTo(struct DispChannel *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannel_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_GpuResource_dispchnGetMapAddrSpace(struct DispChannel *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -195,6 +195,10 @@ static NV_STATUS __nvoc_thunk_Notifier_dispchnUnregisterEvent(struct DispChannel return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispChannel_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_dispchnControlSerialization_Prologue(struct DispChannel *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannel_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_dispchnCanCopy(struct DispChannel *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannel_RsResource.offset)); } @@ -207,6 +211,10 @@ static NV_STATUS __nvoc_thunk_RsResource_dispchnIsDuplicate(struct DispChannel * return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannel_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_dispchnControlSerialization_Epilogue(struct DispChannel *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannel_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_dispchnGetNotificationListPtr(struct DispChannel *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispChannel_Notifier.offset)); } @@ -275,11 +283,11 @@ static void __nvoc_init_funcTable_DispChannel_1(DispChannel *pThis) { pThis->__dispchnShareCallback__ = &__nvoc_thunk_GpuResource_dispchnShareCallback; - pThis->__dispchnMapTo__ = &__nvoc_thunk_RsResource_dispchnMapTo; + pThis->__dispchnCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispchnCheckMemInterUnmap; pThis->__dispchnGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_dispchnGetOrAllocNotifShare; - pThis->__dispchnCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispchnCheckMemInterUnmap; + pThis->__dispchnMapTo__ = &__nvoc_thunk_RsResource_dispchnMapTo; pThis->__dispchnGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_dispchnGetMapAddrSpace; @@ -313,12 +321,16 @@ static void __nvoc_init_funcTable_DispChannel_1(DispChannel *pThis) { pThis->__dispchnUnregisterEvent__ = &__nvoc_thunk_Notifier_dispchnUnregisterEvent; + pThis->__dispchnControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_dispchnControlSerialization_Prologue; + pThis->__dispchnCanCopy__ = &__nvoc_thunk_RsResource_dispchnCanCopy; pThis->__dispchnPreDestruct__ = &__nvoc_thunk_RsResource_dispchnPreDestruct; pThis->__dispchnIsDuplicate__ = &__nvoc_thunk_RsResource_dispchnIsDuplicate; + pThis->__dispchnControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_dispchnControlSerialization_Epilogue; + pThis->__dispchnGetNotificationListPtr__ = &__nvoc_thunk_Notifier_dispchnGetNotificationListPtr; pThis->__dispchnGetNotificationShare__ = &__nvoc_thunk_Notifier_dispchnGetNotificationShare; @@ -353,13 +365,16 @@ NV_STATUS __nvoc_objCreate_DispChannel(DispChannel **ppThis, Dynamic *pParent, N Object *pParentObj; DispChannel *pThis; - pThis = portMemAllocNonPaged(sizeof(DispChannel)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DispChannel), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(DispChannel)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DispChannel); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -375,11 +390,17 @@ NV_STATUS __nvoc_objCreate_DispChannel(DispChannel **ppThis, Dynamic *pParent, N if (status != NV_OK) goto __nvoc_objCreate_DispChannel_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_DispChannel_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(DispChannel)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -511,16 +532,16 @@ static NvBool __nvoc_thunk_GpuResource_dispchnpioShareCallback(struct DispChanne return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispChannelPio_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_RsResource_dispchnpioMapTo(struct DispChannelPio *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelPio_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_dispchnpioCheckMemInterUnmap(struct DispChannelPio *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispChannelPio_RmResource.offset), bSubdeviceHandleProvided); } static NV_STATUS __nvoc_thunk_Notifier_dispchnpioGetOrAllocNotifShare(struct DispChannelPio *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispChannelPio_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); } -static NV_STATUS __nvoc_thunk_RmResource_dispchnpioCheckMemInterUnmap(struct DispChannelPio *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispChannelPio_RmResource.offset), bSubdeviceHandleProvided); +static NV_STATUS __nvoc_thunk_RsResource_dispchnpioMapTo(struct DispChannelPio *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelPio_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_GpuResource_dispchnpioGetMapAddrSpace(struct DispChannelPio *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -591,6 +612,10 @@ static NV_STATUS __nvoc_thunk_Notifier_dispchnpioUnregisterEvent(struct DispChan return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispChannelPio_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_dispchnpioControlSerialization_Prologue(struct DispChannelPio *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelPio_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_dispchnpioCanCopy(struct DispChannelPio *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelPio_RsResource.offset)); } @@ -603,6 +628,10 @@ static NV_STATUS __nvoc_thunk_RsResource_dispchnpioIsDuplicate(struct DispChanne return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelPio_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_dispchnpioControlSerialization_Epilogue(struct DispChannelPio *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelPio_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_dispchnpioGetNotificationListPtr(struct DispChannelPio *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispChannelPio_Notifier.offset)); } @@ -659,11 +688,11 @@ static void __nvoc_init_funcTable_DispChannelPio_1(DispChannelPio *pThis) { pThis->__dispchnpioShareCallback__ = &__nvoc_thunk_GpuResource_dispchnpioShareCallback; - pThis->__dispchnpioMapTo__ = &__nvoc_thunk_RsResource_dispchnpioMapTo; + pThis->__dispchnpioCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispchnpioCheckMemInterUnmap; pThis->__dispchnpioGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_dispchnpioGetOrAllocNotifShare; - pThis->__dispchnpioCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispchnpioCheckMemInterUnmap; + pThis->__dispchnpioMapTo__ = &__nvoc_thunk_RsResource_dispchnpioMapTo; pThis->__dispchnpioGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_dispchnpioGetMapAddrSpace; @@ -699,12 +728,16 @@ static void __nvoc_init_funcTable_DispChannelPio_1(DispChannelPio *pThis) { pThis->__dispchnpioUnregisterEvent__ = &__nvoc_thunk_Notifier_dispchnpioUnregisterEvent; + pThis->__dispchnpioControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_dispchnpioControlSerialization_Prologue; + pThis->__dispchnpioCanCopy__ = &__nvoc_thunk_RsResource_dispchnpioCanCopy; pThis->__dispchnpioPreDestruct__ = &__nvoc_thunk_RsResource_dispchnpioPreDestruct; pThis->__dispchnpioIsDuplicate__ = &__nvoc_thunk_RsResource_dispchnpioIsDuplicate; + pThis->__dispchnpioControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_dispchnpioControlSerialization_Epilogue; + pThis->__dispchnpioGetNotificationListPtr__ = &__nvoc_thunk_Notifier_dispchnpioGetNotificationListPtr; pThis->__dispchnpioGetNotificationShare__ = &__nvoc_thunk_Notifier_dispchnpioGetNotificationShare; @@ -738,13 +771,16 @@ NV_STATUS __nvoc_objCreate_DispChannelPio(DispChannelPio **ppThis, Dynamic *pPar Object *pParentObj; DispChannelPio *pThis; - pThis = portMemAllocNonPaged(sizeof(DispChannelPio)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DispChannelPio), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(DispChannelPio)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DispChannelPio); + pThis->__nvoc_base_DispChannel.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -760,11 +796,17 @@ NV_STATUS __nvoc_objCreate_DispChannelPio(DispChannelPio **ppThis, Dynamic *pPar if (status != NV_OK) goto __nvoc_objCreate_DispChannelPio_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_DispChannelPio_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(DispChannelPio)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -895,16 +937,16 @@ static NvBool __nvoc_thunk_GpuResource_dispchndmaShareCallback(struct DispChanne return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispChannelDma_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_RsResource_dispchndmaMapTo(struct DispChannelDma *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelDma_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_dispchndmaCheckMemInterUnmap(struct DispChannelDma *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispChannelDma_RmResource.offset), bSubdeviceHandleProvided); } static NV_STATUS __nvoc_thunk_Notifier_dispchndmaGetOrAllocNotifShare(struct DispChannelDma *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispChannelDma_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); } -static NV_STATUS __nvoc_thunk_RmResource_dispchndmaCheckMemInterUnmap(struct DispChannelDma *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispChannelDma_RmResource.offset), bSubdeviceHandleProvided); +static NV_STATUS __nvoc_thunk_RsResource_dispchndmaMapTo(struct DispChannelDma *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelDma_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_GpuResource_dispchndmaGetMapAddrSpace(struct DispChannelDma *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -975,6 +1017,10 @@ static NV_STATUS __nvoc_thunk_Notifier_dispchndmaUnregisterEvent(struct DispChan return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispChannelDma_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_dispchndmaControlSerialization_Prologue(struct DispChannelDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelDma_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_dispchndmaCanCopy(struct DispChannelDma *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelDma_RsResource.offset)); } @@ -987,6 +1033,10 @@ static NV_STATUS __nvoc_thunk_RsResource_dispchndmaIsDuplicate(struct DispChanne return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelDma_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_dispchndmaControlSerialization_Epilogue(struct DispChannelDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelDma_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_dispchndmaGetNotificationListPtr(struct DispChannelDma *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispChannelDma_Notifier.offset)); } @@ -1043,11 +1093,11 @@ static void __nvoc_init_funcTable_DispChannelDma_1(DispChannelDma *pThis) { pThis->__dispchndmaShareCallback__ = &__nvoc_thunk_GpuResource_dispchndmaShareCallback; - pThis->__dispchndmaMapTo__ = &__nvoc_thunk_RsResource_dispchndmaMapTo; + pThis->__dispchndmaCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispchndmaCheckMemInterUnmap; pThis->__dispchndmaGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_dispchndmaGetOrAllocNotifShare; - pThis->__dispchndmaCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispchndmaCheckMemInterUnmap; + pThis->__dispchndmaMapTo__ = &__nvoc_thunk_RsResource_dispchndmaMapTo; pThis->__dispchndmaGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_dispchndmaGetMapAddrSpace; @@ -1083,12 +1133,16 @@ static void __nvoc_init_funcTable_DispChannelDma_1(DispChannelDma *pThis) { pThis->__dispchndmaUnregisterEvent__ = &__nvoc_thunk_Notifier_dispchndmaUnregisterEvent; + pThis->__dispchndmaControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_dispchndmaControlSerialization_Prologue; + pThis->__dispchndmaCanCopy__ = &__nvoc_thunk_RsResource_dispchndmaCanCopy; pThis->__dispchndmaPreDestruct__ = &__nvoc_thunk_RsResource_dispchndmaPreDestruct; pThis->__dispchndmaIsDuplicate__ = &__nvoc_thunk_RsResource_dispchndmaIsDuplicate; + pThis->__dispchndmaControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_dispchndmaControlSerialization_Epilogue; + pThis->__dispchndmaGetNotificationListPtr__ = &__nvoc_thunk_Notifier_dispchndmaGetNotificationListPtr; pThis->__dispchndmaGetNotificationShare__ = &__nvoc_thunk_Notifier_dispchndmaGetNotificationShare; @@ -1122,13 +1176,16 @@ NV_STATUS __nvoc_objCreate_DispChannelDma(DispChannelDma **ppThis, Dynamic *pPar Object *pParentObj; DispChannelDma *pThis; - pThis = portMemAllocNonPaged(sizeof(DispChannelDma)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DispChannelDma), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(DispChannelDma)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DispChannelDma); + pThis->__nvoc_base_DispChannel.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -1144,11 +1201,17 @@ NV_STATUS __nvoc_objCreate_DispChannelDma(DispChannelDma **ppThis, Dynamic *pPar if (status != NV_OK) goto __nvoc_objCreate_DispChannelDma_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_DispChannelDma_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(DispChannelDma)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_disp_channel_nvoc.h b/src/nvidia/generated/g_disp_channel_nvoc.h index 5d2a21800..f5a977095 100644 --- a/src/nvidia/generated/g_disp_channel_nvoc.h +++ b/src/nvidia/generated/g_disp_channel_nvoc.h @@ -91,9 +91,9 @@ struct DispChannel { struct DispChannel *__nvoc_pbase_DispChannel; NV_STATUS (*__dispchnGetRegBaseOffsetAndSize__)(struct DispChannel *, struct OBJGPU *, NvU32 *, NvU32 *); NvBool (*__dispchnShareCallback__)(struct DispChannel *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__dispchnMapTo__)(struct DispChannel *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__dispchnGetOrAllocNotifShare__)(struct DispChannel *, NvHandle, NvHandle, struct NotifShare **); NV_STATUS (*__dispchnCheckMemInterUnmap__)(struct DispChannel *, NvBool); + NV_STATUS (*__dispchnGetOrAllocNotifShare__)(struct DispChannel *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__dispchnMapTo__)(struct DispChannel *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__dispchnGetMapAddrSpace__)(struct DispChannel *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); void (*__dispchnSetNotificationShare__)(struct DispChannel *, struct NotifShare *); NvU32 (*__dispchnGetRefCount__)(struct DispChannel *); @@ -110,9 +110,11 @@ struct DispChannel { NV_STATUS (*__dispchnGetMemoryMappingDescriptor__)(struct DispChannel *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__dispchnControlFilter__)(struct DispChannel *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispchnUnregisterEvent__)(struct DispChannel *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__dispchnControlSerialization_Prologue__)(struct DispChannel *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispchnCanCopy__)(struct DispChannel *); void (*__dispchnPreDestruct__)(struct DispChannel *); NV_STATUS (*__dispchnIsDuplicate__)(struct DispChannel *, NvHandle, NvBool *); + void (*__dispchnControlSerialization_Epilogue__)(struct DispChannel *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__dispchnGetNotificationListPtr__)(struct DispChannel *); struct NotifShare *(*__dispchnGetNotificationShare__)(struct DispChannel *); NV_STATUS (*__dispchnMap__)(struct DispChannel *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -157,9 +159,9 @@ NV_STATUS __nvoc_objCreate_DispChannel(DispChannel**, Dynamic*, NvU32, struct CA #define dispchnGetRegBaseOffsetAndSize(pDispChannel, pGpu, pOffset, pSize) dispchnGetRegBaseOffsetAndSize_DISPATCH(pDispChannel, pGpu, pOffset, pSize) #define dispchnShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) dispchnShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define dispchnMapTo(pResource, pParams) dispchnMapTo_DISPATCH(pResource, pParams) -#define dispchnGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) dispchnGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) #define dispchnCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) dispchnCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define dispchnGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) dispchnGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define dispchnMapTo(pResource, pParams) dispchnMapTo_DISPATCH(pResource, pParams) #define dispchnGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) dispchnGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) #define dispchnSetNotificationShare(pNotifier, pNotifShare) dispchnSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define dispchnGetRefCount(pResource) dispchnGetRefCount_DISPATCH(pResource) @@ -176,9 +178,11 @@ NV_STATUS __nvoc_objCreate_DispChannel(DispChannel**, Dynamic*, NvU32, struct CA #define dispchnGetMemoryMappingDescriptor(pRmResource, ppMemDesc) dispchnGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define dispchnControlFilter(pResource, pCallContext, pParams) dispchnControlFilter_DISPATCH(pResource, pCallContext, pParams) #define dispchnUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) dispchnUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define dispchnControlSerialization_Prologue(pResource, pCallContext, pParams) dispchnControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dispchnCanCopy(pResource) dispchnCanCopy_DISPATCH(pResource) #define dispchnPreDestruct(pResource) dispchnPreDestruct_DISPATCH(pResource) #define dispchnIsDuplicate(pResource, hMemory, pDuplicate) dispchnIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define dispchnControlSerialization_Epilogue(pResource, pCallContext, pParams) dispchnControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define dispchnGetNotificationListPtr(pNotifier) dispchnGetNotificationListPtr_DISPATCH(pNotifier) #define dispchnGetNotificationShare(pNotifier) dispchnGetNotificationShare_DISPATCH(pNotifier) #define dispchnMap(pGpuResource, pCallContext, pParams, pCpuMapping) dispchnMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -193,16 +197,16 @@ static inline NvBool dispchnShareCallback_DISPATCH(struct DispChannel *pGpuResou return pGpuResource->__dispchnShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS dispchnMapTo_DISPATCH(struct DispChannel *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__dispchnMapTo__(pResource, pParams); +static inline NV_STATUS dispchnCheckMemInterUnmap_DISPATCH(struct DispChannel *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__dispchnCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } static inline NV_STATUS dispchnGetOrAllocNotifShare_DISPATCH(struct DispChannel *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return pNotifier->__dispchnGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); } -static inline NV_STATUS dispchnCheckMemInterUnmap_DISPATCH(struct DispChannel *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__dispchnCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline NV_STATUS dispchnMapTo_DISPATCH(struct DispChannel *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__dispchnMapTo__(pResource, pParams); } static inline NV_STATUS dispchnGetMapAddrSpace_DISPATCH(struct DispChannel *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -269,6 +273,10 @@ static inline NV_STATUS dispchnUnregisterEvent_DISPATCH(struct DispChannel *pNot return pNotifier->__dispchnUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS dispchnControlSerialization_Prologue_DISPATCH(struct DispChannel *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dispchnControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool dispchnCanCopy_DISPATCH(struct DispChannel *pResource) { return pResource->__dispchnCanCopy__(pResource); } @@ -281,6 +289,10 @@ static inline NV_STATUS dispchnIsDuplicate_DISPATCH(struct DispChannel *pResourc return pResource->__dispchnIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void dispchnControlSerialization_Epilogue_DISPATCH(struct DispChannel *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__dispchnControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *dispchnGetNotificationListPtr_DISPATCH(struct DispChannel *pNotifier) { return pNotifier->__dispchnGetNotificationListPtr__(pNotifier); } @@ -370,9 +382,9 @@ struct DispChannelPio { struct DispChannel *__nvoc_pbase_DispChannel; struct DispChannelPio *__nvoc_pbase_DispChannelPio; NvBool (*__dispchnpioShareCallback__)(struct DispChannelPio *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__dispchnpioMapTo__)(struct DispChannelPio *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__dispchnpioGetOrAllocNotifShare__)(struct DispChannelPio *, NvHandle, NvHandle, struct NotifShare **); NV_STATUS (*__dispchnpioCheckMemInterUnmap__)(struct DispChannelPio *, NvBool); + NV_STATUS (*__dispchnpioGetOrAllocNotifShare__)(struct DispChannelPio *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__dispchnpioMapTo__)(struct DispChannelPio *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__dispchnpioGetMapAddrSpace__)(struct DispChannelPio *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); void (*__dispchnpioSetNotificationShare__)(struct DispChannelPio *, struct NotifShare *); NvU32 (*__dispchnpioGetRefCount__)(struct DispChannelPio *); @@ -390,9 +402,11 @@ struct DispChannelPio { NV_STATUS (*__dispchnpioGetMemoryMappingDescriptor__)(struct DispChannelPio *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__dispchnpioControlFilter__)(struct DispChannelPio *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispchnpioUnregisterEvent__)(struct DispChannelPio *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__dispchnpioControlSerialization_Prologue__)(struct DispChannelPio *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispchnpioCanCopy__)(struct DispChannelPio *); void (*__dispchnpioPreDestruct__)(struct DispChannelPio *); NV_STATUS (*__dispchnpioIsDuplicate__)(struct DispChannelPio *, NvHandle, NvBool *); + void (*__dispchnpioControlSerialization_Epilogue__)(struct DispChannelPio *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__dispchnpioGetNotificationListPtr__)(struct DispChannelPio *); struct NotifShare *(*__dispchnpioGetNotificationShare__)(struct DispChannelPio *); NV_STATUS (*__dispchnpioMap__)(struct DispChannelPio *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -428,9 +442,9 @@ NV_STATUS __nvoc_objCreate_DispChannelPio(DispChannelPio**, Dynamic*, NvU32, str __nvoc_objCreate_DispChannelPio((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) #define dispchnpioShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) dispchnpioShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define dispchnpioMapTo(pResource, pParams) dispchnpioMapTo_DISPATCH(pResource, pParams) -#define dispchnpioGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) dispchnpioGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) #define dispchnpioCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) dispchnpioCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define dispchnpioGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) dispchnpioGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define dispchnpioMapTo(pResource, pParams) dispchnpioMapTo_DISPATCH(pResource, pParams) #define dispchnpioGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) dispchnpioGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) #define dispchnpioSetNotificationShare(pNotifier, pNotifShare) dispchnpioSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define dispchnpioGetRefCount(pResource) dispchnpioGetRefCount_DISPATCH(pResource) @@ -448,9 +462,11 @@ NV_STATUS __nvoc_objCreate_DispChannelPio(DispChannelPio**, Dynamic*, NvU32, str #define dispchnpioGetMemoryMappingDescriptor(pRmResource, ppMemDesc) dispchnpioGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define dispchnpioControlFilter(pResource, pCallContext, pParams) dispchnpioControlFilter_DISPATCH(pResource, pCallContext, pParams) #define dispchnpioUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) dispchnpioUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define dispchnpioControlSerialization_Prologue(pResource, pCallContext, pParams) dispchnpioControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dispchnpioCanCopy(pResource) dispchnpioCanCopy_DISPATCH(pResource) #define dispchnpioPreDestruct(pResource) dispchnpioPreDestruct_DISPATCH(pResource) #define dispchnpioIsDuplicate(pResource, hMemory, pDuplicate) dispchnpioIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define dispchnpioControlSerialization_Epilogue(pResource, pCallContext, pParams) dispchnpioControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define dispchnpioGetNotificationListPtr(pNotifier) dispchnpioGetNotificationListPtr_DISPATCH(pNotifier) #define dispchnpioGetNotificationShare(pNotifier) dispchnpioGetNotificationShare_DISPATCH(pNotifier) #define dispchnpioMap(pGpuResource, pCallContext, pParams, pCpuMapping) dispchnpioMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -459,16 +475,16 @@ static inline NvBool dispchnpioShareCallback_DISPATCH(struct DispChannelPio *pGp return pGpuResource->__dispchnpioShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS dispchnpioMapTo_DISPATCH(struct DispChannelPio *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__dispchnpioMapTo__(pResource, pParams); +static inline NV_STATUS dispchnpioCheckMemInterUnmap_DISPATCH(struct DispChannelPio *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__dispchnpioCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } static inline NV_STATUS dispchnpioGetOrAllocNotifShare_DISPATCH(struct DispChannelPio *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return pNotifier->__dispchnpioGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); } -static inline NV_STATUS dispchnpioCheckMemInterUnmap_DISPATCH(struct DispChannelPio *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__dispchnpioCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline NV_STATUS dispchnpioMapTo_DISPATCH(struct DispChannelPio *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__dispchnpioMapTo__(pResource, pParams); } static inline NV_STATUS dispchnpioGetMapAddrSpace_DISPATCH(struct DispChannelPio *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -539,6 +555,10 @@ static inline NV_STATUS dispchnpioUnregisterEvent_DISPATCH(struct DispChannelPio return pNotifier->__dispchnpioUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS dispchnpioControlSerialization_Prologue_DISPATCH(struct DispChannelPio *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dispchnpioControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool dispchnpioCanCopy_DISPATCH(struct DispChannelPio *pResource) { return pResource->__dispchnpioCanCopy__(pResource); } @@ -551,6 +571,10 @@ static inline NV_STATUS dispchnpioIsDuplicate_DISPATCH(struct DispChannelPio *pR return pResource->__dispchnpioIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void dispchnpioControlSerialization_Epilogue_DISPATCH(struct DispChannelPio *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__dispchnpioControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *dispchnpioGetNotificationListPtr_DISPATCH(struct DispChannelPio *pNotifier) { return pNotifier->__dispchnpioGetNotificationListPtr__(pNotifier); } @@ -594,9 +618,9 @@ struct DispChannelDma { struct DispChannel *__nvoc_pbase_DispChannel; struct DispChannelDma *__nvoc_pbase_DispChannelDma; NvBool (*__dispchndmaShareCallback__)(struct DispChannelDma *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__dispchndmaMapTo__)(struct DispChannelDma *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__dispchndmaGetOrAllocNotifShare__)(struct DispChannelDma *, NvHandle, NvHandle, struct NotifShare **); NV_STATUS (*__dispchndmaCheckMemInterUnmap__)(struct DispChannelDma *, NvBool); + NV_STATUS (*__dispchndmaGetOrAllocNotifShare__)(struct DispChannelDma *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__dispchndmaMapTo__)(struct DispChannelDma *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__dispchndmaGetMapAddrSpace__)(struct DispChannelDma *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); void (*__dispchndmaSetNotificationShare__)(struct DispChannelDma *, struct NotifShare *); NvU32 (*__dispchndmaGetRefCount__)(struct DispChannelDma *); @@ -614,9 +638,11 @@ struct DispChannelDma { NV_STATUS (*__dispchndmaGetMemoryMappingDescriptor__)(struct DispChannelDma *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__dispchndmaControlFilter__)(struct DispChannelDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispchndmaUnregisterEvent__)(struct DispChannelDma *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__dispchndmaControlSerialization_Prologue__)(struct DispChannelDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispchndmaCanCopy__)(struct DispChannelDma *); void (*__dispchndmaPreDestruct__)(struct DispChannelDma *); NV_STATUS (*__dispchndmaIsDuplicate__)(struct DispChannelDma *, NvHandle, NvBool *); + void (*__dispchndmaControlSerialization_Epilogue__)(struct DispChannelDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__dispchndmaGetNotificationListPtr__)(struct DispChannelDma *); struct NotifShare *(*__dispchndmaGetNotificationShare__)(struct DispChannelDma *); NV_STATUS (*__dispchndmaMap__)(struct DispChannelDma *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -652,9 +678,9 @@ NV_STATUS __nvoc_objCreate_DispChannelDma(DispChannelDma**, Dynamic*, NvU32, str __nvoc_objCreate_DispChannelDma((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) #define dispchndmaShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) dispchndmaShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define dispchndmaMapTo(pResource, pParams) dispchndmaMapTo_DISPATCH(pResource, pParams) -#define dispchndmaGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) dispchndmaGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) #define dispchndmaCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) dispchndmaCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define dispchndmaGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) dispchndmaGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define dispchndmaMapTo(pResource, pParams) dispchndmaMapTo_DISPATCH(pResource, pParams) #define dispchndmaGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) dispchndmaGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) #define dispchndmaSetNotificationShare(pNotifier, pNotifShare) dispchndmaSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define dispchndmaGetRefCount(pResource) dispchndmaGetRefCount_DISPATCH(pResource) @@ -672,9 +698,11 @@ NV_STATUS __nvoc_objCreate_DispChannelDma(DispChannelDma**, Dynamic*, NvU32, str #define dispchndmaGetMemoryMappingDescriptor(pRmResource, ppMemDesc) dispchndmaGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define dispchndmaControlFilter(pResource, pCallContext, pParams) dispchndmaControlFilter_DISPATCH(pResource, pCallContext, pParams) #define dispchndmaUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) dispchndmaUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define dispchndmaControlSerialization_Prologue(pResource, pCallContext, pParams) dispchndmaControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dispchndmaCanCopy(pResource) dispchndmaCanCopy_DISPATCH(pResource) #define dispchndmaPreDestruct(pResource) dispchndmaPreDestruct_DISPATCH(pResource) #define dispchndmaIsDuplicate(pResource, hMemory, pDuplicate) dispchndmaIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define dispchndmaControlSerialization_Epilogue(pResource, pCallContext, pParams) dispchndmaControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define dispchndmaGetNotificationListPtr(pNotifier) dispchndmaGetNotificationListPtr_DISPATCH(pNotifier) #define dispchndmaGetNotificationShare(pNotifier) dispchndmaGetNotificationShare_DISPATCH(pNotifier) #define dispchndmaMap(pGpuResource, pCallContext, pParams, pCpuMapping) dispchndmaMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -683,16 +711,16 @@ static inline NvBool dispchndmaShareCallback_DISPATCH(struct DispChannelDma *pGp return pGpuResource->__dispchndmaShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS dispchndmaMapTo_DISPATCH(struct DispChannelDma *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__dispchndmaMapTo__(pResource, pParams); +static inline NV_STATUS dispchndmaCheckMemInterUnmap_DISPATCH(struct DispChannelDma *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__dispchndmaCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } static inline NV_STATUS dispchndmaGetOrAllocNotifShare_DISPATCH(struct DispChannelDma *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return pNotifier->__dispchndmaGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); } -static inline NV_STATUS dispchndmaCheckMemInterUnmap_DISPATCH(struct DispChannelDma *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__dispchndmaCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline NV_STATUS dispchndmaMapTo_DISPATCH(struct DispChannelDma *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__dispchndmaMapTo__(pResource, pParams); } static inline NV_STATUS dispchndmaGetMapAddrSpace_DISPATCH(struct DispChannelDma *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -763,6 +791,10 @@ static inline NV_STATUS dispchndmaUnregisterEvent_DISPATCH(struct DispChannelDma return pNotifier->__dispchndmaUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS dispchndmaControlSerialization_Prologue_DISPATCH(struct DispChannelDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dispchndmaControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool dispchndmaCanCopy_DISPATCH(struct DispChannelDma *pResource) { return pResource->__dispchndmaCanCopy__(pResource); } @@ -775,6 +807,10 @@ static inline NV_STATUS dispchndmaIsDuplicate_DISPATCH(struct DispChannelDma *pR return pResource->__dispchndmaIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void dispchndmaControlSerialization_Epilogue_DISPATCH(struct DispChannelDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__dispchndmaControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *dispchndmaGetNotificationListPtr_DISPATCH(struct DispChannelDma *pNotifier) { return pNotifier->__dispchndmaGetNotificationListPtr__(pNotifier); } diff --git a/src/nvidia/generated/g_disp_inst_mem_nvoc.c b/src/nvidia/generated/g_disp_inst_mem_nvoc.c index 32deea27e..9ca145cf1 100644 --- a/src/nvidia/generated/g_disp_inst_mem_nvoc.c +++ b/src/nvidia/generated/g_disp_inst_mem_nvoc.c @@ -195,13 +195,16 @@ NV_STATUS __nvoc_objCreate_DisplayInstanceMemory(DisplayInstanceMemory **ppThis, DisplayInstanceMemory *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(DisplayInstanceMemory)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DisplayInstanceMemory), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(DisplayInstanceMemory)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DisplayInstanceMemory); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -221,11 +224,17 @@ NV_STATUS __nvoc_objCreate_DisplayInstanceMemory(DisplayInstanceMemory **ppThis, if (status != NV_OK) goto __nvoc_objCreate_DisplayInstanceMemory_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_DisplayInstanceMemory_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(DisplayInstanceMemory)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_disp_objs_nvoc.c b/src/nvidia/generated/g_disp_objs_nvoc.c index 9c370ff76..e27e649f9 100644 --- a/src/nvidia/generated/g_disp_objs_nvoc.c +++ b/src/nvidia/generated/g_disp_objs_nvoc.c @@ -122,10 +122,38 @@ static NV_STATUS __nvoc_thunk_RmResource_dispapiCheckMemInterUnmap(struct Displa return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DisplayApi_RmResource.offset), bSubdeviceHandleProvided); } +static NV_STATUS __nvoc_thunk_RsResource_dispapiMapTo(struct DisplayApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), pParams); +} + static NvBool __nvoc_thunk_RmResource_dispapiAccessCallback(struct DisplayApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RmResource.offset), pInvokingClient, pAllocParams, accessRight); } +static void __nvoc_thunk_Notifier_dispapiSetNotificationShare(struct DisplayApi *pNotifier, struct NotifShare *pNotifShare) { + notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DisplayApi_Notifier.offset), pNotifShare); +} + +static NvU32 __nvoc_thunk_RsResource_dispapiGetRefCount(struct DisplayApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_dispapiAddAdditionalDependants(struct RsClient *pClient, struct DisplayApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispapiUnmapFrom(struct DisplayApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispapiControlLookup(struct DisplayApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), pParams, ppEntry); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispapiUnmap(struct DisplayApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), pCallContext, pCpuMapping); +} + static NV_STATUS __nvoc_thunk_RmResource_dispapiGetMemInterMapParams(struct DisplayApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DisplayApi_RmResource.offset), pParams); } @@ -134,50 +162,34 @@ static NV_STATUS __nvoc_thunk_RmResource_dispapiGetMemoryMappingDescriptor(struc return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DisplayApi_RmResource.offset), ppMemDesc); } -static void __nvoc_thunk_Notifier_dispapiSetNotificationShare(struct DisplayApi *pNotifier, struct NotifShare *pNotifShare) { - notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DisplayApi_Notifier.offset), pNotifShare); -} - static NV_STATUS __nvoc_thunk_RsResource_dispapiControlFilter(struct DisplayApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), pCallContext, pParams); } -static NvU32 __nvoc_thunk_RsResource_dispapiGetRefCount(struct DisplayApi *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_Notifier_dispapiUnregisterEvent(struct DisplayApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DisplayApi_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static NV_STATUS __nvoc_thunk_RsResource_dispapiUnmap(struct DisplayApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RmResource_dispapiControlSerialization_Prologue(struct DisplayApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_dispapiCanCopy(struct DisplayApi *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_dispapiMapTo(struct DisplayApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RsResource_dispapiAddAdditionalDependants(struct RsClient *pClient, struct DisplayApi *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), pReference); -} - static void __nvoc_thunk_RsResource_dispapiPreDestruct(struct DisplayApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_dispapiUnmapFrom(struct DisplayApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_dispapiIsDuplicate(struct DisplayApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_dispapiControlSerialization_Epilogue(struct DisplayApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_dispapiGetNotificationListPtr(struct DisplayApi *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DisplayApi_Notifier.offset)); } @@ -186,10 +198,6 @@ static struct NotifShare *__nvoc_thunk_Notifier_dispapiGetNotificationShare(stru return notifyGetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DisplayApi_Notifier.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_dispapiControlLookup(struct DisplayApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_RsResource_dispapiMap(struct DisplayApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return resMap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), pCallContext, pParams, pCpuMapping); } @@ -270,40 +278,44 @@ static void __nvoc_init_funcTable_DisplayApi_1(DisplayApi *pThis, RmHalspecOwner pThis->__dispapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispapiCheckMemInterUnmap; + pThis->__dispapiMapTo__ = &__nvoc_thunk_RsResource_dispapiMapTo; + pThis->__dispapiAccessCallback__ = &__nvoc_thunk_RmResource_dispapiAccessCallback; + pThis->__dispapiSetNotificationShare__ = &__nvoc_thunk_Notifier_dispapiSetNotificationShare; + + pThis->__dispapiGetRefCount__ = &__nvoc_thunk_RsResource_dispapiGetRefCount; + + pThis->__dispapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_dispapiAddAdditionalDependants; + + pThis->__dispapiUnmapFrom__ = &__nvoc_thunk_RsResource_dispapiUnmapFrom; + + pThis->__dispapiControlLookup__ = &__nvoc_thunk_RsResource_dispapiControlLookup; + + pThis->__dispapiUnmap__ = &__nvoc_thunk_RsResource_dispapiUnmap; + pThis->__dispapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_dispapiGetMemInterMapParams; pThis->__dispapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_dispapiGetMemoryMappingDescriptor; - pThis->__dispapiSetNotificationShare__ = &__nvoc_thunk_Notifier_dispapiSetNotificationShare; - pThis->__dispapiControlFilter__ = &__nvoc_thunk_RsResource_dispapiControlFilter; - pThis->__dispapiGetRefCount__ = &__nvoc_thunk_RsResource_dispapiGetRefCount; - pThis->__dispapiUnregisterEvent__ = &__nvoc_thunk_Notifier_dispapiUnregisterEvent; - pThis->__dispapiUnmap__ = &__nvoc_thunk_RsResource_dispapiUnmap; + pThis->__dispapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_dispapiControlSerialization_Prologue; pThis->__dispapiCanCopy__ = &__nvoc_thunk_RsResource_dispapiCanCopy; - pThis->__dispapiMapTo__ = &__nvoc_thunk_RsResource_dispapiMapTo; - - pThis->__dispapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_dispapiAddAdditionalDependants; - pThis->__dispapiPreDestruct__ = &__nvoc_thunk_RsResource_dispapiPreDestruct; - pThis->__dispapiUnmapFrom__ = &__nvoc_thunk_RsResource_dispapiUnmapFrom; - pThis->__dispapiIsDuplicate__ = &__nvoc_thunk_RsResource_dispapiIsDuplicate; + pThis->__dispapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_dispapiControlSerialization_Epilogue; + pThis->__dispapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_dispapiGetNotificationListPtr; pThis->__dispapiGetNotificationShare__ = &__nvoc_thunk_Notifier_dispapiGetNotificationShare; - pThis->__dispapiControlLookup__ = &__nvoc_thunk_RsResource_dispapiControlLookup; - pThis->__dispapiMap__ = &__nvoc_thunk_RsResource_dispapiMap; pThis->__dispapiGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_dispapiGetOrAllocNotifShare; @@ -334,13 +346,16 @@ NV_STATUS __nvoc_objCreate_DisplayApi(DisplayApi **ppThis, Dynamic *pParent, NvU DisplayApi *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(DisplayApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DisplayApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(DisplayApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DisplayApi); + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -360,11 +375,17 @@ NV_STATUS __nvoc_objCreate_DisplayApi(DisplayApi **ppThis, Dynamic *pParent, NvU if (status != NV_OK) goto __nvoc_objCreate_DisplayApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_DisplayApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(DisplayApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -486,14 +507,54 @@ static NvBool __nvoc_thunk_RmResource_dispobjShareCallback(struct DispObject *pR return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_DisplayApi_dispobjControl(struct DispObject *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return dispapiControl((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispObject_DisplayApi.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_dispobjCheckMemInterUnmap(struct DispObject *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispObject_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispobjMapTo(struct DispObject *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset), pParams); } static NvBool __nvoc_thunk_RmResource_dispobjAccessCallback(struct DispObject *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RmResource.offset), pInvokingClient, pAllocParams, accessRight); } +static void __nvoc_thunk_Notifier_dispobjSetNotificationShare(struct DispObject *pNotifier, struct NotifShare *pNotifShare) { + notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispObject_Notifier.offset), pNotifShare); +} + +static NvU32 __nvoc_thunk_RsResource_dispobjGetRefCount(struct DispObject *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_dispobjAddAdditionalDependants(struct RsClient *pClient, struct DispObject *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_DisplayApi_dispobjControl_Prologue(struct DispObject *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + return dispapiControl_Prologue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispObject_DisplayApi.offset), pCallContext, pRsParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispobjUnmapFrom(struct DispObject *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset), pParams); +} + +static void __nvoc_thunk_DisplayApi_dispobjControl_Epilogue(struct DispObject *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + dispapiControl_Epilogue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispObject_DisplayApi.offset), pCallContext, pRsParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispobjControlLookup(struct DispObject *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset), pParams, ppEntry); +} + +static NV_STATUS __nvoc_thunk_DisplayApi_dispobjControl(struct DispObject *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return dispapiControl((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispObject_DisplayApi.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispobjUnmap(struct DispObject *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset), pCallContext, pCpuMapping); +} + static NV_STATUS __nvoc_thunk_RmResource_dispobjGetMemInterMapParams(struct DispObject *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispObject_RmResource.offset), pParams); } @@ -502,74 +563,42 @@ static NV_STATUS __nvoc_thunk_RmResource_dispobjGetMemoryMappingDescriptor(struc return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispObject_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_RmResource_dispobjCheckMemInterUnmap(struct DispObject *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispObject_RmResource.offset), bSubdeviceHandleProvided); -} - -static void __nvoc_thunk_Notifier_dispobjSetNotificationShare(struct DispObject *pNotifier, struct NotifShare *pNotifShare) { - notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispObject_Notifier.offset), pNotifShare); -} - static NV_STATUS __nvoc_thunk_RsResource_dispobjControlFilter(struct DispObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset), pCallContext, pParams); } -static NvU32 __nvoc_thunk_RsResource_dispobjGetRefCount(struct DispObject *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_Notifier_dispobjUnregisterEvent(struct DispObject *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispObject_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static NV_STATUS __nvoc_thunk_RsResource_dispobjUnmap(struct DispObject *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset), pCallContext, pCpuMapping); -} - -static NV_STATUS __nvoc_thunk_DisplayApi_dispobjControl_Prologue(struct DispObject *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - return dispapiControl_Prologue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispObject_DisplayApi.offset), pCallContext, pRsParams); +static NV_STATUS __nvoc_thunk_RmResource_dispobjControlSerialization_Prologue(struct DispObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_dispobjCanCopy(struct DispObject *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_dispobjMapTo(struct DispObject *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RsResource_dispobjAddAdditionalDependants(struct RsClient *pClient, struct DispObject *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset), pReference); -} - static void __nvoc_thunk_RsResource_dispobjPreDestruct(struct DispObject *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_dispobjUnmapFrom(struct DispObject *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_dispobjIsDuplicate(struct DispObject *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_dispobjControlSerialization_Epilogue(struct DispObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_dispobjGetNotificationListPtr(struct DispObject *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispObject_Notifier.offset)); } -static void __nvoc_thunk_DisplayApi_dispobjControl_Epilogue(struct DispObject *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - dispapiControl_Epilogue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispObject_DisplayApi.offset), pCallContext, pRsParams); -} - static struct NotifShare *__nvoc_thunk_Notifier_dispobjGetNotificationShare(struct DispObject *pNotifier) { return notifyGetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispObject_Notifier.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_dispobjControlLookup(struct DispObject *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_RsResource_dispobjMap(struct DispObject *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return resMap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset), pCallContext, pParams, pCpuMapping); } @@ -735,27 +764,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispObje #endif }, { /* [10] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*pFunc=*/ (void (*)(void)) NULL, -#else - /*pFunc=*/ (void (*)(void)) dispobjCtrlCmdGetRgConnectedLockpin_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, - /*accessRight=*/0x0u, - /*methodId=*/ 0x50700207u, - /*paramSize=*/ sizeof(NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS), - /*pClassInfo=*/ &(__nvoc_class_def_DispObject.classInfo), -#if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "dispobjCtrlCmdGetRgConnectedLockpin" -#endif - }, - { /* [11] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispobjCtrlCmdGetRgConnectedLockpinStateless_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) - /*flags=*/ 0x200u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + /*flags=*/ 0x0u, /*accessRight=*/0x0u, /*methodId=*/ 0x5070020au, /*paramSize=*/ sizeof(NV5070_CTRL_GET_RG_CONNECTED_LOCKPIN_STATELESS_PARAMS), @@ -764,7 +778,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispObje /*func=*/ "dispobjCtrlCmdGetRgConnectedLockpinStateless" #endif }, - { /* [12] */ + { /* [11] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -779,7 +793,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispObje /*func=*/ "dispobjCtrlCmdGetPinsetLockpins" #endif }, - { /* [13] */ + { /* [12] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -794,7 +808,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispObje /*func=*/ "dispobjCtrlCmdGetRgScanLine" #endif }, - { /* [14] */ + { /* [13] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -809,7 +823,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispObje /*func=*/ "dispobjCtrlCmdGetFrameLockHeaderLockPins" #endif }, - { /* [15] */ + { /* [14] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -824,7 +838,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispObje /*func=*/ "dispobjCtrlCmdGetSorSeqCtl" #endif }, - { /* [16] */ + { /* [15] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -839,7 +853,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispObje /*func=*/ "dispobjCtrlCmdSetSorSeqCtl" #endif }, - { /* [17] */ + { /* [16] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -854,7 +868,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispObje /*func=*/ "dispobjCtrlCmdGetPiorSeqCtl" #endif }, - { /* [18] */ + { /* [17] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -869,7 +883,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispObje /*func=*/ "dispobjCtrlCmdSetPiorSeqCtl" #endif }, - { /* [19] */ + { /* [18] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -884,7 +898,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispObje /*func=*/ "dispobjCtrlCmdSeqProgSpeed" #endif }, - { /* [20] */ + { /* [19] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -899,7 +913,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispObje /*func=*/ "dispobjCtrlCmdGetSorPwm" #endif }, - { /* [21] */ + { /* [20] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -914,7 +928,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispObje /*func=*/ "dispobjCtrlCmdSetSorPwm" #endif }, - { /* [22] */ + { /* [21] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -929,7 +943,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispObje /*func=*/ "dispobjCtrlCmdGetSorOpMode" #endif }, - { /* [23] */ + { /* [22] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -944,7 +958,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispObje /*func=*/ "dispobjCtrlCmdSetSorOpMode" #endif }, - { /* [24] */ + { /* [23] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -959,7 +973,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispObje /*func=*/ "dispobjCtrlCmdGetPiorOpMode" #endif }, - { /* [25] */ + { /* [24] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -974,7 +988,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispObje /*func=*/ "dispobjCtrlCmdSetPiorOpMode" #endif }, - { /* [26] */ + { /* [25] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -989,7 +1003,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispObje /*func=*/ "dispobjCtrlCmdSetSorFlushMode" #endif }, - { /* [27] */ + { /* [26] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1004,7 +1018,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispObje /*func=*/ "dispobjCtrlCmdSystemGetCapsV2" #endif }, - { /* [28] */ + { /* [27] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1019,7 +1033,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispObje /*func=*/ "dispobjCtrlCmdEventSetTrigger" #endif }, - { /* [29] */ + { /* [28] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1039,7 +1053,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispObje const struct NVOC_EXPORT_INFO __nvoc_export_info_DispObject = { - /*numEntries=*/ 30, + /*numEntries=*/ 29, /*pExportEntries=*/ __nvoc_exported_method_def_DispObject }; @@ -1153,11 +1167,7 @@ static void __nvoc_init_funcTable_DispObject_1(DispObject *pThis, RmHalspecOwner pThis->__dispobjCtrlCmdSetRgFliplockProp__ = &dispobjCtrlCmdSetRgFliplockProp_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - pThis->__dispobjCtrlCmdGetRgConnectedLockpin__ = &dispobjCtrlCmdGetRgConnectedLockpin_IMPL; -#endif - -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) pThis->__dispobjCtrlCmdGetRgConnectedLockpinStateless__ = &dispobjCtrlCmdGetRgConnectedLockpinStateless_IMPL; #endif @@ -1207,48 +1217,52 @@ static void __nvoc_init_funcTable_DispObject_1(DispObject *pThis, RmHalspecOwner pThis->__dispobjShareCallback__ = &__nvoc_thunk_RmResource_dispobjShareCallback; - pThis->__dispobjControl__ = &__nvoc_thunk_DisplayApi_dispobjControl; + pThis->__dispobjCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispobjCheckMemInterUnmap; + + pThis->__dispobjMapTo__ = &__nvoc_thunk_RsResource_dispobjMapTo; pThis->__dispobjAccessCallback__ = &__nvoc_thunk_RmResource_dispobjAccessCallback; + pThis->__dispobjSetNotificationShare__ = &__nvoc_thunk_Notifier_dispobjSetNotificationShare; + + pThis->__dispobjGetRefCount__ = &__nvoc_thunk_RsResource_dispobjGetRefCount; + + pThis->__dispobjAddAdditionalDependants__ = &__nvoc_thunk_RsResource_dispobjAddAdditionalDependants; + + pThis->__dispobjControl_Prologue__ = &__nvoc_thunk_DisplayApi_dispobjControl_Prologue; + + pThis->__dispobjUnmapFrom__ = &__nvoc_thunk_RsResource_dispobjUnmapFrom; + + pThis->__dispobjControl_Epilogue__ = &__nvoc_thunk_DisplayApi_dispobjControl_Epilogue; + + pThis->__dispobjControlLookup__ = &__nvoc_thunk_RsResource_dispobjControlLookup; + + pThis->__dispobjControl__ = &__nvoc_thunk_DisplayApi_dispobjControl; + + pThis->__dispobjUnmap__ = &__nvoc_thunk_RsResource_dispobjUnmap; + pThis->__dispobjGetMemInterMapParams__ = &__nvoc_thunk_RmResource_dispobjGetMemInterMapParams; pThis->__dispobjGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_dispobjGetMemoryMappingDescriptor; - pThis->__dispobjCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispobjCheckMemInterUnmap; - - pThis->__dispobjSetNotificationShare__ = &__nvoc_thunk_Notifier_dispobjSetNotificationShare; - pThis->__dispobjControlFilter__ = &__nvoc_thunk_RsResource_dispobjControlFilter; - pThis->__dispobjGetRefCount__ = &__nvoc_thunk_RsResource_dispobjGetRefCount; - pThis->__dispobjUnregisterEvent__ = &__nvoc_thunk_Notifier_dispobjUnregisterEvent; - pThis->__dispobjUnmap__ = &__nvoc_thunk_RsResource_dispobjUnmap; - - pThis->__dispobjControl_Prologue__ = &__nvoc_thunk_DisplayApi_dispobjControl_Prologue; + pThis->__dispobjControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_dispobjControlSerialization_Prologue; pThis->__dispobjCanCopy__ = &__nvoc_thunk_RsResource_dispobjCanCopy; - pThis->__dispobjMapTo__ = &__nvoc_thunk_RsResource_dispobjMapTo; - - pThis->__dispobjAddAdditionalDependants__ = &__nvoc_thunk_RsResource_dispobjAddAdditionalDependants; - pThis->__dispobjPreDestruct__ = &__nvoc_thunk_RsResource_dispobjPreDestruct; - pThis->__dispobjUnmapFrom__ = &__nvoc_thunk_RsResource_dispobjUnmapFrom; - pThis->__dispobjIsDuplicate__ = &__nvoc_thunk_RsResource_dispobjIsDuplicate; + pThis->__dispobjControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_dispobjControlSerialization_Epilogue; + pThis->__dispobjGetNotificationListPtr__ = &__nvoc_thunk_Notifier_dispobjGetNotificationListPtr; - pThis->__dispobjControl_Epilogue__ = &__nvoc_thunk_DisplayApi_dispobjControl_Epilogue; - pThis->__dispobjGetNotificationShare__ = &__nvoc_thunk_Notifier_dispobjGetNotificationShare; - pThis->__dispobjControlLookup__ = &__nvoc_thunk_RsResource_dispobjControlLookup; - pThis->__dispobjMap__ = &__nvoc_thunk_RsResource_dispobjMap; pThis->__dispobjGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_dispobjGetOrAllocNotifShare; @@ -1278,13 +1292,16 @@ NV_STATUS __nvoc_objCreate_DispObject(DispObject **ppThis, Dynamic *pParent, NvU DispObject *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(DispObject)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DispObject), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(DispObject)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DispObject); + pThis->__nvoc_base_DisplayApi.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -1304,11 +1321,17 @@ NV_STATUS __nvoc_objCreate_DispObject(DispObject **ppThis, Dynamic *pParent, NvU if (status != NV_OK) goto __nvoc_objCreate_DispObject_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_DispObject_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(DispObject)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -1439,14 +1462,54 @@ static NvBool __nvoc_thunk_RmResource_nvdispapiShareCallback(struct NvDispApi *p return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_DisplayApi_nvdispapiControl(struct NvDispApi *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return dispapiControl((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_NvDispApi_DisplayApi.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_nvdispapiCheckMemInterUnmap(struct NvDispApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_NvDispApi_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_nvdispapiMapTo(struct NvDispApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset), pParams); } static NvBool __nvoc_thunk_RmResource_nvdispapiAccessCallback(struct NvDispApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RmResource.offset), pInvokingClient, pAllocParams, accessRight); } +static void __nvoc_thunk_Notifier_nvdispapiSetNotificationShare(struct NvDispApi *pNotifier, struct NotifShare *pNotifShare) { + notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_NvDispApi_Notifier.offset), pNotifShare); +} + +static NvU32 __nvoc_thunk_RsResource_nvdispapiGetRefCount(struct NvDispApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_nvdispapiAddAdditionalDependants(struct RsClient *pClient, struct NvDispApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_DisplayApi_nvdispapiControl_Prologue(struct NvDispApi *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + return dispapiControl_Prologue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_NvDispApi_DisplayApi.offset), pCallContext, pRsParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_nvdispapiUnmapFrom(struct NvDispApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset), pParams); +} + +static void __nvoc_thunk_DisplayApi_nvdispapiControl_Epilogue(struct NvDispApi *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + dispapiControl_Epilogue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_NvDispApi_DisplayApi.offset), pCallContext, pRsParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_nvdispapiControlLookup(struct NvDispApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset), pParams, ppEntry); +} + +static NV_STATUS __nvoc_thunk_DisplayApi_nvdispapiControl(struct NvDispApi *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return dispapiControl((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_NvDispApi_DisplayApi.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_nvdispapiUnmap(struct NvDispApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset), pCallContext, pCpuMapping); +} + static NV_STATUS __nvoc_thunk_RmResource_nvdispapiGetMemInterMapParams(struct NvDispApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_NvDispApi_RmResource.offset), pParams); } @@ -1455,74 +1518,42 @@ static NV_STATUS __nvoc_thunk_RmResource_nvdispapiGetMemoryMappingDescriptor(str return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_NvDispApi_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_RmResource_nvdispapiCheckMemInterUnmap(struct NvDispApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_NvDispApi_RmResource.offset), bSubdeviceHandleProvided); -} - -static void __nvoc_thunk_Notifier_nvdispapiSetNotificationShare(struct NvDispApi *pNotifier, struct NotifShare *pNotifShare) { - notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_NvDispApi_Notifier.offset), pNotifShare); -} - static NV_STATUS __nvoc_thunk_RsResource_nvdispapiControlFilter(struct NvDispApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset), pCallContext, pParams); } -static NvU32 __nvoc_thunk_RsResource_nvdispapiGetRefCount(struct NvDispApi *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_Notifier_nvdispapiUnregisterEvent(struct NvDispApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_NvDispApi_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static NV_STATUS __nvoc_thunk_RsResource_nvdispapiUnmap(struct NvDispApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset), pCallContext, pCpuMapping); -} - -static NV_STATUS __nvoc_thunk_DisplayApi_nvdispapiControl_Prologue(struct NvDispApi *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - return dispapiControl_Prologue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_NvDispApi_DisplayApi.offset), pCallContext, pRsParams); +static NV_STATUS __nvoc_thunk_RmResource_nvdispapiControlSerialization_Prologue(struct NvDispApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_nvdispapiCanCopy(struct NvDispApi *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_nvdispapiMapTo(struct NvDispApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RsResource_nvdispapiAddAdditionalDependants(struct RsClient *pClient, struct NvDispApi *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset), pReference); -} - static void __nvoc_thunk_RsResource_nvdispapiPreDestruct(struct NvDispApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_nvdispapiUnmapFrom(struct NvDispApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_nvdispapiIsDuplicate(struct NvDispApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_nvdispapiControlSerialization_Epilogue(struct NvDispApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_nvdispapiGetNotificationListPtr(struct NvDispApi *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_NvDispApi_Notifier.offset)); } -static void __nvoc_thunk_DisplayApi_nvdispapiControl_Epilogue(struct NvDispApi *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - dispapiControl_Epilogue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_NvDispApi_DisplayApi.offset), pCallContext, pRsParams); -} - static struct NotifShare *__nvoc_thunk_Notifier_nvdispapiGetNotificationShare(struct NvDispApi *pNotifier) { return notifyGetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_NvDispApi_Notifier.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_nvdispapiControlLookup(struct NvDispApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_RsResource_nvdispapiMap(struct NvDispApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return resMap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset), pCallContext, pParams, pCpuMapping); } @@ -1713,48 +1744,52 @@ static void __nvoc_init_funcTable_NvDispApi_1(NvDispApi *pThis) { pThis->__nvdispapiShareCallback__ = &__nvoc_thunk_RmResource_nvdispapiShareCallback; - pThis->__nvdispapiControl__ = &__nvoc_thunk_DisplayApi_nvdispapiControl; + pThis->__nvdispapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_nvdispapiCheckMemInterUnmap; + + pThis->__nvdispapiMapTo__ = &__nvoc_thunk_RsResource_nvdispapiMapTo; pThis->__nvdispapiAccessCallback__ = &__nvoc_thunk_RmResource_nvdispapiAccessCallback; + pThis->__nvdispapiSetNotificationShare__ = &__nvoc_thunk_Notifier_nvdispapiSetNotificationShare; + + pThis->__nvdispapiGetRefCount__ = &__nvoc_thunk_RsResource_nvdispapiGetRefCount; + + pThis->__nvdispapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_nvdispapiAddAdditionalDependants; + + pThis->__nvdispapiControl_Prologue__ = &__nvoc_thunk_DisplayApi_nvdispapiControl_Prologue; + + pThis->__nvdispapiUnmapFrom__ = &__nvoc_thunk_RsResource_nvdispapiUnmapFrom; + + pThis->__nvdispapiControl_Epilogue__ = &__nvoc_thunk_DisplayApi_nvdispapiControl_Epilogue; + + pThis->__nvdispapiControlLookup__ = &__nvoc_thunk_RsResource_nvdispapiControlLookup; + + pThis->__nvdispapiControl__ = &__nvoc_thunk_DisplayApi_nvdispapiControl; + + pThis->__nvdispapiUnmap__ = &__nvoc_thunk_RsResource_nvdispapiUnmap; + pThis->__nvdispapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_nvdispapiGetMemInterMapParams; pThis->__nvdispapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_nvdispapiGetMemoryMappingDescriptor; - pThis->__nvdispapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_nvdispapiCheckMemInterUnmap; - - pThis->__nvdispapiSetNotificationShare__ = &__nvoc_thunk_Notifier_nvdispapiSetNotificationShare; - pThis->__nvdispapiControlFilter__ = &__nvoc_thunk_RsResource_nvdispapiControlFilter; - pThis->__nvdispapiGetRefCount__ = &__nvoc_thunk_RsResource_nvdispapiGetRefCount; - pThis->__nvdispapiUnregisterEvent__ = &__nvoc_thunk_Notifier_nvdispapiUnregisterEvent; - pThis->__nvdispapiUnmap__ = &__nvoc_thunk_RsResource_nvdispapiUnmap; - - pThis->__nvdispapiControl_Prologue__ = &__nvoc_thunk_DisplayApi_nvdispapiControl_Prologue; + pThis->__nvdispapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_nvdispapiControlSerialization_Prologue; pThis->__nvdispapiCanCopy__ = &__nvoc_thunk_RsResource_nvdispapiCanCopy; - pThis->__nvdispapiMapTo__ = &__nvoc_thunk_RsResource_nvdispapiMapTo; - - pThis->__nvdispapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_nvdispapiAddAdditionalDependants; - pThis->__nvdispapiPreDestruct__ = &__nvoc_thunk_RsResource_nvdispapiPreDestruct; - pThis->__nvdispapiUnmapFrom__ = &__nvoc_thunk_RsResource_nvdispapiUnmapFrom; - pThis->__nvdispapiIsDuplicate__ = &__nvoc_thunk_RsResource_nvdispapiIsDuplicate; + pThis->__nvdispapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_nvdispapiControlSerialization_Epilogue; + pThis->__nvdispapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_nvdispapiGetNotificationListPtr; - pThis->__nvdispapiControl_Epilogue__ = &__nvoc_thunk_DisplayApi_nvdispapiControl_Epilogue; - pThis->__nvdispapiGetNotificationShare__ = &__nvoc_thunk_Notifier_nvdispapiGetNotificationShare; - pThis->__nvdispapiControlLookup__ = &__nvoc_thunk_RsResource_nvdispapiControlLookup; - pThis->__nvdispapiMap__ = &__nvoc_thunk_RsResource_nvdispapiMap; pThis->__nvdispapiGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_nvdispapiGetOrAllocNotifShare; @@ -1785,13 +1820,16 @@ NV_STATUS __nvoc_objCreate_NvDispApi(NvDispApi **ppThis, Dynamic *pParent, NvU32 NvDispApi *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(NvDispApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(NvDispApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(NvDispApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_NvDispApi); + pThis->__nvoc_base_DispObject.__nvoc_base_DisplayApi.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -1811,11 +1849,17 @@ NV_STATUS __nvoc_objCreate_NvDispApi(NvDispApi **ppThis, Dynamic *pParent, NvU32 if (status != NV_OK) goto __nvoc_objCreate_NvDispApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_NvDispApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(NvDispApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -1937,14 +1981,54 @@ static NvBool __nvoc_thunk_RmResource_dispswobjShareCallback(struct DispSwObj *p return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_DisplayApi_dispswobjControl(struct DispSwObj *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return dispapiControl((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispSwObj_DisplayApi.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_dispswobjCheckMemInterUnmap(struct DispSwObj *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispSwObj_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispswobjMapTo(struct DispSwObj *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset), pParams); } static NvBool __nvoc_thunk_RmResource_dispswobjAccessCallback(struct DispSwObj *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RmResource.offset), pInvokingClient, pAllocParams, accessRight); } +static void __nvoc_thunk_Notifier_dispswobjSetNotificationShare(struct DispSwObj *pNotifier, struct NotifShare *pNotifShare) { + notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispSwObj_Notifier.offset), pNotifShare); +} + +static NvU32 __nvoc_thunk_RsResource_dispswobjGetRefCount(struct DispSwObj *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_dispswobjAddAdditionalDependants(struct RsClient *pClient, struct DispSwObj *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_DisplayApi_dispswobjControl_Prologue(struct DispSwObj *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + return dispapiControl_Prologue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispSwObj_DisplayApi.offset), pCallContext, pRsParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispswobjUnmapFrom(struct DispSwObj *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset), pParams); +} + +static void __nvoc_thunk_DisplayApi_dispswobjControl_Epilogue(struct DispSwObj *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + dispapiControl_Epilogue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispSwObj_DisplayApi.offset), pCallContext, pRsParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispswobjControlLookup(struct DispSwObj *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset), pParams, ppEntry); +} + +static NV_STATUS __nvoc_thunk_DisplayApi_dispswobjControl(struct DispSwObj *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return dispapiControl((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispSwObj_DisplayApi.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispswobjUnmap(struct DispSwObj *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset), pCallContext, pCpuMapping); +} + static NV_STATUS __nvoc_thunk_RmResource_dispswobjGetMemInterMapParams(struct DispSwObj *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispSwObj_RmResource.offset), pParams); } @@ -1953,74 +2037,42 @@ static NV_STATUS __nvoc_thunk_RmResource_dispswobjGetMemoryMappingDescriptor(str return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispSwObj_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_RmResource_dispswobjCheckMemInterUnmap(struct DispSwObj *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispSwObj_RmResource.offset), bSubdeviceHandleProvided); -} - -static void __nvoc_thunk_Notifier_dispswobjSetNotificationShare(struct DispSwObj *pNotifier, struct NotifShare *pNotifShare) { - notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispSwObj_Notifier.offset), pNotifShare); -} - static NV_STATUS __nvoc_thunk_RsResource_dispswobjControlFilter(struct DispSwObj *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset), pCallContext, pParams); } -static NvU32 __nvoc_thunk_RsResource_dispswobjGetRefCount(struct DispSwObj *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_Notifier_dispswobjUnregisterEvent(struct DispSwObj *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispSwObj_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static NV_STATUS __nvoc_thunk_RsResource_dispswobjUnmap(struct DispSwObj *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset), pCallContext, pCpuMapping); -} - -static NV_STATUS __nvoc_thunk_DisplayApi_dispswobjControl_Prologue(struct DispSwObj *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - return dispapiControl_Prologue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispSwObj_DisplayApi.offset), pCallContext, pRsParams); +static NV_STATUS __nvoc_thunk_RmResource_dispswobjControlSerialization_Prologue(struct DispSwObj *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_dispswobjCanCopy(struct DispSwObj *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_dispswobjMapTo(struct DispSwObj *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RsResource_dispswobjAddAdditionalDependants(struct RsClient *pClient, struct DispSwObj *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset), pReference); -} - static void __nvoc_thunk_RsResource_dispswobjPreDestruct(struct DispSwObj *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_dispswobjUnmapFrom(struct DispSwObj *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_dispswobjIsDuplicate(struct DispSwObj *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_dispswobjControlSerialization_Epilogue(struct DispSwObj *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_dispswobjGetNotificationListPtr(struct DispSwObj *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispSwObj_Notifier.offset)); } -static void __nvoc_thunk_DisplayApi_dispswobjControl_Epilogue(struct DispSwObj *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - dispapiControl_Epilogue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispSwObj_DisplayApi.offset), pCallContext, pRsParams); -} - static struct NotifShare *__nvoc_thunk_Notifier_dispswobjGetNotificationShare(struct DispSwObj *pNotifier) { return notifyGetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispSwObj_Notifier.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_dispswobjControlLookup(struct DispSwObj *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_RsResource_dispswobjMap(struct DispSwObj *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return resMap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset), pCallContext, pParams, pCpuMapping); } @@ -2154,48 +2206,52 @@ static void __nvoc_init_funcTable_DispSwObj_1(DispSwObj *pThis) { pThis->__dispswobjShareCallback__ = &__nvoc_thunk_RmResource_dispswobjShareCallback; - pThis->__dispswobjControl__ = &__nvoc_thunk_DisplayApi_dispswobjControl; + pThis->__dispswobjCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispswobjCheckMemInterUnmap; + + pThis->__dispswobjMapTo__ = &__nvoc_thunk_RsResource_dispswobjMapTo; pThis->__dispswobjAccessCallback__ = &__nvoc_thunk_RmResource_dispswobjAccessCallback; + pThis->__dispswobjSetNotificationShare__ = &__nvoc_thunk_Notifier_dispswobjSetNotificationShare; + + pThis->__dispswobjGetRefCount__ = &__nvoc_thunk_RsResource_dispswobjGetRefCount; + + pThis->__dispswobjAddAdditionalDependants__ = &__nvoc_thunk_RsResource_dispswobjAddAdditionalDependants; + + pThis->__dispswobjControl_Prologue__ = &__nvoc_thunk_DisplayApi_dispswobjControl_Prologue; + + pThis->__dispswobjUnmapFrom__ = &__nvoc_thunk_RsResource_dispswobjUnmapFrom; + + pThis->__dispswobjControl_Epilogue__ = &__nvoc_thunk_DisplayApi_dispswobjControl_Epilogue; + + pThis->__dispswobjControlLookup__ = &__nvoc_thunk_RsResource_dispswobjControlLookup; + + pThis->__dispswobjControl__ = &__nvoc_thunk_DisplayApi_dispswobjControl; + + pThis->__dispswobjUnmap__ = &__nvoc_thunk_RsResource_dispswobjUnmap; + pThis->__dispswobjGetMemInterMapParams__ = &__nvoc_thunk_RmResource_dispswobjGetMemInterMapParams; pThis->__dispswobjGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_dispswobjGetMemoryMappingDescriptor; - pThis->__dispswobjCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispswobjCheckMemInterUnmap; - - pThis->__dispswobjSetNotificationShare__ = &__nvoc_thunk_Notifier_dispswobjSetNotificationShare; - pThis->__dispswobjControlFilter__ = &__nvoc_thunk_RsResource_dispswobjControlFilter; - pThis->__dispswobjGetRefCount__ = &__nvoc_thunk_RsResource_dispswobjGetRefCount; - pThis->__dispswobjUnregisterEvent__ = &__nvoc_thunk_Notifier_dispswobjUnregisterEvent; - pThis->__dispswobjUnmap__ = &__nvoc_thunk_RsResource_dispswobjUnmap; - - pThis->__dispswobjControl_Prologue__ = &__nvoc_thunk_DisplayApi_dispswobjControl_Prologue; + pThis->__dispswobjControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_dispswobjControlSerialization_Prologue; pThis->__dispswobjCanCopy__ = &__nvoc_thunk_RsResource_dispswobjCanCopy; - pThis->__dispswobjMapTo__ = &__nvoc_thunk_RsResource_dispswobjMapTo; - - pThis->__dispswobjAddAdditionalDependants__ = &__nvoc_thunk_RsResource_dispswobjAddAdditionalDependants; - pThis->__dispswobjPreDestruct__ = &__nvoc_thunk_RsResource_dispswobjPreDestruct; - pThis->__dispswobjUnmapFrom__ = &__nvoc_thunk_RsResource_dispswobjUnmapFrom; - pThis->__dispswobjIsDuplicate__ = &__nvoc_thunk_RsResource_dispswobjIsDuplicate; + pThis->__dispswobjControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_dispswobjControlSerialization_Epilogue; + pThis->__dispswobjGetNotificationListPtr__ = &__nvoc_thunk_Notifier_dispswobjGetNotificationListPtr; - pThis->__dispswobjControl_Epilogue__ = &__nvoc_thunk_DisplayApi_dispswobjControl_Epilogue; - pThis->__dispswobjGetNotificationShare__ = &__nvoc_thunk_Notifier_dispswobjGetNotificationShare; - pThis->__dispswobjControlLookup__ = &__nvoc_thunk_RsResource_dispswobjControlLookup; - pThis->__dispswobjMap__ = &__nvoc_thunk_RsResource_dispswobjMap; pThis->__dispswobjGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_dispswobjGetOrAllocNotifShare; @@ -2225,13 +2281,16 @@ NV_STATUS __nvoc_objCreate_DispSwObj(DispSwObj **ppThis, Dynamic *pParent, NvU32 DispSwObj *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(DispSwObj)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DispSwObj), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(DispSwObj)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DispSwObj); + pThis->__nvoc_base_DisplayApi.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -2251,11 +2310,17 @@ NV_STATUS __nvoc_objCreate_DispSwObj(DispSwObj **ppThis, Dynamic *pParent, NvU32 if (status != NV_OK) goto __nvoc_objCreate_DispSwObj_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_DispSwObj_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(DispSwObj)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -2377,14 +2442,54 @@ static NvBool __nvoc_thunk_RmResource_dispcmnShareCallback(struct DispCommon *pR return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_DisplayApi_dispcmnControl(struct DispCommon *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return dispapiControl((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispCommon_DisplayApi.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_dispcmnCheckMemInterUnmap(struct DispCommon *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispCommon_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispcmnMapTo(struct DispCommon *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset), pParams); } static NvBool __nvoc_thunk_RmResource_dispcmnAccessCallback(struct DispCommon *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RmResource.offset), pInvokingClient, pAllocParams, accessRight); } +static void __nvoc_thunk_Notifier_dispcmnSetNotificationShare(struct DispCommon *pNotifier, struct NotifShare *pNotifShare) { + notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispCommon_Notifier.offset), pNotifShare); +} + +static NvU32 __nvoc_thunk_RsResource_dispcmnGetRefCount(struct DispCommon *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_dispcmnAddAdditionalDependants(struct RsClient *pClient, struct DispCommon *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_DisplayApi_dispcmnControl_Prologue(struct DispCommon *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + return dispapiControl_Prologue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispCommon_DisplayApi.offset), pCallContext, pRsParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispcmnUnmapFrom(struct DispCommon *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset), pParams); +} + +static void __nvoc_thunk_DisplayApi_dispcmnControl_Epilogue(struct DispCommon *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + dispapiControl_Epilogue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispCommon_DisplayApi.offset), pCallContext, pRsParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispcmnControlLookup(struct DispCommon *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset), pParams, ppEntry); +} + +static NV_STATUS __nvoc_thunk_DisplayApi_dispcmnControl(struct DispCommon *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return dispapiControl((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispCommon_DisplayApi.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispcmnUnmap(struct DispCommon *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset), pCallContext, pCpuMapping); +} + static NV_STATUS __nvoc_thunk_RmResource_dispcmnGetMemInterMapParams(struct DispCommon *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispCommon_RmResource.offset), pParams); } @@ -2393,74 +2498,42 @@ static NV_STATUS __nvoc_thunk_RmResource_dispcmnGetMemoryMappingDescriptor(struc return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispCommon_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_RmResource_dispcmnCheckMemInterUnmap(struct DispCommon *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispCommon_RmResource.offset), bSubdeviceHandleProvided); -} - -static void __nvoc_thunk_Notifier_dispcmnSetNotificationShare(struct DispCommon *pNotifier, struct NotifShare *pNotifShare) { - notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispCommon_Notifier.offset), pNotifShare); -} - static NV_STATUS __nvoc_thunk_RsResource_dispcmnControlFilter(struct DispCommon *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset), pCallContext, pParams); } -static NvU32 __nvoc_thunk_RsResource_dispcmnGetRefCount(struct DispCommon *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_Notifier_dispcmnUnregisterEvent(struct DispCommon *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispCommon_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static NV_STATUS __nvoc_thunk_RsResource_dispcmnUnmap(struct DispCommon *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset), pCallContext, pCpuMapping); -} - -static NV_STATUS __nvoc_thunk_DisplayApi_dispcmnControl_Prologue(struct DispCommon *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - return dispapiControl_Prologue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispCommon_DisplayApi.offset), pCallContext, pRsParams); +static NV_STATUS __nvoc_thunk_RmResource_dispcmnControlSerialization_Prologue(struct DispCommon *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_dispcmnCanCopy(struct DispCommon *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_dispcmnMapTo(struct DispCommon *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RsResource_dispcmnAddAdditionalDependants(struct RsClient *pClient, struct DispCommon *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset), pReference); -} - static void __nvoc_thunk_RsResource_dispcmnPreDestruct(struct DispCommon *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_dispcmnUnmapFrom(struct DispCommon *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_dispcmnIsDuplicate(struct DispCommon *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_dispcmnControlSerialization_Epilogue(struct DispCommon *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_dispcmnGetNotificationListPtr(struct DispCommon *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispCommon_Notifier.offset)); } -static void __nvoc_thunk_DisplayApi_dispcmnControl_Epilogue(struct DispCommon *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - dispapiControl_Epilogue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispCommon_DisplayApi.offset), pCallContext, pRsParams); -} - static struct NotifShare *__nvoc_thunk_Notifier_dispcmnGetNotificationShare(struct DispCommon *pNotifier) { return notifyGetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispCommon_Notifier.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_dispcmnControlLookup(struct DispCommon *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_RsResource_dispcmnMap(struct DispCommon *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return resMap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset), pCallContext, pParams, pCpuMapping); } @@ -2583,6 +2656,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm { /* [7] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSystemGetHotplugState_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x730124u, + /*paramSize=*/ sizeof(NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdSystemGetHotplugState" +#endif + }, + { /* [8] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSystemGetHeadRoutingMap_IMPL, #endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) @@ -2595,7 +2683,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemGetHeadRoutingMap" #endif }, - { /* [8] */ + { /* [9] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2610,7 +2698,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemGetActive" #endif }, - { /* [9] */ + { /* [10] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2625,7 +2713,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemGetCapsV2" #endif }, - { /* [10] */ + { /* [11] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2640,7 +2728,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemGetAcpiIdMap" #endif }, - { /* [11] */ + { /* [12] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2655,7 +2743,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemGetInternalDisplays" #endif }, - { /* [12] */ + { /* [13] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSystemGetConnectorTable_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x730165u, + /*paramSize=*/ sizeof(NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdSystemGetConnectorTable" +#endif + }, + { /* [14] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2670,7 +2773,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemGetBootDisplays" #endif }, - { /* [13] */ + { /* [15] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x12u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2685,7 +2788,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemExecuteAcpiMethod" #endif }, - { /* [14] */ + { /* [16] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2700,7 +2803,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemGetHotplugUnplugState" #endif }, - { /* [15] */ + { /* [17] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2715,7 +2818,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdClearELVBlock" #endif }, - { /* [16] */ + { /* [18] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2730,7 +2833,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemArmLightweightSupervisor" #endif }, - { /* [17] */ + { /* [19] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2745,7 +2848,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemConfigVrrPstateSwitch" #endif }, - { /* [18] */ + { /* [20] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2760,7 +2863,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemQueryDisplayIdsWithMux" #endif }, - { /* [19] */ + { /* [21] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2775,7 +2878,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemAllocateDisplayBandwidth" #endif }, - { /* [20] */ + { /* [22] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2790,7 +2893,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemGetHotplugEventConfig" #endif }, - { /* [21] */ + { /* [23] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2805,7 +2908,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemSetHotplugEventConfig" #endif }, - { /* [22] */ + { /* [24] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2820,7 +2923,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpRecordChannelRegisters" #endif }, - { /* [23] */ + { /* [25] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2835,7 +2938,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemCheckSidebandI2cSupport" #endif }, - { /* [24] */ + { /* [26] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2850,7 +2953,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemCheckSidebandSrSupport" #endif }, - { /* [25] */ + { /* [27] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2865,7 +2968,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetI2cPortid" #endif }, - { /* [26] */ + { /* [28] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x206u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2880,7 +2983,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetType" #endif }, - { /* [27] */ + { /* [29] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2895,7 +2998,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificFakeDevice" #endif }, - { /* [28] */ + { /* [30] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2910,7 +3013,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetEdidV2" #endif }, - { /* [29] */ + { /* [31] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2925,7 +3028,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetEdidV2" #endif }, - { /* [30] */ + { /* [32] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2940,7 +3043,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetConnectorData" #endif }, - { /* [31] */ + { /* [33] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2955,7 +3058,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetHdmiEnable" #endif }, - { /* [32] */ + { /* [34] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2970,7 +3073,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificCtrlHdmi" #endif }, - { /* [33] */ + { /* [35] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSpecificSetHdmiAudioMutestream_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x730275u, + /*paramSize=*/ sizeof(NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdSpecificSetHdmiAudioMutestream" +#endif + }, + { /* [36] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2985,7 +3103,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetAcpiIdMapping" #endif }, - { /* [34] */ + { /* [37] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3000,7 +3118,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetAcpiDodDisplayPortAttachment" #endif }, - { /* [35] */ + { /* [38] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3015,7 +3133,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetAllHeadMask" #endif }, - { /* [36] */ + { /* [39] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3030,7 +3148,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetOdPacket" #endif }, - { /* [37] */ + { /* [40] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3045,7 +3163,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetOdPacketCtrl" #endif }, - { /* [38] */ + { /* [41] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3060,7 +3178,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetPclkLimit" #endif }, - { /* [39] */ + { /* [42] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x206u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3075,7 +3193,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificOrGetInfo" #endif }, - { /* [40] */ + { /* [43] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3090,7 +3208,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetBacklightBrightness" #endif }, - { /* [41] */ + { /* [44] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3105,7 +3223,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetBacklightBrightness" #endif }, - { /* [42] */ + { /* [45] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3120,7 +3238,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetHdmiSinkCaps" #endif }, - { /* [43] */ + { /* [46] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3135,7 +3253,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetMonitorPower" #endif }, - { /* [44] */ + { /* [47] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3150,7 +3268,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetHdmiFrlLinkConfig" #endif }, - { /* [45] */ + { /* [48] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3165,7 +3283,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificApplyEdidOverrideV2" #endif }, - { /* [46] */ + { /* [49] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3180,7 +3298,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetHdmiGpuCaps" #endif }, - { /* [47] */ + { /* [50] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3195,7 +3313,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificDisplayChange" #endif }, - { /* [48] */ + { /* [51] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3210,7 +3328,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetHdmiScdcData" #endif }, - { /* [49] */ + { /* [52] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3225,7 +3343,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificIsDirectmodeDisplay" #endif }, - { /* [50] */ + { /* [53] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3240,7 +3358,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation" #endif }, - { /* [51] */ + { /* [54] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3255,7 +3373,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetSharedGenericPacket" #endif }, - { /* [52] */ + { /* [55] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3270,7 +3388,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificAcquireSharedGenericPacket" #endif }, - { /* [53] */ + { /* [56] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3285,7 +3403,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificReleaseSharedGenericPacket" #endif }, - { /* [54] */ + { /* [57] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3300,7 +3418,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificDispI2cReadWrite" #endif }, - { /* [55] */ + { /* [58] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3315,7 +3433,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment" #endif }, - { /* [56] */ + { /* [59] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSpecificDefaultAdaptivesyncDisplay_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*flags=*/ 0x200u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x7302aeu, + /*paramSize=*/ sizeof(NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdSpecificDefaultAdaptivesyncDisplay" +#endif + }, + { /* [60] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3330,13 +3463,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdInternalGetHotplugUnplugState" #endif }, - { /* [57] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x206u) + { /* [61] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDfpGetInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x206u) - /*flags=*/ 0x206u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) + /*flags=*/ 0x212u, /*accessRight=*/0x0u, /*methodId=*/ 0x731140u, /*paramSize=*/ sizeof(NV0073_CTRL_DFP_GET_INFO_PARAMS), @@ -3345,7 +3478,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetInfo" #endif }, - { /* [58] */ + { /* [62] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3360,7 +3493,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetDisplayportDongleInfo" #endif }, - { /* [59] */ + { /* [63] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3375,7 +3508,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpSetEldAudioCaps" #endif }, - { /* [60] */ + { /* [64] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3390,7 +3523,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetSpreadSpectrum" #endif }, - { /* [61] */ + { /* [65] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3405,7 +3538,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpUpdateDynamicDfpCache" #endif }, - { /* [62] */ + { /* [66] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3420,13 +3553,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpSetAudioEnable" #endif }, - { /* [63] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + { /* [67] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDfpAssignSor_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) - /*flags=*/ 0x204u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*flags=*/ 0x200u, /*accessRight=*/0x0u, /*methodId=*/ 0x731152u, /*paramSize=*/ sizeof(NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS), @@ -3435,7 +3568,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpAssignSor" #endif }, - { /* [64] */ + { /* [68] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3450,7 +3583,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetPadlinkMask" #endif }, - { /* [65] */ + { /* [69] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3465,7 +3598,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetLcdGpioPinNum" #endif }, - { /* [66] */ + { /* [70] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3480,7 +3613,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpConfigTwoHeadOneOr" #endif }, - { /* [67] */ + { /* [71] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3495,7 +3628,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpDscCrcControl" #endif }, - { /* [68] */ + { /* [72] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3510,7 +3643,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpInitMuxData" #endif }, - { /* [69] */ + { /* [73] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3525,7 +3658,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpSwitchDispMux" #endif }, - { /* [70] */ + { /* [74] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3540,7 +3673,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpRunPreDispMuxOperations" #endif }, - { /* [71] */ + { /* [75] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3555,7 +3688,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpRunPostDispMuxOperations" #endif }, - { /* [72] */ + { /* [76] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3570,7 +3703,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetDispMuxStatus" #endif }, - { /* [73] */ + { /* [77] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3585,7 +3718,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetDsiModeTiming" #endif }, - { /* [74] */ + { /* [78] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x202u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3600,7 +3733,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetFixedModeTiming" #endif }, - { /* [75] */ + { /* [79] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3615,7 +3748,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpAuxchCtrl" #endif }, - { /* [76] */ + { /* [80] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3630,7 +3763,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpAuxchSetSema" #endif }, - { /* [77] */ + { /* [81] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3645,7 +3778,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpCtrl" #endif }, - { /* [78] */ + { /* [82] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3660,7 +3793,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetLaneData" #endif }, - { /* [79] */ + { /* [83] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3675,7 +3808,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetLaneData" #endif }, - { /* [80] */ + { /* [84] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3690,7 +3823,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetTestpattern" #endif }, - { /* [81] */ + { /* [85] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3705,7 +3838,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetPreemphasisDrivecurrentPostcursor2Data" #endif }, - { /* [82] */ + { /* [86] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3720,7 +3853,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetPreemphasisDrivecurrentPostcursor2Data" #endif }, - { /* [83] */ + { /* [87] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3735,7 +3868,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpMainLinkCtrl" #endif }, - { /* [84] */ + { /* [88] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3750,7 +3883,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetAudioMuteStream" #endif }, - { /* [85] */ + { /* [89] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3765,7 +3898,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetAudioMuteStream" #endif }, - { /* [86] */ + { /* [90] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3780,7 +3913,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpASSRCtrl" #endif }, - { /* [87] */ + { /* [91] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3795,7 +3928,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpTopologyAllocateDisplayId" #endif }, - { /* [88] */ + { /* [92] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3810,7 +3943,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpTopologyFreeDisplayId" #endif }, - { /* [89] */ + { /* [93] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3825,7 +3958,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetLinkConfig" #endif }, - { /* [90] */ + { /* [94] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3840,7 +3973,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetEDPData" #endif }, - { /* [91] */ + { /* [95] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3855,7 +3988,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpConfigStream" #endif }, - { /* [92] */ + { /* [96] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3870,7 +4003,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetRateGov" #endif }, - { /* [93] */ + { /* [97] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3885,7 +4018,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetManualDisplayPort" #endif }, - { /* [94] */ + { /* [98] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3900,7 +4033,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetEcf" #endif }, - { /* [95] */ + { /* [99] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3915,7 +4048,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSendACT" #endif }, - { /* [96] */ + { /* [100] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x206u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3930,7 +4063,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetCaps" #endif }, - { /* [97] */ + { /* [101] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3945,7 +4078,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGenerateFakeInterrupt" #endif }, - { /* [98] */ + { /* [102] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3960,7 +4093,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpConfigRadScratchReg" #endif }, - { /* [99] */ + { /* [103] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3975,7 +4108,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpConfigSingleHeadMultiStream" #endif }, - { /* [100] */ + { /* [104] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3990,7 +4123,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetTriggerSelect" #endif }, - { /* [101] */ + { /* [105] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4005,7 +4138,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetTriggerAll" #endif }, - { /* [102] */ + { /* [106] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4020,7 +4153,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetAuxLogData" #endif }, - { /* [103] */ + { /* [107] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4035,7 +4168,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpConfigIndexedLinkRates" #endif }, - { /* [104] */ + { /* [108] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4050,7 +4183,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetStereoMSAProperties" #endif }, - { /* [105] */ + { /* [109] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4065,7 +4198,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpConfigureFec" #endif }, - { /* [106] */ + { /* [110] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4080,7 +4213,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpConfigMacroPad" #endif }, - { /* [107] */ + { /* [111] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4095,7 +4228,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpAuxchI2cTransferCtrl" #endif }, - { /* [108] */ + { /* [112] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4110,7 +4243,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpEnableVrr" #endif }, - { /* [109] */ + { /* [113] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4125,7 +4258,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetGenericInfoframe" #endif }, - { /* [110] */ + { /* [114] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4140,7 +4273,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetMsaAttributes" #endif }, - { /* [111] */ + { /* [115] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4155,7 +4288,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpInternalLcdOverdrive" #endif }, - { /* [112] */ + { /* [116] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4168,6 +4301,51 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "dispcmnCtrlCmdDpSetMSAPropertiesv2" +#endif + }, + { /* [117] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDfpExecuteInternalLcdOverDrivePolicy_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*flags=*/ 0x200u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x731382u, + /*paramSize=*/ sizeof(NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdDfpExecuteInternalLcdOverDrivePolicy" +#endif + }, + { /* [118] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdPsrGetSrPanelInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x731602u, + /*paramSize=*/ sizeof(NV0073_CTRL_PSR_GET_SR_PANEL_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdPsrGetSrPanelInfo" +#endif + }, + { /* [119] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdStereoDongleSupported_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x731702u, + /*paramSize=*/ sizeof(NV0073_CTRL_STEREO_DONGLE_SUPPORTED_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdStereoDongleSupported" #endif }, @@ -4175,7 +4353,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm const struct NVOC_EXPORT_INFO __nvoc_export_info_DispCommon = { - /*numEntries=*/ 113, + /*numEntries=*/ 120, /*pExportEntries=*/ __nvoc_exported_method_def_DispCommon }; @@ -4223,12 +4401,16 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdSystemCheckSidebandSrSupport__ = &dispcmnCtrlCmdSystemCheckSidebandSrSupport_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__dispcmnCtrlCmdSystemGetHotplugState__ = &dispcmnCtrlCmdSystemGetHotplugState_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) pThis->__dispcmnCtrlCmdSystemGetInternalDisplays__ = &dispcmnCtrlCmdSystemGetInternalDisplays_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) - pThis->__dispcmnCtrlCmdDpEnableVrr__ = &dispcmnCtrlCmdDpEnableVrr_IMPL; + pThis->__dispcmnCtrlCmdSystemGetConnectorTable__ = &dispcmnCtrlCmdSystemGetConnectorTable_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) @@ -4247,6 +4429,10 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdDfpGetLcdGpioPinNum__ = &dispcmnCtrlCmdDfpGetLcdGpioPinNum_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + pThis->__dispcmnCtrlCmdDpEnableVrr__ = &dispcmnCtrlCmdDpEnableVrr_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpGetAudioMuteStream__ = &dispcmnCtrlCmdDpGetAudioMuteStream_IMPL; #endif @@ -4263,6 +4449,14 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdDpSetEcf__ = &dispcmnCtrlCmdDpSetEcf_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + pThis->__dispcmnCtrlCmdStereoDongleSupported__ = &dispcmnCtrlCmdStereoDongleSupported_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + pThis->__dispcmnCtrlCmdDfpRecordChannelRegisters__ = &dispcmnCtrlCmdDfpRecordChannelRegisters_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) pThis->__dispcmnCtrlCmdSpecificGetBacklightBrightness__ = &dispcmnCtrlCmdSpecificGetBacklightBrightness_IMPL; #endif @@ -4271,6 +4465,10 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdSpecificSetBacklightBrightness__ = &dispcmnCtrlCmdSpecificSetBacklightBrightness_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + pThis->__dispcmnCtrlCmdPsrGetSrPanelInfo__ = &dispcmnCtrlCmdPsrGetSrPanelInfo_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDfpSwitchDispMux__ = &dispcmnCtrlCmdDfpSwitchDispMux_IMPL; #endif @@ -4287,14 +4485,14 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdDfpGetDispMuxStatus__ = &dispcmnCtrlCmdDfpGetDispMuxStatus_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) - pThis->__dispcmnCtrlCmdDfpRecordChannelRegisters__ = &dispcmnCtrlCmdDfpRecordChannelRegisters_IMPL; -#endif - #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDfpInternalLcdOverdrive__ = &dispcmnCtrlCmdDfpInternalLcdOverdrive_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + pThis->__dispcmnCtrlCmdDfpExecuteInternalLcdOverDrivePolicy__ = &dispcmnCtrlCmdDfpExecuteInternalLcdOverDrivePolicy_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x12u) pThis->__dispcmnCtrlCmdSystemExecuteAcpiMethod__ = &dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL; #endif @@ -4475,6 +4673,10 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdSpecificIsDirectmodeDisplay__ = &dispcmnCtrlCmdSpecificIsDirectmodeDisplay_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + pThis->__dispcmnCtrlCmdSpecificDefaultAdaptivesyncDisplay__ = &dispcmnCtrlCmdSpecificDefaultAdaptivesyncDisplay_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) pThis->__dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation__ = &dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation_IMPL; #endif @@ -4487,7 +4689,11 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment__ = &dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x206u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + pThis->__dispcmnCtrlCmdSpecificSetHdmiAudioMutestream__ = &dispcmnCtrlCmdSpecificSetHdmiAudioMutestream_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) pThis->__dispcmnCtrlCmdDfpGetInfo__ = &dispcmnCtrlCmdDfpGetInfo_IMPL; #endif @@ -4507,7 +4713,7 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdDfpUpdateDynamicDfpCache__ = &dispcmnCtrlCmdDfpUpdateDynamicDfpCache_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) pThis->__dispcmnCtrlCmdDfpAssignSor__ = &dispcmnCtrlCmdDfpAssignSor_IMPL; #endif @@ -4665,48 +4871,52 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnShareCallback__ = &__nvoc_thunk_RmResource_dispcmnShareCallback; - pThis->__dispcmnControl__ = &__nvoc_thunk_DisplayApi_dispcmnControl; + pThis->__dispcmnCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispcmnCheckMemInterUnmap; + + pThis->__dispcmnMapTo__ = &__nvoc_thunk_RsResource_dispcmnMapTo; pThis->__dispcmnAccessCallback__ = &__nvoc_thunk_RmResource_dispcmnAccessCallback; + pThis->__dispcmnSetNotificationShare__ = &__nvoc_thunk_Notifier_dispcmnSetNotificationShare; + + pThis->__dispcmnGetRefCount__ = &__nvoc_thunk_RsResource_dispcmnGetRefCount; + + pThis->__dispcmnAddAdditionalDependants__ = &__nvoc_thunk_RsResource_dispcmnAddAdditionalDependants; + + pThis->__dispcmnControl_Prologue__ = &__nvoc_thunk_DisplayApi_dispcmnControl_Prologue; + + pThis->__dispcmnUnmapFrom__ = &__nvoc_thunk_RsResource_dispcmnUnmapFrom; + + pThis->__dispcmnControl_Epilogue__ = &__nvoc_thunk_DisplayApi_dispcmnControl_Epilogue; + + pThis->__dispcmnControlLookup__ = &__nvoc_thunk_RsResource_dispcmnControlLookup; + + pThis->__dispcmnControl__ = &__nvoc_thunk_DisplayApi_dispcmnControl; + + pThis->__dispcmnUnmap__ = &__nvoc_thunk_RsResource_dispcmnUnmap; + pThis->__dispcmnGetMemInterMapParams__ = &__nvoc_thunk_RmResource_dispcmnGetMemInterMapParams; pThis->__dispcmnGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_dispcmnGetMemoryMappingDescriptor; - pThis->__dispcmnCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispcmnCheckMemInterUnmap; - - pThis->__dispcmnSetNotificationShare__ = &__nvoc_thunk_Notifier_dispcmnSetNotificationShare; - pThis->__dispcmnControlFilter__ = &__nvoc_thunk_RsResource_dispcmnControlFilter; - pThis->__dispcmnGetRefCount__ = &__nvoc_thunk_RsResource_dispcmnGetRefCount; - pThis->__dispcmnUnregisterEvent__ = &__nvoc_thunk_Notifier_dispcmnUnregisterEvent; - pThis->__dispcmnUnmap__ = &__nvoc_thunk_RsResource_dispcmnUnmap; - - pThis->__dispcmnControl_Prologue__ = &__nvoc_thunk_DisplayApi_dispcmnControl_Prologue; + pThis->__dispcmnControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_dispcmnControlSerialization_Prologue; pThis->__dispcmnCanCopy__ = &__nvoc_thunk_RsResource_dispcmnCanCopy; - pThis->__dispcmnMapTo__ = &__nvoc_thunk_RsResource_dispcmnMapTo; - - pThis->__dispcmnAddAdditionalDependants__ = &__nvoc_thunk_RsResource_dispcmnAddAdditionalDependants; - pThis->__dispcmnPreDestruct__ = &__nvoc_thunk_RsResource_dispcmnPreDestruct; - pThis->__dispcmnUnmapFrom__ = &__nvoc_thunk_RsResource_dispcmnUnmapFrom; - pThis->__dispcmnIsDuplicate__ = &__nvoc_thunk_RsResource_dispcmnIsDuplicate; + pThis->__dispcmnControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_dispcmnControlSerialization_Epilogue; + pThis->__dispcmnGetNotificationListPtr__ = &__nvoc_thunk_Notifier_dispcmnGetNotificationListPtr; - pThis->__dispcmnControl_Epilogue__ = &__nvoc_thunk_DisplayApi_dispcmnControl_Epilogue; - pThis->__dispcmnGetNotificationShare__ = &__nvoc_thunk_Notifier_dispcmnGetNotificationShare; - pThis->__dispcmnControlLookup__ = &__nvoc_thunk_RsResource_dispcmnControlLookup; - pThis->__dispcmnMap__ = &__nvoc_thunk_RsResource_dispcmnMap; pThis->__dispcmnGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_dispcmnGetOrAllocNotifShare; @@ -4736,13 +4946,16 @@ NV_STATUS __nvoc_objCreate_DispCommon(DispCommon **ppThis, Dynamic *pParent, NvU DispCommon *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(DispCommon)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DispCommon), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(DispCommon)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DispCommon); + pThis->__nvoc_base_DisplayApi.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -4762,11 +4975,17 @@ NV_STATUS __nvoc_objCreate_DispCommon(DispCommon **ppThis, Dynamic *pParent, NvU if (status != NV_OK) goto __nvoc_objCreate_DispCommon_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_DispCommon_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(DispCommon)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_disp_objs_nvoc.h b/src/nvidia/generated/g_disp_objs_nvoc.h index c5dafeb04..41689864e 100644 --- a/src/nvidia/generated/g_disp_objs_nvoc.h +++ b/src/nvidia/generated/g_disp_objs_nvoc.h @@ -120,23 +120,25 @@ struct DisplayApi { void (*__dispapiControl_Epilogue__)(struct DisplayApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispapiShareCallback__)(struct DisplayApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__dispapiCheckMemInterUnmap__)(struct DisplayApi *, NvBool); + NV_STATUS (*__dispapiMapTo__)(struct DisplayApi *, RS_RES_MAP_TO_PARAMS *); NvBool (*__dispapiAccessCallback__)(struct DisplayApi *, struct RsClient *, void *, RsAccessRight); + void (*__dispapiSetNotificationShare__)(struct DisplayApi *, struct NotifShare *); + NvU32 (*__dispapiGetRefCount__)(struct DisplayApi *); + void (*__dispapiAddAdditionalDependants__)(struct RsClient *, struct DisplayApi *, RsResourceRef *); + NV_STATUS (*__dispapiUnmapFrom__)(struct DisplayApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__dispapiControlLookup__)(struct DisplayApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__dispapiUnmap__)(struct DisplayApi *, struct CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__dispapiGetMemInterMapParams__)(struct DisplayApi *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__dispapiGetMemoryMappingDescriptor__)(struct DisplayApi *, struct MEMORY_DESCRIPTOR **); - void (*__dispapiSetNotificationShare__)(struct DisplayApi *, struct NotifShare *); NV_STATUS (*__dispapiControlFilter__)(struct DisplayApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvU32 (*__dispapiGetRefCount__)(struct DisplayApi *); NV_STATUS (*__dispapiUnregisterEvent__)(struct DisplayApi *, NvHandle, NvHandle, NvHandle, NvHandle); - NV_STATUS (*__dispapiUnmap__)(struct DisplayApi *, struct CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__dispapiControlSerialization_Prologue__)(struct DisplayApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispapiCanCopy__)(struct DisplayApi *); - NV_STATUS (*__dispapiMapTo__)(struct DisplayApi *, RS_RES_MAP_TO_PARAMS *); - void (*__dispapiAddAdditionalDependants__)(struct RsClient *, struct DisplayApi *, RsResourceRef *); void (*__dispapiPreDestruct__)(struct DisplayApi *); - NV_STATUS (*__dispapiUnmapFrom__)(struct DisplayApi *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__dispapiIsDuplicate__)(struct DisplayApi *, NvHandle, NvBool *); + void (*__dispapiControlSerialization_Epilogue__)(struct DisplayApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__dispapiGetNotificationListPtr__)(struct DisplayApi *); struct NotifShare *(*__dispapiGetNotificationShare__)(struct DisplayApi *); - NV_STATUS (*__dispapiControlLookup__)(struct DisplayApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__dispapiMap__)(struct DisplayApi *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NV_STATUS (*__dispapiGetOrAllocNotifShare__)(struct DisplayApi *, NvHandle, NvHandle, struct NotifShare **); struct OBJGPU *pGpuInRmctrl; @@ -181,23 +183,25 @@ NV_STATUS __nvoc_objCreate_DisplayApi(DisplayApi**, Dynamic*, NvU32, struct CALL #define dispapiControl_Epilogue(pDisplayApi, pCallContext, pRsParams) dispapiControl_Epilogue_DISPATCH(pDisplayApi, pCallContext, pRsParams) #define dispapiShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) dispapiShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define dispapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) dispapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define dispapiMapTo(pResource, pParams) dispapiMapTo_DISPATCH(pResource, pParams) #define dispapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) dispapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +#define dispapiSetNotificationShare(pNotifier, pNotifShare) dispapiSetNotificationShare_DISPATCH(pNotifier, pNotifShare) +#define dispapiGetRefCount(pResource) dispapiGetRefCount_DISPATCH(pResource) +#define dispapiAddAdditionalDependants(pClient, pResource, pReference) dispapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define dispapiUnmapFrom(pResource, pParams) dispapiUnmapFrom_DISPATCH(pResource, pParams) +#define dispapiControlLookup(pResource, pParams, ppEntry) dispapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define dispapiUnmap(pResource, pCallContext, pCpuMapping) dispapiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define dispapiGetMemInterMapParams(pRmResource, pParams) dispapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define dispapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) dispapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define dispapiSetNotificationShare(pNotifier, pNotifShare) dispapiSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define dispapiControlFilter(pResource, pCallContext, pParams) dispapiControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define dispapiGetRefCount(pResource) dispapiGetRefCount_DISPATCH(pResource) #define dispapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) dispapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) -#define dispapiUnmap(pResource, pCallContext, pCpuMapping) dispapiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define dispapiControlSerialization_Prologue(pResource, pCallContext, pParams) dispapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dispapiCanCopy(pResource) dispapiCanCopy_DISPATCH(pResource) -#define dispapiMapTo(pResource, pParams) dispapiMapTo_DISPATCH(pResource, pParams) -#define dispapiAddAdditionalDependants(pClient, pResource, pReference) dispapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define dispapiPreDestruct(pResource) dispapiPreDestruct_DISPATCH(pResource) -#define dispapiUnmapFrom(pResource, pParams) dispapiUnmapFrom_DISPATCH(pResource, pParams) #define dispapiIsDuplicate(pResource, hMemory, pDuplicate) dispapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define dispapiControlSerialization_Epilogue(pResource, pCallContext, pParams) dispapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define dispapiGetNotificationListPtr(pNotifier) dispapiGetNotificationListPtr_DISPATCH(pNotifier) #define dispapiGetNotificationShare(pNotifier) dispapiGetNotificationShare_DISPATCH(pNotifier) -#define dispapiControlLookup(pResource, pParams, ppEntry) dispapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define dispapiMap(pResource, pCallContext, pParams, pCpuMapping) dispapiMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) #define dispapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) dispapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) NV_STATUS dispapiSetUnicastAndSynchronize_KERNEL(struct DisplayApi *pDisplayApi, struct OBJGPUGRP *pGpuGroup, struct OBJGPU **ppGpu, NvU32 subDeviceInstance); @@ -240,10 +244,38 @@ static inline NV_STATUS dispapiCheckMemInterUnmap_DISPATCH(struct DisplayApi *pR return pRmResource->__dispapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } +static inline NV_STATUS dispapiMapTo_DISPATCH(struct DisplayApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__dispapiMapTo__(pResource, pParams); +} + static inline NvBool dispapiAccessCallback_DISPATCH(struct DisplayApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return pResource->__dispapiAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); } +static inline void dispapiSetNotificationShare_DISPATCH(struct DisplayApi *pNotifier, struct NotifShare *pNotifShare) { + pNotifier->__dispapiSetNotificationShare__(pNotifier, pNotifShare); +} + +static inline NvU32 dispapiGetRefCount_DISPATCH(struct DisplayApi *pResource) { + return pResource->__dispapiGetRefCount__(pResource); +} + +static inline void dispapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct DisplayApi *pResource, RsResourceRef *pReference) { + pResource->__dispapiAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS dispapiUnmapFrom_DISPATCH(struct DisplayApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__dispapiUnmapFrom__(pResource, pParams); +} + +static inline NV_STATUS dispapiControlLookup_DISPATCH(struct DisplayApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__dispapiControlLookup__(pResource, pParams, ppEntry); +} + +static inline NV_STATUS dispapiUnmap_DISPATCH(struct DisplayApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__dispapiUnmap__(pResource, pCallContext, pCpuMapping); +} + static inline NV_STATUS dispapiGetMemInterMapParams_DISPATCH(struct DisplayApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { return pRmResource->__dispapiGetMemInterMapParams__(pRmResource, pParams); } @@ -252,50 +284,34 @@ static inline NV_STATUS dispapiGetMemoryMappingDescriptor_DISPATCH(struct Displa return pRmResource->__dispapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline void dispapiSetNotificationShare_DISPATCH(struct DisplayApi *pNotifier, struct NotifShare *pNotifShare) { - pNotifier->__dispapiSetNotificationShare__(pNotifier, pNotifShare); -} - static inline NV_STATUS dispapiControlFilter_DISPATCH(struct DisplayApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__dispapiControlFilter__(pResource, pCallContext, pParams); } -static inline NvU32 dispapiGetRefCount_DISPATCH(struct DisplayApi *pResource) { - return pResource->__dispapiGetRefCount__(pResource); -} - static inline NV_STATUS dispapiUnregisterEvent_DISPATCH(struct DisplayApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { return pNotifier->__dispapiUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static inline NV_STATUS dispapiUnmap_DISPATCH(struct DisplayApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pResource->__dispapiUnmap__(pResource, pCallContext, pCpuMapping); +static inline NV_STATUS dispapiControlSerialization_Prologue_DISPATCH(struct DisplayApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dispapiControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool dispapiCanCopy_DISPATCH(struct DisplayApi *pResource) { return pResource->__dispapiCanCopy__(pResource); } -static inline NV_STATUS dispapiMapTo_DISPATCH(struct DisplayApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__dispapiMapTo__(pResource, pParams); -} - -static inline void dispapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct DisplayApi *pResource, RsResourceRef *pReference) { - pResource->__dispapiAddAdditionalDependants__(pClient, pResource, pReference); -} - static inline void dispapiPreDestruct_DISPATCH(struct DisplayApi *pResource) { pResource->__dispapiPreDestruct__(pResource); } -static inline NV_STATUS dispapiUnmapFrom_DISPATCH(struct DisplayApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__dispapiUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS dispapiIsDuplicate_DISPATCH(struct DisplayApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__dispapiIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void dispapiControlSerialization_Epilogue_DISPATCH(struct DisplayApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__dispapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *dispapiGetNotificationListPtr_DISPATCH(struct DisplayApi *pNotifier) { return pNotifier->__dispapiGetNotificationListPtr__(pNotifier); } @@ -304,10 +320,6 @@ static inline struct NotifShare *dispapiGetNotificationShare_DISPATCH(struct Dis return pNotifier->__dispapiGetNotificationShare__(pNotifier); } -static inline NV_STATUS dispapiControlLookup_DISPATCH(struct DisplayApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__dispapiControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS dispapiMap_DISPATCH(struct DisplayApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return pResource->__dispapiMap__(pResource, pCallContext, pParams, pCpuMapping); } @@ -376,7 +388,6 @@ struct DispObject { NV_STATUS (*__dispobjCtrlCmdSetRgUnderflowProp__)(struct DispObject *, NV5070_CTRL_CMD_SET_RG_UNDERFLOW_PROP_PARAMS *); NV_STATUS (*__dispobjCtrlCmdGetRgFliplockProp__)(struct DispObject *, NV5070_CTRL_CMD_GET_RG_FLIPLOCK_PROP_PARAMS *); NV_STATUS (*__dispobjCtrlCmdSetRgFliplockProp__)(struct DispObject *, NV5070_CTRL_CMD_SET_RG_FLIPLOCK_PROP_PARAMS *); - NV_STATUS (*__dispobjCtrlCmdGetRgConnectedLockpin__)(struct DispObject *, NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS *); NV_STATUS (*__dispobjCtrlCmdGetRgConnectedLockpinStateless__)(struct DispObject *, NV5070_CTRL_GET_RG_CONNECTED_LOCKPIN_STATELESS_PARAMS *); NV_STATUS (*__dispobjCtrlCmdGetRgScanLine__)(struct DispObject *, NV5070_CTRL_CMD_GET_RG_SCAN_LINE_PARAMS *); NV_STATUS (*__dispobjCtrlCmdGetSorSeqCtl__)(struct DispObject *, NV5070_CTRL_CMD_GET_SOR_SEQ_CTL_PARAMS *); @@ -390,27 +401,29 @@ struct DispObject { NV_STATUS (*__dispobjCtrlCmdSystemGetCapsV2__)(struct DispObject *, NV5070_CTRL_SYSTEM_GET_CAPS_V2_PARAMS *); NV_STATUS (*__dispobjCtrlCmdEventSetTrigger__)(struct DispObject *); NvBool (*__dispobjShareCallback__)(struct DispObject *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__dispobjControl__)(struct DispObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispobjCheckMemInterUnmap__)(struct DispObject *, NvBool); + NV_STATUS (*__dispobjMapTo__)(struct DispObject *, RS_RES_MAP_TO_PARAMS *); NvBool (*__dispobjAccessCallback__)(struct DispObject *, struct RsClient *, void *, RsAccessRight); + void (*__dispobjSetNotificationShare__)(struct DispObject *, struct NotifShare *); + NvU32 (*__dispobjGetRefCount__)(struct DispObject *); + void (*__dispobjAddAdditionalDependants__)(struct RsClient *, struct DispObject *, RsResourceRef *); + NV_STATUS (*__dispobjControl_Prologue__)(struct DispObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispobjUnmapFrom__)(struct DispObject *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__dispobjControl_Epilogue__)(struct DispObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispobjControlLookup__)(struct DispObject *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__dispobjControl__)(struct DispObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispobjUnmap__)(struct DispObject *, struct CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__dispobjGetMemInterMapParams__)(struct DispObject *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__dispobjGetMemoryMappingDescriptor__)(struct DispObject *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__dispobjCheckMemInterUnmap__)(struct DispObject *, NvBool); - void (*__dispobjSetNotificationShare__)(struct DispObject *, struct NotifShare *); NV_STATUS (*__dispobjControlFilter__)(struct DispObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvU32 (*__dispobjGetRefCount__)(struct DispObject *); NV_STATUS (*__dispobjUnregisterEvent__)(struct DispObject *, NvHandle, NvHandle, NvHandle, NvHandle); - NV_STATUS (*__dispobjUnmap__)(struct DispObject *, struct CALL_CONTEXT *, RsCpuMapping *); - NV_STATUS (*__dispobjControl_Prologue__)(struct DispObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispobjControlSerialization_Prologue__)(struct DispObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispobjCanCopy__)(struct DispObject *); - NV_STATUS (*__dispobjMapTo__)(struct DispObject *, RS_RES_MAP_TO_PARAMS *); - void (*__dispobjAddAdditionalDependants__)(struct RsClient *, struct DispObject *, RsResourceRef *); void (*__dispobjPreDestruct__)(struct DispObject *); - NV_STATUS (*__dispobjUnmapFrom__)(struct DispObject *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__dispobjIsDuplicate__)(struct DispObject *, NvHandle, NvBool *); + void (*__dispobjControlSerialization_Epilogue__)(struct DispObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__dispobjGetNotificationListPtr__)(struct DispObject *); - void (*__dispobjControl_Epilogue__)(struct DispObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); struct NotifShare *(*__dispobjGetNotificationShare__)(struct DispObject *); - NV_STATUS (*__dispobjControlLookup__)(struct DispObject *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__dispobjMap__)(struct DispObject *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NV_STATUS (*__dispobjGetOrAllocNotifShare__)(struct DispObject *, NvHandle, NvHandle, struct NotifShare **); NvU32 rmFreeFlags; @@ -461,7 +474,6 @@ NV_STATUS __nvoc_objCreate_DispObject(DispObject**, Dynamic*, NvU32, struct CALL #define dispobjCtrlCmdSetRgUnderflowProp(pDispObject, pParams) dispobjCtrlCmdSetRgUnderflowProp_DISPATCH(pDispObject, pParams) #define dispobjCtrlCmdGetRgFliplockProp(pDispObject, pParams) dispobjCtrlCmdGetRgFliplockProp_DISPATCH(pDispObject, pParams) #define dispobjCtrlCmdSetRgFliplockProp(pDispObject, pParams) dispobjCtrlCmdSetRgFliplockProp_DISPATCH(pDispObject, pParams) -#define dispobjCtrlCmdGetRgConnectedLockpin(pDispObject, pParams) dispobjCtrlCmdGetRgConnectedLockpin_DISPATCH(pDispObject, pParams) #define dispobjCtrlCmdGetRgConnectedLockpinStateless(pDispObject, pParams) dispobjCtrlCmdGetRgConnectedLockpinStateless_DISPATCH(pDispObject, pParams) #define dispobjCtrlCmdGetRgScanLine(pDispObject, pParams) dispobjCtrlCmdGetRgScanLine_DISPATCH(pDispObject, pParams) #define dispobjCtrlCmdGetSorSeqCtl(pDispObject, pParams) dispobjCtrlCmdGetSorSeqCtl_DISPATCH(pDispObject, pParams) @@ -475,27 +487,29 @@ NV_STATUS __nvoc_objCreate_DispObject(DispObject**, Dynamic*, NvU32, struct CALL #define dispobjCtrlCmdSystemGetCapsV2(pDispObject, pCapsParams) dispobjCtrlCmdSystemGetCapsV2_DISPATCH(pDispObject, pCapsParams) #define dispobjCtrlCmdEventSetTrigger(pDispObject) dispobjCtrlCmdEventSetTrigger_DISPATCH(pDispObject) #define dispobjShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) dispobjShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) -#define dispobjControl(pDisplayApi, pCallContext, pParams) dispobjControl_DISPATCH(pDisplayApi, pCallContext, pParams) +#define dispobjCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) dispobjCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define dispobjMapTo(pResource, pParams) dispobjMapTo_DISPATCH(pResource, pParams) #define dispobjAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) dispobjAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +#define dispobjSetNotificationShare(pNotifier, pNotifShare) dispobjSetNotificationShare_DISPATCH(pNotifier, pNotifShare) +#define dispobjGetRefCount(pResource) dispobjGetRefCount_DISPATCH(pResource) +#define dispobjAddAdditionalDependants(pClient, pResource, pReference) dispobjAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define dispobjControl_Prologue(pDisplayApi, pCallContext, pRsParams) dispobjControl_Prologue_DISPATCH(pDisplayApi, pCallContext, pRsParams) +#define dispobjUnmapFrom(pResource, pParams) dispobjUnmapFrom_DISPATCH(pResource, pParams) +#define dispobjControl_Epilogue(pDisplayApi, pCallContext, pRsParams) dispobjControl_Epilogue_DISPATCH(pDisplayApi, pCallContext, pRsParams) +#define dispobjControlLookup(pResource, pParams, ppEntry) dispobjControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define dispobjControl(pDisplayApi, pCallContext, pParams) dispobjControl_DISPATCH(pDisplayApi, pCallContext, pParams) +#define dispobjUnmap(pResource, pCallContext, pCpuMapping) dispobjUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define dispobjGetMemInterMapParams(pRmResource, pParams) dispobjGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define dispobjGetMemoryMappingDescriptor(pRmResource, ppMemDesc) dispobjGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define dispobjCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) dispobjCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define dispobjSetNotificationShare(pNotifier, pNotifShare) dispobjSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define dispobjControlFilter(pResource, pCallContext, pParams) dispobjControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define dispobjGetRefCount(pResource) dispobjGetRefCount_DISPATCH(pResource) #define dispobjUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) dispobjUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) -#define dispobjUnmap(pResource, pCallContext, pCpuMapping) dispobjUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) -#define dispobjControl_Prologue(pDisplayApi, pCallContext, pRsParams) dispobjControl_Prologue_DISPATCH(pDisplayApi, pCallContext, pRsParams) +#define dispobjControlSerialization_Prologue(pResource, pCallContext, pParams) dispobjControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dispobjCanCopy(pResource) dispobjCanCopy_DISPATCH(pResource) -#define dispobjMapTo(pResource, pParams) dispobjMapTo_DISPATCH(pResource, pParams) -#define dispobjAddAdditionalDependants(pClient, pResource, pReference) dispobjAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define dispobjPreDestruct(pResource) dispobjPreDestruct_DISPATCH(pResource) -#define dispobjUnmapFrom(pResource, pParams) dispobjUnmapFrom_DISPATCH(pResource, pParams) #define dispobjIsDuplicate(pResource, hMemory, pDuplicate) dispobjIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define dispobjControlSerialization_Epilogue(pResource, pCallContext, pParams) dispobjControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define dispobjGetNotificationListPtr(pNotifier) dispobjGetNotificationListPtr_DISPATCH(pNotifier) -#define dispobjControl_Epilogue(pDisplayApi, pCallContext, pRsParams) dispobjControl_Epilogue_DISPATCH(pDisplayApi, pCallContext, pRsParams) #define dispobjGetNotificationShare(pNotifier) dispobjGetNotificationShare_DISPATCH(pNotifier) -#define dispobjControlLookup(pResource, pParams, ppEntry) dispobjControlLookup_DISPATCH(pResource, pParams, ppEntry) #define dispobjMap(pResource, pCallContext, pParams, pCpuMapping) dispobjMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) #define dispobjGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) dispobjGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) NV_STATUS dispobjConstructHal_IMPL(struct DispObject *pDispObject, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); @@ -614,12 +628,6 @@ static inline NV_STATUS dispobjCtrlCmdSetRgFliplockProp_DISPATCH(struct DispObje return pDispObject->__dispobjCtrlCmdSetRgFliplockProp__(pDispObject, pParams); } -NV_STATUS dispobjCtrlCmdGetRgConnectedLockpin_IMPL(struct DispObject *pDispObject, NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS *pParams); - -static inline NV_STATUS dispobjCtrlCmdGetRgConnectedLockpin_DISPATCH(struct DispObject *pDispObject, NV5070_CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_PARAMS *pParams) { - return pDispObject->__dispobjCtrlCmdGetRgConnectedLockpin__(pDispObject, pParams); -} - NV_STATUS dispobjCtrlCmdGetRgConnectedLockpinStateless_IMPL(struct DispObject *pDispObject, NV5070_CTRL_GET_RG_CONNECTED_LOCKPIN_STATELESS_PARAMS *pParams); static inline NV_STATUS dispobjCtrlCmdGetRgConnectedLockpinStateless_DISPATCH(struct DispObject *pDispObject, NV5070_CTRL_GET_RG_CONNECTED_LOCKPIN_STATELESS_PARAMS *pParams) { @@ -696,14 +704,54 @@ static inline NvBool dispobjShareCallback_DISPATCH(struct DispObject *pResource, return pResource->__dispobjShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS dispobjControl_DISPATCH(struct DispObject *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pDisplayApi->__dispobjControl__(pDisplayApi, pCallContext, pParams); +static inline NV_STATUS dispobjCheckMemInterUnmap_DISPATCH(struct DispObject *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__dispobjCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS dispobjMapTo_DISPATCH(struct DispObject *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__dispobjMapTo__(pResource, pParams); } static inline NvBool dispobjAccessCallback_DISPATCH(struct DispObject *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return pResource->__dispobjAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); } +static inline void dispobjSetNotificationShare_DISPATCH(struct DispObject *pNotifier, struct NotifShare *pNotifShare) { + pNotifier->__dispobjSetNotificationShare__(pNotifier, pNotifShare); +} + +static inline NvU32 dispobjGetRefCount_DISPATCH(struct DispObject *pResource) { + return pResource->__dispobjGetRefCount__(pResource); +} + +static inline void dispobjAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct DispObject *pResource, RsResourceRef *pReference) { + pResource->__dispobjAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS dispobjControl_Prologue_DISPATCH(struct DispObject *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + return pDisplayApi->__dispobjControl_Prologue__(pDisplayApi, pCallContext, pRsParams); +} + +static inline NV_STATUS dispobjUnmapFrom_DISPATCH(struct DispObject *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__dispobjUnmapFrom__(pResource, pParams); +} + +static inline void dispobjControl_Epilogue_DISPATCH(struct DispObject *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + pDisplayApi->__dispobjControl_Epilogue__(pDisplayApi, pCallContext, pRsParams); +} + +static inline NV_STATUS dispobjControlLookup_DISPATCH(struct DispObject *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__dispobjControlLookup__(pResource, pParams, ppEntry); +} + +static inline NV_STATUS dispobjControl_DISPATCH(struct DispObject *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pDisplayApi->__dispobjControl__(pDisplayApi, pCallContext, pParams); +} + +static inline NV_STATUS dispobjUnmap_DISPATCH(struct DispObject *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__dispobjUnmap__(pResource, pCallContext, pCpuMapping); +} + static inline NV_STATUS dispobjGetMemInterMapParams_DISPATCH(struct DispObject *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { return pRmResource->__dispobjGetMemInterMapParams__(pRmResource, pParams); } @@ -712,74 +760,42 @@ static inline NV_STATUS dispobjGetMemoryMappingDescriptor_DISPATCH(struct DispOb return pRmResource->__dispobjGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS dispobjCheckMemInterUnmap_DISPATCH(struct DispObject *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__dispobjCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline void dispobjSetNotificationShare_DISPATCH(struct DispObject *pNotifier, struct NotifShare *pNotifShare) { - pNotifier->__dispobjSetNotificationShare__(pNotifier, pNotifShare); -} - static inline NV_STATUS dispobjControlFilter_DISPATCH(struct DispObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__dispobjControlFilter__(pResource, pCallContext, pParams); } -static inline NvU32 dispobjGetRefCount_DISPATCH(struct DispObject *pResource) { - return pResource->__dispobjGetRefCount__(pResource); -} - static inline NV_STATUS dispobjUnregisterEvent_DISPATCH(struct DispObject *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { return pNotifier->__dispobjUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static inline NV_STATUS dispobjUnmap_DISPATCH(struct DispObject *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pResource->__dispobjUnmap__(pResource, pCallContext, pCpuMapping); -} - -static inline NV_STATUS dispobjControl_Prologue_DISPATCH(struct DispObject *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - return pDisplayApi->__dispobjControl_Prologue__(pDisplayApi, pCallContext, pRsParams); +static inline NV_STATUS dispobjControlSerialization_Prologue_DISPATCH(struct DispObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dispobjControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool dispobjCanCopy_DISPATCH(struct DispObject *pResource) { return pResource->__dispobjCanCopy__(pResource); } -static inline NV_STATUS dispobjMapTo_DISPATCH(struct DispObject *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__dispobjMapTo__(pResource, pParams); -} - -static inline void dispobjAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct DispObject *pResource, RsResourceRef *pReference) { - pResource->__dispobjAddAdditionalDependants__(pClient, pResource, pReference); -} - static inline void dispobjPreDestruct_DISPATCH(struct DispObject *pResource) { pResource->__dispobjPreDestruct__(pResource); } -static inline NV_STATUS dispobjUnmapFrom_DISPATCH(struct DispObject *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__dispobjUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS dispobjIsDuplicate_DISPATCH(struct DispObject *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__dispobjIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void dispobjControlSerialization_Epilogue_DISPATCH(struct DispObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__dispobjControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *dispobjGetNotificationListPtr_DISPATCH(struct DispObject *pNotifier) { return pNotifier->__dispobjGetNotificationListPtr__(pNotifier); } -static inline void dispobjControl_Epilogue_DISPATCH(struct DispObject *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - pDisplayApi->__dispobjControl_Epilogue__(pDisplayApi, pCallContext, pRsParams); -} - static inline struct NotifShare *dispobjGetNotificationShare_DISPATCH(struct DispObject *pNotifier) { return pNotifier->__dispobjGetNotificationShare__(pNotifier); } -static inline NV_STATUS dispobjControlLookup_DISPATCH(struct DispObject *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__dispobjControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS dispobjMap_DISPATCH(struct DispObject *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return pResource->__dispobjMap__(pResource, pCallContext, pParams, pCpuMapping); } @@ -853,27 +869,29 @@ struct NvDispApi { NV_STATUS (*__nvdispapiCtrlCmdGetLockpinsCaps__)(struct NvDispApi *, NVC370_CTRL_GET_LOCKPINS_CAPS_PARAMS *); NV_STATUS (*__nvdispapiCtrlCmdSetForceModeswitchFlagsOverrides__)(struct NvDispApi *, NVC370_CTRL_CMD_SET_FORCE_MODESWITCH_FLAGS_OVERRIDES_PARAMS *); NvBool (*__nvdispapiShareCallback__)(struct NvDispApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__nvdispapiControl__)(struct NvDispApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__nvdispapiCheckMemInterUnmap__)(struct NvDispApi *, NvBool); + NV_STATUS (*__nvdispapiMapTo__)(struct NvDispApi *, RS_RES_MAP_TO_PARAMS *); NvBool (*__nvdispapiAccessCallback__)(struct NvDispApi *, struct RsClient *, void *, RsAccessRight); + void (*__nvdispapiSetNotificationShare__)(struct NvDispApi *, struct NotifShare *); + NvU32 (*__nvdispapiGetRefCount__)(struct NvDispApi *); + void (*__nvdispapiAddAdditionalDependants__)(struct RsClient *, struct NvDispApi *, RsResourceRef *); + NV_STATUS (*__nvdispapiControl_Prologue__)(struct NvDispApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__nvdispapiUnmapFrom__)(struct NvDispApi *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__nvdispapiControl_Epilogue__)(struct NvDispApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__nvdispapiControlLookup__)(struct NvDispApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__nvdispapiControl__)(struct NvDispApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__nvdispapiUnmap__)(struct NvDispApi *, struct CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__nvdispapiGetMemInterMapParams__)(struct NvDispApi *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__nvdispapiGetMemoryMappingDescriptor__)(struct NvDispApi *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__nvdispapiCheckMemInterUnmap__)(struct NvDispApi *, NvBool); - void (*__nvdispapiSetNotificationShare__)(struct NvDispApi *, struct NotifShare *); NV_STATUS (*__nvdispapiControlFilter__)(struct NvDispApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvU32 (*__nvdispapiGetRefCount__)(struct NvDispApi *); NV_STATUS (*__nvdispapiUnregisterEvent__)(struct NvDispApi *, NvHandle, NvHandle, NvHandle, NvHandle); - NV_STATUS (*__nvdispapiUnmap__)(struct NvDispApi *, struct CALL_CONTEXT *, RsCpuMapping *); - NV_STATUS (*__nvdispapiControl_Prologue__)(struct NvDispApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__nvdispapiControlSerialization_Prologue__)(struct NvDispApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__nvdispapiCanCopy__)(struct NvDispApi *); - NV_STATUS (*__nvdispapiMapTo__)(struct NvDispApi *, RS_RES_MAP_TO_PARAMS *); - void (*__nvdispapiAddAdditionalDependants__)(struct RsClient *, struct NvDispApi *, RsResourceRef *); void (*__nvdispapiPreDestruct__)(struct NvDispApi *); - NV_STATUS (*__nvdispapiUnmapFrom__)(struct NvDispApi *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__nvdispapiIsDuplicate__)(struct NvDispApi *, NvHandle, NvBool *); + void (*__nvdispapiControlSerialization_Epilogue__)(struct NvDispApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__nvdispapiGetNotificationListPtr__)(struct NvDispApi *); - void (*__nvdispapiControl_Epilogue__)(struct NvDispApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); struct NotifShare *(*__nvdispapiGetNotificationShare__)(struct NvDispApi *); - NV_STATUS (*__nvdispapiControlLookup__)(struct NvDispApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__nvdispapiMap__)(struct NvDispApi *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NV_STATUS (*__nvdispapiGetOrAllocNotifShare__)(struct NvDispApi *, NvHandle, NvHandle, struct NotifShare **); }; @@ -914,27 +932,29 @@ NV_STATUS __nvoc_objCreate_NvDispApi(NvDispApi**, Dynamic*, NvU32, struct CALL_C #define nvdispapiCtrlCmdGetLockpinsCaps(pNvDispApi, pParams) nvdispapiCtrlCmdGetLockpinsCaps_DISPATCH(pNvDispApi, pParams) #define nvdispapiCtrlCmdSetForceModeswitchFlagsOverrides(pNvDispApi, pParams) nvdispapiCtrlCmdSetForceModeswitchFlagsOverrides_DISPATCH(pNvDispApi, pParams) #define nvdispapiShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) nvdispapiShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) -#define nvdispapiControl(pDisplayApi, pCallContext, pParams) nvdispapiControl_DISPATCH(pDisplayApi, pCallContext, pParams) +#define nvdispapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) nvdispapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define nvdispapiMapTo(pResource, pParams) nvdispapiMapTo_DISPATCH(pResource, pParams) #define nvdispapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) nvdispapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +#define nvdispapiSetNotificationShare(pNotifier, pNotifShare) nvdispapiSetNotificationShare_DISPATCH(pNotifier, pNotifShare) +#define nvdispapiGetRefCount(pResource) nvdispapiGetRefCount_DISPATCH(pResource) +#define nvdispapiAddAdditionalDependants(pClient, pResource, pReference) nvdispapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define nvdispapiControl_Prologue(pDisplayApi, pCallContext, pRsParams) nvdispapiControl_Prologue_DISPATCH(pDisplayApi, pCallContext, pRsParams) +#define nvdispapiUnmapFrom(pResource, pParams) nvdispapiUnmapFrom_DISPATCH(pResource, pParams) +#define nvdispapiControl_Epilogue(pDisplayApi, pCallContext, pRsParams) nvdispapiControl_Epilogue_DISPATCH(pDisplayApi, pCallContext, pRsParams) +#define nvdispapiControlLookup(pResource, pParams, ppEntry) nvdispapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define nvdispapiControl(pDisplayApi, pCallContext, pParams) nvdispapiControl_DISPATCH(pDisplayApi, pCallContext, pParams) +#define nvdispapiUnmap(pResource, pCallContext, pCpuMapping) nvdispapiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define nvdispapiGetMemInterMapParams(pRmResource, pParams) nvdispapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define nvdispapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) nvdispapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define nvdispapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) nvdispapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define nvdispapiSetNotificationShare(pNotifier, pNotifShare) nvdispapiSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define nvdispapiControlFilter(pResource, pCallContext, pParams) nvdispapiControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define nvdispapiGetRefCount(pResource) nvdispapiGetRefCount_DISPATCH(pResource) #define nvdispapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) nvdispapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) -#define nvdispapiUnmap(pResource, pCallContext, pCpuMapping) nvdispapiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) -#define nvdispapiControl_Prologue(pDisplayApi, pCallContext, pRsParams) nvdispapiControl_Prologue_DISPATCH(pDisplayApi, pCallContext, pRsParams) +#define nvdispapiControlSerialization_Prologue(pResource, pCallContext, pParams) nvdispapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define nvdispapiCanCopy(pResource) nvdispapiCanCopy_DISPATCH(pResource) -#define nvdispapiMapTo(pResource, pParams) nvdispapiMapTo_DISPATCH(pResource, pParams) -#define nvdispapiAddAdditionalDependants(pClient, pResource, pReference) nvdispapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define nvdispapiPreDestruct(pResource) nvdispapiPreDestruct_DISPATCH(pResource) -#define nvdispapiUnmapFrom(pResource, pParams) nvdispapiUnmapFrom_DISPATCH(pResource, pParams) #define nvdispapiIsDuplicate(pResource, hMemory, pDuplicate) nvdispapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define nvdispapiControlSerialization_Epilogue(pResource, pCallContext, pParams) nvdispapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define nvdispapiGetNotificationListPtr(pNotifier) nvdispapiGetNotificationListPtr_DISPATCH(pNotifier) -#define nvdispapiControl_Epilogue(pDisplayApi, pCallContext, pRsParams) nvdispapiControl_Epilogue_DISPATCH(pDisplayApi, pCallContext, pRsParams) #define nvdispapiGetNotificationShare(pNotifier) nvdispapiGetNotificationShare_DISPATCH(pNotifier) -#define nvdispapiControlLookup(pResource, pParams, ppEntry) nvdispapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define nvdispapiMap(pResource, pCallContext, pParams, pCpuMapping) nvdispapiMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) #define nvdispapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) nvdispapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) NV_STATUS nvdispapiCtrlCmdIdleChannel_IMPL(struct NvDispApi *pNvDispApi, NVC370_CTRL_IDLE_CHANNEL_PARAMS *pParams); @@ -983,14 +1003,54 @@ static inline NvBool nvdispapiShareCallback_DISPATCH(struct NvDispApi *pResource return pResource->__nvdispapiShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS nvdispapiControl_DISPATCH(struct NvDispApi *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pDisplayApi->__nvdispapiControl__(pDisplayApi, pCallContext, pParams); +static inline NV_STATUS nvdispapiCheckMemInterUnmap_DISPATCH(struct NvDispApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__nvdispapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS nvdispapiMapTo_DISPATCH(struct NvDispApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__nvdispapiMapTo__(pResource, pParams); } static inline NvBool nvdispapiAccessCallback_DISPATCH(struct NvDispApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return pResource->__nvdispapiAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); } +static inline void nvdispapiSetNotificationShare_DISPATCH(struct NvDispApi *pNotifier, struct NotifShare *pNotifShare) { + pNotifier->__nvdispapiSetNotificationShare__(pNotifier, pNotifShare); +} + +static inline NvU32 nvdispapiGetRefCount_DISPATCH(struct NvDispApi *pResource) { + return pResource->__nvdispapiGetRefCount__(pResource); +} + +static inline void nvdispapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct NvDispApi *pResource, RsResourceRef *pReference) { + pResource->__nvdispapiAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS nvdispapiControl_Prologue_DISPATCH(struct NvDispApi *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + return pDisplayApi->__nvdispapiControl_Prologue__(pDisplayApi, pCallContext, pRsParams); +} + +static inline NV_STATUS nvdispapiUnmapFrom_DISPATCH(struct NvDispApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__nvdispapiUnmapFrom__(pResource, pParams); +} + +static inline void nvdispapiControl_Epilogue_DISPATCH(struct NvDispApi *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + pDisplayApi->__nvdispapiControl_Epilogue__(pDisplayApi, pCallContext, pRsParams); +} + +static inline NV_STATUS nvdispapiControlLookup_DISPATCH(struct NvDispApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__nvdispapiControlLookup__(pResource, pParams, ppEntry); +} + +static inline NV_STATUS nvdispapiControl_DISPATCH(struct NvDispApi *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pDisplayApi->__nvdispapiControl__(pDisplayApi, pCallContext, pParams); +} + +static inline NV_STATUS nvdispapiUnmap_DISPATCH(struct NvDispApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__nvdispapiUnmap__(pResource, pCallContext, pCpuMapping); +} + static inline NV_STATUS nvdispapiGetMemInterMapParams_DISPATCH(struct NvDispApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { return pRmResource->__nvdispapiGetMemInterMapParams__(pRmResource, pParams); } @@ -999,74 +1059,42 @@ static inline NV_STATUS nvdispapiGetMemoryMappingDescriptor_DISPATCH(struct NvDi return pRmResource->__nvdispapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS nvdispapiCheckMemInterUnmap_DISPATCH(struct NvDispApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__nvdispapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline void nvdispapiSetNotificationShare_DISPATCH(struct NvDispApi *pNotifier, struct NotifShare *pNotifShare) { - pNotifier->__nvdispapiSetNotificationShare__(pNotifier, pNotifShare); -} - static inline NV_STATUS nvdispapiControlFilter_DISPATCH(struct NvDispApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__nvdispapiControlFilter__(pResource, pCallContext, pParams); } -static inline NvU32 nvdispapiGetRefCount_DISPATCH(struct NvDispApi *pResource) { - return pResource->__nvdispapiGetRefCount__(pResource); -} - static inline NV_STATUS nvdispapiUnregisterEvent_DISPATCH(struct NvDispApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { return pNotifier->__nvdispapiUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static inline NV_STATUS nvdispapiUnmap_DISPATCH(struct NvDispApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pResource->__nvdispapiUnmap__(pResource, pCallContext, pCpuMapping); -} - -static inline NV_STATUS nvdispapiControl_Prologue_DISPATCH(struct NvDispApi *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - return pDisplayApi->__nvdispapiControl_Prologue__(pDisplayApi, pCallContext, pRsParams); +static inline NV_STATUS nvdispapiControlSerialization_Prologue_DISPATCH(struct NvDispApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__nvdispapiControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool nvdispapiCanCopy_DISPATCH(struct NvDispApi *pResource) { return pResource->__nvdispapiCanCopy__(pResource); } -static inline NV_STATUS nvdispapiMapTo_DISPATCH(struct NvDispApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__nvdispapiMapTo__(pResource, pParams); -} - -static inline void nvdispapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct NvDispApi *pResource, RsResourceRef *pReference) { - pResource->__nvdispapiAddAdditionalDependants__(pClient, pResource, pReference); -} - static inline void nvdispapiPreDestruct_DISPATCH(struct NvDispApi *pResource) { pResource->__nvdispapiPreDestruct__(pResource); } -static inline NV_STATUS nvdispapiUnmapFrom_DISPATCH(struct NvDispApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__nvdispapiUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS nvdispapiIsDuplicate_DISPATCH(struct NvDispApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__nvdispapiIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void nvdispapiControlSerialization_Epilogue_DISPATCH(struct NvDispApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__nvdispapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *nvdispapiGetNotificationListPtr_DISPATCH(struct NvDispApi *pNotifier) { return pNotifier->__nvdispapiGetNotificationListPtr__(pNotifier); } -static inline void nvdispapiControl_Epilogue_DISPATCH(struct NvDispApi *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - pDisplayApi->__nvdispapiControl_Epilogue__(pDisplayApi, pCallContext, pRsParams); -} - static inline struct NotifShare *nvdispapiGetNotificationShare_DISPATCH(struct NvDispApi *pNotifier) { return pNotifier->__nvdispapiGetNotificationShare__(pNotifier); } -static inline NV_STATUS nvdispapiControlLookup_DISPATCH(struct NvDispApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__nvdispapiControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS nvdispapiMap_DISPATCH(struct NvDispApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return pResource->__nvdispapiMap__(pResource, pCallContext, pParams, pCpuMapping); } @@ -1112,27 +1140,29 @@ struct DispSwObj { NV_STATUS (*__dispswobjCtrlCmdVideoAdaptiveRefreshRate__)(struct DispSwObj *, NVC372_CTRL_CMD_VIDEO_ADAPTIVE_REFRESH_RATE_PARAMS *); NV_STATUS (*__dispswobjCtrlCmdGetActiveViewportPointIn__)(struct DispSwObj *, NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN_PARAMS *); NvBool (*__dispswobjShareCallback__)(struct DispSwObj *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__dispswobjControl__)(struct DispSwObj *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispswobjCheckMemInterUnmap__)(struct DispSwObj *, NvBool); + NV_STATUS (*__dispswobjMapTo__)(struct DispSwObj *, RS_RES_MAP_TO_PARAMS *); NvBool (*__dispswobjAccessCallback__)(struct DispSwObj *, struct RsClient *, void *, RsAccessRight); + void (*__dispswobjSetNotificationShare__)(struct DispSwObj *, struct NotifShare *); + NvU32 (*__dispswobjGetRefCount__)(struct DispSwObj *); + void (*__dispswobjAddAdditionalDependants__)(struct RsClient *, struct DispSwObj *, RsResourceRef *); + NV_STATUS (*__dispswobjControl_Prologue__)(struct DispSwObj *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispswobjUnmapFrom__)(struct DispSwObj *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__dispswobjControl_Epilogue__)(struct DispSwObj *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispswobjControlLookup__)(struct DispSwObj *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__dispswobjControl__)(struct DispSwObj *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispswobjUnmap__)(struct DispSwObj *, struct CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__dispswobjGetMemInterMapParams__)(struct DispSwObj *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__dispswobjGetMemoryMappingDescriptor__)(struct DispSwObj *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__dispswobjCheckMemInterUnmap__)(struct DispSwObj *, NvBool); - void (*__dispswobjSetNotificationShare__)(struct DispSwObj *, struct NotifShare *); NV_STATUS (*__dispswobjControlFilter__)(struct DispSwObj *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvU32 (*__dispswobjGetRefCount__)(struct DispSwObj *); NV_STATUS (*__dispswobjUnregisterEvent__)(struct DispSwObj *, NvHandle, NvHandle, NvHandle, NvHandle); - NV_STATUS (*__dispswobjUnmap__)(struct DispSwObj *, struct CALL_CONTEXT *, RsCpuMapping *); - NV_STATUS (*__dispswobjControl_Prologue__)(struct DispSwObj *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispswobjControlSerialization_Prologue__)(struct DispSwObj *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispswobjCanCopy__)(struct DispSwObj *); - NV_STATUS (*__dispswobjMapTo__)(struct DispSwObj *, RS_RES_MAP_TO_PARAMS *); - void (*__dispswobjAddAdditionalDependants__)(struct RsClient *, struct DispSwObj *, RsResourceRef *); void (*__dispswobjPreDestruct__)(struct DispSwObj *); - NV_STATUS (*__dispswobjUnmapFrom__)(struct DispSwObj *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__dispswobjIsDuplicate__)(struct DispSwObj *, NvHandle, NvBool *); + void (*__dispswobjControlSerialization_Epilogue__)(struct DispSwObj *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__dispswobjGetNotificationListPtr__)(struct DispSwObj *); - void (*__dispswobjControl_Epilogue__)(struct DispSwObj *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); struct NotifShare *(*__dispswobjGetNotificationShare__)(struct DispSwObj *); - NV_STATUS (*__dispswobjControlLookup__)(struct DispSwObj *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__dispswobjMap__)(struct DispSwObj *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NV_STATUS (*__dispswobjGetOrAllocNotifShare__)(struct DispSwObj *, NvHandle, NvHandle, struct NotifShare **); }; @@ -1170,27 +1200,29 @@ NV_STATUS __nvoc_objCreate_DispSwObj(DispSwObj**, Dynamic*, NvU32, struct CALL_C #define dispswobjCtrlCmdVideoAdaptiveRefreshRate(pDispSwObj, pParams) dispswobjCtrlCmdVideoAdaptiveRefreshRate_DISPATCH(pDispSwObj, pParams) #define dispswobjCtrlCmdGetActiveViewportPointIn(pDispSwObj, pParams) dispswobjCtrlCmdGetActiveViewportPointIn_DISPATCH(pDispSwObj, pParams) #define dispswobjShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) dispswobjShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) -#define dispswobjControl(pDisplayApi, pCallContext, pParams) dispswobjControl_DISPATCH(pDisplayApi, pCallContext, pParams) +#define dispswobjCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) dispswobjCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define dispswobjMapTo(pResource, pParams) dispswobjMapTo_DISPATCH(pResource, pParams) #define dispswobjAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) dispswobjAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +#define dispswobjSetNotificationShare(pNotifier, pNotifShare) dispswobjSetNotificationShare_DISPATCH(pNotifier, pNotifShare) +#define dispswobjGetRefCount(pResource) dispswobjGetRefCount_DISPATCH(pResource) +#define dispswobjAddAdditionalDependants(pClient, pResource, pReference) dispswobjAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define dispswobjControl_Prologue(pDisplayApi, pCallContext, pRsParams) dispswobjControl_Prologue_DISPATCH(pDisplayApi, pCallContext, pRsParams) +#define dispswobjUnmapFrom(pResource, pParams) dispswobjUnmapFrom_DISPATCH(pResource, pParams) +#define dispswobjControl_Epilogue(pDisplayApi, pCallContext, pRsParams) dispswobjControl_Epilogue_DISPATCH(pDisplayApi, pCallContext, pRsParams) +#define dispswobjControlLookup(pResource, pParams, ppEntry) dispswobjControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define dispswobjControl(pDisplayApi, pCallContext, pParams) dispswobjControl_DISPATCH(pDisplayApi, pCallContext, pParams) +#define dispswobjUnmap(pResource, pCallContext, pCpuMapping) dispswobjUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define dispswobjGetMemInterMapParams(pRmResource, pParams) dispswobjGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define dispswobjGetMemoryMappingDescriptor(pRmResource, ppMemDesc) dispswobjGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define dispswobjCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) dispswobjCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define dispswobjSetNotificationShare(pNotifier, pNotifShare) dispswobjSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define dispswobjControlFilter(pResource, pCallContext, pParams) dispswobjControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define dispswobjGetRefCount(pResource) dispswobjGetRefCount_DISPATCH(pResource) #define dispswobjUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) dispswobjUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) -#define dispswobjUnmap(pResource, pCallContext, pCpuMapping) dispswobjUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) -#define dispswobjControl_Prologue(pDisplayApi, pCallContext, pRsParams) dispswobjControl_Prologue_DISPATCH(pDisplayApi, pCallContext, pRsParams) +#define dispswobjControlSerialization_Prologue(pResource, pCallContext, pParams) dispswobjControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dispswobjCanCopy(pResource) dispswobjCanCopy_DISPATCH(pResource) -#define dispswobjMapTo(pResource, pParams) dispswobjMapTo_DISPATCH(pResource, pParams) -#define dispswobjAddAdditionalDependants(pClient, pResource, pReference) dispswobjAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define dispswobjPreDestruct(pResource) dispswobjPreDestruct_DISPATCH(pResource) -#define dispswobjUnmapFrom(pResource, pParams) dispswobjUnmapFrom_DISPATCH(pResource, pParams) #define dispswobjIsDuplicate(pResource, hMemory, pDuplicate) dispswobjIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define dispswobjControlSerialization_Epilogue(pResource, pCallContext, pParams) dispswobjControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define dispswobjGetNotificationListPtr(pNotifier) dispswobjGetNotificationListPtr_DISPATCH(pNotifier) -#define dispswobjControl_Epilogue(pDisplayApi, pCallContext, pRsParams) dispswobjControl_Epilogue_DISPATCH(pDisplayApi, pCallContext, pRsParams) #define dispswobjGetNotificationShare(pNotifier) dispswobjGetNotificationShare_DISPATCH(pNotifier) -#define dispswobjControlLookup(pResource, pParams, ppEntry) dispswobjControlLookup_DISPATCH(pResource, pParams, ppEntry) #define dispswobjMap(pResource, pCallContext, pParams, pCpuMapping) dispswobjMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) #define dispswobjGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) dispswobjGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) NV_STATUS dispswobjCtrlCmdIsModePossible_IMPL(struct DispSwObj *pDispSwObj, NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS *pParams); @@ -1221,14 +1253,54 @@ static inline NvBool dispswobjShareCallback_DISPATCH(struct DispSwObj *pResource return pResource->__dispswobjShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS dispswobjControl_DISPATCH(struct DispSwObj *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pDisplayApi->__dispswobjControl__(pDisplayApi, pCallContext, pParams); +static inline NV_STATUS dispswobjCheckMemInterUnmap_DISPATCH(struct DispSwObj *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__dispswobjCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS dispswobjMapTo_DISPATCH(struct DispSwObj *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__dispswobjMapTo__(pResource, pParams); } static inline NvBool dispswobjAccessCallback_DISPATCH(struct DispSwObj *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return pResource->__dispswobjAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); } +static inline void dispswobjSetNotificationShare_DISPATCH(struct DispSwObj *pNotifier, struct NotifShare *pNotifShare) { + pNotifier->__dispswobjSetNotificationShare__(pNotifier, pNotifShare); +} + +static inline NvU32 dispswobjGetRefCount_DISPATCH(struct DispSwObj *pResource) { + return pResource->__dispswobjGetRefCount__(pResource); +} + +static inline void dispswobjAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct DispSwObj *pResource, RsResourceRef *pReference) { + pResource->__dispswobjAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS dispswobjControl_Prologue_DISPATCH(struct DispSwObj *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + return pDisplayApi->__dispswobjControl_Prologue__(pDisplayApi, pCallContext, pRsParams); +} + +static inline NV_STATUS dispswobjUnmapFrom_DISPATCH(struct DispSwObj *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__dispswobjUnmapFrom__(pResource, pParams); +} + +static inline void dispswobjControl_Epilogue_DISPATCH(struct DispSwObj *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + pDisplayApi->__dispswobjControl_Epilogue__(pDisplayApi, pCallContext, pRsParams); +} + +static inline NV_STATUS dispswobjControlLookup_DISPATCH(struct DispSwObj *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__dispswobjControlLookup__(pResource, pParams, ppEntry); +} + +static inline NV_STATUS dispswobjControl_DISPATCH(struct DispSwObj *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pDisplayApi->__dispswobjControl__(pDisplayApi, pCallContext, pParams); +} + +static inline NV_STATUS dispswobjUnmap_DISPATCH(struct DispSwObj *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__dispswobjUnmap__(pResource, pCallContext, pCpuMapping); +} + static inline NV_STATUS dispswobjGetMemInterMapParams_DISPATCH(struct DispSwObj *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { return pRmResource->__dispswobjGetMemInterMapParams__(pRmResource, pParams); } @@ -1237,74 +1309,42 @@ static inline NV_STATUS dispswobjGetMemoryMappingDescriptor_DISPATCH(struct Disp return pRmResource->__dispswobjGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS dispswobjCheckMemInterUnmap_DISPATCH(struct DispSwObj *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__dispswobjCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline void dispswobjSetNotificationShare_DISPATCH(struct DispSwObj *pNotifier, struct NotifShare *pNotifShare) { - pNotifier->__dispswobjSetNotificationShare__(pNotifier, pNotifShare); -} - static inline NV_STATUS dispswobjControlFilter_DISPATCH(struct DispSwObj *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__dispswobjControlFilter__(pResource, pCallContext, pParams); } -static inline NvU32 dispswobjGetRefCount_DISPATCH(struct DispSwObj *pResource) { - return pResource->__dispswobjGetRefCount__(pResource); -} - static inline NV_STATUS dispswobjUnregisterEvent_DISPATCH(struct DispSwObj *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { return pNotifier->__dispswobjUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static inline NV_STATUS dispswobjUnmap_DISPATCH(struct DispSwObj *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pResource->__dispswobjUnmap__(pResource, pCallContext, pCpuMapping); -} - -static inline NV_STATUS dispswobjControl_Prologue_DISPATCH(struct DispSwObj *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - return pDisplayApi->__dispswobjControl_Prologue__(pDisplayApi, pCallContext, pRsParams); +static inline NV_STATUS dispswobjControlSerialization_Prologue_DISPATCH(struct DispSwObj *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dispswobjControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool dispswobjCanCopy_DISPATCH(struct DispSwObj *pResource) { return pResource->__dispswobjCanCopy__(pResource); } -static inline NV_STATUS dispswobjMapTo_DISPATCH(struct DispSwObj *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__dispswobjMapTo__(pResource, pParams); -} - -static inline void dispswobjAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct DispSwObj *pResource, RsResourceRef *pReference) { - pResource->__dispswobjAddAdditionalDependants__(pClient, pResource, pReference); -} - static inline void dispswobjPreDestruct_DISPATCH(struct DispSwObj *pResource) { pResource->__dispswobjPreDestruct__(pResource); } -static inline NV_STATUS dispswobjUnmapFrom_DISPATCH(struct DispSwObj *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__dispswobjUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS dispswobjIsDuplicate_DISPATCH(struct DispSwObj *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__dispswobjIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void dispswobjControlSerialization_Epilogue_DISPATCH(struct DispSwObj *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__dispswobjControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *dispswobjGetNotificationListPtr_DISPATCH(struct DispSwObj *pNotifier) { return pNotifier->__dispswobjGetNotificationListPtr__(pNotifier); } -static inline void dispswobjControl_Epilogue_DISPATCH(struct DispSwObj *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - pDisplayApi->__dispswobjControl_Epilogue__(pDisplayApi, pCallContext, pRsParams); -} - static inline struct NotifShare *dispswobjGetNotificationShare_DISPATCH(struct DispSwObj *pNotifier) { return pNotifier->__dispswobjGetNotificationShare__(pNotifier); } -static inline NV_STATUS dispswobjControlLookup_DISPATCH(struct DispSwObj *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__dispswobjControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS dispswobjMap_DISPATCH(struct DispSwObj *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return pResource->__dispswobjMap__(pResource, pCallContext, pParams, pCpuMapping); } @@ -1344,24 +1384,29 @@ struct DispCommon { NV_STATUS (*__dispcmnCtrlCmdSystemGetVblankCounter__)(struct DispCommon *, NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSystemGetVblankEnable__)(struct DispCommon *, NV0073_CTRL_SYSTEM_GET_VBLANK_ENABLE_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSystemCheckSidebandSrSupport__)(struct DispCommon *, NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdSystemGetHotplugState__)(struct DispCommon *, NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSystemGetInternalDisplays__)(struct DispCommon *, NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS *); - NV_STATUS (*__dispcmnCtrlCmdDpEnableVrr__)(struct DispCommon *, NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdSystemGetConnectorTable__)(struct DispCommon *, NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdClearELVBlock__)(struct DispCommon *, NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSpecificDisplayChange__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpGetSpreadSpectrum__)(struct DispCommon *, NV0073_CTRL_DFP_GET_SPREAD_SPECTRUM_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpGetLcdGpioPinNum__)(struct DispCommon *, NV0073_CTRL_DFP_GET_LCD_GPIO_PIN_NUM_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdDpEnableVrr__)(struct DispCommon *, NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDpGetAudioMuteStream__)(struct DispCommon *, NV0073_CTRL_DP_GET_AUDIO_MUTESTREAM_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDpAuxchI2cTransferCtrl__)(struct DispCommon *, NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_CTRL_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDpASSRCtrl__)(struct DispCommon *, NV0073_CTRL_DP_ASSR_CTRL_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDpSetEcf__)(struct DispCommon *, NV0073_CTRL_CMD_DP_SET_ECF_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdStereoDongleSupported__)(struct DispCommon *, NV0073_CTRL_STEREO_DONGLE_SUPPORTED_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdDfpRecordChannelRegisters__)(struct DispCommon *, NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSpecificGetBacklightBrightness__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSpecificSetBacklightBrightness__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdPsrGetSrPanelInfo__)(struct DispCommon *, NV0073_CTRL_PSR_GET_SR_PANEL_INFO_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpSwitchDispMux__)(struct DispCommon *, NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpRunPreDispMuxOperations__)(struct DispCommon *, NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpRunPostDispMuxOperations__)(struct DispCommon *, NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpGetDispMuxStatus__)(struct DispCommon *, NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS *); - NV_STATUS (*__dispcmnCtrlCmdDfpRecordChannelRegisters__)(struct DispCommon *, NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpInternalLcdOverdrive__)(struct DispCommon *, NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdDfpExecuteInternalLcdOverDrivePolicy__)(struct DispCommon *, NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSystemExecuteAcpiMethod__)(struct DispCommon *, NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSystemGetAcpiIdMap__)(struct DispCommon *, NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSpecificSetAcpiIdMapping__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_SET_ACPI_ID_MAPPING_PARAMS *); @@ -1407,9 +1452,11 @@ struct DispCommon { NV_STATUS (*__dispcmnCtrlCmdSpecificGetHdmiGpuCaps__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_GET_HDMI_GPU_CAPS_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSpecificGetHdmiScdcData__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_GET_HDMI_SCDC_DATA_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSpecificIsDirectmodeDisplay__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_IS_DIRECTMODE_DISPLAY_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdSpecificDefaultAdaptivesyncDisplay__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSpecificDispI2cReadWrite__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdSpecificSetHdmiAudioMutestream__)(struct DispCommon *, NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpGetInfo__)(struct DispCommon *, NV0073_CTRL_DFP_GET_INFO_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpGetDisplayportDongleInfo__)(struct DispCommon *, NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpSetEldAudioCaps__)(struct DispCommon *, NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS *); @@ -1455,27 +1502,29 @@ struct DispCommon { NV_STATUS (*__dispcmnCtrlCmdDpSetPreemphasisDrivecurrentPostcursor2Data__)(struct DispCommon *, NV0073_CTRL_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDpGetPreemphasisDrivecurrentPostcursor2Data__)(struct DispCommon *, NV0073_CTRL_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS *); NvBool (*__dispcmnShareCallback__)(struct DispCommon *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__dispcmnControl__)(struct DispCommon *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispcmnCheckMemInterUnmap__)(struct DispCommon *, NvBool); + NV_STATUS (*__dispcmnMapTo__)(struct DispCommon *, RS_RES_MAP_TO_PARAMS *); NvBool (*__dispcmnAccessCallback__)(struct DispCommon *, struct RsClient *, void *, RsAccessRight); + void (*__dispcmnSetNotificationShare__)(struct DispCommon *, struct NotifShare *); + NvU32 (*__dispcmnGetRefCount__)(struct DispCommon *); + void (*__dispcmnAddAdditionalDependants__)(struct RsClient *, struct DispCommon *, RsResourceRef *); + NV_STATUS (*__dispcmnControl_Prologue__)(struct DispCommon *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispcmnUnmapFrom__)(struct DispCommon *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__dispcmnControl_Epilogue__)(struct DispCommon *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispcmnControlLookup__)(struct DispCommon *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__dispcmnControl__)(struct DispCommon *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispcmnUnmap__)(struct DispCommon *, struct CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__dispcmnGetMemInterMapParams__)(struct DispCommon *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__dispcmnGetMemoryMappingDescriptor__)(struct DispCommon *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__dispcmnCheckMemInterUnmap__)(struct DispCommon *, NvBool); - void (*__dispcmnSetNotificationShare__)(struct DispCommon *, struct NotifShare *); NV_STATUS (*__dispcmnControlFilter__)(struct DispCommon *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvU32 (*__dispcmnGetRefCount__)(struct DispCommon *); NV_STATUS (*__dispcmnUnregisterEvent__)(struct DispCommon *, NvHandle, NvHandle, NvHandle, NvHandle); - NV_STATUS (*__dispcmnUnmap__)(struct DispCommon *, struct CALL_CONTEXT *, RsCpuMapping *); - NV_STATUS (*__dispcmnControl_Prologue__)(struct DispCommon *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispcmnControlSerialization_Prologue__)(struct DispCommon *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispcmnCanCopy__)(struct DispCommon *); - NV_STATUS (*__dispcmnMapTo__)(struct DispCommon *, RS_RES_MAP_TO_PARAMS *); - void (*__dispcmnAddAdditionalDependants__)(struct RsClient *, struct DispCommon *, RsResourceRef *); void (*__dispcmnPreDestruct__)(struct DispCommon *); - NV_STATUS (*__dispcmnUnmapFrom__)(struct DispCommon *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__dispcmnIsDuplicate__)(struct DispCommon *, NvHandle, NvBool *); + void (*__dispcmnControlSerialization_Epilogue__)(struct DispCommon *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__dispcmnGetNotificationListPtr__)(struct DispCommon *); - void (*__dispcmnControl_Epilogue__)(struct DispCommon *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); struct NotifShare *(*__dispcmnGetNotificationShare__)(struct DispCommon *); - NV_STATUS (*__dispcmnControlLookup__)(struct DispCommon *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__dispcmnMap__)(struct DispCommon *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NV_STATUS (*__dispcmnGetOrAllocNotifShare__)(struct DispCommon *, NvHandle, NvHandle, struct NotifShare **); NvU32 hotPlugMaskToBeReported; @@ -1513,24 +1562,29 @@ NV_STATUS __nvoc_objCreate_DispCommon(DispCommon**, Dynamic*, NvU32, struct CALL #define dispcmnCtrlCmdSystemGetVblankCounter(pDispCommon, pVBCounterParams) dispcmnCtrlCmdSystemGetVblankCounter_DISPATCH(pDispCommon, pVBCounterParams) #define dispcmnCtrlCmdSystemGetVblankEnable(pDispCommon, pVBEnableParams) dispcmnCtrlCmdSystemGetVblankEnable_DISPATCH(pDispCommon, pVBEnableParams) #define dispcmnCtrlCmdSystemCheckSidebandSrSupport(pDispCommon, pParams) dispcmnCtrlCmdSystemCheckSidebandSrSupport_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdSystemGetHotplugState(pDispCommon, pHotplugParams) dispcmnCtrlCmdSystemGetHotplugState_DISPATCH(pDispCommon, pHotplugParams) #define dispcmnCtrlCmdSystemGetInternalDisplays(pDispCommon, pInternalDisplaysParams) dispcmnCtrlCmdSystemGetInternalDisplays_DISPATCH(pDispCommon, pInternalDisplaysParams) -#define dispcmnCtrlCmdDpEnableVrr(pDispCommon, pParams) dispcmnCtrlCmdDpEnableVrr_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdSystemGetConnectorTable(pDispCommon, pParams) dispcmnCtrlCmdSystemGetConnectorTable_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdClearELVBlock(pDispCommon, pParams) dispcmnCtrlCmdClearELVBlock_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSpecificDisplayChange(pDispCommon, pParams) dispcmnCtrlCmdSpecificDisplayChange_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpGetSpreadSpectrum(pDispCommon, pParams) dispcmnCtrlCmdDfpGetSpreadSpectrum_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpGetLcdGpioPinNum(pDispCommon, pParams) dispcmnCtrlCmdDfpGetLcdGpioPinNum_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdDpEnableVrr(pDispCommon, pParams) dispcmnCtrlCmdDpEnableVrr_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDpGetAudioMuteStream(pDispCommon, pParams) dispcmnCtrlCmdDpGetAudioMuteStream_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDpAuxchI2cTransferCtrl(pDispCommon, pParams) dispcmnCtrlCmdDpAuxchI2cTransferCtrl_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDpASSRCtrl(pDispCommon, pParams) dispcmnCtrlCmdDpASSRCtrl_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDpSetEcf(pDispCommon, pCtrlEcfParams) dispcmnCtrlCmdDpSetEcf_DISPATCH(pDispCommon, pCtrlEcfParams) +#define dispcmnCtrlCmdStereoDongleSupported(pDispCommon, pCtrlStereoParams) dispcmnCtrlCmdStereoDongleSupported_DISPATCH(pDispCommon, pCtrlStereoParams) +#define dispcmnCtrlCmdDfpRecordChannelRegisters(pDispCommon, pParams) dispcmnCtrlCmdDfpRecordChannelRegisters_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSpecificGetBacklightBrightness(pDispCommon, pAllHeadMaskParams) dispcmnCtrlCmdSpecificGetBacklightBrightness_DISPATCH(pDispCommon, pAllHeadMaskParams) #define dispcmnCtrlCmdSpecificSetBacklightBrightness(pDispCommon, pParams) dispcmnCtrlCmdSpecificSetBacklightBrightness_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdPsrGetSrPanelInfo(pDispCommon, pParams) dispcmnCtrlCmdPsrGetSrPanelInfo_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpSwitchDispMux(pDispCommon, pParams) dispcmnCtrlCmdDfpSwitchDispMux_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpRunPreDispMuxOperations(pDispCommon, pParams) dispcmnCtrlCmdDfpRunPreDispMuxOperations_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpRunPostDispMuxOperations(pDispCommon, pParams) dispcmnCtrlCmdDfpRunPostDispMuxOperations_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpGetDispMuxStatus(pDispCommon, pParams) dispcmnCtrlCmdDfpGetDispMuxStatus_DISPATCH(pDispCommon, pParams) -#define dispcmnCtrlCmdDfpRecordChannelRegisters(pDispCommon, pParams) dispcmnCtrlCmdDfpRecordChannelRegisters_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpInternalLcdOverdrive(pDispCommon, pParams) dispcmnCtrlCmdDfpInternalLcdOverdrive_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdDfpExecuteInternalLcdOverDrivePolicy(pDispCommon, pParams) dispcmnCtrlCmdDfpExecuteInternalLcdOverDrivePolicy_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSystemExecuteAcpiMethod(pDispCommon, pAcpiMethodParams) dispcmnCtrlCmdSystemExecuteAcpiMethod_DISPATCH(pDispCommon, pAcpiMethodParams) #define dispcmnCtrlCmdSystemGetAcpiIdMap(pDispCommon, pAcpiIdMapParams) dispcmnCtrlCmdSystemGetAcpiIdMap_DISPATCH(pDispCommon, pAcpiIdMapParams) #define dispcmnCtrlCmdSpecificSetAcpiIdMapping(pDispCommon, pParams) dispcmnCtrlCmdSpecificSetAcpiIdMapping_DISPATCH(pDispCommon, pParams) @@ -1576,9 +1630,11 @@ NV_STATUS __nvoc_objCreate_DispCommon(DispCommon**, Dynamic*, NvU32, struct CALL #define dispcmnCtrlCmdSpecificGetHdmiGpuCaps(pDispCommon, pParams) dispcmnCtrlCmdSpecificGetHdmiGpuCaps_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSpecificGetHdmiScdcData(pDispCommon, pParams) dispcmnCtrlCmdSpecificGetHdmiScdcData_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSpecificIsDirectmodeDisplay(pDispCommon, pParams) dispcmnCtrlCmdSpecificIsDirectmodeDisplay_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdSpecificDefaultAdaptivesyncDisplay(pDispCommon, pParams) dispcmnCtrlCmdSpecificDefaultAdaptivesyncDisplay_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation(pDispCommon, pParams) dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSpecificDispI2cReadWrite(pDispCommon, pParams) dispcmnCtrlCmdSpecificDispI2cReadWrite_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment(pDispCommon, pParams) dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdSpecificSetHdmiAudioMutestream(pDispCommon, pParams) dispcmnCtrlCmdSpecificSetHdmiAudioMutestream_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpGetInfo(pDispCommon, pParams) dispcmnCtrlCmdDfpGetInfo_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpGetDisplayportDongleInfo(pDispCommon, pParams) dispcmnCtrlCmdDfpGetDisplayportDongleInfo_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpSetEldAudioCaps(pDispCommon, pEldAudioCapsParams) dispcmnCtrlCmdDfpSetEldAudioCaps_DISPATCH(pDispCommon, pEldAudioCapsParams) @@ -1624,27 +1680,29 @@ NV_STATUS __nvoc_objCreate_DispCommon(DispCommon**, Dynamic*, NvU32, struct CALL #define dispcmnCtrlCmdDpSetPreemphasisDrivecurrentPostcursor2Data(pDispCommon, pParams) dispcmnCtrlCmdDpSetPreemphasisDrivecurrentPostcursor2Data_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDpGetPreemphasisDrivecurrentPostcursor2Data(pDispCommon, pParams) dispcmnCtrlCmdDpGetPreemphasisDrivecurrentPostcursor2Data_DISPATCH(pDispCommon, pParams) #define dispcmnShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) dispcmnShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) -#define dispcmnControl(pDisplayApi, pCallContext, pParams) dispcmnControl_DISPATCH(pDisplayApi, pCallContext, pParams) +#define dispcmnCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) dispcmnCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define dispcmnMapTo(pResource, pParams) dispcmnMapTo_DISPATCH(pResource, pParams) #define dispcmnAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) dispcmnAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +#define dispcmnSetNotificationShare(pNotifier, pNotifShare) dispcmnSetNotificationShare_DISPATCH(pNotifier, pNotifShare) +#define dispcmnGetRefCount(pResource) dispcmnGetRefCount_DISPATCH(pResource) +#define dispcmnAddAdditionalDependants(pClient, pResource, pReference) dispcmnAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define dispcmnControl_Prologue(pDisplayApi, pCallContext, pRsParams) dispcmnControl_Prologue_DISPATCH(pDisplayApi, pCallContext, pRsParams) +#define dispcmnUnmapFrom(pResource, pParams) dispcmnUnmapFrom_DISPATCH(pResource, pParams) +#define dispcmnControl_Epilogue(pDisplayApi, pCallContext, pRsParams) dispcmnControl_Epilogue_DISPATCH(pDisplayApi, pCallContext, pRsParams) +#define dispcmnControlLookup(pResource, pParams, ppEntry) dispcmnControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define dispcmnControl(pDisplayApi, pCallContext, pParams) dispcmnControl_DISPATCH(pDisplayApi, pCallContext, pParams) +#define dispcmnUnmap(pResource, pCallContext, pCpuMapping) dispcmnUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define dispcmnGetMemInterMapParams(pRmResource, pParams) dispcmnGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define dispcmnGetMemoryMappingDescriptor(pRmResource, ppMemDesc) dispcmnGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define dispcmnCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) dispcmnCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define dispcmnSetNotificationShare(pNotifier, pNotifShare) dispcmnSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define dispcmnControlFilter(pResource, pCallContext, pParams) dispcmnControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define dispcmnGetRefCount(pResource) dispcmnGetRefCount_DISPATCH(pResource) #define dispcmnUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) dispcmnUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) -#define dispcmnUnmap(pResource, pCallContext, pCpuMapping) dispcmnUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) -#define dispcmnControl_Prologue(pDisplayApi, pCallContext, pRsParams) dispcmnControl_Prologue_DISPATCH(pDisplayApi, pCallContext, pRsParams) +#define dispcmnControlSerialization_Prologue(pResource, pCallContext, pParams) dispcmnControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dispcmnCanCopy(pResource) dispcmnCanCopy_DISPATCH(pResource) -#define dispcmnMapTo(pResource, pParams) dispcmnMapTo_DISPATCH(pResource, pParams) -#define dispcmnAddAdditionalDependants(pClient, pResource, pReference) dispcmnAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define dispcmnPreDestruct(pResource) dispcmnPreDestruct_DISPATCH(pResource) -#define dispcmnUnmapFrom(pResource, pParams) dispcmnUnmapFrom_DISPATCH(pResource, pParams) #define dispcmnIsDuplicate(pResource, hMemory, pDuplicate) dispcmnIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define dispcmnControlSerialization_Epilogue(pResource, pCallContext, pParams) dispcmnControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define dispcmnGetNotificationListPtr(pNotifier) dispcmnGetNotificationListPtr_DISPATCH(pNotifier) -#define dispcmnControl_Epilogue(pDisplayApi, pCallContext, pRsParams) dispcmnControl_Epilogue_DISPATCH(pDisplayApi, pCallContext, pRsParams) #define dispcmnGetNotificationShare(pNotifier) dispcmnGetNotificationShare_DISPATCH(pNotifier) -#define dispcmnControlLookup(pResource, pParams, ppEntry) dispcmnControlLookup_DISPATCH(pResource, pParams, ppEntry) #define dispcmnMap(pResource, pCallContext, pParams, pCpuMapping) dispcmnMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) #define dispcmnGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) dispcmnGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) NV_STATUS dispcmnCtrlCmdSystemGetVblankCounter_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS *pVBCounterParams); @@ -1665,16 +1723,22 @@ static inline NV_STATUS dispcmnCtrlCmdSystemCheckSidebandSrSupport_DISPATCH(stru return pDispCommon->__dispcmnCtrlCmdSystemCheckSidebandSrSupport__(pDispCommon, pParams); } +NV_STATUS dispcmnCtrlCmdSystemGetHotplugState_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS *pHotplugParams); + +static inline NV_STATUS dispcmnCtrlCmdSystemGetHotplugState_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_GET_HOTPLUG_STATE_PARAMS *pHotplugParams) { + return pDispCommon->__dispcmnCtrlCmdSystemGetHotplugState__(pDispCommon, pHotplugParams); +} + NV_STATUS dispcmnCtrlCmdSystemGetInternalDisplays_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS *pInternalDisplaysParams); static inline NV_STATUS dispcmnCtrlCmdSystemGetInternalDisplays_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS *pInternalDisplaysParams) { return pDispCommon->__dispcmnCtrlCmdSystemGetInternalDisplays__(pDispCommon, pInternalDisplaysParams); } -NV_STATUS dispcmnCtrlCmdDpEnableVrr_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS *pParams); +NV_STATUS dispcmnCtrlCmdSystemGetConnectorTable_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS *pParams); -static inline NV_STATUS dispcmnCtrlCmdDpEnableVrr_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS *pParams) { - return pDispCommon->__dispcmnCtrlCmdDpEnableVrr__(pDispCommon, pParams); +static inline NV_STATUS dispcmnCtrlCmdSystemGetConnectorTable_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_GET_CONNECTOR_TABLE_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdSystemGetConnectorTable__(pDispCommon, pParams); } NV_STATUS dispcmnCtrlCmdClearELVBlock_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS *pParams); @@ -1701,6 +1765,12 @@ static inline NV_STATUS dispcmnCtrlCmdDfpGetLcdGpioPinNum_DISPATCH(struct DispCo return pDispCommon->__dispcmnCtrlCmdDfpGetLcdGpioPinNum__(pDispCommon, pParams); } +NV_STATUS dispcmnCtrlCmdDpEnableVrr_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdDpEnableVrr_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdDpEnableVrr__(pDispCommon, pParams); +} + NV_STATUS dispcmnCtrlCmdDpGetAudioMuteStream_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_DP_GET_AUDIO_MUTESTREAM_PARAMS *pParams); static inline NV_STATUS dispcmnCtrlCmdDpGetAudioMuteStream_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_DP_GET_AUDIO_MUTESTREAM_PARAMS *pParams) { @@ -1725,6 +1795,18 @@ static inline NV_STATUS dispcmnCtrlCmdDpSetEcf_DISPATCH(struct DispCommon *pDisp return pDispCommon->__dispcmnCtrlCmdDpSetEcf__(pDispCommon, pCtrlEcfParams); } +NV_STATUS dispcmnCtrlCmdStereoDongleSupported_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_STEREO_DONGLE_SUPPORTED_PARAMS *pCtrlStereoParams); + +static inline NV_STATUS dispcmnCtrlCmdStereoDongleSupported_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_STEREO_DONGLE_SUPPORTED_PARAMS *pCtrlStereoParams) { + return pDispCommon->__dispcmnCtrlCmdStereoDongleSupported__(pDispCommon, pCtrlStereoParams); +} + +NV_STATUS dispcmnCtrlCmdDfpRecordChannelRegisters_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdDfpRecordChannelRegisters_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdDfpRecordChannelRegisters__(pDispCommon, pParams); +} + NV_STATUS dispcmnCtrlCmdSpecificGetBacklightBrightness_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS *pAllHeadMaskParams); static inline NV_STATUS dispcmnCtrlCmdSpecificGetBacklightBrightness_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS *pAllHeadMaskParams) { @@ -1737,6 +1819,12 @@ static inline NV_STATUS dispcmnCtrlCmdSpecificSetBacklightBrightness_DISPATCH(st return pDispCommon->__dispcmnCtrlCmdSpecificSetBacklightBrightness__(pDispCommon, pParams); } +NV_STATUS dispcmnCtrlCmdPsrGetSrPanelInfo_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_PSR_GET_SR_PANEL_INFO_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdPsrGetSrPanelInfo_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_PSR_GET_SR_PANEL_INFO_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdPsrGetSrPanelInfo__(pDispCommon, pParams); +} + NV_STATUS dispcmnCtrlCmdDfpSwitchDispMux_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS *pParams); static inline NV_STATUS dispcmnCtrlCmdDfpSwitchDispMux_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS *pParams) { @@ -1761,18 +1849,18 @@ static inline NV_STATUS dispcmnCtrlCmdDfpGetDispMuxStatus_DISPATCH(struct DispCo return pDispCommon->__dispcmnCtrlCmdDfpGetDispMuxStatus__(pDispCommon, pParams); } -NV_STATUS dispcmnCtrlCmdDfpRecordChannelRegisters_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS *pParams); - -static inline NV_STATUS dispcmnCtrlCmdDfpRecordChannelRegisters_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS *pParams) { - return pDispCommon->__dispcmnCtrlCmdDfpRecordChannelRegisters__(pDispCommon, pParams); -} - NV_STATUS dispcmnCtrlCmdDfpInternalLcdOverdrive_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS *pParams); static inline NV_STATUS dispcmnCtrlCmdDfpInternalLcdOverdrive_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS *pParams) { return pDispCommon->__dispcmnCtrlCmdDfpInternalLcdOverdrive__(pDispCommon, pParams); } +NV_STATUS dispcmnCtrlCmdDfpExecuteInternalLcdOverDrivePolicy_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdDfpExecuteInternalLcdOverDrivePolicy_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdDfpExecuteInternalLcdOverDrivePolicy__(pDispCommon, pParams); +} + NV_STATUS dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS *pAcpiMethodParams); static inline NV_STATUS dispcmnCtrlCmdSystemExecuteAcpiMethod_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS *pAcpiMethodParams) { @@ -2043,6 +2131,12 @@ static inline NV_STATUS dispcmnCtrlCmdSpecificIsDirectmodeDisplay_DISPATCH(struc return pDispCommon->__dispcmnCtrlCmdSpecificIsDirectmodeDisplay__(pDispCommon, pParams); } +NV_STATUS dispcmnCtrlCmdSpecificDefaultAdaptivesyncDisplay_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdSpecificDefaultAdaptivesyncDisplay_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdSpecificDefaultAdaptivesyncDisplay__(pDispCommon, pParams); +} + NV_STATUS dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_PARAMS *pParams); static inline NV_STATUS dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_PARAMS *pParams) { @@ -2061,6 +2155,12 @@ static inline NV_STATUS dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment_DISPA return pDispCommon->__dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment__(pDispCommon, pParams); } +NV_STATUS dispcmnCtrlCmdSpecificSetHdmiAudioMutestream_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdSpecificSetHdmiAudioMutestream_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdSpecificSetHdmiAudioMutestream__(pDispCommon, pParams); +} + NV_STATUS dispcmnCtrlCmdDfpGetInfo_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_DFP_GET_INFO_PARAMS *pParams); static inline NV_STATUS dispcmnCtrlCmdDfpGetInfo_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_DFP_GET_INFO_PARAMS *pParams) { @@ -2329,14 +2429,54 @@ static inline NvBool dispcmnShareCallback_DISPATCH(struct DispCommon *pResource, return pResource->__dispcmnShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS dispcmnControl_DISPATCH(struct DispCommon *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pDisplayApi->__dispcmnControl__(pDisplayApi, pCallContext, pParams); +static inline NV_STATUS dispcmnCheckMemInterUnmap_DISPATCH(struct DispCommon *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__dispcmnCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS dispcmnMapTo_DISPATCH(struct DispCommon *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__dispcmnMapTo__(pResource, pParams); } static inline NvBool dispcmnAccessCallback_DISPATCH(struct DispCommon *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return pResource->__dispcmnAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); } +static inline void dispcmnSetNotificationShare_DISPATCH(struct DispCommon *pNotifier, struct NotifShare *pNotifShare) { + pNotifier->__dispcmnSetNotificationShare__(pNotifier, pNotifShare); +} + +static inline NvU32 dispcmnGetRefCount_DISPATCH(struct DispCommon *pResource) { + return pResource->__dispcmnGetRefCount__(pResource); +} + +static inline void dispcmnAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct DispCommon *pResource, RsResourceRef *pReference) { + pResource->__dispcmnAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS dispcmnControl_Prologue_DISPATCH(struct DispCommon *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + return pDisplayApi->__dispcmnControl_Prologue__(pDisplayApi, pCallContext, pRsParams); +} + +static inline NV_STATUS dispcmnUnmapFrom_DISPATCH(struct DispCommon *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__dispcmnUnmapFrom__(pResource, pParams); +} + +static inline void dispcmnControl_Epilogue_DISPATCH(struct DispCommon *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { + pDisplayApi->__dispcmnControl_Epilogue__(pDisplayApi, pCallContext, pRsParams); +} + +static inline NV_STATUS dispcmnControlLookup_DISPATCH(struct DispCommon *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__dispcmnControlLookup__(pResource, pParams, ppEntry); +} + +static inline NV_STATUS dispcmnControl_DISPATCH(struct DispCommon *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pDisplayApi->__dispcmnControl__(pDisplayApi, pCallContext, pParams); +} + +static inline NV_STATUS dispcmnUnmap_DISPATCH(struct DispCommon *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__dispcmnUnmap__(pResource, pCallContext, pCpuMapping); +} + static inline NV_STATUS dispcmnGetMemInterMapParams_DISPATCH(struct DispCommon *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { return pRmResource->__dispcmnGetMemInterMapParams__(pRmResource, pParams); } @@ -2345,74 +2485,42 @@ static inline NV_STATUS dispcmnGetMemoryMappingDescriptor_DISPATCH(struct DispCo return pRmResource->__dispcmnGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS dispcmnCheckMemInterUnmap_DISPATCH(struct DispCommon *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__dispcmnCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline void dispcmnSetNotificationShare_DISPATCH(struct DispCommon *pNotifier, struct NotifShare *pNotifShare) { - pNotifier->__dispcmnSetNotificationShare__(pNotifier, pNotifShare); -} - static inline NV_STATUS dispcmnControlFilter_DISPATCH(struct DispCommon *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__dispcmnControlFilter__(pResource, pCallContext, pParams); } -static inline NvU32 dispcmnGetRefCount_DISPATCH(struct DispCommon *pResource) { - return pResource->__dispcmnGetRefCount__(pResource); -} - static inline NV_STATUS dispcmnUnregisterEvent_DISPATCH(struct DispCommon *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { return pNotifier->__dispcmnUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static inline NV_STATUS dispcmnUnmap_DISPATCH(struct DispCommon *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pResource->__dispcmnUnmap__(pResource, pCallContext, pCpuMapping); -} - -static inline NV_STATUS dispcmnControl_Prologue_DISPATCH(struct DispCommon *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - return pDisplayApi->__dispcmnControl_Prologue__(pDisplayApi, pCallContext, pRsParams); +static inline NV_STATUS dispcmnControlSerialization_Prologue_DISPATCH(struct DispCommon *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dispcmnControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool dispcmnCanCopy_DISPATCH(struct DispCommon *pResource) { return pResource->__dispcmnCanCopy__(pResource); } -static inline NV_STATUS dispcmnMapTo_DISPATCH(struct DispCommon *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__dispcmnMapTo__(pResource, pParams); -} - -static inline void dispcmnAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct DispCommon *pResource, RsResourceRef *pReference) { - pResource->__dispcmnAddAdditionalDependants__(pClient, pResource, pReference); -} - static inline void dispcmnPreDestruct_DISPATCH(struct DispCommon *pResource) { pResource->__dispcmnPreDestruct__(pResource); } -static inline NV_STATUS dispcmnUnmapFrom_DISPATCH(struct DispCommon *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__dispcmnUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS dispcmnIsDuplicate_DISPATCH(struct DispCommon *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__dispcmnIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void dispcmnControlSerialization_Epilogue_DISPATCH(struct DispCommon *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__dispcmnControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *dispcmnGetNotificationListPtr_DISPATCH(struct DispCommon *pNotifier) { return pNotifier->__dispcmnGetNotificationListPtr__(pNotifier); } -static inline void dispcmnControl_Epilogue_DISPATCH(struct DispCommon *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams) { - pDisplayApi->__dispcmnControl_Epilogue__(pDisplayApi, pCallContext, pRsParams); -} - static inline struct NotifShare *dispcmnGetNotificationShare_DISPATCH(struct DispCommon *pNotifier) { return pNotifier->__dispcmnGetNotificationShare__(pNotifier); } -static inline NV_STATUS dispcmnControlLookup_DISPATCH(struct DispCommon *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__dispcmnControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS dispcmnMap_DISPATCH(struct DispCommon *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return pResource->__dispcmnMap__(pResource, pCallContext, pParams, pCpuMapping); } diff --git a/src/nvidia/generated/g_disp_sf_user_nvoc.c b/src/nvidia/generated/g_disp_sf_user_nvoc.c index 279760081..a8503abc5 100644 --- a/src/nvidia/generated/g_disp_sf_user_nvoc.c +++ b/src/nvidia/generated/g_disp_sf_user_nvoc.c @@ -101,6 +101,50 @@ static NvBool __nvoc_thunk_GpuResource_dispsfShareCallback(struct DispSfUser *pG return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispSfUser_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } +static NV_STATUS __nvoc_thunk_RmResource_dispsfCheckMemInterUnmap(struct DispSfUser *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispSfUser_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispsfMapTo(struct DispSfUser *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_dispsfGetMapAddrSpace(struct DispSfUser *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispSfUser_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_dispsfGetRefCount(struct DispSfUser *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_dispsfAddAdditionalDependants(struct RsClient *pClient, struct DispSfUser *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_dispsfControl_Prologue(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_dispsfInternalControlForward(struct DispSfUser *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispSfUser_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispsfUnmapFrom(struct DispSfUser *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_dispsfControl_Epilogue(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_dispsfControlLookup(struct DispSfUser *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset), pParams, ppEntry); +} + +static NvHandle __nvoc_thunk_GpuResource_dispsfGetInternalObjectHandle(struct DispSfUser *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispSfUser_GpuResource.offset)); +} + static NV_STATUS __nvoc_thunk_GpuResource_dispsfControl(struct DispSfUser *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispSfUser_GpuResource.offset), pCallContext, pParams); } @@ -117,64 +161,28 @@ static NV_STATUS __nvoc_thunk_RmResource_dispsfGetMemoryMappingDescriptor(struct return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispSfUser_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_GpuResource_dispsfGetMapAddrSpace(struct DispSfUser *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispSfUser_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvHandle __nvoc_thunk_GpuResource_dispsfGetInternalObjectHandle(struct DispSfUser *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispSfUser_GpuResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_dispsfControlFilter(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_dispsfAddAdditionalDependants(struct RsClient *pClient, struct DispSfUser *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_dispsfGetRefCount(struct DispSfUser *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RmResource_dispsfCheckMemInterUnmap(struct DispSfUser *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DispSfUser_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_dispsfMapTo(struct DispSfUser *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_dispsfControl_Prologue(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RmResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_dispsfControlSerialization_Prologue(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_dispsfCanCopy(struct DispSfUser *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_dispsfInternalControlForward(struct DispSfUser *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispSfUser_GpuResource.offset), command, pParams, size); -} - static void __nvoc_thunk_RsResource_dispsfPreDestruct(struct DispSfUser *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_dispsfUnmapFrom(struct DispSfUser *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_dispsfIsDuplicate(struct DispSfUser *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset), hMemory, pDuplicate); } -static void __nvoc_thunk_RmResource_dispsfControl_Epilogue(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_dispsfControlLookup(struct DispSfUser *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_dispsfControlSerialization_Epilogue(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_dispsfMap(struct DispSfUser *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -229,6 +237,28 @@ static void __nvoc_init_funcTable_DispSfUser_1(DispSfUser *pThis) { pThis->__dispsfShareCallback__ = &__nvoc_thunk_GpuResource_dispsfShareCallback; + pThis->__dispsfCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispsfCheckMemInterUnmap; + + pThis->__dispsfMapTo__ = &__nvoc_thunk_RsResource_dispsfMapTo; + + pThis->__dispsfGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_dispsfGetMapAddrSpace; + + pThis->__dispsfGetRefCount__ = &__nvoc_thunk_RsResource_dispsfGetRefCount; + + pThis->__dispsfAddAdditionalDependants__ = &__nvoc_thunk_RsResource_dispsfAddAdditionalDependants; + + pThis->__dispsfControl_Prologue__ = &__nvoc_thunk_RmResource_dispsfControl_Prologue; + + pThis->__dispsfInternalControlForward__ = &__nvoc_thunk_GpuResource_dispsfInternalControlForward; + + pThis->__dispsfUnmapFrom__ = &__nvoc_thunk_RsResource_dispsfUnmapFrom; + + pThis->__dispsfControl_Epilogue__ = &__nvoc_thunk_RmResource_dispsfControl_Epilogue; + + pThis->__dispsfControlLookup__ = &__nvoc_thunk_RsResource_dispsfControlLookup; + + pThis->__dispsfGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_dispsfGetInternalObjectHandle; + pThis->__dispsfControl__ = &__nvoc_thunk_GpuResource_dispsfControl; pThis->__dispsfUnmap__ = &__nvoc_thunk_GpuResource_dispsfUnmap; @@ -237,35 +267,17 @@ static void __nvoc_init_funcTable_DispSfUser_1(DispSfUser *pThis) { pThis->__dispsfGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_dispsfGetMemoryMappingDescriptor; - pThis->__dispsfGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_dispsfGetMapAddrSpace; - - pThis->__dispsfGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_dispsfGetInternalObjectHandle; - pThis->__dispsfControlFilter__ = &__nvoc_thunk_RsResource_dispsfControlFilter; - pThis->__dispsfAddAdditionalDependants__ = &__nvoc_thunk_RsResource_dispsfAddAdditionalDependants; - - pThis->__dispsfGetRefCount__ = &__nvoc_thunk_RsResource_dispsfGetRefCount; - - pThis->__dispsfCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_dispsfCheckMemInterUnmap; - - pThis->__dispsfMapTo__ = &__nvoc_thunk_RsResource_dispsfMapTo; - - pThis->__dispsfControl_Prologue__ = &__nvoc_thunk_RmResource_dispsfControl_Prologue; + pThis->__dispsfControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_dispsfControlSerialization_Prologue; pThis->__dispsfCanCopy__ = &__nvoc_thunk_RsResource_dispsfCanCopy; - pThis->__dispsfInternalControlForward__ = &__nvoc_thunk_GpuResource_dispsfInternalControlForward; - pThis->__dispsfPreDestruct__ = &__nvoc_thunk_RsResource_dispsfPreDestruct; - pThis->__dispsfUnmapFrom__ = &__nvoc_thunk_RsResource_dispsfUnmapFrom; - pThis->__dispsfIsDuplicate__ = &__nvoc_thunk_RsResource_dispsfIsDuplicate; - pThis->__dispsfControl_Epilogue__ = &__nvoc_thunk_RmResource_dispsfControl_Epilogue; - - pThis->__dispsfControlLookup__ = &__nvoc_thunk_RsResource_dispsfControlLookup; + pThis->__dispsfControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_dispsfControlSerialization_Epilogue; pThis->__dispsfMap__ = &__nvoc_thunk_GpuResource_dispsfMap; @@ -293,13 +305,16 @@ NV_STATUS __nvoc_objCreate_DispSfUser(DispSfUser **ppThis, Dynamic *pParent, NvU Object *pParentObj; DispSfUser *pThis; - pThis = portMemAllocNonPaged(sizeof(DispSfUser)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DispSfUser), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(DispSfUser)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DispSfUser); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -315,11 +330,17 @@ NV_STATUS __nvoc_objCreate_DispSfUser(DispSfUser **ppThis, Dynamic *pParent, NvU if (status != NV_OK) goto __nvoc_objCreate_DispSfUser_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_DispSfUser_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(DispSfUser)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_disp_sf_user_nvoc.h b/src/nvidia/generated/g_disp_sf_user_nvoc.h index c735a4d80..8878a8f04 100644 --- a/src/nvidia/generated/g_disp_sf_user_nvoc.h +++ b/src/nvidia/generated/g_disp_sf_user_nvoc.h @@ -62,25 +62,27 @@ struct DispSfUser { struct DispSfUser *__nvoc_pbase_DispSfUser; NV_STATUS (*__dispsfGetRegBaseOffsetAndSize__)(struct DispSfUser *, struct OBJGPU *, NvU32 *, NvU32 *); NvBool (*__dispsfShareCallback__)(struct DispSfUser *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__dispsfCheckMemInterUnmap__)(struct DispSfUser *, NvBool); + NV_STATUS (*__dispsfMapTo__)(struct DispSfUser *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__dispsfGetMapAddrSpace__)(struct DispSfUser *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__dispsfGetRefCount__)(struct DispSfUser *); + void (*__dispsfAddAdditionalDependants__)(struct RsClient *, struct DispSfUser *, RsResourceRef *); + NV_STATUS (*__dispsfControl_Prologue__)(struct DispSfUser *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispsfInternalControlForward__)(struct DispSfUser *, NvU32, void *, NvU32); + NV_STATUS (*__dispsfUnmapFrom__)(struct DispSfUser *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__dispsfControl_Epilogue__)(struct DispSfUser *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispsfControlLookup__)(struct DispSfUser *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__dispsfGetInternalObjectHandle__)(struct DispSfUser *); NV_STATUS (*__dispsfControl__)(struct DispSfUser *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispsfUnmap__)(struct DispSfUser *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__dispsfGetMemInterMapParams__)(struct DispSfUser *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__dispsfGetMemoryMappingDescriptor__)(struct DispSfUser *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__dispsfGetMapAddrSpace__)(struct DispSfUser *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__dispsfGetInternalObjectHandle__)(struct DispSfUser *); NV_STATUS (*__dispsfControlFilter__)(struct DispSfUser *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__dispsfAddAdditionalDependants__)(struct RsClient *, struct DispSfUser *, RsResourceRef *); - NvU32 (*__dispsfGetRefCount__)(struct DispSfUser *); - NV_STATUS (*__dispsfCheckMemInterUnmap__)(struct DispSfUser *, NvBool); - NV_STATUS (*__dispsfMapTo__)(struct DispSfUser *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__dispsfControl_Prologue__)(struct DispSfUser *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__dispsfControlSerialization_Prologue__)(struct DispSfUser *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispsfCanCopy__)(struct DispSfUser *); - NV_STATUS (*__dispsfInternalControlForward__)(struct DispSfUser *, NvU32, void *, NvU32); void (*__dispsfPreDestruct__)(struct DispSfUser *); - NV_STATUS (*__dispsfUnmapFrom__)(struct DispSfUser *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__dispsfIsDuplicate__)(struct DispSfUser *, NvHandle, NvBool *); - void (*__dispsfControl_Epilogue__)(struct DispSfUser *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__dispsfControlLookup__)(struct DispSfUser *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__dispsfControlSerialization_Epilogue__)(struct DispSfUser *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispsfMap__)(struct DispSfUser *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__dispsfAccessCallback__)(struct DispSfUser *, struct RsClient *, void *, RsAccessRight); NvU32 ControlOffset; @@ -117,25 +119,27 @@ NV_STATUS __nvoc_objCreate_DispSfUser(DispSfUser**, Dynamic*, NvU32, struct CALL #define dispsfGetRegBaseOffsetAndSize(pDispSfUser, pGpu, pOffset, pSize) dispsfGetRegBaseOffsetAndSize_DISPATCH(pDispSfUser, pGpu, pOffset, pSize) #define dispsfShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) dispsfShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define dispsfCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) dispsfCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define dispsfMapTo(pResource, pParams) dispsfMapTo_DISPATCH(pResource, pParams) +#define dispsfGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) dispsfGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define dispsfGetRefCount(pResource) dispsfGetRefCount_DISPATCH(pResource) +#define dispsfAddAdditionalDependants(pClient, pResource, pReference) dispsfAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define dispsfControl_Prologue(pResource, pCallContext, pParams) dispsfControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define dispsfInternalControlForward(pGpuResource, command, pParams, size) dispsfInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define dispsfUnmapFrom(pResource, pParams) dispsfUnmapFrom_DISPATCH(pResource, pParams) +#define dispsfControl_Epilogue(pResource, pCallContext, pParams) dispsfControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define dispsfControlLookup(pResource, pParams, ppEntry) dispsfControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define dispsfGetInternalObjectHandle(pGpuResource) dispsfGetInternalObjectHandle_DISPATCH(pGpuResource) #define dispsfControl(pGpuResource, pCallContext, pParams) dispsfControl_DISPATCH(pGpuResource, pCallContext, pParams) #define dispsfUnmap(pGpuResource, pCallContext, pCpuMapping) dispsfUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define dispsfGetMemInterMapParams(pRmResource, pParams) dispsfGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define dispsfGetMemoryMappingDescriptor(pRmResource, ppMemDesc) dispsfGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define dispsfGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) dispsfGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define dispsfGetInternalObjectHandle(pGpuResource) dispsfGetInternalObjectHandle_DISPATCH(pGpuResource) #define dispsfControlFilter(pResource, pCallContext, pParams) dispsfControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define dispsfAddAdditionalDependants(pClient, pResource, pReference) dispsfAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define dispsfGetRefCount(pResource) dispsfGetRefCount_DISPATCH(pResource) -#define dispsfCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) dispsfCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define dispsfMapTo(pResource, pParams) dispsfMapTo_DISPATCH(pResource, pParams) -#define dispsfControl_Prologue(pResource, pCallContext, pParams) dispsfControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define dispsfControlSerialization_Prologue(pResource, pCallContext, pParams) dispsfControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dispsfCanCopy(pResource) dispsfCanCopy_DISPATCH(pResource) -#define dispsfInternalControlForward(pGpuResource, command, pParams, size) dispsfInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define dispsfPreDestruct(pResource) dispsfPreDestruct_DISPATCH(pResource) -#define dispsfUnmapFrom(pResource, pParams) dispsfUnmapFrom_DISPATCH(pResource, pParams) #define dispsfIsDuplicate(pResource, hMemory, pDuplicate) dispsfIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) -#define dispsfControl_Epilogue(pResource, pCallContext, pParams) dispsfControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define dispsfControlLookup(pResource, pParams, ppEntry) dispsfControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define dispsfControlSerialization_Epilogue(pResource, pCallContext, pParams) dispsfControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define dispsfMap(pGpuResource, pCallContext, pParams, pCpuMapping) dispsfMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define dispsfAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) dispsfAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS dispsfGetRegBaseOffsetAndSize_IMPL(struct DispSfUser *pDispSfUser, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize); @@ -148,6 +152,50 @@ static inline NvBool dispsfShareCallback_DISPATCH(struct DispSfUser *pGpuResourc return pGpuResource->__dispsfShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } +static inline NV_STATUS dispsfCheckMemInterUnmap_DISPATCH(struct DispSfUser *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__dispsfCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS dispsfMapTo_DISPATCH(struct DispSfUser *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__dispsfMapTo__(pResource, pParams); +} + +static inline NV_STATUS dispsfGetMapAddrSpace_DISPATCH(struct DispSfUser *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__dispsfGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 dispsfGetRefCount_DISPATCH(struct DispSfUser *pResource) { + return pResource->__dispsfGetRefCount__(pResource); +} + +static inline void dispsfAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct DispSfUser *pResource, RsResourceRef *pReference) { + pResource->__dispsfAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS dispsfControl_Prologue_DISPATCH(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dispsfControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS dispsfInternalControlForward_DISPATCH(struct DispSfUser *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__dispsfInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS dispsfUnmapFrom_DISPATCH(struct DispSfUser *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__dispsfUnmapFrom__(pResource, pParams); +} + +static inline void dispsfControl_Epilogue_DISPATCH(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__dispsfControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS dispsfControlLookup_DISPATCH(struct DispSfUser *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__dispsfControlLookup__(pResource, pParams, ppEntry); +} + +static inline NvHandle dispsfGetInternalObjectHandle_DISPATCH(struct DispSfUser *pGpuResource) { + return pGpuResource->__dispsfGetInternalObjectHandle__(pGpuResource); +} + static inline NV_STATUS dispsfControl_DISPATCH(struct DispSfUser *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pGpuResource->__dispsfControl__(pGpuResource, pCallContext, pParams); } @@ -164,64 +212,28 @@ static inline NV_STATUS dispsfGetMemoryMappingDescriptor_DISPATCH(struct DispSfU return pRmResource->__dispsfGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS dispsfGetMapAddrSpace_DISPATCH(struct DispSfUser *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__dispsfGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvHandle dispsfGetInternalObjectHandle_DISPATCH(struct DispSfUser *pGpuResource) { - return pGpuResource->__dispsfGetInternalObjectHandle__(pGpuResource); -} - static inline NV_STATUS dispsfControlFilter_DISPATCH(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__dispsfControlFilter__(pResource, pCallContext, pParams); } -static inline void dispsfAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct DispSfUser *pResource, RsResourceRef *pReference) { - pResource->__dispsfAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 dispsfGetRefCount_DISPATCH(struct DispSfUser *pResource) { - return pResource->__dispsfGetRefCount__(pResource); -} - -static inline NV_STATUS dispsfCheckMemInterUnmap_DISPATCH(struct DispSfUser *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__dispsfCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS dispsfMapTo_DISPATCH(struct DispSfUser *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__dispsfMapTo__(pResource, pParams); -} - -static inline NV_STATUS dispsfControl_Prologue_DISPATCH(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__dispsfControl_Prologue__(pResource, pCallContext, pParams); +static inline NV_STATUS dispsfControlSerialization_Prologue_DISPATCH(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dispsfControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool dispsfCanCopy_DISPATCH(struct DispSfUser *pResource) { return pResource->__dispsfCanCopy__(pResource); } -static inline NV_STATUS dispsfInternalControlForward_DISPATCH(struct DispSfUser *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__dispsfInternalControlForward__(pGpuResource, command, pParams, size); -} - static inline void dispsfPreDestruct_DISPATCH(struct DispSfUser *pResource) { pResource->__dispsfPreDestruct__(pResource); } -static inline NV_STATUS dispsfUnmapFrom_DISPATCH(struct DispSfUser *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__dispsfUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS dispsfIsDuplicate_DISPATCH(struct DispSfUser *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__dispsfIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline void dispsfControl_Epilogue_DISPATCH(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__dispsfControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS dispsfControlLookup_DISPATCH(struct DispSfUser *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__dispsfControlLookup__(pResource, pParams, ppEntry); +static inline void dispsfControlSerialization_Epilogue_DISPATCH(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__dispsfControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS dispsfMap_DISPATCH(struct DispSfUser *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_dispsw_nvoc.c b/src/nvidia/generated/g_dispsw_nvoc.c index 1e8656595..6ef4a73d7 100644 --- a/src/nvidia/generated/g_dispsw_nvoc.c +++ b/src/nvidia/generated/g_dispsw_nvoc.c @@ -120,7 +120,7 @@ const struct NVOC_CLASS_DEF __nvoc_class_def_DispSwObject = /*pExportInfo=*/ &__nvoc_export_info_DispSwObject }; -static NV_STATUS __nvoc_thunk_DispSwObject_chandesGetSwMethods(struct ChannelDescendant *pDispSw, METHOD **ppMethods, NvU32 *pNumMethods) { +static NV_STATUS __nvoc_thunk_DispSwObject_chandesGetSwMethods(struct ChannelDescendant *pDispSw, const METHOD **ppMethods, NvU32 *pNumMethods) { return dispswGetSwMethods((struct DispSwObject *)(((unsigned char *)pDispSw) - __nvoc_rtti_DispSwObject_ChannelDescendant.offset), ppMethods, pNumMethods); } @@ -212,6 +212,10 @@ static NV_STATUS __nvoc_thunk_Notifier_dispswUnregisterEvent(struct DispSwObject return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispSwObject_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_dispswControlSerialization_Prologue(struct DispSwObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObject_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_dispswCanCopy(struct DispSwObject *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObject_RsResource.offset)); } @@ -224,6 +228,10 @@ static NV_STATUS __nvoc_thunk_RsResource_dispswIsDuplicate(struct DispSwObject * return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObject_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_dispswControlSerialization_Epilogue(struct DispSwObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObject_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_dispswGetNotificationListPtr(struct DispSwObject *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispSwObject_Notifier.offset)); } @@ -369,12 +377,16 @@ static void __nvoc_init_funcTable_DispSwObject_1(DispSwObject *pThis, RmHalspecO pThis->__dispswUnregisterEvent__ = &__nvoc_thunk_Notifier_dispswUnregisterEvent; + pThis->__dispswControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_dispswControlSerialization_Prologue; + pThis->__dispswCanCopy__ = &__nvoc_thunk_RsResource_dispswCanCopy; pThis->__dispswPreDestruct__ = &__nvoc_thunk_RsResource_dispswPreDestruct; pThis->__dispswIsDuplicate__ = &__nvoc_thunk_RsResource_dispswIsDuplicate; + pThis->__dispswControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_dispswControlSerialization_Epilogue; + pThis->__dispswGetNotificationListPtr__ = &__nvoc_thunk_Notifier_dispswGetNotificationListPtr; pThis->__dispswGetNotificationShare__ = &__nvoc_thunk_Notifier_dispswGetNotificationShare; @@ -409,13 +421,16 @@ NV_STATUS __nvoc_objCreate_DispSwObject(DispSwObject **ppThis, Dynamic *pParent, DispSwObject *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(DispSwObject)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DispSwObject), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(DispSwObject)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DispSwObject); + pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -435,11 +450,17 @@ NV_STATUS __nvoc_objCreate_DispSwObject(DispSwObject **ppThis, Dynamic *pParent, if (status != NV_OK) goto __nvoc_objCreate_DispSwObject_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_DispSwObject_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(DispSwObject)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_dispsw_nvoc.h b/src/nvidia/generated/g_dispsw_nvoc.h index c9c56c45b..1f5210133 100644 --- a/src/nvidia/generated/g_dispsw_nvoc.h +++ b/src/nvidia/generated/g_dispsw_nvoc.h @@ -122,7 +122,7 @@ struct DispSwObject { struct Notifier *__nvoc_pbase_Notifier; struct ChannelDescendant *__nvoc_pbase_ChannelDescendant; struct DispSwObject *__nvoc_pbase_DispSwObject; - NV_STATUS (*__dispswGetSwMethods__)(struct DispSwObject *, METHOD **, NvU32 *); + NV_STATUS (*__dispswGetSwMethods__)(struct DispSwObject *, const METHOD **, NvU32 *); NV_STATUS (*__dispswCtrlCmdNotifyOnVblank__)(struct DispSwObject *, NV9072_CTRL_CMD_NOTIFY_ON_VBLANK_PARAMS *); NV_STATUS (*__dispswCheckMemInterUnmap__)(struct DispSwObject *, NvBool); NvBool (*__dispswShareCallback__)(struct DispSwObject *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); @@ -146,9 +146,11 @@ struct DispSwObject { NvBool (*__dispswIsSwMethodStalling__)(struct DispSwObject *, NvU32); NV_STATUS (*__dispswControlFilter__)(struct DispSwObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispswUnregisterEvent__)(struct DispSwObject *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__dispswControlSerialization_Prologue__)(struct DispSwObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispswCanCopy__)(struct DispSwObject *); void (*__dispswPreDestruct__)(struct DispSwObject *); NV_STATUS (*__dispswIsDuplicate__)(struct DispSwObject *, NvHandle, NvBool *); + void (*__dispswControlSerialization_Epilogue__)(struct DispSwObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__dispswGetNotificationListPtr__)(struct DispSwObject *); struct NotifShare *(*__dispswGetNotificationShare__)(struct DispSwObject *); NV_STATUS (*__dispswMap__)(struct DispSwObject *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -212,18 +214,20 @@ NV_STATUS __nvoc_objCreate_DispSwObject(DispSwObject**, Dynamic*, NvU32, CALL_CO #define dispswIsSwMethodStalling(pChannelDescendant, hHandle) dispswIsSwMethodStalling_DISPATCH(pChannelDescendant, hHandle) #define dispswControlFilter(pResource, pCallContext, pParams) dispswControlFilter_DISPATCH(pResource, pCallContext, pParams) #define dispswUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) dispswUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define dispswControlSerialization_Prologue(pResource, pCallContext, pParams) dispswControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dispswCanCopy(pResource) dispswCanCopy_DISPATCH(pResource) #define dispswPreDestruct(pResource) dispswPreDestruct_DISPATCH(pResource) #define dispswIsDuplicate(pResource, hMemory, pDuplicate) dispswIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define dispswControlSerialization_Epilogue(pResource, pCallContext, pParams) dispswControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define dispswGetNotificationListPtr(pNotifier) dispswGetNotificationListPtr_DISPATCH(pNotifier) #define dispswGetNotificationShare(pNotifier) dispswGetNotificationShare_DISPATCH(pNotifier) #define dispswMap(pGpuResource, pCallContext, pParams, pCpuMapping) dispswMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define dispswGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) dispswGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) -static inline NV_STATUS dispswGetSwMethods_46f6a7(struct DispSwObject *pDispSw, METHOD **ppMethods, NvU32 *pNumMethods) { +static inline NV_STATUS dispswGetSwMethods_46f6a7(struct DispSwObject *pDispSw, const METHOD **ppMethods, NvU32 *pNumMethods) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS dispswGetSwMethods_DISPATCH(struct DispSwObject *pDispSw, METHOD **ppMethods, NvU32 *pNumMethods) { +static inline NV_STATUS dispswGetSwMethods_DISPATCH(struct DispSwObject *pDispSw, const METHOD **ppMethods, NvU32 *pNumMethods) { return pDispSw->__dispswGetSwMethods__(pDispSw, ppMethods, pNumMethods); } @@ -321,6 +325,10 @@ static inline NV_STATUS dispswUnregisterEvent_DISPATCH(struct DispSwObject *pNot return pNotifier->__dispswUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS dispswControlSerialization_Prologue_DISPATCH(struct DispSwObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__dispswControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool dispswCanCopy_DISPATCH(struct DispSwObject *pResource) { return pResource->__dispswCanCopy__(pResource); } @@ -333,6 +341,10 @@ static inline NV_STATUS dispswIsDuplicate_DISPATCH(struct DispSwObject *pResourc return pResource->__dispswIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void dispswControlSerialization_Epilogue_DISPATCH(struct DispSwObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__dispswControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *dispswGetNotificationListPtr_DISPATCH(struct DispSwObject *pNotifier) { return pNotifier->__dispswGetNotificationListPtr__(pNotifier); } diff --git a/src/nvidia/generated/g_eng_desc_nvoc.h b/src/nvidia/generated/g_eng_desc_nvoc.h index 074b22169..ddd1484f4 100644 --- a/src/nvidia/generated/g_eng_desc_nvoc.h +++ b/src/nvidia/generated/g_eng_desc_nvoc.h @@ -440,6 +440,18 @@ typedef struct KernelPerf KernelPerf; #endif /* __nvoc_class_id_KernelPerf */ +struct Pxuc; + +#ifndef __NVOC_CLASS_Pxuc_TYPEDEF__ +#define __NVOC_CLASS_Pxuc_TYPEDEF__ +typedef struct Pxuc Pxuc; +#endif /* __NVOC_CLASS_Pxuc_TYPEDEF__ */ + +#ifndef __nvoc_class_id_Pxuc +#define __nvoc_class_id_Pxuc 0xba06f5 +#endif /* __nvoc_class_id_Pxuc */ + + struct OBJBIF; #ifndef __NVOC_CLASS_OBJBIF_TYPEDEF__ @@ -1124,18 +1136,6 @@ typedef struct OBJNVJPG OBJNVJPG; #endif /* __nvoc_class_id_OBJNVJPG */ -struct OBJFAS; - -#ifndef __NVOC_CLASS_OBJFAS_TYPEDEF__ -#define __NVOC_CLASS_OBJFAS_TYPEDEF__ -typedef struct OBJFAS OBJFAS; -#endif /* __NVOC_CLASS_OBJFAS_TYPEDEF__ */ - -#ifndef __nvoc_class_id_OBJFAS -#define __nvoc_class_id_OBJFAS 0x4ddf48 -#endif /* __nvoc_class_id_OBJFAS */ - - struct OBJVMMU; #ifndef __NVOC_CLASS_OBJVMMU_TYPEDEF__ @@ -1268,16 +1268,16 @@ typedef struct OBJDISPMACRO OBJDISPMACRO; #endif /* __nvoc_class_id_OBJDISPMACRO */ -struct OBJNNE; +struct Nne; -#ifndef __NVOC_CLASS_OBJNNE_TYPEDEF__ -#define __NVOC_CLASS_OBJNNE_TYPEDEF__ -typedef struct OBJNNE OBJNNE; -#endif /* __NVOC_CLASS_OBJNNE_TYPEDEF__ */ +#ifndef __NVOC_CLASS_Nne_TYPEDEF__ +#define __NVOC_CLASS_Nne_TYPEDEF__ +typedef struct Nne Nne; +#endif /* __NVOC_CLASS_Nne_TYPEDEF__ */ -#ifndef __nvoc_class_id_OBJNNE -#define __nvoc_class_id_OBJNNE 0xc7f0f8 -#endif /* __nvoc_class_id_OBJNNE */ +#ifndef __nvoc_class_id_Nne +#define __nvoc_class_id_Nne 0x2487e2 +#endif /* __nvoc_class_id_Nne */ struct Smbpbi; @@ -1380,9 +1380,10 @@ typedef struct KernelCcu KernelCcu; #define ENG_INFOROM MKENGDESC(classId(OBJINFOROM), 0) #define ENG_PERF MKENGDESC(classId(Perf), 0) #define ENG_KERNEL_PERF MKENGDESC(classId(KernelPerf), 0) +#define ENG_PXUC MKENGDESC(classId(Pxuc), 0) #define ENG_BIF MKENGDESC(classId(OBJBIF), 0) #define ENG_KERNEL_BIF MKENGDESC(classId(KernelBif), 0) -#define ENG_HSHUBMANAGER MKENGDESC(classId(OBJHSHUBMANAGER)), 0) +#define ENG_HSHUBMANAGER MKENGDESC(classId(OBJHSHUBMANAGER), 0) #define ENG_SF MKENGDESC(classId(OBJSF), 0) #define ENG_GPIO MKENGDESC(classId(OBJGPIO), 0) #define ENG_CLK MKENGDESC(classId(ClockManager), 0) diff --git a/src/nvidia/generated/g_eng_state_nvoc.c b/src/nvidia/generated/g_eng_state_nvoc.c index 6ed668adb..1b8ae6583 100644 --- a/src/nvidia/generated/g_eng_state_nvoc.c +++ b/src/nvidia/generated/g_eng_state_nvoc.c @@ -117,18 +117,6 @@ static void __nvoc_init_funcTable_OBJENGSTATE_1(OBJENGSTATE *pThis) { pThis->__engstateStateDestroy__ = &engstateStateDestroy_IMPL; - pThis->__engstateAllocTunableState__ = &engstateAllocTunableState_IMPL; - - pThis->__engstateFreeTunableState__ = &engstateFreeTunableState_IMPL; - - pThis->__engstateGetTunableState__ = &engstateGetTunableState_IMPL; - - pThis->__engstateSetTunableState__ = &engstateSetTunableState_IMPL; - - pThis->__engstateReconcileTunableState__ = &engstateReconcileTunableState_IMPL; - - pThis->__engstateCompareTunableState__ = &engstateCompareTunableState_IMPL; - pThis->__engstateIsPresent__ = &engstateIsPresent_IMPL; } @@ -149,13 +137,16 @@ NV_STATUS __nvoc_objCreate_OBJENGSTATE(OBJENGSTATE **ppThis, Dynamic *pParent, N Object *pParentObj; OBJENGSTATE *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJENGSTATE)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJENGSTATE), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJENGSTATE)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJENGSTATE); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -171,11 +162,17 @@ NV_STATUS __nvoc_objCreate_OBJENGSTATE(OBJENGSTATE **ppThis, Dynamic *pParent, N if (status != NV_OK) goto __nvoc_objCreate_OBJENGSTATE_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJENGSTATE_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJENGSTATE)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_eng_state_nvoc.h b/src/nvidia/generated/g_eng_state_nvoc.h index d45b02903..09d1ba717 100644 --- a/src/nvidia/generated/g_eng_state_nvoc.h +++ b/src/nvidia/generated/g_eng_state_nvoc.h @@ -106,16 +106,9 @@ struct OBJENGSTATE { NV_STATUS (*__engstateStateUnload__)(POBJGPU, POBJENGSTATE, NvU32); NV_STATUS (*__engstateStatePostUnload__)(POBJGPU, POBJENGSTATE, NvU32); void (*__engstateStateDestroy__)(POBJGPU, POBJENGSTATE); - NV_STATUS (*__engstateAllocTunableState__)(POBJGPU, POBJENGSTATE, void **); - void (*__engstateFreeTunableState__)(POBJGPU, POBJENGSTATE, void *); - NV_STATUS (*__engstateGetTunableState__)(POBJGPU, POBJENGSTATE, void *); - NV_STATUS (*__engstateSetTunableState__)(POBJGPU, POBJENGSTATE, void *); - NV_STATUS (*__engstateReconcileTunableState__)(POBJGPU, POBJENGSTATE, void *); - NV_STATUS (*__engstateCompareTunableState__)(POBJGPU, POBJENGSTATE, void *, void *); NvBool (*__engstateIsPresent__)(POBJGPU, POBJENGSTATE); NvBool PDB_PROP_ENGSTATE_IS_MISSING; ENGDESCRIPTOR engDesc; - void *pOriginalTunableState; struct OBJGPU *pGpu; ENGSTATE_STATE currentState; ENGSTATE_STATS stats[11]; @@ -165,12 +158,6 @@ NV_STATUS __nvoc_objCreate_OBJENGSTATE(OBJENGSTATE**, Dynamic*, NvU32); #define engstateStateUnload(pGpu, pEngstate, arg0) engstateStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define engstateStatePostUnload(pGpu, pEngstate, arg0) engstateStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) #define engstateStateDestroy(pGpu, pEngstate) engstateStateDestroy_DISPATCH(pGpu, pEngstate) -#define engstateAllocTunableState(pGpu, pEngstate, ppTunableState) engstateAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define engstateFreeTunableState(pGpu, pEngstate, pTunableState) engstateFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define engstateGetTunableState(pGpu, pEngstate, pTunableState) engstateGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define engstateSetTunableState(pGpu, pEngstate, pTunableState) engstateSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define engstateReconcileTunableState(pGpu, pEngstate, pTunableState) engstateReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define engstateCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) engstateCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) #define engstateIsPresent(pGpu, pEngstate) engstateIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS engstateConstructEngine_IMPL(POBJGPU pGpu, POBJENGSTATE pEngstate, ENGDESCRIPTOR arg0); @@ -250,42 +237,6 @@ static inline void engstateStateDestroy_DISPATCH(POBJGPU pGpu, POBJENGSTATE pEng pEngstate->__engstateStateDestroy__(pGpu, pEngstate); } -NV_STATUS engstateAllocTunableState_IMPL(POBJGPU pGpu, POBJENGSTATE pEngstate, void **ppTunableState); - -static inline NV_STATUS engstateAllocTunableState_DISPATCH(POBJGPU pGpu, POBJENGSTATE pEngstate, void **ppTunableState) { - return pEngstate->__engstateAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -void engstateFreeTunableState_IMPL(POBJGPU pGpu, POBJENGSTATE pEngstate, void *pTunableState); - -static inline void engstateFreeTunableState_DISPATCH(POBJGPU pGpu, POBJENGSTATE pEngstate, void *pTunableState) { - pEngstate->__engstateFreeTunableState__(pGpu, pEngstate, pTunableState); -} - -NV_STATUS engstateGetTunableState_IMPL(POBJGPU pGpu, POBJENGSTATE pEngstate, void *pTunableState); - -static inline NV_STATUS engstateGetTunableState_DISPATCH(POBJGPU pGpu, POBJENGSTATE pEngstate, void *pTunableState) { - return pEngstate->__engstateGetTunableState__(pGpu, pEngstate, pTunableState); -} - -NV_STATUS engstateSetTunableState_IMPL(POBJGPU pGpu, POBJENGSTATE pEngstate, void *pTunableState); - -static inline NV_STATUS engstateSetTunableState_DISPATCH(POBJGPU pGpu, POBJENGSTATE pEngstate, void *pTunableState) { - return pEngstate->__engstateSetTunableState__(pGpu, pEngstate, pTunableState); -} - -NV_STATUS engstateReconcileTunableState_IMPL(POBJGPU pGpu, POBJENGSTATE pEngstate, void *pTunableState); - -static inline NV_STATUS engstateReconcileTunableState_DISPATCH(POBJGPU pGpu, POBJENGSTATE pEngstate, void *pTunableState) { - return pEngstate->__engstateReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - -NV_STATUS engstateCompareTunableState_IMPL(POBJGPU pGpu, POBJENGSTATE pEngstate, void *pTunables1, void *pTunables2); - -static inline NV_STATUS engstateCompareTunableState_DISPATCH(POBJGPU pGpu, POBJENGSTATE pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__engstateCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - NvBool engstateIsPresent_IMPL(POBJGPU pGpu, POBJENGSTATE pEngstate); static inline NvBool engstateIsPresent_DISPATCH(POBJGPU pGpu, POBJENGSTATE pEngstate) { diff --git a/src/nvidia/generated/g_event_buffer_nvoc.c b/src/nvidia/generated/g_event_buffer_nvoc.c index 398e706f6..61083ee54 100644 --- a/src/nvidia/generated/g_event_buffer_nvoc.c +++ b/src/nvidia/generated/g_event_buffer_nvoc.c @@ -116,8 +116,12 @@ static void __nvoc_thunk_RsResource_eventbufferAddAdditionalDependants(struct Rs resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_eventbufferUnmap(struct EventBuffer *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RsResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_eventbufferUnmapFrom(struct EventBuffer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_eventbufferControlSerialization_Prologue(struct EventBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_RmResource_eventbufferControl_Prologue(struct EventBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -128,22 +132,26 @@ static NvBool __nvoc_thunk_RsResource_eventbufferCanCopy(struct EventBuffer *pRe return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_eventbufferMapTo(struct EventBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_eventbufferUnmap(struct EventBuffer *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RsResource.offset), pCallContext, pCpuMapping); } static void __nvoc_thunk_RsResource_eventbufferPreDestruct(struct EventBuffer *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_eventbufferUnmapFrom(struct EventBuffer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_eventbufferMapTo(struct EventBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_RsResource_eventbufferIsDuplicate(struct EventBuffer *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_eventbufferControlSerialization_Epilogue(struct EventBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RmResource.offset), pCallContext, pParams); +} + static void __nvoc_thunk_RmResource_eventbufferControl_Epilogue(struct EventBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RmResource.offset), pCallContext, pParams); } @@ -300,20 +308,24 @@ static void __nvoc_init_funcTable_EventBuffer_1(EventBuffer *pThis) { pThis->__eventbufferAddAdditionalDependants__ = &__nvoc_thunk_RsResource_eventbufferAddAdditionalDependants; - pThis->__eventbufferUnmap__ = &__nvoc_thunk_RsResource_eventbufferUnmap; + pThis->__eventbufferUnmapFrom__ = &__nvoc_thunk_RsResource_eventbufferUnmapFrom; + + pThis->__eventbufferControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_eventbufferControlSerialization_Prologue; pThis->__eventbufferControl_Prologue__ = &__nvoc_thunk_RmResource_eventbufferControl_Prologue; pThis->__eventbufferCanCopy__ = &__nvoc_thunk_RsResource_eventbufferCanCopy; - pThis->__eventbufferMapTo__ = &__nvoc_thunk_RsResource_eventbufferMapTo; + pThis->__eventbufferUnmap__ = &__nvoc_thunk_RsResource_eventbufferUnmap; pThis->__eventbufferPreDestruct__ = &__nvoc_thunk_RsResource_eventbufferPreDestruct; - pThis->__eventbufferUnmapFrom__ = &__nvoc_thunk_RsResource_eventbufferUnmapFrom; + pThis->__eventbufferMapTo__ = &__nvoc_thunk_RsResource_eventbufferMapTo; pThis->__eventbufferIsDuplicate__ = &__nvoc_thunk_RsResource_eventbufferIsDuplicate; + pThis->__eventbufferControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_eventbufferControlSerialization_Epilogue; + pThis->__eventbufferControl_Epilogue__ = &__nvoc_thunk_RmResource_eventbufferControl_Epilogue; pThis->__eventbufferControlLookup__ = &__nvoc_thunk_RsResource_eventbufferControlLookup; @@ -343,13 +355,16 @@ NV_STATUS __nvoc_objCreate_EventBuffer(EventBuffer **ppThis, Dynamic *pParent, N Object *pParentObj; EventBuffer *pThis; - pThis = portMemAllocNonPaged(sizeof(EventBuffer)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(EventBuffer), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(EventBuffer)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_EventBuffer); + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -365,11 +380,17 @@ NV_STATUS __nvoc_objCreate_EventBuffer(EventBuffer **ppThis, Dynamic *pParent, N if (status != NV_OK) goto __nvoc_objCreate_EventBuffer_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_EventBuffer_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(EventBuffer)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_event_buffer_nvoc.h b/src/nvidia/generated/g_event_buffer_nvoc.h index 8a0549319..b82b39824 100644 --- a/src/nvidia/generated/g_event_buffer_nvoc.h +++ b/src/nvidia/generated/g_event_buffer_nvoc.h @@ -93,13 +93,15 @@ struct EventBuffer { NvU32 (*__eventbufferGetRefCount__)(struct EventBuffer *); NV_STATUS (*__eventbufferControlFilter__)(struct EventBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__eventbufferAddAdditionalDependants__)(struct RsClient *, struct EventBuffer *, RsResourceRef *); - NV_STATUS (*__eventbufferUnmap__)(struct EventBuffer *, struct CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__eventbufferUnmapFrom__)(struct EventBuffer *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__eventbufferControlSerialization_Prologue__)(struct EventBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__eventbufferControl_Prologue__)(struct EventBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__eventbufferCanCopy__)(struct EventBuffer *); - NV_STATUS (*__eventbufferMapTo__)(struct EventBuffer *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__eventbufferUnmap__)(struct EventBuffer *, struct CALL_CONTEXT *, RsCpuMapping *); void (*__eventbufferPreDestruct__)(struct EventBuffer *); - NV_STATUS (*__eventbufferUnmapFrom__)(struct EventBuffer *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__eventbufferMapTo__)(struct EventBuffer *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__eventbufferIsDuplicate__)(struct EventBuffer *, NvHandle, NvBool *); + void (*__eventbufferControlSerialization_Epilogue__)(struct EventBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__eventbufferControl_Epilogue__)(struct EventBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__eventbufferControlLookup__)(struct EventBuffer *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__eventbufferMap__)(struct EventBuffer *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -166,13 +168,15 @@ NV_STATUS __nvoc_objCreate_EventBuffer(EventBuffer**, Dynamic*, NvU32, struct CA #define eventbufferGetRefCount(pResource) eventbufferGetRefCount_DISPATCH(pResource) #define eventbufferControlFilter(pResource, pCallContext, pParams) eventbufferControlFilter_DISPATCH(pResource, pCallContext, pParams) #define eventbufferAddAdditionalDependants(pClient, pResource, pReference) eventbufferAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define eventbufferUnmap(pResource, pCallContext, pCpuMapping) eventbufferUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define eventbufferUnmapFrom(pResource, pParams) eventbufferUnmapFrom_DISPATCH(pResource, pParams) +#define eventbufferControlSerialization_Prologue(pResource, pCallContext, pParams) eventbufferControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define eventbufferControl_Prologue(pResource, pCallContext, pParams) eventbufferControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define eventbufferCanCopy(pResource) eventbufferCanCopy_DISPATCH(pResource) -#define eventbufferMapTo(pResource, pParams) eventbufferMapTo_DISPATCH(pResource, pParams) +#define eventbufferUnmap(pResource, pCallContext, pCpuMapping) eventbufferUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define eventbufferPreDestruct(pResource) eventbufferPreDestruct_DISPATCH(pResource) -#define eventbufferUnmapFrom(pResource, pParams) eventbufferUnmapFrom_DISPATCH(pResource, pParams) +#define eventbufferMapTo(pResource, pParams) eventbufferMapTo_DISPATCH(pResource, pParams) #define eventbufferIsDuplicate(pResource, hMemory, pDuplicate) eventbufferIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define eventbufferControlSerialization_Epilogue(pResource, pCallContext, pParams) eventbufferControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define eventbufferControl_Epilogue(pResource, pCallContext, pParams) eventbufferControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define eventbufferControlLookup(pResource, pParams, ppEntry) eventbufferControlLookup_DISPATCH(pResource, pParams, ppEntry) #define eventbufferMap(pResource, pCallContext, pParams, pCpuMapping) eventbufferMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -233,8 +237,12 @@ static inline void eventbufferAddAdditionalDependants_DISPATCH(struct RsClient * pResource->__eventbufferAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS eventbufferUnmap_DISPATCH(struct EventBuffer *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pResource->__eventbufferUnmap__(pResource, pCallContext, pCpuMapping); +static inline NV_STATUS eventbufferUnmapFrom_DISPATCH(struct EventBuffer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__eventbufferUnmapFrom__(pResource, pParams); +} + +static inline NV_STATUS eventbufferControlSerialization_Prologue_DISPATCH(struct EventBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__eventbufferControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS eventbufferControl_Prologue_DISPATCH(struct EventBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -245,22 +253,26 @@ static inline NvBool eventbufferCanCopy_DISPATCH(struct EventBuffer *pResource) return pResource->__eventbufferCanCopy__(pResource); } -static inline NV_STATUS eventbufferMapTo_DISPATCH(struct EventBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__eventbufferMapTo__(pResource, pParams); +static inline NV_STATUS eventbufferUnmap_DISPATCH(struct EventBuffer *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__eventbufferUnmap__(pResource, pCallContext, pCpuMapping); } static inline void eventbufferPreDestruct_DISPATCH(struct EventBuffer *pResource) { pResource->__eventbufferPreDestruct__(pResource); } -static inline NV_STATUS eventbufferUnmapFrom_DISPATCH(struct EventBuffer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__eventbufferUnmapFrom__(pResource, pParams); +static inline NV_STATUS eventbufferMapTo_DISPATCH(struct EventBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__eventbufferMapTo__(pResource, pParams); } static inline NV_STATUS eventbufferIsDuplicate_DISPATCH(struct EventBuffer *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__eventbufferIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void eventbufferControlSerialization_Epilogue_DISPATCH(struct EventBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__eventbufferControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline void eventbufferControl_Epilogue_DISPATCH(struct EventBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__eventbufferControl_Epilogue__(pResource, pCallContext, pParams); } diff --git a/src/nvidia/generated/g_event_nvoc.c b/src/nvidia/generated/g_event_nvoc.c index d2b8d9e02..8f61342e2 100644 --- a/src/nvidia/generated/g_event_nvoc.c +++ b/src/nvidia/generated/g_event_nvoc.c @@ -124,13 +124,16 @@ NV_STATUS __nvoc_objCreate_NotifShare(NotifShare **ppThis, Dynamic *pParent, NvU Object *pParentObj; NotifShare *pThis; - pThis = portMemAllocNonPaged(sizeof(NotifShare)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(NotifShare), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(NotifShare)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_NotifShare); + pThis->__nvoc_base_RsShared.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -146,11 +149,17 @@ NV_STATUS __nvoc_objCreate_NotifShare(NotifShare **ppThis, Dynamic *pParent, NvU if (status != NV_OK) goto __nvoc_objCreate_NotifShare_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_NotifShare_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(NotifShare)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -271,8 +280,12 @@ static void __nvoc_thunk_RsResource_eventAddAdditionalDependants(struct RsClient resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_eventUnmap(struct Event *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RsResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_eventUnmapFrom(struct Event *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_eventControlSerialization_Prologue(struct Event *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_RmResource_eventControl_Prologue(struct Event *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -283,22 +296,26 @@ static NvBool __nvoc_thunk_RsResource_eventCanCopy(struct Event *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_eventMapTo(struct Event *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_eventUnmap(struct Event *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RsResource.offset), pCallContext, pCpuMapping); } static void __nvoc_thunk_RsResource_eventPreDestruct(struct Event *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_eventUnmapFrom(struct Event *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_eventMapTo(struct Event *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_RsResource_eventIsDuplicate(struct Event *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_eventControlSerialization_Epilogue(struct Event *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RmResource.offset), pCallContext, pParams); +} + static void __nvoc_thunk_RmResource_eventControl_Epilogue(struct Event *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RmResource.offset), pCallContext, pParams); } @@ -370,20 +387,24 @@ static void __nvoc_init_funcTable_Event_1(Event *pThis) { pThis->__eventAddAdditionalDependants__ = &__nvoc_thunk_RsResource_eventAddAdditionalDependants; - pThis->__eventUnmap__ = &__nvoc_thunk_RsResource_eventUnmap; + pThis->__eventUnmapFrom__ = &__nvoc_thunk_RsResource_eventUnmapFrom; + + pThis->__eventControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_eventControlSerialization_Prologue; pThis->__eventControl_Prologue__ = &__nvoc_thunk_RmResource_eventControl_Prologue; pThis->__eventCanCopy__ = &__nvoc_thunk_RsResource_eventCanCopy; - pThis->__eventMapTo__ = &__nvoc_thunk_RsResource_eventMapTo; + pThis->__eventUnmap__ = &__nvoc_thunk_RsResource_eventUnmap; pThis->__eventPreDestruct__ = &__nvoc_thunk_RsResource_eventPreDestruct; - pThis->__eventUnmapFrom__ = &__nvoc_thunk_RsResource_eventUnmapFrom; + pThis->__eventMapTo__ = &__nvoc_thunk_RsResource_eventMapTo; pThis->__eventIsDuplicate__ = &__nvoc_thunk_RsResource_eventIsDuplicate; + pThis->__eventControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_eventControlSerialization_Epilogue; + pThis->__eventControl_Epilogue__ = &__nvoc_thunk_RmResource_eventControl_Epilogue; pThis->__eventControlLookup__ = &__nvoc_thunk_RsResource_eventControlLookup; @@ -413,13 +434,16 @@ NV_STATUS __nvoc_objCreate_Event(Event **ppThis, Dynamic *pParent, NvU32 createF Object *pParentObj; Event *pThis; - pThis = portMemAllocNonPaged(sizeof(Event)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Event), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(Event)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Event); + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -435,11 +459,17 @@ NV_STATUS __nvoc_objCreate_Event(Event **ppThis, Dynamic *pParent, NvU32 createF if (status != NV_OK) goto __nvoc_objCreate_Event_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_Event_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(Event)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_event_nvoc.h b/src/nvidia/generated/g_event_nvoc.h index 2b05ff42b..830f5b92d 100644 --- a/src/nvidia/generated/g_event_nvoc.h +++ b/src/nvidia/generated/g_event_nvoc.h @@ -179,13 +179,15 @@ struct Event { NvU32 (*__eventGetRefCount__)(struct Event *); NV_STATUS (*__eventControlFilter__)(struct Event *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__eventAddAdditionalDependants__)(struct RsClient *, struct Event *, RsResourceRef *); - NV_STATUS (*__eventUnmap__)(struct Event *, struct CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__eventUnmapFrom__)(struct Event *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__eventControlSerialization_Prologue__)(struct Event *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__eventControl_Prologue__)(struct Event *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__eventCanCopy__)(struct Event *); - NV_STATUS (*__eventMapTo__)(struct Event *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__eventUnmap__)(struct Event *, struct CALL_CONTEXT *, RsCpuMapping *); void (*__eventPreDestruct__)(struct Event *); - NV_STATUS (*__eventUnmapFrom__)(struct Event *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__eventMapTo__)(struct Event *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__eventIsDuplicate__)(struct Event *, NvHandle, NvBool *); + void (*__eventControlSerialization_Epilogue__)(struct Event *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__eventControl_Epilogue__)(struct Event *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__eventControlLookup__)(struct Event *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__eventMap__)(struct Event *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -232,13 +234,15 @@ NV_STATUS __nvoc_objCreate_Event(Event**, Dynamic*, NvU32, struct CALL_CONTEXT * #define eventGetRefCount(pResource) eventGetRefCount_DISPATCH(pResource) #define eventControlFilter(pResource, pCallContext, pParams) eventControlFilter_DISPATCH(pResource, pCallContext, pParams) #define eventAddAdditionalDependants(pClient, pResource, pReference) eventAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define eventUnmap(pResource, pCallContext, pCpuMapping) eventUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define eventUnmapFrom(pResource, pParams) eventUnmapFrom_DISPATCH(pResource, pParams) +#define eventControlSerialization_Prologue(pResource, pCallContext, pParams) eventControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define eventControl_Prologue(pResource, pCallContext, pParams) eventControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define eventCanCopy(pResource) eventCanCopy_DISPATCH(pResource) -#define eventMapTo(pResource, pParams) eventMapTo_DISPATCH(pResource, pParams) +#define eventUnmap(pResource, pCallContext, pCpuMapping) eventUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define eventPreDestruct(pResource) eventPreDestruct_DISPATCH(pResource) -#define eventUnmapFrom(pResource, pParams) eventUnmapFrom_DISPATCH(pResource, pParams) +#define eventMapTo(pResource, pParams) eventMapTo_DISPATCH(pResource, pParams) #define eventIsDuplicate(pResource, hMemory, pDuplicate) eventIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define eventControlSerialization_Epilogue(pResource, pCallContext, pParams) eventControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define eventControl_Epilogue(pResource, pCallContext, pParams) eventControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define eventControlLookup(pResource, pParams, ppEntry) eventControlLookup_DISPATCH(pResource, pParams, ppEntry) #define eventMap(pResource, pCallContext, pParams, pCpuMapping) eventMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -275,8 +279,12 @@ static inline void eventAddAdditionalDependants_DISPATCH(struct RsClient *pClien pResource->__eventAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS eventUnmap_DISPATCH(struct Event *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pResource->__eventUnmap__(pResource, pCallContext, pCpuMapping); +static inline NV_STATUS eventUnmapFrom_DISPATCH(struct Event *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__eventUnmapFrom__(pResource, pParams); +} + +static inline NV_STATUS eventControlSerialization_Prologue_DISPATCH(struct Event *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__eventControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS eventControl_Prologue_DISPATCH(struct Event *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -287,22 +295,26 @@ static inline NvBool eventCanCopy_DISPATCH(struct Event *pResource) { return pResource->__eventCanCopy__(pResource); } -static inline NV_STATUS eventMapTo_DISPATCH(struct Event *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__eventMapTo__(pResource, pParams); +static inline NV_STATUS eventUnmap_DISPATCH(struct Event *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__eventUnmap__(pResource, pCallContext, pCpuMapping); } static inline void eventPreDestruct_DISPATCH(struct Event *pResource) { pResource->__eventPreDestruct__(pResource); } -static inline NV_STATUS eventUnmapFrom_DISPATCH(struct Event *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__eventUnmapFrom__(pResource, pParams); +static inline NV_STATUS eventMapTo_DISPATCH(struct Event *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__eventMapTo__(pResource, pParams); } static inline NV_STATUS eventIsDuplicate_DISPATCH(struct Event *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__eventIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void eventControlSerialization_Epilogue_DISPATCH(struct Event *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__eventControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline void eventControl_Epilogue_DISPATCH(struct Event *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__eventControl_Epilogue__(pResource, pCallContext, pParams); } diff --git a/src/nvidia/generated/g_fabric_nvoc.c b/src/nvidia/generated/g_fabric_nvoc.c index 45f8bfa81..f41c01dd1 100644 --- a/src/nvidia/generated/g_fabric_nvoc.c +++ b/src/nvidia/generated/g_fabric_nvoc.c @@ -114,13 +114,16 @@ NV_STATUS __nvoc_objCreate_Fabric(Fabric **ppThis, Dynamic *pParent, NvU32 creat Object *pParentObj; Fabric *pThis; - pThis = portMemAllocNonPaged(sizeof(Fabric)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Fabric), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(Fabric)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Fabric); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -136,11 +139,17 @@ NV_STATUS __nvoc_objCreate_Fabric(Fabric **ppThis, Dynamic *pParent, NvU32 creat if (status != NV_OK) goto __nvoc_objCreate_Fabric_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_Fabric_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(Fabric)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_fabric_vaspace_nvoc.c b/src/nvidia/generated/g_fabric_vaspace_nvoc.c index a83ca6905..ee1e4a19e 100644 --- a/src/nvidia/generated/g_fabric_vaspace_nvoc.c +++ b/src/nvidia/generated/g_fabric_vaspace_nvoc.c @@ -146,7 +146,7 @@ static PMEMORY_DESCRIPTOR __nvoc_thunk_OBJVASPACE_fabricvaspaceGetKernelPageDirB return vaspaceGetKernelPageDirBase((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_FABRIC_VASPACE_OBJVASPACE.offset), pGpu); } -static NvU32 __nvoc_thunk_OBJVASPACE_fabricvaspaceGetMapPageSize(struct FABRIC_VASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { +static NvU64 __nvoc_thunk_OBJVASPACE_fabricvaspaceGetMapPageSize(struct FABRIC_VASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { return vaspaceGetMapPageSize((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_FABRIC_VASPACE_OBJVASPACE.offset), pGpu, pMemBlock); } @@ -319,13 +319,16 @@ NV_STATUS __nvoc_objCreate_FABRIC_VASPACE(FABRIC_VASPACE **ppThis, Dynamic *pPar Object *pParentObj; FABRIC_VASPACE *pThis; - pThis = portMemAllocNonPaged(sizeof(FABRIC_VASPACE)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(FABRIC_VASPACE), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(FABRIC_VASPACE)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_FABRIC_VASPACE); + pThis->__nvoc_base_OBJVASPACE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -341,11 +344,17 @@ NV_STATUS __nvoc_objCreate_FABRIC_VASPACE(FABRIC_VASPACE **ppThis, Dynamic *pPar if (status != NV_OK) goto __nvoc_objCreate_FABRIC_VASPACE_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_FABRIC_VASPACE_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(FABRIC_VASPACE)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_fabric_vaspace_nvoc.h b/src/nvidia/generated/g_fabric_vaspace_nvoc.h index d1001ea2e..926df7dbd 100644 --- a/src/nvidia/generated/g_fabric_vaspace_nvoc.h +++ b/src/nvidia/generated/g_fabric_vaspace_nvoc.h @@ -97,7 +97,7 @@ struct FABRIC_VASPACE { NvU64 (*__fabricvaspaceGetVaLimit__)(struct FABRIC_VASPACE *); PMEMORY_DESCRIPTOR (*__fabricvaspaceGetPageDirBase__)(struct FABRIC_VASPACE *, struct OBJGPU *); PMEMORY_DESCRIPTOR (*__fabricvaspaceGetKernelPageDirBase__)(struct FABRIC_VASPACE *, struct OBJGPU *); - NvU32 (*__fabricvaspaceGetMapPageSize__)(struct FABRIC_VASPACE *, struct OBJGPU *, EMEMBLOCK *); + NvU64 (*__fabricvaspaceGetMapPageSize__)(struct FABRIC_VASPACE *, struct OBJGPU *, EMEMBLOCK *); struct OBJEHEAP *(*__fabricvaspaceGetHeap__)(struct FABRIC_VASPACE *); NvBool (*__fabricvaspaceIsFaultCapable__)(struct FABRIC_VASPACE *); NvU64 (*__fabricvaspaceGetVaStart__)(struct FABRIC_VASPACE *); @@ -278,7 +278,7 @@ static inline PMEMORY_DESCRIPTOR fabricvaspaceGetKernelPageDirBase_DISPATCH(stru return pVAS->__fabricvaspaceGetKernelPageDirBase__(pVAS, pGpu); } -static inline NvU32 fabricvaspaceGetMapPageSize_DISPATCH(struct FABRIC_VASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { +static inline NvU64 fabricvaspaceGetMapPageSize_DISPATCH(struct FABRIC_VASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { return pVAS->__fabricvaspaceGetMapPageSize__(pVAS, pGpu, pMemBlock); } diff --git a/src/nvidia/generated/g_fbsr_nvoc.c b/src/nvidia/generated/g_fbsr_nvoc.c index a65aa9d33..cdc63a610 100644 --- a/src/nvidia/generated/g_fbsr_nvoc.c +++ b/src/nvidia/generated/g_fbsr_nvoc.c @@ -153,13 +153,16 @@ NV_STATUS __nvoc_objCreate_OBJFBSR(OBJFBSR **ppThis, Dynamic *pParent, NvU32 cre OBJFBSR *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(OBJFBSR)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJFBSR), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJFBSR)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJFBSR); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -179,11 +182,17 @@ NV_STATUS __nvoc_objCreate_OBJFBSR(OBJFBSR **ppThis, Dynamic *pParent, NvU32 cre if (status != NV_OK) goto __nvoc_objCreate_OBJFBSR_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJFBSR_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJFBSR)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_fla_mem_nvoc.c b/src/nvidia/generated/g_fla_mem_nvoc.c index 7f7c8e4ab..268fa7b90 100644 --- a/src/nvidia/generated/g_fla_mem_nvoc.c +++ b/src/nvidia/generated/g_fla_mem_nvoc.c @@ -101,6 +101,46 @@ static NV_STATUS __nvoc_thunk_Memory_flamemCheckMemInterUnmap(struct FlaMemory * return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), bSubdeviceHandleProvided); } +static NvBool __nvoc_thunk_RmResource_flamemShareCallback(struct FlaMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RsResource_flamemMapTo(struct FlaMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_flamemGetMapAddrSpace(struct FlaMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_flamemGetRefCount(struct FlaMemory *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_flamemAddAdditionalDependants(struct RsClient *pClient, struct FlaMemory *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_flamemControl_Prologue(struct FlaMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_Memory_flamemIsGpuMapAllowed(struct FlaMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), pGpu); +} + +static NV_STATUS __nvoc_thunk_RsResource_flamemUnmapFrom(struct FlaMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_flamemControl_Epilogue(struct FlaMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_flamemControlLookup(struct FlaMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RsResource.offset), pParams, ppEntry); +} + static NV_STATUS __nvoc_thunk_Memory_flamemControl(struct FlaMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), pCallContext, pParams); } @@ -117,36 +157,12 @@ static NV_STATUS __nvoc_thunk_Memory_flamemGetMemoryMappingDescriptor(struct Fla return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_Memory_flamemGetMapAddrSpace(struct FlaMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvBool __nvoc_thunk_RmResource_flamemShareCallback(struct FlaMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); -} - static NV_STATUS __nvoc_thunk_RsResource_flamemControlFilter(struct FlaMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_flamemAddAdditionalDependants(struct RsClient *pClient, struct FlaMemory *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_flamemGetRefCount(struct FlaMemory *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RsResource_flamemMapTo(struct FlaMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_flamemControl_Prologue(struct FlaMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RmResource.offset), pCallContext, pParams); -} - -static NvBool __nvoc_thunk_Memory_flamemIsGpuMapAllowed(struct FlaMemory *pMemory, struct OBJGPU *pGpu) { - return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), pGpu); +static NV_STATUS __nvoc_thunk_RmResource_flamemControlSerialization_Prologue(struct FlaMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_flamemIsReady(struct FlaMemory *pMemory, NvBool bCopyConstructorContext) { @@ -165,16 +181,8 @@ static NV_STATUS __nvoc_thunk_Memory_flamemIsDuplicate(struct FlaMemory *pMemory return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), hMemory, pDuplicate); } -static NV_STATUS __nvoc_thunk_RsResource_flamemUnmapFrom(struct FlaMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RmResource_flamemControl_Epilogue(struct FlaMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_flamemControlLookup(struct FlaMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_flamemControlSerialization_Epilogue(struct FlaMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_flamemMap(struct FlaMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -232,6 +240,26 @@ static void __nvoc_init_funcTable_FlaMemory_1(FlaMemory *pThis) { pThis->__flamemCheckMemInterUnmap__ = &__nvoc_thunk_Memory_flamemCheckMemInterUnmap; + pThis->__flamemShareCallback__ = &__nvoc_thunk_RmResource_flamemShareCallback; + + pThis->__flamemMapTo__ = &__nvoc_thunk_RsResource_flamemMapTo; + + pThis->__flamemGetMapAddrSpace__ = &__nvoc_thunk_Memory_flamemGetMapAddrSpace; + + pThis->__flamemGetRefCount__ = &__nvoc_thunk_RsResource_flamemGetRefCount; + + pThis->__flamemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_flamemAddAdditionalDependants; + + pThis->__flamemControl_Prologue__ = &__nvoc_thunk_RmResource_flamemControl_Prologue; + + pThis->__flamemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_flamemIsGpuMapAllowed; + + pThis->__flamemUnmapFrom__ = &__nvoc_thunk_RsResource_flamemUnmapFrom; + + pThis->__flamemControl_Epilogue__ = &__nvoc_thunk_RmResource_flamemControl_Epilogue; + + pThis->__flamemControlLookup__ = &__nvoc_thunk_RsResource_flamemControlLookup; + pThis->__flamemControl__ = &__nvoc_thunk_Memory_flamemControl; pThis->__flamemUnmap__ = &__nvoc_thunk_Memory_flamemUnmap; @@ -240,21 +268,9 @@ static void __nvoc_init_funcTable_FlaMemory_1(FlaMemory *pThis) { pThis->__flamemGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_flamemGetMemoryMappingDescriptor; - pThis->__flamemGetMapAddrSpace__ = &__nvoc_thunk_Memory_flamemGetMapAddrSpace; - - pThis->__flamemShareCallback__ = &__nvoc_thunk_RmResource_flamemShareCallback; - pThis->__flamemControlFilter__ = &__nvoc_thunk_RsResource_flamemControlFilter; - pThis->__flamemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_flamemAddAdditionalDependants; - - pThis->__flamemGetRefCount__ = &__nvoc_thunk_RsResource_flamemGetRefCount; - - pThis->__flamemMapTo__ = &__nvoc_thunk_RsResource_flamemMapTo; - - pThis->__flamemControl_Prologue__ = &__nvoc_thunk_RmResource_flamemControl_Prologue; - - pThis->__flamemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_flamemIsGpuMapAllowed; + pThis->__flamemControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_flamemControlSerialization_Prologue; pThis->__flamemIsReady__ = &__nvoc_thunk_Memory_flamemIsReady; @@ -264,11 +280,7 @@ static void __nvoc_init_funcTable_FlaMemory_1(FlaMemory *pThis) { pThis->__flamemIsDuplicate__ = &__nvoc_thunk_Memory_flamemIsDuplicate; - pThis->__flamemUnmapFrom__ = &__nvoc_thunk_RsResource_flamemUnmapFrom; - - pThis->__flamemControl_Epilogue__ = &__nvoc_thunk_RmResource_flamemControl_Epilogue; - - pThis->__flamemControlLookup__ = &__nvoc_thunk_RsResource_flamemControlLookup; + pThis->__flamemControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_flamemControlSerialization_Epilogue; pThis->__flamemMap__ = &__nvoc_thunk_Memory_flamemMap; @@ -296,13 +308,16 @@ NV_STATUS __nvoc_objCreate_FlaMemory(FlaMemory **ppThis, Dynamic *pParent, NvU32 Object *pParentObj; FlaMemory *pThis; - pThis = portMemAllocNonPaged(sizeof(FlaMemory)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(FlaMemory), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(FlaMemory)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_FlaMemory); + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -318,11 +333,17 @@ NV_STATUS __nvoc_objCreate_FlaMemory(FlaMemory **ppThis, Dynamic *pParent, NvU32 if (status != NV_OK) goto __nvoc_objCreate_FlaMemory_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_FlaMemory_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(FlaMemory)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_fla_mem_nvoc.h b/src/nvidia/generated/g_fla_mem_nvoc.h index 7bbf2d28f..88ec60e82 100644 --- a/src/nvidia/generated/g_fla_mem_nvoc.h +++ b/src/nvidia/generated/g_fla_mem_nvoc.h @@ -56,25 +56,27 @@ struct FlaMemory { NvBool (*__flamemCanCopy__)(struct FlaMemory *); NV_STATUS (*__flamemCopyConstruct__)(struct FlaMemory *, CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); NV_STATUS (*__flamemCheckMemInterUnmap__)(struct FlaMemory *, NvBool); + NvBool (*__flamemShareCallback__)(struct FlaMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__flamemMapTo__)(struct FlaMemory *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__flamemGetMapAddrSpace__)(struct FlaMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__flamemGetRefCount__)(struct FlaMemory *); + void (*__flamemAddAdditionalDependants__)(struct RsClient *, struct FlaMemory *, RsResourceRef *); + NV_STATUS (*__flamemControl_Prologue__)(struct FlaMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__flamemIsGpuMapAllowed__)(struct FlaMemory *, struct OBJGPU *); + NV_STATUS (*__flamemUnmapFrom__)(struct FlaMemory *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__flamemControl_Epilogue__)(struct FlaMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__flamemControlLookup__)(struct FlaMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__flamemControl__)(struct FlaMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__flamemUnmap__)(struct FlaMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__flamemGetMemInterMapParams__)(struct FlaMemory *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__flamemGetMemoryMappingDescriptor__)(struct FlaMemory *, MEMORY_DESCRIPTOR **); - NV_STATUS (*__flamemGetMapAddrSpace__)(struct FlaMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvBool (*__flamemShareCallback__)(struct FlaMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__flamemControlFilter__)(struct FlaMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__flamemAddAdditionalDependants__)(struct RsClient *, struct FlaMemory *, RsResourceRef *); - NvU32 (*__flamemGetRefCount__)(struct FlaMemory *); - NV_STATUS (*__flamemMapTo__)(struct FlaMemory *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__flamemControl_Prologue__)(struct FlaMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvBool (*__flamemIsGpuMapAllowed__)(struct FlaMemory *, struct OBJGPU *); + NV_STATUS (*__flamemControlSerialization_Prologue__)(struct FlaMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__flamemIsReady__)(struct FlaMemory *, NvBool); NV_STATUS (*__flamemCheckCopyPermissions__)(struct FlaMemory *, struct OBJGPU *, NvHandle); void (*__flamemPreDestruct__)(struct FlaMemory *); NV_STATUS (*__flamemIsDuplicate__)(struct FlaMemory *, NvHandle, NvBool *); - NV_STATUS (*__flamemUnmapFrom__)(struct FlaMemory *, RS_RES_UNMAP_FROM_PARAMS *); - void (*__flamemControl_Epilogue__)(struct FlaMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__flamemControlLookup__)(struct FlaMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__flamemControlSerialization_Epilogue__)(struct FlaMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__flamemMap__)(struct FlaMemory *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__flamemAccessCallback__)(struct FlaMemory *, struct RsClient *, void *, RsAccessRight); NvU32 peerDeviceInst; @@ -113,25 +115,27 @@ NV_STATUS __nvoc_objCreate_FlaMemory(FlaMemory**, Dynamic*, NvU32, CALL_CONTEXT #define flamemCanCopy(pFlaMemory) flamemCanCopy_DISPATCH(pFlaMemory) #define flamemCopyConstruct(pFlaMemory, pCallContext, pParams) flamemCopyConstruct_DISPATCH(pFlaMemory, pCallContext, pParams) #define flamemCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) flamemCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define flamemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) flamemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define flamemMapTo(pResource, pParams) flamemMapTo_DISPATCH(pResource, pParams) +#define flamemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) flamemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define flamemGetRefCount(pResource) flamemGetRefCount_DISPATCH(pResource) +#define flamemAddAdditionalDependants(pClient, pResource, pReference) flamemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define flamemControl_Prologue(pResource, pCallContext, pParams) flamemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define flamemIsGpuMapAllowed(pMemory, pGpu) flamemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define flamemUnmapFrom(pResource, pParams) flamemUnmapFrom_DISPATCH(pResource, pParams) +#define flamemControl_Epilogue(pResource, pCallContext, pParams) flamemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define flamemControlLookup(pResource, pParams, ppEntry) flamemControlLookup_DISPATCH(pResource, pParams, ppEntry) #define flamemControl(pMemory, pCallContext, pParams) flamemControl_DISPATCH(pMemory, pCallContext, pParams) #define flamemUnmap(pMemory, pCallContext, pCpuMapping) flamemUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define flamemGetMemInterMapParams(pMemory, pParams) flamemGetMemInterMapParams_DISPATCH(pMemory, pParams) #define flamemGetMemoryMappingDescriptor(pMemory, ppMemDesc) flamemGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define flamemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) flamemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) -#define flamemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) flamemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define flamemControlFilter(pResource, pCallContext, pParams) flamemControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define flamemAddAdditionalDependants(pClient, pResource, pReference) flamemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define flamemGetRefCount(pResource) flamemGetRefCount_DISPATCH(pResource) -#define flamemMapTo(pResource, pParams) flamemMapTo_DISPATCH(pResource, pParams) -#define flamemControl_Prologue(pResource, pCallContext, pParams) flamemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define flamemIsGpuMapAllowed(pMemory, pGpu) flamemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define flamemControlSerialization_Prologue(pResource, pCallContext, pParams) flamemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define flamemIsReady(pMemory, bCopyConstructorContext) flamemIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define flamemCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) flamemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) #define flamemPreDestruct(pResource) flamemPreDestruct_DISPATCH(pResource) #define flamemIsDuplicate(pMemory, hMemory, pDuplicate) flamemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) -#define flamemUnmapFrom(pResource, pParams) flamemUnmapFrom_DISPATCH(pResource, pParams) -#define flamemControl_Epilogue(pResource, pCallContext, pParams) flamemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define flamemControlLookup(pResource, pParams, ppEntry) flamemControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define flamemControlSerialization_Epilogue(pResource, pCallContext, pParams) flamemControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define flamemMap(pMemory, pCallContext, pParams, pCpuMapping) flamemMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define flamemAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) flamemAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool flamemCanCopy_IMPL(struct FlaMemory *pFlaMemory); @@ -150,6 +154,46 @@ static inline NV_STATUS flamemCheckMemInterUnmap_DISPATCH(struct FlaMemory *pMem return pMemory->__flamemCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } +static inline NvBool flamemShareCallback_DISPATCH(struct FlaMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__flamemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS flamemMapTo_DISPATCH(struct FlaMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__flamemMapTo__(pResource, pParams); +} + +static inline NV_STATUS flamemGetMapAddrSpace_DISPATCH(struct FlaMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__flamemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 flamemGetRefCount_DISPATCH(struct FlaMemory *pResource) { + return pResource->__flamemGetRefCount__(pResource); +} + +static inline void flamemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct FlaMemory *pResource, RsResourceRef *pReference) { + pResource->__flamemAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS flamemControl_Prologue_DISPATCH(struct FlaMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__flamemControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool flamemIsGpuMapAllowed_DISPATCH(struct FlaMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__flamemIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline NV_STATUS flamemUnmapFrom_DISPATCH(struct FlaMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__flamemUnmapFrom__(pResource, pParams); +} + +static inline void flamemControl_Epilogue_DISPATCH(struct FlaMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__flamemControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS flamemControlLookup_DISPATCH(struct FlaMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__flamemControlLookup__(pResource, pParams, ppEntry); +} + static inline NV_STATUS flamemControl_DISPATCH(struct FlaMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pMemory->__flamemControl__(pMemory, pCallContext, pParams); } @@ -166,36 +210,12 @@ static inline NV_STATUS flamemGetMemoryMappingDescriptor_DISPATCH(struct FlaMemo return pMemory->__flamemGetMemoryMappingDescriptor__(pMemory, ppMemDesc); } -static inline NV_STATUS flamemGetMapAddrSpace_DISPATCH(struct FlaMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pMemory->__flamemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvBool flamemShareCallback_DISPATCH(struct FlaMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pResource->__flamemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); -} - static inline NV_STATUS flamemControlFilter_DISPATCH(struct FlaMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__flamemControlFilter__(pResource, pCallContext, pParams); } -static inline void flamemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct FlaMemory *pResource, RsResourceRef *pReference) { - pResource->__flamemAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 flamemGetRefCount_DISPATCH(struct FlaMemory *pResource) { - return pResource->__flamemGetRefCount__(pResource); -} - -static inline NV_STATUS flamemMapTo_DISPATCH(struct FlaMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__flamemMapTo__(pResource, pParams); -} - -static inline NV_STATUS flamemControl_Prologue_DISPATCH(struct FlaMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__flamemControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NvBool flamemIsGpuMapAllowed_DISPATCH(struct FlaMemory *pMemory, struct OBJGPU *pGpu) { - return pMemory->__flamemIsGpuMapAllowed__(pMemory, pGpu); +static inline NV_STATUS flamemControlSerialization_Prologue_DISPATCH(struct FlaMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__flamemControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS flamemIsReady_DISPATCH(struct FlaMemory *pMemory, NvBool bCopyConstructorContext) { @@ -214,16 +234,8 @@ static inline NV_STATUS flamemIsDuplicate_DISPATCH(struct FlaMemory *pMemory, Nv return pMemory->__flamemIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline NV_STATUS flamemUnmapFrom_DISPATCH(struct FlaMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__flamemUnmapFrom__(pResource, pParams); -} - -static inline void flamemControl_Epilogue_DISPATCH(struct FlaMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__flamemControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS flamemControlLookup_DISPATCH(struct FlaMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__flamemControlLookup__(pResource, pParams, ppEntry); +static inline void flamemControlSerialization_Epilogue_DISPATCH(struct FlaMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__flamemControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS flamemMap_DISPATCH(struct FlaMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_fm_session_api_nvoc.c b/src/nvidia/generated/g_fm_session_api_nvoc.c index 596dd968c..ce018ae69 100644 --- a/src/nvidia/generated/g_fm_session_api_nvoc.c +++ b/src/nvidia/generated/g_fm_session_api_nvoc.c @@ -110,10 +110,50 @@ static NV_STATUS __nvoc_thunk_RmResource_fmsessionapiCheckMemInterUnmap(struct F return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), bSubdeviceHandleProvided); } +static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiMapTo(struct FmSessionApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pParams); +} + static NvBool __nvoc_thunk_RmResource_fmsessionapiAccessCallback(struct FmSessionApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), pInvokingClient, pAllocParams, accessRight); } +static void __nvoc_thunk_Notifier_fmsessionapiSetNotificationShare(struct FmSessionApi *pNotifier, struct NotifShare *pNotifShare) { + notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_FmSessionApi_Notifier.offset), pNotifShare); +} + +static NvU32 __nvoc_thunk_RsResource_fmsessionapiGetRefCount(struct FmSessionApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_fmsessionapiAddAdditionalDependants(struct RsClient *pClient, struct FmSessionApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_fmsessionapiControl_Prologue(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiUnmapFrom(struct FmSessionApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_fmsessionapiControl_Epilogue(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiControlLookup(struct FmSessionApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pParams, ppEntry); +} + +static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiControl(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControl((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiUnmap(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pCallContext, pCpuMapping); +} + static NV_STATUS __nvoc_thunk_RmResource_fmsessionapiGetMemInterMapParams(struct FmSessionApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), pParams); } @@ -122,74 +162,42 @@ static NV_STATUS __nvoc_thunk_RmResource_fmsessionapiGetMemoryMappingDescriptor( return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), ppMemDesc); } -static void __nvoc_thunk_Notifier_fmsessionapiSetNotificationShare(struct FmSessionApi *pNotifier, struct NotifShare *pNotifShare) { - notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_FmSessionApi_Notifier.offset), pNotifShare); -} - -static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiControl(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControl((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pCallContext, pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiControlFilter(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pCallContext, pParams); } -static NvU32 __nvoc_thunk_RsResource_fmsessionapiGetRefCount(struct FmSessionApi *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_Notifier_fmsessionapiUnregisterEvent(struct FmSessionApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_FmSessionApi_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiUnmap(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RmResource_fmsessionapiControlSerialization_Prologue(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_fmsessionapiCanCopy(struct FmSessionApi *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RmResource_fmsessionapiControl_Prologue(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiMapTo(struct FmSessionApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RsResource_fmsessionapiAddAdditionalDependants(struct RsClient *pClient, struct FmSessionApi *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pReference); -} - static void __nvoc_thunk_RsResource_fmsessionapiPreDestruct(struct FmSessionApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiUnmapFrom(struct FmSessionApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiIsDuplicate(struct FmSessionApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_fmsessionapiControlSerialization_Epilogue(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_fmsessionapiGetNotificationListPtr(struct FmSessionApi *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_FmSessionApi_Notifier.offset)); } -static void __nvoc_thunk_RmResource_fmsessionapiControl_Epilogue(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), pCallContext, pParams); -} - static struct NotifShare *__nvoc_thunk_Notifier_fmsessionapiGetNotificationShare(struct FmSessionApi *pNotifier) { return notifyGetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_FmSessionApi_Notifier.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiControlLookup(struct FmSessionApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiMap(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return resMap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pCallContext, pParams, pCpuMapping); } @@ -295,46 +303,50 @@ static void __nvoc_init_funcTable_FmSessionApi_1(FmSessionApi *pThis) { pThis->__fmsessionapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_fmsessionapiCheckMemInterUnmap; + pThis->__fmsessionapiMapTo__ = &__nvoc_thunk_RsResource_fmsessionapiMapTo; + pThis->__fmsessionapiAccessCallback__ = &__nvoc_thunk_RmResource_fmsessionapiAccessCallback; + pThis->__fmsessionapiSetNotificationShare__ = &__nvoc_thunk_Notifier_fmsessionapiSetNotificationShare; + + pThis->__fmsessionapiGetRefCount__ = &__nvoc_thunk_RsResource_fmsessionapiGetRefCount; + + pThis->__fmsessionapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_fmsessionapiAddAdditionalDependants; + + pThis->__fmsessionapiControl_Prologue__ = &__nvoc_thunk_RmResource_fmsessionapiControl_Prologue; + + pThis->__fmsessionapiUnmapFrom__ = &__nvoc_thunk_RsResource_fmsessionapiUnmapFrom; + + pThis->__fmsessionapiControl_Epilogue__ = &__nvoc_thunk_RmResource_fmsessionapiControl_Epilogue; + + pThis->__fmsessionapiControlLookup__ = &__nvoc_thunk_RsResource_fmsessionapiControlLookup; + + pThis->__fmsessionapiControl__ = &__nvoc_thunk_RsResource_fmsessionapiControl; + + pThis->__fmsessionapiUnmap__ = &__nvoc_thunk_RsResource_fmsessionapiUnmap; + pThis->__fmsessionapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_fmsessionapiGetMemInterMapParams; pThis->__fmsessionapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_fmsessionapiGetMemoryMappingDescriptor; - pThis->__fmsessionapiSetNotificationShare__ = &__nvoc_thunk_Notifier_fmsessionapiSetNotificationShare; - - pThis->__fmsessionapiControl__ = &__nvoc_thunk_RsResource_fmsessionapiControl; - pThis->__fmsessionapiControlFilter__ = &__nvoc_thunk_RsResource_fmsessionapiControlFilter; - pThis->__fmsessionapiGetRefCount__ = &__nvoc_thunk_RsResource_fmsessionapiGetRefCount; - pThis->__fmsessionapiUnregisterEvent__ = &__nvoc_thunk_Notifier_fmsessionapiUnregisterEvent; - pThis->__fmsessionapiUnmap__ = &__nvoc_thunk_RsResource_fmsessionapiUnmap; + pThis->__fmsessionapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_fmsessionapiControlSerialization_Prologue; pThis->__fmsessionapiCanCopy__ = &__nvoc_thunk_RsResource_fmsessionapiCanCopy; - pThis->__fmsessionapiControl_Prologue__ = &__nvoc_thunk_RmResource_fmsessionapiControl_Prologue; - - pThis->__fmsessionapiMapTo__ = &__nvoc_thunk_RsResource_fmsessionapiMapTo; - - pThis->__fmsessionapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_fmsessionapiAddAdditionalDependants; - pThis->__fmsessionapiPreDestruct__ = &__nvoc_thunk_RsResource_fmsessionapiPreDestruct; - pThis->__fmsessionapiUnmapFrom__ = &__nvoc_thunk_RsResource_fmsessionapiUnmapFrom; - pThis->__fmsessionapiIsDuplicate__ = &__nvoc_thunk_RsResource_fmsessionapiIsDuplicate; + pThis->__fmsessionapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_fmsessionapiControlSerialization_Epilogue; + pThis->__fmsessionapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_fmsessionapiGetNotificationListPtr; - pThis->__fmsessionapiControl_Epilogue__ = &__nvoc_thunk_RmResource_fmsessionapiControl_Epilogue; - pThis->__fmsessionapiGetNotificationShare__ = &__nvoc_thunk_Notifier_fmsessionapiGetNotificationShare; - pThis->__fmsessionapiControlLookup__ = &__nvoc_thunk_RsResource_fmsessionapiControlLookup; - pThis->__fmsessionapiMap__ = &__nvoc_thunk_RsResource_fmsessionapiMap; pThis->__fmsessionapiGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_fmsessionapiGetOrAllocNotifShare; @@ -364,13 +376,16 @@ NV_STATUS __nvoc_objCreate_FmSessionApi(FmSessionApi **ppThis, Dynamic *pParent, Object *pParentObj; FmSessionApi *pThis; - pThis = portMemAllocNonPaged(sizeof(FmSessionApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(FmSessionApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(FmSessionApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_FmSessionApi); + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -386,11 +401,17 @@ NV_STATUS __nvoc_objCreate_FmSessionApi(FmSessionApi **ppThis, Dynamic *pParent, if (status != NV_OK) goto __nvoc_objCreate_FmSessionApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_FmSessionApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(FmSessionApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_fm_session_api_nvoc.h b/src/nvidia/generated/g_fm_session_api_nvoc.h index 1295b49ff..3afc8083f 100644 --- a/src/nvidia/generated/g_fm_session_api_nvoc.h +++ b/src/nvidia/generated/g_fm_session_api_nvoc.h @@ -84,26 +84,28 @@ struct FmSessionApi { NV_STATUS (*__fmsessionapiCtrlCmdClearFmState__)(struct FmSessionApi *); NvBool (*__fmsessionapiShareCallback__)(struct FmSessionApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__fmsessionapiCheckMemInterUnmap__)(struct FmSessionApi *, NvBool); + NV_STATUS (*__fmsessionapiMapTo__)(struct FmSessionApi *, RS_RES_MAP_TO_PARAMS *); NvBool (*__fmsessionapiAccessCallback__)(struct FmSessionApi *, struct RsClient *, void *, RsAccessRight); + void (*__fmsessionapiSetNotificationShare__)(struct FmSessionApi *, struct NotifShare *); + NvU32 (*__fmsessionapiGetRefCount__)(struct FmSessionApi *); + void (*__fmsessionapiAddAdditionalDependants__)(struct RsClient *, struct FmSessionApi *, RsResourceRef *); + NV_STATUS (*__fmsessionapiControl_Prologue__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__fmsessionapiUnmapFrom__)(struct FmSessionApi *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__fmsessionapiControl_Epilogue__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__fmsessionapiControlLookup__)(struct FmSessionApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__fmsessionapiControl__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__fmsessionapiUnmap__)(struct FmSessionApi *, struct CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__fmsessionapiGetMemInterMapParams__)(struct FmSessionApi *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__fmsessionapiGetMemoryMappingDescriptor__)(struct FmSessionApi *, struct MEMORY_DESCRIPTOR **); - void (*__fmsessionapiSetNotificationShare__)(struct FmSessionApi *, struct NotifShare *); - NV_STATUS (*__fmsessionapiControl__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__fmsessionapiControlFilter__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvU32 (*__fmsessionapiGetRefCount__)(struct FmSessionApi *); NV_STATUS (*__fmsessionapiUnregisterEvent__)(struct FmSessionApi *, NvHandle, NvHandle, NvHandle, NvHandle); - NV_STATUS (*__fmsessionapiUnmap__)(struct FmSessionApi *, struct CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__fmsessionapiControlSerialization_Prologue__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__fmsessionapiCanCopy__)(struct FmSessionApi *); - NV_STATUS (*__fmsessionapiControl_Prologue__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__fmsessionapiMapTo__)(struct FmSessionApi *, RS_RES_MAP_TO_PARAMS *); - void (*__fmsessionapiAddAdditionalDependants__)(struct RsClient *, struct FmSessionApi *, RsResourceRef *); void (*__fmsessionapiPreDestruct__)(struct FmSessionApi *); - NV_STATUS (*__fmsessionapiUnmapFrom__)(struct FmSessionApi *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__fmsessionapiIsDuplicate__)(struct FmSessionApi *, NvHandle, NvBool *); + void (*__fmsessionapiControlSerialization_Epilogue__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__fmsessionapiGetNotificationListPtr__)(struct FmSessionApi *); - void (*__fmsessionapiControl_Epilogue__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); struct NotifShare *(*__fmsessionapiGetNotificationShare__)(struct FmSessionApi *); - NV_STATUS (*__fmsessionapiControlLookup__)(struct FmSessionApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__fmsessionapiMap__)(struct FmSessionApi *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NV_STATUS (*__fmsessionapiGetOrAllocNotifShare__)(struct FmSessionApi *, NvHandle, NvHandle, struct NotifShare **); NvU64 dupedCapDescriptor; @@ -141,26 +143,28 @@ NV_STATUS __nvoc_objCreate_FmSessionApi(FmSessionApi**, Dynamic*, NvU32, struct #define fmsessionapiCtrlCmdClearFmState(pFmSessionApi) fmsessionapiCtrlCmdClearFmState_DISPATCH(pFmSessionApi) #define fmsessionapiShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) fmsessionapiShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define fmsessionapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) fmsessionapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define fmsessionapiMapTo(pResource, pParams) fmsessionapiMapTo_DISPATCH(pResource, pParams) #define fmsessionapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) fmsessionapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +#define fmsessionapiSetNotificationShare(pNotifier, pNotifShare) fmsessionapiSetNotificationShare_DISPATCH(pNotifier, pNotifShare) +#define fmsessionapiGetRefCount(pResource) fmsessionapiGetRefCount_DISPATCH(pResource) +#define fmsessionapiAddAdditionalDependants(pClient, pResource, pReference) fmsessionapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define fmsessionapiControl_Prologue(pResource, pCallContext, pParams) fmsessionapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define fmsessionapiUnmapFrom(pResource, pParams) fmsessionapiUnmapFrom_DISPATCH(pResource, pParams) +#define fmsessionapiControl_Epilogue(pResource, pCallContext, pParams) fmsessionapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define fmsessionapiControlLookup(pResource, pParams, ppEntry) fmsessionapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define fmsessionapiControl(pResource, pCallContext, pParams) fmsessionapiControl_DISPATCH(pResource, pCallContext, pParams) +#define fmsessionapiUnmap(pResource, pCallContext, pCpuMapping) fmsessionapiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define fmsessionapiGetMemInterMapParams(pRmResource, pParams) fmsessionapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define fmsessionapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) fmsessionapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define fmsessionapiSetNotificationShare(pNotifier, pNotifShare) fmsessionapiSetNotificationShare_DISPATCH(pNotifier, pNotifShare) -#define fmsessionapiControl(pResource, pCallContext, pParams) fmsessionapiControl_DISPATCH(pResource, pCallContext, pParams) #define fmsessionapiControlFilter(pResource, pCallContext, pParams) fmsessionapiControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define fmsessionapiGetRefCount(pResource) fmsessionapiGetRefCount_DISPATCH(pResource) #define fmsessionapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) fmsessionapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) -#define fmsessionapiUnmap(pResource, pCallContext, pCpuMapping) fmsessionapiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define fmsessionapiControlSerialization_Prologue(pResource, pCallContext, pParams) fmsessionapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define fmsessionapiCanCopy(pResource) fmsessionapiCanCopy_DISPATCH(pResource) -#define fmsessionapiControl_Prologue(pResource, pCallContext, pParams) fmsessionapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define fmsessionapiMapTo(pResource, pParams) fmsessionapiMapTo_DISPATCH(pResource, pParams) -#define fmsessionapiAddAdditionalDependants(pClient, pResource, pReference) fmsessionapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define fmsessionapiPreDestruct(pResource) fmsessionapiPreDestruct_DISPATCH(pResource) -#define fmsessionapiUnmapFrom(pResource, pParams) fmsessionapiUnmapFrom_DISPATCH(pResource, pParams) #define fmsessionapiIsDuplicate(pResource, hMemory, pDuplicate) fmsessionapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define fmsessionapiControlSerialization_Epilogue(pResource, pCallContext, pParams) fmsessionapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define fmsessionapiGetNotificationListPtr(pNotifier) fmsessionapiGetNotificationListPtr_DISPATCH(pNotifier) -#define fmsessionapiControl_Epilogue(pResource, pCallContext, pParams) fmsessionapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define fmsessionapiGetNotificationShare(pNotifier) fmsessionapiGetNotificationShare_DISPATCH(pNotifier) -#define fmsessionapiControlLookup(pResource, pParams, ppEntry) fmsessionapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define fmsessionapiMap(pResource, pCallContext, pParams, pCpuMapping) fmsessionapiMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) #define fmsessionapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) fmsessionapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) NV_STATUS fmsessionapiCtrlCmdSetFmState_IMPL(struct FmSessionApi *pFmSessionApi); @@ -183,10 +187,50 @@ static inline NV_STATUS fmsessionapiCheckMemInterUnmap_DISPATCH(struct FmSession return pRmResource->__fmsessionapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } +static inline NV_STATUS fmsessionapiMapTo_DISPATCH(struct FmSessionApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__fmsessionapiMapTo__(pResource, pParams); +} + static inline NvBool fmsessionapiAccessCallback_DISPATCH(struct FmSessionApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return pResource->__fmsessionapiAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); } +static inline void fmsessionapiSetNotificationShare_DISPATCH(struct FmSessionApi *pNotifier, struct NotifShare *pNotifShare) { + pNotifier->__fmsessionapiSetNotificationShare__(pNotifier, pNotifShare); +} + +static inline NvU32 fmsessionapiGetRefCount_DISPATCH(struct FmSessionApi *pResource) { + return pResource->__fmsessionapiGetRefCount__(pResource); +} + +static inline void fmsessionapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct FmSessionApi *pResource, RsResourceRef *pReference) { + pResource->__fmsessionapiAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS fmsessionapiControl_Prologue_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__fmsessionapiControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS fmsessionapiUnmapFrom_DISPATCH(struct FmSessionApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__fmsessionapiUnmapFrom__(pResource, pParams); +} + +static inline void fmsessionapiControl_Epilogue_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__fmsessionapiControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS fmsessionapiControlLookup_DISPATCH(struct FmSessionApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__fmsessionapiControlLookup__(pResource, pParams, ppEntry); +} + +static inline NV_STATUS fmsessionapiControl_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__fmsessionapiControl__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS fmsessionapiUnmap_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__fmsessionapiUnmap__(pResource, pCallContext, pCpuMapping); +} + static inline NV_STATUS fmsessionapiGetMemInterMapParams_DISPATCH(struct FmSessionApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { return pRmResource->__fmsessionapiGetMemInterMapParams__(pRmResource, pParams); } @@ -195,74 +239,42 @@ static inline NV_STATUS fmsessionapiGetMemoryMappingDescriptor_DISPATCH(struct F return pRmResource->__fmsessionapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline void fmsessionapiSetNotificationShare_DISPATCH(struct FmSessionApi *pNotifier, struct NotifShare *pNotifShare) { - pNotifier->__fmsessionapiSetNotificationShare__(pNotifier, pNotifShare); -} - -static inline NV_STATUS fmsessionapiControl_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__fmsessionapiControl__(pResource, pCallContext, pParams); -} - static inline NV_STATUS fmsessionapiControlFilter_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__fmsessionapiControlFilter__(pResource, pCallContext, pParams); } -static inline NvU32 fmsessionapiGetRefCount_DISPATCH(struct FmSessionApi *pResource) { - return pResource->__fmsessionapiGetRefCount__(pResource); -} - static inline NV_STATUS fmsessionapiUnregisterEvent_DISPATCH(struct FmSessionApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { return pNotifier->__fmsessionapiUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static inline NV_STATUS fmsessionapiUnmap_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pResource->__fmsessionapiUnmap__(pResource, pCallContext, pCpuMapping); +static inline NV_STATUS fmsessionapiControlSerialization_Prologue_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__fmsessionapiControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool fmsessionapiCanCopy_DISPATCH(struct FmSessionApi *pResource) { return pResource->__fmsessionapiCanCopy__(pResource); } -static inline NV_STATUS fmsessionapiControl_Prologue_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__fmsessionapiControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS fmsessionapiMapTo_DISPATCH(struct FmSessionApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__fmsessionapiMapTo__(pResource, pParams); -} - -static inline void fmsessionapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct FmSessionApi *pResource, RsResourceRef *pReference) { - pResource->__fmsessionapiAddAdditionalDependants__(pClient, pResource, pReference); -} - static inline void fmsessionapiPreDestruct_DISPATCH(struct FmSessionApi *pResource) { pResource->__fmsessionapiPreDestruct__(pResource); } -static inline NV_STATUS fmsessionapiUnmapFrom_DISPATCH(struct FmSessionApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__fmsessionapiUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS fmsessionapiIsDuplicate_DISPATCH(struct FmSessionApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__fmsessionapiIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void fmsessionapiControlSerialization_Epilogue_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__fmsessionapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *fmsessionapiGetNotificationListPtr_DISPATCH(struct FmSessionApi *pNotifier) { return pNotifier->__fmsessionapiGetNotificationListPtr__(pNotifier); } -static inline void fmsessionapiControl_Epilogue_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__fmsessionapiControl_Epilogue__(pResource, pCallContext, pParams); -} - static inline struct NotifShare *fmsessionapiGetNotificationShare_DISPATCH(struct FmSessionApi *pNotifier) { return pNotifier->__fmsessionapiGetNotificationShare__(pNotifier); } -static inline NV_STATUS fmsessionapiControlLookup_DISPATCH(struct FmSessionApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__fmsessionapiControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS fmsessionapiMap_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return pResource->__fmsessionapiMap__(pResource, pCallContext, pParams, pCpuMapping); } diff --git a/src/nvidia/generated/g_generic_engine_nvoc.c b/src/nvidia/generated/g_generic_engine_nvoc.c index 213f1f264..8c05ba103 100644 --- a/src/nvidia/generated/g_generic_engine_nvoc.c +++ b/src/nvidia/generated/g_generic_engine_nvoc.c @@ -109,6 +109,50 @@ static NvBool __nvoc_thunk_GpuResource_genapiShareCallback(struct GenericEngineA return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GenericEngineApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } +static NV_STATUS __nvoc_thunk_RmResource_genapiCheckMemInterUnmap(struct GenericEngineApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GenericEngineApi_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_genapiMapTo(struct GenericEngineApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset), pParams); +} + +static NvU32 __nvoc_thunk_RsResource_genapiGetRefCount(struct GenericEngineApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_genapiAddAdditionalDependants(struct RsClient *pClient, struct GenericEngineApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_genapiControl_Prologue(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_genapiGetRegBaseOffsetAndSize(struct GenericEngineApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GenericEngineApi_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_genapiInternalControlForward(struct GenericEngineApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GenericEngineApi_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_genapiUnmapFrom(struct GenericEngineApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_genapiControl_Epilogue(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_genapiControlLookup(struct GenericEngineApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset), pParams, ppEntry); +} + +static NvHandle __nvoc_thunk_GpuResource_genapiGetInternalObjectHandle(struct GenericEngineApi *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GenericEngineApi_GpuResource.offset)); +} + static NV_STATUS __nvoc_thunk_GpuResource_genapiUnmap(struct GenericEngineApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GenericEngineApi_GpuResource.offset), pCallContext, pCpuMapping); } @@ -121,64 +165,28 @@ static NV_STATUS __nvoc_thunk_RmResource_genapiGetMemoryMappingDescriptor(struct return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GenericEngineApi_RmResource.offset), ppMemDesc); } -static NvHandle __nvoc_thunk_GpuResource_genapiGetInternalObjectHandle(struct GenericEngineApi *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GenericEngineApi_GpuResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_genapiControlFilter(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_genapiAddAdditionalDependants(struct RsClient *pClient, struct GenericEngineApi *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_genapiGetRefCount(struct GenericEngineApi *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RmResource_genapiCheckMemInterUnmap(struct GenericEngineApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GenericEngineApi_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_genapiMapTo(struct GenericEngineApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_genapiControl_Prologue(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_GpuResource_genapiGetRegBaseOffsetAndSize(struct GenericEngineApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GenericEngineApi_GpuResource.offset), pGpu, pOffset, pSize); +static NV_STATUS __nvoc_thunk_RmResource_genapiControlSerialization_Prologue(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_genapiCanCopy(struct GenericEngineApi *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_genapiInternalControlForward(struct GenericEngineApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GenericEngineApi_GpuResource.offset), command, pParams, size); -} - static void __nvoc_thunk_RsResource_genapiPreDestruct(struct GenericEngineApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_genapiUnmapFrom(struct GenericEngineApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_genapiIsDuplicate(struct GenericEngineApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset), hMemory, pDuplicate); } -static void __nvoc_thunk_RmResource_genapiControl_Epilogue(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_genapiControlLookup(struct GenericEngineApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_genapiControlSerialization_Epilogue(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RmResource_genapiAccessCallback(struct GenericEngineApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { @@ -285,41 +293,45 @@ static void __nvoc_init_funcTable_GenericEngineApi_1(GenericEngineApi *pThis) { pThis->__genapiShareCallback__ = &__nvoc_thunk_GpuResource_genapiShareCallback; + pThis->__genapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_genapiCheckMemInterUnmap; + + pThis->__genapiMapTo__ = &__nvoc_thunk_RsResource_genapiMapTo; + + pThis->__genapiGetRefCount__ = &__nvoc_thunk_RsResource_genapiGetRefCount; + + pThis->__genapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_genapiAddAdditionalDependants; + + pThis->__genapiControl_Prologue__ = &__nvoc_thunk_RmResource_genapiControl_Prologue; + + pThis->__genapiGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_genapiGetRegBaseOffsetAndSize; + + pThis->__genapiInternalControlForward__ = &__nvoc_thunk_GpuResource_genapiInternalControlForward; + + pThis->__genapiUnmapFrom__ = &__nvoc_thunk_RsResource_genapiUnmapFrom; + + pThis->__genapiControl_Epilogue__ = &__nvoc_thunk_RmResource_genapiControl_Epilogue; + + pThis->__genapiControlLookup__ = &__nvoc_thunk_RsResource_genapiControlLookup; + + pThis->__genapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_genapiGetInternalObjectHandle; + pThis->__genapiUnmap__ = &__nvoc_thunk_GpuResource_genapiUnmap; pThis->__genapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_genapiGetMemInterMapParams; pThis->__genapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_genapiGetMemoryMappingDescriptor; - pThis->__genapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_genapiGetInternalObjectHandle; - pThis->__genapiControlFilter__ = &__nvoc_thunk_RsResource_genapiControlFilter; - pThis->__genapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_genapiAddAdditionalDependants; - - pThis->__genapiGetRefCount__ = &__nvoc_thunk_RsResource_genapiGetRefCount; - - pThis->__genapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_genapiCheckMemInterUnmap; - - pThis->__genapiMapTo__ = &__nvoc_thunk_RsResource_genapiMapTo; - - pThis->__genapiControl_Prologue__ = &__nvoc_thunk_RmResource_genapiControl_Prologue; - - pThis->__genapiGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_genapiGetRegBaseOffsetAndSize; + pThis->__genapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_genapiControlSerialization_Prologue; pThis->__genapiCanCopy__ = &__nvoc_thunk_RsResource_genapiCanCopy; - pThis->__genapiInternalControlForward__ = &__nvoc_thunk_GpuResource_genapiInternalControlForward; - pThis->__genapiPreDestruct__ = &__nvoc_thunk_RsResource_genapiPreDestruct; - pThis->__genapiUnmapFrom__ = &__nvoc_thunk_RsResource_genapiUnmapFrom; - pThis->__genapiIsDuplicate__ = &__nvoc_thunk_RsResource_genapiIsDuplicate; - pThis->__genapiControl_Epilogue__ = &__nvoc_thunk_RmResource_genapiControl_Epilogue; - - pThis->__genapiControlLookup__ = &__nvoc_thunk_RsResource_genapiControlLookup; + pThis->__genapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_genapiControlSerialization_Epilogue; pThis->__genapiAccessCallback__ = &__nvoc_thunk_RmResource_genapiAccessCallback; } @@ -345,13 +357,16 @@ NV_STATUS __nvoc_objCreate_GenericEngineApi(GenericEngineApi **ppThis, Dynamic * Object *pParentObj; GenericEngineApi *pThis; - pThis = portMemAllocNonPaged(sizeof(GenericEngineApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(GenericEngineApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(GenericEngineApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_GenericEngineApi); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -367,11 +382,17 @@ NV_STATUS __nvoc_objCreate_GenericEngineApi(GenericEngineApi **ppThis, Dynamic * if (status != NV_OK) goto __nvoc_objCreate_GenericEngineApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_GenericEngineApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(GenericEngineApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_generic_engine_nvoc.h b/src/nvidia/generated/g_generic_engine_nvoc.h index 76d50221f..b3ac4bccb 100644 --- a/src/nvidia/generated/g_generic_engine_nvoc.h +++ b/src/nvidia/generated/g_generic_engine_nvoc.h @@ -62,24 +62,26 @@ struct GenericEngineApi { NV_STATUS (*__genapiCtrlCmdMasterGetErrorIntrOffsetMask__)(struct GenericEngineApi *, NV90E6_CTRL_MASTER_GET_ERROR_INTR_OFFSET_MASK_PARAMS *); NV_STATUS (*__genapiCtrlCmdMasterGetVirtualFunctionErrorContIntrMask__)(struct GenericEngineApi *, NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS *); NvBool (*__genapiShareCallback__)(struct GenericEngineApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__genapiCheckMemInterUnmap__)(struct GenericEngineApi *, NvBool); + NV_STATUS (*__genapiMapTo__)(struct GenericEngineApi *, RS_RES_MAP_TO_PARAMS *); + NvU32 (*__genapiGetRefCount__)(struct GenericEngineApi *); + void (*__genapiAddAdditionalDependants__)(struct RsClient *, struct GenericEngineApi *, RsResourceRef *); + NV_STATUS (*__genapiControl_Prologue__)(struct GenericEngineApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__genapiGetRegBaseOffsetAndSize__)(struct GenericEngineApi *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__genapiInternalControlForward__)(struct GenericEngineApi *, NvU32, void *, NvU32); + NV_STATUS (*__genapiUnmapFrom__)(struct GenericEngineApi *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__genapiControl_Epilogue__)(struct GenericEngineApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__genapiControlLookup__)(struct GenericEngineApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__genapiGetInternalObjectHandle__)(struct GenericEngineApi *); NV_STATUS (*__genapiUnmap__)(struct GenericEngineApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__genapiGetMemInterMapParams__)(struct GenericEngineApi *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__genapiGetMemoryMappingDescriptor__)(struct GenericEngineApi *, struct MEMORY_DESCRIPTOR **); - NvHandle (*__genapiGetInternalObjectHandle__)(struct GenericEngineApi *); NV_STATUS (*__genapiControlFilter__)(struct GenericEngineApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__genapiAddAdditionalDependants__)(struct RsClient *, struct GenericEngineApi *, RsResourceRef *); - NvU32 (*__genapiGetRefCount__)(struct GenericEngineApi *); - NV_STATUS (*__genapiCheckMemInterUnmap__)(struct GenericEngineApi *, NvBool); - NV_STATUS (*__genapiMapTo__)(struct GenericEngineApi *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__genapiControl_Prologue__)(struct GenericEngineApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__genapiGetRegBaseOffsetAndSize__)(struct GenericEngineApi *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__genapiControlSerialization_Prologue__)(struct GenericEngineApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__genapiCanCopy__)(struct GenericEngineApi *); - NV_STATUS (*__genapiInternalControlForward__)(struct GenericEngineApi *, NvU32, void *, NvU32); void (*__genapiPreDestruct__)(struct GenericEngineApi *); - NV_STATUS (*__genapiUnmapFrom__)(struct GenericEngineApi *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__genapiIsDuplicate__)(struct GenericEngineApi *, NvHandle, NvBool *); - void (*__genapiControl_Epilogue__)(struct GenericEngineApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__genapiControlLookup__)(struct GenericEngineApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__genapiControlSerialization_Epilogue__)(struct GenericEngineApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__genapiAccessCallback__)(struct GenericEngineApi *, struct RsClient *, void *, RsAccessRight); }; @@ -117,24 +119,26 @@ NV_STATUS __nvoc_objCreate_GenericEngineApi(GenericEngineApi**, Dynamic*, NvU32, #define genapiCtrlCmdMasterGetErrorIntrOffsetMask(pGenericEngineApi, pParams) genapiCtrlCmdMasterGetErrorIntrOffsetMask_DISPATCH(pGenericEngineApi, pParams) #define genapiCtrlCmdMasterGetVirtualFunctionErrorContIntrMask(pGenericEngineApi, pParams) genapiCtrlCmdMasterGetVirtualFunctionErrorContIntrMask_DISPATCH(pGenericEngineApi, pParams) #define genapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) genapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define genapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) genapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define genapiMapTo(pResource, pParams) genapiMapTo_DISPATCH(pResource, pParams) +#define genapiGetRefCount(pResource) genapiGetRefCount_DISPATCH(pResource) +#define genapiAddAdditionalDependants(pClient, pResource, pReference) genapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define genapiControl_Prologue(pResource, pCallContext, pParams) genapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define genapiGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) genapiGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define genapiInternalControlForward(pGpuResource, command, pParams, size) genapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define genapiUnmapFrom(pResource, pParams) genapiUnmapFrom_DISPATCH(pResource, pParams) +#define genapiControl_Epilogue(pResource, pCallContext, pParams) genapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define genapiControlLookup(pResource, pParams, ppEntry) genapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define genapiGetInternalObjectHandle(pGpuResource) genapiGetInternalObjectHandle_DISPATCH(pGpuResource) #define genapiUnmap(pGpuResource, pCallContext, pCpuMapping) genapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define genapiGetMemInterMapParams(pRmResource, pParams) genapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define genapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) genapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define genapiGetInternalObjectHandle(pGpuResource) genapiGetInternalObjectHandle_DISPATCH(pGpuResource) #define genapiControlFilter(pResource, pCallContext, pParams) genapiControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define genapiAddAdditionalDependants(pClient, pResource, pReference) genapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define genapiGetRefCount(pResource) genapiGetRefCount_DISPATCH(pResource) -#define genapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) genapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define genapiMapTo(pResource, pParams) genapiMapTo_DISPATCH(pResource, pParams) -#define genapiControl_Prologue(pResource, pCallContext, pParams) genapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define genapiGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) genapiGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define genapiControlSerialization_Prologue(pResource, pCallContext, pParams) genapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define genapiCanCopy(pResource) genapiCanCopy_DISPATCH(pResource) -#define genapiInternalControlForward(pGpuResource, command, pParams, size) genapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define genapiPreDestruct(pResource) genapiPreDestruct_DISPATCH(pResource) -#define genapiUnmapFrom(pResource, pParams) genapiUnmapFrom_DISPATCH(pResource, pParams) #define genapiIsDuplicate(pResource, hMemory, pDuplicate) genapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) -#define genapiControl_Epilogue(pResource, pCallContext, pParams) genapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define genapiControlLookup(pResource, pParams, ppEntry) genapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define genapiControlSerialization_Epilogue(pResource, pCallContext, pParams) genapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define genapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) genapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS genapiMap_IMPL(struct GenericEngineApi *pGenericEngineApi, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping); @@ -170,6 +174,50 @@ static inline NvBool genapiShareCallback_DISPATCH(struct GenericEngineApi *pGpuR return pGpuResource->__genapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } +static inline NV_STATUS genapiCheckMemInterUnmap_DISPATCH(struct GenericEngineApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__genapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS genapiMapTo_DISPATCH(struct GenericEngineApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__genapiMapTo__(pResource, pParams); +} + +static inline NvU32 genapiGetRefCount_DISPATCH(struct GenericEngineApi *pResource) { + return pResource->__genapiGetRefCount__(pResource); +} + +static inline void genapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct GenericEngineApi *pResource, RsResourceRef *pReference) { + pResource->__genapiAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS genapiControl_Prologue_DISPATCH(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__genapiControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS genapiGetRegBaseOffsetAndSize_DISPATCH(struct GenericEngineApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__genapiGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS genapiInternalControlForward_DISPATCH(struct GenericEngineApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__genapiInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS genapiUnmapFrom_DISPATCH(struct GenericEngineApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__genapiUnmapFrom__(pResource, pParams); +} + +static inline void genapiControl_Epilogue_DISPATCH(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__genapiControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS genapiControlLookup_DISPATCH(struct GenericEngineApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__genapiControlLookup__(pResource, pParams, ppEntry); +} + +static inline NvHandle genapiGetInternalObjectHandle_DISPATCH(struct GenericEngineApi *pGpuResource) { + return pGpuResource->__genapiGetInternalObjectHandle__(pGpuResource); +} + static inline NV_STATUS genapiUnmap_DISPATCH(struct GenericEngineApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { return pGpuResource->__genapiUnmap__(pGpuResource, pCallContext, pCpuMapping); } @@ -182,64 +230,28 @@ static inline NV_STATUS genapiGetMemoryMappingDescriptor_DISPATCH(struct Generic return pRmResource->__genapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NvHandle genapiGetInternalObjectHandle_DISPATCH(struct GenericEngineApi *pGpuResource) { - return pGpuResource->__genapiGetInternalObjectHandle__(pGpuResource); -} - static inline NV_STATUS genapiControlFilter_DISPATCH(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__genapiControlFilter__(pResource, pCallContext, pParams); } -static inline void genapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct GenericEngineApi *pResource, RsResourceRef *pReference) { - pResource->__genapiAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 genapiGetRefCount_DISPATCH(struct GenericEngineApi *pResource) { - return pResource->__genapiGetRefCount__(pResource); -} - -static inline NV_STATUS genapiCheckMemInterUnmap_DISPATCH(struct GenericEngineApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__genapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS genapiMapTo_DISPATCH(struct GenericEngineApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__genapiMapTo__(pResource, pParams); -} - -static inline NV_STATUS genapiControl_Prologue_DISPATCH(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__genapiControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS genapiGetRegBaseOffsetAndSize_DISPATCH(struct GenericEngineApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__genapiGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +static inline NV_STATUS genapiControlSerialization_Prologue_DISPATCH(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__genapiControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool genapiCanCopy_DISPATCH(struct GenericEngineApi *pResource) { return pResource->__genapiCanCopy__(pResource); } -static inline NV_STATUS genapiInternalControlForward_DISPATCH(struct GenericEngineApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__genapiInternalControlForward__(pGpuResource, command, pParams, size); -} - static inline void genapiPreDestruct_DISPATCH(struct GenericEngineApi *pResource) { pResource->__genapiPreDestruct__(pResource); } -static inline NV_STATUS genapiUnmapFrom_DISPATCH(struct GenericEngineApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__genapiUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS genapiIsDuplicate_DISPATCH(struct GenericEngineApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__genapiIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline void genapiControl_Epilogue_DISPATCH(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__genapiControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS genapiControlLookup_DISPATCH(struct GenericEngineApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__genapiControlLookup__(pResource, pParams, ppEntry); +static inline void genapiControlSerialization_Epilogue_DISPATCH(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__genapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NvBool genapiAccessCallback_DISPATCH(struct GenericEngineApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { diff --git a/src/nvidia/generated/g_gpu_access_nvoc.c b/src/nvidia/generated/g_gpu_access_nvoc.c new file mode 100644 index 000000000..507bec0d4 --- /dev/null +++ b/src/nvidia/generated/g_gpu_access_nvoc.c @@ -0,0 +1,491 @@ +#define NVOC_GPU_ACCESS_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_gpu_access_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x40549c = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_IoAperture; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RegisterAperture; + +void __nvoc_init_IoAperture(IoAperture*); +void __nvoc_init_funcTable_IoAperture(IoAperture*); +NV_STATUS __nvoc_ctor_IoAperture(IoAperture*, struct IoAperture * arg_pParentAperture, OBJGPU * arg_pGpu, NvU32 arg_deviceIndex, NvU32 arg_deviceInstance, DEVICE_MAPPING * arg_pMapping, NvU32 arg_mappingStartAddr, NvU32 arg_offset, NvU32 arg_length); +void __nvoc_init_dataField_IoAperture(IoAperture*); +void __nvoc_dtor_IoAperture(IoAperture*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_IoAperture; + +static const struct NVOC_RTTI __nvoc_rtti_IoAperture_IoAperture = { + /*pClassDef=*/ &__nvoc_class_def_IoAperture, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_IoAperture, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_IoAperture_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(IoAperture, __nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_IoAperture_RegisterAperture = { + /*pClassDef=*/ &__nvoc_class_def_RegisterAperture, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(IoAperture, __nvoc_base_RegisterAperture), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_IoAperture = { + /*numRelatives=*/ 3, + /*relatives=*/ { + &__nvoc_rtti_IoAperture_IoAperture, + &__nvoc_rtti_IoAperture_RegisterAperture, + &__nvoc_rtti_IoAperture_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_IoAperture = +{ + /*classInfo=*/ { + /*size=*/ sizeof(IoAperture), + /*classId=*/ classId(IoAperture), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "IoAperture", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_IoAperture, + /*pCastInfo=*/ &__nvoc_castinfo_IoAperture, + /*pExportInfo=*/ &__nvoc_export_info_IoAperture +}; + +static NvU8 __nvoc_thunk_IoAperture_regaprtReadReg08(struct RegisterAperture *pAperture, NvU32 addr) { + return ioaprtReadReg08((struct IoAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_IoAperture_RegisterAperture.offset), addr); +} + +static NvU16 __nvoc_thunk_IoAperture_regaprtReadReg16(struct RegisterAperture *pAperture, NvU32 addr) { + return ioaprtReadReg16((struct IoAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_IoAperture_RegisterAperture.offset), addr); +} + +static NvU32 __nvoc_thunk_IoAperture_regaprtReadReg32(struct RegisterAperture *pAperture, NvU32 addr) { + return ioaprtReadReg32((struct IoAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_IoAperture_RegisterAperture.offset), addr); +} + +static void __nvoc_thunk_IoAperture_regaprtWriteReg08(struct RegisterAperture *pAperture, NvU32 addr, NvV8 value) { + ioaprtWriteReg08((struct IoAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_IoAperture_RegisterAperture.offset), addr, value); +} + +static void __nvoc_thunk_IoAperture_regaprtWriteReg16(struct RegisterAperture *pAperture, NvU32 addr, NvV16 value) { + ioaprtWriteReg16((struct IoAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_IoAperture_RegisterAperture.offset), addr, value); +} + +static void __nvoc_thunk_IoAperture_regaprtWriteReg32(struct RegisterAperture *pAperture, NvU32 addr, NvV32 value) { + ioaprtWriteReg32((struct IoAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_IoAperture_RegisterAperture.offset), addr, value); +} + +static void __nvoc_thunk_IoAperture_regaprtWriteReg32Uc(struct RegisterAperture *pAperture, NvU32 addr, NvV32 value) { + ioaprtWriteReg32Uc((struct IoAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_IoAperture_RegisterAperture.offset), addr, value); +} + +static NvBool __nvoc_thunk_IoAperture_regaprtIsRegValid(struct RegisterAperture *pAperture, NvU32 addr) { + return ioaprtIsRegValid((struct IoAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_IoAperture_RegisterAperture.offset), addr); +} + +const struct NVOC_EXPORT_INFO __nvoc_export_info_IoAperture = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_Object(Object*); +void __nvoc_dtor_RegisterAperture(RegisterAperture*); +void __nvoc_dtor_IoAperture(IoAperture *pThis) { + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); + __nvoc_dtor_RegisterAperture(&pThis->__nvoc_base_RegisterAperture); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_IoAperture(IoAperture *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_Object(Object* ); +NV_STATUS __nvoc_ctor_RegisterAperture(RegisterAperture* ); +NV_STATUS __nvoc_ctor_IoAperture(IoAperture *pThis, struct IoAperture * arg_pParentAperture, OBJGPU * arg_pGpu, NvU32 arg_deviceIndex, NvU32 arg_deviceInstance, DEVICE_MAPPING * arg_pMapping, NvU32 arg_mappingStartAddr, NvU32 arg_offset, NvU32 arg_length) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_Object(&pThis->__nvoc_base_Object); + if (status != NV_OK) goto __nvoc_ctor_IoAperture_fail_Object; + status = __nvoc_ctor_RegisterAperture(&pThis->__nvoc_base_RegisterAperture); + if (status != NV_OK) goto __nvoc_ctor_IoAperture_fail_RegisterAperture; + __nvoc_init_dataField_IoAperture(pThis); + + status = __nvoc_ioaprtConstruct(pThis, arg_pParentAperture, arg_pGpu, arg_deviceIndex, arg_deviceInstance, arg_pMapping, arg_mappingStartAddr, arg_offset, arg_length); + if (status != NV_OK) goto __nvoc_ctor_IoAperture_fail__init; + goto __nvoc_ctor_IoAperture_exit; // Success + +__nvoc_ctor_IoAperture_fail__init: + __nvoc_dtor_RegisterAperture(&pThis->__nvoc_base_RegisterAperture); +__nvoc_ctor_IoAperture_fail_RegisterAperture: + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); +__nvoc_ctor_IoAperture_fail_Object: +__nvoc_ctor_IoAperture_exit: + + return status; +} + +static void __nvoc_init_funcTable_IoAperture_1(IoAperture *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + + pThis->__ioaprtReadReg08__ = &ioaprtReadReg08_IMPL; + + pThis->__ioaprtReadReg16__ = &ioaprtReadReg16_IMPL; + + pThis->__ioaprtReadReg32__ = &ioaprtReadReg32_IMPL; + + pThis->__ioaprtWriteReg08__ = &ioaprtWriteReg08_IMPL; + + pThis->__ioaprtWriteReg16__ = &ioaprtWriteReg16_IMPL; + + pThis->__ioaprtWriteReg32__ = &ioaprtWriteReg32_IMPL; + + pThis->__ioaprtWriteReg32Uc__ = &ioaprtWriteReg32Uc_IMPL; + + pThis->__ioaprtIsRegValid__ = &ioaprtIsRegValid_IMPL; + + pThis->__nvoc_base_RegisterAperture.__regaprtReadReg08__ = &__nvoc_thunk_IoAperture_regaprtReadReg08; + + pThis->__nvoc_base_RegisterAperture.__regaprtReadReg16__ = &__nvoc_thunk_IoAperture_regaprtReadReg16; + + pThis->__nvoc_base_RegisterAperture.__regaprtReadReg32__ = &__nvoc_thunk_IoAperture_regaprtReadReg32; + + pThis->__nvoc_base_RegisterAperture.__regaprtWriteReg08__ = &__nvoc_thunk_IoAperture_regaprtWriteReg08; + + pThis->__nvoc_base_RegisterAperture.__regaprtWriteReg16__ = &__nvoc_thunk_IoAperture_regaprtWriteReg16; + + pThis->__nvoc_base_RegisterAperture.__regaprtWriteReg32__ = &__nvoc_thunk_IoAperture_regaprtWriteReg32; + + pThis->__nvoc_base_RegisterAperture.__regaprtWriteReg32Uc__ = &__nvoc_thunk_IoAperture_regaprtWriteReg32Uc; + + pThis->__nvoc_base_RegisterAperture.__regaprtIsRegValid__ = &__nvoc_thunk_IoAperture_regaprtIsRegValid; +} + +void __nvoc_init_funcTable_IoAperture(IoAperture *pThis) { + __nvoc_init_funcTable_IoAperture_1(pThis); +} + +void __nvoc_init_Object(Object*); +void __nvoc_init_RegisterAperture(RegisterAperture*); +void __nvoc_init_IoAperture(IoAperture *pThis) { + pThis->__nvoc_pbase_IoAperture = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Object; + pThis->__nvoc_pbase_RegisterAperture = &pThis->__nvoc_base_RegisterAperture; + __nvoc_init_Object(&pThis->__nvoc_base_Object); + __nvoc_init_RegisterAperture(&pThis->__nvoc_base_RegisterAperture); + __nvoc_init_funcTable_IoAperture(pThis); +} + +NV_STATUS __nvoc_objCreate_IoAperture(IoAperture **ppThis, Dynamic *pParent, NvU32 createFlags, struct IoAperture * arg_pParentAperture, OBJGPU * arg_pGpu, NvU32 arg_deviceIndex, NvU32 arg_deviceInstance, DEVICE_MAPPING * arg_pMapping, NvU32 arg_mappingStartAddr, NvU32 arg_offset, NvU32 arg_length) { + NV_STATUS status; + Object *pParentObj; + IoAperture *pThis; + + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(IoAperture), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + portMemSet(pThis, 0, sizeof(IoAperture)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_IoAperture); + + pThis->__nvoc_base_Object.createFlags = createFlags; + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_IoAperture(pThis); + status = __nvoc_ctor_IoAperture(pThis, arg_pParentAperture, arg_pGpu, arg_deviceIndex, arg_deviceInstance, arg_pMapping, arg_mappingStartAddr, arg_offset, arg_length); + if (status != NV_OK) goto __nvoc_objCreate_IoAperture_cleanup; + + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_IoAperture_cleanup: + // do not call destructors here since the constructor already called them + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(IoAperture)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_IoAperture(IoAperture **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + struct IoAperture * arg_pParentAperture = va_arg(args, struct IoAperture *); + OBJGPU * arg_pGpu = va_arg(args, OBJGPU *); + NvU32 arg_deviceIndex = va_arg(args, NvU32); + NvU32 arg_deviceInstance = va_arg(args, NvU32); + DEVICE_MAPPING * arg_pMapping = va_arg(args, DEVICE_MAPPING *); + NvU32 arg_mappingStartAddr = va_arg(args, NvU32); + NvU32 arg_offset = va_arg(args, NvU32); + NvU32 arg_length = va_arg(args, NvU32); + + status = __nvoc_objCreate_IoAperture(ppThis, pParent, createFlags, arg_pParentAperture, arg_pGpu, arg_deviceIndex, arg_deviceInstance, arg_pMapping, arg_mappingStartAddr, arg_offset, arg_length); + + return status; +} + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x6d0f88 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_SwBcAperture; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RegisterAperture; + +void __nvoc_init_SwBcAperture(SwBcAperture*); +void __nvoc_init_funcTable_SwBcAperture(SwBcAperture*); +NV_STATUS __nvoc_ctor_SwBcAperture(SwBcAperture*, struct IoAperture * arg_pApertures, NvU32 arg_numApertures); +void __nvoc_init_dataField_SwBcAperture(SwBcAperture*); +void __nvoc_dtor_SwBcAperture(SwBcAperture*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_SwBcAperture; + +static const struct NVOC_RTTI __nvoc_rtti_SwBcAperture_SwBcAperture = { + /*pClassDef=*/ &__nvoc_class_def_SwBcAperture, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_SwBcAperture, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_SwBcAperture_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(SwBcAperture, __nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_SwBcAperture_RegisterAperture = { + /*pClassDef=*/ &__nvoc_class_def_RegisterAperture, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(SwBcAperture, __nvoc_base_RegisterAperture), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_SwBcAperture = { + /*numRelatives=*/ 3, + /*relatives=*/ { + &__nvoc_rtti_SwBcAperture_SwBcAperture, + &__nvoc_rtti_SwBcAperture_RegisterAperture, + &__nvoc_rtti_SwBcAperture_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_SwBcAperture = +{ + /*classInfo=*/ { + /*size=*/ sizeof(SwBcAperture), + /*classId=*/ classId(SwBcAperture), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "SwBcAperture", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_SwBcAperture, + /*pCastInfo=*/ &__nvoc_castinfo_SwBcAperture, + /*pExportInfo=*/ &__nvoc_export_info_SwBcAperture +}; + +static NvU8 __nvoc_thunk_SwBcAperture_regaprtReadReg08(struct RegisterAperture *pAperture, NvU32 addr) { + return swbcaprtReadReg08((struct SwBcAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_SwBcAperture_RegisterAperture.offset), addr); +} + +static NvU16 __nvoc_thunk_SwBcAperture_regaprtReadReg16(struct RegisterAperture *pAperture, NvU32 addr) { + return swbcaprtReadReg16((struct SwBcAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_SwBcAperture_RegisterAperture.offset), addr); +} + +static NvU32 __nvoc_thunk_SwBcAperture_regaprtReadReg32(struct RegisterAperture *pAperture, NvU32 addr) { + return swbcaprtReadReg32((struct SwBcAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_SwBcAperture_RegisterAperture.offset), addr); +} + +static void __nvoc_thunk_SwBcAperture_regaprtWriteReg08(struct RegisterAperture *pAperture, NvU32 addr, NvV8 value) { + swbcaprtWriteReg08((struct SwBcAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_SwBcAperture_RegisterAperture.offset), addr, value); +} + +static void __nvoc_thunk_SwBcAperture_regaprtWriteReg16(struct RegisterAperture *pAperture, NvU32 addr, NvV16 value) { + swbcaprtWriteReg16((struct SwBcAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_SwBcAperture_RegisterAperture.offset), addr, value); +} + +static void __nvoc_thunk_SwBcAperture_regaprtWriteReg32(struct RegisterAperture *pAperture, NvU32 addr, NvV32 value) { + swbcaprtWriteReg32((struct SwBcAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_SwBcAperture_RegisterAperture.offset), addr, value); +} + +static void __nvoc_thunk_SwBcAperture_regaprtWriteReg32Uc(struct RegisterAperture *pAperture, NvU32 addr, NvV32 value) { + swbcaprtWriteReg32Uc((struct SwBcAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_SwBcAperture_RegisterAperture.offset), addr, value); +} + +static NvBool __nvoc_thunk_SwBcAperture_regaprtIsRegValid(struct RegisterAperture *pAperture, NvU32 addr) { + return swbcaprtIsRegValid((struct SwBcAperture *)(((unsigned char *)pAperture) - __nvoc_rtti_SwBcAperture_RegisterAperture.offset), addr); +} + +const struct NVOC_EXPORT_INFO __nvoc_export_info_SwBcAperture = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_Object(Object*); +void __nvoc_dtor_RegisterAperture(RegisterAperture*); +void __nvoc_dtor_SwBcAperture(SwBcAperture *pThis) { + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); + __nvoc_dtor_RegisterAperture(&pThis->__nvoc_base_RegisterAperture); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_SwBcAperture(SwBcAperture *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_Object(Object* ); +NV_STATUS __nvoc_ctor_RegisterAperture(RegisterAperture* ); +NV_STATUS __nvoc_ctor_SwBcAperture(SwBcAperture *pThis, struct IoAperture * arg_pApertures, NvU32 arg_numApertures) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_Object(&pThis->__nvoc_base_Object); + if (status != NV_OK) goto __nvoc_ctor_SwBcAperture_fail_Object; + status = __nvoc_ctor_RegisterAperture(&pThis->__nvoc_base_RegisterAperture); + if (status != NV_OK) goto __nvoc_ctor_SwBcAperture_fail_RegisterAperture; + __nvoc_init_dataField_SwBcAperture(pThis); + + status = __nvoc_swbcaprtConstruct(pThis, arg_pApertures, arg_numApertures); + if (status != NV_OK) goto __nvoc_ctor_SwBcAperture_fail__init; + goto __nvoc_ctor_SwBcAperture_exit; // Success + +__nvoc_ctor_SwBcAperture_fail__init: + __nvoc_dtor_RegisterAperture(&pThis->__nvoc_base_RegisterAperture); +__nvoc_ctor_SwBcAperture_fail_RegisterAperture: + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); +__nvoc_ctor_SwBcAperture_fail_Object: +__nvoc_ctor_SwBcAperture_exit: + + return status; +} + +static void __nvoc_init_funcTable_SwBcAperture_1(SwBcAperture *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + + pThis->__swbcaprtReadReg08__ = &swbcaprtReadReg08_IMPL; + + pThis->__swbcaprtReadReg16__ = &swbcaprtReadReg16_IMPL; + + pThis->__swbcaprtReadReg32__ = &swbcaprtReadReg32_IMPL; + + pThis->__swbcaprtWriteReg08__ = &swbcaprtWriteReg08_IMPL; + + pThis->__swbcaprtWriteReg16__ = &swbcaprtWriteReg16_IMPL; + + pThis->__swbcaprtWriteReg32__ = &swbcaprtWriteReg32_IMPL; + + pThis->__swbcaprtWriteReg32Uc__ = &swbcaprtWriteReg32Uc_IMPL; + + pThis->__swbcaprtIsRegValid__ = &swbcaprtIsRegValid_IMPL; + + pThis->__nvoc_base_RegisterAperture.__regaprtReadReg08__ = &__nvoc_thunk_SwBcAperture_regaprtReadReg08; + + pThis->__nvoc_base_RegisterAperture.__regaprtReadReg16__ = &__nvoc_thunk_SwBcAperture_regaprtReadReg16; + + pThis->__nvoc_base_RegisterAperture.__regaprtReadReg32__ = &__nvoc_thunk_SwBcAperture_regaprtReadReg32; + + pThis->__nvoc_base_RegisterAperture.__regaprtWriteReg08__ = &__nvoc_thunk_SwBcAperture_regaprtWriteReg08; + + pThis->__nvoc_base_RegisterAperture.__regaprtWriteReg16__ = &__nvoc_thunk_SwBcAperture_regaprtWriteReg16; + + pThis->__nvoc_base_RegisterAperture.__regaprtWriteReg32__ = &__nvoc_thunk_SwBcAperture_regaprtWriteReg32; + + pThis->__nvoc_base_RegisterAperture.__regaprtWriteReg32Uc__ = &__nvoc_thunk_SwBcAperture_regaprtWriteReg32Uc; + + pThis->__nvoc_base_RegisterAperture.__regaprtIsRegValid__ = &__nvoc_thunk_SwBcAperture_regaprtIsRegValid; +} + +void __nvoc_init_funcTable_SwBcAperture(SwBcAperture *pThis) { + __nvoc_init_funcTable_SwBcAperture_1(pThis); +} + +void __nvoc_init_Object(Object*); +void __nvoc_init_RegisterAperture(RegisterAperture*); +void __nvoc_init_SwBcAperture(SwBcAperture *pThis) { + pThis->__nvoc_pbase_SwBcAperture = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Object; + pThis->__nvoc_pbase_RegisterAperture = &pThis->__nvoc_base_RegisterAperture; + __nvoc_init_Object(&pThis->__nvoc_base_Object); + __nvoc_init_RegisterAperture(&pThis->__nvoc_base_RegisterAperture); + __nvoc_init_funcTable_SwBcAperture(pThis); +} + +NV_STATUS __nvoc_objCreate_SwBcAperture(SwBcAperture **ppThis, Dynamic *pParent, NvU32 createFlags, struct IoAperture * arg_pApertures, NvU32 arg_numApertures) { + NV_STATUS status; + Object *pParentObj; + SwBcAperture *pThis; + + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(SwBcAperture), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + portMemSet(pThis, 0, sizeof(SwBcAperture)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_SwBcAperture); + + pThis->__nvoc_base_Object.createFlags = createFlags; + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_SwBcAperture(pThis); + status = __nvoc_ctor_SwBcAperture(pThis, arg_pApertures, arg_numApertures); + if (status != NV_OK) goto __nvoc_objCreate_SwBcAperture_cleanup; + + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_SwBcAperture_cleanup: + // do not call destructors here since the constructor already called them + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(SwBcAperture)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_SwBcAperture(SwBcAperture **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + struct IoAperture * arg_pApertures = va_arg(args, struct IoAperture *); + NvU32 arg_numApertures = va_arg(args, NvU32); + + status = __nvoc_objCreate_SwBcAperture(ppThis, pParent, createFlags, arg_pApertures, arg_numApertures); + + return status; +} + diff --git a/src/nvidia/generated/g_gpu_access_nvoc.h b/src/nvidia/generated/g_gpu_access_nvoc.h new file mode 100644 index 000000000..6116af33c --- /dev/null +++ b/src/nvidia/generated/g_gpu_access_nvoc.h @@ -0,0 +1,631 @@ +#ifndef _G_GPU_ACCESS_NVOC_H_ +#define _G_GPU_ACCESS_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2004-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include "g_gpu_access_nvoc.h" + +#ifndef _GPU_ACCESS_H_ +#define _GPU_ACCESS_H_ + +#include "core/core.h" +#include "ioaccess/ioaccess.h" +#include "gpu/gpu_device_mapping.h" + +// Go straight at the memory or hardware. +#define MEM_RD08(a) (*(const volatile NvU8 *)(a)) +#define MEM_RD16(a) (*(const volatile NvU16 *)(a)) +#define MEM_RD32(a) (*(const volatile NvU32 *)(a)) +#define MEM_WR08(a, d) do { *(volatile NvU8 *)(a) = (d); } while (0) +#define MEM_WR16(a, d) do { *(volatile NvU16 *)(a) = (d); } while (0) +#define MEM_WR32(a, d) do { *(volatile NvU32 *)(a) = (d); } while (0) +#define MEM_WR64(a, d) do { *(volatile NvU64 *)(a) = (d); } while (0) + +// +// Define the signature of the register filter callback function +// +// flags can be optionally used for filters to decide whether to actually +// touch HW or not. flags should be OR'ed every time a new filter is found. (see objgpu.c) +// +typedef void (*GpuWriteRegCallback)(OBJGPU *, void *, NvU32 addr, NvU32 val, NvU32 accessSize, NvU32 flags); +typedef NvU32 (*GpuReadRegCallback)(OBJGPU *, void *, NvU32 addr, NvU32 accessSize, NvU32 flags); + +union GPUHWREG +{ + volatile NvV8 Reg008[1]; + volatile NvV16 Reg016[1]; + volatile NvV32 Reg032[1]; +}; + +typedef union GPUHWREG GPUHWREG; + +// +// Register filter record +// +// If REGISTER_FILTER_FLAGS_READ is set, then that means that the base RegRead +// function will not read the register, so the provided read callback function +// is expected to read the register and return the value. +// +// If REGISTER_FILTER_FLAGS_WRITE is set, then that means that the base RegWrite +// function will not write the register, so the provided callback write function +// is expected to write the given value to the register. +// +// It is an error to specify REGISTER_FILTER_FLAGS_READ and not provide a +// read callback function. +// +// It is an error to specify REGISTER_FILTER_FLAGS_WRITE and not provide a +// write callback function. +// +#define REGISTER_FILTER_FLAGS_READ (NVBIT(0)) +#define REGISTER_FILTER_FLAGS_WRITE (NVBIT(1)) +// filter is in the list but it is invalid and should be removed +#define REGISTER_FILTER_FLAGS_INVALID (NVBIT(2)) + +#define REGISTER_FILTER_FLAGS_VIRTUAL (0) +#define REGISTER_FILTER_FLAGS_READ_WRITE (REGISTER_FILTER_FLAGS_READ | REGISTER_FILTER_FLAGS_WRITE) + +typedef struct REGISTER_FILTER REGISTER_FILTER; + +struct REGISTER_FILTER +{ + REGISTER_FILTER *pNext; //!< pointer to next filter + NvU32 flags; //!< attributes of this filter + DEVICE_INDEX devIndex; //!< filter device + NvU32 devInstance; //!< filter device instance + NvU32 rangeStart; //!< filter range start (can overlap) + NvU32 rangeEnd; //!< filter range end (can overlap) + GpuWriteRegCallback pWriteCallback; //!< callback for write + GpuReadRegCallback pReadCallback; //!< callback for read + void *pParam; //!< pointer to param which gets passed to callbacks +}; + +typedef struct { + REGISTER_FILTER *pRegFilterList; // Active filters + REGISTER_FILTER *pRegFilterRecycleList; // Inactive filters + PORT_SPINLOCK * pRegFilterLock; // Thread-safe list management + NvU32 regFilterRefCnt; // Thread-safe list management + NvBool bRegFilterNeedRemove; // Thread-safe list garbage collection +} DEVICE_REGFILTER_INFO; + +typedef struct DEVICE_MAPPING +{ + GPUHWREG *gpuNvAddr; // CPU Virtual Address + RmPhysAddr gpuNvPAddr; // Physical Base Address + NvU32 gpuNvLength; // Length of the Aperture + NvU32 gpuNvSaveLength; + NvU32 gpuDeviceEnum; // Device ID NV_DEVID_* + NvU32 refCount; // refCount for the device map. + DEVICE_REGFILTER_INFO devRegFilterInfo; // register filter range list +} DEVICE_MAPPING; + +typedef struct +{ + // Pointer to GPU linked to this RegisterAccess object + OBJGPU *pGpu; + + // HW register access tools + GPUHWREG *gpuFbAddr; + GPUHWREG *gpuInstAddr; + + // Register access profiling + NvU32 regReadCount; + NvU32 regWriteCount; +} RegisterAccess; + +/*! Init register IO access path */ +NV_STATUS regAccessConstruct(RegisterAccess *, OBJGPU *pGpu); + +/*! Shutdown register IO access path */ +void regAccessDestruct(RegisterAccess *); + +/*! Writes to 8 bit register */ +void regWrite008(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32, NvV8); + +/*! Writes to 16 bit register */ +void regWrite016(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32, NvV16); + +/*! Writes to 32 bit register, with thread state on the stack */ +void regWrite032(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32, NvV32, THREAD_STATE_NODE *); + +/*! Unicast register access, with thread state on the stack */ +void regWrite032Unicast(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32, NvV32, THREAD_STATE_NODE *); + +/*! Reads from 8 bit register */ +NvU8 regRead008(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32); + +/*! Reads from 16 bit register */ +NvU16 regRead016(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32); + +/*! Reads from 32 bit register, with thread state on the stack */ +NvU32 regRead032(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32, THREAD_STATE_NODE *); + +/*! Reads from 32 bit register and checks bit mask, with thread state on the stack */ +NvU32 regCheckRead032(RegisterAccess *, NvU32, NvU32, THREAD_STATE_NODE *); + +/*! Reads 32 bit register and polls bit field for specific value */ +NV_STATUS regRead032_AndPoll(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32, NvU32); + +/*! Adds a register filter */ +NV_STATUS regAddRegisterFilter(RegisterAccess *, NvU32, DEVICE_INDEX, NvU32, NvU32, NvU32, GpuWriteRegCallback, GpuReadRegCallback, void *, REGISTER_FILTER **); + +/*! Removes register filter */ +void regRemoveRegisterFilter(RegisterAccess *, REGISTER_FILTER *); + +/*! Check status of read return value for GPU/bus errors */ +void regCheckAndLogReadFailure(RegisterAccess *, NvU32 addr, NvU32 mask, NvU32 value); + +// +// GPU register I/O macros. +// + +// +// GPU neutral macros typically used for register I/O. +// +#define GPU_DRF_SHIFT(drf) ((0?drf) % 32) +#define GPU_DRF_MASK(drf) (0xFFFFFFFF>>(31-((1?drf) % 32)+((0?drf) % 32))) +#define GPU_DRF_DEF(d,r,f,c) ((NV ## d ## r ## f ## c)<>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) +#define GPU_DRF_SHIFTMASK(drf) (GPU_DRF_MASK(drf)<<(GPU_DRF_SHIFT(drf))) +#define GPU_DRF_WIDTH(drf) ((1?drf) - (0?drf) + 1) + + +// Device independent macros +// Multiple device instance macros + +#define REG_INST_RD08(g,dev,inst,a) regRead008(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a) +#define REG_INST_RD16(g,dev,inst,a) regRead016(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a) +#define REG_INST_RD32(g,dev,inst,a) regRead032(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a, NULL) + +#define REG_INST_WR08(g,dev,inst,a,v) regWrite008(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a, v) +#define REG_INST_WR16(g,dev,inst,a,v) regWrite016(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a, v) +#define REG_INST_WR32(g,dev,inst,a,v) regWrite032(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a, v, NULL) +#define REG_INST_WR32_UC(g,dev,inst,a,v) regWrite032Unicast(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a, v, NULL) + +#define REG_INST_RD32_EX(g,dev,inst,a,t) regRead032(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a, t) +#define REG_INST_WR32_EX(g,dev,inst,a,v,t) regWrite032(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a, v, t) + +#define REG_INST_DEVIDX_RD32_EX(g,devidx,inst,a,t) regRead032(GPU_GET_REGISTER_ACCESS(g), devidx, inst, a, t) +#define REG_INST_DEVIDX_WR32_EX(g,devidx,inst,a,v,t) regWrite032(GPU_GET_REGISTER_ACCESS(g), devidx, inst, a, v, t) + +// Get the address of a register given the Aperture and offset. +#define REG_GET_ADDR(ap, offset) ioaprtGetRegAddr(ap, offset) + +// GPU macros defined in terms of DEV_ macros +#define GPU_REG_RD08(g,a) REG_INST_RD08(g,GPU,0,a) +#define GPU_REG_RD16(g,a) REG_INST_RD16(g,GPU,0,a) +#define GPU_REG_RD32(g,a) REG_INST_RD32(g,GPU,0,a) +#define GPU_CHECK_REG_RD32(g,a,m) regCheckRead032(GPU_GET_REGISTER_ACCESS(g),a,m,NULL) +#define GPU_REG_RD32_AND_POLL(g,r,m,v) regRead032_AndPoll(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_GPU, r, m, v) + +#define GPU_REG_WR08(g,a,v) REG_INST_WR08(g,GPU,0,a,v) +#define GPU_REG_WR16(g,a,v) REG_INST_WR16(g,GPU,0,a,v) +#define GPU_REG_WR32(g,a,v) REG_INST_WR32(g,GPU,0,a,v) +#define GPU_REG_WR32_UC(g,a,v) REG_INST_WR32_UC(g,GPU,0,a,v) + +// GPU macros for SR-IOV +#define GPU_VREG_RD32(g, a) GPU_REG_RD32(g, g->sriovState.virtualRegPhysOffset + a) +#define GPU_VREG_WR32(g, a, v) GPU_REG_WR32(g, g->sriovState.virtualRegPhysOffset + a, v) +#define GPU_VREG_RD32_EX(g,a,t) REG_INST_RD32_EX(g, GPU, 0, g->sriovState.virtualRegPhysOffset + a, t) +#define GPU_VREG_WR32_EX(g,a,v,t) REG_INST_WR32_EX(g, GPU, 0, g->sriovState.virtualRegPhysOffset + a, v, t) +#define GPU_VREG_FLD_WR_DRF_DEF(g,d,r,f,c) GPU_VREG_WR32(g, NV##d##r,(GPU_VREG_RD32(g,NV##d##r)&~(GPU_DRF_MASK(NV##d##r##f)<>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) + +#define VREG_INST_RD32(g,dev,inst,a) regRead032(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, g->sriovState.virtualRegPhysOffset + a, NULL) +#define VREG_INST_WR32(g,dev,inst,a,v) regWrite032(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, g->sriovState.virtualRegPhysOffset + a, v, NULL) +#define GPU_VREG_FLD_WR_DRF_NUM(g,d,r,f,n) VREG_INST_WR32(g,GPU,0,NV##d##r,(VREG_INST_RD32(g,GPU,0,NV##d##r)&~(GPU_DRF_MASK(NV##d##r##f)<sriovState.virtualRegPhysOffset + a) + +#define GPU_VREG_IDX_RD_DRF(g,d,r,i,f) (((GPU_VREG_RD32(g, NV ## d ## r(i)))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) +#define GPU_VREG_FLD_IDX_WR_DRF_DEF(g,d,r,i,f,c) GPU_VREG_WR32(g, NV##d##r(i),(GPU_VREG_RD32(g,NV##d##r(i))&~(GPU_DRF_MASK(NV##d##r##f)<sriovState.virtualRegPhysOffset + a) +#define GPU_VREG_WR32(g, a, v) gpuRegWr32_dumpinfo(__FUNCTION__,#a,"(VREG)",g, g->sriovState.virtualRegPhysOffset + a, v) + +#endif // GPU_REGISTER_ACCESS_DUMP + +// +// Macros for register I/O +// +#define GPU_FLD_WR_DRF_NUM(g,d,r,f,n) REG_INST_WR32(g,GPU,0,NV##d##r,(REG_INST_RD32(g,GPU,0,NV##d##r)&~(GPU_DRF_MASK(NV##d##r##f)<>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) +#define GPU_FLD_TEST_DRF_DEF(g,d,r,f,c) (GPU_REG_RD_DRF(g, d, r, f) == NV##d##r##f##c) +#define GPU_FLD_TEST_DRF_NUM(g,d,r,f,n) (GPU_REG_RD_DRF(g, d, r, f) == n) +#define GPU_FLD_IDX_TEST_DRF_DEF(g,d,r,f,c,i) (GPU_REG_IDX_RD_DRF(g, d, r, i, f) == NV##d##r##f##c) +#define GPU_FLD_2IDX_TEST_DRF_DEF(g,d,r,f,c,i,j) (GPU_REG_2IDX_RD_DRF(g, d, r, i, j, f) == NV##d##r##f##c) + +#define GPU_REG_RD_DRF_EX(g,d,r,f,t) (((GPU_REG_RD32_EX(g, NV ## d ## r, t))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) + +#define GPU_FLD_WR_DRF_NUM_EX(g,d,r,f,n,t) REG_INST_WR32_EX(g,GPU,0,NV##d##r,(REG_INST_RD32_EX(g,GPU,0,NV##d##r,t)&~(GPU_DRF_MASK(NV##d##r##f)<>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) +#define GPU_REG_2IDX_RD_DRF(g,d,r,i,j,f) (((GPU_REG_RD32(g, NV ## d ## r(i, j)))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) +#define GPU_REG_RD_DRF_IDX(g,d,r,f,i) (((GPU_REG_RD32(g, NV ## d ## r))>>GPU_DRF_SHIFT(NV ## d ## r ## f(i)))&GPU_DRF_MASK(NV ## d ## r ## f(i))) +#define GPU_REG_IDX_OFFSET_RD_DRF(g,d,r,i,o,f) (((GPU_REG_RD32(g, NV ## d ## r(i,o)))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) + +// +// Macros that abstract the use of bif object to access GPU bus config registers +// This is the preferred set >= NV50 +// +#define GPU_BUS_CFG_RD32(g,r,d) gpuReadBusConfigReg_HAL(g, r, d) +#define GPU_BUS_CFG_WR32(g,r,d) gpuWriteBusConfigReg_HAL(g, r, d) +#define GPU_BUS_CFG_FLD_WR_DRF_DEF(g,x,d,r,f,c) GPU_BUS_CFG_WR32(g, NV##d##r,(x &~(GPU_DRF_MASK(NV##d##r##f)<>(31-(1?sf)+(0?sf))) +#define SF_SHIFTMASK(sf) (SF_MASK(sf) << SF_SHIFT(sf)) +#define SF_DEF(s,f,c) ((NV ## s ## f ## c)<>SF_SHIFT(NV ## s ## f))&SF_MASK(NV ## s ## f)) +#define SF_WIDTH(sf) ((1?sf) - (0?sf) + 1) +// This macro parses multi-word/array defines +#define SF_ARR32_VAL(s,f,arr) \ + (((arr)[SF_INDEX(NV ## s ## f)] >> SF_SHIFT(NV ## s ## f)) & SF_MASK(NV ## s ## f)) +#define FLD_SF_DEF(s,f,d,l) ((l)&~(SF_MASK(NV##s##f) << SF_SHIFT(NV##s##f)))| SF_DEF(s,f,d) +#define FLD_SF_NUM(s,f,n,l) ((l)&~(SF_MASK(NV##s##f) << SF_SHIFT(NV##s##f)))| SF_NUM(s,f,n) +#define FLD_SF_IDX_DEF(s,f,c,i,l) (((l) & ~SF_SHIFTMASK(NV ## s ## f(i))) | SF_IDX_DEF(s,f,c,i)) +#define FLD_SF_IDX_NUM(s,f,n,i,l) (((l) & ~SF_SHIFTMASK(NV ## s ## f(i))) | SF_IDX_NUM(s,f,n,i)) + +#ifdef NVOC_GPU_ACCESS_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct IoAperture { + const struct NVOC_RTTI *__nvoc_rtti; + struct Object __nvoc_base_Object; + struct RegisterAperture __nvoc_base_RegisterAperture; + struct Object *__nvoc_pbase_Object; + struct RegisterAperture *__nvoc_pbase_RegisterAperture; + struct IoAperture *__nvoc_pbase_IoAperture; + NvU8 (*__ioaprtReadReg08__)(struct IoAperture *, NvU32); + NvU16 (*__ioaprtReadReg16__)(struct IoAperture *, NvU32); + NvU32 (*__ioaprtReadReg32__)(struct IoAperture *, NvU32); + void (*__ioaprtWriteReg08__)(struct IoAperture *, NvU32, NvV8); + void (*__ioaprtWriteReg16__)(struct IoAperture *, NvU32, NvV16); + void (*__ioaprtWriteReg32__)(struct IoAperture *, NvU32, NvV32); + void (*__ioaprtWriteReg32Uc__)(struct IoAperture *, NvU32, NvV32); + NvBool (*__ioaprtIsRegValid__)(struct IoAperture *, NvU32); + OBJGPU *pGpu; + NvU32 deviceIndex; + NvU32 deviceInstance; + DEVICE_MAPPING *pMapping; + NvU32 mappingStartAddr; + NvU32 baseAddress; + NvU32 length; +}; + +#ifndef __NVOC_CLASS_IoAperture_TYPEDEF__ +#define __NVOC_CLASS_IoAperture_TYPEDEF__ +typedef struct IoAperture IoAperture; +#endif /* __NVOC_CLASS_IoAperture_TYPEDEF__ */ + +#ifndef __nvoc_class_id_IoAperture +#define __nvoc_class_id_IoAperture 0x40549c +#endif /* __nvoc_class_id_IoAperture */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_IoAperture; + +#define __staticCast_IoAperture(pThis) \ + ((pThis)->__nvoc_pbase_IoAperture) + +#ifdef __nvoc_gpu_access_h_disabled +#define __dynamicCast_IoAperture(pThis) ((IoAperture*)NULL) +#else //__nvoc_gpu_access_h_disabled +#define __dynamicCast_IoAperture(pThis) \ + ((IoAperture*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(IoAperture))) +#endif //__nvoc_gpu_access_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_IoAperture(IoAperture**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_IoAperture(IoAperture**, Dynamic*, NvU32, struct IoAperture * arg_pParentAperture, OBJGPU * arg_pGpu, NvU32 arg_deviceIndex, NvU32 arg_deviceInstance, DEVICE_MAPPING * arg_pMapping, NvU32 arg_mappingStartAddr, NvU32 arg_offset, NvU32 arg_length); +#define __objCreate_IoAperture(ppNewObj, pParent, createFlags, arg_pParentAperture, arg_pGpu, arg_deviceIndex, arg_deviceInstance, arg_pMapping, arg_mappingStartAddr, arg_offset, arg_length) \ + __nvoc_objCreate_IoAperture((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pParentAperture, arg_pGpu, arg_deviceIndex, arg_deviceInstance, arg_pMapping, arg_mappingStartAddr, arg_offset, arg_length) + +#define ioaprtReadReg08(pAperture, addr) ioaprtReadReg08_DISPATCH(pAperture, addr) +#define ioaprtReadReg16(pAperture, addr) ioaprtReadReg16_DISPATCH(pAperture, addr) +#define ioaprtReadReg32(pAperture, addr) ioaprtReadReg32_DISPATCH(pAperture, addr) +#define ioaprtWriteReg08(pAperture, addr, value) ioaprtWriteReg08_DISPATCH(pAperture, addr, value) +#define ioaprtWriteReg16(pAperture, addr, value) ioaprtWriteReg16_DISPATCH(pAperture, addr, value) +#define ioaprtWriteReg32(pAperture, addr, value) ioaprtWriteReg32_DISPATCH(pAperture, addr, value) +#define ioaprtWriteReg32Uc(pAperture, addr, value) ioaprtWriteReg32Uc_DISPATCH(pAperture, addr, value) +#define ioaprtIsRegValid(pAperture, addr) ioaprtIsRegValid_DISPATCH(pAperture, addr) +NvU8 ioaprtReadReg08_IMPL(struct IoAperture *pAperture, NvU32 addr); + +static inline NvU8 ioaprtReadReg08_DISPATCH(struct IoAperture *pAperture, NvU32 addr) { + return pAperture->__ioaprtReadReg08__(pAperture, addr); +} + +NvU16 ioaprtReadReg16_IMPL(struct IoAperture *pAperture, NvU32 addr); + +static inline NvU16 ioaprtReadReg16_DISPATCH(struct IoAperture *pAperture, NvU32 addr) { + return pAperture->__ioaprtReadReg16__(pAperture, addr); +} + +NvU32 ioaprtReadReg32_IMPL(struct IoAperture *pAperture, NvU32 addr); + +static inline NvU32 ioaprtReadReg32_DISPATCH(struct IoAperture *pAperture, NvU32 addr) { + return pAperture->__ioaprtReadReg32__(pAperture, addr); +} + +void ioaprtWriteReg08_IMPL(struct IoAperture *pAperture, NvU32 addr, NvV8 value); + +static inline void ioaprtWriteReg08_DISPATCH(struct IoAperture *pAperture, NvU32 addr, NvV8 value) { + pAperture->__ioaprtWriteReg08__(pAperture, addr, value); +} + +void ioaprtWriteReg16_IMPL(struct IoAperture *pAperture, NvU32 addr, NvV16 value); + +static inline void ioaprtWriteReg16_DISPATCH(struct IoAperture *pAperture, NvU32 addr, NvV16 value) { + pAperture->__ioaprtWriteReg16__(pAperture, addr, value); +} + +void ioaprtWriteReg32_IMPL(struct IoAperture *pAperture, NvU32 addr, NvV32 value); + +static inline void ioaprtWriteReg32_DISPATCH(struct IoAperture *pAperture, NvU32 addr, NvV32 value) { + pAperture->__ioaprtWriteReg32__(pAperture, addr, value); +} + +void ioaprtWriteReg32Uc_IMPL(struct IoAperture *pAperture, NvU32 addr, NvV32 value); + +static inline void ioaprtWriteReg32Uc_DISPATCH(struct IoAperture *pAperture, NvU32 addr, NvV32 value) { + pAperture->__ioaprtWriteReg32Uc__(pAperture, addr, value); +} + +NvBool ioaprtIsRegValid_IMPL(struct IoAperture *pAperture, NvU32 addr); + +static inline NvBool ioaprtIsRegValid_DISPATCH(struct IoAperture *pAperture, NvU32 addr) { + return pAperture->__ioaprtIsRegValid__(pAperture, addr); +} + +static inline NvU32 ioaprtGetRegAddr(struct IoAperture *pAperture, NvU32 addr) { + return pAperture->baseAddress + addr; +} + +static inline NvU32 ioaprtGetBaseAddr(struct IoAperture *pAperture) { + return pAperture->baseAddress; +} + +static inline NvU32 ioaprtGetLength(struct IoAperture *pAperture) { + return pAperture->length; +} + +NV_STATUS ioaprtConstruct_IMPL(struct IoAperture *arg_pAperture, struct IoAperture *arg_pParentAperture, OBJGPU *arg_pGpu, NvU32 arg_deviceIndex, NvU32 arg_deviceInstance, DEVICE_MAPPING *arg_pMapping, NvU32 arg_mappingStartAddr, NvU32 arg_offset, NvU32 arg_length); + +#define __nvoc_ioaprtConstruct(arg_pAperture, arg_pParentAperture, arg_pGpu, arg_deviceIndex, arg_deviceInstance, arg_pMapping, arg_mappingStartAddr, arg_offset, arg_length) ioaprtConstruct_IMPL(arg_pAperture, arg_pParentAperture, arg_pGpu, arg_deviceIndex, arg_deviceInstance, arg_pMapping, arg_mappingStartAddr, arg_offset, arg_length) +#undef PRIVATE_FIELD + + +// In-place construct wrapper +NV_STATUS ioaprtInit(struct IoAperture *pAperture, struct IoAperture *pParentAperture, NvU32 offset, NvU32 length); + +#ifdef NVOC_GPU_ACCESS_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct SwBcAperture { + const struct NVOC_RTTI *__nvoc_rtti; + struct Object __nvoc_base_Object; + struct RegisterAperture __nvoc_base_RegisterAperture; + struct Object *__nvoc_pbase_Object; + struct RegisterAperture *__nvoc_pbase_RegisterAperture; + struct SwBcAperture *__nvoc_pbase_SwBcAperture; + NvU8 (*__swbcaprtReadReg08__)(struct SwBcAperture *, NvU32); + NvU16 (*__swbcaprtReadReg16__)(struct SwBcAperture *, NvU32); + NvU32 (*__swbcaprtReadReg32__)(struct SwBcAperture *, NvU32); + void (*__swbcaprtWriteReg08__)(struct SwBcAperture *, NvU32, NvV8); + void (*__swbcaprtWriteReg16__)(struct SwBcAperture *, NvU32, NvV16); + void (*__swbcaprtWriteReg32__)(struct SwBcAperture *, NvU32, NvV32); + void (*__swbcaprtWriteReg32Uc__)(struct SwBcAperture *, NvU32, NvV32); + NvBool (*__swbcaprtIsRegValid__)(struct SwBcAperture *, NvU32); + struct IoAperture *pApertures; + NvU32 numApertures; +}; + +#ifndef __NVOC_CLASS_SwBcAperture_TYPEDEF__ +#define __NVOC_CLASS_SwBcAperture_TYPEDEF__ +typedef struct SwBcAperture SwBcAperture; +#endif /* __NVOC_CLASS_SwBcAperture_TYPEDEF__ */ + +#ifndef __nvoc_class_id_SwBcAperture +#define __nvoc_class_id_SwBcAperture 0x6d0f88 +#endif /* __nvoc_class_id_SwBcAperture */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_SwBcAperture; + +#define __staticCast_SwBcAperture(pThis) \ + ((pThis)->__nvoc_pbase_SwBcAperture) + +#ifdef __nvoc_gpu_access_h_disabled +#define __dynamicCast_SwBcAperture(pThis) ((SwBcAperture*)NULL) +#else //__nvoc_gpu_access_h_disabled +#define __dynamicCast_SwBcAperture(pThis) \ + ((SwBcAperture*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(SwBcAperture))) +#endif //__nvoc_gpu_access_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_SwBcAperture(SwBcAperture**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_SwBcAperture(SwBcAperture**, Dynamic*, NvU32, struct IoAperture * arg_pApertures, NvU32 arg_numApertures); +#define __objCreate_SwBcAperture(ppNewObj, pParent, createFlags, arg_pApertures, arg_numApertures) \ + __nvoc_objCreate_SwBcAperture((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pApertures, arg_numApertures) + +#define swbcaprtReadReg08(pAperture, addr) swbcaprtReadReg08_DISPATCH(pAperture, addr) +#define swbcaprtReadReg16(pAperture, addr) swbcaprtReadReg16_DISPATCH(pAperture, addr) +#define swbcaprtReadReg32(pAperture, addr) swbcaprtReadReg32_DISPATCH(pAperture, addr) +#define swbcaprtWriteReg08(pAperture, addr, value) swbcaprtWriteReg08_DISPATCH(pAperture, addr, value) +#define swbcaprtWriteReg16(pAperture, addr, value) swbcaprtWriteReg16_DISPATCH(pAperture, addr, value) +#define swbcaprtWriteReg32(pAperture, addr, value) swbcaprtWriteReg32_DISPATCH(pAperture, addr, value) +#define swbcaprtWriteReg32Uc(pAperture, addr, value) swbcaprtWriteReg32Uc_DISPATCH(pAperture, addr, value) +#define swbcaprtIsRegValid(pAperture, addr) swbcaprtIsRegValid_DISPATCH(pAperture, addr) +NvU8 swbcaprtReadReg08_IMPL(struct SwBcAperture *pAperture, NvU32 addr); + +static inline NvU8 swbcaprtReadReg08_DISPATCH(struct SwBcAperture *pAperture, NvU32 addr) { + return pAperture->__swbcaprtReadReg08__(pAperture, addr); +} + +NvU16 swbcaprtReadReg16_IMPL(struct SwBcAperture *pAperture, NvU32 addr); + +static inline NvU16 swbcaprtReadReg16_DISPATCH(struct SwBcAperture *pAperture, NvU32 addr) { + return pAperture->__swbcaprtReadReg16__(pAperture, addr); +} + +NvU32 swbcaprtReadReg32_IMPL(struct SwBcAperture *pAperture, NvU32 addr); + +static inline NvU32 swbcaprtReadReg32_DISPATCH(struct SwBcAperture *pAperture, NvU32 addr) { + return pAperture->__swbcaprtReadReg32__(pAperture, addr); +} + +void swbcaprtWriteReg08_IMPL(struct SwBcAperture *pAperture, NvU32 addr, NvV8 value); + +static inline void swbcaprtWriteReg08_DISPATCH(struct SwBcAperture *pAperture, NvU32 addr, NvV8 value) { + pAperture->__swbcaprtWriteReg08__(pAperture, addr, value); +} + +void swbcaprtWriteReg16_IMPL(struct SwBcAperture *pAperture, NvU32 addr, NvV16 value); + +static inline void swbcaprtWriteReg16_DISPATCH(struct SwBcAperture *pAperture, NvU32 addr, NvV16 value) { + pAperture->__swbcaprtWriteReg16__(pAperture, addr, value); +} + +void swbcaprtWriteReg32_IMPL(struct SwBcAperture *pAperture, NvU32 addr, NvV32 value); + +static inline void swbcaprtWriteReg32_DISPATCH(struct SwBcAperture *pAperture, NvU32 addr, NvV32 value) { + pAperture->__swbcaprtWriteReg32__(pAperture, addr, value); +} + +void swbcaprtWriteReg32Uc_IMPL(struct SwBcAperture *pAperture, NvU32 addr, NvV32 value); + +static inline void swbcaprtWriteReg32Uc_DISPATCH(struct SwBcAperture *pAperture, NvU32 addr, NvV32 value) { + pAperture->__swbcaprtWriteReg32Uc__(pAperture, addr, value); +} + +NvBool swbcaprtIsRegValid_IMPL(struct SwBcAperture *pAperture, NvU32 addr); + +static inline NvBool swbcaprtIsRegValid_DISPATCH(struct SwBcAperture *pAperture, NvU32 addr) { + return pAperture->__swbcaprtIsRegValid__(pAperture, addr); +} + +NV_STATUS swbcaprtConstruct_IMPL(struct SwBcAperture *arg_pAperture, struct IoAperture *arg_pApertures, NvU32 arg_numApertures); + +#define __nvoc_swbcaprtConstruct(arg_pAperture, arg_pApertures, arg_numApertures) swbcaprtConstruct_IMPL(arg_pAperture, arg_pApertures, arg_numApertures) +#undef PRIVATE_FIELD + + +#endif // _GPU_ACCESS_H_ + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_GPU_ACCESS_NVOC_H_ diff --git a/src/nvidia/generated/g_gpu_acct_nvoc.c b/src/nvidia/generated/g_gpu_acct_nvoc.c index 4e9d9eb1b..aa519c9dc 100644 --- a/src/nvidia/generated/g_gpu_acct_nvoc.c +++ b/src/nvidia/generated/g_gpu_acct_nvoc.c @@ -114,13 +114,16 @@ NV_STATUS __nvoc_objCreate_GpuAccounting(GpuAccounting **ppThis, Dynamic *pParen Object *pParentObj; GpuAccounting *pThis; - pThis = portMemAllocNonPaged(sizeof(GpuAccounting)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(GpuAccounting), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(GpuAccounting)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_GpuAccounting); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -136,11 +139,17 @@ NV_STATUS __nvoc_objCreate_GpuAccounting(GpuAccounting **ppThis, Dynamic *pParen if (status != NV_OK) goto __nvoc_objCreate_GpuAccounting_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_GpuAccounting_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(GpuAccounting)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_gpu_boost_mgr_nvoc.c b/src/nvidia/generated/g_gpu_boost_mgr_nvoc.c index e812acf3e..aee661c35 100644 --- a/src/nvidia/generated/g_gpu_boost_mgr_nvoc.c +++ b/src/nvidia/generated/g_gpu_boost_mgr_nvoc.c @@ -114,13 +114,16 @@ NV_STATUS __nvoc_objCreate_OBJGPUBOOSTMGR(OBJGPUBOOSTMGR **ppThis, Dynamic *pPar Object *pParentObj; OBJGPUBOOSTMGR *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJGPUBOOSTMGR)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJGPUBOOSTMGR), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJGPUBOOSTMGR)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJGPUBOOSTMGR); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -136,11 +139,17 @@ NV_STATUS __nvoc_objCreate_OBJGPUBOOSTMGR(OBJGPUBOOSTMGR **ppThis, Dynamic *pPar if (status != NV_OK) goto __nvoc_objCreate_OBJGPUBOOSTMGR_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJGPUBOOSTMGR_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJGPUBOOSTMGR)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_gpu_db_nvoc.c b/src/nvidia/generated/g_gpu_db_nvoc.c index b1d3150e3..f39488484 100644 --- a/src/nvidia/generated/g_gpu_db_nvoc.c +++ b/src/nvidia/generated/g_gpu_db_nvoc.c @@ -114,13 +114,16 @@ NV_STATUS __nvoc_objCreate_GpuDb(GpuDb **ppThis, Dynamic *pParent, NvU32 createF Object *pParentObj; GpuDb *pThis; - pThis = portMemAllocNonPaged(sizeof(GpuDb)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(GpuDb), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(GpuDb)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_GpuDb); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -136,11 +139,17 @@ NV_STATUS __nvoc_objCreate_GpuDb(GpuDb **ppThis, Dynamic *pParent, NvU32 createF if (status != NV_OK) goto __nvoc_objCreate_GpuDb_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_GpuDb_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(GpuDb)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_gpu_group_nvoc.c b/src/nvidia/generated/g_gpu_group_nvoc.c index 3e792c4f8..984180beb 100644 --- a/src/nvidia/generated/g_gpu_group_nvoc.c +++ b/src/nvidia/generated/g_gpu_group_nvoc.c @@ -108,13 +108,16 @@ NV_STATUS __nvoc_objCreate_OBJGPUGRP(OBJGPUGRP **ppThis, Dynamic *pParent, NvU32 Object *pParentObj; OBJGPUGRP *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJGPUGRP)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJGPUGRP), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJGPUGRP)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJGPUGRP); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -130,11 +133,17 @@ NV_STATUS __nvoc_objCreate_OBJGPUGRP(OBJGPUGRP **ppThis, Dynamic *pParent, NvU32 if (status != NV_OK) goto __nvoc_objCreate_OBJGPUGRP_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJGPUGRP_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJGPUGRP)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_gpu_instance_subscription_nvoc.c b/src/nvidia/generated/g_gpu_instance_subscription_nvoc.c index 70da87a7c..0c4743d6e 100644 --- a/src/nvidia/generated/g_gpu_instance_subscription_nvoc.c +++ b/src/nvidia/generated/g_gpu_instance_subscription_nvoc.c @@ -101,6 +101,54 @@ static NvBool __nvoc_thunk_GpuResource_gisubscriptionShareCallback(struct GPUIns return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GPUInstanceSubscription_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } +static NV_STATUS __nvoc_thunk_RmResource_gisubscriptionCheckMemInterUnmap(struct GPUInstanceSubscription *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GPUInstanceSubscription_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_gisubscriptionMapTo(struct GPUInstanceSubscription *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_gisubscriptionGetMapAddrSpace(struct GPUInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GPUInstanceSubscription_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_gisubscriptionGetRefCount(struct GPUInstanceSubscription *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_gisubscriptionAddAdditionalDependants(struct RsClient *pClient, struct GPUInstanceSubscription *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_gisubscriptionControl_Prologue(struct GPUInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_gisubscriptionGetRegBaseOffsetAndSize(struct GPUInstanceSubscription *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GPUInstanceSubscription_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_gisubscriptionInternalControlForward(struct GPUInstanceSubscription *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GPUInstanceSubscription_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_gisubscriptionUnmapFrom(struct GPUInstanceSubscription *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_gisubscriptionControl_Epilogue(struct GPUInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_gisubscriptionControlLookup(struct GPUInstanceSubscription *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset), pParams, ppEntry); +} + +static NvHandle __nvoc_thunk_GpuResource_gisubscriptionGetInternalObjectHandle(struct GPUInstanceSubscription *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GPUInstanceSubscription_GpuResource.offset)); +} + static NV_STATUS __nvoc_thunk_GpuResource_gisubscriptionControl(struct GPUInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GPUInstanceSubscription_GpuResource.offset), pCallContext, pParams); } @@ -117,64 +165,24 @@ static NV_STATUS __nvoc_thunk_RmResource_gisubscriptionGetMemoryMappingDescripto return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GPUInstanceSubscription_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_GpuResource_gisubscriptionGetMapAddrSpace(struct GPUInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GPUInstanceSubscription_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvHandle __nvoc_thunk_GpuResource_gisubscriptionGetInternalObjectHandle(struct GPUInstanceSubscription *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GPUInstanceSubscription_GpuResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_gisubscriptionControlFilter(struct GPUInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_gisubscriptionAddAdditionalDependants(struct RsClient *pClient, struct GPUInstanceSubscription *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_gisubscriptionGetRefCount(struct GPUInstanceSubscription *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RmResource_gisubscriptionCheckMemInterUnmap(struct GPUInstanceSubscription *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GPUInstanceSubscription_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_gisubscriptionMapTo(struct GPUInstanceSubscription *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_gisubscriptionControl_Prologue(struct GPUInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_GpuResource_gisubscriptionGetRegBaseOffsetAndSize(struct GPUInstanceSubscription *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GPUInstanceSubscription_GpuResource.offset), pGpu, pOffset, pSize); -} - -static NV_STATUS __nvoc_thunk_GpuResource_gisubscriptionInternalControlForward(struct GPUInstanceSubscription *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GPUInstanceSubscription_GpuResource.offset), command, pParams, size); +static NV_STATUS __nvoc_thunk_RmResource_gisubscriptionControlSerialization_Prologue(struct GPUInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RmResource.offset), pCallContext, pParams); } static void __nvoc_thunk_RsResource_gisubscriptionPreDestruct(struct GPUInstanceSubscription *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_gisubscriptionUnmapFrom(struct GPUInstanceSubscription *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_gisubscriptionIsDuplicate(struct GPUInstanceSubscription *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset), hMemory, pDuplicate); } -static void __nvoc_thunk_RmResource_gisubscriptionControl_Epilogue(struct GPUInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_gisubscriptionControlLookup(struct GPUInstanceSubscription *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_gisubscriptionControlSerialization_Epilogue(struct GPUInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_gisubscriptionMap(struct GPUInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -372,6 +380,30 @@ static void __nvoc_init_funcTable_GPUInstanceSubscription_1(GPUInstanceSubscript pThis->__gisubscriptionShareCallback__ = &__nvoc_thunk_GpuResource_gisubscriptionShareCallback; + pThis->__gisubscriptionCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_gisubscriptionCheckMemInterUnmap; + + pThis->__gisubscriptionMapTo__ = &__nvoc_thunk_RsResource_gisubscriptionMapTo; + + pThis->__gisubscriptionGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_gisubscriptionGetMapAddrSpace; + + pThis->__gisubscriptionGetRefCount__ = &__nvoc_thunk_RsResource_gisubscriptionGetRefCount; + + pThis->__gisubscriptionAddAdditionalDependants__ = &__nvoc_thunk_RsResource_gisubscriptionAddAdditionalDependants; + + pThis->__gisubscriptionControl_Prologue__ = &__nvoc_thunk_RmResource_gisubscriptionControl_Prologue; + + pThis->__gisubscriptionGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_gisubscriptionGetRegBaseOffsetAndSize; + + pThis->__gisubscriptionInternalControlForward__ = &__nvoc_thunk_GpuResource_gisubscriptionInternalControlForward; + + pThis->__gisubscriptionUnmapFrom__ = &__nvoc_thunk_RsResource_gisubscriptionUnmapFrom; + + pThis->__gisubscriptionControl_Epilogue__ = &__nvoc_thunk_RmResource_gisubscriptionControl_Epilogue; + + pThis->__gisubscriptionControlLookup__ = &__nvoc_thunk_RsResource_gisubscriptionControlLookup; + + pThis->__gisubscriptionGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_gisubscriptionGetInternalObjectHandle; + pThis->__gisubscriptionControl__ = &__nvoc_thunk_GpuResource_gisubscriptionControl; pThis->__gisubscriptionUnmap__ = &__nvoc_thunk_GpuResource_gisubscriptionUnmap; @@ -380,35 +412,15 @@ static void __nvoc_init_funcTable_GPUInstanceSubscription_1(GPUInstanceSubscript pThis->__gisubscriptionGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_gisubscriptionGetMemoryMappingDescriptor; - pThis->__gisubscriptionGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_gisubscriptionGetMapAddrSpace; - - pThis->__gisubscriptionGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_gisubscriptionGetInternalObjectHandle; - pThis->__gisubscriptionControlFilter__ = &__nvoc_thunk_RsResource_gisubscriptionControlFilter; - pThis->__gisubscriptionAddAdditionalDependants__ = &__nvoc_thunk_RsResource_gisubscriptionAddAdditionalDependants; - - pThis->__gisubscriptionGetRefCount__ = &__nvoc_thunk_RsResource_gisubscriptionGetRefCount; - - pThis->__gisubscriptionCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_gisubscriptionCheckMemInterUnmap; - - pThis->__gisubscriptionMapTo__ = &__nvoc_thunk_RsResource_gisubscriptionMapTo; - - pThis->__gisubscriptionControl_Prologue__ = &__nvoc_thunk_RmResource_gisubscriptionControl_Prologue; - - pThis->__gisubscriptionGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_gisubscriptionGetRegBaseOffsetAndSize; - - pThis->__gisubscriptionInternalControlForward__ = &__nvoc_thunk_GpuResource_gisubscriptionInternalControlForward; + pThis->__gisubscriptionControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_gisubscriptionControlSerialization_Prologue; pThis->__gisubscriptionPreDestruct__ = &__nvoc_thunk_RsResource_gisubscriptionPreDestruct; - pThis->__gisubscriptionUnmapFrom__ = &__nvoc_thunk_RsResource_gisubscriptionUnmapFrom; - pThis->__gisubscriptionIsDuplicate__ = &__nvoc_thunk_RsResource_gisubscriptionIsDuplicate; - pThis->__gisubscriptionControl_Epilogue__ = &__nvoc_thunk_RmResource_gisubscriptionControl_Epilogue; - - pThis->__gisubscriptionControlLookup__ = &__nvoc_thunk_RsResource_gisubscriptionControlLookup; + pThis->__gisubscriptionControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_gisubscriptionControlSerialization_Epilogue; pThis->__gisubscriptionMap__ = &__nvoc_thunk_GpuResource_gisubscriptionMap; @@ -436,13 +448,16 @@ NV_STATUS __nvoc_objCreate_GPUInstanceSubscription(GPUInstanceSubscription **ppT Object *pParentObj; GPUInstanceSubscription *pThis; - pThis = portMemAllocNonPaged(sizeof(GPUInstanceSubscription)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(GPUInstanceSubscription), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(GPUInstanceSubscription)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_GPUInstanceSubscription); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -458,11 +473,17 @@ NV_STATUS __nvoc_objCreate_GPUInstanceSubscription(GPUInstanceSubscription **ppT if (status != NV_OK) goto __nvoc_objCreate_GPUInstanceSubscription_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_GPUInstanceSubscription_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(GPUInstanceSubscription)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_gpu_instance_subscription_nvoc.h b/src/nvidia/generated/g_gpu_instance_subscription_nvoc.h index bb1031b45..6bb624b69 100644 --- a/src/nvidia/generated/g_gpu_instance_subscription_nvoc.h +++ b/src/nvidia/generated/g_gpu_instance_subscription_nvoc.h @@ -72,25 +72,27 @@ struct GPUInstanceSubscription { NV_STATUS (*__gisubscriptionCtrlCmdExecPartitionsExport__)(struct GPUInstanceSubscription *, NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS *); NV_STATUS (*__gisubscriptionCtrlCmdExecPartitionsImport__)(struct GPUInstanceSubscription *, NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS *); NvBool (*__gisubscriptionShareCallback__)(struct GPUInstanceSubscription *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__gisubscriptionCheckMemInterUnmap__)(struct GPUInstanceSubscription *, NvBool); + NV_STATUS (*__gisubscriptionMapTo__)(struct GPUInstanceSubscription *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__gisubscriptionGetMapAddrSpace__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__gisubscriptionGetRefCount__)(struct GPUInstanceSubscription *); + void (*__gisubscriptionAddAdditionalDependants__)(struct RsClient *, struct GPUInstanceSubscription *, RsResourceRef *); + NV_STATUS (*__gisubscriptionControl_Prologue__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__gisubscriptionGetRegBaseOffsetAndSize__)(struct GPUInstanceSubscription *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__gisubscriptionInternalControlForward__)(struct GPUInstanceSubscription *, NvU32, void *, NvU32); + NV_STATUS (*__gisubscriptionUnmapFrom__)(struct GPUInstanceSubscription *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__gisubscriptionControl_Epilogue__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__gisubscriptionControlLookup__)(struct GPUInstanceSubscription *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__gisubscriptionGetInternalObjectHandle__)(struct GPUInstanceSubscription *); NV_STATUS (*__gisubscriptionControl__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__gisubscriptionUnmap__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__gisubscriptionGetMemInterMapParams__)(struct GPUInstanceSubscription *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__gisubscriptionGetMemoryMappingDescriptor__)(struct GPUInstanceSubscription *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__gisubscriptionGetMapAddrSpace__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__gisubscriptionGetInternalObjectHandle__)(struct GPUInstanceSubscription *); NV_STATUS (*__gisubscriptionControlFilter__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__gisubscriptionAddAdditionalDependants__)(struct RsClient *, struct GPUInstanceSubscription *, RsResourceRef *); - NvU32 (*__gisubscriptionGetRefCount__)(struct GPUInstanceSubscription *); - NV_STATUS (*__gisubscriptionCheckMemInterUnmap__)(struct GPUInstanceSubscription *, NvBool); - NV_STATUS (*__gisubscriptionMapTo__)(struct GPUInstanceSubscription *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__gisubscriptionControl_Prologue__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__gisubscriptionGetRegBaseOffsetAndSize__)(struct GPUInstanceSubscription *, struct OBJGPU *, NvU32 *, NvU32 *); - NV_STATUS (*__gisubscriptionInternalControlForward__)(struct GPUInstanceSubscription *, NvU32, void *, NvU32); + NV_STATUS (*__gisubscriptionControlSerialization_Prologue__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__gisubscriptionPreDestruct__)(struct GPUInstanceSubscription *); - NV_STATUS (*__gisubscriptionUnmapFrom__)(struct GPUInstanceSubscription *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__gisubscriptionIsDuplicate__)(struct GPUInstanceSubscription *, NvHandle, NvBool *); - void (*__gisubscriptionControl_Epilogue__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__gisubscriptionControlLookup__)(struct GPUInstanceSubscription *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__gisubscriptionControlSerialization_Epilogue__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__gisubscriptionMap__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__gisubscriptionAccessCallback__)(struct GPUInstanceSubscription *, struct RsClient *, void *, RsAccessRight); KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance; @@ -136,25 +138,27 @@ NV_STATUS __nvoc_objCreate_GPUInstanceSubscription(GPUInstanceSubscription**, Dy #define gisubscriptionCtrlCmdExecPartitionsExport(arg0, arg1) gisubscriptionCtrlCmdExecPartitionsExport_DISPATCH(arg0, arg1) #define gisubscriptionCtrlCmdExecPartitionsImport(arg0, arg1) gisubscriptionCtrlCmdExecPartitionsImport_DISPATCH(arg0, arg1) #define gisubscriptionShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) gisubscriptionShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define gisubscriptionCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) gisubscriptionCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define gisubscriptionMapTo(pResource, pParams) gisubscriptionMapTo_DISPATCH(pResource, pParams) +#define gisubscriptionGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) gisubscriptionGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define gisubscriptionGetRefCount(pResource) gisubscriptionGetRefCount_DISPATCH(pResource) +#define gisubscriptionAddAdditionalDependants(pClient, pResource, pReference) gisubscriptionAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define gisubscriptionControl_Prologue(pResource, pCallContext, pParams) gisubscriptionControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define gisubscriptionGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) gisubscriptionGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define gisubscriptionInternalControlForward(pGpuResource, command, pParams, size) gisubscriptionInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define gisubscriptionUnmapFrom(pResource, pParams) gisubscriptionUnmapFrom_DISPATCH(pResource, pParams) +#define gisubscriptionControl_Epilogue(pResource, pCallContext, pParams) gisubscriptionControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define gisubscriptionControlLookup(pResource, pParams, ppEntry) gisubscriptionControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define gisubscriptionGetInternalObjectHandle(pGpuResource) gisubscriptionGetInternalObjectHandle_DISPATCH(pGpuResource) #define gisubscriptionControl(pGpuResource, pCallContext, pParams) gisubscriptionControl_DISPATCH(pGpuResource, pCallContext, pParams) #define gisubscriptionUnmap(pGpuResource, pCallContext, pCpuMapping) gisubscriptionUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define gisubscriptionGetMemInterMapParams(pRmResource, pParams) gisubscriptionGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define gisubscriptionGetMemoryMappingDescriptor(pRmResource, ppMemDesc) gisubscriptionGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define gisubscriptionGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) gisubscriptionGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define gisubscriptionGetInternalObjectHandle(pGpuResource) gisubscriptionGetInternalObjectHandle_DISPATCH(pGpuResource) #define gisubscriptionControlFilter(pResource, pCallContext, pParams) gisubscriptionControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define gisubscriptionAddAdditionalDependants(pClient, pResource, pReference) gisubscriptionAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define gisubscriptionGetRefCount(pResource) gisubscriptionGetRefCount_DISPATCH(pResource) -#define gisubscriptionCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) gisubscriptionCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define gisubscriptionMapTo(pResource, pParams) gisubscriptionMapTo_DISPATCH(pResource, pParams) -#define gisubscriptionControl_Prologue(pResource, pCallContext, pParams) gisubscriptionControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define gisubscriptionGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) gisubscriptionGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) -#define gisubscriptionInternalControlForward(pGpuResource, command, pParams, size) gisubscriptionInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define gisubscriptionControlSerialization_Prologue(pResource, pCallContext, pParams) gisubscriptionControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define gisubscriptionPreDestruct(pResource) gisubscriptionPreDestruct_DISPATCH(pResource) -#define gisubscriptionUnmapFrom(pResource, pParams) gisubscriptionUnmapFrom_DISPATCH(pResource, pParams) #define gisubscriptionIsDuplicate(pResource, hMemory, pDuplicate) gisubscriptionIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) -#define gisubscriptionControl_Epilogue(pResource, pCallContext, pParams) gisubscriptionControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define gisubscriptionControlLookup(pResource, pParams, ppEntry) gisubscriptionControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define gisubscriptionControlSerialization_Epilogue(pResource, pCallContext, pParams) gisubscriptionControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define gisubscriptionMap(pGpuResource, pCallContext, pParams, pCpuMapping) gisubscriptionMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define gisubscriptionAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) gisubscriptionAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool gisubscriptionCanCopy_IMPL(struct GPUInstanceSubscription *arg0); @@ -209,6 +213,54 @@ static inline NvBool gisubscriptionShareCallback_DISPATCH(struct GPUInstanceSubs return pGpuResource->__gisubscriptionShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } +static inline NV_STATUS gisubscriptionCheckMemInterUnmap_DISPATCH(struct GPUInstanceSubscription *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__gisubscriptionCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS gisubscriptionMapTo_DISPATCH(struct GPUInstanceSubscription *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__gisubscriptionMapTo__(pResource, pParams); +} + +static inline NV_STATUS gisubscriptionGetMapAddrSpace_DISPATCH(struct GPUInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__gisubscriptionGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 gisubscriptionGetRefCount_DISPATCH(struct GPUInstanceSubscription *pResource) { + return pResource->__gisubscriptionGetRefCount__(pResource); +} + +static inline void gisubscriptionAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct GPUInstanceSubscription *pResource, RsResourceRef *pReference) { + pResource->__gisubscriptionAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS gisubscriptionControl_Prologue_DISPATCH(struct GPUInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__gisubscriptionControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS gisubscriptionGetRegBaseOffsetAndSize_DISPATCH(struct GPUInstanceSubscription *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__gisubscriptionGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS gisubscriptionInternalControlForward_DISPATCH(struct GPUInstanceSubscription *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__gisubscriptionInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS gisubscriptionUnmapFrom_DISPATCH(struct GPUInstanceSubscription *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__gisubscriptionUnmapFrom__(pResource, pParams); +} + +static inline void gisubscriptionControl_Epilogue_DISPATCH(struct GPUInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__gisubscriptionControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS gisubscriptionControlLookup_DISPATCH(struct GPUInstanceSubscription *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__gisubscriptionControlLookup__(pResource, pParams, ppEntry); +} + +static inline NvHandle gisubscriptionGetInternalObjectHandle_DISPATCH(struct GPUInstanceSubscription *pGpuResource) { + return pGpuResource->__gisubscriptionGetInternalObjectHandle__(pGpuResource); +} + static inline NV_STATUS gisubscriptionControl_DISPATCH(struct GPUInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pGpuResource->__gisubscriptionControl__(pGpuResource, pCallContext, pParams); } @@ -225,64 +277,24 @@ static inline NV_STATUS gisubscriptionGetMemoryMappingDescriptor_DISPATCH(struct return pRmResource->__gisubscriptionGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS gisubscriptionGetMapAddrSpace_DISPATCH(struct GPUInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__gisubscriptionGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvHandle gisubscriptionGetInternalObjectHandle_DISPATCH(struct GPUInstanceSubscription *pGpuResource) { - return pGpuResource->__gisubscriptionGetInternalObjectHandle__(pGpuResource); -} - static inline NV_STATUS gisubscriptionControlFilter_DISPATCH(struct GPUInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__gisubscriptionControlFilter__(pResource, pCallContext, pParams); } -static inline void gisubscriptionAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct GPUInstanceSubscription *pResource, RsResourceRef *pReference) { - pResource->__gisubscriptionAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 gisubscriptionGetRefCount_DISPATCH(struct GPUInstanceSubscription *pResource) { - return pResource->__gisubscriptionGetRefCount__(pResource); -} - -static inline NV_STATUS gisubscriptionCheckMemInterUnmap_DISPATCH(struct GPUInstanceSubscription *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__gisubscriptionCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS gisubscriptionMapTo_DISPATCH(struct GPUInstanceSubscription *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__gisubscriptionMapTo__(pResource, pParams); -} - -static inline NV_STATUS gisubscriptionControl_Prologue_DISPATCH(struct GPUInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__gisubscriptionControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS gisubscriptionGetRegBaseOffsetAndSize_DISPATCH(struct GPUInstanceSubscription *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__gisubscriptionGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); -} - -static inline NV_STATUS gisubscriptionInternalControlForward_DISPATCH(struct GPUInstanceSubscription *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__gisubscriptionInternalControlForward__(pGpuResource, command, pParams, size); +static inline NV_STATUS gisubscriptionControlSerialization_Prologue_DISPATCH(struct GPUInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__gisubscriptionControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline void gisubscriptionPreDestruct_DISPATCH(struct GPUInstanceSubscription *pResource) { pResource->__gisubscriptionPreDestruct__(pResource); } -static inline NV_STATUS gisubscriptionUnmapFrom_DISPATCH(struct GPUInstanceSubscription *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__gisubscriptionUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS gisubscriptionIsDuplicate_DISPATCH(struct GPUInstanceSubscription *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__gisubscriptionIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline void gisubscriptionControl_Epilogue_DISPATCH(struct GPUInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__gisubscriptionControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS gisubscriptionControlLookup_DISPATCH(struct GPUInstanceSubscription *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__gisubscriptionControlLookup__(pResource, pParams, ppEntry); +static inline void gisubscriptionControlSerialization_Epilogue_DISPATCH(struct GPUInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__gisubscriptionControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS gisubscriptionMap_DISPATCH(struct GPUInstanceSubscription *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_gpu_mgmt_api_nvoc.c b/src/nvidia/generated/g_gpu_mgmt_api_nvoc.c index de8999db4..627c208e7 100644 --- a/src/nvidia/generated/g_gpu_mgmt_api_nvoc.c +++ b/src/nvidia/generated/g_gpu_mgmt_api_nvoc.c @@ -116,8 +116,12 @@ static void __nvoc_thunk_RsResource_gpumgmtapiAddAdditionalDependants(struct RsC resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_gpumgmtapiUnmap(struct GpuManagementApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RsResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_gpumgmtapiUnmapFrom(struct GpuManagementApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_gpumgmtapiControlSerialization_Prologue(struct GpuManagementApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_RmResource_gpumgmtapiControl_Prologue(struct GpuManagementApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -128,22 +132,26 @@ static NvBool __nvoc_thunk_RsResource_gpumgmtapiCanCopy(struct GpuManagementApi return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_gpumgmtapiMapTo(struct GpuManagementApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_gpumgmtapiUnmap(struct GpuManagementApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RsResource.offset), pCallContext, pCpuMapping); } static void __nvoc_thunk_RsResource_gpumgmtapiPreDestruct(struct GpuManagementApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_gpumgmtapiUnmapFrom(struct GpuManagementApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_gpumgmtapiMapTo(struct GpuManagementApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_RsResource_gpumgmtapiIsDuplicate(struct GpuManagementApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_gpumgmtapiControlSerialization_Epilogue(struct GpuManagementApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RmResource.offset), pCallContext, pParams); +} + static void __nvoc_thunk_RmResource_gpumgmtapiControl_Epilogue(struct GpuManagementApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RmResource.offset), pCallContext, pParams); } @@ -243,20 +251,24 @@ static void __nvoc_init_funcTable_GpuManagementApi_1(GpuManagementApi *pThis) { pThis->__gpumgmtapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_gpumgmtapiAddAdditionalDependants; - pThis->__gpumgmtapiUnmap__ = &__nvoc_thunk_RsResource_gpumgmtapiUnmap; + pThis->__gpumgmtapiUnmapFrom__ = &__nvoc_thunk_RsResource_gpumgmtapiUnmapFrom; + + pThis->__gpumgmtapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_gpumgmtapiControlSerialization_Prologue; pThis->__gpumgmtapiControl_Prologue__ = &__nvoc_thunk_RmResource_gpumgmtapiControl_Prologue; pThis->__gpumgmtapiCanCopy__ = &__nvoc_thunk_RsResource_gpumgmtapiCanCopy; - pThis->__gpumgmtapiMapTo__ = &__nvoc_thunk_RsResource_gpumgmtapiMapTo; + pThis->__gpumgmtapiUnmap__ = &__nvoc_thunk_RsResource_gpumgmtapiUnmap; pThis->__gpumgmtapiPreDestruct__ = &__nvoc_thunk_RsResource_gpumgmtapiPreDestruct; - pThis->__gpumgmtapiUnmapFrom__ = &__nvoc_thunk_RsResource_gpumgmtapiUnmapFrom; + pThis->__gpumgmtapiMapTo__ = &__nvoc_thunk_RsResource_gpumgmtapiMapTo; pThis->__gpumgmtapiIsDuplicate__ = &__nvoc_thunk_RsResource_gpumgmtapiIsDuplicate; + pThis->__gpumgmtapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_gpumgmtapiControlSerialization_Epilogue; + pThis->__gpumgmtapiControl_Epilogue__ = &__nvoc_thunk_RmResource_gpumgmtapiControl_Epilogue; pThis->__gpumgmtapiControlLookup__ = &__nvoc_thunk_RsResource_gpumgmtapiControlLookup; @@ -286,13 +298,16 @@ NV_STATUS __nvoc_objCreate_GpuManagementApi(GpuManagementApi **ppThis, Dynamic * Object *pParentObj; GpuManagementApi *pThis; - pThis = portMemAllocNonPaged(sizeof(GpuManagementApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(GpuManagementApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(GpuManagementApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_GpuManagementApi); + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -308,11 +323,17 @@ NV_STATUS __nvoc_objCreate_GpuManagementApi(GpuManagementApi **ppThis, Dynamic * if (status != NV_OK) goto __nvoc_objCreate_GpuManagementApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_GpuManagementApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(GpuManagementApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_gpu_mgmt_api_nvoc.h b/src/nvidia/generated/g_gpu_mgmt_api_nvoc.h index ff5a5d82c..3013a2178 100644 --- a/src/nvidia/generated/g_gpu_mgmt_api_nvoc.h +++ b/src/nvidia/generated/g_gpu_mgmt_api_nvoc.h @@ -69,13 +69,15 @@ struct GpuManagementApi { NvU32 (*__gpumgmtapiGetRefCount__)(struct GpuManagementApi *); NV_STATUS (*__gpumgmtapiControlFilter__)(struct GpuManagementApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__gpumgmtapiAddAdditionalDependants__)(struct RsClient *, struct GpuManagementApi *, RsResourceRef *); - NV_STATUS (*__gpumgmtapiUnmap__)(struct GpuManagementApi *, struct CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__gpumgmtapiUnmapFrom__)(struct GpuManagementApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__gpumgmtapiControlSerialization_Prologue__)(struct GpuManagementApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__gpumgmtapiControl_Prologue__)(struct GpuManagementApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__gpumgmtapiCanCopy__)(struct GpuManagementApi *); - NV_STATUS (*__gpumgmtapiMapTo__)(struct GpuManagementApi *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__gpumgmtapiUnmap__)(struct GpuManagementApi *, struct CALL_CONTEXT *, RsCpuMapping *); void (*__gpumgmtapiPreDestruct__)(struct GpuManagementApi *); - NV_STATUS (*__gpumgmtapiUnmapFrom__)(struct GpuManagementApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__gpumgmtapiMapTo__)(struct GpuManagementApi *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__gpumgmtapiIsDuplicate__)(struct GpuManagementApi *, NvHandle, NvBool *); + void (*__gpumgmtapiControlSerialization_Epilogue__)(struct GpuManagementApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__gpumgmtapiControl_Epilogue__)(struct GpuManagementApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__gpumgmtapiControlLookup__)(struct GpuManagementApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__gpumgmtapiMap__)(struct GpuManagementApi *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -119,13 +121,15 @@ NV_STATUS __nvoc_objCreate_GpuManagementApi(GpuManagementApi**, Dynamic*, NvU32, #define gpumgmtapiGetRefCount(pResource) gpumgmtapiGetRefCount_DISPATCH(pResource) #define gpumgmtapiControlFilter(pResource, pCallContext, pParams) gpumgmtapiControlFilter_DISPATCH(pResource, pCallContext, pParams) #define gpumgmtapiAddAdditionalDependants(pClient, pResource, pReference) gpumgmtapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define gpumgmtapiUnmap(pResource, pCallContext, pCpuMapping) gpumgmtapiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define gpumgmtapiUnmapFrom(pResource, pParams) gpumgmtapiUnmapFrom_DISPATCH(pResource, pParams) +#define gpumgmtapiControlSerialization_Prologue(pResource, pCallContext, pParams) gpumgmtapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define gpumgmtapiControl_Prologue(pResource, pCallContext, pParams) gpumgmtapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define gpumgmtapiCanCopy(pResource) gpumgmtapiCanCopy_DISPATCH(pResource) -#define gpumgmtapiMapTo(pResource, pParams) gpumgmtapiMapTo_DISPATCH(pResource, pParams) +#define gpumgmtapiUnmap(pResource, pCallContext, pCpuMapping) gpumgmtapiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define gpumgmtapiPreDestruct(pResource) gpumgmtapiPreDestruct_DISPATCH(pResource) -#define gpumgmtapiUnmapFrom(pResource, pParams) gpumgmtapiUnmapFrom_DISPATCH(pResource, pParams) +#define gpumgmtapiMapTo(pResource, pParams) gpumgmtapiMapTo_DISPATCH(pResource, pParams) #define gpumgmtapiIsDuplicate(pResource, hMemory, pDuplicate) gpumgmtapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define gpumgmtapiControlSerialization_Epilogue(pResource, pCallContext, pParams) gpumgmtapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define gpumgmtapiControl_Epilogue(pResource, pCallContext, pParams) gpumgmtapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define gpumgmtapiControlLookup(pResource, pParams, ppEntry) gpumgmtapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define gpumgmtapiMap(pResource, pCallContext, pParams, pCpuMapping) gpumgmtapiMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -168,8 +172,12 @@ static inline void gpumgmtapiAddAdditionalDependants_DISPATCH(struct RsClient *p pResource->__gpumgmtapiAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS gpumgmtapiUnmap_DISPATCH(struct GpuManagementApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pResource->__gpumgmtapiUnmap__(pResource, pCallContext, pCpuMapping); +static inline NV_STATUS gpumgmtapiUnmapFrom_DISPATCH(struct GpuManagementApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__gpumgmtapiUnmapFrom__(pResource, pParams); +} + +static inline NV_STATUS gpumgmtapiControlSerialization_Prologue_DISPATCH(struct GpuManagementApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__gpumgmtapiControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS gpumgmtapiControl_Prologue_DISPATCH(struct GpuManagementApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -180,22 +188,26 @@ static inline NvBool gpumgmtapiCanCopy_DISPATCH(struct GpuManagementApi *pResour return pResource->__gpumgmtapiCanCopy__(pResource); } -static inline NV_STATUS gpumgmtapiMapTo_DISPATCH(struct GpuManagementApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__gpumgmtapiMapTo__(pResource, pParams); +static inline NV_STATUS gpumgmtapiUnmap_DISPATCH(struct GpuManagementApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__gpumgmtapiUnmap__(pResource, pCallContext, pCpuMapping); } static inline void gpumgmtapiPreDestruct_DISPATCH(struct GpuManagementApi *pResource) { pResource->__gpumgmtapiPreDestruct__(pResource); } -static inline NV_STATUS gpumgmtapiUnmapFrom_DISPATCH(struct GpuManagementApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__gpumgmtapiUnmapFrom__(pResource, pParams); +static inline NV_STATUS gpumgmtapiMapTo_DISPATCH(struct GpuManagementApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__gpumgmtapiMapTo__(pResource, pParams); } static inline NV_STATUS gpumgmtapiIsDuplicate_DISPATCH(struct GpuManagementApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__gpumgmtapiIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void gpumgmtapiControlSerialization_Epilogue_DISPATCH(struct GpuManagementApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__gpumgmtapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline void gpumgmtapiControl_Epilogue_DISPATCH(struct GpuManagementApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__gpumgmtapiControl_Epilogue__(pResource, pCallContext, pParams); } diff --git a/src/nvidia/generated/g_gpu_mgr_nvoc.c b/src/nvidia/generated/g_gpu_mgr_nvoc.c index 8f939ace5..832a2b7e8 100644 --- a/src/nvidia/generated/g_gpu_mgr_nvoc.c +++ b/src/nvidia/generated/g_gpu_mgr_nvoc.c @@ -114,13 +114,16 @@ NV_STATUS __nvoc_objCreate_OBJGPUMGR(OBJGPUMGR **ppThis, Dynamic *pParent, NvU32 Object *pParentObj; OBJGPUMGR *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJGPUMGR)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJGPUMGR), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJGPUMGR)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJGPUMGR); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -136,11 +139,17 @@ NV_STATUS __nvoc_objCreate_OBJGPUMGR(OBJGPUMGR **ppThis, Dynamic *pParent, NvU32 if (status != NV_OK) goto __nvoc_objCreate_OBJGPUMGR_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJGPUMGR_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJGPUMGR)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_gpu_mgr_nvoc.h b/src/nvidia/generated/g_gpu_mgr_nvoc.h index 1ae0e2121..9aec97a53 100644 --- a/src/nvidia/generated/g_gpu_mgr_nvoc.h +++ b/src/nvidia/generated/g_gpu_mgr_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -30,6 +30,7 @@ extern "C" { */ #include "g_gpu_mgr_nvoc.h" + #ifndef _GPUMGR_H_ #define _GPUMGR_H_ @@ -52,6 +53,8 @@ struct OBJGPU; #include "nvoc/utility.h" #include "nv_firmware_types.h" +#include "gpu_mgr/gpu_mgr_sli.h" + #include "gpu/perf/kern_perf_gpuboostsync.h" #include "utils/nvbitvector.h" @@ -78,7 +81,6 @@ TYPEDEF_BITVECTOR(MC_ENGINE_BITVECTOR); #define gpumgrGetSliLinkConnectionCount(pGpu) ((NvU32) 0) #define gpumgrGetSLIConfig(gpuInstance, onlyWithSliLink) ((NvU32) 0) #define gpumgrDisableVidLink(pGpu, head, max_dr_port) -#define gpumgrPinsetToPinsetTableIndex(pinset, pPinsetIndex) (NV_ERR_NOT_SUPPORTED) #define gpumgrGetBcEnabledStatus(g) (NV_FALSE) #define gpumgrGetBcEnabledStatusEx(g, t) (NV_FALSE) #define gpumgrSetBcEnabledStatus(g, b) do { NvBool b2 = b; (void)b2; } while (0) @@ -86,7 +88,6 @@ TYPEDEF_BITVECTOR(MC_ENGINE_BITVECTOR); #define gpumgrSLILoopReentrancyPop(pGpu) ((NvU32)0) #define gpumgrSLILoopReentrancyPush(pGpu, sliLoopReentrancy) do { NvU32 x = sliLoopReentrancy; (void)x; } while(0) - typedef struct { NvU32 gpuId; @@ -131,6 +132,23 @@ typedef struct _def_gpumgr_save_vbios_state #define SLI_BT_VIDLINK 0 #define SLI_BT_NVLINK 1 +/*! + * SLI link detection HAL flag defines for Sli/Vid/NvLink link detection HAL functions. + */ +#define GPU_LINK_DETECTION_HAL_STUB 0 +#define GPU_LINK_DETECTION_HAL_GK104 1 +#define GPU_LINK_DETECTION_HAL_GP100 2 +#define GPU_LINK_DETECTION_HAL_GP102 3 + +// +// GPU NVLINK reduced bandwidth mode +// +#define GPU_NVLINK_BW_MODE_FULL (0x0) +#define GPU_NVLINK_BW_MODE_OFF (0x1) +#define GPU_NVLINK_BW_MODE_MIN (0x2) +#define GPU_NVLINK_BW_MODE_HALF (0x3) +#define GPU_NVLINK_BW_MODE_3QUARTER (0x4) + typedef struct NVLINK_TOPOLOGY_PARAMS { NvU32 sysmemLinks; @@ -250,11 +268,13 @@ struct OBJGPUMGR { struct OBJGPUGRP *pGpuGrpTable[32]; NvU32 gpuInstMaskTable[32]; NvU8 gpuBridgeType; + NvU8 gpuSliLinkRoute[2][32][32][2]; SLI_GPU_BOOST_SYNC sliGpuBoostSync; GPUMGRSAVEVBIOSSTATE primaryVbiosState; NvU8 powerDisconnectedGpuCount; NvU8 powerDisconnectedGpuBus[32]; NVLINK_TOPOLOGY_INFO nvlinkTopologyInfo[32]; + NvU8 nvlinkBwMode; GPUMGR_SAVE_MIG_INSTANCE_TOPOLOGY MIGTopologyInfo[32]; GPU_HANDLE_ID gpuHandleIDList[32]; NvU32 numGpuHandles; @@ -341,6 +361,15 @@ NV_STATUS gpumgrSetGpuInitDisabledNvlinks_IMPL(NvU32 gpuId, NvU32 mask, NvBool b NV_STATUS gpumgrGetGpuInitDisabledNvlinks_IMPL(NvU32 gpuId, NvU32 *pMask, NvBool *pbSkipHwNvlinkDisable); #define gpumgrGetGpuInitDisabledNvlinks(gpuId, pMask, pbSkipHwNvlinkDisable) gpumgrGetGpuInitDisabledNvlinks_IMPL(gpuId, pMask, pbSkipHwNvlinkDisable) +NvU8 gpumgrGetGpuNvlinkBwMode_IMPL(void); + +#define gpumgrGetGpuNvlinkBwMode() gpumgrGetGpuNvlinkBwMode_IMPL() +void gpumgrSetGpuNvlinkBwModeFromRegistry_IMPL(struct OBJGPU *pGpu); + +#define gpumgrSetGpuNvlinkBwModeFromRegistry(pGpu) gpumgrSetGpuNvlinkBwModeFromRegistry_IMPL(pGpu) +NV_STATUS gpumgrSetGpuNvlinkBwMode_IMPL(NvU8 mode); + +#define gpumgrSetGpuNvlinkBwMode(mode) gpumgrSetGpuNvlinkBwMode_IMPL(mode) NvBool gpumgrCheckIndirectPeer_IMPL(struct OBJGPU *pGpu, struct OBJGPU *pRemoteGpu); #define gpumgrCheckIndirectPeer(pGpu, pRemoteGpu) gpumgrCheckIndirectPeer_IMPL(pGpu, pRemoteGpu) @@ -482,6 +511,7 @@ NvBool gpumgrSetGpuAcquire(OBJGPU *pGpu); void gpumgrSetGpuRelease(void); NvU8 gpumgrGetGpuBridgeType(void); NvBool gpumgrAreAllGpusInOffloadMode(void); +NvBool gpumgrIsSafeToReadGpuInfo(void); // // gpumgrIsSubDeviceCountOne diff --git a/src/nvidia/generated/g_gpu_nvoc.c b/src/nvidia/generated/g_gpu_nvoc.c index c03aa99f0..2af03a1df 100644 --- a/src/nvidia/generated/g_gpu_nvoc.c +++ b/src/nvidia/generated/g_gpu_nvoc.c @@ -199,7 +199,7 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { } // NVOC Property Hal field -- PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE, ((NvBool)(0 == 0))); } @@ -209,6 +209,12 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { pThis->setProperty(pThis, PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE, ((NvBool)(0 != 0))); } + // NVOC Property Hal field -- PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->setProperty(pThis, PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED, ((NvBool)(0 == 0))); + } + // NVOC Property Hal field -- PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { @@ -313,6 +319,12 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { { pThis->bSriovCapable = ((NvBool)(0 == 0)); } + + // Hal field -- bRecheckSliSupportAtResume + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->bRecheckSliSupportAtResume = ((NvBool)(0 == 0)); + } } NV_STATUS __nvoc_ctor_Object(Object* ); @@ -355,6 +367,20 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { PORT_UNREFERENCED_VARIABLE(rmVariantHal); PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); + // Hal function -- gpuConstructDeviceInfoTable + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->__gpuConstructDeviceInfoTable__ = &gpuConstructDeviceInfoTable_FWCLIENT; + } + // default + else + { + pThis->__gpuConstructDeviceInfoTable__ = &gpuConstructDeviceInfoTable_56cd7a; + } + } + // Hal function -- gpuWriteBusConfigReg if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { @@ -382,7 +408,7 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { } else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__gpuReadBusConfigRegEx__ = &gpuReadBusConfigRegEx_46f6a7; + pThis->__gpuReadBusConfigRegEx__ = &gpuReadBusConfigRegEx_5baef9; } // Hal function -- gpuReadFunctionConfigReg @@ -525,19 +551,23 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { { pThis->__gpuFuseSupportsDisplay__ = &gpuFuseSupportsDisplay_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__gpuFuseSupportsDisplay__ = &gpuFuseSupportsDisplay_GA100; } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ + { + pThis->__gpuFuseSupportsDisplay__ = &gpuFuseSupportsDisplay_491d52; + } // Hal function -- gpuClearFbhubPoisonIntrForBug2924523 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ { pThis->__gpuClearFbhubPoisonIntrForBug2924523__ = &gpuClearFbhubPoisonIntrForBug2924523_GA100_KERNEL; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__gpuClearFbhubPoisonIntrForBug2924523__ = &gpuClearFbhubPoisonIntrForBug2924523_56cd7a; } @@ -553,20 +583,6 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { pThis->__gpuReadDeviceId__ = &gpuReadDeviceId_GH100; } - // Hal function -- gpuConstructDeviceInfoTable - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__gpuConstructDeviceInfoTable__ = &gpuConstructDeviceInfoTable_FWCLIENT; - } - // default - else - { - pThis->__gpuConstructDeviceInfoTable__ = &gpuConstructDeviceInfoTable_56cd7a; - } - } - // Hal function -- gpuGetFlaVasSize if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { @@ -633,13 +649,16 @@ NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU **ppThis, Dynamic *pParent, NvU32 creat Object *pParentObj; OBJGPU *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJGPU)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJGPU), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJGPU)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJGPU); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -655,11 +674,17 @@ NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU **ppThis, Dynamic *pParent, NvU32 creat if (status != NV_OK) goto __nvoc_objCreate_OBJGPU_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJGPU_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJGPU)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_gpu_nvoc.h b/src/nvidia/generated/g_gpu_nvoc.h index 1b4e83d8b..6e5f1bc82 100644 --- a/src/nvidia/generated/g_gpu_nvoc.h +++ b/src/nvidia/generated/g_gpu_nvoc.h @@ -143,16 +143,16 @@ typedef struct OBJHOSTENG OBJHOSTENG; #endif /* __nvoc_class_id_OBJHOSTENG */ -struct OBJPMUCLIENT; +struct OBJPMU_CLIENT_IMPLEMENTER; -#ifndef __NVOC_CLASS_OBJPMUCLIENT_TYPEDEF__ -#define __NVOC_CLASS_OBJPMUCLIENT_TYPEDEF__ -typedef struct OBJPMUCLIENT OBJPMUCLIENT; -#endif /* __NVOC_CLASS_OBJPMUCLIENT_TYPEDEF__ */ +#ifndef __NVOC_CLASS_OBJPMU_CLIENT_IMPLEMENTER_TYPEDEF__ +#define __NVOC_CLASS_OBJPMU_CLIENT_IMPLEMENTER_TYPEDEF__ +typedef struct OBJPMU_CLIENT_IMPLEMENTER OBJPMU_CLIENT_IMPLEMENTER; +#endif /* __NVOC_CLASS_OBJPMU_CLIENT_IMPLEMENTER_TYPEDEF__ */ -#ifndef __nvoc_class_id_OBJPMUCLIENT -#define __nvoc_class_id_OBJPMUCLIENT 0xea631d -#endif /* __nvoc_class_id_OBJPMUCLIENT */ +#ifndef __nvoc_class_id_OBJPMU_CLIENT_IMPLEMENTER +#define __nvoc_class_id_OBJPMU_CLIENT_IMPLEMENTER 0x88cace +#endif /* __nvoc_class_id_OBJPMU_CLIENT_IMPLEMENTER */ struct OBJINTRABLE; @@ -338,7 +338,7 @@ typedef struct } GPU_CHILD_ITER; typedef GPU_CHILD_ITER ENGSTATE_ITER; -typedef GPU_CHILD_ITER PMUCLIENT_ITER; +typedef GPU_CHILD_ITER PMU_CLIENT_IMPLEMENTER_ITER; // // Object 'get' macros for GPU relative object retrievals. @@ -595,6 +595,13 @@ typedef struct // GPU specific data for core logic object, stored in GPU object PORTDATA boardDownstreamPort; // If there is no BR03 these data are not set. } GPUCLDATA; +// For SLI Support Using Peer Model +typedef struct +{ + OBJGPU *pGpu; // Mapping from the local pinset number (i.e. array index) to peer GPU + NvU32 pinset; // Mapping from the local pinset number (i.e. array index) to peer pinset number +} _GPU_SLI_PEER; + // // Flags for gpuStateLoad() and gpuStateUnload() routines. Flags *must* be used @@ -777,7 +784,11 @@ typedef struct // parsing the DEVICE_INFO2 table during init. // -typedef struct NV2080_CTRL_INTERNAL_DEVICE_INFO DEVICE_INFO2_TABLE; +typedef struct NV2080_CTRL_INTERNAL_DEVICE_INFO DEVICE_INFO2_ENTRY; + + +//! Value of DEV_GROUP_ID used in gpuGetDeviceEntryByType for any group ID. +#define DEVICE_INFO2_ENTRY_GROUP_ID_ANY (-1) #define NV_GPU_INTERNAL_DEVICE_HANDLE 0xABCD0080 #define NV_GPU_INTERNAL_SUBDEVICE_HANDLE 0xABCD2080 @@ -816,6 +827,7 @@ struct OBJGPU { struct RmHalspecOwner *__nvoc_pbase_RmHalspecOwner; struct OBJTRACEABLE *__nvoc_pbase_OBJTRACEABLE; struct OBJGPU *__nvoc_pbase_OBJGPU; + NV_STATUS (*__gpuConstructDeviceInfoTable__)(struct OBJGPU *); NV_STATUS (*__gpuWriteBusConfigReg__)(struct OBJGPU *, NvU32, NvU32); NV_STATUS (*__gpuReadBusConfigReg__)(struct OBJGPU *, NvU32, NvU32 *); NV_STATUS (*__gpuReadBusConfigRegEx__)(struct OBJGPU *, NvU32, NvU32 *, THREAD_STATE_NODE *); @@ -831,10 +843,11 @@ struct OBJGPU { NvBool (*__gpuFuseSupportsDisplay__)(struct OBJGPU *); NV_STATUS (*__gpuClearFbhubPoisonIntrForBug2924523__)(struct OBJGPU *); void (*__gpuReadDeviceId__)(struct OBJGPU *, NvU32 *, NvU32 *); - NV_STATUS (*__gpuConstructDeviceInfoTable__)(struct OBJGPU *); NvU64 (*__gpuGetFlaVasSize__)(struct OBJGPU *, NvBool); NvBool (*__gpuIsAtsSupportedWithSmcMemPartitioning__)(struct OBJGPU *); NvBool (*__gpuIsSliCapableWithoutDisplay__)(struct OBJGPU *); + NvBool PDB_PROP_GPU_HIGH_SPEED_BRIDGE_CONNECTED; + NvBool bVideoLinkDisabled; GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo; NvU32 moduleId; NvU8 nvswitchSupport; @@ -893,8 +906,13 @@ struct OBJGPU { NvBool PDB_PROP_GPU_DO_NOT_CHECK_REG_ACCESS_IN_PM_CODEPATH; NvBool PDB_PROP_GPU_EXTERNAL_HEAP_CONTROL; NvBool PDB_PROP_GPU_IS_MOBILE; + NvBool PDB_PROP_GPU_RTD3_GC6_SUPPORTED; NvBool PDB_PROP_GPU_RTD3_GC6_ACTIVE; NvBool PDB_PROP_GPU_FAST_GC6_ACTIVE; + NvBool PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED; + NvBool PDB_PROP_GPU_RTD3_GCOFF_SUPPORTED; + NvBool PDB_PROP_GPU_GCOFF_STATE_ENTERING; + NvBool PDB_PROP_GPU_GCOFF_STATE_ENTERED; NvBool PDB_PROP_GPU_ACCOUNTING_ON; NvBool PDB_PROP_GPU_INACCESSIBLE; NvBool PDB_PROP_GPU_NVLINK_SYSMEM; @@ -957,7 +975,7 @@ struct OBJGPU { RmPhysAddr dmaStartAddress; NvU32 gpuDeviceMapCount; DEVICE_MAPPING deviceMappings[60]; - PIO_APERTURE pIOApertures[12]; + struct IoAperture *pIOApertures[12]; DEVICE_MAPPING *pDeviceMappingsByDeviceInstance[12]; void *gpuCfgAddr; TIMEOUT_DATA timeoutData; @@ -1029,7 +1047,7 @@ struct OBJGPU { NvHandle hDefaultClientShareDevice; NvHandle hDefaultClientShareSubDevice; NvU32 externalKernelClientCount; - DEVICE_INFO2_TABLE *pDeviceInfoTable; + DEVICE_INFO2_ENTRY *pDeviceInfoTable; NvU32 numDeviceInfoEntries; NvHandle hInternalClient; NvHandle hInternalDevice; @@ -1057,7 +1075,6 @@ struct OBJGPU { NvBool bIsVirtualWithSriov; NvU32 P2PPeerGpuCount; GPU_P2P_PEER_GPU_CAPS P2PPeerGpuCaps[32]; - NvBool bCpuFirmwareHandlesFbEccInterruptEnabled; NvBool bStateLoading; NvBool bStateUnloading; NvBool bStateLoaded; @@ -1105,6 +1122,9 @@ struct OBJGPU { NvU8 fabricProbeSlowdownThreshold; NvBool bVgpuGspPluginOffloadEnabled; NvBool bSriovCapable; + NvBool bRecheckSliSupportAtResume; + _GPU_SLI_PEER peer[2]; + NvBool bIsGspOwnedFaultBuffersEnabled; }; #ifndef __NVOC_CLASS_OBJGPU_TYPEDEF__ @@ -1130,6 +1150,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; #define PDB_PROP_GPU_EXTERNAL_HEAP_CONTROL_BASE_CAST #define PDB_PROP_GPU_EXTERNAL_HEAP_CONTROL_BASE_NAME PDB_PROP_GPU_EXTERNAL_HEAP_CONTROL +#define PDB_PROP_GPU_RTD3_GC6_SUPPORTED_BASE_CAST +#define PDB_PROP_GPU_RTD3_GC6_SUPPORTED_BASE_NAME PDB_PROP_GPU_RTD3_GC6_SUPPORTED #define PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU_BASE_CAST #define PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU_BASE_NAME PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU #define PDB_PROP_GPU_INACCESSIBLE_BASE_CAST @@ -1148,10 +1170,12 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; #define PDB_PROP_GPU_IS_COT_ENABLED_BASE_NAME PDB_PROP_GPU_IS_COT_ENABLED #define PDB_PROP_GPU_COHERENT_CPU_MAPPING_BASE_CAST #define PDB_PROP_GPU_COHERENT_CPU_MAPPING_BASE_NAME PDB_PROP_GPU_COHERENT_CPU_MAPPING -#define PDB_PROP_GPU_UPSTREAM_PORT_L0S_UNSUPPORTED_BASE_CAST -#define PDB_PROP_GPU_UPSTREAM_PORT_L0S_UNSUPPORTED_BASE_NAME PDB_PROP_GPU_UPSTREAM_PORT_L0S_UNSUPPORTED +#define PDB_PROP_GPU_HIGH_SPEED_BRIDGE_CONNECTED_BASE_CAST +#define PDB_PROP_GPU_HIGH_SPEED_BRIDGE_CONNECTED_BASE_NAME PDB_PROP_GPU_HIGH_SPEED_BRIDGE_CONNECTED #define PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY_BASE_CAST #define PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY_BASE_NAME PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY +#define PDB_PROP_GPU_UPSTREAM_PORT_L0S_UNSUPPORTED_BASE_CAST +#define PDB_PROP_GPU_UPSTREAM_PORT_L0S_UNSUPPORTED_BASE_NAME PDB_PROP_GPU_UPSTREAM_PORT_L0S_UNSUPPORTED #define PDB_PROP_GPU_SLI_LINK_ACTIVE_BASE_CAST #define PDB_PROP_GPU_SLI_LINK_ACTIVE_BASE_NAME PDB_PROP_GPU_SLI_LINK_ACTIVE #define PDB_PROP_GPU_IN_TCC_MODE_BASE_CAST @@ -1212,6 +1236,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; #define PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE_BASE_NAME PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE #define PDB_PROP_GPU_CAN_OPTIMIZE_COMPUTE_USE_CASE_BASE_CAST #define PDB_PROP_GPU_CAN_OPTIMIZE_COMPUTE_USE_CASE_BASE_NAME PDB_PROP_GPU_CAN_OPTIMIZE_COMPUTE_USE_CASE +#define PDB_PROP_GPU_GCOFF_STATE_ENTERING_BASE_CAST +#define PDB_PROP_GPU_GCOFF_STATE_ENTERING_BASE_NAME PDB_PROP_GPU_GCOFF_STATE_ENTERING #define PDB_PROP_GPU_ACCOUNTING_ON_BASE_CAST #define PDB_PROP_GPU_ACCOUNTING_ON_BASE_NAME PDB_PROP_GPU_ACCOUNTING_ON #define PDB_PROP_GPU_IN_HIBERNATE_BASE_CAST @@ -1222,6 +1248,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; #define PDB_PROP_GPU_ENABLE_IOMMU_SUPPORT_BASE_NAME PDB_PROP_GPU_ENABLE_IOMMU_SUPPORT #define PDB_PROP_GPU_IN_TIMEOUT_RECOVERY_BASE_CAST #define PDB_PROP_GPU_IN_TIMEOUT_RECOVERY_BASE_NAME PDB_PROP_GPU_IN_TIMEOUT_RECOVERY +#define PDB_PROP_GPU_GCOFF_STATE_ENTERED_BASE_CAST +#define PDB_PROP_GPU_GCOFF_STATE_ENTERED_BASE_NAME PDB_PROP_GPU_GCOFF_STATE_ENTERED #define PDB_PROP_GPU_FAST_GC6_ACTIVE_BASE_CAST #define PDB_PROP_GPU_FAST_GC6_ACTIVE_BASE_NAME PDB_PROP_GPU_FAST_GC6_ACTIVE #define PDB_PROP_GPU_IN_FULLCHIP_RESET_BASE_CAST @@ -1236,6 +1264,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; #define PDB_PROP_GPU_IS_BR03_PRESENT_BASE_NAME PDB_PROP_GPU_IS_BR03_PRESENT #define PDB_PROP_GPU_IS_GEMINI_BASE_CAST #define PDB_PROP_GPU_IS_GEMINI_BASE_NAME PDB_PROP_GPU_IS_GEMINI +#define PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED_BASE_CAST +#define PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED_BASE_NAME PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED #define PDB_PROP_GPU_STATE_INITIALIZED_BASE_CAST #define PDB_PROP_GPU_STATE_INITIALIZED_BASE_NAME PDB_PROP_GPU_STATE_INITIALIZED #define PDB_PROP_GPU_NV_USERMODE_ENABLED_BASE_CAST @@ -1266,6 +1296,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; #define PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK_BASE_NAME PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK #define PDB_PROP_GPU_TEGRA_SOC_IGPU_BASE_CAST #define PDB_PROP_GPU_TEGRA_SOC_IGPU_BASE_NAME PDB_PROP_GPU_TEGRA_SOC_IGPU +#define PDB_PROP_GPU_RTD3_GCOFF_SUPPORTED_BASE_CAST +#define PDB_PROP_GPU_RTD3_GCOFF_SUPPORTED_BASE_NAME PDB_PROP_GPU_RTD3_GCOFF_SUPPORTED #define PDB_PROP_GPU_ATS_SUPPORTED_BASE_CAST #define PDB_PROP_GPU_ATS_SUPPORTED_BASE_NAME PDB_PROP_GPU_ATS_SUPPORTED #define PDB_PROP_GPU_EMULATION_BASE_CAST @@ -1296,6 +1328,8 @@ NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU**, Dynamic*, NvU32, #define __objCreate_OBJGPU(ppNewObj, pParent, createFlags, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, DispIpHal_ipver, arg_gpuInstance) \ __nvoc_objCreate_OBJGPU((ppNewObj), staticCast((pParent), Dynamic), (createFlags), ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, DispIpHal_ipver, arg_gpuInstance) +#define gpuConstructDeviceInfoTable(pGpu) gpuConstructDeviceInfoTable_DISPATCH(pGpu) +#define gpuConstructDeviceInfoTable_HAL(pGpu) gpuConstructDeviceInfoTable_DISPATCH(pGpu) #define gpuWriteBusConfigReg(pGpu, index, value) gpuWriteBusConfigReg_DISPATCH(pGpu, index, value) #define gpuWriteBusConfigReg_HAL(pGpu, index, value) gpuWriteBusConfigReg_DISPATCH(pGpu, index, value) #define gpuReadBusConfigReg(pGpu, index, data) gpuReadBusConfigReg_DISPATCH(pGpu, index, data) @@ -1326,8 +1360,6 @@ NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU**, Dynamic*, NvU32, #define gpuClearFbhubPoisonIntrForBug2924523_HAL(pGpu) gpuClearFbhubPoisonIntrForBug2924523_DISPATCH(pGpu) #define gpuReadDeviceId(pGpu, arg0, arg1) gpuReadDeviceId_DISPATCH(pGpu, arg0, arg1) #define gpuReadDeviceId_HAL(pGpu, arg0, arg1) gpuReadDeviceId_DISPATCH(pGpu, arg0, arg1) -#define gpuConstructDeviceInfoTable(pGpu) gpuConstructDeviceInfoTable_DISPATCH(pGpu) -#define gpuConstructDeviceInfoTable_HAL(pGpu) gpuConstructDeviceInfoTable_DISPATCH(pGpu) #define gpuGetFlaVasSize(pGpu, bNvswitchVirtualization) gpuGetFlaVasSize_DISPATCH(pGpu, bNvswitchVirtualization) #define gpuGetFlaVasSize_HAL(pGpu, bNvswitchVirtualization) gpuGetFlaVasSize_DISPATCH(pGpu, bNvswitchVirtualization) #define gpuIsAtsSupportedWithSmcMemPartitioning(pGpu) gpuIsAtsSupportedWithSmcMemPartitioning_DISPATCH(pGpu) @@ -1665,6 +1697,21 @@ static inline void gpuInitProperties(struct OBJGPU *pGpu) { #define gpuInitProperties_HAL(pGpu) gpuInitProperties(pGpu) +static inline void gpuSetThreadBcState_b3696a(struct OBJGPU *pGpu, NvBool arg0) { + return; +} + + +#ifdef __nvoc_gpu_h_disabled +static inline void gpuSetThreadBcState(struct OBJGPU *pGpu, NvBool arg0) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); +} +#else //__nvoc_gpu_h_disabled +#define gpuSetThreadBcState(pGpu, arg0) gpuSetThreadBcState_b3696a(pGpu, arg0) +#endif //__nvoc_gpu_h_disabled + +#define gpuSetThreadBcState_HAL(pGpu, arg0) gpuSetThreadBcState(pGpu, arg0) + static inline void gpuDeterminePersistantIllumSettings_b3696a(struct OBJGPU *pGpu) { return; } @@ -1797,6 +1844,38 @@ static inline NV_STATUS gpuMarkDeviceForReset(struct OBJGPU *pGpu) { #define gpuMarkDeviceForReset_HAL(pGpu) gpuMarkDeviceForReset(pGpu) +static inline NV_STATUS gpuUnmarkDeviceForReset_46f6a7(struct OBJGPU *pGpu) { + return NV_ERR_NOT_SUPPORTED; +} + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuUnmarkDeviceForReset(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuUnmarkDeviceForReset(pGpu) gpuUnmarkDeviceForReset_46f6a7(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuUnmarkDeviceForReset_HAL(pGpu) gpuUnmarkDeviceForReset(pGpu) + +static inline NV_STATUS gpuIsDeviceMarkedForReset_46f6a7(struct OBJGPU *pGpu, NvBool *pbResetRequired) { + return NV_ERR_NOT_SUPPORTED; +} + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuIsDeviceMarkedForReset(struct OBJGPU *pGpu, NvBool *pbResetRequired) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuIsDeviceMarkedForReset(pGpu, pbResetRequired) gpuIsDeviceMarkedForReset_46f6a7(pGpu, pbResetRequired) +#endif //__nvoc_gpu_h_disabled + +#define gpuIsDeviceMarkedForReset_HAL(pGpu, pbResetRequired) gpuIsDeviceMarkedForReset(pGpu, pbResetRequired) + static inline NV_STATUS gpuMarkDeviceForDrainAndReset_46f6a7(struct OBJGPU *pGpu) { return NV_ERR_NOT_SUPPORTED; } @@ -1813,6 +1892,38 @@ static inline NV_STATUS gpuMarkDeviceForDrainAndReset(struct OBJGPU *pGpu) { #define gpuMarkDeviceForDrainAndReset_HAL(pGpu) gpuMarkDeviceForDrainAndReset(pGpu) +static inline NV_STATUS gpuUnmarkDeviceForDrainAndReset_46f6a7(struct OBJGPU *pGpu) { + return NV_ERR_NOT_SUPPORTED; +} + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuUnmarkDeviceForDrainAndReset(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuUnmarkDeviceForDrainAndReset(pGpu) gpuUnmarkDeviceForDrainAndReset_46f6a7(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuUnmarkDeviceForDrainAndReset_HAL(pGpu) gpuUnmarkDeviceForDrainAndReset(pGpu) + +static inline NV_STATUS gpuIsDeviceMarkedForDrainAndReset_46f6a7(struct OBJGPU *pGpu, NvBool *pbDrainRecommended) { + return NV_ERR_NOT_SUPPORTED; +} + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuIsDeviceMarkedForDrainAndReset(struct OBJGPU *pGpu, NvBool *pbDrainRecommended) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuIsDeviceMarkedForDrainAndReset(pGpu, pbDrainRecommended) gpuIsDeviceMarkedForDrainAndReset_46f6a7(pGpu, pbDrainRecommended) +#endif //__nvoc_gpu_h_disabled + +#define gpuIsDeviceMarkedForDrainAndReset_HAL(pGpu, pbDrainRecommended) gpuIsDeviceMarkedForDrainAndReset(pGpu, pbDrainRecommended) + static inline NvU32 gpuGetSliFingerPinsetMask_4a4dee(struct OBJGPU *pGpu) { return 0; } @@ -2149,6 +2260,33 @@ static inline void gpuDestroyDefaultClientShare(struct OBJGPU *pGpu) { #define gpuDestroyDefaultClientShare_HAL(pGpu) gpuDestroyDefaultClientShare(pGpu) +void gpuUpdateUserSharedData_KERNEL(struct OBJGPU *pGpu); + + +#ifdef __nvoc_gpu_h_disabled +static inline void gpuUpdateUserSharedData(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); +} +#else //__nvoc_gpu_h_disabled +#define gpuUpdateUserSharedData(pGpu) gpuUpdateUserSharedData_KERNEL(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuUpdateUserSharedData_HAL(pGpu) gpuUpdateUserSharedData(pGpu) + +NV_STATUS gpuJtVersionSanityCheck_TU102(struct OBJGPU *pGpu); + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuJtVersionSanityCheck(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuJtVersionSanityCheck(pGpu) gpuJtVersionSanityCheck_TU102(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuJtVersionSanityCheck_HAL(pGpu) gpuJtVersionSanityCheck(pGpu) + NvU32 gpuGetActiveFBIOs_FWCLIENT(struct OBJGPU *pGpu); NvU32 gpuGetActiveFBIOs_GM107(struct OBJGPU *pGpu); @@ -2295,13 +2433,13 @@ static inline NvBool gpuCheckIsP2PAllocated(struct OBJGPU *pGpu) { #define gpuCheckIsP2PAllocated_HAL(pGpu) gpuCheckIsP2PAllocated(pGpu) -static inline void gpuDecodeDeviceInfoTableGroupId_b3696a(struct OBJGPU *pGpu, DEVICE_INFO2_TABLE *pEntry, NvU32 *pDeviceAccum) { +static inline void gpuDecodeDeviceInfoTableGroupId_b3696a(struct OBJGPU *pGpu, DEVICE_INFO2_ENTRY *pEntry, NvU32 *pDeviceAccum) { return; } #ifdef __nvoc_gpu_h_disabled -static inline void gpuDecodeDeviceInfoTableGroupId(struct OBJGPU *pGpu, DEVICE_INFO2_TABLE *pEntry, NvU32 *pDeviceAccum) { +static inline void gpuDecodeDeviceInfoTableGroupId(struct OBJGPU *pGpu, DEVICE_INFO2_ENTRY *pEntry, NvU32 *pDeviceAccum) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); } #else //__nvoc_gpu_h_disabled @@ -2341,6 +2479,64 @@ static inline void gpuResetVFRegisters(struct OBJGPU *pGpu, NvU32 gfid) { #define gpuResetVFRegisters_HAL(pGpu, gfid) gpuResetVFRegisters(pGpu, gfid) +static inline NvU32 gpuGetSliLinkDetectionHalFlag_539ab4(struct OBJGPU *pGpu) { + return 1; +} + + +#ifdef __nvoc_gpu_h_disabled +static inline NvU32 gpuGetSliLinkDetectionHalFlag(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return 0; +} +#else //__nvoc_gpu_h_disabled +#define gpuGetSliLinkDetectionHalFlag(pGpu) gpuGetSliLinkDetectionHalFlag_539ab4(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuGetSliLinkDetectionHalFlag_HAL(pGpu) gpuGetSliLinkDetectionHalFlag(pGpu) + +void gpuDetectSliLinkFromGpus_GK104(struct OBJGPU *pGpu, NvU32 gpuCount, NvU32 gpuMaskArg, NvU32 *pSliLinkOutputMask, NvBool *pSliLinkCircular, NvU32 *pSliLinkEndsMask, NvU32 *pVidLinkCount); + + +#ifdef __nvoc_gpu_h_disabled +static inline void gpuDetectSliLinkFromGpus(struct OBJGPU *pGpu, NvU32 gpuCount, NvU32 gpuMaskArg, NvU32 *pSliLinkOutputMask, NvBool *pSliLinkCircular, NvU32 *pSliLinkEndsMask, NvU32 *pVidLinkCount) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); +} +#else //__nvoc_gpu_h_disabled +#define gpuDetectSliLinkFromGpus(pGpu, gpuCount, gpuMaskArg, pSliLinkOutputMask, pSliLinkCircular, pSliLinkEndsMask, pVidLinkCount) gpuDetectSliLinkFromGpus_GK104(pGpu, gpuCount, gpuMaskArg, pSliLinkOutputMask, pSliLinkCircular, pSliLinkEndsMask, pVidLinkCount) +#endif //__nvoc_gpu_h_disabled + +#define gpuDetectSliLinkFromGpus_HAL(pGpu, gpuCount, gpuMaskArg, pSliLinkOutputMask, pSliLinkCircular, pSliLinkEndsMask, pVidLinkCount) gpuDetectSliLinkFromGpus(pGpu, gpuCount, gpuMaskArg, pSliLinkOutputMask, pSliLinkCircular, pSliLinkEndsMask, pVidLinkCount) + +static inline NvU32 gpuGetNvlinkLinkDetectionHalFlag_adde13(struct OBJGPU *pGpu) { + return 2; +} + + +#ifdef __nvoc_gpu_h_disabled +static inline NvU32 gpuGetNvlinkLinkDetectionHalFlag(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return 0; +} +#else //__nvoc_gpu_h_disabled +#define gpuGetNvlinkLinkDetectionHalFlag(pGpu) gpuGetNvlinkLinkDetectionHalFlag_adde13(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuGetNvlinkLinkDetectionHalFlag_HAL(pGpu) gpuGetNvlinkLinkDetectionHalFlag(pGpu) + +void gpuDetectNvlinkLinkFromGpus_GP100(struct OBJGPU *pGpu, NvU32 gpuCount, NvU32 gpuMaskArg, NvU32 *pSliLinkOutputMask, NvBool *pSliLinkCircular, NvU32 *pSliLinkEndsMask, NvU32 *pVidLinkCount); + + +#ifdef __nvoc_gpu_h_disabled +static inline void gpuDetectNvlinkLinkFromGpus(struct OBJGPU *pGpu, NvU32 gpuCount, NvU32 gpuMaskArg, NvU32 *pSliLinkOutputMask, NvBool *pSliLinkCircular, NvU32 *pSliLinkEndsMask, NvU32 *pVidLinkCount) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); +} +#else //__nvoc_gpu_h_disabled +#define gpuDetectNvlinkLinkFromGpus(pGpu, gpuCount, gpuMaskArg, pSliLinkOutputMask, pSliLinkCircular, pSliLinkEndsMask, pVidLinkCount) gpuDetectNvlinkLinkFromGpus_GP100(pGpu, gpuCount, gpuMaskArg, pSliLinkOutputMask, pSliLinkCircular, pSliLinkEndsMask, pVidLinkCount) +#endif //__nvoc_gpu_h_disabled + +#define gpuDetectNvlinkLinkFromGpus_HAL(pGpu, gpuCount, gpuMaskArg, pSliLinkOutputMask, pSliLinkCircular, pSliLinkEndsMask, pVidLinkCount) gpuDetectNvlinkLinkFromGpus(pGpu, gpuCount, gpuMaskArg, pSliLinkOutputMask, pSliLinkCircular, pSliLinkEndsMask, pVidLinkCount) + NvU32 gpuGetLitterValues_FWCLIENT(struct OBJGPU *pGpu, NvU32 index); NvU32 gpuGetLitterValues_TU102(struct OBJGPU *pGpu, NvU32 index); @@ -2471,6 +2667,18 @@ static inline GPU_P2P_PEER_GPU_CAPS *gpuFindP2PPeerGpuCapsByGpuId(struct OBJGPU #define gpuFindP2PPeerGpuCapsByGpuId_HAL(pGpu, peerGpuId) gpuFindP2PPeerGpuCapsByGpuId(pGpu, peerGpuId) +NV_STATUS gpuConstructDeviceInfoTable_FWCLIENT(struct OBJGPU *pGpu); + +static inline NV_STATUS gpuConstructDeviceInfoTable_56cd7a(struct OBJGPU *pGpu) { + return NV_OK; +} + +NV_STATUS gpuConstructDeviceInfoTable_GA100(struct OBJGPU *pGpu); + +static inline NV_STATUS gpuConstructDeviceInfoTable_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuConstructDeviceInfoTable__(pGpu); +} + NV_STATUS gpuWriteBusConfigReg_GM107(struct OBJGPU *pGpu, NvU32 index, NvU32 value); NV_STATUS gpuWriteBusConfigReg_GH100(struct OBJGPU *pGpu, NvU32 index, NvU32 value); @@ -2489,8 +2697,8 @@ static inline NV_STATUS gpuReadBusConfigReg_DISPATCH(struct OBJGPU *pGpu, NvU32 NV_STATUS gpuReadBusConfigRegEx_GM107(struct OBJGPU *pGpu, NvU32 index, NvU32 *data, THREAD_STATE_NODE *pThreadState); -static inline NV_STATUS gpuReadBusConfigRegEx_46f6a7(struct OBJGPU *pGpu, NvU32 index, NvU32 *data, THREAD_STATE_NODE *pThreadState) { - return NV_ERR_NOT_SUPPORTED; +static inline NV_STATUS gpuReadBusConfigRegEx_5baef9(struct OBJGPU *pGpu, NvU32 index, NvU32 *data, THREAD_STATE_NODE *pThreadState) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } static inline NV_STATUS gpuReadBusConfigRegEx_DISPATCH(struct OBJGPU *pGpu, NvU32 index, NvU32 *data, THREAD_STATE_NODE *pThreadState) { @@ -2603,6 +2811,10 @@ NvBool gpuFuseSupportsDisplay_GM107(struct OBJGPU *pGpu); NvBool gpuFuseSupportsDisplay_GA100(struct OBJGPU *pGpu); +static inline NvBool gpuFuseSupportsDisplay_491d52(struct OBJGPU *pGpu) { + return ((NvBool)(0 != 0)); +} + static inline NvBool gpuFuseSupportsDisplay_DISPATCH(struct OBJGPU *pGpu) { return pGpu->__gpuFuseSupportsDisplay__(pGpu); } @@ -2627,18 +2839,6 @@ static inline void gpuReadDeviceId_DISPATCH(struct OBJGPU *pGpu, NvU32 *arg0, Nv pGpu->__gpuReadDeviceId__(pGpu, arg0, arg1); } -NV_STATUS gpuConstructDeviceInfoTable_FWCLIENT(struct OBJGPU *pGpu); - -static inline NV_STATUS gpuConstructDeviceInfoTable_56cd7a(struct OBJGPU *pGpu) { - return NV_OK; -} - -NV_STATUS gpuConstructDeviceInfoTable_GA100(struct OBJGPU *pGpu); - -static inline NV_STATUS gpuConstructDeviceInfoTable_DISPATCH(struct OBJGPU *pGpu) { - return pGpu->__gpuConstructDeviceInfoTable__(pGpu); -} - NvU64 gpuGetFlaVasSize_GA100(struct OBJGPU *pGpu, NvBool bNvswitchVirtualization); NvU64 gpuGetFlaVasSize_GH100(struct OBJGPU *pGpu, NvBool bNvswitchVirtualization); @@ -2774,6 +2974,10 @@ static inline NvU64 gpuGetVmmuSegmentSize(struct OBJGPU *pGpu) { return pGpu->vmmuSegmentSize; } +static inline NvBool gpuIsVideoLinkDisabled(struct OBJGPU *pGpu) { + return pGpu->bVideoLinkDisabled; +} + static inline const NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS *gpuGetChipInfo(struct OBJGPU *pGpu) { return pGpu->pChipInfo; } @@ -2910,8 +3114,8 @@ static inline NvBool gpuIsSriovCapable(struct OBJGPU *pGpu) { return pGpu->bSriovCapable; } -static inline NvBool gpuIsCpuFirmwareHandlesFbEccInterruptEnabled(struct OBJGPU *pGpu) { - return pGpu->bCpuFirmwareHandlesFbEccInterruptEnabled; +static inline NvBool gpuIsGspOwnedFaultBuffersEnabled(struct OBJGPU *pGpu) { + return pGpu->bIsGspOwnedFaultBuffersEnabled; } NV_STATUS gpuConstruct_IMPL(struct OBJGPU *arg_pGpu, NvU32 arg_gpuInstance); @@ -3040,6 +3244,17 @@ static inline NvBool gpuIsGpuFullPowerForPmResume(struct OBJGPU *pGpu) { #define gpuIsGpuFullPowerForPmResume(pGpu) gpuIsGpuFullPowerForPmResume_IMPL(pGpu) #endif //__nvoc_gpu_h_disabled +NV_STATUS gpuGetDeviceEntryByType_IMPL(struct OBJGPU *pGpu, NvU32 deviceTypeEnum, NvS32 groupId, NvU32 instanceId, const DEVICE_INFO2_ENTRY **ppDeviceEntry); + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuGetDeviceEntryByType(struct OBJGPU *pGpu, NvU32 deviceTypeEnum, NvS32 groupId, NvU32 instanceId, const DEVICE_INFO2_ENTRY **ppDeviceEntry) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuGetDeviceEntryByType(pGpu, deviceTypeEnum, groupId, instanceId, ppDeviceEntry) gpuGetDeviceEntryByType_IMPL(pGpu, deviceTypeEnum, groupId, instanceId, ppDeviceEntry) +#endif //__nvoc_gpu_h_disabled + NV_STATUS gpuBuildClassDB_IMPL(struct OBJGPU *pGpu); #ifdef __nvoc_gpu_h_disabled @@ -3394,16 +3609,6 @@ static inline NV_STATUS gpuGetGidInfo(struct OBJGPU *pGpu, NvU8 **ppGidString, N #define gpuGetGidInfo(pGpu, ppGidString, pGidStrlen, gidFlags) gpuGetGidInfo_IMPL(pGpu, ppGidString, pGidStrlen, gidFlags) #endif //__nvoc_gpu_h_disabled -void gpuSetThreadBcState_IMPL(struct OBJGPU *pGpu, NvBool arg0); - -#ifdef __nvoc_gpu_h_disabled -static inline void gpuSetThreadBcState(struct OBJGPU *pGpu, NvBool arg0) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); -} -#else //__nvoc_gpu_h_disabled -#define gpuSetThreadBcState(pGpu, arg0) gpuSetThreadBcState_IMPL(pGpu, arg0) -#endif //__nvoc_gpu_h_disabled - void gpuSetDisconnectedProperties_IMPL(struct OBJGPU *pGpu); #ifdef __nvoc_gpu_h_disabled @@ -3727,6 +3932,50 @@ static inline NV_STATUS gpuFindClientInfoWithPidIterator(struct OBJGPU *pGpu, Nv #define gpuFindClientInfoWithPidIterator(pGpu, pid, subPid, internalClassId, pData, pSmcInfo, pRef, bGlobalInfo) gpuFindClientInfoWithPidIterator_IMPL(pGpu, pid, subPid, internalClassId, pData, pSmcInfo, pRef, bGlobalInfo) #endif //__nvoc_gpu_h_disabled +NV_STATUS gpuEnterStandby_IMPL(struct OBJGPU *pGpu); + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuEnterStandby(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuEnterStandby(pGpu) gpuEnterStandby_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + +NV_STATUS gpuEnterHibernate_IMPL(struct OBJGPU *pGpu); + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuEnterHibernate(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuEnterHibernate(pGpu) gpuEnterHibernate_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + +NV_STATUS gpuResumeFromStandby_IMPL(struct OBJGPU *pGpu); + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuResumeFromStandby(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuResumeFromStandby(pGpu) gpuResumeFromStandby_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + +NV_STATUS gpuResumeFromHibernate_IMPL(struct OBJGPU *pGpu); + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuResumeFromHibernate(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuResumeFromHibernate(pGpu) gpuResumeFromHibernate_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + NvBool gpuCheckSysmemAccess_IMPL(struct OBJGPU *pGpu); #ifdef __nvoc_gpu_h_disabled @@ -3781,6 +4030,17 @@ static inline NV_STATUS gpuValidateRegOffset(struct OBJGPU *pGpu, NvU32 arg0) { #define gpuValidateRegOffset(pGpu, arg0) gpuValidateRegOffset_IMPL(pGpu, arg0) #endif //__nvoc_gpu_h_disabled +NV_STATUS gpuSetGC6SBIOSCapabilities_IMPL(struct OBJGPU *pGpu); + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuSetGC6SBIOSCapabilities(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuSetGC6SBIOSCapabilities(pGpu) gpuSetGC6SBIOSCapabilities_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + #undef PRIVATE_FIELD @@ -3799,11 +4059,11 @@ NV_STATUS gpuGetByHandle(struct RsClient *pClient, NvHandle hResource, NvBool *p // // Generates GPU child accessor macros (i.e.: GPU_GET_{ENG}) // -#define GPU_CHILD_SINGLE_INST(className, accessorName, numInstances, bConstructEarly, bAlwaysCreate, gpuField) \ +#define GPU_CHILD_SINGLE_INST(className, accessorName, numInstances, bConstructEarly, gpuField) \ static NV_FORCEINLINE className *accessorName(OBJGPU *pGpu) { return pGpu->gpuField; } \ ct_assert(numInstances == 1); -#define GPU_CHILD_MULTI_INST(className, accessorName, numInstances, bConstructEarly, bAlwaysCreate, gpuField) \ +#define GPU_CHILD_MULTI_INST(className, accessorName, numInstances, bConstructEarly, gpuField) \ static NV_FORCEINLINE className *accessorName(OBJGPU *pGpu, NvU32 index) { return index < numInstances ? pGpu->gpuField[index] : NULL; } #include "gpu/gpu_child_list.h" @@ -3813,10 +4073,10 @@ static NV_FORCEINLINE struct Graphics *GPU_GET_GR(struct OBJGPU *pGpu) { return // Temporary stubs #if RM_STRICT_CONFIG_EMIT_DISABLED_GPU_ENGINE_ACCESSORS #define GPU_CHILD_LIST_DISABLED_ONLY -#define GPU_CHILD_SINGLE_INST(className, accessorName, numInstances, bConstructEarly, bAlwaysCreate, gpuField) \ +#define GPU_CHILD_SINGLE_INST(className, accessorName, numInstances, bConstructEarly, gpuField) \ static NV_FORCEINLINE className *accessorName(OBJGPU *pGpu) { return NULL; } -#define GPU_CHILD_MULTI_INST(className, accessorName, numInstances, bConstructEarly, bAlwaysCreate, gpuField) \ +#define GPU_CHILD_MULTI_INST(className, accessorName, numInstances, bConstructEarly, gpuField) \ static NV_FORCEINLINE className *accessorName(OBJGPU *pGpu, NvU32 index) { return NULL; } #include "gpu/gpu_child_list.h" diff --git a/src/nvidia/generated/g_gpu_resource_nvoc.c b/src/nvidia/generated/g_gpu_resource_nvoc.c index 793cd55ce..5ba180013 100644 --- a/src/nvidia/generated/g_gpu_resource_nvoc.c +++ b/src/nvidia/generated/g_gpu_resource_nvoc.c @@ -124,6 +124,14 @@ static void __nvoc_thunk_RsResource_gpuresAddAdditionalDependants(struct RsClien resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RsResource.offset), pReference); } +static NV_STATUS __nvoc_thunk_RsResource_gpuresUnmapFrom(struct GpuResource *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_gpuresControlSerialization_Prologue(struct GpuResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RmResource.offset), pCallContext, pParams); +} + static NV_STATUS __nvoc_thunk_RmResource_gpuresControl_Prologue(struct GpuResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RmResource.offset), pCallContext, pParams); } @@ -132,22 +140,22 @@ static NvBool __nvoc_thunk_RsResource_gpuresCanCopy(struct GpuResource *pResourc return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_gpuresMapTo(struct GpuResource *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RsResource.offset), pParams); -} - static void __nvoc_thunk_RsResource_gpuresPreDestruct(struct GpuResource *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_gpuresUnmapFrom(struct GpuResource *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_gpuresMapTo(struct GpuResource *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_RsResource_gpuresIsDuplicate(struct GpuResource *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_gpuresControlSerialization_Epilogue(struct GpuResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RmResource.offset), pCallContext, pParams); +} + static void __nvoc_thunk_RmResource_gpuresControl_Epilogue(struct GpuResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RmResource.offset), pCallContext, pParams); } @@ -234,18 +242,22 @@ static void __nvoc_init_funcTable_GpuResource_1(GpuResource *pThis) { pThis->__gpuresAddAdditionalDependants__ = &__nvoc_thunk_RsResource_gpuresAddAdditionalDependants; + pThis->__gpuresUnmapFrom__ = &__nvoc_thunk_RsResource_gpuresUnmapFrom; + + pThis->__gpuresControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_gpuresControlSerialization_Prologue; + pThis->__gpuresControl_Prologue__ = &__nvoc_thunk_RmResource_gpuresControl_Prologue; pThis->__gpuresCanCopy__ = &__nvoc_thunk_RsResource_gpuresCanCopy; - pThis->__gpuresMapTo__ = &__nvoc_thunk_RsResource_gpuresMapTo; - pThis->__gpuresPreDestruct__ = &__nvoc_thunk_RsResource_gpuresPreDestruct; - pThis->__gpuresUnmapFrom__ = &__nvoc_thunk_RsResource_gpuresUnmapFrom; + pThis->__gpuresMapTo__ = &__nvoc_thunk_RsResource_gpuresMapTo; pThis->__gpuresIsDuplicate__ = &__nvoc_thunk_RsResource_gpuresIsDuplicate; + pThis->__gpuresControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_gpuresControlSerialization_Epilogue; + pThis->__gpuresControl_Epilogue__ = &__nvoc_thunk_RmResource_gpuresControl_Epilogue; pThis->__gpuresControlLookup__ = &__nvoc_thunk_RsResource_gpuresControlLookup; @@ -273,13 +285,16 @@ NV_STATUS __nvoc_objCreate_GpuResource(GpuResource **ppThis, Dynamic *pParent, N Object *pParentObj; GpuResource *pThis; - pThis = portMemAllocNonPaged(sizeof(GpuResource)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(GpuResource), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(GpuResource)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_GpuResource); + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -295,11 +310,17 @@ NV_STATUS __nvoc_objCreate_GpuResource(GpuResource **ppThis, Dynamic *pParent, N if (status != NV_OK) goto __nvoc_objCreate_GpuResource_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_GpuResource_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(GpuResource)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_gpu_resource_nvoc.h b/src/nvidia/generated/g_gpu_resource_nvoc.h index 2c84005ac..00f658439 100644 --- a/src/nvidia/generated/g_gpu_resource_nvoc.h +++ b/src/nvidia/generated/g_gpu_resource_nvoc.h @@ -80,10 +80,7 @@ typedef struct Subdevice Subdevice; #define GPU_RES_GET_DEVICE(pRes) staticCastNoPtrCheck((pRes), GpuResource)->pDevice #define GPU_RES_GET_SUBDEVICE(pRes) staticCastNoPtrCheck((pRes), GpuResource)->pSubdevice -#define GPU_RES_SET_THREAD_BC_STATE(pRes) do { \ - gpuSetThreadBcState(staticCastNoPtrCheck((pRes), GpuResource)->pGpu, \ - staticCastNoPtrCheck((pRes), GpuResource)->bBcResource); \ - } while(0) +#define GPU_RES_SET_THREAD_BC_STATE(pRes) PORT_UNREFERENCED_VARIABLE(pRes) /*! * Abstract base class for common CPU mapping operations @@ -115,12 +112,14 @@ struct GpuResource { NvU32 (*__gpuresGetRefCount__)(struct GpuResource *); NV_STATUS (*__gpuresControlFilter__)(struct GpuResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__gpuresAddAdditionalDependants__)(struct RsClient *, struct GpuResource *, RsResourceRef *); + NV_STATUS (*__gpuresUnmapFrom__)(struct GpuResource *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__gpuresControlSerialization_Prologue__)(struct GpuResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__gpuresControl_Prologue__)(struct GpuResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__gpuresCanCopy__)(struct GpuResource *); - NV_STATUS (*__gpuresMapTo__)(struct GpuResource *, RS_RES_MAP_TO_PARAMS *); void (*__gpuresPreDestruct__)(struct GpuResource *); - NV_STATUS (*__gpuresUnmapFrom__)(struct GpuResource *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__gpuresMapTo__)(struct GpuResource *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__gpuresIsDuplicate__)(struct GpuResource *, NvHandle, NvBool *); + void (*__gpuresControlSerialization_Epilogue__)(struct GpuResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__gpuresControl_Epilogue__)(struct GpuResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__gpuresControlLookup__)(struct GpuResource *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvBool (*__gpuresAccessCallback__)(struct GpuResource *, struct RsClient *, void *, RsAccessRight); @@ -173,12 +172,14 @@ NV_STATUS __nvoc_objCreate_GpuResource(GpuResource**, Dynamic*, NvU32, struct CA #define gpuresGetRefCount(pResource) gpuresGetRefCount_DISPATCH(pResource) #define gpuresControlFilter(pResource, pCallContext, pParams) gpuresControlFilter_DISPATCH(pResource, pCallContext, pParams) #define gpuresAddAdditionalDependants(pClient, pResource, pReference) gpuresAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define gpuresUnmapFrom(pResource, pParams) gpuresUnmapFrom_DISPATCH(pResource, pParams) +#define gpuresControlSerialization_Prologue(pResource, pCallContext, pParams) gpuresControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define gpuresControl_Prologue(pResource, pCallContext, pParams) gpuresControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define gpuresCanCopy(pResource) gpuresCanCopy_DISPATCH(pResource) -#define gpuresMapTo(pResource, pParams) gpuresMapTo_DISPATCH(pResource, pParams) #define gpuresPreDestruct(pResource) gpuresPreDestruct_DISPATCH(pResource) -#define gpuresUnmapFrom(pResource, pParams) gpuresUnmapFrom_DISPATCH(pResource, pParams) +#define gpuresMapTo(pResource, pParams) gpuresMapTo_DISPATCH(pResource, pParams) #define gpuresIsDuplicate(pResource, hMemory, pDuplicate) gpuresIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define gpuresControlSerialization_Epilogue(pResource, pCallContext, pParams) gpuresControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define gpuresControl_Epilogue(pResource, pCallContext, pParams) gpuresControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define gpuresControlLookup(pResource, pParams, ppEntry) gpuresControlLookup_DISPATCH(pResource, pParams, ppEntry) #define gpuresAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) gpuresAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) @@ -254,6 +255,14 @@ static inline void gpuresAddAdditionalDependants_DISPATCH(struct RsClient *pClie pResource->__gpuresAddAdditionalDependants__(pClient, pResource, pReference); } +static inline NV_STATUS gpuresUnmapFrom_DISPATCH(struct GpuResource *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__gpuresUnmapFrom__(pResource, pParams); +} + +static inline NV_STATUS gpuresControlSerialization_Prologue_DISPATCH(struct GpuResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__gpuresControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NV_STATUS gpuresControl_Prologue_DISPATCH(struct GpuResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__gpuresControl_Prologue__(pResource, pCallContext, pParams); } @@ -262,22 +271,22 @@ static inline NvBool gpuresCanCopy_DISPATCH(struct GpuResource *pResource) { return pResource->__gpuresCanCopy__(pResource); } -static inline NV_STATUS gpuresMapTo_DISPATCH(struct GpuResource *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__gpuresMapTo__(pResource, pParams); -} - static inline void gpuresPreDestruct_DISPATCH(struct GpuResource *pResource) { pResource->__gpuresPreDestruct__(pResource); } -static inline NV_STATUS gpuresUnmapFrom_DISPATCH(struct GpuResource *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__gpuresUnmapFrom__(pResource, pParams); +static inline NV_STATUS gpuresMapTo_DISPATCH(struct GpuResource *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__gpuresMapTo__(pResource, pParams); } static inline NV_STATUS gpuresIsDuplicate_DISPATCH(struct GpuResource *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__gpuresIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void gpuresControlSerialization_Epilogue_DISPATCH(struct GpuResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__gpuresControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline void gpuresControl_Epilogue_DISPATCH(struct GpuResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__gpuresControl_Epilogue__(pResource, pCallContext, pParams); } diff --git a/src/nvidia/generated/g_gpu_user_shared_data_nvoc.c b/src/nvidia/generated/g_gpu_user_shared_data_nvoc.c index 025788917..6537d2865 100644 --- a/src/nvidia/generated/g_gpu_user_shared_data_nvoc.c +++ b/src/nvidia/generated/g_gpu_user_shared_data_nvoc.c @@ -113,30 +113,6 @@ static NvBool __nvoc_thunk_GpuResource_gpushareddataShareCallback(struct GpuUser return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GpuUserSharedData_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuResource_gpushareddataControl(struct GpuUserSharedData *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GpuUserSharedData_GpuResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_gpushareddataGetMemInterMapParams(struct GpuUserSharedData *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), pParams); -} - -static NvHandle __nvoc_thunk_GpuResource_gpushareddataGetInternalObjectHandle(struct GpuUserSharedData *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GpuUserSharedData_GpuResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RsResource_gpushareddataControlFilter(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), pCallContext, pParams); -} - -static void __nvoc_thunk_RsResource_gpushareddataAddAdditionalDependants(struct RsClient *pClient, struct GpuUserSharedData *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_gpushareddataGetRefCount(struct GpuUserSharedData *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_RmResource_gpushareddataCheckMemInterUnmap(struct GpuUserSharedData *pRmResource, NvBool bSubdeviceHandleProvided) { return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), bSubdeviceHandleProvided); } @@ -145,6 +121,14 @@ static NV_STATUS __nvoc_thunk_RsResource_gpushareddataMapTo(struct GpuUserShared return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), pParams); } +static NvU32 __nvoc_thunk_RsResource_gpushareddataGetRefCount(struct GpuUserSharedData *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_gpushareddataAddAdditionalDependants(struct RsClient *pClient, struct GpuUserSharedData *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), pReference); +} + static NV_STATUS __nvoc_thunk_RmResource_gpushareddataControl_Prologue(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), pCallContext, pParams); } @@ -153,26 +137,14 @@ static NV_STATUS __nvoc_thunk_GpuResource_gpushareddataGetRegBaseOffsetAndSize(s return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GpuUserSharedData_GpuResource.offset), pGpu, pOffset, pSize); } -static NvBool __nvoc_thunk_RsResource_gpushareddataCanCopy(struct GpuUserSharedData *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_GpuResource_gpushareddataInternalControlForward(struct GpuUserSharedData *pGpuResource, NvU32 command, void *pParams, NvU32 size) { return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GpuUserSharedData_GpuResource.offset), command, pParams, size); } -static void __nvoc_thunk_RsResource_gpushareddataPreDestruct(struct GpuUserSharedData *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_gpushareddataUnmapFrom(struct GpuUserSharedData *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RsResource_gpushareddataIsDuplicate(struct GpuUserSharedData *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), hMemory, pDuplicate); -} - static void __nvoc_thunk_RmResource_gpushareddataControl_Epilogue(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), pCallContext, pParams); } @@ -181,6 +153,42 @@ static NV_STATUS __nvoc_thunk_RsResource_gpushareddataControlLookup(struct GpuUs return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), pParams, ppEntry); } +static NvHandle __nvoc_thunk_GpuResource_gpushareddataGetInternalObjectHandle(struct GpuUserSharedData *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GpuUserSharedData_GpuResource.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_gpushareddataControl(struct GpuUserSharedData *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GpuUserSharedData_GpuResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_gpushareddataGetMemInterMapParams(struct GpuUserSharedData *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_gpushareddataControlFilter(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_gpushareddataControlSerialization_Prologue(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_RsResource_gpushareddataCanCopy(struct GpuUserSharedData *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_gpushareddataPreDestruct(struct GpuUserSharedData *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_gpushareddataIsDuplicate(struct GpuUserSharedData *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_gpushareddataControlSerialization_Epilogue(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RmResource_gpushareddataAccessCallback(struct GpuUserSharedData *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), pInvokingClient, pAllocParams, accessRight); } @@ -242,40 +250,44 @@ static void __nvoc_init_funcTable_GpuUserSharedData_1(GpuUserSharedData *pThis) pThis->__gpushareddataShareCallback__ = &__nvoc_thunk_GpuResource_gpushareddataShareCallback; - pThis->__gpushareddataControl__ = &__nvoc_thunk_GpuResource_gpushareddataControl; - - pThis->__gpushareddataGetMemInterMapParams__ = &__nvoc_thunk_RmResource_gpushareddataGetMemInterMapParams; - - pThis->__gpushareddataGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_gpushareddataGetInternalObjectHandle; - - pThis->__gpushareddataControlFilter__ = &__nvoc_thunk_RsResource_gpushareddataControlFilter; - - pThis->__gpushareddataAddAdditionalDependants__ = &__nvoc_thunk_RsResource_gpushareddataAddAdditionalDependants; - - pThis->__gpushareddataGetRefCount__ = &__nvoc_thunk_RsResource_gpushareddataGetRefCount; - pThis->__gpushareddataCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_gpushareddataCheckMemInterUnmap; pThis->__gpushareddataMapTo__ = &__nvoc_thunk_RsResource_gpushareddataMapTo; + pThis->__gpushareddataGetRefCount__ = &__nvoc_thunk_RsResource_gpushareddataGetRefCount; + + pThis->__gpushareddataAddAdditionalDependants__ = &__nvoc_thunk_RsResource_gpushareddataAddAdditionalDependants; + pThis->__gpushareddataControl_Prologue__ = &__nvoc_thunk_RmResource_gpushareddataControl_Prologue; pThis->__gpushareddataGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_gpushareddataGetRegBaseOffsetAndSize; - pThis->__gpushareddataCanCopy__ = &__nvoc_thunk_RsResource_gpushareddataCanCopy; - pThis->__gpushareddataInternalControlForward__ = &__nvoc_thunk_GpuResource_gpushareddataInternalControlForward; - pThis->__gpushareddataPreDestruct__ = &__nvoc_thunk_RsResource_gpushareddataPreDestruct; - pThis->__gpushareddataUnmapFrom__ = &__nvoc_thunk_RsResource_gpushareddataUnmapFrom; - pThis->__gpushareddataIsDuplicate__ = &__nvoc_thunk_RsResource_gpushareddataIsDuplicate; - pThis->__gpushareddataControl_Epilogue__ = &__nvoc_thunk_RmResource_gpushareddataControl_Epilogue; pThis->__gpushareddataControlLookup__ = &__nvoc_thunk_RsResource_gpushareddataControlLookup; + pThis->__gpushareddataGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_gpushareddataGetInternalObjectHandle; + + pThis->__gpushareddataControl__ = &__nvoc_thunk_GpuResource_gpushareddataControl; + + pThis->__gpushareddataGetMemInterMapParams__ = &__nvoc_thunk_RmResource_gpushareddataGetMemInterMapParams; + + pThis->__gpushareddataControlFilter__ = &__nvoc_thunk_RsResource_gpushareddataControlFilter; + + pThis->__gpushareddataControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_gpushareddataControlSerialization_Prologue; + + pThis->__gpushareddataCanCopy__ = &__nvoc_thunk_RsResource_gpushareddataCanCopy; + + pThis->__gpushareddataPreDestruct__ = &__nvoc_thunk_RsResource_gpushareddataPreDestruct; + + pThis->__gpushareddataIsDuplicate__ = &__nvoc_thunk_RsResource_gpushareddataIsDuplicate; + + pThis->__gpushareddataControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_gpushareddataControlSerialization_Epilogue; + pThis->__gpushareddataAccessCallback__ = &__nvoc_thunk_RmResource_gpushareddataAccessCallback; } @@ -300,13 +312,16 @@ NV_STATUS __nvoc_objCreate_GpuUserSharedData(GpuUserSharedData **ppThis, Dynamic Object *pParentObj; GpuUserSharedData *pThis; - pThis = portMemAllocNonPaged(sizeof(GpuUserSharedData)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(GpuUserSharedData), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(GpuUserSharedData)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_GpuUserSharedData); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -322,11 +337,17 @@ NV_STATUS __nvoc_objCreate_GpuUserSharedData(GpuUserSharedData **ppThis, Dynamic if (status != NV_OK) goto __nvoc_objCreate_GpuUserSharedData_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_GpuUserSharedData_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(GpuUserSharedData)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_gpu_user_shared_data_nvoc.h b/src/nvidia/generated/g_gpu_user_shared_data_nvoc.h index ca8a7c078..407a6a917 100644 --- a/src/nvidia/generated/g_gpu_user_shared_data_nvoc.h +++ b/src/nvidia/generated/g_gpu_user_shared_data_nvoc.h @@ -64,23 +64,25 @@ struct GpuUserSharedData { NV_STATUS (*__gpushareddataGetMapAddrSpace__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); NV_STATUS (*__gpushareddataGetMemoryMappingDescriptor__)(struct GpuUserSharedData *, struct MEMORY_DESCRIPTOR **); NvBool (*__gpushareddataShareCallback__)(struct GpuUserSharedData *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__gpushareddataControl__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__gpushareddataGetMemInterMapParams__)(struct GpuUserSharedData *, RMRES_MEM_INTER_MAP_PARAMS *); - NvHandle (*__gpushareddataGetInternalObjectHandle__)(struct GpuUserSharedData *); - NV_STATUS (*__gpushareddataControlFilter__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__gpushareddataAddAdditionalDependants__)(struct RsClient *, struct GpuUserSharedData *, RsResourceRef *); - NvU32 (*__gpushareddataGetRefCount__)(struct GpuUserSharedData *); NV_STATUS (*__gpushareddataCheckMemInterUnmap__)(struct GpuUserSharedData *, NvBool); NV_STATUS (*__gpushareddataMapTo__)(struct GpuUserSharedData *, RS_RES_MAP_TO_PARAMS *); + NvU32 (*__gpushareddataGetRefCount__)(struct GpuUserSharedData *); + void (*__gpushareddataAddAdditionalDependants__)(struct RsClient *, struct GpuUserSharedData *, RsResourceRef *); NV_STATUS (*__gpushareddataControl_Prologue__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__gpushareddataGetRegBaseOffsetAndSize__)(struct GpuUserSharedData *, struct OBJGPU *, NvU32 *, NvU32 *); - NvBool (*__gpushareddataCanCopy__)(struct GpuUserSharedData *); NV_STATUS (*__gpushareddataInternalControlForward__)(struct GpuUserSharedData *, NvU32, void *, NvU32); - void (*__gpushareddataPreDestruct__)(struct GpuUserSharedData *); NV_STATUS (*__gpushareddataUnmapFrom__)(struct GpuUserSharedData *, RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__gpushareddataIsDuplicate__)(struct GpuUserSharedData *, NvHandle, NvBool *); void (*__gpushareddataControl_Epilogue__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__gpushareddataControlLookup__)(struct GpuUserSharedData *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__gpushareddataGetInternalObjectHandle__)(struct GpuUserSharedData *); + NV_STATUS (*__gpushareddataControl__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__gpushareddataGetMemInterMapParams__)(struct GpuUserSharedData *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__gpushareddataControlFilter__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__gpushareddataControlSerialization_Prologue__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__gpushareddataCanCopy__)(struct GpuUserSharedData *); + void (*__gpushareddataPreDestruct__)(struct GpuUserSharedData *); + NV_STATUS (*__gpushareddataIsDuplicate__)(struct GpuUserSharedData *, NvHandle, NvBool *); + void (*__gpushareddataControlSerialization_Epilogue__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__gpushareddataAccessCallback__)(struct GpuUserSharedData *, struct RsClient *, void *, RsAccessRight); }; @@ -117,23 +119,25 @@ NV_STATUS __nvoc_objCreate_GpuUserSharedData(GpuUserSharedData**, Dynamic*, NvU3 #define gpushareddataGetMapAddrSpace(pData, pCallContext, mapFlags, pAddrSpace) gpushareddataGetMapAddrSpace_DISPATCH(pData, pCallContext, mapFlags, pAddrSpace) #define gpushareddataGetMemoryMappingDescriptor(pData, ppMemDesc) gpushareddataGetMemoryMappingDescriptor_DISPATCH(pData, ppMemDesc) #define gpushareddataShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) gpushareddataShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define gpushareddataControl(pGpuResource, pCallContext, pParams) gpushareddataControl_DISPATCH(pGpuResource, pCallContext, pParams) -#define gpushareddataGetMemInterMapParams(pRmResource, pParams) gpushareddataGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define gpushareddataGetInternalObjectHandle(pGpuResource) gpushareddataGetInternalObjectHandle_DISPATCH(pGpuResource) -#define gpushareddataControlFilter(pResource, pCallContext, pParams) gpushareddataControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define gpushareddataAddAdditionalDependants(pClient, pResource, pReference) gpushareddataAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define gpushareddataGetRefCount(pResource) gpushareddataGetRefCount_DISPATCH(pResource) #define gpushareddataCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) gpushareddataCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define gpushareddataMapTo(pResource, pParams) gpushareddataMapTo_DISPATCH(pResource, pParams) +#define gpushareddataGetRefCount(pResource) gpushareddataGetRefCount_DISPATCH(pResource) +#define gpushareddataAddAdditionalDependants(pClient, pResource, pReference) gpushareddataAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define gpushareddataControl_Prologue(pResource, pCallContext, pParams) gpushareddataControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define gpushareddataGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) gpushareddataGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) -#define gpushareddataCanCopy(pResource) gpushareddataCanCopy_DISPATCH(pResource) #define gpushareddataInternalControlForward(pGpuResource, command, pParams, size) gpushareddataInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) -#define gpushareddataPreDestruct(pResource) gpushareddataPreDestruct_DISPATCH(pResource) #define gpushareddataUnmapFrom(pResource, pParams) gpushareddataUnmapFrom_DISPATCH(pResource, pParams) -#define gpushareddataIsDuplicate(pResource, hMemory, pDuplicate) gpushareddataIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define gpushareddataControl_Epilogue(pResource, pCallContext, pParams) gpushareddataControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define gpushareddataControlLookup(pResource, pParams, ppEntry) gpushareddataControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define gpushareddataGetInternalObjectHandle(pGpuResource) gpushareddataGetInternalObjectHandle_DISPATCH(pGpuResource) +#define gpushareddataControl(pGpuResource, pCallContext, pParams) gpushareddataControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define gpushareddataGetMemInterMapParams(pRmResource, pParams) gpushareddataGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define gpushareddataControlFilter(pResource, pCallContext, pParams) gpushareddataControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define gpushareddataControlSerialization_Prologue(pResource, pCallContext, pParams) gpushareddataControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define gpushareddataCanCopy(pResource) gpushareddataCanCopy_DISPATCH(pResource) +#define gpushareddataPreDestruct(pResource) gpushareddataPreDestruct_DISPATCH(pResource) +#define gpushareddataIsDuplicate(pResource, hMemory, pDuplicate) gpushareddataIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define gpushareddataControlSerialization_Epilogue(pResource, pCallContext, pParams) gpushareddataControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define gpushareddataAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) gpushareddataAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS gpushareddataMap_IMPL(struct GpuUserSharedData *pData, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping); @@ -163,30 +167,6 @@ static inline NvBool gpushareddataShareCallback_DISPATCH(struct GpuUserSharedDat return pGpuResource->__gpushareddataShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS gpushareddataControl_DISPATCH(struct GpuUserSharedData *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pGpuResource->__gpushareddataControl__(pGpuResource, pCallContext, pParams); -} - -static inline NV_STATUS gpushareddataGetMemInterMapParams_DISPATCH(struct GpuUserSharedData *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__gpushareddataGetMemInterMapParams__(pRmResource, pParams); -} - -static inline NvHandle gpushareddataGetInternalObjectHandle_DISPATCH(struct GpuUserSharedData *pGpuResource) { - return pGpuResource->__gpushareddataGetInternalObjectHandle__(pGpuResource); -} - -static inline NV_STATUS gpushareddataControlFilter_DISPATCH(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__gpushareddataControlFilter__(pResource, pCallContext, pParams); -} - -static inline void gpushareddataAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct GpuUserSharedData *pResource, RsResourceRef *pReference) { - pResource->__gpushareddataAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 gpushareddataGetRefCount_DISPATCH(struct GpuUserSharedData *pResource) { - return pResource->__gpushareddataGetRefCount__(pResource); -} - static inline NV_STATUS gpushareddataCheckMemInterUnmap_DISPATCH(struct GpuUserSharedData *pRmResource, NvBool bSubdeviceHandleProvided) { return pRmResource->__gpushareddataCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } @@ -195,6 +175,14 @@ static inline NV_STATUS gpushareddataMapTo_DISPATCH(struct GpuUserSharedData *pR return pResource->__gpushareddataMapTo__(pResource, pParams); } +static inline NvU32 gpushareddataGetRefCount_DISPATCH(struct GpuUserSharedData *pResource) { + return pResource->__gpushareddataGetRefCount__(pResource); +} + +static inline void gpushareddataAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct GpuUserSharedData *pResource, RsResourceRef *pReference) { + pResource->__gpushareddataAddAdditionalDependants__(pClient, pResource, pReference); +} + static inline NV_STATUS gpushareddataControl_Prologue_DISPATCH(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__gpushareddataControl_Prologue__(pResource, pCallContext, pParams); } @@ -203,26 +191,14 @@ static inline NV_STATUS gpushareddataGetRegBaseOffsetAndSize_DISPATCH(struct Gpu return pGpuResource->__gpushareddataGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); } -static inline NvBool gpushareddataCanCopy_DISPATCH(struct GpuUserSharedData *pResource) { - return pResource->__gpushareddataCanCopy__(pResource); -} - static inline NV_STATUS gpushareddataInternalControlForward_DISPATCH(struct GpuUserSharedData *pGpuResource, NvU32 command, void *pParams, NvU32 size) { return pGpuResource->__gpushareddataInternalControlForward__(pGpuResource, command, pParams, size); } -static inline void gpushareddataPreDestruct_DISPATCH(struct GpuUserSharedData *pResource) { - pResource->__gpushareddataPreDestruct__(pResource); -} - static inline NV_STATUS gpushareddataUnmapFrom_DISPATCH(struct GpuUserSharedData *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__gpushareddataUnmapFrom__(pResource, pParams); } -static inline NV_STATUS gpushareddataIsDuplicate_DISPATCH(struct GpuUserSharedData *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return pResource->__gpushareddataIsDuplicate__(pResource, hMemory, pDuplicate); -} - static inline void gpushareddataControl_Epilogue_DISPATCH(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__gpushareddataControl_Epilogue__(pResource, pCallContext, pParams); } @@ -231,6 +207,42 @@ static inline NV_STATUS gpushareddataControlLookup_DISPATCH(struct GpuUserShared return pResource->__gpushareddataControlLookup__(pResource, pParams, ppEntry); } +static inline NvHandle gpushareddataGetInternalObjectHandle_DISPATCH(struct GpuUserSharedData *pGpuResource) { + return pGpuResource->__gpushareddataGetInternalObjectHandle__(pGpuResource); +} + +static inline NV_STATUS gpushareddataControl_DISPATCH(struct GpuUserSharedData *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__gpushareddataControl__(pGpuResource, pCallContext, pParams); +} + +static inline NV_STATUS gpushareddataGetMemInterMapParams_DISPATCH(struct GpuUserSharedData *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__gpushareddataGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS gpushareddataControlFilter_DISPATCH(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__gpushareddataControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS gpushareddataControlSerialization_Prologue_DISPATCH(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__gpushareddataControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool gpushareddataCanCopy_DISPATCH(struct GpuUserSharedData *pResource) { + return pResource->__gpushareddataCanCopy__(pResource); +} + +static inline void gpushareddataPreDestruct_DISPATCH(struct GpuUserSharedData *pResource) { + pResource->__gpushareddataPreDestruct__(pResource); +} + +static inline NV_STATUS gpushareddataIsDuplicate_DISPATCH(struct GpuUserSharedData *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__gpushareddataIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void gpushareddataControlSerialization_Epilogue_DISPATCH(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__gpushareddataControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline NvBool gpushareddataAccessCallback_DISPATCH(struct GpuUserSharedData *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return pResource->__gpushareddataAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); } diff --git a/src/nvidia/generated/g_gpu_vaspace_nvoc.c b/src/nvidia/generated/g_gpu_vaspace_nvoc.c index b0a1d89ae..4f86b25d2 100644 --- a/src/nvidia/generated/g_gpu_vaspace_nvoc.c +++ b/src/nvidia/generated/g_gpu_vaspace_nvoc.c @@ -102,7 +102,7 @@ static struct OBJEHEAP *__nvoc_thunk_OBJGVASPACE_vaspaceGetHeap(struct OBJVASPAC return gvaspaceGetHeap((struct OBJGVASPACE *)(((unsigned char *)pVAS) - __nvoc_rtti_OBJGVASPACE_OBJVASPACE.offset)); } -static NvU32 __nvoc_thunk_OBJGVASPACE_vaspaceGetMapPageSize(struct OBJVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { +static NvU64 __nvoc_thunk_OBJGVASPACE_vaspaceGetMapPageSize(struct OBJVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { return gvaspaceGetMapPageSize((struct OBJGVASPACE *)(((unsigned char *)pVAS) - __nvoc_rtti_OBJGVASPACE_OBJVASPACE.offset), pGpu, pMemBlock); } @@ -355,13 +355,16 @@ NV_STATUS __nvoc_objCreate_OBJGVASPACE(OBJGVASPACE **ppThis, Dynamic *pParent, N Object *pParentObj; OBJGVASPACE *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJGVASPACE)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJGVASPACE), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJGVASPACE)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJGVASPACE); + pThis->__nvoc_base_OBJVASPACE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -377,11 +380,17 @@ NV_STATUS __nvoc_objCreate_OBJGVASPACE(OBJGVASPACE **ppThis, Dynamic *pParent, N if (status != NV_OK) goto __nvoc_objCreate_OBJGVASPACE_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJGVASPACE_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJGVASPACE)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_gpu_vaspace_nvoc.h b/src/nvidia/generated/g_gpu_vaspace_nvoc.h index 9107e32d0..0d4efef87 100644 --- a/src/nvidia/generated/g_gpu_vaspace_nvoc.h +++ b/src/nvidia/generated/g_gpu_vaspace_nvoc.h @@ -227,7 +227,7 @@ struct OBJGVASPACE { NV_STATUS (*__gvaspaceMap__)(struct OBJGVASPACE *, struct OBJGPU *, const NvU64, const NvU64, const MMU_MAP_TARGET *, const VAS_MAP_FLAGS); void (*__gvaspaceUnmap__)(struct OBJGVASPACE *, struct OBJGPU *, const NvU64, const NvU64); struct OBJEHEAP *(*__gvaspaceGetHeap__)(struct OBJGVASPACE *); - NvU32 (*__gvaspaceGetMapPageSize__)(struct OBJGVASPACE *, struct OBJGPU *, EMEMBLOCK *); + NvU64 (*__gvaspaceGetMapPageSize__)(struct OBJGVASPACE *, struct OBJGPU *, EMEMBLOCK *); NvU32 (*__gvaspaceGetBigPageSize__)(struct OBJGVASPACE *); NvU32 (*__gvaspaceGetFlags__)(struct OBJGVASPACE *); NvBool (*__gvaspaceIsMirrored__)(struct OBJGVASPACE *); @@ -386,9 +386,9 @@ static inline struct OBJEHEAP *gvaspaceGetHeap_DISPATCH(struct OBJGVASPACE *pVAS return pVAS->__gvaspaceGetHeap__(pVAS); } -NvU32 gvaspaceGetMapPageSize_IMPL(struct OBJGVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock); +NvU64 gvaspaceGetMapPageSize_IMPL(struct OBJGVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock); -static inline NvU32 gvaspaceGetMapPageSize_DISPATCH(struct OBJGVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { +static inline NvU64 gvaspaceGetMapPageSize_DISPATCH(struct OBJGVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { return pVAS->__gvaspaceGetMapPageSize__(pVAS, pGpu, pMemBlock); } diff --git a/src/nvidia/generated/g_gsync_api_nvoc.c b/src/nvidia/generated/g_gsync_api_nvoc.c index 2e8a80031..14b264be5 100644 --- a/src/nvidia/generated/g_gsync_api_nvoc.c +++ b/src/nvidia/generated/g_gsync_api_nvoc.c @@ -114,10 +114,46 @@ static NV_STATUS __nvoc_thunk_RmResource_gsyncapiCheckMemInterUnmap(struct GSync return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GSyncApi_RmResource.offset), bSubdeviceHandleProvided); } +static NV_STATUS __nvoc_thunk_RsResource_gsyncapiMapTo(struct GSyncApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pParams); +} + static NvBool __nvoc_thunk_RmResource_gsyncapiAccessCallback(struct GSyncApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RmResource.offset), pInvokingClient, pAllocParams, accessRight); } +static void __nvoc_thunk_Notifier_gsyncapiSetNotificationShare(struct GSyncApi *pNotifier, struct NotifShare *pNotifShare) { + notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_GSyncApi_Notifier.offset), pNotifShare); +} + +static NvU32 __nvoc_thunk_RsResource_gsyncapiGetRefCount(struct GSyncApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_gsyncapiAddAdditionalDependants(struct RsClient *pClient, struct GSyncApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_gsyncapiControl_Prologue(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_gsyncapiUnmapFrom(struct GSyncApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_gsyncapiControl_Epilogue(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_gsyncapiControlLookup(struct GSyncApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pParams, ppEntry); +} + +static NV_STATUS __nvoc_thunk_RsResource_gsyncapiUnmap(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pCallContext, pCpuMapping); +} + static NV_STATUS __nvoc_thunk_RmResource_gsyncapiGetMemInterMapParams(struct GSyncApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GSyncApi_RmResource.offset), pParams); } @@ -126,70 +162,42 @@ static NV_STATUS __nvoc_thunk_RmResource_gsyncapiGetMemoryMappingDescriptor(stru return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GSyncApi_RmResource.offset), ppMemDesc); } -static void __nvoc_thunk_Notifier_gsyncapiSetNotificationShare(struct GSyncApi *pNotifier, struct NotifShare *pNotifShare) { - notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_GSyncApi_Notifier.offset), pNotifShare); -} - static NV_STATUS __nvoc_thunk_RsResource_gsyncapiControlFilter(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pCallContext, pParams); } -static NvU32 __nvoc_thunk_RsResource_gsyncapiGetRefCount(struct GSyncApi *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_Notifier_gsyncapiUnregisterEvent(struct GSyncApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_GSyncApi_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static NV_STATUS __nvoc_thunk_RsResource_gsyncapiUnmap(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RmResource_gsyncapiControlSerialization_Prologue(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_gsyncapiCanCopy(struct GSyncApi *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RmResource_gsyncapiControl_Prologue(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_gsyncapiMapTo(struct GSyncApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RsResource_gsyncapiAddAdditionalDependants(struct RsClient *pClient, struct GSyncApi *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pReference); -} - static void __nvoc_thunk_RsResource_gsyncapiPreDestruct(struct GSyncApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_gsyncapiUnmapFrom(struct GSyncApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_gsyncapiIsDuplicate(struct GSyncApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_gsyncapiControlSerialization_Epilogue(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_gsyncapiGetNotificationListPtr(struct GSyncApi *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_GSyncApi_Notifier.offset)); } -static void __nvoc_thunk_RmResource_gsyncapiControl_Epilogue(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RmResource.offset), pCallContext, pParams); -} - static struct NotifShare *__nvoc_thunk_Notifier_gsyncapiGetNotificationShare(struct GSyncApi *pNotifier) { return notifyGetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_GSyncApi_Notifier.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_gsyncapiControlLookup(struct GSyncApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_RsResource_gsyncapiMap(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return resMap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pCallContext, pParams, pCpuMapping); } @@ -811,44 +819,48 @@ static void __nvoc_init_funcTable_GSyncApi_1(GSyncApi *pThis) { pThis->__gsyncapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_gsyncapiCheckMemInterUnmap; + pThis->__gsyncapiMapTo__ = &__nvoc_thunk_RsResource_gsyncapiMapTo; + pThis->__gsyncapiAccessCallback__ = &__nvoc_thunk_RmResource_gsyncapiAccessCallback; + pThis->__gsyncapiSetNotificationShare__ = &__nvoc_thunk_Notifier_gsyncapiSetNotificationShare; + + pThis->__gsyncapiGetRefCount__ = &__nvoc_thunk_RsResource_gsyncapiGetRefCount; + + pThis->__gsyncapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_gsyncapiAddAdditionalDependants; + + pThis->__gsyncapiControl_Prologue__ = &__nvoc_thunk_RmResource_gsyncapiControl_Prologue; + + pThis->__gsyncapiUnmapFrom__ = &__nvoc_thunk_RsResource_gsyncapiUnmapFrom; + + pThis->__gsyncapiControl_Epilogue__ = &__nvoc_thunk_RmResource_gsyncapiControl_Epilogue; + + pThis->__gsyncapiControlLookup__ = &__nvoc_thunk_RsResource_gsyncapiControlLookup; + + pThis->__gsyncapiUnmap__ = &__nvoc_thunk_RsResource_gsyncapiUnmap; + pThis->__gsyncapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_gsyncapiGetMemInterMapParams; pThis->__gsyncapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_gsyncapiGetMemoryMappingDescriptor; - pThis->__gsyncapiSetNotificationShare__ = &__nvoc_thunk_Notifier_gsyncapiSetNotificationShare; - pThis->__gsyncapiControlFilter__ = &__nvoc_thunk_RsResource_gsyncapiControlFilter; - pThis->__gsyncapiGetRefCount__ = &__nvoc_thunk_RsResource_gsyncapiGetRefCount; - pThis->__gsyncapiUnregisterEvent__ = &__nvoc_thunk_Notifier_gsyncapiUnregisterEvent; - pThis->__gsyncapiUnmap__ = &__nvoc_thunk_RsResource_gsyncapiUnmap; + pThis->__gsyncapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_gsyncapiControlSerialization_Prologue; pThis->__gsyncapiCanCopy__ = &__nvoc_thunk_RsResource_gsyncapiCanCopy; - pThis->__gsyncapiControl_Prologue__ = &__nvoc_thunk_RmResource_gsyncapiControl_Prologue; - - pThis->__gsyncapiMapTo__ = &__nvoc_thunk_RsResource_gsyncapiMapTo; - - pThis->__gsyncapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_gsyncapiAddAdditionalDependants; - pThis->__gsyncapiPreDestruct__ = &__nvoc_thunk_RsResource_gsyncapiPreDestruct; - pThis->__gsyncapiUnmapFrom__ = &__nvoc_thunk_RsResource_gsyncapiUnmapFrom; - pThis->__gsyncapiIsDuplicate__ = &__nvoc_thunk_RsResource_gsyncapiIsDuplicate; + pThis->__gsyncapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_gsyncapiControlSerialization_Epilogue; + pThis->__gsyncapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_gsyncapiGetNotificationListPtr; - pThis->__gsyncapiControl_Epilogue__ = &__nvoc_thunk_RmResource_gsyncapiControl_Epilogue; - pThis->__gsyncapiGetNotificationShare__ = &__nvoc_thunk_Notifier_gsyncapiGetNotificationShare; - pThis->__gsyncapiControlLookup__ = &__nvoc_thunk_RsResource_gsyncapiControlLookup; - pThis->__gsyncapiMap__ = &__nvoc_thunk_RsResource_gsyncapiMap; pThis->__gsyncapiGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_gsyncapiGetOrAllocNotifShare; @@ -878,13 +890,16 @@ NV_STATUS __nvoc_objCreate_GSyncApi(GSyncApi **ppThis, Dynamic *pParent, NvU32 c Object *pParentObj; GSyncApi *pThis; - pThis = portMemAllocNonPaged(sizeof(GSyncApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(GSyncApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(GSyncApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_GSyncApi); + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -900,11 +915,17 @@ NV_STATUS __nvoc_objCreate_GSyncApi(GSyncApi **ppThis, Dynamic *pParent, NvU32 c if (status != NV_OK) goto __nvoc_objCreate_GSyncApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_GSyncApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(GSyncApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_gsync_api_nvoc.h b/src/nvidia/generated/g_gsync_api_nvoc.h index a902e7251..78d6bf0e3 100644 --- a/src/nvidia/generated/g_gsync_api_nvoc.h +++ b/src/nvidia/generated/g_gsync_api_nvoc.h @@ -91,25 +91,27 @@ struct GSyncApi { NV_STATUS (*__gsyncapiCtrlCmdGsyncSetHouseSyncMode__)(struct GSyncApi *, NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS *); NvBool (*__gsyncapiShareCallback__)(struct GSyncApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__gsyncapiCheckMemInterUnmap__)(struct GSyncApi *, NvBool); + NV_STATUS (*__gsyncapiMapTo__)(struct GSyncApi *, RS_RES_MAP_TO_PARAMS *); NvBool (*__gsyncapiAccessCallback__)(struct GSyncApi *, struct RsClient *, void *, RsAccessRight); + void (*__gsyncapiSetNotificationShare__)(struct GSyncApi *, struct NotifShare *); + NvU32 (*__gsyncapiGetRefCount__)(struct GSyncApi *); + void (*__gsyncapiAddAdditionalDependants__)(struct RsClient *, struct GSyncApi *, RsResourceRef *); + NV_STATUS (*__gsyncapiControl_Prologue__)(struct GSyncApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__gsyncapiUnmapFrom__)(struct GSyncApi *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__gsyncapiControl_Epilogue__)(struct GSyncApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__gsyncapiControlLookup__)(struct GSyncApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__gsyncapiUnmap__)(struct GSyncApi *, struct CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__gsyncapiGetMemInterMapParams__)(struct GSyncApi *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__gsyncapiGetMemoryMappingDescriptor__)(struct GSyncApi *, struct MEMORY_DESCRIPTOR **); - void (*__gsyncapiSetNotificationShare__)(struct GSyncApi *, struct NotifShare *); NV_STATUS (*__gsyncapiControlFilter__)(struct GSyncApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvU32 (*__gsyncapiGetRefCount__)(struct GSyncApi *); NV_STATUS (*__gsyncapiUnregisterEvent__)(struct GSyncApi *, NvHandle, NvHandle, NvHandle, NvHandle); - NV_STATUS (*__gsyncapiUnmap__)(struct GSyncApi *, struct CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__gsyncapiControlSerialization_Prologue__)(struct GSyncApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__gsyncapiCanCopy__)(struct GSyncApi *); - NV_STATUS (*__gsyncapiControl_Prologue__)(struct GSyncApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__gsyncapiMapTo__)(struct GSyncApi *, RS_RES_MAP_TO_PARAMS *); - void (*__gsyncapiAddAdditionalDependants__)(struct RsClient *, struct GSyncApi *, RsResourceRef *); void (*__gsyncapiPreDestruct__)(struct GSyncApi *); - NV_STATUS (*__gsyncapiUnmapFrom__)(struct GSyncApi *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__gsyncapiIsDuplicate__)(struct GSyncApi *, NvHandle, NvBool *); + void (*__gsyncapiControlSerialization_Epilogue__)(struct GSyncApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__gsyncapiGetNotificationListPtr__)(struct GSyncApi *); - void (*__gsyncapiControl_Epilogue__)(struct GSyncApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); struct NotifShare *(*__gsyncapiGetNotificationShare__)(struct GSyncApi *); - NV_STATUS (*__gsyncapiControlLookup__)(struct GSyncApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__gsyncapiMap__)(struct GSyncApi *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NV_STATUS (*__gsyncapiGetOrAllocNotifShare__)(struct GSyncApi *, NvHandle, NvHandle, struct NotifShare **); NvU32 instance; @@ -180,25 +182,27 @@ NV_STATUS __nvoc_objCreate_GSyncApi(GSyncApi**, Dynamic*, NvU32, struct CALL_CON #define gsyncapiCtrlCmdGsyncSetHouseSyncMode(pGsyncApi, pParams) gsyncapiCtrlCmdGsyncSetHouseSyncMode_DISPATCH(pGsyncApi, pParams) #define gsyncapiShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) gsyncapiShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define gsyncapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) gsyncapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define gsyncapiMapTo(pResource, pParams) gsyncapiMapTo_DISPATCH(pResource, pParams) #define gsyncapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) gsyncapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +#define gsyncapiSetNotificationShare(pNotifier, pNotifShare) gsyncapiSetNotificationShare_DISPATCH(pNotifier, pNotifShare) +#define gsyncapiGetRefCount(pResource) gsyncapiGetRefCount_DISPATCH(pResource) +#define gsyncapiAddAdditionalDependants(pClient, pResource, pReference) gsyncapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define gsyncapiControl_Prologue(pResource, pCallContext, pParams) gsyncapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define gsyncapiUnmapFrom(pResource, pParams) gsyncapiUnmapFrom_DISPATCH(pResource, pParams) +#define gsyncapiControl_Epilogue(pResource, pCallContext, pParams) gsyncapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define gsyncapiControlLookup(pResource, pParams, ppEntry) gsyncapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define gsyncapiUnmap(pResource, pCallContext, pCpuMapping) gsyncapiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define gsyncapiGetMemInterMapParams(pRmResource, pParams) gsyncapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define gsyncapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) gsyncapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define gsyncapiSetNotificationShare(pNotifier, pNotifShare) gsyncapiSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define gsyncapiControlFilter(pResource, pCallContext, pParams) gsyncapiControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define gsyncapiGetRefCount(pResource) gsyncapiGetRefCount_DISPATCH(pResource) #define gsyncapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) gsyncapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) -#define gsyncapiUnmap(pResource, pCallContext, pCpuMapping) gsyncapiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define gsyncapiControlSerialization_Prologue(pResource, pCallContext, pParams) gsyncapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define gsyncapiCanCopy(pResource) gsyncapiCanCopy_DISPATCH(pResource) -#define gsyncapiControl_Prologue(pResource, pCallContext, pParams) gsyncapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define gsyncapiMapTo(pResource, pParams) gsyncapiMapTo_DISPATCH(pResource, pParams) -#define gsyncapiAddAdditionalDependants(pClient, pResource, pReference) gsyncapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define gsyncapiPreDestruct(pResource) gsyncapiPreDestruct_DISPATCH(pResource) -#define gsyncapiUnmapFrom(pResource, pParams) gsyncapiUnmapFrom_DISPATCH(pResource, pParams) #define gsyncapiIsDuplicate(pResource, hMemory, pDuplicate) gsyncapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define gsyncapiControlSerialization_Epilogue(pResource, pCallContext, pParams) gsyncapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define gsyncapiGetNotificationListPtr(pNotifier) gsyncapiGetNotificationListPtr_DISPATCH(pNotifier) -#define gsyncapiControl_Epilogue(pResource, pCallContext, pParams) gsyncapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define gsyncapiGetNotificationShare(pNotifier) gsyncapiGetNotificationShare_DISPATCH(pNotifier) -#define gsyncapiControlLookup(pResource, pParams, ppEntry) gsyncapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define gsyncapiMap(pResource, pCallContext, pParams, pCpuMapping) gsyncapiMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) #define gsyncapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) gsyncapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) NV_STATUS gsyncapiControl_IMPL(struct GSyncApi *pGsyncApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); @@ -389,10 +393,46 @@ static inline NV_STATUS gsyncapiCheckMemInterUnmap_DISPATCH(struct GSyncApi *pRm return pRmResource->__gsyncapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } +static inline NV_STATUS gsyncapiMapTo_DISPATCH(struct GSyncApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__gsyncapiMapTo__(pResource, pParams); +} + static inline NvBool gsyncapiAccessCallback_DISPATCH(struct GSyncApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return pResource->__gsyncapiAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); } +static inline void gsyncapiSetNotificationShare_DISPATCH(struct GSyncApi *pNotifier, struct NotifShare *pNotifShare) { + pNotifier->__gsyncapiSetNotificationShare__(pNotifier, pNotifShare); +} + +static inline NvU32 gsyncapiGetRefCount_DISPATCH(struct GSyncApi *pResource) { + return pResource->__gsyncapiGetRefCount__(pResource); +} + +static inline void gsyncapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct GSyncApi *pResource, RsResourceRef *pReference) { + pResource->__gsyncapiAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS gsyncapiControl_Prologue_DISPATCH(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__gsyncapiControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS gsyncapiUnmapFrom_DISPATCH(struct GSyncApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__gsyncapiUnmapFrom__(pResource, pParams); +} + +static inline void gsyncapiControl_Epilogue_DISPATCH(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__gsyncapiControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS gsyncapiControlLookup_DISPATCH(struct GSyncApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__gsyncapiControlLookup__(pResource, pParams, ppEntry); +} + +static inline NV_STATUS gsyncapiUnmap_DISPATCH(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__gsyncapiUnmap__(pResource, pCallContext, pCpuMapping); +} + static inline NV_STATUS gsyncapiGetMemInterMapParams_DISPATCH(struct GSyncApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { return pRmResource->__gsyncapiGetMemInterMapParams__(pRmResource, pParams); } @@ -401,70 +441,42 @@ static inline NV_STATUS gsyncapiGetMemoryMappingDescriptor_DISPATCH(struct GSync return pRmResource->__gsyncapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline void gsyncapiSetNotificationShare_DISPATCH(struct GSyncApi *pNotifier, struct NotifShare *pNotifShare) { - pNotifier->__gsyncapiSetNotificationShare__(pNotifier, pNotifShare); -} - static inline NV_STATUS gsyncapiControlFilter_DISPATCH(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__gsyncapiControlFilter__(pResource, pCallContext, pParams); } -static inline NvU32 gsyncapiGetRefCount_DISPATCH(struct GSyncApi *pResource) { - return pResource->__gsyncapiGetRefCount__(pResource); -} - static inline NV_STATUS gsyncapiUnregisterEvent_DISPATCH(struct GSyncApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { return pNotifier->__gsyncapiUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } -static inline NV_STATUS gsyncapiUnmap_DISPATCH(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pResource->__gsyncapiUnmap__(pResource, pCallContext, pCpuMapping); +static inline NV_STATUS gsyncapiControlSerialization_Prologue_DISPATCH(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__gsyncapiControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool gsyncapiCanCopy_DISPATCH(struct GSyncApi *pResource) { return pResource->__gsyncapiCanCopy__(pResource); } -static inline NV_STATUS gsyncapiControl_Prologue_DISPATCH(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__gsyncapiControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS gsyncapiMapTo_DISPATCH(struct GSyncApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__gsyncapiMapTo__(pResource, pParams); -} - -static inline void gsyncapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct GSyncApi *pResource, RsResourceRef *pReference) { - pResource->__gsyncapiAddAdditionalDependants__(pClient, pResource, pReference); -} - static inline void gsyncapiPreDestruct_DISPATCH(struct GSyncApi *pResource) { pResource->__gsyncapiPreDestruct__(pResource); } -static inline NV_STATUS gsyncapiUnmapFrom_DISPATCH(struct GSyncApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__gsyncapiUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS gsyncapiIsDuplicate_DISPATCH(struct GSyncApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__gsyncapiIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void gsyncapiControlSerialization_Epilogue_DISPATCH(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__gsyncapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *gsyncapiGetNotificationListPtr_DISPATCH(struct GSyncApi *pNotifier) { return pNotifier->__gsyncapiGetNotificationListPtr__(pNotifier); } -static inline void gsyncapiControl_Epilogue_DISPATCH(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__gsyncapiControl_Epilogue__(pResource, pCallContext, pParams); -} - static inline struct NotifShare *gsyncapiGetNotificationShare_DISPATCH(struct GSyncApi *pNotifier) { return pNotifier->__gsyncapiGetNotificationShare__(pNotifier); } -static inline NV_STATUS gsyncapiControlLookup_DISPATCH(struct GSyncApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__gsyncapiControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS gsyncapiMap_DISPATCH(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return pResource->__gsyncapiMap__(pResource, pCallContext, pParams, pCpuMapping); } diff --git a/src/nvidia/generated/g_gsync_nvoc.c b/src/nvidia/generated/g_gsync_nvoc.c index 9fec6af9b..8333a8995 100644 --- a/src/nvidia/generated/g_gsync_nvoc.c +++ b/src/nvidia/generated/g_gsync_nvoc.c @@ -114,13 +114,16 @@ NV_STATUS __nvoc_objCreate_OBJGSYNCMGR(OBJGSYNCMGR **ppThis, Dynamic *pParent, N Object *pParentObj; OBJGSYNCMGR *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJGSYNCMGR)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJGSYNCMGR), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJGSYNCMGR)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJGSYNCMGR); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -136,11 +139,17 @@ NV_STATUS __nvoc_objCreate_OBJGSYNCMGR(OBJGSYNCMGR **ppThis, Dynamic *pParent, N if (status != NV_OK) goto __nvoc_objCreate_OBJGSYNCMGR_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJGSYNCMGR_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJGSYNCMGR)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_gsync_nvoc.h b/src/nvidia/generated/g_gsync_nvoc.h index 0e260023b..cf9ad3fa9 100644 --- a/src/nvidia/generated/g_gsync_nvoc.h +++ b/src/nvidia/generated/g_gsync_nvoc.h @@ -141,6 +141,8 @@ typedef NV_STATUS GsyncSetMosaic (struct OBJGPU *, PDACEXTERNALDEVICE, N typedef NV_STATUS GsyncConfigFlashGsync (struct OBJGPU *, PDACEXTERNALDEVICE, NvU32); typedef NV_STATUS GsyncGetHouseSyncMode (struct OBJGPU *, PDACEXTERNALDEVICE, NvU8*); typedef NV_STATUS GsyncSetHouseSyncMode (struct OBJGPU *, PDACEXTERNALDEVICE, NvU8); +typedef NV_STATUS GsyncGetMulDiv (struct OBJGPU *, DACEXTERNALDEVICE *, NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS *); +typedef NV_STATUS GsyncSetMulDiv (struct OBJGPU *, DACEXTERNALDEVICE *, NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS *); typedef struct GSYNC_HAL_IFACES { @@ -176,6 +178,8 @@ typedef struct GSYNC_HAL_IFACES { GsyncConfigFlashGsync *gsyncConfigFlashGsync; GsyncGetHouseSyncMode *gsyncGetHouseSyncMode; GsyncSetHouseSyncMode *gsyncSetHouseSyncMode; + GsyncGetMulDiv *gsyncGetMulDiv; + GsyncSetMulDiv *gsyncSetMulDiv; } GSYNC_HAL_IFACES; diff --git a/src/nvidia/generated/g_hal.h b/src/nvidia/generated/g_hal.h index f57724ce8..2434e9080 100644 --- a/src/nvidia/generated/g_hal.h +++ b/src/nvidia/generated/g_hal.h @@ -38,7 +38,6 @@ typedef struct IGRP_IP_VERSIONS_TABLE_INFO IGRP_IP_VERSIONS_TABLE_INFO; // generic form of Head_iGrp_ipVersions_getInfo typedef -typedef NV_STATUS IGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *); typedef void IGrp_ipVersions_install(IGRP_IP_VERSIONS_TABLE_INFO *); typedef NV_STATUS IGrp_ipVersions_wrapup(IGRP_IP_VERSIONS_TABLE_INFO *); diff --git a/src/nvidia/generated/g_hal_mgr_nvoc.c b/src/nvidia/generated/g_hal_mgr_nvoc.c index b2e449098..c6bc50995 100644 --- a/src/nvidia/generated/g_hal_mgr_nvoc.c +++ b/src/nvidia/generated/g_hal_mgr_nvoc.c @@ -114,13 +114,16 @@ NV_STATUS __nvoc_objCreate_OBJHALMGR(OBJHALMGR **ppThis, Dynamic *pParent, NvU32 Object *pParentObj; OBJHALMGR *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJHALMGR)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJHALMGR), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJHALMGR)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJHALMGR); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -136,11 +139,17 @@ NV_STATUS __nvoc_objCreate_OBJHALMGR(OBJHALMGR **ppThis, Dynamic *pParent, NvU32 if (status != NV_OK) goto __nvoc_objCreate_OBJHALMGR_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJHALMGR_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJHALMGR)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_hal_nvoc.c b/src/nvidia/generated/g_hal_nvoc.c index 2cdd8ef74..a4b5bb321 100644 --- a/src/nvidia/generated/g_hal_nvoc.c +++ b/src/nvidia/generated/g_hal_nvoc.c @@ -108,13 +108,16 @@ NV_STATUS __nvoc_objCreate_OBJHAL(OBJHAL **ppThis, Dynamic *pParent, NvU32 creat Object *pParentObj; OBJHAL *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJHAL)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJHAL), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJHAL)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJHAL); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -130,11 +133,17 @@ NV_STATUS __nvoc_objCreate_OBJHAL(OBJHAL **ppThis, Dynamic *pParent, NvU32 creat if (status != NV_OK) goto __nvoc_objCreate_OBJHAL_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJHAL_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJHAL)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_hal_nvoc.h b/src/nvidia/generated/g_hal_nvoc.h index 5d3267900..481d61fdf 100644 --- a/src/nvidia/generated/g_hal_nvoc.h +++ b/src/nvidia/generated/g_hal_nvoc.h @@ -133,12 +133,6 @@ static inline PMODULEDESCRIPTOR objhalGetModuleDescriptor(struct OBJHAL *pHal) { #undef PRIVATE_FIELD -//-------------------------------------------------------------------- -// RM routines. -//-------------------------------------------------------------------- - -NV_STATUS ipVersionsSetupHal(struct OBJGPU *, void *pDynamic, IGrp_ipVersions_getInfo getInfoFn); - #endif // _OBJHAL_H_ #ifdef __cplusplus diff --git a/src/nvidia/generated/g_hal_stubs.h b/src/nvidia/generated/g_hal_stubs.h index e02bacb06..d36ee1f7b 100644 --- a/src/nvidia/generated/g_hal_stubs.h +++ b/src/nvidia/generated/g_hal_stubs.h @@ -550,8 +550,9 @@ NV_STATUS gpioWritePinHwEnum_MISSING( return NV_ERR_NOT_SUPPORTED; } -// GPIO:hal:CHECK_PROTECTION - GPIO disabled -NV_STATUS gpioCheckProtection_MISSING( +// GPIO:hal:OUTPUT_CNTL_CHECK_PROTECTION - GPIO disabled +NV_STATUS gpioOutputCntlCheckProtection_MISSING( + POBJGPU pGpu, POBJGPIO pGpio, NvU32 gpioPin, NvBool *pbIsProtected @@ -560,6 +561,17 @@ NV_STATUS gpioCheckProtection_MISSING( return NV_ERR_NOT_SUPPORTED; } +// GPIO:hal:INPUT_CNTL_CHECK_PROTECTION - GPIO disabled +NV_STATUS gpioInputCntlCheckProtection_MISSING( + POBJGPU pGpu, + POBJGPIO pGpio, + NvU32 inputHwEnum, + NvBool *pbIsProtected +) +{ + return NV_ERR_NOT_SUPPORTED; +} + // GPIO:hal:READ_INPUT - GPIO disabled NV_STATUS gpioReadInput_FWCLIENT( POBJGPIO pGpio, @@ -888,6 +900,17 @@ NV_STATUS rpcRmfsTest_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS - RPCSTRUCTURECOPY disabled +NV_STATUS deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_STUB( + NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + // RPCSTRUCTURECOPY:hal:NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS - RPCSTRUCTURECOPY disabled NV_STATUS deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_STUB( NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *data, diff --git a/src/nvidia/generated/g_hda_codec_api_nvoc.c b/src/nvidia/generated/g_hda_codec_api_nvoc.c index fe4fed75b..aeacf574f 100644 --- a/src/nvidia/generated/g_hda_codec_api_nvoc.c +++ b/src/nvidia/generated/g_hda_codec_api_nvoc.c @@ -97,6 +97,54 @@ static NvBool __nvoc_thunk_GpuResource_hdacodecShareCallback(struct Hdacodec *pG return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Hdacodec_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } +static NV_STATUS __nvoc_thunk_RmResource_hdacodecCheckMemInterUnmap(struct Hdacodec *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Hdacodec_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_hdacodecMapTo(struct Hdacodec *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_hdacodecGetMapAddrSpace(struct Hdacodec *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Hdacodec_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_hdacodecGetRefCount(struct Hdacodec *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_hdacodecAddAdditionalDependants(struct RsClient *pClient, struct Hdacodec *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_hdacodecControl_Prologue(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_hdacodecGetRegBaseOffsetAndSize(struct Hdacodec *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Hdacodec_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_hdacodecInternalControlForward(struct Hdacodec *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Hdacodec_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_hdacodecUnmapFrom(struct Hdacodec *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_hdacodecControl_Epilogue(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_hdacodecControlLookup(struct Hdacodec *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset), pParams, ppEntry); +} + +static NvHandle __nvoc_thunk_GpuResource_hdacodecGetInternalObjectHandle(struct Hdacodec *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Hdacodec_GpuResource.offset)); +} + static NV_STATUS __nvoc_thunk_GpuResource_hdacodecControl(struct Hdacodec *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Hdacodec_GpuResource.offset), pCallContext, pParams); } @@ -113,68 +161,28 @@ static NV_STATUS __nvoc_thunk_RmResource_hdacodecGetMemoryMappingDescriptor(stru return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Hdacodec_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_GpuResource_hdacodecGetMapAddrSpace(struct Hdacodec *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Hdacodec_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvHandle __nvoc_thunk_GpuResource_hdacodecGetInternalObjectHandle(struct Hdacodec *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Hdacodec_GpuResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_hdacodecControlFilter(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_hdacodecAddAdditionalDependants(struct RsClient *pClient, struct Hdacodec *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_hdacodecGetRefCount(struct Hdacodec *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RmResource_hdacodecCheckMemInterUnmap(struct Hdacodec *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Hdacodec_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_hdacodecMapTo(struct Hdacodec *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_hdacodecControl_Prologue(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_GpuResource_hdacodecGetRegBaseOffsetAndSize(struct Hdacodec *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Hdacodec_GpuResource.offset), pGpu, pOffset, pSize); +static NV_STATUS __nvoc_thunk_RmResource_hdacodecControlSerialization_Prologue(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_hdacodecCanCopy(struct Hdacodec *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_hdacodecInternalControlForward(struct Hdacodec *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Hdacodec_GpuResource.offset), command, pParams, size); -} - static void __nvoc_thunk_RsResource_hdacodecPreDestruct(struct Hdacodec *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_hdacodecUnmapFrom(struct Hdacodec *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_hdacodecIsDuplicate(struct Hdacodec *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset), hMemory, pDuplicate); } -static void __nvoc_thunk_RmResource_hdacodecControl_Epilogue(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_hdacodecControlLookup(struct Hdacodec *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_hdacodecControlSerialization_Epilogue(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_hdacodecMap(struct Hdacodec *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -225,6 +233,30 @@ static void __nvoc_init_funcTable_Hdacodec_1(Hdacodec *pThis) { pThis->__hdacodecShareCallback__ = &__nvoc_thunk_GpuResource_hdacodecShareCallback; + pThis->__hdacodecCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_hdacodecCheckMemInterUnmap; + + pThis->__hdacodecMapTo__ = &__nvoc_thunk_RsResource_hdacodecMapTo; + + pThis->__hdacodecGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_hdacodecGetMapAddrSpace; + + pThis->__hdacodecGetRefCount__ = &__nvoc_thunk_RsResource_hdacodecGetRefCount; + + pThis->__hdacodecAddAdditionalDependants__ = &__nvoc_thunk_RsResource_hdacodecAddAdditionalDependants; + + pThis->__hdacodecControl_Prologue__ = &__nvoc_thunk_RmResource_hdacodecControl_Prologue; + + pThis->__hdacodecGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_hdacodecGetRegBaseOffsetAndSize; + + pThis->__hdacodecInternalControlForward__ = &__nvoc_thunk_GpuResource_hdacodecInternalControlForward; + + pThis->__hdacodecUnmapFrom__ = &__nvoc_thunk_RsResource_hdacodecUnmapFrom; + + pThis->__hdacodecControl_Epilogue__ = &__nvoc_thunk_RmResource_hdacodecControl_Epilogue; + + pThis->__hdacodecControlLookup__ = &__nvoc_thunk_RsResource_hdacodecControlLookup; + + pThis->__hdacodecGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_hdacodecGetInternalObjectHandle; + pThis->__hdacodecControl__ = &__nvoc_thunk_GpuResource_hdacodecControl; pThis->__hdacodecUnmap__ = &__nvoc_thunk_GpuResource_hdacodecUnmap; @@ -233,37 +265,17 @@ static void __nvoc_init_funcTable_Hdacodec_1(Hdacodec *pThis) { pThis->__hdacodecGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_hdacodecGetMemoryMappingDescriptor; - pThis->__hdacodecGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_hdacodecGetMapAddrSpace; - - pThis->__hdacodecGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_hdacodecGetInternalObjectHandle; - pThis->__hdacodecControlFilter__ = &__nvoc_thunk_RsResource_hdacodecControlFilter; - pThis->__hdacodecAddAdditionalDependants__ = &__nvoc_thunk_RsResource_hdacodecAddAdditionalDependants; - - pThis->__hdacodecGetRefCount__ = &__nvoc_thunk_RsResource_hdacodecGetRefCount; - - pThis->__hdacodecCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_hdacodecCheckMemInterUnmap; - - pThis->__hdacodecMapTo__ = &__nvoc_thunk_RsResource_hdacodecMapTo; - - pThis->__hdacodecControl_Prologue__ = &__nvoc_thunk_RmResource_hdacodecControl_Prologue; - - pThis->__hdacodecGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_hdacodecGetRegBaseOffsetAndSize; + pThis->__hdacodecControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_hdacodecControlSerialization_Prologue; pThis->__hdacodecCanCopy__ = &__nvoc_thunk_RsResource_hdacodecCanCopy; - pThis->__hdacodecInternalControlForward__ = &__nvoc_thunk_GpuResource_hdacodecInternalControlForward; - pThis->__hdacodecPreDestruct__ = &__nvoc_thunk_RsResource_hdacodecPreDestruct; - pThis->__hdacodecUnmapFrom__ = &__nvoc_thunk_RsResource_hdacodecUnmapFrom; - pThis->__hdacodecIsDuplicate__ = &__nvoc_thunk_RsResource_hdacodecIsDuplicate; - pThis->__hdacodecControl_Epilogue__ = &__nvoc_thunk_RmResource_hdacodecControl_Epilogue; - - pThis->__hdacodecControlLookup__ = &__nvoc_thunk_RsResource_hdacodecControlLookup; + pThis->__hdacodecControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_hdacodecControlSerialization_Epilogue; pThis->__hdacodecMap__ = &__nvoc_thunk_GpuResource_hdacodecMap; @@ -291,13 +303,16 @@ NV_STATUS __nvoc_objCreate_Hdacodec(Hdacodec **ppThis, Dynamic *pParent, NvU32 c Object *pParentObj; Hdacodec *pThis; - pThis = portMemAllocNonPaged(sizeof(Hdacodec)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Hdacodec), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(Hdacodec)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Hdacodec); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -313,11 +328,17 @@ NV_STATUS __nvoc_objCreate_Hdacodec(Hdacodec **ppThis, Dynamic *pParent, NvU32 c if (status != NV_OK) goto __nvoc_objCreate_Hdacodec_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_Hdacodec_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(Hdacodec)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_hda_codec_api_nvoc.h b/src/nvidia/generated/g_hda_codec_api_nvoc.h index 22590ee9e..9efd54290 100644 --- a/src/nvidia/generated/g_hda_codec_api_nvoc.h +++ b/src/nvidia/generated/g_hda_codec_api_nvoc.h @@ -55,26 +55,28 @@ struct Hdacodec { struct GpuResource *__nvoc_pbase_GpuResource; struct Hdacodec *__nvoc_pbase_Hdacodec; NvBool (*__hdacodecShareCallback__)(struct Hdacodec *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__hdacodecCheckMemInterUnmap__)(struct Hdacodec *, NvBool); + NV_STATUS (*__hdacodecMapTo__)(struct Hdacodec *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__hdacodecGetMapAddrSpace__)(struct Hdacodec *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__hdacodecGetRefCount__)(struct Hdacodec *); + void (*__hdacodecAddAdditionalDependants__)(struct RsClient *, struct Hdacodec *, RsResourceRef *); + NV_STATUS (*__hdacodecControl_Prologue__)(struct Hdacodec *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__hdacodecGetRegBaseOffsetAndSize__)(struct Hdacodec *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__hdacodecInternalControlForward__)(struct Hdacodec *, NvU32, void *, NvU32); + NV_STATUS (*__hdacodecUnmapFrom__)(struct Hdacodec *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__hdacodecControl_Epilogue__)(struct Hdacodec *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__hdacodecControlLookup__)(struct Hdacodec *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__hdacodecGetInternalObjectHandle__)(struct Hdacodec *); NV_STATUS (*__hdacodecControl__)(struct Hdacodec *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__hdacodecUnmap__)(struct Hdacodec *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__hdacodecGetMemInterMapParams__)(struct Hdacodec *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__hdacodecGetMemoryMappingDescriptor__)(struct Hdacodec *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__hdacodecGetMapAddrSpace__)(struct Hdacodec *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__hdacodecGetInternalObjectHandle__)(struct Hdacodec *); NV_STATUS (*__hdacodecControlFilter__)(struct Hdacodec *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__hdacodecAddAdditionalDependants__)(struct RsClient *, struct Hdacodec *, RsResourceRef *); - NvU32 (*__hdacodecGetRefCount__)(struct Hdacodec *); - NV_STATUS (*__hdacodecCheckMemInterUnmap__)(struct Hdacodec *, NvBool); - NV_STATUS (*__hdacodecMapTo__)(struct Hdacodec *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__hdacodecControl_Prologue__)(struct Hdacodec *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__hdacodecGetRegBaseOffsetAndSize__)(struct Hdacodec *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__hdacodecControlSerialization_Prologue__)(struct Hdacodec *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__hdacodecCanCopy__)(struct Hdacodec *); - NV_STATUS (*__hdacodecInternalControlForward__)(struct Hdacodec *, NvU32, void *, NvU32); void (*__hdacodecPreDestruct__)(struct Hdacodec *); - NV_STATUS (*__hdacodecUnmapFrom__)(struct Hdacodec *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__hdacodecIsDuplicate__)(struct Hdacodec *, NvHandle, NvBool *); - void (*__hdacodecControl_Epilogue__)(struct Hdacodec *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__hdacodecControlLookup__)(struct Hdacodec *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__hdacodecControlSerialization_Epilogue__)(struct Hdacodec *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__hdacodecMap__)(struct Hdacodec *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__hdacodecAccessCallback__)(struct Hdacodec *, struct RsClient *, void *, RsAccessRight); }; @@ -108,32 +110,82 @@ NV_STATUS __nvoc_objCreate_Hdacodec(Hdacodec**, Dynamic*, NvU32, struct CALL_CON __nvoc_objCreate_Hdacodec((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) #define hdacodecShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) hdacodecShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define hdacodecCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) hdacodecCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define hdacodecMapTo(pResource, pParams) hdacodecMapTo_DISPATCH(pResource, pParams) +#define hdacodecGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) hdacodecGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define hdacodecGetRefCount(pResource) hdacodecGetRefCount_DISPATCH(pResource) +#define hdacodecAddAdditionalDependants(pClient, pResource, pReference) hdacodecAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define hdacodecControl_Prologue(pResource, pCallContext, pParams) hdacodecControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define hdacodecGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) hdacodecGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define hdacodecInternalControlForward(pGpuResource, command, pParams, size) hdacodecInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define hdacodecUnmapFrom(pResource, pParams) hdacodecUnmapFrom_DISPATCH(pResource, pParams) +#define hdacodecControl_Epilogue(pResource, pCallContext, pParams) hdacodecControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define hdacodecControlLookup(pResource, pParams, ppEntry) hdacodecControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define hdacodecGetInternalObjectHandle(pGpuResource) hdacodecGetInternalObjectHandle_DISPATCH(pGpuResource) #define hdacodecControl(pGpuResource, pCallContext, pParams) hdacodecControl_DISPATCH(pGpuResource, pCallContext, pParams) #define hdacodecUnmap(pGpuResource, pCallContext, pCpuMapping) hdacodecUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define hdacodecGetMemInterMapParams(pRmResource, pParams) hdacodecGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define hdacodecGetMemoryMappingDescriptor(pRmResource, ppMemDesc) hdacodecGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define hdacodecGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) hdacodecGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define hdacodecGetInternalObjectHandle(pGpuResource) hdacodecGetInternalObjectHandle_DISPATCH(pGpuResource) #define hdacodecControlFilter(pResource, pCallContext, pParams) hdacodecControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define hdacodecAddAdditionalDependants(pClient, pResource, pReference) hdacodecAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define hdacodecGetRefCount(pResource) hdacodecGetRefCount_DISPATCH(pResource) -#define hdacodecCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) hdacodecCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define hdacodecMapTo(pResource, pParams) hdacodecMapTo_DISPATCH(pResource, pParams) -#define hdacodecControl_Prologue(pResource, pCallContext, pParams) hdacodecControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define hdacodecGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) hdacodecGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define hdacodecControlSerialization_Prologue(pResource, pCallContext, pParams) hdacodecControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define hdacodecCanCopy(pResource) hdacodecCanCopy_DISPATCH(pResource) -#define hdacodecInternalControlForward(pGpuResource, command, pParams, size) hdacodecInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define hdacodecPreDestruct(pResource) hdacodecPreDestruct_DISPATCH(pResource) -#define hdacodecUnmapFrom(pResource, pParams) hdacodecUnmapFrom_DISPATCH(pResource, pParams) #define hdacodecIsDuplicate(pResource, hMemory, pDuplicate) hdacodecIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) -#define hdacodecControl_Epilogue(pResource, pCallContext, pParams) hdacodecControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define hdacodecControlLookup(pResource, pParams, ppEntry) hdacodecControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define hdacodecControlSerialization_Epilogue(pResource, pCallContext, pParams) hdacodecControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define hdacodecMap(pGpuResource, pCallContext, pParams, pCpuMapping) hdacodecMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define hdacodecAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) hdacodecAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) static inline NvBool hdacodecShareCallback_DISPATCH(struct Hdacodec *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__hdacodecShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } +static inline NV_STATUS hdacodecCheckMemInterUnmap_DISPATCH(struct Hdacodec *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__hdacodecCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS hdacodecMapTo_DISPATCH(struct Hdacodec *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__hdacodecMapTo__(pResource, pParams); +} + +static inline NV_STATUS hdacodecGetMapAddrSpace_DISPATCH(struct Hdacodec *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__hdacodecGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 hdacodecGetRefCount_DISPATCH(struct Hdacodec *pResource) { + return pResource->__hdacodecGetRefCount__(pResource); +} + +static inline void hdacodecAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct Hdacodec *pResource, RsResourceRef *pReference) { + pResource->__hdacodecAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS hdacodecControl_Prologue_DISPATCH(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__hdacodecControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS hdacodecGetRegBaseOffsetAndSize_DISPATCH(struct Hdacodec *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__hdacodecGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS hdacodecInternalControlForward_DISPATCH(struct Hdacodec *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__hdacodecInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS hdacodecUnmapFrom_DISPATCH(struct Hdacodec *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__hdacodecUnmapFrom__(pResource, pParams); +} + +static inline void hdacodecControl_Epilogue_DISPATCH(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__hdacodecControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS hdacodecControlLookup_DISPATCH(struct Hdacodec *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__hdacodecControlLookup__(pResource, pParams, ppEntry); +} + +static inline NvHandle hdacodecGetInternalObjectHandle_DISPATCH(struct Hdacodec *pGpuResource) { + return pGpuResource->__hdacodecGetInternalObjectHandle__(pGpuResource); +} + static inline NV_STATUS hdacodecControl_DISPATCH(struct Hdacodec *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pGpuResource->__hdacodecControl__(pGpuResource, pCallContext, pParams); } @@ -150,68 +202,28 @@ static inline NV_STATUS hdacodecGetMemoryMappingDescriptor_DISPATCH(struct Hdaco return pRmResource->__hdacodecGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS hdacodecGetMapAddrSpace_DISPATCH(struct Hdacodec *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__hdacodecGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvHandle hdacodecGetInternalObjectHandle_DISPATCH(struct Hdacodec *pGpuResource) { - return pGpuResource->__hdacodecGetInternalObjectHandle__(pGpuResource); -} - static inline NV_STATUS hdacodecControlFilter_DISPATCH(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__hdacodecControlFilter__(pResource, pCallContext, pParams); } -static inline void hdacodecAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct Hdacodec *pResource, RsResourceRef *pReference) { - pResource->__hdacodecAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 hdacodecGetRefCount_DISPATCH(struct Hdacodec *pResource) { - return pResource->__hdacodecGetRefCount__(pResource); -} - -static inline NV_STATUS hdacodecCheckMemInterUnmap_DISPATCH(struct Hdacodec *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__hdacodecCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS hdacodecMapTo_DISPATCH(struct Hdacodec *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__hdacodecMapTo__(pResource, pParams); -} - -static inline NV_STATUS hdacodecControl_Prologue_DISPATCH(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__hdacodecControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS hdacodecGetRegBaseOffsetAndSize_DISPATCH(struct Hdacodec *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__hdacodecGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +static inline NV_STATUS hdacodecControlSerialization_Prologue_DISPATCH(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__hdacodecControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool hdacodecCanCopy_DISPATCH(struct Hdacodec *pResource) { return pResource->__hdacodecCanCopy__(pResource); } -static inline NV_STATUS hdacodecInternalControlForward_DISPATCH(struct Hdacodec *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__hdacodecInternalControlForward__(pGpuResource, command, pParams, size); -} - static inline void hdacodecPreDestruct_DISPATCH(struct Hdacodec *pResource) { pResource->__hdacodecPreDestruct__(pResource); } -static inline NV_STATUS hdacodecUnmapFrom_DISPATCH(struct Hdacodec *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__hdacodecUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS hdacodecIsDuplicate_DISPATCH(struct Hdacodec *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__hdacodecIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline void hdacodecControl_Epilogue_DISPATCH(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__hdacodecControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS hdacodecControlLookup_DISPATCH(struct Hdacodec *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__hdacodecControlLookup__(pResource, pParams, ppEntry); +static inline void hdacodecControlSerialization_Epilogue_DISPATCH(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__hdacodecControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS hdacodecMap_DISPATCH(struct Hdacodec *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_heap_nvoc.c b/src/nvidia/generated/g_heap_nvoc.c index 9583b7e78..bdd853d0c 100644 --- a/src/nvidia/generated/g_heap_nvoc.c +++ b/src/nvidia/generated/g_heap_nvoc.c @@ -109,13 +109,16 @@ NV_STATUS __nvoc_objCreate_Heap(Heap **ppThis, Dynamic *pParent, NvU32 createFla Object *pParentObj; Heap *pThis; - pThis = portMemAllocNonPaged(sizeof(Heap)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Heap), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(Heap)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Heap); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -131,11 +134,17 @@ NV_STATUS __nvoc_objCreate_Heap(Heap **ppThis, Dynamic *pParent, NvU32 createFla if (status != NV_OK) goto __nvoc_objCreate_Heap_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_Heap_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(Heap)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_host_eng_nvoc.c b/src/nvidia/generated/g_host_eng_nvoc.c index 5e2b392c8..9286db148 100644 --- a/src/nvidia/generated/g_host_eng_nvoc.c +++ b/src/nvidia/generated/g_host_eng_nvoc.c @@ -76,11 +76,7 @@ __nvoc_ctor_OBJHOSTENG_exit: static void __nvoc_init_funcTable_OBJHOSTENG_1(OBJHOSTENG *pThis) { PORT_UNREFERENCED_VARIABLE(pThis); - pThis->__hostengHaltEngine__ = &hostengHaltEngine_IMPL; - pThis->__hostengHaltAndReset__ = &hostengHaltAndReset_IMPL; - - pThis->__hostengReset__ = &hostengReset_IMPL; } void __nvoc_init_funcTable_OBJHOSTENG(OBJHOSTENG *pThis) { diff --git a/src/nvidia/generated/g_host_eng_nvoc.h b/src/nvidia/generated/g_host_eng_nvoc.h index db1a743c3..0fcfed85c 100644 --- a/src/nvidia/generated/g_host_eng_nvoc.h +++ b/src/nvidia/generated/g_host_eng_nvoc.h @@ -57,9 +57,7 @@ typedef struct OBJHOSTENG *POBJHOSTENG; struct OBJHOSTENG { const struct NVOC_RTTI *__nvoc_rtti; struct OBJHOSTENG *__nvoc_pbase_OBJHOSTENG; - NV_STATUS (*__hostengHaltEngine__)(struct OBJGPU *, struct OBJHOSTENG *); NV_STATUS (*__hostengHaltAndReset__)(struct OBJGPU *, struct OBJHOSTENG *, RMTIMEOUT *); - NV_STATUS (*__hostengReset__)(struct OBJGPU *, struct OBJHOSTENG *, NvBool, struct KernelChannel *, struct KernelChannel **); }; #ifndef __NVOC_CLASS_OBJHOSTENG_TYPEDEF__ @@ -90,27 +88,13 @@ NV_STATUS __nvoc_objCreate_OBJHOSTENG(OBJHOSTENG**, Dynamic*, NvU32); #define __objCreate_OBJHOSTENG(ppNewObj, pParent, createFlags) \ __nvoc_objCreate_OBJHOSTENG((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) -#define hostengHaltEngine(pGpu, pHosteng) hostengHaltEngine_DISPATCH(pGpu, pHosteng) #define hostengHaltAndReset(pGpu, pHosteng, pRmTimeout) hostengHaltAndReset_DISPATCH(pGpu, pHosteng, pRmTimeout) -#define hostengReset(pGpu, pHosteng, bReload, pKernelChannel, ppCurrentKernelChannel) hostengReset_DISPATCH(pGpu, pHosteng, bReload, pKernelChannel, ppCurrentKernelChannel) -NV_STATUS hostengHaltEngine_IMPL(struct OBJGPU *pGpu, struct OBJHOSTENG *pHosteng); - -static inline NV_STATUS hostengHaltEngine_DISPATCH(struct OBJGPU *pGpu, struct OBJHOSTENG *pHosteng) { - return pHosteng->__hostengHaltEngine__(pGpu, pHosteng); -} - NV_STATUS hostengHaltAndReset_IMPL(struct OBJGPU *pGpu, struct OBJHOSTENG *pHosteng, RMTIMEOUT *pRmTimeout); static inline NV_STATUS hostengHaltAndReset_DISPATCH(struct OBJGPU *pGpu, struct OBJHOSTENG *pHosteng, RMTIMEOUT *pRmTimeout) { return pHosteng->__hostengHaltAndReset__(pGpu, pHosteng, pRmTimeout); } -NV_STATUS hostengReset_IMPL(struct OBJGPU *pGpu, struct OBJHOSTENG *pHosteng, NvBool bReload, struct KernelChannel *pKernelChannel, struct KernelChannel **ppCurrentKernelChannel); - -static inline NV_STATUS hostengReset_DISPATCH(struct OBJGPU *pGpu, struct OBJHOSTENG *pHosteng, NvBool bReload, struct KernelChannel *pKernelChannel, struct KernelChannel **ppCurrentKernelChannel) { - return pHosteng->__hostengReset__(pGpu, pHosteng, bReload, pKernelChannel, ppCurrentKernelChannel); -} - #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_hw_resources_nvoc.c b/src/nvidia/generated/g_hw_resources_nvoc.c index 3a20492d0..adb0378bf 100644 --- a/src/nvidia/generated/g_hw_resources_nvoc.c +++ b/src/nvidia/generated/g_hw_resources_nvoc.c @@ -101,6 +101,46 @@ static NV_STATUS __nvoc_thunk_Memory_hwresCheckMemInterUnmap(struct MemoryHwReso return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), bSubdeviceHandleProvided); } +static NvBool __nvoc_thunk_RmResource_hwresShareCallback(struct MemoryHwResources *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RsResource_hwresMapTo(struct MemoryHwResources *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_hwresGetMapAddrSpace(struct MemoryHwResources *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_hwresGetRefCount(struct MemoryHwResources *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_hwresAddAdditionalDependants(struct RsClient *pClient, struct MemoryHwResources *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_hwresControl_Prologue(struct MemoryHwResources *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_Memory_hwresIsGpuMapAllowed(struct MemoryHwResources *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), pGpu); +} + +static NV_STATUS __nvoc_thunk_RsResource_hwresUnmapFrom(struct MemoryHwResources *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_hwresControl_Epilogue(struct MemoryHwResources *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_hwresControlLookup(struct MemoryHwResources *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RsResource.offset), pParams, ppEntry); +} + static NV_STATUS __nvoc_thunk_Memory_hwresControl(struct MemoryHwResources *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), pCallContext, pParams); } @@ -117,36 +157,12 @@ static NV_STATUS __nvoc_thunk_Memory_hwresGetMemoryMappingDescriptor(struct Memo return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_Memory_hwresGetMapAddrSpace(struct MemoryHwResources *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvBool __nvoc_thunk_RmResource_hwresShareCallback(struct MemoryHwResources *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); -} - static NV_STATUS __nvoc_thunk_RsResource_hwresControlFilter(struct MemoryHwResources *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_hwresAddAdditionalDependants(struct RsClient *pClient, struct MemoryHwResources *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_hwresGetRefCount(struct MemoryHwResources *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RsResource_hwresMapTo(struct MemoryHwResources *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_hwresControl_Prologue(struct MemoryHwResources *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RmResource.offset), pCallContext, pParams); -} - -static NvBool __nvoc_thunk_Memory_hwresIsGpuMapAllowed(struct MemoryHwResources *pMemory, struct OBJGPU *pGpu) { - return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), pGpu); +static NV_STATUS __nvoc_thunk_RmResource_hwresControlSerialization_Prologue(struct MemoryHwResources *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_hwresIsReady(struct MemoryHwResources *pMemory, NvBool bCopyConstructorContext) { @@ -165,16 +181,8 @@ static NV_STATUS __nvoc_thunk_Memory_hwresIsDuplicate(struct MemoryHwResources * return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), hMemory, pDuplicate); } -static NV_STATUS __nvoc_thunk_RsResource_hwresUnmapFrom(struct MemoryHwResources *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RmResource_hwresControl_Epilogue(struct MemoryHwResources *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_hwresControlLookup(struct MemoryHwResources *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_hwresControlSerialization_Epilogue(struct MemoryHwResources *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_hwresMap(struct MemoryHwResources *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -230,6 +238,26 @@ static void __nvoc_init_funcTable_MemoryHwResources_1(MemoryHwResources *pThis) pThis->__hwresCheckMemInterUnmap__ = &__nvoc_thunk_Memory_hwresCheckMemInterUnmap; + pThis->__hwresShareCallback__ = &__nvoc_thunk_RmResource_hwresShareCallback; + + pThis->__hwresMapTo__ = &__nvoc_thunk_RsResource_hwresMapTo; + + pThis->__hwresGetMapAddrSpace__ = &__nvoc_thunk_Memory_hwresGetMapAddrSpace; + + pThis->__hwresGetRefCount__ = &__nvoc_thunk_RsResource_hwresGetRefCount; + + pThis->__hwresAddAdditionalDependants__ = &__nvoc_thunk_RsResource_hwresAddAdditionalDependants; + + pThis->__hwresControl_Prologue__ = &__nvoc_thunk_RmResource_hwresControl_Prologue; + + pThis->__hwresIsGpuMapAllowed__ = &__nvoc_thunk_Memory_hwresIsGpuMapAllowed; + + pThis->__hwresUnmapFrom__ = &__nvoc_thunk_RsResource_hwresUnmapFrom; + + pThis->__hwresControl_Epilogue__ = &__nvoc_thunk_RmResource_hwresControl_Epilogue; + + pThis->__hwresControlLookup__ = &__nvoc_thunk_RsResource_hwresControlLookup; + pThis->__hwresControl__ = &__nvoc_thunk_Memory_hwresControl; pThis->__hwresUnmap__ = &__nvoc_thunk_Memory_hwresUnmap; @@ -238,21 +266,9 @@ static void __nvoc_init_funcTable_MemoryHwResources_1(MemoryHwResources *pThis) pThis->__hwresGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_hwresGetMemoryMappingDescriptor; - pThis->__hwresGetMapAddrSpace__ = &__nvoc_thunk_Memory_hwresGetMapAddrSpace; - - pThis->__hwresShareCallback__ = &__nvoc_thunk_RmResource_hwresShareCallback; - pThis->__hwresControlFilter__ = &__nvoc_thunk_RsResource_hwresControlFilter; - pThis->__hwresAddAdditionalDependants__ = &__nvoc_thunk_RsResource_hwresAddAdditionalDependants; - - pThis->__hwresGetRefCount__ = &__nvoc_thunk_RsResource_hwresGetRefCount; - - pThis->__hwresMapTo__ = &__nvoc_thunk_RsResource_hwresMapTo; - - pThis->__hwresControl_Prologue__ = &__nvoc_thunk_RmResource_hwresControl_Prologue; - - pThis->__hwresIsGpuMapAllowed__ = &__nvoc_thunk_Memory_hwresIsGpuMapAllowed; + pThis->__hwresControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_hwresControlSerialization_Prologue; pThis->__hwresIsReady__ = &__nvoc_thunk_Memory_hwresIsReady; @@ -262,11 +278,7 @@ static void __nvoc_init_funcTable_MemoryHwResources_1(MemoryHwResources *pThis) pThis->__hwresIsDuplicate__ = &__nvoc_thunk_Memory_hwresIsDuplicate; - pThis->__hwresUnmapFrom__ = &__nvoc_thunk_RsResource_hwresUnmapFrom; - - pThis->__hwresControl_Epilogue__ = &__nvoc_thunk_RmResource_hwresControl_Epilogue; - - pThis->__hwresControlLookup__ = &__nvoc_thunk_RsResource_hwresControlLookup; + pThis->__hwresControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_hwresControlSerialization_Epilogue; pThis->__hwresMap__ = &__nvoc_thunk_Memory_hwresMap; @@ -294,13 +306,16 @@ NV_STATUS __nvoc_objCreate_MemoryHwResources(MemoryHwResources **ppThis, Dynamic Object *pParentObj; MemoryHwResources *pThis; - pThis = portMemAllocNonPaged(sizeof(MemoryHwResources)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MemoryHwResources), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(MemoryHwResources)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MemoryHwResources); + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -316,11 +331,17 @@ NV_STATUS __nvoc_objCreate_MemoryHwResources(MemoryHwResources **ppThis, Dynamic if (status != NV_OK) goto __nvoc_objCreate_MemoryHwResources_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_MemoryHwResources_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(MemoryHwResources)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_hw_resources_nvoc.h b/src/nvidia/generated/g_hw_resources_nvoc.h index 8da45bd94..a284f6662 100644 --- a/src/nvidia/generated/g_hw_resources_nvoc.h +++ b/src/nvidia/generated/g_hw_resources_nvoc.h @@ -55,25 +55,27 @@ struct MemoryHwResources { struct MemoryHwResources *__nvoc_pbase_MemoryHwResources; NvBool (*__hwresCanCopy__)(struct MemoryHwResources *); NV_STATUS (*__hwresCheckMemInterUnmap__)(struct MemoryHwResources *, NvBool); + NvBool (*__hwresShareCallback__)(struct MemoryHwResources *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__hwresMapTo__)(struct MemoryHwResources *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__hwresGetMapAddrSpace__)(struct MemoryHwResources *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__hwresGetRefCount__)(struct MemoryHwResources *); + void (*__hwresAddAdditionalDependants__)(struct RsClient *, struct MemoryHwResources *, RsResourceRef *); + NV_STATUS (*__hwresControl_Prologue__)(struct MemoryHwResources *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__hwresIsGpuMapAllowed__)(struct MemoryHwResources *, struct OBJGPU *); + NV_STATUS (*__hwresUnmapFrom__)(struct MemoryHwResources *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__hwresControl_Epilogue__)(struct MemoryHwResources *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__hwresControlLookup__)(struct MemoryHwResources *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__hwresControl__)(struct MemoryHwResources *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__hwresUnmap__)(struct MemoryHwResources *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__hwresGetMemInterMapParams__)(struct MemoryHwResources *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__hwresGetMemoryMappingDescriptor__)(struct MemoryHwResources *, MEMORY_DESCRIPTOR **); - NV_STATUS (*__hwresGetMapAddrSpace__)(struct MemoryHwResources *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvBool (*__hwresShareCallback__)(struct MemoryHwResources *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__hwresControlFilter__)(struct MemoryHwResources *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__hwresAddAdditionalDependants__)(struct RsClient *, struct MemoryHwResources *, RsResourceRef *); - NvU32 (*__hwresGetRefCount__)(struct MemoryHwResources *); - NV_STATUS (*__hwresMapTo__)(struct MemoryHwResources *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__hwresControl_Prologue__)(struct MemoryHwResources *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvBool (*__hwresIsGpuMapAllowed__)(struct MemoryHwResources *, struct OBJGPU *); + NV_STATUS (*__hwresControlSerialization_Prologue__)(struct MemoryHwResources *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__hwresIsReady__)(struct MemoryHwResources *, NvBool); NV_STATUS (*__hwresCheckCopyPermissions__)(struct MemoryHwResources *, struct OBJGPU *, NvHandle); void (*__hwresPreDestruct__)(struct MemoryHwResources *); NV_STATUS (*__hwresIsDuplicate__)(struct MemoryHwResources *, NvHandle, NvBool *); - NV_STATUS (*__hwresUnmapFrom__)(struct MemoryHwResources *, RS_RES_UNMAP_FROM_PARAMS *); - void (*__hwresControl_Epilogue__)(struct MemoryHwResources *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__hwresControlLookup__)(struct MemoryHwResources *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__hwresControlSerialization_Epilogue__)(struct MemoryHwResources *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__hwresMap__)(struct MemoryHwResources *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__hwresAccessCallback__)(struct MemoryHwResources *, struct RsClient *, void *, RsAccessRight); }; @@ -108,25 +110,27 @@ NV_STATUS __nvoc_objCreate_MemoryHwResources(MemoryHwResources**, Dynamic*, NvU3 #define hwresCanCopy(pMemoryHwResources) hwresCanCopy_DISPATCH(pMemoryHwResources) #define hwresCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) hwresCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define hwresShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) hwresShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define hwresMapTo(pResource, pParams) hwresMapTo_DISPATCH(pResource, pParams) +#define hwresGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) hwresGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define hwresGetRefCount(pResource) hwresGetRefCount_DISPATCH(pResource) +#define hwresAddAdditionalDependants(pClient, pResource, pReference) hwresAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define hwresControl_Prologue(pResource, pCallContext, pParams) hwresControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define hwresIsGpuMapAllowed(pMemory, pGpu) hwresIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define hwresUnmapFrom(pResource, pParams) hwresUnmapFrom_DISPATCH(pResource, pParams) +#define hwresControl_Epilogue(pResource, pCallContext, pParams) hwresControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define hwresControlLookup(pResource, pParams, ppEntry) hwresControlLookup_DISPATCH(pResource, pParams, ppEntry) #define hwresControl(pMemory, pCallContext, pParams) hwresControl_DISPATCH(pMemory, pCallContext, pParams) #define hwresUnmap(pMemory, pCallContext, pCpuMapping) hwresUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define hwresGetMemInterMapParams(pMemory, pParams) hwresGetMemInterMapParams_DISPATCH(pMemory, pParams) #define hwresGetMemoryMappingDescriptor(pMemory, ppMemDesc) hwresGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define hwresGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) hwresGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) -#define hwresShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) hwresShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define hwresControlFilter(pResource, pCallContext, pParams) hwresControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define hwresAddAdditionalDependants(pClient, pResource, pReference) hwresAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define hwresGetRefCount(pResource) hwresGetRefCount_DISPATCH(pResource) -#define hwresMapTo(pResource, pParams) hwresMapTo_DISPATCH(pResource, pParams) -#define hwresControl_Prologue(pResource, pCallContext, pParams) hwresControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define hwresIsGpuMapAllowed(pMemory, pGpu) hwresIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define hwresControlSerialization_Prologue(pResource, pCallContext, pParams) hwresControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define hwresIsReady(pMemory, bCopyConstructorContext) hwresIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define hwresCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) hwresCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) #define hwresPreDestruct(pResource) hwresPreDestruct_DISPATCH(pResource) #define hwresIsDuplicate(pMemory, hMemory, pDuplicate) hwresIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) -#define hwresUnmapFrom(pResource, pParams) hwresUnmapFrom_DISPATCH(pResource, pParams) -#define hwresControl_Epilogue(pResource, pCallContext, pParams) hwresControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define hwresControlLookup(pResource, pParams, ppEntry) hwresControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define hwresControlSerialization_Epilogue(pResource, pCallContext, pParams) hwresControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define hwresMap(pMemory, pCallContext, pParams, pCpuMapping) hwresMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define hwresAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) hwresAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool hwresCanCopy_IMPL(struct MemoryHwResources *pMemoryHwResources); @@ -139,6 +143,46 @@ static inline NV_STATUS hwresCheckMemInterUnmap_DISPATCH(struct MemoryHwResource return pMemory->__hwresCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } +static inline NvBool hwresShareCallback_DISPATCH(struct MemoryHwResources *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__hwresShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS hwresMapTo_DISPATCH(struct MemoryHwResources *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__hwresMapTo__(pResource, pParams); +} + +static inline NV_STATUS hwresGetMapAddrSpace_DISPATCH(struct MemoryHwResources *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__hwresGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 hwresGetRefCount_DISPATCH(struct MemoryHwResources *pResource) { + return pResource->__hwresGetRefCount__(pResource); +} + +static inline void hwresAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct MemoryHwResources *pResource, RsResourceRef *pReference) { + pResource->__hwresAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS hwresControl_Prologue_DISPATCH(struct MemoryHwResources *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__hwresControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool hwresIsGpuMapAllowed_DISPATCH(struct MemoryHwResources *pMemory, struct OBJGPU *pGpu) { + return pMemory->__hwresIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline NV_STATUS hwresUnmapFrom_DISPATCH(struct MemoryHwResources *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__hwresUnmapFrom__(pResource, pParams); +} + +static inline void hwresControl_Epilogue_DISPATCH(struct MemoryHwResources *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__hwresControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS hwresControlLookup_DISPATCH(struct MemoryHwResources *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__hwresControlLookup__(pResource, pParams, ppEntry); +} + static inline NV_STATUS hwresControl_DISPATCH(struct MemoryHwResources *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pMemory->__hwresControl__(pMemory, pCallContext, pParams); } @@ -155,36 +199,12 @@ static inline NV_STATUS hwresGetMemoryMappingDescriptor_DISPATCH(struct MemoryHw return pMemory->__hwresGetMemoryMappingDescriptor__(pMemory, ppMemDesc); } -static inline NV_STATUS hwresGetMapAddrSpace_DISPATCH(struct MemoryHwResources *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pMemory->__hwresGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvBool hwresShareCallback_DISPATCH(struct MemoryHwResources *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pResource->__hwresShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); -} - static inline NV_STATUS hwresControlFilter_DISPATCH(struct MemoryHwResources *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__hwresControlFilter__(pResource, pCallContext, pParams); } -static inline void hwresAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct MemoryHwResources *pResource, RsResourceRef *pReference) { - pResource->__hwresAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 hwresGetRefCount_DISPATCH(struct MemoryHwResources *pResource) { - return pResource->__hwresGetRefCount__(pResource); -} - -static inline NV_STATUS hwresMapTo_DISPATCH(struct MemoryHwResources *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__hwresMapTo__(pResource, pParams); -} - -static inline NV_STATUS hwresControl_Prologue_DISPATCH(struct MemoryHwResources *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__hwresControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NvBool hwresIsGpuMapAllowed_DISPATCH(struct MemoryHwResources *pMemory, struct OBJGPU *pGpu) { - return pMemory->__hwresIsGpuMapAllowed__(pMemory, pGpu); +static inline NV_STATUS hwresControlSerialization_Prologue_DISPATCH(struct MemoryHwResources *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__hwresControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS hwresIsReady_DISPATCH(struct MemoryHwResources *pMemory, NvBool bCopyConstructorContext) { @@ -203,16 +223,8 @@ static inline NV_STATUS hwresIsDuplicate_DISPATCH(struct MemoryHwResources *pMem return pMemory->__hwresIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline NV_STATUS hwresUnmapFrom_DISPATCH(struct MemoryHwResources *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__hwresUnmapFrom__(pResource, pParams); -} - -static inline void hwresControl_Epilogue_DISPATCH(struct MemoryHwResources *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__hwresControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS hwresControlLookup_DISPATCH(struct MemoryHwResources *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__hwresControlLookup__(pResource, pParams, ppEntry); +static inline void hwresControlSerialization_Epilogue_DISPATCH(struct MemoryHwResources *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__hwresControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS hwresMap_DISPATCH(struct MemoryHwResources *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_hypervisor_nvoc.c b/src/nvidia/generated/g_hypervisor_nvoc.c index e33606906..fe6c775d7 100644 --- a/src/nvidia/generated/g_hypervisor_nvoc.c +++ b/src/nvidia/generated/g_hypervisor_nvoc.c @@ -114,13 +114,16 @@ NV_STATUS __nvoc_objCreate_OBJHYPERVISOR(OBJHYPERVISOR **ppThis, Dynamic *pParen Object *pParentObj; OBJHYPERVISOR *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJHYPERVISOR)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJHYPERVISOR), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJHYPERVISOR)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJHYPERVISOR); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -136,11 +139,17 @@ NV_STATUS __nvoc_objCreate_OBJHYPERVISOR(OBJHYPERVISOR **ppThis, Dynamic *pParen if (status != NV_OK) goto __nvoc_objCreate_OBJHYPERVISOR_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJHYPERVISOR_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJHYPERVISOR)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_hypervisor_nvoc.h b/src/nvidia/generated/g_hypervisor_nvoc.h index 7126164b5..1ae0b4b69 100644 --- a/src/nvidia/generated/g_hypervisor_nvoc.h +++ b/src/nvidia/generated/g_hypervisor_nvoc.h @@ -153,163 +153,6 @@ static inline void hypervisorSetHypervVgpuSupported(struct OBJHYPERVISOR *arg0) #define hypervisorSetHypervVgpuSupported_HAL(arg0) hypervisorSetHypervVgpuSupported(arg0) -static inline NV_STATUS hypervisorSetupGuestVmBusChannel_56cd7a(struct OBJHYPERVISOR *arg0, struct OBJGPU *arg1) { - return NV_OK; -} - - -#ifdef __nvoc_hypervisor_h_disabled -static inline NV_STATUS hypervisorSetupGuestVmBusChannel(struct OBJHYPERVISOR *arg0, struct OBJGPU *arg1) { - NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_hypervisor_h_disabled -#define hypervisorSetupGuestVmBusChannel(arg0, arg1) hypervisorSetupGuestVmBusChannel_56cd7a(arg0, arg1) -#endif //__nvoc_hypervisor_h_disabled - -#define hypervisorSetupGuestVmBusChannel_HAL(arg0, arg1) hypervisorSetupGuestVmBusChannel(arg0, arg1) - -static inline void hypervisorDestroyGuestVmBusChannel_b3696a(struct OBJHYPERVISOR *arg0) { - return; -} - - -#ifdef __nvoc_hypervisor_h_disabled -static inline void hypervisorDestroyGuestVmBusChannel(struct OBJHYPERVISOR *arg0) { - NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); -} -#else //__nvoc_hypervisor_h_disabled -#define hypervisorDestroyGuestVmBusChannel(arg0) hypervisorDestroyGuestVmBusChannel_b3696a(arg0) -#endif //__nvoc_hypervisor_h_disabled - -#define hypervisorDestroyGuestVmBusChannel_HAL(arg0) hypervisorDestroyGuestVmBusChannel(arg0) - -static inline NV_STATUS hypervisorSetupHostVmBusChannel_56cd7a(struct OBJHYPERVISOR *arg0, NvU64 arg1, struct OBJGPU *arg2, HOST_VGPU_DEVICE *arg3) { - return NV_OK; -} - - -#ifdef __nvoc_hypervisor_h_disabled -static inline NV_STATUS hypervisorSetupHostVmBusChannel(struct OBJHYPERVISOR *arg0, NvU64 arg1, struct OBJGPU *arg2, HOST_VGPU_DEVICE *arg3) { - NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_hypervisor_h_disabled -#define hypervisorSetupHostVmBusChannel(arg0, arg1, arg2, arg3) hypervisorSetupHostVmBusChannel_56cd7a(arg0, arg1, arg2, arg3) -#endif //__nvoc_hypervisor_h_disabled - -#define hypervisorSetupHostVmBusChannel_HAL(arg0, arg1, arg2, arg3) hypervisorSetupHostVmBusChannel(arg0, arg1, arg2, arg3) - -static inline void hypervisorResetHostVmBusChannel_b3696a(struct OBJHYPERVISOR *arg0, HOST_VGPU_DEVICE *arg1) { - return; -} - - -#ifdef __nvoc_hypervisor_h_disabled -static inline void hypervisorResetHostVmBusChannel(struct OBJHYPERVISOR *arg0, HOST_VGPU_DEVICE *arg1) { - NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); -} -#else //__nvoc_hypervisor_h_disabled -#define hypervisorResetHostVmBusChannel(arg0, arg1) hypervisorResetHostVmBusChannel_b3696a(arg0, arg1) -#endif //__nvoc_hypervisor_h_disabled - -#define hypervisorResetHostVmBusChannel_HAL(arg0, arg1) hypervisorResetHostVmBusChannel(arg0, arg1) - -static inline NV_STATUS hypervisorGuestPinPages_56cd7a(struct OBJHYPERVISOR *arg0, MEMORY_DESCRIPTOR *arg1) { - return NV_OK; -} - - -#ifdef __nvoc_hypervisor_h_disabled -static inline NV_STATUS hypervisorGuestPinPages(struct OBJHYPERVISOR *arg0, MEMORY_DESCRIPTOR *arg1) { - NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_hypervisor_h_disabled -#define hypervisorGuestPinPages(arg0, arg1) hypervisorGuestPinPages_56cd7a(arg0, arg1) -#endif //__nvoc_hypervisor_h_disabled - -#define hypervisorGuestPinPages_HAL(arg0, arg1) hypervisorGuestPinPages(arg0, arg1) - -static inline NV_STATUS hypervisorGuestPinPagesUsingPfns_56cd7a(struct OBJHYPERVISOR *arg0, NvU32 arg1, NvU64 *arg2) { - return NV_OK; -} - - -#ifdef __nvoc_hypervisor_h_disabled -static inline NV_STATUS hypervisorGuestPinPagesUsingPfns(struct OBJHYPERVISOR *arg0, NvU32 arg1, NvU64 *arg2) { - NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_hypervisor_h_disabled -#define hypervisorGuestPinPagesUsingPfns(arg0, arg1, arg2) hypervisorGuestPinPagesUsingPfns_56cd7a(arg0, arg1, arg2) -#endif //__nvoc_hypervisor_h_disabled - -#define hypervisorGuestPinPagesUsingPfns_HAL(arg0, arg1, arg2) hypervisorGuestPinPagesUsingPfns(arg0, arg1, arg2) - -static inline NV_STATUS hypervisorSendEventToGuest_56cd7a(struct OBJHYPERVISOR *arg0, void *arg1) { - return NV_OK; -} - - -#ifdef __nvoc_hypervisor_h_disabled -static inline NV_STATUS hypervisorSendEventToGuest(struct OBJHYPERVISOR *arg0, void *arg1) { - NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_hypervisor_h_disabled -#define hypervisorSendEventToGuest(arg0, arg1) hypervisorSendEventToGuest_56cd7a(arg0, arg1) -#endif //__nvoc_hypervisor_h_disabled - -#define hypervisorSendEventToGuest_HAL(arg0, arg1) hypervisorSendEventToGuest(arg0, arg1) - -static inline NV_STATUS hypervisorAllocHostVmbusChannel_56cd7a(struct OBJHYPERVISOR *arg0, HOST_VGPU_DEVICE *arg1) { - return NV_OK; -} - - -#ifdef __nvoc_hypervisor_h_disabled -static inline NV_STATUS hypervisorAllocHostVmbusChannel(struct OBJHYPERVISOR *arg0, HOST_VGPU_DEVICE *arg1) { - NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_hypervisor_h_disabled -#define hypervisorAllocHostVmbusChannel(arg0, arg1) hypervisorAllocHostVmbusChannel_56cd7a(arg0, arg1) -#endif //__nvoc_hypervisor_h_disabled - -#define hypervisorAllocHostVmbusChannel_HAL(arg0, arg1) hypervisorAllocHostVmbusChannel(arg0, arg1) - -static inline void hypervisorFreeHostVmbusChannel_b3696a(struct OBJHYPERVISOR *arg0, HOST_VGPU_DEVICE *arg1) { - return; -} - - -#ifdef __nvoc_hypervisor_h_disabled -static inline void hypervisorFreeHostVmbusChannel(struct OBJHYPERVISOR *arg0, HOST_VGPU_DEVICE *arg1) { - NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); -} -#else //__nvoc_hypervisor_h_disabled -#define hypervisorFreeHostVmbusChannel(arg0, arg1) hypervisorFreeHostVmbusChannel_b3696a(arg0, arg1) -#endif //__nvoc_hypervisor_h_disabled - -#define hypervisorFreeHostVmbusChannel_HAL(arg0, arg1) hypervisorFreeHostVmbusChannel(arg0, arg1) - -static inline NV_STATUS hypervisorVmbusHostCompletePacket_56cd7a(struct OBJHYPERVISOR *arg0, NvU64 arg1, HOST_VGPU_DEVICE *arg2) { - return NV_OK; -} - - -#ifdef __nvoc_hypervisor_h_disabled -static inline NV_STATUS hypervisorVmbusHostCompletePacket(struct OBJHYPERVISOR *arg0, NvU64 arg1, HOST_VGPU_DEVICE *arg2) { - NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_hypervisor_h_disabled -#define hypervisorVmbusHostCompletePacket(arg0, arg1, arg2) hypervisorVmbusHostCompletePacket_56cd7a(arg0, arg1, arg2) -#endif //__nvoc_hypervisor_h_disabled - -#define hypervisorVmbusHostCompletePacket_HAL(arg0, arg1, arg2) hypervisorVmbusHostCompletePacket(arg0, arg1, arg2) - NvBool hypervisorCheckForObjectAccess_IMPL(NvHandle hClient); #define hypervisorCheckForObjectAccess(hClient) hypervisorCheckForObjectAccess_IMPL(hClient) diff --git a/src/nvidia/generated/g_i2c_api_nvoc.c b/src/nvidia/generated/g_i2c_api_nvoc.c index 3cfff37ad..f91095630 100644 --- a/src/nvidia/generated/g_i2c_api_nvoc.c +++ b/src/nvidia/generated/g_i2c_api_nvoc.c @@ -97,6 +97,54 @@ static NvBool __nvoc_thunk_GpuResource_i2capiShareCallback(struct I2cApi *pGpuRe return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_I2cApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } +static NV_STATUS __nvoc_thunk_RmResource_i2capiCheckMemInterUnmap(struct I2cApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_I2cApi_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_i2capiMapTo(struct I2cApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_i2capiGetMapAddrSpace(struct I2cApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_I2cApi_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_i2capiGetRefCount(struct I2cApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_i2capiAddAdditionalDependants(struct RsClient *pClient, struct I2cApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_i2capiControl_Prologue(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_i2capiGetRegBaseOffsetAndSize(struct I2cApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_I2cApi_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_i2capiInternalControlForward(struct I2cApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_I2cApi_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_i2capiUnmapFrom(struct I2cApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_i2capiControl_Epilogue(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_i2capiControlLookup(struct I2cApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset), pParams, ppEntry); +} + +static NvHandle __nvoc_thunk_GpuResource_i2capiGetInternalObjectHandle(struct I2cApi *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_I2cApi_GpuResource.offset)); +} + static NV_STATUS __nvoc_thunk_GpuResource_i2capiControl(struct I2cApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_I2cApi_GpuResource.offset), pCallContext, pParams); } @@ -113,68 +161,28 @@ static NV_STATUS __nvoc_thunk_RmResource_i2capiGetMemoryMappingDescriptor(struct return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_I2cApi_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_GpuResource_i2capiGetMapAddrSpace(struct I2cApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_I2cApi_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvHandle __nvoc_thunk_GpuResource_i2capiGetInternalObjectHandle(struct I2cApi *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_I2cApi_GpuResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_i2capiControlFilter(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_i2capiAddAdditionalDependants(struct RsClient *pClient, struct I2cApi *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_i2capiGetRefCount(struct I2cApi *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RmResource_i2capiCheckMemInterUnmap(struct I2cApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_I2cApi_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_i2capiMapTo(struct I2cApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_i2capiControl_Prologue(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_GpuResource_i2capiGetRegBaseOffsetAndSize(struct I2cApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_I2cApi_GpuResource.offset), pGpu, pOffset, pSize); +static NV_STATUS __nvoc_thunk_RmResource_i2capiControlSerialization_Prologue(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_i2capiCanCopy(struct I2cApi *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_i2capiInternalControlForward(struct I2cApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_I2cApi_GpuResource.offset), command, pParams, size); -} - static void __nvoc_thunk_RsResource_i2capiPreDestruct(struct I2cApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_i2capiUnmapFrom(struct I2cApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_i2capiIsDuplicate(struct I2cApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset), hMemory, pDuplicate); } -static void __nvoc_thunk_RmResource_i2capiControl_Epilogue(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_i2capiControlLookup(struct I2cApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_i2capiControlSerialization_Epilogue(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_i2capiMap(struct I2cApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -330,6 +338,30 @@ static void __nvoc_init_funcTable_I2cApi_1(I2cApi *pThis) { pThis->__i2capiShareCallback__ = &__nvoc_thunk_GpuResource_i2capiShareCallback; + pThis->__i2capiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_i2capiCheckMemInterUnmap; + + pThis->__i2capiMapTo__ = &__nvoc_thunk_RsResource_i2capiMapTo; + + pThis->__i2capiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_i2capiGetMapAddrSpace; + + pThis->__i2capiGetRefCount__ = &__nvoc_thunk_RsResource_i2capiGetRefCount; + + pThis->__i2capiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_i2capiAddAdditionalDependants; + + pThis->__i2capiControl_Prologue__ = &__nvoc_thunk_RmResource_i2capiControl_Prologue; + + pThis->__i2capiGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_i2capiGetRegBaseOffsetAndSize; + + pThis->__i2capiInternalControlForward__ = &__nvoc_thunk_GpuResource_i2capiInternalControlForward; + + pThis->__i2capiUnmapFrom__ = &__nvoc_thunk_RsResource_i2capiUnmapFrom; + + pThis->__i2capiControl_Epilogue__ = &__nvoc_thunk_RmResource_i2capiControl_Epilogue; + + pThis->__i2capiControlLookup__ = &__nvoc_thunk_RsResource_i2capiControlLookup; + + pThis->__i2capiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_i2capiGetInternalObjectHandle; + pThis->__i2capiControl__ = &__nvoc_thunk_GpuResource_i2capiControl; pThis->__i2capiUnmap__ = &__nvoc_thunk_GpuResource_i2capiUnmap; @@ -338,37 +370,17 @@ static void __nvoc_init_funcTable_I2cApi_1(I2cApi *pThis) { pThis->__i2capiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_i2capiGetMemoryMappingDescriptor; - pThis->__i2capiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_i2capiGetMapAddrSpace; - - pThis->__i2capiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_i2capiGetInternalObjectHandle; - pThis->__i2capiControlFilter__ = &__nvoc_thunk_RsResource_i2capiControlFilter; - pThis->__i2capiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_i2capiAddAdditionalDependants; - - pThis->__i2capiGetRefCount__ = &__nvoc_thunk_RsResource_i2capiGetRefCount; - - pThis->__i2capiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_i2capiCheckMemInterUnmap; - - pThis->__i2capiMapTo__ = &__nvoc_thunk_RsResource_i2capiMapTo; - - pThis->__i2capiControl_Prologue__ = &__nvoc_thunk_RmResource_i2capiControl_Prologue; - - pThis->__i2capiGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_i2capiGetRegBaseOffsetAndSize; + pThis->__i2capiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_i2capiControlSerialization_Prologue; pThis->__i2capiCanCopy__ = &__nvoc_thunk_RsResource_i2capiCanCopy; - pThis->__i2capiInternalControlForward__ = &__nvoc_thunk_GpuResource_i2capiInternalControlForward; - pThis->__i2capiPreDestruct__ = &__nvoc_thunk_RsResource_i2capiPreDestruct; - pThis->__i2capiUnmapFrom__ = &__nvoc_thunk_RsResource_i2capiUnmapFrom; - pThis->__i2capiIsDuplicate__ = &__nvoc_thunk_RsResource_i2capiIsDuplicate; - pThis->__i2capiControl_Epilogue__ = &__nvoc_thunk_RmResource_i2capiControl_Epilogue; - - pThis->__i2capiControlLookup__ = &__nvoc_thunk_RsResource_i2capiControlLookup; + pThis->__i2capiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_i2capiControlSerialization_Epilogue; pThis->__i2capiMap__ = &__nvoc_thunk_GpuResource_i2capiMap; @@ -396,13 +408,16 @@ NV_STATUS __nvoc_objCreate_I2cApi(I2cApi **ppThis, Dynamic *pParent, NvU32 creat Object *pParentObj; I2cApi *pThis; - pThis = portMemAllocNonPaged(sizeof(I2cApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(I2cApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(I2cApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_I2cApi); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -418,11 +433,17 @@ NV_STATUS __nvoc_objCreate_I2cApi(I2cApi **ppThis, Dynamic *pParent, NvU32 creat if (status != NV_OK) goto __nvoc_objCreate_I2cApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_I2cApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(I2cApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_i2c_api_nvoc.h b/src/nvidia/generated/g_i2c_api_nvoc.h index dd0afaaa6..9ee62c762 100644 --- a/src/nvidia/generated/g_i2c_api_nvoc.h +++ b/src/nvidia/generated/g_i2c_api_nvoc.h @@ -61,26 +61,28 @@ struct I2cApi { NV_STATUS (*__i2capiCtrlCmdI2cTableGetDevInfo__)(struct I2cApi *, NV402C_CTRL_I2C_TABLE_GET_DEV_INFO_PARAMS *); NV_STATUS (*__i2capiCtrlCmdI2cTransaction__)(struct I2cApi *, NV402C_CTRL_I2C_TRANSACTION_PARAMS *); NvBool (*__i2capiShareCallback__)(struct I2cApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__i2capiCheckMemInterUnmap__)(struct I2cApi *, NvBool); + NV_STATUS (*__i2capiMapTo__)(struct I2cApi *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__i2capiGetMapAddrSpace__)(struct I2cApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__i2capiGetRefCount__)(struct I2cApi *); + void (*__i2capiAddAdditionalDependants__)(struct RsClient *, struct I2cApi *, RsResourceRef *); + NV_STATUS (*__i2capiControl_Prologue__)(struct I2cApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__i2capiGetRegBaseOffsetAndSize__)(struct I2cApi *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__i2capiInternalControlForward__)(struct I2cApi *, NvU32, void *, NvU32); + NV_STATUS (*__i2capiUnmapFrom__)(struct I2cApi *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__i2capiControl_Epilogue__)(struct I2cApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__i2capiControlLookup__)(struct I2cApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__i2capiGetInternalObjectHandle__)(struct I2cApi *); NV_STATUS (*__i2capiControl__)(struct I2cApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__i2capiUnmap__)(struct I2cApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__i2capiGetMemInterMapParams__)(struct I2cApi *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__i2capiGetMemoryMappingDescriptor__)(struct I2cApi *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__i2capiGetMapAddrSpace__)(struct I2cApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__i2capiGetInternalObjectHandle__)(struct I2cApi *); NV_STATUS (*__i2capiControlFilter__)(struct I2cApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__i2capiAddAdditionalDependants__)(struct RsClient *, struct I2cApi *, RsResourceRef *); - NvU32 (*__i2capiGetRefCount__)(struct I2cApi *); - NV_STATUS (*__i2capiCheckMemInterUnmap__)(struct I2cApi *, NvBool); - NV_STATUS (*__i2capiMapTo__)(struct I2cApi *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__i2capiControl_Prologue__)(struct I2cApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__i2capiGetRegBaseOffsetAndSize__)(struct I2cApi *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__i2capiControlSerialization_Prologue__)(struct I2cApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__i2capiCanCopy__)(struct I2cApi *); - NV_STATUS (*__i2capiInternalControlForward__)(struct I2cApi *, NvU32, void *, NvU32); void (*__i2capiPreDestruct__)(struct I2cApi *); - NV_STATUS (*__i2capiUnmapFrom__)(struct I2cApi *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__i2capiIsDuplicate__)(struct I2cApi *, NvHandle, NvBool *); - void (*__i2capiControl_Epilogue__)(struct I2cApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__i2capiControlLookup__)(struct I2cApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__i2capiControlSerialization_Epilogue__)(struct I2cApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__i2capiMap__)(struct I2cApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__i2capiAccessCallback__)(struct I2cApi *, struct RsClient *, void *, RsAccessRight); }; @@ -119,26 +121,28 @@ NV_STATUS __nvoc_objCreate_I2cApi(I2cApi**, Dynamic*, NvU32, struct CALL_CONTEXT #define i2capiCtrlCmdI2cTableGetDevInfo(pI2cApi, pParams) i2capiCtrlCmdI2cTableGetDevInfo_DISPATCH(pI2cApi, pParams) #define i2capiCtrlCmdI2cTransaction(pI2cApi, pParams) i2capiCtrlCmdI2cTransaction_DISPATCH(pI2cApi, pParams) #define i2capiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) i2capiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define i2capiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) i2capiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define i2capiMapTo(pResource, pParams) i2capiMapTo_DISPATCH(pResource, pParams) +#define i2capiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) i2capiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define i2capiGetRefCount(pResource) i2capiGetRefCount_DISPATCH(pResource) +#define i2capiAddAdditionalDependants(pClient, pResource, pReference) i2capiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define i2capiControl_Prologue(pResource, pCallContext, pParams) i2capiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define i2capiGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) i2capiGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define i2capiInternalControlForward(pGpuResource, command, pParams, size) i2capiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define i2capiUnmapFrom(pResource, pParams) i2capiUnmapFrom_DISPATCH(pResource, pParams) +#define i2capiControl_Epilogue(pResource, pCallContext, pParams) i2capiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define i2capiControlLookup(pResource, pParams, ppEntry) i2capiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define i2capiGetInternalObjectHandle(pGpuResource) i2capiGetInternalObjectHandle_DISPATCH(pGpuResource) #define i2capiControl(pGpuResource, pCallContext, pParams) i2capiControl_DISPATCH(pGpuResource, pCallContext, pParams) #define i2capiUnmap(pGpuResource, pCallContext, pCpuMapping) i2capiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define i2capiGetMemInterMapParams(pRmResource, pParams) i2capiGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define i2capiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) i2capiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define i2capiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) i2capiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define i2capiGetInternalObjectHandle(pGpuResource) i2capiGetInternalObjectHandle_DISPATCH(pGpuResource) #define i2capiControlFilter(pResource, pCallContext, pParams) i2capiControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define i2capiAddAdditionalDependants(pClient, pResource, pReference) i2capiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define i2capiGetRefCount(pResource) i2capiGetRefCount_DISPATCH(pResource) -#define i2capiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) i2capiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define i2capiMapTo(pResource, pParams) i2capiMapTo_DISPATCH(pResource, pParams) -#define i2capiControl_Prologue(pResource, pCallContext, pParams) i2capiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define i2capiGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) i2capiGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define i2capiControlSerialization_Prologue(pResource, pCallContext, pParams) i2capiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define i2capiCanCopy(pResource) i2capiCanCopy_DISPATCH(pResource) -#define i2capiInternalControlForward(pGpuResource, command, pParams, size) i2capiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define i2capiPreDestruct(pResource) i2capiPreDestruct_DISPATCH(pResource) -#define i2capiUnmapFrom(pResource, pParams) i2capiUnmapFrom_DISPATCH(pResource, pParams) #define i2capiIsDuplicate(pResource, hMemory, pDuplicate) i2capiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) -#define i2capiControl_Epilogue(pResource, pCallContext, pParams) i2capiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define i2capiControlLookup(pResource, pParams, ppEntry) i2capiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define i2capiControlSerialization_Epilogue(pResource, pCallContext, pParams) i2capiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define i2capiMap(pGpuResource, pCallContext, pParams, pCpuMapping) i2capiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define i2capiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) i2capiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS i2capiCtrlCmdI2cGetPortInfo_IMPL(struct I2cApi *pI2cApi, NV402C_CTRL_I2C_GET_PORT_INFO_PARAMS *pParams); @@ -175,6 +179,54 @@ static inline NvBool i2capiShareCallback_DISPATCH(struct I2cApi *pGpuResource, s return pGpuResource->__i2capiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } +static inline NV_STATUS i2capiCheckMemInterUnmap_DISPATCH(struct I2cApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__i2capiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS i2capiMapTo_DISPATCH(struct I2cApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__i2capiMapTo__(pResource, pParams); +} + +static inline NV_STATUS i2capiGetMapAddrSpace_DISPATCH(struct I2cApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__i2capiGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 i2capiGetRefCount_DISPATCH(struct I2cApi *pResource) { + return pResource->__i2capiGetRefCount__(pResource); +} + +static inline void i2capiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct I2cApi *pResource, RsResourceRef *pReference) { + pResource->__i2capiAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS i2capiControl_Prologue_DISPATCH(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__i2capiControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS i2capiGetRegBaseOffsetAndSize_DISPATCH(struct I2cApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__i2capiGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS i2capiInternalControlForward_DISPATCH(struct I2cApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__i2capiInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS i2capiUnmapFrom_DISPATCH(struct I2cApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__i2capiUnmapFrom__(pResource, pParams); +} + +static inline void i2capiControl_Epilogue_DISPATCH(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__i2capiControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS i2capiControlLookup_DISPATCH(struct I2cApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__i2capiControlLookup__(pResource, pParams, ppEntry); +} + +static inline NvHandle i2capiGetInternalObjectHandle_DISPATCH(struct I2cApi *pGpuResource) { + return pGpuResource->__i2capiGetInternalObjectHandle__(pGpuResource); +} + static inline NV_STATUS i2capiControl_DISPATCH(struct I2cApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pGpuResource->__i2capiControl__(pGpuResource, pCallContext, pParams); } @@ -191,68 +243,28 @@ static inline NV_STATUS i2capiGetMemoryMappingDescriptor_DISPATCH(struct I2cApi return pRmResource->__i2capiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS i2capiGetMapAddrSpace_DISPATCH(struct I2cApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__i2capiGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvHandle i2capiGetInternalObjectHandle_DISPATCH(struct I2cApi *pGpuResource) { - return pGpuResource->__i2capiGetInternalObjectHandle__(pGpuResource); -} - static inline NV_STATUS i2capiControlFilter_DISPATCH(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__i2capiControlFilter__(pResource, pCallContext, pParams); } -static inline void i2capiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct I2cApi *pResource, RsResourceRef *pReference) { - pResource->__i2capiAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 i2capiGetRefCount_DISPATCH(struct I2cApi *pResource) { - return pResource->__i2capiGetRefCount__(pResource); -} - -static inline NV_STATUS i2capiCheckMemInterUnmap_DISPATCH(struct I2cApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__i2capiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS i2capiMapTo_DISPATCH(struct I2cApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__i2capiMapTo__(pResource, pParams); -} - -static inline NV_STATUS i2capiControl_Prologue_DISPATCH(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__i2capiControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS i2capiGetRegBaseOffsetAndSize_DISPATCH(struct I2cApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__i2capiGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +static inline NV_STATUS i2capiControlSerialization_Prologue_DISPATCH(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__i2capiControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool i2capiCanCopy_DISPATCH(struct I2cApi *pResource) { return pResource->__i2capiCanCopy__(pResource); } -static inline NV_STATUS i2capiInternalControlForward_DISPATCH(struct I2cApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__i2capiInternalControlForward__(pGpuResource, command, pParams, size); -} - static inline void i2capiPreDestruct_DISPATCH(struct I2cApi *pResource) { pResource->__i2capiPreDestruct__(pResource); } -static inline NV_STATUS i2capiUnmapFrom_DISPATCH(struct I2cApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__i2capiUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS i2capiIsDuplicate_DISPATCH(struct I2cApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__i2capiIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline void i2capiControl_Epilogue_DISPATCH(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__i2capiControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS i2capiControlLookup_DISPATCH(struct I2cApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__i2capiControlLookup__(pResource, pParams, ppEntry); +static inline void i2capiControlSerialization_Epilogue_DISPATCH(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__i2capiControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS i2capiMap_DISPATCH(struct I2cApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_intr_nvoc.c b/src/nvidia/generated/g_intr_nvoc.c index 12a4aa245..f9d2d96c3 100644 --- a/src/nvidia/generated/g_intr_nvoc.c +++ b/src/nvidia/generated/g_intr_nvoc.c @@ -90,10 +90,6 @@ static NV_STATUS __nvoc_thunk_Intr_engstateStateUnload(OBJGPU *pGpu, struct OBJE return intrStateUnload(pGpu, (struct Intr *)(((unsigned char *)pIntr) - __nvoc_rtti_Intr_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_intrReconcileTunableState(POBJGPU pGpu, struct Intr *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_intrStatePreLoad(POBJGPU pGpu, struct Intr *pEngstate, NvU32 arg0) { return engstateStatePreLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset), arg0); } @@ -118,30 +114,10 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_intrStatePreInitUnlocked(POBJGPU pGpu, return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_intrGetTunableState(POBJGPU pGpu, struct Intr *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_intrCompareTunableState(POBJGPU pGpu, struct Intr *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_intrFreeTunableState(POBJGPU pGpu, struct Intr *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_intrStatePostLoad(POBJGPU pGpu, struct Intr *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_intrAllocTunableState(POBJGPU pGpu, struct Intr *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_intrSetTunableState(POBJGPU pGpu, struct Intr *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_intrIsPresent(POBJGPU pGpu, struct Intr *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_Intr_OBJENGSTATE.offset)); } @@ -329,16 +305,6 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec pThis->__intrWriteRegTopEnClear__ = &intrWriteRegTopEnClear_GA102; } - // Hal function -- intrGetStallSubtreeLast - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__intrGetStallSubtreeLast__ = &intrGetStallSubtreeLast_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__intrGetStallSubtreeLast__ = &intrGetStallSubtreeLast_GH100; - } - // Hal function -- intrGetNumLeaves if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { @@ -453,8 +419,6 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec pThis->__nvoc_base_OBJENGSTATE.__engstateStateUnload__ = &__nvoc_thunk_Intr_engstateStateUnload; - pThis->__intrReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_intrReconcileTunableState; - pThis->__intrStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_intrStatePreLoad; pThis->__intrStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_intrStatePostUnload; @@ -467,18 +431,8 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec pThis->__intrStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_intrStatePreInitUnlocked; - pThis->__intrGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_intrGetTunableState; - - pThis->__intrCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_intrCompareTunableState; - - pThis->__intrFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_intrFreeTunableState; - pThis->__intrStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_intrStatePostLoad; - pThis->__intrAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_intrAllocTunableState; - - pThis->__intrSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_intrSetTunableState; - pThis->__intrIsPresent__ = &__nvoc_thunk_OBJENGSTATE_intrIsPresent; } @@ -501,13 +455,16 @@ NV_STATUS __nvoc_objCreate_Intr(Intr **ppThis, Dynamic *pParent, NvU32 createFla Intr *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(Intr)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Intr), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(Intr)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Intr); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -527,11 +484,17 @@ NV_STATUS __nvoc_objCreate_Intr(Intr **ppThis, Dynamic *pParent, NvU32 createFla if (status != NV_OK) goto __nvoc_objCreate_Intr_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_Intr_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(Intr)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_intr_nvoc.h b/src/nvidia/generated/g_intr_nvoc.h index 7c42efb24..0cd572180 100644 --- a/src/nvidia/generated/g_intr_nvoc.h +++ b/src/nvidia/generated/g_intr_nvoc.h @@ -41,6 +41,7 @@ extern "C" { #include "dev_ctrl_defines.h" #include "kernel/gpu/intr/engine_idx.h" #include "kernel/gpu/intr/intr_service.h" +#include "ctrl/ctrl2080/ctrl2080internal.h" // // Interrupt Type @@ -93,7 +94,6 @@ typedef struct // The max number of interrupts we can fit in the dynamically populated, // but statically sized, interrupt table. // -#define INTR_TABLE_MAX_STATIC_PHYSICAL_INTRS 19 #define INTR_TABLE_MAX_STATIC_KERNEL_INTRS 17 #define POPULATE_INTR_TABLE(pTable, numEntries, localMcEngineIdxs, localIntrVectors, localCount, localMax) \ @@ -183,6 +183,7 @@ typedef struct MC_ENGINE_BITVECTOR intrMask; } INTR_MASK_CTX; + // // IntrMask Locking Flag Defines // @@ -210,10 +211,9 @@ struct Intr { NvU32 (*__intrReadRegTopEnSet__)(OBJGPU *, struct Intr *, NvU32, struct THREAD_STATE_NODE *); void (*__intrWriteRegTopEnSet__)(OBJGPU *, struct Intr *, NvU32, NvU32, struct THREAD_STATE_NODE *); void (*__intrWriteRegTopEnClear__)(OBJGPU *, struct Intr *, NvU32, NvU32, struct THREAD_STATE_NODE *); - NvU32 (*__intrGetStallSubtreeLast__)(OBJGPU *, struct Intr *); NvU32 (*__intrGetNumLeaves__)(OBJGPU *, struct Intr *); NvU32 (*__intrGetLeafSize__)(OBJGPU *, struct Intr *); - NvU32 (*__intrGetIntrTopNonStallMask__)(OBJGPU *, struct Intr *); + NvU64 (*__intrGetIntrTopNonStallMask__)(OBJGPU *, struct Intr *); void (*__intrSanityCheckEngineIntrStallVector__)(OBJGPU *, struct Intr *, NvU32, NvU16); void (*__intrSanityCheckEngineIntrNotificationVector__)(OBJGPU *, struct Intr *, NvU32, NvU16); NV_STATUS (*__intrStateLoad__)(OBJGPU *, struct Intr *, NvU32); @@ -221,19 +221,13 @@ struct Intr { NV_STATUS (*__intrSetIntrMask__)(OBJGPU *, struct Intr *, union MC_ENGINE_BITVECTOR *, struct THREAD_STATE_NODE *); void (*__intrSetIntrEnInHw__)(OBJGPU *, struct Intr *, NvU32, struct THREAD_STATE_NODE *); NvU32 (*__intrGetIntrEnFromHw__)(OBJGPU *, struct Intr *, struct THREAD_STATE_NODE *); - NV_STATUS (*__intrReconcileTunableState__)(POBJGPU, struct Intr *, void *); NV_STATUS (*__intrStatePreLoad__)(POBJGPU, struct Intr *, NvU32); NV_STATUS (*__intrStatePostUnload__)(POBJGPU, struct Intr *, NvU32); NV_STATUS (*__intrStatePreUnload__)(POBJGPU, struct Intr *, NvU32); void (*__intrInitMissing__)(POBJGPU, struct Intr *); NV_STATUS (*__intrStatePreInitLocked__)(POBJGPU, struct Intr *); NV_STATUS (*__intrStatePreInitUnlocked__)(POBJGPU, struct Intr *); - NV_STATUS (*__intrGetTunableState__)(POBJGPU, struct Intr *, void *); - NV_STATUS (*__intrCompareTunableState__)(POBJGPU, struct Intr *, void *, void *); - void (*__intrFreeTunableState__)(POBJGPU, struct Intr *, void *); NV_STATUS (*__intrStatePostLoad__)(POBJGPU, struct Intr *, NvU32); - NV_STATUS (*__intrAllocTunableState__)(POBJGPU, struct Intr *, void **); - NV_STATUS (*__intrSetTunableState__)(POBJGPU, struct Intr *, void *); NvBool (*__intrIsPresent__)(POBJGPU, struct Intr *); NvBool PDB_PROP_INTR_ENABLE_DETAILED_LOGS; NvBool PDB_PROP_INTR_HOST_DRIVEN_ENGINES_REMOVED_FROM_PMC; @@ -249,12 +243,12 @@ struct Intr { NvU32 replayableFaultIntrVector; NvU32 accessCntrIntrVector; NvU32 displayIntrVector; - NvU32 intrTopEnMask; - IntrServiceRecord intrServiceTable[163]; + NvU64 intrTopEnMask; + IntrServiceRecord intrServiceTable[166]; NvBool bDefaultNonstallNotify; NvU32 intrTableSz; INTR_TABLE_ENTRY *pIntrTable; - INTR_TABLE_ENTRY pStaticPhysicalTable[19]; + NV2080_INTR_CATEGORY_SUBTREE_MAP subtreeMap[7]; INTR_TABLE_ENTRY pStaticKernelTable[17]; NvBool bDpcStarted; union MC_ENGINE_BITVECTOR pmcIntrPending; @@ -338,8 +332,6 @@ NV_STATUS __nvoc_objCreate_Intr(Intr**, Dynamic*, NvU32); #define intrWriteRegTopEnSet_HAL(pGpu, pIntr, arg0, arg1, arg2) intrWriteRegTopEnSet_DISPATCH(pGpu, pIntr, arg0, arg1, arg2) #define intrWriteRegTopEnClear(pGpu, pIntr, arg0, arg1, arg2) intrWriteRegTopEnClear_DISPATCH(pGpu, pIntr, arg0, arg1, arg2) #define intrWriteRegTopEnClear_HAL(pGpu, pIntr, arg0, arg1, arg2) intrWriteRegTopEnClear_DISPATCH(pGpu, pIntr, arg0, arg1, arg2) -#define intrGetStallSubtreeLast(pGpu, pIntr) intrGetStallSubtreeLast_DISPATCH(pGpu, pIntr) -#define intrGetStallSubtreeLast_HAL(pGpu, pIntr) intrGetStallSubtreeLast_DISPATCH(pGpu, pIntr) #define intrGetNumLeaves(pGpu, pIntr) intrGetNumLeaves_DISPATCH(pGpu, pIntr) #define intrGetNumLeaves_HAL(pGpu, pIntr) intrGetNumLeaves_DISPATCH(pGpu, pIntr) #define intrGetLeafSize(pGpu, pIntr) intrGetLeafSize_DISPATCH(pGpu, pIntr) @@ -360,19 +352,13 @@ NV_STATUS __nvoc_objCreate_Intr(Intr**, Dynamic*, NvU32); #define intrSetIntrEnInHw_HAL(pGpu, pIntr, arg0, arg1) intrSetIntrEnInHw_DISPATCH(pGpu, pIntr, arg0, arg1) #define intrGetIntrEnFromHw(pGpu, pIntr, arg0) intrGetIntrEnFromHw_DISPATCH(pGpu, pIntr, arg0) #define intrGetIntrEnFromHw_HAL(pGpu, pIntr, arg0) intrGetIntrEnFromHw_DISPATCH(pGpu, pIntr, arg0) -#define intrReconcileTunableState(pGpu, pEngstate, pTunableState) intrReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define intrStatePreLoad(pGpu, pEngstate, arg0) intrStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define intrStatePostUnload(pGpu, pEngstate, arg0) intrStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) #define intrStatePreUnload(pGpu, pEngstate, arg0) intrStatePreUnload_DISPATCH(pGpu, pEngstate, arg0) #define intrInitMissing(pGpu, pEngstate) intrInitMissing_DISPATCH(pGpu, pEngstate) #define intrStatePreInitLocked(pGpu, pEngstate) intrStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define intrStatePreInitUnlocked(pGpu, pEngstate) intrStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define intrGetTunableState(pGpu, pEngstate, pTunableState) intrGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define intrCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) intrCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define intrFreeTunableState(pGpu, pEngstate, pTunableState) intrFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define intrStatePostLoad(pGpu, pEngstate, arg0) intrStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define intrAllocTunableState(pGpu, pEngstate, ppTunableState) intrAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define intrSetTunableState(pGpu, pEngstate, pTunableState) intrSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define intrIsPresent(pGpu, pEngstate) intrIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS intrCheckFecsEventbufferPending_IMPL(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, NvBool *arg1); @@ -745,20 +731,6 @@ static inline void intrDisableStallSWIntr(OBJGPU *pGpu, struct Intr *pIntr) { #define intrDisableStallSWIntr_HAL(pGpu, pIntr) intrDisableStallSWIntr(pGpu, pIntr) -NV_STATUS intrEnableVirtualIntrLeaf_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid); - - -#ifdef __nvoc_intr_h_disabled -static inline NV_STATUS intrEnableVirtualIntrLeaf(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid) { - NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_intr_h_disabled -#define intrEnableVirtualIntrLeaf(pGpu, pIntr, gfid) intrEnableVirtualIntrLeaf_TU102(pGpu, pIntr, gfid) -#endif //__nvoc_intr_h_disabled - -#define intrEnableVirtualIntrLeaf_HAL(pGpu, pIntr, gfid) intrEnableVirtualIntrLeaf(pGpu, pIntr, gfid) - void intrServiceVirtual_TU102(OBJGPU *pGpu, struct Intr *pIntr); @@ -1006,57 +978,22 @@ static inline void intrWriteRegLeaf(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0 #define intrWriteRegLeaf_HAL(pGpu, pIntr, arg0, arg1, arg2) intrWriteRegLeaf(pGpu, pIntr, arg0, arg1, arg2) -static inline NvU32 intrUpdateIntrCtrlValue_4a4dee(OBJGPU *pGpu, struct Intr *pIntr, NvU32 intrCtrl, NvU32 routing) { - return 0; -} - -NvU32 intrUpdateIntrCtrlValue_GH100(OBJGPU *pGpu, struct Intr *pIntr, NvU32 intrCtrl, NvU32 routing); - - -#ifdef __nvoc_intr_h_disabled -static inline NvU32 intrUpdateIntrCtrlValue(OBJGPU *pGpu, struct Intr *pIntr, NvU32 intrCtrl, NvU32 routing) { - NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); - return 0; -} -#else //__nvoc_intr_h_disabled -#define intrUpdateIntrCtrlValue(pGpu, pIntr, intrCtrl, routing) intrUpdateIntrCtrlValue_4a4dee(pGpu, pIntr, intrCtrl, routing) -#endif //__nvoc_intr_h_disabled - -#define intrUpdateIntrCtrlValue_HAL(pGpu, pIntr, intrCtrl, routing) intrUpdateIntrCtrlValue(pGpu, pIntr, intrCtrl, routing) - -static inline void intrSetRouting_b3696a(OBJGPU *pGpu, struct Intr *pIntr, NvU32 intrCtrl, NvU32 intrCtrlReg, NvU32 routing) { +static inline void intrRouteInterruptsToSystemFirmware_b3696a(OBJGPU *pGpu, struct Intr *pIntr, NvBool bEnable) { return; } -void intrSetRouting_GH100(OBJGPU *pGpu, struct Intr *pIntr, NvU32 intrCtrl, NvU32 intrCtrlReg, NvU32 routing); +void intrRouteInterruptsToSystemFirmware_GH100(OBJGPU *pGpu, struct Intr *pIntr, NvBool bEnable); #ifdef __nvoc_intr_h_disabled -static inline void intrSetRouting(OBJGPU *pGpu, struct Intr *pIntr, NvU32 intrCtrl, NvU32 intrCtrlReg, NvU32 routing) { +static inline void intrRouteInterruptsToSystemFirmware(OBJGPU *pGpu, struct Intr *pIntr, NvBool bEnable) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); } #else //__nvoc_intr_h_disabled -#define intrSetRouting(pGpu, pIntr, intrCtrl, intrCtrlReg, routing) intrSetRouting_b3696a(pGpu, pIntr, intrCtrl, intrCtrlReg, routing) +#define intrRouteInterruptsToSystemFirmware(pGpu, pIntr, bEnable) intrRouteInterruptsToSystemFirmware_b3696a(pGpu, pIntr, bEnable) #endif //__nvoc_intr_h_disabled -#define intrSetRouting_HAL(pGpu, pIntr, intrCtrl, intrCtrlReg, routing) intrSetRouting(pGpu, pIntr, intrCtrl, intrCtrlReg, routing) - -static inline void intrRouteFBInterruptsToSystemFirmware_b3696a(OBJGPU *pGpu, struct Intr *pIntr, NvBool bEnable) { - return; -} - -void intrRouteFBInterruptsToSystemFirmware_GH100(OBJGPU *pGpu, struct Intr *pIntr, NvBool bEnable); - - -#ifdef __nvoc_intr_h_disabled -static inline void intrRouteFBInterruptsToSystemFirmware(OBJGPU *pGpu, struct Intr *pIntr, NvBool bEnable) { - NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); -} -#else //__nvoc_intr_h_disabled -#define intrRouteFBInterruptsToSystemFirmware(pGpu, pIntr, bEnable) intrRouteFBInterruptsToSystemFirmware_b3696a(pGpu, pIntr, bEnable) -#endif //__nvoc_intr_h_disabled - -#define intrRouteFBInterruptsToSystemFirmware_HAL(pGpu, pIntr, bEnable) intrRouteFBInterruptsToSystemFirmware(pGpu, pIntr, bEnable) +#define intrRouteInterruptsToSystemFirmware_HAL(pGpu, pIntr, bEnable) intrRouteInterruptsToSystemFirmware(pGpu, pIntr, bEnable) static inline NV_STATUS intrInitDynamicInterruptTable_5baef9(OBJGPU *pGpu, struct Intr *pIntr, struct OBJFIFO *arg0, INTR_TABLE_ENTRY *arg1, NvU32 arg2, NvU32 initFlags) { NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); @@ -1090,6 +1027,26 @@ static inline NV_STATUS intrInitAnyInterruptTable(OBJGPU *pGpu, struct Intr *pIn #define intrInitAnyInterruptTable_HAL(pGpu, pIntr, ppIntrTable, pIntrTableSz, initFlags) intrInitAnyInterruptTable(pGpu, pIntr, ppIntrTable, pIntrTableSz, initFlags) +static inline NV_STATUS intrInitSubtreeMap_395e98(OBJGPU *pGpu, struct Intr *pIntr) { + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS intrInitSubtreeMap_TU102(OBJGPU *pGpu, struct Intr *pIntr); + +NV_STATUS intrInitSubtreeMap_GH100(OBJGPU *pGpu, struct Intr *pIntr); + + +#ifdef __nvoc_intr_h_disabled +static inline NV_STATUS intrInitSubtreeMap(OBJGPU *pGpu, struct Intr *pIntr) { + NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_intr_h_disabled +#define intrInitSubtreeMap(pGpu, pIntr) intrInitSubtreeMap_395e98(pGpu, pIntr) +#endif //__nvoc_intr_h_disabled + +#define intrInitSubtreeMap_HAL(pGpu, pIntr) intrInitSubtreeMap(pGpu, pIntr) + NV_STATUS intrInitInterruptTable_KERNEL(OBJGPU *pGpu, struct Intr *pIntr); @@ -1606,14 +1563,6 @@ static inline void intrWriteRegTopEnClear_DISPATCH(OBJGPU *pGpu, struct Intr *pI pIntr->__intrWriteRegTopEnClear__(pGpu, pIntr, arg0, arg1, arg2); } -NvU32 intrGetStallSubtreeLast_TU102(OBJGPU *pGpu, struct Intr *pIntr); - -NvU32 intrGetStallSubtreeLast_GH100(OBJGPU *pGpu, struct Intr *pIntr); - -static inline NvU32 intrGetStallSubtreeLast_DISPATCH(OBJGPU *pGpu, struct Intr *pIntr) { - return pIntr->__intrGetStallSubtreeLast__(pGpu, pIntr); -} - NvU32 intrGetNumLeaves_TU102(OBJGPU *pGpu, struct Intr *pIntr); NvU32 intrGetNumLeaves_GH100(OBJGPU *pGpu, struct Intr *pIntr); @@ -1630,11 +1579,11 @@ static inline NvU32 intrGetLeafSize_DISPATCH(OBJGPU *pGpu, struct Intr *pIntr) { return pIntr->__intrGetLeafSize__(pGpu, pIntr); } -NvU32 intrGetIntrTopNonStallMask_TU102(OBJGPU *pGpu, struct Intr *pIntr); +NvU64 intrGetIntrTopNonStallMask_TU102(OBJGPU *pGpu, struct Intr *pIntr); -NvU32 intrGetIntrTopNonStallMask_GH100(OBJGPU *pGpu, struct Intr *pIntr); +NvU64 intrGetIntrTopNonStallMask_GH100(OBJGPU *pGpu, struct Intr *pIntr); -static inline NvU32 intrGetIntrTopNonStallMask_DISPATCH(OBJGPU *pGpu, struct Intr *pIntr) { +static inline NvU64 intrGetIntrTopNonStallMask_DISPATCH(OBJGPU *pGpu, struct Intr *pIntr) { return pIntr->__intrGetIntrTopNonStallMask__(pGpu, pIntr); } @@ -1704,10 +1653,6 @@ static inline NvU32 intrGetIntrEnFromHw_DISPATCH(OBJGPU *pGpu, struct Intr *pInt return pIntr->__intrGetIntrEnFromHw__(pGpu, pIntr, arg0); } -static inline NV_STATUS intrReconcileTunableState_DISPATCH(POBJGPU pGpu, struct Intr *pEngstate, void *pTunableState) { - return pEngstate->__intrReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS intrStatePreLoad_DISPATCH(POBJGPU pGpu, struct Intr *pEngstate, NvU32 arg0) { return pEngstate->__intrStatePreLoad__(pGpu, pEngstate, arg0); } @@ -1732,30 +1677,10 @@ static inline NV_STATUS intrStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct I return pEngstate->__intrStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS intrGetTunableState_DISPATCH(POBJGPU pGpu, struct Intr *pEngstate, void *pTunableState) { - return pEngstate->__intrGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS intrCompareTunableState_DISPATCH(POBJGPU pGpu, struct Intr *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__intrCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void intrFreeTunableState_DISPATCH(POBJGPU pGpu, struct Intr *pEngstate, void *pTunableState) { - pEngstate->__intrFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS intrStatePostLoad_DISPATCH(POBJGPU pGpu, struct Intr *pEngstate, NvU32 arg0) { return pEngstate->__intrStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS intrAllocTunableState_DISPATCH(POBJGPU pGpu, struct Intr *pEngstate, void **ppTunableState) { - return pEngstate->__intrAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS intrSetTunableState_DISPATCH(POBJGPU pGpu, struct Intr *pEngstate, void *pTunableState) { - return pEngstate->__intrSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool intrIsPresent_DISPATCH(POBJGPU pGpu, struct Intr *pEngstate) { return pEngstate->__intrIsPresent__(pGpu, pEngstate); } @@ -1785,6 +1710,50 @@ static inline NV_STATUS intrServiceNotificationRecords(OBJGPU *pGpu, struct Intr #define intrServiceNotificationRecords(pGpu, pIntr, mcEngineIdx, arg0) intrServiceNotificationRecords_IMPL(pGpu, pIntr, mcEngineIdx, arg0) #endif //__nvoc_intr_h_disabled +NvU64 intrGetIntrTopLegacyStallMask_IMPL(struct Intr *pIntr); + +#ifdef __nvoc_intr_h_disabled +static inline NvU64 intrGetIntrTopLegacyStallMask(struct Intr *pIntr) { + NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); + return 0; +} +#else //__nvoc_intr_h_disabled +#define intrGetIntrTopLegacyStallMask(pIntr) intrGetIntrTopLegacyStallMask_IMPL(pIntr) +#endif //__nvoc_intr_h_disabled + +NvU64 intrGetIntrTopLockedMask_IMPL(OBJGPU *pGpu, struct Intr *pIntr); + +#ifdef __nvoc_intr_h_disabled +static inline NvU64 intrGetIntrTopLockedMask(OBJGPU *pGpu, struct Intr *pIntr) { + NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); + return 0; +} +#else //__nvoc_intr_h_disabled +#define intrGetIntrTopLockedMask(pGpu, pIntr) intrGetIntrTopLockedMask_IMPL(pGpu, pIntr) +#endif //__nvoc_intr_h_disabled + +NV_STATUS intrGetSubtreeRange_IMPL(struct Intr *pIntr, NV2080_INTR_CATEGORY category, NV2080_INTR_CATEGORY_SUBTREE_MAP *pRange); + +#ifdef __nvoc_intr_h_disabled +static inline NV_STATUS intrGetSubtreeRange(struct Intr *pIntr, NV2080_INTR_CATEGORY category, NV2080_INTR_CATEGORY_SUBTREE_MAP *pRange) { + NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_intr_h_disabled +#define intrGetSubtreeRange(pIntr, category, pRange) intrGetSubtreeRange_IMPL(pIntr, category, pRange) +#endif //__nvoc_intr_h_disabled + +NvU64 intrGetIntrTopCategoryMask_IMPL(struct Intr *pIntr, NV2080_INTR_CATEGORY category); + +#ifdef __nvoc_intr_h_disabled +static inline NvU64 intrGetIntrTopCategoryMask(struct Intr *pIntr, NV2080_INTR_CATEGORY category) { + NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); + return 0; +} +#else //__nvoc_intr_h_disabled +#define intrGetIntrTopCategoryMask(pIntr, category) intrGetIntrTopCategoryMask_IMPL(pIntr, category) +#endif //__nvoc_intr_h_disabled + void intrServiceStallListAllGpusCond_IMPL(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, NvBool arg1); #ifdef __nvoc_intr_h_disabled diff --git a/src/nvidia/generated/g_intr_service_nvoc.h b/src/nvidia/generated/g_intr_service_nvoc.h index 4d33474a3..274729441 100644 --- a/src/nvidia/generated/g_intr_service_nvoc.h +++ b/src/nvidia/generated/g_intr_service_nvoc.h @@ -122,9 +122,9 @@ NV_STATUS __nvoc_objCreate_IntrService(IntrService**, Dynamic*, NvU32); #define intrservClearInterrupt(pGpu, pIntrService, pParams) intrservClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define intrservServiceInterrupt(pGpu, pIntrService, pParams) intrservServiceInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define intrservServiceNotificationInterrupt(pGpu, pIntrService, pParams) intrservServiceNotificationInterrupt_DISPATCH(pGpu, pIntrService, pParams) -void intrservRegisterIntrService_IMPL(struct OBJGPU *pGpu, struct IntrService *pIntrService, IntrServiceRecord pRecords[163]); +void intrservRegisterIntrService_IMPL(struct OBJGPU *pGpu, struct IntrService *pIntrService, IntrServiceRecord pRecords[166]); -static inline void intrservRegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct IntrService *pIntrService, IntrServiceRecord pRecords[163]) { +static inline void intrservRegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct IntrService *pIntrService, IntrServiceRecord pRecords[166]) { pIntrService->__intrservRegisterIntrService__(pGpu, pIntrService, pRecords); } diff --git a/src/nvidia/generated/g_io_vaspace_nvoc.c b/src/nvidia/generated/g_io_vaspace_nvoc.c index 7c66710ee..dd2ffaa40 100644 --- a/src/nvidia/generated/g_io_vaspace_nvoc.c +++ b/src/nvidia/generated/g_io_vaspace_nvoc.c @@ -134,7 +134,7 @@ static PMEMORY_DESCRIPTOR __nvoc_thunk_OBJVASPACE_iovaspaceGetKernelPageDirBase( return vaspaceGetKernelPageDirBase((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_OBJIOVASPACE_OBJVASPACE.offset), pGpu); } -static NvU32 __nvoc_thunk_OBJVASPACE_iovaspaceGetMapPageSize(struct OBJIOVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { +static NvU64 __nvoc_thunk_OBJVASPACE_iovaspaceGetMapPageSize(struct OBJIOVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { return vaspaceGetMapPageSize((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_OBJIOVASPACE_OBJVASPACE.offset), pGpu, pMemBlock); } @@ -315,13 +315,16 @@ NV_STATUS __nvoc_objCreate_OBJIOVASPACE(OBJIOVASPACE **ppThis, Dynamic *pParent, Object *pParentObj; OBJIOVASPACE *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJIOVASPACE)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJIOVASPACE), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJIOVASPACE)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJIOVASPACE); + pThis->__nvoc_base_OBJVASPACE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -337,11 +340,17 @@ NV_STATUS __nvoc_objCreate_OBJIOVASPACE(OBJIOVASPACE **ppThis, Dynamic *pParent, if (status != NV_OK) goto __nvoc_objCreate_OBJIOVASPACE_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJIOVASPACE_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJIOVASPACE)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_io_vaspace_nvoc.h b/src/nvidia/generated/g_io_vaspace_nvoc.h index dd578a3a3..b38a7747b 100644 --- a/src/nvidia/generated/g_io_vaspace_nvoc.h +++ b/src/nvidia/generated/g_io_vaspace_nvoc.h @@ -163,7 +163,7 @@ struct OBJIOVASPACE { NV_STATUS (*__iovaspaceGetPteInfo__)(struct OBJIOVASPACE *, struct OBJGPU *, NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS *, RmPhysAddr *); PMEMORY_DESCRIPTOR (*__iovaspaceGetPageDirBase__)(struct OBJIOVASPACE *, struct OBJGPU *); PMEMORY_DESCRIPTOR (*__iovaspaceGetKernelPageDirBase__)(struct OBJIOVASPACE *, struct OBJGPU *); - NvU32 (*__iovaspaceGetMapPageSize__)(struct OBJIOVASPACE *, struct OBJGPU *, EMEMBLOCK *); + NvU64 (*__iovaspaceGetMapPageSize__)(struct OBJIOVASPACE *, struct OBJGPU *, EMEMBLOCK *); struct OBJEHEAP *(*__iovaspaceGetHeap__)(struct OBJIOVASPACE *); NvBool (*__iovaspaceIsFaultCapable__)(struct OBJIOVASPACE *); void (*__iovaspaceUnmap__)(struct OBJIOVASPACE *, struct OBJGPU *, const NvU64, const NvU64); @@ -321,7 +321,7 @@ static inline PMEMORY_DESCRIPTOR iovaspaceGetKernelPageDirBase_DISPATCH(struct O return pVAS->__iovaspaceGetKernelPageDirBase__(pVAS, pGpu); } -static inline NvU32 iovaspaceGetMapPageSize_DISPATCH(struct OBJIOVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { +static inline NvU64 iovaspaceGetMapPageSize_DISPATCH(struct OBJIOVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { return pVAS->__iovaspaceGetMapPageSize__(pVAS, pGpu, pMemBlock); } diff --git a/src/nvidia/generated/g_ioaccess_nvoc.c b/src/nvidia/generated/g_ioaccess_nvoc.c new file mode 100644 index 000000000..f7386e9ad --- /dev/null +++ b/src/nvidia/generated/g_ioaccess_nvoc.c @@ -0,0 +1,113 @@ +#define NVOC_IOACCESS_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_ioaccess_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0xfcaf2e = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RegisterAperture; + +void __nvoc_init_RegisterAperture(RegisterAperture*); +void __nvoc_init_funcTable_RegisterAperture(RegisterAperture*); +NV_STATUS __nvoc_ctor_RegisterAperture(RegisterAperture*); +void __nvoc_init_dataField_RegisterAperture(RegisterAperture*); +void __nvoc_dtor_RegisterAperture(RegisterAperture*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_RegisterAperture; + +static const struct NVOC_RTTI __nvoc_rtti_RegisterAperture_RegisterAperture = { + /*pClassDef=*/ &__nvoc_class_def_RegisterAperture, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_RegisterAperture, + /*offset=*/ 0, +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_RegisterAperture = { + /*numRelatives=*/ 1, + /*relatives=*/ { + &__nvoc_rtti_RegisterAperture_RegisterAperture, + }, +}; + +// Not instantiable because it's not derived from class "Object" +// Not instantiable because it's an abstract class with following pure virtual functions: +// regaprtReadReg08 +// regaprtReadReg16 +// regaprtReadReg32 +// regaprtWriteReg08 +// regaprtWriteReg16 +// regaprtWriteReg32 +// regaprtWriteReg32Uc +// regaprtIsRegValid +const struct NVOC_CLASS_DEF __nvoc_class_def_RegisterAperture = +{ + /*classInfo=*/ { + /*size=*/ sizeof(RegisterAperture), + /*classId=*/ classId(RegisterAperture), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "RegisterAperture", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) NULL, + /*pCastInfo=*/ &__nvoc_castinfo_RegisterAperture, + /*pExportInfo=*/ &__nvoc_export_info_RegisterAperture +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_RegisterAperture = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_RegisterAperture(RegisterAperture *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_RegisterAperture(RegisterAperture *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_RegisterAperture(RegisterAperture *pThis) { + NV_STATUS status = NV_OK; + __nvoc_init_dataField_RegisterAperture(pThis); + goto __nvoc_ctor_RegisterAperture_exit; // Success + +__nvoc_ctor_RegisterAperture_exit: + + return status; +} + +static void __nvoc_init_funcTable_RegisterAperture_1(RegisterAperture *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + + pThis->__regaprtReadReg08__ = NULL; + + pThis->__regaprtReadReg16__ = NULL; + + pThis->__regaprtReadReg32__ = NULL; + + pThis->__regaprtWriteReg08__ = NULL; + + pThis->__regaprtWriteReg16__ = NULL; + + pThis->__regaprtWriteReg32__ = NULL; + + pThis->__regaprtWriteReg32Uc__ = NULL; + + pThis->__regaprtIsRegValid__ = NULL; +} + +void __nvoc_init_funcTable_RegisterAperture(RegisterAperture *pThis) { + __nvoc_init_funcTable_RegisterAperture_1(pThis); +} + +void __nvoc_init_RegisterAperture(RegisterAperture *pThis) { + pThis->__nvoc_pbase_RegisterAperture = pThis; + __nvoc_init_funcTable_RegisterAperture(pThis); +} + diff --git a/src/nvidia/generated/g_ioaccess_nvoc.h b/src/nvidia/generated/g_ioaccess_nvoc.h new file mode 100644 index 000000000..348a9a6fa --- /dev/null +++ b/src/nvidia/generated/g_ioaccess_nvoc.h @@ -0,0 +1,236 @@ +#ifndef _G_IOACCESS_NVOC_H_ +#define _G_IOACCESS_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#if (defined(NVRM) || defined(RMCFG_FEATURE_PLATFORM_GSP)) && !defined(NVWATCH) +#include "g_ioaccess_nvoc.h" +#endif + +#ifndef _IO_ACCESS_H_ +#define _IO_ACCESS_H_ + +#include "nvtypes.h" +#include "nvstatus.h" +#if (defined(NVRM) || defined(RMCFG_FEATURE_PLATFORM_GSP)) && !defined(NVWATCH) +#include "nvoc/prelude.h" +#endif + +#define REG_DRF_SHIFT(drf) ((0?drf) % 32) +#define REG_DRF_MASK(drf) (0xFFFFFFFF>>(31-((1?drf) % 32)+((0?drf) % 32))) +#define REG_DRF_DEF(d,r,f,c) ((NV ## d ## r ## f ## c)<>REG_DRF_SHIFT(NV ## d ## r ## f))®_DRF_MASK(NV ## d ## r ## f)) +#define REG_DRF_SHIFTMASK(drf) (REG_DRF_MASK(drf)<<(REG_DRF_SHIFT(drf))) +#define REG_DRF_WIDTH(drf) ((1?drf) - (0?drf) + 1) + +#if (defined(NVRM) || defined(RMCFG_FEATURE_PLATFORM_GSP)) && !defined(NVWATCH) +#define REG_RD08(ap, addr) regaprtReadReg08 (staticCast(ap, RegisterAperture), addr) +#define REG_RD16(ap, addr) regaprtReadReg16 (staticCast(ap, RegisterAperture), addr) +#define REG_RD32(ap, addr) regaprtReadReg32 (staticCast(ap, RegisterAperture), addr) +#define REG_WR08(ap, addr, val) regaprtWriteReg08 (staticCast(ap, RegisterAperture), addr, val) +#define REG_WR16(ap, addr, val) regaprtWriteReg16 (staticCast(ap, RegisterAperture), addr, val) +#define REG_WR32(ap, addr, val) regaprtWriteReg32 (staticCast(ap, RegisterAperture), addr, val) +#define REG_WR32_UC(ap, addr, val) regaprtWriteReg32Uc(staticCast(ap, RegisterAperture), addr, val) +#define REG_VALID(ap, addr) regaprtIsRegValid (staticCast(ap, RegisterAperture), addr) + +#ifdef NVOC_IOACCESS_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct RegisterAperture { + const struct NVOC_RTTI *__nvoc_rtti; + struct RegisterAperture *__nvoc_pbase_RegisterAperture; + NvU8 (*__regaprtReadReg08__)(struct RegisterAperture *, NvU32); + NvU16 (*__regaprtReadReg16__)(struct RegisterAperture *, NvU32); + NvU32 (*__regaprtReadReg32__)(struct RegisterAperture *, NvU32); + void (*__regaprtWriteReg08__)(struct RegisterAperture *, NvU32, NvV8); + void (*__regaprtWriteReg16__)(struct RegisterAperture *, NvU32, NvV16); + void (*__regaprtWriteReg32__)(struct RegisterAperture *, NvU32, NvV32); + void (*__regaprtWriteReg32Uc__)(struct RegisterAperture *, NvU32, NvV32); + NvBool (*__regaprtIsRegValid__)(struct RegisterAperture *, NvU32); +}; + +#ifndef __NVOC_CLASS_RegisterAperture_TYPEDEF__ +#define __NVOC_CLASS_RegisterAperture_TYPEDEF__ +typedef struct RegisterAperture RegisterAperture; +#endif /* __NVOC_CLASS_RegisterAperture_TYPEDEF__ */ + +#ifndef __nvoc_class_id_RegisterAperture +#define __nvoc_class_id_RegisterAperture 0xfcaf2e +#endif /* __nvoc_class_id_RegisterAperture */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RegisterAperture; + +#define __staticCast_RegisterAperture(pThis) \ + ((pThis)->__nvoc_pbase_RegisterAperture) + +#ifdef __nvoc_ioaccess_h_disabled +#define __dynamicCast_RegisterAperture(pThis) ((RegisterAperture*)NULL) +#else //__nvoc_ioaccess_h_disabled +#define __dynamicCast_RegisterAperture(pThis) \ + ((RegisterAperture*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(RegisterAperture))) +#endif //__nvoc_ioaccess_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_RegisterAperture(RegisterAperture**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_RegisterAperture(RegisterAperture**, Dynamic*, NvU32); +#define __objCreate_RegisterAperture(ppNewObj, pParent, createFlags) \ + __nvoc_objCreate_RegisterAperture((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) + +#define regaprtReadReg08(pAperture, addr) regaprtReadReg08_DISPATCH(pAperture, addr) +#define regaprtReadReg16(pAperture, addr) regaprtReadReg16_DISPATCH(pAperture, addr) +#define regaprtReadReg32(pAperture, addr) regaprtReadReg32_DISPATCH(pAperture, addr) +#define regaprtWriteReg08(pAperture, addr, value) regaprtWriteReg08_DISPATCH(pAperture, addr, value) +#define regaprtWriteReg16(pAperture, addr, value) regaprtWriteReg16_DISPATCH(pAperture, addr, value) +#define regaprtWriteReg32(pAperture, addr, value) regaprtWriteReg32_DISPATCH(pAperture, addr, value) +#define regaprtWriteReg32Uc(pAperture, addr, value) regaprtWriteReg32Uc_DISPATCH(pAperture, addr, value) +#define regaprtIsRegValid(pAperture, addr) regaprtIsRegValid_DISPATCH(pAperture, addr) +static inline NvU8 regaprtReadReg08_DISPATCH(struct RegisterAperture *pAperture, NvU32 addr) { + return pAperture->__regaprtReadReg08__(pAperture, addr); +} + +static inline NvU16 regaprtReadReg16_DISPATCH(struct RegisterAperture *pAperture, NvU32 addr) { + return pAperture->__regaprtReadReg16__(pAperture, addr); +} + +static inline NvU32 regaprtReadReg32_DISPATCH(struct RegisterAperture *pAperture, NvU32 addr) { + return pAperture->__regaprtReadReg32__(pAperture, addr); +} + +static inline void regaprtWriteReg08_DISPATCH(struct RegisterAperture *pAperture, NvU32 addr, NvV8 value) { + pAperture->__regaprtWriteReg08__(pAperture, addr, value); +} + +static inline void regaprtWriteReg16_DISPATCH(struct RegisterAperture *pAperture, NvU32 addr, NvV16 value) { + pAperture->__regaprtWriteReg16__(pAperture, addr, value); +} + +static inline void regaprtWriteReg32_DISPATCH(struct RegisterAperture *pAperture, NvU32 addr, NvV32 value) { + pAperture->__regaprtWriteReg32__(pAperture, addr, value); +} + +static inline void regaprtWriteReg32Uc_DISPATCH(struct RegisterAperture *pAperture, NvU32 addr, NvV32 value) { + pAperture->__regaprtWriteReg32Uc__(pAperture, addr, value); +} + +static inline NvBool regaprtIsRegValid_DISPATCH(struct RegisterAperture *pAperture, NvU32 addr) { + return pAperture->__regaprtIsRegValid__(pAperture, addr); +} + +#undef PRIVATE_FIELD + + +// +// TODO: Remove the wrapper structure WAR once NVOC supports in-place object construction +// The proxy structure was introduced to avoid major refactoring until the feature is implemented +// Also fix IoAperture getters +// Use the interface class in NVWATCH once NVOC is enabled there +// +#else // (defined(NVRM) || defined(RMCFG_FEATURE_PLATFORM_GSP)) && !defined(NVWATCH) +typedef struct IO_DEVICE IO_DEVICE; +typedef struct IO_APERTURE IO_APERTURE; + +typedef NvU8 ReadReg008Fn(IO_APERTURE *a, NvU32 addr); +typedef NvU16 ReadReg016Fn(IO_APERTURE *a, NvU32 addr); +typedef NvU32 ReadReg032Fn(IO_APERTURE *a, NvU32 addr); +typedef void WriteReg008Fn(IO_APERTURE *a, NvU32 addr, NvV8 value); +typedef void WriteReg016Fn(IO_APERTURE *a, NvU32 addr, NvV16 value); +typedef void WriteReg032Fn(IO_APERTURE *a, NvU32 addr, NvV32 value); +typedef NvBool ValidRegFn(IO_APERTURE *a, NvU32 addr); + +#define REG_RD08(ap, addr) (ap)->pDevice->pReadReg008Fn((ap), (addr)) +#define REG_RD16(ap, addr) (ap)->pDevice->pReadReg016Fn((ap), (addr)) +#define REG_RD32(ap, addr) (ap)->pDevice->pReadReg032Fn((ap), (addr)) +#define REG_WR08(ap, addr, val) (ap)->pDevice->pWriteReg008Fn((ap), (addr), (val)) +#define REG_WR16(ap, addr, val) (ap)->pDevice->pWriteReg016Fn((ap), (addr), (val)) +#define REG_WR32(ap, addr, val) (ap)->pDevice->pWriteReg032Fn((ap), (addr), (val)) +#define REG_WR32_UC(ap, addr, val) (ap)->pDevice->pWriteReg032UcFn((ap), (addr), (val)) +#define REG_VALID(ap, addr) (ap)->pDevice->pValidRegFn((ap), (addr)) + +// Get the address of a register given the Aperture and offset. +#define REG_GET_ADDR(ap, offset) ((ap)->baseAddress + (offset)) + +struct IO_DEVICE +{ + ReadReg008Fn *pReadReg008Fn; + ReadReg016Fn *pReadReg016Fn; + ReadReg032Fn *pReadReg032Fn; + WriteReg008Fn *pWriteReg008Fn; + WriteReg016Fn *pWriteReg016Fn; + WriteReg032Fn *pWriteReg032Fn; + WriteReg032Fn *pWriteReg032UcFn; + ValidRegFn *pValidRegFn; +}; + +struct IO_APERTURE +{ + IO_DEVICE *pDevice; // Pointer to module specific IO_DEVICE + NvU32 baseAddress; // register base address + NvU32 length; // length of aperture +}; + +NV_STATUS ioaccessInitIOAperture +( + IO_APERTURE *pAperture, + IO_APERTURE *pParentAperture, + IO_DEVICE *pDevice, + NvU32 offset, + NvU32 length +); +#endif // (defined(NVRM) || defined(RMCFG_FEATURE_PLATFORM_GSP)) && !defined(NVWATCH) + + +// +// Macros for register I/O +// + +#define REG_FLD_WR_DRF_NUM(ap,d,r,f,n) REG_WR32(ap,NV##d##r,(REG_RD32(ap,NV##d##r)&~(REG_DRF_MASK(NV##d##r##f)<>REG_DRF_SHIFT(NV ## d ## r ## f))®_DRF_MASK(NV ## d ## r ## f)) +#define REG_FLD_TEST_DRF_DEF(ap,d,r,f,c) (REG_RD_DRF(ap,d, r, f) == NV##d##r##f##c) +#define REG_FLD_TEST_DRF_NUM(ap,d,r,f,n) (REG_RD_DRF(ap,d, r, f) == n) +#define REG_FLD_IDX_TEST_DRF_DEF(ap,d,r,f,c,i) (REG_IDX_RD_DRF(ap, d, r, i, f) == NV##d##r##f##c) + +// Read/write a field or entire register of which there are several copies each accessed via an index +#define REG_IDX_WR_DRF_NUM(ap,d,r,i,f,n) REG_WR32(ap,NV ## d ## r(i), REG_DRF_NUM(d,r,f,n)) +#define REG_IDX_WR_DRF_DEF(ap,d,r,i,f,c) REG_WR32(ap,NV ## d ## r(i), REG_DRF_DEF(d,r,f,c)) +#define REG_FLD_IDX_WR_DRF_NUM(ap,d,r,i,f,n) REG_WR32(ap,NV##d##r(i),(REG_RD32(ap,NV##d##r(i))&~(REG_DRF_MASK(NV##d##r##f)<>REG_DRF_SHIFT(NV ## d ## r ## f))®_DRF_MASK(NV ## d ## r ## f)) +#define REG_RD_DRF_IDX(ap,d,r,f,i) (((REG_RD32(ap,NV ## d ## r))>>REG_DRF_SHIFT(NV ## d ## r ## f(i)))®_DRF_MASK(NV ## d ## r ## f(i))) +#define REG_IDX_OFFSET_RD_DRF(ap,d,r,i,o,f) (((REG_RD32(ap,NV ## d ## r(i,o)))>>REG_DRF_SHIFT(NV ## d ## r ## f))®_DRF_MASK(NV ## d ## r ## f)) + +#endif // _IO_ACCESS_H_ + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_IOACCESS_NVOC_H_ diff --git a/src/nvidia/generated/g_journal_nvoc.c b/src/nvidia/generated/g_journal_nvoc.c index 4062a862e..2cee60538 100644 --- a/src/nvidia/generated/g_journal_nvoc.c +++ b/src/nvidia/generated/g_journal_nvoc.c @@ -134,13 +134,16 @@ NV_STATUS __nvoc_objCreate_OBJRCDB(OBJRCDB **ppThis, Dynamic *pParent, NvU32 cre Object *pParentObj; OBJRCDB *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJRCDB)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJRCDB), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJRCDB)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJRCDB); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -156,11 +159,17 @@ NV_STATUS __nvoc_objCreate_OBJRCDB(OBJRCDB **ppThis, Dynamic *pParent, NvU32 cre if (status != NV_OK) goto __nvoc_objCreate_OBJRCDB_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJRCDB_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJRCDB)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kern_bus_nvoc.c b/src/nvidia/generated/g_kern_bus_nvoc.c index c4ea40087..ccf872aac 100644 --- a/src/nvidia/generated/g_kern_bus_nvoc.c +++ b/src/nvidia/generated/g_kern_bus_nvoc.c @@ -78,10 +78,6 @@ static NV_STATUS __nvoc_thunk_KernelBus_engstateStateInitLocked(OBJGPU *pGpu, st return kbusStateInitLocked(pGpu, (struct KernelBus *)(((unsigned char *)pKernelBus) - __nvoc_rtti_KernelBus_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_KernelBus_engstateStatePreLoad(OBJGPU *pGpu, struct OBJENGSTATE *pKernelBus, NvU32 arg0) { - return kbusStatePreLoad(pGpu, (struct KernelBus *)(((unsigned char *)pKernelBus) - __nvoc_rtti_KernelBus_OBJENGSTATE.offset), arg0); -} - static NV_STATUS __nvoc_thunk_KernelBus_engstateStateLoad(OBJGPU *pGpu, struct OBJENGSTATE *pKernelBus, NvU32 arg0) { return kbusStateLoad(pGpu, (struct KernelBus *)(((unsigned char *)pKernelBus) - __nvoc_rtti_KernelBus_OBJENGSTATE.offset), arg0); } @@ -102,8 +98,8 @@ static void __nvoc_thunk_KernelBus_engstateStateDestroy(OBJGPU *pGpu, struct OBJ kbusStateDestroy(pGpu, (struct KernelBus *)(((unsigned char *)pKernelBus) - __nvoc_rtti_KernelBus_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbusReconcileTunableState(POBJGPU pGpu, struct KernelBus *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBus_OBJENGSTATE.offset), pTunableState); +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbusStatePreLoad(POBJGPU pGpu, struct KernelBus *pEngstate, NvU32 arg0) { + return engstateStatePreLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBus_OBJENGSTATE.offset), arg0); } static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbusStatePostUnload(POBJGPU pGpu, struct KernelBus *pEngstate, NvU32 arg0) { @@ -122,26 +118,6 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbusStatePreInitUnlocked(POBJGPU pGpu, return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBus_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbusGetTunableState(POBJGPU pGpu, struct KernelBus *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBus_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbusCompareTunableState(POBJGPU pGpu, struct KernelBus *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBus_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kbusFreeTunableState(POBJGPU pGpu, struct KernelBus *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBus_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbusAllocTunableState(POBJGPU pGpu, struct KernelBus *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBus_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbusSetTunableState(POBJGPU pGpu, struct KernelBus *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBus_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_kbusIsPresent(POBJGPU pGpu, struct KernelBus *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBus_OBJENGSTATE.offset)); } @@ -212,6 +188,17 @@ void __nvoc_init_dataField_KernelBus(KernelBus *pThis, RmHalspecOwner *pRmhalspe pThis->bBar2InternalOnly = ((NvBool)(0 != 0)); } + // Hal field -- bIsEntireBar2RegionVirtuallyAddressible + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->bIsEntireBar2RegionVirtuallyAddressible = ((NvBool)(0 == 0)); + } + // default + else + { + pThis->bIsEntireBar2RegionVirtuallyAddressible = ((NvBool)(0 != 0)); + } + // Hal field -- bSkipBar2TestOnGc6Exit // default { @@ -278,12 +265,6 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * pThis->__kbusStateInitLocked__ = &kbusStateInitLocked_IMPL; - // Hal function -- kbusStatePreLoad - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__kbusStatePreLoad__ = &kbusStatePreLoad_56cd7a; - } - // Hal function -- kbusStateLoad if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { @@ -306,9 +287,12 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * } // Hal function -- kbusStateUnload - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - pThis->__kbusStateUnload__ = &kbusStateUnload_GM107; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->__kbusStateUnload__ = &kbusStateUnload_GM107; + } } // Hal function -- kbusStateDestroy @@ -674,8 +658,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * { pThis->__kbusSetupUnbindFla__ = &kbusSetupUnbindFla_GH100; } - // default - else + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbusSetupUnbindFla__ = &kbusSetupUnbindFla_46f6a7; } @@ -692,8 +675,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * { pThis->__kbusSetupBindFla__ = &kbusSetupBindFla_GH100; } - // default - else + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbusSetupBindFla__ = &kbusSetupBindFla_46f6a7; } @@ -834,8 +816,6 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_KernelBus_engstateStateInitLocked; - pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreLoad__ = &__nvoc_thunk_KernelBus_engstateStatePreLoad; - pThis->__nvoc_base_OBJENGSTATE.__engstateStateLoad__ = &__nvoc_thunk_KernelBus_engstateStateLoad; pThis->__nvoc_base_OBJENGSTATE.__engstateStatePostLoad__ = &__nvoc_thunk_KernelBus_engstateStatePostLoad; @@ -846,7 +826,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_KernelBus_engstateStateDestroy; - pThis->__kbusReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kbusReconcileTunableState; + pThis->__kbusStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_kbusStatePreLoad; pThis->__kbusStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_kbusStatePostUnload; @@ -856,16 +836,6 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * pThis->__kbusStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kbusStatePreInitUnlocked; - pThis->__kbusGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kbusGetTunableState; - - pThis->__kbusCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kbusCompareTunableState; - - pThis->__kbusFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kbusFreeTunableState; - - pThis->__kbusAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kbusAllocTunableState; - - pThis->__kbusSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kbusSetTunableState; - pThis->__kbusIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kbusIsPresent; } @@ -906,13 +876,16 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus **ppThis, Dynamic *pParent, NvU32 KernelBus *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelBus)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelBus), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelBus)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelBus); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -932,11 +905,17 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus **ppThis, Dynamic *pParent, NvU32 if (status != NV_OK) goto __nvoc_objCreate_KernelBus_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelBus_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelBus)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kern_bus_nvoc.h b/src/nvidia/generated/g_kern_bus_nvoc.h index be49a8cab..20ed69026 100644 --- a/src/nvidia/generated/g_kern_bus_nvoc.h +++ b/src/nvidia/generated/g_kern_bus_nvoc.h @@ -297,7 +297,6 @@ struct KernelBus { NV_STATUS (*__kbusConstructEngine__)(OBJGPU *, struct KernelBus *, ENGDESCRIPTOR); NV_STATUS (*__kbusStatePreInitLocked__)(OBJGPU *, struct KernelBus *); NV_STATUS (*__kbusStateInitLocked__)(OBJGPU *, struct KernelBus *); - NV_STATUS (*__kbusStatePreLoad__)(OBJGPU *, struct KernelBus *, NvU32); NV_STATUS (*__kbusStateLoad__)(OBJGPU *, struct KernelBus *, NvU32); NV_STATUS (*__kbusStatePostLoad__)(OBJGPU *, struct KernelBus *, NvU32); NV_STATUS (*__kbusStatePreUnload__)(OBJGPU *, struct KernelBus *, NvU32); @@ -348,16 +347,11 @@ struct KernelBus { NvU8 *(*__kbusMapCoherentCpuMapping__)(OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR); void (*__kbusUnmapCoherentCpuMapping__)(OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR); void (*__kbusTeardownCoherentCpuMapping__)(OBJGPU *, struct KernelBus *, NvBool); - NV_STATUS (*__kbusReconcileTunableState__)(POBJGPU, struct KernelBus *, void *); + NV_STATUS (*__kbusStatePreLoad__)(POBJGPU, struct KernelBus *, NvU32); NV_STATUS (*__kbusStatePostUnload__)(POBJGPU, struct KernelBus *, NvU32); NV_STATUS (*__kbusStateInitUnlocked__)(POBJGPU, struct KernelBus *); void (*__kbusInitMissing__)(POBJGPU, struct KernelBus *); NV_STATUS (*__kbusStatePreInitUnlocked__)(POBJGPU, struct KernelBus *); - NV_STATUS (*__kbusGetTunableState__)(POBJGPU, struct KernelBus *, void *); - NV_STATUS (*__kbusCompareTunableState__)(POBJGPU, struct KernelBus *, void *, void *); - void (*__kbusFreeTunableState__)(POBJGPU, struct KernelBus *, void *); - NV_STATUS (*__kbusAllocTunableState__)(POBJGPU, struct KernelBus *, void **); - NV_STATUS (*__kbusSetTunableState__)(POBJGPU, struct KernelBus *, void *); NvBool (*__kbusIsPresent__)(POBJGPU, struct KernelBus *); NvU32 totalPciBars; RmPhysAddr pciBars[8]; @@ -402,6 +396,7 @@ struct KernelBus { NvBool bAllowReflectedMappingAccess; NvBool bBar2Tunnelled; NvBool bBar2InternalOnly; + NvBool bIsEntireBar2RegionVirtuallyAddressible; NvBool bSkipBar2TestOnGc6Exit; NvBool bFbFlushDisabled; PMEMORY_DESCRIPTOR pFlushMemDesc; @@ -452,8 +447,6 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus**, Dynamic*, NvU32); #define kbusStatePreInitLocked(pGpu, pKernelBus) kbusStatePreInitLocked_DISPATCH(pGpu, pKernelBus) #define kbusStatePreInitLocked_HAL(pGpu, pKernelBus) kbusStatePreInitLocked_DISPATCH(pGpu, pKernelBus) #define kbusStateInitLocked(pGpu, pKernelBus) kbusStateInitLocked_DISPATCH(pGpu, pKernelBus) -#define kbusStatePreLoad(pGpu, pKernelBus, arg0) kbusStatePreLoad_DISPATCH(pGpu, pKernelBus, arg0) -#define kbusStatePreLoad_HAL(pGpu, pKernelBus, arg0) kbusStatePreLoad_DISPATCH(pGpu, pKernelBus, arg0) #define kbusStateLoad(pGpu, pKernelBus, arg0) kbusStateLoad_DISPATCH(pGpu, pKernelBus, arg0) #define kbusStateLoad_HAL(pGpu, pKernelBus, arg0) kbusStateLoad_DISPATCH(pGpu, pKernelBus, arg0) #define kbusStatePostLoad(pGpu, pKernelBus, arg0) kbusStatePostLoad_DISPATCH(pGpu, pKernelBus, arg0) @@ -556,16 +549,11 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus**, Dynamic*, NvU32); #define kbusUnmapCoherentCpuMapping_HAL(pGpu, pKernelBus, arg0) kbusUnmapCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) #define kbusTeardownCoherentCpuMapping(pGpu, pKernelBus, arg0) kbusTeardownCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) #define kbusTeardownCoherentCpuMapping_HAL(pGpu, pKernelBus, arg0) kbusTeardownCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) -#define kbusReconcileTunableState(pGpu, pEngstate, pTunableState) kbusReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) +#define kbusStatePreLoad(pGpu, pEngstate, arg0) kbusStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kbusStatePostUnload(pGpu, pEngstate, arg0) kbusStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) #define kbusStateInitUnlocked(pGpu, pEngstate) kbusStateInitUnlocked_DISPATCH(pGpu, pEngstate) #define kbusInitMissing(pGpu, pEngstate) kbusInitMissing_DISPATCH(pGpu, pEngstate) #define kbusStatePreInitUnlocked(pGpu, pEngstate) kbusStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kbusGetTunableState(pGpu, pEngstate, pTunableState) kbusGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kbusCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kbusCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kbusFreeTunableState(pGpu, pEngstate, pTunableState) kbusFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kbusAllocTunableState(pGpu, pEngstate, ppTunableState) kbusAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kbusSetTunableState(pGpu, pEngstate, pTunableState) kbusSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kbusIsPresent(pGpu, pEngstate) kbusIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS kbusInitBarsSize_KERNEL(OBJGPU *pGpu, struct KernelBus *pKernelBus); @@ -1605,14 +1593,6 @@ static inline NV_STATUS kbusStateInitLocked_DISPATCH(OBJGPU *pGpu, struct Kernel return pKernelBus->__kbusStateInitLocked__(pGpu, pKernelBus); } -static inline NV_STATUS kbusStatePreLoad_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { - return NV_OK; -} - -static inline NV_STATUS kbusStatePreLoad_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { - return pKernelBus->__kbusStatePreLoad__(pGpu, pKernelBus, arg0); -} - NV_STATUS kbusStateLoad_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0); static inline NV_STATUS kbusStateLoad_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { @@ -2089,8 +2069,8 @@ static inline void kbusTeardownCoherentCpuMapping_DISPATCH(OBJGPU *pGpu, struct pKernelBus->__kbusTeardownCoherentCpuMapping__(pGpu, pKernelBus, arg0); } -static inline NV_STATUS kbusReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelBus *pEngstate, void *pTunableState) { - return pEngstate->__kbusReconcileTunableState__(pGpu, pEngstate, pTunableState); +static inline NV_STATUS kbusStatePreLoad_DISPATCH(POBJGPU pGpu, struct KernelBus *pEngstate, NvU32 arg0) { + return pEngstate->__kbusStatePreLoad__(pGpu, pEngstate, arg0); } static inline NV_STATUS kbusStatePostUnload_DISPATCH(POBJGPU pGpu, struct KernelBus *pEngstate, NvU32 arg0) { @@ -2109,26 +2089,6 @@ static inline NV_STATUS kbusStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct K return pEngstate->__kbusStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kbusGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelBus *pEngstate, void *pTunableState) { - return pEngstate->__kbusGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kbusCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelBus *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kbusCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kbusFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelBus *pEngstate, void *pTunableState) { - pEngstate->__kbusFreeTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kbusAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelBus *pEngstate, void **ppTunableState) { - return pEngstate->__kbusAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kbusSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelBus *pEngstate, void *pTunableState) { - return pEngstate->__kbusSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kbusIsPresent_DISPATCH(POBJGPU pGpu, struct KernelBus *pEngstate) { return pEngstate->__kbusIsPresent__(pGpu, pEngstate); } @@ -2376,6 +2336,13 @@ static inline NvU8 *kbusCpuOffsetInBar2WindowGet(OBJGPU *pGpu, struct KernelBus kbusUnmapRmApertureWithFlags_HAL(pGpu, pMemDesc, pCpuPtr, \ (bFlush) ? TRANSFER_FLAGS_NONE : TRANSFER_FLAGS_DEFER_FLUSH) +// +// For SHH/GH180, BAR0 PRAMIN and CPU-visible BAR1/2 should be disabled when C2C is being used. +// For P9+GV100, BAR0 PRAMIN and CPU-visible BAR1/2 should never be disabled. +// +#define KBUS_BAR0_PRAMIN_DISABLED(pGpu) NV_FALSE +#define KBUS_CPU_VISIBLE_BAR12_DISABLED(pGpu) NV_FALSE + #endif // KERN_BUS_H #ifdef __cplusplus diff --git a/src/nvidia/generated/g_kern_disp_nvoc.c b/src/nvidia/generated/g_kern_disp_nvoc.c index 881429f44..db6be6f5a 100644 --- a/src/nvidia/generated/g_kern_disp_nvoc.c +++ b/src/nvidia/generated/g_kern_disp_nvoc.c @@ -99,7 +99,7 @@ static NV_STATUS __nvoc_thunk_KernelDisplay_engstateStateUnload(OBJGPU *pGpu, st return kdispStateUnload(pGpu, (struct KernelDisplay *)(((unsigned char *)pKernelDisplay) - __nvoc_rtti_KernelDisplay_OBJENGSTATE.offset), flags); } -static void __nvoc_thunk_KernelDisplay_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pKernelDisplay, IntrServiceRecord pRecords[163]) { +static void __nvoc_thunk_KernelDisplay_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pKernelDisplay, IntrServiceRecord pRecords[166]) { kdispRegisterIntrService(pGpu, (struct KernelDisplay *)(((unsigned char *)pKernelDisplay) - __nvoc_rtti_KernelDisplay_IntrService.offset), pRecords); } @@ -107,10 +107,6 @@ static NvU32 __nvoc_thunk_KernelDisplay_intrservServiceInterrupt(OBJGPU *pGpu, s return kdispServiceInterrupt(pGpu, (struct KernelDisplay *)(((unsigned char *)pKernelDisplay) - __nvoc_rtti_KernelDisplay_IntrService.offset), pParams); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kdispReconcileTunableState(POBJGPU pGpu, struct KernelDisplay *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelDisplay_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_IntrService_kdispServiceNotificationInterrupt(OBJGPU *pGpu, struct KernelDisplay *pIntrService, IntrServiceServiceNotificationInterruptArguments *pParams) { return intrservServiceNotificationInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_KernelDisplay_IntrService.offset), pParams); } @@ -139,18 +135,6 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_kdispStatePreInitUnlocked(POBJGPU pGpu return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelDisplay_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kdispGetTunableState(POBJGPU pGpu, struct KernelDisplay *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelDisplay_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kdispCompareTunableState(POBJGPU pGpu, struct KernelDisplay *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelDisplay_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kdispFreeTunableState(POBJGPU pGpu, struct KernelDisplay *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelDisplay_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_IntrService_kdispClearInterrupt(OBJGPU *pGpu, struct KernelDisplay *pIntrService, IntrServiceClearInterruptArguments *pParams) { return intrservClearInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_KernelDisplay_IntrService.offset), pParams); } @@ -159,14 +143,6 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_kdispStatePostLoad(POBJGPU pGpu, struc return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelDisplay_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kdispAllocTunableState(POBJGPU pGpu, struct KernelDisplay *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelDisplay_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kdispSetTunableState(POBJGPU pGpu, struct KernelDisplay *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelDisplay_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_kdispIsPresent(POBJGPU pGpu, struct KernelDisplay *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelDisplay_OBJENGSTATE.offset)); } @@ -209,7 +185,7 @@ void __nvoc_init_dataField_KernelDisplay(KernelDisplay *pThis, RmHalspecOwner *p } // NVOC Property Hal field -- PDB_PROP_KDISP_IMP_ENABLE - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ && (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ )) { pThis->setProperty(pThis, PDB_PROP_KDISP_IMP_ENABLE, ((NvBool)(0 == 0))); } @@ -389,6 +365,34 @@ static void __nvoc_init_funcTable_KernelDisplay_1(KernelDisplay *pThis, RmHalspe pThis->__kdispSetSwapBarrierLsrMinTime__ = &kdispSetSwapBarrierLsrMinTime_b3696a; } + // Hal function -- kdispGetRgScanLock + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + { + pThis->__kdispGetRgScanLock__ = &kdispGetRgScanLock_v02_01; + } + // default + else + { + pThis->__kdispGetRgScanLock__ = &kdispGetRgScanLock_92bfc3; + } + } + + // Hal function -- kdispDetectSliLink + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + { + pThis->__kdispDetectSliLink__ = &kdispDetectSliLink_v04_00; + } + // default + else + { + pThis->__kdispDetectSliLink__ = &kdispDetectSliLink_92bfc3; + } + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelDisplay_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreInitLocked__ = &__nvoc_thunk_KernelDisplay_engstateStatePreInitLocked; @@ -405,8 +409,6 @@ static void __nvoc_init_funcTable_KernelDisplay_1(KernelDisplay *pThis, RmHalspe pThis->__nvoc_base_IntrService.__intrservServiceInterrupt__ = &__nvoc_thunk_KernelDisplay_intrservServiceInterrupt; - pThis->__kdispReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kdispReconcileTunableState; - pThis->__kdispServiceNotificationInterrupt__ = &__nvoc_thunk_IntrService_kdispServiceNotificationInterrupt; pThis->__kdispStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_kdispStatePreLoad; @@ -421,20 +423,10 @@ static void __nvoc_init_funcTable_KernelDisplay_1(KernelDisplay *pThis, RmHalspe pThis->__kdispStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kdispStatePreInitUnlocked; - pThis->__kdispGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kdispGetTunableState; - - pThis->__kdispCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kdispCompareTunableState; - - pThis->__kdispFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kdispFreeTunableState; - pThis->__kdispClearInterrupt__ = &__nvoc_thunk_IntrService_kdispClearInterrupt; pThis->__kdispStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kdispStatePostLoad; - pThis->__kdispAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kdispAllocTunableState; - - pThis->__kdispSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kdispSetTunableState; - pThis->__kdispIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kdispIsPresent; } @@ -460,13 +452,16 @@ NV_STATUS __nvoc_objCreate_KernelDisplay(KernelDisplay **ppThis, Dynamic *pParen KernelDisplay *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelDisplay)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelDisplay), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelDisplay)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelDisplay); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -486,11 +481,17 @@ NV_STATUS __nvoc_objCreate_KernelDisplay(KernelDisplay **ppThis, Dynamic *pParen if (status != NV_OK) goto __nvoc_objCreate_KernelDisplay_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelDisplay_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelDisplay)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kern_disp_nvoc.h b/src/nvidia/generated/g_kern_disp_nvoc.h index 4e1851648..2932236b3 100644 --- a/src/nvidia/generated/g_kern_disp_nvoc.h +++ b/src/nvidia/generated/g_kern_disp_nvoc.h @@ -118,7 +118,8 @@ struct KernelDisplay { void (*__kdispRestoreOriginalLsrMinTime__)(OBJGPU *, struct KernelDisplay *, NvU32, NvU32); NV_STATUS (*__kdispComputeLsrMinTimeValue__)(OBJGPU *, struct KernelDisplay *, NvU32, NvU32, NvU32 *); void (*__kdispSetSwapBarrierLsrMinTime__)(OBJGPU *, struct KernelDisplay *, NvU32, NvU32 *, NvU32); - NV_STATUS (*__kdispReconcileTunableState__)(POBJGPU, struct KernelDisplay *, void *); + NV_STATUS (*__kdispGetRgScanLock__)(OBJGPU *, struct KernelDisplay *, NvU32, OBJGPU *, NvU32, NvBool *, NvU32 *, NvBool *, NvU32 *); + NV_STATUS (*__kdispDetectSliLink__)(struct KernelDisplay *, OBJGPU *, OBJGPU *, NvU32, NvU32); NV_STATUS (*__kdispServiceNotificationInterrupt__)(OBJGPU *, struct KernelDisplay *, IntrServiceServiceNotificationInterruptArguments *); NV_STATUS (*__kdispStatePreLoad__)(POBJGPU, struct KernelDisplay *, NvU32); NV_STATUS (*__kdispStatePostUnload__)(POBJGPU, struct KernelDisplay *, NvU32); @@ -126,13 +127,8 @@ struct KernelDisplay { NV_STATUS (*__kdispStateInitUnlocked__)(POBJGPU, struct KernelDisplay *); void (*__kdispInitMissing__)(POBJGPU, struct KernelDisplay *); NV_STATUS (*__kdispStatePreInitUnlocked__)(POBJGPU, struct KernelDisplay *); - NV_STATUS (*__kdispGetTunableState__)(POBJGPU, struct KernelDisplay *, void *); - NV_STATUS (*__kdispCompareTunableState__)(POBJGPU, struct KernelDisplay *, void *, void *); - void (*__kdispFreeTunableState__)(POBJGPU, struct KernelDisplay *, void *); NvBool (*__kdispClearInterrupt__)(OBJGPU *, struct KernelDisplay *, IntrServiceClearInterruptArguments *); NV_STATUS (*__kdispStatePostLoad__)(POBJGPU, struct KernelDisplay *, NvU32); - NV_STATUS (*__kdispAllocTunableState__)(POBJGPU, struct KernelDisplay *, void **); - NV_STATUS (*__kdispSetTunableState__)(POBJGPU, struct KernelDisplay *, void *); NvBool (*__kdispIsPresent__)(POBJGPU, struct KernelDisplay *); NvBool PDB_PROP_KDISP_IMP_ENABLE; struct DisplayInstanceMemory *pInst; @@ -206,7 +202,10 @@ NV_STATUS __nvoc_objCreate_KernelDisplay(KernelDisplay**, Dynamic*, NvU32); #define kdispComputeLsrMinTimeValue_HAL(pGpu, pKernelDisplay, head, swapRdyHiLsrMinTime, pComputedLsrMinTime) kdispComputeLsrMinTimeValue_DISPATCH(pGpu, pKernelDisplay, head, swapRdyHiLsrMinTime, pComputedLsrMinTime) #define kdispSetSwapBarrierLsrMinTime(pGpu, pKernelDisplay, head, pOrigLsrMinTime, newLsrMinTime) kdispSetSwapBarrierLsrMinTime_DISPATCH(pGpu, pKernelDisplay, head, pOrigLsrMinTime, newLsrMinTime) #define kdispSetSwapBarrierLsrMinTime_HAL(pGpu, pKernelDisplay, head, pOrigLsrMinTime, newLsrMinTime) kdispSetSwapBarrierLsrMinTime_DISPATCH(pGpu, pKernelDisplay, head, pOrigLsrMinTime, newLsrMinTime) -#define kdispReconcileTunableState(pGpu, pEngstate, pTunableState) kdispReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) +#define kdispGetRgScanLock(pGpu, pKernelDisplay, head0, pPeerGpu, head1, pMasterScanLock, pMasterScanLockPin, pSlaveScanLock, pSlaveScanLockPin) kdispGetRgScanLock_DISPATCH(pGpu, pKernelDisplay, head0, pPeerGpu, head1, pMasterScanLock, pMasterScanLockPin, pSlaveScanLock, pSlaveScanLockPin) +#define kdispGetRgScanLock_HAL(pGpu, pKernelDisplay, head0, pPeerGpu, head1, pMasterScanLock, pMasterScanLockPin, pSlaveScanLock, pSlaveScanLockPin) kdispGetRgScanLock_DISPATCH(pGpu, pKernelDisplay, head0, pPeerGpu, head1, pMasterScanLock, pMasterScanLockPin, pSlaveScanLock, pSlaveScanLockPin) +#define kdispDetectSliLink(pKernelDisplay, pParentGpu, pChildGpu, ParentDrPort, ChildDrPort) kdispDetectSliLink_DISPATCH(pKernelDisplay, pParentGpu, pChildGpu, ParentDrPort, ChildDrPort) +#define kdispDetectSliLink_HAL(pKernelDisplay, pParentGpu, pChildGpu, ParentDrPort, ChildDrPort) kdispDetectSliLink_DISPATCH(pKernelDisplay, pParentGpu, pChildGpu, ParentDrPort, ChildDrPort) #define kdispServiceNotificationInterrupt(pGpu, pIntrService, pParams) kdispServiceNotificationInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define kdispStatePreLoad(pGpu, pEngstate, arg0) kdispStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kdispStatePostUnload(pGpu, pEngstate, arg0) kdispStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) @@ -214,13 +213,8 @@ NV_STATUS __nvoc_objCreate_KernelDisplay(KernelDisplay**, Dynamic*, NvU32); #define kdispStateInitUnlocked(pGpu, pEngstate) kdispStateInitUnlocked_DISPATCH(pGpu, pEngstate) #define kdispInitMissing(pGpu, pEngstate) kdispInitMissing_DISPATCH(pGpu, pEngstate) #define kdispStatePreInitUnlocked(pGpu, pEngstate) kdispStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kdispGetTunableState(pGpu, pEngstate, pTunableState) kdispGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kdispCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kdispCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kdispFreeTunableState(pGpu, pEngstate, pTunableState) kdispFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kdispClearInterrupt(pGpu, pIntrService, pParams) kdispClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define kdispStatePostLoad(pGpu, pEngstate, arg0) kdispStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define kdispAllocTunableState(pGpu, pEngstate, ppTunableState) kdispAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kdispSetTunableState(pGpu, pEngstate, pTunableState) kdispSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kdispIsPresent(pGpu, pEngstate) kdispIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS kdispConstructInstMem_IMPL(struct KernelDisplay *pKernelDisplay); @@ -506,9 +500,9 @@ static inline NV_STATUS kdispStateUnload_DISPATCH(OBJGPU *pGpu, struct KernelDis return pKernelDisplay->__kdispStateUnload__(pGpu, pKernelDisplay, flags); } -void kdispRegisterIntrService_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, IntrServiceRecord pRecords[163]); +void kdispRegisterIntrService_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, IntrServiceRecord pRecords[166]); -static inline void kdispRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, IntrServiceRecord pRecords[163]) { +static inline void kdispRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, IntrServiceRecord pRecords[166]) { pKernelDisplay->__kdispRegisterIntrService__(pGpu, pKernelDisplay, pRecords); } @@ -623,8 +617,26 @@ static inline void kdispSetSwapBarrierLsrMinTime_DISPATCH(OBJGPU *pGpu, struct K pKernelDisplay->__kdispSetSwapBarrierLsrMinTime__(pGpu, pKernelDisplay, head, pOrigLsrMinTime, newLsrMinTime); } -static inline NV_STATUS kdispReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelDisplay *pEngstate, void *pTunableState) { - return pEngstate->__kdispReconcileTunableState__(pGpu, pEngstate, pTunableState); +NV_STATUS kdispGetRgScanLock_v02_01(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 head0, OBJGPU *pPeerGpu, NvU32 head1, NvBool *pMasterScanLock, NvU32 *pMasterScanLockPin, NvBool *pSlaveScanLock, NvU32 *pSlaveScanLockPin); + +static inline NV_STATUS kdispGetRgScanLock_92bfc3(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 head0, OBJGPU *pPeerGpu, NvU32 head1, NvBool *pMasterScanLock, NvU32 *pMasterScanLockPin, NvBool *pSlaveScanLock, NvU32 *pSlaveScanLockPin) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kdispGetRgScanLock_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 head0, OBJGPU *pPeerGpu, NvU32 head1, NvBool *pMasterScanLock, NvU32 *pMasterScanLockPin, NvBool *pSlaveScanLock, NvU32 *pSlaveScanLockPin) { + return pKernelDisplay->__kdispGetRgScanLock__(pGpu, pKernelDisplay, head0, pPeerGpu, head1, pMasterScanLock, pMasterScanLockPin, pSlaveScanLock, pSlaveScanLockPin); +} + +NV_STATUS kdispDetectSliLink_v04_00(struct KernelDisplay *pKernelDisplay, OBJGPU *pParentGpu, OBJGPU *pChildGpu, NvU32 ParentDrPort, NvU32 ChildDrPort); + +static inline NV_STATUS kdispDetectSliLink_92bfc3(struct KernelDisplay *pKernelDisplay, OBJGPU *pParentGpu, OBJGPU *pChildGpu, NvU32 ParentDrPort, NvU32 ChildDrPort) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kdispDetectSliLink_DISPATCH(struct KernelDisplay *pKernelDisplay, OBJGPU *pParentGpu, OBJGPU *pChildGpu, NvU32 ParentDrPort, NvU32 ChildDrPort) { + return pKernelDisplay->__kdispDetectSliLink__(pKernelDisplay, pParentGpu, pChildGpu, ParentDrPort, ChildDrPort); } static inline NV_STATUS kdispServiceNotificationInterrupt_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pIntrService, IntrServiceServiceNotificationInterruptArguments *pParams) { @@ -655,18 +667,6 @@ static inline NV_STATUS kdispStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct return pEngstate->__kdispStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kdispGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelDisplay *pEngstate, void *pTunableState) { - return pEngstate->__kdispGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kdispCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelDisplay *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kdispCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kdispFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelDisplay *pEngstate, void *pTunableState) { - pEngstate->__kdispFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kdispClearInterrupt_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pIntrService, IntrServiceClearInterruptArguments *pParams) { return pIntrService->__kdispClearInterrupt__(pGpu, pIntrService, pParams); } @@ -675,14 +675,6 @@ static inline NV_STATUS kdispStatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelD return pEngstate->__kdispStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS kdispAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelDisplay *pEngstate, void **ppTunableState) { - return pEngstate->__kdispAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kdispSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelDisplay *pEngstate, void *pTunableState) { - return pEngstate->__kdispSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kdispIsPresent_DISPATCH(POBJGPU pGpu, struct KernelDisplay *pEngstate) { return pEngstate->__kdispIsPresent__(pGpu, pEngstate); } diff --git a/src/nvidia/generated/g_kern_fsp_nvoc.c b/src/nvidia/generated/g_kern_fsp_nvoc.c index 111578c8b..07da73a8c 100644 --- a/src/nvidia/generated/g_kern_fsp_nvoc.c +++ b/src/nvidia/generated/g_kern_fsp_nvoc.c @@ -74,10 +74,6 @@ static void __nvoc_thunk_KernelFsp_engstateStateDestroy(struct OBJGPU *pGpu, str kfspStateDestroy(pGpu, (struct KernelFsp *)(((unsigned char *)pKernelFsp) - __nvoc_rtti_KernelFsp_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfspReconcileTunableState(POBJGPU pGpu, struct KernelFsp *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfspStateLoad(POBJGPU pGpu, struct KernelFsp *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset), arg0); } @@ -118,30 +114,10 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfspStatePreInitUnlocked(POBJGPU pGpu, return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfspGetTunableState(POBJGPU pGpu, struct KernelFsp *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfspCompareTunableState(POBJGPU pGpu, struct KernelFsp *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kfspFreeTunableState(POBJGPU pGpu, struct KernelFsp *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfspStatePostLoad(POBJGPU pGpu, struct KernelFsp *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfspAllocTunableState(POBJGPU pGpu, struct KernelFsp *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfspSetTunableState(POBJGPU pGpu, struct KernelFsp *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_kfspIsPresent(POBJGPU pGpu, struct KernelFsp *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFsp_OBJENGSTATE.offset)); } @@ -441,12 +417,20 @@ static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner * pThis->__kfspCheckGspSecureScratch__ = &kfspCheckGspSecureScratch_491d52; } + // Hal function -- kfspWaitForGspTargetMaskReleased + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfspWaitForGspTargetMaskReleased__ = &kfspWaitForGspTargetMaskReleased_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__kfspWaitForGspTargetMaskReleased__ = &kfspWaitForGspTargetMaskReleased_395e98; + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelFsp_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_KernelFsp_engstateStateDestroy; - pThis->__kfspReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kfspReconcileTunableState; - pThis->__kfspStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kfspStateLoad; pThis->__kfspStateUnload__ = &__nvoc_thunk_OBJENGSTATE_kfspStateUnload; @@ -467,18 +451,8 @@ static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner * pThis->__kfspStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kfspStatePreInitUnlocked; - pThis->__kfspGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kfspGetTunableState; - - pThis->__kfspCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kfspCompareTunableState; - - pThis->__kfspFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kfspFreeTunableState; - pThis->__kfspStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kfspStatePostLoad; - pThis->__kfspAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kfspAllocTunableState; - - pThis->__kfspSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kfspSetTunableState; - pThis->__kfspIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kfspIsPresent; } @@ -501,13 +475,16 @@ NV_STATUS __nvoc_objCreate_KernelFsp(KernelFsp **ppThis, Dynamic *pParent, NvU32 KernelFsp *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelFsp)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelFsp), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelFsp)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelFsp); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -527,11 +504,17 @@ NV_STATUS __nvoc_objCreate_KernelFsp(KernelFsp **ppThis, Dynamic *pParent, NvU32 if (status != NV_OK) goto __nvoc_objCreate_KernelFsp_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelFsp_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelFsp)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kern_fsp_nvoc.h b/src/nvidia/generated/g_kern_fsp_nvoc.h index 0fa2171ee..be7c0ae43 100644 --- a/src/nvidia/generated/g_kern_fsp_nvoc.h +++ b/src/nvidia/generated/g_kern_fsp_nvoc.h @@ -153,7 +153,7 @@ struct KernelFsp { void (*__kfspGetQueueHeadTail__)(struct OBJGPU *, struct KernelFsp *, NvU32 *, NvU32 *); void (*__kfspUpdateMsgQueueHeadTail__)(struct OBJGPU *, struct KernelFsp *, NvU32, NvU32); void (*__kfspGetMsgQueueHeadTail__)(struct OBJGPU *, struct KernelFsp *, NvU32 *, NvU32 *); - NvU8 (*__kfspNvdmToSeid__)(POBJGPU, struct KernelFsp *, NvU8); + NvU8 (*__kfspNvdmToSeid__)(struct OBJGPU *, struct KernelFsp *, NvU8); NvU32 (*__kfspCreateMctpHeader__)(struct OBJGPU *, struct KernelFsp *, NvU8, NvU8, NvU8, NvU8); NvU32 (*__kfspCreateNvdmHeader__)(struct OBJGPU *, struct KernelFsp *, NvU32); NV_STATUS (*__kfspWriteToEmem__)(struct OBJGPU *, struct KernelFsp *, NvU8 *, NvU32); @@ -166,7 +166,7 @@ struct KernelFsp { NV_STATUS (*__kfspErrorCode2NvStatusMap__)(struct OBJGPU *, struct KernelFsp *, NvU32); NvU64 (*__kfspGetExtraReservedMemorySize__)(struct OBJGPU *, struct KernelFsp *); NvBool (*__kfspCheckGspSecureScratch__)(struct OBJGPU *, struct KernelFsp *); - NV_STATUS (*__kfspReconcileTunableState__)(POBJGPU, struct KernelFsp *, void *); + NV_STATUS (*__kfspWaitForGspTargetMaskReleased__)(struct OBJGPU *, struct KernelFsp *); NV_STATUS (*__kfspStateLoad__)(POBJGPU, struct KernelFsp *, NvU32); NV_STATUS (*__kfspStateUnload__)(POBJGPU, struct KernelFsp *, NvU32); NV_STATUS (*__kfspStateInitLocked__)(POBJGPU, struct KernelFsp *); @@ -177,19 +177,13 @@ struct KernelFsp { void (*__kfspInitMissing__)(POBJGPU, struct KernelFsp *); NV_STATUS (*__kfspStatePreInitLocked__)(POBJGPU, struct KernelFsp *); NV_STATUS (*__kfspStatePreInitUnlocked__)(POBJGPU, struct KernelFsp *); - NV_STATUS (*__kfspGetTunableState__)(POBJGPU, struct KernelFsp *, void *); - NV_STATUS (*__kfspCompareTunableState__)(POBJGPU, struct KernelFsp *, void *, void *); - void (*__kfspFreeTunableState__)(POBJGPU, struct KernelFsp *, void *); NV_STATUS (*__kfspStatePostLoad__)(POBJGPU, struct KernelFsp *, NvU32); - NV_STATUS (*__kfspAllocTunableState__)(POBJGPU, struct KernelFsp *, void **); - NV_STATUS (*__kfspSetTunableState__)(POBJGPU, struct KernelFsp *, void *); NvBool (*__kfspIsPresent__)(POBJGPU, struct KernelFsp *); NvBool PDB_PROP_KFSP_BOOT_COMMAND_OK; NvBool PDB_PROP_KFSP_GSP_MODE_GSPRM; NvBool PDB_PROP_KFSP_DISABLE_FRTS_SYSMEM; NvBool PDB_PROP_KFSP_DISABLE_FRTS_VIDMEM; NvBool PDB_PROP_KFSP_DISABLE_GSPFMC; - NvBool PDB_PROP_KFSP_HULK_EXECUTED; MEMORY_DESCRIPTOR *pSysmemFrtsMemdesc; MEMORY_DESCRIPTOR *pVidmemFrtsMemdesc; MEMORY_DESCRIPTOR *pGspFmcMemdesc; @@ -227,8 +221,6 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelFsp; #define PDB_PROP_KFSP_IS_MISSING_BASE_NAME PDB_PROP_ENGSTATE_IS_MISSING #define PDB_PROP_KFSP_GSP_MODE_GSPRM_BASE_CAST #define PDB_PROP_KFSP_GSP_MODE_GSPRM_BASE_NAME PDB_PROP_KFSP_GSP_MODE_GSPRM -#define PDB_PROP_KFSP_HULK_EXECUTED_BASE_CAST -#define PDB_PROP_KFSP_HULK_EXECUTED_BASE_NAME PDB_PROP_KFSP_HULK_EXECUTED #define PDB_PROP_KFSP_BOOT_COMMAND_OK_BASE_CAST #define PDB_PROP_KFSP_BOOT_COMMAND_OK_BASE_NAME PDB_PROP_KFSP_BOOT_COMMAND_OK #define PDB_PROP_KFSP_DISABLE_FRTS_SYSMEM_BASE_CAST @@ -293,7 +285,8 @@ NV_STATUS __nvoc_objCreate_KernelFsp(KernelFsp**, Dynamic*, NvU32); #define kfspGetExtraReservedMemorySize_HAL(pGpu, pKernelFsp) kfspGetExtraReservedMemorySize_DISPATCH(pGpu, pKernelFsp) #define kfspCheckGspSecureScratch(pGpu, pKernelFsp) kfspCheckGspSecureScratch_DISPATCH(pGpu, pKernelFsp) #define kfspCheckGspSecureScratch_HAL(pGpu, pKernelFsp) kfspCheckGspSecureScratch_DISPATCH(pGpu, pKernelFsp) -#define kfspReconcileTunableState(pGpu, pEngstate, pTunableState) kfspReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) +#define kfspWaitForGspTargetMaskReleased(pGpu, pKernelFsp) kfspWaitForGspTargetMaskReleased_DISPATCH(pGpu, pKernelFsp) +#define kfspWaitForGspTargetMaskReleased_HAL(pGpu, pKernelFsp) kfspWaitForGspTargetMaskReleased_DISPATCH(pGpu, pKernelFsp) #define kfspStateLoad(pGpu, pEngstate, arg0) kfspStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kfspStateUnload(pGpu, pEngstate, arg0) kfspStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define kfspStateInitLocked(pGpu, pEngstate) kfspStateInitLocked_DISPATCH(pGpu, pEngstate) @@ -304,12 +297,7 @@ NV_STATUS __nvoc_objCreate_KernelFsp(KernelFsp**, Dynamic*, NvU32); #define kfspInitMissing(pGpu, pEngstate) kfspInitMissing_DISPATCH(pGpu, pEngstate) #define kfspStatePreInitLocked(pGpu, pEngstate) kfspStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kfspStatePreInitUnlocked(pGpu, pEngstate) kfspStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kfspGetTunableState(pGpu, pEngstate, pTunableState) kfspGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kfspCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kfspCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kfspFreeTunableState(pGpu, pEngstate, pTunableState) kfspFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kfspStatePostLoad(pGpu, pEngstate, arg0) kfspStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define kfspAllocTunableState(pGpu, pEngstate, ppTunableState) kfspAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kfspSetTunableState(pGpu, pEngstate, pTunableState) kfspSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kfspIsPresent(pGpu, pEngstate) kfspIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS kfspConstructEngine_IMPL(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, ENGDESCRIPTOR arg0); @@ -455,13 +443,13 @@ static inline void kfspGetMsgQueueHeadTail_DISPATCH(struct OBJGPU *pGpu, struct pKernelFsp->__kfspGetMsgQueueHeadTail__(pGpu, pKernelFsp, pMsgqHead, pMsgqTail); } -NvU8 kfspNvdmToSeid_GH100(POBJGPU pGpu, struct KernelFsp *pKernelFsp, NvU8 nvdmType); +NvU8 kfspNvdmToSeid_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 nvdmType); -static inline NvU8 kfspNvdmToSeid_b2b553(POBJGPU pGpu, struct KernelFsp *pKernelFsp, NvU8 nvdmType) { +static inline NvU8 kfspNvdmToSeid_b2b553(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 nvdmType) { return 0; } -static inline NvU8 kfspNvdmToSeid_DISPATCH(POBJGPU pGpu, struct KernelFsp *pKernelFsp, NvU8 nvdmType) { +static inline NvU8 kfspNvdmToSeid_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp, NvU8 nvdmType) { return pKernelFsp->__kfspNvdmToSeid__(pGpu, pKernelFsp, nvdmType); } @@ -585,8 +573,14 @@ static inline NvBool kfspCheckGspSecureScratch_DISPATCH(struct OBJGPU *pGpu, str return pKernelFsp->__kfspCheckGspSecureScratch__(pGpu, pKernelFsp); } -static inline NV_STATUS kfspReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate, void *pTunableState) { - return pEngstate->__kfspReconcileTunableState__(pGpu, pEngstate, pTunableState); +NV_STATUS kfspWaitForGspTargetMaskReleased_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp); + +static inline NV_STATUS kfspWaitForGspTargetMaskReleased_395e98(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kfspWaitForGspTargetMaskReleased_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + return pKernelFsp->__kfspWaitForGspTargetMaskReleased__(pGpu, pKernelFsp); } static inline NV_STATUS kfspStateLoad_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate, NvU32 arg0) { @@ -629,30 +623,10 @@ static inline NV_STATUS kfspStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct K return pEngstate->__kfspStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kfspGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate, void *pTunableState) { - return pEngstate->__kfspGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kfspCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kfspCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kfspFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate, void *pTunableState) { - pEngstate->__kfspFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kfspStatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate, NvU32 arg0) { return pEngstate->__kfspStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS kfspAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate, void **ppTunableState) { - return pEngstate->__kfspAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kfspSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate, void *pTunableState) { - return pEngstate->__kfspSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kfspIsPresent_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate) { return pEngstate->__kfspIsPresent__(pGpu, pEngstate); } diff --git a/src/nvidia/generated/g_kern_gmmu_nvoc.c b/src/nvidia/generated/g_kern_gmmu_nvoc.c index 01dba5bb1..73d7016db 100644 --- a/src/nvidia/generated/g_kern_gmmu_nvoc.c +++ b/src/nvidia/generated/g_kern_gmmu_nvoc.c @@ -95,7 +95,7 @@ static void __nvoc_thunk_KernelGmmu_engstateStateDestroy(OBJGPU *pGpu, struct OB kgmmuStateDestroy(pGpu, (struct KernelGmmu *)(((unsigned char *)pKernelGmmu) - __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset)); } -static void __nvoc_thunk_KernelGmmu_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pKernelGmmu, IntrServiceRecord arg0[163]) { +static void __nvoc_thunk_KernelGmmu_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pKernelGmmu, IntrServiceRecord arg0[166]) { kgmmuRegisterIntrService(pGpu, (struct KernelGmmu *)(((unsigned char *)pKernelGmmu) - __nvoc_rtti_KernelGmmu_IntrService.offset), arg0); } @@ -103,10 +103,6 @@ static NvU32 __nvoc_thunk_KernelGmmu_intrservServiceInterrupt(OBJGPU *pGpu, stru return kgmmuServiceInterrupt(pGpu, (struct KernelGmmu *)(((unsigned char *)pKernelGmmu) - __nvoc_rtti_KernelGmmu_IntrService.offset), pParams); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgmmuReconcileTunableState(POBJGPU pGpu, struct KernelGmmu *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgmmuStateLoad(POBJGPU pGpu, struct KernelGmmu *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset), arg0); } @@ -143,30 +139,10 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgmmuStatePreInitUnlocked(POBJGPU pGpu return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgmmuGetTunableState(POBJGPU pGpu, struct KernelGmmu *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgmmuCompareTunableState(POBJGPU pGpu, struct KernelGmmu *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kgmmuFreeTunableState(POBJGPU pGpu, struct KernelGmmu *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_IntrService_kgmmuClearInterrupt(struct OBJGPU *pGpu, struct KernelGmmu *pIntrService, IntrServiceClearInterruptArguments *pParams) { return intrservClearInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_KernelGmmu_IntrService.offset), pParams); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgmmuAllocTunableState(POBJGPU pGpu, struct KernelGmmu *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgmmuSetTunableState(POBJGPU pGpu, struct KernelGmmu *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_kgmmuIsPresent(POBJGPU pGpu, struct KernelGmmu *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset)); } @@ -452,6 +428,46 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner pThis->__kgmmuTranslatePdePcfFromHw__ = &kgmmuTranslatePdePcfFromHw_56cd7a; } + // Hal function -- kgmmuGetFaultRegisterMappings + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__kgmmuGetFaultRegisterMappings__ = &kgmmuGetFaultRegisterMappings_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuGetFaultRegisterMappings__ = &kgmmuGetFaultRegisterMappings_GH100; + } + + // Hal function -- kgmmuIssueReplayableFaultBufferFlush + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuIssueReplayableFaultBufferFlush__ = &kgmmuIssueReplayableFaultBufferFlush_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__kgmmuIssueReplayableFaultBufferFlush__ = &kgmmuIssueReplayableFaultBufferFlush_46f6a7; + } + + // Hal function -- kgmmuFaultBufferAllocSharedMemory + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuFaultBufferAllocSharedMemory__ = &kgmmuFaultBufferAllocSharedMemory_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__kgmmuFaultBufferAllocSharedMemory__ = &kgmmuFaultBufferAllocSharedMemory_56cd7a; + } + + // Hal function -- kgmmuFaultBufferFreeSharedMemory + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuFaultBufferFreeSharedMemory__ = &kgmmuFaultBufferFreeSharedMemory_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__kgmmuFaultBufferFreeSharedMemory__ = &kgmmuFaultBufferFreeSharedMemory_b3696a; + } + // Hal function -- kgmmuSetupWarForBug2720120 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ { @@ -486,8 +502,6 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner pThis->__nvoc_base_IntrService.__intrservServiceInterrupt__ = &__nvoc_thunk_KernelGmmu_intrservServiceInterrupt; - pThis->__kgmmuReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgmmuReconcileTunableState; - pThis->__kgmmuStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kgmmuStateLoad; pThis->__kgmmuStateUnload__ = &__nvoc_thunk_OBJENGSTATE_kgmmuStateUnload; @@ -506,18 +520,8 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner pThis->__kgmmuStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kgmmuStatePreInitUnlocked; - pThis->__kgmmuGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgmmuGetTunableState; - - pThis->__kgmmuCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgmmuCompareTunableState; - - pThis->__kgmmuFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgmmuFreeTunableState; - pThis->__kgmmuClearInterrupt__ = &__nvoc_thunk_IntrService_kgmmuClearInterrupt; - pThis->__kgmmuAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgmmuAllocTunableState; - - pThis->__kgmmuSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgmmuSetTunableState; - pThis->__kgmmuIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kgmmuIsPresent; } @@ -543,13 +547,16 @@ NV_STATUS __nvoc_objCreate_KernelGmmu(KernelGmmu **ppThis, Dynamic *pParent, NvU KernelGmmu *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelGmmu)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelGmmu), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelGmmu)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelGmmu); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -569,11 +576,17 @@ NV_STATUS __nvoc_objCreate_KernelGmmu(KernelGmmu **ppThis, Dynamic *pParent, NvU if (status != NV_OK) goto __nvoc_objCreate_KernelGmmu_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelGmmu_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelGmmu)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kern_gmmu_nvoc.h b/src/nvidia/generated/g_kern_gmmu_nvoc.h index 170f744d5..673a4923a 100644 --- a/src/nvidia/generated/g_kern_gmmu_nvoc.h +++ b/src/nvidia/generated/g_kern_gmmu_nvoc.h @@ -145,6 +145,25 @@ struct HW_FAULT_BUFFER NvU32 faultBufferSize; }; +/*! + * This structure holds information shared between CPU-RM + * and GSP-RM + */ +typedef struct +{ + /*! + * The value updated by GSP-RM to notify CPU-RM that + * a successful flush has happened + */ + NvU32 flushBufferSeqNum; + + /*! + * The GET index of replayable shadow buffer. This + * is updated by UVM driver and read by GSP-RM + */ + NvU32 swGetIndex; +} FAULT_BUFFER_SHARED_MEMORY; + /*! * This structure holds information about the client shadow fault buffer. */ @@ -185,6 +204,16 @@ typedef struct GMMU_FAULT_BUFFER_PAGE *pBufferPages; NvU32 numBufferPages; + + /*! + * Used only by the replayable fault buffer. Memory descriptor used to + * describe shared memory b/w CPU-RM and GSP-RM. + */ + MEMORY_DESCRIPTOR *pFaultBufferSharedMemDesc; + + NvP64 pFaultBufferSharedMemoryAddress; + + NvP64 pFaultBufferSharedMemoryPriv; } GMMU_CLIENT_SHADOW_FAULT_BUFFER; /*! @@ -209,9 +238,11 @@ struct GMMU_FAULT_BUFFER /*! * Client shadow fault buffer data and pointer protected by gpu locks. + * Client may allocate upto 2 shadow buffers one each for replayable and + * non-replayable faults */ - GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuffer; - GMMU_CLIENT_SHADOW_FAULT_BUFFER clientShadowFaultBuffer; + GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuffer[NUM_FAULT_BUFFERS]; + GMMU_CLIENT_SHADOW_FAULT_BUFFER clientShadowFaultBuffer[NUM_FAULT_BUFFERS]; /*! * SpinLock to protect shadow buffer pointers @@ -294,9 +325,12 @@ struct KernelGmmu { NV_STATUS (*__kgmmuTranslatePtePcfFromHw__)(struct KernelGmmu *, NvU32, NvBool, NvU32 *); NV_STATUS (*__kgmmuTranslatePdePcfFromSw__)(struct KernelGmmu *, NvU32, NvU32 *); NV_STATUS (*__kgmmuTranslatePdePcfFromHw__)(struct KernelGmmu *, NvU32, GMMU_APERTURE, NvU32 *); + NV_STATUS (*__kgmmuGetFaultRegisterMappings__)(OBJGPU *, struct KernelGmmu *, NvU32, NvP64 *, NvP64 *, NvP64 *, NvP64 *, NvP64 *, NvP64 *, NvU32 *, NvP64 *); + NV_STATUS (*__kgmmuIssueReplayableFaultBufferFlush__)(OBJGPU *, struct KernelGmmu *); + NV_STATUS (*__kgmmuFaultBufferAllocSharedMemory__)(OBJGPU *, struct KernelGmmu *, FAULT_BUFFER_TYPE); + void (*__kgmmuFaultBufferFreeSharedMemory__)(OBJGPU *, struct KernelGmmu *, FAULT_BUFFER_TYPE); NV_STATUS (*__kgmmuSetupWarForBug2720120__)(struct KernelGmmu *, GMMU_FMT_FAMILY *); NvU32 (*__kgmmuGetGraphicsEngineId__)(struct KernelGmmu *); - NV_STATUS (*__kgmmuReconcileTunableState__)(POBJGPU, struct KernelGmmu *, void *); NV_STATUS (*__kgmmuStateLoad__)(POBJGPU, struct KernelGmmu *, NvU32); NV_STATUS (*__kgmmuStateUnload__)(POBJGPU, struct KernelGmmu *, NvU32); NV_STATUS (*__kgmmuServiceNotificationInterrupt__)(struct OBJGPU *, struct KernelGmmu *, IntrServiceServiceNotificationInterruptArguments *); @@ -306,12 +340,7 @@ struct KernelGmmu { void (*__kgmmuInitMissing__)(POBJGPU, struct KernelGmmu *); NV_STATUS (*__kgmmuStatePreInitLocked__)(POBJGPU, struct KernelGmmu *); NV_STATUS (*__kgmmuStatePreInitUnlocked__)(POBJGPU, struct KernelGmmu *); - NV_STATUS (*__kgmmuGetTunableState__)(POBJGPU, struct KernelGmmu *, void *); - NV_STATUS (*__kgmmuCompareTunableState__)(POBJGPU, struct KernelGmmu *, void *, void *); - void (*__kgmmuFreeTunableState__)(POBJGPU, struct KernelGmmu *, void *); NvBool (*__kgmmuClearInterrupt__)(struct OBJGPU *, struct KernelGmmu *, IntrServiceClearInterruptArguments *); - NV_STATUS (*__kgmmuAllocTunableState__)(POBJGPU, struct KernelGmmu *, void **); - NV_STATUS (*__kgmmuSetTunableState__)(POBJGPU, struct KernelGmmu *, void *); NvBool (*__kgmmuIsPresent__)(POBJGPU, struct KernelGmmu *); NvBool PDB_PROP_KGMMU_SYSMEM_FAULT_BUFFER_GPU_UNCACHED; NvBool PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED; @@ -372,9 +401,12 @@ struct KernelGmmu_PRIVATE { NV_STATUS (*__kgmmuTranslatePtePcfFromHw__)(struct KernelGmmu *, NvU32, NvBool, NvU32 *); NV_STATUS (*__kgmmuTranslatePdePcfFromSw__)(struct KernelGmmu *, NvU32, NvU32 *); NV_STATUS (*__kgmmuTranslatePdePcfFromHw__)(struct KernelGmmu *, NvU32, GMMU_APERTURE, NvU32 *); + NV_STATUS (*__kgmmuGetFaultRegisterMappings__)(OBJGPU *, struct KernelGmmu *, NvU32, NvP64 *, NvP64 *, NvP64 *, NvP64 *, NvP64 *, NvP64 *, NvU32 *, NvP64 *); + NV_STATUS (*__kgmmuIssueReplayableFaultBufferFlush__)(OBJGPU *, struct KernelGmmu *); + NV_STATUS (*__kgmmuFaultBufferAllocSharedMemory__)(OBJGPU *, struct KernelGmmu *, FAULT_BUFFER_TYPE); + void (*__kgmmuFaultBufferFreeSharedMemory__)(OBJGPU *, struct KernelGmmu *, FAULT_BUFFER_TYPE); NV_STATUS (*__kgmmuSetupWarForBug2720120__)(struct KernelGmmu *, GMMU_FMT_FAMILY *); NvU32 (*__kgmmuGetGraphicsEngineId__)(struct KernelGmmu *); - NV_STATUS (*__kgmmuReconcileTunableState__)(POBJGPU, struct KernelGmmu *, void *); NV_STATUS (*__kgmmuStateLoad__)(POBJGPU, struct KernelGmmu *, NvU32); NV_STATUS (*__kgmmuStateUnload__)(POBJGPU, struct KernelGmmu *, NvU32); NV_STATUS (*__kgmmuServiceNotificationInterrupt__)(struct OBJGPU *, struct KernelGmmu *, IntrServiceServiceNotificationInterruptArguments *); @@ -384,12 +416,7 @@ struct KernelGmmu_PRIVATE { void (*__kgmmuInitMissing__)(POBJGPU, struct KernelGmmu *); NV_STATUS (*__kgmmuStatePreInitLocked__)(POBJGPU, struct KernelGmmu *); NV_STATUS (*__kgmmuStatePreInitUnlocked__)(POBJGPU, struct KernelGmmu *); - NV_STATUS (*__kgmmuGetTunableState__)(POBJGPU, struct KernelGmmu *, void *); - NV_STATUS (*__kgmmuCompareTunableState__)(POBJGPU, struct KernelGmmu *, void *, void *); - void (*__kgmmuFreeTunableState__)(POBJGPU, struct KernelGmmu *, void *); NvBool (*__kgmmuClearInterrupt__)(struct OBJGPU *, struct KernelGmmu *, IntrServiceClearInterruptArguments *); - NV_STATUS (*__kgmmuAllocTunableState__)(POBJGPU, struct KernelGmmu *, void **); - NV_STATUS (*__kgmmuSetTunableState__)(POBJGPU, struct KernelGmmu *, void *); NvBool (*__kgmmuIsPresent__)(POBJGPU, struct KernelGmmu *); NvBool PDB_PROP_KGMMU_SYSMEM_FAULT_BUFFER_GPU_UNCACHED; NvBool PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED; @@ -494,11 +521,18 @@ NV_STATUS __nvoc_objCreate_KernelGmmu(KernelGmmu**, Dynamic*, NvU32); #define kgmmuTranslatePdePcfFromSw_HAL(pKernelGmmu, arg0, arg1) kgmmuTranslatePdePcfFromSw_DISPATCH(pKernelGmmu, arg0, arg1) #define kgmmuTranslatePdePcfFromHw(pKernelGmmu, arg0, arg1, arg2) kgmmuTranslatePdePcfFromHw_DISPATCH(pKernelGmmu, arg0, arg1, arg2) #define kgmmuTranslatePdePcfFromHw_HAL(pKernelGmmu, arg0, arg1, arg2) kgmmuTranslatePdePcfFromHw_DISPATCH(pKernelGmmu, arg0, arg1, arg2) +#define kgmmuGetFaultRegisterMappings(pGpu, pKernelGmmu, index, pFaultBufferGet, pFaultBufferPut, pFaultBufferInfo, faultIntr, faultIntrSet, faultIntrClear, faultMask, pPrefetchCtrl) kgmmuGetFaultRegisterMappings_DISPATCH(pGpu, pKernelGmmu, index, pFaultBufferGet, pFaultBufferPut, pFaultBufferInfo, faultIntr, faultIntrSet, faultIntrClear, faultMask, pPrefetchCtrl) +#define kgmmuGetFaultRegisterMappings_HAL(pGpu, pKernelGmmu, index, pFaultBufferGet, pFaultBufferPut, pFaultBufferInfo, faultIntr, faultIntrSet, faultIntrClear, faultMask, pPrefetchCtrl) kgmmuGetFaultRegisterMappings_DISPATCH(pGpu, pKernelGmmu, index, pFaultBufferGet, pFaultBufferPut, pFaultBufferInfo, faultIntr, faultIntrSet, faultIntrClear, faultMask, pPrefetchCtrl) +#define kgmmuIssueReplayableFaultBufferFlush(pGpu, pKernelGmmu) kgmmuIssueReplayableFaultBufferFlush_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuIssueReplayableFaultBufferFlush_HAL(pGpu, pKernelGmmu) kgmmuIssueReplayableFaultBufferFlush_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuFaultBufferAllocSharedMemory(pGpu, pKernelGmmu, arg0) kgmmuFaultBufferAllocSharedMemory_DISPATCH(pGpu, pKernelGmmu, arg0) +#define kgmmuFaultBufferAllocSharedMemory_HAL(pGpu, pKernelGmmu, arg0) kgmmuFaultBufferAllocSharedMemory_DISPATCH(pGpu, pKernelGmmu, arg0) +#define kgmmuFaultBufferFreeSharedMemory(pGpu, pKernelGmmu, arg0) kgmmuFaultBufferFreeSharedMemory_DISPATCH(pGpu, pKernelGmmu, arg0) +#define kgmmuFaultBufferFreeSharedMemory_HAL(pGpu, pKernelGmmu, arg0) kgmmuFaultBufferFreeSharedMemory_DISPATCH(pGpu, pKernelGmmu, arg0) #define kgmmuSetupWarForBug2720120(pKernelGmmu, pFam) kgmmuSetupWarForBug2720120_DISPATCH(pKernelGmmu, pFam) #define kgmmuSetupWarForBug2720120_HAL(pKernelGmmu, pFam) kgmmuSetupWarForBug2720120_DISPATCH(pKernelGmmu, pFam) #define kgmmuGetGraphicsEngineId(pKernelGmmu) kgmmuGetGraphicsEngineId_DISPATCH(pKernelGmmu) #define kgmmuGetGraphicsEngineId_HAL(pKernelGmmu) kgmmuGetGraphicsEngineId_DISPATCH(pKernelGmmu) -#define kgmmuReconcileTunableState(pGpu, pEngstate, pTunableState) kgmmuReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kgmmuStateLoad(pGpu, pEngstate, arg0) kgmmuStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kgmmuStateUnload(pGpu, pEngstate, arg0) kgmmuStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define kgmmuServiceNotificationInterrupt(pGpu, pIntrService, pParams) kgmmuServiceNotificationInterrupt_DISPATCH(pGpu, pIntrService, pParams) @@ -508,12 +542,7 @@ NV_STATUS __nvoc_objCreate_KernelGmmu(KernelGmmu**, Dynamic*, NvU32); #define kgmmuInitMissing(pGpu, pEngstate) kgmmuInitMissing_DISPATCH(pGpu, pEngstate) #define kgmmuStatePreInitLocked(pGpu, pEngstate) kgmmuStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kgmmuStatePreInitUnlocked(pGpu, pEngstate) kgmmuStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kgmmuGetTunableState(pGpu, pEngstate, pTunableState) kgmmuGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kgmmuCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kgmmuCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kgmmuFreeTunableState(pGpu, pEngstate, pTunableState) kgmmuFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kgmmuClearInterrupt(pGpu, pIntrService, pParams) kgmmuClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) -#define kgmmuAllocTunableState(pGpu, pEngstate, ppTunableState) kgmmuAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kgmmuSetTunableState(pGpu, pEngstate, pTunableState) kgmmuSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kgmmuIsPresent(pGpu, pEngstate) kgmmuIsPresent_DISPATCH(pGpu, pEngstate) NvU32 kgmmuGetMaxBigPageSize_GM107(struct KernelGmmu *pKernelGmmu); @@ -735,20 +764,6 @@ static inline void kgmmuDetermineMaxVASize(OBJGPU *pGpu, struct KernelGmmu *pKer #define kgmmuDetermineMaxVASize_HAL(pGpu, pKernelGmmu) kgmmuDetermineMaxVASize(pGpu, pKernelGmmu) -NV_STATUS kgmmuGetFaultRegisterMappings_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvP64 *pFaultBufferGet, NvP64 *pFaultBufferPut, NvP64 *pFaultBufferInfo, NvP64 *faultIntr, NvP64 *faultIntrSet, NvP64 *faultIntrClear, NvU32 *faultMask, NvP64 *pPrefetchCtrl); - - -#ifdef __nvoc_kern_gmmu_h_disabled -static inline NV_STATUS kgmmuGetFaultRegisterMappings(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvP64 *pFaultBufferGet, NvP64 *pFaultBufferPut, NvP64 *pFaultBufferInfo, NvP64 *faultIntr, NvP64 *faultIntrSet, NvP64 *faultIntrClear, NvU32 *faultMask, NvP64 *pPrefetchCtrl) { - NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_gmmu_h_disabled -#define kgmmuGetFaultRegisterMappings(pGpu, pKernelGmmu, index, pFaultBufferGet, pFaultBufferPut, pFaultBufferInfo, faultIntr, faultIntrSet, faultIntrClear, faultMask, pPrefetchCtrl) kgmmuGetFaultRegisterMappings_TU102(pGpu, pKernelGmmu, index, pFaultBufferGet, pFaultBufferPut, pFaultBufferInfo, faultIntr, faultIntrSet, faultIntrClear, faultMask, pPrefetchCtrl) -#endif //__nvoc_kern_gmmu_h_disabled - -#define kgmmuGetFaultRegisterMappings_HAL(pGpu, pKernelGmmu, index, pFaultBufferGet, pFaultBufferPut, pFaultBufferInfo, faultIntr, faultIntrSet, faultIntrClear, faultMask, pPrefetchCtrl) kgmmuGetFaultRegisterMappings(pGpu, pKernelGmmu, index, pFaultBufferGet, pFaultBufferPut, pFaultBufferInfo, faultIntr, faultIntrSet, faultIntrClear, faultMask, pPrefetchCtrl) - const char *kgmmuGetFaultTypeString_GP100(struct KernelGmmu *pKernelGmmu, NvU32 faultType); @@ -888,33 +903,33 @@ static inline NvBool kgmmuIsNonReplayableFaultPending(OBJGPU *pGpu, struct Kerne #define kgmmuIsNonReplayableFaultPending_HAL(pGpu, pKernelGmmu, arg0) kgmmuIsNonReplayableFaultPending(pGpu, pKernelGmmu, arg0) -NV_STATUS kgmmuClientShadowFaultBufferAlloc_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); +NV_STATUS kgmmuClientShadowFaultBufferAlloc_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0); #ifdef __nvoc_kern_gmmu_h_disabled -static inline NV_STATUS kgmmuClientShadowFaultBufferAlloc(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { +static inline NV_STATUS kgmmuClientShadowFaultBufferAlloc(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kern_gmmu_h_disabled -#define kgmmuClientShadowFaultBufferAlloc(pGpu, pKernelGmmu) kgmmuClientShadowFaultBufferAlloc_GV100(pGpu, pKernelGmmu) +#define kgmmuClientShadowFaultBufferAlloc(pGpu, pKernelGmmu, arg0) kgmmuClientShadowFaultBufferAlloc_GV100(pGpu, pKernelGmmu, arg0) #endif //__nvoc_kern_gmmu_h_disabled -#define kgmmuClientShadowFaultBufferAlloc_HAL(pGpu, pKernelGmmu) kgmmuClientShadowFaultBufferAlloc(pGpu, pKernelGmmu) +#define kgmmuClientShadowFaultBufferAlloc_HAL(pGpu, pKernelGmmu, arg0) kgmmuClientShadowFaultBufferAlloc(pGpu, pKernelGmmu, arg0) -NV_STATUS kgmmuClientShadowFaultBufferFree_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); +NV_STATUS kgmmuClientShadowFaultBufferFree_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0); #ifdef __nvoc_kern_gmmu_h_disabled -static inline NV_STATUS kgmmuClientShadowFaultBufferFree(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { +static inline NV_STATUS kgmmuClientShadowFaultBufferFree(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kern_gmmu_h_disabled -#define kgmmuClientShadowFaultBufferFree(pGpu, pKernelGmmu) kgmmuClientShadowFaultBufferFree_GV100(pGpu, pKernelGmmu) +#define kgmmuClientShadowFaultBufferFree(pGpu, pKernelGmmu, arg0) kgmmuClientShadowFaultBufferFree_GV100(pGpu, pKernelGmmu, arg0) #endif //__nvoc_kern_gmmu_h_disabled -#define kgmmuClientShadowFaultBufferFree_HAL(pGpu, pKernelGmmu) kgmmuClientShadowFaultBufferFree(pGpu, pKernelGmmu) +#define kgmmuClientShadowFaultBufferFree_HAL(pGpu, pKernelGmmu, arg0) kgmmuClientShadowFaultBufferFree(pGpu, pKernelGmmu, arg0) void kgmmuEncodeSysmemAddrs_GM107(struct KernelGmmu *pKernelGmmu, NvU64 *pAddresses, NvU64 count); @@ -1014,9 +1029,9 @@ static inline void kgmmuStateDestroy_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *p pKernelGmmu->__kgmmuStateDestroy__(pGpu, pKernelGmmu); } -void kgmmuRegisterIntrService_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, IntrServiceRecord arg0[163]); +void kgmmuRegisterIntrService_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, IntrServiceRecord arg0[166]); -static inline void kgmmuRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, IntrServiceRecord arg0[163]) { +static inline void kgmmuRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, IntrServiceRecord arg0[166]) { pKernelGmmu->__kgmmuRegisterIntrService__(pGpu, pKernelGmmu, arg0); } @@ -1167,6 +1182,44 @@ static inline NV_STATUS kgmmuTranslatePdePcfFromHw_DISPATCH(struct KernelGmmu *p return pKernelGmmu->__kgmmuTranslatePdePcfFromHw__(pKernelGmmu, arg0, arg1, arg2); } +NV_STATUS kgmmuGetFaultRegisterMappings_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvP64 *pFaultBufferGet, NvP64 *pFaultBufferPut, NvP64 *pFaultBufferInfo, NvP64 *faultIntr, NvP64 *faultIntrSet, NvP64 *faultIntrClear, NvU32 *faultMask, NvP64 *pPrefetchCtrl); + +NV_STATUS kgmmuGetFaultRegisterMappings_GH100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvP64 *pFaultBufferGet, NvP64 *pFaultBufferPut, NvP64 *pFaultBufferInfo, NvP64 *faultIntr, NvP64 *faultIntrSet, NvP64 *faultIntrClear, NvU32 *faultMask, NvP64 *pPrefetchCtrl); + +static inline NV_STATUS kgmmuGetFaultRegisterMappings_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvP64 *pFaultBufferGet, NvP64 *pFaultBufferPut, NvP64 *pFaultBufferInfo, NvP64 *faultIntr, NvP64 *faultIntrSet, NvP64 *faultIntrClear, NvU32 *faultMask, NvP64 *pPrefetchCtrl) { + return pKernelGmmu->__kgmmuGetFaultRegisterMappings__(pGpu, pKernelGmmu, index, pFaultBufferGet, pFaultBufferPut, pFaultBufferInfo, faultIntr, faultIntrSet, faultIntrClear, faultMask, pPrefetchCtrl); +} + +NV_STATUS kgmmuIssueReplayableFaultBufferFlush_GH100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + +static inline NV_STATUS kgmmuIssueReplayableFaultBufferFlush_46f6a7(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kgmmuIssueReplayableFaultBufferFlush_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + return pKernelGmmu->__kgmmuIssueReplayableFaultBufferFlush__(pGpu, pKernelGmmu); +} + +NV_STATUS kgmmuFaultBufferAllocSharedMemory_GH100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0); + +static inline NV_STATUS kgmmuFaultBufferAllocSharedMemory_56cd7a(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0) { + return NV_OK; +} + +static inline NV_STATUS kgmmuFaultBufferAllocSharedMemory_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0) { + return pKernelGmmu->__kgmmuFaultBufferAllocSharedMemory__(pGpu, pKernelGmmu, arg0); +} + +void kgmmuFaultBufferFreeSharedMemory_GH100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0); + +static inline void kgmmuFaultBufferFreeSharedMemory_b3696a(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0) { + return; +} + +static inline void kgmmuFaultBufferFreeSharedMemory_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0) { + pKernelGmmu->__kgmmuFaultBufferFreeSharedMemory__(pGpu, pKernelGmmu, arg0); +} + NV_STATUS kgmmuSetupWarForBug2720120_GA100(struct KernelGmmu *pKernelGmmu, GMMU_FMT_FAMILY *pFam); static inline NV_STATUS kgmmuSetupWarForBug2720120_56cd7a(struct KernelGmmu *pKernelGmmu, GMMU_FMT_FAMILY *pFam) { @@ -1185,10 +1238,6 @@ static inline NvU32 kgmmuGetGraphicsEngineId_DISPATCH(struct KernelGmmu *pKernel return pKernelGmmu->__kgmmuGetGraphicsEngineId__(pKernelGmmu); } -static inline NV_STATUS kgmmuReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelGmmu *pEngstate, void *pTunableState) { - return pEngstate->__kgmmuReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kgmmuStateLoad_DISPATCH(POBJGPU pGpu, struct KernelGmmu *pEngstate, NvU32 arg0) { return pEngstate->__kgmmuStateLoad__(pGpu, pEngstate, arg0); } @@ -1225,30 +1274,10 @@ static inline NV_STATUS kgmmuStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct return pEngstate->__kgmmuStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kgmmuGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelGmmu *pEngstate, void *pTunableState) { - return pEngstate->__kgmmuGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kgmmuCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelGmmu *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kgmmuCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kgmmuFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelGmmu *pEngstate, void *pTunableState) { - pEngstate->__kgmmuFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kgmmuClearInterrupt_DISPATCH(struct OBJGPU *pGpu, struct KernelGmmu *pIntrService, IntrServiceClearInterruptArguments *pParams) { return pIntrService->__kgmmuClearInterrupt__(pGpu, pIntrService, pParams); } -static inline NV_STATUS kgmmuAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelGmmu *pEngstate, void **ppTunableState) { - return pEngstate->__kgmmuAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kgmmuSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelGmmu *pEngstate, void *pTunableState) { - return pEngstate->__kgmmuSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kgmmuIsPresent_DISPATCH(POBJGPU pGpu, struct KernelGmmu *pEngstate) { return pEngstate->__kgmmuIsPresent__(pGpu, pEngstate); } @@ -1544,67 +1573,67 @@ static inline NV_STATUS kgmmuFaultBufferUnregister(OBJGPU *pGpu, struct KernelGm #define kgmmuFaultBufferUnregister(pGpu, pKernelGmmu, arg0) kgmmuFaultBufferUnregister_IMPL(pGpu, pKernelGmmu, arg0) #endif //__nvoc_kern_gmmu_h_disabled -NV_STATUS kgmmuClientShadowFaultBufferNonreplayableAllocate_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); +NV_STATUS kgmmuClientShadowFaultBufferAllocate_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0); #ifdef __nvoc_kern_gmmu_h_disabled -static inline NV_STATUS kgmmuClientShadowFaultBufferNonreplayableAllocate(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { +static inline NV_STATUS kgmmuClientShadowFaultBufferAllocate(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kern_gmmu_h_disabled -#define kgmmuClientShadowFaultBufferNonreplayableAllocate(pGpu, pKernelGmmu) kgmmuClientShadowFaultBufferNonreplayableAllocate_IMPL(pGpu, pKernelGmmu) +#define kgmmuClientShadowFaultBufferAllocate(pGpu, pKernelGmmu, arg0) kgmmuClientShadowFaultBufferAllocate_IMPL(pGpu, pKernelGmmu, arg0) #endif //__nvoc_kern_gmmu_h_disabled -NV_STATUS kgmmuClientShadowFaultBufferNonreplayableDestroy_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); +NV_STATUS kgmmuClientShadowFaultBufferDestroy_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0); #ifdef __nvoc_kern_gmmu_h_disabled -static inline NV_STATUS kgmmuClientShadowFaultBufferNonreplayableDestroy(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { +static inline NV_STATUS kgmmuClientShadowFaultBufferDestroy(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kern_gmmu_h_disabled -#define kgmmuClientShadowFaultBufferNonreplayableDestroy(pGpu, pKernelGmmu) kgmmuClientShadowFaultBufferNonreplayableDestroy_IMPL(pGpu, pKernelGmmu) +#define kgmmuClientShadowFaultBufferDestroy(pGpu, pKernelGmmu, arg0) kgmmuClientShadowFaultBufferDestroy_IMPL(pGpu, pKernelGmmu, arg0) #endif //__nvoc_kern_gmmu_h_disabled -NV_STATUS kgmmuClientShadowFaultBufferRegister_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); +NV_STATUS kgmmuClientShadowFaultBufferRegister_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0); #ifdef __nvoc_kern_gmmu_h_disabled -static inline NV_STATUS kgmmuClientShadowFaultBufferRegister(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { +static inline NV_STATUS kgmmuClientShadowFaultBufferRegister(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kern_gmmu_h_disabled -#define kgmmuClientShadowFaultBufferRegister(pGpu, pKernelGmmu) kgmmuClientShadowFaultBufferRegister_IMPL(pGpu, pKernelGmmu) +#define kgmmuClientShadowFaultBufferRegister(pGpu, pKernelGmmu, arg0) kgmmuClientShadowFaultBufferRegister_IMPL(pGpu, pKernelGmmu, arg0) #endif //__nvoc_kern_gmmu_h_disabled -void kgmmuClientShadowFaultBufferUnregister_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); +void kgmmuClientShadowFaultBufferUnregister_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0); #ifdef __nvoc_kern_gmmu_h_disabled -static inline void kgmmuClientShadowFaultBufferUnregister(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { +static inline void kgmmuClientShadowFaultBufferUnregister(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); } #else //__nvoc_kern_gmmu_h_disabled -#define kgmmuClientShadowFaultBufferUnregister(pGpu, pKernelGmmu) kgmmuClientShadowFaultBufferUnregister_IMPL(pGpu, pKernelGmmu) +#define kgmmuClientShadowFaultBufferUnregister(pGpu, pKernelGmmu, arg0) kgmmuClientShadowFaultBufferUnregister_IMPL(pGpu, pKernelGmmu, arg0) #endif //__nvoc_kern_gmmu_h_disabled -void kgmmuClientShadowFaultBufferPagesDestroy_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvBool arg0); +void kgmmuClientShadowFaultBufferPagesDestroy_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvBool arg0, FAULT_BUFFER_TYPE arg1); #ifdef __nvoc_kern_gmmu_h_disabled -static inline void kgmmuClientShadowFaultBufferPagesDestroy(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvBool arg0) { +static inline void kgmmuClientShadowFaultBufferPagesDestroy(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvBool arg0, FAULT_BUFFER_TYPE arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); } #else //__nvoc_kern_gmmu_h_disabled -#define kgmmuClientShadowFaultBufferPagesDestroy(pGpu, pKernelGmmu, arg0) kgmmuClientShadowFaultBufferPagesDestroy_IMPL(pGpu, pKernelGmmu, arg0) +#define kgmmuClientShadowFaultBufferPagesDestroy(pGpu, pKernelGmmu, arg0, arg1) kgmmuClientShadowFaultBufferPagesDestroy_IMPL(pGpu, pKernelGmmu, arg0, arg1) #endif //__nvoc_kern_gmmu_h_disabled -void kgmmuClientShadowFaultBufferQueueDestroy_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvBool arg0); +void kgmmuClientShadowFaultBufferQueueDestroy_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvBool arg0, FAULT_BUFFER_TYPE arg1); #ifdef __nvoc_kern_gmmu_h_disabled -static inline void kgmmuClientShadowFaultBufferQueueDestroy(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvBool arg0) { +static inline void kgmmuClientShadowFaultBufferQueueDestroy(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvBool arg0, FAULT_BUFFER_TYPE arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); } #else //__nvoc_kern_gmmu_h_disabled -#define kgmmuClientShadowFaultBufferQueueDestroy(pGpu, pKernelGmmu, arg0) kgmmuClientShadowFaultBufferQueueDestroy_IMPL(pGpu, pKernelGmmu, arg0) +#define kgmmuClientShadowFaultBufferQueueDestroy(pGpu, pKernelGmmu, arg0, arg1) kgmmuClientShadowFaultBufferQueueDestroy_IMPL(pGpu, pKernelGmmu, arg0, arg1) #endif //__nvoc_kern_gmmu_h_disabled NvU64 kgmmuGetSizeOfPageTables_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, const struct GMMU_FMT *arg0, NvU64 arg1, NvU64 arg2, NvU64 arg3); diff --git a/src/nvidia/generated/g_kern_mem_sys_nvoc.c b/src/nvidia/generated/g_kern_mem_sys_nvoc.c index d279d724c..5b41d8af1 100644 --- a/src/nvidia/generated/g_kern_mem_sys_nvoc.c +++ b/src/nvidia/generated/g_kern_mem_sys_nvoc.c @@ -82,10 +82,6 @@ static void __nvoc_thunk_KernelMemorySystem_engstateStateDestroy(OBJGPU *pGpu, s kmemsysStateDestroy(pGpu, (struct KernelMemorySystem *)(((unsigned char *)pKernelMemorySystem) - __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmemsysReconcileTunableState(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmemsysStateLoad(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset), arg0); } @@ -118,30 +114,10 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmemsysStatePreInitUnlocked(POBJGPU pG return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmemsysGetTunableState(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmemsysCompareTunableState(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kmemsysFreeTunableState(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmemsysStatePostLoad(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmemsysAllocTunableState(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmemsysSetTunableState(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_kmemsysIsPresent(POBJGPU pGpu, struct KernelMemorySystem *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset)); } @@ -194,6 +170,17 @@ void __nvoc_init_dataField_KernelMemorySystem(KernelMemorySystem *pThis, RmHalsp // Hal field -- bPreserveComptagBackingStoreOnSuspend pThis->bPreserveComptagBackingStoreOnSuspend = ((NvBool)(0 != 0)); + + // Hal field -- bBug3656943WAR + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->bBug3656943WAR = ((NvBool)(0 == 0)); + } + // default + else + { + pThis->bBug3656943WAR = ((NvBool)(0 != 0)); + } } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); @@ -404,8 +391,6 @@ static void __nvoc_init_funcTable_KernelMemorySystem_1(KernelMemorySystem *pThis pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_KernelMemorySystem_engstateStateDestroy; - pThis->__kmemsysReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmemsysReconcileTunableState; - pThis->__kmemsysStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kmemsysStateLoad; pThis->__kmemsysStateUnload__ = &__nvoc_thunk_OBJENGSTATE_kmemsysStateUnload; @@ -422,18 +407,8 @@ static void __nvoc_init_funcTable_KernelMemorySystem_1(KernelMemorySystem *pThis pThis->__kmemsysStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kmemsysStatePreInitUnlocked; - pThis->__kmemsysGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmemsysGetTunableState; - - pThis->__kmemsysCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmemsysCompareTunableState; - - pThis->__kmemsysFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmemsysFreeTunableState; - pThis->__kmemsysStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kmemsysStatePostLoad; - pThis->__kmemsysAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmemsysAllocTunableState; - - pThis->__kmemsysSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmemsysSetTunableState; - pThis->__kmemsysIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kmemsysIsPresent; } @@ -456,13 +431,16 @@ NV_STATUS __nvoc_objCreate_KernelMemorySystem(KernelMemorySystem **ppThis, Dynam KernelMemorySystem *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelMemorySystem)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelMemorySystem), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelMemorySystem)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelMemorySystem); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -482,11 +460,17 @@ NV_STATUS __nvoc_objCreate_KernelMemorySystem(KernelMemorySystem **ppThis, Dynam if (status != NV_OK) goto __nvoc_objCreate_KernelMemorySystem_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelMemorySystem_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelMemorySystem)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kern_mem_sys_nvoc.h b/src/nvidia/generated/g_kern_mem_sys_nvoc.h index 8ff796e07..60607fd59 100644 --- a/src/nvidia/generated/g_kern_mem_sys_nvoc.h +++ b/src/nvidia/generated/g_kern_mem_sys_nvoc.h @@ -215,7 +215,6 @@ struct KernelMemorySystem { NV_STATUS (*__kmemsysReadMIGMemoryCfg__)(OBJGPU *, struct KernelMemorySystem *); NV_STATUS (*__kmemsysInitMIGMemoryPartitionTable__)(OBJGPU *, struct KernelMemorySystem *); NV_STATUS (*__kmemsysSwizzIdToVmmuSegmentsRange__)(OBJGPU *, struct KernelMemorySystem *, NvU32, NvU32, NvU32); - NV_STATUS (*__kmemsysReconcileTunableState__)(POBJGPU, struct KernelMemorySystem *, void *); NV_STATUS (*__kmemsysStateLoad__)(POBJGPU, struct KernelMemorySystem *, NvU32); NV_STATUS (*__kmemsysStateUnload__)(POBJGPU, struct KernelMemorySystem *, NvU32); NV_STATUS (*__kmemsysStatePostUnload__)(POBJGPU, struct KernelMemorySystem *, NvU32); @@ -224,18 +223,14 @@ struct KernelMemorySystem { void (*__kmemsysInitMissing__)(POBJGPU, struct KernelMemorySystem *); NV_STATUS (*__kmemsysStatePreInitLocked__)(POBJGPU, struct KernelMemorySystem *); NV_STATUS (*__kmemsysStatePreInitUnlocked__)(POBJGPU, struct KernelMemorySystem *); - NV_STATUS (*__kmemsysGetTunableState__)(POBJGPU, struct KernelMemorySystem *, void *); - NV_STATUS (*__kmemsysCompareTunableState__)(POBJGPU, struct KernelMemorySystem *, void *, void *); - void (*__kmemsysFreeTunableState__)(POBJGPU, struct KernelMemorySystem *, void *); NV_STATUS (*__kmemsysStatePostLoad__)(POBJGPU, struct KernelMemorySystem *, NvU32); - NV_STATUS (*__kmemsysAllocTunableState__)(POBJGPU, struct KernelMemorySystem *, void **); - NV_STATUS (*__kmemsysSetTunableState__)(POBJGPU, struct KernelMemorySystem *, void *); NvBool (*__kmemsysIsPresent__)(POBJGPU, struct KernelMemorySystem *); NvBool bDisableTiledCachingInvalidatesWithEccBug1521641; NvBool bGpuCacheEnable; NvBool bNumaNodesAdded; NvBool bL2CleanFbPull; NvBool bPreserveComptagBackingStoreOnSuspend; + NvBool bBug3656943WAR; const MEMORY_SYSTEM_STATIC_CONFIG *pStaticConfig; MEM_PARTITION_NUMA_INFO *memPartitionNumaInfo; MIG_MEM_BOUNDARY_CONFIG_TABLE memBoundaryCfgTable; @@ -311,7 +306,6 @@ NV_STATUS __nvoc_objCreate_KernelMemorySystem(KernelMemorySystem**, Dynamic*, Nv #define kmemsysInitMIGMemoryPartitionTable_HAL(pGpu, pKernelMemorySystem) kmemsysInitMIGMemoryPartitionTable_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysSwizzIdToVmmuSegmentsRange(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments) kmemsysSwizzIdToVmmuSegmentsRange_DISPATCH(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments) #define kmemsysSwizzIdToVmmuSegmentsRange_HAL(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments) kmemsysSwizzIdToVmmuSegmentsRange_DISPATCH(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments) -#define kmemsysReconcileTunableState(pGpu, pEngstate, pTunableState) kmemsysReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kmemsysStateLoad(pGpu, pEngstate, arg0) kmemsysStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kmemsysStateUnload(pGpu, pEngstate, arg0) kmemsysStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define kmemsysStatePostUnload(pGpu, pEngstate, arg0) kmemsysStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) @@ -320,12 +314,7 @@ NV_STATUS __nvoc_objCreate_KernelMemorySystem(KernelMemorySystem**, Dynamic*, Nv #define kmemsysInitMissing(pGpu, pEngstate) kmemsysInitMissing_DISPATCH(pGpu, pEngstate) #define kmemsysStatePreInitLocked(pGpu, pEngstate) kmemsysStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kmemsysStatePreInitUnlocked(pGpu, pEngstate) kmemsysStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kmemsysGetTunableState(pGpu, pEngstate, pTunableState) kmemsysGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kmemsysCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kmemsysCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kmemsysFreeTunableState(pGpu, pEngstate, pTunableState) kmemsysFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kmemsysStatePostLoad(pGpu, pEngstate, arg0) kmemsysStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define kmemsysAllocTunableState(pGpu, pEngstate, ppTunableState) kmemsysAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kmemsysSetTunableState(pGpu, pEngstate, pTunableState) kmemsysSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kmemsysIsPresent(pGpu, pEngstate) kmemsysIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS kmemsysGetUsableFbSize_KERNEL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU64 *pFbSize); @@ -653,10 +642,6 @@ static inline NV_STATUS kmemsysSwizzIdToVmmuSegmentsRange_DISPATCH(OBJGPU *pGpu, return pKernelMemorySystem->__kmemsysSwizzIdToVmmuSegmentsRange__(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments); } -static inline NV_STATUS kmemsysReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, void *pTunableState) { - return pEngstate->__kmemsysReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kmemsysStateLoad_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, NvU32 arg0) { return pEngstate->__kmemsysStateLoad__(pGpu, pEngstate, arg0); } @@ -689,30 +674,10 @@ static inline NV_STATUS kmemsysStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struc return pEngstate->__kmemsysStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kmemsysGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, void *pTunableState) { - return pEngstate->__kmemsysGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kmemsysCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kmemsysCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kmemsysFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, void *pTunableState) { - pEngstate->__kmemsysFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kmemsysStatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, NvU32 arg0) { return pEngstate->__kmemsysStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS kmemsysAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, void **ppTunableState) { - return pEngstate->__kmemsysAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kmemsysSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, void *pTunableState) { - return pEngstate->__kmemsysSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kmemsysIsPresent_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate) { return pEngstate->__kmemsysIsPresent__(pGpu, pEngstate); } diff --git a/src/nvidia/generated/g_kern_perf_nvoc.c b/src/nvidia/generated/g_kern_perf_nvoc.c index 83eced674..12ab9fc9d 100644 --- a/src/nvidia/generated/g_kern_perf_nvoc.c +++ b/src/nvidia/generated/g_kern_perf_nvoc.c @@ -86,10 +86,6 @@ static void __nvoc_thunk_KernelPerf_engstateStateDestroy(struct OBJGPU *pGpu, st kperfStateDestroy(pGpu, (struct KernelPerf *)(((unsigned char *)pKernelPerf) - __nvoc_rtti_KernelPerf_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kperfReconcileTunableState(POBJGPU pGpu, struct KernelPerf *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPerf_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kperfStatePreLoad(POBJGPU pGpu, struct KernelPerf *pEngstate, NvU32 arg0) { return engstateStatePreLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPerf_OBJENGSTATE.offset), arg0); } @@ -118,30 +114,10 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_kperfStatePreInitUnlocked(POBJGPU pGpu return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPerf_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kperfGetTunableState(POBJGPU pGpu, struct KernelPerf *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPerf_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kperfCompareTunableState(POBJGPU pGpu, struct KernelPerf *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPerf_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kperfFreeTunableState(POBJGPU pGpu, struct KernelPerf *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPerf_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kperfStatePostLoad(POBJGPU pGpu, struct KernelPerf *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPerf_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kperfAllocTunableState(POBJGPU pGpu, struct KernelPerf *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPerf_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kperfSetTunableState(POBJGPU pGpu, struct KernelPerf *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPerf_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_kperfIsPresent(POBJGPU pGpu, struct KernelPerf *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPerf_OBJENGSTATE.offset)); } @@ -209,8 +185,6 @@ static void __nvoc_init_funcTable_KernelPerf_1(KernelPerf *pThis, RmHalspecOwner pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_KernelPerf_engstateStateDestroy; - pThis->__kperfReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kperfReconcileTunableState; - pThis->__kperfStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_kperfStatePreLoad; pThis->__kperfStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_kperfStatePostUnload; @@ -225,18 +199,8 @@ static void __nvoc_init_funcTable_KernelPerf_1(KernelPerf *pThis, RmHalspecOwner pThis->__kperfStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kperfStatePreInitUnlocked; - pThis->__kperfGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kperfGetTunableState; - - pThis->__kperfCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kperfCompareTunableState; - - pThis->__kperfFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kperfFreeTunableState; - pThis->__kperfStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kperfStatePostLoad; - pThis->__kperfAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kperfAllocTunableState; - - pThis->__kperfSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kperfSetTunableState; - pThis->__kperfIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kperfIsPresent; } @@ -259,13 +223,16 @@ NV_STATUS __nvoc_objCreate_KernelPerf(KernelPerf **ppThis, Dynamic *pParent, NvU KernelPerf *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelPerf)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelPerf), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelPerf)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelPerf); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -285,11 +252,17 @@ NV_STATUS __nvoc_objCreate_KernelPerf(KernelPerf **ppThis, Dynamic *pParent, NvU if (status != NV_OK) goto __nvoc_objCreate_KernelPerf_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelPerf_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelPerf)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kern_perf_nvoc.h b/src/nvidia/generated/g_kern_perf_nvoc.h index 535603ce7..9fc6eccf2 100644 --- a/src/nvidia/generated/g_kern_perf_nvoc.h +++ b/src/nvidia/generated/g_kern_perf_nvoc.h @@ -77,7 +77,6 @@ struct KernelPerf { NV_STATUS (*__kperfStateLoad__)(struct OBJGPU *, struct KernelPerf *, NvU32); NV_STATUS (*__kperfStateUnload__)(struct OBJGPU *, struct KernelPerf *, NvU32); void (*__kperfStateDestroy__)(struct OBJGPU *, struct KernelPerf *); - NV_STATUS (*__kperfReconcileTunableState__)(POBJGPU, struct KernelPerf *, void *); NV_STATUS (*__kperfStatePreLoad__)(POBJGPU, struct KernelPerf *, NvU32); NV_STATUS (*__kperfStatePostUnload__)(POBJGPU, struct KernelPerf *, NvU32); NV_STATUS (*__kperfStatePreUnload__)(POBJGPU, struct KernelPerf *, NvU32); @@ -85,12 +84,7 @@ struct KernelPerf { void (*__kperfInitMissing__)(POBJGPU, struct KernelPerf *); NV_STATUS (*__kperfStatePreInitLocked__)(POBJGPU, struct KernelPerf *); NV_STATUS (*__kperfStatePreInitUnlocked__)(POBJGPU, struct KernelPerf *); - NV_STATUS (*__kperfGetTunableState__)(POBJGPU, struct KernelPerf *, void *); - NV_STATUS (*__kperfCompareTunableState__)(POBJGPU, struct KernelPerf *, void *, void *); - void (*__kperfFreeTunableState__)(POBJGPU, struct KernelPerf *, void *); NV_STATUS (*__kperfStatePostLoad__)(POBJGPU, struct KernelPerf *, NvU32); - NV_STATUS (*__kperfAllocTunableState__)(POBJGPU, struct KernelPerf *, void **); - NV_STATUS (*__kperfSetTunableState__)(POBJGPU, struct KernelPerf *, void *); NvBool (*__kperfIsPresent__)(POBJGPU, struct KernelPerf *); struct KERNEL_PERF_GPU_BOOST_SYNC sliGpuBoostSync; NvU32 reentrancyMask; @@ -131,7 +125,6 @@ NV_STATUS __nvoc_objCreate_KernelPerf(KernelPerf**, Dynamic*, NvU32); #define kperfStateLoad(pGpu, pKernelPerf, flags) kperfStateLoad_DISPATCH(pGpu, pKernelPerf, flags) #define kperfStateUnload(pGpu, pKernelPerf, flags) kperfStateUnload_DISPATCH(pGpu, pKernelPerf, flags) #define kperfStateDestroy(pGpu, pKernelPerf) kperfStateDestroy_DISPATCH(pGpu, pKernelPerf) -#define kperfReconcileTunableState(pGpu, pEngstate, pTunableState) kperfReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kperfStatePreLoad(pGpu, pEngstate, arg0) kperfStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kperfStatePostUnload(pGpu, pEngstate, arg0) kperfStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) #define kperfStatePreUnload(pGpu, pEngstate, arg0) kperfStatePreUnload_DISPATCH(pGpu, pEngstate, arg0) @@ -139,12 +132,7 @@ NV_STATUS __nvoc_objCreate_KernelPerf(KernelPerf**, Dynamic*, NvU32); #define kperfInitMissing(pGpu, pEngstate) kperfInitMissing_DISPATCH(pGpu, pEngstate) #define kperfStatePreInitLocked(pGpu, pEngstate) kperfStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kperfStatePreInitUnlocked(pGpu, pEngstate) kperfStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kperfGetTunableState(pGpu, pEngstate, pTunableState) kperfGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kperfCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kperfCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kperfFreeTunableState(pGpu, pEngstate, pTunableState) kperfFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kperfStatePostLoad(pGpu, pEngstate, arg0) kperfStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define kperfAllocTunableState(pGpu, pEngstate, ppTunableState) kperfAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kperfSetTunableState(pGpu, pEngstate, pTunableState) kperfSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kperfIsPresent(pGpu, pEngstate) kperfIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS kperfGpuBoostSyncStateInit_IMPL(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf); @@ -204,10 +192,6 @@ static inline void kperfStateDestroy_DISPATCH(struct OBJGPU *pGpu, struct Kernel pKernelPerf->__kperfStateDestroy__(pGpu, pKernelPerf); } -static inline NV_STATUS kperfReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelPerf *pEngstate, void *pTunableState) { - return pEngstate->__kperfReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kperfStatePreLoad_DISPATCH(POBJGPU pGpu, struct KernelPerf *pEngstate, NvU32 arg0) { return pEngstate->__kperfStatePreLoad__(pGpu, pEngstate, arg0); } @@ -236,30 +220,10 @@ static inline NV_STATUS kperfStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct return pEngstate->__kperfStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kperfGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelPerf *pEngstate, void *pTunableState) { - return pEngstate->__kperfGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kperfCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelPerf *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kperfCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kperfFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelPerf *pEngstate, void *pTunableState) { - pEngstate->__kperfFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kperfStatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelPerf *pEngstate, NvU32 arg0) { return pEngstate->__kperfStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS kperfAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelPerf *pEngstate, void **ppTunableState) { - return pEngstate->__kperfAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kperfSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelPerf *pEngstate, void *pTunableState) { - return pEngstate->__kperfSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kperfIsPresent_DISPATCH(POBJGPU pGpu, struct KernelPerf *pEngstate) { return pEngstate->__kperfIsPresent__(pGpu, pEngstate); } diff --git a/src/nvidia/generated/g_kern_perfbuffer_nvoc.c b/src/nvidia/generated/g_kern_perfbuffer_nvoc.c index e26af1a6c..a99446f14 100644 --- a/src/nvidia/generated/g_kern_perfbuffer_nvoc.c +++ b/src/nvidia/generated/g_kern_perfbuffer_nvoc.c @@ -97,6 +97,54 @@ static NvBool __nvoc_thunk_GpuResource_perfbufferShareCallback(struct PerfBuffer return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_PerfBuffer_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } +static NV_STATUS __nvoc_thunk_RmResource_perfbufferCheckMemInterUnmap(struct PerfBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_PerfBuffer_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_perfbufferMapTo(struct PerfBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_perfbufferGetMapAddrSpace(struct PerfBuffer *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_PerfBuffer_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_perfbufferGetRefCount(struct PerfBuffer *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_perfbufferAddAdditionalDependants(struct RsClient *pClient, struct PerfBuffer *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_perfbufferControl_Prologue(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_perfbufferGetRegBaseOffsetAndSize(struct PerfBuffer *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_PerfBuffer_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_perfbufferInternalControlForward(struct PerfBuffer *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_PerfBuffer_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_perfbufferUnmapFrom(struct PerfBuffer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_perfbufferControl_Epilogue(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_perfbufferControlLookup(struct PerfBuffer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset), pParams, ppEntry); +} + +static NvHandle __nvoc_thunk_GpuResource_perfbufferGetInternalObjectHandle(struct PerfBuffer *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_PerfBuffer_GpuResource.offset)); +} + static NV_STATUS __nvoc_thunk_GpuResource_perfbufferControl(struct PerfBuffer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_PerfBuffer_GpuResource.offset), pCallContext, pParams); } @@ -113,68 +161,28 @@ static NV_STATUS __nvoc_thunk_RmResource_perfbufferGetMemoryMappingDescriptor(st return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_PerfBuffer_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_GpuResource_perfbufferGetMapAddrSpace(struct PerfBuffer *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_PerfBuffer_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvHandle __nvoc_thunk_GpuResource_perfbufferGetInternalObjectHandle(struct PerfBuffer *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_PerfBuffer_GpuResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_perfbufferControlFilter(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_perfbufferAddAdditionalDependants(struct RsClient *pClient, struct PerfBuffer *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_perfbufferGetRefCount(struct PerfBuffer *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RmResource_perfbufferCheckMemInterUnmap(struct PerfBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_PerfBuffer_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_perfbufferMapTo(struct PerfBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_perfbufferControl_Prologue(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_GpuResource_perfbufferGetRegBaseOffsetAndSize(struct PerfBuffer *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_PerfBuffer_GpuResource.offset), pGpu, pOffset, pSize); +static NV_STATUS __nvoc_thunk_RmResource_perfbufferControlSerialization_Prologue(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_perfbufferCanCopy(struct PerfBuffer *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_perfbufferInternalControlForward(struct PerfBuffer *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_PerfBuffer_GpuResource.offset), command, pParams, size); -} - static void __nvoc_thunk_RsResource_perfbufferPreDestruct(struct PerfBuffer *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_perfbufferUnmapFrom(struct PerfBuffer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_perfbufferIsDuplicate(struct PerfBuffer *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset), hMemory, pDuplicate); } -static void __nvoc_thunk_RmResource_perfbufferControl_Epilogue(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_perfbufferControlLookup(struct PerfBuffer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_perfbufferControlSerialization_Epilogue(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_perfbufferMap(struct PerfBuffer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -236,6 +244,30 @@ static void __nvoc_init_funcTable_PerfBuffer_1(PerfBuffer *pThis, RmHalspecOwner pThis->__perfbufferShareCallback__ = &__nvoc_thunk_GpuResource_perfbufferShareCallback; + pThis->__perfbufferCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_perfbufferCheckMemInterUnmap; + + pThis->__perfbufferMapTo__ = &__nvoc_thunk_RsResource_perfbufferMapTo; + + pThis->__perfbufferGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_perfbufferGetMapAddrSpace; + + pThis->__perfbufferGetRefCount__ = &__nvoc_thunk_RsResource_perfbufferGetRefCount; + + pThis->__perfbufferAddAdditionalDependants__ = &__nvoc_thunk_RsResource_perfbufferAddAdditionalDependants; + + pThis->__perfbufferControl_Prologue__ = &__nvoc_thunk_RmResource_perfbufferControl_Prologue; + + pThis->__perfbufferGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_perfbufferGetRegBaseOffsetAndSize; + + pThis->__perfbufferInternalControlForward__ = &__nvoc_thunk_GpuResource_perfbufferInternalControlForward; + + pThis->__perfbufferUnmapFrom__ = &__nvoc_thunk_RsResource_perfbufferUnmapFrom; + + pThis->__perfbufferControl_Epilogue__ = &__nvoc_thunk_RmResource_perfbufferControl_Epilogue; + + pThis->__perfbufferControlLookup__ = &__nvoc_thunk_RsResource_perfbufferControlLookup; + + pThis->__perfbufferGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_perfbufferGetInternalObjectHandle; + pThis->__perfbufferControl__ = &__nvoc_thunk_GpuResource_perfbufferControl; pThis->__perfbufferUnmap__ = &__nvoc_thunk_GpuResource_perfbufferUnmap; @@ -244,37 +276,17 @@ static void __nvoc_init_funcTable_PerfBuffer_1(PerfBuffer *pThis, RmHalspecOwner pThis->__perfbufferGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_perfbufferGetMemoryMappingDescriptor; - pThis->__perfbufferGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_perfbufferGetMapAddrSpace; - - pThis->__perfbufferGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_perfbufferGetInternalObjectHandle; - pThis->__perfbufferControlFilter__ = &__nvoc_thunk_RsResource_perfbufferControlFilter; - pThis->__perfbufferAddAdditionalDependants__ = &__nvoc_thunk_RsResource_perfbufferAddAdditionalDependants; - - pThis->__perfbufferGetRefCount__ = &__nvoc_thunk_RsResource_perfbufferGetRefCount; - - pThis->__perfbufferCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_perfbufferCheckMemInterUnmap; - - pThis->__perfbufferMapTo__ = &__nvoc_thunk_RsResource_perfbufferMapTo; - - pThis->__perfbufferControl_Prologue__ = &__nvoc_thunk_RmResource_perfbufferControl_Prologue; - - pThis->__perfbufferGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_perfbufferGetRegBaseOffsetAndSize; + pThis->__perfbufferControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_perfbufferControlSerialization_Prologue; pThis->__perfbufferCanCopy__ = &__nvoc_thunk_RsResource_perfbufferCanCopy; - pThis->__perfbufferInternalControlForward__ = &__nvoc_thunk_GpuResource_perfbufferInternalControlForward; - pThis->__perfbufferPreDestruct__ = &__nvoc_thunk_RsResource_perfbufferPreDestruct; - pThis->__perfbufferUnmapFrom__ = &__nvoc_thunk_RsResource_perfbufferUnmapFrom; - pThis->__perfbufferIsDuplicate__ = &__nvoc_thunk_RsResource_perfbufferIsDuplicate; - pThis->__perfbufferControl_Epilogue__ = &__nvoc_thunk_RmResource_perfbufferControl_Epilogue; - - pThis->__perfbufferControlLookup__ = &__nvoc_thunk_RsResource_perfbufferControlLookup; + pThis->__perfbufferControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_perfbufferControlSerialization_Epilogue; pThis->__perfbufferMap__ = &__nvoc_thunk_GpuResource_perfbufferMap; @@ -303,13 +315,16 @@ NV_STATUS __nvoc_objCreate_PerfBuffer(PerfBuffer **ppThis, Dynamic *pParent, NvU PerfBuffer *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(PerfBuffer)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(PerfBuffer), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(PerfBuffer)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_PerfBuffer); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -329,11 +344,17 @@ NV_STATUS __nvoc_objCreate_PerfBuffer(PerfBuffer **ppThis, Dynamic *pParent, NvU if (status != NV_OK) goto __nvoc_objCreate_PerfBuffer_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_PerfBuffer_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(PerfBuffer)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kern_perfbuffer_nvoc.h b/src/nvidia/generated/g_kern_perfbuffer_nvoc.h index d7660022a..61d17ac09 100644 --- a/src/nvidia/generated/g_kern_perfbuffer_nvoc.h +++ b/src/nvidia/generated/g_kern_perfbuffer_nvoc.h @@ -56,26 +56,28 @@ struct PerfBuffer { struct GpuResource *__nvoc_pbase_GpuResource; struct PerfBuffer *__nvoc_pbase_PerfBuffer; NvBool (*__perfbufferShareCallback__)(struct PerfBuffer *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__perfbufferCheckMemInterUnmap__)(struct PerfBuffer *, NvBool); + NV_STATUS (*__perfbufferMapTo__)(struct PerfBuffer *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__perfbufferGetMapAddrSpace__)(struct PerfBuffer *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__perfbufferGetRefCount__)(struct PerfBuffer *); + void (*__perfbufferAddAdditionalDependants__)(struct RsClient *, struct PerfBuffer *, RsResourceRef *); + NV_STATUS (*__perfbufferControl_Prologue__)(struct PerfBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__perfbufferGetRegBaseOffsetAndSize__)(struct PerfBuffer *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__perfbufferInternalControlForward__)(struct PerfBuffer *, NvU32, void *, NvU32); + NV_STATUS (*__perfbufferUnmapFrom__)(struct PerfBuffer *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__perfbufferControl_Epilogue__)(struct PerfBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__perfbufferControlLookup__)(struct PerfBuffer *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__perfbufferGetInternalObjectHandle__)(struct PerfBuffer *); NV_STATUS (*__perfbufferControl__)(struct PerfBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__perfbufferUnmap__)(struct PerfBuffer *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__perfbufferGetMemInterMapParams__)(struct PerfBuffer *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__perfbufferGetMemoryMappingDescriptor__)(struct PerfBuffer *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__perfbufferGetMapAddrSpace__)(struct PerfBuffer *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__perfbufferGetInternalObjectHandle__)(struct PerfBuffer *); NV_STATUS (*__perfbufferControlFilter__)(struct PerfBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__perfbufferAddAdditionalDependants__)(struct RsClient *, struct PerfBuffer *, RsResourceRef *); - NvU32 (*__perfbufferGetRefCount__)(struct PerfBuffer *); - NV_STATUS (*__perfbufferCheckMemInterUnmap__)(struct PerfBuffer *, NvBool); - NV_STATUS (*__perfbufferMapTo__)(struct PerfBuffer *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__perfbufferControl_Prologue__)(struct PerfBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__perfbufferGetRegBaseOffsetAndSize__)(struct PerfBuffer *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__perfbufferControlSerialization_Prologue__)(struct PerfBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__perfbufferCanCopy__)(struct PerfBuffer *); - NV_STATUS (*__perfbufferInternalControlForward__)(struct PerfBuffer *, NvU32, void *, NvU32); void (*__perfbufferPreDestruct__)(struct PerfBuffer *); - NV_STATUS (*__perfbufferUnmapFrom__)(struct PerfBuffer *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__perfbufferIsDuplicate__)(struct PerfBuffer *, NvHandle, NvBool *); - void (*__perfbufferControl_Epilogue__)(struct PerfBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__perfbufferControlLookup__)(struct PerfBuffer *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__perfbufferControlSerialization_Epilogue__)(struct PerfBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__perfbufferMap__)(struct PerfBuffer *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__perfbufferAccessCallback__)(struct PerfBuffer *, struct RsClient *, void *, RsAccessRight); void *pObject; @@ -110,26 +112,28 @@ NV_STATUS __nvoc_objCreate_PerfBuffer(PerfBuffer**, Dynamic*, NvU32, struct CALL __nvoc_objCreate_PerfBuffer((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) #define perfbufferShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) perfbufferShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define perfbufferCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) perfbufferCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define perfbufferMapTo(pResource, pParams) perfbufferMapTo_DISPATCH(pResource, pParams) +#define perfbufferGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) perfbufferGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define perfbufferGetRefCount(pResource) perfbufferGetRefCount_DISPATCH(pResource) +#define perfbufferAddAdditionalDependants(pClient, pResource, pReference) perfbufferAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define perfbufferControl_Prologue(pResource, pCallContext, pParams) perfbufferControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define perfbufferGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) perfbufferGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define perfbufferInternalControlForward(pGpuResource, command, pParams, size) perfbufferInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define perfbufferUnmapFrom(pResource, pParams) perfbufferUnmapFrom_DISPATCH(pResource, pParams) +#define perfbufferControl_Epilogue(pResource, pCallContext, pParams) perfbufferControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define perfbufferControlLookup(pResource, pParams, ppEntry) perfbufferControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define perfbufferGetInternalObjectHandle(pGpuResource) perfbufferGetInternalObjectHandle_DISPATCH(pGpuResource) #define perfbufferControl(pGpuResource, pCallContext, pParams) perfbufferControl_DISPATCH(pGpuResource, pCallContext, pParams) #define perfbufferUnmap(pGpuResource, pCallContext, pCpuMapping) perfbufferUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define perfbufferGetMemInterMapParams(pRmResource, pParams) perfbufferGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define perfbufferGetMemoryMappingDescriptor(pRmResource, ppMemDesc) perfbufferGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define perfbufferGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) perfbufferGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define perfbufferGetInternalObjectHandle(pGpuResource) perfbufferGetInternalObjectHandle_DISPATCH(pGpuResource) #define perfbufferControlFilter(pResource, pCallContext, pParams) perfbufferControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define perfbufferAddAdditionalDependants(pClient, pResource, pReference) perfbufferAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define perfbufferGetRefCount(pResource) perfbufferGetRefCount_DISPATCH(pResource) -#define perfbufferCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) perfbufferCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define perfbufferMapTo(pResource, pParams) perfbufferMapTo_DISPATCH(pResource, pParams) -#define perfbufferControl_Prologue(pResource, pCallContext, pParams) perfbufferControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define perfbufferGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) perfbufferGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define perfbufferControlSerialization_Prologue(pResource, pCallContext, pParams) perfbufferControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define perfbufferCanCopy(pResource) perfbufferCanCopy_DISPATCH(pResource) -#define perfbufferInternalControlForward(pGpuResource, command, pParams, size) perfbufferInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define perfbufferPreDestruct(pResource) perfbufferPreDestruct_DISPATCH(pResource) -#define perfbufferUnmapFrom(pResource, pParams) perfbufferUnmapFrom_DISPATCH(pResource, pParams) #define perfbufferIsDuplicate(pResource, hMemory, pDuplicate) perfbufferIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) -#define perfbufferControl_Epilogue(pResource, pCallContext, pParams) perfbufferControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define perfbufferControlLookup(pResource, pParams, ppEntry) perfbufferControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define perfbufferControlSerialization_Epilogue(pResource, pCallContext, pParams) perfbufferControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define perfbufferMap(pGpuResource, pCallContext, pParams, pCpuMapping) perfbufferMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define perfbufferAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) perfbufferAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS perfbufferConstructHal_KERNEL(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); @@ -156,6 +160,54 @@ static inline NvBool perfbufferShareCallback_DISPATCH(struct PerfBuffer *pGpuRes return pGpuResource->__perfbufferShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } +static inline NV_STATUS perfbufferCheckMemInterUnmap_DISPATCH(struct PerfBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__perfbufferCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS perfbufferMapTo_DISPATCH(struct PerfBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__perfbufferMapTo__(pResource, pParams); +} + +static inline NV_STATUS perfbufferGetMapAddrSpace_DISPATCH(struct PerfBuffer *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__perfbufferGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 perfbufferGetRefCount_DISPATCH(struct PerfBuffer *pResource) { + return pResource->__perfbufferGetRefCount__(pResource); +} + +static inline void perfbufferAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct PerfBuffer *pResource, RsResourceRef *pReference) { + pResource->__perfbufferAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS perfbufferControl_Prologue_DISPATCH(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__perfbufferControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS perfbufferGetRegBaseOffsetAndSize_DISPATCH(struct PerfBuffer *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__perfbufferGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS perfbufferInternalControlForward_DISPATCH(struct PerfBuffer *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__perfbufferInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS perfbufferUnmapFrom_DISPATCH(struct PerfBuffer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__perfbufferUnmapFrom__(pResource, pParams); +} + +static inline void perfbufferControl_Epilogue_DISPATCH(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__perfbufferControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS perfbufferControlLookup_DISPATCH(struct PerfBuffer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__perfbufferControlLookup__(pResource, pParams, ppEntry); +} + +static inline NvHandle perfbufferGetInternalObjectHandle_DISPATCH(struct PerfBuffer *pGpuResource) { + return pGpuResource->__perfbufferGetInternalObjectHandle__(pGpuResource); +} + static inline NV_STATUS perfbufferControl_DISPATCH(struct PerfBuffer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pGpuResource->__perfbufferControl__(pGpuResource, pCallContext, pParams); } @@ -172,68 +224,28 @@ static inline NV_STATUS perfbufferGetMemoryMappingDescriptor_DISPATCH(struct Per return pRmResource->__perfbufferGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS perfbufferGetMapAddrSpace_DISPATCH(struct PerfBuffer *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__perfbufferGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvHandle perfbufferGetInternalObjectHandle_DISPATCH(struct PerfBuffer *pGpuResource) { - return pGpuResource->__perfbufferGetInternalObjectHandle__(pGpuResource); -} - static inline NV_STATUS perfbufferControlFilter_DISPATCH(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__perfbufferControlFilter__(pResource, pCallContext, pParams); } -static inline void perfbufferAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct PerfBuffer *pResource, RsResourceRef *pReference) { - pResource->__perfbufferAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 perfbufferGetRefCount_DISPATCH(struct PerfBuffer *pResource) { - return pResource->__perfbufferGetRefCount__(pResource); -} - -static inline NV_STATUS perfbufferCheckMemInterUnmap_DISPATCH(struct PerfBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__perfbufferCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS perfbufferMapTo_DISPATCH(struct PerfBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__perfbufferMapTo__(pResource, pParams); -} - -static inline NV_STATUS perfbufferControl_Prologue_DISPATCH(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__perfbufferControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS perfbufferGetRegBaseOffsetAndSize_DISPATCH(struct PerfBuffer *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__perfbufferGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +static inline NV_STATUS perfbufferControlSerialization_Prologue_DISPATCH(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__perfbufferControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool perfbufferCanCopy_DISPATCH(struct PerfBuffer *pResource) { return pResource->__perfbufferCanCopy__(pResource); } -static inline NV_STATUS perfbufferInternalControlForward_DISPATCH(struct PerfBuffer *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__perfbufferInternalControlForward__(pGpuResource, command, pParams, size); -} - static inline void perfbufferPreDestruct_DISPATCH(struct PerfBuffer *pResource) { pResource->__perfbufferPreDestruct__(pResource); } -static inline NV_STATUS perfbufferUnmapFrom_DISPATCH(struct PerfBuffer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__perfbufferUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS perfbufferIsDuplicate_DISPATCH(struct PerfBuffer *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__perfbufferIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline void perfbufferControl_Epilogue_DISPATCH(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__perfbufferControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS perfbufferControlLookup_DISPATCH(struct PerfBuffer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__perfbufferControlLookup__(pResource, pParams, ppEntry); +static inline void perfbufferControlSerialization_Epilogue_DISPATCH(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__perfbufferControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS perfbufferMap_DISPATCH(struct PerfBuffer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_kern_pmu_nvoc.c b/src/nvidia/generated/g_kern_pmu_nvoc.c index 662941ab5..d992278c4 100644 --- a/src/nvidia/generated/g_kern_pmu_nvoc.c +++ b/src/nvidia/generated/g_kern_pmu_nvoc.c @@ -17,10 +17,10 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJENGSTATE; -void __nvoc_init_KernelPmu(KernelPmu*, RmHalspecOwner* ); -void __nvoc_init_funcTable_KernelPmu(KernelPmu*, RmHalspecOwner* ); -NV_STATUS __nvoc_ctor_KernelPmu(KernelPmu*, RmHalspecOwner* ); -void __nvoc_init_dataField_KernelPmu(KernelPmu*, RmHalspecOwner* ); +void __nvoc_init_KernelPmu(KernelPmu*); +void __nvoc_init_funcTable_KernelPmu(KernelPmu*); +NV_STATUS __nvoc_ctor_KernelPmu(KernelPmu*); +void __nvoc_init_dataField_KernelPmu(KernelPmu*); void __nvoc_dtor_KernelPmu(KernelPmu*); extern const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelPmu; @@ -74,10 +74,6 @@ static NV_STATUS __nvoc_thunk_KernelPmu_engstateStateInitLocked(struct OBJGPU *p return kpmuStateInitLocked(pGpu, (struct KernelPmu *)(((unsigned char *)pKernelPmu) - __nvoc_rtti_KernelPmu_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kpmuReconcileTunableState(POBJGPU pGpu, struct KernelPmu *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPmu_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kpmuStateLoad(POBJGPU pGpu, struct KernelPmu *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPmu_OBJENGSTATE.offset), arg0); } @@ -118,30 +114,10 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_kpmuStatePreInitUnlocked(POBJGPU pGpu, return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPmu_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kpmuGetTunableState(POBJGPU pGpu, struct KernelPmu *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPmu_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kpmuCompareTunableState(POBJGPU pGpu, struct KernelPmu *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPmu_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kpmuFreeTunableState(POBJGPU pGpu, struct KernelPmu *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPmu_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kpmuStatePostLoad(POBJGPU pGpu, struct KernelPmu *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPmu_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kpmuAllocTunableState(POBJGPU pGpu, struct KernelPmu *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPmu_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kpmuSetTunableState(POBJGPU pGpu, struct KernelPmu *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPmu_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_kpmuIsPresent(POBJGPU pGpu, struct KernelPmu *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPmu_OBJENGSTATE.offset)); } @@ -159,21 +135,16 @@ void __nvoc_dtor_KernelPmu(KernelPmu *pThis) { PORT_UNREFERENCED_VARIABLE(pThis); } -void __nvoc_init_dataField_KernelPmu(KernelPmu *pThis, RmHalspecOwner *pRmhalspecowner) { - ChipHal *chipHal = &pRmhalspecowner->chipHal; - const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; +void __nvoc_init_dataField_KernelPmu(KernelPmu *pThis) { PORT_UNREFERENCED_VARIABLE(pThis); - PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); - PORT_UNREFERENCED_VARIABLE(chipHal); - PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); -NV_STATUS __nvoc_ctor_KernelPmu(KernelPmu *pThis, RmHalspecOwner *pRmhalspecowner) { +NV_STATUS __nvoc_ctor_KernelPmu(KernelPmu *pThis) { NV_STATUS status = NV_OK; status = __nvoc_ctor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); if (status != NV_OK) goto __nvoc_ctor_KernelPmu_fail_OBJENGSTATE; - __nvoc_init_dataField_KernelPmu(pThis, pRmhalspecowner); + __nvoc_init_dataField_KernelPmu(pThis); goto __nvoc_ctor_KernelPmu_exit; // Success __nvoc_ctor_KernelPmu_fail_OBJENGSTATE: @@ -182,35 +153,17 @@ __nvoc_ctor_KernelPmu_exit: return status; } -static void __nvoc_init_funcTable_KernelPmu_1(KernelPmu *pThis, RmHalspecOwner *pRmhalspecowner) { - ChipHal *chipHal = &pRmhalspecowner->chipHal; - const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; +static void __nvoc_init_funcTable_KernelPmu_1(KernelPmu *pThis) { PORT_UNREFERENCED_VARIABLE(pThis); - PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); - PORT_UNREFERENCED_VARIABLE(chipHal); - PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); pThis->__kpmuConstructEngine__ = &kpmuConstructEngine_IMPL; pThis->__kpmuStateInitLocked__ = &kpmuStateInitLocked_IMPL; - // Hal function -- kpmuPreOsGlobalErotGrantRequest - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kpmuPreOsGlobalErotGrantRequest__ = &kpmuPreOsGlobalErotGrantRequest_AD102; - } - // default - else - { - pThis->__kpmuPreOsGlobalErotGrantRequest__ = &kpmuPreOsGlobalErotGrantRequest_56cd7a; - } - pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelPmu_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_KernelPmu_engstateStateInitLocked; - pThis->__kpmuReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kpmuReconcileTunableState; - pThis->__kpmuStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kpmuStateLoad; pThis->__kpmuStateUnload__ = &__nvoc_thunk_OBJENGSTATE_kpmuStateUnload; @@ -231,47 +184,39 @@ static void __nvoc_init_funcTable_KernelPmu_1(KernelPmu *pThis, RmHalspecOwner * pThis->__kpmuStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kpmuStatePreInitUnlocked; - pThis->__kpmuGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kpmuGetTunableState; - - pThis->__kpmuCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kpmuCompareTunableState; - - pThis->__kpmuFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kpmuFreeTunableState; - pThis->__kpmuStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kpmuStatePostLoad; - pThis->__kpmuAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kpmuAllocTunableState; - - pThis->__kpmuSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kpmuSetTunableState; - pThis->__kpmuIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kpmuIsPresent; } -void __nvoc_init_funcTable_KernelPmu(KernelPmu *pThis, RmHalspecOwner *pRmhalspecowner) { - __nvoc_init_funcTable_KernelPmu_1(pThis, pRmhalspecowner); +void __nvoc_init_funcTable_KernelPmu(KernelPmu *pThis) { + __nvoc_init_funcTable_KernelPmu_1(pThis); } void __nvoc_init_OBJENGSTATE(OBJENGSTATE*); -void __nvoc_init_KernelPmu(KernelPmu *pThis, RmHalspecOwner *pRmhalspecowner) { +void __nvoc_init_KernelPmu(KernelPmu *pThis) { pThis->__nvoc_pbase_KernelPmu = pThis; pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object; pThis->__nvoc_pbase_OBJENGSTATE = &pThis->__nvoc_base_OBJENGSTATE; __nvoc_init_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); - __nvoc_init_funcTable_KernelPmu(pThis, pRmhalspecowner); + __nvoc_init_funcTable_KernelPmu(pThis); } NV_STATUS __nvoc_objCreate_KernelPmu(KernelPmu **ppThis, Dynamic *pParent, NvU32 createFlags) { NV_STATUS status; Object *pParentObj; KernelPmu *pThis; - RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelPmu)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelPmu), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelPmu)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelPmu); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -282,20 +227,22 @@ NV_STATUS __nvoc_objCreate_KernelPmu(KernelPmu **ppThis, Dynamic *pParent, NvU32 pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.pParent = NULL; } - if ((pRmhalspecowner = dynamicCast(pParent, RmHalspecOwner)) == NULL) - pRmhalspecowner = objFindAncestorOfType(RmHalspecOwner, pParent); - NV_ASSERT_OR_RETURN(pRmhalspecowner != NULL, NV_ERR_INVALID_ARGUMENT); - - __nvoc_init_KernelPmu(pThis, pRmhalspecowner); - status = __nvoc_ctor_KernelPmu(pThis, pRmhalspecowner); + __nvoc_init_KernelPmu(pThis); + status = __nvoc_ctor_KernelPmu(pThis); if (status != NV_OK) goto __nvoc_objCreate_KernelPmu_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelPmu_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelPmu)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kern_pmu_nvoc.h b/src/nvidia/generated/g_kern_pmu_nvoc.h index c146573e1..d954f7e5c 100644 --- a/src/nvidia/generated/g_kern_pmu_nvoc.h +++ b/src/nvidia/generated/g_kern_pmu_nvoc.h @@ -66,8 +66,6 @@ struct KernelPmu { struct KernelPmu *__nvoc_pbase_KernelPmu; NV_STATUS (*__kpmuConstructEngine__)(struct OBJGPU *, struct KernelPmu *, ENGDESCRIPTOR); NV_STATUS (*__kpmuStateInitLocked__)(struct OBJGPU *, struct KernelPmu *); - NV_STATUS (*__kpmuPreOsGlobalErotGrantRequest__)(struct OBJGPU *, struct KernelPmu *); - NV_STATUS (*__kpmuReconcileTunableState__)(POBJGPU, struct KernelPmu *, void *); NV_STATUS (*__kpmuStateLoad__)(POBJGPU, struct KernelPmu *, NvU32); NV_STATUS (*__kpmuStateUnload__)(POBJGPU, struct KernelPmu *, NvU32); NV_STATUS (*__kpmuStatePreLoad__)(POBJGPU, struct KernelPmu *, NvU32); @@ -78,12 +76,7 @@ struct KernelPmu { void (*__kpmuInitMissing__)(POBJGPU, struct KernelPmu *); NV_STATUS (*__kpmuStatePreInitLocked__)(POBJGPU, struct KernelPmu *); NV_STATUS (*__kpmuStatePreInitUnlocked__)(POBJGPU, struct KernelPmu *); - NV_STATUS (*__kpmuGetTunableState__)(POBJGPU, struct KernelPmu *, void *); - NV_STATUS (*__kpmuCompareTunableState__)(POBJGPU, struct KernelPmu *, void *, void *); - void (*__kpmuFreeTunableState__)(POBJGPU, struct KernelPmu *, void *); NV_STATUS (*__kpmuStatePostLoad__)(POBJGPU, struct KernelPmu *, NvU32); - NV_STATUS (*__kpmuAllocTunableState__)(POBJGPU, struct KernelPmu *, void **); - NV_STATUS (*__kpmuSetTunableState__)(POBJGPU, struct KernelPmu *, void *); NvBool (*__kpmuIsPresent__)(POBJGPU, struct KernelPmu *); LIBOS_LOG_DECODE logDecode; NvU32 printBufSize; @@ -124,9 +117,6 @@ NV_STATUS __nvoc_objCreate_KernelPmu(KernelPmu**, Dynamic*, NvU32); #define kpmuConstructEngine(pGpu, pKernelPmu, engDesc) kpmuConstructEngine_DISPATCH(pGpu, pKernelPmu, engDesc) #define kpmuStateInitLocked(pGpu, pKernelPmu) kpmuStateInitLocked_DISPATCH(pGpu, pKernelPmu) -#define kpmuPreOsGlobalErotGrantRequest(pGpu, pKernelPmu) kpmuPreOsGlobalErotGrantRequest_DISPATCH(pGpu, pKernelPmu) -#define kpmuPreOsGlobalErotGrantRequest_HAL(pGpu, pKernelPmu) kpmuPreOsGlobalErotGrantRequest_DISPATCH(pGpu, pKernelPmu) -#define kpmuReconcileTunableState(pGpu, pEngstate, pTunableState) kpmuReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kpmuStateLoad(pGpu, pEngstate, arg0) kpmuStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kpmuStateUnload(pGpu, pEngstate, arg0) kpmuStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define kpmuStatePreLoad(pGpu, pEngstate, arg0) kpmuStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) @@ -137,12 +127,7 @@ NV_STATUS __nvoc_objCreate_KernelPmu(KernelPmu**, Dynamic*, NvU32); #define kpmuInitMissing(pGpu, pEngstate) kpmuInitMissing_DISPATCH(pGpu, pEngstate) #define kpmuStatePreInitLocked(pGpu, pEngstate) kpmuStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kpmuStatePreInitUnlocked(pGpu, pEngstate) kpmuStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kpmuGetTunableState(pGpu, pEngstate, pTunableState) kpmuGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kpmuCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kpmuCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kpmuFreeTunableState(pGpu, pEngstate, pTunableState) kpmuFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kpmuStatePostLoad(pGpu, pEngstate, arg0) kpmuStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define kpmuAllocTunableState(pGpu, pEngstate, ppTunableState) kpmuAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kpmuSetTunableState(pGpu, pEngstate, pTunableState) kpmuSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kpmuIsPresent(pGpu, pEngstate) kpmuIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS kpmuConstructEngine_IMPL(struct OBJGPU *pGpu, struct KernelPmu *pKernelPmu, ENGDESCRIPTOR engDesc); @@ -156,20 +141,6 @@ static inline NV_STATUS kpmuStateInitLocked_DISPATCH(struct OBJGPU *pGpu, struct return pKernelPmu->__kpmuStateInitLocked__(pGpu, pKernelPmu); } -NV_STATUS kpmuPreOsGlobalErotGrantRequest_AD102(struct OBJGPU *pGpu, struct KernelPmu *pKernelPmu); - -static inline NV_STATUS kpmuPreOsGlobalErotGrantRequest_56cd7a(struct OBJGPU *pGpu, struct KernelPmu *pKernelPmu) { - return NV_OK; -} - -static inline NV_STATUS kpmuPreOsGlobalErotGrantRequest_DISPATCH(struct OBJGPU *pGpu, struct KernelPmu *pKernelPmu) { - return pKernelPmu->__kpmuPreOsGlobalErotGrantRequest__(pGpu, pKernelPmu); -} - -static inline NV_STATUS kpmuReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelPmu *pEngstate, void *pTunableState) { - return pEngstate->__kpmuReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kpmuStateLoad_DISPATCH(POBJGPU pGpu, struct KernelPmu *pEngstate, NvU32 arg0) { return pEngstate->__kpmuStateLoad__(pGpu, pEngstate, arg0); } @@ -210,30 +181,10 @@ static inline NV_STATUS kpmuStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct K return pEngstate->__kpmuStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kpmuGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelPmu *pEngstate, void *pTunableState) { - return pEngstate->__kpmuGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kpmuCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelPmu *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kpmuCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kpmuFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelPmu *pEngstate, void *pTunableState) { - pEngstate->__kpmuFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kpmuStatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelPmu *pEngstate, NvU32 arg0) { return pEngstate->__kpmuStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS kpmuAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelPmu *pEngstate, void **ppTunableState) { - return pEngstate->__kpmuAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kpmuSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelPmu *pEngstate, void *pTunableState) { - return pEngstate->__kpmuSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kpmuIsPresent_DISPATCH(POBJGPU pGpu, struct KernelPmu *pEngstate) { return pEngstate->__kpmuIsPresent__(pGpu, pEngstate); } diff --git a/src/nvidia/generated/g_kernel_bif_nvoc.c b/src/nvidia/generated/g_kernel_bif_nvoc.c index 7370f1ea9..280089ebb 100644 --- a/src/nvidia/generated/g_kernel_bif_nvoc.c +++ b/src/nvidia/generated/g_kernel_bif_nvoc.c @@ -86,10 +86,6 @@ static NV_STATUS __nvoc_thunk_KernelBif_engstateStateUnload(struct OBJGPU *pGpu, return kbifStateUnload(pGpu, (struct KernelBif *)(((unsigned char *)pKernelBif) - __nvoc_rtti_KernelBif_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbifReconcileTunableState(POBJGPU pGpu, struct KernelBif *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBif_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbifStatePreLoad(POBJGPU pGpu, struct KernelBif *pEngstate, NvU32 arg0) { return engstateStatePreLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBif_OBJENGSTATE.offset), arg0); } @@ -122,26 +118,6 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbifStatePreInitUnlocked(POBJGPU pGpu, return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBif_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbifGetTunableState(POBJGPU pGpu, struct KernelBif *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBif_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbifCompareTunableState(POBJGPU pGpu, struct KernelBif *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBif_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kbifFreeTunableState(POBJGPU pGpu, struct KernelBif *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBif_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbifAllocTunableState(POBJGPU pGpu, struct KernelBif *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBif_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbifSetTunableState(POBJGPU pGpu, struct KernelBif *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBif_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_kbifIsPresent(POBJGPU pGpu, struct KernelBif *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBif_OBJENGSTATE.offset)); } @@ -333,7 +309,7 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner * } else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbifVerifyPcieConfigAccessTestRegisters__ = &kbifVerifyPcieConfigAccessTestRegisters_46f6a7; + pThis->__kbifVerifyPcieConfigAccessTestRegisters__ = &kbifVerifyPcieConfigAccessTestRegisters_56cd7a; } } @@ -488,6 +464,17 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner * } } + // Hal function -- kbifEnablePcieAtomics + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifEnablePcieAtomics__ = &kbifEnablePcieAtomics_GH100; + } + // default + else + { + pThis->__kbifEnablePcieAtomics__ = &kbifEnablePcieAtomics_b3696a; + } + // Hal function -- kbifGetPciConfigSpacePriMirror if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { @@ -508,6 +495,17 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner * pThis->__kbifGetBusOptionsAddr__ = &kbifGetBusOptionsAddr_GH100; } + // Hal function -- kbifPreOsGlobalErotGrantRequest + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__kbifPreOsGlobalErotGrantRequest__ = &kbifPreOsGlobalErotGrantRequest_AD102; + } + // default + else + { + pThis->__kbifPreOsGlobalErotGrantRequest__ = &kbifPreOsGlobalErotGrantRequest_56cd7a; + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelBif_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_KernelBif_engstateStateInitLocked; @@ -518,8 +516,6 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner * pThis->__nvoc_base_OBJENGSTATE.__engstateStateUnload__ = &__nvoc_thunk_KernelBif_engstateStateUnload; - pThis->__kbifReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kbifReconcileTunableState; - pThis->__kbifStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_kbifStatePreLoad; pThis->__kbifStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_kbifStatePostUnload; @@ -536,16 +532,6 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner * pThis->__kbifStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kbifStatePreInitUnlocked; - pThis->__kbifGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kbifGetTunableState; - - pThis->__kbifCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kbifCompareTunableState; - - pThis->__kbifFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kbifFreeTunableState; - - pThis->__kbifAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kbifAllocTunableState; - - pThis->__kbifSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kbifSetTunableState; - pThis->__kbifIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kbifIsPresent; } @@ -568,13 +554,16 @@ NV_STATUS __nvoc_objCreate_KernelBif(KernelBif **ppThis, Dynamic *pParent, NvU32 KernelBif *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelBif)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelBif), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelBif)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelBif); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -594,11 +583,17 @@ NV_STATUS __nvoc_objCreate_KernelBif(KernelBif **ppThis, Dynamic *pParent, NvU32 if (status != NV_OK) goto __nvoc_objCreate_KernelBif_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelBif_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelBif)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_bif_nvoc.h b/src/nvidia/generated/g_kernel_bif_nvoc.h index 610b6067d..1b93d9d80 100644 --- a/src/nvidia/generated/g_kernel_bif_nvoc.h +++ b/src/nvidia/generated/g_kernel_bif_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -111,9 +111,10 @@ struct KernelBif { NV_STATUS (*__kbifEnableNoSnoop__)(struct OBJGPU *, struct KernelBif *, NvBool); void (*__kbifApplyWARBug3208922__)(struct OBJGPU *, struct KernelBif *); void (*__kbifProbePcieReqAtomicCaps__)(struct OBJGPU *, struct KernelBif *); + void (*__kbifEnablePcieAtomics__)(struct OBJGPU *, struct KernelBif *); NV_STATUS (*__kbifGetPciConfigSpacePriMirror__)(struct OBJGPU *, struct KernelBif *, NvU32 *, NvU32 *); NV_STATUS (*__kbifGetBusOptionsAddr__)(struct OBJGPU *, struct KernelBif *, BUS_OPTIONS, NvU32 *); - NV_STATUS (*__kbifReconcileTunableState__)(POBJGPU, struct KernelBif *, void *); + NV_STATUS (*__kbifPreOsGlobalErotGrantRequest__)(struct OBJGPU *, struct KernelBif *); NV_STATUS (*__kbifStatePreLoad__)(POBJGPU, struct KernelBif *, NvU32); NV_STATUS (*__kbifStatePostUnload__)(POBJGPU, struct KernelBif *, NvU32); void (*__kbifStateDestroy__)(POBJGPU, struct KernelBif *); @@ -122,11 +123,6 @@ struct KernelBif { void (*__kbifInitMissing__)(POBJGPU, struct KernelBif *); NV_STATUS (*__kbifStatePreInitLocked__)(POBJGPU, struct KernelBif *); NV_STATUS (*__kbifStatePreInitUnlocked__)(POBJGPU, struct KernelBif *); - NV_STATUS (*__kbifGetTunableState__)(POBJGPU, struct KernelBif *, void *); - NV_STATUS (*__kbifCompareTunableState__)(POBJGPU, struct KernelBif *, void *, void *); - void (*__kbifFreeTunableState__)(POBJGPU, struct KernelBif *, void *); - NV_STATUS (*__kbifAllocTunableState__)(POBJGPU, struct KernelBif *, void **); - NV_STATUS (*__kbifSetTunableState__)(POBJGPU, struct KernelBif *, void *); NvBool (*__kbifIsPresent__)(POBJGPU, struct KernelBif *); NvBool PDB_PROP_KBIF_CHECK_IF_GPU_EXISTS_DEF; NvBool PDB_PROP_KBIF_IS_MSI_ENABLED; @@ -142,6 +138,7 @@ struct KernelBif { NvBool PDB_PROP_KBIF_SUPPORT_NONCOHERENT; NvBool PDB_PROP_KBIF_PCIE_GEN4_CAPABLE; NvBool PDB_PROP_KBIF_PCIE_RELAXED_ORDERING_SET_IN_EMULATED_CONFIG_SPACE; + NvBool PDB_PROP_KBIF_SYSTEM_ACCESS_DISABLED; NvU32 dmaCaps; RmPhysAddr dmaWindowStartAddress; NvU32 p2pOverride; @@ -186,6 +183,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelBif; #define PDB_PROP_KBIF_IS_MSI_ENABLED_BASE_NAME PDB_PROP_KBIF_IS_MSI_ENABLED #define PDB_PROP_KBIF_PCIE_RELAXED_ORDERING_SET_IN_EMULATED_CONFIG_SPACE_BASE_CAST #define PDB_PROP_KBIF_PCIE_RELAXED_ORDERING_SET_IN_EMULATED_CONFIG_SPACE_BASE_NAME PDB_PROP_KBIF_PCIE_RELAXED_ORDERING_SET_IN_EMULATED_CONFIG_SPACE +#define PDB_PROP_KBIF_SYSTEM_ACCESS_DISABLED_BASE_CAST +#define PDB_PROP_KBIF_SYSTEM_ACCESS_DISABLED_BASE_NAME PDB_PROP_KBIF_SYSTEM_ACCESS_DISABLED #define PDB_PROP_KBIF_UPSTREAM_LTR_SUPPORT_WAR_BUG_200634944_BASE_CAST #define PDB_PROP_KBIF_UPSTREAM_LTR_SUPPORT_WAR_BUG_200634944_BASE_NAME PDB_PROP_KBIF_UPSTREAM_LTR_SUPPORT_WAR_BUG_200634944 #define PDB_PROP_KBIF_IS_MSIX_CACHED_BASE_CAST @@ -255,11 +254,14 @@ NV_STATUS __nvoc_objCreate_KernelBif(KernelBif**, Dynamic*, NvU32); #define kbifApplyWARBug3208922_HAL(pGpu, pKernelBif) kbifApplyWARBug3208922_DISPATCH(pGpu, pKernelBif) #define kbifProbePcieReqAtomicCaps(pGpu, pKernelBif) kbifProbePcieReqAtomicCaps_DISPATCH(pGpu, pKernelBif) #define kbifProbePcieReqAtomicCaps_HAL(pGpu, pKernelBif) kbifProbePcieReqAtomicCaps_DISPATCH(pGpu, pKernelBif) +#define kbifEnablePcieAtomics(pGpu, pKernelBif) kbifEnablePcieAtomics_DISPATCH(pGpu, pKernelBif) +#define kbifEnablePcieAtomics_HAL(pGpu, pKernelBif) kbifEnablePcieAtomics_DISPATCH(pGpu, pKernelBif) #define kbifGetPciConfigSpacePriMirror(pGpu, pKernelBif, pMirrorBase, pMirrorSize) kbifGetPciConfigSpacePriMirror_DISPATCH(pGpu, pKernelBif, pMirrorBase, pMirrorSize) #define kbifGetPciConfigSpacePriMirror_HAL(pGpu, pKernelBif, pMirrorBase, pMirrorSize) kbifGetPciConfigSpacePriMirror_DISPATCH(pGpu, pKernelBif, pMirrorBase, pMirrorSize) #define kbifGetBusOptionsAddr(pGpu, pKernelBif, options, addrReg) kbifGetBusOptionsAddr_DISPATCH(pGpu, pKernelBif, options, addrReg) #define kbifGetBusOptionsAddr_HAL(pGpu, pKernelBif, options, addrReg) kbifGetBusOptionsAddr_DISPATCH(pGpu, pKernelBif, options, addrReg) -#define kbifReconcileTunableState(pGpu, pEngstate, pTunableState) kbifReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) +#define kbifPreOsGlobalErotGrantRequest(pGpu, pKernelBif) kbifPreOsGlobalErotGrantRequest_DISPATCH(pGpu, pKernelBif) +#define kbifPreOsGlobalErotGrantRequest_HAL(pGpu, pKernelBif) kbifPreOsGlobalErotGrantRequest_DISPATCH(pGpu, pKernelBif) #define kbifStatePreLoad(pGpu, pEngstate, arg0) kbifStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kbifStatePostUnload(pGpu, pEngstate, arg0) kbifStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) #define kbifStateDestroy(pGpu, pEngstate) kbifStateDestroy_DISPATCH(pGpu, pEngstate) @@ -268,11 +270,6 @@ NV_STATUS __nvoc_objCreate_KernelBif(KernelBif**, Dynamic*, NvU32); #define kbifInitMissing(pGpu, pEngstate) kbifInitMissing_DISPATCH(pGpu, pEngstate) #define kbifStatePreInitLocked(pGpu, pEngstate) kbifStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kbifStatePreInitUnlocked(pGpu, pEngstate) kbifStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kbifGetTunableState(pGpu, pEngstate, pTunableState) kbifGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kbifCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kbifCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kbifFreeTunableState(pGpu, pEngstate, pTunableState) kbifFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kbifAllocTunableState(pGpu, pEngstate, ppTunableState) kbifAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kbifSetTunableState(pGpu, pEngstate, pTunableState) kbifSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kbifIsPresent(pGpu, pEngstate) kbifIsPresent_DISPATCH(pGpu, pEngstate) static inline NvU32 kbifGetBusIntfType_2f2c74(struct KernelBif *pKernelBif) { return (3); @@ -357,6 +354,20 @@ static inline NV_STATUS kbifGetVFSparseMmapRegions(struct OBJGPU *pGpu, struct K #define kbifGetVFSparseMmapRegions_HAL(pGpu, pKernelBif, pKernelHostVgpuDevice, os_page_size, offsets, sizes) kbifGetVFSparseMmapRegions(pGpu, pKernelBif, pKernelHostVgpuDevice, os_page_size, offsets, sizes) +NV_STATUS kbifDisableSysmemAccess_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool bDisable); + + +#ifdef __nvoc_kernel_bif_h_disabled +static inline NV_STATUS kbifDisableSysmemAccess(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool bDisable) { + NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_bif_h_disabled +#define kbifDisableSysmemAccess(pGpu, pKernelBif, bDisable) kbifDisableSysmemAccess_GM107(pGpu, pKernelBif, bDisable) +#endif //__nvoc_kernel_bif_h_disabled + +#define kbifDisableSysmemAccess_HAL(pGpu, pKernelBif, bDisable) kbifDisableSysmemAccess(pGpu, pKernelBif, bDisable) + NV_STATUS kbifConstructEngine_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, ENGDESCRIPTOR arg0); static inline NV_STATUS kbifConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, ENGDESCRIPTOR arg0) { @@ -431,8 +442,8 @@ static inline void kbifGetPcieConfigAccessTestRegisters_DISPATCH(struct OBJGPU * NV_STATUS kbifVerifyPcieConfigAccessTestRegisters_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 nvXveId, NvU32 nvXveVccapHdr); -static inline NV_STATUS kbifVerifyPcieConfigAccessTestRegisters_46f6a7(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 nvXveId, NvU32 nvXveVccapHdr) { - return NV_ERR_NOT_SUPPORTED; +static inline NV_STATUS kbifVerifyPcieConfigAccessTestRegisters_56cd7a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 nvXveId, NvU32 nvXveVccapHdr) { + return NV_OK; } static inline NV_STATUS kbifVerifyPcieConfigAccessTestRegisters_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 nvXveId, NvU32 nvXveVccapHdr) { @@ -557,6 +568,16 @@ static inline void kbifProbePcieReqAtomicCaps_DISPATCH(struct OBJGPU *pGpu, stru pKernelBif->__kbifProbePcieReqAtomicCaps__(pGpu, pKernelBif); } +void kbifEnablePcieAtomics_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline void kbifEnablePcieAtomics_b3696a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return; +} + +static inline void kbifEnablePcieAtomics_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + pKernelBif->__kbifEnablePcieAtomics__(pGpu, pKernelBif); +} + NV_STATUS kbifGetPciConfigSpacePriMirror_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pMirrorBase, NvU32 *pMirrorSize); NV_STATUS kbifGetPciConfigSpacePriMirror_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pMirrorBase, NvU32 *pMirrorSize); @@ -573,8 +594,14 @@ static inline NV_STATUS kbifGetBusOptionsAddr_DISPATCH(struct OBJGPU *pGpu, stru return pKernelBif->__kbifGetBusOptionsAddr__(pGpu, pKernelBif, options, addrReg); } -static inline NV_STATUS kbifReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelBif *pEngstate, void *pTunableState) { - return pEngstate->__kbifReconcileTunableState__(pGpu, pEngstate, pTunableState); +NV_STATUS kbifPreOsGlobalErotGrantRequest_AD102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline NV_STATUS kbifPreOsGlobalErotGrantRequest_56cd7a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return NV_OK; +} + +static inline NV_STATUS kbifPreOsGlobalErotGrantRequest_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return pKernelBif->__kbifPreOsGlobalErotGrantRequest__(pGpu, pKernelBif); } static inline NV_STATUS kbifStatePreLoad_DISPATCH(POBJGPU pGpu, struct KernelBif *pEngstate, NvU32 arg0) { @@ -609,26 +636,6 @@ static inline NV_STATUS kbifStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct K return pEngstate->__kbifStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kbifGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelBif *pEngstate, void *pTunableState) { - return pEngstate->__kbifGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kbifCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelBif *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kbifCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kbifFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelBif *pEngstate, void *pTunableState) { - pEngstate->__kbifFreeTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kbifAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelBif *pEngstate, void **ppTunableState) { - return pEngstate->__kbifAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kbifSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelBif *pEngstate, void *pTunableState) { - return pEngstate->__kbifSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kbifIsPresent_DISPATCH(POBJGPU pGpu, struct KernelBif *pEngstate) { return pEngstate->__kbifIsPresent__(pGpu, pEngstate); } @@ -686,6 +693,17 @@ static inline NvBool kbifIsMSIXEnabled(struct OBJGPU *pGpu, struct KernelBif *pK #define kbifIsMSIXEnabled(pGpu, pKernelBif) kbifIsMSIXEnabled_IMPL(pGpu, pKernelBif) #endif //__nvoc_kernel_bif_h_disabled +NV_STATUS kbifPollDeviceOnBus_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +#ifdef __nvoc_kernel_bif_h_disabled +static inline NV_STATUS kbifPollDeviceOnBus(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_bif_h_disabled +#define kbifPollDeviceOnBus(pGpu, pKernelBif) kbifPollDeviceOnBus_IMPL(pGpu, pKernelBif) +#endif //__nvoc_kernel_bif_h_disabled + NvBool kbifIsPciBusFamily_IMPL(struct KernelBif *pKernelBif); #ifdef __nvoc_kernel_bif_h_disabled diff --git a/src/nvidia/generated/g_kernel_ccu_api_nvoc.c b/src/nvidia/generated/g_kernel_ccu_api_nvoc.c index ae582382c..14370bfc9 100644 --- a/src/nvidia/generated/g_kernel_ccu_api_nvoc.c +++ b/src/nvidia/generated/g_kernel_ccu_api_nvoc.c @@ -113,30 +113,6 @@ static NvBool __nvoc_thunk_GpuResource_kccuapiShareCallback(struct KernelCcuApi return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCcuApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuResource_kccuapiControl(struct KernelCcuApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCcuApi_GpuResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_kccuapiGetMemInterMapParams(struct KernelCcuApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelCcuApi_RmResource.offset), pParams); -} - -static NvHandle __nvoc_thunk_GpuResource_kccuapiGetInternalObjectHandle(struct KernelCcuApi *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCcuApi_GpuResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RsResource_kccuapiControlFilter(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset), pCallContext, pParams); -} - -static void __nvoc_thunk_RsResource_kccuapiAddAdditionalDependants(struct RsClient *pClient, struct KernelCcuApi *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_kccuapiGetRefCount(struct KernelCcuApi *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_RmResource_kccuapiCheckMemInterUnmap(struct KernelCcuApi *pRmResource, NvBool bSubdeviceHandleProvided) { return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelCcuApi_RmResource.offset), bSubdeviceHandleProvided); } @@ -145,6 +121,14 @@ static NV_STATUS __nvoc_thunk_RsResource_kccuapiMapTo(struct KernelCcuApi *pReso return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset), pParams); } +static NvU32 __nvoc_thunk_RsResource_kccuapiGetRefCount(struct KernelCcuApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_kccuapiAddAdditionalDependants(struct RsClient *pClient, struct KernelCcuApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset), pReference); +} + static NV_STATUS __nvoc_thunk_RmResource_kccuapiControl_Prologue(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RmResource.offset), pCallContext, pParams); } @@ -153,26 +137,14 @@ static NV_STATUS __nvoc_thunk_GpuResource_kccuapiGetRegBaseOffsetAndSize(struct return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCcuApi_GpuResource.offset), pGpu, pOffset, pSize); } -static NvBool __nvoc_thunk_RsResource_kccuapiCanCopy(struct KernelCcuApi *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_GpuResource_kccuapiInternalControlForward(struct KernelCcuApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCcuApi_GpuResource.offset), command, pParams, size); } -static void __nvoc_thunk_RsResource_kccuapiPreDestruct(struct KernelCcuApi *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_kccuapiUnmapFrom(struct KernelCcuApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RsResource_kccuapiIsDuplicate(struct KernelCcuApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset), hMemory, pDuplicate); -} - static void __nvoc_thunk_RmResource_kccuapiControl_Epilogue(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RmResource.offset), pCallContext, pParams); } @@ -181,6 +153,42 @@ static NV_STATUS __nvoc_thunk_RsResource_kccuapiControlLookup(struct KernelCcuAp return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset), pParams, ppEntry); } +static NvHandle __nvoc_thunk_GpuResource_kccuapiGetInternalObjectHandle(struct KernelCcuApi *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCcuApi_GpuResource.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_kccuapiControl(struct KernelCcuApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCcuApi_GpuResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_kccuapiGetMemInterMapParams(struct KernelCcuApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelCcuApi_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_kccuapiControlFilter(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_kccuapiControlSerialization_Prologue(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_RsResource_kccuapiCanCopy(struct KernelCcuApi *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_kccuapiPreDestruct(struct KernelCcuApi *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_kccuapiIsDuplicate(struct KernelCcuApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_kccuapiControlSerialization_Epilogue(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RmResource_kccuapiAccessCallback(struct KernelCcuApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RmResource.offset), pInvokingClient, pAllocParams, accessRight); } @@ -327,40 +335,44 @@ static void __nvoc_init_funcTable_KernelCcuApi_1(KernelCcuApi *pThis) { pThis->__kccuapiShareCallback__ = &__nvoc_thunk_GpuResource_kccuapiShareCallback; - pThis->__kccuapiControl__ = &__nvoc_thunk_GpuResource_kccuapiControl; - - pThis->__kccuapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_kccuapiGetMemInterMapParams; - - pThis->__kccuapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_kccuapiGetInternalObjectHandle; - - pThis->__kccuapiControlFilter__ = &__nvoc_thunk_RsResource_kccuapiControlFilter; - - pThis->__kccuapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_kccuapiAddAdditionalDependants; - - pThis->__kccuapiGetRefCount__ = &__nvoc_thunk_RsResource_kccuapiGetRefCount; - pThis->__kccuapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_kccuapiCheckMemInterUnmap; pThis->__kccuapiMapTo__ = &__nvoc_thunk_RsResource_kccuapiMapTo; + pThis->__kccuapiGetRefCount__ = &__nvoc_thunk_RsResource_kccuapiGetRefCount; + + pThis->__kccuapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_kccuapiAddAdditionalDependants; + pThis->__kccuapiControl_Prologue__ = &__nvoc_thunk_RmResource_kccuapiControl_Prologue; pThis->__kccuapiGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_kccuapiGetRegBaseOffsetAndSize; - pThis->__kccuapiCanCopy__ = &__nvoc_thunk_RsResource_kccuapiCanCopy; - pThis->__kccuapiInternalControlForward__ = &__nvoc_thunk_GpuResource_kccuapiInternalControlForward; - pThis->__kccuapiPreDestruct__ = &__nvoc_thunk_RsResource_kccuapiPreDestruct; - pThis->__kccuapiUnmapFrom__ = &__nvoc_thunk_RsResource_kccuapiUnmapFrom; - pThis->__kccuapiIsDuplicate__ = &__nvoc_thunk_RsResource_kccuapiIsDuplicate; - pThis->__kccuapiControl_Epilogue__ = &__nvoc_thunk_RmResource_kccuapiControl_Epilogue; pThis->__kccuapiControlLookup__ = &__nvoc_thunk_RsResource_kccuapiControlLookup; + pThis->__kccuapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_kccuapiGetInternalObjectHandle; + + pThis->__kccuapiControl__ = &__nvoc_thunk_GpuResource_kccuapiControl; + + pThis->__kccuapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_kccuapiGetMemInterMapParams; + + pThis->__kccuapiControlFilter__ = &__nvoc_thunk_RsResource_kccuapiControlFilter; + + pThis->__kccuapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_kccuapiControlSerialization_Prologue; + + pThis->__kccuapiCanCopy__ = &__nvoc_thunk_RsResource_kccuapiCanCopy; + + pThis->__kccuapiPreDestruct__ = &__nvoc_thunk_RsResource_kccuapiPreDestruct; + + pThis->__kccuapiIsDuplicate__ = &__nvoc_thunk_RsResource_kccuapiIsDuplicate; + + pThis->__kccuapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_kccuapiControlSerialization_Epilogue; + pThis->__kccuapiAccessCallback__ = &__nvoc_thunk_RmResource_kccuapiAccessCallback; } @@ -385,13 +397,16 @@ NV_STATUS __nvoc_objCreate_KernelCcuApi(KernelCcuApi **ppThis, Dynamic *pParent, Object *pParentObj; KernelCcuApi *pThis; - pThis = portMemAllocNonPaged(sizeof(KernelCcuApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelCcuApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelCcuApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelCcuApi); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -407,11 +422,17 @@ NV_STATUS __nvoc_objCreate_KernelCcuApi(KernelCcuApi **ppThis, Dynamic *pParent, if (status != NV_OK) goto __nvoc_objCreate_KernelCcuApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelCcuApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelCcuApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_ccu_api_nvoc.h b/src/nvidia/generated/g_kernel_ccu_api_nvoc.h index e3152677d..e20c17689 100644 --- a/src/nvidia/generated/g_kernel_ccu_api_nvoc.h +++ b/src/nvidia/generated/g_kernel_ccu_api_nvoc.h @@ -66,23 +66,25 @@ struct KernelCcuApi { NV_STATUS (*__kccuapiCtrlCmdSetStreamState__)(struct KernelCcuApi *, NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS *); NV_STATUS (*__kccuapiCtrlCmdGetStreamState__)(struct KernelCcuApi *, NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS *); NvBool (*__kccuapiShareCallback__)(struct KernelCcuApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__kccuapiControl__)(struct KernelCcuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__kccuapiGetMemInterMapParams__)(struct KernelCcuApi *, RMRES_MEM_INTER_MAP_PARAMS *); - NvHandle (*__kccuapiGetInternalObjectHandle__)(struct KernelCcuApi *); - NV_STATUS (*__kccuapiControlFilter__)(struct KernelCcuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__kccuapiAddAdditionalDependants__)(struct RsClient *, struct KernelCcuApi *, RsResourceRef *); - NvU32 (*__kccuapiGetRefCount__)(struct KernelCcuApi *); NV_STATUS (*__kccuapiCheckMemInterUnmap__)(struct KernelCcuApi *, NvBool); NV_STATUS (*__kccuapiMapTo__)(struct KernelCcuApi *, RS_RES_MAP_TO_PARAMS *); + NvU32 (*__kccuapiGetRefCount__)(struct KernelCcuApi *); + void (*__kccuapiAddAdditionalDependants__)(struct RsClient *, struct KernelCcuApi *, RsResourceRef *); NV_STATUS (*__kccuapiControl_Prologue__)(struct KernelCcuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kccuapiGetRegBaseOffsetAndSize__)(struct KernelCcuApi *, struct OBJGPU *, NvU32 *, NvU32 *); - NvBool (*__kccuapiCanCopy__)(struct KernelCcuApi *); NV_STATUS (*__kccuapiInternalControlForward__)(struct KernelCcuApi *, NvU32, void *, NvU32); - void (*__kccuapiPreDestruct__)(struct KernelCcuApi *); NV_STATUS (*__kccuapiUnmapFrom__)(struct KernelCcuApi *, RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__kccuapiIsDuplicate__)(struct KernelCcuApi *, NvHandle, NvBool *); void (*__kccuapiControl_Epilogue__)(struct KernelCcuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kccuapiControlLookup__)(struct KernelCcuApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__kccuapiGetInternalObjectHandle__)(struct KernelCcuApi *); + NV_STATUS (*__kccuapiControl__)(struct KernelCcuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kccuapiGetMemInterMapParams__)(struct KernelCcuApi *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__kccuapiControlFilter__)(struct KernelCcuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kccuapiControlSerialization_Prologue__)(struct KernelCcuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__kccuapiCanCopy__)(struct KernelCcuApi *); + void (*__kccuapiPreDestruct__)(struct KernelCcuApi *); + NV_STATUS (*__kccuapiIsDuplicate__)(struct KernelCcuApi *, NvHandle, NvBool *); + void (*__kccuapiControlSerialization_Epilogue__)(struct KernelCcuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__kccuapiAccessCallback__)(struct KernelCcuApi *, struct RsClient *, void *, RsAccessRight); }; @@ -123,23 +125,25 @@ NV_STATUS __nvoc_objCreate_KernelCcuApi(KernelCcuApi**, Dynamic*, NvU32, struct #define kccuapiCtrlCmdSetStreamState(pKernelCcuApi, pParams) kccuapiCtrlCmdSetStreamState_DISPATCH(pKernelCcuApi, pParams) #define kccuapiCtrlCmdGetStreamState(pKernelCcuApi, pParams) kccuapiCtrlCmdGetStreamState_DISPATCH(pKernelCcuApi, pParams) #define kccuapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) kccuapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define kccuapiControl(pGpuResource, pCallContext, pParams) kccuapiControl_DISPATCH(pGpuResource, pCallContext, pParams) -#define kccuapiGetMemInterMapParams(pRmResource, pParams) kccuapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define kccuapiGetInternalObjectHandle(pGpuResource) kccuapiGetInternalObjectHandle_DISPATCH(pGpuResource) -#define kccuapiControlFilter(pResource, pCallContext, pParams) kccuapiControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define kccuapiAddAdditionalDependants(pClient, pResource, pReference) kccuapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define kccuapiGetRefCount(pResource) kccuapiGetRefCount_DISPATCH(pResource) #define kccuapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) kccuapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define kccuapiMapTo(pResource, pParams) kccuapiMapTo_DISPATCH(pResource, pParams) +#define kccuapiGetRefCount(pResource) kccuapiGetRefCount_DISPATCH(pResource) +#define kccuapiAddAdditionalDependants(pClient, pResource, pReference) kccuapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define kccuapiControl_Prologue(pResource, pCallContext, pParams) kccuapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define kccuapiGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) kccuapiGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) -#define kccuapiCanCopy(pResource) kccuapiCanCopy_DISPATCH(pResource) #define kccuapiInternalControlForward(pGpuResource, command, pParams, size) kccuapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) -#define kccuapiPreDestruct(pResource) kccuapiPreDestruct_DISPATCH(pResource) #define kccuapiUnmapFrom(pResource, pParams) kccuapiUnmapFrom_DISPATCH(pResource, pParams) -#define kccuapiIsDuplicate(pResource, hMemory, pDuplicate) kccuapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define kccuapiControl_Epilogue(pResource, pCallContext, pParams) kccuapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define kccuapiControlLookup(pResource, pParams, ppEntry) kccuapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define kccuapiGetInternalObjectHandle(pGpuResource) kccuapiGetInternalObjectHandle_DISPATCH(pGpuResource) +#define kccuapiControl(pGpuResource, pCallContext, pParams) kccuapiControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define kccuapiGetMemInterMapParams(pRmResource, pParams) kccuapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define kccuapiControlFilter(pResource, pCallContext, pParams) kccuapiControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define kccuapiControlSerialization_Prologue(pResource, pCallContext, pParams) kccuapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define kccuapiCanCopy(pResource) kccuapiCanCopy_DISPATCH(pResource) +#define kccuapiPreDestruct(pResource) kccuapiPreDestruct_DISPATCH(pResource) +#define kccuapiIsDuplicate(pResource, hMemory, pDuplicate) kccuapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define kccuapiControlSerialization_Epilogue(pResource, pCallContext, pParams) kccuapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define kccuapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) kccuapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS kccuapiMap_IMPL(struct KernelCcuApi *pKernelCcuApi, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping); @@ -193,30 +197,6 @@ static inline NvBool kccuapiShareCallback_DISPATCH(struct KernelCcuApi *pGpuReso return pGpuResource->__kccuapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS kccuapiControl_DISPATCH(struct KernelCcuApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pGpuResource->__kccuapiControl__(pGpuResource, pCallContext, pParams); -} - -static inline NV_STATUS kccuapiGetMemInterMapParams_DISPATCH(struct KernelCcuApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__kccuapiGetMemInterMapParams__(pRmResource, pParams); -} - -static inline NvHandle kccuapiGetInternalObjectHandle_DISPATCH(struct KernelCcuApi *pGpuResource) { - return pGpuResource->__kccuapiGetInternalObjectHandle__(pGpuResource); -} - -static inline NV_STATUS kccuapiControlFilter_DISPATCH(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__kccuapiControlFilter__(pResource, pCallContext, pParams); -} - -static inline void kccuapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct KernelCcuApi *pResource, RsResourceRef *pReference) { - pResource->__kccuapiAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 kccuapiGetRefCount_DISPATCH(struct KernelCcuApi *pResource) { - return pResource->__kccuapiGetRefCount__(pResource); -} - static inline NV_STATUS kccuapiCheckMemInterUnmap_DISPATCH(struct KernelCcuApi *pRmResource, NvBool bSubdeviceHandleProvided) { return pRmResource->__kccuapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } @@ -225,6 +205,14 @@ static inline NV_STATUS kccuapiMapTo_DISPATCH(struct KernelCcuApi *pResource, RS return pResource->__kccuapiMapTo__(pResource, pParams); } +static inline NvU32 kccuapiGetRefCount_DISPATCH(struct KernelCcuApi *pResource) { + return pResource->__kccuapiGetRefCount__(pResource); +} + +static inline void kccuapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct KernelCcuApi *pResource, RsResourceRef *pReference) { + pResource->__kccuapiAddAdditionalDependants__(pClient, pResource, pReference); +} + static inline NV_STATUS kccuapiControl_Prologue_DISPATCH(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__kccuapiControl_Prologue__(pResource, pCallContext, pParams); } @@ -233,26 +221,14 @@ static inline NV_STATUS kccuapiGetRegBaseOffsetAndSize_DISPATCH(struct KernelCcu return pGpuResource->__kccuapiGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); } -static inline NvBool kccuapiCanCopy_DISPATCH(struct KernelCcuApi *pResource) { - return pResource->__kccuapiCanCopy__(pResource); -} - static inline NV_STATUS kccuapiInternalControlForward_DISPATCH(struct KernelCcuApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { return pGpuResource->__kccuapiInternalControlForward__(pGpuResource, command, pParams, size); } -static inline void kccuapiPreDestruct_DISPATCH(struct KernelCcuApi *pResource) { - pResource->__kccuapiPreDestruct__(pResource); -} - static inline NV_STATUS kccuapiUnmapFrom_DISPATCH(struct KernelCcuApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__kccuapiUnmapFrom__(pResource, pParams); } -static inline NV_STATUS kccuapiIsDuplicate_DISPATCH(struct KernelCcuApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return pResource->__kccuapiIsDuplicate__(pResource, hMemory, pDuplicate); -} - static inline void kccuapiControl_Epilogue_DISPATCH(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__kccuapiControl_Epilogue__(pResource, pCallContext, pParams); } @@ -261,6 +237,42 @@ static inline NV_STATUS kccuapiControlLookup_DISPATCH(struct KernelCcuApi *pReso return pResource->__kccuapiControlLookup__(pResource, pParams, ppEntry); } +static inline NvHandle kccuapiGetInternalObjectHandle_DISPATCH(struct KernelCcuApi *pGpuResource) { + return pGpuResource->__kccuapiGetInternalObjectHandle__(pGpuResource); +} + +static inline NV_STATUS kccuapiControl_DISPATCH(struct KernelCcuApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__kccuapiControl__(pGpuResource, pCallContext, pParams); +} + +static inline NV_STATUS kccuapiGetMemInterMapParams_DISPATCH(struct KernelCcuApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__kccuapiGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS kccuapiControlFilter_DISPATCH(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__kccuapiControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS kccuapiControlSerialization_Prologue_DISPATCH(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__kccuapiControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool kccuapiCanCopy_DISPATCH(struct KernelCcuApi *pResource) { + return pResource->__kccuapiCanCopy__(pResource); +} + +static inline void kccuapiPreDestruct_DISPATCH(struct KernelCcuApi *pResource) { + pResource->__kccuapiPreDestruct__(pResource); +} + +static inline NV_STATUS kccuapiIsDuplicate_DISPATCH(struct KernelCcuApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__kccuapiIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void kccuapiControlSerialization_Epilogue_DISPATCH(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__kccuapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline NvBool kccuapiAccessCallback_DISPATCH(struct KernelCcuApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { return pResource->__kccuapiAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); } diff --git a/src/nvidia/generated/g_kernel_ccu_nvoc.c b/src/nvidia/generated/g_kernel_ccu_nvoc.c index 2e5def272..e77ee50ec 100644 --- a/src/nvidia/generated/g_kernel_ccu_nvoc.c +++ b/src/nvidia/generated/g_kernel_ccu_nvoc.c @@ -78,10 +78,6 @@ static NV_STATUS __nvoc_thunk_KernelCcu_engstateStateUnload(OBJGPU *arg0, struct return kccuStateUnload(arg0, (struct KernelCcu *)(((unsigned char *)arg1) - __nvoc_rtti_KernelCcu_OBJENGSTATE.offset), flags); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kccuReconcileTunableState(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kccuStateInitLocked(POBJGPU pGpu, struct KernelCcu *pEngstate) { return engstateStateInitLocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset)); } @@ -118,30 +114,10 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_kccuStatePreInitUnlocked(POBJGPU pGpu, return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kccuGetTunableState(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kccuCompareTunableState(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kccuFreeTunableState(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kccuStatePostLoad(POBJGPU pGpu, struct KernelCcu *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kccuAllocTunableState(POBJGPU pGpu, struct KernelCcu *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kccuSetTunableState(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_kccuIsPresent(POBJGPU pGpu, struct KernelCcu *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCcu_OBJENGSTATE.offset)); } @@ -225,8 +201,6 @@ static void __nvoc_init_funcTable_KernelCcu_1(KernelCcu *pThis, RmHalspecOwner * pThis->__nvoc_base_OBJENGSTATE.__engstateStateUnload__ = &__nvoc_thunk_KernelCcu_engstateStateUnload; - pThis->__kccuReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kccuReconcileTunableState; - pThis->__kccuStateInitLocked__ = &__nvoc_thunk_OBJENGSTATE_kccuStateInitLocked; pThis->__kccuStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_kccuStatePreLoad; @@ -245,18 +219,8 @@ static void __nvoc_init_funcTable_KernelCcu_1(KernelCcu *pThis, RmHalspecOwner * pThis->__kccuStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kccuStatePreInitUnlocked; - pThis->__kccuGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kccuGetTunableState; - - pThis->__kccuCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kccuCompareTunableState; - - pThis->__kccuFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kccuFreeTunableState; - pThis->__kccuStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kccuStatePostLoad; - pThis->__kccuAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kccuAllocTunableState; - - pThis->__kccuSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kccuSetTunableState; - pThis->__kccuIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kccuIsPresent; } @@ -279,13 +243,16 @@ NV_STATUS __nvoc_objCreate_KernelCcu(KernelCcu **ppThis, Dynamic *pParent, NvU32 KernelCcu *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelCcu)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelCcu), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelCcu)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelCcu); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -305,11 +272,17 @@ NV_STATUS __nvoc_objCreate_KernelCcu(KernelCcu **ppThis, Dynamic *pParent, NvU32 if (status != NV_OK) goto __nvoc_objCreate_KernelCcu_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelCcu_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelCcu)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_ccu_nvoc.h b/src/nvidia/generated/g_kernel_ccu_nvoc.h index b033f283e..634ee2fe1 100644 --- a/src/nvidia/generated/g_kernel_ccu_nvoc.h +++ b/src/nvidia/generated/g_kernel_ccu_nvoc.h @@ -117,7 +117,6 @@ struct KernelCcu { NV_STATUS (*__kccuStateLoad__)(OBJGPU *, struct KernelCcu *, NvU32); NV_STATUS (*__kccuStateUnload__)(OBJGPU *, struct KernelCcu *, NvU32); NV_STATUS (*__kccuMigShrBufHandler__)(OBJGPU *, struct KernelCcu *, NvBool); - NV_STATUS (*__kccuReconcileTunableState__)(POBJGPU, struct KernelCcu *, void *); NV_STATUS (*__kccuStateInitLocked__)(POBJGPU, struct KernelCcu *); NV_STATUS (*__kccuStatePreLoad__)(POBJGPU, struct KernelCcu *, NvU32); NV_STATUS (*__kccuStatePostUnload__)(POBJGPU, struct KernelCcu *, NvU32); @@ -127,12 +126,7 @@ struct KernelCcu { void (*__kccuInitMissing__)(POBJGPU, struct KernelCcu *); NV_STATUS (*__kccuStatePreInitLocked__)(POBJGPU, struct KernelCcu *); NV_STATUS (*__kccuStatePreInitUnlocked__)(POBJGPU, struct KernelCcu *); - NV_STATUS (*__kccuGetTunableState__)(POBJGPU, struct KernelCcu *, void *); - NV_STATUS (*__kccuCompareTunableState__)(POBJGPU, struct KernelCcu *, void *, void *); - void (*__kccuFreeTunableState__)(POBJGPU, struct KernelCcu *, void *); NV_STATUS (*__kccuStatePostLoad__)(POBJGPU, struct KernelCcu *, NvU32); - NV_STATUS (*__kccuAllocTunableState__)(POBJGPU, struct KernelCcu *, void **); - NV_STATUS (*__kccuSetTunableState__)(POBJGPU, struct KernelCcu *, void *); NvBool (*__kccuIsPresent__)(POBJGPU, struct KernelCcu *); MEMORY_DESCRIPTOR *pMemDesc[9]; NvBool bStreamState; @@ -176,7 +170,6 @@ NV_STATUS __nvoc_objCreate_KernelCcu(KernelCcu**, Dynamic*, NvU32); #define kccuStateUnload(arg0, arg1, flags) kccuStateUnload_DISPATCH(arg0, arg1, flags) #define kccuMigShrBufHandler(arg0, arg1, bMigEnabled) kccuMigShrBufHandler_DISPATCH(arg0, arg1, bMigEnabled) #define kccuMigShrBufHandler_HAL(arg0, arg1, bMigEnabled) kccuMigShrBufHandler_DISPATCH(arg0, arg1, bMigEnabled) -#define kccuReconcileTunableState(pGpu, pEngstate, pTunableState) kccuReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kccuStateInitLocked(pGpu, pEngstate) kccuStateInitLocked_DISPATCH(pGpu, pEngstate) #define kccuStatePreLoad(pGpu, pEngstate, arg0) kccuStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kccuStatePostUnload(pGpu, pEngstate, arg0) kccuStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) @@ -186,12 +179,7 @@ NV_STATUS __nvoc_objCreate_KernelCcu(KernelCcu**, Dynamic*, NvU32); #define kccuInitMissing(pGpu, pEngstate) kccuInitMissing_DISPATCH(pGpu, pEngstate) #define kccuStatePreInitLocked(pGpu, pEngstate) kccuStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kccuStatePreInitUnlocked(pGpu, pEngstate) kccuStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kccuGetTunableState(pGpu, pEngstate, pTunableState) kccuGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kccuCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kccuCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kccuFreeTunableState(pGpu, pEngstate, pTunableState) kccuFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kccuStatePostLoad(pGpu, pEngstate, arg0) kccuStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define kccuAllocTunableState(pGpu, pEngstate, ppTunableState) kccuAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kccuSetTunableState(pGpu, pEngstate, pTunableState) kccuSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kccuIsPresent(pGpu, pEngstate) kccuIsPresent_DISPATCH(pGpu, pEngstate) void kccuDestruct_IMPL(struct KernelCcu *arg0); @@ -225,10 +213,6 @@ static inline NV_STATUS kccuMigShrBufHandler_DISPATCH(OBJGPU *arg0, struct Kerne return arg1->__kccuMigShrBufHandler__(arg0, arg1, bMigEnabled); } -static inline NV_STATUS kccuReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunableState) { - return pEngstate->__kccuReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kccuStateInitLocked_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate) { return pEngstate->__kccuStateInitLocked__(pGpu, pEngstate); } @@ -265,30 +249,10 @@ static inline NV_STATUS kccuStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct K return pEngstate->__kccuStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kccuGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunableState) { - return pEngstate->__kccuGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kccuCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kccuCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kccuFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunableState) { - pEngstate->__kccuFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kccuStatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate, NvU32 arg0) { return pEngstate->__kccuStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS kccuAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate, void **ppTunableState) { - return pEngstate->__kccuAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kccuSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunableState) { - return pEngstate->__kccuSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kccuIsPresent_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate) { return pEngstate->__kccuIsPresent__(pGpu, pEngstate); } diff --git a/src/nvidia/generated/g_kernel_ce_context_nvoc.c b/src/nvidia/generated/g_kernel_ce_context_nvoc.c index 78a7be16f..aa39ddc1b 100644 --- a/src/nvidia/generated/g_kernel_ce_context_nvoc.c +++ b/src/nvidia/generated/g_kernel_ce_context_nvoc.c @@ -176,7 +176,7 @@ static NV_STATUS __nvoc_thunk_RsResource_kcectxControlLookup(struct KernelCeCont return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCeContext_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_ChannelDescendant_kcectxGetSwMethods(struct KernelCeContext *pChannelDescendant, METHOD **ppMethods, NvU32 *pNumMethods) { +static NV_STATUS __nvoc_thunk_ChannelDescendant_kcectxGetSwMethods(struct KernelCeContext *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return chandesGetSwMethods((struct ChannelDescendant *)(((unsigned char *)pChannelDescendant) + __nvoc_rtti_KernelCeContext_ChannelDescendant.offset), ppMethods, pNumMethods); } @@ -212,6 +212,10 @@ static NV_STATUS __nvoc_thunk_Notifier_kcectxUnregisterEvent(struct KernelCeCont return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelCeContext_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_kcectxControlSerialization_Prologue(struct KernelCeContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCeContext_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_kcectxCanCopy(struct KernelCeContext *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCeContext_RsResource.offset)); } @@ -224,6 +228,10 @@ static NV_STATUS __nvoc_thunk_RsResource_kcectxIsDuplicate(struct KernelCeContex return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCeContext_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_kcectxControlSerialization_Epilogue(struct KernelCeContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCeContext_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_kcectxGetNotificationListPtr(struct KernelCeContext *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelCeContext_Notifier.offset)); } @@ -325,12 +333,16 @@ static void __nvoc_init_funcTable_KernelCeContext_1(KernelCeContext *pThis) { pThis->__kcectxUnregisterEvent__ = &__nvoc_thunk_Notifier_kcectxUnregisterEvent; + pThis->__kcectxControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_kcectxControlSerialization_Prologue; + pThis->__kcectxCanCopy__ = &__nvoc_thunk_RsResource_kcectxCanCopy; pThis->__kcectxPreDestruct__ = &__nvoc_thunk_RsResource_kcectxPreDestruct; pThis->__kcectxIsDuplicate__ = &__nvoc_thunk_RsResource_kcectxIsDuplicate; + pThis->__kcectxControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_kcectxControlSerialization_Epilogue; + pThis->__kcectxGetNotificationListPtr__ = &__nvoc_thunk_Notifier_kcectxGetNotificationListPtr; pThis->__kcectxGetNotificationShare__ = &__nvoc_thunk_Notifier_kcectxGetNotificationShare; @@ -365,13 +377,16 @@ NV_STATUS __nvoc_objCreate_KernelCeContext(KernelCeContext **ppThis, Dynamic *pP KernelCeContext *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelCeContext)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelCeContext), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelCeContext)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelCeContext); + pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -391,11 +406,17 @@ NV_STATUS __nvoc_objCreate_KernelCeContext(KernelCeContext **ppThis, Dynamic *pP if (status != NV_OK) goto __nvoc_objCreate_KernelCeContext_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelCeContext_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelCeContext)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_ce_context_nvoc.h b/src/nvidia/generated/g_kernel_ce_context_nvoc.h index e24415f1d..d418a73b5 100644 --- a/src/nvidia/generated/g_kernel_ce_context_nvoc.h +++ b/src/nvidia/generated/g_kernel_ce_context_nvoc.h @@ -76,7 +76,7 @@ struct KernelCeContext { NV_STATUS (*__kcectxUnmapFrom__)(struct KernelCeContext *, RS_RES_UNMAP_FROM_PARAMS *); void (*__kcectxControl_Epilogue__)(struct KernelCeContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kcectxControlLookup__)(struct KernelCeContext *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); - NV_STATUS (*__kcectxGetSwMethods__)(struct KernelCeContext *, METHOD **, NvU32 *); + NV_STATUS (*__kcectxGetSwMethods__)(struct KernelCeContext *, const METHOD **, NvU32 *); NvHandle (*__kcectxGetInternalObjectHandle__)(struct KernelCeContext *); NV_STATUS (*__kcectxControl__)(struct KernelCeContext *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kcectxUnmap__)(struct KernelCeContext *, CALL_CONTEXT *, RsCpuMapping *); @@ -85,9 +85,11 @@ struct KernelCeContext { NvBool (*__kcectxIsSwMethodStalling__)(struct KernelCeContext *, NvU32); NV_STATUS (*__kcectxControlFilter__)(struct KernelCeContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kcectxUnregisterEvent__)(struct KernelCeContext *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__kcectxControlSerialization_Prologue__)(struct KernelCeContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__kcectxCanCopy__)(struct KernelCeContext *); void (*__kcectxPreDestruct__)(struct KernelCeContext *); NV_STATUS (*__kcectxIsDuplicate__)(struct KernelCeContext *, NvHandle, NvBool *); + void (*__kcectxControlSerialization_Epilogue__)(struct KernelCeContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__kcectxGetNotificationListPtr__)(struct KernelCeContext *); struct NotifShare *(*__kcectxGetNotificationShare__)(struct KernelCeContext *); NV_STATUS (*__kcectxMap__)(struct KernelCeContext *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -145,9 +147,11 @@ NV_STATUS __nvoc_objCreate_KernelCeContext(KernelCeContext**, Dynamic*, NvU32, C #define kcectxIsSwMethodStalling(pChannelDescendant, hHandle) kcectxIsSwMethodStalling_DISPATCH(pChannelDescendant, hHandle) #define kcectxControlFilter(pResource, pCallContext, pParams) kcectxControlFilter_DISPATCH(pResource, pCallContext, pParams) #define kcectxUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) kcectxUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define kcectxControlSerialization_Prologue(pResource, pCallContext, pParams) kcectxControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define kcectxCanCopy(pResource) kcectxCanCopy_DISPATCH(pResource) #define kcectxPreDestruct(pResource) kcectxPreDestruct_DISPATCH(pResource) #define kcectxIsDuplicate(pResource, hMemory, pDuplicate) kcectxIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define kcectxControlSerialization_Epilogue(pResource, pCallContext, pParams) kcectxControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define kcectxGetNotificationListPtr(pNotifier) kcectxGetNotificationListPtr_DISPATCH(pNotifier) #define kcectxGetNotificationShare(pNotifier) kcectxGetNotificationShare_DISPATCH(pNotifier) #define kcectxMap(pGpuResource, pCallContext, pParams, pCpuMapping) kcectxMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -208,7 +212,7 @@ static inline NV_STATUS kcectxControlLookup_DISPATCH(struct KernelCeContext *pRe return pResource->__kcectxControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS kcectxGetSwMethods_DISPATCH(struct KernelCeContext *pChannelDescendant, METHOD **ppMethods, NvU32 *pNumMethods) { +static inline NV_STATUS kcectxGetSwMethods_DISPATCH(struct KernelCeContext *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return pChannelDescendant->__kcectxGetSwMethods__(pChannelDescendant, ppMethods, pNumMethods); } @@ -244,6 +248,10 @@ static inline NV_STATUS kcectxUnregisterEvent_DISPATCH(struct KernelCeContext *p return pNotifier->__kcectxUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS kcectxControlSerialization_Prologue_DISPATCH(struct KernelCeContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__kcectxControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool kcectxCanCopy_DISPATCH(struct KernelCeContext *pResource) { return pResource->__kcectxCanCopy__(pResource); } @@ -256,6 +264,10 @@ static inline NV_STATUS kcectxIsDuplicate_DISPATCH(struct KernelCeContext *pReso return pResource->__kcectxIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void kcectxControlSerialization_Epilogue_DISPATCH(struct KernelCeContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__kcectxControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *kcectxGetNotificationListPtr_DISPATCH(struct KernelCeContext *pNotifier) { return pNotifier->__kcectxGetNotificationListPtr__(pNotifier); } diff --git a/src/nvidia/generated/g_kernel_ce_nvoc.c b/src/nvidia/generated/g_kernel_ce_nvoc.c index e9e792e20..4a2beca94 100644 --- a/src/nvidia/generated/g_kernel_ce_nvoc.c +++ b/src/nvidia/generated/g_kernel_ce_nvoc.c @@ -87,7 +87,11 @@ static NV_STATUS __nvoc_thunk_KernelCE_engstateStateLoad(OBJGPU *arg0, struct OB return kceStateLoad(arg0, (struct KernelCE *)(((unsigned char *)arg1) - __nvoc_rtti_KernelCE_OBJENGSTATE.offset), arg2); } -static void __nvoc_thunk_KernelCE_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[163]) { +static NV_STATUS __nvoc_thunk_KernelCE_engstateStateUnload(OBJGPU *pGpu, struct OBJENGSTATE *pKCe, NvU32 flags) { + return kceStateUnload(pGpu, (struct KernelCE *)(((unsigned char *)pKCe) - __nvoc_rtti_KernelCE_OBJENGSTATE.offset), flags); +} + +static void __nvoc_thunk_KernelCE_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[166]) { kceRegisterIntrService(arg0, (struct KernelCE *)(((unsigned char *)arg1) - __nvoc_rtti_KernelCE_IntrService.offset), arg2); } @@ -95,14 +99,6 @@ static NV_STATUS __nvoc_thunk_KernelCE_intrservServiceNotificationInterrupt(OBJG return kceServiceNotificationInterrupt(arg0, (struct KernelCE *)(((unsigned char *)arg1) - __nvoc_rtti_KernelCE_IntrService.offset), arg2); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceReconcileTunableState(POBJGPU pGpu, struct KernelCE *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceStateUnload(POBJGPU pGpu, struct KernelCE *pEngstate, NvU32 arg0) { - return engstateStateUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset), arg0); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceStateInitLocked(POBJGPU pGpu, struct KernelCE *pEngstate) { return engstateStateInitLocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset)); } @@ -139,18 +135,6 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceStatePreInitUnlocked(POBJGPU pGpu, return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceGetTunableState(POBJGPU pGpu, struct KernelCE *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceCompareTunableState(POBJGPU pGpu, struct KernelCE *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kceFreeTunableState(POBJGPU pGpu, struct KernelCE *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_IntrService_kceClearInterrupt(OBJGPU *pGpu, struct KernelCE *pIntrService, IntrServiceClearInterruptArguments *pParams) { return intrservClearInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_KernelCE_IntrService.offset), pParams); } @@ -159,14 +143,6 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceStatePostLoad(POBJGPU pGpu, struct return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceAllocTunableState(POBJGPU pGpu, struct KernelCE *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceSetTunableState(POBJGPU pGpu, struct KernelCE *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset), pTunableState); -} - static NvU32 __nvoc_thunk_IntrService_kceServiceInterrupt(OBJGPU *pGpu, struct KernelCE *pIntrService, IntrServiceServiceInterruptArguments *pParams) { return intrservServiceInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_KernelCE_IntrService.offset), pParams); } @@ -243,6 +219,12 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR pThis->__kceStateLoad__ = &kceStateLoad_GP100; } + // Hal function -- kceStateUnload + // default + { + pThis->__kceStateUnload__ = &kceStateUnload_56cd7a; + } + pThis->__kceRegisterIntrService__ = &kceRegisterIntrService_IMPL; pThis->__kceServiceNotificationInterrupt__ = &kceServiceNotificationInterrupt_IMPL; @@ -324,7 +306,8 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR { pThis->__kceMapPceLceForGRCE__ = &kceMapPceLceForGRCE_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + // default + else { pThis->__kceMapPceLceForGRCE__ = &kceMapPceLceForGRCE_b3696a; } @@ -443,14 +426,12 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR pThis->__nvoc_base_OBJENGSTATE.__engstateStateLoad__ = &__nvoc_thunk_KernelCE_engstateStateLoad; + pThis->__nvoc_base_OBJENGSTATE.__engstateStateUnload__ = &__nvoc_thunk_KernelCE_engstateStateUnload; + pThis->__nvoc_base_IntrService.__intrservRegisterIntrService__ = &__nvoc_thunk_KernelCE_intrservRegisterIntrService; pThis->__nvoc_base_IntrService.__intrservServiceNotificationInterrupt__ = &__nvoc_thunk_KernelCE_intrservServiceNotificationInterrupt; - pThis->__kceReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kceReconcileTunableState; - - pThis->__kceStateUnload__ = &__nvoc_thunk_OBJENGSTATE_kceStateUnload; - pThis->__kceStateInitLocked__ = &__nvoc_thunk_OBJENGSTATE_kceStateInitLocked; pThis->__kceStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_kceStatePreLoad; @@ -469,20 +450,10 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR pThis->__kceStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kceStatePreInitUnlocked; - pThis->__kceGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kceGetTunableState; - - pThis->__kceCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kceCompareTunableState; - - pThis->__kceFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kceFreeTunableState; - pThis->__kceClearInterrupt__ = &__nvoc_thunk_IntrService_kceClearInterrupt; pThis->__kceStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kceStatePostLoad; - pThis->__kceAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kceAllocTunableState; - - pThis->__kceSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kceSetTunableState; - pThis->__kceServiceInterrupt__ = &__nvoc_thunk_IntrService_kceServiceInterrupt; } @@ -508,13 +479,16 @@ NV_STATUS __nvoc_objCreate_KernelCE(KernelCE **ppThis, Dynamic *pParent, NvU32 c KernelCE *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelCE)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelCE), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelCE)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelCE); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -534,11 +508,17 @@ NV_STATUS __nvoc_objCreate_KernelCE(KernelCE **ppThis, Dynamic *pParent, NvU32 c if (status != NV_OK) goto __nvoc_objCreate_KernelCE_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelCE_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelCE)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_ce_nvoc.h b/src/nvidia/generated/g_kernel_ce_nvoc.h index 678133316..865aca646 100644 --- a/src/nvidia/generated/g_kernel_ce_nvoc.h +++ b/src/nvidia/generated/g_kernel_ce_nvoc.h @@ -110,6 +110,7 @@ struct KernelCE { NV_STATUS (*__kceConstructEngine__)(OBJGPU *, struct KernelCE *, ENGDESCRIPTOR); NvBool (*__kceIsPresent__)(OBJGPU *, struct KernelCE *); NV_STATUS (*__kceStateLoad__)(OBJGPU *, struct KernelCE *, NvU32); + NV_STATUS (*__kceStateUnload__)(OBJGPU *, struct KernelCE *, NvU32); void (*__kceRegisterIntrService__)(OBJGPU *, struct KernelCE *, IntrServiceRecord *); NV_STATUS (*__kceServiceNotificationInterrupt__)(OBJGPU *, struct KernelCE *, IntrServiceServiceNotificationInterruptArguments *); NV_STATUS (*__kceGetNvlinkAutoConfigCeValues__)(OBJGPU *, struct KernelCE *, NvU32 *, NvU32 *, NvU32 *); @@ -127,8 +128,6 @@ struct KernelCE { NvU32 (*__kceGetGrceSupportedLceMask__)(OBJGPU *, struct KernelCE *); NvBool (*__kceIsGenXorHigherSupported__)(OBJGPU *, struct KernelCE *, NvU32); void (*__kceApplyGen4orHigherMapping__)(OBJGPU *, struct KernelCE *, NvU32 *, NvU32 *, NvU32, NvU32); - NV_STATUS (*__kceReconcileTunableState__)(POBJGPU, struct KernelCE *, void *); - NV_STATUS (*__kceStateUnload__)(POBJGPU, struct KernelCE *, NvU32); NV_STATUS (*__kceStateInitLocked__)(POBJGPU, struct KernelCE *); NV_STATUS (*__kceStatePreLoad__)(POBJGPU, struct KernelCE *, NvU32); NV_STATUS (*__kceStatePostUnload__)(POBJGPU, struct KernelCE *, NvU32); @@ -138,13 +137,8 @@ struct KernelCE { void (*__kceInitMissing__)(POBJGPU, struct KernelCE *); NV_STATUS (*__kceStatePreInitLocked__)(POBJGPU, struct KernelCE *); NV_STATUS (*__kceStatePreInitUnlocked__)(POBJGPU, struct KernelCE *); - NV_STATUS (*__kceGetTunableState__)(POBJGPU, struct KernelCE *, void *); - NV_STATUS (*__kceCompareTunableState__)(POBJGPU, struct KernelCE *, void *, void *); - void (*__kceFreeTunableState__)(POBJGPU, struct KernelCE *, void *); NvBool (*__kceClearInterrupt__)(OBJGPU *, struct KernelCE *, IntrServiceClearInterruptArguments *); NV_STATUS (*__kceStatePostLoad__)(POBJGPU, struct KernelCE *, NvU32); - NV_STATUS (*__kceAllocTunableState__)(POBJGPU, struct KernelCE *, void **); - NV_STATUS (*__kceSetTunableState__)(POBJGPU, struct KernelCE *, void *); NvU32 (*__kceServiceInterrupt__)(OBJGPU *, struct KernelCE *, IntrServiceServiceInterruptArguments *); NvU32 publicID; NvBool bShimOwner; @@ -153,7 +147,7 @@ struct KernelCE { NvU32 nvlinkNumPeers; NvBool bIsAutoConfigEnabled; NvBool bUseGen4Mapping; - struct IO_APERTURE aperture; + struct IoAperture aperture; }; #ifndef __NVOC_CLASS_KernelCE_TYPEDEF__ @@ -191,6 +185,8 @@ NV_STATUS __nvoc_objCreate_KernelCE(KernelCE**, Dynamic*, NvU32); #define kceIsPresent_HAL(pGpu, pKCe) kceIsPresent_DISPATCH(pGpu, pKCe) #define kceStateLoad(arg0, arg1, arg2) kceStateLoad_DISPATCH(arg0, arg1, arg2) #define kceStateLoad_HAL(arg0, arg1, arg2) kceStateLoad_DISPATCH(arg0, arg1, arg2) +#define kceStateUnload(pGpu, pKCe, flags) kceStateUnload_DISPATCH(pGpu, pKCe, flags) +#define kceStateUnload_HAL(pGpu, pKCe, flags) kceStateUnload_DISPATCH(pGpu, pKCe, flags) #define kceRegisterIntrService(arg0, arg1, arg2) kceRegisterIntrService_DISPATCH(arg0, arg1, arg2) #define kceServiceNotificationInterrupt(arg0, arg1, arg2) kceServiceNotificationInterrupt_DISPATCH(arg0, arg1, arg2) #define kceGetNvlinkAutoConfigCeValues(pGpu, pKCe, arg0, arg1, arg2) kceGetNvlinkAutoConfigCeValues_DISPATCH(pGpu, pKCe, arg0, arg1, arg2) @@ -223,8 +219,6 @@ NV_STATUS __nvoc_objCreate_KernelCE(KernelCE**, Dynamic*, NvU32); #define kceIsGenXorHigherSupported_HAL(pGpu, pCe, checkGen) kceIsGenXorHigherSupported_DISPATCH(pGpu, pCe, checkGen) #define kceApplyGen4orHigherMapping(pGpu, pCe, arg0, arg1, arg2, arg3) kceApplyGen4orHigherMapping_DISPATCH(pGpu, pCe, arg0, arg1, arg2, arg3) #define kceApplyGen4orHigherMapping_HAL(pGpu, pCe, arg0, arg1, arg2, arg3) kceApplyGen4orHigherMapping_DISPATCH(pGpu, pCe, arg0, arg1, arg2, arg3) -#define kceReconcileTunableState(pGpu, pEngstate, pTunableState) kceReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kceStateUnload(pGpu, pEngstate, arg0) kceStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define kceStateInitLocked(pGpu, pEngstate) kceStateInitLocked_DISPATCH(pGpu, pEngstate) #define kceStatePreLoad(pGpu, pEngstate, arg0) kceStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kceStatePostUnload(pGpu, pEngstate, arg0) kceStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) @@ -234,13 +228,8 @@ NV_STATUS __nvoc_objCreate_KernelCE(KernelCE**, Dynamic*, NvU32); #define kceInitMissing(pGpu, pEngstate) kceInitMissing_DISPATCH(pGpu, pEngstate) #define kceStatePreInitLocked(pGpu, pEngstate) kceStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kceStatePreInitUnlocked(pGpu, pEngstate) kceStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kceGetTunableState(pGpu, pEngstate, pTunableState) kceGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kceCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kceCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kceFreeTunableState(pGpu, pEngstate, pTunableState) kceFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kceClearInterrupt(pGpu, pIntrService, pParams) kceClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define kceStatePostLoad(pGpu, pEngstate, arg0) kceStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define kceAllocTunableState(pGpu, pEngstate, ppTunableState) kceAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kceSetTunableState(pGpu, pEngstate, pTunableState) kceSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kceServiceInterrupt(pGpu, pIntrService, pParams) kceServiceInterrupt_DISPATCH(pGpu, pIntrService, pParams) static inline void kceNonstallIntrCheckAndClear_b3696a(OBJGPU *arg0, struct KernelCE *arg1, struct THREAD_STATE_NODE *arg2) { return; @@ -399,9 +388,17 @@ static inline NV_STATUS kceStateLoad_DISPATCH(OBJGPU *arg0, struct KernelCE *arg return arg1->__kceStateLoad__(arg0, arg1, arg2); } -void kceRegisterIntrService_IMPL(OBJGPU *arg0, struct KernelCE *arg1, IntrServiceRecord arg2[163]); +static inline NV_STATUS kceStateUnload_56cd7a(OBJGPU *pGpu, struct KernelCE *pKCe, NvU32 flags) { + return NV_OK; +} -static inline void kceRegisterIntrService_DISPATCH(OBJGPU *arg0, struct KernelCE *arg1, IntrServiceRecord arg2[163]) { +static inline NV_STATUS kceStateUnload_DISPATCH(OBJGPU *pGpu, struct KernelCE *pKCe, NvU32 flags) { + return pKCe->__kceStateUnload__(pGpu, pKCe, flags); +} + +void kceRegisterIntrService_IMPL(OBJGPU *arg0, struct KernelCE *arg1, IntrServiceRecord arg2[166]); + +static inline void kceRegisterIntrService_DISPATCH(OBJGPU *arg0, struct KernelCE *arg1, IntrServiceRecord arg2[166]) { arg1->__kceRegisterIntrService__(arg0, arg1, arg2); } @@ -577,14 +574,6 @@ static inline void kceApplyGen4orHigherMapping_DISPATCH(OBJGPU *pGpu, struct Ker pCe->__kceApplyGen4orHigherMapping__(pGpu, pCe, arg0, arg1, arg2, arg3); } -static inline NV_STATUS kceReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelCE *pEngstate, void *pTunableState) { - return pEngstate->__kceReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kceStateUnload_DISPATCH(POBJGPU pGpu, struct KernelCE *pEngstate, NvU32 arg0) { - return pEngstate->__kceStateUnload__(pGpu, pEngstate, arg0); -} - static inline NV_STATUS kceStateInitLocked_DISPATCH(POBJGPU pGpu, struct KernelCE *pEngstate) { return pEngstate->__kceStateInitLocked__(pGpu, pEngstate); } @@ -621,18 +610,6 @@ static inline NV_STATUS kceStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct Ke return pEngstate->__kceStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kceGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelCE *pEngstate, void *pTunableState) { - return pEngstate->__kceGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kceCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelCE *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kceCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kceFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelCE *pEngstate, void *pTunableState) { - pEngstate->__kceFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kceClearInterrupt_DISPATCH(OBJGPU *pGpu, struct KernelCE *pIntrService, IntrServiceClearInterruptArguments *pParams) { return pIntrService->__kceClearInterrupt__(pGpu, pIntrService, pParams); } @@ -641,14 +618,6 @@ static inline NV_STATUS kceStatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelCE return pEngstate->__kceStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS kceAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelCE *pEngstate, void **ppTunableState) { - return pEngstate->__kceAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kceSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelCE *pEngstate, void *pTunableState) { - return pEngstate->__kceSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvU32 kceServiceInterrupt_DISPATCH(OBJGPU *pGpu, struct KernelCE *pIntrService, IntrServiceServiceInterruptArguments *pParams) { return pIntrService->__kceServiceInterrupt__(pGpu, pIntrService, pParams); } diff --git a/src/nvidia/generated/g_kernel_channel_group_api_nvoc.c b/src/nvidia/generated/g_kernel_channel_group_api_nvoc.c index f4edd147a..2e509deb1 100644 --- a/src/nvidia/generated/g_kernel_channel_group_api_nvoc.c +++ b/src/nvidia/generated/g_kernel_channel_group_api_nvoc.c @@ -105,38 +105,6 @@ static NvBool __nvoc_thunk_GpuResource_kchangrpapiShareCallback(struct KernelCha return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelChannelGroupApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_GpuResource_kchangrpapiUnmap(struct KernelChannelGroupApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelChannelGroupApi_GpuResource.offset), pCallContext, pCpuMapping); -} - -static NV_STATUS __nvoc_thunk_RmResource_kchangrpapiGetMemInterMapParams(struct KernelChannelGroupApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelChannelGroupApi_RmResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_kchangrpapiGetMemoryMappingDescriptor(struct KernelChannelGroupApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelChannelGroupApi_RmResource.offset), ppMemDesc); -} - -static NV_STATUS __nvoc_thunk_GpuResource_kchangrpapiGetMapAddrSpace(struct KernelChannelGroupApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelChannelGroupApi_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvHandle __nvoc_thunk_GpuResource_kchangrpapiGetInternalObjectHandle(struct KernelChannelGroupApi *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelChannelGroupApi_GpuResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RsResource_kchangrpapiControlFilter(struct KernelChannelGroupApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset), pCallContext, pParams); -} - -static void __nvoc_thunk_RsResource_kchangrpapiAddAdditionalDependants(struct RsClient *pClient, struct KernelChannelGroupApi *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_kchangrpapiGetRefCount(struct KernelChannelGroupApi *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_RmResource_kchangrpapiCheckMemInterUnmap(struct KernelChannelGroupApi *pRmResource, NvBool bSubdeviceHandleProvided) { return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelChannelGroupApi_RmResource.offset), bSubdeviceHandleProvided); } @@ -145,6 +113,18 @@ static NV_STATUS __nvoc_thunk_RsResource_kchangrpapiMapTo(struct KernelChannelGr return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_GpuResource_kchangrpapiGetMapAddrSpace(struct KernelChannelGroupApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelChannelGroupApi_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_kchangrpapiGetRefCount(struct KernelChannelGroupApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_kchangrpapiAddAdditionalDependants(struct RsClient *pClient, struct KernelChannelGroupApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset), pReference); +} + static NV_STATUS __nvoc_thunk_RmResource_kchangrpapiControl_Prologue(struct KernelChannelGroupApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RmResource.offset), pCallContext, pParams); } @@ -157,18 +137,10 @@ static NV_STATUS __nvoc_thunk_GpuResource_kchangrpapiInternalControlForward(stru return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelChannelGroupApi_GpuResource.offset), command, pParams, size); } -static void __nvoc_thunk_RsResource_kchangrpapiPreDestruct(struct KernelChannelGroupApi *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_kchangrpapiUnmapFrom(struct KernelChannelGroupApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RsResource_kchangrpapiIsDuplicate(struct KernelChannelGroupApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset), hMemory, pDuplicate); -} - static void __nvoc_thunk_RmResource_kchangrpapiControl_Epilogue(struct KernelChannelGroupApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RmResource.offset), pCallContext, pParams); } @@ -177,6 +149,42 @@ static NV_STATUS __nvoc_thunk_RsResource_kchangrpapiControlLookup(struct KernelC return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset), pParams, ppEntry); } +static NvHandle __nvoc_thunk_GpuResource_kchangrpapiGetInternalObjectHandle(struct KernelChannelGroupApi *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelChannelGroupApi_GpuResource.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_kchangrpapiUnmap(struct KernelChannelGroupApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelChannelGroupApi_GpuResource.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_RmResource_kchangrpapiGetMemInterMapParams(struct KernelChannelGroupApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelChannelGroupApi_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_kchangrpapiGetMemoryMappingDescriptor(struct KernelChannelGroupApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelChannelGroupApi_RmResource.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_kchangrpapiControlFilter(struct KernelChannelGroupApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_kchangrpapiControlSerialization_Prologue(struct KernelChannelGroupApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RmResource.offset), pCallContext, pParams); +} + +static void __nvoc_thunk_RsResource_kchangrpapiPreDestruct(struct KernelChannelGroupApi *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_kchangrpapiIsDuplicate(struct KernelChannelGroupApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_kchangrpapiControlSerialization_Epilogue(struct KernelChannelGroupApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RmResource.offset), pCallContext, pParams); +} + static NV_STATUS __nvoc_thunk_GpuResource_kchangrpapiMap(struct KernelChannelGroupApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { return gpuresMap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelChannelGroupApi_GpuResource.offset), pCallContext, pParams, pCpuMapping); } @@ -549,42 +557,46 @@ static void __nvoc_init_funcTable_KernelChannelGroupApi_1(KernelChannelGroupApi pThis->__kchangrpapiShareCallback__ = &__nvoc_thunk_GpuResource_kchangrpapiShareCallback; - pThis->__kchangrpapiUnmap__ = &__nvoc_thunk_GpuResource_kchangrpapiUnmap; - - pThis->__kchangrpapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_kchangrpapiGetMemInterMapParams; - - pThis->__kchangrpapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_kchangrpapiGetMemoryMappingDescriptor; - - pThis->__kchangrpapiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_kchangrpapiGetMapAddrSpace; - - pThis->__kchangrpapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_kchangrpapiGetInternalObjectHandle; - - pThis->__kchangrpapiControlFilter__ = &__nvoc_thunk_RsResource_kchangrpapiControlFilter; - - pThis->__kchangrpapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_kchangrpapiAddAdditionalDependants; - - pThis->__kchangrpapiGetRefCount__ = &__nvoc_thunk_RsResource_kchangrpapiGetRefCount; - pThis->__kchangrpapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_kchangrpapiCheckMemInterUnmap; pThis->__kchangrpapiMapTo__ = &__nvoc_thunk_RsResource_kchangrpapiMapTo; + pThis->__kchangrpapiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_kchangrpapiGetMapAddrSpace; + + pThis->__kchangrpapiGetRefCount__ = &__nvoc_thunk_RsResource_kchangrpapiGetRefCount; + + pThis->__kchangrpapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_kchangrpapiAddAdditionalDependants; + pThis->__kchangrpapiControl_Prologue__ = &__nvoc_thunk_RmResource_kchangrpapiControl_Prologue; pThis->__kchangrpapiGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_kchangrpapiGetRegBaseOffsetAndSize; pThis->__kchangrpapiInternalControlForward__ = &__nvoc_thunk_GpuResource_kchangrpapiInternalControlForward; - pThis->__kchangrpapiPreDestruct__ = &__nvoc_thunk_RsResource_kchangrpapiPreDestruct; - pThis->__kchangrpapiUnmapFrom__ = &__nvoc_thunk_RsResource_kchangrpapiUnmapFrom; - pThis->__kchangrpapiIsDuplicate__ = &__nvoc_thunk_RsResource_kchangrpapiIsDuplicate; - pThis->__kchangrpapiControl_Epilogue__ = &__nvoc_thunk_RmResource_kchangrpapiControl_Epilogue; pThis->__kchangrpapiControlLookup__ = &__nvoc_thunk_RsResource_kchangrpapiControlLookup; + pThis->__kchangrpapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_kchangrpapiGetInternalObjectHandle; + + pThis->__kchangrpapiUnmap__ = &__nvoc_thunk_GpuResource_kchangrpapiUnmap; + + pThis->__kchangrpapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_kchangrpapiGetMemInterMapParams; + + pThis->__kchangrpapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_kchangrpapiGetMemoryMappingDescriptor; + + pThis->__kchangrpapiControlFilter__ = &__nvoc_thunk_RsResource_kchangrpapiControlFilter; + + pThis->__kchangrpapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_kchangrpapiControlSerialization_Prologue; + + pThis->__kchangrpapiPreDestruct__ = &__nvoc_thunk_RsResource_kchangrpapiPreDestruct; + + pThis->__kchangrpapiIsDuplicate__ = &__nvoc_thunk_RsResource_kchangrpapiIsDuplicate; + + pThis->__kchangrpapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_kchangrpapiControlSerialization_Epilogue; + pThis->__kchangrpapiMap__ = &__nvoc_thunk_GpuResource_kchangrpapiMap; pThis->__kchangrpapiAccessCallback__ = &__nvoc_thunk_RmResource_kchangrpapiAccessCallback; @@ -611,13 +623,16 @@ NV_STATUS __nvoc_objCreate_KernelChannelGroupApi(KernelChannelGroupApi **ppThis, Object *pParentObj; KernelChannelGroupApi *pThis; - pThis = portMemAllocNonPaged(sizeof(KernelChannelGroupApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelChannelGroupApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelChannelGroupApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelChannelGroupApi); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -633,11 +648,17 @@ NV_STATUS __nvoc_objCreate_KernelChannelGroupApi(KernelChannelGroupApi **ppThis, if (status != NV_OK) goto __nvoc_objCreate_KernelChannelGroupApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelChannelGroupApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelChannelGroupApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_channel_group_api_nvoc.h b/src/nvidia/generated/g_kernel_channel_group_api_nvoc.h index 3bb218f44..c9be207e2 100644 --- a/src/nvidia/generated/g_kernel_channel_group_api_nvoc.h +++ b/src/nvidia/generated/g_kernel_channel_group_api_nvoc.h @@ -103,24 +103,26 @@ struct KernelChannelGroupApi { NV_STATUS (*__kchangrpapiCtrlGetMMUDebugMode__)(struct KernelChannelGroupApi *, NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS *); NV_STATUS (*__kchangrpapiCtrlProgramVidmemPromote__)(struct KernelChannelGroupApi *, NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS *); NvBool (*__kchangrpapiShareCallback__)(struct KernelChannelGroupApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__kchangrpapiUnmap__)(struct KernelChannelGroupApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); - NV_STATUS (*__kchangrpapiGetMemInterMapParams__)(struct KernelChannelGroupApi *, RMRES_MEM_INTER_MAP_PARAMS *); - NV_STATUS (*__kchangrpapiGetMemoryMappingDescriptor__)(struct KernelChannelGroupApi *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__kchangrpapiGetMapAddrSpace__)(struct KernelChannelGroupApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__kchangrpapiGetInternalObjectHandle__)(struct KernelChannelGroupApi *); - NV_STATUS (*__kchangrpapiControlFilter__)(struct KernelChannelGroupApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__kchangrpapiAddAdditionalDependants__)(struct RsClient *, struct KernelChannelGroupApi *, RsResourceRef *); - NvU32 (*__kchangrpapiGetRefCount__)(struct KernelChannelGroupApi *); NV_STATUS (*__kchangrpapiCheckMemInterUnmap__)(struct KernelChannelGroupApi *, NvBool); NV_STATUS (*__kchangrpapiMapTo__)(struct KernelChannelGroupApi *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__kchangrpapiGetMapAddrSpace__)(struct KernelChannelGroupApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__kchangrpapiGetRefCount__)(struct KernelChannelGroupApi *); + void (*__kchangrpapiAddAdditionalDependants__)(struct RsClient *, struct KernelChannelGroupApi *, RsResourceRef *); NV_STATUS (*__kchangrpapiControl_Prologue__)(struct KernelChannelGroupApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kchangrpapiGetRegBaseOffsetAndSize__)(struct KernelChannelGroupApi *, struct OBJGPU *, NvU32 *, NvU32 *); NV_STATUS (*__kchangrpapiInternalControlForward__)(struct KernelChannelGroupApi *, NvU32, void *, NvU32); - void (*__kchangrpapiPreDestruct__)(struct KernelChannelGroupApi *); NV_STATUS (*__kchangrpapiUnmapFrom__)(struct KernelChannelGroupApi *, RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__kchangrpapiIsDuplicate__)(struct KernelChannelGroupApi *, NvHandle, NvBool *); void (*__kchangrpapiControl_Epilogue__)(struct KernelChannelGroupApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kchangrpapiControlLookup__)(struct KernelChannelGroupApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__kchangrpapiGetInternalObjectHandle__)(struct KernelChannelGroupApi *); + NV_STATUS (*__kchangrpapiUnmap__)(struct KernelChannelGroupApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__kchangrpapiGetMemInterMapParams__)(struct KernelChannelGroupApi *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__kchangrpapiGetMemoryMappingDescriptor__)(struct KernelChannelGroupApi *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__kchangrpapiControlFilter__)(struct KernelChannelGroupApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kchangrpapiControlSerialization_Prologue__)(struct KernelChannelGroupApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__kchangrpapiPreDestruct__)(struct KernelChannelGroupApi *); + NV_STATUS (*__kchangrpapiIsDuplicate__)(struct KernelChannelGroupApi *, NvHandle, NvBool *); + void (*__kchangrpapiControlSerialization_Epilogue__)(struct KernelChannelGroupApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kchangrpapiMap__)(struct KernelChannelGroupApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__kchangrpapiAccessCallback__)(struct KernelChannelGroupApi *, struct RsClient *, void *, RsAccessRight); struct KernelChannelGroup *pKernelChannelGroup; @@ -180,24 +182,26 @@ NV_STATUS __nvoc_objCreate_KernelChannelGroupApi(KernelChannelGroupApi**, Dynami #define kchangrpapiCtrlGetMMUDebugMode(pKernelChannelGroupApi, pParams) kchangrpapiCtrlGetMMUDebugMode_DISPATCH(pKernelChannelGroupApi, pParams) #define kchangrpapiCtrlProgramVidmemPromote(pKernelChannelGroupApi, pParams) kchangrpapiCtrlProgramVidmemPromote_DISPATCH(pKernelChannelGroupApi, pParams) #define kchangrpapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) kchangrpapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define kchangrpapiUnmap(pGpuResource, pCallContext, pCpuMapping) kchangrpapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) -#define kchangrpapiGetMemInterMapParams(pRmResource, pParams) kchangrpapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) -#define kchangrpapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) kchangrpapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define kchangrpapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) kchangrpapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define kchangrpapiGetInternalObjectHandle(pGpuResource) kchangrpapiGetInternalObjectHandle_DISPATCH(pGpuResource) -#define kchangrpapiControlFilter(pResource, pCallContext, pParams) kchangrpapiControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define kchangrpapiAddAdditionalDependants(pClient, pResource, pReference) kchangrpapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define kchangrpapiGetRefCount(pResource) kchangrpapiGetRefCount_DISPATCH(pResource) #define kchangrpapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) kchangrpapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define kchangrpapiMapTo(pResource, pParams) kchangrpapiMapTo_DISPATCH(pResource, pParams) +#define kchangrpapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) kchangrpapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define kchangrpapiGetRefCount(pResource) kchangrpapiGetRefCount_DISPATCH(pResource) +#define kchangrpapiAddAdditionalDependants(pClient, pResource, pReference) kchangrpapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define kchangrpapiControl_Prologue(pResource, pCallContext, pParams) kchangrpapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define kchangrpapiGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) kchangrpapiGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) #define kchangrpapiInternalControlForward(pGpuResource, command, pParams, size) kchangrpapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) -#define kchangrpapiPreDestruct(pResource) kchangrpapiPreDestruct_DISPATCH(pResource) #define kchangrpapiUnmapFrom(pResource, pParams) kchangrpapiUnmapFrom_DISPATCH(pResource, pParams) -#define kchangrpapiIsDuplicate(pResource, hMemory, pDuplicate) kchangrpapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define kchangrpapiControl_Epilogue(pResource, pCallContext, pParams) kchangrpapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define kchangrpapiControlLookup(pResource, pParams, ppEntry) kchangrpapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define kchangrpapiGetInternalObjectHandle(pGpuResource) kchangrpapiGetInternalObjectHandle_DISPATCH(pGpuResource) +#define kchangrpapiUnmap(pGpuResource, pCallContext, pCpuMapping) kchangrpapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define kchangrpapiGetMemInterMapParams(pRmResource, pParams) kchangrpapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define kchangrpapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) kchangrpapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define kchangrpapiControlFilter(pResource, pCallContext, pParams) kchangrpapiControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define kchangrpapiControlSerialization_Prologue(pResource, pCallContext, pParams) kchangrpapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define kchangrpapiPreDestruct(pResource) kchangrpapiPreDestruct_DISPATCH(pResource) +#define kchangrpapiIsDuplicate(pResource, hMemory, pDuplicate) kchangrpapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define kchangrpapiControlSerialization_Epilogue(pResource, pCallContext, pParams) kchangrpapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define kchangrpapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) kchangrpapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define kchangrpapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) kchangrpapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool kchangrpapiCanCopy_IMPL(struct KernelChannelGroupApi *pKernelChannelGroupApi); @@ -326,38 +330,6 @@ static inline NvBool kchangrpapiShareCallback_DISPATCH(struct KernelChannelGroup return pGpuResource->__kchangrpapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS kchangrpapiUnmap_DISPATCH(struct KernelChannelGroupApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { - return pGpuResource->__kchangrpapiUnmap__(pGpuResource, pCallContext, pCpuMapping); -} - -static inline NV_STATUS kchangrpapiGetMemInterMapParams_DISPATCH(struct KernelChannelGroupApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__kchangrpapiGetMemInterMapParams__(pRmResource, pParams); -} - -static inline NV_STATUS kchangrpapiGetMemoryMappingDescriptor_DISPATCH(struct KernelChannelGroupApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__kchangrpapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); -} - -static inline NV_STATUS kchangrpapiGetMapAddrSpace_DISPATCH(struct KernelChannelGroupApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__kchangrpapiGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvHandle kchangrpapiGetInternalObjectHandle_DISPATCH(struct KernelChannelGroupApi *pGpuResource) { - return pGpuResource->__kchangrpapiGetInternalObjectHandle__(pGpuResource); -} - -static inline NV_STATUS kchangrpapiControlFilter_DISPATCH(struct KernelChannelGroupApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__kchangrpapiControlFilter__(pResource, pCallContext, pParams); -} - -static inline void kchangrpapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct KernelChannelGroupApi *pResource, RsResourceRef *pReference) { - pResource->__kchangrpapiAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 kchangrpapiGetRefCount_DISPATCH(struct KernelChannelGroupApi *pResource) { - return pResource->__kchangrpapiGetRefCount__(pResource); -} - static inline NV_STATUS kchangrpapiCheckMemInterUnmap_DISPATCH(struct KernelChannelGroupApi *pRmResource, NvBool bSubdeviceHandleProvided) { return pRmResource->__kchangrpapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } @@ -366,6 +338,18 @@ static inline NV_STATUS kchangrpapiMapTo_DISPATCH(struct KernelChannelGroupApi * return pResource->__kchangrpapiMapTo__(pResource, pParams); } +static inline NV_STATUS kchangrpapiGetMapAddrSpace_DISPATCH(struct KernelChannelGroupApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__kchangrpapiGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 kchangrpapiGetRefCount_DISPATCH(struct KernelChannelGroupApi *pResource) { + return pResource->__kchangrpapiGetRefCount__(pResource); +} + +static inline void kchangrpapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct KernelChannelGroupApi *pResource, RsResourceRef *pReference) { + pResource->__kchangrpapiAddAdditionalDependants__(pClient, pResource, pReference); +} + static inline NV_STATUS kchangrpapiControl_Prologue_DISPATCH(struct KernelChannelGroupApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__kchangrpapiControl_Prologue__(pResource, pCallContext, pParams); } @@ -378,18 +362,10 @@ static inline NV_STATUS kchangrpapiInternalControlForward_DISPATCH(struct Kernel return pGpuResource->__kchangrpapiInternalControlForward__(pGpuResource, command, pParams, size); } -static inline void kchangrpapiPreDestruct_DISPATCH(struct KernelChannelGroupApi *pResource) { - pResource->__kchangrpapiPreDestruct__(pResource); -} - static inline NV_STATUS kchangrpapiUnmapFrom_DISPATCH(struct KernelChannelGroupApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__kchangrpapiUnmapFrom__(pResource, pParams); } -static inline NV_STATUS kchangrpapiIsDuplicate_DISPATCH(struct KernelChannelGroupApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { - return pResource->__kchangrpapiIsDuplicate__(pResource, hMemory, pDuplicate); -} - static inline void kchangrpapiControl_Epilogue_DISPATCH(struct KernelChannelGroupApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__kchangrpapiControl_Epilogue__(pResource, pCallContext, pParams); } @@ -398,6 +374,42 @@ static inline NV_STATUS kchangrpapiControlLookup_DISPATCH(struct KernelChannelGr return pResource->__kchangrpapiControlLookup__(pResource, pParams, ppEntry); } +static inline NvHandle kchangrpapiGetInternalObjectHandle_DISPATCH(struct KernelChannelGroupApi *pGpuResource) { + return pGpuResource->__kchangrpapiGetInternalObjectHandle__(pGpuResource); +} + +static inline NV_STATUS kchangrpapiUnmap_DISPATCH(struct KernelChannelGroupApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__kchangrpapiUnmap__(pGpuResource, pCallContext, pCpuMapping); +} + +static inline NV_STATUS kchangrpapiGetMemInterMapParams_DISPATCH(struct KernelChannelGroupApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__kchangrpapiGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS kchangrpapiGetMemoryMappingDescriptor_DISPATCH(struct KernelChannelGroupApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__kchangrpapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +} + +static inline NV_STATUS kchangrpapiControlFilter_DISPATCH(struct KernelChannelGroupApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__kchangrpapiControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS kchangrpapiControlSerialization_Prologue_DISPATCH(struct KernelChannelGroupApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__kchangrpapiControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline void kchangrpapiPreDestruct_DISPATCH(struct KernelChannelGroupApi *pResource) { + pResource->__kchangrpapiPreDestruct__(pResource); +} + +static inline NV_STATUS kchangrpapiIsDuplicate_DISPATCH(struct KernelChannelGroupApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__kchangrpapiIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void kchangrpapiControlSerialization_Epilogue_DISPATCH(struct KernelChannelGroupApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__kchangrpapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline NV_STATUS kchangrpapiMap_DISPATCH(struct KernelChannelGroupApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { return pGpuResource->__kchangrpapiMap__(pGpuResource, pCallContext, pParams, pCpuMapping); } diff --git a/src/nvidia/generated/g_kernel_channel_group_nvoc.c b/src/nvidia/generated/g_kernel_channel_group_nvoc.c index 58dcac12b..82d86f721 100644 --- a/src/nvidia/generated/g_kernel_channel_group_nvoc.c +++ b/src/nvidia/generated/g_kernel_channel_group_nvoc.c @@ -143,13 +143,16 @@ NV_STATUS __nvoc_objCreate_KernelChannelGroup(KernelChannelGroup **ppThis, Dynam KernelChannelGroup *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelChannelGroup)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelChannelGroup), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelChannelGroup)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelChannelGroup); + pThis->__nvoc_base_RsShared.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -169,11 +172,17 @@ NV_STATUS __nvoc_objCreate_KernelChannelGroup(KernelChannelGroup **ppThis, Dynam if (status != NV_OK) goto __nvoc_objCreate_KernelChannelGroup_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelChannelGroup_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelChannelGroup)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_channel_group_nvoc.h b/src/nvidia/generated/g_kernel_channel_group_nvoc.h index 9b6ac5f44..8abac989b 100644 --- a/src/nvidia/generated/g_kernel_channel_group_nvoc.h +++ b/src/nvidia/generated/g_kernel_channel_group_nvoc.h @@ -192,20 +192,6 @@ static inline NV_STATUS kchangrpSetInterleaveLevelSched(struct OBJGPU *pGpu, str #define kchangrpSetInterleaveLevelSched_HAL(pGpu, pKernelChannelGroup, value) kchangrpSetInterleaveLevelSched(pGpu, pKernelChannelGroup, value) -NvU32 kchangrpGetDefaultRunlist_GM107(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup); - - -#ifdef __nvoc_kernel_channel_group_h_disabled -static inline NvU32 kchangrpGetDefaultRunlist(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup) { - NV_ASSERT_FAILED_PRECOMP("KernelChannelGroup was disabled!"); - return 0; -} -#else //__nvoc_kernel_channel_group_h_disabled -#define kchangrpGetDefaultRunlist(pGpu, pKernelChannelGroup) kchangrpGetDefaultRunlist_GM107(pGpu, pKernelChannelGroup) -#endif //__nvoc_kernel_channel_group_h_disabled - -#define kchangrpGetDefaultRunlist_HAL(pGpu, pKernelChannelGroup) kchangrpGetDefaultRunlist(pGpu, pKernelChannelGroup) - static inline void kchangrpUpdateSubcontextMask_b3696a(struct OBJGPU *pGpu, struct KernelChannelGroup *arg0, NvU32 arg1, NvBool arg2) { return; } @@ -255,22 +241,6 @@ static inline NvBool kchangrpGetSubcontextZombieState(struct OBJGPU *pGpu, struc #define kchangrpGetSubcontextZombieState_HAL(pGpu, arg0, arg1) kchangrpGetSubcontextZombieState(pGpu, arg0, arg1) -static inline NV_STATUS kchangrpFreeGrSubcontextHdrs_56cd7a(struct OBJGPU *pGpu, struct KernelChannelGroup *arg0) { - return NV_OK; -} - - -#ifdef __nvoc_kernel_channel_group_h_disabled -static inline NV_STATUS kchangrpFreeGrSubcontextHdrs(struct OBJGPU *pGpu, struct KernelChannelGroup *arg0) { - NV_ASSERT_FAILED_PRECOMP("KernelChannelGroup was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_channel_group_h_disabled -#define kchangrpFreeGrSubcontextHdrs(pGpu, arg0) kchangrpFreeGrSubcontextHdrs_56cd7a(pGpu, arg0) -#endif //__nvoc_kernel_channel_group_h_disabled - -#define kchangrpFreeGrSubcontextHdrs_HAL(pGpu, arg0) kchangrpFreeGrSubcontextHdrs(pGpu, arg0) - NV_STATUS kchangrpAllocFaultMethodBuffers_GV100(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup); diff --git a/src/nvidia/generated/g_kernel_channel_nvoc.c b/src/nvidia/generated/g_kernel_channel_nvoc.c index 5b8e0acc4..12c1d4b56 100644 --- a/src/nvidia/generated/g_kernel_channel_nvoc.c +++ b/src/nvidia/generated/g_kernel_channel_nvoc.c @@ -135,14 +135,14 @@ static NvBool __nvoc_thunk_GpuResource_kchannelShareCallback(struct KernelChanne return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelChannel_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_RsResource_kchannelMapTo(struct KernelChannel *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannel_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_Notifier_kchannelGetOrAllocNotifShare(struct KernelChannel *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelChannel_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); } +static NV_STATUS __nvoc_thunk_RsResource_kchannelMapTo(struct KernelChannel *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannel_RsResource.offset), pParams); +} + static void __nvoc_thunk_Notifier_kchannelSetNotificationShare(struct KernelChannel *pNotifier, struct NotifShare *pNotifShare) { notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelChannel_Notifier.offset), pNotifShare); } @@ -199,6 +199,10 @@ static NV_STATUS __nvoc_thunk_Notifier_kchannelUnregisterEvent(struct KernelChan return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelChannel_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_kchannelControlSerialization_Prologue(struct KernelChannel *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannel_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_kchannelCanCopy(struct KernelChannel *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannel_RsResource.offset)); } @@ -211,6 +215,10 @@ static NV_STATUS __nvoc_thunk_RsResource_kchannelIsDuplicate(struct KernelChanne return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannel_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_kchannelControlSerialization_Epilogue(struct KernelChannel *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannel_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_kchannelGetNotificationListPtr(struct KernelChannel *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelChannel_Notifier.offset)); } @@ -1254,10 +1262,10 @@ static void __nvoc_init_funcTable_KernelChannel_1(KernelChannel *pThis, RmHalspe pThis->__kchannelShareCallback__ = &__nvoc_thunk_GpuResource_kchannelShareCallback; - pThis->__kchannelMapTo__ = &__nvoc_thunk_RsResource_kchannelMapTo; - pThis->__kchannelGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_kchannelGetOrAllocNotifShare; + pThis->__kchannelMapTo__ = &__nvoc_thunk_RsResource_kchannelMapTo; + pThis->__kchannelSetNotificationShare__ = &__nvoc_thunk_Notifier_kchannelSetNotificationShare; pThis->__kchannelGetRefCount__ = &__nvoc_thunk_RsResource_kchannelGetRefCount; @@ -1286,12 +1294,16 @@ static void __nvoc_init_funcTable_KernelChannel_1(KernelChannel *pThis, RmHalspe pThis->__kchannelUnregisterEvent__ = &__nvoc_thunk_Notifier_kchannelUnregisterEvent; + pThis->__kchannelControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_kchannelControlSerialization_Prologue; + pThis->__kchannelCanCopy__ = &__nvoc_thunk_RsResource_kchannelCanCopy; pThis->__kchannelPreDestruct__ = &__nvoc_thunk_RsResource_kchannelPreDestruct; pThis->__kchannelIsDuplicate__ = &__nvoc_thunk_RsResource_kchannelIsDuplicate; + pThis->__kchannelControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_kchannelControlSerialization_Epilogue; + pThis->__kchannelGetNotificationListPtr__ = &__nvoc_thunk_Notifier_kchannelGetNotificationListPtr; pThis->__kchannelGetNotificationShare__ = &__nvoc_thunk_Notifier_kchannelGetNotificationShare; @@ -1325,13 +1337,16 @@ NV_STATUS __nvoc_objCreate_KernelChannel(KernelChannel **ppThis, Dynamic *pParen KernelChannel *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelChannel)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelChannel), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelChannel)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelChannel); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -1351,11 +1366,17 @@ NV_STATUS __nvoc_objCreate_KernelChannel(KernelChannel **ppThis, Dynamic *pParen if (status != NV_OK) goto __nvoc_objCreate_KernelChannel_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelChannel_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelChannel)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_channel_nvoc.h b/src/nvidia/generated/g_kernel_channel_nvoc.h index 740ecb5b3..ac7487681 100644 --- a/src/nvidia/generated/g_kernel_channel_nvoc.h +++ b/src/nvidia/generated/g_kernel_channel_nvoc.h @@ -262,8 +262,8 @@ struct KernelChannel { NV_STATUS (*__kchannelCtrlGetMMUDebugMode__)(struct KernelChannel *, NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS *); NV_STATUS (*__kchannelCtrlProgramVidmemPromote__)(struct KernelChannel *, NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS *); NvBool (*__kchannelShareCallback__)(struct KernelChannel *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__kchannelMapTo__)(struct KernelChannel *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__kchannelGetOrAllocNotifShare__)(struct KernelChannel *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__kchannelMapTo__)(struct KernelChannel *, RS_RES_MAP_TO_PARAMS *); void (*__kchannelSetNotificationShare__)(struct KernelChannel *, struct NotifShare *); NvU32 (*__kchannelGetRefCount__)(struct KernelChannel *); void (*__kchannelAddAdditionalDependants__)(struct RsClient *, struct KernelChannel *, RsResourceRef *); @@ -278,9 +278,11 @@ struct KernelChannel { NV_STATUS (*__kchannelGetMemoryMappingDescriptor__)(struct KernelChannel *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__kchannelControlFilter__)(struct KernelChannel *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kchannelUnregisterEvent__)(struct KernelChannel *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__kchannelControlSerialization_Prologue__)(struct KernelChannel *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__kchannelCanCopy__)(struct KernelChannel *); void (*__kchannelPreDestruct__)(struct KernelChannel *); NV_STATUS (*__kchannelIsDuplicate__)(struct KernelChannel *, NvHandle, NvBool *); + void (*__kchannelControlSerialization_Epilogue__)(struct KernelChannel *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__kchannelGetNotificationListPtr__)(struct KernelChannel *); struct NotifShare *(*__kchannelGetNotificationShare__)(struct KernelChannel *); NvBool (*__kchannelAccessCallback__)(struct KernelChannel *, struct RsClient *, void *, RsAccessRight); @@ -410,8 +412,8 @@ NV_STATUS __nvoc_objCreate_KernelChannel(KernelChannel**, Dynamic*, NvU32, CALL_ #define kchannelCtrlGetMMUDebugMode(pKernelChannel, pParams) kchannelCtrlGetMMUDebugMode_DISPATCH(pKernelChannel, pParams) #define kchannelCtrlProgramVidmemPromote(pKernelChannel, pParams) kchannelCtrlProgramVidmemPromote_DISPATCH(pKernelChannel, pParams) #define kchannelShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) kchannelShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define kchannelMapTo(pResource, pParams) kchannelMapTo_DISPATCH(pResource, pParams) #define kchannelGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) kchannelGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define kchannelMapTo(pResource, pParams) kchannelMapTo_DISPATCH(pResource, pParams) #define kchannelSetNotificationShare(pNotifier, pNotifShare) kchannelSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define kchannelGetRefCount(pResource) kchannelGetRefCount_DISPATCH(pResource) #define kchannelAddAdditionalDependants(pClient, pResource, pReference) kchannelAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) @@ -426,9 +428,11 @@ NV_STATUS __nvoc_objCreate_KernelChannel(KernelChannel**, Dynamic*, NvU32, CALL_ #define kchannelGetMemoryMappingDescriptor(pRmResource, ppMemDesc) kchannelGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define kchannelControlFilter(pResource, pCallContext, pParams) kchannelControlFilter_DISPATCH(pResource, pCallContext, pParams) #define kchannelUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) kchannelUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define kchannelControlSerialization_Prologue(pResource, pCallContext, pParams) kchannelControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define kchannelCanCopy(pResource) kchannelCanCopy_DISPATCH(pResource) #define kchannelPreDestruct(pResource) kchannelPreDestruct_DISPATCH(pResource) #define kchannelIsDuplicate(pResource, hMemory, pDuplicate) kchannelIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define kchannelControlSerialization_Epilogue(pResource, pCallContext, pParams) kchannelControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define kchannelGetNotificationListPtr(pNotifier) kchannelGetNotificationListPtr_DISPATCH(pNotifier) #define kchannelGetNotificationShare(pNotifier) kchannelGetNotificationShare_DISPATCH(pNotifier) #define kchannelAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) kchannelAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) @@ -1095,14 +1099,14 @@ static inline NvBool kchannelShareCallback_DISPATCH(struct KernelChannel *pGpuRe return pGpuResource->__kchannelShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS kchannelMapTo_DISPATCH(struct KernelChannel *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__kchannelMapTo__(pResource, pParams); -} - static inline NV_STATUS kchannelGetOrAllocNotifShare_DISPATCH(struct KernelChannel *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return pNotifier->__kchannelGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); } +static inline NV_STATUS kchannelMapTo_DISPATCH(struct KernelChannel *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__kchannelMapTo__(pResource, pParams); +} + static inline void kchannelSetNotificationShare_DISPATCH(struct KernelChannel *pNotifier, struct NotifShare *pNotifShare) { pNotifier->__kchannelSetNotificationShare__(pNotifier, pNotifShare); } @@ -1159,6 +1163,10 @@ static inline NV_STATUS kchannelUnregisterEvent_DISPATCH(struct KernelChannel *p return pNotifier->__kchannelUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS kchannelControlSerialization_Prologue_DISPATCH(struct KernelChannel *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__kchannelControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool kchannelCanCopy_DISPATCH(struct KernelChannel *pResource) { return pResource->__kchannelCanCopy__(pResource); } @@ -1171,6 +1179,10 @@ static inline NV_STATUS kchannelIsDuplicate_DISPATCH(struct KernelChannel *pReso return pResource->__kchannelIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void kchannelControlSerialization_Epilogue_DISPATCH(struct KernelChannel *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__kchannelControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *kchannelGetNotificationListPtr_DISPATCH(struct KernelChannel *pNotifier) { return pNotifier->__kchannelGetNotificationListPtr__(pNotifier); } diff --git a/src/nvidia/generated/g_kernel_ctxshare_nvoc.c b/src/nvidia/generated/g_kernel_ctxshare_nvoc.c index 25033deef..f6e477dba 100644 --- a/src/nvidia/generated/g_kernel_ctxshare_nvoc.c +++ b/src/nvidia/generated/g_kernel_ctxshare_nvoc.c @@ -135,13 +135,16 @@ NV_STATUS __nvoc_objCreate_KernelCtxShare(KernelCtxShare **ppThis, Dynamic *pPar KernelCtxShare *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelCtxShare)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelCtxShare), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelCtxShare)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelCtxShare); + pThis->__nvoc_base_RsShared.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -161,11 +164,17 @@ NV_STATUS __nvoc_objCreate_KernelCtxShare(KernelCtxShare **ppThis, Dynamic *pPar if (status != NV_OK) goto __nvoc_objCreate_KernelCtxShare_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelCtxShare_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelCtxShare)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -271,6 +280,54 @@ static NvBool __nvoc_thunk_GpuResource_kctxshareapiShareCallback(struct KernelCt return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCtxShareApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } +static NV_STATUS __nvoc_thunk_RmResource_kctxshareapiCheckMemInterUnmap(struct KernelCtxShareApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelCtxShareApi_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_kctxshareapiMapTo(struct KernelCtxShareApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_kctxshareapiGetMapAddrSpace(struct KernelCtxShareApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCtxShareApi_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_kctxshareapiGetRefCount(struct KernelCtxShareApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_kctxshareapiAddAdditionalDependants(struct RsClient *pClient, struct KernelCtxShareApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_kctxshareapiControl_Prologue(struct KernelCtxShareApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_kctxshareapiGetRegBaseOffsetAndSize(struct KernelCtxShareApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCtxShareApi_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_kctxshareapiInternalControlForward(struct KernelCtxShareApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCtxShareApi_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_kctxshareapiUnmapFrom(struct KernelCtxShareApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_kctxshareapiControl_Epilogue(struct KernelCtxShareApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_kctxshareapiControlLookup(struct KernelCtxShareApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset), pParams, ppEntry); +} + +static NvHandle __nvoc_thunk_GpuResource_kctxshareapiGetInternalObjectHandle(struct KernelCtxShareApi *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCtxShareApi_GpuResource.offset)); +} + static NV_STATUS __nvoc_thunk_GpuResource_kctxshareapiControl(struct KernelCtxShareApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCtxShareApi_GpuResource.offset), pCallContext, pParams); } @@ -287,64 +344,24 @@ static NV_STATUS __nvoc_thunk_RmResource_kctxshareapiGetMemoryMappingDescriptor( return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelCtxShareApi_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_GpuResource_kctxshareapiGetMapAddrSpace(struct KernelCtxShareApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCtxShareApi_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvHandle __nvoc_thunk_GpuResource_kctxshareapiGetInternalObjectHandle(struct KernelCtxShareApi *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCtxShareApi_GpuResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_kctxshareapiControlFilter(struct KernelCtxShareApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_kctxshareapiAddAdditionalDependants(struct RsClient *pClient, struct KernelCtxShareApi *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_kctxshareapiGetRefCount(struct KernelCtxShareApi *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RmResource_kctxshareapiCheckMemInterUnmap(struct KernelCtxShareApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelCtxShareApi_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_kctxshareapiMapTo(struct KernelCtxShareApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_kctxshareapiControl_Prologue(struct KernelCtxShareApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_GpuResource_kctxshareapiGetRegBaseOffsetAndSize(struct KernelCtxShareApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCtxShareApi_GpuResource.offset), pGpu, pOffset, pSize); -} - -static NV_STATUS __nvoc_thunk_GpuResource_kctxshareapiInternalControlForward(struct KernelCtxShareApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCtxShareApi_GpuResource.offset), command, pParams, size); +static NV_STATUS __nvoc_thunk_RmResource_kctxshareapiControlSerialization_Prologue(struct KernelCtxShareApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RmResource.offset), pCallContext, pParams); } static void __nvoc_thunk_RsResource_kctxshareapiPreDestruct(struct KernelCtxShareApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_kctxshareapiUnmapFrom(struct KernelCtxShareApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_kctxshareapiIsDuplicate(struct KernelCtxShareApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset), hMemory, pDuplicate); } -static void __nvoc_thunk_RmResource_kctxshareapiControl_Epilogue(struct KernelCtxShareApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_kctxshareapiControlLookup(struct KernelCtxShareApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_kctxshareapiControlSerialization_Epilogue(struct KernelCtxShareApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_kctxshareapiMap(struct KernelCtxShareApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -466,6 +483,30 @@ static void __nvoc_init_funcTable_KernelCtxShareApi_1(KernelCtxShareApi *pThis) pThis->__kctxshareapiShareCallback__ = &__nvoc_thunk_GpuResource_kctxshareapiShareCallback; + pThis->__kctxshareapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_kctxshareapiCheckMemInterUnmap; + + pThis->__kctxshareapiMapTo__ = &__nvoc_thunk_RsResource_kctxshareapiMapTo; + + pThis->__kctxshareapiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_kctxshareapiGetMapAddrSpace; + + pThis->__kctxshareapiGetRefCount__ = &__nvoc_thunk_RsResource_kctxshareapiGetRefCount; + + pThis->__kctxshareapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_kctxshareapiAddAdditionalDependants; + + pThis->__kctxshareapiControl_Prologue__ = &__nvoc_thunk_RmResource_kctxshareapiControl_Prologue; + + pThis->__kctxshareapiGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_kctxshareapiGetRegBaseOffsetAndSize; + + pThis->__kctxshareapiInternalControlForward__ = &__nvoc_thunk_GpuResource_kctxshareapiInternalControlForward; + + pThis->__kctxshareapiUnmapFrom__ = &__nvoc_thunk_RsResource_kctxshareapiUnmapFrom; + + pThis->__kctxshareapiControl_Epilogue__ = &__nvoc_thunk_RmResource_kctxshareapiControl_Epilogue; + + pThis->__kctxshareapiControlLookup__ = &__nvoc_thunk_RsResource_kctxshareapiControlLookup; + + pThis->__kctxshareapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_kctxshareapiGetInternalObjectHandle; + pThis->__kctxshareapiControl__ = &__nvoc_thunk_GpuResource_kctxshareapiControl; pThis->__kctxshareapiUnmap__ = &__nvoc_thunk_GpuResource_kctxshareapiUnmap; @@ -474,35 +515,15 @@ static void __nvoc_init_funcTable_KernelCtxShareApi_1(KernelCtxShareApi *pThis) pThis->__kctxshareapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_kctxshareapiGetMemoryMappingDescriptor; - pThis->__kctxshareapiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_kctxshareapiGetMapAddrSpace; - - pThis->__kctxshareapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_kctxshareapiGetInternalObjectHandle; - pThis->__kctxshareapiControlFilter__ = &__nvoc_thunk_RsResource_kctxshareapiControlFilter; - pThis->__kctxshareapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_kctxshareapiAddAdditionalDependants; - - pThis->__kctxshareapiGetRefCount__ = &__nvoc_thunk_RsResource_kctxshareapiGetRefCount; - - pThis->__kctxshareapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_kctxshareapiCheckMemInterUnmap; - - pThis->__kctxshareapiMapTo__ = &__nvoc_thunk_RsResource_kctxshareapiMapTo; - - pThis->__kctxshareapiControl_Prologue__ = &__nvoc_thunk_RmResource_kctxshareapiControl_Prologue; - - pThis->__kctxshareapiGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_kctxshareapiGetRegBaseOffsetAndSize; - - pThis->__kctxshareapiInternalControlForward__ = &__nvoc_thunk_GpuResource_kctxshareapiInternalControlForward; + pThis->__kctxshareapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_kctxshareapiControlSerialization_Prologue; pThis->__kctxshareapiPreDestruct__ = &__nvoc_thunk_RsResource_kctxshareapiPreDestruct; - pThis->__kctxshareapiUnmapFrom__ = &__nvoc_thunk_RsResource_kctxshareapiUnmapFrom; - pThis->__kctxshareapiIsDuplicate__ = &__nvoc_thunk_RsResource_kctxshareapiIsDuplicate; - pThis->__kctxshareapiControl_Epilogue__ = &__nvoc_thunk_RmResource_kctxshareapiControl_Epilogue; - - pThis->__kctxshareapiControlLookup__ = &__nvoc_thunk_RsResource_kctxshareapiControlLookup; + pThis->__kctxshareapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_kctxshareapiControlSerialization_Epilogue; pThis->__kctxshareapiMap__ = &__nvoc_thunk_GpuResource_kctxshareapiMap; @@ -530,13 +551,16 @@ NV_STATUS __nvoc_objCreate_KernelCtxShareApi(KernelCtxShareApi **ppThis, Dynamic Object *pParentObj; KernelCtxShareApi *pThis; - pThis = portMemAllocNonPaged(sizeof(KernelCtxShareApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelCtxShareApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelCtxShareApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelCtxShareApi); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -552,11 +576,17 @@ NV_STATUS __nvoc_objCreate_KernelCtxShareApi(KernelCtxShareApi **ppThis, Dynamic if (status != NV_OK) goto __nvoc_objCreate_KernelCtxShareApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelCtxShareApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelCtxShareApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_ctxshare_nvoc.h b/src/nvidia/generated/g_kernel_ctxshare_nvoc.h index 159f5b24e..6bdffeb6d 100644 --- a/src/nvidia/generated/g_kernel_ctxshare_nvoc.h +++ b/src/nvidia/generated/g_kernel_ctxshare_nvoc.h @@ -206,25 +206,27 @@ struct KernelCtxShareApi { NV_STATUS (*__kctxshareapiCtrlCmdGetCwdWatermark__)(struct KernelCtxShareApi *, NV9067_CTRL_CWD_WATERMARK_PARAMS *); NV_STATUS (*__kctxshareapiCtrlCmdSetCwdWatermark__)(struct KernelCtxShareApi *, NV9067_CTRL_CWD_WATERMARK_PARAMS *); NvBool (*__kctxshareapiShareCallback__)(struct KernelCtxShareApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__kctxshareapiCheckMemInterUnmap__)(struct KernelCtxShareApi *, NvBool); + NV_STATUS (*__kctxshareapiMapTo__)(struct KernelCtxShareApi *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__kctxshareapiGetMapAddrSpace__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__kctxshareapiGetRefCount__)(struct KernelCtxShareApi *); + void (*__kctxshareapiAddAdditionalDependants__)(struct RsClient *, struct KernelCtxShareApi *, RsResourceRef *); + NV_STATUS (*__kctxshareapiControl_Prologue__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kctxshareapiGetRegBaseOffsetAndSize__)(struct KernelCtxShareApi *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__kctxshareapiInternalControlForward__)(struct KernelCtxShareApi *, NvU32, void *, NvU32); + NV_STATUS (*__kctxshareapiUnmapFrom__)(struct KernelCtxShareApi *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__kctxshareapiControl_Epilogue__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kctxshareapiControlLookup__)(struct KernelCtxShareApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__kctxshareapiGetInternalObjectHandle__)(struct KernelCtxShareApi *); NV_STATUS (*__kctxshareapiControl__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kctxshareapiUnmap__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__kctxshareapiGetMemInterMapParams__)(struct KernelCtxShareApi *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__kctxshareapiGetMemoryMappingDescriptor__)(struct KernelCtxShareApi *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__kctxshareapiGetMapAddrSpace__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__kctxshareapiGetInternalObjectHandle__)(struct KernelCtxShareApi *); NV_STATUS (*__kctxshareapiControlFilter__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__kctxshareapiAddAdditionalDependants__)(struct RsClient *, struct KernelCtxShareApi *, RsResourceRef *); - NvU32 (*__kctxshareapiGetRefCount__)(struct KernelCtxShareApi *); - NV_STATUS (*__kctxshareapiCheckMemInterUnmap__)(struct KernelCtxShareApi *, NvBool); - NV_STATUS (*__kctxshareapiMapTo__)(struct KernelCtxShareApi *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__kctxshareapiControl_Prologue__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__kctxshareapiGetRegBaseOffsetAndSize__)(struct KernelCtxShareApi *, struct OBJGPU *, NvU32 *, NvU32 *); - NV_STATUS (*__kctxshareapiInternalControlForward__)(struct KernelCtxShareApi *, NvU32, void *, NvU32); + NV_STATUS (*__kctxshareapiControlSerialization_Prologue__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__kctxshareapiPreDestruct__)(struct KernelCtxShareApi *); - NV_STATUS (*__kctxshareapiUnmapFrom__)(struct KernelCtxShareApi *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__kctxshareapiIsDuplicate__)(struct KernelCtxShareApi *, NvHandle, NvBool *); - void (*__kctxshareapiControl_Epilogue__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__kctxshareapiControlLookup__)(struct KernelCtxShareApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__kctxshareapiControlSerialization_Epilogue__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kctxshareapiMap__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__kctxshareapiAccessCallback__)(struct KernelCtxShareApi *, struct RsClient *, void *, RsAccessRight); struct KernelCtxShare *pShareData; @@ -264,25 +266,27 @@ NV_STATUS __nvoc_objCreate_KernelCtxShareApi(KernelCtxShareApi**, Dynamic*, NvU3 #define kctxshareapiCtrlCmdGetCwdWatermark(pKernelCtxShareApi, pParams) kctxshareapiCtrlCmdGetCwdWatermark_DISPATCH(pKernelCtxShareApi, pParams) #define kctxshareapiCtrlCmdSetCwdWatermark(pKernelCtxShareApi, pParams) kctxshareapiCtrlCmdSetCwdWatermark_DISPATCH(pKernelCtxShareApi, pParams) #define kctxshareapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) kctxshareapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define kctxshareapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) kctxshareapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define kctxshareapiMapTo(pResource, pParams) kctxshareapiMapTo_DISPATCH(pResource, pParams) +#define kctxshareapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) kctxshareapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define kctxshareapiGetRefCount(pResource) kctxshareapiGetRefCount_DISPATCH(pResource) +#define kctxshareapiAddAdditionalDependants(pClient, pResource, pReference) kctxshareapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define kctxshareapiControl_Prologue(pResource, pCallContext, pParams) kctxshareapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define kctxshareapiGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) kctxshareapiGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define kctxshareapiInternalControlForward(pGpuResource, command, pParams, size) kctxshareapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define kctxshareapiUnmapFrom(pResource, pParams) kctxshareapiUnmapFrom_DISPATCH(pResource, pParams) +#define kctxshareapiControl_Epilogue(pResource, pCallContext, pParams) kctxshareapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define kctxshareapiControlLookup(pResource, pParams, ppEntry) kctxshareapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define kctxshareapiGetInternalObjectHandle(pGpuResource) kctxshareapiGetInternalObjectHandle_DISPATCH(pGpuResource) #define kctxshareapiControl(pGpuResource, pCallContext, pParams) kctxshareapiControl_DISPATCH(pGpuResource, pCallContext, pParams) #define kctxshareapiUnmap(pGpuResource, pCallContext, pCpuMapping) kctxshareapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define kctxshareapiGetMemInterMapParams(pRmResource, pParams) kctxshareapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define kctxshareapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) kctxshareapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define kctxshareapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) kctxshareapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define kctxshareapiGetInternalObjectHandle(pGpuResource) kctxshareapiGetInternalObjectHandle_DISPATCH(pGpuResource) #define kctxshareapiControlFilter(pResource, pCallContext, pParams) kctxshareapiControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define kctxshareapiAddAdditionalDependants(pClient, pResource, pReference) kctxshareapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define kctxshareapiGetRefCount(pResource) kctxshareapiGetRefCount_DISPATCH(pResource) -#define kctxshareapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) kctxshareapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define kctxshareapiMapTo(pResource, pParams) kctxshareapiMapTo_DISPATCH(pResource, pParams) -#define kctxshareapiControl_Prologue(pResource, pCallContext, pParams) kctxshareapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define kctxshareapiGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) kctxshareapiGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) -#define kctxshareapiInternalControlForward(pGpuResource, command, pParams, size) kctxshareapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define kctxshareapiControlSerialization_Prologue(pResource, pCallContext, pParams) kctxshareapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define kctxshareapiPreDestruct(pResource) kctxshareapiPreDestruct_DISPATCH(pResource) -#define kctxshareapiUnmapFrom(pResource, pParams) kctxshareapiUnmapFrom_DISPATCH(pResource, pParams) #define kctxshareapiIsDuplicate(pResource, hMemory, pDuplicate) kctxshareapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) -#define kctxshareapiControl_Epilogue(pResource, pCallContext, pParams) kctxshareapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define kctxshareapiControlLookup(pResource, pParams, ppEntry) kctxshareapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define kctxshareapiControlSerialization_Epilogue(pResource, pCallContext, pParams) kctxshareapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define kctxshareapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) kctxshareapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define kctxshareapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) kctxshareapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool kctxshareapiCanCopy_IMPL(struct KernelCtxShareApi *pKernelCtxShareApi); @@ -313,6 +317,54 @@ static inline NvBool kctxshareapiShareCallback_DISPATCH(struct KernelCtxShareApi return pGpuResource->__kctxshareapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } +static inline NV_STATUS kctxshareapiCheckMemInterUnmap_DISPATCH(struct KernelCtxShareApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__kctxshareapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS kctxshareapiMapTo_DISPATCH(struct KernelCtxShareApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__kctxshareapiMapTo__(pResource, pParams); +} + +static inline NV_STATUS kctxshareapiGetMapAddrSpace_DISPATCH(struct KernelCtxShareApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__kctxshareapiGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 kctxshareapiGetRefCount_DISPATCH(struct KernelCtxShareApi *pResource) { + return pResource->__kctxshareapiGetRefCount__(pResource); +} + +static inline void kctxshareapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct KernelCtxShareApi *pResource, RsResourceRef *pReference) { + pResource->__kctxshareapiAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS kctxshareapiControl_Prologue_DISPATCH(struct KernelCtxShareApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__kctxshareapiControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS kctxshareapiGetRegBaseOffsetAndSize_DISPATCH(struct KernelCtxShareApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__kctxshareapiGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS kctxshareapiInternalControlForward_DISPATCH(struct KernelCtxShareApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__kctxshareapiInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS kctxshareapiUnmapFrom_DISPATCH(struct KernelCtxShareApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__kctxshareapiUnmapFrom__(pResource, pParams); +} + +static inline void kctxshareapiControl_Epilogue_DISPATCH(struct KernelCtxShareApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__kctxshareapiControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS kctxshareapiControlLookup_DISPATCH(struct KernelCtxShareApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__kctxshareapiControlLookup__(pResource, pParams, ppEntry); +} + +static inline NvHandle kctxshareapiGetInternalObjectHandle_DISPATCH(struct KernelCtxShareApi *pGpuResource) { + return pGpuResource->__kctxshareapiGetInternalObjectHandle__(pGpuResource); +} + static inline NV_STATUS kctxshareapiControl_DISPATCH(struct KernelCtxShareApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pGpuResource->__kctxshareapiControl__(pGpuResource, pCallContext, pParams); } @@ -329,64 +381,24 @@ static inline NV_STATUS kctxshareapiGetMemoryMappingDescriptor_DISPATCH(struct K return pRmResource->__kctxshareapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS kctxshareapiGetMapAddrSpace_DISPATCH(struct KernelCtxShareApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__kctxshareapiGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvHandle kctxshareapiGetInternalObjectHandle_DISPATCH(struct KernelCtxShareApi *pGpuResource) { - return pGpuResource->__kctxshareapiGetInternalObjectHandle__(pGpuResource); -} - static inline NV_STATUS kctxshareapiControlFilter_DISPATCH(struct KernelCtxShareApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__kctxshareapiControlFilter__(pResource, pCallContext, pParams); } -static inline void kctxshareapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct KernelCtxShareApi *pResource, RsResourceRef *pReference) { - pResource->__kctxshareapiAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 kctxshareapiGetRefCount_DISPATCH(struct KernelCtxShareApi *pResource) { - return pResource->__kctxshareapiGetRefCount__(pResource); -} - -static inline NV_STATUS kctxshareapiCheckMemInterUnmap_DISPATCH(struct KernelCtxShareApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__kctxshareapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS kctxshareapiMapTo_DISPATCH(struct KernelCtxShareApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__kctxshareapiMapTo__(pResource, pParams); -} - -static inline NV_STATUS kctxshareapiControl_Prologue_DISPATCH(struct KernelCtxShareApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__kctxshareapiControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS kctxshareapiGetRegBaseOffsetAndSize_DISPATCH(struct KernelCtxShareApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__kctxshareapiGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); -} - -static inline NV_STATUS kctxshareapiInternalControlForward_DISPATCH(struct KernelCtxShareApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__kctxshareapiInternalControlForward__(pGpuResource, command, pParams, size); +static inline NV_STATUS kctxshareapiControlSerialization_Prologue_DISPATCH(struct KernelCtxShareApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__kctxshareapiControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline void kctxshareapiPreDestruct_DISPATCH(struct KernelCtxShareApi *pResource) { pResource->__kctxshareapiPreDestruct__(pResource); } -static inline NV_STATUS kctxshareapiUnmapFrom_DISPATCH(struct KernelCtxShareApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__kctxshareapiUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS kctxshareapiIsDuplicate_DISPATCH(struct KernelCtxShareApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__kctxshareapiIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline void kctxshareapiControl_Epilogue_DISPATCH(struct KernelCtxShareApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__kctxshareapiControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS kctxshareapiControlLookup_DISPATCH(struct KernelCtxShareApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__kctxshareapiControlLookup__(pResource, pParams, ppEntry); +static inline void kctxshareapiControlSerialization_Epilogue_DISPATCH(struct KernelCtxShareApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__kctxshareapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS kctxshareapiMap_DISPATCH(struct KernelCtxShareApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_kernel_falcon_nvoc.c b/src/nvidia/generated/g_kernel_falcon_nvoc.c index 203f22c71..97113bb73 100644 --- a/src/nvidia/generated/g_kernel_falcon_nvoc.c +++ b/src/nvidia/generated/g_kernel_falcon_nvoc.c @@ -36,7 +36,6 @@ static const struct NVOC_CASTINFO __nvoc_castinfo_KernelFalcon = { // Not instantiable because it's not derived from class "Object" // Not instantiable because it's an abstract class with following pure virtual functions: // kflcnResetHw -// kflcnIsEngineInReset const struct NVOC_CLASS_DEF __nvoc_class_def_KernelFalcon = { /*classInfo=*/ { @@ -165,8 +164,6 @@ static void __nvoc_init_funcTable_KernelFalcon_1(KernelFalcon *pThis, RmHalspecO } } - pThis->__kflcnIsEngineInReset__ = NULL; - // Hal function -- kflcnReadIntrStatus if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { @@ -301,11 +298,7 @@ static NV_STATUS __nvoc_thunk_GenericKernelFalcon_kflcnResetHw(struct OBJGPU *pG return gkflcnResetHw(pGpu, (struct GenericKernelFalcon *)(((unsigned char *)pGenKernFlcn) - __nvoc_rtti_GenericKernelFalcon_KernelFalcon.offset)); } -static NvBool __nvoc_thunk_GenericKernelFalcon_kflcnIsEngineInReset(struct OBJGPU *pGpu, struct KernelFalcon *pGenKernFlcn) { - return gkflcnIsEngineInReset(pGpu, (struct GenericKernelFalcon *)(((unsigned char *)pGenKernFlcn) - __nvoc_rtti_GenericKernelFalcon_KernelFalcon.offset)); -} - -static void __nvoc_thunk_GenericKernelFalcon_intrservRegisterIntrService(struct OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[163]) { +static void __nvoc_thunk_GenericKernelFalcon_intrservRegisterIntrService(struct OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[166]) { gkflcnRegisterIntrService(arg0, (struct GenericKernelFalcon *)(((unsigned char *)arg1) - __nvoc_rtti_GenericKernelFalcon_IntrService.offset), arg2); } @@ -375,16 +368,12 @@ static void __nvoc_init_funcTable_GenericKernelFalcon_1(GenericKernelFalcon *pTh pThis->__gkflcnResetHw__ = &gkflcnResetHw_IMPL; - pThis->__gkflcnIsEngineInReset__ = &gkflcnIsEngineInReset_IMPL; - pThis->__gkflcnRegisterIntrService__ = &gkflcnRegisterIntrService_IMPL; pThis->__gkflcnServiceNotificationInterrupt__ = &gkflcnServiceNotificationInterrupt_IMPL; pThis->__nvoc_base_KernelFalcon.__kflcnResetHw__ = &__nvoc_thunk_GenericKernelFalcon_kflcnResetHw; - pThis->__nvoc_base_KernelFalcon.__kflcnIsEngineInReset__ = &__nvoc_thunk_GenericKernelFalcon_kflcnIsEngineInReset; - pThis->__nvoc_base_IntrService.__intrservRegisterIntrService__ = &__nvoc_thunk_GenericKernelFalcon_intrservRegisterIntrService; pThis->__nvoc_base_IntrService.__intrservServiceNotificationInterrupt__ = &__nvoc_thunk_GenericKernelFalcon_intrservServiceNotificationInterrupt; @@ -418,13 +407,16 @@ NV_STATUS __nvoc_objCreate_GenericKernelFalcon(GenericKernelFalcon **ppThis, Dyn GenericKernelFalcon *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(GenericKernelFalcon)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(GenericKernelFalcon), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(GenericKernelFalcon)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_GenericKernelFalcon); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -444,11 +436,17 @@ NV_STATUS __nvoc_objCreate_GenericKernelFalcon(GenericKernelFalcon **ppThis, Dyn if (status != NV_OK) goto __nvoc_objCreate_GenericKernelFalcon_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_GenericKernelFalcon_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(GenericKernelFalcon)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_falcon_nvoc.h b/src/nvidia/generated/g_kernel_falcon_nvoc.h index 00ffe25e1..4d1263fb3 100644 --- a/src/nvidia/generated/g_kernel_falcon_nvoc.h +++ b/src/nvidia/generated/g_kernel_falcon_nvoc.h @@ -86,7 +86,6 @@ struct KernelFalcon { NV_STATUS (*__kflcnResetHw__)(struct OBJGPU *, struct KernelFalcon *); NV_STATUS (*__kflcnPreResetWait__)(struct OBJGPU *, struct KernelFalcon *); NV_STATUS (*__kflcnWaitForResetToFinish__)(struct OBJGPU *, struct KernelFalcon *); - NvBool (*__kflcnIsEngineInReset__)(struct OBJGPU *, struct KernelFalcon *); NvU32 (*__kflcnReadIntrStatus__)(struct OBJGPU *, struct KernelFalcon *); void (*__kflcnIntrRetrigger__)(struct OBJGPU *, struct KernelFalcon *); NvU32 (*__kflcnMaskImemAddr__)(struct OBJGPU *, struct KernelFalcon *, NvU32); @@ -142,7 +141,6 @@ NV_STATUS __nvoc_objCreate_KernelFalcon(KernelFalcon**, Dynamic*, NvU32); #define kflcnPreResetWait_HAL(pGpu, pKernelFlcn) kflcnPreResetWait_DISPATCH(pGpu, pKernelFlcn) #define kflcnWaitForResetToFinish(pGpu, pKernelFlcn) kflcnWaitForResetToFinish_DISPATCH(pGpu, pKernelFlcn) #define kflcnWaitForResetToFinish_HAL(pGpu, pKernelFlcn) kflcnWaitForResetToFinish_DISPATCH(pGpu, pKernelFlcn) -#define kflcnIsEngineInReset(pGpu, pKernelFlcn) kflcnIsEngineInReset_DISPATCH(pGpu, pKernelFlcn) #define kflcnReadIntrStatus(pGpu, pKerneFlcn) kflcnReadIntrStatus_DISPATCH(pGpu, pKerneFlcn) #define kflcnReadIntrStatus_HAL(pGpu, pKerneFlcn) kflcnReadIntrStatus_DISPATCH(pGpu, pKerneFlcn) #define kflcnIntrRetrigger(pGpu, pKernelFlcn) kflcnIntrRetrigger_DISPATCH(pGpu, pKernelFlcn) @@ -348,10 +346,6 @@ static inline NV_STATUS kflcnWaitForResetToFinish_DISPATCH(struct OBJGPU *pGpu, return pKernelFlcn->__kflcnWaitForResetToFinish__(pGpu, pKernelFlcn); } -static inline NvBool kflcnIsEngineInReset_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { - return pKernelFlcn->__kflcnIsEngineInReset__(pGpu, pKernelFlcn); -} - NvU32 kflcnReadIntrStatus_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKerneFlcn); NvU32 kflcnReadIntrStatus_GA102(struct OBJGPU *pGpu, struct KernelFalcon *pKerneFlcn); @@ -440,7 +434,6 @@ struct GenericKernelFalcon { struct Object *__nvoc_pbase_Object; struct GenericKernelFalcon *__nvoc_pbase_GenericKernelFalcon; NV_STATUS (*__gkflcnResetHw__)(struct OBJGPU *, struct GenericKernelFalcon *); - NvBool (*__gkflcnIsEngineInReset__)(struct OBJGPU *, struct GenericKernelFalcon *); void (*__gkflcnRegisterIntrService__)(struct OBJGPU *, struct GenericKernelFalcon *, IntrServiceRecord *); NV_STATUS (*__gkflcnServiceNotificationInterrupt__)(struct OBJGPU *, struct GenericKernelFalcon *, IntrServiceServiceNotificationInterruptArguments *); NvBool (*__gkflcnClearInterrupt__)(struct OBJGPU *, struct GenericKernelFalcon *, IntrServiceClearInterruptArguments *); @@ -476,7 +469,6 @@ NV_STATUS __nvoc_objCreate_GenericKernelFalcon(GenericKernelFalcon**, Dynamic*, __nvoc_objCreate_GenericKernelFalcon((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pGpu, arg_pFalconConfig) #define gkflcnResetHw(pGpu, pGenKernFlcn) gkflcnResetHw_DISPATCH(pGpu, pGenKernFlcn) -#define gkflcnIsEngineInReset(pGpu, pGenKernFlcn) gkflcnIsEngineInReset_DISPATCH(pGpu, pGenKernFlcn) #define gkflcnRegisterIntrService(arg0, arg1, arg2) gkflcnRegisterIntrService_DISPATCH(arg0, arg1, arg2) #define gkflcnServiceNotificationInterrupt(arg0, arg1, arg2) gkflcnServiceNotificationInterrupt_DISPATCH(arg0, arg1, arg2) #define gkflcnClearInterrupt(pGpu, pIntrService, pParams) gkflcnClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) @@ -487,15 +479,9 @@ static inline NV_STATUS gkflcnResetHw_DISPATCH(struct OBJGPU *pGpu, struct Gener return pGenKernFlcn->__gkflcnResetHw__(pGpu, pGenKernFlcn); } -NvBool gkflcnIsEngineInReset_IMPL(struct OBJGPU *pGpu, struct GenericKernelFalcon *pGenKernFlcn); +void gkflcnRegisterIntrService_IMPL(struct OBJGPU *arg0, struct GenericKernelFalcon *arg1, IntrServiceRecord arg2[166]); -static inline NvBool gkflcnIsEngineInReset_DISPATCH(struct OBJGPU *pGpu, struct GenericKernelFalcon *pGenKernFlcn) { - return pGenKernFlcn->__gkflcnIsEngineInReset__(pGpu, pGenKernFlcn); -} - -void gkflcnRegisterIntrService_IMPL(struct OBJGPU *arg0, struct GenericKernelFalcon *arg1, IntrServiceRecord arg2[163]); - -static inline void gkflcnRegisterIntrService_DISPATCH(struct OBJGPU *arg0, struct GenericKernelFalcon *arg1, IntrServiceRecord arg2[163]) { +static inline void gkflcnRegisterIntrService_DISPATCH(struct OBJGPU *arg0, struct GenericKernelFalcon *arg1, IntrServiceRecord arg2[166]) { arg1->__gkflcnRegisterIntrService__(arg0, arg1, arg2); } diff --git a/src/nvidia/generated/g_kernel_fifo_nvoc.c b/src/nvidia/generated/g_kernel_fifo_nvoc.c index 78e39bd7a..d368d2840 100644 --- a/src/nvidia/generated/g_kernel_fifo_nvoc.c +++ b/src/nvidia/generated/g_kernel_fifo_nvoc.c @@ -86,10 +86,6 @@ static NV_STATUS __nvoc_thunk_KernelFifo_engstateStatePreUnload(struct OBJGPU *p return kfifoStatePreUnload(pGpu, (struct KernelFifo *)(((unsigned char *)pKernelFifo) - __nvoc_rtti_KernelFifo_OBJENGSTATE.offset), flags); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfifoReconcileTunableState(POBJGPU pGpu, struct KernelFifo *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFifo_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfifoStateLoad(POBJGPU pGpu, struct KernelFifo *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFifo_OBJENGSTATE.offset), arg0); } @@ -122,26 +118,6 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfifoStatePreInitUnlocked(POBJGPU pGpu return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFifo_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfifoGetTunableState(POBJGPU pGpu, struct KernelFifo *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFifo_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfifoCompareTunableState(POBJGPU pGpu, struct KernelFifo *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFifo_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kfifoFreeTunableState(POBJGPU pGpu, struct KernelFifo *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFifo_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfifoAllocTunableState(POBJGPU pGpu, struct KernelFifo *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFifo_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfifoSetTunableState(POBJGPU pGpu, struct KernelFifo *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFifo_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_kfifoIsPresent(POBJGPU pGpu, struct KernelFifo *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFifo_OBJENGSTATE.offset)); } @@ -383,16 +359,6 @@ static void __nvoc_init_funcTable_KernelFifo_1(KernelFifo *pThis, RmHalspecOwner pThis->__kfifoGetMaxCeChannelGroups__ = &kfifoGetMaxCeChannelGroups_GA100; } - // Hal function -- kfifoSetupUserD - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ - { - pThis->__kfifoSetupUserD__ = &kfifoSetupUserD_GM107; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kfifoSetupUserD__ = &kfifoSetupUserD_GA100; - } - pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelFifo_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_KernelFifo_engstateStateInitLocked; @@ -403,8 +369,6 @@ static void __nvoc_init_funcTable_KernelFifo_1(KernelFifo *pThis, RmHalspecOwner pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreUnload__ = &__nvoc_thunk_KernelFifo_engstateStatePreUnload; - pThis->__kfifoReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kfifoReconcileTunableState; - pThis->__kfifoStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kfifoStateLoad; pThis->__kfifoStateUnload__ = &__nvoc_thunk_OBJENGSTATE_kfifoStateUnload; @@ -421,16 +385,6 @@ static void __nvoc_init_funcTable_KernelFifo_1(KernelFifo *pThis, RmHalspecOwner pThis->__kfifoStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kfifoStatePreInitUnlocked; - pThis->__kfifoGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kfifoGetTunableState; - - pThis->__kfifoCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kfifoCompareTunableState; - - pThis->__kfifoFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kfifoFreeTunableState; - - pThis->__kfifoAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kfifoAllocTunableState; - - pThis->__kfifoSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kfifoSetTunableState; - pThis->__kfifoIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kfifoIsPresent; } @@ -453,13 +407,16 @@ NV_STATUS __nvoc_objCreate_KernelFifo(KernelFifo **ppThis, Dynamic *pParent, NvU KernelFifo *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelFifo)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelFifo), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelFifo)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelFifo); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -479,11 +436,17 @@ NV_STATUS __nvoc_objCreate_KernelFifo(KernelFifo **ppThis, Dynamic *pParent, NvU if (status != NV_OK) goto __nvoc_objCreate_KernelFifo_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelFifo_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelFifo)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_fifo_nvoc.h b/src/nvidia/generated/g_kernel_fifo_nvoc.h index 3d0d999b0..a72cc768b 100644 --- a/src/nvidia/generated/g_kernel_fifo_nvoc.h +++ b/src/nvidia/generated/g_kernel_fifo_nvoc.h @@ -56,6 +56,8 @@ extern "C" { #include "ctrl/ctrl2080/ctrl2080internal.h" // NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_* #include "ctrl/ctrl906f.h" +#include "class/clc369.h" // MMU_FAULT_BUFFER + struct KernelChannel; #ifndef __NVOC_CLASS_KernelChannel_TYPEDEF__ @@ -116,6 +118,9 @@ MAKE_BITVECTOR(CHID_MGR_VALID_BIT_VECTOR, MAX_NUM_RUNLISTS); #define VID_PB_ALLOWED 0x1 #define PCI_PB_ALLOWED 0x2 +#define PBDMA_FAULT_MAX_ID (0x1 << DRF_SIZE_MW(NVC369_BUF_ENTRY_ENGINE_ID)) +MAKE_BITVECTOR(PBDMA_ID_BITVECTOR, PBDMA_FAULT_MAX_ID); + /*! * USERD isolation domain * @@ -274,42 +279,87 @@ struct channel_iterator typedef enum { + /* ************************************************************************* + * Bug 3820969 + * THINK BEFORE CHANGING ENUM ORDER HERE. + * VGPU-guest uses this same ordering. Because this enum is not versioned, + * changing the order here WILL BREAK old-guest-on-newer-host compatibility. + * ************************************************************************/ + // *ENG_XYZ, e.g.: ENG_GR, ENG_CE etc., ENGINE_INFO_TYPE_ENG_DESC = 0, + // HW engine ID ENGINE_INFO_TYPE_FIFO_TAG, + // RM_ENGINE_TYPE_* ENGINE_INFO_TYPE_RM_ENGINE_TYPE, + + // // runlist id (meaning varies by GPU) + // Valid only for Esched-driven engines + // ENGINE_INFO_TYPE_RUNLIST, + // NV_PFIFO_INTR_MMU_FAULT_ENG_ID_* ENGINE_INFO_TYPE_MMU_FAULT_ID, + // ROBUST_CHANNEL_* ENGINE_INFO_TYPE_RC_MASK, + // Reset Bit Position. On Ampere, only valid if not _INVALID ENGINE_INFO_TYPE_RESET, + // Interrupt Bit Position ENGINE_INFO_TYPE_INTR, + // log2(MC_ENGINE_*) ENGINE_INFO_TYPE_MC, + // The DEV_TYPE_ENUM for this engine ENGINE_INFO_TYPE_DEV_TYPE_ENUM, + // The particular instance of this engine type ENGINE_INFO_TYPE_INSTANCE_ID, + + // // The base address for this engine's NV_RUNLIST. Valid only on Ampere+ + // Valid only for Esched-driven engines + // ENGINE_INFO_TYPE_RUNLIST_PRI_BASE, - // If this entry is a host-driven engine. Valid only on Ampere+ - ENGINE_INFO_TYPE_IS_ENGINE, + + // + // If this entry is a host-driven engine. + // Update _isEngineInfoTypeValidForOnlyHostDriven when adding any new entry. + // + ENGINE_INFO_TYPE_IS_HOST_DRIVEN_ENGINE, + + // // The index into the per-engine NV_RUNLIST registers. Valid only on Ampere+ + // Valid only for Esched-driven engines + // ENGINE_INFO_TYPE_RUNLIST_ENGINE_ID, - // The base address for this engine's NV_CHRAM registers. Valid only on Ampere+ + + // + // The base address for this engine's NV_CHRAM registers. Valid only on + // Ampere+ + // + // Valid only for Esched-driven engines + // ENGINE_INFO_TYPE_CHRAM_PRI_BASE, // Used for iterating the engine info table by the index passed. ENGINE_INFO_TYPE_INVALID, - // Input-only parameter for fifoEngineInfoXlate. + // Input-only parameter for kfifoEngineInfoXlate. ENGINE_INFO_TYPE_PBDMA_ID + + /* ************************************************************************* + * Bug 3820969 + * THINK BEFORE CHANGING ENUM ORDER HERE. + * VGPU-guest uses this same ordering. Because this enum is not versioned, + * changing the order here WILL BREAK old-guest-on-newer-host compatibility. + * ************************************************************************/ } ENGINE_INFO_TYPE; // Maximum number of pbdma IDs for a given engine @@ -335,10 +385,20 @@ typedef struct typedef struct _def_engine_info { - NvU32 maxNumPbdmas; // max number of PBDMAs - NvU32 basePbdmaFaultId; // base PBDMA Fault ID - NvU32 maxNumRunlists; // max number of runlists - NvU32 numRunlists; // Gets the number of runlists, not the maximum + NvU32 maxNumPbdmas; + PBDMA_ID_BITVECTOR validEngineIdsForPbdmas; + // + // The highest runlist ID. Valid runlist IDs are < maxNumRunlists + // However, the entire [0, maxNumRunlists) range is not valid. There are + // missing runlist IDs in this range. + // + NvU32 maxNumRunlists; + // + // Multiple engines may have the same runlist ID. This is the total number + // of engines with a runlist which is equal to the number of Esched driven + // engines and does not include the SW engine. + // + NvU32 numRunlists; NvU32 engineInfoListSize; FIFO_ENGINE_LIST *engineInfoList; } ENGINE_INFO; @@ -429,8 +489,6 @@ struct KernelFifo { NV_STATUS (*__kfifoUpdateUsermodeDoorbell__)(struct OBJGPU *, struct KernelFifo *, NvU32, NvU32); NvU32 (*__kfifoRunlistGetBaseShift__)(struct KernelFifo *); NvU32 (*__kfifoGetMaxCeChannelGroups__)(struct OBJGPU *, struct KernelFifo *); - void (*__kfifoSetupUserD__)(struct KernelFifo *, NvU8 *); - NV_STATUS (*__kfifoReconcileTunableState__)(POBJGPU, struct KernelFifo *, void *); NV_STATUS (*__kfifoStateLoad__)(POBJGPU, struct KernelFifo *, NvU32); NV_STATUS (*__kfifoStateUnload__)(POBJGPU, struct KernelFifo *, NvU32); NV_STATUS (*__kfifoStatePreLoad__)(POBJGPU, struct KernelFifo *, NvU32); @@ -439,11 +497,6 @@ struct KernelFifo { void (*__kfifoInitMissing__)(POBJGPU, struct KernelFifo *); NV_STATUS (*__kfifoStatePreInitLocked__)(POBJGPU, struct KernelFifo *); NV_STATUS (*__kfifoStatePreInitUnlocked__)(POBJGPU, struct KernelFifo *); - NV_STATUS (*__kfifoGetTunableState__)(POBJGPU, struct KernelFifo *, void *); - NV_STATUS (*__kfifoCompareTunableState__)(POBJGPU, struct KernelFifo *, void *, void *); - void (*__kfifoFreeTunableState__)(POBJGPU, struct KernelFifo *, void *); - NV_STATUS (*__kfifoAllocTunableState__)(POBJGPU, struct KernelFifo *, void **); - NV_STATUS (*__kfifoSetTunableState__)(POBJGPU, struct KernelFifo *, void *); NvBool (*__kfifoIsPresent__)(POBJGPU, struct KernelFifo *); struct KernelSchedMgr *pKernelSchedMgr; CHID_MGR **ppChidMgr; @@ -535,9 +588,6 @@ NV_STATUS __nvoc_objCreate_KernelFifo(KernelFifo**, Dynamic*, NvU32); #define kfifoRunlistGetBaseShift_HAL(pKernelFifo) kfifoRunlistGetBaseShift_DISPATCH(pKernelFifo) #define kfifoGetMaxCeChannelGroups(pGpu, pKernelFifo) kfifoGetMaxCeChannelGroups_DISPATCH(pGpu, pKernelFifo) #define kfifoGetMaxCeChannelGroups_HAL(pGpu, pKernelFifo) kfifoGetMaxCeChannelGroups_DISPATCH(pGpu, pKernelFifo) -#define kfifoSetupUserD(pKernelFifo, pUserD) kfifoSetupUserD_DISPATCH(pKernelFifo, pUserD) -#define kfifoSetupUserD_HAL(pKernelFifo, pUserD) kfifoSetupUserD_DISPATCH(pKernelFifo, pUserD) -#define kfifoReconcileTunableState(pGpu, pEngstate, pTunableState) kfifoReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kfifoStateLoad(pGpu, pEngstate, arg0) kfifoStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kfifoStateUnload(pGpu, pEngstate, arg0) kfifoStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define kfifoStatePreLoad(pGpu, pEngstate, arg0) kfifoStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) @@ -546,11 +596,6 @@ NV_STATUS __nvoc_objCreate_KernelFifo(KernelFifo**, Dynamic*, NvU32); #define kfifoInitMissing(pGpu, pEngstate) kfifoInitMissing_DISPATCH(pGpu, pEngstate) #define kfifoStatePreInitLocked(pGpu, pEngstate) kfifoStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kfifoStatePreInitUnlocked(pGpu, pEngstate) kfifoStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kfifoGetTunableState(pGpu, pEngstate, pTunableState) kfifoGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kfifoCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kfifoCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kfifoFreeTunableState(pGpu, pEngstate, pTunableState) kfifoFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kfifoAllocTunableState(pGpu, pEngstate, ppTunableState) kfifoAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kfifoSetTunableState(pGpu, pEngstate, pTunableState) kfifoSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kfifoIsPresent(pGpu, pEngstate) kfifoIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS kfifoConstructHal_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); @@ -1026,6 +1071,22 @@ static inline NV_STATUS kfifoGetEnginePbdmaIds(struct OBJGPU *pGpu, struct Kerne #define kfifoGetEnginePbdmaIds_HAL(pGpu, pKernelFifo, type, val, ppPbdmaIds, pNumPbdmas) kfifoGetEnginePbdmaIds(pGpu, pKernelFifo, type, val, ppPbdmaIds, pNumPbdmas) +static inline NV_STATUS kfifoReservePbdmaFaultIds_56cd7a(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, FIFO_ENGINE_LIST *arg0, NvU32 arg1) { + return NV_OK; +} + + +#ifdef __nvoc_kernel_fifo_h_disabled +static inline NV_STATUS kfifoReservePbdmaFaultIds(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, FIFO_ENGINE_LIST *arg0, NvU32 arg1) { + NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_fifo_h_disabled +#define kfifoReservePbdmaFaultIds(pGpu, pKernelFifo, arg0, arg1) kfifoReservePbdmaFaultIds_56cd7a(pGpu, pKernelFifo, arg0, arg1) +#endif //__nvoc_kernel_fifo_h_disabled + +#define kfifoReservePbdmaFaultIds_HAL(pGpu, pKernelFifo, arg0, arg1) kfifoReservePbdmaFaultIds(pGpu, pKernelFifo, arg0, arg1) + NV_STATUS kfifoGetEnginePartnerList_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS *pParams); @@ -1271,6 +1332,19 @@ static inline NV_STATUS kfifoRunlistSetIdByEngine(struct OBJGPU *pGpu, struct Ke #define kfifoRunlistSetIdByEngine_HAL(pGpu, pKernelFifo, arg0, engDesc) kfifoRunlistSetIdByEngine(pGpu, pKernelFifo, arg0, engDesc) +void kfifoSetupUserD_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, MEMORY_DESCRIPTOR *pMemDesc); + + +#ifdef __nvoc_kernel_fifo_h_disabled +static inline void kfifoSetupUserD(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, MEMORY_DESCRIPTOR *pMemDesc) { + NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); +} +#else //__nvoc_kernel_fifo_h_disabled +#define kfifoSetupUserD(pGpu, pKernelFifo, pMemDesc) kfifoSetupUserD_GM107(pGpu, pKernelFifo, pMemDesc) +#endif //__nvoc_kernel_fifo_h_disabled + +#define kfifoSetupUserD_HAL(pGpu, pKernelFifo, pMemDesc) kfifoSetupUserD(pGpu, pKernelFifo, pMemDesc) + NV_STATUS kfifoConstructEngine_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, ENGDESCRIPTOR engDesc); static inline NV_STATUS kfifoConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, ENGDESCRIPTOR engDesc) { @@ -1391,18 +1465,6 @@ static inline NvU32 kfifoGetMaxCeChannelGroups_DISPATCH(struct OBJGPU *pGpu, str return pKernelFifo->__kfifoGetMaxCeChannelGroups__(pGpu, pKernelFifo); } -void kfifoSetupUserD_GM107(struct KernelFifo *pKernelFifo, NvU8 *pUserD); - -void kfifoSetupUserD_GA100(struct KernelFifo *pKernelFifo, NvU8 *pUserD); - -static inline void kfifoSetupUserD_DISPATCH(struct KernelFifo *pKernelFifo, NvU8 *pUserD) { - pKernelFifo->__kfifoSetupUserD__(pKernelFifo, pUserD); -} - -static inline NV_STATUS kfifoReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelFifo *pEngstate, void *pTunableState) { - return pEngstate->__kfifoReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kfifoStateLoad_DISPATCH(POBJGPU pGpu, struct KernelFifo *pEngstate, NvU32 arg0) { return pEngstate->__kfifoStateLoad__(pGpu, pEngstate, arg0); } @@ -1435,26 +1497,6 @@ static inline NV_STATUS kfifoStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct return pEngstate->__kfifoStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kfifoGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelFifo *pEngstate, void *pTunableState) { - return pEngstate->__kfifoGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kfifoCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelFifo *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kfifoCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kfifoFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelFifo *pEngstate, void *pTunableState) { - pEngstate->__kfifoFreeTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kfifoAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelFifo *pEngstate, void **ppTunableState) { - return pEngstate->__kfifoAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kfifoSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelFifo *pEngstate, void *pTunableState) { - return pEngstate->__kfifoSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kfifoIsPresent_DISPATCH(POBJGPU pGpu, struct KernelFifo *pEngstate) { return pEngstate->__kfifoIsPresent__(pGpu, pEngstate); } @@ -1593,37 +1635,37 @@ static inline NV_STATUS kfifoChidMgrFreeChid(struct OBJGPU *pGpu, struct KernelF #define kfifoChidMgrFreeChid(pGpu, pKernelFifo, pChidMgr, ChID) kfifoChidMgrFreeChid_IMPL(pGpu, pKernelFifo, pChidMgr, ChID) #endif //__nvoc_kernel_fifo_h_disabled -NV_STATUS kfifoChidMgrReserveSystemChids_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 numChannels, NvU32 flags, NvU32 gfid, NvU32 *pChidOffset, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList); +NV_STATUS kfifoChidMgrReserveSystemChids_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 numChannels, NvU32 flags, NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList); #ifdef __nvoc_kernel_fifo_h_disabled -static inline NV_STATUS kfifoChidMgrReserveSystemChids(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 numChannels, NvU32 flags, NvU32 gfid, NvU32 *pChidOffset, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { +static inline NV_STATUS kfifoChidMgrReserveSystemChids(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 numChannels, NvU32 flags, NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_fifo_h_disabled -#define kfifoChidMgrReserveSystemChids(pGpu, pKernelFifo, pChidMgr, numChannels, flags, gfid, pChidOffset, hMigClient, engineFifoListNumEntries, pEngineFifoList) kfifoChidMgrReserveSystemChids_IMPL(pGpu, pKernelFifo, pChidMgr, numChannels, flags, gfid, pChidOffset, hMigClient, engineFifoListNumEntries, pEngineFifoList) +#define kfifoChidMgrReserveSystemChids(pGpu, pKernelFifo, pChidMgr, numChannels, flags, gfid, pChidOffset, pChannelCount, hMigClient, engineFifoListNumEntries, pEngineFifoList) kfifoChidMgrReserveSystemChids_IMPL(pGpu, pKernelFifo, pChidMgr, numChannels, flags, gfid, pChidOffset, pChannelCount, hMigClient, engineFifoListNumEntries, pEngineFifoList) #endif //__nvoc_kernel_fifo_h_disabled -NV_STATUS kfifoChidMgrFreeSystemChids_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 gfid, NvU32 *pChidOffset, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList); +NV_STATUS kfifoChidMgrFreeSystemChids_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList); #ifdef __nvoc_kernel_fifo_h_disabled -static inline NV_STATUS kfifoChidMgrFreeSystemChids(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 gfid, NvU32 *pChidOffset, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { +static inline NV_STATUS kfifoChidMgrFreeSystemChids(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_fifo_h_disabled -#define kfifoChidMgrFreeSystemChids(pGpu, pKernelFifo, pChidMgr, gfid, pChidOffset, hMigClient, engineFifoListNumEntries, pEngineFifoList) kfifoChidMgrFreeSystemChids_IMPL(pGpu, pKernelFifo, pChidMgr, gfid, pChidOffset, hMigClient, engineFifoListNumEntries, pEngineFifoList) +#define kfifoChidMgrFreeSystemChids(pGpu, pKernelFifo, pChidMgr, gfid, pChidOffset, pChannelCount, hMigClient, engineFifoListNumEntries, pEngineFifoList) kfifoChidMgrFreeSystemChids_IMPL(pGpu, pKernelFifo, pChidMgr, gfid, pChidOffset, pChannelCount, hMigClient, engineFifoListNumEntries, pEngineFifoList) #endif //__nvoc_kernel_fifo_h_disabled -NV_STATUS kfifoSetChidOffset_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 offset, NvU32 numChannels, NvU32 gfid, NvU32 *pChidOffset, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList); +NV_STATUS kfifoSetChidOffset_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 offset, NvU32 numChannels, NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList); #ifdef __nvoc_kernel_fifo_h_disabled -static inline NV_STATUS kfifoSetChidOffset(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 offset, NvU32 numChannels, NvU32 gfid, NvU32 *pChidOffset, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { +static inline NV_STATUS kfifoSetChidOffset(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 offset, NvU32 numChannels, NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_fifo_h_disabled -#define kfifoSetChidOffset(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, pChidOffset, hMigClient, engineFifoListNumEntries, pEngineFifoList) kfifoSetChidOffset_IMPL(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, pChidOffset, hMigClient, engineFifoListNumEntries, pEngineFifoList) +#define kfifoSetChidOffset(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, pChidOffset, pChannelCount, hMigClient, engineFifoListNumEntries, pEngineFifoList) kfifoSetChidOffset_IMPL(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, pChidOffset, pChannelCount, hMigClient, engineFifoListNumEntries, pEngineFifoList) #endif //__nvoc_kernel_fifo_h_disabled NvU32 kfifoChidMgrGetNumChannels_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr); @@ -1991,6 +2033,17 @@ static inline NV_STATUS kfifoChannelGroupSetTimeslice(struct OBJGPU *pGpu, struc const FIFO_GUEST_ENGINE_TABLE *kfifoGetGuestEngineLookupTable_IMPL(NvU32 *pTableSize); #define kfifoGetGuestEngineLookupTable(pTableSize) kfifoGetGuestEngineLookupTable_IMPL(pTableSize) +NvU32 kfifoGetNumEschedDrivenEngines_IMPL(struct KernelFifo *pKernelFifo); + +#ifdef __nvoc_kernel_fifo_h_disabled +static inline NvU32 kfifoGetNumEschedDrivenEngines(struct KernelFifo *pKernelFifo) { + NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); + return 0; +} +#else //__nvoc_kernel_fifo_h_disabled +#define kfifoGetNumEschedDrivenEngines(pKernelFifo) kfifoGetNumEschedDrivenEngines_IMPL(pKernelFifo) +#endif //__nvoc_kernel_fifo_h_disabled + #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_kernel_graphics_context_nvoc.c b/src/nvidia/generated/g_kernel_graphics_context_nvoc.c index 597752517..1a8c9950a 100644 --- a/src/nvidia/generated/g_kernel_graphics_context_nvoc.c +++ b/src/nvidia/generated/g_kernel_graphics_context_nvoc.c @@ -105,6 +105,50 @@ static NvBool __nvoc_thunk_GpuResource_kgrctxShareCallback(struct KernelGraphics return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelGraphicsContext_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } +static NV_STATUS __nvoc_thunk_RmResource_kgrctxCheckMemInterUnmap(struct KernelGraphicsContext *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelGraphicsContext_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_kgrctxMapTo(struct KernelGraphicsContext *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_kgrctxGetMapAddrSpace(struct KernelGraphicsContext *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelGraphicsContext_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_kgrctxGetRefCount(struct KernelGraphicsContext *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_kgrctxAddAdditionalDependants(struct RsClient *pClient, struct KernelGraphicsContext *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_kgrctxControl_Prologue(struct KernelGraphicsContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_kgrctxGetRegBaseOffsetAndSize(struct KernelGraphicsContext *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelGraphicsContext_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_kgrctxInternalControlForward(struct KernelGraphicsContext *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelGraphicsContext_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_kgrctxUnmapFrom(struct KernelGraphicsContext *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_kgrctxControl_Epilogue(struct KernelGraphicsContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_kgrctxControlLookup(struct KernelGraphicsContext *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset), pParams, ppEntry); +} + static NV_STATUS __nvoc_thunk_GpuResource_kgrctxControl(struct KernelGraphicsContext *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelGraphicsContext_GpuResource.offset), pCallContext, pParams); } @@ -121,60 +165,24 @@ static NV_STATUS __nvoc_thunk_RmResource_kgrctxGetMemoryMappingDescriptor(struct return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelGraphicsContext_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_GpuResource_kgrctxGetMapAddrSpace(struct KernelGraphicsContext *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelGraphicsContext_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); -} - static NV_STATUS __nvoc_thunk_RsResource_kgrctxControlFilter(struct KernelGraphicsContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_kgrctxAddAdditionalDependants(struct RsClient *pClient, struct KernelGraphicsContext *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_kgrctxGetRefCount(struct KernelGraphicsContext *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RmResource_kgrctxCheckMemInterUnmap(struct KernelGraphicsContext *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelGraphicsContext_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_kgrctxMapTo(struct KernelGraphicsContext *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_kgrctxControl_Prologue(struct KernelGraphicsContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_GpuResource_kgrctxGetRegBaseOffsetAndSize(struct KernelGraphicsContext *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelGraphicsContext_GpuResource.offset), pGpu, pOffset, pSize); -} - -static NV_STATUS __nvoc_thunk_GpuResource_kgrctxInternalControlForward(struct KernelGraphicsContext *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelGraphicsContext_GpuResource.offset), command, pParams, size); +static NV_STATUS __nvoc_thunk_RmResource_kgrctxControlSerialization_Prologue(struct KernelGraphicsContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RmResource.offset), pCallContext, pParams); } static void __nvoc_thunk_RsResource_kgrctxPreDestruct(struct KernelGraphicsContext *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_kgrctxUnmapFrom(struct KernelGraphicsContext *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_kgrctxIsDuplicate(struct KernelGraphicsContext *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset), hMemory, pDuplicate); } -static void __nvoc_thunk_RmResource_kgrctxControl_Epilogue(struct KernelGraphicsContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_kgrctxControlLookup(struct KernelGraphicsContext *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_kgrctxControlSerialization_Epilogue(struct KernelGraphicsContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_kgrctxMap(struct KernelGraphicsContext *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -337,6 +345,28 @@ static void __nvoc_init_funcTable_KernelGraphicsContext_1(KernelGraphicsContext pThis->__kgrctxShareCallback__ = &__nvoc_thunk_GpuResource_kgrctxShareCallback; + pThis->__kgrctxCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_kgrctxCheckMemInterUnmap; + + pThis->__kgrctxMapTo__ = &__nvoc_thunk_RsResource_kgrctxMapTo; + + pThis->__kgrctxGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_kgrctxGetMapAddrSpace; + + pThis->__kgrctxGetRefCount__ = &__nvoc_thunk_RsResource_kgrctxGetRefCount; + + pThis->__kgrctxAddAdditionalDependants__ = &__nvoc_thunk_RsResource_kgrctxAddAdditionalDependants; + + pThis->__kgrctxControl_Prologue__ = &__nvoc_thunk_RmResource_kgrctxControl_Prologue; + + pThis->__kgrctxGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_kgrctxGetRegBaseOffsetAndSize; + + pThis->__kgrctxInternalControlForward__ = &__nvoc_thunk_GpuResource_kgrctxInternalControlForward; + + pThis->__kgrctxUnmapFrom__ = &__nvoc_thunk_RsResource_kgrctxUnmapFrom; + + pThis->__kgrctxControl_Epilogue__ = &__nvoc_thunk_RmResource_kgrctxControl_Epilogue; + + pThis->__kgrctxControlLookup__ = &__nvoc_thunk_RsResource_kgrctxControlLookup; + pThis->__kgrctxControl__ = &__nvoc_thunk_GpuResource_kgrctxControl; pThis->__kgrctxUnmap__ = &__nvoc_thunk_GpuResource_kgrctxUnmap; @@ -345,33 +375,15 @@ static void __nvoc_init_funcTable_KernelGraphicsContext_1(KernelGraphicsContext pThis->__kgrctxGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_kgrctxGetMemoryMappingDescriptor; - pThis->__kgrctxGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_kgrctxGetMapAddrSpace; - pThis->__kgrctxControlFilter__ = &__nvoc_thunk_RsResource_kgrctxControlFilter; - pThis->__kgrctxAddAdditionalDependants__ = &__nvoc_thunk_RsResource_kgrctxAddAdditionalDependants; - - pThis->__kgrctxGetRefCount__ = &__nvoc_thunk_RsResource_kgrctxGetRefCount; - - pThis->__kgrctxCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_kgrctxCheckMemInterUnmap; - - pThis->__kgrctxMapTo__ = &__nvoc_thunk_RsResource_kgrctxMapTo; - - pThis->__kgrctxControl_Prologue__ = &__nvoc_thunk_RmResource_kgrctxControl_Prologue; - - pThis->__kgrctxGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_kgrctxGetRegBaseOffsetAndSize; - - pThis->__kgrctxInternalControlForward__ = &__nvoc_thunk_GpuResource_kgrctxInternalControlForward; + pThis->__kgrctxControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_kgrctxControlSerialization_Prologue; pThis->__kgrctxPreDestruct__ = &__nvoc_thunk_RsResource_kgrctxPreDestruct; - pThis->__kgrctxUnmapFrom__ = &__nvoc_thunk_RsResource_kgrctxUnmapFrom; - pThis->__kgrctxIsDuplicate__ = &__nvoc_thunk_RsResource_kgrctxIsDuplicate; - pThis->__kgrctxControl_Epilogue__ = &__nvoc_thunk_RmResource_kgrctxControl_Epilogue; - - pThis->__kgrctxControlLookup__ = &__nvoc_thunk_RsResource_kgrctxControlLookup; + pThis->__kgrctxControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_kgrctxControlSerialization_Epilogue; pThis->__kgrctxMap__ = &__nvoc_thunk_GpuResource_kgrctxMap; @@ -400,13 +412,16 @@ NV_STATUS __nvoc_objCreate_KernelGraphicsContext(KernelGraphicsContext **ppThis, KernelGraphicsContext *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelGraphicsContext)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelGraphicsContext), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelGraphicsContext)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelGraphicsContext); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -426,11 +441,17 @@ NV_STATUS __nvoc_objCreate_KernelGraphicsContext(KernelGraphicsContext **ppThis, if (status != NV_OK) goto __nvoc_objCreate_KernelGraphicsContext_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelGraphicsContext_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelGraphicsContext)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -561,13 +582,16 @@ NV_STATUS __nvoc_objCreate_KernelGraphicsContextShared(KernelGraphicsContextShar Object *pParentObj; KernelGraphicsContextShared *pThis; - pThis = portMemAllocNonPaged(sizeof(KernelGraphicsContextShared)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelGraphicsContextShared), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelGraphicsContextShared)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelGraphicsContextShared); + pThis->__nvoc_base_RsShared.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -583,11 +607,17 @@ NV_STATUS __nvoc_objCreate_KernelGraphicsContextShared(KernelGraphicsContextShar if (status != NV_OK) goto __nvoc_objCreate_KernelGraphicsContextShared_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelGraphicsContextShared_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelGraphicsContextShared)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_graphics_context_nvoc.h b/src/nvidia/generated/g_kernel_graphics_context_nvoc.h index 34006173b..6ac1b2085 100644 --- a/src/nvidia/generated/g_kernel_graphics_context_nvoc.h +++ b/src/nvidia/generated/g_kernel_graphics_context_nvoc.h @@ -169,24 +169,26 @@ struct KernelGraphicsContext { NV_STATUS (*__kgrctxCtrlGetMMUDebugMode__)(struct KernelGraphicsContext *, NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS *); NV_STATUS (*__kgrctxCtrlProgramVidmemPromote__)(struct KernelGraphicsContext *, NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS *); NvBool (*__kgrctxShareCallback__)(struct KernelGraphicsContext *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__kgrctxCheckMemInterUnmap__)(struct KernelGraphicsContext *, NvBool); + NV_STATUS (*__kgrctxMapTo__)(struct KernelGraphicsContext *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__kgrctxGetMapAddrSpace__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__kgrctxGetRefCount__)(struct KernelGraphicsContext *); + void (*__kgrctxAddAdditionalDependants__)(struct RsClient *, struct KernelGraphicsContext *, RsResourceRef *); + NV_STATUS (*__kgrctxControl_Prologue__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kgrctxGetRegBaseOffsetAndSize__)(struct KernelGraphicsContext *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__kgrctxInternalControlForward__)(struct KernelGraphicsContext *, NvU32, void *, NvU32); + NV_STATUS (*__kgrctxUnmapFrom__)(struct KernelGraphicsContext *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__kgrctxControl_Epilogue__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kgrctxControlLookup__)(struct KernelGraphicsContext *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__kgrctxControl__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kgrctxUnmap__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__kgrctxGetMemInterMapParams__)(struct KernelGraphicsContext *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__kgrctxGetMemoryMappingDescriptor__)(struct KernelGraphicsContext *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__kgrctxGetMapAddrSpace__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); NV_STATUS (*__kgrctxControlFilter__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__kgrctxAddAdditionalDependants__)(struct RsClient *, struct KernelGraphicsContext *, RsResourceRef *); - NvU32 (*__kgrctxGetRefCount__)(struct KernelGraphicsContext *); - NV_STATUS (*__kgrctxCheckMemInterUnmap__)(struct KernelGraphicsContext *, NvBool); - NV_STATUS (*__kgrctxMapTo__)(struct KernelGraphicsContext *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__kgrctxControl_Prologue__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__kgrctxGetRegBaseOffsetAndSize__)(struct KernelGraphicsContext *, struct OBJGPU *, NvU32 *, NvU32 *); - NV_STATUS (*__kgrctxInternalControlForward__)(struct KernelGraphicsContext *, NvU32, void *, NvU32); + NV_STATUS (*__kgrctxControlSerialization_Prologue__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__kgrctxPreDestruct__)(struct KernelGraphicsContext *); - NV_STATUS (*__kgrctxUnmapFrom__)(struct KernelGraphicsContext *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__kgrctxIsDuplicate__)(struct KernelGraphicsContext *, NvHandle, NvBool *); - void (*__kgrctxControl_Epilogue__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__kgrctxControlLookup__)(struct KernelGraphicsContext *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__kgrctxControlSerialization_Epilogue__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kgrctxMap__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__kgrctxAccessCallback__)(struct KernelGraphicsContext *, struct RsClient *, void *, RsAccessRight); struct KernelGraphicsContextShared *pShared; @@ -227,24 +229,26 @@ NV_STATUS __nvoc_objCreate_KernelGraphicsContext(KernelGraphicsContext**, Dynami #define kgrctxCtrlGetMMUDebugMode(pKernelGraphicsContext, pParams) kgrctxCtrlGetMMUDebugMode_DISPATCH(pKernelGraphicsContext, pParams) #define kgrctxCtrlProgramVidmemPromote(pKernelGraphicsContext, pParams) kgrctxCtrlProgramVidmemPromote_DISPATCH(pKernelGraphicsContext, pParams) #define kgrctxShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) kgrctxShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define kgrctxCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) kgrctxCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define kgrctxMapTo(pResource, pParams) kgrctxMapTo_DISPATCH(pResource, pParams) +#define kgrctxGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) kgrctxGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define kgrctxGetRefCount(pResource) kgrctxGetRefCount_DISPATCH(pResource) +#define kgrctxAddAdditionalDependants(pClient, pResource, pReference) kgrctxAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define kgrctxControl_Prologue(pResource, pCallContext, pParams) kgrctxControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define kgrctxGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) kgrctxGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define kgrctxInternalControlForward(pGpuResource, command, pParams, size) kgrctxInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define kgrctxUnmapFrom(pResource, pParams) kgrctxUnmapFrom_DISPATCH(pResource, pParams) +#define kgrctxControl_Epilogue(pResource, pCallContext, pParams) kgrctxControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define kgrctxControlLookup(pResource, pParams, ppEntry) kgrctxControlLookup_DISPATCH(pResource, pParams, ppEntry) #define kgrctxControl(pGpuResource, pCallContext, pParams) kgrctxControl_DISPATCH(pGpuResource, pCallContext, pParams) #define kgrctxUnmap(pGpuResource, pCallContext, pCpuMapping) kgrctxUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define kgrctxGetMemInterMapParams(pRmResource, pParams) kgrctxGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define kgrctxGetMemoryMappingDescriptor(pRmResource, ppMemDesc) kgrctxGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define kgrctxGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) kgrctxGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) #define kgrctxControlFilter(pResource, pCallContext, pParams) kgrctxControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define kgrctxAddAdditionalDependants(pClient, pResource, pReference) kgrctxAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define kgrctxGetRefCount(pResource) kgrctxGetRefCount_DISPATCH(pResource) -#define kgrctxCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) kgrctxCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define kgrctxMapTo(pResource, pParams) kgrctxMapTo_DISPATCH(pResource, pParams) -#define kgrctxControl_Prologue(pResource, pCallContext, pParams) kgrctxControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define kgrctxGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) kgrctxGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) -#define kgrctxInternalControlForward(pGpuResource, command, pParams, size) kgrctxInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define kgrctxControlSerialization_Prologue(pResource, pCallContext, pParams) kgrctxControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define kgrctxPreDestruct(pResource) kgrctxPreDestruct_DISPATCH(pResource) -#define kgrctxUnmapFrom(pResource, pParams) kgrctxUnmapFrom_DISPATCH(pResource, pParams) #define kgrctxIsDuplicate(pResource, hMemory, pDuplicate) kgrctxIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) -#define kgrctxControl_Epilogue(pResource, pCallContext, pParams) kgrctxControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define kgrctxControlLookup(pResource, pParams, ppEntry) kgrctxControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define kgrctxControlSerialization_Epilogue(pResource, pCallContext, pParams) kgrctxControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define kgrctxMap(pGpuResource, pCallContext, pParams, pCpuMapping) kgrctxMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define kgrctxAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) kgrctxAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool kgrctxShouldManageCtxBuffers_KERNEL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, NvU32 gfid); @@ -400,6 +404,50 @@ static inline NvBool kgrctxShareCallback_DISPATCH(struct KernelGraphicsContext * return pGpuResource->__kgrctxShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } +static inline NV_STATUS kgrctxCheckMemInterUnmap_DISPATCH(struct KernelGraphicsContext *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__kgrctxCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS kgrctxMapTo_DISPATCH(struct KernelGraphicsContext *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__kgrctxMapTo__(pResource, pParams); +} + +static inline NV_STATUS kgrctxGetMapAddrSpace_DISPATCH(struct KernelGraphicsContext *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__kgrctxGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 kgrctxGetRefCount_DISPATCH(struct KernelGraphicsContext *pResource) { + return pResource->__kgrctxGetRefCount__(pResource); +} + +static inline void kgrctxAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct KernelGraphicsContext *pResource, RsResourceRef *pReference) { + pResource->__kgrctxAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS kgrctxControl_Prologue_DISPATCH(struct KernelGraphicsContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__kgrctxControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS kgrctxGetRegBaseOffsetAndSize_DISPATCH(struct KernelGraphicsContext *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__kgrctxGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS kgrctxInternalControlForward_DISPATCH(struct KernelGraphicsContext *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__kgrctxInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS kgrctxUnmapFrom_DISPATCH(struct KernelGraphicsContext *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__kgrctxUnmapFrom__(pResource, pParams); +} + +static inline void kgrctxControl_Epilogue_DISPATCH(struct KernelGraphicsContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__kgrctxControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS kgrctxControlLookup_DISPATCH(struct KernelGraphicsContext *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__kgrctxControlLookup__(pResource, pParams, ppEntry); +} + static inline NV_STATUS kgrctxControl_DISPATCH(struct KernelGraphicsContext *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pGpuResource->__kgrctxControl__(pGpuResource, pCallContext, pParams); } @@ -416,60 +464,24 @@ static inline NV_STATUS kgrctxGetMemoryMappingDescriptor_DISPATCH(struct KernelG return pRmResource->__kgrctxGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS kgrctxGetMapAddrSpace_DISPATCH(struct KernelGraphicsContext *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__kgrctxGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); -} - static inline NV_STATUS kgrctxControlFilter_DISPATCH(struct KernelGraphicsContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__kgrctxControlFilter__(pResource, pCallContext, pParams); } -static inline void kgrctxAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct KernelGraphicsContext *pResource, RsResourceRef *pReference) { - pResource->__kgrctxAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 kgrctxGetRefCount_DISPATCH(struct KernelGraphicsContext *pResource) { - return pResource->__kgrctxGetRefCount__(pResource); -} - -static inline NV_STATUS kgrctxCheckMemInterUnmap_DISPATCH(struct KernelGraphicsContext *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__kgrctxCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS kgrctxMapTo_DISPATCH(struct KernelGraphicsContext *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__kgrctxMapTo__(pResource, pParams); -} - -static inline NV_STATUS kgrctxControl_Prologue_DISPATCH(struct KernelGraphicsContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__kgrctxControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS kgrctxGetRegBaseOffsetAndSize_DISPATCH(struct KernelGraphicsContext *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__kgrctxGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); -} - -static inline NV_STATUS kgrctxInternalControlForward_DISPATCH(struct KernelGraphicsContext *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__kgrctxInternalControlForward__(pGpuResource, command, pParams, size); +static inline NV_STATUS kgrctxControlSerialization_Prologue_DISPATCH(struct KernelGraphicsContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__kgrctxControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline void kgrctxPreDestruct_DISPATCH(struct KernelGraphicsContext *pResource) { pResource->__kgrctxPreDestruct__(pResource); } -static inline NV_STATUS kgrctxUnmapFrom_DISPATCH(struct KernelGraphicsContext *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__kgrctxUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS kgrctxIsDuplicate_DISPATCH(struct KernelGraphicsContext *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__kgrctxIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline void kgrctxControl_Epilogue_DISPATCH(struct KernelGraphicsContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__kgrctxControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS kgrctxControlLookup_DISPATCH(struct KernelGraphicsContext *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__kgrctxControlLookup__(pResource, pParams, ppEntry); +static inline void kgrctxControlSerialization_Epilogue_DISPATCH(struct KernelGraphicsContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__kgrctxControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS kgrctxMap_DISPATCH(struct KernelGraphicsContext *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -578,6 +590,17 @@ static inline void kgrctxRecordMmuFault(struct OBJGPU *arg0, struct KernelGraphi #define kgrctxRecordMmuFault(arg0, arg1, mmuFaultInfo, mmuFaultAddress, mmuFaultType, mmuFaultAccessType) kgrctxRecordMmuFault_IMPL(arg0, arg1, mmuFaultInfo, mmuFaultAddress, mmuFaultType, mmuFaultAccessType) #endif //__nvoc_kernel_graphics_context_h_disabled +NvBool kgrctxIsValid_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelChannel *arg2); + +#ifdef __nvoc_kernel_graphics_context_h_disabled +static inline NvBool kgrctxIsValid(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelChannel *arg2) { + NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); + return NV_FALSE; +} +#else //__nvoc_kernel_graphics_context_h_disabled +#define kgrctxIsValid(arg0, arg1, arg2) kgrctxIsValid_IMPL(arg0, arg1, arg2) +#endif //__nvoc_kernel_graphics_context_h_disabled + NvBool kgrctxIsMainContextAllocated_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1); #ifdef __nvoc_kernel_graphics_context_h_disabled @@ -950,7 +973,7 @@ struct KernelGraphicsContextShared { struct Object *__nvoc_pbase_Object; struct RsShared *__nvoc_pbase_RsShared; struct KernelGraphicsContextShared *__nvoc_pbase_KernelGraphicsContextShared; - struct KernelGraphicsContextUnicast *pKernelGraphicsContextUnicast; + struct KernelGraphicsContextUnicast kernelGraphicsContextUnicast; }; #ifndef __NVOC_CLASS_KernelGraphicsContextShared_TYPEDEF__ diff --git a/src/nvidia/generated/g_kernel_graphics_manager_nvoc.c b/src/nvidia/generated/g_kernel_graphics_manager_nvoc.c index 75eca8041..b9155541e 100644 --- a/src/nvidia/generated/g_kernel_graphics_manager_nvoc.c +++ b/src/nvidia/generated/g_kernel_graphics_manager_nvoc.c @@ -70,10 +70,6 @@ static NV_STATUS __nvoc_thunk_KernelGraphicsManager_engstateConstructEngine(stru return kgrmgrConstructEngine(arg0, (struct KernelGraphicsManager *)(((unsigned char *)arg1) - __nvoc_rtti_KernelGraphicsManager_OBJENGSTATE.offset), arg2); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgrmgrReconcileTunableState(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphicsManager_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgrmgrStateLoad(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphicsManager_OBJENGSTATE.offset), arg0); } @@ -118,30 +114,10 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgrmgrStatePreInitUnlocked(POBJGPU pGp return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphicsManager_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgrmgrGetTunableState(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphicsManager_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgrmgrCompareTunableState(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphicsManager_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kgrmgrFreeTunableState(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphicsManager_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgrmgrStatePostLoad(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphicsManager_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgrmgrAllocTunableState(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphicsManager_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgrmgrSetTunableState(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphicsManager_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_kgrmgrIsPresent(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphicsManager_OBJENGSTATE.offset)); } @@ -184,8 +160,6 @@ static void __nvoc_init_funcTable_KernelGraphicsManager_1(KernelGraphicsManager pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelGraphicsManager_engstateConstructEngine; - pThis->__kgrmgrReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgrmgrReconcileTunableState; - pThis->__kgrmgrStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kgrmgrStateLoad; pThis->__kgrmgrStateUnload__ = &__nvoc_thunk_OBJENGSTATE_kgrmgrStateUnload; @@ -208,18 +182,8 @@ static void __nvoc_init_funcTable_KernelGraphicsManager_1(KernelGraphicsManager pThis->__kgrmgrStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kgrmgrStatePreInitUnlocked; - pThis->__kgrmgrGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgrmgrGetTunableState; - - pThis->__kgrmgrCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgrmgrCompareTunableState; - - pThis->__kgrmgrFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgrmgrFreeTunableState; - pThis->__kgrmgrStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kgrmgrStatePostLoad; - pThis->__kgrmgrAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgrmgrAllocTunableState; - - pThis->__kgrmgrSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgrmgrSetTunableState; - pThis->__kgrmgrIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kgrmgrIsPresent; } @@ -241,13 +205,16 @@ NV_STATUS __nvoc_objCreate_KernelGraphicsManager(KernelGraphicsManager **ppThis, Object *pParentObj; KernelGraphicsManager *pThis; - pThis = portMemAllocNonPaged(sizeof(KernelGraphicsManager)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelGraphicsManager), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelGraphicsManager)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelGraphicsManager); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -263,11 +230,17 @@ NV_STATUS __nvoc_objCreate_KernelGraphicsManager(KernelGraphicsManager **ppThis, if (status != NV_OK) goto __nvoc_objCreate_KernelGraphicsManager_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelGraphicsManager_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelGraphicsManager)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_graphics_manager_nvoc.h b/src/nvidia/generated/g_kernel_graphics_manager_nvoc.h index 0f1405471..a259bfb4f 100644 --- a/src/nvidia/generated/g_kernel_graphics_manager_nvoc.h +++ b/src/nvidia/generated/g_kernel_graphics_manager_nvoc.h @@ -71,7 +71,6 @@ struct KernelGraphicsManager { struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; struct KernelGraphicsManager *__nvoc_pbase_KernelGraphicsManager; NV_STATUS (*__kgrmgrConstructEngine__)(struct OBJGPU *, struct KernelGraphicsManager *, ENGDESCRIPTOR); - NV_STATUS (*__kgrmgrReconcileTunableState__)(POBJGPU, struct KernelGraphicsManager *, void *); NV_STATUS (*__kgrmgrStateLoad__)(POBJGPU, struct KernelGraphicsManager *, NvU32); NV_STATUS (*__kgrmgrStateUnload__)(POBJGPU, struct KernelGraphicsManager *, NvU32); NV_STATUS (*__kgrmgrStateInitLocked__)(POBJGPU, struct KernelGraphicsManager *); @@ -83,12 +82,7 @@ struct KernelGraphicsManager { void (*__kgrmgrInitMissing__)(POBJGPU, struct KernelGraphicsManager *); NV_STATUS (*__kgrmgrStatePreInitLocked__)(POBJGPU, struct KernelGraphicsManager *); NV_STATUS (*__kgrmgrStatePreInitUnlocked__)(POBJGPU, struct KernelGraphicsManager *); - NV_STATUS (*__kgrmgrGetTunableState__)(POBJGPU, struct KernelGraphicsManager *, void *); - NV_STATUS (*__kgrmgrCompareTunableState__)(POBJGPU, struct KernelGraphicsManager *, void *, void *); - void (*__kgrmgrFreeTunableState__)(POBJGPU, struct KernelGraphicsManager *, void *); NV_STATUS (*__kgrmgrStatePostLoad__)(POBJGPU, struct KernelGraphicsManager *, NvU32); - NV_STATUS (*__kgrmgrAllocTunableState__)(POBJGPU, struct KernelGraphicsManager *, void **); - NV_STATUS (*__kgrmgrSetTunableState__)(POBJGPU, struct KernelGraphicsManager *, void *); NvBool (*__kgrmgrIsPresent__)(POBJGPU, struct KernelGraphicsManager *); struct GRMGR_LEGACY_KGRAPHICS_STATIC_INFO legacyKgraphicsStaticInfo; NvU64 veidInUseMask; @@ -127,7 +121,6 @@ NV_STATUS __nvoc_objCreate_KernelGraphicsManager(KernelGraphicsManager**, Dynami __nvoc_objCreate_KernelGraphicsManager((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) #define kgrmgrConstructEngine(arg0, arg1, arg2) kgrmgrConstructEngine_DISPATCH(arg0, arg1, arg2) -#define kgrmgrReconcileTunableState(pGpu, pEngstate, pTunableState) kgrmgrReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kgrmgrStateLoad(pGpu, pEngstate, arg0) kgrmgrStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kgrmgrStateUnload(pGpu, pEngstate, arg0) kgrmgrStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define kgrmgrStateInitLocked(pGpu, pEngstate) kgrmgrStateInitLocked_DISPATCH(pGpu, pEngstate) @@ -139,12 +132,7 @@ NV_STATUS __nvoc_objCreate_KernelGraphicsManager(KernelGraphicsManager**, Dynami #define kgrmgrInitMissing(pGpu, pEngstate) kgrmgrInitMissing_DISPATCH(pGpu, pEngstate) #define kgrmgrStatePreInitLocked(pGpu, pEngstate) kgrmgrStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kgrmgrStatePreInitUnlocked(pGpu, pEngstate) kgrmgrStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kgrmgrGetTunableState(pGpu, pEngstate, pTunableState) kgrmgrGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kgrmgrCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kgrmgrCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kgrmgrFreeTunableState(pGpu, pEngstate, pTunableState) kgrmgrFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kgrmgrStatePostLoad(pGpu, pEngstate, arg0) kgrmgrStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define kgrmgrAllocTunableState(pGpu, pEngstate, ppTunableState) kgrmgrAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kgrmgrSetTunableState(pGpu, pEngstate, pTunableState) kgrmgrSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kgrmgrIsPresent(pGpu, pEngstate) kgrmgrIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS kgrmgrConstructEngine_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, ENGDESCRIPTOR arg2); @@ -152,10 +140,6 @@ static inline NV_STATUS kgrmgrConstructEngine_DISPATCH(struct OBJGPU *arg0, stru return arg1->__kgrmgrConstructEngine__(arg0, arg1, arg2); } -static inline NV_STATUS kgrmgrReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, void *pTunableState) { - return pEngstate->__kgrmgrReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kgrmgrStateLoad_DISPATCH(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, NvU32 arg0) { return pEngstate->__kgrmgrStateLoad__(pGpu, pEngstate, arg0); } @@ -200,30 +184,10 @@ static inline NV_STATUS kgrmgrStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct return pEngstate->__kgrmgrStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kgrmgrGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, void *pTunableState) { - return pEngstate->__kgrmgrGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kgrmgrCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kgrmgrCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kgrmgrFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, void *pTunableState) { - pEngstate->__kgrmgrFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kgrmgrStatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, NvU32 arg0) { return pEngstate->__kgrmgrStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS kgrmgrAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, void **ppTunableState) { - return pEngstate->__kgrmgrAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kgrmgrSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, void *pTunableState) { - return pEngstate->__kgrmgrSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kgrmgrIsPresent_DISPATCH(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate) { return pEngstate->__kgrmgrIsPresent__(pGpu, pEngstate); } diff --git a/src/nvidia/generated/g_kernel_graphics_nvoc.c b/src/nvidia/generated/g_kernel_graphics_nvoc.c index c0ddce77b..30ba12771 100644 --- a/src/nvidia/generated/g_kernel_graphics_nvoc.c +++ b/src/nvidia/generated/g_kernel_graphics_nvoc.c @@ -107,7 +107,7 @@ static NV_STATUS __nvoc_thunk_KernelGraphics_engstateStatePostLoad(OBJGPU *arg0, return kgraphicsStatePostLoad(arg0, (struct KernelGraphics *)(((unsigned char *)arg1) - __nvoc_rtti_KernelGraphics_OBJENGSTATE.offset), flags); } -static void __nvoc_thunk_KernelGraphics_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[163]) { +static void __nvoc_thunk_KernelGraphics_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[166]) { kgraphicsRegisterIntrService(arg0, (struct KernelGraphics *)(((unsigned char *)arg1) - __nvoc_rtti_KernelGraphics_IntrService.offset), arg2); } @@ -123,10 +123,6 @@ static NvU32 __nvoc_thunk_KernelGraphics_intrservServiceInterrupt(OBJGPU *arg0, return kgraphicsServiceInterrupt(arg0, (struct KernelGraphics *)(((unsigned char *)arg1) - __nvoc_rtti_KernelGraphics_IntrService.offset), arg2); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgraphicsReconcileTunableState(POBJGPU pGpu, struct KernelGraphics *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphics_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgraphicsStatePreLoad(POBJGPU pGpu, struct KernelGraphics *pEngstate, NvU32 arg0) { return engstateStatePreLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphics_OBJENGSTATE.offset), arg0); } @@ -151,26 +147,6 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgraphicsStatePreInitUnlocked(POBJGPU return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphics_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgraphicsGetTunableState(POBJGPU pGpu, struct KernelGraphics *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphics_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgraphicsCompareTunableState(POBJGPU pGpu, struct KernelGraphics *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphics_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kgraphicsFreeTunableState(POBJGPU pGpu, struct KernelGraphics *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphics_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgraphicsAllocTunableState(POBJGPU pGpu, struct KernelGraphics *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphics_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgraphicsSetTunableState(POBJGPU pGpu, struct KernelGraphics *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGraphics_OBJENGSTATE.offset), pTunableState); -} - const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelGraphics = { /*numEntries=*/ 0, @@ -233,6 +209,20 @@ void __nvoc_init_dataField_KernelGraphics(KernelGraphics *pThis, RmHalspecOwner { pThis->bRtvCbSupported = ((NvBool)(0 == 0)); } + + // Hal field -- bFecsRecordUcodeSeqnoSupported + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->bFecsRecordUcodeSeqnoSupported = ((NvBool)(0 == 0)); + } + // default + else + { + pThis->bFecsRecordUcodeSeqnoSupported = ((NvBool)(0 != 0)); + } + } } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); @@ -322,8 +312,6 @@ static void __nvoc_init_funcTable_KernelGraphics_1(KernelGraphics *pThis, RmHals pThis->__nvoc_base_IntrService.__intrservServiceInterrupt__ = &__nvoc_thunk_KernelGraphics_intrservServiceInterrupt; - pThis->__kgraphicsReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgraphicsReconcileTunableState; - pThis->__kgraphicsStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_kgraphicsStatePreLoad; pThis->__kgraphicsStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_kgraphicsStatePostUnload; @@ -335,16 +323,6 @@ static void __nvoc_init_funcTable_KernelGraphics_1(KernelGraphics *pThis, RmHals pThis->__kgraphicsStatePreInitLocked__ = &__nvoc_thunk_OBJENGSTATE_kgraphicsStatePreInitLocked; pThis->__kgraphicsStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kgraphicsStatePreInitUnlocked; - - pThis->__kgraphicsGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgraphicsGetTunableState; - - pThis->__kgraphicsCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgraphicsCompareTunableState; - - pThis->__kgraphicsFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgraphicsFreeTunableState; - - pThis->__kgraphicsAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgraphicsAllocTunableState; - - pThis->__kgraphicsSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgraphicsSetTunableState; } void __nvoc_init_funcTable_KernelGraphics(KernelGraphics *pThis, RmHalspecOwner *pRmhalspecowner) { @@ -369,13 +347,16 @@ NV_STATUS __nvoc_objCreate_KernelGraphics(KernelGraphics **ppThis, Dynamic *pPar KernelGraphics *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelGraphics)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelGraphics), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelGraphics)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelGraphics); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -395,11 +376,17 @@ NV_STATUS __nvoc_objCreate_KernelGraphics(KernelGraphics **ppThis, Dynamic *pPar if (status != NV_OK) goto __nvoc_objCreate_KernelGraphics_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelGraphics_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelGraphics)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_graphics_nvoc.h b/src/nvidia/generated/g_kernel_graphics_nvoc.h index 3f4e983b1..9e62cd2ef 100644 --- a/src/nvidia/generated/g_kernel_graphics_nvoc.h +++ b/src/nvidia/generated/g_kernel_graphics_nvoc.h @@ -170,18 +170,12 @@ struct KernelGraphics { NV_STATUS (*__kgraphicsServiceNotificationInterrupt__)(OBJGPU *, struct KernelGraphics *, IntrServiceServiceNotificationInterruptArguments *); NvBool (*__kgraphicsClearInterrupt__)(OBJGPU *, struct KernelGraphics *, IntrServiceClearInterruptArguments *); NvU32 (*__kgraphicsServiceInterrupt__)(OBJGPU *, struct KernelGraphics *, IntrServiceServiceInterruptArguments *); - NV_STATUS (*__kgraphicsReconcileTunableState__)(POBJGPU, struct KernelGraphics *, void *); NV_STATUS (*__kgraphicsStatePreLoad__)(POBJGPU, struct KernelGraphics *, NvU32); NV_STATUS (*__kgraphicsStatePostUnload__)(POBJGPU, struct KernelGraphics *, NvU32); NV_STATUS (*__kgraphicsStateInitUnlocked__)(POBJGPU, struct KernelGraphics *); void (*__kgraphicsInitMissing__)(POBJGPU, struct KernelGraphics *); NV_STATUS (*__kgraphicsStatePreInitLocked__)(POBJGPU, struct KernelGraphics *); NV_STATUS (*__kgraphicsStatePreInitUnlocked__)(POBJGPU, struct KernelGraphics *); - NV_STATUS (*__kgraphicsGetTunableState__)(POBJGPU, struct KernelGraphics *, void *); - NV_STATUS (*__kgraphicsCompareTunableState__)(POBJGPU, struct KernelGraphics *, void *, void *); - void (*__kgraphicsFreeTunableState__)(POBJGPU, struct KernelGraphics *, void *); - NV_STATUS (*__kgraphicsAllocTunableState__)(POBJGPU, struct KernelGraphics *, void **); - NV_STATUS (*__kgraphicsSetTunableState__)(POBJGPU, struct KernelGraphics *, void *); NvBool bCtxswLoggingSupported; NvBool bIntrDrivenCtxswLoggingEnabled; NvBool bBottomHalfCtxswLoggingEnabled; @@ -190,6 +184,7 @@ struct KernelGraphics { NvBool bSetContextBuffersGPUPrivileged; NvBool bUcodeSupportsPrivAccessMap; NvBool bRtvCbSupported; + NvBool bFecsRecordUcodeSeqnoSupported; NvU32 instance; KGRAPHICS_PRIVATE_DATA *pPrivate; NvBool bCollectingDeferredStaticData; @@ -244,18 +239,12 @@ NV_STATUS __nvoc_objCreate_KernelGraphics(KernelGraphics**, Dynamic*, NvU32); #define kgraphicsClearInterrupt_HAL(arg0, arg1, arg2) kgraphicsClearInterrupt_DISPATCH(arg0, arg1, arg2) #define kgraphicsServiceInterrupt(arg0, arg1, arg2) kgraphicsServiceInterrupt_DISPATCH(arg0, arg1, arg2) #define kgraphicsServiceInterrupt_HAL(arg0, arg1, arg2) kgraphicsServiceInterrupt_DISPATCH(arg0, arg1, arg2) -#define kgraphicsReconcileTunableState(pGpu, pEngstate, pTunableState) kgraphicsReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kgraphicsStatePreLoad(pGpu, pEngstate, arg0) kgraphicsStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kgraphicsStatePostUnload(pGpu, pEngstate, arg0) kgraphicsStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) #define kgraphicsStateInitUnlocked(pGpu, pEngstate) kgraphicsStateInitUnlocked_DISPATCH(pGpu, pEngstate) #define kgraphicsInitMissing(pGpu, pEngstate) kgraphicsInitMissing_DISPATCH(pGpu, pEngstate) #define kgraphicsStatePreInitLocked(pGpu, pEngstate) kgraphicsStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kgraphicsStatePreInitUnlocked(pGpu, pEngstate) kgraphicsStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kgraphicsGetTunableState(pGpu, pEngstate, pTunableState) kgraphicsGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kgraphicsCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kgraphicsCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kgraphicsFreeTunableState(pGpu, pEngstate, pTunableState) kgraphicsFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kgraphicsAllocTunableState(pGpu, pEngstate, ppTunableState) kgraphicsAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kgraphicsSetTunableState(pGpu, pEngstate, pTunableState) kgraphicsSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) static inline NvBool kgraphicsShouldForceMainCtxContiguity_cbe027(OBJGPU *arg0, struct KernelGraphics *arg1) { return ((NvBool)(0 == 0)); } @@ -418,9 +407,9 @@ static inline NV_STATUS kgraphicsStatePostLoad_DISPATCH(OBJGPU *arg0, struct Ker return arg1->__kgraphicsStatePostLoad__(arg0, arg1, flags); } -void kgraphicsRegisterIntrService_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceRecord arg2[163]); +void kgraphicsRegisterIntrService_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceRecord arg2[166]); -static inline void kgraphicsRegisterIntrService_DISPATCH(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceRecord arg2[163]) { +static inline void kgraphicsRegisterIntrService_DISPATCH(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceRecord arg2[166]) { arg1->__kgraphicsRegisterIntrService__(arg0, arg1, arg2); } @@ -442,10 +431,6 @@ static inline NvU32 kgraphicsServiceInterrupt_DISPATCH(OBJGPU *arg0, struct Kern return arg1->__kgraphicsServiceInterrupt__(arg0, arg1, arg2); } -static inline NV_STATUS kgraphicsReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelGraphics *pEngstate, void *pTunableState) { - return pEngstate->__kgraphicsReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kgraphicsStatePreLoad_DISPATCH(POBJGPU pGpu, struct KernelGraphics *pEngstate, NvU32 arg0) { return pEngstate->__kgraphicsStatePreLoad__(pGpu, pEngstate, arg0); } @@ -470,26 +455,6 @@ static inline NV_STATUS kgraphicsStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, str return pEngstate->__kgraphicsStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kgraphicsGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelGraphics *pEngstate, void *pTunableState) { - return pEngstate->__kgraphicsGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kgraphicsCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelGraphics *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kgraphicsCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kgraphicsFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelGraphics *pEngstate, void *pTunableState) { - pEngstate->__kgraphicsFreeTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kgraphicsAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelGraphics *pEngstate, void **ppTunableState) { - return pEngstate->__kgraphicsAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kgraphicsSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelGraphics *pEngstate, void *pTunableState) { - return pEngstate->__kgraphicsSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline KGRAPHICS_FECS_TRACE_INFO *kgraphicsGetFecsTraceInfo(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics) { return pKernelGraphics->pFecsTraceInfo; } @@ -546,6 +511,10 @@ static inline NvBool kgraphicsIsRtvCbSupported(OBJGPU *pGpu, struct KernelGraphi return pKernelGraphics->bRtvCbSupported; } +static inline NvBool kgraphicsIsFecsRecordUcodeSeqnoSupported(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics) { + return pKernelGraphics->bFecsRecordUcodeSeqnoSupported; +} + void kgraphicsDestruct_IMPL(struct KernelGraphics *arg0); #define __nvoc_kgraphicsDestruct(arg0) kgraphicsDestruct_IMPL(arg0) @@ -730,6 +699,28 @@ static inline NV_STATUS kgraphicsCreateGoldenImageChannel(OBJGPU *arg0, struct K #define kgraphicsCreateGoldenImageChannel(arg0, arg1) kgraphicsCreateGoldenImageChannel_IMPL(arg0, arg1) #endif //__nvoc_kernel_graphics_h_disabled +NvBool kgraphicsIsGFXSupported_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1); + +#ifdef __nvoc_kernel_graphics_h_disabled +static inline NvBool kgraphicsIsGFXSupported(OBJGPU *arg0, struct KernelGraphics *arg1) { + NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); + return NV_FALSE; +} +#else //__nvoc_kernel_graphics_h_disabled +#define kgraphicsIsGFXSupported(arg0, arg1) kgraphicsIsGFXSupported_IMPL(arg0, arg1) +#endif //__nvoc_kernel_graphics_h_disabled + +NV_STATUS kgraphicsDiscoverMaxLocalCtxBufferSize_IMPL(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics); + +#ifdef __nvoc_kernel_graphics_h_disabled +static inline NV_STATUS kgraphicsDiscoverMaxLocalCtxBufferSize(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics) { + NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_graphics_h_disabled +#define kgraphicsDiscoverMaxLocalCtxBufferSize(pGpu, pKernelGraphics) kgraphicsDiscoverMaxLocalCtxBufferSize_IMPL(pGpu, pKernelGraphics) +#endif //__nvoc_kernel_graphics_h_disabled + NV_STATUS kgraphicsInitializeDeferredStaticData_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1, NvHandle hClient, NvHandle hSubdevice); #ifdef __nvoc_kernel_graphics_h_disabled diff --git a/src/nvidia/generated/g_kernel_graphics_object_nvoc.c b/src/nvidia/generated/g_kernel_graphics_object_nvoc.c index f95267727..45474cd4a 100644 --- a/src/nvidia/generated/g_kernel_graphics_object_nvoc.c +++ b/src/nvidia/generated/g_kernel_graphics_object_nvoc.c @@ -180,7 +180,7 @@ static NV_STATUS __nvoc_thunk_RsResource_kgrobjControlLookup(struct KernelGraphi return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsObject_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_ChannelDescendant_kgrobjGetSwMethods(struct KernelGraphicsObject *pChannelDescendant, METHOD **ppMethods, NvU32 *pNumMethods) { +static NV_STATUS __nvoc_thunk_ChannelDescendant_kgrobjGetSwMethods(struct KernelGraphicsObject *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return chandesGetSwMethods((struct ChannelDescendant *)(((unsigned char *)pChannelDescendant) + __nvoc_rtti_KernelGraphicsObject_ChannelDescendant.offset), ppMethods, pNumMethods); } @@ -212,6 +212,10 @@ static NV_STATUS __nvoc_thunk_Notifier_kgrobjUnregisterEvent(struct KernelGraphi return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelGraphicsObject_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_kgrobjControlSerialization_Prologue(struct KernelGraphicsObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsObject_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_kgrobjCanCopy(struct KernelGraphicsObject *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsObject_RsResource.offset)); } @@ -224,6 +228,10 @@ static NV_STATUS __nvoc_thunk_RsResource_kgrobjIsDuplicate(struct KernelGraphics return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsObject_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_kgrobjControlSerialization_Epilogue(struct KernelGraphicsObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsObject_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_kgrobjGetNotificationListPtr(struct KernelGraphicsObject *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelGraphicsObject_Notifier.offset)); } @@ -345,12 +353,16 @@ static void __nvoc_init_funcTable_KernelGraphicsObject_1(KernelGraphicsObject *p pThis->__kgrobjUnregisterEvent__ = &__nvoc_thunk_Notifier_kgrobjUnregisterEvent; + pThis->__kgrobjControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_kgrobjControlSerialization_Prologue; + pThis->__kgrobjCanCopy__ = &__nvoc_thunk_RsResource_kgrobjCanCopy; pThis->__kgrobjPreDestruct__ = &__nvoc_thunk_RsResource_kgrobjPreDestruct; pThis->__kgrobjIsDuplicate__ = &__nvoc_thunk_RsResource_kgrobjIsDuplicate; + pThis->__kgrobjControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_kgrobjControlSerialization_Epilogue; + pThis->__kgrobjGetNotificationListPtr__ = &__nvoc_thunk_Notifier_kgrobjGetNotificationListPtr; pThis->__kgrobjGetNotificationShare__ = &__nvoc_thunk_Notifier_kgrobjGetNotificationShare; @@ -385,13 +397,16 @@ NV_STATUS __nvoc_objCreate_KernelGraphicsObject(KernelGraphicsObject **ppThis, D KernelGraphicsObject *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelGraphicsObject)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelGraphicsObject), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelGraphicsObject)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelGraphicsObject); + pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -411,11 +426,17 @@ NV_STATUS __nvoc_objCreate_KernelGraphicsObject(KernelGraphicsObject **ppThis, D if (status != NV_OK) goto __nvoc_objCreate_KernelGraphicsObject_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelGraphicsObject_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelGraphicsObject)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_graphics_object_nvoc.h b/src/nvidia/generated/g_kernel_graphics_object_nvoc.h index 7005d4736..a9391348a 100644 --- a/src/nvidia/generated/g_kernel_graphics_object_nvoc.h +++ b/src/nvidia/generated/g_kernel_graphics_object_nvoc.h @@ -91,7 +91,7 @@ struct KernelGraphicsObject { NV_STATUS (*__kgrobjUnmapFrom__)(struct KernelGraphicsObject *, RS_RES_UNMAP_FROM_PARAMS *); void (*__kgrobjControl_Epilogue__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kgrobjControlLookup__)(struct KernelGraphicsObject *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); - NV_STATUS (*__kgrobjGetSwMethods__)(struct KernelGraphicsObject *, METHOD **, NvU32 *); + NV_STATUS (*__kgrobjGetSwMethods__)(struct KernelGraphicsObject *, const METHOD **, NvU32 *); NvHandle (*__kgrobjGetInternalObjectHandle__)(struct KernelGraphicsObject *); NV_STATUS (*__kgrobjControl__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kgrobjUnmap__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -99,9 +99,11 @@ struct KernelGraphicsObject { NvBool (*__kgrobjIsSwMethodStalling__)(struct KernelGraphicsObject *, NvU32); NV_STATUS (*__kgrobjControlFilter__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kgrobjUnregisterEvent__)(struct KernelGraphicsObject *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__kgrobjControlSerialization_Prologue__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__kgrobjCanCopy__)(struct KernelGraphicsObject *); void (*__kgrobjPreDestruct__)(struct KernelGraphicsObject *); NV_STATUS (*__kgrobjIsDuplicate__)(struct KernelGraphicsObject *, NvHandle, NvBool *); + void (*__kgrobjControlSerialization_Epilogue__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__kgrobjGetNotificationListPtr__)(struct KernelGraphicsObject *); struct NotifShare *(*__kgrobjGetNotificationShare__)(struct KernelGraphicsObject *); NV_STATUS (*__kgrobjMap__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -162,9 +164,11 @@ NV_STATUS __nvoc_objCreate_KernelGraphicsObject(KernelGraphicsObject**, Dynamic* #define kgrobjIsSwMethodStalling(pChannelDescendant, hHandle) kgrobjIsSwMethodStalling_DISPATCH(pChannelDescendant, hHandle) #define kgrobjControlFilter(pResource, pCallContext, pParams) kgrobjControlFilter_DISPATCH(pResource, pCallContext, pParams) #define kgrobjUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) kgrobjUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define kgrobjControlSerialization_Prologue(pResource, pCallContext, pParams) kgrobjControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define kgrobjCanCopy(pResource) kgrobjCanCopy_DISPATCH(pResource) #define kgrobjPreDestruct(pResource) kgrobjPreDestruct_DISPATCH(pResource) #define kgrobjIsDuplicate(pResource, hMemory, pDuplicate) kgrobjIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define kgrobjControlSerialization_Epilogue(pResource, pCallContext, pParams) kgrobjControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define kgrobjGetNotificationListPtr(pNotifier) kgrobjGetNotificationListPtr_DISPATCH(pNotifier) #define kgrobjGetNotificationShare(pNotifier) kgrobjGetNotificationShare_DISPATCH(pNotifier) #define kgrobjMap(pGpuResource, pCallContext, pParams, pCpuMapping) kgrobjMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -285,7 +289,7 @@ static inline NV_STATUS kgrobjControlLookup_DISPATCH(struct KernelGraphicsObject return pResource->__kgrobjControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS kgrobjGetSwMethods_DISPATCH(struct KernelGraphicsObject *pChannelDescendant, METHOD **ppMethods, NvU32 *pNumMethods) { +static inline NV_STATUS kgrobjGetSwMethods_DISPATCH(struct KernelGraphicsObject *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return pChannelDescendant->__kgrobjGetSwMethods__(pChannelDescendant, ppMethods, pNumMethods); } @@ -317,6 +321,10 @@ static inline NV_STATUS kgrobjUnregisterEvent_DISPATCH(struct KernelGraphicsObje return pNotifier->__kgrobjUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS kgrobjControlSerialization_Prologue_DISPATCH(struct KernelGraphicsObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__kgrobjControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool kgrobjCanCopy_DISPATCH(struct KernelGraphicsObject *pResource) { return pResource->__kgrobjCanCopy__(pResource); } @@ -329,6 +337,10 @@ static inline NV_STATUS kgrobjIsDuplicate_DISPATCH(struct KernelGraphicsObject * return pResource->__kgrobjIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void kgrobjControlSerialization_Epilogue_DISPATCH(struct KernelGraphicsObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__kgrobjControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *kgrobjGetNotificationListPtr_DISPATCH(struct KernelGraphicsObject *pNotifier) { return pNotifier->__kgrobjGetNotificationListPtr__(pNotifier); } diff --git a/src/nvidia/generated/g_kernel_gsp_nvoc.c b/src/nvidia/generated/g_kernel_gsp_nvoc.c index de45262c0..12c36becf 100644 --- a/src/nvidia/generated/g_kernel_gsp_nvoc.c +++ b/src/nvidia/generated/g_kernel_gsp_nvoc.c @@ -88,7 +88,7 @@ static NV_STATUS __nvoc_thunk_KernelGsp_engstateConstructEngine(struct OBJGPU *p return kgspConstructEngine(pGpu, (struct KernelGsp *)(((unsigned char *)pKernelGsp) - __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), arg0); } -static void __nvoc_thunk_KernelGsp_intrservRegisterIntrService(struct OBJGPU *pGpu, struct IntrService *pKernelGsp, IntrServiceRecord pRecords[163]) { +static void __nvoc_thunk_KernelGsp_intrservRegisterIntrService(struct OBJGPU *pGpu, struct IntrService *pKernelGsp, IntrServiceRecord pRecords[166]) { kgspRegisterIntrService(pGpu, (struct KernelGsp *)(((unsigned char *)pKernelGsp) - __nvoc_rtti_KernelGsp_IntrService.offset), pRecords); } @@ -100,34 +100,6 @@ static NV_STATUS __nvoc_thunk_KernelGsp_kflcnResetHw(struct OBJGPU *pGpu, struct return kgspResetHw(pGpu, (struct KernelGsp *)(((unsigned char *)pKernelGsp) - __nvoc_rtti_KernelGsp_KernelFalcon.offset)); } -static NvBool __nvoc_thunk_KernelGsp_kflcnIsEngineInReset(struct OBJGPU *pGpu, struct KernelFalcon *pKernelGsp) { - return kgspIsEngineInReset(pGpu, (struct KernelGsp *)(((unsigned char *)pKernelGsp) - __nvoc_rtti_KernelGsp_KernelFalcon.offset)); -} - -static void __nvoc_thunk_OBJENGSTATE_kgspStateDestroy(POBJGPU pGpu, struct KernelGsp *pEngstate) { - engstateStateDestroy(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset)); -} - -static void __nvoc_thunk_OBJENGSTATE_kgspFreeTunableState(POBJGPU pGpu, struct KernelGsp *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspCompareTunableState(POBJGPU pGpu, struct KernelGsp *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static NvBool __nvoc_thunk_IntrService_kgspClearInterrupt(struct OBJGPU *pGpu, struct KernelGsp *pIntrService, IntrServiceClearInterruptArguments *pParams) { - return intrservClearInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_KernelGsp_IntrService.offset), pParams); -} - -static NvBool __nvoc_thunk_OBJENGSTATE_kgspIsPresent(POBJGPU pGpu, struct KernelGsp *pEngstate) { - return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset)); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspReconcileTunableState(POBJGPU pGpu, struct KernelGsp *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspStateLoad(POBJGPU pGpu, struct KernelGsp *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), arg0); } @@ -152,12 +124,12 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspStatePostUnload(POBJGPU pGpu, stru return engstateStatePostUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspStatePreUnload(POBJGPU pGpu, struct KernelGsp *pEngstate, NvU32 arg0) { - return engstateStatePreUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), arg0); +static void __nvoc_thunk_OBJENGSTATE_kgspStateDestroy(POBJGPU pGpu, struct KernelGsp *pEngstate) { + engstateStateDestroy(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspGetTunableState(POBJGPU pGpu, struct KernelGsp *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), pTunableState); +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspStatePreUnload(POBJGPU pGpu, struct KernelGsp *pEngstate, NvU32 arg0) { + return engstateStatePreUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), arg0); } static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspStateInitUnlocked(POBJGPU pGpu, struct KernelGsp *pEngstate) { @@ -176,16 +148,16 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspStatePreInitUnlocked(POBJGPU pGpu, return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset)); } +static NvBool __nvoc_thunk_IntrService_kgspClearInterrupt(struct OBJGPU *pGpu, struct KernelGsp *pIntrService, IntrServiceClearInterruptArguments *pParams) { + return intrservClearInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_KernelGsp_IntrService.offset), pParams); +} + static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspStatePostLoad(POBJGPU pGpu, struct KernelGsp *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspAllocTunableState(POBJGPU pGpu, struct KernelGsp *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspSetTunableState(POBJGPU pGpu, struct KernelGsp *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), pTunableState); +static NvBool __nvoc_thunk_OBJENGSTATE_kgspIsPresent(POBJGPU pGpu, struct KernelGsp *pEngstate) { + return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset)); } const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelGsp = @@ -217,6 +189,9 @@ void __nvoc_init_dataField_KernelGsp(KernelGsp *pThis, RmHalspecOwner *pRmhalspe PORT_UNREFERENCED_VARIABLE(rmVariantHal); PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); + // Hal field -- bIsTaskIsrQueueRequired + pThis->bIsTaskIsrQueueRequired = ((NvBool)(0 != 0)); + // Hal field -- bPartitionedFmc if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { @@ -475,15 +450,6 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * } } - // Hal function -- kgspIsEngineInReset - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->__kgspIsEngineInReset__ = &kgspIsEngineInReset_TU102; - } - } - // Hal function -- kgspGetFrtsSize if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { @@ -681,26 +647,22 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * { if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GH100 */ { - pThis->__kgspGetWprHeapSize__ = &kgspGetWprHeapSize_5661b8; + pThis->__kgspGetWprHeapSize__ = &kgspGetWprHeapSize_45a5e0; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { - pThis->__kgspGetWprHeapSize__ = &kgspGetWprHeapSize_15390a; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__kgspGetWprHeapSize__ = &kgspGetWprHeapSize_AD102; + pThis->__kgspGetWprHeapSize__ = &kgspGetWprHeapSize_31541f; } } // Hal function -- kgspInitVgpuPartitionLogging if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x1000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GH100 */ { pThis->__kgspInitVgpuPartitionLogging__ = &kgspInitVgpuPartitionLogging_395e98; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgspInitVgpuPartitionLogging__ = &kgspInitVgpuPartitionLogging_IMPL; } @@ -709,11 +671,11 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * // Hal function -- kgspFreeVgpuPartitionLogging if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x1000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GH100 */ { pThis->__kgspFreeVgpuPartitionLogging__ = &kgspFreeVgpuPartitionLogging_395e98; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgspFreeVgpuPartitionLogging__ = &kgspFreeVgpuPartitionLogging_IMPL; } @@ -755,20 +717,6 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * pThis->__nvoc_base_KernelFalcon.__kflcnResetHw__ = &__nvoc_thunk_KernelGsp_kflcnResetHw; - pThis->__nvoc_base_KernelFalcon.__kflcnIsEngineInReset__ = &__nvoc_thunk_KernelGsp_kflcnIsEngineInReset; - - pThis->__kgspStateDestroy__ = &__nvoc_thunk_OBJENGSTATE_kgspStateDestroy; - - pThis->__kgspFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgspFreeTunableState; - - pThis->__kgspCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgspCompareTunableState; - - pThis->__kgspClearInterrupt__ = &__nvoc_thunk_IntrService_kgspClearInterrupt; - - pThis->__kgspIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kgspIsPresent; - - pThis->__kgspReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgspReconcileTunableState; - pThis->__kgspStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kgspStateLoad; pThis->__kgspStateUnload__ = &__nvoc_thunk_OBJENGSTATE_kgspStateUnload; @@ -781,9 +729,9 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * pThis->__kgspStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_kgspStatePostUnload; - pThis->__kgspStatePreUnload__ = &__nvoc_thunk_OBJENGSTATE_kgspStatePreUnload; + pThis->__kgspStateDestroy__ = &__nvoc_thunk_OBJENGSTATE_kgspStateDestroy; - pThis->__kgspGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgspGetTunableState; + pThis->__kgspStatePreUnload__ = &__nvoc_thunk_OBJENGSTATE_kgspStatePreUnload; pThis->__kgspStateInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kgspStateInitUnlocked; @@ -793,11 +741,11 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * pThis->__kgspStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kgspStatePreInitUnlocked; + pThis->__kgspClearInterrupt__ = &__nvoc_thunk_IntrService_kgspClearInterrupt; + pThis->__kgspStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kgspStatePostLoad; - pThis->__kgspAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgspAllocTunableState; - - pThis->__kgspSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kgspSetTunableState; + pThis->__kgspIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kgspIsPresent; } void __nvoc_init_funcTable_KernelGsp(KernelGsp *pThis, RmHalspecOwner *pRmhalspecowner) { @@ -825,13 +773,16 @@ NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp **ppThis, Dynamic *pParent, NvU32 KernelGsp *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelGsp)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelGsp), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelGsp)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelGsp); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -851,11 +802,17 @@ NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp **ppThis, Dynamic *pParent, NvU32 if (status != NV_OK) goto __nvoc_objCreate_KernelGsp_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelGsp_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelGsp)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_gsp_nvoc.h b/src/nvidia/generated/g_kernel_gsp_nvoc.h index d6219e777..13762fe38 100644 --- a/src/nvidia/generated/g_kernel_gsp_nvoc.h +++ b/src/nvidia/generated/g_kernel_gsp_nvoc.h @@ -48,12 +48,14 @@ extern "C" { #include "gpu/falcon/kernel_falcon.h" #include "gpu/gsp/gsp_static_config.h" #include "gpu/gsp/gsp_init_args.h" +#include "gpu/gsp/gsp_fw_heap.h" #include "nv-firmware.h" #include "nv_sriov_defines.h" #include "rmRiscvUcode.h" #include "libos_init_args.h" #include "gsp_fw_wpr_meta.h" +#include "gsp_fw_sr_meta.h" #include "liblogdecode.h" /*! @@ -239,6 +241,9 @@ typedef struct #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif +struct MESSAGE_QUEUE_COLLECTION; + + struct KernelGsp { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; @@ -266,7 +271,6 @@ struct KernelGsp { NV_STATUS (*__kgspExecuteSequencerCommand__)(struct OBJGPU *, struct KernelGsp *, NvU32, NvU32 *, NvU32); NvU32 (*__kgspReadUcodeFuseVersion__)(struct OBJGPU *, struct KernelGsp *, NvU32); NV_STATUS (*__kgspResetHw__)(struct OBJGPU *, struct KernelGsp *); - NvBool (*__kgspIsEngineInReset__)(struct OBJGPU *, struct KernelGsp *); NvU32 (*__kgspGetFrtsSize__)(struct OBJGPU *, struct KernelGsp *); NvU64 (*__kgspGetPrescrubbedTopFbSize__)(struct OBJGPU *, struct KernelGsp *); NV_STATUS (*__kgspExtractVbiosFromRom__)(struct OBJGPU *, struct KernelGsp *, KernelGspVbiosImg **); @@ -274,7 +278,7 @@ struct KernelGsp { NV_STATUS (*__kgspExecuteFwsecSb__)(struct OBJGPU *, struct KernelGsp *, KernelGspFlcnUcode *); NV_STATUS (*__kgspExecuteScrubberIfNeeded__)(struct OBJGPU *, struct KernelGsp *); NV_STATUS (*__kgspExecuteBooterLoad__)(struct OBJGPU *, struct KernelGsp *, const NvU64); - NV_STATUS (*__kgspExecuteBooterUnloadIfNeeded__)(struct OBJGPU *, struct KernelGsp *); + NV_STATUS (*__kgspExecuteBooterUnloadIfNeeded__)(struct OBJGPU *, struct KernelGsp *, const NvU64); NV_STATUS (*__kgspExecuteHsFalcon__)(struct OBJGPU *, struct KernelGsp *, KernelGspFlcnUcode *, struct KernelFalcon *, NvU32 *, NvU32 *); NV_STATUS (*__kgspWaitForGfwBootOk__)(struct OBJGPU *, struct KernelGsp *); const BINDATA_ARCHIVE *(*__kgspGetBinArchiveBooterLoadUcode__)(struct KernelGsp *); @@ -284,28 +288,24 @@ struct KernelGsp { NV_STATUS (*__kgspFreeVgpuPartitionLogging__)(struct OBJGPU *, struct KernelGsp *, NvU32); const char *(*__kgspGetSignatureSectionNamePrefix__)(struct OBJGPU *, struct KernelGsp *); NV_STATUS (*__kgspSetupGspFmcArgs__)(struct OBJGPU *, struct KernelGsp *, GSP_FIRMWARE *); - void (*__kgspStateDestroy__)(POBJGPU, struct KernelGsp *); - void (*__kgspFreeTunableState__)(POBJGPU, struct KernelGsp *, void *); - NV_STATUS (*__kgspCompareTunableState__)(POBJGPU, struct KernelGsp *, void *, void *); - NvBool (*__kgspClearInterrupt__)(struct OBJGPU *, struct KernelGsp *, IntrServiceClearInterruptArguments *); - NvBool (*__kgspIsPresent__)(POBJGPU, struct KernelGsp *); - NV_STATUS (*__kgspReconcileTunableState__)(POBJGPU, struct KernelGsp *, void *); NV_STATUS (*__kgspStateLoad__)(POBJGPU, struct KernelGsp *, NvU32); NV_STATUS (*__kgspStateUnload__)(POBJGPU, struct KernelGsp *, NvU32); NV_STATUS (*__kgspServiceNotificationInterrupt__)(struct OBJGPU *, struct KernelGsp *, IntrServiceServiceNotificationInterruptArguments *); NV_STATUS (*__kgspStateInitLocked__)(POBJGPU, struct KernelGsp *); NV_STATUS (*__kgspStatePreLoad__)(POBJGPU, struct KernelGsp *, NvU32); NV_STATUS (*__kgspStatePostUnload__)(POBJGPU, struct KernelGsp *, NvU32); + void (*__kgspStateDestroy__)(POBJGPU, struct KernelGsp *); NV_STATUS (*__kgspStatePreUnload__)(POBJGPU, struct KernelGsp *, NvU32); - NV_STATUS (*__kgspGetTunableState__)(POBJGPU, struct KernelGsp *, void *); NV_STATUS (*__kgspStateInitUnlocked__)(POBJGPU, struct KernelGsp *); void (*__kgspInitMissing__)(POBJGPU, struct KernelGsp *); NV_STATUS (*__kgspStatePreInitLocked__)(POBJGPU, struct KernelGsp *); NV_STATUS (*__kgspStatePreInitUnlocked__)(POBJGPU, struct KernelGsp *); + NvBool (*__kgspClearInterrupt__)(struct OBJGPU *, struct KernelGsp *, IntrServiceClearInterruptArguments *); NV_STATUS (*__kgspStatePostLoad__)(POBJGPU, struct KernelGsp *, NvU32); - NV_STATUS (*__kgspAllocTunableState__)(POBJGPU, struct KernelGsp *, void **); - NV_STATUS (*__kgspSetTunableState__)(POBJGPU, struct KernelGsp *, void *); + NvBool (*__kgspIsPresent__)(POBJGPU, struct KernelGsp *); + struct MESSAGE_QUEUE_COLLECTION *pMQCollection; struct OBJRPC *pRpc; + struct OBJRPC *pLocklessRpc; KernelGspFlcnUcode *pFwsecUcode; KernelGspFlcnUcode *pScrubberUcode; KernelGspFlcnUcode *pBooterLoadUcode; @@ -313,6 +313,8 @@ struct KernelGsp { MEMORY_DESCRIPTOR *pWprMetaDescriptor; GspFwWprMeta *pWprMeta; NvP64 pWprMetaMappingPriv; + MEMORY_DESCRIPTOR *pSRMetaDescriptor; + MEMORY_DESCRIPTOR *pSRRadix3Descriptor; MEMORY_DESCRIPTOR *pGspFmcArgumentsDescriptor; GSP_FMC_BOOT_PARAMS *pGspFmcArgumentsCached; NvP64 pGspFmcArgumentsMappingPriv; @@ -345,6 +347,7 @@ struct KernelGsp { SimAccessBuffer *pSimAccessBuf; NvP64 pSimAccessBufPriv; GspStaticConfigInfo gspStaticInfo; + NvBool bIsTaskIsrQueueRequired; NvBool bPartitionedFmc; }; @@ -409,8 +412,6 @@ NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp**, Dynamic*, NvU32); #define kgspReadUcodeFuseVersion_HAL(pGpu, pKernelGsp, ucodeId) kgspReadUcodeFuseVersion_DISPATCH(pGpu, pKernelGsp, ucodeId) #define kgspResetHw(pGpu, pKernelGsp) kgspResetHw_DISPATCH(pGpu, pKernelGsp) #define kgspResetHw_HAL(pGpu, pKernelGsp) kgspResetHw_DISPATCH(pGpu, pKernelGsp) -#define kgspIsEngineInReset(pGpu, pKernelGsp) kgspIsEngineInReset_DISPATCH(pGpu, pKernelGsp) -#define kgspIsEngineInReset_HAL(pGpu, pKernelGsp) kgspIsEngineInReset_DISPATCH(pGpu, pKernelGsp) #define kgspGetFrtsSize(pGpu, pKernelGsp) kgspGetFrtsSize_DISPATCH(pGpu, pKernelGsp) #define kgspGetFrtsSize_HAL(pGpu, pKernelGsp) kgspGetFrtsSize_DISPATCH(pGpu, pKernelGsp) #define kgspGetPrescrubbedTopFbSize(pGpu, pKernelGsp) kgspGetPrescrubbedTopFbSize_DISPATCH(pGpu, pKernelGsp) @@ -423,10 +424,10 @@ NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp**, Dynamic*, NvU32); #define kgspExecuteFwsecSb_HAL(pGpu, pKernelGsp, pFwsecUcode) kgspExecuteFwsecSb_DISPATCH(pGpu, pKernelGsp, pFwsecUcode) #define kgspExecuteScrubberIfNeeded(pGpu, pKernelGsp) kgspExecuteScrubberIfNeeded_DISPATCH(pGpu, pKernelGsp) #define kgspExecuteScrubberIfNeeded_HAL(pGpu, pKernelGsp) kgspExecuteScrubberIfNeeded_DISPATCH(pGpu, pKernelGsp) -#define kgspExecuteBooterLoad(pGpu, pKernelGsp, gspFwWprMetaOffset) kgspExecuteBooterLoad_DISPATCH(pGpu, pKernelGsp, gspFwWprMetaOffset) -#define kgspExecuteBooterLoad_HAL(pGpu, pKernelGsp, gspFwWprMetaOffset) kgspExecuteBooterLoad_DISPATCH(pGpu, pKernelGsp, gspFwWprMetaOffset) -#define kgspExecuteBooterUnloadIfNeeded(pGpu, pKernelGsp) kgspExecuteBooterUnloadIfNeeded_DISPATCH(pGpu, pKernelGsp) -#define kgspExecuteBooterUnloadIfNeeded_HAL(pGpu, pKernelGsp) kgspExecuteBooterUnloadIfNeeded_DISPATCH(pGpu, pKernelGsp) +#define kgspExecuteBooterLoad(pGpu, pKernelGsp, sysmemAddrOfData) kgspExecuteBooterLoad_DISPATCH(pGpu, pKernelGsp, sysmemAddrOfData) +#define kgspExecuteBooterLoad_HAL(pGpu, pKernelGsp, sysmemAddrOfData) kgspExecuteBooterLoad_DISPATCH(pGpu, pKernelGsp, sysmemAddrOfData) +#define kgspExecuteBooterUnloadIfNeeded(pGpu, pKernelGsp, sysmemAddrOfSuspendResumeData) kgspExecuteBooterUnloadIfNeeded_DISPATCH(pGpu, pKernelGsp, sysmemAddrOfSuspendResumeData) +#define kgspExecuteBooterUnloadIfNeeded_HAL(pGpu, pKernelGsp, sysmemAddrOfSuspendResumeData) kgspExecuteBooterUnloadIfNeeded_DISPATCH(pGpu, pKernelGsp, sysmemAddrOfSuspendResumeData) #define kgspExecuteHsFalcon(pGpu, pKernelGsp, pFlcnUcode, pKernelFlcn, pMailbox0, pMailbox1) kgspExecuteHsFalcon_DISPATCH(pGpu, pKernelGsp, pFlcnUcode, pKernelFlcn, pMailbox0, pMailbox1) #define kgspExecuteHsFalcon_HAL(pGpu, pKernelGsp, pFlcnUcode, pKernelFlcn, pMailbox0, pMailbox1) kgspExecuteHsFalcon_DISPATCH(pGpu, pKernelGsp, pFlcnUcode, pKernelFlcn, pMailbox0, pMailbox1) #define kgspWaitForGfwBootOk(pGpu, pKernelGsp) kgspWaitForGfwBootOk_DISPATCH(pGpu, pKernelGsp) @@ -445,27 +446,21 @@ NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp**, Dynamic*, NvU32); #define kgspGetSignatureSectionNamePrefix_HAL(pGpu, pKernelGsp) kgspGetSignatureSectionNamePrefix_DISPATCH(pGpu, pKernelGsp) #define kgspSetupGspFmcArgs(pGpu, pKernelGsp, pGspFw) kgspSetupGspFmcArgs_DISPATCH(pGpu, pKernelGsp, pGspFw) #define kgspSetupGspFmcArgs_HAL(pGpu, pKernelGsp, pGspFw) kgspSetupGspFmcArgs_DISPATCH(pGpu, pKernelGsp, pGspFw) -#define kgspStateDestroy(pGpu, pEngstate) kgspStateDestroy_DISPATCH(pGpu, pEngstate) -#define kgspFreeTunableState(pGpu, pEngstate, pTunableState) kgspFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kgspCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kgspCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kgspClearInterrupt(pGpu, pIntrService, pParams) kgspClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) -#define kgspIsPresent(pGpu, pEngstate) kgspIsPresent_DISPATCH(pGpu, pEngstate) -#define kgspReconcileTunableState(pGpu, pEngstate, pTunableState) kgspReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kgspStateLoad(pGpu, pEngstate, arg0) kgspStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kgspStateUnload(pGpu, pEngstate, arg0) kgspStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define kgspServiceNotificationInterrupt(pGpu, pIntrService, pParams) kgspServiceNotificationInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define kgspStateInitLocked(pGpu, pEngstate) kgspStateInitLocked_DISPATCH(pGpu, pEngstate) #define kgspStatePreLoad(pGpu, pEngstate, arg0) kgspStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kgspStatePostUnload(pGpu, pEngstate, arg0) kgspStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) +#define kgspStateDestroy(pGpu, pEngstate) kgspStateDestroy_DISPATCH(pGpu, pEngstate) #define kgspStatePreUnload(pGpu, pEngstate, arg0) kgspStatePreUnload_DISPATCH(pGpu, pEngstate, arg0) -#define kgspGetTunableState(pGpu, pEngstate, pTunableState) kgspGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kgspStateInitUnlocked(pGpu, pEngstate) kgspStateInitUnlocked_DISPATCH(pGpu, pEngstate) #define kgspInitMissing(pGpu, pEngstate) kgspInitMissing_DISPATCH(pGpu, pEngstate) #define kgspStatePreInitLocked(pGpu, pEngstate) kgspStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kgspStatePreInitUnlocked(pGpu, pEngstate) kgspStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) +#define kgspClearInterrupt(pGpu, pIntrService, pParams) kgspClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define kgspStatePostLoad(pGpu, pEngstate, arg0) kgspStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define kgspAllocTunableState(pGpu, pEngstate, ppTunableState) kgspAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kgspSetTunableState(pGpu, pEngstate, pTunableState) kgspSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) +#define kgspIsPresent(pGpu, pEngstate) kgspIsPresent_DISPATCH(pGpu, pEngstate) void kgspProgramLibosBootArgsAddr_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); @@ -534,15 +529,56 @@ static inline NV_STATUS kgspWaitForProcessorSuspend(struct OBJGPU *pGpu, struct #define kgspWaitForProcessorSuspend_HAL(pGpu, pKernelGsp) kgspWaitForProcessorSuspend(pGpu, pKernelGsp) +NV_STATUS kgspSavePowerMgmtState_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + + +#ifdef __nvoc_kernel_gsp_h_disabled +static inline NV_STATUS kgspSavePowerMgmtState(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_gsp_h_disabled +#define kgspSavePowerMgmtState(pGpu, pKernelGsp) kgspSavePowerMgmtState_TU102(pGpu, pKernelGsp) +#endif //__nvoc_kernel_gsp_h_disabled + +#define kgspSavePowerMgmtState_HAL(pGpu, pKernelGsp) kgspSavePowerMgmtState(pGpu, pKernelGsp) + +NV_STATUS kgspRestorePowerMgmtState_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + + +#ifdef __nvoc_kernel_gsp_h_disabled +static inline NV_STATUS kgspRestorePowerMgmtState(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_gsp_h_disabled +#define kgspRestorePowerMgmtState(pGpu, pKernelGsp) kgspRestorePowerMgmtState_TU102(pGpu, pKernelGsp) +#endif //__nvoc_kernel_gsp_h_disabled + +#define kgspRestorePowerMgmtState_HAL(pGpu, pKernelGsp) kgspRestorePowerMgmtState(pGpu, pKernelGsp) + +void kgspFreeSuspendResumeData_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + + +#ifdef __nvoc_kernel_gsp_h_disabled +static inline void kgspFreeSuspendResumeData(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); +} +#else //__nvoc_kernel_gsp_h_disabled +#define kgspFreeSuspendResumeData(pGpu, pKernelGsp) kgspFreeSuspendResumeData_TU102(pGpu, pKernelGsp) +#endif //__nvoc_kernel_gsp_h_disabled + +#define kgspFreeSuspendResumeData_HAL(pGpu, pKernelGsp) kgspFreeSuspendResumeData(pGpu, pKernelGsp) + NV_STATUS kgspConstructEngine_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, ENGDESCRIPTOR arg0); static inline NV_STATUS kgspConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, ENGDESCRIPTOR arg0) { return pKernelGsp->__kgspConstructEngine__(pGpu, pKernelGsp, arg0); } -void kgspRegisterIntrService_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, IntrServiceRecord pRecords[163]); +void kgspRegisterIntrService_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, IntrServiceRecord pRecords[166]); -static inline void kgspRegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, IntrServiceRecord pRecords[163]) { +static inline void kgspRegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, IntrServiceRecord pRecords[166]) { pKernelGsp->__kgspRegisterIntrService__(pGpu, pKernelGsp, pRecords); } @@ -684,12 +720,6 @@ static inline NV_STATUS kgspResetHw_DISPATCH(struct OBJGPU *pGpu, struct KernelG return pKernelGsp->__kgspResetHw__(pGpu, pKernelGsp); } -NvBool kgspIsEngineInReset_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); - -static inline NvBool kgspIsEngineInReset_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - return pKernelGsp->__kgspIsEngineInReset__(pGpu, pKernelGsp); -} - NvU32 kgspGetFrtsSize_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); static inline NvU32 kgspGetFrtsSize_4a4dee(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { @@ -752,24 +782,24 @@ static inline NV_STATUS kgspExecuteScrubberIfNeeded_DISPATCH(struct OBJGPU *pGpu return pKernelGsp->__kgspExecuteScrubberIfNeeded__(pGpu, pKernelGsp); } -NV_STATUS kgspExecuteBooterLoad_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const NvU64 gspFwWprMetaOffset); +NV_STATUS kgspExecuteBooterLoad_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const NvU64 sysmemAddrOfData); -static inline NV_STATUS kgspExecuteBooterLoad_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const NvU64 gspFwWprMetaOffset) { +static inline NV_STATUS kgspExecuteBooterLoad_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const NvU64 sysmemAddrOfData) { NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } -static inline NV_STATUS kgspExecuteBooterLoad_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const NvU64 gspFwWprMetaOffset) { - return pKernelGsp->__kgspExecuteBooterLoad__(pGpu, pKernelGsp, gspFwWprMetaOffset); +static inline NV_STATUS kgspExecuteBooterLoad_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const NvU64 sysmemAddrOfData) { + return pKernelGsp->__kgspExecuteBooterLoad__(pGpu, pKernelGsp, sysmemAddrOfData); } -NV_STATUS kgspExecuteBooterUnloadIfNeeded_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); +NV_STATUS kgspExecuteBooterUnloadIfNeeded_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const NvU64 sysmemAddrOfSuspendResumeData); -static inline NV_STATUS kgspExecuteBooterUnloadIfNeeded_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { +static inline NV_STATUS kgspExecuteBooterUnloadIfNeeded_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const NvU64 sysmemAddrOfSuspendResumeData) { NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } -static inline NV_STATUS kgspExecuteBooterUnloadIfNeeded_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - return pKernelGsp->__kgspExecuteBooterUnloadIfNeeded__(pGpu, pKernelGsp); +static inline NV_STATUS kgspExecuteBooterUnloadIfNeeded_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const NvU64 sysmemAddrOfSuspendResumeData) { + return pKernelGsp->__kgspExecuteBooterUnloadIfNeeded__(pGpu, pKernelGsp, sysmemAddrOfSuspendResumeData); } NV_STATUS kgspExecuteHsFalcon_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFlcnUcode, struct KernelFalcon *pKernelFlcn, NvU32 *pMailbox0, NvU32 *pMailbox1); @@ -828,16 +858,14 @@ static inline const BINDATA_ARCHIVE *kgspGetBinArchiveBooterUnloadUcode_DISPATCH return pKernelGsp->__kgspGetBinArchiveBooterUnloadUcode__(pKernelGsp); } -static inline NvU64 kgspGetWprHeapSize_5661b8(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - return 64 * 1024 * 1024; +static inline NvU64 kgspGetWprHeapSize_45a5e0(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return (64U << 20); } -static inline NvU64 kgspGetWprHeapSize_15390a(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - return 80 * 1024 * 1024; +static inline NvU64 kgspGetWprHeapSize_31541f(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return pGpu->bVgpuGspPluginOffloadEnabled ? (549U << 20) : (84U << 20); } -NvU64 kgspGetWprHeapSize_AD102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); - static inline NvU64 kgspGetWprHeapSize_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { return pKernelGsp->__kgspGetWprHeapSize__(pGpu, pKernelGsp); } @@ -882,30 +910,6 @@ static inline NV_STATUS kgspSetupGspFmcArgs_DISPATCH(struct OBJGPU *pGpu, struct return pKernelGsp->__kgspSetupGspFmcArgs__(pGpu, pKernelGsp, pGspFw); } -static inline void kgspStateDestroy_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate) { - pEngstate->__kgspStateDestroy__(pGpu, pEngstate); -} - -static inline void kgspFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate, void *pTunableState) { - pEngstate->__kgspFreeTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kgspCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kgspCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline NvBool kgspClearInterrupt_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pIntrService, IntrServiceClearInterruptArguments *pParams) { - return pIntrService->__kgspClearInterrupt__(pGpu, pIntrService, pParams); -} - -static inline NvBool kgspIsPresent_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate) { - return pEngstate->__kgspIsPresent__(pGpu, pEngstate); -} - -static inline NV_STATUS kgspReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate, void *pTunableState) { - return pEngstate->__kgspReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kgspStateLoad_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate, NvU32 arg0) { return pEngstate->__kgspStateLoad__(pGpu, pEngstate, arg0); } @@ -930,12 +934,12 @@ static inline NV_STATUS kgspStatePostUnload_DISPATCH(POBJGPU pGpu, struct Kernel return pEngstate->__kgspStatePostUnload__(pGpu, pEngstate, arg0); } -static inline NV_STATUS kgspStatePreUnload_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate, NvU32 arg0) { - return pEngstate->__kgspStatePreUnload__(pGpu, pEngstate, arg0); +static inline void kgspStateDestroy_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate) { + pEngstate->__kgspStateDestroy__(pGpu, pEngstate); } -static inline NV_STATUS kgspGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate, void *pTunableState) { - return pEngstate->__kgspGetTunableState__(pGpu, pEngstate, pTunableState); +static inline NV_STATUS kgspStatePreUnload_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate, NvU32 arg0) { + return pEngstate->__kgspStatePreUnload__(pGpu, pEngstate, arg0); } static inline NV_STATUS kgspStateInitUnlocked_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate) { @@ -954,16 +958,16 @@ static inline NV_STATUS kgspStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct K return pEngstate->__kgspStatePreInitUnlocked__(pGpu, pEngstate); } +static inline NvBool kgspClearInterrupt_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pIntrService, IntrServiceClearInterruptArguments *pParams) { + return pIntrService->__kgspClearInterrupt__(pGpu, pIntrService, pParams); +} + static inline NV_STATUS kgspStatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate, NvU32 arg0) { return pEngstate->__kgspStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS kgspAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate, void **ppTunableState) { - return pEngstate->__kgspAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kgspSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate, void *pTunableState) { - return pEngstate->__kgspSetTunableState__(pGpu, pEngstate, pTunableState); +static inline NvBool kgspIsPresent_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate) { + return pEngstate->__kgspIsPresent__(pGpu, pEngstate); } void kgspDestruct_IMPL(struct KernelGsp *pKernelGsp); @@ -990,6 +994,17 @@ static inline NV_STATUS kgspInitRm(struct OBJGPU *pGpu, struct KernelGsp *pKerne #define kgspInitRm(pGpu, pKernelGsp, pGspFw) kgspInitRm_IMPL(pGpu, pKernelGsp, pGspFw) #endif //__nvoc_kernel_gsp_h_disabled +NV_STATUS kgspCreateRadix3_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, MEMORY_DESCRIPTOR **ppMemdescRadix3, MEMORY_DESCRIPTOR *pMemdescData, const void *pData, NvU64 sizeOfData); + +#ifdef __nvoc_kernel_gsp_h_disabled +static inline NV_STATUS kgspCreateRadix3(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, MEMORY_DESCRIPTOR **ppMemdescRadix3, MEMORY_DESCRIPTOR *pMemdescData, const void *pData, NvU64 sizeOfData) { + NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_gsp_h_disabled +#define kgspCreateRadix3(pGpu, pKernelGsp, ppMemdescRadix3, pMemdescData, pData, sizeOfData) kgspCreateRadix3_IMPL(pGpu, pKernelGsp, ppMemdescRadix3, pMemdescData, pData, sizeOfData) +#endif //__nvoc_kernel_gsp_h_disabled + NV_STATUS kgspUnloadRm_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); #ifdef __nvoc_kernel_gsp_h_disabled diff --git a/src/nvidia/generated/g_kernel_head_nvoc.c b/src/nvidia/generated/g_kernel_head_nvoc.c index efb184b29..7ede9a947 100644 --- a/src/nvidia/generated/g_kernel_head_nvoc.c +++ b/src/nvidia/generated/g_kernel_head_nvoc.c @@ -184,13 +184,16 @@ NV_STATUS __nvoc_objCreate_KernelHead(KernelHead **ppThis, Dynamic *pParent, NvU KernelHead *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelHead)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelHead), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelHead)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelHead); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -210,11 +213,17 @@ NV_STATUS __nvoc_objCreate_KernelHead(KernelHead **ppThis, Dynamic *pParent, NvU if (status != NV_OK) goto __nvoc_objCreate_KernelHead_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelHead_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelHead)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.c b/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.c index e55fae9ee..7f6a2f662 100644 --- a/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.c +++ b/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.c @@ -124,13 +124,16 @@ NV_STATUS __nvoc_objCreate_KernelHostVgpuDeviceShr(KernelHostVgpuDeviceShr **ppT Object *pParentObj; KernelHostVgpuDeviceShr *pThis; - pThis = portMemAllocNonPaged(sizeof(KernelHostVgpuDeviceShr)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelHostVgpuDeviceShr), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelHostVgpuDeviceShr)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelHostVgpuDeviceShr); + pThis->__nvoc_base_RsShared.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -146,11 +149,17 @@ NV_STATUS __nvoc_objCreate_KernelHostVgpuDeviceShr(KernelHostVgpuDeviceShr **ppT if (status != NV_OK) goto __nvoc_objCreate_KernelHostVgpuDeviceShr_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelHostVgpuDeviceShr_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelHostVgpuDeviceShr)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -274,16 +283,16 @@ static NvBool __nvoc_thunk_GpuResource_kernelhostvgpudeviceapiShareCallback(stru return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_RsResource_kernelhostvgpudeviceapiMapTo(struct KernelHostVgpuDeviceApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_kernelhostvgpudeviceapiCheckMemInterUnmap(struct KernelHostVgpuDeviceApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RmResource.offset), bSubdeviceHandleProvided); } static NV_STATUS __nvoc_thunk_Notifier_kernelhostvgpudeviceapiGetOrAllocNotifShare(struct KernelHostVgpuDeviceApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelHostVgpuDeviceApi_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); } -static NV_STATUS __nvoc_thunk_RmResource_kernelhostvgpudeviceapiCheckMemInterUnmap(struct KernelHostVgpuDeviceApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RmResource.offset), bSubdeviceHandleProvided); +static NV_STATUS __nvoc_thunk_RsResource_kernelhostvgpudeviceapiMapTo(struct KernelHostVgpuDeviceApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_GpuResource_kernelhostvgpudeviceapiGetMapAddrSpace(struct KernelHostVgpuDeviceApi *pGpuResource, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -354,6 +363,10 @@ static NV_STATUS __nvoc_thunk_Notifier_kernelhostvgpudeviceapiUnregisterEvent(st return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelHostVgpuDeviceApi_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_kernelhostvgpudeviceapiControlSerialization_Prologue(struct KernelHostVgpuDeviceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RmResource.offset), pCallContext, pParams); +} + static void __nvoc_thunk_RsResource_kernelhostvgpudeviceapiPreDestruct(struct KernelHostVgpuDeviceApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RsResource.offset)); } @@ -362,6 +375,10 @@ static NV_STATUS __nvoc_thunk_RsResource_kernelhostvgpudeviceapiIsDuplicate(stru return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_kernelhostvgpudeviceapiControlSerialization_Epilogue(struct KernelHostVgpuDeviceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_kernelhostvgpudeviceapiGetNotificationListPtr(struct KernelHostVgpuDeviceApi *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelHostVgpuDeviceApi_Notifier.offset)); } @@ -517,6 +534,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelHo /*pClassInfo=*/ &(__nvoc_class_def_KernelHostVgpuDeviceApi.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "kernelhostvgpudeviceapiCtrlCmdSetGuestId" +#endif + }, + { /* [9] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa084010au, + /*paramSize=*/ sizeof(NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_KernelHostVgpuDeviceApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges" #endif }, @@ -524,7 +556,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelHo const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelHostVgpuDeviceApi = { - /*numEntries=*/ 9, + /*numEntries=*/ 10, /*pExportEntries=*/ __nvoc_exported_method_def_KernelHostVgpuDeviceApi }; @@ -606,15 +638,19 @@ static void __nvoc_init_funcTable_KernelHostVgpuDeviceApi_1(KernelHostVgpuDevice pThis->__kernelhostvgpudeviceapiCtrlCmdSetGuestId__ = &kernelhostvgpudeviceapiCtrlCmdSetGuestId_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges__ = &kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges_IMPL; +#endif + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__resCanCopy__ = &__nvoc_thunk_KernelHostVgpuDeviceApi_resCanCopy; pThis->__kernelhostvgpudeviceapiShareCallback__ = &__nvoc_thunk_GpuResource_kernelhostvgpudeviceapiShareCallback; - pThis->__kernelhostvgpudeviceapiMapTo__ = &__nvoc_thunk_RsResource_kernelhostvgpudeviceapiMapTo; + pThis->__kernelhostvgpudeviceapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_kernelhostvgpudeviceapiCheckMemInterUnmap; pThis->__kernelhostvgpudeviceapiGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_kernelhostvgpudeviceapiGetOrAllocNotifShare; - pThis->__kernelhostvgpudeviceapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_kernelhostvgpudeviceapiCheckMemInterUnmap; + pThis->__kernelhostvgpudeviceapiMapTo__ = &__nvoc_thunk_RsResource_kernelhostvgpudeviceapiMapTo; pThis->__kernelhostvgpudeviceapiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_kernelhostvgpudeviceapiGetMapAddrSpace; @@ -650,10 +686,14 @@ static void __nvoc_init_funcTable_KernelHostVgpuDeviceApi_1(KernelHostVgpuDevice pThis->__kernelhostvgpudeviceapiUnregisterEvent__ = &__nvoc_thunk_Notifier_kernelhostvgpudeviceapiUnregisterEvent; + pThis->__kernelhostvgpudeviceapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_kernelhostvgpudeviceapiControlSerialization_Prologue; + pThis->__kernelhostvgpudeviceapiPreDestruct__ = &__nvoc_thunk_RsResource_kernelhostvgpudeviceapiPreDestruct; pThis->__kernelhostvgpudeviceapiIsDuplicate__ = &__nvoc_thunk_RsResource_kernelhostvgpudeviceapiIsDuplicate; + pThis->__kernelhostvgpudeviceapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_kernelhostvgpudeviceapiControlSerialization_Epilogue; + pThis->__kernelhostvgpudeviceapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_kernelhostvgpudeviceapiGetNotificationListPtr; pThis->__kernelhostvgpudeviceapiGetNotificationShare__ = &__nvoc_thunk_Notifier_kernelhostvgpudeviceapiGetNotificationShare; @@ -688,13 +728,16 @@ NV_STATUS __nvoc_objCreate_KernelHostVgpuDeviceApi(KernelHostVgpuDeviceApi **ppT Object *pParentObj; KernelHostVgpuDeviceApi *pThis; - pThis = portMemAllocNonPaged(sizeof(KernelHostVgpuDeviceApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelHostVgpuDeviceApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelHostVgpuDeviceApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelHostVgpuDeviceApi); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -710,11 +753,17 @@ NV_STATUS __nvoc_objCreate_KernelHostVgpuDeviceApi(KernelHostVgpuDeviceApi **ppT if (status != NV_OK) goto __nvoc_objCreate_KernelHostVgpuDeviceApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelHostVgpuDeviceApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelHostVgpuDeviceApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h b/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h index b78e32357..f27b6ff19 100644 --- a/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h +++ b/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h @@ -121,10 +121,11 @@ struct KernelHostVgpuDeviceApi { NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdEventSetNotification__)(struct KernelHostVgpuDeviceApi *, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS *); NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdSetSriovState__)(struct KernelHostVgpuDeviceApi *, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS *); NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdSetGuestId__)(struct KernelHostVgpuDeviceApi *, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS *); + NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges__)(struct KernelHostVgpuDeviceApi *, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS *); NvBool (*__kernelhostvgpudeviceapiShareCallback__)(struct KernelHostVgpuDeviceApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__kernelhostvgpudeviceapiMapTo__)(struct KernelHostVgpuDeviceApi *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__kernelhostvgpudeviceapiGetOrAllocNotifShare__)(struct KernelHostVgpuDeviceApi *, NvHandle, NvHandle, struct NotifShare **); NV_STATUS (*__kernelhostvgpudeviceapiCheckMemInterUnmap__)(struct KernelHostVgpuDeviceApi *, NvBool); + NV_STATUS (*__kernelhostvgpudeviceapiGetOrAllocNotifShare__)(struct KernelHostVgpuDeviceApi *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__kernelhostvgpudeviceapiMapTo__)(struct KernelHostVgpuDeviceApi *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__kernelhostvgpudeviceapiGetMapAddrSpace__)(struct KernelHostVgpuDeviceApi *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); void (*__kernelhostvgpudeviceapiSetNotificationShare__)(struct KernelHostVgpuDeviceApi *, struct NotifShare *); NvU32 (*__kernelhostvgpudeviceapiGetRefCount__)(struct KernelHostVgpuDeviceApi *); @@ -142,8 +143,10 @@ struct KernelHostVgpuDeviceApi { NV_STATUS (*__kernelhostvgpudeviceapiGetMemoryMappingDescriptor__)(struct KernelHostVgpuDeviceApi *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__kernelhostvgpudeviceapiControlFilter__)(struct KernelHostVgpuDeviceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kernelhostvgpudeviceapiUnregisterEvent__)(struct KernelHostVgpuDeviceApi *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__kernelhostvgpudeviceapiControlSerialization_Prologue__)(struct KernelHostVgpuDeviceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__kernelhostvgpudeviceapiPreDestruct__)(struct KernelHostVgpuDeviceApi *); NV_STATUS (*__kernelhostvgpudeviceapiIsDuplicate__)(struct KernelHostVgpuDeviceApi *, NvHandle, NvBool *); + void (*__kernelhostvgpudeviceapiControlSerialization_Epilogue__)(struct KernelHostVgpuDeviceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__kernelhostvgpudeviceapiGetNotificationListPtr__)(struct KernelHostVgpuDeviceApi *); struct NotifShare *(*__kernelhostvgpudeviceapiGetNotificationShare__)(struct KernelHostVgpuDeviceApi *); NV_STATUS (*__kernelhostvgpudeviceapiMap__)(struct KernelHostVgpuDeviceApi *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -190,10 +193,11 @@ NV_STATUS __nvoc_objCreate_KernelHostVgpuDeviceApi(KernelHostVgpuDeviceApi**, Dy #define kernelhostvgpudeviceapiCtrlCmdEventSetNotification(pKernelHostVgpuDeviceApi, pSetEventParams) kernelhostvgpudeviceapiCtrlCmdEventSetNotification_DISPATCH(pKernelHostVgpuDeviceApi, pSetEventParams) #define kernelhostvgpudeviceapiCtrlCmdSetSriovState(pKernelHostVgpuDeviceApi, pParams) kernelhostvgpudeviceapiCtrlCmdSetSriovState_DISPATCH(pKernelHostVgpuDeviceApi, pParams) #define kernelhostvgpudeviceapiCtrlCmdSetGuestId(pKernelHostVgpuDeviceApi, pParams) kernelhostvgpudeviceapiCtrlCmdSetGuestId_DISPATCH(pKernelHostVgpuDeviceApi, pParams) +#define kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges(pKernelHostVgpuDeviceApi, pParams) kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges_DISPATCH(pKernelHostVgpuDeviceApi, pParams) #define kernelhostvgpudeviceapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) kernelhostvgpudeviceapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define kernelhostvgpudeviceapiMapTo(pResource, pParams) kernelhostvgpudeviceapiMapTo_DISPATCH(pResource, pParams) -#define kernelhostvgpudeviceapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) kernelhostvgpudeviceapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) #define kernelhostvgpudeviceapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) kernelhostvgpudeviceapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define kernelhostvgpudeviceapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) kernelhostvgpudeviceapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define kernelhostvgpudeviceapiMapTo(pResource, pParams) kernelhostvgpudeviceapiMapTo_DISPATCH(pResource, pParams) #define kernelhostvgpudeviceapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) kernelhostvgpudeviceapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) #define kernelhostvgpudeviceapiSetNotificationShare(pNotifier, pNotifShare) kernelhostvgpudeviceapiSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define kernelhostvgpudeviceapiGetRefCount(pResource) kernelhostvgpudeviceapiGetRefCount_DISPATCH(pResource) @@ -211,8 +215,10 @@ NV_STATUS __nvoc_objCreate_KernelHostVgpuDeviceApi(KernelHostVgpuDeviceApi**, Dy #define kernelhostvgpudeviceapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) kernelhostvgpudeviceapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define kernelhostvgpudeviceapiControlFilter(pResource, pCallContext, pParams) kernelhostvgpudeviceapiControlFilter_DISPATCH(pResource, pCallContext, pParams) #define kernelhostvgpudeviceapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) kernelhostvgpudeviceapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define kernelhostvgpudeviceapiControlSerialization_Prologue(pResource, pCallContext, pParams) kernelhostvgpudeviceapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define kernelhostvgpudeviceapiPreDestruct(pResource) kernelhostvgpudeviceapiPreDestruct_DISPATCH(pResource) #define kernelhostvgpudeviceapiIsDuplicate(pResource, hMemory, pDuplicate) kernelhostvgpudeviceapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define kernelhostvgpudeviceapiControlSerialization_Epilogue(pResource, pCallContext, pParams) kernelhostvgpudeviceapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define kernelhostvgpudeviceapiGetNotificationListPtr(pNotifier) kernelhostvgpudeviceapiGetNotificationListPtr_DISPATCH(pNotifier) #define kernelhostvgpudeviceapiGetNotificationShare(pNotifier) kernelhostvgpudeviceapiGetNotificationShare_DISPATCH(pNotifier) #define kernelhostvgpudeviceapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) kernelhostvgpudeviceapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -277,20 +283,26 @@ static inline NV_STATUS kernelhostvgpudeviceapiCtrlCmdSetGuestId_DISPATCH(struct return pKernelHostVgpuDeviceApi->__kernelhostvgpudeviceapiCtrlCmdSetGuestId__(pKernelHostVgpuDeviceApi, pParams); } +NV_STATUS kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges_IMPL(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS *pParams); + +static inline NV_STATUS kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges_DISPATCH(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS *pParams) { + return pKernelHostVgpuDeviceApi->__kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges__(pKernelHostVgpuDeviceApi, pParams); +} + static inline NvBool kernelhostvgpudeviceapiShareCallback_DISPATCH(struct KernelHostVgpuDeviceApi *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__kernelhostvgpudeviceapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS kernelhostvgpudeviceapiMapTo_DISPATCH(struct KernelHostVgpuDeviceApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__kernelhostvgpudeviceapiMapTo__(pResource, pParams); +static inline NV_STATUS kernelhostvgpudeviceapiCheckMemInterUnmap_DISPATCH(struct KernelHostVgpuDeviceApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__kernelhostvgpudeviceapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } static inline NV_STATUS kernelhostvgpudeviceapiGetOrAllocNotifShare_DISPATCH(struct KernelHostVgpuDeviceApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return pNotifier->__kernelhostvgpudeviceapiGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); } -static inline NV_STATUS kernelhostvgpudeviceapiCheckMemInterUnmap_DISPATCH(struct KernelHostVgpuDeviceApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__kernelhostvgpudeviceapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline NV_STATUS kernelhostvgpudeviceapiMapTo_DISPATCH(struct KernelHostVgpuDeviceApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__kernelhostvgpudeviceapiMapTo__(pResource, pParams); } static inline NV_STATUS kernelhostvgpudeviceapiGetMapAddrSpace_DISPATCH(struct KernelHostVgpuDeviceApi *pGpuResource, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -361,6 +373,10 @@ static inline NV_STATUS kernelhostvgpudeviceapiUnregisterEvent_DISPATCH(struct K return pNotifier->__kernelhostvgpudeviceapiUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS kernelhostvgpudeviceapiControlSerialization_Prologue_DISPATCH(struct KernelHostVgpuDeviceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__kernelhostvgpudeviceapiControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline void kernelhostvgpudeviceapiPreDestruct_DISPATCH(struct KernelHostVgpuDeviceApi *pResource) { pResource->__kernelhostvgpudeviceapiPreDestruct__(pResource); } @@ -369,6 +385,10 @@ static inline NV_STATUS kernelhostvgpudeviceapiIsDuplicate_DISPATCH(struct Kerne return pResource->__kernelhostvgpudeviceapiIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void kernelhostvgpudeviceapiControlSerialization_Epilogue_DISPATCH(struct KernelHostVgpuDeviceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__kernelhostvgpudeviceapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *kernelhostvgpudeviceapiGetNotificationListPtr_DISPATCH(struct KernelHostVgpuDeviceApi *pNotifier) { return pNotifier->__kernelhostvgpudeviceapiGetNotificationListPtr__(pNotifier); } diff --git a/src/nvidia/generated/g_kernel_ioctrl_nvoc.c b/src/nvidia/generated/g_kernel_ioctrl_nvoc.c index 4f6bad131..479c61881 100644 --- a/src/nvidia/generated/g_kernel_ioctrl_nvoc.c +++ b/src/nvidia/generated/g_kernel_ioctrl_nvoc.c @@ -70,10 +70,6 @@ static NV_STATUS __nvoc_thunk_KernelIoctrl_engstateConstructEngine(struct OBJGPU return kioctrlConstructEngine(arg0, (struct KernelIoctrl *)(((unsigned char *)arg1) - __nvoc_rtti_KernelIoctrl_OBJENGSTATE.offset), arg2); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kioctrlReconcileTunableState(POBJGPU pGpu, struct KernelIoctrl *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelIoctrl_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kioctrlStateLoad(POBJGPU pGpu, struct KernelIoctrl *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelIoctrl_OBJENGSTATE.offset), arg0); } @@ -118,30 +114,10 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_kioctrlStatePreInitUnlocked(POBJGPU pG return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelIoctrl_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kioctrlGetTunableState(POBJGPU pGpu, struct KernelIoctrl *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelIoctrl_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kioctrlCompareTunableState(POBJGPU pGpu, struct KernelIoctrl *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelIoctrl_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kioctrlFreeTunableState(POBJGPU pGpu, struct KernelIoctrl *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelIoctrl_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kioctrlStatePostLoad(POBJGPU pGpu, struct KernelIoctrl *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelIoctrl_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kioctrlAllocTunableState(POBJGPU pGpu, struct KernelIoctrl *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelIoctrl_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kioctrlSetTunableState(POBJGPU pGpu, struct KernelIoctrl *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelIoctrl_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_kioctrlIsPresent(POBJGPU pGpu, struct KernelIoctrl *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelIoctrl_OBJENGSTATE.offset)); } @@ -244,8 +220,6 @@ static void __nvoc_init_funcTable_KernelIoctrl_1(KernelIoctrl *pThis, RmHalspecO pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelIoctrl_engstateConstructEngine; - pThis->__kioctrlReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kioctrlReconcileTunableState; - pThis->__kioctrlStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kioctrlStateLoad; pThis->__kioctrlStateUnload__ = &__nvoc_thunk_OBJENGSTATE_kioctrlStateUnload; @@ -268,18 +242,8 @@ static void __nvoc_init_funcTable_KernelIoctrl_1(KernelIoctrl *pThis, RmHalspecO pThis->__kioctrlStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kioctrlStatePreInitUnlocked; - pThis->__kioctrlGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kioctrlGetTunableState; - - pThis->__kioctrlCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kioctrlCompareTunableState; - - pThis->__kioctrlFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kioctrlFreeTunableState; - pThis->__kioctrlStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kioctrlStatePostLoad; - pThis->__kioctrlAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kioctrlAllocTunableState; - - pThis->__kioctrlSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kioctrlSetTunableState; - pThis->__kioctrlIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kioctrlIsPresent; } @@ -302,13 +266,16 @@ NV_STATUS __nvoc_objCreate_KernelIoctrl(KernelIoctrl **ppThis, Dynamic *pParent, KernelIoctrl *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelIoctrl)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelIoctrl), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelIoctrl)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelIoctrl); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -328,11 +295,17 @@ NV_STATUS __nvoc_objCreate_KernelIoctrl(KernelIoctrl **ppThis, Dynamic *pParent, if (status != NV_OK) goto __nvoc_objCreate_KernelIoctrl_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelIoctrl_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelIoctrl)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_ioctrl_nvoc.h b/src/nvidia/generated/g_kernel_ioctrl_nvoc.h index fb0043b21..f133e3be1 100644 --- a/src/nvidia/generated/g_kernel_ioctrl_nvoc.h +++ b/src/nvidia/generated/g_kernel_ioctrl_nvoc.h @@ -65,7 +65,6 @@ struct KernelIoctrl { NV_STATUS (*__kioctrlConstructEngine__)(struct OBJGPU *, struct KernelIoctrl *, NvU32); NvBool (*__kioctrlGetMinionEnableDefault__)(struct OBJGPU *, struct KernelIoctrl *); NV_STATUS (*__kioctrlMinionConstruct__)(struct OBJGPU *, struct KernelIoctrl *); - NV_STATUS (*__kioctrlReconcileTunableState__)(POBJGPU, struct KernelIoctrl *, void *); NV_STATUS (*__kioctrlStateLoad__)(POBJGPU, struct KernelIoctrl *, NvU32); NV_STATUS (*__kioctrlStateUnload__)(POBJGPU, struct KernelIoctrl *, NvU32); NV_STATUS (*__kioctrlStateInitLocked__)(POBJGPU, struct KernelIoctrl *); @@ -77,12 +76,7 @@ struct KernelIoctrl { void (*__kioctrlInitMissing__)(POBJGPU, struct KernelIoctrl *); NV_STATUS (*__kioctrlStatePreInitLocked__)(POBJGPU, struct KernelIoctrl *); NV_STATUS (*__kioctrlStatePreInitUnlocked__)(POBJGPU, struct KernelIoctrl *); - NV_STATUS (*__kioctrlGetTunableState__)(POBJGPU, struct KernelIoctrl *, void *); - NV_STATUS (*__kioctrlCompareTunableState__)(POBJGPU, struct KernelIoctrl *, void *, void *); - void (*__kioctrlFreeTunableState__)(POBJGPU, struct KernelIoctrl *, void *); NV_STATUS (*__kioctrlStatePostLoad__)(POBJGPU, struct KernelIoctrl *, NvU32); - NV_STATUS (*__kioctrlAllocTunableState__)(POBJGPU, struct KernelIoctrl *, void **); - NV_STATUS (*__kioctrlSetTunableState__)(POBJGPU, struct KernelIoctrl *, void *); NvBool (*__kioctrlIsPresent__)(POBJGPU, struct KernelIoctrl *); NvBool PDB_PROP_KIOCTRL_MINION_AVAILABLE; NvBool PDB_PROP_KIOCTRL_MINION_FORCE_BOOT; @@ -137,7 +131,6 @@ NV_STATUS __nvoc_objCreate_KernelIoctrl(KernelIoctrl**, Dynamic*, NvU32); #define kioctrlGetMinionEnableDefault_HAL(pGpu, pKernelIoctrl) kioctrlGetMinionEnableDefault_DISPATCH(pGpu, pKernelIoctrl) #define kioctrlMinionConstruct(pGpu, pKernelIoctrl) kioctrlMinionConstruct_DISPATCH(pGpu, pKernelIoctrl) #define kioctrlMinionConstruct_HAL(pGpu, pKernelIoctrl) kioctrlMinionConstruct_DISPATCH(pGpu, pKernelIoctrl) -#define kioctrlReconcileTunableState(pGpu, pEngstate, pTunableState) kioctrlReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kioctrlStateLoad(pGpu, pEngstate, arg0) kioctrlStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kioctrlStateUnload(pGpu, pEngstate, arg0) kioctrlStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define kioctrlStateInitLocked(pGpu, pEngstate) kioctrlStateInitLocked_DISPATCH(pGpu, pEngstate) @@ -149,12 +142,7 @@ NV_STATUS __nvoc_objCreate_KernelIoctrl(KernelIoctrl**, Dynamic*, NvU32); #define kioctrlInitMissing(pGpu, pEngstate) kioctrlInitMissing_DISPATCH(pGpu, pEngstate) #define kioctrlStatePreInitLocked(pGpu, pEngstate) kioctrlStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kioctrlStatePreInitUnlocked(pGpu, pEngstate) kioctrlStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kioctrlGetTunableState(pGpu, pEngstate, pTunableState) kioctrlGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kioctrlCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kioctrlCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kioctrlFreeTunableState(pGpu, pEngstate, pTunableState) kioctrlFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kioctrlStatePostLoad(pGpu, pEngstate, arg0) kioctrlStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define kioctrlAllocTunableState(pGpu, pEngstate, ppTunableState) kioctrlAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kioctrlSetTunableState(pGpu, pEngstate, pTunableState) kioctrlSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kioctrlIsPresent(pGpu, pEngstate) kioctrlIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS kioctrlConstructEngine_IMPL(struct OBJGPU *arg0, struct KernelIoctrl *arg1, NvU32 arg2); @@ -182,10 +170,6 @@ static inline NV_STATUS kioctrlMinionConstruct_DISPATCH(struct OBJGPU *pGpu, str return pKernelIoctrl->__kioctrlMinionConstruct__(pGpu, pKernelIoctrl); } -static inline NV_STATUS kioctrlReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelIoctrl *pEngstate, void *pTunableState) { - return pEngstate->__kioctrlReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kioctrlStateLoad_DISPATCH(POBJGPU pGpu, struct KernelIoctrl *pEngstate, NvU32 arg0) { return pEngstate->__kioctrlStateLoad__(pGpu, pEngstate, arg0); } @@ -230,30 +214,10 @@ static inline NV_STATUS kioctrlStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struc return pEngstate->__kioctrlStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kioctrlGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelIoctrl *pEngstate, void *pTunableState) { - return pEngstate->__kioctrlGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kioctrlCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelIoctrl *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kioctrlCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kioctrlFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelIoctrl *pEngstate, void *pTunableState) { - pEngstate->__kioctrlFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kioctrlStatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelIoctrl *pEngstate, NvU32 arg0) { return pEngstate->__kioctrlStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS kioctrlAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelIoctrl *pEngstate, void **ppTunableState) { - return pEngstate->__kioctrlAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kioctrlSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelIoctrl *pEngstate, void *pTunableState) { - return pEngstate->__kioctrlSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kioctrlIsPresent_DISPATCH(POBJGPU pGpu, struct KernelIoctrl *pEngstate) { return pEngstate->__kioctrlIsPresent__(pGpu, pEngstate); } diff --git a/src/nvidia/generated/g_kernel_mc_nvoc.c b/src/nvidia/generated/g_kernel_mc_nvoc.c index 2de971eb9..e1053aa9f 100644 --- a/src/nvidia/generated/g_kernel_mc_nvoc.c +++ b/src/nvidia/generated/g_kernel_mc_nvoc.c @@ -74,10 +74,6 @@ static NV_STATUS __nvoc_thunk_KernelMc_engstateStateLoad(struct OBJGPU *pGpu, st return kmcStateLoad(pGpu, (struct KernelMc *)(((unsigned char *)pKernelMc) - __nvoc_rtti_KernelMc_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmcReconcileTunableState(POBJGPU pGpu, struct KernelMc *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMc_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmcStateUnload(POBJGPU pGpu, struct KernelMc *pEngstate, NvU32 arg0) { return engstateStateUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMc_OBJENGSTATE.offset), arg0); } @@ -114,30 +110,10 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmcStatePreInitUnlocked(POBJGPU pGpu, return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMc_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmcGetTunableState(POBJGPU pGpu, struct KernelMc *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMc_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmcCompareTunableState(POBJGPU pGpu, struct KernelMc *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMc_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kmcFreeTunableState(POBJGPU pGpu, struct KernelMc *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMc_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmcStatePostLoad(POBJGPU pGpu, struct KernelMc *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMc_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmcAllocTunableState(POBJGPU pGpu, struct KernelMc *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMc_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmcSetTunableState(POBJGPU pGpu, struct KernelMc *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMc_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmcConstructEngine(POBJGPU pGpu, struct KernelMc *pEngstate, ENGDESCRIPTOR arg0) { return engstateConstructEngine(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMc_OBJENGSTATE.offset), arg0); } @@ -217,8 +193,6 @@ static void __nvoc_init_funcTable_KernelMc_1(KernelMc *pThis, RmHalspecOwner *pR pThis->__nvoc_base_OBJENGSTATE.__engstateStateLoad__ = &__nvoc_thunk_KernelMc_engstateStateLoad; - pThis->__kmcReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmcReconcileTunableState; - pThis->__kmcStateUnload__ = &__nvoc_thunk_OBJENGSTATE_kmcStateUnload; pThis->__kmcStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_kmcStatePreLoad; @@ -237,18 +211,8 @@ static void __nvoc_init_funcTable_KernelMc_1(KernelMc *pThis, RmHalspecOwner *pR pThis->__kmcStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kmcStatePreInitUnlocked; - pThis->__kmcGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmcGetTunableState; - - pThis->__kmcCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmcCompareTunableState; - - pThis->__kmcFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmcFreeTunableState; - pThis->__kmcStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kmcStatePostLoad; - pThis->__kmcAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmcAllocTunableState; - - pThis->__kmcSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmcSetTunableState; - pThis->__kmcConstructEngine__ = &__nvoc_thunk_OBJENGSTATE_kmcConstructEngine; pThis->__kmcIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kmcIsPresent; @@ -273,13 +237,16 @@ NV_STATUS __nvoc_objCreate_KernelMc(KernelMc **ppThis, Dynamic *pParent, NvU32 c KernelMc *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelMc)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelMc), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelMc)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelMc); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -299,11 +266,17 @@ NV_STATUS __nvoc_objCreate_KernelMc(KernelMc **ppThis, Dynamic *pParent, NvU32 c if (status != NV_OK) goto __nvoc_objCreate_KernelMc_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelMc_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelMc)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_mc_nvoc.h b/src/nvidia/generated/g_kernel_mc_nvoc.h index f248e5565..7961b3f29 100644 --- a/src/nvidia/generated/g_kernel_mc_nvoc.h +++ b/src/nvidia/generated/g_kernel_mc_nvoc.h @@ -66,7 +66,6 @@ struct KernelMc { NV_STATUS (*__kmcStateLoad__)(struct OBJGPU *, struct KernelMc *, NvU32); NV_STATUS (*__kmcWritePmcEnableReg__)(struct OBJGPU *, struct KernelMc *, NvU32, NvBool, NvBool); NvU32 (*__kmcReadPmcEnableReg__)(struct OBJGPU *, struct KernelMc *, NvBool); - NV_STATUS (*__kmcReconcileTunableState__)(POBJGPU, struct KernelMc *, void *); NV_STATUS (*__kmcStateUnload__)(POBJGPU, struct KernelMc *, NvU32); NV_STATUS (*__kmcStatePreLoad__)(POBJGPU, struct KernelMc *, NvU32); NV_STATUS (*__kmcStatePostUnload__)(POBJGPU, struct KernelMc *, NvU32); @@ -76,12 +75,7 @@ struct KernelMc { void (*__kmcInitMissing__)(POBJGPU, struct KernelMc *); NV_STATUS (*__kmcStatePreInitLocked__)(POBJGPU, struct KernelMc *); NV_STATUS (*__kmcStatePreInitUnlocked__)(POBJGPU, struct KernelMc *); - NV_STATUS (*__kmcGetTunableState__)(POBJGPU, struct KernelMc *, void *); - NV_STATUS (*__kmcCompareTunableState__)(POBJGPU, struct KernelMc *, void *, void *); - void (*__kmcFreeTunableState__)(POBJGPU, struct KernelMc *, void *); NV_STATUS (*__kmcStatePostLoad__)(POBJGPU, struct KernelMc *, NvU32); - NV_STATUS (*__kmcAllocTunableState__)(POBJGPU, struct KernelMc *, void **); - NV_STATUS (*__kmcSetTunableState__)(POBJGPU, struct KernelMc *, void *); NV_STATUS (*__kmcConstructEngine__)(POBJGPU, struct KernelMc *, ENGDESCRIPTOR); NvBool (*__kmcIsPresent__)(POBJGPU, struct KernelMc *); LATENCY_TIMER_CONTROL LatencyTimerControl; @@ -123,7 +117,6 @@ NV_STATUS __nvoc_objCreate_KernelMc(KernelMc**, Dynamic*, NvU32); #define kmcWritePmcEnableReg_HAL(pGpu, pKernelMc, arg0, arg1, arg2) kmcWritePmcEnableReg_DISPATCH(pGpu, pKernelMc, arg0, arg1, arg2) #define kmcReadPmcEnableReg(pGpu, pKernelMc, arg0) kmcReadPmcEnableReg_DISPATCH(pGpu, pKernelMc, arg0) #define kmcReadPmcEnableReg_HAL(pGpu, pKernelMc, arg0) kmcReadPmcEnableReg_DISPATCH(pGpu, pKernelMc, arg0) -#define kmcReconcileTunableState(pGpu, pEngstate, pTunableState) kmcReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kmcStateUnload(pGpu, pEngstate, arg0) kmcStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define kmcStatePreLoad(pGpu, pEngstate, arg0) kmcStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kmcStatePostUnload(pGpu, pEngstate, arg0) kmcStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) @@ -133,12 +126,7 @@ NV_STATUS __nvoc_objCreate_KernelMc(KernelMc**, Dynamic*, NvU32); #define kmcInitMissing(pGpu, pEngstate) kmcInitMissing_DISPATCH(pGpu, pEngstate) #define kmcStatePreInitLocked(pGpu, pEngstate) kmcStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kmcStatePreInitUnlocked(pGpu, pEngstate) kmcStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kmcGetTunableState(pGpu, pEngstate, pTunableState) kmcGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kmcCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kmcCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kmcFreeTunableState(pGpu, pEngstate, pTunableState) kmcFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kmcStatePostLoad(pGpu, pEngstate, arg0) kmcStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define kmcAllocTunableState(pGpu, pEngstate, ppTunableState) kmcAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kmcSetTunableState(pGpu, pEngstate, pTunableState) kmcSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kmcConstructEngine(pGpu, pEngstate, arg0) kmcConstructEngine_DISPATCH(pGpu, pEngstate, arg0) #define kmcIsPresent(pGpu, pEngstate) kmcIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS kmcPrepareForXVEReset_GK104(struct OBJGPU *pGpu, struct KernelMc *pKernelMc); @@ -197,10 +185,6 @@ static inline NvU32 kmcReadPmcEnableReg_DISPATCH(struct OBJGPU *pGpu, struct Ker return pKernelMc->__kmcReadPmcEnableReg__(pGpu, pKernelMc, arg0); } -static inline NV_STATUS kmcReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelMc *pEngstate, void *pTunableState) { - return pEngstate->__kmcReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kmcStateUnload_DISPATCH(POBJGPU pGpu, struct KernelMc *pEngstate, NvU32 arg0) { return pEngstate->__kmcStateUnload__(pGpu, pEngstate, arg0); } @@ -237,30 +221,10 @@ static inline NV_STATUS kmcStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct Ke return pEngstate->__kmcStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kmcGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelMc *pEngstate, void *pTunableState) { - return pEngstate->__kmcGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kmcCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelMc *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kmcCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kmcFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelMc *pEngstate, void *pTunableState) { - pEngstate->__kmcFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kmcStatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelMc *pEngstate, NvU32 arg0) { return pEngstate->__kmcStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS kmcAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelMc *pEngstate, void **ppTunableState) { - return pEngstate->__kmcAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kmcSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelMc *pEngstate, void *pTunableState) { - return pEngstate->__kmcSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kmcConstructEngine_DISPATCH(POBJGPU pGpu, struct KernelMc *pEngstate, ENGDESCRIPTOR arg0) { return pEngstate->__kmcConstructEngine__(pGpu, pEngstate, arg0); } diff --git a/src/nvidia/generated/g_kernel_mig_manager_nvoc.c b/src/nvidia/generated/g_kernel_mig_manager_nvoc.c index 5d0ae8916..e18880a03 100644 --- a/src/nvidia/generated/g_kernel_mig_manager_nvoc.c +++ b/src/nvidia/generated/g_kernel_mig_manager_nvoc.c @@ -78,10 +78,6 @@ static NV_STATUS __nvoc_thunk_KernelMIGManager_engstateStateUnload(OBJGPU *arg0, return kmigmgrStateUnload(arg0, (struct KernelMIGManager *)(((unsigned char *)arg1) - __nvoc_rtti_KernelMIGManager_OBJENGSTATE.offset), flags); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmigmgrReconcileTunableState(POBJGPU pGpu, struct KernelMIGManager *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMIGManager_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmigmgrStateLoad(POBJGPU pGpu, struct KernelMIGManager *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMIGManager_OBJENGSTATE.offset), arg0); } @@ -118,30 +114,10 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmigmgrStatePreInitUnlocked(POBJGPU pG return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMIGManager_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmigmgrGetTunableState(POBJGPU pGpu, struct KernelMIGManager *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMIGManager_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmigmgrCompareTunableState(POBJGPU pGpu, struct KernelMIGManager *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMIGManager_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_kmigmgrFreeTunableState(POBJGPU pGpu, struct KernelMIGManager *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMIGManager_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmigmgrStatePostLoad(POBJGPU pGpu, struct KernelMIGManager *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMIGManager_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmigmgrAllocTunableState(POBJGPU pGpu, struct KernelMIGManager *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMIGManager_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmigmgrSetTunableState(POBJGPU pGpu, struct KernelMIGManager *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMIGManager_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_kmigmgrIsPresent(POBJGPU pGpu, struct KernelMIGManager *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMIGManager_OBJENGSTATE.offset)); } @@ -297,8 +273,6 @@ static void __nvoc_init_funcTable_KernelMIGManager_1(KernelMIGManager *pThis, Rm pThis->__nvoc_base_OBJENGSTATE.__engstateStateUnload__ = &__nvoc_thunk_KernelMIGManager_engstateStateUnload; - pThis->__kmigmgrReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmigmgrReconcileTunableState; - pThis->__kmigmgrStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kmigmgrStateLoad; pThis->__kmigmgrStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_kmigmgrStatePreLoad; @@ -317,18 +291,8 @@ static void __nvoc_init_funcTable_KernelMIGManager_1(KernelMIGManager *pThis, Rm pThis->__kmigmgrStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kmigmgrStatePreInitUnlocked; - pThis->__kmigmgrGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmigmgrGetTunableState; - - pThis->__kmigmgrCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmigmgrCompareTunableState; - - pThis->__kmigmgrFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmigmgrFreeTunableState; - pThis->__kmigmgrStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kmigmgrStatePostLoad; - pThis->__kmigmgrAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmigmgrAllocTunableState; - - pThis->__kmigmgrSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kmigmgrSetTunableState; - pThis->__kmigmgrIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kmigmgrIsPresent; } @@ -351,13 +315,16 @@ NV_STATUS __nvoc_objCreate_KernelMIGManager(KernelMIGManager **ppThis, Dynamic * KernelMIGManager *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelMIGManager)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelMIGManager), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelMIGManager)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelMIGManager); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -377,11 +344,17 @@ NV_STATUS __nvoc_objCreate_KernelMIGManager(KernelMIGManager **ppThis, Dynamic * if (status != NV_OK) goto __nvoc_objCreate_KernelMIGManager_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelMIGManager_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelMIGManager)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_mig_manager_nvoc.h b/src/nvidia/generated/g_kernel_mig_manager_nvoc.h index 46cf1d165..a4aa473b6 100644 --- a/src/nvidia/generated/g_kernel_mig_manager_nvoc.h +++ b/src/nvidia/generated/g_kernel_mig_manager_nvoc.h @@ -124,6 +124,11 @@ typedef struct MIG_RESOURCE_ALLOCATION */ NvU32 gpcCount; + /*! + * Number of GFX GPCs associated with this instance. This should be a subset of gpcs included in gpcCount. + */ + NvU32 gfxGpcCount; + /*! * VEID start offset for this instance */ @@ -473,7 +478,6 @@ struct KernelMIGManager { NvBool (*__kmigmgrIsMemoryPartitioningRequested__)(OBJGPU *, struct KernelMIGManager *, NvU32); NvBool (*__kmigmgrIsMemoryPartitioningNeeded__)(OBJGPU *, struct KernelMIGManager *, NvU32); struct NV_RANGE (*__kmigmgrMemSizeFlagToSwizzIdRange__)(OBJGPU *, struct KernelMIGManager *, NvU32); - NV_STATUS (*__kmigmgrReconcileTunableState__)(POBJGPU, struct KernelMIGManager *, void *); NV_STATUS (*__kmigmgrStateLoad__)(POBJGPU, struct KernelMIGManager *, NvU32); NV_STATUS (*__kmigmgrStatePreLoad__)(POBJGPU, struct KernelMIGManager *, NvU32); NV_STATUS (*__kmigmgrStatePostUnload__)(POBJGPU, struct KernelMIGManager *, NvU32); @@ -483,12 +487,7 @@ struct KernelMIGManager { void (*__kmigmgrInitMissing__)(POBJGPU, struct KernelMIGManager *); NV_STATUS (*__kmigmgrStatePreInitLocked__)(POBJGPU, struct KernelMIGManager *); NV_STATUS (*__kmigmgrStatePreInitUnlocked__)(POBJGPU, struct KernelMIGManager *); - NV_STATUS (*__kmigmgrGetTunableState__)(POBJGPU, struct KernelMIGManager *, void *); - NV_STATUS (*__kmigmgrCompareTunableState__)(POBJGPU, struct KernelMIGManager *, void *, void *); - void (*__kmigmgrFreeTunableState__)(POBJGPU, struct KernelMIGManager *, void *); NV_STATUS (*__kmigmgrStatePostLoad__)(POBJGPU, struct KernelMIGManager *, NvU32); - NV_STATUS (*__kmigmgrAllocTunableState__)(POBJGPU, struct KernelMIGManager *, void **); - NV_STATUS (*__kmigmgrSetTunableState__)(POBJGPU, struct KernelMIGManager *, void *); NvBool (*__kmigmgrIsPresent__)(POBJGPU, struct KernelMIGManager *); NvBool bIsA100ReducedConfig; KERNEL_MIG_MANAGER_PRIVATE_DATA *pPrivate; @@ -549,7 +548,6 @@ NV_STATUS __nvoc_objCreate_KernelMIGManager(KernelMIGManager**, Dynamic*, NvU32) #define kmigmgrIsMemoryPartitioningNeeded_HAL(arg0, arg1, swizzId) kmigmgrIsMemoryPartitioningNeeded_DISPATCH(arg0, arg1, swizzId) #define kmigmgrMemSizeFlagToSwizzIdRange(arg0, arg1, memSizeFlag) kmigmgrMemSizeFlagToSwizzIdRange_DISPATCH(arg0, arg1, memSizeFlag) #define kmigmgrMemSizeFlagToSwizzIdRange_HAL(arg0, arg1, memSizeFlag) kmigmgrMemSizeFlagToSwizzIdRange_DISPATCH(arg0, arg1, memSizeFlag) -#define kmigmgrReconcileTunableState(pGpu, pEngstate, pTunableState) kmigmgrReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kmigmgrStateLoad(pGpu, pEngstate, arg0) kmigmgrStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kmigmgrStatePreLoad(pGpu, pEngstate, arg0) kmigmgrStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kmigmgrStatePostUnload(pGpu, pEngstate, arg0) kmigmgrStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) @@ -559,12 +557,7 @@ NV_STATUS __nvoc_objCreate_KernelMIGManager(KernelMIGManager**, Dynamic*, NvU32) #define kmigmgrInitMissing(pGpu, pEngstate) kmigmgrInitMissing_DISPATCH(pGpu, pEngstate) #define kmigmgrStatePreInitLocked(pGpu, pEngstate) kmigmgrStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kmigmgrStatePreInitUnlocked(pGpu, pEngstate) kmigmgrStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kmigmgrGetTunableState(pGpu, pEngstate, pTunableState) kmigmgrGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kmigmgrCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kmigmgrCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define kmigmgrFreeTunableState(pGpu, pEngstate, pTunableState) kmigmgrFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kmigmgrStatePostLoad(pGpu, pEngstate, arg0) kmigmgrStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define kmigmgrAllocTunableState(pGpu, pEngstate, ppTunableState) kmigmgrAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define kmigmgrSetTunableState(pGpu, pEngstate, pTunableState) kmigmgrSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kmigmgrIsPresent(pGpu, pEngstate) kmigmgrIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS kmigmgrLoadStaticInfo_KERNEL(OBJGPU *arg0, struct KernelMIGManager *arg1); @@ -832,10 +825,6 @@ static inline struct NV_RANGE kmigmgrMemSizeFlagToSwizzIdRange_DISPATCH(OBJGPU * return arg1->__kmigmgrMemSizeFlagToSwizzIdRange__(arg0, arg1, memSizeFlag); } -static inline NV_STATUS kmigmgrReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelMIGManager *pEngstate, void *pTunableState) { - return pEngstate->__kmigmgrReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kmigmgrStateLoad_DISPATCH(POBJGPU pGpu, struct KernelMIGManager *pEngstate, NvU32 arg0) { return pEngstate->__kmigmgrStateLoad__(pGpu, pEngstate, arg0); } @@ -872,30 +861,10 @@ static inline NV_STATUS kmigmgrStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struc return pEngstate->__kmigmgrStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS kmigmgrGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelMIGManager *pEngstate, void *pTunableState) { - return pEngstate->__kmigmgrGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS kmigmgrCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelMIGManager *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__kmigmgrCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void kmigmgrFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelMIGManager *pEngstate, void *pTunableState) { - pEngstate->__kmigmgrFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS kmigmgrStatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelMIGManager *pEngstate, NvU32 arg0) { return pEngstate->__kmigmgrStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS kmigmgrAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelMIGManager *pEngstate, void **ppTunableState) { - return pEngstate->__kmigmgrAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS kmigmgrSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelMIGManager *pEngstate, void *pTunableState) { - return pEngstate->__kmigmgrSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool kmigmgrIsPresent_DISPATCH(POBJGPU pGpu, struct KernelMIGManager *pEngstate) { return pEngstate->__kmigmgrIsPresent__(pGpu, pEngstate); } @@ -1409,6 +1378,17 @@ static inline NV_STATUS kmigmgrEnableAllLCEs(OBJGPU *arg0, struct KernelMIGManag #define kmigmgrEnableAllLCEs(arg0, arg1, bEnableAllLCEs) kmigmgrEnableAllLCEs_IMPL(arg0, arg1, bEnableAllLCEs) #endif //__nvoc_kernel_mig_manager_h_disabled +NV_STATUS kmigmgrGetInstanceRefFromDevice_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, NvHandle hDevice, struct MIG_INSTANCE_REF *arg2); + +#ifdef __nvoc_kernel_mig_manager_h_disabled +static inline NV_STATUS kmigmgrGetInstanceRefFromDevice(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, NvHandle hDevice, struct MIG_INSTANCE_REF *arg2) { + NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_mig_manager_h_disabled +#define kmigmgrGetInstanceRefFromDevice(arg0, arg1, hClient, hDevice, arg2) kmigmgrGetInstanceRefFromDevice_IMPL(arg0, arg1, hClient, hDevice, arg2) +#endif //__nvoc_kernel_mig_manager_h_disabled + NV_STATUS kmigmgrGetInstanceRefFromClient_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, struct MIG_INSTANCE_REF *arg2); #ifdef __nvoc_kernel_mig_manager_h_disabled @@ -1420,6 +1400,17 @@ static inline NV_STATUS kmigmgrGetInstanceRefFromClient(OBJGPU *arg0, struct Ker #define kmigmgrGetInstanceRefFromClient(arg0, arg1, hClient, arg2) kmigmgrGetInstanceRefFromClient_IMPL(arg0, arg1, hClient, arg2) #endif //__nvoc_kernel_mig_manager_h_disabled +NV_STATUS kmigmgrGetMemoryPartitionHeapFromDevice_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, NvHandle hDevice, struct Heap **arg2); + +#ifdef __nvoc_kernel_mig_manager_h_disabled +static inline NV_STATUS kmigmgrGetMemoryPartitionHeapFromDevice(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, NvHandle hDevice, struct Heap **arg2) { + NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_mig_manager_h_disabled +#define kmigmgrGetMemoryPartitionHeapFromDevice(arg0, arg1, hClient, hDevice, arg2) kmigmgrGetMemoryPartitionHeapFromDevice_IMPL(arg0, arg1, hClient, hDevice, arg2) +#endif //__nvoc_kernel_mig_manager_h_disabled + NV_STATUS kmigmgrGetMemoryPartitionHeapFromClient_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, struct Heap **arg2); #ifdef __nvoc_kernel_mig_manager_h_disabled diff --git a/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.c b/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.c index 5eb62487d..009a98b9d 100644 --- a/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.c +++ b/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.c @@ -176,7 +176,7 @@ static NV_STATUS __nvoc_thunk_RsResource_nvdecctxControlLookup(struct NvdecConte return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvdecContext_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_ChannelDescendant_nvdecctxGetSwMethods(struct NvdecContext *pChannelDescendant, METHOD **ppMethods, NvU32 *pNumMethods) { +static NV_STATUS __nvoc_thunk_ChannelDescendant_nvdecctxGetSwMethods(struct NvdecContext *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return chandesGetSwMethods((struct ChannelDescendant *)(((unsigned char *)pChannelDescendant) + __nvoc_rtti_NvdecContext_ChannelDescendant.offset), ppMethods, pNumMethods); } @@ -212,6 +212,10 @@ static NV_STATUS __nvoc_thunk_Notifier_nvdecctxUnregisterEvent(struct NvdecConte return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_NvdecContext_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_nvdecctxControlSerialization_Prologue(struct NvdecContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvdecContext_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_nvdecctxCanCopy(struct NvdecContext *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvdecContext_RsResource.offset)); } @@ -224,6 +228,10 @@ static NV_STATUS __nvoc_thunk_RsResource_nvdecctxIsDuplicate(struct NvdecContext return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvdecContext_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_nvdecctxControlSerialization_Epilogue(struct NvdecContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvdecContext_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_nvdecctxGetNotificationListPtr(struct NvdecContext *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_NvdecContext_Notifier.offset)); } @@ -335,12 +343,16 @@ static void __nvoc_init_funcTable_NvdecContext_1(NvdecContext *pThis, RmHalspecO pThis->__nvdecctxUnregisterEvent__ = &__nvoc_thunk_Notifier_nvdecctxUnregisterEvent; + pThis->__nvdecctxControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_nvdecctxControlSerialization_Prologue; + pThis->__nvdecctxCanCopy__ = &__nvoc_thunk_RsResource_nvdecctxCanCopy; pThis->__nvdecctxPreDestruct__ = &__nvoc_thunk_RsResource_nvdecctxPreDestruct; pThis->__nvdecctxIsDuplicate__ = &__nvoc_thunk_RsResource_nvdecctxIsDuplicate; + pThis->__nvdecctxControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_nvdecctxControlSerialization_Epilogue; + pThis->__nvdecctxGetNotificationListPtr__ = &__nvoc_thunk_Notifier_nvdecctxGetNotificationListPtr; pThis->__nvdecctxGetNotificationShare__ = &__nvoc_thunk_Notifier_nvdecctxGetNotificationShare; @@ -375,13 +387,16 @@ NV_STATUS __nvoc_objCreate_NvdecContext(NvdecContext **ppThis, Dynamic *pParent, NvdecContext *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(NvdecContext)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(NvdecContext), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(NvdecContext)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_NvdecContext); + pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -401,11 +416,17 @@ NV_STATUS __nvoc_objCreate_NvdecContext(NvdecContext **ppThis, Dynamic *pParent, if (status != NV_OK) goto __nvoc_objCreate_NvdecContext_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_NvdecContext_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(NvdecContext)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.h b/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.h index 72867537c..10b56a252 100644 --- a/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.h +++ b/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.h @@ -72,7 +72,7 @@ struct NvdecContext { NV_STATUS (*__nvdecctxUnmapFrom__)(struct NvdecContext *, RS_RES_UNMAP_FROM_PARAMS *); void (*__nvdecctxControl_Epilogue__)(struct NvdecContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__nvdecctxControlLookup__)(struct NvdecContext *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); - NV_STATUS (*__nvdecctxGetSwMethods__)(struct NvdecContext *, METHOD **, NvU32 *); + NV_STATUS (*__nvdecctxGetSwMethods__)(struct NvdecContext *, const METHOD **, NvU32 *); NvHandle (*__nvdecctxGetInternalObjectHandle__)(struct NvdecContext *); NV_STATUS (*__nvdecctxControl__)(struct NvdecContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__nvdecctxUnmap__)(struct NvdecContext *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -81,9 +81,11 @@ struct NvdecContext { NvBool (*__nvdecctxIsSwMethodStalling__)(struct NvdecContext *, NvU32); NV_STATUS (*__nvdecctxControlFilter__)(struct NvdecContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__nvdecctxUnregisterEvent__)(struct NvdecContext *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__nvdecctxControlSerialization_Prologue__)(struct NvdecContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__nvdecctxCanCopy__)(struct NvdecContext *); void (*__nvdecctxPreDestruct__)(struct NvdecContext *); NV_STATUS (*__nvdecctxIsDuplicate__)(struct NvdecContext *, NvHandle, NvBool *); + void (*__nvdecctxControlSerialization_Epilogue__)(struct NvdecContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__nvdecctxGetNotificationListPtr__)(struct NvdecContext *); struct NotifShare *(*__nvdecctxGetNotificationShare__)(struct NvdecContext *); NV_STATUS (*__nvdecctxMap__)(struct NvdecContext *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -141,9 +143,11 @@ NV_STATUS __nvoc_objCreate_NvdecContext(NvdecContext**, Dynamic*, NvU32, struct #define nvdecctxIsSwMethodStalling(pChannelDescendant, hHandle) nvdecctxIsSwMethodStalling_DISPATCH(pChannelDescendant, hHandle) #define nvdecctxControlFilter(pResource, pCallContext, pParams) nvdecctxControlFilter_DISPATCH(pResource, pCallContext, pParams) #define nvdecctxUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) nvdecctxUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define nvdecctxControlSerialization_Prologue(pResource, pCallContext, pParams) nvdecctxControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define nvdecctxCanCopy(pResource) nvdecctxCanCopy_DISPATCH(pResource) #define nvdecctxPreDestruct(pResource) nvdecctxPreDestruct_DISPATCH(pResource) #define nvdecctxIsDuplicate(pResource, hMemory, pDuplicate) nvdecctxIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define nvdecctxControlSerialization_Epilogue(pResource, pCallContext, pParams) nvdecctxControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define nvdecctxGetNotificationListPtr(pNotifier) nvdecctxGetNotificationListPtr_DISPATCH(pNotifier) #define nvdecctxGetNotificationShare(pNotifier) nvdecctxGetNotificationShare_DISPATCH(pNotifier) #define nvdecctxMap(pGpuResource, pCallContext, pParams, pCpuMapping) nvdecctxMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -231,7 +235,7 @@ static inline NV_STATUS nvdecctxControlLookup_DISPATCH(struct NvdecContext *pRes return pResource->__nvdecctxControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS nvdecctxGetSwMethods_DISPATCH(struct NvdecContext *pChannelDescendant, METHOD **ppMethods, NvU32 *pNumMethods) { +static inline NV_STATUS nvdecctxGetSwMethods_DISPATCH(struct NvdecContext *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return pChannelDescendant->__nvdecctxGetSwMethods__(pChannelDescendant, ppMethods, pNumMethods); } @@ -267,6 +271,10 @@ static inline NV_STATUS nvdecctxUnregisterEvent_DISPATCH(struct NvdecContext *pN return pNotifier->__nvdecctxUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS nvdecctxControlSerialization_Prologue_DISPATCH(struct NvdecContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__nvdecctxControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool nvdecctxCanCopy_DISPATCH(struct NvdecContext *pResource) { return pResource->__nvdecctxCanCopy__(pResource); } @@ -279,6 +287,10 @@ static inline NV_STATUS nvdecctxIsDuplicate_DISPATCH(struct NvdecContext *pResou return pResource->__nvdecctxIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void nvdecctxControlSerialization_Epilogue_DISPATCH(struct NvdecContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__nvdecctxControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *nvdecctxGetNotificationListPtr_DISPATCH(struct NvdecContext *pNotifier) { return pNotifier->__nvdecctxGetNotificationListPtr__(pNotifier); } diff --git a/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.c b/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.c index 9740f5cc1..dfd990269 100644 --- a/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.c +++ b/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.c @@ -176,7 +176,7 @@ static NV_STATUS __nvoc_thunk_RsResource_msencctxControlLookup(struct MsencConte return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MsencContext_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_ChannelDescendant_msencctxGetSwMethods(struct MsencContext *pChannelDescendant, METHOD **ppMethods, NvU32 *pNumMethods) { +static NV_STATUS __nvoc_thunk_ChannelDescendant_msencctxGetSwMethods(struct MsencContext *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return chandesGetSwMethods((struct ChannelDescendant *)(((unsigned char *)pChannelDescendant) + __nvoc_rtti_MsencContext_ChannelDescendant.offset), ppMethods, pNumMethods); } @@ -212,6 +212,10 @@ static NV_STATUS __nvoc_thunk_Notifier_msencctxUnregisterEvent(struct MsencConte return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_MsencContext_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_msencctxControlSerialization_Prologue(struct MsencContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MsencContext_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_msencctxCanCopy(struct MsencContext *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MsencContext_RsResource.offset)); } @@ -224,6 +228,10 @@ static NV_STATUS __nvoc_thunk_RsResource_msencctxIsDuplicate(struct MsencContext return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MsencContext_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_msencctxControlSerialization_Epilogue(struct MsencContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MsencContext_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_msencctxGetNotificationListPtr(struct MsencContext *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_MsencContext_Notifier.offset)); } @@ -335,12 +343,16 @@ static void __nvoc_init_funcTable_MsencContext_1(MsencContext *pThis, RmHalspecO pThis->__msencctxUnregisterEvent__ = &__nvoc_thunk_Notifier_msencctxUnregisterEvent; + pThis->__msencctxControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_msencctxControlSerialization_Prologue; + pThis->__msencctxCanCopy__ = &__nvoc_thunk_RsResource_msencctxCanCopy; pThis->__msencctxPreDestruct__ = &__nvoc_thunk_RsResource_msencctxPreDestruct; pThis->__msencctxIsDuplicate__ = &__nvoc_thunk_RsResource_msencctxIsDuplicate; + pThis->__msencctxControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_msencctxControlSerialization_Epilogue; + pThis->__msencctxGetNotificationListPtr__ = &__nvoc_thunk_Notifier_msencctxGetNotificationListPtr; pThis->__msencctxGetNotificationShare__ = &__nvoc_thunk_Notifier_msencctxGetNotificationShare; @@ -375,13 +387,16 @@ NV_STATUS __nvoc_objCreate_MsencContext(MsencContext **ppThis, Dynamic *pParent, MsencContext *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(MsencContext)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MsencContext), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(MsencContext)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MsencContext); + pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -401,11 +416,17 @@ NV_STATUS __nvoc_objCreate_MsencContext(MsencContext **ppThis, Dynamic *pParent, if (status != NV_OK) goto __nvoc_objCreate_MsencContext_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_MsencContext_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(MsencContext)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.h b/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.h index 9da17e2bc..5a5281095 100644 --- a/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.h +++ b/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.h @@ -72,7 +72,7 @@ struct MsencContext { NV_STATUS (*__msencctxUnmapFrom__)(struct MsencContext *, RS_RES_UNMAP_FROM_PARAMS *); void (*__msencctxControl_Epilogue__)(struct MsencContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__msencctxControlLookup__)(struct MsencContext *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); - NV_STATUS (*__msencctxGetSwMethods__)(struct MsencContext *, METHOD **, NvU32 *); + NV_STATUS (*__msencctxGetSwMethods__)(struct MsencContext *, const METHOD **, NvU32 *); NvHandle (*__msencctxGetInternalObjectHandle__)(struct MsencContext *); NV_STATUS (*__msencctxControl__)(struct MsencContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__msencctxUnmap__)(struct MsencContext *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -81,9 +81,11 @@ struct MsencContext { NvBool (*__msencctxIsSwMethodStalling__)(struct MsencContext *, NvU32); NV_STATUS (*__msencctxControlFilter__)(struct MsencContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__msencctxUnregisterEvent__)(struct MsencContext *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__msencctxControlSerialization_Prologue__)(struct MsencContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__msencctxCanCopy__)(struct MsencContext *); void (*__msencctxPreDestruct__)(struct MsencContext *); NV_STATUS (*__msencctxIsDuplicate__)(struct MsencContext *, NvHandle, NvBool *); + void (*__msencctxControlSerialization_Epilogue__)(struct MsencContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__msencctxGetNotificationListPtr__)(struct MsencContext *); struct NotifShare *(*__msencctxGetNotificationShare__)(struct MsencContext *); NV_STATUS (*__msencctxMap__)(struct MsencContext *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -141,9 +143,11 @@ NV_STATUS __nvoc_objCreate_MsencContext(MsencContext**, Dynamic*, NvU32, struct #define msencctxIsSwMethodStalling(pChannelDescendant, hHandle) msencctxIsSwMethodStalling_DISPATCH(pChannelDescendant, hHandle) #define msencctxControlFilter(pResource, pCallContext, pParams) msencctxControlFilter_DISPATCH(pResource, pCallContext, pParams) #define msencctxUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) msencctxUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define msencctxControlSerialization_Prologue(pResource, pCallContext, pParams) msencctxControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define msencctxCanCopy(pResource) msencctxCanCopy_DISPATCH(pResource) #define msencctxPreDestruct(pResource) msencctxPreDestruct_DISPATCH(pResource) #define msencctxIsDuplicate(pResource, hMemory, pDuplicate) msencctxIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define msencctxControlSerialization_Epilogue(pResource, pCallContext, pParams) msencctxControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define msencctxGetNotificationListPtr(pNotifier) msencctxGetNotificationListPtr_DISPATCH(pNotifier) #define msencctxGetNotificationShare(pNotifier) msencctxGetNotificationShare_DISPATCH(pNotifier) #define msencctxMap(pGpuResource, pCallContext, pParams, pCpuMapping) msencctxMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -231,7 +235,7 @@ static inline NV_STATUS msencctxControlLookup_DISPATCH(struct MsencContext *pRes return pResource->__msencctxControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS msencctxGetSwMethods_DISPATCH(struct MsencContext *pChannelDescendant, METHOD **ppMethods, NvU32 *pNumMethods) { +static inline NV_STATUS msencctxGetSwMethods_DISPATCH(struct MsencContext *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return pChannelDescendant->__msencctxGetSwMethods__(pChannelDescendant, ppMethods, pNumMethods); } @@ -267,6 +271,10 @@ static inline NV_STATUS msencctxUnregisterEvent_DISPATCH(struct MsencContext *pN return pNotifier->__msencctxUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS msencctxControlSerialization_Prologue_DISPATCH(struct MsencContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__msencctxControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool msencctxCanCopy_DISPATCH(struct MsencContext *pResource) { return pResource->__msencctxCanCopy__(pResource); } @@ -279,6 +287,10 @@ static inline NV_STATUS msencctxIsDuplicate_DISPATCH(struct MsencContext *pResou return pResource->__msencctxIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void msencctxControlSerialization_Epilogue_DISPATCH(struct MsencContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__msencctxControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *msencctxGetNotificationListPtr_DISPATCH(struct MsencContext *pNotifier) { return pNotifier->__msencctxGetNotificationListPtr__(pNotifier); } diff --git a/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.c b/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.c index 5b011761e..f64b22d81 100644 --- a/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.c +++ b/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.c @@ -176,7 +176,7 @@ static NV_STATUS __nvoc_thunk_RsResource_nvjpgctxControlLookup(struct NvjpgConte return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvjpgContext_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_ChannelDescendant_nvjpgctxGetSwMethods(struct NvjpgContext *pChannelDescendant, METHOD **ppMethods, NvU32 *pNumMethods) { +static NV_STATUS __nvoc_thunk_ChannelDescendant_nvjpgctxGetSwMethods(struct NvjpgContext *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return chandesGetSwMethods((struct ChannelDescendant *)(((unsigned char *)pChannelDescendant) + __nvoc_rtti_NvjpgContext_ChannelDescendant.offset), ppMethods, pNumMethods); } @@ -212,6 +212,10 @@ static NV_STATUS __nvoc_thunk_Notifier_nvjpgctxUnregisterEvent(struct NvjpgConte return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_NvjpgContext_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_nvjpgctxControlSerialization_Prologue(struct NvjpgContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvjpgContext_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_nvjpgctxCanCopy(struct NvjpgContext *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvjpgContext_RsResource.offset)); } @@ -224,6 +228,10 @@ static NV_STATUS __nvoc_thunk_RsResource_nvjpgctxIsDuplicate(struct NvjpgContext return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvjpgContext_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_nvjpgctxControlSerialization_Epilogue(struct NvjpgContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvjpgContext_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_nvjpgctxGetNotificationListPtr(struct NvjpgContext *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_NvjpgContext_Notifier.offset)); } @@ -335,12 +343,16 @@ static void __nvoc_init_funcTable_NvjpgContext_1(NvjpgContext *pThis, RmHalspecO pThis->__nvjpgctxUnregisterEvent__ = &__nvoc_thunk_Notifier_nvjpgctxUnregisterEvent; + pThis->__nvjpgctxControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_nvjpgctxControlSerialization_Prologue; + pThis->__nvjpgctxCanCopy__ = &__nvoc_thunk_RsResource_nvjpgctxCanCopy; pThis->__nvjpgctxPreDestruct__ = &__nvoc_thunk_RsResource_nvjpgctxPreDestruct; pThis->__nvjpgctxIsDuplicate__ = &__nvoc_thunk_RsResource_nvjpgctxIsDuplicate; + pThis->__nvjpgctxControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_nvjpgctxControlSerialization_Epilogue; + pThis->__nvjpgctxGetNotificationListPtr__ = &__nvoc_thunk_Notifier_nvjpgctxGetNotificationListPtr; pThis->__nvjpgctxGetNotificationShare__ = &__nvoc_thunk_Notifier_nvjpgctxGetNotificationShare; @@ -375,13 +387,16 @@ NV_STATUS __nvoc_objCreate_NvjpgContext(NvjpgContext **ppThis, Dynamic *pParent, NvjpgContext *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(NvjpgContext)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(NvjpgContext), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(NvjpgContext)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_NvjpgContext); + pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -401,11 +416,17 @@ NV_STATUS __nvoc_objCreate_NvjpgContext(NvjpgContext **ppThis, Dynamic *pParent, if (status != NV_OK) goto __nvoc_objCreate_NvjpgContext_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_NvjpgContext_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(NvjpgContext)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.h b/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.h index 64a4e24ec..26c42965c 100644 --- a/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.h +++ b/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.h @@ -72,7 +72,7 @@ struct NvjpgContext { NV_STATUS (*__nvjpgctxUnmapFrom__)(struct NvjpgContext *, RS_RES_UNMAP_FROM_PARAMS *); void (*__nvjpgctxControl_Epilogue__)(struct NvjpgContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__nvjpgctxControlLookup__)(struct NvjpgContext *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); - NV_STATUS (*__nvjpgctxGetSwMethods__)(struct NvjpgContext *, METHOD **, NvU32 *); + NV_STATUS (*__nvjpgctxGetSwMethods__)(struct NvjpgContext *, const METHOD **, NvU32 *); NvHandle (*__nvjpgctxGetInternalObjectHandle__)(struct NvjpgContext *); NV_STATUS (*__nvjpgctxControl__)(struct NvjpgContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__nvjpgctxUnmap__)(struct NvjpgContext *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -81,9 +81,11 @@ struct NvjpgContext { NvBool (*__nvjpgctxIsSwMethodStalling__)(struct NvjpgContext *, NvU32); NV_STATUS (*__nvjpgctxControlFilter__)(struct NvjpgContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__nvjpgctxUnregisterEvent__)(struct NvjpgContext *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__nvjpgctxControlSerialization_Prologue__)(struct NvjpgContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__nvjpgctxCanCopy__)(struct NvjpgContext *); void (*__nvjpgctxPreDestruct__)(struct NvjpgContext *); NV_STATUS (*__nvjpgctxIsDuplicate__)(struct NvjpgContext *, NvHandle, NvBool *); + void (*__nvjpgctxControlSerialization_Epilogue__)(struct NvjpgContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__nvjpgctxGetNotificationListPtr__)(struct NvjpgContext *); struct NotifShare *(*__nvjpgctxGetNotificationShare__)(struct NvjpgContext *); NV_STATUS (*__nvjpgctxMap__)(struct NvjpgContext *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -141,9 +143,11 @@ NV_STATUS __nvoc_objCreate_NvjpgContext(NvjpgContext**, Dynamic*, NvU32, struct #define nvjpgctxIsSwMethodStalling(pChannelDescendant, hHandle) nvjpgctxIsSwMethodStalling_DISPATCH(pChannelDescendant, hHandle) #define nvjpgctxControlFilter(pResource, pCallContext, pParams) nvjpgctxControlFilter_DISPATCH(pResource, pCallContext, pParams) #define nvjpgctxUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) nvjpgctxUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define nvjpgctxControlSerialization_Prologue(pResource, pCallContext, pParams) nvjpgctxControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define nvjpgctxCanCopy(pResource) nvjpgctxCanCopy_DISPATCH(pResource) #define nvjpgctxPreDestruct(pResource) nvjpgctxPreDestruct_DISPATCH(pResource) #define nvjpgctxIsDuplicate(pResource, hMemory, pDuplicate) nvjpgctxIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define nvjpgctxControlSerialization_Epilogue(pResource, pCallContext, pParams) nvjpgctxControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define nvjpgctxGetNotificationListPtr(pNotifier) nvjpgctxGetNotificationListPtr_DISPATCH(pNotifier) #define nvjpgctxGetNotificationShare(pNotifier) nvjpgctxGetNotificationShare_DISPATCH(pNotifier) #define nvjpgctxMap(pGpuResource, pCallContext, pParams, pCpuMapping) nvjpgctxMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -231,7 +235,7 @@ static inline NV_STATUS nvjpgctxControlLookup_DISPATCH(struct NvjpgContext *pRes return pResource->__nvjpgctxControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS nvjpgctxGetSwMethods_DISPATCH(struct NvjpgContext *pChannelDescendant, METHOD **ppMethods, NvU32 *pNumMethods) { +static inline NV_STATUS nvjpgctxGetSwMethods_DISPATCH(struct NvjpgContext *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return pChannelDescendant->__nvjpgctxGetSwMethods__(pChannelDescendant, ppMethods, pNumMethods); } @@ -267,6 +271,10 @@ static inline NV_STATUS nvjpgctxUnregisterEvent_DISPATCH(struct NvjpgContext *pN return pNotifier->__nvjpgctxUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS nvjpgctxControlSerialization_Prologue_DISPATCH(struct NvjpgContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__nvjpgctxControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool nvjpgctxCanCopy_DISPATCH(struct NvjpgContext *pResource) { return pResource->__nvjpgctxCanCopy__(pResource); } @@ -279,6 +287,10 @@ static inline NV_STATUS nvjpgctxIsDuplicate_DISPATCH(struct NvjpgContext *pResou return pResource->__nvjpgctxIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void nvjpgctxControlSerialization_Epilogue_DISPATCH(struct NvjpgContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__nvjpgctxControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *nvjpgctxGetNotificationListPtr_DISPATCH(struct NvjpgContext *pNotifier) { return pNotifier->__nvjpgctxGetNotificationListPtr__(pNotifier); } diff --git a/src/nvidia/generated/g_kernel_nvlink_nvoc.c b/src/nvidia/generated/g_kernel_nvlink_nvoc.c index c5a357d4b..0803262a8 100644 --- a/src/nvidia/generated/g_kernel_nvlink_nvoc.c +++ b/src/nvidia/generated/g_kernel_nvlink_nvoc.c @@ -94,10 +94,6 @@ static NvBool __nvoc_thunk_KernelNvlink_engstateIsPresent(OBJGPU *arg0, struct O return knvlinkIsPresent(arg0, (struct KernelNvlink *)(((unsigned char *)arg1) - __nvoc_rtti_KernelNvlink_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_knvlinkReconcileTunableState(POBJGPU pGpu, struct KernelNvlink *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvlink_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_knvlinkStateInitLocked(POBJGPU pGpu, struct KernelNvlink *pEngstate) { return engstateStateInitLocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvlink_OBJENGSTATE.offset)); } @@ -126,26 +122,6 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_knvlinkStatePreInitUnlocked(POBJGPU pG return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvlink_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_knvlinkGetTunableState(POBJGPU pGpu, struct KernelNvlink *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvlink_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_knvlinkCompareTunableState(POBJGPU pGpu, struct KernelNvlink *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvlink_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_knvlinkFreeTunableState(POBJGPU pGpu, struct KernelNvlink *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvlink_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_knvlinkAllocTunableState(POBJGPU pGpu, struct KernelNvlink *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvlink_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_knvlinkSetTunableState(POBJGPU pGpu, struct KernelNvlink *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelNvlink_OBJENGSTATE.offset), pTunableState); -} - const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelNvlink = { /*numEntries=*/ 0, @@ -589,16 +565,42 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO } } - // Hal function -- knvlinkIsFloorSweepingNeeded + // Hal function -- knvlinkGetEffectivePeerLinkMask if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__knvlinkIsFloorSweepingNeeded__ = &knvlinkIsFloorSweepingNeeded_GH100; + pThis->__knvlinkGetEffectivePeerLinkMask__ = &knvlinkGetEffectivePeerLinkMask_GH100; } else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { - pThis->__knvlinkIsFloorSweepingNeeded__ = &knvlinkIsFloorSweepingNeeded_491d52; + pThis->__knvlinkGetEffectivePeerLinkMask__ = &knvlinkGetEffectivePeerLinkMask_b3696a; + } + } + + // Hal function -- knvlinkGetNumLinksToBeReducedPerIoctrl + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__knvlinkGetNumLinksToBeReducedPerIoctrl__ = &knvlinkGetNumLinksToBeReducedPerIoctrl_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__knvlinkGetNumLinksToBeReducedPerIoctrl__ = &knvlinkGetNumLinksToBeReducedPerIoctrl_4a4dee; + } + } + + // Hal function -- knvlinkIsBandwidthModeOff + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__knvlinkIsBandwidthModeOff__ = &knvlinkIsBandwidthModeOff_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__knvlinkIsBandwidthModeOff__ = &knvlinkIsBandwidthModeOff_491d52; } } @@ -615,6 +617,19 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO } } + // Hal function -- knvlinkIsFloorSweepingNeeded + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__knvlinkIsFloorSweepingNeeded__ = &knvlinkIsFloorSweepingNeeded_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__knvlinkIsFloorSweepingNeeded__ = &knvlinkIsFloorSweepingNeeded_491d52; + } + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelNvlink_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreInitLocked__ = &__nvoc_thunk_KernelNvlink_engstateStatePreInitLocked; @@ -629,8 +644,6 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO pThis->__nvoc_base_OBJENGSTATE.__engstateIsPresent__ = &__nvoc_thunk_KernelNvlink_engstateIsPresent; - pThis->__knvlinkReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_knvlinkReconcileTunableState; - pThis->__knvlinkStateInitLocked__ = &__nvoc_thunk_OBJENGSTATE_knvlinkStateInitLocked; pThis->__knvlinkStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_knvlinkStatePreLoad; @@ -644,16 +657,6 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO pThis->__knvlinkInitMissing__ = &__nvoc_thunk_OBJENGSTATE_knvlinkInitMissing; pThis->__knvlinkStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_knvlinkStatePreInitUnlocked; - - pThis->__knvlinkGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_knvlinkGetTunableState; - - pThis->__knvlinkCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_knvlinkCompareTunableState; - - pThis->__knvlinkFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_knvlinkFreeTunableState; - - pThis->__knvlinkAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_knvlinkAllocTunableState; - - pThis->__knvlinkSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_knvlinkSetTunableState; } void __nvoc_init_funcTable_KernelNvlink(KernelNvlink *pThis, RmHalspecOwner *pRmhalspecowner) { @@ -675,13 +678,16 @@ NV_STATUS __nvoc_objCreate_KernelNvlink(KernelNvlink **ppThis, Dynamic *pParent, KernelNvlink *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelNvlink)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelNvlink), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelNvlink)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelNvlink); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -701,11 +707,17 @@ NV_STATUS __nvoc_objCreate_KernelNvlink(KernelNvlink **ppThis, Dynamic *pParent, if (status != NV_OK) goto __nvoc_objCreate_KernelNvlink_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelNvlink_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelNvlink)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_nvlink_nvoc.h b/src/nvidia/generated/g_kernel_nvlink_nvoc.h index 7d35edb3d..81acbb097 100644 --- a/src/nvidia/generated/g_kernel_nvlink_nvoc.h +++ b/src/nvidia/generated/g_kernel_nvlink_nvoc.h @@ -190,7 +190,7 @@ typedef struct _def_knvlink_link typedef struct NVLINK_INBAND_CALLBACK { NvU32 messageType; - void (*pCallback)(OBJGPU *pGpu, + void (*pCallback)(NvU32 gpuInstance, NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pMessage); NvU32 wqItemFlags; } NVLINK_INBAND_MSG_CALLBACK; @@ -245,9 +245,11 @@ struct KernelNvlink { NV_STATUS (*__knvlinkPostSetupNvlinkPeer__)(OBJGPU *, struct KernelNvlink *); NV_STATUS (*__knvlinkDiscoverPostRxDetLinks__)(OBJGPU *, struct KernelNvlink *, OBJGPU *); NV_STATUS (*__knvlinkLogAliDebugMessages__)(OBJGPU *, struct KernelNvlink *); - NvBool (*__knvlinkIsFloorSweepingNeeded__)(OBJGPU *, struct KernelNvlink *, NvU32, NvU32); + void (*__knvlinkGetEffectivePeerLinkMask__)(OBJGPU *, struct KernelNvlink *, OBJGPU *, NvU32 *); + NvU32 (*__knvlinkGetNumLinksToBeReducedPerIoctrl__)(struct KernelNvlink *); + NvBool (*__knvlinkIsBandwidthModeOff__)(struct KernelNvlink *); void (*__knvlinkDirectConnectCheck__)(OBJGPU *, struct KernelNvlink *); - NV_STATUS (*__knvlinkReconcileTunableState__)(POBJGPU, struct KernelNvlink *, void *); + NvBool (*__knvlinkIsFloorSweepingNeeded__)(OBJGPU *, struct KernelNvlink *, NvU32, NvU32); NV_STATUS (*__knvlinkStateInitLocked__)(POBJGPU, struct KernelNvlink *); NV_STATUS (*__knvlinkStatePreLoad__)(POBJGPU, struct KernelNvlink *, NvU32); void (*__knvlinkStateDestroy__)(POBJGPU, struct KernelNvlink *); @@ -255,13 +257,7 @@ struct KernelNvlink { NV_STATUS (*__knvlinkStateInitUnlocked__)(POBJGPU, struct KernelNvlink *); void (*__knvlinkInitMissing__)(POBJGPU, struct KernelNvlink *); NV_STATUS (*__knvlinkStatePreInitUnlocked__)(POBJGPU, struct KernelNvlink *); - NV_STATUS (*__knvlinkGetTunableState__)(POBJGPU, struct KernelNvlink *, void *); - NV_STATUS (*__knvlinkCompareTunableState__)(POBJGPU, struct KernelNvlink *, void *, void *); - void (*__knvlinkFreeTunableState__)(POBJGPU, struct KernelNvlink *, void *); - NV_STATUS (*__knvlinkAllocTunableState__)(POBJGPU, struct KernelNvlink *, void **); - NV_STATUS (*__knvlinkSetTunableState__)(POBJGPU, struct KernelNvlink *, void *); NvBool PDB_PROP_KNVLINK_ENABLED; - NvBool PDB_PROP_KNVLINK_SINGLE_LANE_POWER_STATE_ENABLED; NvBool PDB_PROP_KNVLINK_L2_POWER_STATE_ENABLED; NvBool PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_SUPPORTED; NvBool PDB_PROP_KNVLINK_CONFIG_REQUIRE_INITIALIZED_LINKS_CHECK; @@ -318,7 +314,6 @@ struct KernelNvlink { NvBool bEnableAli; NvBool bFloorSwept; NvBool bLinkTrainingDebugSpew; - NvBool bDisableSingleLaneMode; NvBool bDisableL2Mode; NvU32 nvlinkLinkSpeed; NvU32 errorRecoveries[18]; @@ -369,8 +364,6 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelNvlink; #define PDB_PROP_KNVLINK_IS_MISSING_BASE_NAME PDB_PROP_ENGSTATE_IS_MISSING #define PDB_PROP_KNVLINK_WAR_BUG_3471679_PEERID_FILTERING_BASE_CAST #define PDB_PROP_KNVLINK_WAR_BUG_3471679_PEERID_FILTERING_BASE_NAME PDB_PROP_KNVLINK_WAR_BUG_3471679_PEERID_FILTERING -#define PDB_PROP_KNVLINK_SINGLE_LANE_POWER_STATE_ENABLED_BASE_CAST -#define PDB_PROP_KNVLINK_SINGLE_LANE_POWER_STATE_ENABLED_BASE_NAME PDB_PROP_KNVLINK_SINGLE_LANE_POWER_STATE_ENABLED #define PDB_PROP_KNVLINK_BUG2274645_RESET_FOR_RTD3_FGC6_BASE_CAST #define PDB_PROP_KNVLINK_BUG2274645_RESET_FOR_RTD3_FGC6_BASE_NAME PDB_PROP_KNVLINK_BUG2274645_RESET_FOR_RTD3_FGC6 #define PDB_PROP_KNVLINK_LANE_SHUTDOWN_ON_UNLOAD_BASE_CAST @@ -431,11 +424,16 @@ NV_STATUS __nvoc_objCreate_KernelNvlink(KernelNvlink**, Dynamic*, NvU32); #define knvlinkDiscoverPostRxDetLinks_HAL(pGpu, pKernelNvlink, pPeerGpu) knvlinkDiscoverPostRxDetLinks_DISPATCH(pGpu, pKernelNvlink, pPeerGpu) #define knvlinkLogAliDebugMessages(pGpu, pKernelNvlink) knvlinkLogAliDebugMessages_DISPATCH(pGpu, pKernelNvlink) #define knvlinkLogAliDebugMessages_HAL(pGpu, pKernelNvlink) knvlinkLogAliDebugMessages_DISPATCH(pGpu, pKernelNvlink) -#define knvlinkIsFloorSweepingNeeded(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl) knvlinkIsFloorSweepingNeeded_DISPATCH(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl) -#define knvlinkIsFloorSweepingNeeded_HAL(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl) knvlinkIsFloorSweepingNeeded_DISPATCH(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl) +#define knvlinkGetEffectivePeerLinkMask(pGpu, pKernelNvlink, pRemoteGpu, pPeerLinkMask) knvlinkGetEffectivePeerLinkMask_DISPATCH(pGpu, pKernelNvlink, pRemoteGpu, pPeerLinkMask) +#define knvlinkGetEffectivePeerLinkMask_HAL(pGpu, pKernelNvlink, pRemoteGpu, pPeerLinkMask) knvlinkGetEffectivePeerLinkMask_DISPATCH(pGpu, pKernelNvlink, pRemoteGpu, pPeerLinkMask) +#define knvlinkGetNumLinksToBeReducedPerIoctrl(pKernelNvlink) knvlinkGetNumLinksToBeReducedPerIoctrl_DISPATCH(pKernelNvlink) +#define knvlinkGetNumLinksToBeReducedPerIoctrl_HAL(pKernelNvlink) knvlinkGetNumLinksToBeReducedPerIoctrl_DISPATCH(pKernelNvlink) +#define knvlinkIsBandwidthModeOff(pKernelNvlink) knvlinkIsBandwidthModeOff_DISPATCH(pKernelNvlink) +#define knvlinkIsBandwidthModeOff_HAL(pKernelNvlink) knvlinkIsBandwidthModeOff_DISPATCH(pKernelNvlink) #define knvlinkDirectConnectCheck(pGpu, pKernelNvlink) knvlinkDirectConnectCheck_DISPATCH(pGpu, pKernelNvlink) #define knvlinkDirectConnectCheck_HAL(pGpu, pKernelNvlink) knvlinkDirectConnectCheck_DISPATCH(pGpu, pKernelNvlink) -#define knvlinkReconcileTunableState(pGpu, pEngstate, pTunableState) knvlinkReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) +#define knvlinkIsFloorSweepingNeeded(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl) knvlinkIsFloorSweepingNeeded_DISPATCH(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl) +#define knvlinkIsFloorSweepingNeeded_HAL(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl) knvlinkIsFloorSweepingNeeded_DISPATCH(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl) #define knvlinkStateInitLocked(pGpu, pEngstate) knvlinkStateInitLocked_DISPATCH(pGpu, pEngstate) #define knvlinkStatePreLoad(pGpu, pEngstate, arg0) knvlinkStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define knvlinkStateDestroy(pGpu, pEngstate) knvlinkStateDestroy_DISPATCH(pGpu, pEngstate) @@ -443,11 +441,6 @@ NV_STATUS __nvoc_objCreate_KernelNvlink(KernelNvlink**, Dynamic*, NvU32); #define knvlinkStateInitUnlocked(pGpu, pEngstate) knvlinkStateInitUnlocked_DISPATCH(pGpu, pEngstate) #define knvlinkInitMissing(pGpu, pEngstate) knvlinkInitMissing_DISPATCH(pGpu, pEngstate) #define knvlinkStatePreInitUnlocked(pGpu, pEngstate) knvlinkStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define knvlinkGetTunableState(pGpu, pEngstate, pTunableState) knvlinkGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define knvlinkCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) knvlinkCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define knvlinkFreeTunableState(pGpu, pEngstate, pTunableState) knvlinkFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define knvlinkAllocTunableState(pGpu, pEngstate, ppTunableState) knvlinkAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define knvlinkSetTunableState(pGpu, pEngstate, pTunableState) knvlinkSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) NvBool knvlinkIsForcedConfig_IMPL(OBJGPU *arg0, struct KernelNvlink *arg1); @@ -1553,14 +1546,34 @@ static inline NV_STATUS knvlinkLogAliDebugMessages_DISPATCH(OBJGPU *pGpu, struct return pKernelNvlink->__knvlinkLogAliDebugMessages__(pGpu, pKernelNvlink); } -static inline NvBool knvlinkIsFloorSweepingNeeded_491d52(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numActiveLinksPerIoctrl, NvU32 numLinksPerIoctrl) { +static inline void knvlinkGetEffectivePeerLinkMask_b3696a(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pRemoteGpu, NvU32 *pPeerLinkMask) { + return; +} + +void knvlinkGetEffectivePeerLinkMask_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pRemoteGpu, NvU32 *pPeerLinkMask); + +static inline void knvlinkGetEffectivePeerLinkMask_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pRemoteGpu, NvU32 *pPeerLinkMask) { + pKernelNvlink->__knvlinkGetEffectivePeerLinkMask__(pGpu, pKernelNvlink, pRemoteGpu, pPeerLinkMask); +} + +static inline NvU32 knvlinkGetNumLinksToBeReducedPerIoctrl_4a4dee(struct KernelNvlink *pKernelNvlink) { + return 0; +} + +NvU32 knvlinkGetNumLinksToBeReducedPerIoctrl_GH100(struct KernelNvlink *pKernelNvlink); + +static inline NvU32 knvlinkGetNumLinksToBeReducedPerIoctrl_DISPATCH(struct KernelNvlink *pKernelNvlink) { + return pKernelNvlink->__knvlinkGetNumLinksToBeReducedPerIoctrl__(pKernelNvlink); +} + +static inline NvBool knvlinkIsBandwidthModeOff_491d52(struct KernelNvlink *pKernelNvlink) { return ((NvBool)(0 != 0)); } -NvBool knvlinkIsFloorSweepingNeeded_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numActiveLinksPerIoctrl, NvU32 numLinksPerIoctrl); +NvBool knvlinkIsBandwidthModeOff_GH100(struct KernelNvlink *pKernelNvlink); -static inline NvBool knvlinkIsFloorSweepingNeeded_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numActiveLinksPerIoctrl, NvU32 numLinksPerIoctrl) { - return pKernelNvlink->__knvlinkIsFloorSweepingNeeded__(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl); +static inline NvBool knvlinkIsBandwidthModeOff_DISPATCH(struct KernelNvlink *pKernelNvlink) { + return pKernelNvlink->__knvlinkIsBandwidthModeOff__(pKernelNvlink); } static inline void knvlinkDirectConnectCheck_b3696a(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { @@ -1573,8 +1586,14 @@ static inline void knvlinkDirectConnectCheck_DISPATCH(OBJGPU *pGpu, struct Kerne pKernelNvlink->__knvlinkDirectConnectCheck__(pGpu, pKernelNvlink); } -static inline NV_STATUS knvlinkReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelNvlink *pEngstate, void *pTunableState) { - return pEngstate->__knvlinkReconcileTunableState__(pGpu, pEngstate, pTunableState); +static inline NvBool knvlinkIsFloorSweepingNeeded_491d52(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numActiveLinksPerIoctrl, NvU32 numLinksPerIoctrl) { + return ((NvBool)(0 != 0)); +} + +NvBool knvlinkIsFloorSweepingNeeded_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numActiveLinksPerIoctrl, NvU32 numLinksPerIoctrl); + +static inline NvBool knvlinkIsFloorSweepingNeeded_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numActiveLinksPerIoctrl, NvU32 numLinksPerIoctrl) { + return pKernelNvlink->__knvlinkIsFloorSweepingNeeded__(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl); } static inline NV_STATUS knvlinkStateInitLocked_DISPATCH(POBJGPU pGpu, struct KernelNvlink *pEngstate) { @@ -1605,26 +1624,6 @@ static inline NV_STATUS knvlinkStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struc return pEngstate->__knvlinkStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS knvlinkGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelNvlink *pEngstate, void *pTunableState) { - return pEngstate->__knvlinkGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS knvlinkCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelNvlink *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__knvlinkCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void knvlinkFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelNvlink *pEngstate, void *pTunableState) { - pEngstate->__knvlinkFreeTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS knvlinkAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelNvlink *pEngstate, void **ppTunableState) { - return pEngstate->__knvlinkAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS knvlinkSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelNvlink *pEngstate, void *pTunableState) { - return pEngstate->__knvlinkSetTunableState__(pGpu, pEngstate, pTunableState); -} - void knvlinkDestruct_IMPL(struct KernelNvlink *arg0); #define __nvoc_knvlinkDestruct(arg0) knvlinkDestruct_IMPL(arg0) diff --git a/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.c b/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.c index c566e4e2d..1e84364b3 100644 --- a/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.c +++ b/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.c @@ -176,7 +176,7 @@ static NV_STATUS __nvoc_thunk_RsResource_ofactxControlLookup(struct OfaContext * return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OfaContext_RsResource.offset), pParams, ppEntry); } -static NV_STATUS __nvoc_thunk_ChannelDescendant_ofactxGetSwMethods(struct OfaContext *pChannelDescendant, METHOD **ppMethods, NvU32 *pNumMethods) { +static NV_STATUS __nvoc_thunk_ChannelDescendant_ofactxGetSwMethods(struct OfaContext *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return chandesGetSwMethods((struct ChannelDescendant *)(((unsigned char *)pChannelDescendant) + __nvoc_rtti_OfaContext_ChannelDescendant.offset), ppMethods, pNumMethods); } @@ -212,6 +212,10 @@ static NV_STATUS __nvoc_thunk_Notifier_ofactxUnregisterEvent(struct OfaContext * return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_OfaContext_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_ofactxControlSerialization_Prologue(struct OfaContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_OfaContext_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_ofactxCanCopy(struct OfaContext *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OfaContext_RsResource.offset)); } @@ -224,6 +228,10 @@ static NV_STATUS __nvoc_thunk_RsResource_ofactxIsDuplicate(struct OfaContext *pR return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OfaContext_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_ofactxControlSerialization_Epilogue(struct OfaContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_OfaContext_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_ofactxGetNotificationListPtr(struct OfaContext *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_OfaContext_Notifier.offset)); } @@ -335,12 +343,16 @@ static void __nvoc_init_funcTable_OfaContext_1(OfaContext *pThis, RmHalspecOwner pThis->__ofactxUnregisterEvent__ = &__nvoc_thunk_Notifier_ofactxUnregisterEvent; + pThis->__ofactxControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_ofactxControlSerialization_Prologue; + pThis->__ofactxCanCopy__ = &__nvoc_thunk_RsResource_ofactxCanCopy; pThis->__ofactxPreDestruct__ = &__nvoc_thunk_RsResource_ofactxPreDestruct; pThis->__ofactxIsDuplicate__ = &__nvoc_thunk_RsResource_ofactxIsDuplicate; + pThis->__ofactxControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_ofactxControlSerialization_Epilogue; + pThis->__ofactxGetNotificationListPtr__ = &__nvoc_thunk_Notifier_ofactxGetNotificationListPtr; pThis->__ofactxGetNotificationShare__ = &__nvoc_thunk_Notifier_ofactxGetNotificationShare; @@ -375,13 +387,16 @@ NV_STATUS __nvoc_objCreate_OfaContext(OfaContext **ppThis, Dynamic *pParent, NvU OfaContext *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(OfaContext)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OfaContext), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OfaContext)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OfaContext); + pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -401,11 +416,17 @@ NV_STATUS __nvoc_objCreate_OfaContext(OfaContext **ppThis, Dynamic *pParent, NvU if (status != NV_OK) goto __nvoc_objCreate_OfaContext_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OfaContext_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OfaContext)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.h b/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.h index 657521f28..105c9eb7d 100644 --- a/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.h +++ b/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.h @@ -70,7 +70,7 @@ struct OfaContext { NV_STATUS (*__ofactxUnmapFrom__)(struct OfaContext *, RS_RES_UNMAP_FROM_PARAMS *); void (*__ofactxControl_Epilogue__)(struct OfaContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__ofactxControlLookup__)(struct OfaContext *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); - NV_STATUS (*__ofactxGetSwMethods__)(struct OfaContext *, METHOD **, NvU32 *); + NV_STATUS (*__ofactxGetSwMethods__)(struct OfaContext *, const METHOD **, NvU32 *); NvHandle (*__ofactxGetInternalObjectHandle__)(struct OfaContext *); NV_STATUS (*__ofactxControl__)(struct OfaContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__ofactxUnmap__)(struct OfaContext *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -79,9 +79,11 @@ struct OfaContext { NvBool (*__ofactxIsSwMethodStalling__)(struct OfaContext *, NvU32); NV_STATUS (*__ofactxControlFilter__)(struct OfaContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__ofactxUnregisterEvent__)(struct OfaContext *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__ofactxControlSerialization_Prologue__)(struct OfaContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__ofactxCanCopy__)(struct OfaContext *); void (*__ofactxPreDestruct__)(struct OfaContext *); NV_STATUS (*__ofactxIsDuplicate__)(struct OfaContext *, NvHandle, NvBool *); + void (*__ofactxControlSerialization_Epilogue__)(struct OfaContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__ofactxGetNotificationListPtr__)(struct OfaContext *); struct NotifShare *(*__ofactxGetNotificationShare__)(struct OfaContext *); NV_STATUS (*__ofactxMap__)(struct OfaContext *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -139,9 +141,11 @@ NV_STATUS __nvoc_objCreate_OfaContext(OfaContext**, Dynamic*, NvU32, struct CALL #define ofactxIsSwMethodStalling(pChannelDescendant, hHandle) ofactxIsSwMethodStalling_DISPATCH(pChannelDescendant, hHandle) #define ofactxControlFilter(pResource, pCallContext, pParams) ofactxControlFilter_DISPATCH(pResource, pCallContext, pParams) #define ofactxUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) ofactxUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define ofactxControlSerialization_Prologue(pResource, pCallContext, pParams) ofactxControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define ofactxCanCopy(pResource) ofactxCanCopy_DISPATCH(pResource) #define ofactxPreDestruct(pResource) ofactxPreDestruct_DISPATCH(pResource) #define ofactxIsDuplicate(pResource, hMemory, pDuplicate) ofactxIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define ofactxControlSerialization_Epilogue(pResource, pCallContext, pParams) ofactxControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define ofactxGetNotificationListPtr(pNotifier) ofactxGetNotificationListPtr_DISPATCH(pNotifier) #define ofactxGetNotificationShare(pNotifier) ofactxGetNotificationShare_DISPATCH(pNotifier) #define ofactxMap(pGpuResource, pCallContext, pParams, pCpuMapping) ofactxMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -229,7 +233,7 @@ static inline NV_STATUS ofactxControlLookup_DISPATCH(struct OfaContext *pResourc return pResource->__ofactxControlLookup__(pResource, pParams, ppEntry); } -static inline NV_STATUS ofactxGetSwMethods_DISPATCH(struct OfaContext *pChannelDescendant, METHOD **ppMethods, NvU32 *pNumMethods) { +static inline NV_STATUS ofactxGetSwMethods_DISPATCH(struct OfaContext *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return pChannelDescendant->__ofactxGetSwMethods__(pChannelDescendant, ppMethods, pNumMethods); } @@ -265,6 +269,10 @@ static inline NV_STATUS ofactxUnregisterEvent_DISPATCH(struct OfaContext *pNotif return pNotifier->__ofactxUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS ofactxControlSerialization_Prologue_DISPATCH(struct OfaContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__ofactxControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool ofactxCanCopy_DISPATCH(struct OfaContext *pResource) { return pResource->__ofactxCanCopy__(pResource); } @@ -277,6 +285,10 @@ static inline NV_STATUS ofactxIsDuplicate_DISPATCH(struct OfaContext *pResource, return pResource->__ofactxIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void ofactxControlSerialization_Epilogue_DISPATCH(struct OfaContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__ofactxControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *ofactxGetNotificationListPtr_DISPATCH(struct OfaContext *pNotifier) { return pNotifier->__ofactxGetNotificationListPtr__(pNotifier); } diff --git a/src/nvidia/generated/g_kernel_rc_nvoc.c b/src/nvidia/generated/g_kernel_rc_nvoc.c index 0baff802e..fed668f80 100644 --- a/src/nvidia/generated/g_kernel_rc_nvoc.c +++ b/src/nvidia/generated/g_kernel_rc_nvoc.c @@ -70,10 +70,6 @@ static NV_STATUS __nvoc_thunk_KernelRc_engstateConstructEngine(struct OBJGPU *pG return krcConstructEngine(pGpu, (struct KernelRc *)(((unsigned char *)pKernelRc) - __nvoc_rtti_KernelRc_OBJENGSTATE.offset), engDescriptor); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_krcReconcileTunableState(POBJGPU pGpu, struct KernelRc *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelRc_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_krcStateLoad(POBJGPU pGpu, struct KernelRc *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelRc_OBJENGSTATE.offset), arg0); } @@ -118,30 +114,10 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_krcStatePreInitUnlocked(POBJGPU pGpu, return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelRc_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_krcGetTunableState(POBJGPU pGpu, struct KernelRc *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelRc_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_krcCompareTunableState(POBJGPU pGpu, struct KernelRc *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelRc_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_krcFreeTunableState(POBJGPU pGpu, struct KernelRc *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelRc_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_krcStatePostLoad(POBJGPU pGpu, struct KernelRc *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelRc_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_krcAllocTunableState(POBJGPU pGpu, struct KernelRc *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelRc_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_krcSetTunableState(POBJGPU pGpu, struct KernelRc *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelRc_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_krcIsPresent(POBJGPU pGpu, struct KernelRc *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelRc_OBJENGSTATE.offset)); } @@ -201,8 +177,6 @@ static void __nvoc_init_funcTable_KernelRc_1(KernelRc *pThis, RmHalspecOwner *pR pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelRc_engstateConstructEngine; - pThis->__krcReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_krcReconcileTunableState; - pThis->__krcStateLoad__ = &__nvoc_thunk_OBJENGSTATE_krcStateLoad; pThis->__krcStateUnload__ = &__nvoc_thunk_OBJENGSTATE_krcStateUnload; @@ -225,18 +199,8 @@ static void __nvoc_init_funcTable_KernelRc_1(KernelRc *pThis, RmHalspecOwner *pR pThis->__krcStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_krcStatePreInitUnlocked; - pThis->__krcGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_krcGetTunableState; - - pThis->__krcCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_krcCompareTunableState; - - pThis->__krcFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_krcFreeTunableState; - pThis->__krcStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_krcStatePostLoad; - pThis->__krcAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_krcAllocTunableState; - - pThis->__krcSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_krcSetTunableState; - pThis->__krcIsPresent__ = &__nvoc_thunk_OBJENGSTATE_krcIsPresent; } @@ -259,13 +223,16 @@ NV_STATUS __nvoc_objCreate_KernelRc(KernelRc **ppThis, Dynamic *pParent, NvU32 c KernelRc *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelRc)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelRc), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelRc)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelRc); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -285,11 +252,17 @@ NV_STATUS __nvoc_objCreate_KernelRc(KernelRc **ppThis, Dynamic *pParent, NvU32 c if (status != NV_OK) goto __nvoc_objCreate_KernelRc_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelRc_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelRc)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_rc_nvoc.h b/src/nvidia/generated/g_kernel_rc_nvoc.h index 2026ec8ed..c7bdf1b68 100644 --- a/src/nvidia/generated/g_kernel_rc_nvoc.h +++ b/src/nvidia/generated/g_kernel_rc_nvoc.h @@ -65,7 +65,6 @@ struct KernelRc { struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; struct KernelRc *__nvoc_pbase_KernelRc; NV_STATUS (*__krcConstructEngine__)(struct OBJGPU *, struct KernelRc *, ENGDESCRIPTOR); - NV_STATUS (*__krcReconcileTunableState__)(POBJGPU, struct KernelRc *, void *); NV_STATUS (*__krcStateLoad__)(POBJGPU, struct KernelRc *, NvU32); NV_STATUS (*__krcStateUnload__)(POBJGPU, struct KernelRc *, NvU32); NV_STATUS (*__krcStateInitLocked__)(POBJGPU, struct KernelRc *); @@ -77,12 +76,7 @@ struct KernelRc { void (*__krcInitMissing__)(POBJGPU, struct KernelRc *); NV_STATUS (*__krcStatePreInitLocked__)(POBJGPU, struct KernelRc *); NV_STATUS (*__krcStatePreInitUnlocked__)(POBJGPU, struct KernelRc *); - NV_STATUS (*__krcGetTunableState__)(POBJGPU, struct KernelRc *, void *); - NV_STATUS (*__krcCompareTunableState__)(POBJGPU, struct KernelRc *, void *, void *); - void (*__krcFreeTunableState__)(POBJGPU, struct KernelRc *, void *); NV_STATUS (*__krcStatePostLoad__)(POBJGPU, struct KernelRc *, NvU32); - NV_STATUS (*__krcAllocTunableState__)(POBJGPU, struct KernelRc *, void **); - NV_STATUS (*__krcSetTunableState__)(POBJGPU, struct KernelRc *, void *); NvBool (*__krcIsPresent__)(POBJGPU, struct KernelRc *); NvBool bRobustChannelsEnabled; NvBool bBreakOnRc; @@ -125,7 +119,6 @@ NV_STATUS __nvoc_objCreate_KernelRc(KernelRc**, Dynamic*, NvU32); __nvoc_objCreate_KernelRc((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) #define krcConstructEngine(pGpu, pKernelRc, engDescriptor) krcConstructEngine_DISPATCH(pGpu, pKernelRc, engDescriptor) -#define krcReconcileTunableState(pGpu, pEngstate, pTunableState) krcReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define krcStateLoad(pGpu, pEngstate, arg0) krcStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define krcStateUnload(pGpu, pEngstate, arg0) krcStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define krcStateInitLocked(pGpu, pEngstate) krcStateInitLocked_DISPATCH(pGpu, pEngstate) @@ -137,12 +130,7 @@ NV_STATUS __nvoc_objCreate_KernelRc(KernelRc**, Dynamic*, NvU32); #define krcInitMissing(pGpu, pEngstate) krcInitMissing_DISPATCH(pGpu, pEngstate) #define krcStatePreInitLocked(pGpu, pEngstate) krcStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define krcStatePreInitUnlocked(pGpu, pEngstate) krcStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define krcGetTunableState(pGpu, pEngstate, pTunableState) krcGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define krcCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) krcCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define krcFreeTunableState(pGpu, pEngstate, pTunableState) krcFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define krcStatePostLoad(pGpu, pEngstate, arg0) krcStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define krcAllocTunableState(pGpu, pEngstate, ppTunableState) krcAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define krcSetTunableState(pGpu, pEngstate, pTunableState) krcSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define krcIsPresent(pGpu, pEngstate) krcIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS krcErrorWriteNotifier_CPU(struct OBJGPU *pGpu, struct KernelRc *pKernelRc, struct KernelChannel *pKernelChannel, NvU32 exceptType, RM_ENGINE_TYPE localRmEngineType, NV_STATUS notifierStatus, NvU32 *pFlushFlags); @@ -329,10 +317,6 @@ static inline NV_STATUS krcConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct return pKernelRc->__krcConstructEngine__(pGpu, pKernelRc, engDescriptor); } -static inline NV_STATUS krcReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelRc *pEngstate, void *pTunableState) { - return pEngstate->__krcReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS krcStateLoad_DISPATCH(POBJGPU pGpu, struct KernelRc *pEngstate, NvU32 arg0) { return pEngstate->__krcStateLoad__(pGpu, pEngstate, arg0); } @@ -377,30 +361,10 @@ static inline NV_STATUS krcStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct Ke return pEngstate->__krcStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS krcGetTunableState_DISPATCH(POBJGPU pGpu, struct KernelRc *pEngstate, void *pTunableState) { - return pEngstate->__krcGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS krcCompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelRc *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__krcCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void krcFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelRc *pEngstate, void *pTunableState) { - pEngstate->__krcFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS krcStatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelRc *pEngstate, NvU32 arg0) { return pEngstate->__krcStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS krcAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelRc *pEngstate, void **ppTunableState) { - return pEngstate->__krcAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS krcSetTunableState_DISPATCH(POBJGPU pGpu, struct KernelRc *pEngstate, void *pTunableState) { - return pEngstate->__krcSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool krcIsPresent_DISPATCH(POBJGPU pGpu, struct KernelRc *pEngstate) { return pEngstate->__krcIsPresent__(pGpu, pEngstate); } diff --git a/src/nvidia/generated/g_kernel_sched_mgr_nvoc.c b/src/nvidia/generated/g_kernel_sched_mgr_nvoc.c index d1a923de2..56df886b4 100644 --- a/src/nvidia/generated/g_kernel_sched_mgr_nvoc.c +++ b/src/nvidia/generated/g_kernel_sched_mgr_nvoc.c @@ -110,13 +110,16 @@ NV_STATUS __nvoc_objCreate_KernelSchedMgr(KernelSchedMgr **ppThis, Dynamic *pPar Object *pParentObj; KernelSchedMgr *pThis; - pThis = portMemAllocNonPaged(sizeof(KernelSchedMgr)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelSchedMgr), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelSchedMgr)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelSchedMgr); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -132,11 +135,17 @@ NV_STATUS __nvoc_objCreate_KernelSchedMgr(KernelSchedMgr **ppThis, Dynamic *pPar if (status != NV_OK) goto __nvoc_objCreate_KernelSchedMgr_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelSchedMgr_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelSchedMgr)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_sec2_nvoc.c b/src/nvidia/generated/g_kernel_sec2_nvoc.c index 8e75e56cc..fc2b0159c 100644 --- a/src/nvidia/generated/g_kernel_sec2_nvoc.c +++ b/src/nvidia/generated/g_kernel_sec2_nvoc.c @@ -17,6 +17,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJENGSTATE; +extern const struct NVOC_CLASS_DEF __nvoc_class_def_IntrService; + extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelFalcon; void __nvoc_init_KernelSec2(KernelSec2*, RmHalspecOwner* ); @@ -44,6 +46,12 @@ static const struct NVOC_RTTI __nvoc_rtti_KernelSec2_OBJENGSTATE = { /*offset=*/ NV_OFFSETOF(KernelSec2, __nvoc_base_OBJENGSTATE), }; +static const struct NVOC_RTTI __nvoc_rtti_KernelSec2_IntrService = { + /*pClassDef=*/ &__nvoc_class_def_IntrService, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelSec2, __nvoc_base_IntrService), +}; + static const struct NVOC_RTTI __nvoc_rtti_KernelSec2_KernelFalcon = { /*pClassDef=*/ &__nvoc_class_def_KernelFalcon, /*dtor=*/ &__nvoc_destructFromBase, @@ -51,10 +59,11 @@ static const struct NVOC_RTTI __nvoc_rtti_KernelSec2_KernelFalcon = { }; static const struct NVOC_CASTINFO __nvoc_castinfo_KernelSec2 = { - /*numRelatives=*/ 4, + /*numRelatives=*/ 5, /*relatives=*/ { &__nvoc_rtti_KernelSec2_KernelSec2, &__nvoc_rtti_KernelSec2_KernelFalcon, + &__nvoc_rtti_KernelSec2_IntrService, &__nvoc_rtti_KernelSec2_OBJENGSTATE, &__nvoc_rtti_KernelSec2_Object, }, @@ -79,18 +88,18 @@ static NV_STATUS __nvoc_thunk_KernelSec2_engstateConstructEngine(struct OBJGPU * return ksec2ConstructEngine(pGpu, (struct KernelSec2 *)(((unsigned char *)pKernelSec2) - __nvoc_rtti_KernelSec2_OBJENGSTATE.offset), arg0); } +static void __nvoc_thunk_KernelSec2_intrservRegisterIntrService(struct OBJGPU *pGpu, struct IntrService *pKernelSec2, IntrServiceRecord pRecords[166]) { + ksec2RegisterIntrService(pGpu, (struct KernelSec2 *)(((unsigned char *)pKernelSec2) - __nvoc_rtti_KernelSec2_IntrService.offset), pRecords); +} + +static NV_STATUS __nvoc_thunk_KernelSec2_intrservServiceNotificationInterrupt(struct OBJGPU *arg0, struct IntrService *arg1, IntrServiceServiceNotificationInterruptArguments *arg2) { + return ksec2ServiceNotificationInterrupt(arg0, (struct KernelSec2 *)(((unsigned char *)arg1) - __nvoc_rtti_KernelSec2_IntrService.offset), arg2); +} + static NV_STATUS __nvoc_thunk_KernelSec2_kflcnResetHw(struct OBJGPU *pGpu, struct KernelFalcon *pKernelSec2) { return ksec2ResetHw(pGpu, (struct KernelSec2 *)(((unsigned char *)pKernelSec2) - __nvoc_rtti_KernelSec2_KernelFalcon.offset)); } -static NvBool __nvoc_thunk_KernelSec2_kflcnIsEngineInReset(struct OBJGPU *pGpu, struct KernelFalcon *pKernelSec2) { - return ksec2IsEngineInReset(pGpu, (struct KernelSec2 *)(((unsigned char *)pKernelSec2) - __nvoc_rtti_KernelSec2_KernelFalcon.offset)); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_ksec2ReconcileTunableState(POBJGPU pGpu, struct KernelSec2 *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelSec2_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_ksec2StateLoad(POBJGPU pGpu, struct KernelSec2 *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelSec2_OBJENGSTATE.offset), arg0); } @@ -135,34 +144,22 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_ksec2StatePreInitUnlocked(POBJGPU pGpu return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelSec2_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_ksec2GetTunableState(POBJGPU pGpu, struct KernelSec2 *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelSec2_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_ksec2CompareTunableState(POBJGPU pGpu, struct KernelSec2 *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelSec2_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_ksec2FreeTunableState(POBJGPU pGpu, struct KernelSec2 *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelSec2_OBJENGSTATE.offset), pTunableState); +static NvBool __nvoc_thunk_IntrService_ksec2ClearInterrupt(struct OBJGPU *pGpu, struct KernelSec2 *pIntrService, IntrServiceClearInterruptArguments *pParams) { + return intrservClearInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_KernelSec2_IntrService.offset), pParams); } static NV_STATUS __nvoc_thunk_OBJENGSTATE_ksec2StatePostLoad(POBJGPU pGpu, struct KernelSec2 *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelSec2_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_ksec2AllocTunableState(POBJGPU pGpu, struct KernelSec2 *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelSec2_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_ksec2SetTunableState(POBJGPU pGpu, struct KernelSec2 *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelSec2_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_ksec2IsPresent(POBJGPU pGpu, struct KernelSec2 *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelSec2_OBJENGSTATE.offset)); } +static NvU32 __nvoc_thunk_IntrService_ksec2ServiceInterrupt(struct OBJGPU *pGpu, struct KernelSec2 *pIntrService, IntrServiceServiceInterruptArguments *pParams) { + return intrservServiceInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_KernelSec2_IntrService.offset), pParams); +} + const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelSec2 = { /*numEntries=*/ 0, @@ -170,10 +167,12 @@ const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelSec2 = }; void __nvoc_dtor_OBJENGSTATE(OBJENGSTATE*); +void __nvoc_dtor_IntrService(IntrService*); void __nvoc_dtor_KernelFalcon(KernelFalcon*); void __nvoc_dtor_KernelSec2(KernelSec2 *pThis) { __nvoc_ksec2Destruct(pThis); __nvoc_dtor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); + __nvoc_dtor_IntrService(&pThis->__nvoc_base_IntrService); __nvoc_dtor_KernelFalcon(&pThis->__nvoc_base_KernelFalcon); PORT_UNREFERENCED_VARIABLE(pThis); } @@ -192,17 +191,22 @@ void __nvoc_init_dataField_KernelSec2(KernelSec2 *pThis, RmHalspecOwner *pRmhals } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); +NV_STATUS __nvoc_ctor_IntrService(IntrService* ); NV_STATUS __nvoc_ctor_KernelFalcon(KernelFalcon* , RmHalspecOwner* ); NV_STATUS __nvoc_ctor_KernelSec2(KernelSec2 *pThis, RmHalspecOwner *pRmhalspecowner) { NV_STATUS status = NV_OK; status = __nvoc_ctor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); if (status != NV_OK) goto __nvoc_ctor_KernelSec2_fail_OBJENGSTATE; + status = __nvoc_ctor_IntrService(&pThis->__nvoc_base_IntrService); + if (status != NV_OK) goto __nvoc_ctor_KernelSec2_fail_IntrService; status = __nvoc_ctor_KernelFalcon(&pThis->__nvoc_base_KernelFalcon, pRmhalspecowner); if (status != NV_OK) goto __nvoc_ctor_KernelSec2_fail_KernelFalcon; __nvoc_init_dataField_KernelSec2(pThis, pRmhalspecowner); goto __nvoc_ctor_KernelSec2_exit; // Success __nvoc_ctor_KernelSec2_fail_KernelFalcon: + __nvoc_dtor_IntrService(&pThis->__nvoc_base_IntrService); +__nvoc_ctor_KernelSec2_fail_IntrService: __nvoc_dtor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); __nvoc_ctor_KernelSec2_fail_OBJENGSTATE: __nvoc_ctor_KernelSec2_exit: @@ -228,6 +232,18 @@ static void __nvoc_init_funcTable_KernelSec2_1(KernelSec2 *pThis, RmHalspecOwner pThis->__ksec2ConstructEngine__ = &ksec2ConstructEngine_IMPL; } + // Hal function -- ksec2RegisterIntrService + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + pThis->__ksec2RegisterIntrService__ = &ksec2RegisterIntrService_IMPL; + } + + // Hal function -- ksec2ServiceNotificationInterrupt + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + pThis->__ksec2ServiceNotificationInterrupt__ = &ksec2ServiceNotificationInterrupt_IMPL; + } + // Hal function -- ksec2ConfigureFalcon if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { @@ -239,40 +255,19 @@ static void __nvoc_init_funcTable_KernelSec2_1(KernelSec2 *pThis, RmHalspecOwner { pThis->__ksec2ConfigureFalcon__ = &ksec2ConfigureFalcon_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__ksec2ConfigureFalcon__ = &ksec2ConfigureFalcon_GA102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__ksec2ConfigureFalcon__ = &ksec2ConfigureFalcon_f2d351; - } } // Hal function -- ksec2ResetHw if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__ksec2ResetHw__ = &ksec2ResetHw_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__ksec2ResetHw__ = &ksec2ResetHw_5baef9; - } - } - - // Hal function -- ksec2IsEngineInReset - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ - { - pThis->__ksec2IsEngineInReset__ = &ksec2IsEngineInReset_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__ksec2IsEngineInReset__ = &ksec2IsEngineInReset_108313; - } } // Hal function -- ksec2ReadUcodeFuseVersion @@ -329,12 +324,12 @@ static void __nvoc_init_funcTable_KernelSec2_1(KernelSec2 *pThis, RmHalspecOwner pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelSec2_engstateConstructEngine; + pThis->__nvoc_base_IntrService.__intrservRegisterIntrService__ = &__nvoc_thunk_KernelSec2_intrservRegisterIntrService; + + pThis->__nvoc_base_IntrService.__intrservServiceNotificationInterrupt__ = &__nvoc_thunk_KernelSec2_intrservServiceNotificationInterrupt; + pThis->__nvoc_base_KernelFalcon.__kflcnResetHw__ = &__nvoc_thunk_KernelSec2_kflcnResetHw; - pThis->__nvoc_base_KernelFalcon.__kflcnIsEngineInReset__ = &__nvoc_thunk_KernelSec2_kflcnIsEngineInReset; - - pThis->__ksec2ReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_ksec2ReconcileTunableState; - pThis->__ksec2StateLoad__ = &__nvoc_thunk_OBJENGSTATE_ksec2StateLoad; pThis->__ksec2StateUnload__ = &__nvoc_thunk_OBJENGSTATE_ksec2StateUnload; @@ -357,19 +352,13 @@ static void __nvoc_init_funcTable_KernelSec2_1(KernelSec2 *pThis, RmHalspecOwner pThis->__ksec2StatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_ksec2StatePreInitUnlocked; - pThis->__ksec2GetTunableState__ = &__nvoc_thunk_OBJENGSTATE_ksec2GetTunableState; - - pThis->__ksec2CompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_ksec2CompareTunableState; - - pThis->__ksec2FreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_ksec2FreeTunableState; + pThis->__ksec2ClearInterrupt__ = &__nvoc_thunk_IntrService_ksec2ClearInterrupt; pThis->__ksec2StatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_ksec2StatePostLoad; - pThis->__ksec2AllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_ksec2AllocTunableState; - - pThis->__ksec2SetTunableState__ = &__nvoc_thunk_OBJENGSTATE_ksec2SetTunableState; - pThis->__ksec2IsPresent__ = &__nvoc_thunk_OBJENGSTATE_ksec2IsPresent; + + pThis->__ksec2ServiceInterrupt__ = &__nvoc_thunk_IntrService_ksec2ServiceInterrupt; } void __nvoc_init_funcTable_KernelSec2(KernelSec2 *pThis, RmHalspecOwner *pRmhalspecowner) { @@ -377,13 +366,16 @@ void __nvoc_init_funcTable_KernelSec2(KernelSec2 *pThis, RmHalspecOwner *pRmhals } void __nvoc_init_OBJENGSTATE(OBJENGSTATE*); +void __nvoc_init_IntrService(IntrService*); void __nvoc_init_KernelFalcon(KernelFalcon*, RmHalspecOwner* ); void __nvoc_init_KernelSec2(KernelSec2 *pThis, RmHalspecOwner *pRmhalspecowner) { pThis->__nvoc_pbase_KernelSec2 = pThis; pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object; pThis->__nvoc_pbase_OBJENGSTATE = &pThis->__nvoc_base_OBJENGSTATE; + pThis->__nvoc_pbase_IntrService = &pThis->__nvoc_base_IntrService; pThis->__nvoc_pbase_KernelFalcon = &pThis->__nvoc_base_KernelFalcon; __nvoc_init_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); + __nvoc_init_IntrService(&pThis->__nvoc_base_IntrService); __nvoc_init_KernelFalcon(&pThis->__nvoc_base_KernelFalcon, pRmhalspecowner); __nvoc_init_funcTable_KernelSec2(pThis, pRmhalspecowner); } @@ -394,13 +386,16 @@ NV_STATUS __nvoc_objCreate_KernelSec2(KernelSec2 **ppThis, Dynamic *pParent, NvU KernelSec2 *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(KernelSec2)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelSec2), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelSec2)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelSec2); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -420,11 +415,17 @@ NV_STATUS __nvoc_objCreate_KernelSec2(KernelSec2 **ppThis, Dynamic *pParent, NvU if (status != NV_OK) goto __nvoc_objCreate_KernelSec2_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelSec2_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelSec2)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_sec2_nvoc.h b/src/nvidia/generated/g_kernel_sec2_nvoc.h index 4a371ff5f..78a94d49c 100644 --- a/src/nvidia/generated/g_kernel_sec2_nvoc.h +++ b/src/nvidia/generated/g_kernel_sec2_nvoc.h @@ -52,20 +52,22 @@ typedef struct _def_rm_flcn_bl_desc RM_FLCN_BL_DESC; struct KernelSec2 { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; + struct IntrService __nvoc_base_IntrService; struct KernelFalcon __nvoc_base_KernelFalcon; struct Object *__nvoc_pbase_Object; struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; + struct IntrService *__nvoc_pbase_IntrService; struct KernelFalcon *__nvoc_pbase_KernelFalcon; struct KernelSec2 *__nvoc_pbase_KernelSec2; NV_STATUS (*__ksec2ConstructEngine__)(struct OBJGPU *, struct KernelSec2 *, ENGDESCRIPTOR); + void (*__ksec2RegisterIntrService__)(struct OBJGPU *, struct KernelSec2 *, IntrServiceRecord *); + NV_STATUS (*__ksec2ServiceNotificationInterrupt__)(struct OBJGPU *, struct KernelSec2 *, IntrServiceServiceNotificationInterruptArguments *); void (*__ksec2ConfigureFalcon__)(struct OBJGPU *, struct KernelSec2 *); NV_STATUS (*__ksec2ResetHw__)(struct OBJGPU *, struct KernelSec2 *); - NvBool (*__ksec2IsEngineInReset__)(struct OBJGPU *, struct KernelSec2 *); NvU32 (*__ksec2ReadUcodeFuseVersion__)(struct OBJGPU *, struct KernelSec2 *, NvU32); const BINDATA_ARCHIVE *(*__ksec2GetBinArchiveBlUcode__)(struct OBJGPU *, struct KernelSec2 *); NV_STATUS (*__ksec2GetGenericBlUcode__)(struct OBJGPU *, struct KernelSec2 *, const RM_FLCN_BL_DESC **, const NvU8 **); const BINDATA_ARCHIVE *(*__ksec2GetBinArchiveSecurescrubUcode__)(struct OBJGPU *, struct KernelSec2 *); - NV_STATUS (*__ksec2ReconcileTunableState__)(POBJGPU, struct KernelSec2 *, void *); NV_STATUS (*__ksec2StateLoad__)(POBJGPU, struct KernelSec2 *, NvU32); NV_STATUS (*__ksec2StateUnload__)(POBJGPU, struct KernelSec2 *, NvU32); NV_STATUS (*__ksec2StateInitLocked__)(POBJGPU, struct KernelSec2 *); @@ -77,13 +79,10 @@ struct KernelSec2 { void (*__ksec2InitMissing__)(POBJGPU, struct KernelSec2 *); NV_STATUS (*__ksec2StatePreInitLocked__)(POBJGPU, struct KernelSec2 *); NV_STATUS (*__ksec2StatePreInitUnlocked__)(POBJGPU, struct KernelSec2 *); - NV_STATUS (*__ksec2GetTunableState__)(POBJGPU, struct KernelSec2 *, void *); - NV_STATUS (*__ksec2CompareTunableState__)(POBJGPU, struct KernelSec2 *, void *, void *); - void (*__ksec2FreeTunableState__)(POBJGPU, struct KernelSec2 *, void *); + NvBool (*__ksec2ClearInterrupt__)(struct OBJGPU *, struct KernelSec2 *, IntrServiceClearInterruptArguments *); NV_STATUS (*__ksec2StatePostLoad__)(POBJGPU, struct KernelSec2 *, NvU32); - NV_STATUS (*__ksec2AllocTunableState__)(POBJGPU, struct KernelSec2 *, void **); - NV_STATUS (*__ksec2SetTunableState__)(POBJGPU, struct KernelSec2 *, void *); NvBool (*__ksec2IsPresent__)(POBJGPU, struct KernelSec2 *); + NvU32 (*__ksec2ServiceInterrupt__)(struct OBJGPU *, struct KernelSec2 *, IntrServiceServiceInterruptArguments *); const RM_FLCN_BL_DESC *pGenericBlUcodeDesc; const NvU8 *pGenericBlUcodeImg; }; @@ -120,12 +119,14 @@ NV_STATUS __nvoc_objCreate_KernelSec2(KernelSec2**, Dynamic*, NvU32); #define ksec2ConstructEngine(pGpu, pKernelSec2, arg0) ksec2ConstructEngine_DISPATCH(pGpu, pKernelSec2, arg0) #define ksec2ConstructEngine_HAL(pGpu, pKernelSec2, arg0) ksec2ConstructEngine_DISPATCH(pGpu, pKernelSec2, arg0) +#define ksec2RegisterIntrService(pGpu, pKernelSec2, pRecords) ksec2RegisterIntrService_DISPATCH(pGpu, pKernelSec2, pRecords) +#define ksec2RegisterIntrService_HAL(pGpu, pKernelSec2, pRecords) ksec2RegisterIntrService_DISPATCH(pGpu, pKernelSec2, pRecords) +#define ksec2ServiceNotificationInterrupt(arg0, arg1, arg2) ksec2ServiceNotificationInterrupt_DISPATCH(arg0, arg1, arg2) +#define ksec2ServiceNotificationInterrupt_HAL(arg0, arg1, arg2) ksec2ServiceNotificationInterrupt_DISPATCH(arg0, arg1, arg2) #define ksec2ConfigureFalcon(pGpu, pKernelSec2) ksec2ConfigureFalcon_DISPATCH(pGpu, pKernelSec2) #define ksec2ConfigureFalcon_HAL(pGpu, pKernelSec2) ksec2ConfigureFalcon_DISPATCH(pGpu, pKernelSec2) #define ksec2ResetHw(pGpu, pKernelSec2) ksec2ResetHw_DISPATCH(pGpu, pKernelSec2) #define ksec2ResetHw_HAL(pGpu, pKernelSec2) ksec2ResetHw_DISPATCH(pGpu, pKernelSec2) -#define ksec2IsEngineInReset(pGpu, pKernelSec2) ksec2IsEngineInReset_DISPATCH(pGpu, pKernelSec2) -#define ksec2IsEngineInReset_HAL(pGpu, pKernelSec2) ksec2IsEngineInReset_DISPATCH(pGpu, pKernelSec2) #define ksec2ReadUcodeFuseVersion(pGpu, pKernelSec2, ucodeId) ksec2ReadUcodeFuseVersion_DISPATCH(pGpu, pKernelSec2, ucodeId) #define ksec2ReadUcodeFuseVersion_HAL(pGpu, pKernelSec2, ucodeId) ksec2ReadUcodeFuseVersion_DISPATCH(pGpu, pKernelSec2, ucodeId) #define ksec2GetBinArchiveBlUcode(pGpu, pKernelSec2) ksec2GetBinArchiveBlUcode_DISPATCH(pGpu, pKernelSec2) @@ -134,7 +135,6 @@ NV_STATUS __nvoc_objCreate_KernelSec2(KernelSec2**, Dynamic*, NvU32); #define ksec2GetGenericBlUcode_HAL(pGpu, pKernelSec2, ppDesc, ppImg) ksec2GetGenericBlUcode_DISPATCH(pGpu, pKernelSec2, ppDesc, ppImg) #define ksec2GetBinArchiveSecurescrubUcode(pGpu, pKernelSec2) ksec2GetBinArchiveSecurescrubUcode_DISPATCH(pGpu, pKernelSec2) #define ksec2GetBinArchiveSecurescrubUcode_HAL(pGpu, pKernelSec2) ksec2GetBinArchiveSecurescrubUcode_DISPATCH(pGpu, pKernelSec2) -#define ksec2ReconcileTunableState(pGpu, pEngstate, pTunableState) ksec2ReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define ksec2StateLoad(pGpu, pEngstate, arg0) ksec2StateLoad_DISPATCH(pGpu, pEngstate, arg0) #define ksec2StateUnload(pGpu, pEngstate, arg0) ksec2StateUnload_DISPATCH(pGpu, pEngstate, arg0) #define ksec2StateInitLocked(pGpu, pEngstate) ksec2StateInitLocked_DISPATCH(pGpu, pEngstate) @@ -146,53 +146,44 @@ NV_STATUS __nvoc_objCreate_KernelSec2(KernelSec2**, Dynamic*, NvU32); #define ksec2InitMissing(pGpu, pEngstate) ksec2InitMissing_DISPATCH(pGpu, pEngstate) #define ksec2StatePreInitLocked(pGpu, pEngstate) ksec2StatePreInitLocked_DISPATCH(pGpu, pEngstate) #define ksec2StatePreInitUnlocked(pGpu, pEngstate) ksec2StatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define ksec2GetTunableState(pGpu, pEngstate, pTunableState) ksec2GetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define ksec2CompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) ksec2CompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define ksec2FreeTunableState(pGpu, pEngstate, pTunableState) ksec2FreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) +#define ksec2ClearInterrupt(pGpu, pIntrService, pParams) ksec2ClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define ksec2StatePostLoad(pGpu, pEngstate, arg0) ksec2StatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define ksec2AllocTunableState(pGpu, pEngstate, ppTunableState) ksec2AllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define ksec2SetTunableState(pGpu, pEngstate, pTunableState) ksec2SetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define ksec2IsPresent(pGpu, pEngstate) ksec2IsPresent_DISPATCH(pGpu, pEngstate) +#define ksec2ServiceInterrupt(pGpu, pIntrService, pParams) ksec2ServiceInterrupt_DISPATCH(pGpu, pIntrService, pParams) NV_STATUS ksec2ConstructEngine_IMPL(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, ENGDESCRIPTOR arg0); static inline NV_STATUS ksec2ConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, ENGDESCRIPTOR arg0) { return pKernelSec2->__ksec2ConstructEngine__(pGpu, pKernelSec2, arg0); } +void ksec2RegisterIntrService_IMPL(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, IntrServiceRecord pRecords[166]); + +static inline void ksec2RegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, IntrServiceRecord pRecords[166]) { + pKernelSec2->__ksec2RegisterIntrService__(pGpu, pKernelSec2, pRecords); +} + +NV_STATUS ksec2ServiceNotificationInterrupt_IMPL(struct OBJGPU *arg0, struct KernelSec2 *arg1, IntrServiceServiceNotificationInterruptArguments *arg2); + +static inline NV_STATUS ksec2ServiceNotificationInterrupt_DISPATCH(struct OBJGPU *arg0, struct KernelSec2 *arg1, IntrServiceServiceNotificationInterruptArguments *arg2) { + return arg1->__ksec2ServiceNotificationInterrupt__(arg0, arg1, arg2); +} + void ksec2ConfigureFalcon_TU102(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2); void ksec2ConfigureFalcon_GA100(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2); void ksec2ConfigureFalcon_GA102(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2); -static inline void ksec2ConfigureFalcon_f2d351(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2) { - NV_ASSERT_PRECOMP(0); -} - static inline void ksec2ConfigureFalcon_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2) { pKernelSec2->__ksec2ConfigureFalcon__(pGpu, pKernelSec2); } NV_STATUS ksec2ResetHw_TU102(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2); -static inline NV_STATUS ksec2ResetHw_5baef9(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2) { - NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); -} - static inline NV_STATUS ksec2ResetHw_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2) { return pKernelSec2->__ksec2ResetHw__(pGpu, pKernelSec2); } -NvBool ksec2IsEngineInReset_TU102(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2); - -static inline NvBool ksec2IsEngineInReset_108313(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2) { - NV_ASSERT_OR_RETURN_PRECOMP(0, ((NvBool)(0 != 0))); -} - -static inline NvBool ksec2IsEngineInReset_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2) { - return pKernelSec2->__ksec2IsEngineInReset__(pGpu, pKernelSec2); -} - static inline NvU32 ksec2ReadUcodeFuseVersion_b2b553(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, NvU32 ucodeId) { return 0; } @@ -233,10 +224,6 @@ static inline const BINDATA_ARCHIVE *ksec2GetBinArchiveSecurescrubUcode_DISPATCH return pKernelSec2->__ksec2GetBinArchiveSecurescrubUcode__(pGpu, pKernelSec2); } -static inline NV_STATUS ksec2ReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate, void *pTunableState) { - return pEngstate->__ksec2ReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS ksec2StateLoad_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate, NvU32 arg0) { return pEngstate->__ksec2StateLoad__(pGpu, pEngstate, arg0); } @@ -281,34 +268,22 @@ static inline NV_STATUS ksec2StatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct return pEngstate->__ksec2StatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS ksec2GetTunableState_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate, void *pTunableState) { - return pEngstate->__ksec2GetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS ksec2CompareTunableState_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__ksec2CompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void ksec2FreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate, void *pTunableState) { - pEngstate->__ksec2FreeTunableState__(pGpu, pEngstate, pTunableState); +static inline NvBool ksec2ClearInterrupt_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pIntrService, IntrServiceClearInterruptArguments *pParams) { + return pIntrService->__ksec2ClearInterrupt__(pGpu, pIntrService, pParams); } static inline NV_STATUS ksec2StatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate, NvU32 arg0) { return pEngstate->__ksec2StatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS ksec2AllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate, void **ppTunableState) { - return pEngstate->__ksec2AllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS ksec2SetTunableState_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate, void *pTunableState) { - return pEngstate->__ksec2SetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool ksec2IsPresent_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate) { return pEngstate->__ksec2IsPresent__(pGpu, pEngstate); } +static inline NvU32 ksec2ServiceInterrupt_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pIntrService, IntrServiceServiceInterruptArguments *pParams) { + return pIntrService->__ksec2ServiceInterrupt__(pGpu, pIntrService, pParams); +} + void ksec2Destruct_IMPL(struct KernelSec2 *pKernelSec2); #define __nvoc_ksec2Destruct(pKernelSec2) ksec2Destruct_IMPL(pKernelSec2) diff --git a/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.c b/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.c index cf2094ce1..0c4813668 100644 --- a/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.c +++ b/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.c @@ -144,13 +144,16 @@ NV_STATUS __nvoc_objCreate_RmDebuggerSession(RmDebuggerSession **ppThis, Dynamic Object *pParentObj; RmDebuggerSession *pThis; - pThis = portMemAllocNonPaged(sizeof(RmDebuggerSession)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RmDebuggerSession), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(RmDebuggerSession)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RmDebuggerSession); + pThis->__nvoc_base_RsSession.__nvoc_base_RsShared.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -166,11 +169,17 @@ NV_STATUS __nvoc_objCreate_RmDebuggerSession(RmDebuggerSession **ppThis, Dynamic if (status != NV_OK) goto __nvoc_objCreate_RmDebuggerSession_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_RmDebuggerSession_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(RmDebuggerSession)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -298,16 +307,16 @@ static NvBool __nvoc_thunk_GpuResource_ksmdbgssnShareCallback(struct KernelSMDeb return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelSMDebuggerSession_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_RsResource_ksmdbgssnMapTo(struct KernelSMDebuggerSession *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelSMDebuggerSession_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_ksmdbgssnCheckMemInterUnmap(struct KernelSMDebuggerSession *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelSMDebuggerSession_RmResource.offset), bSubdeviceHandleProvided); } static NV_STATUS __nvoc_thunk_Notifier_ksmdbgssnGetOrAllocNotifShare(struct KernelSMDebuggerSession *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelSMDebuggerSession_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); } -static NV_STATUS __nvoc_thunk_RmResource_ksmdbgssnCheckMemInterUnmap(struct KernelSMDebuggerSession *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelSMDebuggerSession_RmResource.offset), bSubdeviceHandleProvided); +static NV_STATUS __nvoc_thunk_RsResource_ksmdbgssnMapTo(struct KernelSMDebuggerSession *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelSMDebuggerSession_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_GpuResource_ksmdbgssnGetMapAddrSpace(struct KernelSMDebuggerSession *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -370,6 +379,10 @@ static NV_STATUS __nvoc_thunk_Notifier_ksmdbgssnUnregisterEvent(struct KernelSMD return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelSMDebuggerSession_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_ksmdbgssnControlSerialization_Prologue(struct KernelSMDebuggerSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelSMDebuggerSession_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_ksmdbgssnCanCopy(struct KernelSMDebuggerSession *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelSMDebuggerSession_RsResource.offset)); } @@ -382,6 +395,10 @@ static NV_STATUS __nvoc_thunk_RsResource_ksmdbgssnIsDuplicate(struct KernelSMDeb return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelSMDebuggerSession_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_ksmdbgssnControlSerialization_Epilogue(struct KernelSMDebuggerSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelSMDebuggerSession_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_ksmdbgssnGetNotificationListPtr(struct KernelSMDebuggerSession *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelSMDebuggerSession_Notifier.offset)); } @@ -976,11 +993,11 @@ static void __nvoc_init_funcTable_KernelSMDebuggerSession_1(KernelSMDebuggerSess pThis->__ksmdbgssnShareCallback__ = &__nvoc_thunk_GpuResource_ksmdbgssnShareCallback; - pThis->__ksmdbgssnMapTo__ = &__nvoc_thunk_RsResource_ksmdbgssnMapTo; + pThis->__ksmdbgssnCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_ksmdbgssnCheckMemInterUnmap; pThis->__ksmdbgssnGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_ksmdbgssnGetOrAllocNotifShare; - pThis->__ksmdbgssnCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_ksmdbgssnCheckMemInterUnmap; + pThis->__ksmdbgssnMapTo__ = &__nvoc_thunk_RsResource_ksmdbgssnMapTo; pThis->__ksmdbgssnGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_ksmdbgssnGetMapAddrSpace; @@ -1012,12 +1029,16 @@ static void __nvoc_init_funcTable_KernelSMDebuggerSession_1(KernelSMDebuggerSess pThis->__ksmdbgssnUnregisterEvent__ = &__nvoc_thunk_Notifier_ksmdbgssnUnregisterEvent; + pThis->__ksmdbgssnControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_ksmdbgssnControlSerialization_Prologue; + pThis->__ksmdbgssnCanCopy__ = &__nvoc_thunk_RsResource_ksmdbgssnCanCopy; pThis->__ksmdbgssnPreDestruct__ = &__nvoc_thunk_RsResource_ksmdbgssnPreDestruct; pThis->__ksmdbgssnIsDuplicate__ = &__nvoc_thunk_RsResource_ksmdbgssnIsDuplicate; + pThis->__ksmdbgssnControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_ksmdbgssnControlSerialization_Epilogue; + pThis->__ksmdbgssnGetNotificationListPtr__ = &__nvoc_thunk_Notifier_ksmdbgssnGetNotificationListPtr; pThis->__ksmdbgssnGetNotificationShare__ = &__nvoc_thunk_Notifier_ksmdbgssnGetNotificationShare; @@ -1052,13 +1073,16 @@ NV_STATUS __nvoc_objCreate_KernelSMDebuggerSession(KernelSMDebuggerSession **ppT Object *pParentObj; KernelSMDebuggerSession *pThis; - pThis = portMemAllocNonPaged(sizeof(KernelSMDebuggerSession)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelSMDebuggerSession), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelSMDebuggerSession)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelSMDebuggerSession); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -1074,11 +1098,17 @@ NV_STATUS __nvoc_objCreate_KernelSMDebuggerSession(KernelSMDebuggerSession **ppT if (status != NV_OK) goto __nvoc_objCreate_KernelSMDebuggerSession_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelSMDebuggerSession_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelSMDebuggerSession)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.h b/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.h index efa1bd3f7..a88c70c88 100644 --- a/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.h +++ b/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.h @@ -186,9 +186,9 @@ struct KernelSMDebuggerSession { NV_STATUS (*__ksmdbgssnCtrlCmdDebugWriteBatchMemory__)(struct KernelSMDebuggerSession *, NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS *); NV_STATUS (*__ksmdbgssnCtrlCmdDebugReadMMUFaultInfo__)(struct KernelSMDebuggerSession *, NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS *); NvBool (*__ksmdbgssnShareCallback__)(struct KernelSMDebuggerSession *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__ksmdbgssnMapTo__)(struct KernelSMDebuggerSession *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__ksmdbgssnGetOrAllocNotifShare__)(struct KernelSMDebuggerSession *, NvHandle, NvHandle, struct NotifShare **); NV_STATUS (*__ksmdbgssnCheckMemInterUnmap__)(struct KernelSMDebuggerSession *, NvBool); + NV_STATUS (*__ksmdbgssnGetOrAllocNotifShare__)(struct KernelSMDebuggerSession *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__ksmdbgssnMapTo__)(struct KernelSMDebuggerSession *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__ksmdbgssnGetMapAddrSpace__)(struct KernelSMDebuggerSession *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); void (*__ksmdbgssnSetNotificationShare__)(struct KernelSMDebuggerSession *, struct NotifShare *); NvU32 (*__ksmdbgssnGetRefCount__)(struct KernelSMDebuggerSession *); @@ -204,9 +204,11 @@ struct KernelSMDebuggerSession { NV_STATUS (*__ksmdbgssnGetMemoryMappingDescriptor__)(struct KernelSMDebuggerSession *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__ksmdbgssnControlFilter__)(struct KernelSMDebuggerSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__ksmdbgssnUnregisterEvent__)(struct KernelSMDebuggerSession *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__ksmdbgssnControlSerialization_Prologue__)(struct KernelSMDebuggerSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__ksmdbgssnCanCopy__)(struct KernelSMDebuggerSession *); void (*__ksmdbgssnPreDestruct__)(struct KernelSMDebuggerSession *); NV_STATUS (*__ksmdbgssnIsDuplicate__)(struct KernelSMDebuggerSession *, NvHandle, NvBool *); + void (*__ksmdbgssnControlSerialization_Epilogue__)(struct KernelSMDebuggerSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__ksmdbgssnGetNotificationListPtr__)(struct KernelSMDebuggerSession *); struct NotifShare *(*__ksmdbgssnGetNotificationShare__)(struct KernelSMDebuggerSession *); NV_STATUS (*__ksmdbgssnMap__)(struct KernelSMDebuggerSession *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -283,9 +285,9 @@ NV_STATUS __nvoc_objCreate_KernelSMDebuggerSession(KernelSMDebuggerSession**, Dy #define ksmdbgssnCtrlCmdDebugWriteBatchMemory(arg0, arg1) ksmdbgssnCtrlCmdDebugWriteBatchMemory_DISPATCH(arg0, arg1) #define ksmdbgssnCtrlCmdDebugReadMMUFaultInfo(arg0, arg1) ksmdbgssnCtrlCmdDebugReadMMUFaultInfo_DISPATCH(arg0, arg1) #define ksmdbgssnShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) ksmdbgssnShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define ksmdbgssnMapTo(pResource, pParams) ksmdbgssnMapTo_DISPATCH(pResource, pParams) -#define ksmdbgssnGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) ksmdbgssnGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) #define ksmdbgssnCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) ksmdbgssnCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define ksmdbgssnGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) ksmdbgssnGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define ksmdbgssnMapTo(pResource, pParams) ksmdbgssnMapTo_DISPATCH(pResource, pParams) #define ksmdbgssnGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) ksmdbgssnGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) #define ksmdbgssnSetNotificationShare(pNotifier, pNotifShare) ksmdbgssnSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define ksmdbgssnGetRefCount(pResource) ksmdbgssnGetRefCount_DISPATCH(pResource) @@ -301,9 +303,11 @@ NV_STATUS __nvoc_objCreate_KernelSMDebuggerSession(KernelSMDebuggerSession**, Dy #define ksmdbgssnGetMemoryMappingDescriptor(pRmResource, ppMemDesc) ksmdbgssnGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define ksmdbgssnControlFilter(pResource, pCallContext, pParams) ksmdbgssnControlFilter_DISPATCH(pResource, pCallContext, pParams) #define ksmdbgssnUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) ksmdbgssnUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define ksmdbgssnControlSerialization_Prologue(pResource, pCallContext, pParams) ksmdbgssnControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define ksmdbgssnCanCopy(pResource) ksmdbgssnCanCopy_DISPATCH(pResource) #define ksmdbgssnPreDestruct(pResource) ksmdbgssnPreDestruct_DISPATCH(pResource) #define ksmdbgssnIsDuplicate(pResource, hMemory, pDuplicate) ksmdbgssnIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define ksmdbgssnControlSerialization_Epilogue(pResource, pCallContext, pParams) ksmdbgssnControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define ksmdbgssnGetNotificationListPtr(pNotifier) ksmdbgssnGetNotificationListPtr_DISPATCH(pNotifier) #define ksmdbgssnGetNotificationShare(pNotifier) ksmdbgssnGetNotificationShare_DISPATCH(pNotifier) #define ksmdbgssnMap(pGpuResource, pCallContext, pParams, pCpuMapping) ksmdbgssnMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -518,16 +522,16 @@ static inline NvBool ksmdbgssnShareCallback_DISPATCH(struct KernelSMDebuggerSess return pGpuResource->__ksmdbgssnShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS ksmdbgssnMapTo_DISPATCH(struct KernelSMDebuggerSession *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__ksmdbgssnMapTo__(pResource, pParams); +static inline NV_STATUS ksmdbgssnCheckMemInterUnmap_DISPATCH(struct KernelSMDebuggerSession *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__ksmdbgssnCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } static inline NV_STATUS ksmdbgssnGetOrAllocNotifShare_DISPATCH(struct KernelSMDebuggerSession *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return pNotifier->__ksmdbgssnGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); } -static inline NV_STATUS ksmdbgssnCheckMemInterUnmap_DISPATCH(struct KernelSMDebuggerSession *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__ksmdbgssnCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline NV_STATUS ksmdbgssnMapTo_DISPATCH(struct KernelSMDebuggerSession *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__ksmdbgssnMapTo__(pResource, pParams); } static inline NV_STATUS ksmdbgssnGetMapAddrSpace_DISPATCH(struct KernelSMDebuggerSession *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -590,6 +594,10 @@ static inline NV_STATUS ksmdbgssnUnregisterEvent_DISPATCH(struct KernelSMDebugge return pNotifier->__ksmdbgssnUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS ksmdbgssnControlSerialization_Prologue_DISPATCH(struct KernelSMDebuggerSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__ksmdbgssnControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool ksmdbgssnCanCopy_DISPATCH(struct KernelSMDebuggerSession *pResource) { return pResource->__ksmdbgssnCanCopy__(pResource); } @@ -602,6 +610,10 @@ static inline NV_STATUS ksmdbgssnIsDuplicate_DISPATCH(struct KernelSMDebuggerSes return pResource->__ksmdbgssnIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void ksmdbgssnControlSerialization_Epilogue_DISPATCH(struct KernelSMDebuggerSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__ksmdbgssnControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *ksmdbgssnGetNotificationListPtr_DISPATCH(struct KernelSMDebuggerSession *pNotifier) { return pNotifier->__ksmdbgssnGetNotificationListPtr__(pNotifier); } diff --git a/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.c b/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.c index d312e7497..4b4c050d9 100644 --- a/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.c +++ b/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.c @@ -114,13 +114,16 @@ NV_STATUS __nvoc_objCreate_KernelVgpuMgr(KernelVgpuMgr **ppThis, Dynamic *pParen Object *pParentObj; KernelVgpuMgr *pThis; - pThis = portMemAllocNonPaged(sizeof(KernelVgpuMgr)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelVgpuMgr), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(KernelVgpuMgr)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelVgpuMgr); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -136,11 +139,17 @@ NV_STATUS __nvoc_objCreate_KernelVgpuMgr(KernelVgpuMgr **ppThis, Dynamic *pParen if (status != NV_OK) goto __nvoc_objCreate_KernelVgpuMgr_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_KernelVgpuMgr_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelVgpuMgr)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.h b/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.h index ae4c277f2..ee2bb0fee 100644 --- a/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.h +++ b/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.h @@ -112,11 +112,11 @@ typedef struct KERNEL_HOST_VGPU_DEVICE NvU32 swizzId; NvU32 numPluginChannels; NvU32 chidOffset[RM_ENGINE_TYPE_LAST]; + NvU32 channelCount[RM_ENGINE_TYPE_LAST]; /*Number of channels available to the VF*/ NvU8 vgpuUuid[RM_SHA1_GID_SIZE]; void *pVgpuVfioRef; struct REQUEST_VGPU_INFO_NODE *pRequestVgpuInfoNode; struct PhysMemSubAlloc *pPhysMemSubAlloc; - NvU32 gpuInstance; struct HOST_VGPU_DEVICE *pHostVgpuDevice; // Legacy fields NvHandle hPluginFBAllocationClient; diff --git a/src/nvidia/generated/g_mem_desc_nvoc.h b/src/nvidia/generated/g_mem_desc_nvoc.h index 69dabeb12..00e8d05f2 100644 --- a/src/nvidia/generated/g_mem_desc_nvoc.h +++ b/src/nvidia/generated/g_mem_desc_nvoc.h @@ -215,7 +215,7 @@ typedef struct MEMORY_DESCRIPTOR NvU64 _flags; // Size of mapping used for this allocation. Multiple mappings on Fermi must always use the same page size. - NvU32 _pageSize; + NvU64 _pageSize; // Size of the memory allocation in pages NvU64 PageCount; @@ -497,7 +497,7 @@ void memdescDescribe(MEMORY_DESCRIPTOR *pMemDesc, // Fill in a MEMORY_DESCRIPTOR with the physical page addresses returned by PMA. // It should already be initialized with memdescCreate*(). void memdescFillPages(MEMORY_DESCRIPTOR *pMemDesc, NvU32 offset, - NvU64 *pPages, NvU32 pageCount, NvU32 pageSize); + NvU64 *pPages, NvU32 pageCount, NvU64 pageSize); // Create a MEMORY_DESCRIPTOR for a subset of an existing memory allocation. // The new MEMORY_DESCRIPTOR must be freed with memdescDestroy. @@ -574,7 +574,7 @@ MEMORY_DESCRIPTOR *memdescGetMemDescFromIndex(MEMORY_DESCRIPTOR *pMemDesc, NvU32 void memdescPrintMemdesc(MEMORY_DESCRIPTOR *pMemDesc, NvBool bPrintIndividualPages, const char *pPrefixMessage); // Get the page offset for an arbitrary power of two page size -NvU64 memdescGetPageOffset(MEMORY_DESCRIPTOR *pMemDesc, NvU32 pageSize); +NvU64 memdescGetPageOffset(MEMORY_DESCRIPTOR *pMemDesc, NvU64 pageSize); // // Internal APIs for the IOVASPACE to manage IOMMU mappings in a memdesc. @@ -645,11 +645,14 @@ void memdescSetContiguity(PMEMORY_DESCRIPTOR pMemDesc, ADDRESS_TRANSLATION addre NvBool memdescCheckContiguity(PMEMORY_DESCRIPTOR pMemDesc, ADDRESS_TRANSLATION addressTranslation); NV_ADDRESS_SPACE memdescGetAddressSpace(PMEMORY_DESCRIPTOR pMemDesc); NvU32 memdescGetPageSize(MEMORY_DESCRIPTOR *pMemDesc, ADDRESS_TRANSLATION addressTranslation); -void memdescSetPageSize(MEMORY_DESCRIPTOR *pMemDesc, ADDRESS_TRANSLATION addressTranslation, NvU32 pageSize); +void memdescSetPageSize(MEMORY_DESCRIPTOR *pMemDesc, ADDRESS_TRANSLATION addressTranslation, NvU64 pageSize); PMEMORY_DESCRIPTOR memdescGetRootMemDesc(PMEMORY_DESCRIPTOR pMemDesc, NvU64 *pRootOffset); void memdescSetCustomHeap(PMEMORY_DESCRIPTOR); NvBool memdescGetCustomHeap(PMEMORY_DESCRIPTOR); +// Temporary function for 64-bit pageSize transition +NvU64 memdescGetPageSize64(MEMORY_DESCRIPTOR *pMemDesc, ADDRESS_TRANSLATION addressTranslation); + /*! * @brief Get PTE kind * diff --git a/src/nvidia/generated/g_mem_fabric_nvoc.c b/src/nvidia/generated/g_mem_fabric_nvoc.c index 098cb3fee..0b0bb57f6 100644 --- a/src/nvidia/generated/g_mem_fabric_nvoc.c +++ b/src/nvidia/generated/g_mem_fabric_nvoc.c @@ -105,6 +105,46 @@ static NV_STATUS __nvoc_thunk_Memory_memoryfabricCheckMemInterUnmap(struct Memor return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), bSubdeviceHandleProvided); } +static NvBool __nvoc_thunk_RmResource_memoryfabricShareCallback(struct MemoryFabric *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RsResource_memoryfabricMapTo(struct MemoryFabric *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_memoryfabricGetMapAddrSpace(struct MemoryFabric *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_memoryfabricGetRefCount(struct MemoryFabric *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_memoryfabricAddAdditionalDependants(struct RsClient *pClient, struct MemoryFabric *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_memoryfabricControl_Prologue(struct MemoryFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_Memory_memoryfabricIsGpuMapAllowed(struct MemoryFabric *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), pGpu); +} + +static NV_STATUS __nvoc_thunk_RsResource_memoryfabricUnmapFrom(struct MemoryFabric *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_memoryfabricControl_Epilogue(struct MemoryFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_memoryfabricControlLookup(struct MemoryFabric *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RsResource.offset), pParams, ppEntry); +} + static NV_STATUS __nvoc_thunk_Memory_memoryfabricUnmap(struct MemoryFabric *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), pCallContext, pCpuMapping); } @@ -117,36 +157,12 @@ static NV_STATUS __nvoc_thunk_Memory_memoryfabricGetMemoryMappingDescriptor(stru return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_Memory_memoryfabricGetMapAddrSpace(struct MemoryFabric *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvBool __nvoc_thunk_RmResource_memoryfabricShareCallback(struct MemoryFabric *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); -} - static NV_STATUS __nvoc_thunk_RsResource_memoryfabricControlFilter(struct MemoryFabric *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_memoryfabricAddAdditionalDependants(struct RsClient *pClient, struct MemoryFabric *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_memoryfabricGetRefCount(struct MemoryFabric *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RsResource_memoryfabricMapTo(struct MemoryFabric *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_memoryfabricControl_Prologue(struct MemoryFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RmResource.offset), pCallContext, pParams); -} - -static NvBool __nvoc_thunk_Memory_memoryfabricIsGpuMapAllowed(struct MemoryFabric *pMemory, struct OBJGPU *pGpu) { - return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), pGpu); +static NV_STATUS __nvoc_thunk_RmResource_memoryfabricControlSerialization_Prologue(struct MemoryFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_memoryfabricIsReady(struct MemoryFabric *pMemory, NvBool bCopyConstructorContext) { @@ -165,16 +181,8 @@ static NV_STATUS __nvoc_thunk_Memory_memoryfabricIsDuplicate(struct MemoryFabric return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), hMemory, pDuplicate); } -static NV_STATUS __nvoc_thunk_RsResource_memoryfabricUnmapFrom(struct MemoryFabric *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RmResource_memoryfabricControl_Epilogue(struct MemoryFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_memoryfabricControlLookup(struct MemoryFabric *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_memoryfabricControlSerialization_Epilogue(struct MemoryFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_memoryfabricMap(struct MemoryFabric *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -249,6 +257,36 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_MemoryFa /*pClassInfo=*/ &(__nvoc_class_def_MemoryFabric.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "memoryfabricCtrlDetachMem" +#endif + }, + { /* [4] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) memoryfabricCtrlGetNumAttachedMem_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xf80105u, + /*paramSize=*/ sizeof(NV00F8_CTRL_GET_NUM_ATTACHED_MEM_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_MemoryFabric.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "memoryfabricCtrlGetNumAttachedMem" +#endif + }, + { /* [5] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) memoryfabricCtrlGetAttachedMem_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*flags=*/ 0x810u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xf80106u, + /*paramSize=*/ sizeof(NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_MemoryFabric.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "memoryfabricCtrlGetAttachedMem" #endif }, @@ -256,7 +294,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_MemoryFa const struct NVOC_EXPORT_INFO __nvoc_export_info_MemoryFabric = { - /*numEntries=*/ 4, + /*numEntries=*/ 6, /*pExportEntries=*/ __nvoc_exported_method_def_MemoryFabric }; @@ -315,33 +353,49 @@ static void __nvoc_init_funcTable_MemoryFabric_1(MemoryFabric *pThis) { pThis->__memoryfabricCtrlDetachMem__ = &memoryfabricCtrlDetachMem_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + pThis->__memoryfabricCtrlGetNumAttachedMem__ = &memoryfabricCtrlGetNumAttachedMem_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + pThis->__memoryfabricCtrlGetAttachedMem__ = &memoryfabricCtrlGetAttachedMem_IMPL; +#endif + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__resCanCopy__ = &__nvoc_thunk_MemoryFabric_resCanCopy; pThis->__nvoc_base_Memory.__memControl__ = &__nvoc_thunk_MemoryFabric_memControl; pThis->__memoryfabricCheckMemInterUnmap__ = &__nvoc_thunk_Memory_memoryfabricCheckMemInterUnmap; + pThis->__memoryfabricShareCallback__ = &__nvoc_thunk_RmResource_memoryfabricShareCallback; + + pThis->__memoryfabricMapTo__ = &__nvoc_thunk_RsResource_memoryfabricMapTo; + + pThis->__memoryfabricGetMapAddrSpace__ = &__nvoc_thunk_Memory_memoryfabricGetMapAddrSpace; + + pThis->__memoryfabricGetRefCount__ = &__nvoc_thunk_RsResource_memoryfabricGetRefCount; + + pThis->__memoryfabricAddAdditionalDependants__ = &__nvoc_thunk_RsResource_memoryfabricAddAdditionalDependants; + + pThis->__memoryfabricControl_Prologue__ = &__nvoc_thunk_RmResource_memoryfabricControl_Prologue; + + pThis->__memoryfabricIsGpuMapAllowed__ = &__nvoc_thunk_Memory_memoryfabricIsGpuMapAllowed; + + pThis->__memoryfabricUnmapFrom__ = &__nvoc_thunk_RsResource_memoryfabricUnmapFrom; + + pThis->__memoryfabricControl_Epilogue__ = &__nvoc_thunk_RmResource_memoryfabricControl_Epilogue; + + pThis->__memoryfabricControlLookup__ = &__nvoc_thunk_RsResource_memoryfabricControlLookup; + pThis->__memoryfabricUnmap__ = &__nvoc_thunk_Memory_memoryfabricUnmap; pThis->__memoryfabricGetMemInterMapParams__ = &__nvoc_thunk_Memory_memoryfabricGetMemInterMapParams; pThis->__memoryfabricGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_memoryfabricGetMemoryMappingDescriptor; - pThis->__memoryfabricGetMapAddrSpace__ = &__nvoc_thunk_Memory_memoryfabricGetMapAddrSpace; - - pThis->__memoryfabricShareCallback__ = &__nvoc_thunk_RmResource_memoryfabricShareCallback; - pThis->__memoryfabricControlFilter__ = &__nvoc_thunk_RsResource_memoryfabricControlFilter; - pThis->__memoryfabricAddAdditionalDependants__ = &__nvoc_thunk_RsResource_memoryfabricAddAdditionalDependants; - - pThis->__memoryfabricGetRefCount__ = &__nvoc_thunk_RsResource_memoryfabricGetRefCount; - - pThis->__memoryfabricMapTo__ = &__nvoc_thunk_RsResource_memoryfabricMapTo; - - pThis->__memoryfabricControl_Prologue__ = &__nvoc_thunk_RmResource_memoryfabricControl_Prologue; - - pThis->__memoryfabricIsGpuMapAllowed__ = &__nvoc_thunk_Memory_memoryfabricIsGpuMapAllowed; + pThis->__memoryfabricControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_memoryfabricControlSerialization_Prologue; pThis->__memoryfabricIsReady__ = &__nvoc_thunk_Memory_memoryfabricIsReady; @@ -351,11 +405,7 @@ static void __nvoc_init_funcTable_MemoryFabric_1(MemoryFabric *pThis) { pThis->__memoryfabricIsDuplicate__ = &__nvoc_thunk_Memory_memoryfabricIsDuplicate; - pThis->__memoryfabricUnmapFrom__ = &__nvoc_thunk_RsResource_memoryfabricUnmapFrom; - - pThis->__memoryfabricControl_Epilogue__ = &__nvoc_thunk_RmResource_memoryfabricControl_Epilogue; - - pThis->__memoryfabricControlLookup__ = &__nvoc_thunk_RsResource_memoryfabricControlLookup; + pThis->__memoryfabricControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_memoryfabricControlSerialization_Epilogue; pThis->__memoryfabricMap__ = &__nvoc_thunk_Memory_memoryfabricMap; @@ -383,13 +433,16 @@ NV_STATUS __nvoc_objCreate_MemoryFabric(MemoryFabric **ppThis, Dynamic *pParent, Object *pParentObj; MemoryFabric *pThis; - pThis = portMemAllocNonPaged(sizeof(MemoryFabric)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MemoryFabric), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(MemoryFabric)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MemoryFabric); + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -405,11 +458,17 @@ NV_STATUS __nvoc_objCreate_MemoryFabric(MemoryFabric **ppThis, Dynamic *pParent, if (status != NV_OK) goto __nvoc_objCreate_MemoryFabric_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_MemoryFabric_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(MemoryFabric)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_mem_fabric_nvoc.h b/src/nvidia/generated/g_mem_fabric_nvoc.h index 6736c9958..5dbdd6dee 100644 --- a/src/nvidia/generated/g_mem_fabric_nvoc.h +++ b/src/nvidia/generated/g_mem_fabric_nvoc.h @@ -73,25 +73,29 @@ struct MemoryFabric { NV_STATUS (*__memoryfabricCtrlCmdDescribe__)(struct MemoryFabric *, NV00F8_CTRL_DESCRIBE_PARAMS *); NV_STATUS (*__memoryfabricCtrlAttachMem__)(struct MemoryFabric *, NV00F8_CTRL_ATTACH_MEM_PARAMS *); NV_STATUS (*__memoryfabricCtrlDetachMem__)(struct MemoryFabric *, NV00F8_CTRL_DETACH_MEM_PARAMS *); + NV_STATUS (*__memoryfabricCtrlGetNumAttachedMem__)(struct MemoryFabric *, NV00F8_CTRL_GET_NUM_ATTACHED_MEM_PARAMS *); + NV_STATUS (*__memoryfabricCtrlGetAttachedMem__)(struct MemoryFabric *, NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS *); NV_STATUS (*__memoryfabricCheckMemInterUnmap__)(struct MemoryFabric *, NvBool); + NvBool (*__memoryfabricShareCallback__)(struct MemoryFabric *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__memoryfabricMapTo__)(struct MemoryFabric *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__memoryfabricGetMapAddrSpace__)(struct MemoryFabric *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__memoryfabricGetRefCount__)(struct MemoryFabric *); + void (*__memoryfabricAddAdditionalDependants__)(struct RsClient *, struct MemoryFabric *, RsResourceRef *); + NV_STATUS (*__memoryfabricControl_Prologue__)(struct MemoryFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__memoryfabricIsGpuMapAllowed__)(struct MemoryFabric *, struct OBJGPU *); + NV_STATUS (*__memoryfabricUnmapFrom__)(struct MemoryFabric *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__memoryfabricControl_Epilogue__)(struct MemoryFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memoryfabricControlLookup__)(struct MemoryFabric *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__memoryfabricUnmap__)(struct MemoryFabric *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__memoryfabricGetMemInterMapParams__)(struct MemoryFabric *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__memoryfabricGetMemoryMappingDescriptor__)(struct MemoryFabric *, MEMORY_DESCRIPTOR **); - NV_STATUS (*__memoryfabricGetMapAddrSpace__)(struct MemoryFabric *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvBool (*__memoryfabricShareCallback__)(struct MemoryFabric *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__memoryfabricControlFilter__)(struct MemoryFabric *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__memoryfabricAddAdditionalDependants__)(struct RsClient *, struct MemoryFabric *, RsResourceRef *); - NvU32 (*__memoryfabricGetRefCount__)(struct MemoryFabric *); - NV_STATUS (*__memoryfabricMapTo__)(struct MemoryFabric *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__memoryfabricControl_Prologue__)(struct MemoryFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvBool (*__memoryfabricIsGpuMapAllowed__)(struct MemoryFabric *, struct OBJGPU *); + NV_STATUS (*__memoryfabricControlSerialization_Prologue__)(struct MemoryFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memoryfabricIsReady__)(struct MemoryFabric *, NvBool); NV_STATUS (*__memoryfabricCheckCopyPermissions__)(struct MemoryFabric *, struct OBJGPU *, NvHandle); void (*__memoryfabricPreDestruct__)(struct MemoryFabric *); NV_STATUS (*__memoryfabricIsDuplicate__)(struct MemoryFabric *, NvHandle, NvBool *); - NV_STATUS (*__memoryfabricUnmapFrom__)(struct MemoryFabric *, RS_RES_UNMAP_FROM_PARAMS *); - void (*__memoryfabricControl_Epilogue__)(struct MemoryFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__memoryfabricControlLookup__)(struct MemoryFabric *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__memoryfabricControlSerialization_Epilogue__)(struct MemoryFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memoryfabricMap__)(struct MemoryFabric *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__memoryfabricAccessCallback__)(struct MemoryFabric *, struct RsClient *, void *, RsAccessRight); }; @@ -131,25 +135,29 @@ NV_STATUS __nvoc_objCreate_MemoryFabric(MemoryFabric**, Dynamic*, NvU32, CALL_CO #define memoryfabricCtrlCmdDescribe(pMemoryFabric, pParams) memoryfabricCtrlCmdDescribe_DISPATCH(pMemoryFabric, pParams) #define memoryfabricCtrlAttachMem(pMemoryFabric, pParams) memoryfabricCtrlAttachMem_DISPATCH(pMemoryFabric, pParams) #define memoryfabricCtrlDetachMem(pMemoryFabric, pParams) memoryfabricCtrlDetachMem_DISPATCH(pMemoryFabric, pParams) +#define memoryfabricCtrlGetNumAttachedMem(pMemoryFabric, pParams) memoryfabricCtrlGetNumAttachedMem_DISPATCH(pMemoryFabric, pParams) +#define memoryfabricCtrlGetAttachedMem(pMemoryFabric, pParams) memoryfabricCtrlGetAttachedMem_DISPATCH(pMemoryFabric, pParams) #define memoryfabricCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) memoryfabricCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define memoryfabricShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) memoryfabricShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define memoryfabricMapTo(pResource, pParams) memoryfabricMapTo_DISPATCH(pResource, pParams) +#define memoryfabricGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) memoryfabricGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define memoryfabricGetRefCount(pResource) memoryfabricGetRefCount_DISPATCH(pResource) +#define memoryfabricAddAdditionalDependants(pClient, pResource, pReference) memoryfabricAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define memoryfabricControl_Prologue(pResource, pCallContext, pParams) memoryfabricControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define memoryfabricIsGpuMapAllowed(pMemory, pGpu) memoryfabricIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define memoryfabricUnmapFrom(pResource, pParams) memoryfabricUnmapFrom_DISPATCH(pResource, pParams) +#define memoryfabricControl_Epilogue(pResource, pCallContext, pParams) memoryfabricControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define memoryfabricControlLookup(pResource, pParams, ppEntry) memoryfabricControlLookup_DISPATCH(pResource, pParams, ppEntry) #define memoryfabricUnmap(pMemory, pCallContext, pCpuMapping) memoryfabricUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define memoryfabricGetMemInterMapParams(pMemory, pParams) memoryfabricGetMemInterMapParams_DISPATCH(pMemory, pParams) #define memoryfabricGetMemoryMappingDescriptor(pMemory, ppMemDesc) memoryfabricGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define memoryfabricGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) memoryfabricGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) -#define memoryfabricShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) memoryfabricShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define memoryfabricControlFilter(pResource, pCallContext, pParams) memoryfabricControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define memoryfabricAddAdditionalDependants(pClient, pResource, pReference) memoryfabricAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define memoryfabricGetRefCount(pResource) memoryfabricGetRefCount_DISPATCH(pResource) -#define memoryfabricMapTo(pResource, pParams) memoryfabricMapTo_DISPATCH(pResource, pParams) -#define memoryfabricControl_Prologue(pResource, pCallContext, pParams) memoryfabricControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define memoryfabricIsGpuMapAllowed(pMemory, pGpu) memoryfabricIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define memoryfabricControlSerialization_Prologue(pResource, pCallContext, pParams) memoryfabricControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define memoryfabricIsReady(pMemory, bCopyConstructorContext) memoryfabricIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define memoryfabricCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) memoryfabricCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) #define memoryfabricPreDestruct(pResource) memoryfabricPreDestruct_DISPATCH(pResource) #define memoryfabricIsDuplicate(pMemory, hMemory, pDuplicate) memoryfabricIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) -#define memoryfabricUnmapFrom(pResource, pParams) memoryfabricUnmapFrom_DISPATCH(pResource, pParams) -#define memoryfabricControl_Epilogue(pResource, pCallContext, pParams) memoryfabricControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define memoryfabricControlLookup(pResource, pParams, ppEntry) memoryfabricControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define memoryfabricControlSerialization_Epilogue(pResource, pCallContext, pParams) memoryfabricControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define memoryfabricMap(pMemory, pCallContext, pParams, pCpuMapping) memoryfabricMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define memoryfabricAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) memoryfabricAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool memoryfabricCanCopy_IMPL(struct MemoryFabric *pMemoryFabric); @@ -194,10 +202,62 @@ static inline NV_STATUS memoryfabricCtrlDetachMem_DISPATCH(struct MemoryFabric * return pMemoryFabric->__memoryfabricCtrlDetachMem__(pMemoryFabric, pParams); } +NV_STATUS memoryfabricCtrlGetNumAttachedMem_IMPL(struct MemoryFabric *pMemoryFabric, NV00F8_CTRL_GET_NUM_ATTACHED_MEM_PARAMS *pParams); + +static inline NV_STATUS memoryfabricCtrlGetNumAttachedMem_DISPATCH(struct MemoryFabric *pMemoryFabric, NV00F8_CTRL_GET_NUM_ATTACHED_MEM_PARAMS *pParams) { + return pMemoryFabric->__memoryfabricCtrlGetNumAttachedMem__(pMemoryFabric, pParams); +} + +NV_STATUS memoryfabricCtrlGetAttachedMem_IMPL(struct MemoryFabric *pMemoryFabric, NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS *pParams); + +static inline NV_STATUS memoryfabricCtrlGetAttachedMem_DISPATCH(struct MemoryFabric *pMemoryFabric, NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS *pParams) { + return pMemoryFabric->__memoryfabricCtrlGetAttachedMem__(pMemoryFabric, pParams); +} + static inline NV_STATUS memoryfabricCheckMemInterUnmap_DISPATCH(struct MemoryFabric *pMemory, NvBool bSubdeviceHandleProvided) { return pMemory->__memoryfabricCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } +static inline NvBool memoryfabricShareCallback_DISPATCH(struct MemoryFabric *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__memoryfabricShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS memoryfabricMapTo_DISPATCH(struct MemoryFabric *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__memoryfabricMapTo__(pResource, pParams); +} + +static inline NV_STATUS memoryfabricGetMapAddrSpace_DISPATCH(struct MemoryFabric *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__memoryfabricGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 memoryfabricGetRefCount_DISPATCH(struct MemoryFabric *pResource) { + return pResource->__memoryfabricGetRefCount__(pResource); +} + +static inline void memoryfabricAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct MemoryFabric *pResource, RsResourceRef *pReference) { + pResource->__memoryfabricAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS memoryfabricControl_Prologue_DISPATCH(struct MemoryFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memoryfabricControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool memoryfabricIsGpuMapAllowed_DISPATCH(struct MemoryFabric *pMemory, struct OBJGPU *pGpu) { + return pMemory->__memoryfabricIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline NV_STATUS memoryfabricUnmapFrom_DISPATCH(struct MemoryFabric *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__memoryfabricUnmapFrom__(pResource, pParams); +} + +static inline void memoryfabricControl_Epilogue_DISPATCH(struct MemoryFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__memoryfabricControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS memoryfabricControlLookup_DISPATCH(struct MemoryFabric *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__memoryfabricControlLookup__(pResource, pParams, ppEntry); +} + static inline NV_STATUS memoryfabricUnmap_DISPATCH(struct MemoryFabric *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { return pMemory->__memoryfabricUnmap__(pMemory, pCallContext, pCpuMapping); } @@ -210,36 +270,12 @@ static inline NV_STATUS memoryfabricGetMemoryMappingDescriptor_DISPATCH(struct M return pMemory->__memoryfabricGetMemoryMappingDescriptor__(pMemory, ppMemDesc); } -static inline NV_STATUS memoryfabricGetMapAddrSpace_DISPATCH(struct MemoryFabric *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pMemory->__memoryfabricGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvBool memoryfabricShareCallback_DISPATCH(struct MemoryFabric *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pResource->__memoryfabricShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); -} - static inline NV_STATUS memoryfabricControlFilter_DISPATCH(struct MemoryFabric *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__memoryfabricControlFilter__(pResource, pCallContext, pParams); } -static inline void memoryfabricAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct MemoryFabric *pResource, RsResourceRef *pReference) { - pResource->__memoryfabricAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 memoryfabricGetRefCount_DISPATCH(struct MemoryFabric *pResource) { - return pResource->__memoryfabricGetRefCount__(pResource); -} - -static inline NV_STATUS memoryfabricMapTo_DISPATCH(struct MemoryFabric *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__memoryfabricMapTo__(pResource, pParams); -} - -static inline NV_STATUS memoryfabricControl_Prologue_DISPATCH(struct MemoryFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__memoryfabricControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NvBool memoryfabricIsGpuMapAllowed_DISPATCH(struct MemoryFabric *pMemory, struct OBJGPU *pGpu) { - return pMemory->__memoryfabricIsGpuMapAllowed__(pMemory, pGpu); +static inline NV_STATUS memoryfabricControlSerialization_Prologue_DISPATCH(struct MemoryFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memoryfabricControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS memoryfabricIsReady_DISPATCH(struct MemoryFabric *pMemory, NvBool bCopyConstructorContext) { @@ -258,16 +294,8 @@ static inline NV_STATUS memoryfabricIsDuplicate_DISPATCH(struct MemoryFabric *pM return pMemory->__memoryfabricIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline NV_STATUS memoryfabricUnmapFrom_DISPATCH(struct MemoryFabric *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__memoryfabricUnmapFrom__(pResource, pParams); -} - -static inline void memoryfabricControl_Epilogue_DISPATCH(struct MemoryFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__memoryfabricControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS memoryfabricControlLookup_DISPATCH(struct MemoryFabric *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__memoryfabricControlLookup__(pResource, pParams, ppEntry); +static inline void memoryfabricControlSerialization_Epilogue_DISPATCH(struct MemoryFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__memoryfabricControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS memoryfabricMap_DISPATCH(struct MemoryFabric *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -290,6 +318,7 @@ void memoryfabricDestruct_IMPL(struct MemoryFabric *pMemoryFabric); typedef struct { MEMORY_DESCRIPTOR *pPhysMemDesc; + NvU64 physMapOffset; NvU64 physMapLength; NvHandle hDupedPhysMem; NODE node; diff --git a/src/nvidia/generated/g_mem_list_nvoc.c b/src/nvidia/generated/g_mem_list_nvoc.c index 1f701b0a3..b7eceb344 100644 --- a/src/nvidia/generated/g_mem_list_nvoc.c +++ b/src/nvidia/generated/g_mem_list_nvoc.c @@ -101,6 +101,46 @@ static NV_STATUS __nvoc_thunk_Memory_memlistCheckMemInterUnmap(struct MemoryList return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), bSubdeviceHandleProvided); } +static NvBool __nvoc_thunk_RmResource_memlistShareCallback(struct MemoryList *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RsResource_memlistMapTo(struct MemoryList *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_memlistGetMapAddrSpace(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_memlistGetRefCount(struct MemoryList *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_memlistAddAdditionalDependants(struct RsClient *pClient, struct MemoryList *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_memlistControl_Prologue(struct MemoryList *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_Memory_memlistIsGpuMapAllowed(struct MemoryList *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), pGpu); +} + +static NV_STATUS __nvoc_thunk_RsResource_memlistUnmapFrom(struct MemoryList *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_memlistControl_Epilogue(struct MemoryList *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_memlistControlLookup(struct MemoryList *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset), pParams, ppEntry); +} + static NV_STATUS __nvoc_thunk_Memory_memlistControl(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), pCallContext, pParams); } @@ -117,36 +157,12 @@ static NV_STATUS __nvoc_thunk_Memory_memlistGetMemoryMappingDescriptor(struct Me return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_Memory_memlistGetMapAddrSpace(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvBool __nvoc_thunk_RmResource_memlistShareCallback(struct MemoryList *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); -} - static NV_STATUS __nvoc_thunk_RsResource_memlistControlFilter(struct MemoryList *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_memlistAddAdditionalDependants(struct RsClient *pClient, struct MemoryList *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_memlistGetRefCount(struct MemoryList *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RsResource_memlistMapTo(struct MemoryList *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_memlistControl_Prologue(struct MemoryList *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RmResource.offset), pCallContext, pParams); -} - -static NvBool __nvoc_thunk_Memory_memlistIsGpuMapAllowed(struct MemoryList *pMemory, struct OBJGPU *pGpu) { - return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), pGpu); +static NV_STATUS __nvoc_thunk_RmResource_memlistControlSerialization_Prologue(struct MemoryList *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_memlistIsReady(struct MemoryList *pMemory, NvBool bCopyConstructorContext) { @@ -165,16 +181,8 @@ static NV_STATUS __nvoc_thunk_Memory_memlistIsDuplicate(struct MemoryList *pMemo return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), hMemory, pDuplicate); } -static NV_STATUS __nvoc_thunk_RsResource_memlistUnmapFrom(struct MemoryList *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RmResource_memlistControl_Epilogue(struct MemoryList *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_memlistControlLookup(struct MemoryList *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_memlistControlSerialization_Epilogue(struct MemoryList *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_memlistMap(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -229,6 +237,26 @@ static void __nvoc_init_funcTable_MemoryList_1(MemoryList *pThis) { pThis->__memlistCheckMemInterUnmap__ = &__nvoc_thunk_Memory_memlistCheckMemInterUnmap; + pThis->__memlistShareCallback__ = &__nvoc_thunk_RmResource_memlistShareCallback; + + pThis->__memlistMapTo__ = &__nvoc_thunk_RsResource_memlistMapTo; + + pThis->__memlistGetMapAddrSpace__ = &__nvoc_thunk_Memory_memlistGetMapAddrSpace; + + pThis->__memlistGetRefCount__ = &__nvoc_thunk_RsResource_memlistGetRefCount; + + pThis->__memlistAddAdditionalDependants__ = &__nvoc_thunk_RsResource_memlistAddAdditionalDependants; + + pThis->__memlistControl_Prologue__ = &__nvoc_thunk_RmResource_memlistControl_Prologue; + + pThis->__memlistIsGpuMapAllowed__ = &__nvoc_thunk_Memory_memlistIsGpuMapAllowed; + + pThis->__memlistUnmapFrom__ = &__nvoc_thunk_RsResource_memlistUnmapFrom; + + pThis->__memlistControl_Epilogue__ = &__nvoc_thunk_RmResource_memlistControl_Epilogue; + + pThis->__memlistControlLookup__ = &__nvoc_thunk_RsResource_memlistControlLookup; + pThis->__memlistControl__ = &__nvoc_thunk_Memory_memlistControl; pThis->__memlistUnmap__ = &__nvoc_thunk_Memory_memlistUnmap; @@ -237,21 +265,9 @@ static void __nvoc_init_funcTable_MemoryList_1(MemoryList *pThis) { pThis->__memlistGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_memlistGetMemoryMappingDescriptor; - pThis->__memlistGetMapAddrSpace__ = &__nvoc_thunk_Memory_memlistGetMapAddrSpace; - - pThis->__memlistShareCallback__ = &__nvoc_thunk_RmResource_memlistShareCallback; - pThis->__memlistControlFilter__ = &__nvoc_thunk_RsResource_memlistControlFilter; - pThis->__memlistAddAdditionalDependants__ = &__nvoc_thunk_RsResource_memlistAddAdditionalDependants; - - pThis->__memlistGetRefCount__ = &__nvoc_thunk_RsResource_memlistGetRefCount; - - pThis->__memlistMapTo__ = &__nvoc_thunk_RsResource_memlistMapTo; - - pThis->__memlistControl_Prologue__ = &__nvoc_thunk_RmResource_memlistControl_Prologue; - - pThis->__memlistIsGpuMapAllowed__ = &__nvoc_thunk_Memory_memlistIsGpuMapAllowed; + pThis->__memlistControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_memlistControlSerialization_Prologue; pThis->__memlistIsReady__ = &__nvoc_thunk_Memory_memlistIsReady; @@ -261,11 +277,7 @@ static void __nvoc_init_funcTable_MemoryList_1(MemoryList *pThis) { pThis->__memlistIsDuplicate__ = &__nvoc_thunk_Memory_memlistIsDuplicate; - pThis->__memlistUnmapFrom__ = &__nvoc_thunk_RsResource_memlistUnmapFrom; - - pThis->__memlistControl_Epilogue__ = &__nvoc_thunk_RmResource_memlistControl_Epilogue; - - pThis->__memlistControlLookup__ = &__nvoc_thunk_RsResource_memlistControlLookup; + pThis->__memlistControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_memlistControlSerialization_Epilogue; pThis->__memlistMap__ = &__nvoc_thunk_Memory_memlistMap; @@ -293,13 +305,16 @@ NV_STATUS __nvoc_objCreate_MemoryList(MemoryList **ppThis, Dynamic *pParent, NvU Object *pParentObj; MemoryList *pThis; - pThis = portMemAllocNonPaged(sizeof(MemoryList)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MemoryList), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(MemoryList)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MemoryList); + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -315,11 +330,17 @@ NV_STATUS __nvoc_objCreate_MemoryList(MemoryList **ppThis, Dynamic *pParent, NvU if (status != NV_OK) goto __nvoc_objCreate_MemoryList_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_MemoryList_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(MemoryList)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_mem_list_nvoc.h b/src/nvidia/generated/g_mem_list_nvoc.h index 21d2bda25..8d7160404 100644 --- a/src/nvidia/generated/g_mem_list_nvoc.h +++ b/src/nvidia/generated/g_mem_list_nvoc.h @@ -56,25 +56,27 @@ struct MemoryList { struct MemoryList *__nvoc_pbase_MemoryList; NvBool (*__memlistCanCopy__)(struct MemoryList *); NV_STATUS (*__memlistCheckMemInterUnmap__)(struct MemoryList *, NvBool); + NvBool (*__memlistShareCallback__)(struct MemoryList *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__memlistMapTo__)(struct MemoryList *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__memlistGetMapAddrSpace__)(struct MemoryList *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__memlistGetRefCount__)(struct MemoryList *); + void (*__memlistAddAdditionalDependants__)(struct RsClient *, struct MemoryList *, RsResourceRef *); + NV_STATUS (*__memlistControl_Prologue__)(struct MemoryList *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__memlistIsGpuMapAllowed__)(struct MemoryList *, struct OBJGPU *); + NV_STATUS (*__memlistUnmapFrom__)(struct MemoryList *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__memlistControl_Epilogue__)(struct MemoryList *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memlistControlLookup__)(struct MemoryList *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__memlistControl__)(struct MemoryList *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memlistUnmap__)(struct MemoryList *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__memlistGetMemInterMapParams__)(struct MemoryList *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__memlistGetMemoryMappingDescriptor__)(struct MemoryList *, MEMORY_DESCRIPTOR **); - NV_STATUS (*__memlistGetMapAddrSpace__)(struct MemoryList *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvBool (*__memlistShareCallback__)(struct MemoryList *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__memlistControlFilter__)(struct MemoryList *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__memlistAddAdditionalDependants__)(struct RsClient *, struct MemoryList *, RsResourceRef *); - NvU32 (*__memlistGetRefCount__)(struct MemoryList *); - NV_STATUS (*__memlistMapTo__)(struct MemoryList *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__memlistControl_Prologue__)(struct MemoryList *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvBool (*__memlistIsGpuMapAllowed__)(struct MemoryList *, struct OBJGPU *); + NV_STATUS (*__memlistControlSerialization_Prologue__)(struct MemoryList *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memlistIsReady__)(struct MemoryList *, NvBool); NV_STATUS (*__memlistCheckCopyPermissions__)(struct MemoryList *, struct OBJGPU *, NvHandle); void (*__memlistPreDestruct__)(struct MemoryList *); NV_STATUS (*__memlistIsDuplicate__)(struct MemoryList *, NvHandle, NvBool *); - NV_STATUS (*__memlistUnmapFrom__)(struct MemoryList *, RS_RES_UNMAP_FROM_PARAMS *); - void (*__memlistControl_Epilogue__)(struct MemoryList *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__memlistControlLookup__)(struct MemoryList *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__memlistControlSerialization_Epilogue__)(struct MemoryList *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memlistMap__)(struct MemoryList *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__memlistAccessCallback__)(struct MemoryList *, struct RsClient *, void *, RsAccessRight); }; @@ -109,25 +111,27 @@ NV_STATUS __nvoc_objCreate_MemoryList(MemoryList**, Dynamic*, NvU32, CALL_CONTEX #define memlistCanCopy(pMemoryList) memlistCanCopy_DISPATCH(pMemoryList) #define memlistCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) memlistCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define memlistShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) memlistShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define memlistMapTo(pResource, pParams) memlistMapTo_DISPATCH(pResource, pParams) +#define memlistGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) memlistGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define memlistGetRefCount(pResource) memlistGetRefCount_DISPATCH(pResource) +#define memlistAddAdditionalDependants(pClient, pResource, pReference) memlistAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define memlistControl_Prologue(pResource, pCallContext, pParams) memlistControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define memlistIsGpuMapAllowed(pMemory, pGpu) memlistIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define memlistUnmapFrom(pResource, pParams) memlistUnmapFrom_DISPATCH(pResource, pParams) +#define memlistControl_Epilogue(pResource, pCallContext, pParams) memlistControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define memlistControlLookup(pResource, pParams, ppEntry) memlistControlLookup_DISPATCH(pResource, pParams, ppEntry) #define memlistControl(pMemory, pCallContext, pParams) memlistControl_DISPATCH(pMemory, pCallContext, pParams) #define memlistUnmap(pMemory, pCallContext, pCpuMapping) memlistUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define memlistGetMemInterMapParams(pMemory, pParams) memlistGetMemInterMapParams_DISPATCH(pMemory, pParams) #define memlistGetMemoryMappingDescriptor(pMemory, ppMemDesc) memlistGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define memlistGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) memlistGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) -#define memlistShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) memlistShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define memlistControlFilter(pResource, pCallContext, pParams) memlistControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define memlistAddAdditionalDependants(pClient, pResource, pReference) memlistAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define memlistGetRefCount(pResource) memlistGetRefCount_DISPATCH(pResource) -#define memlistMapTo(pResource, pParams) memlistMapTo_DISPATCH(pResource, pParams) -#define memlistControl_Prologue(pResource, pCallContext, pParams) memlistControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define memlistIsGpuMapAllowed(pMemory, pGpu) memlistIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define memlistControlSerialization_Prologue(pResource, pCallContext, pParams) memlistControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define memlistIsReady(pMemory, bCopyConstructorContext) memlistIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define memlistCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) memlistCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) #define memlistPreDestruct(pResource) memlistPreDestruct_DISPATCH(pResource) #define memlistIsDuplicate(pMemory, hMemory, pDuplicate) memlistIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) -#define memlistUnmapFrom(pResource, pParams) memlistUnmapFrom_DISPATCH(pResource, pParams) -#define memlistControl_Epilogue(pResource, pCallContext, pParams) memlistControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define memlistControlLookup(pResource, pParams, ppEntry) memlistControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define memlistControlSerialization_Epilogue(pResource, pCallContext, pParams) memlistControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define memlistMap(pMemory, pCallContext, pParams, pCpuMapping) memlistMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define memlistAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) memlistAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool memlistCanCopy_IMPL(struct MemoryList *pMemoryList); @@ -140,6 +144,46 @@ static inline NV_STATUS memlistCheckMemInterUnmap_DISPATCH(struct MemoryList *pM return pMemory->__memlistCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } +static inline NvBool memlistShareCallback_DISPATCH(struct MemoryList *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__memlistShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS memlistMapTo_DISPATCH(struct MemoryList *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__memlistMapTo__(pResource, pParams); +} + +static inline NV_STATUS memlistGetMapAddrSpace_DISPATCH(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__memlistGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 memlistGetRefCount_DISPATCH(struct MemoryList *pResource) { + return pResource->__memlistGetRefCount__(pResource); +} + +static inline void memlistAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct MemoryList *pResource, RsResourceRef *pReference) { + pResource->__memlistAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS memlistControl_Prologue_DISPATCH(struct MemoryList *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memlistControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool memlistIsGpuMapAllowed_DISPATCH(struct MemoryList *pMemory, struct OBJGPU *pGpu) { + return pMemory->__memlistIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline NV_STATUS memlistUnmapFrom_DISPATCH(struct MemoryList *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__memlistUnmapFrom__(pResource, pParams); +} + +static inline void memlistControl_Epilogue_DISPATCH(struct MemoryList *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__memlistControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS memlistControlLookup_DISPATCH(struct MemoryList *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__memlistControlLookup__(pResource, pParams, ppEntry); +} + static inline NV_STATUS memlistControl_DISPATCH(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pMemory->__memlistControl__(pMemory, pCallContext, pParams); } @@ -156,36 +200,12 @@ static inline NV_STATUS memlistGetMemoryMappingDescriptor_DISPATCH(struct Memory return pMemory->__memlistGetMemoryMappingDescriptor__(pMemory, ppMemDesc); } -static inline NV_STATUS memlistGetMapAddrSpace_DISPATCH(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pMemory->__memlistGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvBool memlistShareCallback_DISPATCH(struct MemoryList *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pResource->__memlistShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); -} - static inline NV_STATUS memlistControlFilter_DISPATCH(struct MemoryList *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__memlistControlFilter__(pResource, pCallContext, pParams); } -static inline void memlistAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct MemoryList *pResource, RsResourceRef *pReference) { - pResource->__memlistAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 memlistGetRefCount_DISPATCH(struct MemoryList *pResource) { - return pResource->__memlistGetRefCount__(pResource); -} - -static inline NV_STATUS memlistMapTo_DISPATCH(struct MemoryList *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__memlistMapTo__(pResource, pParams); -} - -static inline NV_STATUS memlistControl_Prologue_DISPATCH(struct MemoryList *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__memlistControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NvBool memlistIsGpuMapAllowed_DISPATCH(struct MemoryList *pMemory, struct OBJGPU *pGpu) { - return pMemory->__memlistIsGpuMapAllowed__(pMemory, pGpu); +static inline NV_STATUS memlistControlSerialization_Prologue_DISPATCH(struct MemoryList *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memlistControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS memlistIsReady_DISPATCH(struct MemoryList *pMemory, NvBool bCopyConstructorContext) { @@ -204,16 +224,8 @@ static inline NV_STATUS memlistIsDuplicate_DISPATCH(struct MemoryList *pMemory, return pMemory->__memlistIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline NV_STATUS memlistUnmapFrom_DISPATCH(struct MemoryList *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__memlistUnmapFrom__(pResource, pParams); -} - -static inline void memlistControl_Epilogue_DISPATCH(struct MemoryList *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__memlistControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS memlistControlLookup_DISPATCH(struct MemoryList *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__memlistControlLookup__(pResource, pParams, ppEntry); +static inline void memlistControlSerialization_Epilogue_DISPATCH(struct MemoryList *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__memlistControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS memlistMap_DISPATCH(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_mem_mapper_nvoc.c b/src/nvidia/generated/g_mem_mapper_nvoc.c index a82079aa4..791d408b3 100644 --- a/src/nvidia/generated/g_mem_mapper_nvoc.c +++ b/src/nvidia/generated/g_mem_mapper_nvoc.c @@ -97,6 +97,54 @@ static NvBool __nvoc_thunk_GpuResource_memmapperShareCallback(struct MemoryMappe return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } +static NV_STATUS __nvoc_thunk_RmResource_memmapperCheckMemInterUnmap(struct MemoryMapper *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_MemoryMapper_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_memmapperMapTo(struct MemoryMapper *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_memmapperGetMapAddrSpace(struct MemoryMapper *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_memmapperGetRefCount(struct MemoryMapper *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_memmapperAddAdditionalDependants(struct RsClient *pClient, struct MemoryMapper *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_memmapperControl_Prologue(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_memmapperGetRegBaseOffsetAndSize(struct MemoryMapper *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_memmapperInternalControlForward(struct MemoryMapper *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_memmapperUnmapFrom(struct MemoryMapper *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_memmapperControl_Epilogue(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_memmapperControlLookup(struct MemoryMapper *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset), pParams, ppEntry); +} + +static NvHandle __nvoc_thunk_GpuResource_memmapperGetInternalObjectHandle(struct MemoryMapper *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset)); +} + static NV_STATUS __nvoc_thunk_GpuResource_memmapperControl(struct MemoryMapper *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset), pCallContext, pParams); } @@ -113,68 +161,28 @@ static NV_STATUS __nvoc_thunk_RmResource_memmapperGetMemoryMappingDescriptor(str return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_MemoryMapper_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_GpuResource_memmapperGetMapAddrSpace(struct MemoryMapper *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvHandle __nvoc_thunk_GpuResource_memmapperGetInternalObjectHandle(struct MemoryMapper *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_memmapperControlFilter(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_memmapperAddAdditionalDependants(struct RsClient *pClient, struct MemoryMapper *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_memmapperGetRefCount(struct MemoryMapper *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RmResource_memmapperCheckMemInterUnmap(struct MemoryMapper *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_MemoryMapper_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_memmapperMapTo(struct MemoryMapper *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_memmapperControl_Prologue(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_GpuResource_memmapperGetRegBaseOffsetAndSize(struct MemoryMapper *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset), pGpu, pOffset, pSize); +static NV_STATUS __nvoc_thunk_RmResource_memmapperControlSerialization_Prologue(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_memmapperCanCopy(struct MemoryMapper *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_memmapperInternalControlForward(struct MemoryMapper *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset), command, pParams, size); -} - static void __nvoc_thunk_RsResource_memmapperPreDestruct(struct MemoryMapper *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_memmapperUnmapFrom(struct MemoryMapper *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_memmapperIsDuplicate(struct MemoryMapper *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset), hMemory, pDuplicate); } -static void __nvoc_thunk_RmResource_memmapperControl_Epilogue(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_memmapperControlLookup(struct MemoryMapper *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_memmapperControlSerialization_Epilogue(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_memmapperMap(struct MemoryMapper *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -253,6 +261,30 @@ static void __nvoc_init_funcTable_MemoryMapper_1(MemoryMapper *pThis) { pThis->__memmapperShareCallback__ = &__nvoc_thunk_GpuResource_memmapperShareCallback; + pThis->__memmapperCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_memmapperCheckMemInterUnmap; + + pThis->__memmapperMapTo__ = &__nvoc_thunk_RsResource_memmapperMapTo; + + pThis->__memmapperGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_memmapperGetMapAddrSpace; + + pThis->__memmapperGetRefCount__ = &__nvoc_thunk_RsResource_memmapperGetRefCount; + + pThis->__memmapperAddAdditionalDependants__ = &__nvoc_thunk_RsResource_memmapperAddAdditionalDependants; + + pThis->__memmapperControl_Prologue__ = &__nvoc_thunk_RmResource_memmapperControl_Prologue; + + pThis->__memmapperGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_memmapperGetRegBaseOffsetAndSize; + + pThis->__memmapperInternalControlForward__ = &__nvoc_thunk_GpuResource_memmapperInternalControlForward; + + pThis->__memmapperUnmapFrom__ = &__nvoc_thunk_RsResource_memmapperUnmapFrom; + + pThis->__memmapperControl_Epilogue__ = &__nvoc_thunk_RmResource_memmapperControl_Epilogue; + + pThis->__memmapperControlLookup__ = &__nvoc_thunk_RsResource_memmapperControlLookup; + + pThis->__memmapperGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_memmapperGetInternalObjectHandle; + pThis->__memmapperControl__ = &__nvoc_thunk_GpuResource_memmapperControl; pThis->__memmapperUnmap__ = &__nvoc_thunk_GpuResource_memmapperUnmap; @@ -261,37 +293,17 @@ static void __nvoc_init_funcTable_MemoryMapper_1(MemoryMapper *pThis) { pThis->__memmapperGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_memmapperGetMemoryMappingDescriptor; - pThis->__memmapperGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_memmapperGetMapAddrSpace; - - pThis->__memmapperGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_memmapperGetInternalObjectHandle; - pThis->__memmapperControlFilter__ = &__nvoc_thunk_RsResource_memmapperControlFilter; - pThis->__memmapperAddAdditionalDependants__ = &__nvoc_thunk_RsResource_memmapperAddAdditionalDependants; - - pThis->__memmapperGetRefCount__ = &__nvoc_thunk_RsResource_memmapperGetRefCount; - - pThis->__memmapperCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_memmapperCheckMemInterUnmap; - - pThis->__memmapperMapTo__ = &__nvoc_thunk_RsResource_memmapperMapTo; - - pThis->__memmapperControl_Prologue__ = &__nvoc_thunk_RmResource_memmapperControl_Prologue; - - pThis->__memmapperGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_memmapperGetRegBaseOffsetAndSize; + pThis->__memmapperControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_memmapperControlSerialization_Prologue; pThis->__memmapperCanCopy__ = &__nvoc_thunk_RsResource_memmapperCanCopy; - pThis->__memmapperInternalControlForward__ = &__nvoc_thunk_GpuResource_memmapperInternalControlForward; - pThis->__memmapperPreDestruct__ = &__nvoc_thunk_RsResource_memmapperPreDestruct; - pThis->__memmapperUnmapFrom__ = &__nvoc_thunk_RsResource_memmapperUnmapFrom; - pThis->__memmapperIsDuplicate__ = &__nvoc_thunk_RsResource_memmapperIsDuplicate; - pThis->__memmapperControl_Epilogue__ = &__nvoc_thunk_RmResource_memmapperControl_Epilogue; - - pThis->__memmapperControlLookup__ = &__nvoc_thunk_RsResource_memmapperControlLookup; + pThis->__memmapperControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_memmapperControlSerialization_Epilogue; pThis->__memmapperMap__ = &__nvoc_thunk_GpuResource_memmapperMap; @@ -319,13 +331,16 @@ NV_STATUS __nvoc_objCreate_MemoryMapper(MemoryMapper **ppThis, Dynamic *pParent, Object *pParentObj; MemoryMapper *pThis; - pThis = portMemAllocNonPaged(sizeof(MemoryMapper)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MemoryMapper), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(MemoryMapper)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MemoryMapper); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -341,11 +356,17 @@ NV_STATUS __nvoc_objCreate_MemoryMapper(MemoryMapper **ppThis, Dynamic *pParent, if (status != NV_OK) goto __nvoc_objCreate_MemoryMapper_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_MemoryMapper_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(MemoryMapper)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_mem_mapper_nvoc.h b/src/nvidia/generated/g_mem_mapper_nvoc.h index 52e11e279..69483eb85 100644 --- a/src/nvidia/generated/g_mem_mapper_nvoc.h +++ b/src/nvidia/generated/g_mem_mapper_nvoc.h @@ -86,26 +86,28 @@ struct MemoryMapper { struct MemoryMapper *__nvoc_pbase_MemoryMapper; NV_STATUS (*__memmapperCtrlCmdSubmitPagingOperations__)(struct MemoryMapper *, NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS *); NvBool (*__memmapperShareCallback__)(struct MemoryMapper *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__memmapperCheckMemInterUnmap__)(struct MemoryMapper *, NvBool); + NV_STATUS (*__memmapperMapTo__)(struct MemoryMapper *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__memmapperGetMapAddrSpace__)(struct MemoryMapper *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__memmapperGetRefCount__)(struct MemoryMapper *); + void (*__memmapperAddAdditionalDependants__)(struct RsClient *, struct MemoryMapper *, RsResourceRef *); + NV_STATUS (*__memmapperControl_Prologue__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memmapperGetRegBaseOffsetAndSize__)(struct MemoryMapper *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__memmapperInternalControlForward__)(struct MemoryMapper *, NvU32, void *, NvU32); + NV_STATUS (*__memmapperUnmapFrom__)(struct MemoryMapper *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__memmapperControl_Epilogue__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memmapperControlLookup__)(struct MemoryMapper *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__memmapperGetInternalObjectHandle__)(struct MemoryMapper *); NV_STATUS (*__memmapperControl__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memmapperUnmap__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__memmapperGetMemInterMapParams__)(struct MemoryMapper *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__memmapperGetMemoryMappingDescriptor__)(struct MemoryMapper *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__memmapperGetMapAddrSpace__)(struct MemoryMapper *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__memmapperGetInternalObjectHandle__)(struct MemoryMapper *); NV_STATUS (*__memmapperControlFilter__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__memmapperAddAdditionalDependants__)(struct RsClient *, struct MemoryMapper *, RsResourceRef *); - NvU32 (*__memmapperGetRefCount__)(struct MemoryMapper *); - NV_STATUS (*__memmapperCheckMemInterUnmap__)(struct MemoryMapper *, NvBool); - NV_STATUS (*__memmapperMapTo__)(struct MemoryMapper *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__memmapperControl_Prologue__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__memmapperGetRegBaseOffsetAndSize__)(struct MemoryMapper *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__memmapperControlSerialization_Prologue__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__memmapperCanCopy__)(struct MemoryMapper *); - NV_STATUS (*__memmapperInternalControlForward__)(struct MemoryMapper *, NvU32, void *, NvU32); void (*__memmapperPreDestruct__)(struct MemoryMapper *); - NV_STATUS (*__memmapperUnmapFrom__)(struct MemoryMapper *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__memmapperIsDuplicate__)(struct MemoryMapper *, NvHandle, NvBool *); - void (*__memmapperControl_Epilogue__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__memmapperControlLookup__)(struct MemoryMapper *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__memmapperControlSerialization_Epilogue__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memmapperMap__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__memmapperAccessCallback__)(struct MemoryMapper *, struct RsClient *, void *, RsAccessRight); struct Subdevice *pSubDevice; @@ -141,26 +143,28 @@ NV_STATUS __nvoc_objCreate_MemoryMapper(MemoryMapper**, Dynamic*, NvU32, struct #define memmapperCtrlCmdSubmitPagingOperations(pMemoryMapper, pParams) memmapperCtrlCmdSubmitPagingOperations_DISPATCH(pMemoryMapper, pParams) #define memmapperShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) memmapperShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define memmapperCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) memmapperCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define memmapperMapTo(pResource, pParams) memmapperMapTo_DISPATCH(pResource, pParams) +#define memmapperGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) memmapperGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define memmapperGetRefCount(pResource) memmapperGetRefCount_DISPATCH(pResource) +#define memmapperAddAdditionalDependants(pClient, pResource, pReference) memmapperAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define memmapperControl_Prologue(pResource, pCallContext, pParams) memmapperControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define memmapperGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) memmapperGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define memmapperInternalControlForward(pGpuResource, command, pParams, size) memmapperInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define memmapperUnmapFrom(pResource, pParams) memmapperUnmapFrom_DISPATCH(pResource, pParams) +#define memmapperControl_Epilogue(pResource, pCallContext, pParams) memmapperControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define memmapperControlLookup(pResource, pParams, ppEntry) memmapperControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define memmapperGetInternalObjectHandle(pGpuResource) memmapperGetInternalObjectHandle_DISPATCH(pGpuResource) #define memmapperControl(pGpuResource, pCallContext, pParams) memmapperControl_DISPATCH(pGpuResource, pCallContext, pParams) #define memmapperUnmap(pGpuResource, pCallContext, pCpuMapping) memmapperUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define memmapperGetMemInterMapParams(pRmResource, pParams) memmapperGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define memmapperGetMemoryMappingDescriptor(pRmResource, ppMemDesc) memmapperGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define memmapperGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) memmapperGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define memmapperGetInternalObjectHandle(pGpuResource) memmapperGetInternalObjectHandle_DISPATCH(pGpuResource) #define memmapperControlFilter(pResource, pCallContext, pParams) memmapperControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define memmapperAddAdditionalDependants(pClient, pResource, pReference) memmapperAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define memmapperGetRefCount(pResource) memmapperGetRefCount_DISPATCH(pResource) -#define memmapperCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) memmapperCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define memmapperMapTo(pResource, pParams) memmapperMapTo_DISPATCH(pResource, pParams) -#define memmapperControl_Prologue(pResource, pCallContext, pParams) memmapperControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define memmapperGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) memmapperGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define memmapperControlSerialization_Prologue(pResource, pCallContext, pParams) memmapperControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define memmapperCanCopy(pResource) memmapperCanCopy_DISPATCH(pResource) -#define memmapperInternalControlForward(pGpuResource, command, pParams, size) memmapperInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define memmapperPreDestruct(pResource) memmapperPreDestruct_DISPATCH(pResource) -#define memmapperUnmapFrom(pResource, pParams) memmapperUnmapFrom_DISPATCH(pResource, pParams) #define memmapperIsDuplicate(pResource, hMemory, pDuplicate) memmapperIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) -#define memmapperControl_Epilogue(pResource, pCallContext, pParams) memmapperControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define memmapperControlLookup(pResource, pParams, ppEntry) memmapperControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define memmapperControlSerialization_Epilogue(pResource, pCallContext, pParams) memmapperControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define memmapperMap(pGpuResource, pCallContext, pParams, pCpuMapping) memmapperMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define memmapperAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) memmapperAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS memmapperCtrlCmdSubmitPagingOperations_IMPL(struct MemoryMapper *pMemoryMapper, NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS *pParams); @@ -173,6 +177,54 @@ static inline NvBool memmapperShareCallback_DISPATCH(struct MemoryMapper *pGpuRe return pGpuResource->__memmapperShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } +static inline NV_STATUS memmapperCheckMemInterUnmap_DISPATCH(struct MemoryMapper *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__memmapperCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS memmapperMapTo_DISPATCH(struct MemoryMapper *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__memmapperMapTo__(pResource, pParams); +} + +static inline NV_STATUS memmapperGetMapAddrSpace_DISPATCH(struct MemoryMapper *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__memmapperGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 memmapperGetRefCount_DISPATCH(struct MemoryMapper *pResource) { + return pResource->__memmapperGetRefCount__(pResource); +} + +static inline void memmapperAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct MemoryMapper *pResource, RsResourceRef *pReference) { + pResource->__memmapperAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS memmapperControl_Prologue_DISPATCH(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memmapperControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS memmapperGetRegBaseOffsetAndSize_DISPATCH(struct MemoryMapper *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__memmapperGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS memmapperInternalControlForward_DISPATCH(struct MemoryMapper *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__memmapperInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS memmapperUnmapFrom_DISPATCH(struct MemoryMapper *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__memmapperUnmapFrom__(pResource, pParams); +} + +static inline void memmapperControl_Epilogue_DISPATCH(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__memmapperControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS memmapperControlLookup_DISPATCH(struct MemoryMapper *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__memmapperControlLookup__(pResource, pParams, ppEntry); +} + +static inline NvHandle memmapperGetInternalObjectHandle_DISPATCH(struct MemoryMapper *pGpuResource) { + return pGpuResource->__memmapperGetInternalObjectHandle__(pGpuResource); +} + static inline NV_STATUS memmapperControl_DISPATCH(struct MemoryMapper *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pGpuResource->__memmapperControl__(pGpuResource, pCallContext, pParams); } @@ -189,68 +241,28 @@ static inline NV_STATUS memmapperGetMemoryMappingDescriptor_DISPATCH(struct Memo return pRmResource->__memmapperGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS memmapperGetMapAddrSpace_DISPATCH(struct MemoryMapper *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__memmapperGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvHandle memmapperGetInternalObjectHandle_DISPATCH(struct MemoryMapper *pGpuResource) { - return pGpuResource->__memmapperGetInternalObjectHandle__(pGpuResource); -} - static inline NV_STATUS memmapperControlFilter_DISPATCH(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__memmapperControlFilter__(pResource, pCallContext, pParams); } -static inline void memmapperAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct MemoryMapper *pResource, RsResourceRef *pReference) { - pResource->__memmapperAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 memmapperGetRefCount_DISPATCH(struct MemoryMapper *pResource) { - return pResource->__memmapperGetRefCount__(pResource); -} - -static inline NV_STATUS memmapperCheckMemInterUnmap_DISPATCH(struct MemoryMapper *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__memmapperCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS memmapperMapTo_DISPATCH(struct MemoryMapper *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__memmapperMapTo__(pResource, pParams); -} - -static inline NV_STATUS memmapperControl_Prologue_DISPATCH(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__memmapperControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS memmapperGetRegBaseOffsetAndSize_DISPATCH(struct MemoryMapper *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__memmapperGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +static inline NV_STATUS memmapperControlSerialization_Prologue_DISPATCH(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memmapperControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool memmapperCanCopy_DISPATCH(struct MemoryMapper *pResource) { return pResource->__memmapperCanCopy__(pResource); } -static inline NV_STATUS memmapperInternalControlForward_DISPATCH(struct MemoryMapper *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__memmapperInternalControlForward__(pGpuResource, command, pParams, size); -} - static inline void memmapperPreDestruct_DISPATCH(struct MemoryMapper *pResource) { pResource->__memmapperPreDestruct__(pResource); } -static inline NV_STATUS memmapperUnmapFrom_DISPATCH(struct MemoryMapper *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__memmapperUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS memmapperIsDuplicate_DISPATCH(struct MemoryMapper *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__memmapperIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline void memmapperControl_Epilogue_DISPATCH(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__memmapperControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS memmapperControlLookup_DISPATCH(struct MemoryMapper *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__memmapperControlLookup__(pResource, pParams, ppEntry); +static inline void memmapperControlSerialization_Epilogue_DISPATCH(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__memmapperControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS memmapperMap_DISPATCH(struct MemoryMapper *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_mem_mgr_nvoc.c b/src/nvidia/generated/g_mem_mgr_nvoc.c index 889a1e4e7..7a735ec86 100644 --- a/src/nvidia/generated/g_mem_mgr_nvoc.c +++ b/src/nvidia/generated/g_mem_mgr_nvoc.c @@ -94,10 +94,6 @@ static void __nvoc_thunk_MemoryManager_engstateStateDestroy(OBJGPU *pGpu, struct memmgrStateDestroy(pGpu, (struct MemoryManager *)(((unsigned char *)pMemoryManager) - __nvoc_rtti_MemoryManager_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_memmgrReconcileTunableState(POBJGPU pGpu, struct MemoryManager *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_MemoryManager_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_memmgrStatePreLoad(POBJGPU pGpu, struct MemoryManager *pEngstate, NvU32 arg0) { return engstateStatePreLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_MemoryManager_OBJENGSTATE.offset), arg0); } @@ -118,30 +114,10 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_memmgrStatePreInitUnlocked(POBJGPU pGp return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_MemoryManager_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_memmgrGetTunableState(POBJGPU pGpu, struct MemoryManager *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_MemoryManager_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_memmgrCompareTunableState(POBJGPU pGpu, struct MemoryManager *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_MemoryManager_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_memmgrFreeTunableState(POBJGPU pGpu, struct MemoryManager *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_MemoryManager_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_memmgrStatePostLoad(POBJGPU pGpu, struct MemoryManager *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_MemoryManager_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_memmgrAllocTunableState(POBJGPU pGpu, struct MemoryManager *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_MemoryManager_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_memmgrSetTunableState(POBJGPU pGpu, struct MemoryManager *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_MemoryManager_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_memmgrIsPresent(POBJGPU pGpu, struct MemoryManager *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_MemoryManager_OBJENGSTATE.offset)); } @@ -387,6 +363,17 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe pThis->__memmgrGetFlaKind__ = &memmgrGetFlaKind_46f6a7; } + // Hal function -- memmgrIsApertureSupportedByFla + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->__memmgrIsApertureSupportedByFla__ = &memmgrIsApertureSupportedByFla_GA100; + } + // default + else + { + pThis->__memmgrIsApertureSupportedByFla__ = &memmgrIsApertureSupportedByFla_46f6a7; + } + // Hal function -- memmgrDetermineComptag if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { @@ -486,8 +473,6 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_MemoryManager_engstateStateDestroy; - pThis->__memmgrReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_memmgrReconcileTunableState; - pThis->__memmgrStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_memmgrStatePreLoad; pThis->__memmgrStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_memmgrStatePostUnload; @@ -498,18 +483,8 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe pThis->__memmgrStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_memmgrStatePreInitUnlocked; - pThis->__memmgrGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_memmgrGetTunableState; - - pThis->__memmgrCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_memmgrCompareTunableState; - - pThis->__memmgrFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_memmgrFreeTunableState; - pThis->__memmgrStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_memmgrStatePostLoad; - pThis->__memmgrAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_memmgrAllocTunableState; - - pThis->__memmgrSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_memmgrSetTunableState; - pThis->__memmgrIsPresent__ = &__nvoc_thunk_OBJENGSTATE_memmgrIsPresent; } @@ -532,13 +507,16 @@ NV_STATUS __nvoc_objCreate_MemoryManager(MemoryManager **ppThis, Dynamic *pParen MemoryManager *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(MemoryManager)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MemoryManager), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(MemoryManager)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MemoryManager); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -558,11 +536,17 @@ NV_STATUS __nvoc_objCreate_MemoryManager(MemoryManager **ppThis, Dynamic *pParen if (status != NV_OK) goto __nvoc_objCreate_MemoryManager_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_MemoryManager_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(MemoryManager)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_mem_mgr_nvoc.h b/src/nvidia/generated/g_mem_mgr_nvoc.h index 47fda2c80..d6490b56f 100644 --- a/src/nvidia/generated/g_mem_mgr_nvoc.h +++ b/src/nvidia/generated/g_mem_mgr_nvoc.h @@ -75,6 +75,11 @@ typedef enum #define TRANSFER_FLAGS_SHADOW_INIT_MEM NVBIT32(2) // Applicable only for non-PROCESSOR transfers #define TRANSFER_FLAGS_PERSISTENT_CPU_MAPPING NVBIT32(3) // Require long lived PROCESSOR mapping #define TRANSFER_FLAGS_DESTROY_MAPPING NVBIT32(4) // Destroy any cached mappings when complete +#define TRANSFER_FLAGS_USE_BAR1 NVBIT32(5) // Use only BAR1 for PROCESSOR transfers + +// Protection flags: at most 1 may be set, none means READ_WRITE by default +#define TRANSFER_FLAGS_MAP_PROTECT_READABLE NVBIT32(6) // Transfer is only reading data +#define TRANSFER_FLAGS_MAP_PROTECT_WRITEABLE NVBIT32(7) // Transfer is only writing data typedef struct { @@ -413,6 +418,7 @@ struct MemoryManager { NvU32 (*__memmgrGetPteKindPitch__)(OBJGPU *, struct MemoryManager *); NvU32 (*__memmgrChooseKindCompressC__)(OBJGPU *, struct MemoryManager *, FB_ALLOC_PAGE_FORMAT *); NV_STATUS (*__memmgrGetFlaKind__)(OBJGPU *, struct MemoryManager *, NvU32 *); + NvBool (*__memmgrIsApertureSupportedByFla__)(OBJGPU *, struct MemoryManager *, NV_ADDRESS_SPACE); NvU32 (*__memmgrDetermineComptag__)(OBJGPU *, struct MemoryManager *, RmPhysAddr); NV_STATUS (*__memmgrCheckReservedMemorySize__)(OBJGPU *, struct MemoryManager *); NV_STATUS (*__memmgrReadMmuLock__)(OBJGPU *, struct MemoryManager *, NvBool *, NvU64 *, NvU64 *); @@ -421,18 +427,12 @@ struct MemoryManager { void (*__memmgrGetDisablePlcKind__)(struct MemoryManager *, NvU32 *); void (*__memmgrEnableDynamicPageOfflining__)(OBJGPU *, struct MemoryManager *); NV_STATUS (*__memmgrGetBlackListPages__)(OBJGPU *, struct MemoryManager *, BLACKLIST_ADDRESS *, NvU32 *); - NV_STATUS (*__memmgrReconcileTunableState__)(POBJGPU, struct MemoryManager *, void *); NV_STATUS (*__memmgrStatePreLoad__)(POBJGPU, struct MemoryManager *, NvU32); NV_STATUS (*__memmgrStatePostUnload__)(POBJGPU, struct MemoryManager *, NvU32); NV_STATUS (*__memmgrStateInitUnlocked__)(POBJGPU, struct MemoryManager *); void (*__memmgrInitMissing__)(POBJGPU, struct MemoryManager *); NV_STATUS (*__memmgrStatePreInitUnlocked__)(POBJGPU, struct MemoryManager *); - NV_STATUS (*__memmgrGetTunableState__)(POBJGPU, struct MemoryManager *, void *); - NV_STATUS (*__memmgrCompareTunableState__)(POBJGPU, struct MemoryManager *, void *, void *); - void (*__memmgrFreeTunableState__)(POBJGPU, struct MemoryManager *, void *); NV_STATUS (*__memmgrStatePostLoad__)(POBJGPU, struct MemoryManager *, NvU32); - NV_STATUS (*__memmgrAllocTunableState__)(POBJGPU, struct MemoryManager *, void **); - NV_STATUS (*__memmgrSetTunableState__)(POBJGPU, struct MemoryManager *, void *); NvBool (*__memmgrIsPresent__)(POBJGPU, struct MemoryManager *); NvBool bFbsrWddmModeEnabled; NvBool bFbRegionsSupported; @@ -551,6 +551,8 @@ NV_STATUS __nvoc_objCreate_MemoryManager(MemoryManager**, Dynamic*, NvU32); #define memmgrChooseKindCompressC_HAL(pGpu, pMemoryManager, arg0) memmgrChooseKindCompressC_DISPATCH(pGpu, pMemoryManager, arg0) #define memmgrGetFlaKind(pGpu, pMemoryManager, arg0) memmgrGetFlaKind_DISPATCH(pGpu, pMemoryManager, arg0) #define memmgrGetFlaKind_HAL(pGpu, pMemoryManager, arg0) memmgrGetFlaKind_DISPATCH(pGpu, pMemoryManager, arg0) +#define memmgrIsApertureSupportedByFla(pGpu, pMemoryManager, arg0) memmgrIsApertureSupportedByFla_DISPATCH(pGpu, pMemoryManager, arg0) +#define memmgrIsApertureSupportedByFla_HAL(pGpu, pMemoryManager, arg0) memmgrIsApertureSupportedByFla_DISPATCH(pGpu, pMemoryManager, arg0) #define memmgrDetermineComptag(pGpu, pMemoryManager, arg0) memmgrDetermineComptag_DISPATCH(pGpu, pMemoryManager, arg0) #define memmgrDetermineComptag_HAL(pGpu, pMemoryManager, arg0) memmgrDetermineComptag_DISPATCH(pGpu, pMemoryManager, arg0) #define memmgrCheckReservedMemorySize(pGpu, pMemoryManager) memmgrCheckReservedMemorySize_DISPATCH(pGpu, pMemoryManager) @@ -567,18 +569,12 @@ NV_STATUS __nvoc_objCreate_MemoryManager(MemoryManager**, Dynamic*, NvU32); #define memmgrEnableDynamicPageOfflining_HAL(pGpu, pMemoryManager) memmgrEnableDynamicPageOfflining_DISPATCH(pGpu, pMemoryManager) #define memmgrGetBlackListPages(pGpu, pMemoryManager, pBlAddrs, pCount) memmgrGetBlackListPages_DISPATCH(pGpu, pMemoryManager, pBlAddrs, pCount) #define memmgrGetBlackListPages_HAL(pGpu, pMemoryManager, pBlAddrs, pCount) memmgrGetBlackListPages_DISPATCH(pGpu, pMemoryManager, pBlAddrs, pCount) -#define memmgrReconcileTunableState(pGpu, pEngstate, pTunableState) memmgrReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define memmgrStatePreLoad(pGpu, pEngstate, arg0) memmgrStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define memmgrStatePostUnload(pGpu, pEngstate, arg0) memmgrStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) #define memmgrStateInitUnlocked(pGpu, pEngstate) memmgrStateInitUnlocked_DISPATCH(pGpu, pEngstate) #define memmgrInitMissing(pGpu, pEngstate) memmgrInitMissing_DISPATCH(pGpu, pEngstate) #define memmgrStatePreInitUnlocked(pGpu, pEngstate) memmgrStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define memmgrGetTunableState(pGpu, pEngstate, pTunableState) memmgrGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define memmgrCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) memmgrCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define memmgrFreeTunableState(pGpu, pEngstate, pTunableState) memmgrFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define memmgrStatePostLoad(pGpu, pEngstate, arg0) memmgrStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define memmgrAllocTunableState(pGpu, pEngstate, ppTunableState) memmgrAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define memmgrSetTunableState(pGpu, pEngstate, pTunableState) memmgrSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define memmgrIsPresent(pGpu, pEngstate) memmgrIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS memmgrSavePowerMgmtState_KERNEL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); @@ -608,11 +604,11 @@ static inline NV_STATUS memmgrRestorePowerMgmtState(OBJGPU *pGpu, struct MemoryM #define memmgrRestorePowerMgmtState_HAL(pGpu, pMemoryManager) memmgrRestorePowerMgmtState(pGpu, pMemoryManager) -NvU32 memmgrDeterminePageSize_IMPL(struct MemoryManager *pMemoryManager, NvHandle hClient, NvU64 memSize, NvU32 memFormat, NvU32 pageFormatFlags, NvU32 *pRetAttr, NvU32 *pRetAttr2); +NvU64 memmgrDeterminePageSize_IMPL(struct MemoryManager *pMemoryManager, NvHandle hClient, NvU64 memSize, NvU32 memFormat, NvU32 pageFormatFlags, NvU32 *pRetAttr, NvU32 *pRetAttr2); #ifdef __nvoc_mem_mgr_h_disabled -static inline NvU32 memmgrDeterminePageSize(struct MemoryManager *pMemoryManager, NvHandle hClient, NvU64 memSize, NvU32 memFormat, NvU32 pageFormatFlags, NvU32 *pRetAttr, NvU32 *pRetAttr2) { +static inline NvU64 memmgrDeterminePageSize(struct MemoryManager *pMemoryManager, NvHandle hClient, NvU64 memSize, NvU32 memFormat, NvU32 pageFormatFlags, NvU32 *pRetAttr, NvU32 *pRetAttr2) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); return 0; } @@ -1760,23 +1756,23 @@ static inline void memmgrFreeFbsrMemory(OBJGPU *pGpu, struct MemoryManager *pMem #define memmgrFreeFbsrMemory_HAL(pGpu, pMemoryManager) memmgrFreeFbsrMemory(pGpu, pMemoryManager) -static inline NV_STATUS memmgrCreateVgaWorkspaceMemDesc_46f6a7(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { +static inline NV_STATUS memmgrReserveVgaWorkspaceMemDescForFbsr_46f6a7(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { return NV_ERR_NOT_SUPPORTED; } -NV_STATUS memmgrCreateVgaWorkspaceMemDesc_TU102(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); +NV_STATUS memmgrReserveVgaWorkspaceMemDescForFbsr_TU102(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); #ifdef __nvoc_mem_mgr_h_disabled -static inline NV_STATUS memmgrCreateVgaWorkspaceMemDesc(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { +static inline NV_STATUS memmgrReserveVgaWorkspaceMemDescForFbsr(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_mem_mgr_h_disabled -#define memmgrCreateVgaWorkspaceMemDesc(pGpu, pMemoryManager) memmgrCreateVgaWorkspaceMemDesc_46f6a7(pGpu, pMemoryManager) +#define memmgrReserveVgaWorkspaceMemDescForFbsr(pGpu, pMemoryManager) memmgrReserveVgaWorkspaceMemDescForFbsr_46f6a7(pGpu, pMemoryManager) #endif //__nvoc_mem_mgr_h_disabled -#define memmgrCreateVgaWorkspaceMemDesc_HAL(pGpu, pMemoryManager) memmgrCreateVgaWorkspaceMemDesc(pGpu, pMemoryManager) +#define memmgrReserveVgaWorkspaceMemDescForFbsr_HAL(pGpu, pMemoryManager) memmgrReserveVgaWorkspaceMemDescForFbsr(pGpu, pMemoryManager) NV_STATUS memmgrConstructEngine_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, ENGDESCRIPTOR arg0); @@ -1896,6 +1892,16 @@ static inline NV_STATUS memmgrGetFlaKind_DISPATCH(OBJGPU *pGpu, struct MemoryMan return pMemoryManager->__memmgrGetFlaKind__(pGpu, pMemoryManager, arg0); } +NvBool memmgrIsApertureSupportedByFla_GA100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NV_ADDRESS_SPACE arg0); + +static inline NvBool memmgrIsApertureSupportedByFla_46f6a7(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NV_ADDRESS_SPACE arg0) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NvBool memmgrIsApertureSupportedByFla_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NV_ADDRESS_SPACE arg0) { + return pMemoryManager->__memmgrIsApertureSupportedByFla__(pGpu, pMemoryManager, arg0); +} + NvU32 memmgrDetermineComptag_TU102(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, RmPhysAddr arg0); static inline NvU32 memmgrDetermineComptag_13cd8d(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, RmPhysAddr arg0) { @@ -1978,10 +1984,6 @@ static inline NV_STATUS memmgrGetBlackListPages_DISPATCH(OBJGPU *pGpu, struct Me return pMemoryManager->__memmgrGetBlackListPages__(pGpu, pMemoryManager, pBlAddrs, pCount); } -static inline NV_STATUS memmgrReconcileTunableState_DISPATCH(POBJGPU pGpu, struct MemoryManager *pEngstate, void *pTunableState) { - return pEngstate->__memmgrReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS memmgrStatePreLoad_DISPATCH(POBJGPU pGpu, struct MemoryManager *pEngstate, NvU32 arg0) { return pEngstate->__memmgrStatePreLoad__(pGpu, pEngstate, arg0); } @@ -2002,30 +2004,10 @@ static inline NV_STATUS memmgrStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct return pEngstate->__memmgrStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS memmgrGetTunableState_DISPATCH(POBJGPU pGpu, struct MemoryManager *pEngstate, void *pTunableState) { - return pEngstate->__memmgrGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS memmgrCompareTunableState_DISPATCH(POBJGPU pGpu, struct MemoryManager *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__memmgrCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void memmgrFreeTunableState_DISPATCH(POBJGPU pGpu, struct MemoryManager *pEngstate, void *pTunableState) { - pEngstate->__memmgrFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS memmgrStatePostLoad_DISPATCH(POBJGPU pGpu, struct MemoryManager *pEngstate, NvU32 arg0) { return pEngstate->__memmgrStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS memmgrAllocTunableState_DISPATCH(POBJGPU pGpu, struct MemoryManager *pEngstate, void **ppTunableState) { - return pEngstate->__memmgrAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS memmgrSetTunableState_DISPATCH(POBJGPU pGpu, struct MemoryManager *pEngstate, void *pTunableState) { - return pEngstate->__memmgrSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool memmgrIsPresent_DISPATCH(POBJGPU pGpu, struct MemoryManager *pEngstate) { return pEngstate->__memmgrIsPresent__(pGpu, pEngstate); } @@ -2520,21 +2502,10 @@ static inline NV_STATUS memmgrGetKindComprFromMemDesc(struct MemoryManager *pMem #define memmgrGetKindComprFromMemDesc(pMemoryManager, arg0, offset, kind, pComprInfo) memmgrGetKindComprFromMemDesc_IMPL(pMemoryManager, arg0, offset, kind, pComprInfo) #endif //__nvoc_mem_mgr_h_disabled -NvBool memmgrIsCompressible_IMPL(struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR *arg0); +NV_STATUS memmgrFillComprInfo_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 arg0, NvU32 arg1, NvU32 arg2, NvU64 arg3, NvU32 arg4, COMPR_INFO *arg5); #ifdef __nvoc_mem_mgr_h_disabled -static inline NvBool memmgrIsCompressible(struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR *arg0) { - NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); - return NV_FALSE; -} -#else //__nvoc_mem_mgr_h_disabled -#define memmgrIsCompressible(pMemoryManager, arg0) memmgrIsCompressible_IMPL(pMemoryManager, arg0) -#endif //__nvoc_mem_mgr_h_disabled - -NV_STATUS memmgrFillComprInfo_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 arg0, NvU32 arg1, NvU32 arg2, NvU64 arg3, NvU32 arg4, COMPR_INFO *arg5); - -#ifdef __nvoc_mem_mgr_h_disabled -static inline NV_STATUS memmgrFillComprInfo(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 arg0, NvU32 arg1, NvU32 arg2, NvU64 arg3, NvU32 arg4, COMPR_INFO *arg5) { +static inline NV_STATUS memmgrFillComprInfo(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 arg0, NvU32 arg1, NvU32 arg2, NvU64 arg3, NvU32 arg4, COMPR_INFO *arg5) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } diff --git a/src/nvidia/generated/g_mem_multicast_fabric_nvoc.c b/src/nvidia/generated/g_mem_multicast_fabric_nvoc.c index 1ef3f8f5c..a63e60632 100644 --- a/src/nvidia/generated/g_mem_multicast_fabric_nvoc.c +++ b/src/nvidia/generated/g_mem_multicast_fabric_nvoc.c @@ -121,6 +121,34 @@ static NV_STATUS __nvoc_thunk_Memory_memorymulticastfabricCheckMemInterUnmap(str return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryMulticastFabric_Memory.offset), bSubdeviceHandleProvided); } +static NvBool __nvoc_thunk_RmResource_memorymulticastfabricShareCallback(struct MemoryMulticastFabric *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RsResource_memorymulticastfabricMapTo(struct MemoryMulticastFabric *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset), pParams); +} + +static NvU32 __nvoc_thunk_RsResource_memorymulticastfabricGetRefCount(struct MemoryMulticastFabric *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_memorymulticastfabricAddAdditionalDependants(struct RsClient *pClient, struct MemoryMulticastFabric *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RsResource_memorymulticastfabricUnmapFrom(struct MemoryMulticastFabric *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_memorymulticastfabricControl_Epilogue(struct MemoryMulticastFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_memorymulticastfabricControlLookup(struct MemoryMulticastFabric *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset), pParams, ppEntry); +} + static NV_STATUS __nvoc_thunk_Memory_memorymulticastfabricUnmap(struct MemoryMulticastFabric *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryMulticastFabric_Memory.offset), pCallContext, pCpuMapping); } @@ -133,24 +161,12 @@ static NV_STATUS __nvoc_thunk_Memory_memorymulticastfabricGetMemoryMappingDescri return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryMulticastFabric_Memory.offset), ppMemDesc); } -static NvBool __nvoc_thunk_RmResource_memorymulticastfabricShareCallback(struct MemoryMulticastFabric *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); -} - static NV_STATUS __nvoc_thunk_RsResource_memorymulticastfabricControlFilter(struct MemoryMulticastFabric *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_memorymulticastfabricAddAdditionalDependants(struct RsClient *pClient, struct MemoryMulticastFabric *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_memorymulticastfabricGetRefCount(struct MemoryMulticastFabric *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RsResource_memorymulticastfabricMapTo(struct MemoryMulticastFabric *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_memorymulticastfabricControlSerialization_Prologue(struct MemoryMulticastFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_memorymulticastfabricCheckCopyPermissions(struct MemoryMulticastFabric *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { @@ -165,16 +181,8 @@ static NV_STATUS __nvoc_thunk_Memory_memorymulticastfabricIsDuplicate(struct Mem return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryMulticastFabric_Memory.offset), hMemory, pDuplicate); } -static NV_STATUS __nvoc_thunk_RsResource_memorymulticastfabricUnmapFrom(struct MemoryMulticastFabric *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RmResource_memorymulticastfabricControl_Epilogue(struct MemoryMulticastFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_memorymulticastfabricControlLookup(struct MemoryMulticastFabric *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_memorymulticastfabricControlSerialization_Epilogue(struct MemoryMulticastFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_memorymulticastfabricMap(struct MemoryMulticastFabric *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -207,12 +215,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_MemoryMu #endif }, { /* [1] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) memorymulticastfabricCtrlAttachMem_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) - /*flags=*/ 0x811u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*flags=*/ 0x810u, /*accessRight=*/0x0u, /*methodId=*/ 0xfd0102u, /*paramSize=*/ sizeof(NV00FD_CTRL_ATTACH_MEM_PARAMS), @@ -234,6 +242,36 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_MemoryMu /*pClassInfo=*/ &(__nvoc_class_def_MemoryMulticastFabric.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "memorymulticastfabricCtrlRegisterEvent" +#endif + }, + { /* [3] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) memorymulticastfabricCtrlAttachGpu_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*flags=*/ 0x810u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xfd0104u, + /*paramSize=*/ sizeof(NV00FD_CTRL_ATTACH_GPU_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_MemoryMulticastFabric.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "memorymulticastfabricCtrlAttachGpu" +#endif + }, + { /* [4] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) memorymulticastfabricCtrlDetachMem_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*flags=*/ 0x810u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xfd0105u, + /*paramSize=*/ sizeof(NV00FD_CTRL_DETACH_MEM_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_MemoryMulticastFabric.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "memorymulticastfabricCtrlDetachMem" #endif }, @@ -241,7 +279,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_MemoryMu const struct NVOC_EXPORT_INFO __nvoc_export_info_MemoryMulticastFabric = { - /*numEntries=*/ 3, + /*numEntries=*/ 5, /*pExportEntries=*/ __nvoc_exported_method_def_MemoryMulticastFabric }; @@ -296,10 +334,18 @@ static void __nvoc_init_funcTable_MemoryMulticastFabric_1(MemoryMulticastFabric pThis->__memorymulticastfabricCtrlGetInfo__ = &memorymulticastfabricCtrlGetInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) pThis->__memorymulticastfabricCtrlAttachMem__ = &memorymulticastfabricCtrlAttachMem_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + pThis->__memorymulticastfabricCtrlDetachMem__ = &memorymulticastfabricCtrlDetachMem_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + pThis->__memorymulticastfabricCtrlAttachGpu__ = &memorymulticastfabricCtrlAttachGpu_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__memorymulticastfabricCtrlRegisterEvent__ = &memorymulticastfabricCtrlRegisterEvent_IMPL; #endif @@ -318,21 +364,29 @@ static void __nvoc_init_funcTable_MemoryMulticastFabric_1(MemoryMulticastFabric pThis->__memorymulticastfabricCheckMemInterUnmap__ = &__nvoc_thunk_Memory_memorymulticastfabricCheckMemInterUnmap; + pThis->__memorymulticastfabricShareCallback__ = &__nvoc_thunk_RmResource_memorymulticastfabricShareCallback; + + pThis->__memorymulticastfabricMapTo__ = &__nvoc_thunk_RsResource_memorymulticastfabricMapTo; + + pThis->__memorymulticastfabricGetRefCount__ = &__nvoc_thunk_RsResource_memorymulticastfabricGetRefCount; + + pThis->__memorymulticastfabricAddAdditionalDependants__ = &__nvoc_thunk_RsResource_memorymulticastfabricAddAdditionalDependants; + + pThis->__memorymulticastfabricUnmapFrom__ = &__nvoc_thunk_RsResource_memorymulticastfabricUnmapFrom; + + pThis->__memorymulticastfabricControl_Epilogue__ = &__nvoc_thunk_RmResource_memorymulticastfabricControl_Epilogue; + + pThis->__memorymulticastfabricControlLookup__ = &__nvoc_thunk_RsResource_memorymulticastfabricControlLookup; + pThis->__memorymulticastfabricUnmap__ = &__nvoc_thunk_Memory_memorymulticastfabricUnmap; pThis->__memorymulticastfabricGetMemInterMapParams__ = &__nvoc_thunk_Memory_memorymulticastfabricGetMemInterMapParams; pThis->__memorymulticastfabricGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_memorymulticastfabricGetMemoryMappingDescriptor; - pThis->__memorymulticastfabricShareCallback__ = &__nvoc_thunk_RmResource_memorymulticastfabricShareCallback; - pThis->__memorymulticastfabricControlFilter__ = &__nvoc_thunk_RsResource_memorymulticastfabricControlFilter; - pThis->__memorymulticastfabricAddAdditionalDependants__ = &__nvoc_thunk_RsResource_memorymulticastfabricAddAdditionalDependants; - - pThis->__memorymulticastfabricGetRefCount__ = &__nvoc_thunk_RsResource_memorymulticastfabricGetRefCount; - - pThis->__memorymulticastfabricMapTo__ = &__nvoc_thunk_RsResource_memorymulticastfabricMapTo; + pThis->__memorymulticastfabricControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_memorymulticastfabricControlSerialization_Prologue; pThis->__memorymulticastfabricCheckCopyPermissions__ = &__nvoc_thunk_Memory_memorymulticastfabricCheckCopyPermissions; @@ -340,11 +394,7 @@ static void __nvoc_init_funcTable_MemoryMulticastFabric_1(MemoryMulticastFabric pThis->__memorymulticastfabricIsDuplicate__ = &__nvoc_thunk_Memory_memorymulticastfabricIsDuplicate; - pThis->__memorymulticastfabricUnmapFrom__ = &__nvoc_thunk_RsResource_memorymulticastfabricUnmapFrom; - - pThis->__memorymulticastfabricControl_Epilogue__ = &__nvoc_thunk_RmResource_memorymulticastfabricControl_Epilogue; - - pThis->__memorymulticastfabricControlLookup__ = &__nvoc_thunk_RsResource_memorymulticastfabricControlLookup; + pThis->__memorymulticastfabricControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_memorymulticastfabricControlSerialization_Epilogue; pThis->__memorymulticastfabricMap__ = &__nvoc_thunk_Memory_memorymulticastfabricMap; @@ -372,13 +422,16 @@ NV_STATUS __nvoc_objCreate_MemoryMulticastFabric(MemoryMulticastFabric **ppThis, Object *pParentObj; MemoryMulticastFabric *pThis; - pThis = portMemAllocNonPaged(sizeof(MemoryMulticastFabric)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MemoryMulticastFabric), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(MemoryMulticastFabric)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MemoryMulticastFabric); + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -394,11 +447,17 @@ NV_STATUS __nvoc_objCreate_MemoryMulticastFabric(MemoryMulticastFabric **ppThis, if (status != NV_OK) goto __nvoc_objCreate_MemoryMulticastFabric_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_MemoryMulticastFabric_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(MemoryMulticastFabric)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_mem_multicast_fabric_nvoc.h b/src/nvidia/generated/g_mem_multicast_fabric_nvoc.h index 20c234721..b3fd25134 100644 --- a/src/nvidia/generated/g_mem_multicast_fabric_nvoc.h +++ b/src/nvidia/generated/g_mem_multicast_fabric_nvoc.h @@ -53,17 +53,14 @@ extern "C" { // **************************************************************************** // Type Definitions // **************************************************************************** -typedef struct mem_multicast_fabric_attach_mem_info + +typedef struct mem_multicast_fabric_attach_mem_info_node { - NvU64 offset; - NvU64 mapOffset; - NvU64 mapLength; - NvU32 flags; - OBJGPU *pGpu; MEMORY_DESCRIPTOR *pPhysMemDesc; NvHandle hDupedPhysMem; - NvU64 gpuProbeHandle; -} MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO; + NvU64 physMapLength; + NODE node; +} MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO_NODE; typedef struct mem_multicast_fabric_client_info { @@ -71,16 +68,20 @@ typedef struct mem_multicast_fabric_client_info struct Memory *pMemory; } MEM_MULTICAST_FABRIC_CLIENT_INFO; -typedef struct mem_multicast_fabric_gpu_os_info +typedef struct mem_multicast_fabric_gpu_info { - void *gpuOsInfo; -} MEM_MULTICAST_FABRIC_GPU_OS_INFO; + void *pGpuOsInfo; + OBJGPU *pGpu; + NvU64 gpuProbeHandle; + NvBool bMcflaAlloc; -MAKE_LIST(MemMulticastFabricAttachMemInfoList, MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO); + // Tracks memory attached using NV00FD_CTRL_CMD_ATTACH_MEM + PNODE pAttachMemInfoTree; +} MEM_MULTICAST_FABRIC_GPU_INFO; MAKE_LIST(MemMulticastFabricClientInfoList, MEM_MULTICAST_FABRIC_CLIENT_INFO); -MAKE_LIST(MemMulticastFabricGpuOsInfoList, MEM_MULTICAST_FABRIC_GPU_OS_INFO); +MAKE_LIST(MemMulticastFabricGpuInfoList, MEM_MULTICAST_FABRIC_GPU_INFO); typedef enum { @@ -96,14 +97,11 @@ typedef struct mem_multicast_fabric_descriptor // List of clients waiting on this object to be ready MemMulticastFabricClientInfoList waitingClientsList; - // List of attach mem info of GPUs already attached to the mutlicast object - MemMulticastFabricAttachMemInfoList attachMemInfoList; - // Mask representing the list of attached GPUs NvU32 attachedGpusMask; - // List of GPU OS Info - MemMulticastFabricGpuOsInfoList gpuOsInfoList; + // List of attached GPU info + MemMulticastFabricGpuInfoList gpuInfoList; // Boolean to be set when pMemDesc is installed NvBool bMemdescInstalled; @@ -130,7 +128,7 @@ typedef struct mem_multicast_fabric_descriptor NvU64 allocSize; // Page size for the multicast FLA - NvU32 pageSize; + NvU64 pageSize; // Multicast FLA allocation flags NvU32 allocFlags; @@ -165,22 +163,26 @@ struct MemoryMulticastFabric { NV_STATUS (*__memorymulticastfabricGetMapAddrSpace__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); NV_STATUS (*__memorymulticastfabricCtrlGetInfo__)(struct MemoryMulticastFabric *, NV00FD_CTRL_GET_INFO_PARAMS *); NV_STATUS (*__memorymulticastfabricCtrlAttachMem__)(struct MemoryMulticastFabric *, NV00FD_CTRL_ATTACH_MEM_PARAMS *); + NV_STATUS (*__memorymulticastfabricCtrlDetachMem__)(struct MemoryMulticastFabric *, NV00FD_CTRL_DETACH_MEM_PARAMS *); + NV_STATUS (*__memorymulticastfabricCtrlAttachGpu__)(struct MemoryMulticastFabric *, NV00FD_CTRL_ATTACH_GPU_PARAMS *); NV_STATUS (*__memorymulticastfabricCtrlRegisterEvent__)(struct MemoryMulticastFabric *, NV00FD_CTRL_REGISTER_EVENT_PARAMS *); NV_STATUS (*__memorymulticastfabricCheckMemInterUnmap__)(struct MemoryMulticastFabric *, NvBool); - NV_STATUS (*__memorymulticastfabricUnmap__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, RsCpuMapping *); - NV_STATUS (*__memorymulticastfabricGetMemInterMapParams__)(struct MemoryMulticastFabric *, RMRES_MEM_INTER_MAP_PARAMS *); - NV_STATUS (*__memorymulticastfabricGetMemoryMappingDescriptor__)(struct MemoryMulticastFabric *, MEMORY_DESCRIPTOR **); NvBool (*__memorymulticastfabricShareCallback__)(struct MemoryMulticastFabric *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__memorymulticastfabricControlFilter__)(struct MemoryMulticastFabric *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__memorymulticastfabricAddAdditionalDependants__)(struct RsClient *, struct MemoryMulticastFabric *, RsResourceRef *); - NvU32 (*__memorymulticastfabricGetRefCount__)(struct MemoryMulticastFabric *); NV_STATUS (*__memorymulticastfabricMapTo__)(struct MemoryMulticastFabric *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__memorymulticastfabricCheckCopyPermissions__)(struct MemoryMulticastFabric *, struct OBJGPU *, NvHandle); - void (*__memorymulticastfabricPreDestruct__)(struct MemoryMulticastFabric *); - NV_STATUS (*__memorymulticastfabricIsDuplicate__)(struct MemoryMulticastFabric *, NvHandle, NvBool *); + NvU32 (*__memorymulticastfabricGetRefCount__)(struct MemoryMulticastFabric *); + void (*__memorymulticastfabricAddAdditionalDependants__)(struct RsClient *, struct MemoryMulticastFabric *, RsResourceRef *); NV_STATUS (*__memorymulticastfabricUnmapFrom__)(struct MemoryMulticastFabric *, RS_RES_UNMAP_FROM_PARAMS *); void (*__memorymulticastfabricControl_Epilogue__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memorymulticastfabricControlLookup__)(struct MemoryMulticastFabric *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__memorymulticastfabricUnmap__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__memorymulticastfabricGetMemInterMapParams__)(struct MemoryMulticastFabric *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__memorymulticastfabricGetMemoryMappingDescriptor__)(struct MemoryMulticastFabric *, MEMORY_DESCRIPTOR **); + NV_STATUS (*__memorymulticastfabricControlFilter__)(struct MemoryMulticastFabric *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memorymulticastfabricControlSerialization_Prologue__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memorymulticastfabricCheckCopyPermissions__)(struct MemoryMulticastFabric *, struct OBJGPU *, NvHandle); + void (*__memorymulticastfabricPreDestruct__)(struct MemoryMulticastFabric *); + NV_STATUS (*__memorymulticastfabricIsDuplicate__)(struct MemoryMulticastFabric *, NvHandle, NvBool *); + void (*__memorymulticastfabricControlSerialization_Epilogue__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memorymulticastfabricMap__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__memorymulticastfabricAccessCallback__)(struct MemoryMulticastFabric *, struct RsClient *, void *, RsAccessRight); MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc; @@ -223,22 +225,26 @@ NV_STATUS __nvoc_objCreate_MemoryMulticastFabric(MemoryMulticastFabric**, Dynami #define memorymulticastfabricGetMapAddrSpace(pMemoryMulticastFabric, pCallContext, mapFlags, pAddrSpace) memorymulticastfabricGetMapAddrSpace_DISPATCH(pMemoryMulticastFabric, pCallContext, mapFlags, pAddrSpace) #define memorymulticastfabricCtrlGetInfo(pMemoryMulticastFabric, pParams) memorymulticastfabricCtrlGetInfo_DISPATCH(pMemoryMulticastFabric, pParams) #define memorymulticastfabricCtrlAttachMem(pMemoryMulticastFabric, pParams) memorymulticastfabricCtrlAttachMem_DISPATCH(pMemoryMulticastFabric, pParams) +#define memorymulticastfabricCtrlDetachMem(pMemoryMulticastFabric, pParams) memorymulticastfabricCtrlDetachMem_DISPATCH(pMemoryMulticastFabric, pParams) +#define memorymulticastfabricCtrlAttachGpu(pMemoryMulticastFabric, pParams) memorymulticastfabricCtrlAttachGpu_DISPATCH(pMemoryMulticastFabric, pParams) #define memorymulticastfabricCtrlRegisterEvent(pMemoryMulticastFabric, pParams) memorymulticastfabricCtrlRegisterEvent_DISPATCH(pMemoryMulticastFabric, pParams) #define memorymulticastfabricCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) memorymulticastfabricCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) -#define memorymulticastfabricUnmap(pMemory, pCallContext, pCpuMapping) memorymulticastfabricUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) -#define memorymulticastfabricGetMemInterMapParams(pMemory, pParams) memorymulticastfabricGetMemInterMapParams_DISPATCH(pMemory, pParams) -#define memorymulticastfabricGetMemoryMappingDescriptor(pMemory, ppMemDesc) memorymulticastfabricGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) #define memorymulticastfabricShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) memorymulticastfabricShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) -#define memorymulticastfabricControlFilter(pResource, pCallContext, pParams) memorymulticastfabricControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define memorymulticastfabricAddAdditionalDependants(pClient, pResource, pReference) memorymulticastfabricAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define memorymulticastfabricGetRefCount(pResource) memorymulticastfabricGetRefCount_DISPATCH(pResource) #define memorymulticastfabricMapTo(pResource, pParams) memorymulticastfabricMapTo_DISPATCH(pResource, pParams) -#define memorymulticastfabricCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) memorymulticastfabricCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) -#define memorymulticastfabricPreDestruct(pResource) memorymulticastfabricPreDestruct_DISPATCH(pResource) -#define memorymulticastfabricIsDuplicate(pMemory, hMemory, pDuplicate) memorymulticastfabricIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) +#define memorymulticastfabricGetRefCount(pResource) memorymulticastfabricGetRefCount_DISPATCH(pResource) +#define memorymulticastfabricAddAdditionalDependants(pClient, pResource, pReference) memorymulticastfabricAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define memorymulticastfabricUnmapFrom(pResource, pParams) memorymulticastfabricUnmapFrom_DISPATCH(pResource, pParams) #define memorymulticastfabricControl_Epilogue(pResource, pCallContext, pParams) memorymulticastfabricControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define memorymulticastfabricControlLookup(pResource, pParams, ppEntry) memorymulticastfabricControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define memorymulticastfabricUnmap(pMemory, pCallContext, pCpuMapping) memorymulticastfabricUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) +#define memorymulticastfabricGetMemInterMapParams(pMemory, pParams) memorymulticastfabricGetMemInterMapParams_DISPATCH(pMemory, pParams) +#define memorymulticastfabricGetMemoryMappingDescriptor(pMemory, ppMemDesc) memorymulticastfabricGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) +#define memorymulticastfabricControlFilter(pResource, pCallContext, pParams) memorymulticastfabricControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define memorymulticastfabricControlSerialization_Prologue(pResource, pCallContext, pParams) memorymulticastfabricControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define memorymulticastfabricCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) memorymulticastfabricCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define memorymulticastfabricPreDestruct(pResource) memorymulticastfabricPreDestruct_DISPATCH(pResource) +#define memorymulticastfabricIsDuplicate(pMemory, hMemory, pDuplicate) memorymulticastfabricIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) +#define memorymulticastfabricControlSerialization_Epilogue(pResource, pCallContext, pParams) memorymulticastfabricControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define memorymulticastfabricMap(pMemory, pCallContext, pParams, pCpuMapping) memorymulticastfabricMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define memorymulticastfabricAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) memorymulticastfabricAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool memorymulticastfabricCanCopy_IMPL(struct MemoryMulticastFabric *pMemoryMulticastFabric); @@ -295,6 +301,18 @@ static inline NV_STATUS memorymulticastfabricCtrlAttachMem_DISPATCH(struct Memor return pMemoryMulticastFabric->__memorymulticastfabricCtrlAttachMem__(pMemoryMulticastFabric, pParams); } +NV_STATUS memorymulticastfabricCtrlDetachMem_IMPL(struct MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_DETACH_MEM_PARAMS *pParams); + +static inline NV_STATUS memorymulticastfabricCtrlDetachMem_DISPATCH(struct MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_DETACH_MEM_PARAMS *pParams) { + return pMemoryMulticastFabric->__memorymulticastfabricCtrlDetachMem__(pMemoryMulticastFabric, pParams); +} + +NV_STATUS memorymulticastfabricCtrlAttachGpu_IMPL(struct MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_ATTACH_GPU_PARAMS *pParams); + +static inline NV_STATUS memorymulticastfabricCtrlAttachGpu_DISPATCH(struct MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_ATTACH_GPU_PARAMS *pParams) { + return pMemoryMulticastFabric->__memorymulticastfabricCtrlAttachGpu__(pMemoryMulticastFabric, pParams); +} + NV_STATUS memorymulticastfabricCtrlRegisterEvent_IMPL(struct MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_REGISTER_EVENT_PARAMS *pParams); static inline NV_STATUS memorymulticastfabricCtrlRegisterEvent_DISPATCH(struct MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_REGISTER_EVENT_PARAMS *pParams) { @@ -305,6 +323,34 @@ static inline NV_STATUS memorymulticastfabricCheckMemInterUnmap_DISPATCH(struct return pMemory->__memorymulticastfabricCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } +static inline NvBool memorymulticastfabricShareCallback_DISPATCH(struct MemoryMulticastFabric *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__memorymulticastfabricShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS memorymulticastfabricMapTo_DISPATCH(struct MemoryMulticastFabric *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__memorymulticastfabricMapTo__(pResource, pParams); +} + +static inline NvU32 memorymulticastfabricGetRefCount_DISPATCH(struct MemoryMulticastFabric *pResource) { + return pResource->__memorymulticastfabricGetRefCount__(pResource); +} + +static inline void memorymulticastfabricAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct MemoryMulticastFabric *pResource, RsResourceRef *pReference) { + pResource->__memorymulticastfabricAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS memorymulticastfabricUnmapFrom_DISPATCH(struct MemoryMulticastFabric *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__memorymulticastfabricUnmapFrom__(pResource, pParams); +} + +static inline void memorymulticastfabricControl_Epilogue_DISPATCH(struct MemoryMulticastFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__memorymulticastfabricControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS memorymulticastfabricControlLookup_DISPATCH(struct MemoryMulticastFabric *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__memorymulticastfabricControlLookup__(pResource, pParams, ppEntry); +} + static inline NV_STATUS memorymulticastfabricUnmap_DISPATCH(struct MemoryMulticastFabric *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { return pMemory->__memorymulticastfabricUnmap__(pMemory, pCallContext, pCpuMapping); } @@ -317,24 +363,12 @@ static inline NV_STATUS memorymulticastfabricGetMemoryMappingDescriptor_DISPATCH return pMemory->__memorymulticastfabricGetMemoryMappingDescriptor__(pMemory, ppMemDesc); } -static inline NvBool memorymulticastfabricShareCallback_DISPATCH(struct MemoryMulticastFabric *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pResource->__memorymulticastfabricShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); -} - static inline NV_STATUS memorymulticastfabricControlFilter_DISPATCH(struct MemoryMulticastFabric *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__memorymulticastfabricControlFilter__(pResource, pCallContext, pParams); } -static inline void memorymulticastfabricAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct MemoryMulticastFabric *pResource, RsResourceRef *pReference) { - pResource->__memorymulticastfabricAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 memorymulticastfabricGetRefCount_DISPATCH(struct MemoryMulticastFabric *pResource) { - return pResource->__memorymulticastfabricGetRefCount__(pResource); -} - -static inline NV_STATUS memorymulticastfabricMapTo_DISPATCH(struct MemoryMulticastFabric *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__memorymulticastfabricMapTo__(pResource, pParams); +static inline NV_STATUS memorymulticastfabricControlSerialization_Prologue_DISPATCH(struct MemoryMulticastFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memorymulticastfabricControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS memorymulticastfabricCheckCopyPermissions_DISPATCH(struct MemoryMulticastFabric *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { @@ -349,16 +383,8 @@ static inline NV_STATUS memorymulticastfabricIsDuplicate_DISPATCH(struct MemoryM return pMemory->__memorymulticastfabricIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline NV_STATUS memorymulticastfabricUnmapFrom_DISPATCH(struct MemoryMulticastFabric *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__memorymulticastfabricUnmapFrom__(pResource, pParams); -} - -static inline void memorymulticastfabricControl_Epilogue_DISPATCH(struct MemoryMulticastFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__memorymulticastfabricControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS memorymulticastfabricControlLookup_DISPATCH(struct MemoryMulticastFabric *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__memorymulticastfabricControlLookup__(pResource, pParams, ppEntry); +static inline void memorymulticastfabricControlSerialization_Epilogue_DISPATCH(struct MemoryMulticastFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__memorymulticastfabricControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS memorymulticastfabricMap_DISPATCH(struct MemoryMulticastFabric *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -378,7 +404,7 @@ void memorymulticastfabricDestruct_IMPL(struct MemoryMulticastFabric *pMemoryMul #undef PRIVATE_FIELD -void memorymulticastfabricTeamSetupResponseCallback(OBJGPU *pGpu, +void memorymulticastfabricTeamSetupResponseCallback(NvU32 gpuInstance, NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pMessage); #endif // _MEMORYMULTICASTFABRIC_H_ diff --git a/src/nvidia/generated/g_mem_nvoc.c b/src/nvidia/generated/g_mem_nvoc.c index e8987e1bf..1c9ea88dc 100644 --- a/src/nvidia/generated/g_mem_nvoc.c +++ b/src/nvidia/generated/g_mem_nvoc.c @@ -128,6 +128,14 @@ static void __nvoc_thunk_RsResource_memAddAdditionalDependants(struct RsClient * resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Memory_RsResource.offset), pReference); } +static NV_STATUS __nvoc_thunk_RsResource_memUnmapFrom(struct Memory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Memory_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_memControlSerialization_Prologue(struct Memory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Memory_RmResource.offset), pCallContext, pParams); +} + static NV_STATUS __nvoc_thunk_RmResource_memControl_Prologue(struct Memory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Memory_RmResource.offset), pCallContext, pParams); } @@ -136,16 +144,16 @@ static NvBool __nvoc_thunk_RsResource_memCanCopy(struct Memory *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Memory_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_memMapTo(struct Memory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Memory_RsResource.offset), pParams); -} - static void __nvoc_thunk_RsResource_memPreDestruct(struct Memory *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Memory_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_memUnmapFrom(struct Memory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Memory_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_memMapTo(struct Memory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Memory_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_memControlSerialization_Epilogue(struct Memory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Memory_RmResource.offset), pCallContext, pParams); } static void __nvoc_thunk_RmResource_memControl_Epilogue(struct Memory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -366,15 +374,19 @@ static void __nvoc_init_funcTable_Memory_1(Memory *pThis) { pThis->__memAddAdditionalDependants__ = &__nvoc_thunk_RsResource_memAddAdditionalDependants; + pThis->__memUnmapFrom__ = &__nvoc_thunk_RsResource_memUnmapFrom; + + pThis->__memControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_memControlSerialization_Prologue; + pThis->__memControl_Prologue__ = &__nvoc_thunk_RmResource_memControl_Prologue; pThis->__memCanCopy__ = &__nvoc_thunk_RsResource_memCanCopy; - pThis->__memMapTo__ = &__nvoc_thunk_RsResource_memMapTo; - pThis->__memPreDestruct__ = &__nvoc_thunk_RsResource_memPreDestruct; - pThis->__memUnmapFrom__ = &__nvoc_thunk_RsResource_memUnmapFrom; + pThis->__memMapTo__ = &__nvoc_thunk_RsResource_memMapTo; + + pThis->__memControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_memControlSerialization_Epilogue; pThis->__memControl_Epilogue__ = &__nvoc_thunk_RmResource_memControl_Epilogue; @@ -403,13 +415,16 @@ NV_STATUS __nvoc_objCreate_Memory(Memory **ppThis, Dynamic *pParent, NvU32 creat Object *pParentObj; Memory *pThis; - pThis = portMemAllocNonPaged(sizeof(Memory)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Memory), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(Memory)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Memory); + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -425,11 +440,17 @@ NV_STATUS __nvoc_objCreate_Memory(Memory **ppThis, Dynamic *pParent, NvU32 creat if (status != NV_OK) goto __nvoc_objCreate_Memory_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_Memory_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(Memory)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_mem_nvoc.h b/src/nvidia/generated/g_mem_nvoc.h index e36eecfc5..5105051bb 100644 --- a/src/nvidia/generated/g_mem_nvoc.h +++ b/src/nvidia/generated/g_mem_nvoc.h @@ -120,7 +120,6 @@ typedef struct _def_client_vgpu_ns_intr NvU64 guestMSIAddr; // MSI address allocated by guest OS NvU32 guestMSIData; // MSI data value set by guest OS void *pVgpuVfioRef; // Reference to vgpu device in nvidia-vgpu-vfio module - void *pVmBusHostChannel; // VmBus Host channel to communicated the event with the Guest void *pEventDpc; // DPC event to pass the interrupt } VGPU_NS_INTR; @@ -170,11 +169,13 @@ struct Memory { NvU32 (*__memGetRefCount__)(struct Memory *); NV_STATUS (*__memControlFilter__)(struct Memory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__memAddAdditionalDependants__)(struct RsClient *, struct Memory *, RsResourceRef *); + NV_STATUS (*__memUnmapFrom__)(struct Memory *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__memControlSerialization_Prologue__)(struct Memory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memControl_Prologue__)(struct Memory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__memCanCopy__)(struct Memory *); - NV_STATUS (*__memMapTo__)(struct Memory *, RS_RES_MAP_TO_PARAMS *); void (*__memPreDestruct__)(struct Memory *); - NV_STATUS (*__memUnmapFrom__)(struct Memory *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__memMapTo__)(struct Memory *, RS_RES_MAP_TO_PARAMS *); + void (*__memControlSerialization_Epilogue__)(struct Memory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__memControl_Epilogue__)(struct Memory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memControlLookup__)(struct Memory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvBool (*__memAccessCallback__)(struct Memory *, struct RsClient *, void *, RsAccessRight); @@ -256,11 +257,13 @@ NV_STATUS __nvoc_objCreate_Memory(Memory**, Dynamic*, NvU32, CALL_CONTEXT * arg_ #define memGetRefCount(pResource) memGetRefCount_DISPATCH(pResource) #define memControlFilter(pResource, pCallContext, pParams) memControlFilter_DISPATCH(pResource, pCallContext, pParams) #define memAddAdditionalDependants(pClient, pResource, pReference) memAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define memUnmapFrom(pResource, pParams) memUnmapFrom_DISPATCH(pResource, pParams) +#define memControlSerialization_Prologue(pResource, pCallContext, pParams) memControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define memControl_Prologue(pResource, pCallContext, pParams) memControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define memCanCopy(pResource) memCanCopy_DISPATCH(pResource) -#define memMapTo(pResource, pParams) memMapTo_DISPATCH(pResource, pParams) #define memPreDestruct(pResource) memPreDestruct_DISPATCH(pResource) -#define memUnmapFrom(pResource, pParams) memUnmapFrom_DISPATCH(pResource, pParams) +#define memMapTo(pResource, pParams) memMapTo_DISPATCH(pResource, pParams) +#define memControlSerialization_Epilogue(pResource, pCallContext, pParams) memControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define memControl_Epilogue(pResource, pCallContext, pParams) memControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define memControlLookup(pResource, pParams, ppEntry) memControlLookup_DISPATCH(pResource, pParams, ppEntry) #define memAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) memAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) @@ -388,6 +391,14 @@ static inline void memAddAdditionalDependants_DISPATCH(struct RsClient *pClient, pResource->__memAddAdditionalDependants__(pClient, pResource, pReference); } +static inline NV_STATUS memUnmapFrom_DISPATCH(struct Memory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__memUnmapFrom__(pResource, pParams); +} + +static inline NV_STATUS memControlSerialization_Prologue_DISPATCH(struct Memory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NV_STATUS memControl_Prologue_DISPATCH(struct Memory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__memControl_Prologue__(pResource, pCallContext, pParams); } @@ -396,16 +407,16 @@ static inline NvBool memCanCopy_DISPATCH(struct Memory *pResource) { return pResource->__memCanCopy__(pResource); } -static inline NV_STATUS memMapTo_DISPATCH(struct Memory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__memMapTo__(pResource, pParams); -} - static inline void memPreDestruct_DISPATCH(struct Memory *pResource) { pResource->__memPreDestruct__(pResource); } -static inline NV_STATUS memUnmapFrom_DISPATCH(struct Memory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__memUnmapFrom__(pResource, pParams); +static inline NV_STATUS memMapTo_DISPATCH(struct Memory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__memMapTo__(pResource, pParams); +} + +static inline void memControlSerialization_Epilogue_DISPATCH(struct Memory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__memControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline void memControl_Epilogue_DISPATCH(struct Memory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { diff --git a/src/nvidia/generated/g_mig_config_session_nvoc.c b/src/nvidia/generated/g_mig_config_session_nvoc.c index 175098c4d..116872ad8 100644 --- a/src/nvidia/generated/g_mig_config_session_nvoc.c +++ b/src/nvidia/generated/g_mig_config_session_nvoc.c @@ -116,8 +116,12 @@ static void __nvoc_thunk_RsResource_migconfigsessionAddAdditionalDependants(stru resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_migconfigsessionUnmap(struct MIGConfigSession *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RsResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_migconfigsessionUnmapFrom(struct MIGConfigSession *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_migconfigsessionControlSerialization_Prologue(struct MIGConfigSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_RmResource_migconfigsessionControl_Prologue(struct MIGConfigSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -128,22 +132,26 @@ static NvBool __nvoc_thunk_RsResource_migconfigsessionCanCopy(struct MIGConfigSe return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_migconfigsessionMapTo(struct MIGConfigSession *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_migconfigsessionUnmap(struct MIGConfigSession *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RsResource.offset), pCallContext, pCpuMapping); } static void __nvoc_thunk_RsResource_migconfigsessionPreDestruct(struct MIGConfigSession *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_migconfigsessionUnmapFrom(struct MIGConfigSession *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_migconfigsessionMapTo(struct MIGConfigSession *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_RsResource_migconfigsessionIsDuplicate(struct MIGConfigSession *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_migconfigsessionControlSerialization_Epilogue(struct MIGConfigSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RmResource.offset), pCallContext, pParams); +} + static void __nvoc_thunk_RmResource_migconfigsessionControl_Epilogue(struct MIGConfigSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RmResource.offset), pCallContext, pParams); } @@ -215,20 +223,24 @@ static void __nvoc_init_funcTable_MIGConfigSession_1(MIGConfigSession *pThis) { pThis->__migconfigsessionAddAdditionalDependants__ = &__nvoc_thunk_RsResource_migconfigsessionAddAdditionalDependants; - pThis->__migconfigsessionUnmap__ = &__nvoc_thunk_RsResource_migconfigsessionUnmap; + pThis->__migconfigsessionUnmapFrom__ = &__nvoc_thunk_RsResource_migconfigsessionUnmapFrom; + + pThis->__migconfigsessionControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_migconfigsessionControlSerialization_Prologue; pThis->__migconfigsessionControl_Prologue__ = &__nvoc_thunk_RmResource_migconfigsessionControl_Prologue; pThis->__migconfigsessionCanCopy__ = &__nvoc_thunk_RsResource_migconfigsessionCanCopy; - pThis->__migconfigsessionMapTo__ = &__nvoc_thunk_RsResource_migconfigsessionMapTo; + pThis->__migconfigsessionUnmap__ = &__nvoc_thunk_RsResource_migconfigsessionUnmap; pThis->__migconfigsessionPreDestruct__ = &__nvoc_thunk_RsResource_migconfigsessionPreDestruct; - pThis->__migconfigsessionUnmapFrom__ = &__nvoc_thunk_RsResource_migconfigsessionUnmapFrom; + pThis->__migconfigsessionMapTo__ = &__nvoc_thunk_RsResource_migconfigsessionMapTo; pThis->__migconfigsessionIsDuplicate__ = &__nvoc_thunk_RsResource_migconfigsessionIsDuplicate; + pThis->__migconfigsessionControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_migconfigsessionControlSerialization_Epilogue; + pThis->__migconfigsessionControl_Epilogue__ = &__nvoc_thunk_RmResource_migconfigsessionControl_Epilogue; pThis->__migconfigsessionControlLookup__ = &__nvoc_thunk_RsResource_migconfigsessionControlLookup; @@ -258,13 +270,16 @@ NV_STATUS __nvoc_objCreate_MIGConfigSession(MIGConfigSession **ppThis, Dynamic * Object *pParentObj; MIGConfigSession *pThis; - pThis = portMemAllocNonPaged(sizeof(MIGConfigSession)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MIGConfigSession), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(MIGConfigSession)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MIGConfigSession); + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -280,11 +295,17 @@ NV_STATUS __nvoc_objCreate_MIGConfigSession(MIGConfigSession **ppThis, Dynamic * if (status != NV_OK) goto __nvoc_objCreate_MIGConfigSession_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_MIGConfigSession_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(MIGConfigSession)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_mig_config_session_nvoc.h b/src/nvidia/generated/g_mig_config_session_nvoc.h index 28304fd44..37b322e85 100644 --- a/src/nvidia/generated/g_mig_config_session_nvoc.h +++ b/src/nvidia/generated/g_mig_config_session_nvoc.h @@ -73,13 +73,15 @@ struct MIGConfigSession { NvU32 (*__migconfigsessionGetRefCount__)(struct MIGConfigSession *); NV_STATUS (*__migconfigsessionControlFilter__)(struct MIGConfigSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__migconfigsessionAddAdditionalDependants__)(struct RsClient *, struct MIGConfigSession *, RsResourceRef *); - NV_STATUS (*__migconfigsessionUnmap__)(struct MIGConfigSession *, struct CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__migconfigsessionUnmapFrom__)(struct MIGConfigSession *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__migconfigsessionControlSerialization_Prologue__)(struct MIGConfigSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__migconfigsessionControl_Prologue__)(struct MIGConfigSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__migconfigsessionCanCopy__)(struct MIGConfigSession *); - NV_STATUS (*__migconfigsessionMapTo__)(struct MIGConfigSession *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__migconfigsessionUnmap__)(struct MIGConfigSession *, struct CALL_CONTEXT *, RsCpuMapping *); void (*__migconfigsessionPreDestruct__)(struct MIGConfigSession *); - NV_STATUS (*__migconfigsessionUnmapFrom__)(struct MIGConfigSession *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__migconfigsessionMapTo__)(struct MIGConfigSession *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__migconfigsessionIsDuplicate__)(struct MIGConfigSession *, NvHandle, NvBool *); + void (*__migconfigsessionControlSerialization_Epilogue__)(struct MIGConfigSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__migconfigsessionControl_Epilogue__)(struct MIGConfigSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__migconfigsessionControlLookup__)(struct MIGConfigSession *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__migconfigsessionMap__)(struct MIGConfigSession *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -123,13 +125,15 @@ NV_STATUS __nvoc_objCreate_MIGConfigSession(MIGConfigSession**, Dynamic*, NvU32, #define migconfigsessionGetRefCount(pResource) migconfigsessionGetRefCount_DISPATCH(pResource) #define migconfigsessionControlFilter(pResource, pCallContext, pParams) migconfigsessionControlFilter_DISPATCH(pResource, pCallContext, pParams) #define migconfigsessionAddAdditionalDependants(pClient, pResource, pReference) migconfigsessionAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define migconfigsessionUnmap(pResource, pCallContext, pCpuMapping) migconfigsessionUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define migconfigsessionUnmapFrom(pResource, pParams) migconfigsessionUnmapFrom_DISPATCH(pResource, pParams) +#define migconfigsessionControlSerialization_Prologue(pResource, pCallContext, pParams) migconfigsessionControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define migconfigsessionControl_Prologue(pResource, pCallContext, pParams) migconfigsessionControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define migconfigsessionCanCopy(pResource) migconfigsessionCanCopy_DISPATCH(pResource) -#define migconfigsessionMapTo(pResource, pParams) migconfigsessionMapTo_DISPATCH(pResource, pParams) +#define migconfigsessionUnmap(pResource, pCallContext, pCpuMapping) migconfigsessionUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define migconfigsessionPreDestruct(pResource) migconfigsessionPreDestruct_DISPATCH(pResource) -#define migconfigsessionUnmapFrom(pResource, pParams) migconfigsessionUnmapFrom_DISPATCH(pResource, pParams) +#define migconfigsessionMapTo(pResource, pParams) migconfigsessionMapTo_DISPATCH(pResource, pParams) #define migconfigsessionIsDuplicate(pResource, hMemory, pDuplicate) migconfigsessionIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define migconfigsessionControlSerialization_Epilogue(pResource, pCallContext, pParams) migconfigsessionControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define migconfigsessionControl_Epilogue(pResource, pCallContext, pParams) migconfigsessionControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define migconfigsessionControlLookup(pResource, pParams, ppEntry) migconfigsessionControlLookup_DISPATCH(pResource, pParams, ppEntry) #define migconfigsessionMap(pResource, pCallContext, pParams, pCpuMapping) migconfigsessionMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -166,8 +170,12 @@ static inline void migconfigsessionAddAdditionalDependants_DISPATCH(struct RsCli pResource->__migconfigsessionAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS migconfigsessionUnmap_DISPATCH(struct MIGConfigSession *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pResource->__migconfigsessionUnmap__(pResource, pCallContext, pCpuMapping); +static inline NV_STATUS migconfigsessionUnmapFrom_DISPATCH(struct MIGConfigSession *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__migconfigsessionUnmapFrom__(pResource, pParams); +} + +static inline NV_STATUS migconfigsessionControlSerialization_Prologue_DISPATCH(struct MIGConfigSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__migconfigsessionControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS migconfigsessionControl_Prologue_DISPATCH(struct MIGConfigSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -178,22 +186,26 @@ static inline NvBool migconfigsessionCanCopy_DISPATCH(struct MIGConfigSession *p return pResource->__migconfigsessionCanCopy__(pResource); } -static inline NV_STATUS migconfigsessionMapTo_DISPATCH(struct MIGConfigSession *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__migconfigsessionMapTo__(pResource, pParams); +static inline NV_STATUS migconfigsessionUnmap_DISPATCH(struct MIGConfigSession *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__migconfigsessionUnmap__(pResource, pCallContext, pCpuMapping); } static inline void migconfigsessionPreDestruct_DISPATCH(struct MIGConfigSession *pResource) { pResource->__migconfigsessionPreDestruct__(pResource); } -static inline NV_STATUS migconfigsessionUnmapFrom_DISPATCH(struct MIGConfigSession *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__migconfigsessionUnmapFrom__(pResource, pParams); +static inline NV_STATUS migconfigsessionMapTo_DISPATCH(struct MIGConfigSession *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__migconfigsessionMapTo__(pResource, pParams); } static inline NV_STATUS migconfigsessionIsDuplicate_DISPATCH(struct MIGConfigSession *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__migconfigsessionIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void migconfigsessionControlSerialization_Epilogue_DISPATCH(struct MIGConfigSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__migconfigsessionControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline void migconfigsessionControl_Epilogue_DISPATCH(struct MIGConfigSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__migconfigsessionControl_Epilogue__(pResource, pCallContext, pParams); } diff --git a/src/nvidia/generated/g_mig_monitor_session_nvoc.c b/src/nvidia/generated/g_mig_monitor_session_nvoc.c index d27790536..7d3cbdfa4 100644 --- a/src/nvidia/generated/g_mig_monitor_session_nvoc.c +++ b/src/nvidia/generated/g_mig_monitor_session_nvoc.c @@ -116,8 +116,12 @@ static void __nvoc_thunk_RsResource_migmonitorsessionAddAdditionalDependants(str resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_migmonitorsessionUnmap(struct MIGMonitorSession *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RsResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_migmonitorsessionUnmapFrom(struct MIGMonitorSession *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_migmonitorsessionControlSerialization_Prologue(struct MIGMonitorSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_RmResource_migmonitorsessionControl_Prologue(struct MIGMonitorSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -128,22 +132,26 @@ static NvBool __nvoc_thunk_RsResource_migmonitorsessionCanCopy(struct MIGMonitor return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_migmonitorsessionMapTo(struct MIGMonitorSession *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_migmonitorsessionUnmap(struct MIGMonitorSession *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RsResource.offset), pCallContext, pCpuMapping); } static void __nvoc_thunk_RsResource_migmonitorsessionPreDestruct(struct MIGMonitorSession *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_migmonitorsessionUnmapFrom(struct MIGMonitorSession *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_migmonitorsessionMapTo(struct MIGMonitorSession *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_RsResource_migmonitorsessionIsDuplicate(struct MIGMonitorSession *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_migmonitorsessionControlSerialization_Epilogue(struct MIGMonitorSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RmResource.offset), pCallContext, pParams); +} + static void __nvoc_thunk_RmResource_migmonitorsessionControl_Epilogue(struct MIGMonitorSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RmResource.offset), pCallContext, pParams); } @@ -215,20 +223,24 @@ static void __nvoc_init_funcTable_MIGMonitorSession_1(MIGMonitorSession *pThis) pThis->__migmonitorsessionAddAdditionalDependants__ = &__nvoc_thunk_RsResource_migmonitorsessionAddAdditionalDependants; - pThis->__migmonitorsessionUnmap__ = &__nvoc_thunk_RsResource_migmonitorsessionUnmap; + pThis->__migmonitorsessionUnmapFrom__ = &__nvoc_thunk_RsResource_migmonitorsessionUnmapFrom; + + pThis->__migmonitorsessionControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_migmonitorsessionControlSerialization_Prologue; pThis->__migmonitorsessionControl_Prologue__ = &__nvoc_thunk_RmResource_migmonitorsessionControl_Prologue; pThis->__migmonitorsessionCanCopy__ = &__nvoc_thunk_RsResource_migmonitorsessionCanCopy; - pThis->__migmonitorsessionMapTo__ = &__nvoc_thunk_RsResource_migmonitorsessionMapTo; + pThis->__migmonitorsessionUnmap__ = &__nvoc_thunk_RsResource_migmonitorsessionUnmap; pThis->__migmonitorsessionPreDestruct__ = &__nvoc_thunk_RsResource_migmonitorsessionPreDestruct; - pThis->__migmonitorsessionUnmapFrom__ = &__nvoc_thunk_RsResource_migmonitorsessionUnmapFrom; + pThis->__migmonitorsessionMapTo__ = &__nvoc_thunk_RsResource_migmonitorsessionMapTo; pThis->__migmonitorsessionIsDuplicate__ = &__nvoc_thunk_RsResource_migmonitorsessionIsDuplicate; + pThis->__migmonitorsessionControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_migmonitorsessionControlSerialization_Epilogue; + pThis->__migmonitorsessionControl_Epilogue__ = &__nvoc_thunk_RmResource_migmonitorsessionControl_Epilogue; pThis->__migmonitorsessionControlLookup__ = &__nvoc_thunk_RsResource_migmonitorsessionControlLookup; @@ -258,13 +270,16 @@ NV_STATUS __nvoc_objCreate_MIGMonitorSession(MIGMonitorSession **ppThis, Dynamic Object *pParentObj; MIGMonitorSession *pThis; - pThis = portMemAllocNonPaged(sizeof(MIGMonitorSession)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MIGMonitorSession), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(MIGMonitorSession)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MIGMonitorSession); + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -280,11 +295,17 @@ NV_STATUS __nvoc_objCreate_MIGMonitorSession(MIGMonitorSession **ppThis, Dynamic if (status != NV_OK) goto __nvoc_objCreate_MIGMonitorSession_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_MIGMonitorSession_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(MIGMonitorSession)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_mig_monitor_session_nvoc.h b/src/nvidia/generated/g_mig_monitor_session_nvoc.h index 1cf41dc39..5de2a94c9 100644 --- a/src/nvidia/generated/g_mig_monitor_session_nvoc.h +++ b/src/nvidia/generated/g_mig_monitor_session_nvoc.h @@ -74,13 +74,15 @@ struct MIGMonitorSession { NvU32 (*__migmonitorsessionGetRefCount__)(struct MIGMonitorSession *); NV_STATUS (*__migmonitorsessionControlFilter__)(struct MIGMonitorSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__migmonitorsessionAddAdditionalDependants__)(struct RsClient *, struct MIGMonitorSession *, RsResourceRef *); - NV_STATUS (*__migmonitorsessionUnmap__)(struct MIGMonitorSession *, struct CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__migmonitorsessionUnmapFrom__)(struct MIGMonitorSession *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__migmonitorsessionControlSerialization_Prologue__)(struct MIGMonitorSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__migmonitorsessionControl_Prologue__)(struct MIGMonitorSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__migmonitorsessionCanCopy__)(struct MIGMonitorSession *); - NV_STATUS (*__migmonitorsessionMapTo__)(struct MIGMonitorSession *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__migmonitorsessionUnmap__)(struct MIGMonitorSession *, struct CALL_CONTEXT *, RsCpuMapping *); void (*__migmonitorsessionPreDestruct__)(struct MIGMonitorSession *); - NV_STATUS (*__migmonitorsessionUnmapFrom__)(struct MIGMonitorSession *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__migmonitorsessionMapTo__)(struct MIGMonitorSession *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__migmonitorsessionIsDuplicate__)(struct MIGMonitorSession *, NvHandle, NvBool *); + void (*__migmonitorsessionControlSerialization_Epilogue__)(struct MIGMonitorSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__migmonitorsessionControl_Epilogue__)(struct MIGMonitorSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__migmonitorsessionControlLookup__)(struct MIGMonitorSession *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__migmonitorsessionMap__)(struct MIGMonitorSession *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -124,13 +126,15 @@ NV_STATUS __nvoc_objCreate_MIGMonitorSession(MIGMonitorSession**, Dynamic*, NvU3 #define migmonitorsessionGetRefCount(pResource) migmonitorsessionGetRefCount_DISPATCH(pResource) #define migmonitorsessionControlFilter(pResource, pCallContext, pParams) migmonitorsessionControlFilter_DISPATCH(pResource, pCallContext, pParams) #define migmonitorsessionAddAdditionalDependants(pClient, pResource, pReference) migmonitorsessionAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define migmonitorsessionUnmap(pResource, pCallContext, pCpuMapping) migmonitorsessionUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define migmonitorsessionUnmapFrom(pResource, pParams) migmonitorsessionUnmapFrom_DISPATCH(pResource, pParams) +#define migmonitorsessionControlSerialization_Prologue(pResource, pCallContext, pParams) migmonitorsessionControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define migmonitorsessionControl_Prologue(pResource, pCallContext, pParams) migmonitorsessionControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define migmonitorsessionCanCopy(pResource) migmonitorsessionCanCopy_DISPATCH(pResource) -#define migmonitorsessionMapTo(pResource, pParams) migmonitorsessionMapTo_DISPATCH(pResource, pParams) +#define migmonitorsessionUnmap(pResource, pCallContext, pCpuMapping) migmonitorsessionUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define migmonitorsessionPreDestruct(pResource) migmonitorsessionPreDestruct_DISPATCH(pResource) -#define migmonitorsessionUnmapFrom(pResource, pParams) migmonitorsessionUnmapFrom_DISPATCH(pResource, pParams) +#define migmonitorsessionMapTo(pResource, pParams) migmonitorsessionMapTo_DISPATCH(pResource, pParams) #define migmonitorsessionIsDuplicate(pResource, hMemory, pDuplicate) migmonitorsessionIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define migmonitorsessionControlSerialization_Epilogue(pResource, pCallContext, pParams) migmonitorsessionControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define migmonitorsessionControl_Epilogue(pResource, pCallContext, pParams) migmonitorsessionControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define migmonitorsessionControlLookup(pResource, pParams, ppEntry) migmonitorsessionControlLookup_DISPATCH(pResource, pParams, ppEntry) #define migmonitorsessionMap(pResource, pCallContext, pParams, pCpuMapping) migmonitorsessionMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -167,8 +171,12 @@ static inline void migmonitorsessionAddAdditionalDependants_DISPATCH(struct RsCl pResource->__migmonitorsessionAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS migmonitorsessionUnmap_DISPATCH(struct MIGMonitorSession *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pResource->__migmonitorsessionUnmap__(pResource, pCallContext, pCpuMapping); +static inline NV_STATUS migmonitorsessionUnmapFrom_DISPATCH(struct MIGMonitorSession *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__migmonitorsessionUnmapFrom__(pResource, pParams); +} + +static inline NV_STATUS migmonitorsessionControlSerialization_Prologue_DISPATCH(struct MIGMonitorSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__migmonitorsessionControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS migmonitorsessionControl_Prologue_DISPATCH(struct MIGMonitorSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -179,22 +187,26 @@ static inline NvBool migmonitorsessionCanCopy_DISPATCH(struct MIGMonitorSession return pResource->__migmonitorsessionCanCopy__(pResource); } -static inline NV_STATUS migmonitorsessionMapTo_DISPATCH(struct MIGMonitorSession *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__migmonitorsessionMapTo__(pResource, pParams); +static inline NV_STATUS migmonitorsessionUnmap_DISPATCH(struct MIGMonitorSession *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__migmonitorsessionUnmap__(pResource, pCallContext, pCpuMapping); } static inline void migmonitorsessionPreDestruct_DISPATCH(struct MIGMonitorSession *pResource) { pResource->__migmonitorsessionPreDestruct__(pResource); } -static inline NV_STATUS migmonitorsessionUnmapFrom_DISPATCH(struct MIGMonitorSession *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__migmonitorsessionUnmapFrom__(pResource, pParams); +static inline NV_STATUS migmonitorsessionMapTo_DISPATCH(struct MIGMonitorSession *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__migmonitorsessionMapTo__(pResource, pParams); } static inline NV_STATUS migmonitorsessionIsDuplicate_DISPATCH(struct MIGMonitorSession *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__migmonitorsessionIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void migmonitorsessionControlSerialization_Epilogue_DISPATCH(struct MIGMonitorSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__migmonitorsessionControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline void migmonitorsessionControl_Epilogue_DISPATCH(struct MIGMonitorSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__migmonitorsessionControl_Epilogue__(pResource, pCallContext, pParams); } diff --git a/src/nvidia/generated/g_mmu_fault_buffer_nvoc.c b/src/nvidia/generated/g_mmu_fault_buffer_nvoc.c index ac08fd7de..cc77cfe6e 100644 --- a/src/nvidia/generated/g_mmu_fault_buffer_nvoc.c +++ b/src/nvidia/generated/g_mmu_fault_buffer_nvoc.c @@ -127,16 +127,16 @@ static NvBool __nvoc_thunk_GpuResource_faultbufShareCallback(struct MmuFaultBuff return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MmuFaultBuffer_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_RsResource_faultbufMapTo(struct MmuFaultBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MmuFaultBuffer_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_faultbufCheckMemInterUnmap(struct MmuFaultBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_MmuFaultBuffer_RmResource.offset), bSubdeviceHandleProvided); } static NV_STATUS __nvoc_thunk_Notifier_faultbufGetOrAllocNotifShare(struct MmuFaultBuffer *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_MmuFaultBuffer_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); } -static NV_STATUS __nvoc_thunk_RmResource_faultbufCheckMemInterUnmap(struct MmuFaultBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_MmuFaultBuffer_RmResource.offset), bSubdeviceHandleProvided); +static NV_STATUS __nvoc_thunk_RsResource_faultbufMapTo(struct MmuFaultBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MmuFaultBuffer_RsResource.offset), pParams); } static void __nvoc_thunk_Notifier_faultbufSetNotificationShare(struct MmuFaultBuffer *pNotifier, struct NotifShare *pNotifShare) { @@ -199,6 +199,10 @@ static NV_STATUS __nvoc_thunk_Notifier_faultbufUnregisterEvent(struct MmuFaultBu return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_MmuFaultBuffer_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_faultbufControlSerialization_Prologue(struct MmuFaultBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MmuFaultBuffer_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_faultbufCanCopy(struct MmuFaultBuffer *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MmuFaultBuffer_RsResource.offset)); } @@ -211,6 +215,10 @@ static NV_STATUS __nvoc_thunk_RsResource_faultbufIsDuplicate(struct MmuFaultBuff return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MmuFaultBuffer_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_faultbufControlSerialization_Epilogue(struct MmuFaultBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MmuFaultBuffer_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_faultbufGetNotificationListPtr(struct MmuFaultBuffer *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_MmuFaultBuffer_Notifier.offset)); } @@ -287,6 +295,36 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_MmuFault /*pClassInfo=*/ &(__nvoc_class_def_MmuFaultBuffer.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "faultbufCtrlCmdMmuFaultBufferUnregisterNonReplayBuf" +#endif + }, + { /* [4] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) faultbufCtrlCmdMmuFaultBufferRegisterReplayBuf_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + /*flags=*/ 0x0u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xc3690103u, + /*paramSize=*/ sizeof(NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_MmuFaultBuffer.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "faultbufCtrlCmdMmuFaultBufferRegisterReplayBuf" +#endif + }, + { /* [5] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) faultbufCtrlCmdMmuFaultBufferUnregisterReplayBuf_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + /*flags=*/ 0x0u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xc3690104u, + /*paramSize=*/ sizeof(NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_MmuFaultBuffer.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "faultbufCtrlCmdMmuFaultBufferUnregisterReplayBuf" #endif }, @@ -294,7 +332,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_MmuFault const struct NVOC_EXPORT_INFO __nvoc_export_info_MmuFaultBuffer = { - /*numEntries=*/ 4, + /*numEntries=*/ 6, /*pExportEntries=*/ __nvoc_exported_method_def_MmuFaultBuffer }; @@ -360,6 +398,14 @@ static void __nvoc_init_funcTable_MmuFaultBuffer_1(MmuFaultBuffer *pThis) { pThis->__faultbufCtrlCmdMmuFaultBufferUnregisterNonReplayBuf__ = &faultbufCtrlCmdMmuFaultBufferUnregisterNonReplayBuf_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + pThis->__faultbufCtrlCmdMmuFaultBufferRegisterReplayBuf__ = &faultbufCtrlCmdMmuFaultBufferRegisterReplayBuf_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + pThis->__faultbufCtrlCmdMmuFaultBufferUnregisterReplayBuf__ = &faultbufCtrlCmdMmuFaultBufferUnregisterReplayBuf_IMPL; +#endif + pThis->__nvoc_base_GpuResource.__gpuresMap__ = &__nvoc_thunk_MmuFaultBuffer_gpuresMap; pThis->__nvoc_base_GpuResource.__gpuresUnmap__ = &__nvoc_thunk_MmuFaultBuffer_gpuresUnmap; @@ -368,11 +414,11 @@ static void __nvoc_init_funcTable_MmuFaultBuffer_1(MmuFaultBuffer *pThis) { pThis->__faultbufShareCallback__ = &__nvoc_thunk_GpuResource_faultbufShareCallback; - pThis->__faultbufMapTo__ = &__nvoc_thunk_RsResource_faultbufMapTo; + pThis->__faultbufCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_faultbufCheckMemInterUnmap; pThis->__faultbufGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_faultbufGetOrAllocNotifShare; - pThis->__faultbufCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_faultbufCheckMemInterUnmap; + pThis->__faultbufMapTo__ = &__nvoc_thunk_RsResource_faultbufMapTo; pThis->__faultbufSetNotificationShare__ = &__nvoc_thunk_Notifier_faultbufSetNotificationShare; @@ -404,12 +450,16 @@ static void __nvoc_init_funcTable_MmuFaultBuffer_1(MmuFaultBuffer *pThis) { pThis->__faultbufUnregisterEvent__ = &__nvoc_thunk_Notifier_faultbufUnregisterEvent; + pThis->__faultbufControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_faultbufControlSerialization_Prologue; + pThis->__faultbufCanCopy__ = &__nvoc_thunk_RsResource_faultbufCanCopy; pThis->__faultbufPreDestruct__ = &__nvoc_thunk_RsResource_faultbufPreDestruct; pThis->__faultbufIsDuplicate__ = &__nvoc_thunk_RsResource_faultbufIsDuplicate; + pThis->__faultbufControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_faultbufControlSerialization_Epilogue; + pThis->__faultbufGetNotificationListPtr__ = &__nvoc_thunk_Notifier_faultbufGetNotificationListPtr; pThis->__faultbufGetNotificationShare__ = &__nvoc_thunk_Notifier_faultbufGetNotificationShare; @@ -442,13 +492,16 @@ NV_STATUS __nvoc_objCreate_MmuFaultBuffer(MmuFaultBuffer **ppThis, Dynamic *pPar Object *pParentObj; MmuFaultBuffer *pThis; - pThis = portMemAllocNonPaged(sizeof(MmuFaultBuffer)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MmuFaultBuffer), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(MmuFaultBuffer)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MmuFaultBuffer); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -464,11 +517,17 @@ NV_STATUS __nvoc_objCreate_MmuFaultBuffer(MmuFaultBuffer **ppThis, Dynamic *pPar if (status != NV_OK) goto __nvoc_objCreate_MmuFaultBuffer_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_MmuFaultBuffer_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(MmuFaultBuffer)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_mmu_fault_buffer_nvoc.h b/src/nvidia/generated/g_mmu_fault_buffer_nvoc.h index 7befe639f..0bef7787f 100644 --- a/src/nvidia/generated/g_mmu_fault_buffer_nvoc.h +++ b/src/nvidia/generated/g_mmu_fault_buffer_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2010-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -67,10 +67,12 @@ struct MmuFaultBuffer { NV_STATUS (*__faultbufCtrlCmdFaultbufferGetRegisterMappings__)(struct MmuFaultBuffer *, NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS *); NV_STATUS (*__faultbufCtrlCmdMmuFaultBufferRegisterNonReplayBuf__)(struct MmuFaultBuffer *, NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_NON_REPLAY_BUF_PARAMS *); NV_STATUS (*__faultbufCtrlCmdMmuFaultBufferUnregisterNonReplayBuf__)(struct MmuFaultBuffer *, NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_NON_REPLAY_BUF_PARAMS *); + NV_STATUS (*__faultbufCtrlCmdMmuFaultBufferRegisterReplayBuf__)(struct MmuFaultBuffer *, NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF_PARAMS *); + NV_STATUS (*__faultbufCtrlCmdMmuFaultBufferUnregisterReplayBuf__)(struct MmuFaultBuffer *, NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF_PARAMS *); NvBool (*__faultbufShareCallback__)(struct MmuFaultBuffer *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__faultbufMapTo__)(struct MmuFaultBuffer *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__faultbufGetOrAllocNotifShare__)(struct MmuFaultBuffer *, NvHandle, NvHandle, struct NotifShare **); NV_STATUS (*__faultbufCheckMemInterUnmap__)(struct MmuFaultBuffer *, NvBool); + NV_STATUS (*__faultbufGetOrAllocNotifShare__)(struct MmuFaultBuffer *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__faultbufMapTo__)(struct MmuFaultBuffer *, RS_RES_MAP_TO_PARAMS *); void (*__faultbufSetNotificationShare__)(struct MmuFaultBuffer *, struct NotifShare *); NvU32 (*__faultbufGetRefCount__)(struct MmuFaultBuffer *); void (*__faultbufAddAdditionalDependants__)(struct RsClient *, struct MmuFaultBuffer *, RsResourceRef *); @@ -86,9 +88,11 @@ struct MmuFaultBuffer { NV_STATUS (*__faultbufGetMemoryMappingDescriptor__)(struct MmuFaultBuffer *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__faultbufControlFilter__)(struct MmuFaultBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__faultbufUnregisterEvent__)(struct MmuFaultBuffer *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__faultbufControlSerialization_Prologue__)(struct MmuFaultBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__faultbufCanCopy__)(struct MmuFaultBuffer *); void (*__faultbufPreDestruct__)(struct MmuFaultBuffer *); NV_STATUS (*__faultbufIsDuplicate__)(struct MmuFaultBuffer *, NvHandle, NvBool *); + void (*__faultbufControlSerialization_Epilogue__)(struct MmuFaultBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__faultbufGetNotificationListPtr__)(struct MmuFaultBuffer *); struct NotifShare *(*__faultbufGetNotificationShare__)(struct MmuFaultBuffer *); NvBool (*__faultbufAccessCallback__)(struct MmuFaultBuffer *, struct RsClient *, void *, RsAccessRight); @@ -129,10 +133,12 @@ NV_STATUS __nvoc_objCreate_MmuFaultBuffer(MmuFaultBuffer**, Dynamic*, NvU32, str #define faultbufCtrlCmdFaultbufferGetRegisterMappings(pMmuFaultBuffer, pParams) faultbufCtrlCmdFaultbufferGetRegisterMappings_DISPATCH(pMmuFaultBuffer, pParams) #define faultbufCtrlCmdMmuFaultBufferRegisterNonReplayBuf(pMmuFaultBuffer, pParams) faultbufCtrlCmdMmuFaultBufferRegisterNonReplayBuf_DISPATCH(pMmuFaultBuffer, pParams) #define faultbufCtrlCmdMmuFaultBufferUnregisterNonReplayBuf(pMmuFaultBuffer, pParams) faultbufCtrlCmdMmuFaultBufferUnregisterNonReplayBuf_DISPATCH(pMmuFaultBuffer, pParams) +#define faultbufCtrlCmdMmuFaultBufferRegisterReplayBuf(pMmuFaultBuffer, pParams) faultbufCtrlCmdMmuFaultBufferRegisterReplayBuf_DISPATCH(pMmuFaultBuffer, pParams) +#define faultbufCtrlCmdMmuFaultBufferUnregisterReplayBuf(pMmuFaultBuffer, pParams) faultbufCtrlCmdMmuFaultBufferUnregisterReplayBuf_DISPATCH(pMmuFaultBuffer, pParams) #define faultbufShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) faultbufShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define faultbufMapTo(pResource, pParams) faultbufMapTo_DISPATCH(pResource, pParams) -#define faultbufGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) faultbufGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) #define faultbufCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) faultbufCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define faultbufGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) faultbufGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define faultbufMapTo(pResource, pParams) faultbufMapTo_DISPATCH(pResource, pParams) #define faultbufSetNotificationShare(pNotifier, pNotifShare) faultbufSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define faultbufGetRefCount(pResource) faultbufGetRefCount_DISPATCH(pResource) #define faultbufAddAdditionalDependants(pClient, pResource, pReference) faultbufAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) @@ -148,9 +154,11 @@ NV_STATUS __nvoc_objCreate_MmuFaultBuffer(MmuFaultBuffer**, Dynamic*, NvU32, str #define faultbufGetMemoryMappingDescriptor(pRmResource, ppMemDesc) faultbufGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define faultbufControlFilter(pResource, pCallContext, pParams) faultbufControlFilter_DISPATCH(pResource, pCallContext, pParams) #define faultbufUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) faultbufUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define faultbufControlSerialization_Prologue(pResource, pCallContext, pParams) faultbufControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define faultbufCanCopy(pResource) faultbufCanCopy_DISPATCH(pResource) #define faultbufPreDestruct(pResource) faultbufPreDestruct_DISPATCH(pResource) #define faultbufIsDuplicate(pResource, hMemory, pDuplicate) faultbufIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define faultbufControlSerialization_Epilogue(pResource, pCallContext, pParams) faultbufControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define faultbufGetNotificationListPtr(pNotifier) faultbufGetNotificationListPtr_DISPATCH(pNotifier) #define faultbufGetNotificationShare(pNotifier) faultbufGetNotificationShare_DISPATCH(pNotifier) #define faultbufAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) faultbufAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) @@ -196,20 +204,32 @@ static inline NV_STATUS faultbufCtrlCmdMmuFaultBufferUnregisterNonReplayBuf_DISP return pMmuFaultBuffer->__faultbufCtrlCmdMmuFaultBufferUnregisterNonReplayBuf__(pMmuFaultBuffer, pParams); } +NV_STATUS faultbufCtrlCmdMmuFaultBufferRegisterReplayBuf_IMPL(struct MmuFaultBuffer *pMmuFaultBuffer, NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF_PARAMS *pParams); + +static inline NV_STATUS faultbufCtrlCmdMmuFaultBufferRegisterReplayBuf_DISPATCH(struct MmuFaultBuffer *pMmuFaultBuffer, NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF_PARAMS *pParams) { + return pMmuFaultBuffer->__faultbufCtrlCmdMmuFaultBufferRegisterReplayBuf__(pMmuFaultBuffer, pParams); +} + +NV_STATUS faultbufCtrlCmdMmuFaultBufferUnregisterReplayBuf_IMPL(struct MmuFaultBuffer *pMmuFaultBuffer, NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF_PARAMS *pParams); + +static inline NV_STATUS faultbufCtrlCmdMmuFaultBufferUnregisterReplayBuf_DISPATCH(struct MmuFaultBuffer *pMmuFaultBuffer, NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF_PARAMS *pParams) { + return pMmuFaultBuffer->__faultbufCtrlCmdMmuFaultBufferUnregisterReplayBuf__(pMmuFaultBuffer, pParams); +} + static inline NvBool faultbufShareCallback_DISPATCH(struct MmuFaultBuffer *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__faultbufShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS faultbufMapTo_DISPATCH(struct MmuFaultBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__faultbufMapTo__(pResource, pParams); +static inline NV_STATUS faultbufCheckMemInterUnmap_DISPATCH(struct MmuFaultBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__faultbufCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } static inline NV_STATUS faultbufGetOrAllocNotifShare_DISPATCH(struct MmuFaultBuffer *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return pNotifier->__faultbufGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); } -static inline NV_STATUS faultbufCheckMemInterUnmap_DISPATCH(struct MmuFaultBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__faultbufCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline NV_STATUS faultbufMapTo_DISPATCH(struct MmuFaultBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__faultbufMapTo__(pResource, pParams); } static inline void faultbufSetNotificationShare_DISPATCH(struct MmuFaultBuffer *pNotifier, struct NotifShare *pNotifShare) { @@ -272,6 +292,10 @@ static inline NV_STATUS faultbufUnregisterEvent_DISPATCH(struct MmuFaultBuffer * return pNotifier->__faultbufUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS faultbufControlSerialization_Prologue_DISPATCH(struct MmuFaultBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__faultbufControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool faultbufCanCopy_DISPATCH(struct MmuFaultBuffer *pResource) { return pResource->__faultbufCanCopy__(pResource); } @@ -284,6 +308,10 @@ static inline NV_STATUS faultbufIsDuplicate_DISPATCH(struct MmuFaultBuffer *pRes return pResource->__faultbufIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void faultbufControlSerialization_Epilogue_DISPATCH(struct MmuFaultBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__faultbufControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *faultbufGetNotificationListPtr_DISPATCH(struct MmuFaultBuffer *pNotifier) { return pNotifier->__faultbufGetNotificationListPtr__(pNotifier); } diff --git a/src/nvidia/generated/g_mps_api_nvoc.c b/src/nvidia/generated/g_mps_api_nvoc.c index 225f873b8..4ee6ee656 100644 --- a/src/nvidia/generated/g_mps_api_nvoc.c +++ b/src/nvidia/generated/g_mps_api_nvoc.c @@ -116,8 +116,12 @@ static void __nvoc_thunk_RsResource_mpsApiAddAdditionalDependants(struct RsClien resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_mpsApiUnmap(struct MpsApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RsResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_mpsApiUnmapFrom(struct MpsApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_mpsApiControlSerialization_Prologue(struct MpsApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_RmResource_mpsApiControl_Prologue(struct MpsApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -128,22 +132,26 @@ static NvBool __nvoc_thunk_RsResource_mpsApiCanCopy(struct MpsApi *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_mpsApiMapTo(struct MpsApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_mpsApiUnmap(struct MpsApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RsResource.offset), pCallContext, pCpuMapping); } static void __nvoc_thunk_RsResource_mpsApiPreDestruct(struct MpsApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_mpsApiUnmapFrom(struct MpsApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_mpsApiMapTo(struct MpsApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_RsResource_mpsApiIsDuplicate(struct MpsApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_mpsApiControlSerialization_Epilogue(struct MpsApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RmResource.offset), pCallContext, pParams); +} + static void __nvoc_thunk_RmResource_mpsApiControl_Epilogue(struct MpsApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RmResource.offset), pCallContext, pParams); } @@ -215,20 +223,24 @@ static void __nvoc_init_funcTable_MpsApi_1(MpsApi *pThis) { pThis->__mpsApiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_mpsApiAddAdditionalDependants; - pThis->__mpsApiUnmap__ = &__nvoc_thunk_RsResource_mpsApiUnmap; + pThis->__mpsApiUnmapFrom__ = &__nvoc_thunk_RsResource_mpsApiUnmapFrom; + + pThis->__mpsApiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_mpsApiControlSerialization_Prologue; pThis->__mpsApiControl_Prologue__ = &__nvoc_thunk_RmResource_mpsApiControl_Prologue; pThis->__mpsApiCanCopy__ = &__nvoc_thunk_RsResource_mpsApiCanCopy; - pThis->__mpsApiMapTo__ = &__nvoc_thunk_RsResource_mpsApiMapTo; + pThis->__mpsApiUnmap__ = &__nvoc_thunk_RsResource_mpsApiUnmap; pThis->__mpsApiPreDestruct__ = &__nvoc_thunk_RsResource_mpsApiPreDestruct; - pThis->__mpsApiUnmapFrom__ = &__nvoc_thunk_RsResource_mpsApiUnmapFrom; + pThis->__mpsApiMapTo__ = &__nvoc_thunk_RsResource_mpsApiMapTo; pThis->__mpsApiIsDuplicate__ = &__nvoc_thunk_RsResource_mpsApiIsDuplicate; + pThis->__mpsApiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_mpsApiControlSerialization_Epilogue; + pThis->__mpsApiControl_Epilogue__ = &__nvoc_thunk_RmResource_mpsApiControl_Epilogue; pThis->__mpsApiControlLookup__ = &__nvoc_thunk_RsResource_mpsApiControlLookup; @@ -258,13 +270,16 @@ NV_STATUS __nvoc_objCreate_MpsApi(MpsApi **ppThis, Dynamic *pParent, NvU32 creat Object *pParentObj; MpsApi *pThis; - pThis = portMemAllocNonPaged(sizeof(MpsApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MpsApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(MpsApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MpsApi); + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -280,11 +295,17 @@ NV_STATUS __nvoc_objCreate_MpsApi(MpsApi **ppThis, Dynamic *pParent, NvU32 creat if (status != NV_OK) goto __nvoc_objCreate_MpsApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_MpsApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(MpsApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_mps_api_nvoc.h b/src/nvidia/generated/g_mps_api_nvoc.h index 863d26394..2701466b9 100644 --- a/src/nvidia/generated/g_mps_api_nvoc.h +++ b/src/nvidia/generated/g_mps_api_nvoc.h @@ -78,13 +78,15 @@ struct MpsApi { NvU32 (*__mpsApiGetRefCount__)(struct MpsApi *); NV_STATUS (*__mpsApiControlFilter__)(struct MpsApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__mpsApiAddAdditionalDependants__)(struct RsClient *, struct MpsApi *, RsResourceRef *); - NV_STATUS (*__mpsApiUnmap__)(struct MpsApi *, struct CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__mpsApiUnmapFrom__)(struct MpsApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__mpsApiControlSerialization_Prologue__)(struct MpsApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__mpsApiControl_Prologue__)(struct MpsApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__mpsApiCanCopy__)(struct MpsApi *); - NV_STATUS (*__mpsApiMapTo__)(struct MpsApi *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__mpsApiUnmap__)(struct MpsApi *, struct CALL_CONTEXT *, RsCpuMapping *); void (*__mpsApiPreDestruct__)(struct MpsApi *); - NV_STATUS (*__mpsApiUnmapFrom__)(struct MpsApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__mpsApiMapTo__)(struct MpsApi *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__mpsApiIsDuplicate__)(struct MpsApi *, NvHandle, NvBool *); + void (*__mpsApiControlSerialization_Epilogue__)(struct MpsApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__mpsApiControl_Epilogue__)(struct MpsApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__mpsApiControlLookup__)(struct MpsApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__mpsApiMap__)(struct MpsApi *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -127,13 +129,15 @@ NV_STATUS __nvoc_objCreate_MpsApi(MpsApi**, Dynamic*, NvU32, CALL_CONTEXT * arg_ #define mpsApiGetRefCount(pResource) mpsApiGetRefCount_DISPATCH(pResource) #define mpsApiControlFilter(pResource, pCallContext, pParams) mpsApiControlFilter_DISPATCH(pResource, pCallContext, pParams) #define mpsApiAddAdditionalDependants(pClient, pResource, pReference) mpsApiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define mpsApiUnmap(pResource, pCallContext, pCpuMapping) mpsApiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define mpsApiUnmapFrom(pResource, pParams) mpsApiUnmapFrom_DISPATCH(pResource, pParams) +#define mpsApiControlSerialization_Prologue(pResource, pCallContext, pParams) mpsApiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define mpsApiControl_Prologue(pResource, pCallContext, pParams) mpsApiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define mpsApiCanCopy(pResource) mpsApiCanCopy_DISPATCH(pResource) -#define mpsApiMapTo(pResource, pParams) mpsApiMapTo_DISPATCH(pResource, pParams) +#define mpsApiUnmap(pResource, pCallContext, pCpuMapping) mpsApiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define mpsApiPreDestruct(pResource) mpsApiPreDestruct_DISPATCH(pResource) -#define mpsApiUnmapFrom(pResource, pParams) mpsApiUnmapFrom_DISPATCH(pResource, pParams) +#define mpsApiMapTo(pResource, pParams) mpsApiMapTo_DISPATCH(pResource, pParams) #define mpsApiIsDuplicate(pResource, hMemory, pDuplicate) mpsApiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define mpsApiControlSerialization_Epilogue(pResource, pCallContext, pParams) mpsApiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define mpsApiControl_Epilogue(pResource, pCallContext, pParams) mpsApiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define mpsApiControlLookup(pResource, pParams, ppEntry) mpsApiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define mpsApiMap(pResource, pCallContext, pParams, pCpuMapping) mpsApiMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -170,8 +174,12 @@ static inline void mpsApiAddAdditionalDependants_DISPATCH(struct RsClient *pClie pResource->__mpsApiAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS mpsApiUnmap_DISPATCH(struct MpsApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pResource->__mpsApiUnmap__(pResource, pCallContext, pCpuMapping); +static inline NV_STATUS mpsApiUnmapFrom_DISPATCH(struct MpsApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__mpsApiUnmapFrom__(pResource, pParams); +} + +static inline NV_STATUS mpsApiControlSerialization_Prologue_DISPATCH(struct MpsApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__mpsApiControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS mpsApiControl_Prologue_DISPATCH(struct MpsApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -182,22 +190,26 @@ static inline NvBool mpsApiCanCopy_DISPATCH(struct MpsApi *pResource) { return pResource->__mpsApiCanCopy__(pResource); } -static inline NV_STATUS mpsApiMapTo_DISPATCH(struct MpsApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__mpsApiMapTo__(pResource, pParams); +static inline NV_STATUS mpsApiUnmap_DISPATCH(struct MpsApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__mpsApiUnmap__(pResource, pCallContext, pCpuMapping); } static inline void mpsApiPreDestruct_DISPATCH(struct MpsApi *pResource) { pResource->__mpsApiPreDestruct__(pResource); } -static inline NV_STATUS mpsApiUnmapFrom_DISPATCH(struct MpsApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__mpsApiUnmapFrom__(pResource, pParams); +static inline NV_STATUS mpsApiMapTo_DISPATCH(struct MpsApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__mpsApiMapTo__(pResource, pParams); } static inline NV_STATUS mpsApiIsDuplicate_DISPATCH(struct MpsApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__mpsApiIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void mpsApiControlSerialization_Epilogue_DISPATCH(struct MpsApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__mpsApiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline void mpsApiControl_Epilogue_DISPATCH(struct MpsApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__mpsApiControl_Epilogue__(pResource, pCallContext, pParams); } diff --git a/src/nvidia/generated/g_no_device_mem_nvoc.c b/src/nvidia/generated/g_no_device_mem_nvoc.c index d288bb366..1c9b1569b 100644 --- a/src/nvidia/generated/g_no_device_mem_nvoc.c +++ b/src/nvidia/generated/g_no_device_mem_nvoc.c @@ -101,6 +101,42 @@ static NV_STATUS __nvoc_thunk_Memory_nodevicememCheckMemInterUnmap(struct NoDevi return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset), bSubdeviceHandleProvided); } +static NvBool __nvoc_thunk_RmResource_nodevicememShareCallback(struct NoDeviceMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RsResource_nodevicememMapTo(struct NoDeviceMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset), pParams); +} + +static NvU32 __nvoc_thunk_RsResource_nodevicememGetRefCount(struct NoDeviceMemory *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_nodevicememAddAdditionalDependants(struct RsClient *pClient, struct NoDeviceMemory *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_nodevicememControl_Prologue(struct NoDeviceMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_Memory_nodevicememIsGpuMapAllowed(struct NoDeviceMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset), pGpu); +} + +static NV_STATUS __nvoc_thunk_RsResource_nodevicememUnmapFrom(struct NoDeviceMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_nodevicememControl_Epilogue(struct NoDeviceMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_nodevicememControlLookup(struct NoDeviceMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset), pParams, ppEntry); +} + static NV_STATUS __nvoc_thunk_Memory_nodevicememControl(struct NoDeviceMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset), pCallContext, pParams); } @@ -117,32 +153,12 @@ static NV_STATUS __nvoc_thunk_Memory_nodevicememGetMemoryMappingDescriptor(struc return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset), ppMemDesc); } -static NvBool __nvoc_thunk_RmResource_nodevicememShareCallback(struct NoDeviceMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); -} - static NV_STATUS __nvoc_thunk_RsResource_nodevicememControlFilter(struct NoDeviceMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_nodevicememAddAdditionalDependants(struct RsClient *pClient, struct NoDeviceMemory *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_nodevicememGetRefCount(struct NoDeviceMemory *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RsResource_nodevicememMapTo(struct NoDeviceMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_nodevicememControl_Prologue(struct NoDeviceMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RmResource.offset), pCallContext, pParams); -} - -static NvBool __nvoc_thunk_Memory_nodevicememIsGpuMapAllowed(struct NoDeviceMemory *pMemory, struct OBJGPU *pGpu) { - return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset), pGpu); +static NV_STATUS __nvoc_thunk_RmResource_nodevicememControlSerialization_Prologue(struct NoDeviceMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_nodevicememCanCopy(struct NoDeviceMemory *pResource) { @@ -165,16 +181,8 @@ static NV_STATUS __nvoc_thunk_Memory_nodevicememIsDuplicate(struct NoDeviceMemor return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset), hMemory, pDuplicate); } -static NV_STATUS __nvoc_thunk_RsResource_nodevicememUnmapFrom(struct NoDeviceMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RmResource_nodevicememControl_Epilogue(struct NoDeviceMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_nodevicememControlLookup(struct NoDeviceMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_nodevicememControlSerialization_Epilogue(struct NoDeviceMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_nodevicememMap(struct NoDeviceMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -230,6 +238,24 @@ static void __nvoc_init_funcTable_NoDeviceMemory_1(NoDeviceMemory *pThis) { pThis->__nodevicememCheckMemInterUnmap__ = &__nvoc_thunk_Memory_nodevicememCheckMemInterUnmap; + pThis->__nodevicememShareCallback__ = &__nvoc_thunk_RmResource_nodevicememShareCallback; + + pThis->__nodevicememMapTo__ = &__nvoc_thunk_RsResource_nodevicememMapTo; + + pThis->__nodevicememGetRefCount__ = &__nvoc_thunk_RsResource_nodevicememGetRefCount; + + pThis->__nodevicememAddAdditionalDependants__ = &__nvoc_thunk_RsResource_nodevicememAddAdditionalDependants; + + pThis->__nodevicememControl_Prologue__ = &__nvoc_thunk_RmResource_nodevicememControl_Prologue; + + pThis->__nodevicememIsGpuMapAllowed__ = &__nvoc_thunk_Memory_nodevicememIsGpuMapAllowed; + + pThis->__nodevicememUnmapFrom__ = &__nvoc_thunk_RsResource_nodevicememUnmapFrom; + + pThis->__nodevicememControl_Epilogue__ = &__nvoc_thunk_RmResource_nodevicememControl_Epilogue; + + pThis->__nodevicememControlLookup__ = &__nvoc_thunk_RsResource_nodevicememControlLookup; + pThis->__nodevicememControl__ = &__nvoc_thunk_Memory_nodevicememControl; pThis->__nodevicememUnmap__ = &__nvoc_thunk_Memory_nodevicememUnmap; @@ -238,19 +264,9 @@ static void __nvoc_init_funcTable_NoDeviceMemory_1(NoDeviceMemory *pThis) { pThis->__nodevicememGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_nodevicememGetMemoryMappingDescriptor; - pThis->__nodevicememShareCallback__ = &__nvoc_thunk_RmResource_nodevicememShareCallback; - pThis->__nodevicememControlFilter__ = &__nvoc_thunk_RsResource_nodevicememControlFilter; - pThis->__nodevicememAddAdditionalDependants__ = &__nvoc_thunk_RsResource_nodevicememAddAdditionalDependants; - - pThis->__nodevicememGetRefCount__ = &__nvoc_thunk_RsResource_nodevicememGetRefCount; - - pThis->__nodevicememMapTo__ = &__nvoc_thunk_RsResource_nodevicememMapTo; - - pThis->__nodevicememControl_Prologue__ = &__nvoc_thunk_RmResource_nodevicememControl_Prologue; - - pThis->__nodevicememIsGpuMapAllowed__ = &__nvoc_thunk_Memory_nodevicememIsGpuMapAllowed; + pThis->__nodevicememControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_nodevicememControlSerialization_Prologue; pThis->__nodevicememCanCopy__ = &__nvoc_thunk_RsResource_nodevicememCanCopy; @@ -262,11 +278,7 @@ static void __nvoc_init_funcTable_NoDeviceMemory_1(NoDeviceMemory *pThis) { pThis->__nodevicememIsDuplicate__ = &__nvoc_thunk_Memory_nodevicememIsDuplicate; - pThis->__nodevicememUnmapFrom__ = &__nvoc_thunk_RsResource_nodevicememUnmapFrom; - - pThis->__nodevicememControl_Epilogue__ = &__nvoc_thunk_RmResource_nodevicememControl_Epilogue; - - pThis->__nodevicememControlLookup__ = &__nvoc_thunk_RsResource_nodevicememControlLookup; + pThis->__nodevicememControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_nodevicememControlSerialization_Epilogue; pThis->__nodevicememMap__ = &__nvoc_thunk_Memory_nodevicememMap; @@ -294,13 +306,16 @@ NV_STATUS __nvoc_objCreate_NoDeviceMemory(NoDeviceMemory **ppThis, Dynamic *pPar Object *pParentObj; NoDeviceMemory *pThis; - pThis = portMemAllocNonPaged(sizeof(NoDeviceMemory)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(NoDeviceMemory), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(NoDeviceMemory)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_NoDeviceMemory); + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -316,11 +331,17 @@ NV_STATUS __nvoc_objCreate_NoDeviceMemory(NoDeviceMemory **ppThis, Dynamic *pPar if (status != NV_OK) goto __nvoc_objCreate_NoDeviceMemory_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_NoDeviceMemory_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(NoDeviceMemory)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_no_device_mem_nvoc.h b/src/nvidia/generated/g_no_device_mem_nvoc.h index 3f9562b30..c6bea742c 100644 --- a/src/nvidia/generated/g_no_device_mem_nvoc.h +++ b/src/nvidia/generated/g_no_device_mem_nvoc.h @@ -57,25 +57,27 @@ struct NoDeviceMemory { struct NoDeviceMemory *__nvoc_pbase_NoDeviceMemory; NV_STATUS (*__nodevicememGetMapAddrSpace__)(struct NoDeviceMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); NV_STATUS (*__nodevicememCheckMemInterUnmap__)(struct NoDeviceMemory *, NvBool); + NvBool (*__nodevicememShareCallback__)(struct NoDeviceMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__nodevicememMapTo__)(struct NoDeviceMemory *, RS_RES_MAP_TO_PARAMS *); + NvU32 (*__nodevicememGetRefCount__)(struct NoDeviceMemory *); + void (*__nodevicememAddAdditionalDependants__)(struct RsClient *, struct NoDeviceMemory *, RsResourceRef *); + NV_STATUS (*__nodevicememControl_Prologue__)(struct NoDeviceMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__nodevicememIsGpuMapAllowed__)(struct NoDeviceMemory *, struct OBJGPU *); + NV_STATUS (*__nodevicememUnmapFrom__)(struct NoDeviceMemory *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__nodevicememControl_Epilogue__)(struct NoDeviceMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__nodevicememControlLookup__)(struct NoDeviceMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__nodevicememControl__)(struct NoDeviceMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__nodevicememUnmap__)(struct NoDeviceMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__nodevicememGetMemInterMapParams__)(struct NoDeviceMemory *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__nodevicememGetMemoryMappingDescriptor__)(struct NoDeviceMemory *, MEMORY_DESCRIPTOR **); - NvBool (*__nodevicememShareCallback__)(struct NoDeviceMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__nodevicememControlFilter__)(struct NoDeviceMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__nodevicememAddAdditionalDependants__)(struct RsClient *, struct NoDeviceMemory *, RsResourceRef *); - NvU32 (*__nodevicememGetRefCount__)(struct NoDeviceMemory *); - NV_STATUS (*__nodevicememMapTo__)(struct NoDeviceMemory *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__nodevicememControl_Prologue__)(struct NoDeviceMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvBool (*__nodevicememIsGpuMapAllowed__)(struct NoDeviceMemory *, struct OBJGPU *); + NV_STATUS (*__nodevicememControlSerialization_Prologue__)(struct NoDeviceMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__nodevicememCanCopy__)(struct NoDeviceMemory *); NV_STATUS (*__nodevicememIsReady__)(struct NoDeviceMemory *, NvBool); NV_STATUS (*__nodevicememCheckCopyPermissions__)(struct NoDeviceMemory *, struct OBJGPU *, NvHandle); void (*__nodevicememPreDestruct__)(struct NoDeviceMemory *); NV_STATUS (*__nodevicememIsDuplicate__)(struct NoDeviceMemory *, NvHandle, NvBool *); - NV_STATUS (*__nodevicememUnmapFrom__)(struct NoDeviceMemory *, RS_RES_UNMAP_FROM_PARAMS *); - void (*__nodevicememControl_Epilogue__)(struct NoDeviceMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__nodevicememControlLookup__)(struct NoDeviceMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__nodevicememControlSerialization_Epilogue__)(struct NoDeviceMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__nodevicememMap__)(struct NoDeviceMemory *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__nodevicememAccessCallback__)(struct NoDeviceMemory *, struct RsClient *, void *, RsAccessRight); }; @@ -110,25 +112,27 @@ NV_STATUS __nvoc_objCreate_NoDeviceMemory(NoDeviceMemory**, Dynamic*, NvU32, CAL #define nodevicememGetMapAddrSpace(pNoDeviceMemory, pCallContext, mapFlags, pAddrSpace) nodevicememGetMapAddrSpace_DISPATCH(pNoDeviceMemory, pCallContext, mapFlags, pAddrSpace) #define nodevicememCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) nodevicememCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define nodevicememShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) nodevicememShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define nodevicememMapTo(pResource, pParams) nodevicememMapTo_DISPATCH(pResource, pParams) +#define nodevicememGetRefCount(pResource) nodevicememGetRefCount_DISPATCH(pResource) +#define nodevicememAddAdditionalDependants(pClient, pResource, pReference) nodevicememAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define nodevicememControl_Prologue(pResource, pCallContext, pParams) nodevicememControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define nodevicememIsGpuMapAllowed(pMemory, pGpu) nodevicememIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define nodevicememUnmapFrom(pResource, pParams) nodevicememUnmapFrom_DISPATCH(pResource, pParams) +#define nodevicememControl_Epilogue(pResource, pCallContext, pParams) nodevicememControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define nodevicememControlLookup(pResource, pParams, ppEntry) nodevicememControlLookup_DISPATCH(pResource, pParams, ppEntry) #define nodevicememControl(pMemory, pCallContext, pParams) nodevicememControl_DISPATCH(pMemory, pCallContext, pParams) #define nodevicememUnmap(pMemory, pCallContext, pCpuMapping) nodevicememUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define nodevicememGetMemInterMapParams(pMemory, pParams) nodevicememGetMemInterMapParams_DISPATCH(pMemory, pParams) #define nodevicememGetMemoryMappingDescriptor(pMemory, ppMemDesc) nodevicememGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define nodevicememShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) nodevicememShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define nodevicememControlFilter(pResource, pCallContext, pParams) nodevicememControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define nodevicememAddAdditionalDependants(pClient, pResource, pReference) nodevicememAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define nodevicememGetRefCount(pResource) nodevicememGetRefCount_DISPATCH(pResource) -#define nodevicememMapTo(pResource, pParams) nodevicememMapTo_DISPATCH(pResource, pParams) -#define nodevicememControl_Prologue(pResource, pCallContext, pParams) nodevicememControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define nodevicememIsGpuMapAllowed(pMemory, pGpu) nodevicememIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define nodevicememControlSerialization_Prologue(pResource, pCallContext, pParams) nodevicememControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define nodevicememCanCopy(pResource) nodevicememCanCopy_DISPATCH(pResource) #define nodevicememIsReady(pMemory, bCopyConstructorContext) nodevicememIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define nodevicememCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) nodevicememCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) #define nodevicememPreDestruct(pResource) nodevicememPreDestruct_DISPATCH(pResource) #define nodevicememIsDuplicate(pMemory, hMemory, pDuplicate) nodevicememIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) -#define nodevicememUnmapFrom(pResource, pParams) nodevicememUnmapFrom_DISPATCH(pResource, pParams) -#define nodevicememControl_Epilogue(pResource, pCallContext, pParams) nodevicememControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define nodevicememControlLookup(pResource, pParams, ppEntry) nodevicememControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define nodevicememControlSerialization_Epilogue(pResource, pCallContext, pParams) nodevicememControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define nodevicememMap(pMemory, pCallContext, pParams, pCpuMapping) nodevicememMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define nodevicememAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) nodevicememAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS nodevicememGetMapAddrSpace_IMPL(struct NoDeviceMemory *pNoDeviceMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace); @@ -141,6 +145,42 @@ static inline NV_STATUS nodevicememCheckMemInterUnmap_DISPATCH(struct NoDeviceMe return pMemory->__nodevicememCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } +static inline NvBool nodevicememShareCallback_DISPATCH(struct NoDeviceMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__nodevicememShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS nodevicememMapTo_DISPATCH(struct NoDeviceMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__nodevicememMapTo__(pResource, pParams); +} + +static inline NvU32 nodevicememGetRefCount_DISPATCH(struct NoDeviceMemory *pResource) { + return pResource->__nodevicememGetRefCount__(pResource); +} + +static inline void nodevicememAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct NoDeviceMemory *pResource, RsResourceRef *pReference) { + pResource->__nodevicememAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS nodevicememControl_Prologue_DISPATCH(struct NoDeviceMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__nodevicememControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool nodevicememIsGpuMapAllowed_DISPATCH(struct NoDeviceMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__nodevicememIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline NV_STATUS nodevicememUnmapFrom_DISPATCH(struct NoDeviceMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__nodevicememUnmapFrom__(pResource, pParams); +} + +static inline void nodevicememControl_Epilogue_DISPATCH(struct NoDeviceMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__nodevicememControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS nodevicememControlLookup_DISPATCH(struct NoDeviceMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__nodevicememControlLookup__(pResource, pParams, ppEntry); +} + static inline NV_STATUS nodevicememControl_DISPATCH(struct NoDeviceMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pMemory->__nodevicememControl__(pMemory, pCallContext, pParams); } @@ -157,32 +197,12 @@ static inline NV_STATUS nodevicememGetMemoryMappingDescriptor_DISPATCH(struct No return pMemory->__nodevicememGetMemoryMappingDescriptor__(pMemory, ppMemDesc); } -static inline NvBool nodevicememShareCallback_DISPATCH(struct NoDeviceMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pResource->__nodevicememShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); -} - static inline NV_STATUS nodevicememControlFilter_DISPATCH(struct NoDeviceMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__nodevicememControlFilter__(pResource, pCallContext, pParams); } -static inline void nodevicememAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct NoDeviceMemory *pResource, RsResourceRef *pReference) { - pResource->__nodevicememAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 nodevicememGetRefCount_DISPATCH(struct NoDeviceMemory *pResource) { - return pResource->__nodevicememGetRefCount__(pResource); -} - -static inline NV_STATUS nodevicememMapTo_DISPATCH(struct NoDeviceMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__nodevicememMapTo__(pResource, pParams); -} - -static inline NV_STATUS nodevicememControl_Prologue_DISPATCH(struct NoDeviceMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__nodevicememControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NvBool nodevicememIsGpuMapAllowed_DISPATCH(struct NoDeviceMemory *pMemory, struct OBJGPU *pGpu) { - return pMemory->__nodevicememIsGpuMapAllowed__(pMemory, pGpu); +static inline NV_STATUS nodevicememControlSerialization_Prologue_DISPATCH(struct NoDeviceMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__nodevicememControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool nodevicememCanCopy_DISPATCH(struct NoDeviceMemory *pResource) { @@ -205,16 +225,8 @@ static inline NV_STATUS nodevicememIsDuplicate_DISPATCH(struct NoDeviceMemory *p return pMemory->__nodevicememIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline NV_STATUS nodevicememUnmapFrom_DISPATCH(struct NoDeviceMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__nodevicememUnmapFrom__(pResource, pParams); -} - -static inline void nodevicememControl_Epilogue_DISPATCH(struct NoDeviceMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__nodevicememControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS nodevicememControlLookup_DISPATCH(struct NoDeviceMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__nodevicememControlLookup__(pResource, pParams, ppEntry); +static inline void nodevicememControlSerialization_Epilogue_DISPATCH(struct NoDeviceMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__nodevicememControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS nodevicememMap_DISPATCH(struct NoDeviceMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_nv_debug_dump_nvoc.c b/src/nvidia/generated/g_nv_debug_dump_nvoc.c index d5c38aac8..069c772dc 100644 --- a/src/nvidia/generated/g_nv_debug_dump_nvoc.c +++ b/src/nvidia/generated/g_nv_debug_dump_nvoc.c @@ -74,10 +74,6 @@ static NV_STATUS __nvoc_thunk_NvDebugDump_engstateStateInitLocked(struct OBJGPU return nvdStateInitLocked(pGpu, (struct NvDebugDump *)(((unsigned char *)pNvd) - __nvoc_rtti_NvDebugDump_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_nvdReconcileTunableState(POBJGPU pGpu, struct NvDebugDump *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_NvDebugDump_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_nvdStateLoad(POBJGPU pGpu, struct NvDebugDump *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_NvDebugDump_OBJENGSTATE.offset), arg0); } @@ -118,30 +114,10 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_nvdStatePreInitUnlocked(POBJGPU pGpu, return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_NvDebugDump_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_nvdGetTunableState(POBJGPU pGpu, struct NvDebugDump *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_NvDebugDump_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_nvdCompareTunableState(POBJGPU pGpu, struct NvDebugDump *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_NvDebugDump_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_nvdFreeTunableState(POBJGPU pGpu, struct NvDebugDump *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_NvDebugDump_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_nvdStatePostLoad(POBJGPU pGpu, struct NvDebugDump *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_NvDebugDump_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_nvdAllocTunableState(POBJGPU pGpu, struct NvDebugDump *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_NvDebugDump_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_nvdSetTunableState(POBJGPU pGpu, struct NvDebugDump *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_NvDebugDump_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_nvdIsPresent(POBJGPU pGpu, struct NvDebugDump *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_NvDebugDump_OBJENGSTATE.offset)); } @@ -188,8 +164,6 @@ static void __nvoc_init_funcTable_NvDebugDump_1(NvDebugDump *pThis) { pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_NvDebugDump_engstateStateInitLocked; - pThis->__nvdReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_nvdReconcileTunableState; - pThis->__nvdStateLoad__ = &__nvoc_thunk_OBJENGSTATE_nvdStateLoad; pThis->__nvdStateUnload__ = &__nvoc_thunk_OBJENGSTATE_nvdStateUnload; @@ -210,18 +184,8 @@ static void __nvoc_init_funcTable_NvDebugDump_1(NvDebugDump *pThis) { pThis->__nvdStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_nvdStatePreInitUnlocked; - pThis->__nvdGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_nvdGetTunableState; - - pThis->__nvdCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_nvdCompareTunableState; - - pThis->__nvdFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_nvdFreeTunableState; - pThis->__nvdStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_nvdStatePostLoad; - pThis->__nvdAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_nvdAllocTunableState; - - pThis->__nvdSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_nvdSetTunableState; - pThis->__nvdIsPresent__ = &__nvoc_thunk_OBJENGSTATE_nvdIsPresent; } @@ -243,13 +207,16 @@ NV_STATUS __nvoc_objCreate_NvDebugDump(NvDebugDump **ppThis, Dynamic *pParent, N Object *pParentObj; NvDebugDump *pThis; - pThis = portMemAllocNonPaged(sizeof(NvDebugDump)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(NvDebugDump), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(NvDebugDump)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_NvDebugDump); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -265,11 +232,17 @@ NV_STATUS __nvoc_objCreate_NvDebugDump(NvDebugDump **ppThis, Dynamic *pParent, N if (status != NV_OK) goto __nvoc_objCreate_NvDebugDump_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_NvDebugDump_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(NvDebugDump)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_nv_debug_dump_nvoc.h b/src/nvidia/generated/g_nv_debug_dump_nvoc.h index 9b6fda5e8..bbf901447 100644 --- a/src/nvidia/generated/g_nv_debug_dump_nvoc.h +++ b/src/nvidia/generated/g_nv_debug_dump_nvoc.h @@ -165,7 +165,6 @@ struct NvDebugDump { struct NvDebugDump *__nvoc_pbase_NvDebugDump; NV_STATUS (*__nvdConstructEngine__)(struct OBJGPU *, struct NvDebugDump *, ENGDESCRIPTOR); NV_STATUS (*__nvdStateInitLocked__)(struct OBJGPU *, struct NvDebugDump *); - NV_STATUS (*__nvdReconcileTunableState__)(POBJGPU, struct NvDebugDump *, void *); NV_STATUS (*__nvdStateLoad__)(POBJGPU, struct NvDebugDump *, NvU32); NV_STATUS (*__nvdStateUnload__)(POBJGPU, struct NvDebugDump *, NvU32); NV_STATUS (*__nvdStatePreLoad__)(POBJGPU, struct NvDebugDump *, NvU32); @@ -176,12 +175,7 @@ struct NvDebugDump { void (*__nvdInitMissing__)(POBJGPU, struct NvDebugDump *); NV_STATUS (*__nvdStatePreInitLocked__)(POBJGPU, struct NvDebugDump *); NV_STATUS (*__nvdStatePreInitUnlocked__)(POBJGPU, struct NvDebugDump *); - NV_STATUS (*__nvdGetTunableState__)(POBJGPU, struct NvDebugDump *, void *); - NV_STATUS (*__nvdCompareTunableState__)(POBJGPU, struct NvDebugDump *, void *, void *); - void (*__nvdFreeTunableState__)(POBJGPU, struct NvDebugDump *, void *); NV_STATUS (*__nvdStatePostLoad__)(POBJGPU, struct NvDebugDump *, NvU32); - NV_STATUS (*__nvdAllocTunableState__)(POBJGPU, struct NvDebugDump *, void **); - NV_STATUS (*__nvdSetTunableState__)(POBJGPU, struct NvDebugDump *, void *); NvBool (*__nvdIsPresent__)(POBJGPU, struct NvDebugDump *); NVD_DEBUG_BUFFER *pHeadDebugBuffer; NVD_ENGINE_CALLBACK *pCallbacks; @@ -219,7 +213,6 @@ NV_STATUS __nvoc_objCreate_NvDebugDump(NvDebugDump**, Dynamic*, NvU32); #define nvdConstructEngine(pGpu, pNvd, arg0) nvdConstructEngine_DISPATCH(pGpu, pNvd, arg0) #define nvdStateInitLocked(pGpu, pNvd) nvdStateInitLocked_DISPATCH(pGpu, pNvd) -#define nvdReconcileTunableState(pGpu, pEngstate, pTunableState) nvdReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define nvdStateLoad(pGpu, pEngstate, arg0) nvdStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define nvdStateUnload(pGpu, pEngstate, arg0) nvdStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define nvdStatePreLoad(pGpu, pEngstate, arg0) nvdStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) @@ -230,12 +223,7 @@ NV_STATUS __nvoc_objCreate_NvDebugDump(NvDebugDump**, Dynamic*, NvU32); #define nvdInitMissing(pGpu, pEngstate) nvdInitMissing_DISPATCH(pGpu, pEngstate) #define nvdStatePreInitLocked(pGpu, pEngstate) nvdStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define nvdStatePreInitUnlocked(pGpu, pEngstate) nvdStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define nvdGetTunableState(pGpu, pEngstate, pTunableState) nvdGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define nvdCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) nvdCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define nvdFreeTunableState(pGpu, pEngstate, pTunableState) nvdFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define nvdStatePostLoad(pGpu, pEngstate, arg0) nvdStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define nvdAllocTunableState(pGpu, pEngstate, ppTunableState) nvdAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define nvdSetTunableState(pGpu, pEngstate, pTunableState) nvdSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define nvdIsPresent(pGpu, pEngstate) nvdIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS nvdConstructEngine_IMPL(struct OBJGPU *pGpu, struct NvDebugDump *pNvd, ENGDESCRIPTOR arg0); @@ -249,10 +237,6 @@ static inline NV_STATUS nvdStateInitLocked_DISPATCH(struct OBJGPU *pGpu, struct return pNvd->__nvdStateInitLocked__(pGpu, pNvd); } -static inline NV_STATUS nvdReconcileTunableState_DISPATCH(POBJGPU pGpu, struct NvDebugDump *pEngstate, void *pTunableState) { - return pEngstate->__nvdReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS nvdStateLoad_DISPATCH(POBJGPU pGpu, struct NvDebugDump *pEngstate, NvU32 arg0) { return pEngstate->__nvdStateLoad__(pGpu, pEngstate, arg0); } @@ -293,30 +277,10 @@ static inline NV_STATUS nvdStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct Nv return pEngstate->__nvdStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS nvdGetTunableState_DISPATCH(POBJGPU pGpu, struct NvDebugDump *pEngstate, void *pTunableState) { - return pEngstate->__nvdGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS nvdCompareTunableState_DISPATCH(POBJGPU pGpu, struct NvDebugDump *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__nvdCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void nvdFreeTunableState_DISPATCH(POBJGPU pGpu, struct NvDebugDump *pEngstate, void *pTunableState) { - pEngstate->__nvdFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS nvdStatePostLoad_DISPATCH(POBJGPU pGpu, struct NvDebugDump *pEngstate, NvU32 arg0) { return pEngstate->__nvdStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS nvdAllocTunableState_DISPATCH(POBJGPU pGpu, struct NvDebugDump *pEngstate, void **ppTunableState) { - return pEngstate->__nvdAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS nvdSetTunableState_DISPATCH(POBJGPU pGpu, struct NvDebugDump *pEngstate, void *pTunableState) { - return pEngstate->__nvdSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool nvdIsPresent_DISPATCH(POBJGPU pGpu, struct NvDebugDump *pEngstate) { return pEngstate->__nvdIsPresent__(pGpu, pEngstate); } diff --git a/src/nvidia/generated/g_nv_name_released.h b/src/nvidia/generated/g_nv_name_released.h index da6f41067..eb63a94fa 100644 --- a/src/nvidia/generated/g_nv_name_released.h +++ b/src/nvidia/generated/g_nv_name_released.h @@ -992,10 +992,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x13BD, 0x11d0, 0x10DE, "GRID M10-2Q" }, { 0x13BD, 0x11d1, 0x10DE, "GRID M10-4Q" }, { 0x13BD, 0x11d2, 0x10DE, "GRID M10-8Q" }, - { 0x13BD, 0x11d3, 0x10DE, "GRID M10-1A" }, - { 0x13BD, 0x11d4, 0x10DE, "GRID M10-2A" }, - { 0x13BD, 0x11d5, 0x10DE, "GRID M10-4A" }, - { 0x13BD, 0x11d6, 0x10DE, "GRID M10-8A" }, { 0x13BD, 0x1286, 0x10DE, "GRID M10-2B" }, { 0x13BD, 0x12ee, 0x10DE, "GRID M10-2B4" }, { 0x13BD, 0x1339, 0x10DE, "GRID M10-1B4" }, @@ -1007,10 +1003,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x13F2, 0x1176, 0x10DE, "GRID M60-0B" }, { 0x13F2, 0x1177, 0x10DE, "GRID M60-1B" }, { 0x13F2, 0x117d, 0x10DE, "GRID M60-2B" }, - { 0x13F2, 0x11ae, 0x10DE, "GRID M60-1A" }, - { 0x13F2, 0x11af, 0x10DE, "GRID M60-2A" }, - { 0x13F2, 0x11b0, 0x10DE, "GRID M60-4A" }, - { 0x13F2, 0x11b1, 0x10DE, "GRID M60-8A" }, { 0x13F2, 0x12ec, 0x10DE, "GRID M60-2B4" }, { 0x13F2, 0x1337, 0x10DE, "GRID M60-1B4" }, { 0x13F3, 0x117c, 0x10DE, "GRID M6-2B" }, @@ -1021,10 +1013,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x13F3, 0x1182, 0x10DE, "GRID M6-2Q" }, { 0x13F3, 0x1183, 0x10DE, "GRID M6-4Q" }, { 0x13F3, 0x1184, 0x10DE, "GRID M6-8Q" }, - { 0x13F3, 0x11aa, 0x10DE, "GRID M6-1A" }, - { 0x13F3, 0x11ab, 0x10DE, "GRID M6-2A" }, - { 0x13F3, 0x11ac, 0x10DE, "GRID M6-4A" }, - { 0x13F3, 0x11ad, 0x10DE, "GRID M6-8A" }, { 0x13F3, 0x12ed, 0x10DE, "GRID M6-2B4" }, { 0x13F3, 0x1338, 0x10DE, "GRID M6-1B4" }, { 0x15F7, 0x1265, 0x10DE, "GRID P100C-1B" }, @@ -1033,11 +1021,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x15F7, 0x1268, 0x10DE, "GRID P100C-4Q" }, { 0x15F7, 0x1269, 0x10DE, "GRID P100C-6Q" }, { 0x15F7, 0x126a, 0x10DE, "GRID P100C-12Q" }, - { 0x15F7, 0x126b, 0x10DE, "GRID P100C-1A" }, - { 0x15F7, 0x126c, 0x10DE, "GRID P100C-2A" }, - { 0x15F7, 0x126d, 0x10DE, "GRID P100C-4A" }, - { 0x15F7, 0x126e, 0x10DE, "GRID P100C-6A" }, - { 0x15F7, 0x126f, 0x10DE, "GRID P100C-12A" }, { 0x15F7, 0x128d, 0x10DE, "GRID P100C-2B" }, { 0x15F7, 0x12f4, 0x10DE, "GRID P100C-2B4" }, { 0x15F7, 0x133f, 0x10DE, "GRID P100C-1B4" }, @@ -1050,11 +1033,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x15F8, 0x1224, 0x10DE, "GRID P100-4Q" }, { 0x15F8, 0x1225, 0x10DE, "GRID P100-8Q" }, { 0x15F8, 0x1226, 0x10DE, "GRID P100-16Q" }, - { 0x15F8, 0x1227, 0x10DE, "GRID P100-1A" }, - { 0x15F8, 0x1228, 0x10DE, "GRID P100-2A" }, - { 0x15F8, 0x1229, 0x10DE, "GRID P100-4A" }, - { 0x15F8, 0x122a, 0x10DE, "GRID P100-8A" }, - { 0x15F8, 0x122b, 0x10DE, "GRID P100-16A" }, { 0x15F8, 0x128c, 0x10DE, "GRID P100-2B" }, { 0x15F8, 0x12f2, 0x10DE, "GRID P100-2B4" }, { 0x15F8, 0x133d, 0x10DE, "GRID P100-1B4" }, @@ -1067,11 +1045,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x15F9, 0x122f, 0x10DE, "GRID P100X-4Q" }, { 0x15F9, 0x1230, 0x10DE, "GRID P100X-8Q" }, { 0x15F9, 0x1231, 0x10DE, "GRID P100X-16Q" }, - { 0x15F9, 0x1232, 0x10DE, "GRID P100X-1A" }, - { 0x15F9, 0x1233, 0x10DE, "GRID P100X-2A" }, - { 0x15F9, 0x1234, 0x10DE, "GRID P100X-4A" }, - { 0x15F9, 0x1235, 0x10DE, "GRID P100X-8A" }, - { 0x15F9, 0x1236, 0x10DE, "GRID P100X-16A" }, { 0x15F9, 0x128b, 0x10DE, "GRID P100X-2B" }, { 0x15F9, 0x12f3, 0x10DE, "GRID P100X-2B4" }, { 0x15F9, 0x133e, 0x10DE, "GRID P100X-1B4" }, @@ -1087,14 +1060,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1B38, 0x11ed, 0x10DE, "GRID P40-8Q" }, { 0x1B38, 0x11ee, 0x10DE, "GRID P40-12Q" }, { 0x1B38, 0x11ef, 0x10DE, "GRID P40-24Q" }, - { 0x1B38, 0x11f0, 0x10DE, "GRID P40-1A" }, - { 0x1B38, 0x11f1, 0x10DE, "GRID P40-2A" }, - { 0x1B38, 0x11f2, 0x10DE, "GRID P40-3A" }, - { 0x1B38, 0x11f3, 0x10DE, "GRID P40-4A" }, - { 0x1B38, 0x11f4, 0x10DE, "GRID P40-6A" }, - { 0x1B38, 0x11f5, 0x10DE, "GRID P40-8A" }, - { 0x1B38, 0x11f6, 0x10DE, "GRID P40-12A" }, - { 0x1B38, 0x11f7, 0x10DE, "GRID P40-24A" }, { 0x1B38, 0x1287, 0x10DE, "GRID P40-2B" }, { 0x1B38, 0x12b1, 0x10DE, "GeForce GTX P40-24" }, { 0x1B38, 0x12b2, 0x10DE, "GeForce GTX P40-12" }, @@ -1115,10 +1080,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1BB3, 0x1205, 0x10DE, "GRID P4-2Q" }, { 0x1BB3, 0x1206, 0x10DE, "GRID P4-4Q" }, { 0x1BB3, 0x1207, 0x10DE, "GRID P4-8Q" }, - { 0x1BB3, 0x1208, 0x10DE, "GRID P4-1A" }, - { 0x1BB3, 0x1209, 0x10DE, "GRID P4-2A" }, - { 0x1BB3, 0x120a, 0x10DE, "GRID P4-4A" }, - { 0x1BB3, 0x120b, 0x10DE, "GRID P4-8A" }, { 0x1BB3, 0x1288, 0x10DE, "GRID P4-2B" }, { 0x1BB3, 0x12f1, 0x10DE, "GRID P4-2B4" }, { 0x1BB3, 0x133c, 0x10DE, "GRID P4-1B4" }, @@ -1133,11 +1094,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1BB4, 0x11fb, 0x10DE, "GRID P6-4Q" }, { 0x1BB4, 0x11fc, 0x10DE, "GRID P6-8Q" }, { 0x1BB4, 0x11fd, 0x10DE, "GRID P6-16Q" }, - { 0x1BB4, 0x11fe, 0x10DE, "GRID P6-1A" }, - { 0x1BB4, 0x11ff, 0x10DE, "GRID P6-2A" }, - { 0x1BB4, 0x1200, 0x10DE, "GRID P6-4A" }, - { 0x1BB4, 0x1201, 0x10DE, "GRID P6-8A" }, - { 0x1BB4, 0x1202, 0x10DE, "GRID P6-16A" }, { 0x1BB4, 0x1289, 0x10DE, "GRID P6-2B" }, { 0x1BB4, 0x12f0, 0x10DE, "GRID P6-2B4" }, { 0x1BB4, 0x133b, 0x10DE, "GRID P6-1B4" }, @@ -1150,11 +1106,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1DB1, 0x125c, 0x10DE, "GRID V100X-4Q" }, { 0x1DB1, 0x125d, 0x10DE, "GRID V100X-8Q" }, { 0x1DB1, 0x125e, 0x10DE, "GRID V100X-16Q" }, - { 0x1DB1, 0x125f, 0x10DE, "GRID V100X-1A" }, - { 0x1DB1, 0x1260, 0x10DE, "GRID V100X-2A" }, - { 0x1DB1, 0x1261, 0x10DE, "GRID V100X-4A" }, - { 0x1DB1, 0x1262, 0x10DE, "GRID V100X-8A" }, - { 0x1DB1, 0x1263, 0x10DE, "GRID V100X-16A" }, { 0x1DB1, 0x128e, 0x10DE, "GRID V100X-2B" }, { 0x1DB1, 0x12f6, 0x10DE, "GRID V100X-2B4" }, { 0x1DB1, 0x1341, 0x10DE, "GRID V100X-1B4" }, @@ -1168,11 +1119,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1DB3, 0x1294, 0x10DE, "GRID V100L-4Q" }, { 0x1DB3, 0x1295, 0x10DE, "GRID V100L-8Q" }, { 0x1DB3, 0x1296, 0x10DE, "GRID V100L-16Q" }, - { 0x1DB3, 0x1297, 0x10DE, "GRID V100L-1A" }, - { 0x1DB3, 0x1298, 0x10DE, "GRID V100L-2A" }, - { 0x1DB3, 0x1299, 0x10DE, "GRID V100L-4A" }, - { 0x1DB3, 0x129a, 0x10DE, "GRID V100L-8A" }, - { 0x1DB3, 0x129b, 0x10DE, "GRID V100L-16A" }, { 0x1DB3, 0x12f9, 0x10DE, "GRID V100L-2B4" }, { 0x1DB3, 0x1344, 0x10DE, "GRID V100L-1B4" }, { 0x1DB3, 0x137a, 0x10DE, "GRID V100L-16C" }, @@ -1184,11 +1130,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1DB4, 0x1251, 0x10DE, "GRID V100-4Q" }, { 0x1DB4, 0x1252, 0x10DE, "GRID V100-8Q" }, { 0x1DB4, 0x1253, 0x10DE, "GRID V100-16Q" }, - { 0x1DB4, 0x1254, 0x10DE, "GRID V100-1A" }, - { 0x1DB4, 0x1255, 0x10DE, "GRID V100-2A" }, - { 0x1DB4, 0x1256, 0x10DE, "GRID V100-4A" }, - { 0x1DB4, 0x1257, 0x10DE, "GRID V100-8A" }, - { 0x1DB4, 0x1258, 0x10DE, "GRID V100-16A" }, { 0x1DB4, 0x128f, 0x10DE, "GRID V100-2B" }, { 0x1DB4, 0x12f5, 0x10DE, "GRID V100-2B4" }, { 0x1DB4, 0x1340, 0x10DE, "GRID V100-1B4" }, @@ -1203,12 +1144,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1DB5, 0x12d0, 0x10DE, "GRID V100DX-8Q" }, { 0x1DB5, 0x12d1, 0x10DE, "GRID V100DX-16Q" }, { 0x1DB5, 0x12d2, 0x10DE, "GRID V100DX-32Q" }, - { 0x1DB5, 0x12d3, 0x10DE, "GRID V100DX-1A" }, - { 0x1DB5, 0x12d4, 0x10DE, "GRID V100DX-2A" }, - { 0x1DB5, 0x12d5, 0x10DE, "GRID V100DX-4A" }, - { 0x1DB5, 0x12d6, 0x10DE, "GRID V100DX-8A" }, - { 0x1DB5, 0x12d7, 0x10DE, "GRID V100DX-16A" }, - { 0x1DB5, 0x12d8, 0x10DE, "GRID V100DX-32A" }, { 0x1DB5, 0x12f8, 0x10DE, "GRID V100DX-2B4" }, { 0x1DB5, 0x1343, 0x10DE, "GRID V100DX-1B4" }, { 0x1DB5, 0x1376, 0x10DE, "GRID V100DX-32C" }, @@ -1223,12 +1158,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1DB6, 0x12c2, 0x10DE, "GRID V100D-8Q" }, { 0x1DB6, 0x12c3, 0x10DE, "GRID V100D-16Q" }, { 0x1DB6, 0x12c4, 0x10DE, "GRID V100D-32Q" }, - { 0x1DB6, 0x12c5, 0x10DE, "GRID V100D-1A" }, - { 0x1DB6, 0x12c6, 0x10DE, "GRID V100D-2A" }, - { 0x1DB6, 0x12c7, 0x10DE, "GRID V100D-4A" }, - { 0x1DB6, 0x12c8, 0x10DE, "GRID V100D-8A" }, - { 0x1DB6, 0x12c9, 0x10DE, "GRID V100D-16A" }, - { 0x1DB6, 0x12ca, 0x10DE, "GRID V100D-32A" }, { 0x1DB6, 0x12f7, 0x10DE, "GRID V100D-2B4" }, { 0x1DB6, 0x1342, 0x10DE, "GRID V100D-1B4" }, { 0x1DB6, 0x1377, 0x10DE, "GRID V100D-32C" }, @@ -1246,12 +1175,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1DF6, 0x13e8, 0x10DE, "GRID V100S-8Q" }, { 0x1DF6, 0x13e9, 0x10DE, "GRID V100S-16Q" }, { 0x1DF6, 0x13ea, 0x10DE, "GRID V100S-32Q" }, - { 0x1DF6, 0x13eb, 0x10DE, "GRID V100S-1A" }, - { 0x1DF6, 0x13ec, 0x10DE, "GRID V100S-2A" }, - { 0x1DF6, 0x13ed, 0x10DE, "GRID V100S-4A" }, - { 0x1DF6, 0x13ee, 0x10DE, "GRID V100S-8A" }, - { 0x1DF6, 0x13ef, 0x10DE, "GRID V100S-16A" }, - { 0x1DF6, 0x13f0, 0x10DE, "GRID V100S-32A" }, { 0x1DF6, 0x13f1, 0x10DE, "GRID V100S-4C" }, { 0x1DF6, 0x13f2, 0x10DE, "GRID V100S-8C" }, { 0x1DF6, 0x13f3, 0x10DE, "GRID V100S-16C" }, @@ -1296,26 +1219,8 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1E30, 0x13cc, 0x10DE, "GRID RTX8000-16" }, { 0x1E30, 0x1437, 0x10DE, "GRID RTX6000-1B" }, { 0x1E30, 0x1438, 0x10DE, "GRID RTX6000-2B" }, - { 0x1E30, 0x1439, 0x10DE, "GRID RTX6000-1A" }, - { 0x1E30, 0x143a, 0x10DE, "GRID RTX6000-2A" }, - { 0x1E30, 0x143b, 0x10DE, "GRID RTX6000-3A" }, - { 0x1E30, 0x143c, 0x10DE, "GRID RTX6000-4A" }, - { 0x1E30, 0x143d, 0x10DE, "GRID RTX6000-6A" }, - { 0x1E30, 0x143e, 0x10DE, "GRID RTX6000-8A" }, - { 0x1E30, 0x143f, 0x10DE, "GRID RTX6000-12A" }, - { 0x1E30, 0x1440, 0x10DE, "GRID RTX6000-24A" }, { 0x1E30, 0x1441, 0x10DE, "GRID RTX8000-1B" }, { 0x1E30, 0x1442, 0x10DE, "GRID RTX8000-2B" }, - { 0x1E30, 0x1443, 0x10DE, "GRID RTX8000-1A" }, - { 0x1E30, 0x1444, 0x10DE, "GRID RTX8000-2A" }, - { 0x1E30, 0x1445, 0x10DE, "GRID RTX8000-3A" }, - { 0x1E30, 0x1446, 0x10DE, "GRID RTX8000-4A" }, - { 0x1E30, 0x1447, 0x10DE, "GRID RTX8000-6A" }, - { 0x1E30, 0x1448, 0x10DE, "GRID RTX8000-8A" }, - { 0x1E30, 0x1449, 0x10DE, "GRID RTX8000-12A" }, - { 0x1E30, 0x144a, 0x10DE, "GRID RTX8000-16A" }, - { 0x1E30, 0x144b, 0x10DE, "GRID RTX8000-24A" }, - { 0x1E30, 0x144c, 0x10DE, "GRID RTX8000-48A" }, { 0x1E37, 0x1347, 0x10DE, "GeForce RTX T10x-8" }, { 0x1E37, 0x1348, 0x10DE, "GeForce RTX T10x-4" }, { 0x1E37, 0x1349, 0x10DE, "GeForce RTX T10x-2" }, @@ -1341,14 +1246,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1E78, 0x13fe, 0x10DE, "GRID RTX6000P-8Q" }, { 0x1E78, 0x13ff, 0x10DE, "GRID RTX6000P-12Q" }, { 0x1E78, 0x1400, 0x10DE, "GRID RTX6000P-24Q" }, - { 0x1E78, 0x1401, 0x10DE, "GRID RTX6000P-1A" }, - { 0x1E78, 0x1402, 0x10DE, "GRID RTX6000P-2A" }, - { 0x1E78, 0x1403, 0x10DE, "GRID RTX6000P-3A" }, - { 0x1E78, 0x1404, 0x10DE, "GRID RTX6000P-4A" }, - { 0x1E78, 0x1405, 0x10DE, "GRID RTX6000P-6A" }, - { 0x1E78, 0x1406, 0x10DE, "GRID RTX6000P-8A" }, - { 0x1E78, 0x1407, 0x10DE, "GRID RTX6000P-12A" }, - { 0x1E78, 0x1408, 0x10DE, "GRID RTX6000P-24A" }, { 0x1E78, 0x1409, 0x10DE, "GRID RTX6000P-6" }, { 0x1E78, 0x140a, 0x10DE, "GRID RTX6000P-8" }, { 0x1E78, 0x140b, 0x10DE, "GRID RTX6000P-12" }, @@ -1370,15 +1267,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1E78, 0x141b, 0x10DE, "GRID RTX8000P-16Q" }, { 0x1E78, 0x141c, 0x10DE, "GRID RTX8000P-24Q" }, { 0x1E78, 0x141d, 0x10DE, "GRID RTX8000P-48Q" }, - { 0x1E78, 0x141e, 0x10DE, "GRID RTX8000P-1A" }, - { 0x1E78, 0x141f, 0x10DE, "GRID RTX8000P-2A" }, - { 0x1E78, 0x1420, 0x10DE, "GRID RTX8000P-3A" }, - { 0x1E78, 0x1421, 0x10DE, "GRID RTX8000P-4A" }, - { 0x1E78, 0x1422, 0x10DE, "GRID RTX8000P-6A" }, - { 0x1E78, 0x1423, 0x10DE, "GRID RTX8000P-8A" }, - { 0x1E78, 0x1424, 0x10DE, "GRID RTX8000P-12A" }, - { 0x1E78, 0x1425, 0x10DE, "GRID RTX8000P-24A" }, - { 0x1E78, 0x1426, 0x10DE, "GRID RTX8000P-48A" }, { 0x1E78, 0x1427, 0x10DE, "GRID RTX8000P-12" }, { 0x1E78, 0x1428, 0x10DE, "GRID RTX8000P-16" }, { 0x1E78, 0x1429, 0x10DE, "GRID RTX8000P-24" }, @@ -1390,7 +1278,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1E78, 0x142f, 0x10DE, "GRID RTX8000P-16C" }, { 0x1E78, 0x1430, 0x10DE, "GRID RTX8000P-24C" }, { 0x1E78, 0x1431, 0x10DE, "GRID RTX8000P-48C" }, - { 0x1E78, 0x1436, 0x10DE, "GRID RTX8000P-16A" }, { 0x1EB8, 0x1309, 0x10DE, "GRID T4-1B" }, { 0x1EB8, 0x130a, 0x10DE, "GRID T4-2B" }, { 0x1EB8, 0x130b, 0x10DE, "GRID T4-2B4" }, @@ -1399,11 +1286,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1EB8, 0x130e, 0x10DE, "GRID T4-4Q" }, { 0x1EB8, 0x130f, 0x10DE, "GRID T4-8Q" }, { 0x1EB8, 0x1310, 0x10DE, "GRID T4-16Q" }, - { 0x1EB8, 0x1311, 0x10DE, "GRID T4-1A" }, - { 0x1EB8, 0x1312, 0x10DE, "GRID T4-2A" }, - { 0x1EB8, 0x1313, 0x10DE, "GRID T4-4A" }, - { 0x1EB8, 0x1314, 0x10DE, "GRID T4-8A" }, - { 0x1EB8, 0x1315, 0x10DE, "GRID T4-16A" }, { 0x1EB8, 0x1345, 0x10DE, "GRID T4-1B4" }, { 0x1EB8, 0x1367, 0x10DE, "GRID RTX T4-4" }, { 0x1EB8, 0x1368, 0x10DE, "GRID RTX T4-8" }, @@ -1522,16 +1404,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2230, 0x1503, 0x10DE, "NVIDIA RTXA6000-16Q" }, { 0x2230, 0x1504, 0x10DE, "NVIDIA RTXA6000-24Q" }, { 0x2230, 0x1505, 0x10DE, "NVIDIA RTXA6000-48Q" }, - { 0x2230, 0x1506, 0x10DE, "NVIDIA RTXA6000-1A" }, - { 0x2230, 0x1507, 0x10DE, "NVIDIA RTXA6000-2A" }, - { 0x2230, 0x1508, 0x10DE, "NVIDIA RTXA6000-3A" }, - { 0x2230, 0x1509, 0x10DE, "NVIDIA RTXA6000-4A" }, - { 0x2230, 0x150a, 0x10DE, "NVIDIA RTXA6000-6A" }, - { 0x2230, 0x150b, 0x10DE, "NVIDIA RTXA6000-8A" }, - { 0x2230, 0x150c, 0x10DE, "NVIDIA RTXA6000-12A" }, - { 0x2230, 0x150d, 0x10DE, "NVIDIA RTXA6000-16A" }, - { 0x2230, 0x150e, 0x10DE, "NVIDIA RTXA6000-24A" }, - { 0x2230, 0x150f, 0x10DE, "NVIDIA RTXA6000-48A" }, { 0x2230, 0x1510, 0x10DE, "NVIDIA RTXA6000-12" }, { 0x2230, 0x1511, 0x10DE, "NVIDIA RTXA6000-16" }, { 0x2230, 0x1512, 0x10DE, "NVIDIA RTXA6000-24" }, @@ -1553,14 +1425,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2231, 0x1569, 0x10DE, "NVIDIA RTXA5000-8Q" }, { 0x2231, 0x156a, 0x10DE, "NVIDIA RTXA5000-12Q" }, { 0x2231, 0x156b, 0x10DE, "NVIDIA RTXA5000-24Q" }, - { 0x2231, 0x156c, 0x10DE, "NVIDIA RTXA5000-1A" }, - { 0x2231, 0x156d, 0x10DE, "NVIDIA RTXA5000-2A" }, - { 0x2231, 0x156e, 0x10DE, "NVIDIA RTXA5000-3A" }, - { 0x2231, 0x156f, 0x10DE, "NVIDIA RTXA5000-4A" }, - { 0x2231, 0x1570, 0x10DE, "NVIDIA RTXA5000-6A" }, - { 0x2231, 0x1571, 0x10DE, "NVIDIA RTXA5000-8A" }, - { 0x2231, 0x1572, 0x10DE, "NVIDIA RTXA5000-12A" }, - { 0x2231, 0x1573, 0x10DE, "NVIDIA RTXA5000-24A" }, { 0x2231, 0x1574, 0x10DE, "NVIDIA RTXA5000-6" }, { 0x2231, 0x1575, 0x10DE, "NVIDIA RTXA5000-8" }, { 0x2231, 0x1576, 0x10DE, "NVIDIA RTXA5000-12" }, @@ -1580,14 +1444,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2233, 0x1663, 0x10DE, "NVIDIA RTXA5500-8Q" }, { 0x2233, 0x1664, 0x10DE, "NVIDIA RTXA5500-12Q" }, { 0x2233, 0x1665, 0x10DE, "NVIDIA RTXA5500-24Q" }, - { 0x2233, 0x1666, 0x10DE, "NVIDIA RTXA5500-1A" }, - { 0x2233, 0x1667, 0x10DE, "NVIDIA RTXA5500-2A" }, - { 0x2233, 0x1668, 0x10DE, "NVIDIA RTXA5500-3A" }, - { 0x2233, 0x1669, 0x10DE, "NVIDIA RTXA5500-4A" }, - { 0x2233, 0x166a, 0x10DE, "NVIDIA RTXA5500-6A" }, - { 0x2233, 0x166b, 0x10DE, "NVIDIA RTXA5500-8A" }, - { 0x2233, 0x166c, 0x10DE, "NVIDIA RTXA5500-12A" }, - { 0x2233, 0x166d, 0x10DE, "NVIDIA RTXA5500-24A" }, { 0x2233, 0x166e, 0x10DE, "NVIDIA RTXA5500-6" }, { 0x2233, 0x166f, 0x10DE, "NVIDIA RTXA5500-8" }, { 0x2233, 0x1670, 0x10DE, "NVIDIA RTXA5500-12" }, @@ -1609,16 +1465,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2235, 0x14de, 0x10DE, "NVIDIA A40-16Q" }, { 0x2235, 0x14df, 0x10DE, "NVIDIA A40-24Q" }, { 0x2235, 0x14e0, 0x10DE, "NVIDIA A40-48Q" }, - { 0x2235, 0x14e1, 0x10DE, "NVIDIA A40-1A" }, - { 0x2235, 0x14e2, 0x10DE, "NVIDIA A40-2A" }, - { 0x2235, 0x14e3, 0x10DE, "NVIDIA A40-3A" }, - { 0x2235, 0x14e4, 0x10DE, "NVIDIA A40-4A" }, - { 0x2235, 0x14e5, 0x10DE, "NVIDIA A40-6A" }, - { 0x2235, 0x14e6, 0x10DE, "NVIDIA A40-8A" }, - { 0x2235, 0x14e7, 0x10DE, "NVIDIA A40-12A" }, - { 0x2235, 0x14e8, 0x10DE, "NVIDIA A40-16A" }, - { 0x2235, 0x14e9, 0x10DE, "NVIDIA A40-24A" }, - { 0x2235, 0x14ea, 0x10DE, "NVIDIA A40-48A" }, { 0x2235, 0x14eb, 0x10DE, "NVIDIA A40-12" }, { 0x2235, 0x14ec, 0x10DE, "NVIDIA A40-16" }, { 0x2235, 0x14ed, 0x10DE, "NVIDIA A40-24" }, @@ -1646,14 +1492,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2236, 0x14bd, 0x10DE, "NVIDIA A10-8Q" }, { 0x2236, 0x14be, 0x10DE, "NVIDIA A10-12Q" }, { 0x2236, 0x14bf, 0x10DE, "NVIDIA A10-24Q" }, - { 0x2236, 0x14c0, 0x10DE, "NVIDIA A10-1A" }, - { 0x2236, 0x14c1, 0x10DE, "NVIDIA A10-2A" }, - { 0x2236, 0x14c2, 0x10DE, "NVIDIA A10-3A" }, - { 0x2236, 0x14c3, 0x10DE, "NVIDIA A10-4A" }, - { 0x2236, 0x14c4, 0x10DE, "NVIDIA A10-6A" }, - { 0x2236, 0x14c5, 0x10DE, "NVIDIA A10-8A" }, - { 0x2236, 0x14c6, 0x10DE, "NVIDIA A10-12A" }, - { 0x2236, 0x14c7, 0x10DE, "NVIDIA A10-24A" }, { 0x2236, 0x14c8, 0x10DE, "NVIDIA A10-6" }, { 0x2236, 0x14c9, 0x10DE, "NVIDIA A10-8" }, { 0x2236, 0x14ca, 0x10DE, "NVIDIA A10-12" }, @@ -1685,14 +1523,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2237, 0x1631, 0x10DE, "NVIDIA A10G-8Q" }, { 0x2237, 0x1632, 0x10DE, "NVIDIA A10G-12Q" }, { 0x2237, 0x1633, 0x10DE, "NVIDIA A10G-24Q" }, - { 0x2237, 0x1634, 0x10DE, "NVIDIA A10G-1A" }, - { 0x2237, 0x1635, 0x10DE, "NVIDIA A10G-2A" }, - { 0x2237, 0x1636, 0x10DE, "NVIDIA A10G-3A" }, - { 0x2237, 0x1637, 0x10DE, "NVIDIA A10G-4A" }, - { 0x2237, 0x1638, 0x10DE, "NVIDIA A10G-6A" }, - { 0x2237, 0x1639, 0x10DE, "NVIDIA A10G-8A" }, - { 0x2237, 0x163a, 0x10DE, "NVIDIA A10G-12A" }, - { 0x2237, 0x163b, 0x10DE, "NVIDIA A10G-24A" }, { 0x2238, 0x16a3, 0x10DE, "NVIDIA A10M-1B" }, { 0x2238, 0x16a4, 0x10DE, "NVIDIA A10M-2B" }, { 0x2238, 0x16a5, 0x10DE, "NVIDIA A10M-1Q" }, @@ -1701,12 +1531,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2238, 0x16a8, 0x10DE, "NVIDIA A10M-5Q" }, { 0x2238, 0x16a9, 0x10DE, "NVIDIA A10M-10Q" }, { 0x2238, 0x16aa, 0x10DE, "NVIDIA A10M-20Q" }, - { 0x2238, 0x16ab, 0x10DE, "NVIDIA A10M-1A" }, - { 0x2238, 0x16ac, 0x10DE, "NVIDIA A10M-2A" }, - { 0x2238, 0x16ad, 0x10DE, "NVIDIA A10M-4A" }, - { 0x2238, 0x16ae, 0x10DE, "NVIDIA A10M-5A" }, - { 0x2238, 0x16af, 0x10DE, "NVIDIA A10M-10A" }, - { 0x2238, 0x16b0, 0x10DE, "NVIDIA A10M-20A" }, { 0x2238, 0x16b1, 0x10DE, "NVIDIA A10M-2" }, { 0x2238, 0x16b2, 0x10DE, "NVIDIA A10M-4" }, { 0x2238, 0x16b3, 0x10DE, "NVIDIA A10M-5" }, @@ -1717,20 +1541,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2238, 0x16b8, 0x10DE, "NVIDIA A10M-10C" }, { 0x2238, 0x16b9, 0x10DE, "NVIDIA A10M-20C" }, { 0x2238, 0x16e6, 0x10DE, "NVIDIA A10M-1" }, - { 0x2322, 0x17e2, 0x10DE, "NVIDIA GPU-2322-17E2" }, - { 0x2322, 0x17e3, 0x10DE, "NVIDIA GPU-2322-17E3" }, - { 0x2322, 0x17e4, 0x10DE, "NVIDIA GPU-2322-17E4" }, - { 0x2322, 0x17e5, 0x10DE, "NVIDIA GPU-2322-17E5" }, - { 0x2322, 0x17e6, 0x10DE, "NVIDIA GPU-2322-17E6" }, - { 0x2322, 0x17e7, 0x10DE, "NVIDIA GPU-2322-17E7" }, - { 0x2322, 0x17e8, 0x10DE, "NVIDIA GPU-2322-17E8" }, - { 0x2322, 0x17e9, 0x10DE, "NVIDIA GPU-2322-17E9" }, - { 0x2322, 0x17ea, 0x10DE, "NVIDIA GPU-2322-17EA" }, - { 0x2322, 0x17eb, 0x10DE, "NVIDIA GPU-2322-17EB" }, - { 0x2322, 0x17ec, 0x10DE, "NVIDIA GPU-2322-17EC" }, - { 0x2322, 0x17ed, 0x10DE, "NVIDIA GPU-2322-17ED" }, - { 0x2322, 0x17ee, 0x10DE, "NVIDIA GPU-2322-17EE" }, - { 0x2322, 0x17ef, 0x10DE, "NVIDIA GPU-2322-17EF" }, { 0x2331, 0x16d3, 0x10DE, "NVIDIA H100-1-10C" }, { 0x2331, 0x16d4, 0x10DE, "NVIDIA H100-2-20C" }, { 0x2331, 0x16d5, 0x10DE, "NVIDIA H100-3-40C" }, @@ -1752,11 +1562,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x25B6, 0x1601, 0x10DE, "NVIDIA A16-4Q" }, { 0x25B6, 0x1602, 0x10DE, "NVIDIA A16-8Q" }, { 0x25B6, 0x1603, 0x10DE, "NVIDIA A16-16Q" }, - { 0x25B6, 0x1604, 0x10DE, "NVIDIA A16-1A" }, - { 0x25B6, 0x1605, 0x10DE, "NVIDIA A16-2A" }, - { 0x25B6, 0x1606, 0x10DE, "NVIDIA A16-4A" }, - { 0x25B6, 0x1607, 0x10DE, "NVIDIA A16-8A" }, - { 0x25B6, 0x1608, 0x10DE, "NVIDIA A16-16A" }, { 0x25B6, 0x1609, 0x10DE, "NVIDIA A16-4C" }, { 0x25B6, 0x160a, 0x10DE, "NVIDIA A16-8C" }, { 0x25B6, 0x160b, 0x10DE, "NVIDIA A16-16C" }, @@ -1767,11 +1572,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x25B6, 0x164a, 0x10DE, "NVIDIA A2-4Q" }, { 0x25B6, 0x164b, 0x10DE, "NVIDIA A2-8Q" }, { 0x25B6, 0x164c, 0x10DE, "NVIDIA A2-16Q" }, - { 0x25B6, 0x164d, 0x10DE, "NVIDIA A2-1A" }, - { 0x25B6, 0x164e, 0x10DE, "NVIDIA A2-2A" }, - { 0x25B6, 0x164f, 0x10DE, "NVIDIA A2-4A" }, - { 0x25B6, 0x1650, 0x10DE, "NVIDIA A2-8A" }, - { 0x25B6, 0x1651, 0x10DE, "NVIDIA A2-16A" }, { 0x25B6, 0x1652, 0x10DE, "NVIDIA A2-4" }, { 0x25B6, 0x1653, 0x10DE, "NVIDIA A2-8" }, { 0x25B6, 0x1654, 0x10DE, "NVIDIA A2-16" }, @@ -1790,16 +1590,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x26B1, 0x1711, 0x10DE, "NVIDIA RTX6000-Ada-16Q" }, { 0x26B1, 0x1712, 0x10DE, "NVIDIA RTX6000-Ada-24Q" }, { 0x26B1, 0x1713, 0x10DE, "NVIDIA RTX6000-Ada-48Q" }, - { 0x26B1, 0x1714, 0x10DE, "NVIDIA RTX6000-Ada-1A" }, - { 0x26B1, 0x1715, 0x10DE, "NVIDIA RTX6000-Ada-2A" }, - { 0x26B1, 0x1716, 0x10DE, "NVIDIA RTX6000-Ada-3A" }, - { 0x26B1, 0x1717, 0x10DE, "NVIDIA RTX6000-Ada-4A" }, - { 0x26B1, 0x1718, 0x10DE, "NVIDIA RTX6000-Ada-6A" }, - { 0x26B1, 0x1719, 0x10DE, "NVIDIA RTX6000-Ada-8A" }, - { 0x26B1, 0x171a, 0x10DE, "NVIDIA RTX6000-Ada-12A" }, - { 0x26B1, 0x171b, 0x10DE, "NVIDIA RTX6000-Ada-16A" }, - { 0x26B1, 0x171c, 0x10DE, "NVIDIA RTX6000-Ada-24A" }, - { 0x26B1, 0x171d, 0x10DE, "NVIDIA RTX6000-Ada-48A" }, { 0x26B1, 0x171e, 0x10DE, "NVIDIA RTX6000-Ada-1" }, { 0x26B1, 0x171f, 0x10DE, "NVIDIA RTX6000-Ada-2" }, { 0x26B1, 0x1720, 0x10DE, "NVIDIA RTX6000-Ada-3" }, @@ -1829,16 +1619,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x26B5, 0x1776, 0x10DE, "NVIDIA L40-16Q" }, { 0x26B5, 0x1777, 0x10DE, "NVIDIA L40-24Q" }, { 0x26B5, 0x1778, 0x10DE, "NVIDIA L40-48Q" }, - { 0x26B5, 0x1779, 0x10DE, "NVIDIA L40-1A" }, - { 0x26B5, 0x177a, 0x10DE, "NVIDIA L40-2A" }, - { 0x26B5, 0x177b, 0x10DE, "NVIDIA L40-3A" }, - { 0x26B5, 0x177c, 0x10DE, "NVIDIA L40-4A" }, - { 0x26B5, 0x177d, 0x10DE, "NVIDIA L40-6A" }, - { 0x26B5, 0x177e, 0x10DE, "NVIDIA L40-8A" }, - { 0x26B5, 0x177f, 0x10DE, "NVIDIA L40-12A" }, - { 0x26B5, 0x1780, 0x10DE, "NVIDIA L40-16A" }, - { 0x26B5, 0x1781, 0x10DE, "NVIDIA L40-24A" }, - { 0x26B5, 0x1782, 0x10DE, "NVIDIA L40-48A" }, { 0x26B5, 0x1783, 0x10DE, "NVIDIA L40-1" }, { 0x26B5, 0x1784, 0x10DE, "NVIDIA L40-2" }, { 0x26B5, 0x1785, 0x10DE, "NVIDIA L40-3" }, @@ -1866,14 +1646,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x26B8, 0x1755, 0x10DE, "NVIDIA L40G-8Q" }, { 0x26B8, 0x1756, 0x10DE, "NVIDIA L40G-12Q" }, { 0x26B8, 0x1757, 0x10DE, "NVIDIA L40G-24Q" }, - { 0x26B8, 0x1758, 0x10DE, "NVIDIA L40G-1A" }, - { 0x26B8, 0x1759, 0x10DE, "NVIDIA L40G-2A" }, - { 0x26B8, 0x175a, 0x10DE, "NVIDIA L40G-3A" }, - { 0x26B8, 0x175b, 0x10DE, "NVIDIA L40G-4A" }, - { 0x26B8, 0x175c, 0x10DE, "NVIDIA L40G-6A" }, - { 0x26B8, 0x175d, 0x10DE, "NVIDIA L40G-8A" }, - { 0x26B8, 0x175e, 0x10DE, "NVIDIA L40G-12A" }, - { 0x26B8, 0x175f, 0x10DE, "NVIDIA L40G-24A" }, { 0x26B8, 0x1760, 0x10DE, "NVIDIA L40G-1" }, { 0x26B8, 0x1761, 0x10DE, "NVIDIA L40G-2" }, { 0x26B8, 0x1762, 0x10DE, "NVIDIA L40G-3" }, @@ -1887,37 +1659,29 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x26B8, 0x176a, 0x10DE, "NVIDIA L40G-8C" }, { 0x26B8, 0x176b, 0x10DE, "NVIDIA L40G-12C" }, { 0x26B8, 0x176c, 0x10DE, "NVIDIA L40G-24C" }, - { 0x27B8, 0x172f, 0x10DE, "NVIDIA GPU-27B8-172F" }, - { 0x27B8, 0x1730, 0x10DE, "NVIDIA GPU-27B8-1730" }, - { 0x27B8, 0x1731, 0x10DE, "NVIDIA GPU-27B8-1731" }, - { 0x27B8, 0x1732, 0x10DE, "NVIDIA GPU-27B8-1732" }, - { 0x27B8, 0x1733, 0x10DE, "NVIDIA GPU-27B8-1733" }, - { 0x27B8, 0x1734, 0x10DE, "NVIDIA GPU-27B8-1734" }, - { 0x27B8, 0x1735, 0x10DE, "NVIDIA GPU-27B8-1735" }, - { 0x27B8, 0x1736, 0x10DE, "NVIDIA GPU-27B8-1736" }, - { 0x27B8, 0x1737, 0x10DE, "NVIDIA GPU-27B8-1737" }, - { 0x27B8, 0x1738, 0x10DE, "NVIDIA GPU-27B8-1738" }, - { 0x27B8, 0x1739, 0x10DE, "NVIDIA GPU-27B8-1739" }, - { 0x27B8, 0x173a, 0x10DE, "NVIDIA GPU-27B8-173A" }, - { 0x27B8, 0x173b, 0x10DE, "NVIDIA GPU-27B8-173B" }, - { 0x27B8, 0x173c, 0x10DE, "NVIDIA GPU-27B8-173C" }, - { 0x27B8, 0x173d, 0x10DE, "NVIDIA GPU-27B8-173D" }, - { 0x27B8, 0x173e, 0x10DE, "NVIDIA GPU-27B8-173E" }, - { 0x27B8, 0x173f, 0x10DE, "NVIDIA GPU-27B8-173F" }, - { 0x27B8, 0x1740, 0x10DE, "NVIDIA GPU-27B8-1740" }, - { 0x27B8, 0x1741, 0x10DE, "NVIDIA GPU-27B8-1741" }, - { 0x27B8, 0x1742, 0x10DE, "NVIDIA GPU-27B8-1742" }, - { 0x27B8, 0x1743, 0x10DE, "NVIDIA GPU-27B8-1743" }, - { 0x27B8, 0x1744, 0x10DE, "NVIDIA GPU-27B8-1744" }, - { 0x27B8, 0x1745, 0x10DE, "NVIDIA GPU-27B8-1745" }, - { 0x27B8, 0x1746, 0x10DE, "NVIDIA GPU-27B8-1746" }, - { 0x27B8, 0x1747, 0x10DE, "NVIDIA GPU-27B8-1747" }, - { 0x27B8, 0x1748, 0x10DE, "NVIDIA GPU-27B8-1748" }, - { 0x27B8, 0x1749, 0x10DE, "NVIDIA GPU-27B8-1749" }, - { 0x27B8, 0x174a, 0x10DE, "NVIDIA GPU-27B8-174A" }, - { 0x27B8, 0x174b, 0x10DE, "NVIDIA GPU-27B8-174B" }, - { 0x27B8, 0x174c, 0x10DE, "NVIDIA GPU-27B8-174C" }, - { 0x27B8, 0x174d, 0x10DE, "NVIDIA GPU-27B8-174D" }, + { 0x27B8, 0x172f, 0x10DE, "NVIDIA L4-1B" }, + { 0x27B8, 0x1730, 0x10DE, "NVIDIA L4-2B" }, + { 0x27B8, 0x1731, 0x10DE, "NVIDIA L4-1Q" }, + { 0x27B8, 0x1732, 0x10DE, "NVIDIA L4-2Q" }, + { 0x27B8, 0x1733, 0x10DE, "NVIDIA L4-3Q" }, + { 0x27B8, 0x1734, 0x10DE, "NVIDIA L4-4Q" }, + { 0x27B8, 0x1735, 0x10DE, "NVIDIA L4-6Q" }, + { 0x27B8, 0x1736, 0x10DE, "NVIDIA L4-8Q" }, + { 0x27B8, 0x1737, 0x10DE, "NVIDIA L4-12Q" }, + { 0x27B8, 0x1738, 0x10DE, "NVIDIA L4-24Q" }, + { 0x27B8, 0x1741, 0x10DE, "NVIDIA L4-1" }, + { 0x27B8, 0x1742, 0x10DE, "NVIDIA L4-2" }, + { 0x27B8, 0x1743, 0x10DE, "NVIDIA L4-3" }, + { 0x27B8, 0x1744, 0x10DE, "NVIDIA L4-4" }, + { 0x27B8, 0x1745, 0x10DE, "NVIDIA L4-6" }, + { 0x27B8, 0x1746, 0x10DE, "NVIDIA L4-8" }, + { 0x27B8, 0x1747, 0x10DE, "NVIDIA L4-12" }, + { 0x27B8, 0x1748, 0x10DE, "NVIDIA L4-24" }, + { 0x27B8, 0x1749, 0x10DE, "NVIDIA L4-4C" }, + { 0x27B8, 0x174a, 0x10DE, "NVIDIA L4-6C" }, + { 0x27B8, 0x174b, 0x10DE, "NVIDIA L4-8C" }, + { 0x27B8, 0x174c, 0x10DE, "NVIDIA L4-12C" }, + { 0x27B8, 0x174d, 0x10DE, "NVIDIA L4-24C" }, }; #endif // G_NV_NAME_RELEASED_H diff --git a/src/nvidia/generated/g_object_nvoc.c b/src/nvidia/generated/g_object_nvoc.c index 7e87023db..c4c08b854 100644 --- a/src/nvidia/generated/g_object_nvoc.c +++ b/src/nvidia/generated/g_object_nvoc.c @@ -90,13 +90,16 @@ NV_STATUS __nvoc_objCreate_Object(Object **ppThis, Dynamic *pParent, NvU32 creat Object *pParentObj; Object *pThis; - pThis = portMemAllocNonPaged(sizeof(Object)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Object), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(Object)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Object); + pThis->createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -112,11 +115,17 @@ NV_STATUS __nvoc_objCreate_Object(Object **ppThis, Dynamic *pParent, NvU32 creat if (status != NV_OK) goto __nvoc_objCreate_Object_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_Object_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(Object)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_object_nvoc.h b/src/nvidia/generated/g_object_nvoc.h index e12e664b5..6b1f5ebb4 100644 --- a/src/nvidia/generated/g_object_nvoc.h +++ b/src/nvidia/generated/g_object_nvoc.h @@ -79,6 +79,7 @@ struct Object { struct Object *pParent; struct NVOC_CHILD_TREE childTree; NvU32 ipVersion; + NvU32 createFlags; }; #ifndef __NVOC_CLASS_Object_TYPEDEF__ @@ -179,8 +180,6 @@ static inline struct Object *objGetDirectParent(struct Object *pObj) { #define NV_ODB_IP_VER_MAJOR 31:24 /* R-IVF */ #define IPVersion(pObj) staticCast((pObj), Object)->ipVersion -#define IsIPVersionValid(pObj) (DRF_VAL(_ODB, _IP_VER, _MAJOR, IPVersion(pObj)) != 0) -#define IsIPVersionOrLater(pObj, v0) (IPVersion(pObj) >= (v0)) // v0 .. v1 inclusive #define IsIPVersionInRange(pObj, v0, v1) ((IPVersion(pObj) >= (v0)) && (IPVersion(pObj) <= (v1))) diff --git a/src/nvidia/generated/g_objgpumon_nvoc.c b/src/nvidia/generated/g_objgpumon_nvoc.c index 66ca1b088..9c3932782 100644 --- a/src/nvidia/generated/g_objgpumon_nvoc.c +++ b/src/nvidia/generated/g_objgpumon_nvoc.c @@ -66,10 +66,6 @@ const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPUMON = /*pExportInfo=*/ &__nvoc_export_info_OBJGPUMON }; -static NV_STATUS __nvoc_thunk_OBJENGSTATE_gpumonReconcileTunableState(POBJGPU pGpu, struct OBJGPUMON *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJGPUMON_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_gpumonStateLoad(POBJGPU pGpu, struct OBJGPUMON *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJGPUMON_OBJENGSTATE.offset), arg0); } @@ -114,30 +110,10 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_gpumonStatePreInitUnlocked(POBJGPU pGp return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJGPUMON_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_gpumonGetTunableState(POBJGPU pGpu, struct OBJGPUMON *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJGPUMON_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_gpumonCompareTunableState(POBJGPU pGpu, struct OBJGPUMON *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJGPUMON_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_gpumonFreeTunableState(POBJGPU pGpu, struct OBJGPUMON *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJGPUMON_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_gpumonStatePostLoad(POBJGPU pGpu, struct OBJGPUMON *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJGPUMON_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_gpumonAllocTunableState(POBJGPU pGpu, struct OBJGPUMON *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJGPUMON_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_gpumonSetTunableState(POBJGPU pGpu, struct OBJGPUMON *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJGPUMON_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_gpumonConstructEngine(POBJGPU pGpu, struct OBJGPUMON *pEngstate, ENGDESCRIPTOR arg0) { return engstateConstructEngine(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJGPUMON_OBJENGSTATE.offset), arg0); } @@ -189,8 +165,6 @@ static void __nvoc_init_funcTable_OBJGPUMON_1(OBJGPUMON *pThis, RmHalspecOwner * PORT_UNREFERENCED_VARIABLE(chipHal); PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); - pThis->__gpumonReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_gpumonReconcileTunableState; - pThis->__gpumonStateLoad__ = &__nvoc_thunk_OBJENGSTATE_gpumonStateLoad; pThis->__gpumonStateUnload__ = &__nvoc_thunk_OBJENGSTATE_gpumonStateUnload; @@ -213,18 +187,8 @@ static void __nvoc_init_funcTable_OBJGPUMON_1(OBJGPUMON *pThis, RmHalspecOwner * pThis->__gpumonStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_gpumonStatePreInitUnlocked; - pThis->__gpumonGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_gpumonGetTunableState; - - pThis->__gpumonCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_gpumonCompareTunableState; - - pThis->__gpumonFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_gpumonFreeTunableState; - pThis->__gpumonStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_gpumonStatePostLoad; - pThis->__gpumonAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_gpumonAllocTunableState; - - pThis->__gpumonSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_gpumonSetTunableState; - pThis->__gpumonConstructEngine__ = &__nvoc_thunk_OBJENGSTATE_gpumonConstructEngine; pThis->__gpumonIsPresent__ = &__nvoc_thunk_OBJENGSTATE_gpumonIsPresent; @@ -249,13 +213,16 @@ NV_STATUS __nvoc_objCreate_OBJGPUMON(OBJGPUMON **ppThis, Dynamic *pParent, NvU32 OBJGPUMON *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(OBJGPUMON)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJGPUMON), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJGPUMON)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJGPUMON); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -275,11 +242,17 @@ NV_STATUS __nvoc_objCreate_OBJGPUMON(OBJGPUMON **ppThis, Dynamic *pParent, NvU32 if (status != NV_OK) goto __nvoc_objCreate_OBJGPUMON_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJGPUMON_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJGPUMON)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_objgpumon_nvoc.h b/src/nvidia/generated/g_objgpumon_nvoc.h index 5cde8e28e..b9ed79ebb 100644 --- a/src/nvidia/generated/g_objgpumon_nvoc.h +++ b/src/nvidia/generated/g_objgpumon_nvoc.h @@ -42,7 +42,6 @@ extern "C" { #include "gpu/gpu.h" #include "gpu/eng_state.h" -#include "kernel/gpu/fifo/kernel_fifo.h" #include "ctrl/ctrl2080/ctrl2080perf.h" @@ -59,7 +58,6 @@ struct OBJGPUMON { struct Object *__nvoc_pbase_Object; struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; struct OBJGPUMON *__nvoc_pbase_OBJGPUMON; - NV_STATUS (*__gpumonReconcileTunableState__)(POBJGPU, struct OBJGPUMON *, void *); NV_STATUS (*__gpumonStateLoad__)(POBJGPU, struct OBJGPUMON *, NvU32); NV_STATUS (*__gpumonStateUnload__)(POBJGPU, struct OBJGPUMON *, NvU32); NV_STATUS (*__gpumonStateInitLocked__)(POBJGPU, struct OBJGPUMON *); @@ -71,12 +69,7 @@ struct OBJGPUMON { void (*__gpumonInitMissing__)(POBJGPU, struct OBJGPUMON *); NV_STATUS (*__gpumonStatePreInitLocked__)(POBJGPU, struct OBJGPUMON *); NV_STATUS (*__gpumonStatePreInitUnlocked__)(POBJGPU, struct OBJGPUMON *); - NV_STATUS (*__gpumonGetTunableState__)(POBJGPU, struct OBJGPUMON *, void *); - NV_STATUS (*__gpumonCompareTunableState__)(POBJGPU, struct OBJGPUMON *, void *, void *); - void (*__gpumonFreeTunableState__)(POBJGPU, struct OBJGPUMON *, void *); NV_STATUS (*__gpumonStatePostLoad__)(POBJGPU, struct OBJGPUMON *, NvU32); - NV_STATUS (*__gpumonAllocTunableState__)(POBJGPU, struct OBJGPUMON *, void **); - NV_STATUS (*__gpumonSetTunableState__)(POBJGPU, struct OBJGPUMON *, void *); NV_STATUS (*__gpumonConstructEngine__)(POBJGPU, struct OBJGPUMON *, ENGDESCRIPTOR); NvBool (*__gpumonIsPresent__)(POBJGPU, struct OBJGPUMON *); }; @@ -111,7 +104,6 @@ NV_STATUS __nvoc_objCreate_OBJGPUMON(OBJGPUMON**, Dynamic*, NvU32); #define __objCreate_OBJGPUMON(ppNewObj, pParent, createFlags) \ __nvoc_objCreate_OBJGPUMON((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) -#define gpumonReconcileTunableState(pGpu, pEngstate, pTunableState) gpumonReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define gpumonStateLoad(pGpu, pEngstate, arg0) gpumonStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define gpumonStateUnload(pGpu, pEngstate, arg0) gpumonStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define gpumonStateInitLocked(pGpu, pEngstate) gpumonStateInitLocked_DISPATCH(pGpu, pEngstate) @@ -123,30 +115,21 @@ NV_STATUS __nvoc_objCreate_OBJGPUMON(OBJGPUMON**, Dynamic*, NvU32); #define gpumonInitMissing(pGpu, pEngstate) gpumonInitMissing_DISPATCH(pGpu, pEngstate) #define gpumonStatePreInitLocked(pGpu, pEngstate) gpumonStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define gpumonStatePreInitUnlocked(pGpu, pEngstate) gpumonStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define gpumonGetTunableState(pGpu, pEngstate, pTunableState) gpumonGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define gpumonCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) gpumonCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define gpumonFreeTunableState(pGpu, pEngstate, pTunableState) gpumonFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define gpumonStatePostLoad(pGpu, pEngstate, arg0) gpumonStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define gpumonAllocTunableState(pGpu, pEngstate, ppTunableState) gpumonAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define gpumonSetTunableState(pGpu, pEngstate, pTunableState) gpumonSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define gpumonConstructEngine(pGpu, pEngstate, arg0) gpumonConstructEngine_DISPATCH(pGpu, pEngstate, arg0) #define gpumonIsPresent(pGpu, pEngstate) gpumonIsPresent_DISPATCH(pGpu, pEngstate) -void gpumonGetContextProcessInfo_GM107(struct OBJGPU *pGpu, struct OBJGPUMON *pGpumon, RM_ENGINE_TYPE rmEngineTypeBegin, RM_ENGINE_TYPE rmEngineTypeEnd, NvU32 context, NvU32 *pProcID, NvU32 *pSubProcessID, const char **pSubProcessName); +void gpumonGetContextProcessInfo_GM107(struct OBJGPU *pGpu, struct OBJGPUMON *pGpumon, NvU32 arg0, NvU32 *arg1, NvU32 *arg2, const char **arg3); #ifdef __nvoc_objgpumon_h_disabled -static inline void gpumonGetContextProcessInfo(struct OBJGPU *pGpu, struct OBJGPUMON *pGpumon, RM_ENGINE_TYPE rmEngineTypeBegin, RM_ENGINE_TYPE rmEngineTypeEnd, NvU32 context, NvU32 *pProcID, NvU32 *pSubProcessID, const char **pSubProcessName) { +static inline void gpumonGetContextProcessInfo(struct OBJGPU *pGpu, struct OBJGPUMON *pGpumon, NvU32 arg0, NvU32 *arg1, NvU32 *arg2, const char **arg3) { NV_ASSERT_FAILED_PRECOMP("OBJGPUMON was disabled!"); } #else //__nvoc_objgpumon_h_disabled -#define gpumonGetContextProcessInfo(pGpu, pGpumon, rmEngineTypeBegin, rmEngineTypeEnd, context, pProcID, pSubProcessID, pSubProcessName) gpumonGetContextProcessInfo_GM107(pGpu, pGpumon, rmEngineTypeBegin, rmEngineTypeEnd, context, pProcID, pSubProcessID, pSubProcessName) +#define gpumonGetContextProcessInfo(pGpu, pGpumon, arg0, arg1, arg2, arg3) gpumonGetContextProcessInfo_GM107(pGpu, pGpumon, arg0, arg1, arg2, arg3) #endif //__nvoc_objgpumon_h_disabled -#define gpumonGetContextProcessInfo_HAL(pGpu, pGpumon, rmEngineTypeBegin, rmEngineTypeEnd, context, pProcID, pSubProcessID, pSubProcessName) gpumonGetContextProcessInfo(pGpu, pGpumon, rmEngineTypeBegin, rmEngineTypeEnd, context, pProcID, pSubProcessID, pSubProcessName) - -static inline NV_STATUS gpumonReconcileTunableState_DISPATCH(POBJGPU pGpu, struct OBJGPUMON *pEngstate, void *pTunableState) { - return pEngstate->__gpumonReconcileTunableState__(pGpu, pEngstate, pTunableState); -} +#define gpumonGetContextProcessInfo_HAL(pGpu, pGpumon, arg0, arg1, arg2, arg3) gpumonGetContextProcessInfo(pGpu, pGpumon, arg0, arg1, arg2, arg3) static inline NV_STATUS gpumonStateLoad_DISPATCH(POBJGPU pGpu, struct OBJGPUMON *pEngstate, NvU32 arg0) { return pEngstate->__gpumonStateLoad__(pGpu, pEngstate, arg0); @@ -192,30 +175,10 @@ static inline NV_STATUS gpumonStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct return pEngstate->__gpumonStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS gpumonGetTunableState_DISPATCH(POBJGPU pGpu, struct OBJGPUMON *pEngstate, void *pTunableState) { - return pEngstate->__gpumonGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS gpumonCompareTunableState_DISPATCH(POBJGPU pGpu, struct OBJGPUMON *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__gpumonCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void gpumonFreeTunableState_DISPATCH(POBJGPU pGpu, struct OBJGPUMON *pEngstate, void *pTunableState) { - pEngstate->__gpumonFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS gpumonStatePostLoad_DISPATCH(POBJGPU pGpu, struct OBJGPUMON *pEngstate, NvU32 arg0) { return pEngstate->__gpumonStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS gpumonAllocTunableState_DISPATCH(POBJGPU pGpu, struct OBJGPUMON *pEngstate, void **ppTunableState) { - return pEngstate->__gpumonAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS gpumonSetTunableState_DISPATCH(POBJGPU pGpu, struct OBJGPUMON *pEngstate, void *pTunableState) { - return pEngstate->__gpumonSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS gpumonConstructEngine_DISPATCH(POBJGPU pGpu, struct OBJGPUMON *pEngstate, ENGDESCRIPTOR arg0) { return pEngstate->__gpumonConstructEngine__(pGpu, pEngstate, arg0); } diff --git a/src/nvidia/generated/g_objsweng_nvoc.c b/src/nvidia/generated/g_objsweng_nvoc.c index 19b65d935..e63e88e7e 100644 --- a/src/nvidia/generated/g_objsweng_nvoc.c +++ b/src/nvidia/generated/g_objsweng_nvoc.c @@ -70,10 +70,6 @@ static NV_STATUS __nvoc_thunk_OBJSWENG_engstateConstructEngine(struct OBJGPU *pG return swengConstructEngine(pGpu, (struct OBJSWENG *)(((unsigned char *)pSweng) - __nvoc_rtti_OBJSWENG_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_swengReconcileTunableState(POBJGPU pGpu, struct OBJSWENG *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJSWENG_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_swengStateLoad(POBJGPU pGpu, struct OBJSWENG *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJSWENG_OBJENGSTATE.offset), arg0); } @@ -118,30 +114,10 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_swengStatePreInitUnlocked(POBJGPU pGpu return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJSWENG_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_swengGetTunableState(POBJGPU pGpu, struct OBJSWENG *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJSWENG_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_swengCompareTunableState(POBJGPU pGpu, struct OBJSWENG *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJSWENG_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_swengFreeTunableState(POBJGPU pGpu, struct OBJSWENG *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJSWENG_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_swengStatePostLoad(POBJGPU pGpu, struct OBJSWENG *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJSWENG_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_swengAllocTunableState(POBJGPU pGpu, struct OBJSWENG *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJSWENG_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_swengSetTunableState(POBJGPU pGpu, struct OBJSWENG *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJSWENG_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_swengIsPresent(POBJGPU pGpu, struct OBJSWENG *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJSWENG_OBJENGSTATE.offset)); } @@ -183,8 +159,6 @@ static void __nvoc_init_funcTable_OBJSWENG_1(OBJSWENG *pThis) { pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_OBJSWENG_engstateConstructEngine; - pThis->__swengReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_swengReconcileTunableState; - pThis->__swengStateLoad__ = &__nvoc_thunk_OBJENGSTATE_swengStateLoad; pThis->__swengStateUnload__ = &__nvoc_thunk_OBJENGSTATE_swengStateUnload; @@ -207,18 +181,8 @@ static void __nvoc_init_funcTable_OBJSWENG_1(OBJSWENG *pThis) { pThis->__swengStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_swengStatePreInitUnlocked; - pThis->__swengGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_swengGetTunableState; - - pThis->__swengCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_swengCompareTunableState; - - pThis->__swengFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_swengFreeTunableState; - pThis->__swengStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_swengStatePostLoad; - pThis->__swengAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_swengAllocTunableState; - - pThis->__swengSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_swengSetTunableState; - pThis->__swengIsPresent__ = &__nvoc_thunk_OBJENGSTATE_swengIsPresent; } @@ -240,13 +204,16 @@ NV_STATUS __nvoc_objCreate_OBJSWENG(OBJSWENG **ppThis, Dynamic *pParent, NvU32 c Object *pParentObj; OBJSWENG *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJSWENG)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJSWENG), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJSWENG)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJSWENG); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -262,11 +229,17 @@ NV_STATUS __nvoc_objCreate_OBJSWENG(OBJSWENG **ppThis, Dynamic *pParent, NvU32 c if (status != NV_OK) goto __nvoc_objCreate_OBJSWENG_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJSWENG_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJSWENG)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_objsweng_nvoc.h b/src/nvidia/generated/g_objsweng_nvoc.h index 6ba8fc3be..587bba789 100644 --- a/src/nvidia/generated/g_objsweng_nvoc.h +++ b/src/nvidia/generated/g_objsweng_nvoc.h @@ -59,7 +59,6 @@ struct OBJSWENG { struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; struct OBJSWENG *__nvoc_pbase_OBJSWENG; NV_STATUS (*__swengConstructEngine__)(struct OBJGPU *, struct OBJSWENG *, ENGDESCRIPTOR); - NV_STATUS (*__swengReconcileTunableState__)(POBJGPU, struct OBJSWENG *, void *); NV_STATUS (*__swengStateLoad__)(POBJGPU, struct OBJSWENG *, NvU32); NV_STATUS (*__swengStateUnload__)(POBJGPU, struct OBJSWENG *, NvU32); NV_STATUS (*__swengStateInitLocked__)(POBJGPU, struct OBJSWENG *); @@ -71,12 +70,7 @@ struct OBJSWENG { void (*__swengInitMissing__)(POBJGPU, struct OBJSWENG *); NV_STATUS (*__swengStatePreInitLocked__)(POBJGPU, struct OBJSWENG *); NV_STATUS (*__swengStatePreInitUnlocked__)(POBJGPU, struct OBJSWENG *); - NV_STATUS (*__swengGetTunableState__)(POBJGPU, struct OBJSWENG *, void *); - NV_STATUS (*__swengCompareTunableState__)(POBJGPU, struct OBJSWENG *, void *, void *); - void (*__swengFreeTunableState__)(POBJGPU, struct OBJSWENG *, void *); NV_STATUS (*__swengStatePostLoad__)(POBJGPU, struct OBJSWENG *, NvU32); - NV_STATUS (*__swengAllocTunableState__)(POBJGPU, struct OBJSWENG *, void **); - NV_STATUS (*__swengSetTunableState__)(POBJGPU, struct OBJSWENG *, void *); NvBool (*__swengIsPresent__)(POBJGPU, struct OBJSWENG *); }; @@ -111,7 +105,6 @@ NV_STATUS __nvoc_objCreate_OBJSWENG(OBJSWENG**, Dynamic*, NvU32); __nvoc_objCreate_OBJSWENG((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) #define swengConstructEngine(pGpu, pSweng, arg0) swengConstructEngine_DISPATCH(pGpu, pSweng, arg0) -#define swengReconcileTunableState(pGpu, pEngstate, pTunableState) swengReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define swengStateLoad(pGpu, pEngstate, arg0) swengStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define swengStateUnload(pGpu, pEngstate, arg0) swengStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define swengStateInitLocked(pGpu, pEngstate) swengStateInitLocked_DISPATCH(pGpu, pEngstate) @@ -123,12 +116,7 @@ NV_STATUS __nvoc_objCreate_OBJSWENG(OBJSWENG**, Dynamic*, NvU32); #define swengInitMissing(pGpu, pEngstate) swengInitMissing_DISPATCH(pGpu, pEngstate) #define swengStatePreInitLocked(pGpu, pEngstate) swengStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define swengStatePreInitUnlocked(pGpu, pEngstate) swengStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define swengGetTunableState(pGpu, pEngstate, pTunableState) swengGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define swengCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) swengCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define swengFreeTunableState(pGpu, pEngstate, pTunableState) swengFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define swengStatePostLoad(pGpu, pEngstate, arg0) swengStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define swengAllocTunableState(pGpu, pEngstate, ppTunableState) swengAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define swengSetTunableState(pGpu, pEngstate, pTunableState) swengSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define swengIsPresent(pGpu, pEngstate) swengIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS swengConstructEngine_IMPL(struct OBJGPU *pGpu, struct OBJSWENG *pSweng, ENGDESCRIPTOR arg0); @@ -136,10 +124,6 @@ static inline NV_STATUS swengConstructEngine_DISPATCH(struct OBJGPU *pGpu, struc return pSweng->__swengConstructEngine__(pGpu, pSweng, arg0); } -static inline NV_STATUS swengReconcileTunableState_DISPATCH(POBJGPU pGpu, struct OBJSWENG *pEngstate, void *pTunableState) { - return pEngstate->__swengReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS swengStateLoad_DISPATCH(POBJGPU pGpu, struct OBJSWENG *pEngstate, NvU32 arg0) { return pEngstate->__swengStateLoad__(pGpu, pEngstate, arg0); } @@ -184,30 +168,10 @@ static inline NV_STATUS swengStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct return pEngstate->__swengStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS swengGetTunableState_DISPATCH(POBJGPU pGpu, struct OBJSWENG *pEngstate, void *pTunableState) { - return pEngstate->__swengGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS swengCompareTunableState_DISPATCH(POBJGPU pGpu, struct OBJSWENG *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__swengCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void swengFreeTunableState_DISPATCH(POBJGPU pGpu, struct OBJSWENG *pEngstate, void *pTunableState) { - pEngstate->__swengFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS swengStatePostLoad_DISPATCH(POBJGPU pGpu, struct OBJSWENG *pEngstate, NvU32 arg0) { return pEngstate->__swengStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS swengAllocTunableState_DISPATCH(POBJGPU pGpu, struct OBJSWENG *pEngstate, void **ppTunableState) { - return pEngstate->__swengAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS swengSetTunableState_DISPATCH(POBJGPU pGpu, struct OBJSWENG *pEngstate, void *pTunableState) { - return pEngstate->__swengSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool swengIsPresent_DISPATCH(POBJGPU pGpu, struct OBJSWENG *pEngstate) { return pEngstate->__swengIsPresent__(pGpu, pEngstate); } diff --git a/src/nvidia/generated/g_objtmr_nvoc.c b/src/nvidia/generated/g_objtmr_nvoc.c index e197a04eb..833f66011 100644 --- a/src/nvidia/generated/g_objtmr_nvoc.c +++ b/src/nvidia/generated/g_objtmr_nvoc.c @@ -75,7 +75,7 @@ const struct NVOC_CLASS_DEF __nvoc_class_def_OBJTMR = /*pExportInfo=*/ &__nvoc_export_info_OBJTMR }; -static void __nvoc_thunk_OBJTMR_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pTmr, IntrServiceRecord pRecords[163]) { +static void __nvoc_thunk_OBJTMR_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pTmr, IntrServiceRecord pRecords[166]) { tmrRegisterIntrService(pGpu, (struct OBJTMR *)(((unsigned char *)pTmr) - __nvoc_rtti_OBJTMR_IntrService.offset), pRecords); } @@ -111,10 +111,6 @@ static void __nvoc_thunk_OBJTMR_engstateStateDestroy(OBJGPU *pGpu, struct OBJENG tmrStateDestroy(pGpu, (struct OBJTMR *)(((unsigned char *)pTmr) - __nvoc_rtti_OBJTMR_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_tmrReconcileTunableState(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_IntrService_tmrServiceNotificationInterrupt(OBJGPU *pGpu, struct OBJTMR *pIntrService, IntrServiceServiceNotificationInterruptArguments *pParams) { return intrservServiceNotificationInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_OBJTMR_IntrService.offset), pParams); } @@ -143,30 +139,10 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_tmrStatePreInitUnlocked(POBJGPU pGpu, return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_tmrGetTunableState(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_tmrCompareTunableState(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_tmrFreeTunableState(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_tmrStatePostLoad(POBJGPU pGpu, struct OBJTMR *pEngstate, NvU32 arg0) { return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_tmrAllocTunableState(POBJGPU pGpu, struct OBJTMR *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_tmrSetTunableState(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_tmrIsPresent(POBJGPU pGpu, struct OBJTMR *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset)); } @@ -372,8 +348,6 @@ static void __nvoc_init_funcTable_OBJTMR_1(OBJTMR *pThis, RmHalspecOwner *pRmhal pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_OBJTMR_engstateStateDestroy; - pThis->__tmrReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_tmrReconcileTunableState; - pThis->__tmrServiceNotificationInterrupt__ = &__nvoc_thunk_IntrService_tmrServiceNotificationInterrupt; pThis->__tmrStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_tmrStatePreLoad; @@ -388,18 +362,8 @@ static void __nvoc_init_funcTable_OBJTMR_1(OBJTMR *pThis, RmHalspecOwner *pRmhal pThis->__tmrStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_tmrStatePreInitUnlocked; - pThis->__tmrGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_tmrGetTunableState; - - pThis->__tmrCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_tmrCompareTunableState; - - pThis->__tmrFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_tmrFreeTunableState; - pThis->__tmrStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_tmrStatePostLoad; - pThis->__tmrAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_tmrAllocTunableState; - - pThis->__tmrSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_tmrSetTunableState; - pThis->__tmrIsPresent__ = &__nvoc_thunk_OBJENGSTATE_tmrIsPresent; } @@ -425,13 +389,16 @@ NV_STATUS __nvoc_objCreate_OBJTMR(OBJTMR **ppThis, Dynamic *pParent, NvU32 creat OBJTMR *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(OBJTMR)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJTMR), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJTMR)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJTMR); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -451,11 +418,17 @@ NV_STATUS __nvoc_objCreate_OBJTMR(OBJTMR **ppThis, Dynamic *pParent, NvU32 creat if (status != NV_OK) goto __nvoc_objCreate_OBJTMR_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJTMR_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJTMR)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_objtmr_nvoc.h b/src/nvidia/generated/g_objtmr_nvoc.h index 7ebaf7444..2958647ff 100644 --- a/src/nvidia/generated/g_objtmr_nvoc.h +++ b/src/nvidia/generated/g_objtmr_nvoc.h @@ -130,13 +130,14 @@ struct TMR_EVENT_PVT TMR_EVENT super; // Legacy Fields, soon to be obsoleted. - NvBool bLegacy; //__tmrRegisterIntrService__(pGpu, pTmr, pRecords); } @@ -854,10 +844,6 @@ static inline NV_STATUS tmrGetGpuPtimerOffset_DISPATCH(OBJGPU *pGpu, struct OBJT return pTmr->__tmrGetGpuPtimerOffset__(pGpu, pTmr, arg0, arg1); } -static inline NV_STATUS tmrReconcileTunableState_DISPATCH(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunableState) { - return pEngstate->__tmrReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS tmrServiceNotificationInterrupt_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pIntrService, IntrServiceServiceNotificationInterruptArguments *pParams) { return pIntrService->__tmrServiceNotificationInterrupt__(pGpu, pIntrService, pParams); } @@ -886,30 +872,10 @@ static inline NV_STATUS tmrStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct OB return pEngstate->__tmrStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS tmrGetTunableState_DISPATCH(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunableState) { - return pEngstate->__tmrGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS tmrCompareTunableState_DISPATCH(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__tmrCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void tmrFreeTunableState_DISPATCH(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunableState) { - pEngstate->__tmrFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS tmrStatePostLoad_DISPATCH(POBJGPU pGpu, struct OBJTMR *pEngstate, NvU32 arg0) { return pEngstate->__tmrStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS tmrAllocTunableState_DISPATCH(POBJGPU pGpu, struct OBJTMR *pEngstate, void **ppTunableState) { - return pEngstate->__tmrAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS tmrSetTunableState_DISPATCH(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunableState) { - return pEngstate->__tmrSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool tmrIsPresent_DISPATCH(POBJGPU pGpu, struct OBJTMR *pEngstate) { return pEngstate->__tmrIsPresent__(pGpu, pEngstate); } @@ -1104,6 +1070,17 @@ static inline NvBool tmrEventOnList(struct OBJTMR *pTmr, PTMR_EVENT pEvent) { #define tmrEventOnList(pTmr, pEvent) tmrEventOnList_IMPL(pTmr, pEvent) #endif //__nvoc_objtmr_h_disabled +NV_STATUS tmrEventServiceTimer_IMPL(OBJGPU *pGpu, struct OBJTMR *pTmr, PTMR_EVENT pEvent); + +#ifdef __nvoc_objtmr_h_disabled +static inline NV_STATUS tmrEventServiceTimer(OBJGPU *pGpu, struct OBJTMR *pTmr, PTMR_EVENT pEvent) { + NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_objtmr_h_disabled +#define tmrEventServiceTimer(pGpu, pTmr, pEvent) tmrEventServiceTimer_IMPL(pGpu, pTmr, pEvent) +#endif //__nvoc_objtmr_h_disabled + NvBool tmrCallbackOnList_IMPL(struct OBJTMR *pTmr, TIMEPROC_OBSOLETE arg0, void *arg1); #ifdef __nvoc_objtmr_h_disabled diff --git a/src/nvidia/generated/g_os_desc_mem_nvoc.c b/src/nvidia/generated/g_os_desc_mem_nvoc.c index 1f8ef56ba..7ab3b2ee3 100644 --- a/src/nvidia/generated/g_os_desc_mem_nvoc.c +++ b/src/nvidia/generated/g_os_desc_mem_nvoc.c @@ -101,6 +101,46 @@ static NV_STATUS __nvoc_thunk_Memory_osdescCheckMemInterUnmap(struct OsDescMemor return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), bSubdeviceHandleProvided); } +static NvBool __nvoc_thunk_RmResource_osdescShareCallback(struct OsDescMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RsResource_osdescMapTo(struct OsDescMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_osdescGetMapAddrSpace(struct OsDescMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_osdescGetRefCount(struct OsDescMemory *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_osdescAddAdditionalDependants(struct RsClient *pClient, struct OsDescMemory *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_osdescControl_Prologue(struct OsDescMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_Memory_osdescIsGpuMapAllowed(struct OsDescMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), pGpu); +} + +static NV_STATUS __nvoc_thunk_RsResource_osdescUnmapFrom(struct OsDescMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_osdescControl_Epilogue(struct OsDescMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_osdescControlLookup(struct OsDescMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RsResource.offset), pParams, ppEntry); +} + static NV_STATUS __nvoc_thunk_Memory_osdescControl(struct OsDescMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), pCallContext, pParams); } @@ -117,36 +157,12 @@ static NV_STATUS __nvoc_thunk_Memory_osdescGetMemoryMappingDescriptor(struct OsD return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_Memory_osdescGetMapAddrSpace(struct OsDescMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvBool __nvoc_thunk_RmResource_osdescShareCallback(struct OsDescMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); -} - static NV_STATUS __nvoc_thunk_RsResource_osdescControlFilter(struct OsDescMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_osdescAddAdditionalDependants(struct RsClient *pClient, struct OsDescMemory *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_osdescGetRefCount(struct OsDescMemory *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RsResource_osdescMapTo(struct OsDescMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_osdescControl_Prologue(struct OsDescMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RmResource.offset), pCallContext, pParams); -} - -static NvBool __nvoc_thunk_Memory_osdescIsGpuMapAllowed(struct OsDescMemory *pMemory, struct OBJGPU *pGpu) { - return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), pGpu); +static NV_STATUS __nvoc_thunk_RmResource_osdescControlSerialization_Prologue(struct OsDescMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_osdescIsReady(struct OsDescMemory *pMemory, NvBool bCopyConstructorContext) { @@ -165,16 +181,8 @@ static NV_STATUS __nvoc_thunk_Memory_osdescIsDuplicate(struct OsDescMemory *pMem return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), hMemory, pDuplicate); } -static NV_STATUS __nvoc_thunk_RsResource_osdescUnmapFrom(struct OsDescMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RmResource_osdescControl_Epilogue(struct OsDescMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_osdescControlLookup(struct OsDescMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_osdescControlSerialization_Epilogue(struct OsDescMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_osdescMap(struct OsDescMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -229,6 +237,26 @@ static void __nvoc_init_funcTable_OsDescMemory_1(OsDescMemory *pThis) { pThis->__osdescCheckMemInterUnmap__ = &__nvoc_thunk_Memory_osdescCheckMemInterUnmap; + pThis->__osdescShareCallback__ = &__nvoc_thunk_RmResource_osdescShareCallback; + + pThis->__osdescMapTo__ = &__nvoc_thunk_RsResource_osdescMapTo; + + pThis->__osdescGetMapAddrSpace__ = &__nvoc_thunk_Memory_osdescGetMapAddrSpace; + + pThis->__osdescGetRefCount__ = &__nvoc_thunk_RsResource_osdescGetRefCount; + + pThis->__osdescAddAdditionalDependants__ = &__nvoc_thunk_RsResource_osdescAddAdditionalDependants; + + pThis->__osdescControl_Prologue__ = &__nvoc_thunk_RmResource_osdescControl_Prologue; + + pThis->__osdescIsGpuMapAllowed__ = &__nvoc_thunk_Memory_osdescIsGpuMapAllowed; + + pThis->__osdescUnmapFrom__ = &__nvoc_thunk_RsResource_osdescUnmapFrom; + + pThis->__osdescControl_Epilogue__ = &__nvoc_thunk_RmResource_osdescControl_Epilogue; + + pThis->__osdescControlLookup__ = &__nvoc_thunk_RsResource_osdescControlLookup; + pThis->__osdescControl__ = &__nvoc_thunk_Memory_osdescControl; pThis->__osdescUnmap__ = &__nvoc_thunk_Memory_osdescUnmap; @@ -237,21 +265,9 @@ static void __nvoc_init_funcTable_OsDescMemory_1(OsDescMemory *pThis) { pThis->__osdescGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_osdescGetMemoryMappingDescriptor; - pThis->__osdescGetMapAddrSpace__ = &__nvoc_thunk_Memory_osdescGetMapAddrSpace; - - pThis->__osdescShareCallback__ = &__nvoc_thunk_RmResource_osdescShareCallback; - pThis->__osdescControlFilter__ = &__nvoc_thunk_RsResource_osdescControlFilter; - pThis->__osdescAddAdditionalDependants__ = &__nvoc_thunk_RsResource_osdescAddAdditionalDependants; - - pThis->__osdescGetRefCount__ = &__nvoc_thunk_RsResource_osdescGetRefCount; - - pThis->__osdescMapTo__ = &__nvoc_thunk_RsResource_osdescMapTo; - - pThis->__osdescControl_Prologue__ = &__nvoc_thunk_RmResource_osdescControl_Prologue; - - pThis->__osdescIsGpuMapAllowed__ = &__nvoc_thunk_Memory_osdescIsGpuMapAllowed; + pThis->__osdescControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_osdescControlSerialization_Prologue; pThis->__osdescIsReady__ = &__nvoc_thunk_Memory_osdescIsReady; @@ -261,11 +277,7 @@ static void __nvoc_init_funcTable_OsDescMemory_1(OsDescMemory *pThis) { pThis->__osdescIsDuplicate__ = &__nvoc_thunk_Memory_osdescIsDuplicate; - pThis->__osdescUnmapFrom__ = &__nvoc_thunk_RsResource_osdescUnmapFrom; - - pThis->__osdescControl_Epilogue__ = &__nvoc_thunk_RmResource_osdescControl_Epilogue; - - pThis->__osdescControlLookup__ = &__nvoc_thunk_RsResource_osdescControlLookup; + pThis->__osdescControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_osdescControlSerialization_Epilogue; pThis->__osdescMap__ = &__nvoc_thunk_Memory_osdescMap; @@ -293,13 +305,16 @@ NV_STATUS __nvoc_objCreate_OsDescMemory(OsDescMemory **ppThis, Dynamic *pParent, Object *pParentObj; OsDescMemory *pThis; - pThis = portMemAllocNonPaged(sizeof(OsDescMemory)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OsDescMemory), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OsDescMemory)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OsDescMemory); + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -315,11 +330,17 @@ NV_STATUS __nvoc_objCreate_OsDescMemory(OsDescMemory **ppThis, Dynamic *pParent, if (status != NV_OK) goto __nvoc_objCreate_OsDescMemory_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OsDescMemory_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OsDescMemory)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_os_desc_mem_nvoc.h b/src/nvidia/generated/g_os_desc_mem_nvoc.h index 8566e9a7f..163206d01 100644 --- a/src/nvidia/generated/g_os_desc_mem_nvoc.h +++ b/src/nvidia/generated/g_os_desc_mem_nvoc.h @@ -55,25 +55,27 @@ struct OsDescMemory { struct OsDescMemory *__nvoc_pbase_OsDescMemory; NvBool (*__osdescCanCopy__)(struct OsDescMemory *); NV_STATUS (*__osdescCheckMemInterUnmap__)(struct OsDescMemory *, NvBool); + NvBool (*__osdescShareCallback__)(struct OsDescMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__osdescMapTo__)(struct OsDescMemory *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__osdescGetMapAddrSpace__)(struct OsDescMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__osdescGetRefCount__)(struct OsDescMemory *); + void (*__osdescAddAdditionalDependants__)(struct RsClient *, struct OsDescMemory *, RsResourceRef *); + NV_STATUS (*__osdescControl_Prologue__)(struct OsDescMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__osdescIsGpuMapAllowed__)(struct OsDescMemory *, struct OBJGPU *); + NV_STATUS (*__osdescUnmapFrom__)(struct OsDescMemory *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__osdescControl_Epilogue__)(struct OsDescMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__osdescControlLookup__)(struct OsDescMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__osdescControl__)(struct OsDescMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__osdescUnmap__)(struct OsDescMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__osdescGetMemInterMapParams__)(struct OsDescMemory *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__osdescGetMemoryMappingDescriptor__)(struct OsDescMemory *, MEMORY_DESCRIPTOR **); - NV_STATUS (*__osdescGetMapAddrSpace__)(struct OsDescMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvBool (*__osdescShareCallback__)(struct OsDescMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__osdescControlFilter__)(struct OsDescMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__osdescAddAdditionalDependants__)(struct RsClient *, struct OsDescMemory *, RsResourceRef *); - NvU32 (*__osdescGetRefCount__)(struct OsDescMemory *); - NV_STATUS (*__osdescMapTo__)(struct OsDescMemory *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__osdescControl_Prologue__)(struct OsDescMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvBool (*__osdescIsGpuMapAllowed__)(struct OsDescMemory *, struct OBJGPU *); + NV_STATUS (*__osdescControlSerialization_Prologue__)(struct OsDescMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__osdescIsReady__)(struct OsDescMemory *, NvBool); NV_STATUS (*__osdescCheckCopyPermissions__)(struct OsDescMemory *, struct OBJGPU *, NvHandle); void (*__osdescPreDestruct__)(struct OsDescMemory *); NV_STATUS (*__osdescIsDuplicate__)(struct OsDescMemory *, NvHandle, NvBool *); - NV_STATUS (*__osdescUnmapFrom__)(struct OsDescMemory *, RS_RES_UNMAP_FROM_PARAMS *); - void (*__osdescControl_Epilogue__)(struct OsDescMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__osdescControlLookup__)(struct OsDescMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__osdescControlSerialization_Epilogue__)(struct OsDescMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__osdescMap__)(struct OsDescMemory *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__osdescAccessCallback__)(struct OsDescMemory *, struct RsClient *, void *, RsAccessRight); }; @@ -108,25 +110,27 @@ NV_STATUS __nvoc_objCreate_OsDescMemory(OsDescMemory**, Dynamic*, NvU32, CALL_CO #define osdescCanCopy(pOsDescMemory) osdescCanCopy_DISPATCH(pOsDescMemory) #define osdescCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) osdescCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define osdescShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) osdescShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define osdescMapTo(pResource, pParams) osdescMapTo_DISPATCH(pResource, pParams) +#define osdescGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) osdescGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define osdescGetRefCount(pResource) osdescGetRefCount_DISPATCH(pResource) +#define osdescAddAdditionalDependants(pClient, pResource, pReference) osdescAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define osdescControl_Prologue(pResource, pCallContext, pParams) osdescControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define osdescIsGpuMapAllowed(pMemory, pGpu) osdescIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define osdescUnmapFrom(pResource, pParams) osdescUnmapFrom_DISPATCH(pResource, pParams) +#define osdescControl_Epilogue(pResource, pCallContext, pParams) osdescControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define osdescControlLookup(pResource, pParams, ppEntry) osdescControlLookup_DISPATCH(pResource, pParams, ppEntry) #define osdescControl(pMemory, pCallContext, pParams) osdescControl_DISPATCH(pMemory, pCallContext, pParams) #define osdescUnmap(pMemory, pCallContext, pCpuMapping) osdescUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define osdescGetMemInterMapParams(pMemory, pParams) osdescGetMemInterMapParams_DISPATCH(pMemory, pParams) #define osdescGetMemoryMappingDescriptor(pMemory, ppMemDesc) osdescGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define osdescGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) osdescGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) -#define osdescShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) osdescShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define osdescControlFilter(pResource, pCallContext, pParams) osdescControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define osdescAddAdditionalDependants(pClient, pResource, pReference) osdescAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define osdescGetRefCount(pResource) osdescGetRefCount_DISPATCH(pResource) -#define osdescMapTo(pResource, pParams) osdescMapTo_DISPATCH(pResource, pParams) -#define osdescControl_Prologue(pResource, pCallContext, pParams) osdescControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define osdescIsGpuMapAllowed(pMemory, pGpu) osdescIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define osdescControlSerialization_Prologue(pResource, pCallContext, pParams) osdescControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define osdescIsReady(pMemory, bCopyConstructorContext) osdescIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define osdescCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) osdescCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) #define osdescPreDestruct(pResource) osdescPreDestruct_DISPATCH(pResource) #define osdescIsDuplicate(pMemory, hMemory, pDuplicate) osdescIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) -#define osdescUnmapFrom(pResource, pParams) osdescUnmapFrom_DISPATCH(pResource, pParams) -#define osdescControl_Epilogue(pResource, pCallContext, pParams) osdescControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define osdescControlLookup(pResource, pParams, ppEntry) osdescControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define osdescControlSerialization_Epilogue(pResource, pCallContext, pParams) osdescControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define osdescMap(pMemory, pCallContext, pParams, pCpuMapping) osdescMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define osdescAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) osdescAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool osdescCanCopy_IMPL(struct OsDescMemory *pOsDescMemory); @@ -139,6 +143,46 @@ static inline NV_STATUS osdescCheckMemInterUnmap_DISPATCH(struct OsDescMemory *p return pMemory->__osdescCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } +static inline NvBool osdescShareCallback_DISPATCH(struct OsDescMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__osdescShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS osdescMapTo_DISPATCH(struct OsDescMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__osdescMapTo__(pResource, pParams); +} + +static inline NV_STATUS osdescGetMapAddrSpace_DISPATCH(struct OsDescMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__osdescGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 osdescGetRefCount_DISPATCH(struct OsDescMemory *pResource) { + return pResource->__osdescGetRefCount__(pResource); +} + +static inline void osdescAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct OsDescMemory *pResource, RsResourceRef *pReference) { + pResource->__osdescAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS osdescControl_Prologue_DISPATCH(struct OsDescMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__osdescControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool osdescIsGpuMapAllowed_DISPATCH(struct OsDescMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__osdescIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline NV_STATUS osdescUnmapFrom_DISPATCH(struct OsDescMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__osdescUnmapFrom__(pResource, pParams); +} + +static inline void osdescControl_Epilogue_DISPATCH(struct OsDescMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__osdescControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS osdescControlLookup_DISPATCH(struct OsDescMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__osdescControlLookup__(pResource, pParams, ppEntry); +} + static inline NV_STATUS osdescControl_DISPATCH(struct OsDescMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pMemory->__osdescControl__(pMemory, pCallContext, pParams); } @@ -155,36 +199,12 @@ static inline NV_STATUS osdescGetMemoryMappingDescriptor_DISPATCH(struct OsDescM return pMemory->__osdescGetMemoryMappingDescriptor__(pMemory, ppMemDesc); } -static inline NV_STATUS osdescGetMapAddrSpace_DISPATCH(struct OsDescMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pMemory->__osdescGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvBool osdescShareCallback_DISPATCH(struct OsDescMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pResource->__osdescShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); -} - static inline NV_STATUS osdescControlFilter_DISPATCH(struct OsDescMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__osdescControlFilter__(pResource, pCallContext, pParams); } -static inline void osdescAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct OsDescMemory *pResource, RsResourceRef *pReference) { - pResource->__osdescAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 osdescGetRefCount_DISPATCH(struct OsDescMemory *pResource) { - return pResource->__osdescGetRefCount__(pResource); -} - -static inline NV_STATUS osdescMapTo_DISPATCH(struct OsDescMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__osdescMapTo__(pResource, pParams); -} - -static inline NV_STATUS osdescControl_Prologue_DISPATCH(struct OsDescMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__osdescControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NvBool osdescIsGpuMapAllowed_DISPATCH(struct OsDescMemory *pMemory, struct OBJGPU *pGpu) { - return pMemory->__osdescIsGpuMapAllowed__(pMemory, pGpu); +static inline NV_STATUS osdescControlSerialization_Prologue_DISPATCH(struct OsDescMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__osdescControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS osdescIsReady_DISPATCH(struct OsDescMemory *pMemory, NvBool bCopyConstructorContext) { @@ -203,16 +223,8 @@ static inline NV_STATUS osdescIsDuplicate_DISPATCH(struct OsDescMemory *pMemory, return pMemory->__osdescIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline NV_STATUS osdescUnmapFrom_DISPATCH(struct OsDescMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__osdescUnmapFrom__(pResource, pParams); -} - -static inline void osdescControl_Epilogue_DISPATCH(struct OsDescMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__osdescControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS osdescControlLookup_DISPATCH(struct OsDescMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__osdescControlLookup__(pResource, pParams, ppEntry); +static inline void osdescControlSerialization_Epilogue_DISPATCH(struct OsDescMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__osdescControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS osdescMap_DISPATCH(struct OsDescMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_os_nvoc.c b/src/nvidia/generated/g_os_nvoc.c index 5d7c8ebbd..d2eb133b1 100644 --- a/src/nvidia/generated/g_os_nvoc.c +++ b/src/nvidia/generated/g_os_nvoc.c @@ -109,13 +109,16 @@ NV_STATUS __nvoc_objCreate_OBJOS(OBJOS **ppThis, Dynamic *pParent, NvU32 createF Object *pParentObj; OBJOS *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJOS)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJOS), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJOS)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJOS); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -131,11 +134,17 @@ NV_STATUS __nvoc_objCreate_OBJOS(OBJOS **ppThis, Dynamic *pParent, NvU32 createF if (status != NV_OK) goto __nvoc_objCreate_OBJOS_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJOS_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJOS)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_os_nvoc.h b/src/nvidia/generated/g_os_nvoc.h index 13c5ae4ba..abc5ce83b 100644 --- a/src/nvidia/generated/g_os_nvoc.h +++ b/src/nvidia/generated/g_os_nvoc.h @@ -390,14 +390,14 @@ typedef NV_STATUS OSQueueWorkItemWithFlags(OBJGPU *, OSWorkItemFunction, void * typedef NV_STATUS OSQueueSystemWorkItem(OSSystemWorkItemFunction, void *); // MXM ACPI calls -typedef NV_STATUS OSCallACPI_MXMX(OBJGPU *, NvU32, NvU8 *); -typedef NV_STATUS OSCallACPI_DDC(OBJGPU *, NvU32, NvU8*,NvU32*, NvBool); +NV_STATUS osCallACPI_MXMX(OBJGPU *, NvU32, NvU8 *); +NV_STATUS osCallACPI_DDC(OBJGPU *, NvU32, NvU8*,NvU32*, NvBool); typedef NV_STATUS OSCallACPI_BCL(OBJGPU *, NvU32, NvU32 *, NvU16 *); // Display MUX ACPI calls -typedef NV_STATUS OSCallACPI_MXDS(OBJGPU *, NvU32, NvU32 *); -typedef NV_STATUS OSCallACPI_MXDM(OBJGPU *, NvU32, NvU32 *); -typedef NV_STATUS OSCallACPI_MXID(OBJGPU *, NvU32, NvU32 *); +NV_STATUS osCallACPI_MXDS(OBJGPU *, NvU32, NvU32 *); +NV_STATUS osCallACPI_MXDM(OBJGPU *, NvU32, NvU32 *); +NV_STATUS osCallACPI_MXID(OBJGPU *, NvU32, NvU32 *); typedef NV_STATUS OSCallACPI_LRST(OBJGPU *, NvU32, NvU32 *); // Hybrid GPU ACPI calls @@ -407,9 +407,9 @@ typedef NV_STATUS OSCallACPI_NVHG_GPUSTA(OBJGPU *, NvU32 *); typedef NV_STATUS OSCallACPI_NVHG_MXDS(OBJGPU *, NvU32, NvU32 *); typedef NV_STATUS OSCallACPI_NVHG_MXMX(OBJGPU *, NvU32, NvU32 *); typedef NV_STATUS OSCallACPI_NVHG_DOS(OBJGPU *, NvU32, NvU32 *); -typedef NV_STATUS OSCallACPI_NVHG_ROM(OBJGPU *, NvU32 *, NvU32 *); +NV_STATUS osCallACPI_NVHG_ROM(OBJGPU *, NvU32 *, NvU32 *); typedef NV_STATUS OSCallACPI_NVHG_DCS(OBJGPU *, NvU32, NvU32 *); -typedef NV_STATUS OSCallACPI_DOD(OBJGPU *, NvU32 *, NvU32 *); +NV_STATUS osCallACPI_DOD(OBJGPU *, NvU32 *, NvU32 *); // Tegra ACPI calls typedef NV_STATUS OSCallACPI_SUB(OBJGPU *, NvU8 *, NvU32 *); @@ -424,8 +424,8 @@ typedef NV_STATUS OSCallACPI_NBSL(OBJGPU *, NvU32); typedef NV_STATUS OSCallACPI_OPTM_GPUON(OBJGPU *); // Generic ACPI _DSM call -typedef NV_STATUS OSCallACPI_DSM(OBJGPU *pGpu, ACPI_DSM_FUNCTION acpiDSMFunction, - NvU32 NVHGDSMSubfunction, NvU32 *pInOut, NvU16 *size); +NV_STATUS osCallACPI_DSM(OBJGPU *pGpu, ACPI_DSM_FUNCTION acpiDSMFunction, + NvU32 NVHGDSMSubfunction, NvU32 *pInOut, NvU16 *size); // UEFI variable calls typedef NV_STATUS OSGetUefiVariable(OBJGPU *, char *, LPGUID, NvU8 *, NvU32 *, NvU32 *); @@ -631,12 +631,7 @@ struct OBJOS { OSSimEscapeReadBuffer *osSimEscapeReadBuffer; OSRmInitRm *osRmInitRm; OSGetSimulationMode *osGetSimulationMode; - OSCallACPI_MXMX *osCallACPI_MXMX; - OSCallACPI_DDC *osCallACPI_DDC; OSCallACPI_BCL *osCallACPI_BCL; - OSCallACPI_MXDS *osCallACPI_MXDS; - OSCallACPI_MXDM *osCallACPI_MXDM; - OSCallACPI_MXID *osCallACPI_MXID; OSCallACPI_LRST *osCallACPI_LRST; OSCallACPI_NVHG_GPUON *osCallACPI_NVHG_GPUON; OSCallACPI_NVHG_GPUOFF *osCallACPI_NVHG_GPUOFF; @@ -644,13 +639,10 @@ struct OBJOS { OSCallACPI_NVHG_MXDS *osCallACPI_NVHG_MXDS; OSCallACPI_NVHG_MXMX *osCallACPI_NVHG_MXMX; OSCallACPI_NVHG_DOS *osCallACPI_NVHG_DOS; - OSCallACPI_NVHG_ROM *osCallACPI_NVHG_ROM; OSCallACPI_NVHG_DCS *osCallACPI_NVHG_DCS; - OSCallACPI_DOD *osCallACPI_DOD; OSCallACPI_SUB *osCallACPI_SUB; OSCallACPI_ON *osCallACPI_ON; OSCallACPI_OFF *osCallACPI_OFF; - OSCallACPI_DSM *osCallACPI_DSM; OSGetUefiVariable *osGetUefiVariable; OSCheckCallback *osCheckCallback; OSRCCallback *osRCCallback; @@ -840,8 +832,6 @@ NV_STATUS osVgpuVfioWake(void *waitQueue); NV_STATUS osVgpuInjectInterrupt(void *pArg1); NV_STATUS osVgpuRegisterMdev(OS_GPU_INFO *pArg1); NV_STATUS osIsVgpuVfioPresent(void); -NV_STATUS osVgpuAllocVmbusEventDpc(void **ppArg1); -void osVgpuScheduleVmbusEventDpc(void *pArg1, void *pArg2); NV_STATUS rm_is_vgpu_supported_device(OS_GPU_INFO *pNv, NvU32 pmc_boot_1); NV_STATUS osLockPageableDataSection(RM_PAGEABLE_SECTION *pSection); NV_STATUS osUnlockPageableDataSection(RM_PAGEABLE_SECTION *pSection); @@ -1014,6 +1004,9 @@ NV_STATUS osGetAcpiTable(NvU32 tableSignature, NV_STATUS osInitGetAcpiTable(void); +// Read NvGlobal regkey +NV_STATUS osGetNvGlobalRegistryDword(OBJGPU *, const char *pRegParmStr, NvU32 *pData); + NV_STATUS osGetIbmnpuGenregInfo(OS_GPU_INFO *pArg1, NvU64 *pArg2, NvU64 *pArg3); @@ -1109,6 +1102,8 @@ NV_STATUS osGetTegraNumDpAuxInstances(OS_GPU_INFO *pArg1, NvU32 osTegraSocFuseRegRead(NvU32 addr); +NV_STATUS osTegraSocHspSemaphoreAcquire(NvU32 ownerId, NvBool bAcquire, NvU64 timeout); + NV_STATUS osTegraSocDpUphyPllInit(OS_GPU_INFO *pArg1, NvU32, NvU32); NV_STATUS osTegraSocDpUphyPllDeInit(OS_GPU_INFO *pArg1); diff --git a/src/nvidia/generated/g_p2p_api_nvoc.c b/src/nvidia/generated/g_p2p_api_nvoc.c index aef49855f..4f196762d 100644 --- a/src/nvidia/generated/g_p2p_api_nvoc.c +++ b/src/nvidia/generated/g_p2p_api_nvoc.c @@ -116,8 +116,12 @@ static void __nvoc_thunk_RsResource_p2papiAddAdditionalDependants(struct RsClien resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_p2papiUnmap(struct P2PApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RsResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_p2papiUnmapFrom(struct P2PApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_p2papiControlSerialization_Prologue(struct P2PApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_RmResource_p2papiControl_Prologue(struct P2PApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -128,22 +132,26 @@ static NvBool __nvoc_thunk_RsResource_p2papiCanCopy(struct P2PApi *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_p2papiMapTo(struct P2PApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_p2papiUnmap(struct P2PApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RsResource.offset), pCallContext, pCpuMapping); } static void __nvoc_thunk_RsResource_p2papiPreDestruct(struct P2PApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_p2papiUnmapFrom(struct P2PApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_p2papiMapTo(struct P2PApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_RsResource_p2papiIsDuplicate(struct P2PApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_p2papiControlSerialization_Epilogue(struct P2PApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RmResource.offset), pCallContext, pParams); +} + static void __nvoc_thunk_RmResource_p2papiControl_Epilogue(struct P2PApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RmResource.offset), pCallContext, pParams); } @@ -215,20 +223,24 @@ static void __nvoc_init_funcTable_P2PApi_1(P2PApi *pThis) { pThis->__p2papiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_p2papiAddAdditionalDependants; - pThis->__p2papiUnmap__ = &__nvoc_thunk_RsResource_p2papiUnmap; + pThis->__p2papiUnmapFrom__ = &__nvoc_thunk_RsResource_p2papiUnmapFrom; + + pThis->__p2papiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_p2papiControlSerialization_Prologue; pThis->__p2papiControl_Prologue__ = &__nvoc_thunk_RmResource_p2papiControl_Prologue; pThis->__p2papiCanCopy__ = &__nvoc_thunk_RsResource_p2papiCanCopy; - pThis->__p2papiMapTo__ = &__nvoc_thunk_RsResource_p2papiMapTo; + pThis->__p2papiUnmap__ = &__nvoc_thunk_RsResource_p2papiUnmap; pThis->__p2papiPreDestruct__ = &__nvoc_thunk_RsResource_p2papiPreDestruct; - pThis->__p2papiUnmapFrom__ = &__nvoc_thunk_RsResource_p2papiUnmapFrom; + pThis->__p2papiMapTo__ = &__nvoc_thunk_RsResource_p2papiMapTo; pThis->__p2papiIsDuplicate__ = &__nvoc_thunk_RsResource_p2papiIsDuplicate; + pThis->__p2papiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_p2papiControlSerialization_Epilogue; + pThis->__p2papiControl_Epilogue__ = &__nvoc_thunk_RmResource_p2papiControl_Epilogue; pThis->__p2papiControlLookup__ = &__nvoc_thunk_RsResource_p2papiControlLookup; @@ -258,13 +270,16 @@ NV_STATUS __nvoc_objCreate_P2PApi(P2PApi **ppThis, Dynamic *pParent, NvU32 creat Object *pParentObj; P2PApi *pThis; - pThis = portMemAllocNonPaged(sizeof(P2PApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(P2PApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(P2PApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_P2PApi); + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -280,11 +295,17 @@ NV_STATUS __nvoc_objCreate_P2PApi(P2PApi **ppThis, Dynamic *pParent, NvU32 creat if (status != NV_OK) goto __nvoc_objCreate_P2PApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_P2PApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(P2PApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_p2p_api_nvoc.h b/src/nvidia/generated/g_p2p_api_nvoc.h index 68440cc1a..7abf23d77 100644 --- a/src/nvidia/generated/g_p2p_api_nvoc.h +++ b/src/nvidia/generated/g_p2p_api_nvoc.h @@ -73,13 +73,15 @@ struct P2PApi { NvU32 (*__p2papiGetRefCount__)(struct P2PApi *); NV_STATUS (*__p2papiControlFilter__)(struct P2PApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__p2papiAddAdditionalDependants__)(struct RsClient *, struct P2PApi *, RsResourceRef *); - NV_STATUS (*__p2papiUnmap__)(struct P2PApi *, struct CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__p2papiUnmapFrom__)(struct P2PApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__p2papiControlSerialization_Prologue__)(struct P2PApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__p2papiControl_Prologue__)(struct P2PApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__p2papiCanCopy__)(struct P2PApi *); - NV_STATUS (*__p2papiMapTo__)(struct P2PApi *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__p2papiUnmap__)(struct P2PApi *, struct CALL_CONTEXT *, RsCpuMapping *); void (*__p2papiPreDestruct__)(struct P2PApi *); - NV_STATUS (*__p2papiUnmapFrom__)(struct P2PApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__p2papiMapTo__)(struct P2PApi *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__p2papiIsDuplicate__)(struct P2PApi *, NvHandle, NvBool *); + void (*__p2papiControlSerialization_Epilogue__)(struct P2PApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__p2papiControl_Epilogue__)(struct P2PApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__p2papiControlLookup__)(struct P2PApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__p2papiMap__)(struct P2PApi *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -129,13 +131,15 @@ NV_STATUS __nvoc_objCreate_P2PApi(P2PApi**, Dynamic*, NvU32, struct CALL_CONTEXT #define p2papiGetRefCount(pResource) p2papiGetRefCount_DISPATCH(pResource) #define p2papiControlFilter(pResource, pCallContext, pParams) p2papiControlFilter_DISPATCH(pResource, pCallContext, pParams) #define p2papiAddAdditionalDependants(pClient, pResource, pReference) p2papiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define p2papiUnmap(pResource, pCallContext, pCpuMapping) p2papiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define p2papiUnmapFrom(pResource, pParams) p2papiUnmapFrom_DISPATCH(pResource, pParams) +#define p2papiControlSerialization_Prologue(pResource, pCallContext, pParams) p2papiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define p2papiControl_Prologue(pResource, pCallContext, pParams) p2papiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define p2papiCanCopy(pResource) p2papiCanCopy_DISPATCH(pResource) -#define p2papiMapTo(pResource, pParams) p2papiMapTo_DISPATCH(pResource, pParams) +#define p2papiUnmap(pResource, pCallContext, pCpuMapping) p2papiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define p2papiPreDestruct(pResource) p2papiPreDestruct_DISPATCH(pResource) -#define p2papiUnmapFrom(pResource, pParams) p2papiUnmapFrom_DISPATCH(pResource, pParams) +#define p2papiMapTo(pResource, pParams) p2papiMapTo_DISPATCH(pResource, pParams) #define p2papiIsDuplicate(pResource, hMemory, pDuplicate) p2papiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define p2papiControlSerialization_Epilogue(pResource, pCallContext, pParams) p2papiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define p2papiControl_Epilogue(pResource, pCallContext, pParams) p2papiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define p2papiControlLookup(pResource, pParams, ppEntry) p2papiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define p2papiMap(pResource, pCallContext, pParams, pCpuMapping) p2papiMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -172,8 +176,12 @@ static inline void p2papiAddAdditionalDependants_DISPATCH(struct RsClient *pClie pResource->__p2papiAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS p2papiUnmap_DISPATCH(struct P2PApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pResource->__p2papiUnmap__(pResource, pCallContext, pCpuMapping); +static inline NV_STATUS p2papiUnmapFrom_DISPATCH(struct P2PApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__p2papiUnmapFrom__(pResource, pParams); +} + +static inline NV_STATUS p2papiControlSerialization_Prologue_DISPATCH(struct P2PApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__p2papiControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS p2papiControl_Prologue_DISPATCH(struct P2PApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -184,22 +192,26 @@ static inline NvBool p2papiCanCopy_DISPATCH(struct P2PApi *pResource) { return pResource->__p2papiCanCopy__(pResource); } -static inline NV_STATUS p2papiMapTo_DISPATCH(struct P2PApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__p2papiMapTo__(pResource, pParams); +static inline NV_STATUS p2papiUnmap_DISPATCH(struct P2PApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__p2papiUnmap__(pResource, pCallContext, pCpuMapping); } static inline void p2papiPreDestruct_DISPATCH(struct P2PApi *pResource) { pResource->__p2papiPreDestruct__(pResource); } -static inline NV_STATUS p2papiUnmapFrom_DISPATCH(struct P2PApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__p2papiUnmapFrom__(pResource, pParams); +static inline NV_STATUS p2papiMapTo_DISPATCH(struct P2PApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__p2papiMapTo__(pResource, pParams); } static inline NV_STATUS p2papiIsDuplicate_DISPATCH(struct P2PApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__p2papiIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void p2papiControlSerialization_Epilogue_DISPATCH(struct P2PApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__p2papiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline void p2papiControl_Epilogue_DISPATCH(struct P2PApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__p2papiControl_Epilogue__(pResource, pCallContext, pParams); } diff --git a/src/nvidia/generated/g_phys_mem_nvoc.c b/src/nvidia/generated/g_phys_mem_nvoc.c index cc7315c5f..dc561b2e7 100644 --- a/src/nvidia/generated/g_phys_mem_nvoc.c +++ b/src/nvidia/generated/g_phys_mem_nvoc.c @@ -101,6 +101,46 @@ static NV_STATUS __nvoc_thunk_Memory_physmemCheckMemInterUnmap(struct PhysicalMe return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), bSubdeviceHandleProvided); } +static NvBool __nvoc_thunk_RmResource_physmemShareCallback(struct PhysicalMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RsResource_physmemMapTo(struct PhysicalMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_physmemGetMapAddrSpace(struct PhysicalMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_physmemGetRefCount(struct PhysicalMemory *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_physmemAddAdditionalDependants(struct RsClient *pClient, struct PhysicalMemory *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_physmemControl_Prologue(struct PhysicalMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_Memory_physmemIsGpuMapAllowed(struct PhysicalMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), pGpu); +} + +static NV_STATUS __nvoc_thunk_RsResource_physmemUnmapFrom(struct PhysicalMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_physmemControl_Epilogue(struct PhysicalMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_physmemControlLookup(struct PhysicalMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RsResource.offset), pParams, ppEntry); +} + static NV_STATUS __nvoc_thunk_Memory_physmemControl(struct PhysicalMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), pCallContext, pParams); } @@ -117,36 +157,12 @@ static NV_STATUS __nvoc_thunk_Memory_physmemGetMemoryMappingDescriptor(struct Ph return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_Memory_physmemGetMapAddrSpace(struct PhysicalMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvBool __nvoc_thunk_RmResource_physmemShareCallback(struct PhysicalMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); -} - static NV_STATUS __nvoc_thunk_RsResource_physmemControlFilter(struct PhysicalMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_physmemAddAdditionalDependants(struct RsClient *pClient, struct PhysicalMemory *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_physmemGetRefCount(struct PhysicalMemory *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RsResource_physmemMapTo(struct PhysicalMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_physmemControl_Prologue(struct PhysicalMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RmResource.offset), pCallContext, pParams); -} - -static NvBool __nvoc_thunk_Memory_physmemIsGpuMapAllowed(struct PhysicalMemory *pMemory, struct OBJGPU *pGpu) { - return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), pGpu); +static NV_STATUS __nvoc_thunk_RmResource_physmemControlSerialization_Prologue(struct PhysicalMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_physmemIsReady(struct PhysicalMemory *pMemory, NvBool bCopyConstructorContext) { @@ -165,16 +181,8 @@ static NV_STATUS __nvoc_thunk_Memory_physmemIsDuplicate(struct PhysicalMemory *p return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), hMemory, pDuplicate); } -static NV_STATUS __nvoc_thunk_RsResource_physmemUnmapFrom(struct PhysicalMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RmResource_physmemControl_Epilogue(struct PhysicalMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_physmemControlLookup(struct PhysicalMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_physmemControlSerialization_Epilogue(struct PhysicalMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_physmemMap(struct PhysicalMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -229,6 +237,26 @@ static void __nvoc_init_funcTable_PhysicalMemory_1(PhysicalMemory *pThis) { pThis->__physmemCheckMemInterUnmap__ = &__nvoc_thunk_Memory_physmemCheckMemInterUnmap; + pThis->__physmemShareCallback__ = &__nvoc_thunk_RmResource_physmemShareCallback; + + pThis->__physmemMapTo__ = &__nvoc_thunk_RsResource_physmemMapTo; + + pThis->__physmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_physmemGetMapAddrSpace; + + pThis->__physmemGetRefCount__ = &__nvoc_thunk_RsResource_physmemGetRefCount; + + pThis->__physmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_physmemAddAdditionalDependants; + + pThis->__physmemControl_Prologue__ = &__nvoc_thunk_RmResource_physmemControl_Prologue; + + pThis->__physmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_physmemIsGpuMapAllowed; + + pThis->__physmemUnmapFrom__ = &__nvoc_thunk_RsResource_physmemUnmapFrom; + + pThis->__physmemControl_Epilogue__ = &__nvoc_thunk_RmResource_physmemControl_Epilogue; + + pThis->__physmemControlLookup__ = &__nvoc_thunk_RsResource_physmemControlLookup; + pThis->__physmemControl__ = &__nvoc_thunk_Memory_physmemControl; pThis->__physmemUnmap__ = &__nvoc_thunk_Memory_physmemUnmap; @@ -237,21 +265,9 @@ static void __nvoc_init_funcTable_PhysicalMemory_1(PhysicalMemory *pThis) { pThis->__physmemGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_physmemGetMemoryMappingDescriptor; - pThis->__physmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_physmemGetMapAddrSpace; - - pThis->__physmemShareCallback__ = &__nvoc_thunk_RmResource_physmemShareCallback; - pThis->__physmemControlFilter__ = &__nvoc_thunk_RsResource_physmemControlFilter; - pThis->__physmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_physmemAddAdditionalDependants; - - pThis->__physmemGetRefCount__ = &__nvoc_thunk_RsResource_physmemGetRefCount; - - pThis->__physmemMapTo__ = &__nvoc_thunk_RsResource_physmemMapTo; - - pThis->__physmemControl_Prologue__ = &__nvoc_thunk_RmResource_physmemControl_Prologue; - - pThis->__physmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_physmemIsGpuMapAllowed; + pThis->__physmemControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_physmemControlSerialization_Prologue; pThis->__physmemIsReady__ = &__nvoc_thunk_Memory_physmemIsReady; @@ -261,11 +277,7 @@ static void __nvoc_init_funcTable_PhysicalMemory_1(PhysicalMemory *pThis) { pThis->__physmemIsDuplicate__ = &__nvoc_thunk_Memory_physmemIsDuplicate; - pThis->__physmemUnmapFrom__ = &__nvoc_thunk_RsResource_physmemUnmapFrom; - - pThis->__physmemControl_Epilogue__ = &__nvoc_thunk_RmResource_physmemControl_Epilogue; - - pThis->__physmemControlLookup__ = &__nvoc_thunk_RsResource_physmemControlLookup; + pThis->__physmemControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_physmemControlSerialization_Epilogue; pThis->__physmemMap__ = &__nvoc_thunk_Memory_physmemMap; @@ -293,13 +305,16 @@ NV_STATUS __nvoc_objCreate_PhysicalMemory(PhysicalMemory **ppThis, Dynamic *pPar Object *pParentObj; PhysicalMemory *pThis; - pThis = portMemAllocNonPaged(sizeof(PhysicalMemory)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(PhysicalMemory), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(PhysicalMemory)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_PhysicalMemory); + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -315,11 +330,17 @@ NV_STATUS __nvoc_objCreate_PhysicalMemory(PhysicalMemory **ppThis, Dynamic *pPar if (status != NV_OK) goto __nvoc_objCreate_PhysicalMemory_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_PhysicalMemory_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(PhysicalMemory)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_phys_mem_nvoc.h b/src/nvidia/generated/g_phys_mem_nvoc.h index 5f9160460..c4b463a8f 100644 --- a/src/nvidia/generated/g_phys_mem_nvoc.h +++ b/src/nvidia/generated/g_phys_mem_nvoc.h @@ -57,25 +57,27 @@ struct PhysicalMemory { struct PhysicalMemory *__nvoc_pbase_PhysicalMemory; NvBool (*__physmemCanCopy__)(struct PhysicalMemory *); NV_STATUS (*__physmemCheckMemInterUnmap__)(struct PhysicalMemory *, NvBool); + NvBool (*__physmemShareCallback__)(struct PhysicalMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__physmemMapTo__)(struct PhysicalMemory *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__physmemGetMapAddrSpace__)(struct PhysicalMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__physmemGetRefCount__)(struct PhysicalMemory *); + void (*__physmemAddAdditionalDependants__)(struct RsClient *, struct PhysicalMemory *, RsResourceRef *); + NV_STATUS (*__physmemControl_Prologue__)(struct PhysicalMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__physmemIsGpuMapAllowed__)(struct PhysicalMemory *, struct OBJGPU *); + NV_STATUS (*__physmemUnmapFrom__)(struct PhysicalMemory *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__physmemControl_Epilogue__)(struct PhysicalMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__physmemControlLookup__)(struct PhysicalMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__physmemControl__)(struct PhysicalMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__physmemUnmap__)(struct PhysicalMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__physmemGetMemInterMapParams__)(struct PhysicalMemory *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__physmemGetMemoryMappingDescriptor__)(struct PhysicalMemory *, MEMORY_DESCRIPTOR **); - NV_STATUS (*__physmemGetMapAddrSpace__)(struct PhysicalMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvBool (*__physmemShareCallback__)(struct PhysicalMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__physmemControlFilter__)(struct PhysicalMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__physmemAddAdditionalDependants__)(struct RsClient *, struct PhysicalMemory *, RsResourceRef *); - NvU32 (*__physmemGetRefCount__)(struct PhysicalMemory *); - NV_STATUS (*__physmemMapTo__)(struct PhysicalMemory *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__physmemControl_Prologue__)(struct PhysicalMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvBool (*__physmemIsGpuMapAllowed__)(struct PhysicalMemory *, struct OBJGPU *); + NV_STATUS (*__physmemControlSerialization_Prologue__)(struct PhysicalMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__physmemIsReady__)(struct PhysicalMemory *, NvBool); NV_STATUS (*__physmemCheckCopyPermissions__)(struct PhysicalMemory *, struct OBJGPU *, NvHandle); void (*__physmemPreDestruct__)(struct PhysicalMemory *); NV_STATUS (*__physmemIsDuplicate__)(struct PhysicalMemory *, NvHandle, NvBool *); - NV_STATUS (*__physmemUnmapFrom__)(struct PhysicalMemory *, RS_RES_UNMAP_FROM_PARAMS *); - void (*__physmemControl_Epilogue__)(struct PhysicalMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__physmemControlLookup__)(struct PhysicalMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__physmemControlSerialization_Epilogue__)(struct PhysicalMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__physmemMap__)(struct PhysicalMemory *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__physmemAccessCallback__)(struct PhysicalMemory *, struct RsClient *, void *, RsAccessRight); }; @@ -110,25 +112,27 @@ NV_STATUS __nvoc_objCreate_PhysicalMemory(PhysicalMemory**, Dynamic*, NvU32, CAL #define physmemCanCopy(pPhysicalMemory) physmemCanCopy_DISPATCH(pPhysicalMemory) #define physmemCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) physmemCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define physmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) physmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define physmemMapTo(pResource, pParams) physmemMapTo_DISPATCH(pResource, pParams) +#define physmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) physmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define physmemGetRefCount(pResource) physmemGetRefCount_DISPATCH(pResource) +#define physmemAddAdditionalDependants(pClient, pResource, pReference) physmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define physmemControl_Prologue(pResource, pCallContext, pParams) physmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define physmemIsGpuMapAllowed(pMemory, pGpu) physmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define physmemUnmapFrom(pResource, pParams) physmemUnmapFrom_DISPATCH(pResource, pParams) +#define physmemControl_Epilogue(pResource, pCallContext, pParams) physmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define physmemControlLookup(pResource, pParams, ppEntry) physmemControlLookup_DISPATCH(pResource, pParams, ppEntry) #define physmemControl(pMemory, pCallContext, pParams) physmemControl_DISPATCH(pMemory, pCallContext, pParams) #define physmemUnmap(pMemory, pCallContext, pCpuMapping) physmemUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define physmemGetMemInterMapParams(pMemory, pParams) physmemGetMemInterMapParams_DISPATCH(pMemory, pParams) #define physmemGetMemoryMappingDescriptor(pMemory, ppMemDesc) physmemGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define physmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) physmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) -#define physmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) physmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define physmemControlFilter(pResource, pCallContext, pParams) physmemControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define physmemAddAdditionalDependants(pClient, pResource, pReference) physmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define physmemGetRefCount(pResource) physmemGetRefCount_DISPATCH(pResource) -#define physmemMapTo(pResource, pParams) physmemMapTo_DISPATCH(pResource, pParams) -#define physmemControl_Prologue(pResource, pCallContext, pParams) physmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define physmemIsGpuMapAllowed(pMemory, pGpu) physmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define physmemControlSerialization_Prologue(pResource, pCallContext, pParams) physmemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define physmemIsReady(pMemory, bCopyConstructorContext) physmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define physmemCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) physmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) #define physmemPreDestruct(pResource) physmemPreDestruct_DISPATCH(pResource) #define physmemIsDuplicate(pMemory, hMemory, pDuplicate) physmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) -#define physmemUnmapFrom(pResource, pParams) physmemUnmapFrom_DISPATCH(pResource, pParams) -#define physmemControl_Epilogue(pResource, pCallContext, pParams) physmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define physmemControlLookup(pResource, pParams, ppEntry) physmemControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define physmemControlSerialization_Epilogue(pResource, pCallContext, pParams) physmemControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define physmemMap(pMemory, pCallContext, pParams, pCpuMapping) physmemMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define physmemAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) physmemAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool physmemCanCopy_IMPL(struct PhysicalMemory *pPhysicalMemory); @@ -141,6 +145,46 @@ static inline NV_STATUS physmemCheckMemInterUnmap_DISPATCH(struct PhysicalMemory return pMemory->__physmemCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } +static inline NvBool physmemShareCallback_DISPATCH(struct PhysicalMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__physmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS physmemMapTo_DISPATCH(struct PhysicalMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__physmemMapTo__(pResource, pParams); +} + +static inline NV_STATUS physmemGetMapAddrSpace_DISPATCH(struct PhysicalMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__physmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 physmemGetRefCount_DISPATCH(struct PhysicalMemory *pResource) { + return pResource->__physmemGetRefCount__(pResource); +} + +static inline void physmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct PhysicalMemory *pResource, RsResourceRef *pReference) { + pResource->__physmemAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS physmemControl_Prologue_DISPATCH(struct PhysicalMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__physmemControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool physmemIsGpuMapAllowed_DISPATCH(struct PhysicalMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__physmemIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline NV_STATUS physmemUnmapFrom_DISPATCH(struct PhysicalMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__physmemUnmapFrom__(pResource, pParams); +} + +static inline void physmemControl_Epilogue_DISPATCH(struct PhysicalMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__physmemControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS physmemControlLookup_DISPATCH(struct PhysicalMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__physmemControlLookup__(pResource, pParams, ppEntry); +} + static inline NV_STATUS physmemControl_DISPATCH(struct PhysicalMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pMemory->__physmemControl__(pMemory, pCallContext, pParams); } @@ -157,36 +201,12 @@ static inline NV_STATUS physmemGetMemoryMappingDescriptor_DISPATCH(struct Physic return pMemory->__physmemGetMemoryMappingDescriptor__(pMemory, ppMemDesc); } -static inline NV_STATUS physmemGetMapAddrSpace_DISPATCH(struct PhysicalMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pMemory->__physmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvBool physmemShareCallback_DISPATCH(struct PhysicalMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pResource->__physmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); -} - static inline NV_STATUS physmemControlFilter_DISPATCH(struct PhysicalMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__physmemControlFilter__(pResource, pCallContext, pParams); } -static inline void physmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct PhysicalMemory *pResource, RsResourceRef *pReference) { - pResource->__physmemAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 physmemGetRefCount_DISPATCH(struct PhysicalMemory *pResource) { - return pResource->__physmemGetRefCount__(pResource); -} - -static inline NV_STATUS physmemMapTo_DISPATCH(struct PhysicalMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__physmemMapTo__(pResource, pParams); -} - -static inline NV_STATUS physmemControl_Prologue_DISPATCH(struct PhysicalMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__physmemControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NvBool physmemIsGpuMapAllowed_DISPATCH(struct PhysicalMemory *pMemory, struct OBJGPU *pGpu) { - return pMemory->__physmemIsGpuMapAllowed__(pMemory, pGpu); +static inline NV_STATUS physmemControlSerialization_Prologue_DISPATCH(struct PhysicalMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__physmemControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS physmemIsReady_DISPATCH(struct PhysicalMemory *pMemory, NvBool bCopyConstructorContext) { @@ -205,16 +225,8 @@ static inline NV_STATUS physmemIsDuplicate_DISPATCH(struct PhysicalMemory *pMemo return pMemory->__physmemIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline NV_STATUS physmemUnmapFrom_DISPATCH(struct PhysicalMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__physmemUnmapFrom__(pResource, pParams); -} - -static inline void physmemControl_Epilogue_DISPATCH(struct PhysicalMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__physmemControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS physmemControlLookup_DISPATCH(struct PhysicalMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__physmemControlLookup__(pResource, pParams, ppEntry); +static inline void physmemControlSerialization_Epilogue_DISPATCH(struct PhysicalMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__physmemControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS physmemMap_DISPATCH(struct PhysicalMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_platform_nvoc.c b/src/nvidia/generated/g_platform_nvoc.c index 92ce3539c..c3409d224 100644 --- a/src/nvidia/generated/g_platform_nvoc.c +++ b/src/nvidia/generated/g_platform_nvoc.c @@ -115,13 +115,16 @@ NV_STATUS __nvoc_objCreate_OBJPFM(OBJPFM **ppThis, Dynamic *pParent, NvU32 creat Object *pParentObj; OBJPFM *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJPFM)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJPFM), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJPFM)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJPFM); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -137,11 +140,17 @@ NV_STATUS __nvoc_objCreate_OBJPFM(OBJPFM **ppThis, Dynamic *pParent, NvU32 creat if (status != NV_OK) goto __nvoc_objCreate_OBJPFM_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJPFM_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJPFM)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_platform_request_handler_nvoc.h b/src/nvidia/generated/g_platform_request_handler_nvoc.h index 13b9ce919..76f77a91d 100644 --- a/src/nvidia/generated/g_platform_request_handler_nvoc.h +++ b/src/nvidia/generated/g_platform_request_handler_nvoc.h @@ -75,7 +75,7 @@ extern "C" { #define PFM_REQ_HNDLR_CTGP_SENSOR NV0000_CTRL_SYSTEM_PARAM_CTGP #define PFM_REQ_HNDLR_PPMD_SENSOR NV0000_CTRL_SYSTEM_PARAM_PPMD #define PFM_REQ_HNDLR_PSHAREPARAMS_COUNT (9U) -#define PFM_REQ_HNDLR_CURR_BASE (2) +#define PFM_REQ_HNDLR_CURR_BASE (2U) #define PFM_REQ_HNDLR_CURR_VALUE(s) (PFM_REQ_HNDLR_CURR_BASE + ((s)%PFM_REQ_HNDLR_PSHAREPARAMS_COUNT)) #define PFM_REQ_HNDLR_LIMIT_BASE (PFM_REQ_HNDLR_CURR_BASE + PFM_REQ_HNDLR_PSHAREPARAMS_COUNT) #define PFM_REQ_HNDLR_LIMIT(s) (PFM_REQ_HNDLR_LIMIT_BASE + ((s)%PFM_REQ_HNDLR_PSHAREPARAMS_COUNT)) diff --git a/src/nvidia/generated/g_prereq_tracker_nvoc.c b/src/nvidia/generated/g_prereq_tracker_nvoc.c index ee126ac7f..aa4435b19 100644 --- a/src/nvidia/generated/g_prereq_tracker_nvoc.c +++ b/src/nvidia/generated/g_prereq_tracker_nvoc.c @@ -114,13 +114,16 @@ NV_STATUS __nvoc_objCreate_PrereqTracker(PrereqTracker **ppThis, Dynamic *pParen Object *pParentObj; PrereqTracker *pThis; - pThis = portMemAllocNonPaged(sizeof(PrereqTracker)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(PrereqTracker), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(PrereqTracker)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_PrereqTracker); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -136,11 +139,17 @@ NV_STATUS __nvoc_objCreate_PrereqTracker(PrereqTracker **ppThis, Dynamic *pParen if (status != NV_OK) goto __nvoc_objCreate_PrereqTracker_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_PrereqTracker_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(PrereqTracker)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_profiler_v1_nvoc.c b/src/nvidia/generated/g_profiler_v1_nvoc.c index 4083f2b48..93c18a0d0 100644 --- a/src/nvidia/generated/g_profiler_v1_nvoc.c +++ b/src/nvidia/generated/g_profiler_v1_nvoc.c @@ -101,6 +101,54 @@ static NvBool __nvoc_thunk_GpuResource_profilerShareCallback(struct Profiler *pG return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Profiler_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } +static NV_STATUS __nvoc_thunk_RmResource_profilerCheckMemInterUnmap(struct Profiler *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Profiler_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_profilerMapTo(struct Profiler *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_profilerGetMapAddrSpace(struct Profiler *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Profiler_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_profilerGetRefCount(struct Profiler *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_profilerAddAdditionalDependants(struct RsClient *pClient, struct Profiler *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_profilerControl_Prologue(struct Profiler *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_profilerGetRegBaseOffsetAndSize(struct Profiler *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Profiler_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_profilerInternalControlForward(struct Profiler *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Profiler_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_profilerUnmapFrom(struct Profiler *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_profilerControl_Epilogue(struct Profiler *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_profilerControlLookup(struct Profiler *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset), pParams, ppEntry); +} + +static NvHandle __nvoc_thunk_GpuResource_profilerGetInternalObjectHandle(struct Profiler *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Profiler_GpuResource.offset)); +} + static NV_STATUS __nvoc_thunk_GpuResource_profilerUnmap(struct Profiler *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Profiler_GpuResource.offset), pCallContext, pCpuMapping); } @@ -113,68 +161,28 @@ static NV_STATUS __nvoc_thunk_RmResource_profilerGetMemoryMappingDescriptor(stru return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Profiler_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_GpuResource_profilerGetMapAddrSpace(struct Profiler *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Profiler_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvHandle __nvoc_thunk_GpuResource_profilerGetInternalObjectHandle(struct Profiler *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Profiler_GpuResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_profilerControlFilter(struct Profiler *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_profilerAddAdditionalDependants(struct RsClient *pClient, struct Profiler *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_profilerGetRefCount(struct Profiler *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RmResource_profilerCheckMemInterUnmap(struct Profiler *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Profiler_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_profilerMapTo(struct Profiler *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_profilerControl_Prologue(struct Profiler *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_GpuResource_profilerGetRegBaseOffsetAndSize(struct Profiler *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Profiler_GpuResource.offset), pGpu, pOffset, pSize); +static NV_STATUS __nvoc_thunk_RmResource_profilerControlSerialization_Prologue(struct Profiler *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_profilerCanCopy(struct Profiler *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_profilerInternalControlForward(struct Profiler *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Profiler_GpuResource.offset), command, pParams, size); -} - static void __nvoc_thunk_RsResource_profilerPreDestruct(struct Profiler *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_profilerUnmapFrom(struct Profiler *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_profilerIsDuplicate(struct Profiler *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset), hMemory, pDuplicate); } -static void __nvoc_thunk_RmResource_profilerControl_Epilogue(struct Profiler *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_profilerControlLookup(struct Profiler *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_profilerControlSerialization_Epilogue(struct Profiler *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_profilerMap(struct Profiler *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -344,43 +352,47 @@ static void __nvoc_init_funcTable_Profiler_1(Profiler *pThis, RmHalspecOwner *pR pThis->__profilerShareCallback__ = &__nvoc_thunk_GpuResource_profilerShareCallback; + pThis->__profilerCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_profilerCheckMemInterUnmap; + + pThis->__profilerMapTo__ = &__nvoc_thunk_RsResource_profilerMapTo; + + pThis->__profilerGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_profilerGetMapAddrSpace; + + pThis->__profilerGetRefCount__ = &__nvoc_thunk_RsResource_profilerGetRefCount; + + pThis->__profilerAddAdditionalDependants__ = &__nvoc_thunk_RsResource_profilerAddAdditionalDependants; + + pThis->__profilerControl_Prologue__ = &__nvoc_thunk_RmResource_profilerControl_Prologue; + + pThis->__profilerGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_profilerGetRegBaseOffsetAndSize; + + pThis->__profilerInternalControlForward__ = &__nvoc_thunk_GpuResource_profilerInternalControlForward; + + pThis->__profilerUnmapFrom__ = &__nvoc_thunk_RsResource_profilerUnmapFrom; + + pThis->__profilerControl_Epilogue__ = &__nvoc_thunk_RmResource_profilerControl_Epilogue; + + pThis->__profilerControlLookup__ = &__nvoc_thunk_RsResource_profilerControlLookup; + + pThis->__profilerGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_profilerGetInternalObjectHandle; + pThis->__profilerUnmap__ = &__nvoc_thunk_GpuResource_profilerUnmap; pThis->__profilerGetMemInterMapParams__ = &__nvoc_thunk_RmResource_profilerGetMemInterMapParams; pThis->__profilerGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_profilerGetMemoryMappingDescriptor; - pThis->__profilerGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_profilerGetMapAddrSpace; - - pThis->__profilerGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_profilerGetInternalObjectHandle; - pThis->__profilerControlFilter__ = &__nvoc_thunk_RsResource_profilerControlFilter; - pThis->__profilerAddAdditionalDependants__ = &__nvoc_thunk_RsResource_profilerAddAdditionalDependants; - - pThis->__profilerGetRefCount__ = &__nvoc_thunk_RsResource_profilerGetRefCount; - - pThis->__profilerCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_profilerCheckMemInterUnmap; - - pThis->__profilerMapTo__ = &__nvoc_thunk_RsResource_profilerMapTo; - - pThis->__profilerControl_Prologue__ = &__nvoc_thunk_RmResource_profilerControl_Prologue; - - pThis->__profilerGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_profilerGetRegBaseOffsetAndSize; + pThis->__profilerControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_profilerControlSerialization_Prologue; pThis->__profilerCanCopy__ = &__nvoc_thunk_RsResource_profilerCanCopy; - pThis->__profilerInternalControlForward__ = &__nvoc_thunk_GpuResource_profilerInternalControlForward; - pThis->__profilerPreDestruct__ = &__nvoc_thunk_RsResource_profilerPreDestruct; - pThis->__profilerUnmapFrom__ = &__nvoc_thunk_RsResource_profilerUnmapFrom; - pThis->__profilerIsDuplicate__ = &__nvoc_thunk_RsResource_profilerIsDuplicate; - pThis->__profilerControl_Epilogue__ = &__nvoc_thunk_RmResource_profilerControl_Epilogue; - - pThis->__profilerControlLookup__ = &__nvoc_thunk_RsResource_profilerControlLookup; + pThis->__profilerControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_profilerControlSerialization_Epilogue; pThis->__profilerMap__ = &__nvoc_thunk_GpuResource_profilerMap; @@ -409,13 +421,16 @@ NV_STATUS __nvoc_objCreate_Profiler(Profiler **ppThis, Dynamic *pParent, NvU32 c Profiler *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(Profiler)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Profiler), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(Profiler)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Profiler); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -435,11 +450,17 @@ NV_STATUS __nvoc_objCreate_Profiler(Profiler **ppThis, Dynamic *pParent, NvU32 c if (status != NV_OK) goto __nvoc_objCreate_Profiler_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_Profiler_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(Profiler)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_profiler_v1_nvoc.h b/src/nvidia/generated/g_profiler_v1_nvoc.h index 643ce01b9..b2220bd37 100644 --- a/src/nvidia/generated/g_profiler_v1_nvoc.h +++ b/src/nvidia/generated/g_profiler_v1_nvoc.h @@ -63,25 +63,27 @@ struct Profiler { NV_STATUS (*__profilerCtrlCmdProfilerRequestCgControls__)(struct Profiler *, NV90CC_CTRL_POWER_REQUEST_FEATURES_PARAMS *); NV_STATUS (*__profilerCtrlCmdProfilerReleaseCgControls__)(struct Profiler *, NV90CC_CTRL_POWER_RELEASE_FEATURES_PARAMS *); NvBool (*__profilerShareCallback__)(struct Profiler *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__profilerCheckMemInterUnmap__)(struct Profiler *, NvBool); + NV_STATUS (*__profilerMapTo__)(struct Profiler *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__profilerGetMapAddrSpace__)(struct Profiler *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__profilerGetRefCount__)(struct Profiler *); + void (*__profilerAddAdditionalDependants__)(struct RsClient *, struct Profiler *, RsResourceRef *); + NV_STATUS (*__profilerControl_Prologue__)(struct Profiler *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__profilerGetRegBaseOffsetAndSize__)(struct Profiler *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__profilerInternalControlForward__)(struct Profiler *, NvU32, void *, NvU32); + NV_STATUS (*__profilerUnmapFrom__)(struct Profiler *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__profilerControl_Epilogue__)(struct Profiler *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__profilerControlLookup__)(struct Profiler *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__profilerGetInternalObjectHandle__)(struct Profiler *); NV_STATUS (*__profilerUnmap__)(struct Profiler *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__profilerGetMemInterMapParams__)(struct Profiler *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__profilerGetMemoryMappingDescriptor__)(struct Profiler *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__profilerGetMapAddrSpace__)(struct Profiler *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__profilerGetInternalObjectHandle__)(struct Profiler *); NV_STATUS (*__profilerControlFilter__)(struct Profiler *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__profilerAddAdditionalDependants__)(struct RsClient *, struct Profiler *, RsResourceRef *); - NvU32 (*__profilerGetRefCount__)(struct Profiler *); - NV_STATUS (*__profilerCheckMemInterUnmap__)(struct Profiler *, NvBool); - NV_STATUS (*__profilerMapTo__)(struct Profiler *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__profilerControl_Prologue__)(struct Profiler *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__profilerGetRegBaseOffsetAndSize__)(struct Profiler *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__profilerControlSerialization_Prologue__)(struct Profiler *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__profilerCanCopy__)(struct Profiler *); - NV_STATUS (*__profilerInternalControlForward__)(struct Profiler *, NvU32, void *, NvU32); void (*__profilerPreDestruct__)(struct Profiler *); - NV_STATUS (*__profilerUnmapFrom__)(struct Profiler *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__profilerIsDuplicate__)(struct Profiler *, NvHandle, NvBool *); - void (*__profilerControl_Epilogue__)(struct Profiler *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__profilerControlLookup__)(struct Profiler *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__profilerControlSerialization_Epilogue__)(struct Profiler *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__profilerMap__)(struct Profiler *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__profilerAccessCallback__)(struct Profiler *, struct RsClient *, void *, RsAccessRight); }; @@ -121,25 +123,27 @@ NV_STATUS __nvoc_objCreate_Profiler(Profiler**, Dynamic*, NvU32, struct CALL_CON #define profilerCtrlCmdProfilerRequestCgControls(pProfiler, pParams) profilerCtrlCmdProfilerRequestCgControls_DISPATCH(pProfiler, pParams) #define profilerCtrlCmdProfilerReleaseCgControls(pProfiler, pParams) profilerCtrlCmdProfilerReleaseCgControls_DISPATCH(pProfiler, pParams) #define profilerShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) profilerShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define profilerCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) profilerCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define profilerMapTo(pResource, pParams) profilerMapTo_DISPATCH(pResource, pParams) +#define profilerGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) profilerGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define profilerGetRefCount(pResource) profilerGetRefCount_DISPATCH(pResource) +#define profilerAddAdditionalDependants(pClient, pResource, pReference) profilerAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define profilerControl_Prologue(pResource, pCallContext, pParams) profilerControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define profilerGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) profilerGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define profilerInternalControlForward(pGpuResource, command, pParams, size) profilerInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define profilerUnmapFrom(pResource, pParams) profilerUnmapFrom_DISPATCH(pResource, pParams) +#define profilerControl_Epilogue(pResource, pCallContext, pParams) profilerControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define profilerControlLookup(pResource, pParams, ppEntry) profilerControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define profilerGetInternalObjectHandle(pGpuResource) profilerGetInternalObjectHandle_DISPATCH(pGpuResource) #define profilerUnmap(pGpuResource, pCallContext, pCpuMapping) profilerUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define profilerGetMemInterMapParams(pRmResource, pParams) profilerGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define profilerGetMemoryMappingDescriptor(pRmResource, ppMemDesc) profilerGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define profilerGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) profilerGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define profilerGetInternalObjectHandle(pGpuResource) profilerGetInternalObjectHandle_DISPATCH(pGpuResource) #define profilerControlFilter(pResource, pCallContext, pParams) profilerControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define profilerAddAdditionalDependants(pClient, pResource, pReference) profilerAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define profilerGetRefCount(pResource) profilerGetRefCount_DISPATCH(pResource) -#define profilerCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) profilerCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define profilerMapTo(pResource, pParams) profilerMapTo_DISPATCH(pResource, pParams) -#define profilerControl_Prologue(pResource, pCallContext, pParams) profilerControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define profilerGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) profilerGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define profilerControlSerialization_Prologue(pResource, pCallContext, pParams) profilerControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define profilerCanCopy(pResource) profilerCanCopy_DISPATCH(pResource) -#define profilerInternalControlForward(pGpuResource, command, pParams, size) profilerInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define profilerPreDestruct(pResource) profilerPreDestruct_DISPATCH(pResource) -#define profilerUnmapFrom(pResource, pParams) profilerUnmapFrom_DISPATCH(pResource, pParams) #define profilerIsDuplicate(pResource, hMemory, pDuplicate) profilerIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) -#define profilerControl_Epilogue(pResource, pCallContext, pParams) profilerControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define profilerControlLookup(pResource, pParams, ppEntry) profilerControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define profilerControlSerialization_Epilogue(pResource, pCallContext, pParams) profilerControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define profilerMap(pGpuResource, pCallContext, pParams, pCpuMapping) profilerMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define profilerAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) profilerAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool profilerIsProfilingPermitted_IMPL(struct Profiler *pProfiler); @@ -234,6 +238,54 @@ static inline NvBool profilerShareCallback_DISPATCH(struct Profiler *pGpuResourc return pGpuResource->__profilerShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } +static inline NV_STATUS profilerCheckMemInterUnmap_DISPATCH(struct Profiler *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__profilerCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS profilerMapTo_DISPATCH(struct Profiler *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__profilerMapTo__(pResource, pParams); +} + +static inline NV_STATUS profilerGetMapAddrSpace_DISPATCH(struct Profiler *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__profilerGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 profilerGetRefCount_DISPATCH(struct Profiler *pResource) { + return pResource->__profilerGetRefCount__(pResource); +} + +static inline void profilerAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct Profiler *pResource, RsResourceRef *pReference) { + pResource->__profilerAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS profilerControl_Prologue_DISPATCH(struct Profiler *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__profilerControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS profilerGetRegBaseOffsetAndSize_DISPATCH(struct Profiler *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__profilerGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS profilerInternalControlForward_DISPATCH(struct Profiler *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__profilerInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS profilerUnmapFrom_DISPATCH(struct Profiler *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__profilerUnmapFrom__(pResource, pParams); +} + +static inline void profilerControl_Epilogue_DISPATCH(struct Profiler *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__profilerControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS profilerControlLookup_DISPATCH(struct Profiler *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__profilerControlLookup__(pResource, pParams, ppEntry); +} + +static inline NvHandle profilerGetInternalObjectHandle_DISPATCH(struct Profiler *pGpuResource) { + return pGpuResource->__profilerGetInternalObjectHandle__(pGpuResource); +} + static inline NV_STATUS profilerUnmap_DISPATCH(struct Profiler *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { return pGpuResource->__profilerUnmap__(pGpuResource, pCallContext, pCpuMapping); } @@ -246,68 +298,28 @@ static inline NV_STATUS profilerGetMemoryMappingDescriptor_DISPATCH(struct Profi return pRmResource->__profilerGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS profilerGetMapAddrSpace_DISPATCH(struct Profiler *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__profilerGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvHandle profilerGetInternalObjectHandle_DISPATCH(struct Profiler *pGpuResource) { - return pGpuResource->__profilerGetInternalObjectHandle__(pGpuResource); -} - static inline NV_STATUS profilerControlFilter_DISPATCH(struct Profiler *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__profilerControlFilter__(pResource, pCallContext, pParams); } -static inline void profilerAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct Profiler *pResource, RsResourceRef *pReference) { - pResource->__profilerAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 profilerGetRefCount_DISPATCH(struct Profiler *pResource) { - return pResource->__profilerGetRefCount__(pResource); -} - -static inline NV_STATUS profilerCheckMemInterUnmap_DISPATCH(struct Profiler *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__profilerCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS profilerMapTo_DISPATCH(struct Profiler *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__profilerMapTo__(pResource, pParams); -} - -static inline NV_STATUS profilerControl_Prologue_DISPATCH(struct Profiler *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__profilerControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS profilerGetRegBaseOffsetAndSize_DISPATCH(struct Profiler *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__profilerGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +static inline NV_STATUS profilerControlSerialization_Prologue_DISPATCH(struct Profiler *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__profilerControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool profilerCanCopy_DISPATCH(struct Profiler *pResource) { return pResource->__profilerCanCopy__(pResource); } -static inline NV_STATUS profilerInternalControlForward_DISPATCH(struct Profiler *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__profilerInternalControlForward__(pGpuResource, command, pParams, size); -} - static inline void profilerPreDestruct_DISPATCH(struct Profiler *pResource) { pResource->__profilerPreDestruct__(pResource); } -static inline NV_STATUS profilerUnmapFrom_DISPATCH(struct Profiler *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__profilerUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS profilerIsDuplicate_DISPATCH(struct Profiler *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__profilerIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline void profilerControl_Epilogue_DISPATCH(struct Profiler *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__profilerControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS profilerControlLookup_DISPATCH(struct Profiler *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__profilerControlLookup__(pResource, pParams, ppEntry); +static inline void profilerControlSerialization_Epilogue_DISPATCH(struct Profiler *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__profilerControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS profilerMap_DISPATCH(struct Profiler *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_profiler_v2_nvoc.c b/src/nvidia/generated/g_profiler_v2_nvoc.c index d772b1d31..65f74fd56 100644 --- a/src/nvidia/generated/g_profiler_v2_nvoc.c +++ b/src/nvidia/generated/g_profiler_v2_nvoc.c @@ -97,6 +97,54 @@ static NvBool __nvoc_thunk_GpuResource_profilerBaseShareCallback(struct Profiler return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerBase_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } +static NV_STATUS __nvoc_thunk_RmResource_profilerBaseCheckMemInterUnmap(struct ProfilerBase *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ProfilerBase_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_profilerBaseMapTo(struct ProfilerBase *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_profilerBaseGetMapAddrSpace(struct ProfilerBase *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerBase_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_profilerBaseGetRefCount(struct ProfilerBase *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_profilerBaseAddAdditionalDependants(struct RsClient *pClient, struct ProfilerBase *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_profilerBaseControl_Prologue(struct ProfilerBase *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_profilerBaseGetRegBaseOffsetAndSize(struct ProfilerBase *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerBase_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_profilerBaseInternalControlForward(struct ProfilerBase *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerBase_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_profilerBaseUnmapFrom(struct ProfilerBase *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_profilerBaseControl_Epilogue(struct ProfilerBase *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_profilerBaseControlLookup(struct ProfilerBase *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset), pParams, ppEntry); +} + +static NvHandle __nvoc_thunk_GpuResource_profilerBaseGetInternalObjectHandle(struct ProfilerBase *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerBase_GpuResource.offset)); +} + static NV_STATUS __nvoc_thunk_GpuResource_profilerBaseControl(struct ProfilerBase *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerBase_GpuResource.offset), pCallContext, pParams); } @@ -113,68 +161,28 @@ static NV_STATUS __nvoc_thunk_RmResource_profilerBaseGetMemoryMappingDescriptor( return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ProfilerBase_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_GpuResource_profilerBaseGetMapAddrSpace(struct ProfilerBase *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerBase_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvHandle __nvoc_thunk_GpuResource_profilerBaseGetInternalObjectHandle(struct ProfilerBase *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerBase_GpuResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_profilerBaseControlFilter(struct ProfilerBase *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_profilerBaseAddAdditionalDependants(struct RsClient *pClient, struct ProfilerBase *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_profilerBaseGetRefCount(struct ProfilerBase *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RmResource_profilerBaseCheckMemInterUnmap(struct ProfilerBase *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ProfilerBase_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_profilerBaseMapTo(struct ProfilerBase *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_profilerBaseControl_Prologue(struct ProfilerBase *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_GpuResource_profilerBaseGetRegBaseOffsetAndSize(struct ProfilerBase *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerBase_GpuResource.offset), pGpu, pOffset, pSize); +static NV_STATUS __nvoc_thunk_RmResource_profilerBaseControlSerialization_Prologue(struct ProfilerBase *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_profilerBaseCanCopy(struct ProfilerBase *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_profilerBaseInternalControlForward(struct ProfilerBase *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerBase_GpuResource.offset), command, pParams, size); -} - static void __nvoc_thunk_RsResource_profilerBasePreDestruct(struct ProfilerBase *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_profilerBaseUnmapFrom(struct ProfilerBase *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_profilerBaseIsDuplicate(struct ProfilerBase *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset), hMemory, pDuplicate); } -static void __nvoc_thunk_RmResource_profilerBaseControl_Epilogue(struct ProfilerBase *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_profilerBaseControlLookup(struct ProfilerBase *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_profilerBaseControlSerialization_Epilogue(struct ProfilerBase *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_profilerBaseMap(struct ProfilerBase *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -192,12 +200,12 @@ static NvBool __nvoc_thunk_RmResource_profilerBaseAccessCallback(struct Profiler static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_ProfilerBase[] = { { /* [0] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdReserveHwpmLegacy_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, /*accessRight=*/0x0u, /*methodId=*/ 0xb0cc0101u, /*paramSize=*/ sizeof(NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS), @@ -267,12 +275,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler #endif }, { /* [5] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdFreePmaStream_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, /*accessRight=*/0x0u, /*methodId=*/ 0xb0cc0106u, /*paramSize=*/ sizeof(NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS), @@ -282,12 +290,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler #endif }, { /* [6] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdBindPmResources_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, /*accessRight=*/0x0u, /*methodId=*/ 0xb0cc0107u, /*paramSize=*/ 0, @@ -297,12 +305,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler #endif }, { /* [7] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdUnbindPmResources_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, /*accessRight=*/0x0u, /*methodId=*/ 0xb0cc0108u, /*paramSize=*/ 0, @@ -417,21 +425,36 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler #endif }, { /* [15] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdInternalAllocPmaStream_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) - /*flags=*/ 0x610u, + /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdReserveHes_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, /*accessRight=*/0x0u, - /*methodId=*/ 0xb0cc0200u, - /*paramSize=*/ sizeof(NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS), + /*methodId=*/ 0xb0cc0113u, + /*paramSize=*/ sizeof(NVB0CC_CTRL_RESERVE_HES_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_ProfilerBase.classInfo), #if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "profilerBaseCtrlCmdInternalAllocPmaStream" + /*func=*/ "profilerBaseCtrlCmdReserveHes" #endif }, { /* [16] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdReleaseHes_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xb0cc0114u, + /*paramSize=*/ sizeof(NVB0CC_CTRL_RELEASE_HES_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ProfilerBase.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "profilerBaseCtrlCmdReleaseHes" +#endif + }, + { /* [17] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -444,6 +467,96 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler /*pClassInfo=*/ &(__nvoc_class_def_ProfilerBase.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "profilerBaseCtrlCmdInternalPermissionsInit" +#endif + }, + { /* [18] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdInternalAllocPmaStream_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) + /*flags=*/ 0x610u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xb0cc0204u, + /*paramSize=*/ sizeof(NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ProfilerBase.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "profilerBaseCtrlCmdInternalAllocPmaStream" +#endif + }, + { /* [19] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdInternalFreePmaStream_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) + /*flags=*/ 0x610u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xb0cc0206u, + /*paramSize=*/ sizeof(NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ProfilerBase.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "profilerBaseCtrlCmdInternalFreePmaStream" +#endif + }, + { /* [20] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdInternalGetMaxPmas_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) + /*flags=*/ 0x610u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xb0cc0207u, + /*paramSize=*/ sizeof(NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ProfilerBase.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "profilerBaseCtrlCmdInternalGetMaxPmas" +#endif + }, + { /* [21] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdInternalBindPmResources_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) + /*flags=*/ 0x610u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xb0cc0208u, + /*paramSize=*/ 0, + /*pClassInfo=*/ &(__nvoc_class_def_ProfilerBase.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "profilerBaseCtrlCmdInternalBindPmResources" +#endif + }, + { /* [22] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdInternalUnbindPmResources_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) + /*flags=*/ 0x610u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xb0cc0209u, + /*paramSize=*/ 0, + /*pClassInfo=*/ &(__nvoc_class_def_ProfilerBase.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "profilerBaseCtrlCmdInternalUnbindPmResources" +#endif + }, + { /* [23] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdInternalReserveHwpmLegacy_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) + /*flags=*/ 0x610u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xb0cc020au, + /*paramSize=*/ sizeof(NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ProfilerBase.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "profilerBaseCtrlCmdInternalReserveHwpmLegacy" #endif }, @@ -451,7 +564,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler const struct NVOC_EXPORT_INFO __nvoc_export_info_ProfilerBase = { - /*numEntries=*/ 17, + /*numEntries=*/ 24, /*pExportEntries=*/ __nvoc_exported_method_def_ProfilerBase }; @@ -498,10 +611,14 @@ static void __nvoc_init_funcTable_ProfilerBase_1(ProfilerBase *pThis, RmHalspecO PORT_UNREFERENCED_VARIABLE(rmVariantHal); PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__profilerBaseCtrlCmdReserveHwpmLegacy__ = &profilerBaseCtrlCmdReserveHwpmLegacy_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) + pThis->__profilerBaseCtrlCmdInternalReserveHwpmLegacy__ = &profilerBaseCtrlCmdInternalReserveHwpmLegacy_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__profilerBaseCtrlCmdReleaseHwpmLegacy__ = &profilerBaseCtrlCmdReleaseHwpmLegacy_IMPL; #endif @@ -518,18 +635,34 @@ static void __nvoc_init_funcTable_ProfilerBase_1(ProfilerBase *pThis, RmHalspecO pThis->__profilerBaseCtrlCmdAllocPmaStream__ = &profilerBaseCtrlCmdAllocPmaStream_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__profilerBaseCtrlCmdFreePmaStream__ = &profilerBaseCtrlCmdFreePmaStream_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) + pThis->__profilerBaseCtrlCmdInternalFreePmaStream__ = &profilerBaseCtrlCmdInternalFreePmaStream_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) + pThis->__profilerBaseCtrlCmdInternalGetMaxPmas__ = &profilerBaseCtrlCmdInternalGetMaxPmas_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__profilerBaseCtrlCmdBindPmResources__ = &profilerBaseCtrlCmdBindPmResources_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__profilerBaseCtrlCmdUnbindPmResources__ = &profilerBaseCtrlCmdUnbindPmResources_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) + pThis->__profilerBaseCtrlCmdInternalBindPmResources__ = &profilerBaseCtrlCmdInternalBindPmResources_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) + pThis->__profilerBaseCtrlCmdInternalUnbindPmResources__ = &profilerBaseCtrlCmdInternalUnbindPmResources_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__profilerBaseCtrlCmdPmaStreamUpdateGetPut__ = &profilerBaseCtrlCmdPmaStreamUpdateGetPut_IMPL; #endif @@ -566,8 +699,40 @@ static void __nvoc_init_funcTable_ProfilerBase_1(ProfilerBase *pThis, RmHalspecO pThis->__profilerBaseCtrlCmdSetHsCredits__ = &profilerBaseCtrlCmdSetHsCredits_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__profilerBaseCtrlCmdReserveHes__ = &profilerBaseCtrlCmdReserveHes_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__profilerBaseCtrlCmdReleaseHes__ = &profilerBaseCtrlCmdReleaseHes_IMPL; +#endif + pThis->__profilerBaseShareCallback__ = &__nvoc_thunk_GpuResource_profilerBaseShareCallback; + pThis->__profilerBaseCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_profilerBaseCheckMemInterUnmap; + + pThis->__profilerBaseMapTo__ = &__nvoc_thunk_RsResource_profilerBaseMapTo; + + pThis->__profilerBaseGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_profilerBaseGetMapAddrSpace; + + pThis->__profilerBaseGetRefCount__ = &__nvoc_thunk_RsResource_profilerBaseGetRefCount; + + pThis->__profilerBaseAddAdditionalDependants__ = &__nvoc_thunk_RsResource_profilerBaseAddAdditionalDependants; + + pThis->__profilerBaseControl_Prologue__ = &__nvoc_thunk_RmResource_profilerBaseControl_Prologue; + + pThis->__profilerBaseGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_profilerBaseGetRegBaseOffsetAndSize; + + pThis->__profilerBaseInternalControlForward__ = &__nvoc_thunk_GpuResource_profilerBaseInternalControlForward; + + pThis->__profilerBaseUnmapFrom__ = &__nvoc_thunk_RsResource_profilerBaseUnmapFrom; + + pThis->__profilerBaseControl_Epilogue__ = &__nvoc_thunk_RmResource_profilerBaseControl_Epilogue; + + pThis->__profilerBaseControlLookup__ = &__nvoc_thunk_RsResource_profilerBaseControlLookup; + + pThis->__profilerBaseGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_profilerBaseGetInternalObjectHandle; + pThis->__profilerBaseControl__ = &__nvoc_thunk_GpuResource_profilerBaseControl; pThis->__profilerBaseUnmap__ = &__nvoc_thunk_GpuResource_profilerBaseUnmap; @@ -576,37 +741,17 @@ static void __nvoc_init_funcTable_ProfilerBase_1(ProfilerBase *pThis, RmHalspecO pThis->__profilerBaseGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_profilerBaseGetMemoryMappingDescriptor; - pThis->__profilerBaseGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_profilerBaseGetMapAddrSpace; - - pThis->__profilerBaseGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_profilerBaseGetInternalObjectHandle; - pThis->__profilerBaseControlFilter__ = &__nvoc_thunk_RsResource_profilerBaseControlFilter; - pThis->__profilerBaseAddAdditionalDependants__ = &__nvoc_thunk_RsResource_profilerBaseAddAdditionalDependants; - - pThis->__profilerBaseGetRefCount__ = &__nvoc_thunk_RsResource_profilerBaseGetRefCount; - - pThis->__profilerBaseCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_profilerBaseCheckMemInterUnmap; - - pThis->__profilerBaseMapTo__ = &__nvoc_thunk_RsResource_profilerBaseMapTo; - - pThis->__profilerBaseControl_Prologue__ = &__nvoc_thunk_RmResource_profilerBaseControl_Prologue; - - pThis->__profilerBaseGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_profilerBaseGetRegBaseOffsetAndSize; + pThis->__profilerBaseControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_profilerBaseControlSerialization_Prologue; pThis->__profilerBaseCanCopy__ = &__nvoc_thunk_RsResource_profilerBaseCanCopy; - pThis->__profilerBaseInternalControlForward__ = &__nvoc_thunk_GpuResource_profilerBaseInternalControlForward; - pThis->__profilerBasePreDestruct__ = &__nvoc_thunk_RsResource_profilerBasePreDestruct; - pThis->__profilerBaseUnmapFrom__ = &__nvoc_thunk_RsResource_profilerBaseUnmapFrom; - pThis->__profilerBaseIsDuplicate__ = &__nvoc_thunk_RsResource_profilerBaseIsDuplicate; - pThis->__profilerBaseControl_Epilogue__ = &__nvoc_thunk_RmResource_profilerBaseControl_Epilogue; - - pThis->__profilerBaseControlLookup__ = &__nvoc_thunk_RsResource_profilerBaseControlLookup; + pThis->__profilerBaseControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_profilerBaseControlSerialization_Epilogue; pThis->__profilerBaseMap__ = &__nvoc_thunk_GpuResource_profilerBaseMap; @@ -635,13 +780,16 @@ NV_STATUS __nvoc_objCreate_ProfilerBase(ProfilerBase **ppThis, Dynamic *pParent, ProfilerBase *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(ProfilerBase)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ProfilerBase), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(ProfilerBase)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ProfilerBase); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -661,11 +809,17 @@ NV_STATUS __nvoc_objCreate_ProfilerBase(ProfilerBase **ppThis, Dynamic *pParent, if (status != NV_OK) goto __nvoc_objCreate_ProfilerBase_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_ProfilerBase_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(ProfilerBase)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -778,6 +932,54 @@ static NvBool __nvoc_thunk_GpuResource_profilerDevShareCallback(struct ProfilerD return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerDev_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } +static NV_STATUS __nvoc_thunk_RmResource_profilerDevCheckMemInterUnmap(struct ProfilerDev *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ProfilerDev_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_profilerDevMapTo(struct ProfilerDev *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_profilerDevGetMapAddrSpace(struct ProfilerDev *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerDev_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_profilerDevGetRefCount(struct ProfilerDev *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_profilerDevAddAdditionalDependants(struct RsClient *pClient, struct ProfilerDev *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_profilerDevControl_Prologue(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_profilerDevGetRegBaseOffsetAndSize(struct ProfilerDev *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerDev_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_profilerDevInternalControlForward(struct ProfilerDev *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerDev_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_profilerDevUnmapFrom(struct ProfilerDev *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_profilerDevControl_Epilogue(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_profilerDevControlLookup(struct ProfilerDev *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset), pParams, ppEntry); +} + +static NvHandle __nvoc_thunk_GpuResource_profilerDevGetInternalObjectHandle(struct ProfilerDev *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerDev_GpuResource.offset)); +} + static NV_STATUS __nvoc_thunk_GpuResource_profilerDevControl(struct ProfilerDev *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerDev_GpuResource.offset), pCallContext, pParams); } @@ -794,68 +996,28 @@ static NV_STATUS __nvoc_thunk_RmResource_profilerDevGetMemoryMappingDescriptor(s return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ProfilerDev_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_GpuResource_profilerDevGetMapAddrSpace(struct ProfilerDev *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerDev_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvHandle __nvoc_thunk_GpuResource_profilerDevGetInternalObjectHandle(struct ProfilerDev *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerDev_GpuResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_profilerDevControlFilter(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_profilerDevAddAdditionalDependants(struct RsClient *pClient, struct ProfilerDev *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_profilerDevGetRefCount(struct ProfilerDev *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RmResource_profilerDevCheckMemInterUnmap(struct ProfilerDev *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ProfilerDev_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_profilerDevMapTo(struct ProfilerDev *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_profilerDevControl_Prologue(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_GpuResource_profilerDevGetRegBaseOffsetAndSize(struct ProfilerDev *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerDev_GpuResource.offset), pGpu, pOffset, pSize); +static NV_STATUS __nvoc_thunk_RmResource_profilerDevControlSerialization_Prologue(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_profilerDevCanCopy(struct ProfilerDev *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_profilerDevInternalControlForward(struct ProfilerDev *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerDev_GpuResource.offset), command, pParams, size); -} - static void __nvoc_thunk_RsResource_profilerDevPreDestruct(struct ProfilerDev *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_profilerDevUnmapFrom(struct ProfilerDev *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_profilerDevIsDuplicate(struct ProfilerDev *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset), hMemory, pDuplicate); } -static void __nvoc_thunk_RmResource_profilerDevControl_Epilogue(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_profilerDevControlLookup(struct ProfilerDev *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_profilerDevControlSerialization_Epilogue(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_profilerDevMap(struct ProfilerDev *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -917,6 +1079,30 @@ static void __nvoc_init_funcTable_ProfilerDev_1(ProfilerDev *pThis, RmHalspecOwn pThis->__profilerDevShareCallback__ = &__nvoc_thunk_GpuResource_profilerDevShareCallback; + pThis->__profilerDevCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_profilerDevCheckMemInterUnmap; + + pThis->__profilerDevMapTo__ = &__nvoc_thunk_RsResource_profilerDevMapTo; + + pThis->__profilerDevGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_profilerDevGetMapAddrSpace; + + pThis->__profilerDevGetRefCount__ = &__nvoc_thunk_RsResource_profilerDevGetRefCount; + + pThis->__profilerDevAddAdditionalDependants__ = &__nvoc_thunk_RsResource_profilerDevAddAdditionalDependants; + + pThis->__profilerDevControl_Prologue__ = &__nvoc_thunk_RmResource_profilerDevControl_Prologue; + + pThis->__profilerDevGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_profilerDevGetRegBaseOffsetAndSize; + + pThis->__profilerDevInternalControlForward__ = &__nvoc_thunk_GpuResource_profilerDevInternalControlForward; + + pThis->__profilerDevUnmapFrom__ = &__nvoc_thunk_RsResource_profilerDevUnmapFrom; + + pThis->__profilerDevControl_Epilogue__ = &__nvoc_thunk_RmResource_profilerDevControl_Epilogue; + + pThis->__profilerDevControlLookup__ = &__nvoc_thunk_RsResource_profilerDevControlLookup; + + pThis->__profilerDevGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_profilerDevGetInternalObjectHandle; + pThis->__profilerDevControl__ = &__nvoc_thunk_GpuResource_profilerDevControl; pThis->__profilerDevUnmap__ = &__nvoc_thunk_GpuResource_profilerDevUnmap; @@ -925,37 +1111,17 @@ static void __nvoc_init_funcTable_ProfilerDev_1(ProfilerDev *pThis, RmHalspecOwn pThis->__profilerDevGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_profilerDevGetMemoryMappingDescriptor; - pThis->__profilerDevGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_profilerDevGetMapAddrSpace; - - pThis->__profilerDevGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_profilerDevGetInternalObjectHandle; - pThis->__profilerDevControlFilter__ = &__nvoc_thunk_RsResource_profilerDevControlFilter; - pThis->__profilerDevAddAdditionalDependants__ = &__nvoc_thunk_RsResource_profilerDevAddAdditionalDependants; - - pThis->__profilerDevGetRefCount__ = &__nvoc_thunk_RsResource_profilerDevGetRefCount; - - pThis->__profilerDevCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_profilerDevCheckMemInterUnmap; - - pThis->__profilerDevMapTo__ = &__nvoc_thunk_RsResource_profilerDevMapTo; - - pThis->__profilerDevControl_Prologue__ = &__nvoc_thunk_RmResource_profilerDevControl_Prologue; - - pThis->__profilerDevGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_profilerDevGetRegBaseOffsetAndSize; + pThis->__profilerDevControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_profilerDevControlSerialization_Prologue; pThis->__profilerDevCanCopy__ = &__nvoc_thunk_RsResource_profilerDevCanCopy; - pThis->__profilerDevInternalControlForward__ = &__nvoc_thunk_GpuResource_profilerDevInternalControlForward; - pThis->__profilerDevPreDestruct__ = &__nvoc_thunk_RsResource_profilerDevPreDestruct; - pThis->__profilerDevUnmapFrom__ = &__nvoc_thunk_RsResource_profilerDevUnmapFrom; - pThis->__profilerDevIsDuplicate__ = &__nvoc_thunk_RsResource_profilerDevIsDuplicate; - pThis->__profilerDevControl_Epilogue__ = &__nvoc_thunk_RmResource_profilerDevControl_Epilogue; - - pThis->__profilerDevControlLookup__ = &__nvoc_thunk_RsResource_profilerDevControlLookup; + pThis->__profilerDevControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_profilerDevControlSerialization_Epilogue; pThis->__profilerDevMap__ = &__nvoc_thunk_GpuResource_profilerDevMap; @@ -985,13 +1151,16 @@ NV_STATUS __nvoc_objCreate_ProfilerDev(ProfilerDev **ppThis, Dynamic *pParent, N ProfilerDev *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(ProfilerDev)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ProfilerDev), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(ProfilerDev)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ProfilerDev); + pThis->__nvoc_base_ProfilerBase.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -1011,11 +1180,17 @@ NV_STATUS __nvoc_objCreate_ProfilerDev(ProfilerDev **ppThis, Dynamic *pParent, N if (status != NV_OK) goto __nvoc_objCreate_ProfilerDev_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_ProfilerDev_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(ProfilerDev)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_profiler_v2_nvoc.h b/src/nvidia/generated/g_profiler_v2_nvoc.h index 945cbf211..87f1f9e59 100644 --- a/src/nvidia/generated/g_profiler_v2_nvoc.h +++ b/src/nvidia/generated/g_profiler_v2_nvoc.h @@ -67,43 +67,52 @@ struct ProfilerBase { struct GpuResource *__nvoc_pbase_GpuResource; struct ProfilerBase *__nvoc_pbase_ProfilerBase; NV_STATUS (*__profilerBaseCtrlCmdReserveHwpmLegacy__)(struct ProfilerBase *, NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS *); + NV_STATUS (*__profilerBaseCtrlCmdInternalReserveHwpmLegacy__)(struct ProfilerBase *, NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS *); NV_STATUS (*__profilerBaseCtrlCmdReleaseHwpmLegacy__)(struct ProfilerBase *); NV_STATUS (*__profilerBaseCtrlCmdReservePmAreaSmpc__)(struct ProfilerBase *, NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS *); NV_STATUS (*__profilerBaseCtrlCmdReleasePmAreaSmpc__)(struct ProfilerBase *); NV_STATUS (*__profilerBaseCtrlCmdAllocPmaStream__)(struct ProfilerBase *, NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS *); NV_STATUS (*__profilerBaseCtrlCmdFreePmaStream__)(struct ProfilerBase *, NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS *); + NV_STATUS (*__profilerBaseCtrlCmdInternalFreePmaStream__)(struct ProfilerBase *, NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS *); + NV_STATUS (*__profilerBaseCtrlCmdInternalGetMaxPmas__)(struct ProfilerBase *, NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS *); NV_STATUS (*__profilerBaseCtrlCmdBindPmResources__)(struct ProfilerBase *); NV_STATUS (*__profilerBaseCtrlCmdUnbindPmResources__)(struct ProfilerBase *); + NV_STATUS (*__profilerBaseCtrlCmdInternalBindPmResources__)(struct ProfilerBase *); + NV_STATUS (*__profilerBaseCtrlCmdInternalUnbindPmResources__)(struct ProfilerBase *); NV_STATUS (*__profilerBaseCtrlCmdPmaStreamUpdateGetPut__)(struct ProfilerBase *, NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS *); NV_STATUS (*__profilerBaseCtrlCmdExecRegops__)(struct ProfilerBase *, NVB0CC_CTRL_EXEC_REG_OPS_PARAMS *); - NV_STATUS (*__profilerBaseCtrlCmdInternalAllocPmaStream__)(struct ProfilerBase *, NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS *); + NV_STATUS (*__profilerBaseCtrlCmdInternalAllocPmaStream__)(struct ProfilerBase *, NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS *); NV_STATUS (*__profilerBaseCtrlCmdInternalPermissionsInit__)(struct ProfilerBase *, NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS *); NV_STATUS (*__profilerBaseCtrlCmdReservePmAreaPcSampler__)(struct ProfilerBase *); NV_STATUS (*__profilerBaseCtrlCmdReleasePmAreaPcSampler__)(struct ProfilerBase *); NV_STATUS (*__profilerBaseCtrlCmdGetTotalHsCredits__)(struct ProfilerBase *, NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS *); NV_STATUS (*__profilerBaseCtrlCmdGetHsCredits__)(struct ProfilerBase *, NVB0CC_CTRL_GET_HS_CREDITS_PARAMS *); NV_STATUS (*__profilerBaseCtrlCmdSetHsCredits__)(struct ProfilerBase *, NVB0CC_CTRL_SET_HS_CREDITS_PARAMS *); + NV_STATUS (*__profilerBaseCtrlCmdReserveHes__)(struct ProfilerBase *, NVB0CC_CTRL_RESERVE_HES_PARAMS *); + NV_STATUS (*__profilerBaseCtrlCmdReleaseHes__)(struct ProfilerBase *, NVB0CC_CTRL_RELEASE_HES_PARAMS *); NvBool (*__profilerBaseShareCallback__)(struct ProfilerBase *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__profilerBaseCheckMemInterUnmap__)(struct ProfilerBase *, NvBool); + NV_STATUS (*__profilerBaseMapTo__)(struct ProfilerBase *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__profilerBaseGetMapAddrSpace__)(struct ProfilerBase *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__profilerBaseGetRefCount__)(struct ProfilerBase *); + void (*__profilerBaseAddAdditionalDependants__)(struct RsClient *, struct ProfilerBase *, RsResourceRef *); + NV_STATUS (*__profilerBaseControl_Prologue__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__profilerBaseGetRegBaseOffsetAndSize__)(struct ProfilerBase *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__profilerBaseInternalControlForward__)(struct ProfilerBase *, NvU32, void *, NvU32); + NV_STATUS (*__profilerBaseUnmapFrom__)(struct ProfilerBase *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__profilerBaseControl_Epilogue__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__profilerBaseControlLookup__)(struct ProfilerBase *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__profilerBaseGetInternalObjectHandle__)(struct ProfilerBase *); NV_STATUS (*__profilerBaseControl__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__profilerBaseUnmap__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__profilerBaseGetMemInterMapParams__)(struct ProfilerBase *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__profilerBaseGetMemoryMappingDescriptor__)(struct ProfilerBase *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__profilerBaseGetMapAddrSpace__)(struct ProfilerBase *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__profilerBaseGetInternalObjectHandle__)(struct ProfilerBase *); NV_STATUS (*__profilerBaseControlFilter__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__profilerBaseAddAdditionalDependants__)(struct RsClient *, struct ProfilerBase *, RsResourceRef *); - NvU32 (*__profilerBaseGetRefCount__)(struct ProfilerBase *); - NV_STATUS (*__profilerBaseCheckMemInterUnmap__)(struct ProfilerBase *, NvBool); - NV_STATUS (*__profilerBaseMapTo__)(struct ProfilerBase *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__profilerBaseControl_Prologue__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__profilerBaseGetRegBaseOffsetAndSize__)(struct ProfilerBase *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__profilerBaseControlSerialization_Prologue__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__profilerBaseCanCopy__)(struct ProfilerBase *); - NV_STATUS (*__profilerBaseInternalControlForward__)(struct ProfilerBase *, NvU32, void *, NvU32); void (*__profilerBasePreDestruct__)(struct ProfilerBase *); - NV_STATUS (*__profilerBaseUnmapFrom__)(struct ProfilerBase *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__profilerBaseIsDuplicate__)(struct ProfilerBase *, NvHandle, NvBool *); - void (*__profilerBaseControl_Epilogue__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__profilerBaseControlLookup__)(struct ProfilerBase *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__profilerBaseControlSerialization_Epilogue__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__profilerBaseMap__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__profilerBaseAccessCallback__)(struct ProfilerBase *, struct RsClient *, void *, RsAccessRight); }; @@ -137,13 +146,18 @@ NV_STATUS __nvoc_objCreate_ProfilerBase(ProfilerBase**, Dynamic*, NvU32, struct __nvoc_objCreate_ProfilerBase((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) #define profilerBaseCtrlCmdReserveHwpmLegacy(pProfiler, pParams) profilerBaseCtrlCmdReserveHwpmLegacy_DISPATCH(pProfiler, pParams) +#define profilerBaseCtrlCmdInternalReserveHwpmLegacy(pProfiler, pParams) profilerBaseCtrlCmdInternalReserveHwpmLegacy_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdReleaseHwpmLegacy(pProfiler) profilerBaseCtrlCmdReleaseHwpmLegacy_DISPATCH(pProfiler) #define profilerBaseCtrlCmdReservePmAreaSmpc(pProfiler, pParams) profilerBaseCtrlCmdReservePmAreaSmpc_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdReleasePmAreaSmpc(pProfiler) profilerBaseCtrlCmdReleasePmAreaSmpc_DISPATCH(pProfiler) #define profilerBaseCtrlCmdAllocPmaStream(pProfiler, pParams) profilerBaseCtrlCmdAllocPmaStream_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdFreePmaStream(pProfiler, pParams) profilerBaseCtrlCmdFreePmaStream_DISPATCH(pProfiler, pParams) +#define profilerBaseCtrlCmdInternalFreePmaStream(pProfiler, pParams) profilerBaseCtrlCmdInternalFreePmaStream_DISPATCH(pProfiler, pParams) +#define profilerBaseCtrlCmdInternalGetMaxPmas(pProfiler, pParams) profilerBaseCtrlCmdInternalGetMaxPmas_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdBindPmResources(pProfiler) profilerBaseCtrlCmdBindPmResources_DISPATCH(pProfiler) #define profilerBaseCtrlCmdUnbindPmResources(pProfiler) profilerBaseCtrlCmdUnbindPmResources_DISPATCH(pProfiler) +#define profilerBaseCtrlCmdInternalBindPmResources(pProfiler) profilerBaseCtrlCmdInternalBindPmResources_DISPATCH(pProfiler) +#define profilerBaseCtrlCmdInternalUnbindPmResources(pProfiler) profilerBaseCtrlCmdInternalUnbindPmResources_DISPATCH(pProfiler) #define profilerBaseCtrlCmdPmaStreamUpdateGetPut(pProfiler, pParams) profilerBaseCtrlCmdPmaStreamUpdateGetPut_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdExecRegops(pProfiler, pParams) profilerBaseCtrlCmdExecRegops_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdInternalAllocPmaStream(pProfiler, pParams) profilerBaseCtrlCmdInternalAllocPmaStream_DISPATCH(pProfiler, pParams) @@ -153,27 +167,31 @@ NV_STATUS __nvoc_objCreate_ProfilerBase(ProfilerBase**, Dynamic*, NvU32, struct #define profilerBaseCtrlCmdGetTotalHsCredits(pProfiler, pParams) profilerBaseCtrlCmdGetTotalHsCredits_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdGetHsCredits(pProfiler, pParams) profilerBaseCtrlCmdGetHsCredits_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdSetHsCredits(pProfiler, pParams) profilerBaseCtrlCmdSetHsCredits_DISPATCH(pProfiler, pParams) +#define profilerBaseCtrlCmdReserveHes(pProfiler, pParams) profilerBaseCtrlCmdReserveHes_DISPATCH(pProfiler, pParams) +#define profilerBaseCtrlCmdReleaseHes(pProfiler, pParams) profilerBaseCtrlCmdReleaseHes_DISPATCH(pProfiler, pParams) #define profilerBaseShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) profilerBaseShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define profilerBaseCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) profilerBaseCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define profilerBaseMapTo(pResource, pParams) profilerBaseMapTo_DISPATCH(pResource, pParams) +#define profilerBaseGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) profilerBaseGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define profilerBaseGetRefCount(pResource) profilerBaseGetRefCount_DISPATCH(pResource) +#define profilerBaseAddAdditionalDependants(pClient, pResource, pReference) profilerBaseAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define profilerBaseControl_Prologue(pResource, pCallContext, pParams) profilerBaseControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define profilerBaseGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) profilerBaseGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define profilerBaseInternalControlForward(pGpuResource, command, pParams, size) profilerBaseInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define profilerBaseUnmapFrom(pResource, pParams) profilerBaseUnmapFrom_DISPATCH(pResource, pParams) +#define profilerBaseControl_Epilogue(pResource, pCallContext, pParams) profilerBaseControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define profilerBaseControlLookup(pResource, pParams, ppEntry) profilerBaseControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define profilerBaseGetInternalObjectHandle(pGpuResource) profilerBaseGetInternalObjectHandle_DISPATCH(pGpuResource) #define profilerBaseControl(pGpuResource, pCallContext, pParams) profilerBaseControl_DISPATCH(pGpuResource, pCallContext, pParams) #define profilerBaseUnmap(pGpuResource, pCallContext, pCpuMapping) profilerBaseUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define profilerBaseGetMemInterMapParams(pRmResource, pParams) profilerBaseGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define profilerBaseGetMemoryMappingDescriptor(pRmResource, ppMemDesc) profilerBaseGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define profilerBaseGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) profilerBaseGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define profilerBaseGetInternalObjectHandle(pGpuResource) profilerBaseGetInternalObjectHandle_DISPATCH(pGpuResource) #define profilerBaseControlFilter(pResource, pCallContext, pParams) profilerBaseControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define profilerBaseAddAdditionalDependants(pClient, pResource, pReference) profilerBaseAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define profilerBaseGetRefCount(pResource) profilerBaseGetRefCount_DISPATCH(pResource) -#define profilerBaseCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) profilerBaseCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define profilerBaseMapTo(pResource, pParams) profilerBaseMapTo_DISPATCH(pResource, pParams) -#define profilerBaseControl_Prologue(pResource, pCallContext, pParams) profilerBaseControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define profilerBaseGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) profilerBaseGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define profilerBaseControlSerialization_Prologue(pResource, pCallContext, pParams) profilerBaseControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define profilerBaseCanCopy(pResource) profilerBaseCanCopy_DISPATCH(pResource) -#define profilerBaseInternalControlForward(pGpuResource, command, pParams, size) profilerBaseInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define profilerBasePreDestruct(pResource) profilerBasePreDestruct_DISPATCH(pResource) -#define profilerBaseUnmapFrom(pResource, pParams) profilerBaseUnmapFrom_DISPATCH(pResource, pParams) #define profilerBaseIsDuplicate(pResource, hMemory, pDuplicate) profilerBaseIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) -#define profilerBaseControl_Epilogue(pResource, pCallContext, pParams) profilerBaseControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define profilerBaseControlLookup(pResource, pParams, ppEntry) profilerBaseControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define profilerBaseControlSerialization_Epilogue(pResource, pCallContext, pParams) profilerBaseControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define profilerBaseMap(pGpuResource, pCallContext, pParams, pCpuMapping) profilerBaseMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define profilerBaseAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) profilerBaseAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) static inline NV_STATUS profilerBaseConstructState_56cd7a(struct ProfilerBase *pProf, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { @@ -213,6 +231,12 @@ static inline NV_STATUS profilerBaseCtrlCmdReserveHwpmLegacy_DISPATCH(struct Pro return pProfiler->__profilerBaseCtrlCmdReserveHwpmLegacy__(pProfiler, pParams); } +NV_STATUS profilerBaseCtrlCmdInternalReserveHwpmLegacy_IMPL(struct ProfilerBase *pProfiler, NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS *pParams); + +static inline NV_STATUS profilerBaseCtrlCmdInternalReserveHwpmLegacy_DISPATCH(struct ProfilerBase *pProfiler, NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS *pParams) { + return pProfiler->__profilerBaseCtrlCmdInternalReserveHwpmLegacy__(pProfiler, pParams); +} + NV_STATUS profilerBaseCtrlCmdReleaseHwpmLegacy_IMPL(struct ProfilerBase *pProfiler); static inline NV_STATUS profilerBaseCtrlCmdReleaseHwpmLegacy_DISPATCH(struct ProfilerBase *pProfiler) { @@ -243,6 +267,18 @@ static inline NV_STATUS profilerBaseCtrlCmdFreePmaStream_DISPATCH(struct Profile return pProfiler->__profilerBaseCtrlCmdFreePmaStream__(pProfiler, pParams); } +NV_STATUS profilerBaseCtrlCmdInternalFreePmaStream_IMPL(struct ProfilerBase *pProfiler, NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS *pParams); + +static inline NV_STATUS profilerBaseCtrlCmdInternalFreePmaStream_DISPATCH(struct ProfilerBase *pProfiler, NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS *pParams) { + return pProfiler->__profilerBaseCtrlCmdInternalFreePmaStream__(pProfiler, pParams); +} + +NV_STATUS profilerBaseCtrlCmdInternalGetMaxPmas_IMPL(struct ProfilerBase *pProfiler, NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS *pParams); + +static inline NV_STATUS profilerBaseCtrlCmdInternalGetMaxPmas_DISPATCH(struct ProfilerBase *pProfiler, NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS *pParams) { + return pProfiler->__profilerBaseCtrlCmdInternalGetMaxPmas__(pProfiler, pParams); +} + NV_STATUS profilerBaseCtrlCmdBindPmResources_IMPL(struct ProfilerBase *pProfiler); static inline NV_STATUS profilerBaseCtrlCmdBindPmResources_DISPATCH(struct ProfilerBase *pProfiler) { @@ -255,6 +291,18 @@ static inline NV_STATUS profilerBaseCtrlCmdUnbindPmResources_DISPATCH(struct Pro return pProfiler->__profilerBaseCtrlCmdUnbindPmResources__(pProfiler); } +NV_STATUS profilerBaseCtrlCmdInternalBindPmResources_IMPL(struct ProfilerBase *pProfiler); + +static inline NV_STATUS profilerBaseCtrlCmdInternalBindPmResources_DISPATCH(struct ProfilerBase *pProfiler) { + return pProfiler->__profilerBaseCtrlCmdInternalBindPmResources__(pProfiler); +} + +NV_STATUS profilerBaseCtrlCmdInternalUnbindPmResources_IMPL(struct ProfilerBase *pProfiler); + +static inline NV_STATUS profilerBaseCtrlCmdInternalUnbindPmResources_DISPATCH(struct ProfilerBase *pProfiler) { + return pProfiler->__profilerBaseCtrlCmdInternalUnbindPmResources__(pProfiler); +} + NV_STATUS profilerBaseCtrlCmdPmaStreamUpdateGetPut_IMPL(struct ProfilerBase *pProfiler, NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS *pParams); static inline NV_STATUS profilerBaseCtrlCmdPmaStreamUpdateGetPut_DISPATCH(struct ProfilerBase *pProfiler, NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS *pParams) { @@ -267,9 +315,9 @@ static inline NV_STATUS profilerBaseCtrlCmdExecRegops_DISPATCH(struct ProfilerBa return pProfiler->__profilerBaseCtrlCmdExecRegops__(pProfiler, pParams); } -NV_STATUS profilerBaseCtrlCmdInternalAllocPmaStream_IMPL(struct ProfilerBase *pProfiler, NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS *pParams); +NV_STATUS profilerBaseCtrlCmdInternalAllocPmaStream_IMPL(struct ProfilerBase *pProfiler, NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS *pParams); -static inline NV_STATUS profilerBaseCtrlCmdInternalAllocPmaStream_DISPATCH(struct ProfilerBase *pProfiler, NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS *pParams) { +static inline NV_STATUS profilerBaseCtrlCmdInternalAllocPmaStream_DISPATCH(struct ProfilerBase *pProfiler, NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS *pParams) { return pProfiler->__profilerBaseCtrlCmdInternalAllocPmaStream__(pProfiler, pParams); } @@ -309,10 +357,70 @@ static inline NV_STATUS profilerBaseCtrlCmdSetHsCredits_DISPATCH(struct Profiler return pProfiler->__profilerBaseCtrlCmdSetHsCredits__(pProfiler, pParams); } +NV_STATUS profilerBaseCtrlCmdReserveHes_IMPL(struct ProfilerBase *pProfiler, NVB0CC_CTRL_RESERVE_HES_PARAMS *pParams); + +static inline NV_STATUS profilerBaseCtrlCmdReserveHes_DISPATCH(struct ProfilerBase *pProfiler, NVB0CC_CTRL_RESERVE_HES_PARAMS *pParams) { + return pProfiler->__profilerBaseCtrlCmdReserveHes__(pProfiler, pParams); +} + +NV_STATUS profilerBaseCtrlCmdReleaseHes_IMPL(struct ProfilerBase *pProfiler, NVB0CC_CTRL_RELEASE_HES_PARAMS *pParams); + +static inline NV_STATUS profilerBaseCtrlCmdReleaseHes_DISPATCH(struct ProfilerBase *pProfiler, NVB0CC_CTRL_RELEASE_HES_PARAMS *pParams) { + return pProfiler->__profilerBaseCtrlCmdReleaseHes__(pProfiler, pParams); +} + static inline NvBool profilerBaseShareCallback_DISPATCH(struct ProfilerBase *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__profilerBaseShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } +static inline NV_STATUS profilerBaseCheckMemInterUnmap_DISPATCH(struct ProfilerBase *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__profilerBaseCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS profilerBaseMapTo_DISPATCH(struct ProfilerBase *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__profilerBaseMapTo__(pResource, pParams); +} + +static inline NV_STATUS profilerBaseGetMapAddrSpace_DISPATCH(struct ProfilerBase *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__profilerBaseGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 profilerBaseGetRefCount_DISPATCH(struct ProfilerBase *pResource) { + return pResource->__profilerBaseGetRefCount__(pResource); +} + +static inline void profilerBaseAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ProfilerBase *pResource, RsResourceRef *pReference) { + pResource->__profilerBaseAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS profilerBaseControl_Prologue_DISPATCH(struct ProfilerBase *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__profilerBaseControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS profilerBaseGetRegBaseOffsetAndSize_DISPATCH(struct ProfilerBase *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__profilerBaseGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS profilerBaseInternalControlForward_DISPATCH(struct ProfilerBase *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__profilerBaseInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS profilerBaseUnmapFrom_DISPATCH(struct ProfilerBase *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__profilerBaseUnmapFrom__(pResource, pParams); +} + +static inline void profilerBaseControl_Epilogue_DISPATCH(struct ProfilerBase *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__profilerBaseControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS profilerBaseControlLookup_DISPATCH(struct ProfilerBase *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__profilerBaseControlLookup__(pResource, pParams, ppEntry); +} + +static inline NvHandle profilerBaseGetInternalObjectHandle_DISPATCH(struct ProfilerBase *pGpuResource) { + return pGpuResource->__profilerBaseGetInternalObjectHandle__(pGpuResource); +} + static inline NV_STATUS profilerBaseControl_DISPATCH(struct ProfilerBase *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pGpuResource->__profilerBaseControl__(pGpuResource, pCallContext, pParams); } @@ -329,68 +437,28 @@ static inline NV_STATUS profilerBaseGetMemoryMappingDescriptor_DISPATCH(struct P return pRmResource->__profilerBaseGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS profilerBaseGetMapAddrSpace_DISPATCH(struct ProfilerBase *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__profilerBaseGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvHandle profilerBaseGetInternalObjectHandle_DISPATCH(struct ProfilerBase *pGpuResource) { - return pGpuResource->__profilerBaseGetInternalObjectHandle__(pGpuResource); -} - static inline NV_STATUS profilerBaseControlFilter_DISPATCH(struct ProfilerBase *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__profilerBaseControlFilter__(pResource, pCallContext, pParams); } -static inline void profilerBaseAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ProfilerBase *pResource, RsResourceRef *pReference) { - pResource->__profilerBaseAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 profilerBaseGetRefCount_DISPATCH(struct ProfilerBase *pResource) { - return pResource->__profilerBaseGetRefCount__(pResource); -} - -static inline NV_STATUS profilerBaseCheckMemInterUnmap_DISPATCH(struct ProfilerBase *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__profilerBaseCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS profilerBaseMapTo_DISPATCH(struct ProfilerBase *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__profilerBaseMapTo__(pResource, pParams); -} - -static inline NV_STATUS profilerBaseControl_Prologue_DISPATCH(struct ProfilerBase *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__profilerBaseControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS profilerBaseGetRegBaseOffsetAndSize_DISPATCH(struct ProfilerBase *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__profilerBaseGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +static inline NV_STATUS profilerBaseControlSerialization_Prologue_DISPATCH(struct ProfilerBase *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__profilerBaseControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool profilerBaseCanCopy_DISPATCH(struct ProfilerBase *pResource) { return pResource->__profilerBaseCanCopy__(pResource); } -static inline NV_STATUS profilerBaseInternalControlForward_DISPATCH(struct ProfilerBase *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__profilerBaseInternalControlForward__(pGpuResource, command, pParams, size); -} - static inline void profilerBasePreDestruct_DISPATCH(struct ProfilerBase *pResource) { pResource->__profilerBasePreDestruct__(pResource); } -static inline NV_STATUS profilerBaseUnmapFrom_DISPATCH(struct ProfilerBase *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__profilerBaseUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS profilerBaseIsDuplicate_DISPATCH(struct ProfilerBase *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__profilerBaseIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline void profilerBaseControl_Epilogue_DISPATCH(struct ProfilerBase *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__profilerBaseControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS profilerBaseControlLookup_DISPATCH(struct ProfilerBase *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__profilerBaseControlLookup__(pResource, pParams, ppEntry); +static inline void profilerBaseControlSerialization_Epilogue_DISPATCH(struct ProfilerBase *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__profilerBaseControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS profilerBaseMap_DISPATCH(struct ProfilerBase *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -426,26 +494,28 @@ struct ProfilerDev { struct ProfilerBase *__nvoc_pbase_ProfilerBase; struct ProfilerDev *__nvoc_pbase_ProfilerDev; NvBool (*__profilerDevShareCallback__)(struct ProfilerDev *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__profilerDevCheckMemInterUnmap__)(struct ProfilerDev *, NvBool); + NV_STATUS (*__profilerDevMapTo__)(struct ProfilerDev *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__profilerDevGetMapAddrSpace__)(struct ProfilerDev *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__profilerDevGetRefCount__)(struct ProfilerDev *); + void (*__profilerDevAddAdditionalDependants__)(struct RsClient *, struct ProfilerDev *, RsResourceRef *); + NV_STATUS (*__profilerDevControl_Prologue__)(struct ProfilerDev *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__profilerDevGetRegBaseOffsetAndSize__)(struct ProfilerDev *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__profilerDevInternalControlForward__)(struct ProfilerDev *, NvU32, void *, NvU32); + NV_STATUS (*__profilerDevUnmapFrom__)(struct ProfilerDev *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__profilerDevControl_Epilogue__)(struct ProfilerDev *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__profilerDevControlLookup__)(struct ProfilerDev *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__profilerDevGetInternalObjectHandle__)(struct ProfilerDev *); NV_STATUS (*__profilerDevControl__)(struct ProfilerDev *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__profilerDevUnmap__)(struct ProfilerDev *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__profilerDevGetMemInterMapParams__)(struct ProfilerDev *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__profilerDevGetMemoryMappingDescriptor__)(struct ProfilerDev *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__profilerDevGetMapAddrSpace__)(struct ProfilerDev *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__profilerDevGetInternalObjectHandle__)(struct ProfilerDev *); NV_STATUS (*__profilerDevControlFilter__)(struct ProfilerDev *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__profilerDevAddAdditionalDependants__)(struct RsClient *, struct ProfilerDev *, RsResourceRef *); - NvU32 (*__profilerDevGetRefCount__)(struct ProfilerDev *); - NV_STATUS (*__profilerDevCheckMemInterUnmap__)(struct ProfilerDev *, NvBool); - NV_STATUS (*__profilerDevMapTo__)(struct ProfilerDev *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__profilerDevControl_Prologue__)(struct ProfilerDev *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__profilerDevGetRegBaseOffsetAndSize__)(struct ProfilerDev *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__profilerDevControlSerialization_Prologue__)(struct ProfilerDev *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__profilerDevCanCopy__)(struct ProfilerDev *); - NV_STATUS (*__profilerDevInternalControlForward__)(struct ProfilerDev *, NvU32, void *, NvU32); void (*__profilerDevPreDestruct__)(struct ProfilerDev *); - NV_STATUS (*__profilerDevUnmapFrom__)(struct ProfilerDev *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__profilerDevIsDuplicate__)(struct ProfilerDev *, NvHandle, NvBool *); - void (*__profilerDevControl_Epilogue__)(struct ProfilerDev *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__profilerDevControlLookup__)(struct ProfilerDev *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__profilerDevControlSerialization_Epilogue__)(struct ProfilerDev *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__profilerDevMap__)(struct ProfilerDev *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__profilerDevAccessCallback__)(struct ProfilerDev *, struct RsClient *, void *, RsAccessRight); }; @@ -479,26 +549,28 @@ NV_STATUS __nvoc_objCreate_ProfilerDev(ProfilerDev**, Dynamic*, NvU32, struct CA __nvoc_objCreate_ProfilerDev((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) #define profilerDevShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) profilerDevShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define profilerDevCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) profilerDevCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define profilerDevMapTo(pResource, pParams) profilerDevMapTo_DISPATCH(pResource, pParams) +#define profilerDevGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) profilerDevGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define profilerDevGetRefCount(pResource) profilerDevGetRefCount_DISPATCH(pResource) +#define profilerDevAddAdditionalDependants(pClient, pResource, pReference) profilerDevAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define profilerDevControl_Prologue(pResource, pCallContext, pParams) profilerDevControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define profilerDevGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) profilerDevGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define profilerDevInternalControlForward(pGpuResource, command, pParams, size) profilerDevInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define profilerDevUnmapFrom(pResource, pParams) profilerDevUnmapFrom_DISPATCH(pResource, pParams) +#define profilerDevControl_Epilogue(pResource, pCallContext, pParams) profilerDevControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define profilerDevControlLookup(pResource, pParams, ppEntry) profilerDevControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define profilerDevGetInternalObjectHandle(pGpuResource) profilerDevGetInternalObjectHandle_DISPATCH(pGpuResource) #define profilerDevControl(pGpuResource, pCallContext, pParams) profilerDevControl_DISPATCH(pGpuResource, pCallContext, pParams) #define profilerDevUnmap(pGpuResource, pCallContext, pCpuMapping) profilerDevUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define profilerDevGetMemInterMapParams(pRmResource, pParams) profilerDevGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define profilerDevGetMemoryMappingDescriptor(pRmResource, ppMemDesc) profilerDevGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define profilerDevGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) profilerDevGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define profilerDevGetInternalObjectHandle(pGpuResource) profilerDevGetInternalObjectHandle_DISPATCH(pGpuResource) #define profilerDevControlFilter(pResource, pCallContext, pParams) profilerDevControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define profilerDevAddAdditionalDependants(pClient, pResource, pReference) profilerDevAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define profilerDevGetRefCount(pResource) profilerDevGetRefCount_DISPATCH(pResource) -#define profilerDevCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) profilerDevCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define profilerDevMapTo(pResource, pParams) profilerDevMapTo_DISPATCH(pResource, pParams) -#define profilerDevControl_Prologue(pResource, pCallContext, pParams) profilerDevControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define profilerDevGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) profilerDevGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define profilerDevControlSerialization_Prologue(pResource, pCallContext, pParams) profilerDevControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define profilerDevCanCopy(pResource) profilerDevCanCopy_DISPATCH(pResource) -#define profilerDevInternalControlForward(pGpuResource, command, pParams, size) profilerDevInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define profilerDevPreDestruct(pResource) profilerDevPreDestruct_DISPATCH(pResource) -#define profilerDevUnmapFrom(pResource, pParams) profilerDevUnmapFrom_DISPATCH(pResource, pParams) #define profilerDevIsDuplicate(pResource, hMemory, pDuplicate) profilerDevIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) -#define profilerDevControl_Epilogue(pResource, pCallContext, pParams) profilerDevControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define profilerDevControlLookup(pResource, pParams, ppEntry) profilerDevControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define profilerDevControlSerialization_Epilogue(pResource, pCallContext, pParams) profilerDevControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define profilerDevMap(pGpuResource, pCallContext, pParams, pCpuMapping) profilerDevMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define profilerDevAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) profilerDevAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS profilerDevConstructState_IMPL(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams, PROFILER_CLIENT_PERMISSIONS clientPermissions); @@ -590,6 +662,54 @@ static inline NvBool profilerDevShareCallback_DISPATCH(struct ProfilerDev *pGpuR return pGpuResource->__profilerDevShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } +static inline NV_STATUS profilerDevCheckMemInterUnmap_DISPATCH(struct ProfilerDev *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__profilerDevCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS profilerDevMapTo_DISPATCH(struct ProfilerDev *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__profilerDevMapTo__(pResource, pParams); +} + +static inline NV_STATUS profilerDevGetMapAddrSpace_DISPATCH(struct ProfilerDev *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__profilerDevGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 profilerDevGetRefCount_DISPATCH(struct ProfilerDev *pResource) { + return pResource->__profilerDevGetRefCount__(pResource); +} + +static inline void profilerDevAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ProfilerDev *pResource, RsResourceRef *pReference) { + pResource->__profilerDevAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS profilerDevControl_Prologue_DISPATCH(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__profilerDevControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS profilerDevGetRegBaseOffsetAndSize_DISPATCH(struct ProfilerDev *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__profilerDevGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS profilerDevInternalControlForward_DISPATCH(struct ProfilerDev *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__profilerDevInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS profilerDevUnmapFrom_DISPATCH(struct ProfilerDev *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__profilerDevUnmapFrom__(pResource, pParams); +} + +static inline void profilerDevControl_Epilogue_DISPATCH(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__profilerDevControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS profilerDevControlLookup_DISPATCH(struct ProfilerDev *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__profilerDevControlLookup__(pResource, pParams, ppEntry); +} + +static inline NvHandle profilerDevGetInternalObjectHandle_DISPATCH(struct ProfilerDev *pGpuResource) { + return pGpuResource->__profilerDevGetInternalObjectHandle__(pGpuResource); +} + static inline NV_STATUS profilerDevControl_DISPATCH(struct ProfilerDev *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pGpuResource->__profilerDevControl__(pGpuResource, pCallContext, pParams); } @@ -606,68 +726,28 @@ static inline NV_STATUS profilerDevGetMemoryMappingDescriptor_DISPATCH(struct Pr return pRmResource->__profilerDevGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS profilerDevGetMapAddrSpace_DISPATCH(struct ProfilerDev *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__profilerDevGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvHandle profilerDevGetInternalObjectHandle_DISPATCH(struct ProfilerDev *pGpuResource) { - return pGpuResource->__profilerDevGetInternalObjectHandle__(pGpuResource); -} - static inline NV_STATUS profilerDevControlFilter_DISPATCH(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__profilerDevControlFilter__(pResource, pCallContext, pParams); } -static inline void profilerDevAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ProfilerDev *pResource, RsResourceRef *pReference) { - pResource->__profilerDevAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 profilerDevGetRefCount_DISPATCH(struct ProfilerDev *pResource) { - return pResource->__profilerDevGetRefCount__(pResource); -} - -static inline NV_STATUS profilerDevCheckMemInterUnmap_DISPATCH(struct ProfilerDev *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__profilerDevCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS profilerDevMapTo_DISPATCH(struct ProfilerDev *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__profilerDevMapTo__(pResource, pParams); -} - -static inline NV_STATUS profilerDevControl_Prologue_DISPATCH(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__profilerDevControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS profilerDevGetRegBaseOffsetAndSize_DISPATCH(struct ProfilerDev *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__profilerDevGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +static inline NV_STATUS profilerDevControlSerialization_Prologue_DISPATCH(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__profilerDevControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool profilerDevCanCopy_DISPATCH(struct ProfilerDev *pResource) { return pResource->__profilerDevCanCopy__(pResource); } -static inline NV_STATUS profilerDevInternalControlForward_DISPATCH(struct ProfilerDev *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__profilerDevInternalControlForward__(pGpuResource, command, pParams, size); -} - static inline void profilerDevPreDestruct_DISPATCH(struct ProfilerDev *pResource) { pResource->__profilerDevPreDestruct__(pResource); } -static inline NV_STATUS profilerDevUnmapFrom_DISPATCH(struct ProfilerDev *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__profilerDevUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS profilerDevIsDuplicate_DISPATCH(struct ProfilerDev *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__profilerDevIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline void profilerDevControl_Epilogue_DISPATCH(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__profilerDevControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS profilerDevControlLookup_DISPATCH(struct ProfilerDev *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__profilerDevControlLookup__(pResource, pParams, ppEntry); +static inline void profilerDevControlSerialization_Epilogue_DISPATCH(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__profilerDevControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS profilerDevMap_DISPATCH(struct ProfilerDev *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_ref_count_nvoc.c b/src/nvidia/generated/g_ref_count_nvoc.c index f38517b34..a16c1ecb0 100644 --- a/src/nvidia/generated/g_ref_count_nvoc.c +++ b/src/nvidia/generated/g_ref_count_nvoc.c @@ -114,13 +114,16 @@ NV_STATUS __nvoc_objCreate_OBJREFCNT(OBJREFCNT **ppThis, Dynamic *pParent, NvU32 Object *pParentObj; OBJREFCNT *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJREFCNT)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJREFCNT), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJREFCNT)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJREFCNT); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -136,11 +139,17 @@ NV_STATUS __nvoc_objCreate_OBJREFCNT(OBJREFCNT **ppThis, Dynamic *pParent, NvU32 if (status != NV_OK) goto __nvoc_objCreate_OBJREFCNT_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJREFCNT_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJREFCNT)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_reg_mem_nvoc.c b/src/nvidia/generated/g_reg_mem_nvoc.c index 53d65e755..4e6b405b5 100644 --- a/src/nvidia/generated/g_reg_mem_nvoc.c +++ b/src/nvidia/generated/g_reg_mem_nvoc.c @@ -101,6 +101,46 @@ static NV_STATUS __nvoc_thunk_Memory_regmemCheckMemInterUnmap(struct RegisterMem return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), bSubdeviceHandleProvided); } +static NvBool __nvoc_thunk_RmResource_regmemShareCallback(struct RegisterMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RsResource_regmemMapTo(struct RegisterMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_regmemGetMapAddrSpace(struct RegisterMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_regmemGetRefCount(struct RegisterMemory *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_regmemAddAdditionalDependants(struct RsClient *pClient, struct RegisterMemory *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_regmemControl_Prologue(struct RegisterMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_Memory_regmemIsGpuMapAllowed(struct RegisterMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), pGpu); +} + +static NV_STATUS __nvoc_thunk_RsResource_regmemUnmapFrom(struct RegisterMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_regmemControl_Epilogue(struct RegisterMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_regmemControlLookup(struct RegisterMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RsResource.offset), pParams, ppEntry); +} + static NV_STATUS __nvoc_thunk_Memory_regmemControl(struct RegisterMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), pCallContext, pParams); } @@ -117,36 +157,12 @@ static NV_STATUS __nvoc_thunk_Memory_regmemGetMemoryMappingDescriptor(struct Reg return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_Memory_regmemGetMapAddrSpace(struct RegisterMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvBool __nvoc_thunk_RmResource_regmemShareCallback(struct RegisterMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); -} - static NV_STATUS __nvoc_thunk_RsResource_regmemControlFilter(struct RegisterMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_regmemAddAdditionalDependants(struct RsClient *pClient, struct RegisterMemory *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_regmemGetRefCount(struct RegisterMemory *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RsResource_regmemMapTo(struct RegisterMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_regmemControl_Prologue(struct RegisterMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RmResource.offset), pCallContext, pParams); -} - -static NvBool __nvoc_thunk_Memory_regmemIsGpuMapAllowed(struct RegisterMemory *pMemory, struct OBJGPU *pGpu) { - return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), pGpu); +static NV_STATUS __nvoc_thunk_RmResource_regmemControlSerialization_Prologue(struct RegisterMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_regmemIsReady(struct RegisterMemory *pMemory, NvBool bCopyConstructorContext) { @@ -165,16 +181,8 @@ static NV_STATUS __nvoc_thunk_Memory_regmemIsDuplicate(struct RegisterMemory *pM return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), hMemory, pDuplicate); } -static NV_STATUS __nvoc_thunk_RsResource_regmemUnmapFrom(struct RegisterMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RmResource_regmemControl_Epilogue(struct RegisterMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_regmemControlLookup(struct RegisterMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_regmemControlSerialization_Epilogue(struct RegisterMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_regmemMap(struct RegisterMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -229,6 +237,26 @@ static void __nvoc_init_funcTable_RegisterMemory_1(RegisterMemory *pThis) { pThis->__regmemCheckMemInterUnmap__ = &__nvoc_thunk_Memory_regmemCheckMemInterUnmap; + pThis->__regmemShareCallback__ = &__nvoc_thunk_RmResource_regmemShareCallback; + + pThis->__regmemMapTo__ = &__nvoc_thunk_RsResource_regmemMapTo; + + pThis->__regmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_regmemGetMapAddrSpace; + + pThis->__regmemGetRefCount__ = &__nvoc_thunk_RsResource_regmemGetRefCount; + + pThis->__regmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_regmemAddAdditionalDependants; + + pThis->__regmemControl_Prologue__ = &__nvoc_thunk_RmResource_regmemControl_Prologue; + + pThis->__regmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_regmemIsGpuMapAllowed; + + pThis->__regmemUnmapFrom__ = &__nvoc_thunk_RsResource_regmemUnmapFrom; + + pThis->__regmemControl_Epilogue__ = &__nvoc_thunk_RmResource_regmemControl_Epilogue; + + pThis->__regmemControlLookup__ = &__nvoc_thunk_RsResource_regmemControlLookup; + pThis->__regmemControl__ = &__nvoc_thunk_Memory_regmemControl; pThis->__regmemUnmap__ = &__nvoc_thunk_Memory_regmemUnmap; @@ -237,21 +265,9 @@ static void __nvoc_init_funcTable_RegisterMemory_1(RegisterMemory *pThis) { pThis->__regmemGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_regmemGetMemoryMappingDescriptor; - pThis->__regmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_regmemGetMapAddrSpace; - - pThis->__regmemShareCallback__ = &__nvoc_thunk_RmResource_regmemShareCallback; - pThis->__regmemControlFilter__ = &__nvoc_thunk_RsResource_regmemControlFilter; - pThis->__regmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_regmemAddAdditionalDependants; - - pThis->__regmemGetRefCount__ = &__nvoc_thunk_RsResource_regmemGetRefCount; - - pThis->__regmemMapTo__ = &__nvoc_thunk_RsResource_regmemMapTo; - - pThis->__regmemControl_Prologue__ = &__nvoc_thunk_RmResource_regmemControl_Prologue; - - pThis->__regmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_regmemIsGpuMapAllowed; + pThis->__regmemControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_regmemControlSerialization_Prologue; pThis->__regmemIsReady__ = &__nvoc_thunk_Memory_regmemIsReady; @@ -261,11 +277,7 @@ static void __nvoc_init_funcTable_RegisterMemory_1(RegisterMemory *pThis) { pThis->__regmemIsDuplicate__ = &__nvoc_thunk_Memory_regmemIsDuplicate; - pThis->__regmemUnmapFrom__ = &__nvoc_thunk_RsResource_regmemUnmapFrom; - - pThis->__regmemControl_Epilogue__ = &__nvoc_thunk_RmResource_regmemControl_Epilogue; - - pThis->__regmemControlLookup__ = &__nvoc_thunk_RsResource_regmemControlLookup; + pThis->__regmemControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_regmemControlSerialization_Epilogue; pThis->__regmemMap__ = &__nvoc_thunk_Memory_regmemMap; @@ -293,13 +305,16 @@ NV_STATUS __nvoc_objCreate_RegisterMemory(RegisterMemory **ppThis, Dynamic *pPar Object *pParentObj; RegisterMemory *pThis; - pThis = portMemAllocNonPaged(sizeof(RegisterMemory)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RegisterMemory), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(RegisterMemory)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RegisterMemory); + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -315,11 +330,17 @@ NV_STATUS __nvoc_objCreate_RegisterMemory(RegisterMemory **ppThis, Dynamic *pPar if (status != NV_OK) goto __nvoc_objCreate_RegisterMemory_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_RegisterMemory_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(RegisterMemory)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_reg_mem_nvoc.h b/src/nvidia/generated/g_reg_mem_nvoc.h index 6b4f5e8f4..ff373cbe5 100644 --- a/src/nvidia/generated/g_reg_mem_nvoc.h +++ b/src/nvidia/generated/g_reg_mem_nvoc.h @@ -57,25 +57,27 @@ struct RegisterMemory { struct RegisterMemory *__nvoc_pbase_RegisterMemory; NvBool (*__regmemCanCopy__)(struct RegisterMemory *); NV_STATUS (*__regmemCheckMemInterUnmap__)(struct RegisterMemory *, NvBool); + NvBool (*__regmemShareCallback__)(struct RegisterMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__regmemMapTo__)(struct RegisterMemory *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__regmemGetMapAddrSpace__)(struct RegisterMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__regmemGetRefCount__)(struct RegisterMemory *); + void (*__regmemAddAdditionalDependants__)(struct RsClient *, struct RegisterMemory *, RsResourceRef *); + NV_STATUS (*__regmemControl_Prologue__)(struct RegisterMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__regmemIsGpuMapAllowed__)(struct RegisterMemory *, struct OBJGPU *); + NV_STATUS (*__regmemUnmapFrom__)(struct RegisterMemory *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__regmemControl_Epilogue__)(struct RegisterMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__regmemControlLookup__)(struct RegisterMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__regmemControl__)(struct RegisterMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__regmemUnmap__)(struct RegisterMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__regmemGetMemInterMapParams__)(struct RegisterMemory *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__regmemGetMemoryMappingDescriptor__)(struct RegisterMemory *, MEMORY_DESCRIPTOR **); - NV_STATUS (*__regmemGetMapAddrSpace__)(struct RegisterMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvBool (*__regmemShareCallback__)(struct RegisterMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__regmemControlFilter__)(struct RegisterMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__regmemAddAdditionalDependants__)(struct RsClient *, struct RegisterMemory *, RsResourceRef *); - NvU32 (*__regmemGetRefCount__)(struct RegisterMemory *); - NV_STATUS (*__regmemMapTo__)(struct RegisterMemory *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__regmemControl_Prologue__)(struct RegisterMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvBool (*__regmemIsGpuMapAllowed__)(struct RegisterMemory *, struct OBJGPU *); + NV_STATUS (*__regmemControlSerialization_Prologue__)(struct RegisterMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__regmemIsReady__)(struct RegisterMemory *, NvBool); NV_STATUS (*__regmemCheckCopyPermissions__)(struct RegisterMemory *, struct OBJGPU *, NvHandle); void (*__regmemPreDestruct__)(struct RegisterMemory *); NV_STATUS (*__regmemIsDuplicate__)(struct RegisterMemory *, NvHandle, NvBool *); - NV_STATUS (*__regmemUnmapFrom__)(struct RegisterMemory *, RS_RES_UNMAP_FROM_PARAMS *); - void (*__regmemControl_Epilogue__)(struct RegisterMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__regmemControlLookup__)(struct RegisterMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__regmemControlSerialization_Epilogue__)(struct RegisterMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__regmemMap__)(struct RegisterMemory *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__regmemAccessCallback__)(struct RegisterMemory *, struct RsClient *, void *, RsAccessRight); }; @@ -110,25 +112,27 @@ NV_STATUS __nvoc_objCreate_RegisterMemory(RegisterMemory**, Dynamic*, NvU32, CAL #define regmemCanCopy(pRegisterMemory) regmemCanCopy_DISPATCH(pRegisterMemory) #define regmemCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) regmemCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define regmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) regmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define regmemMapTo(pResource, pParams) regmemMapTo_DISPATCH(pResource, pParams) +#define regmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) regmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define regmemGetRefCount(pResource) regmemGetRefCount_DISPATCH(pResource) +#define regmemAddAdditionalDependants(pClient, pResource, pReference) regmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define regmemControl_Prologue(pResource, pCallContext, pParams) regmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define regmemIsGpuMapAllowed(pMemory, pGpu) regmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define regmemUnmapFrom(pResource, pParams) regmemUnmapFrom_DISPATCH(pResource, pParams) +#define regmemControl_Epilogue(pResource, pCallContext, pParams) regmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define regmemControlLookup(pResource, pParams, ppEntry) regmemControlLookup_DISPATCH(pResource, pParams, ppEntry) #define regmemControl(pMemory, pCallContext, pParams) regmemControl_DISPATCH(pMemory, pCallContext, pParams) #define regmemUnmap(pMemory, pCallContext, pCpuMapping) regmemUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define regmemGetMemInterMapParams(pMemory, pParams) regmemGetMemInterMapParams_DISPATCH(pMemory, pParams) #define regmemGetMemoryMappingDescriptor(pMemory, ppMemDesc) regmemGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define regmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) regmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) -#define regmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) regmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define regmemControlFilter(pResource, pCallContext, pParams) regmemControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define regmemAddAdditionalDependants(pClient, pResource, pReference) regmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define regmemGetRefCount(pResource) regmemGetRefCount_DISPATCH(pResource) -#define regmemMapTo(pResource, pParams) regmemMapTo_DISPATCH(pResource, pParams) -#define regmemControl_Prologue(pResource, pCallContext, pParams) regmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define regmemIsGpuMapAllowed(pMemory, pGpu) regmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define regmemControlSerialization_Prologue(pResource, pCallContext, pParams) regmemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define regmemIsReady(pMemory, bCopyConstructorContext) regmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define regmemCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) regmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) #define regmemPreDestruct(pResource) regmemPreDestruct_DISPATCH(pResource) #define regmemIsDuplicate(pMemory, hMemory, pDuplicate) regmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) -#define regmemUnmapFrom(pResource, pParams) regmemUnmapFrom_DISPATCH(pResource, pParams) -#define regmemControl_Epilogue(pResource, pCallContext, pParams) regmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define regmemControlLookup(pResource, pParams, ppEntry) regmemControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define regmemControlSerialization_Epilogue(pResource, pCallContext, pParams) regmemControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define regmemMap(pMemory, pCallContext, pParams, pCpuMapping) regmemMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define regmemAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) regmemAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool regmemCanCopy_IMPL(struct RegisterMemory *pRegisterMemory); @@ -141,6 +145,46 @@ static inline NV_STATUS regmemCheckMemInterUnmap_DISPATCH(struct RegisterMemory return pMemory->__regmemCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } +static inline NvBool regmemShareCallback_DISPATCH(struct RegisterMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__regmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS regmemMapTo_DISPATCH(struct RegisterMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__regmemMapTo__(pResource, pParams); +} + +static inline NV_STATUS regmemGetMapAddrSpace_DISPATCH(struct RegisterMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__regmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 regmemGetRefCount_DISPATCH(struct RegisterMemory *pResource) { + return pResource->__regmemGetRefCount__(pResource); +} + +static inline void regmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct RegisterMemory *pResource, RsResourceRef *pReference) { + pResource->__regmemAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS regmemControl_Prologue_DISPATCH(struct RegisterMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__regmemControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool regmemIsGpuMapAllowed_DISPATCH(struct RegisterMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__regmemIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline NV_STATUS regmemUnmapFrom_DISPATCH(struct RegisterMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__regmemUnmapFrom__(pResource, pParams); +} + +static inline void regmemControl_Epilogue_DISPATCH(struct RegisterMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__regmemControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS regmemControlLookup_DISPATCH(struct RegisterMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__regmemControlLookup__(pResource, pParams, ppEntry); +} + static inline NV_STATUS regmemControl_DISPATCH(struct RegisterMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pMemory->__regmemControl__(pMemory, pCallContext, pParams); } @@ -157,36 +201,12 @@ static inline NV_STATUS regmemGetMemoryMappingDescriptor_DISPATCH(struct Registe return pMemory->__regmemGetMemoryMappingDescriptor__(pMemory, ppMemDesc); } -static inline NV_STATUS regmemGetMapAddrSpace_DISPATCH(struct RegisterMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pMemory->__regmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvBool regmemShareCallback_DISPATCH(struct RegisterMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pResource->__regmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); -} - static inline NV_STATUS regmemControlFilter_DISPATCH(struct RegisterMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__regmemControlFilter__(pResource, pCallContext, pParams); } -static inline void regmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct RegisterMemory *pResource, RsResourceRef *pReference) { - pResource->__regmemAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 regmemGetRefCount_DISPATCH(struct RegisterMemory *pResource) { - return pResource->__regmemGetRefCount__(pResource); -} - -static inline NV_STATUS regmemMapTo_DISPATCH(struct RegisterMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__regmemMapTo__(pResource, pParams); -} - -static inline NV_STATUS regmemControl_Prologue_DISPATCH(struct RegisterMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__regmemControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NvBool regmemIsGpuMapAllowed_DISPATCH(struct RegisterMemory *pMemory, struct OBJGPU *pGpu) { - return pMemory->__regmemIsGpuMapAllowed__(pMemory, pGpu); +static inline NV_STATUS regmemControlSerialization_Prologue_DISPATCH(struct RegisterMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__regmemControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS regmemIsReady_DISPATCH(struct RegisterMemory *pMemory, NvBool bCopyConstructorContext) { @@ -205,16 +225,8 @@ static inline NV_STATUS regmemIsDuplicate_DISPATCH(struct RegisterMemory *pMemor return pMemory->__regmemIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline NV_STATUS regmemUnmapFrom_DISPATCH(struct RegisterMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__regmemUnmapFrom__(pResource, pParams); -} - -static inline void regmemControl_Epilogue_DISPATCH(struct RegisterMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__regmemControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS regmemControlLookup_DISPATCH(struct RegisterMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__regmemControlLookup__(pResource, pParams, ppEntry); +static inline void regmemControlSerialization_Epilogue_DISPATCH(struct RegisterMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__regmemControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS regmemMap_DISPATCH(struct RegisterMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_resource_fwd_decls_nvoc.h b/src/nvidia/generated/g_resource_fwd_decls_nvoc.h index 2eb7c8305..bc0926b1e 100644 --- a/src/nvidia/generated/g_resource_fwd_decls_nvoc.h +++ b/src/nvidia/generated/g_resource_fwd_decls_nvoc.h @@ -805,6 +805,17 @@ typedef struct AccessCounterBuffer AccessCounterBuffer; #define __nvoc_class_id_AccessCounterBuffer 0x1f0074 #endif /* __nvoc_class_id_AccessCounterBuffer */ +struct VidmemAccessBitBuffer; + +#ifndef __NVOC_CLASS_VidmemAccessBitBuffer_TYPEDEF__ +#define __NVOC_CLASS_VidmemAccessBitBuffer_TYPEDEF__ +typedef struct VidmemAccessBitBuffer VidmemAccessBitBuffer; +#endif /* __NVOC_CLASS_VidmemAccessBitBuffer_TYPEDEF__ */ + +#ifndef __nvoc_class_id_VidmemAccessBitBuffer +#define __nvoc_class_id_VidmemAccessBitBuffer 0xebb6da +#endif /* __nvoc_class_id_VidmemAccessBitBuffer */ + struct GPUInstanceSubscription; #ifndef __NVOC_CLASS_GPUInstanceSubscription_TYPEDEF__ @@ -1142,6 +1153,7 @@ struct NVOCFwdDeclHack { struct DispSfUser *PRIVATE_FIELD(DispSfUser_NVC771_DISP_SF_USER); struct MmuFaultBuffer *PRIVATE_FIELD(MmuFaultBuffer_MMU_FAULT_BUFFER); struct AccessCounterBuffer *PRIVATE_FIELD(AccessCounterBuffer_ACCESS_COUNTER_NOTIFY_BUFFER); + struct VidmemAccessBitBuffer *PRIVATE_FIELD(VidmemAccessBitBuffer_MMU_VIDMEM_ACCESS_BIT_BUFFER); struct GPUInstanceSubscription *PRIVATE_FIELD(GPUInstanceSubscription_AMPERE_SMC_PARTITION_REF); struct ComputeInstanceSubscription *PRIVATE_FIELD(ComputeInstanceSubscription_AMPERE_SMC_EXEC_PARTITION_REF); struct MIGConfigSession *PRIVATE_FIELD(MIGConfigSession_AMPERE_SMC_CONFIG_SESSION); diff --git a/src/nvidia/generated/g_resource_nvoc.c b/src/nvidia/generated/g_resource_nvoc.c index c9421b538..4ff85e688 100644 --- a/src/nvidia/generated/g_resource_nvoc.c +++ b/src/nvidia/generated/g_resource_nvoc.c @@ -166,6 +166,14 @@ static NvBool __nvoc_thunk_RmResource_resShareCallback(struct RsResource *pResou return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) - __nvoc_rtti_RmResource_RsResource.offset), pInvokingClient, pParentRef, pSharePolicy); } +static NV_STATUS __nvoc_thunk_RmResource_resControlSerialization_Prologue(struct RsResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) - __nvoc_rtti_RmResource_RsResource.offset), pCallContext, pParams); +} + +static void __nvoc_thunk_RmResource_resControlSerialization_Epilogue(struct RsResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) - __nvoc_rtti_RmResource_RsResource.offset), pCallContext, pParams); +} + static NV_STATUS __nvoc_thunk_RmResource_resControl_Prologue(struct RsResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) - __nvoc_rtti_RmResource_RsResource.offset), pCallContext, pParams); } @@ -277,6 +285,10 @@ static void __nvoc_init_funcTable_RmResource_1(RmResource *pThis) { pThis->__rmresGetMemoryMappingDescriptor__ = &rmresGetMemoryMappingDescriptor_IMPL; + pThis->__rmresControlSerialization_Prologue__ = &rmresControlSerialization_Prologue_IMPL; + + pThis->__rmresControlSerialization_Epilogue__ = &rmresControlSerialization_Epilogue_IMPL; + pThis->__rmresControl_Prologue__ = &rmresControl_Prologue_IMPL; pThis->__rmresControl_Epilogue__ = &rmresControl_Epilogue_IMPL; @@ -285,6 +297,10 @@ static void __nvoc_init_funcTable_RmResource_1(RmResource *pThis) { pThis->__nvoc_base_RsResource.__resShareCallback__ = &__nvoc_thunk_RmResource_resShareCallback; + pThis->__nvoc_base_RsResource.__resControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_resControlSerialization_Prologue; + + pThis->__nvoc_base_RsResource.__resControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_resControlSerialization_Epilogue; + pThis->__nvoc_base_RsResource.__resControl_Prologue__ = &__nvoc_thunk_RmResource_resControl_Prologue; pThis->__nvoc_base_RsResource.__resControl_Epilogue__ = &__nvoc_thunk_RmResource_resControl_Epilogue; @@ -335,13 +351,16 @@ NV_STATUS __nvoc_objCreate_RmResource(RmResource **ppThis, Dynamic *pParent, NvU Object *pParentObj; RmResource *pThis; - pThis = portMemAllocNonPaged(sizeof(RmResource)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RmResource), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(RmResource)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RmResource); + pThis->__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -357,11 +376,17 @@ NV_STATUS __nvoc_objCreate_RmResource(RmResource **ppThis, Dynamic *pParent, NvU if (status != NV_OK) goto __nvoc_objCreate_RmResource_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_RmResource_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(RmResource)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_resource_nvoc.h b/src/nvidia/generated/g_resource_nvoc.h index 313ad8530..5e26bb272 100644 --- a/src/nvidia/generated/g_resource_nvoc.h +++ b/src/nvidia/generated/g_resource_nvoc.h @@ -193,6 +193,8 @@ struct RmResource { NV_STATUS (*__rmresGetMemInterMapParams__)(struct RmResource *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__rmresCheckMemInterUnmap__)(struct RmResource *, NvBool); NV_STATUS (*__rmresGetMemoryMappingDescriptor__)(struct RmResource *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__rmresControlSerialization_Prologue__)(struct RmResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__rmresControlSerialization_Epilogue__)(struct RmResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__rmresControl_Prologue__)(struct RmResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__rmresControl_Epilogue__)(struct RmResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__rmresControl__)(struct RmResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -244,6 +246,8 @@ NV_STATUS __nvoc_objCreate_RmResource(RmResource**, Dynamic*, NvU32, struct CALL #define rmresGetMemInterMapParams(pRmResource, pParams) rmresGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define rmresCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) rmresCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define rmresGetMemoryMappingDescriptor(pRmResource, ppMemDesc) rmresGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define rmresControlSerialization_Prologue(pResource, pCallContext, pParams) rmresControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define rmresControlSerialization_Epilogue(pResource, pCallContext, pParams) rmresControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define rmresControl_Prologue(pResource, pCallContext, pParams) rmresControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define rmresControl_Epilogue(pResource, pCallContext, pParams) rmresControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define rmresControl(pResource, pCallContext, pParams) rmresControl_DISPATCH(pResource, pCallContext, pParams) @@ -288,6 +292,18 @@ static inline NV_STATUS rmresGetMemoryMappingDescriptor_DISPATCH(struct RmResour return pRmResource->__rmresGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } +NV_STATUS rmresControlSerialization_Prologue_IMPL(struct RmResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); + +static inline NV_STATUS rmresControlSerialization_Prologue_DISPATCH(struct RmResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__rmresControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +void rmresControlSerialization_Epilogue_IMPL(struct RmResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); + +static inline void rmresControlSerialization_Epilogue_DISPATCH(struct RmResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__rmresControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + NV_STATUS rmresControl_Prologue_IMPL(struct RmResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); static inline NV_STATUS rmresControl_Prologue_DISPATCH(struct RmResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { diff --git a/src/nvidia/generated/g_resserv_nvoc.h b/src/nvidia/generated/g_resserv_nvoc.h index b413afe71..4ef0b2acf 100644 --- a/src/nvidia/generated/g_resserv_nvoc.h +++ b/src/nvidia/generated/g_resserv_nvoc.h @@ -211,6 +211,7 @@ typedef void *PUID_TOKEN; #define RS_LOCK_FLAGS_NO_CUSTOM_LOCK_3 NVBIT(4) #define RS_LOCK_FLAGS_NO_DEPENDANT_SESSION_LOCK NVBIT(5) #define RS_LOCK_FLAGS_FREE_SESSION_LOCK NVBIT(6) +#define RS_LOCK_FLAGS_LOW_PRIORITY NVBIT(7) /// RS_LOCK_STATE #define RS_LOCK_STATE_TOP_LOCK_ACQUIRED NVBIT(0) @@ -317,6 +318,13 @@ struct CALL_CONTEXT RS_LOCK_INFO *pLockInfo; ///< Saved locking context information for the call API_SECURITY_INFO secInfo; RS_RES_CONTROL_PARAMS_INTERNAL *pControlParams; ///< parameters of the call [optional] + + void *pSerializedParams; ///< Serialized version of the params + void *pDeserializedParams; ///< Deserialized version of the params + NvU32 serializedSize; ///< Serialized size + NvU32 deserializedSize; ///< Deserialized size + NvBool bReserialize; ///< Reserialize before calling into GSP + NvBool bRestoreParams; ///< Need to restore pParams }; typedef enum { diff --git a/src/nvidia/generated/g_rg_line_callback_nvoc.c b/src/nvidia/generated/g_rg_line_callback_nvoc.c index 6adffefb8..8bad33a20 100644 --- a/src/nvidia/generated/g_rg_line_callback_nvoc.c +++ b/src/nvidia/generated/g_rg_line_callback_nvoc.c @@ -97,6 +97,54 @@ static NvBool __nvoc_thunk_GpuResource_rglcbShareCallback(struct RgLineCallback return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_RgLineCallback_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } +static NV_STATUS __nvoc_thunk_RmResource_rglcbCheckMemInterUnmap(struct RgLineCallback *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_RgLineCallback_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_rglcbMapTo(struct RgLineCallback *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_rglcbGetMapAddrSpace(struct RgLineCallback *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_RgLineCallback_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_rglcbGetRefCount(struct RgLineCallback *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_rglcbAddAdditionalDependants(struct RsClient *pClient, struct RgLineCallback *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_rglcbControl_Prologue(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_rglcbGetRegBaseOffsetAndSize(struct RgLineCallback *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_RgLineCallback_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_rglcbInternalControlForward(struct RgLineCallback *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_RgLineCallback_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_rglcbUnmapFrom(struct RgLineCallback *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_rglcbControl_Epilogue(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_rglcbControlLookup(struct RgLineCallback *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset), pParams, ppEntry); +} + +static NvHandle __nvoc_thunk_GpuResource_rglcbGetInternalObjectHandle(struct RgLineCallback *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_RgLineCallback_GpuResource.offset)); +} + static NV_STATUS __nvoc_thunk_GpuResource_rglcbControl(struct RgLineCallback *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_RgLineCallback_GpuResource.offset), pCallContext, pParams); } @@ -113,68 +161,28 @@ static NV_STATUS __nvoc_thunk_RmResource_rglcbGetMemoryMappingDescriptor(struct return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_RgLineCallback_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_GpuResource_rglcbGetMapAddrSpace(struct RgLineCallback *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_RgLineCallback_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvHandle __nvoc_thunk_GpuResource_rglcbGetInternalObjectHandle(struct RgLineCallback *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_RgLineCallback_GpuResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_rglcbControlFilter(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_rglcbAddAdditionalDependants(struct RsClient *pClient, struct RgLineCallback *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_rglcbGetRefCount(struct RgLineCallback *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RmResource_rglcbCheckMemInterUnmap(struct RgLineCallback *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_RgLineCallback_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_rglcbMapTo(struct RgLineCallback *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_rglcbControl_Prologue(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_GpuResource_rglcbGetRegBaseOffsetAndSize(struct RgLineCallback *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_RgLineCallback_GpuResource.offset), pGpu, pOffset, pSize); +static NV_STATUS __nvoc_thunk_RmResource_rglcbControlSerialization_Prologue(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_rglcbCanCopy(struct RgLineCallback *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_rglcbInternalControlForward(struct RgLineCallback *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_RgLineCallback_GpuResource.offset), command, pParams, size); -} - static void __nvoc_thunk_RsResource_rglcbPreDestruct(struct RgLineCallback *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_rglcbUnmapFrom(struct RgLineCallback *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_rglcbIsDuplicate(struct RgLineCallback *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset), hMemory, pDuplicate); } -static void __nvoc_thunk_RmResource_rglcbControl_Epilogue(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_rglcbControlLookup(struct RgLineCallback *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_rglcbControlSerialization_Epilogue(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_rglcbMap(struct RgLineCallback *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -226,6 +234,30 @@ static void __nvoc_init_funcTable_RgLineCallback_1(RgLineCallback *pThis) { pThis->__rglcbShareCallback__ = &__nvoc_thunk_GpuResource_rglcbShareCallback; + pThis->__rglcbCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_rglcbCheckMemInterUnmap; + + pThis->__rglcbMapTo__ = &__nvoc_thunk_RsResource_rglcbMapTo; + + pThis->__rglcbGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_rglcbGetMapAddrSpace; + + pThis->__rglcbGetRefCount__ = &__nvoc_thunk_RsResource_rglcbGetRefCount; + + pThis->__rglcbAddAdditionalDependants__ = &__nvoc_thunk_RsResource_rglcbAddAdditionalDependants; + + pThis->__rglcbControl_Prologue__ = &__nvoc_thunk_RmResource_rglcbControl_Prologue; + + pThis->__rglcbGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_rglcbGetRegBaseOffsetAndSize; + + pThis->__rglcbInternalControlForward__ = &__nvoc_thunk_GpuResource_rglcbInternalControlForward; + + pThis->__rglcbUnmapFrom__ = &__nvoc_thunk_RsResource_rglcbUnmapFrom; + + pThis->__rglcbControl_Epilogue__ = &__nvoc_thunk_RmResource_rglcbControl_Epilogue; + + pThis->__rglcbControlLookup__ = &__nvoc_thunk_RsResource_rglcbControlLookup; + + pThis->__rglcbGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_rglcbGetInternalObjectHandle; + pThis->__rglcbControl__ = &__nvoc_thunk_GpuResource_rglcbControl; pThis->__rglcbUnmap__ = &__nvoc_thunk_GpuResource_rglcbUnmap; @@ -234,37 +266,17 @@ static void __nvoc_init_funcTable_RgLineCallback_1(RgLineCallback *pThis) { pThis->__rglcbGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_rglcbGetMemoryMappingDescriptor; - pThis->__rglcbGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_rglcbGetMapAddrSpace; - - pThis->__rglcbGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_rglcbGetInternalObjectHandle; - pThis->__rglcbControlFilter__ = &__nvoc_thunk_RsResource_rglcbControlFilter; - pThis->__rglcbAddAdditionalDependants__ = &__nvoc_thunk_RsResource_rglcbAddAdditionalDependants; - - pThis->__rglcbGetRefCount__ = &__nvoc_thunk_RsResource_rglcbGetRefCount; - - pThis->__rglcbCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_rglcbCheckMemInterUnmap; - - pThis->__rglcbMapTo__ = &__nvoc_thunk_RsResource_rglcbMapTo; - - pThis->__rglcbControl_Prologue__ = &__nvoc_thunk_RmResource_rglcbControl_Prologue; - - pThis->__rglcbGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_rglcbGetRegBaseOffsetAndSize; + pThis->__rglcbControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_rglcbControlSerialization_Prologue; pThis->__rglcbCanCopy__ = &__nvoc_thunk_RsResource_rglcbCanCopy; - pThis->__rglcbInternalControlForward__ = &__nvoc_thunk_GpuResource_rglcbInternalControlForward; - pThis->__rglcbPreDestruct__ = &__nvoc_thunk_RsResource_rglcbPreDestruct; - pThis->__rglcbUnmapFrom__ = &__nvoc_thunk_RsResource_rglcbUnmapFrom; - pThis->__rglcbIsDuplicate__ = &__nvoc_thunk_RsResource_rglcbIsDuplicate; - pThis->__rglcbControl_Epilogue__ = &__nvoc_thunk_RmResource_rglcbControl_Epilogue; - - pThis->__rglcbControlLookup__ = &__nvoc_thunk_RsResource_rglcbControlLookup; + pThis->__rglcbControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_rglcbControlSerialization_Epilogue; pThis->__rglcbMap__ = &__nvoc_thunk_GpuResource_rglcbMap; @@ -292,13 +304,16 @@ NV_STATUS __nvoc_objCreate_RgLineCallback(RgLineCallback **ppThis, Dynamic *pPar Object *pParentObj; RgLineCallback *pThis; - pThis = portMemAllocNonPaged(sizeof(RgLineCallback)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RgLineCallback), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(RgLineCallback)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RgLineCallback); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -314,11 +329,17 @@ NV_STATUS __nvoc_objCreate_RgLineCallback(RgLineCallback **ppThis, Dynamic *pPar if (status != NV_OK) goto __nvoc_objCreate_RgLineCallback_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_RgLineCallback_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(RgLineCallback)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_rg_line_callback_nvoc.h b/src/nvidia/generated/g_rg_line_callback_nvoc.h index 8aeefe52d..2161d83eb 100644 --- a/src/nvidia/generated/g_rg_line_callback_nvoc.h +++ b/src/nvidia/generated/g_rg_line_callback_nvoc.h @@ -68,26 +68,28 @@ struct RgLineCallback { struct GpuResource *__nvoc_pbase_GpuResource; struct RgLineCallback *__nvoc_pbase_RgLineCallback; NvBool (*__rglcbShareCallback__)(struct RgLineCallback *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__rglcbCheckMemInterUnmap__)(struct RgLineCallback *, NvBool); + NV_STATUS (*__rglcbMapTo__)(struct RgLineCallback *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__rglcbGetMapAddrSpace__)(struct RgLineCallback *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__rglcbGetRefCount__)(struct RgLineCallback *); + void (*__rglcbAddAdditionalDependants__)(struct RsClient *, struct RgLineCallback *, RsResourceRef *); + NV_STATUS (*__rglcbControl_Prologue__)(struct RgLineCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__rglcbGetRegBaseOffsetAndSize__)(struct RgLineCallback *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__rglcbInternalControlForward__)(struct RgLineCallback *, NvU32, void *, NvU32); + NV_STATUS (*__rglcbUnmapFrom__)(struct RgLineCallback *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__rglcbControl_Epilogue__)(struct RgLineCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__rglcbControlLookup__)(struct RgLineCallback *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__rglcbGetInternalObjectHandle__)(struct RgLineCallback *); NV_STATUS (*__rglcbControl__)(struct RgLineCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__rglcbUnmap__)(struct RgLineCallback *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__rglcbGetMemInterMapParams__)(struct RgLineCallback *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__rglcbGetMemoryMappingDescriptor__)(struct RgLineCallback *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__rglcbGetMapAddrSpace__)(struct RgLineCallback *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__rglcbGetInternalObjectHandle__)(struct RgLineCallback *); NV_STATUS (*__rglcbControlFilter__)(struct RgLineCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__rglcbAddAdditionalDependants__)(struct RsClient *, struct RgLineCallback *, RsResourceRef *); - NvU32 (*__rglcbGetRefCount__)(struct RgLineCallback *); - NV_STATUS (*__rglcbCheckMemInterUnmap__)(struct RgLineCallback *, NvBool); - NV_STATUS (*__rglcbMapTo__)(struct RgLineCallback *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__rglcbControl_Prologue__)(struct RgLineCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__rglcbGetRegBaseOffsetAndSize__)(struct RgLineCallback *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__rglcbControlSerialization_Prologue__)(struct RgLineCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__rglcbCanCopy__)(struct RgLineCallback *); - NV_STATUS (*__rglcbInternalControlForward__)(struct RgLineCallback *, NvU32, void *, NvU32); void (*__rglcbPreDestruct__)(struct RgLineCallback *); - NV_STATUS (*__rglcbUnmapFrom__)(struct RgLineCallback *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__rglcbIsDuplicate__)(struct RgLineCallback *, NvHandle, NvBool *); - void (*__rglcbControl_Epilogue__)(struct RgLineCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__rglcbControlLookup__)(struct RgLineCallback *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__rglcbControlSerialization_Epilogue__)(struct RgLineCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__rglcbMap__)(struct RgLineCallback *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__rglcbAccessCallback__)(struct RgLineCallback *, struct RsClient *, void *, RsAccessRight); NvU32 subDeviceInstance; @@ -128,32 +130,82 @@ NV_STATUS __nvoc_objCreate_RgLineCallback(RgLineCallback**, Dynamic*, NvU32, str __nvoc_objCreate_RgLineCallback((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) #define rglcbShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) rglcbShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define rglcbCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) rglcbCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define rglcbMapTo(pResource, pParams) rglcbMapTo_DISPATCH(pResource, pParams) +#define rglcbGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) rglcbGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define rglcbGetRefCount(pResource) rglcbGetRefCount_DISPATCH(pResource) +#define rglcbAddAdditionalDependants(pClient, pResource, pReference) rglcbAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define rglcbControl_Prologue(pResource, pCallContext, pParams) rglcbControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define rglcbGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) rglcbGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define rglcbInternalControlForward(pGpuResource, command, pParams, size) rglcbInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define rglcbUnmapFrom(pResource, pParams) rglcbUnmapFrom_DISPATCH(pResource, pParams) +#define rglcbControl_Epilogue(pResource, pCallContext, pParams) rglcbControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define rglcbControlLookup(pResource, pParams, ppEntry) rglcbControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define rglcbGetInternalObjectHandle(pGpuResource) rglcbGetInternalObjectHandle_DISPATCH(pGpuResource) #define rglcbControl(pGpuResource, pCallContext, pParams) rglcbControl_DISPATCH(pGpuResource, pCallContext, pParams) #define rglcbUnmap(pGpuResource, pCallContext, pCpuMapping) rglcbUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define rglcbGetMemInterMapParams(pRmResource, pParams) rglcbGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define rglcbGetMemoryMappingDescriptor(pRmResource, ppMemDesc) rglcbGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define rglcbGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) rglcbGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define rglcbGetInternalObjectHandle(pGpuResource) rglcbGetInternalObjectHandle_DISPATCH(pGpuResource) #define rglcbControlFilter(pResource, pCallContext, pParams) rglcbControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define rglcbAddAdditionalDependants(pClient, pResource, pReference) rglcbAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define rglcbGetRefCount(pResource) rglcbGetRefCount_DISPATCH(pResource) -#define rglcbCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) rglcbCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define rglcbMapTo(pResource, pParams) rglcbMapTo_DISPATCH(pResource, pParams) -#define rglcbControl_Prologue(pResource, pCallContext, pParams) rglcbControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define rglcbGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) rglcbGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define rglcbControlSerialization_Prologue(pResource, pCallContext, pParams) rglcbControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define rglcbCanCopy(pResource) rglcbCanCopy_DISPATCH(pResource) -#define rglcbInternalControlForward(pGpuResource, command, pParams, size) rglcbInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define rglcbPreDestruct(pResource) rglcbPreDestruct_DISPATCH(pResource) -#define rglcbUnmapFrom(pResource, pParams) rglcbUnmapFrom_DISPATCH(pResource, pParams) #define rglcbIsDuplicate(pResource, hMemory, pDuplicate) rglcbIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) -#define rglcbControl_Epilogue(pResource, pCallContext, pParams) rglcbControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define rglcbControlLookup(pResource, pParams, ppEntry) rglcbControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define rglcbControlSerialization_Epilogue(pResource, pCallContext, pParams) rglcbControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define rglcbMap(pGpuResource, pCallContext, pParams, pCpuMapping) rglcbMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define rglcbAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) rglcbAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) static inline NvBool rglcbShareCallback_DISPATCH(struct RgLineCallback *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__rglcbShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } +static inline NV_STATUS rglcbCheckMemInterUnmap_DISPATCH(struct RgLineCallback *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__rglcbCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS rglcbMapTo_DISPATCH(struct RgLineCallback *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__rglcbMapTo__(pResource, pParams); +} + +static inline NV_STATUS rglcbGetMapAddrSpace_DISPATCH(struct RgLineCallback *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__rglcbGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 rglcbGetRefCount_DISPATCH(struct RgLineCallback *pResource) { + return pResource->__rglcbGetRefCount__(pResource); +} + +static inline void rglcbAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct RgLineCallback *pResource, RsResourceRef *pReference) { + pResource->__rglcbAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS rglcbControl_Prologue_DISPATCH(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__rglcbControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS rglcbGetRegBaseOffsetAndSize_DISPATCH(struct RgLineCallback *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__rglcbGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS rglcbInternalControlForward_DISPATCH(struct RgLineCallback *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__rglcbInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS rglcbUnmapFrom_DISPATCH(struct RgLineCallback *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__rglcbUnmapFrom__(pResource, pParams); +} + +static inline void rglcbControl_Epilogue_DISPATCH(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__rglcbControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS rglcbControlLookup_DISPATCH(struct RgLineCallback *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__rglcbControlLookup__(pResource, pParams, ppEntry); +} + +static inline NvHandle rglcbGetInternalObjectHandle_DISPATCH(struct RgLineCallback *pGpuResource) { + return pGpuResource->__rglcbGetInternalObjectHandle__(pGpuResource); +} + static inline NV_STATUS rglcbControl_DISPATCH(struct RgLineCallback *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pGpuResource->__rglcbControl__(pGpuResource, pCallContext, pParams); } @@ -170,68 +222,28 @@ static inline NV_STATUS rglcbGetMemoryMappingDescriptor_DISPATCH(struct RgLineCa return pRmResource->__rglcbGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS rglcbGetMapAddrSpace_DISPATCH(struct RgLineCallback *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__rglcbGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvHandle rglcbGetInternalObjectHandle_DISPATCH(struct RgLineCallback *pGpuResource) { - return pGpuResource->__rglcbGetInternalObjectHandle__(pGpuResource); -} - static inline NV_STATUS rglcbControlFilter_DISPATCH(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__rglcbControlFilter__(pResource, pCallContext, pParams); } -static inline void rglcbAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct RgLineCallback *pResource, RsResourceRef *pReference) { - pResource->__rglcbAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 rglcbGetRefCount_DISPATCH(struct RgLineCallback *pResource) { - return pResource->__rglcbGetRefCount__(pResource); -} - -static inline NV_STATUS rglcbCheckMemInterUnmap_DISPATCH(struct RgLineCallback *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__rglcbCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS rglcbMapTo_DISPATCH(struct RgLineCallback *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__rglcbMapTo__(pResource, pParams); -} - -static inline NV_STATUS rglcbControl_Prologue_DISPATCH(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__rglcbControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS rglcbGetRegBaseOffsetAndSize_DISPATCH(struct RgLineCallback *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__rglcbGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +static inline NV_STATUS rglcbControlSerialization_Prologue_DISPATCH(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__rglcbControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool rglcbCanCopy_DISPATCH(struct RgLineCallback *pResource) { return pResource->__rglcbCanCopy__(pResource); } -static inline NV_STATUS rglcbInternalControlForward_DISPATCH(struct RgLineCallback *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__rglcbInternalControlForward__(pGpuResource, command, pParams, size); -} - static inline void rglcbPreDestruct_DISPATCH(struct RgLineCallback *pResource) { pResource->__rglcbPreDestruct__(pResource); } -static inline NV_STATUS rglcbUnmapFrom_DISPATCH(struct RgLineCallback *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__rglcbUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS rglcbIsDuplicate_DISPATCH(struct RgLineCallback *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__rglcbIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline void rglcbControl_Epilogue_DISPATCH(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__rglcbControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS rglcbControlLookup_DISPATCH(struct RgLineCallback *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__rglcbControlLookup__(pResource, pParams, ppEntry); +static inline void rglcbControlSerialization_Epilogue_DISPATCH(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__rglcbControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS rglcbMap_DISPATCH(struct RgLineCallback *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_rpc-structures.h b/src/nvidia/generated/g_rpc-structures.h index 033be35aa..3afbb3cc7 100644 --- a/src/nvidia/generated/g_rpc-structures.h +++ b/src/nvidia/generated/g_rpc-structures.h @@ -104,7 +104,7 @@ typedef rpc_idle_channels_v03_00 rpc_idle_channels_v; typedef struct rpc_unloading_guest_driver_v1F_07 { - NvBool bSuspend; + NvBool bInPMTransition; NvBool bGc6Entering; NvU32 newLevel; } rpc_unloading_guest_driver_v1F_07; @@ -480,6 +480,13 @@ typedef struct rpc_nvlink_is_gpu_degraded_v17_00 typedef rpc_nvlink_is_gpu_degraded_v17_00 rpc_nvlink_is_gpu_degraded_v; +typedef struct rpc_gsp_send_user_shared_data_v17_00 +{ + NvU32 data; +} rpc_gsp_send_user_shared_data_v17_00; + +typedef rpc_gsp_send_user_shared_data_v17_00 rpc_gsp_send_user_shared_data_v; + typedef struct rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 { NvU32 sysmemPfnBitmapRing; @@ -790,8 +797,8 @@ static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_unloading_guest_driver_v03_00 = { static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_unloading_guest_driver_v1F_07[] = { { .vtype = vtype_NvBool, - .offset = NV_OFFSETOF(rpc_unloading_guest_driver_v1F_07, bSuspend), - .name = "bSuspend" + .offset = NV_OFFSETOF(rpc_unloading_guest_driver_v1F_07, bInPMTransition), + .name = "bInPMTransition" }, { .vtype = vtype_NvBool, @@ -2058,6 +2065,25 @@ static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_is_gpu_degraded_v17_00 = { }; #endif +#ifndef SKIP_PRINT_rpc_gsp_send_user_shared_data_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_send_user_shared_data_v17_00[] = { + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_gsp_send_user_shared_data_v17_00, data), + .name = "data" + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gsp_send_user_shared_data_v17_00 = { + .name = "rpc_gsp_send_user_shared_data", + .header_length = NV_SIZEOF32(rpc_gsp_send_user_shared_data_v17_00), + .fdesc = vmiopd_fdesc_t_rpc_gsp_send_user_shared_data_v17_00 +}; +#endif + #ifndef SKIP_PRINT_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00[] = { { @@ -2551,6 +2577,13 @@ vmiopd_mdesc_t *rpcdebugNvlinkIsGpuDegraded_v17_00(void) } #endif +#ifndef SKIP_PRINT_rpc_gsp_send_user_shared_data_v17_00 +vmiopd_mdesc_t *rpcdebugGspSendUserSharedData_v17_00(void) +{ + return &vmiopd_mdesc_t_rpc_gsp_send_user_shared_data_v17_00; +} +#endif + #ifndef SKIP_PRINT_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 vmiopd_mdesc_t *rpcdebugSetSysmemDirtyPageTrackingBuffer_v20_00(void) { @@ -2683,6 +2716,8 @@ typedef union rpc_generic_union { rpc_nvlink_inband_received_data_4096_v nvlink_inband_received_data_4096_v; rpc_nvlink_is_gpu_degraded_v17_00 nvlink_is_gpu_degraded_v17_00; rpc_nvlink_is_gpu_degraded_v nvlink_is_gpu_degraded_v; + rpc_gsp_send_user_shared_data_v17_00 gsp_send_user_shared_data_v17_00; + rpc_gsp_send_user_shared_data_v gsp_send_user_shared_data_v; rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 set_sysmem_dirty_page_tracking_buffer_v20_00; rpc_set_sysmem_dirty_page_tracking_buffer_v set_sysmem_dirty_page_tracking_buffer_v; rpc_extdev_intr_service_v17_00 extdev_intr_service_v17_00; diff --git a/src/nvidia/generated/g_rpc_iom.c b/src/nvidia/generated/g_rpc_iom.c index 45dfd15c4..c66f6c48c 100644 --- a/src/nvidia/generated/g_rpc_iom.c +++ b/src/nvidia/generated/g_rpc_iom.c @@ -41,7 +41,7 @@ void rpcObjIfacesSetup(OBJRPC *pRpc) // pRpcMethods->__rpcRecvPollUvm__ = rpcRecvPollUvm_IMPL; # ONLY_IF => VIRTUALIZATION } -void +static void rpcSetPropertiesSpecial ( POBJRPC pRpc diff --git a/src/nvidia/generated/g_rpc_private.h b/src/nvidia/generated/g_rpc_private.h index eacc456ae..fc7e64c2d 100644 --- a/src/nvidia/generated/g_rpc_private.h +++ b/src/nvidia/generated/g_rpc_private.h @@ -2351,6 +2351,23 @@ static void rpc_iGrp_ipVersions_Install_v21_0B(IGRP_IP_VERSIONS_TABLE_INFO *pInf #endif // } +// No enabled chips use this variant provider +static void rpc_iGrp_ipVersions_Install_v22_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; + RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcHal += 0; + + +#endif // +} + @@ -2860,6 +2877,9 @@ static NV_STATUS rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v21_0B[] = { { 0x210B0000, 0xFFFFFFFF, }, // }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v22_01[] = { + { 0x22010000, 0xFFFFFFFF, }, // + }; #define _RPC_HAL_IGRP_ENTRY_INIT(v) \ { RPC_IGRP_IP_VERSIONS_RANGES_##v, NV_ARRAY_ELEMENTS(RPC_IGRP_IP_VERSIONS_RANGES_##v), rpc_iGrp_ipVersions_Install_##v, } @@ -2996,6 +3016,7 @@ static NV_STATUS rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) _RPC_HAL_IGRP_ENTRY_INIT(v21_09), // _RPC_HAL_IGRP_ENTRY_INIT(v21_0A), // _RPC_HAL_IGRP_ENTRY_INIT(v21_0B), // + _RPC_HAL_IGRP_ENTRY_INIT(v22_01), // }; #undef _RPC_HAL_IGRP_ENTRY_INIT diff --git a/src/nvidia/generated/g_rs_client_nvoc.c b/src/nvidia/generated/g_rs_client_nvoc.c index 33eeb681d..bb29043f7 100644 --- a/src/nvidia/generated/g_rs_client_nvoc.c +++ b/src/nvidia/generated/g_rs_client_nvoc.c @@ -136,13 +136,16 @@ NV_STATUS __nvoc_objCreate_RsClient(RsClient **ppThis, Dynamic *pParent, NvU32 c Object *pParentObj; RsClient *pThis; - pThis = portMemAllocNonPaged(sizeof(RsClient)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RsClient), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(RsClient)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RsClient); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -158,11 +161,17 @@ NV_STATUS __nvoc_objCreate_RsClient(RsClient **ppThis, Dynamic *pParent, NvU32 c if (status != NV_OK) goto __nvoc_objCreate_RsClient_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_RsClient_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(RsClient)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -263,6 +272,10 @@ static void __nvoc_thunk_RsResource_clientresAddAdditionalDependants(struct RsCl resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RsClientResource_RsResource.offset), pReference); } +static NV_STATUS __nvoc_thunk_RsResource_clientresControlSerialization_Prologue(struct RsClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlSerialization_Prologue((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RsClientResource_RsResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_clientresCanCopy(struct RsClientResource *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RsClientResource_RsResource.offset)); } @@ -283,6 +296,10 @@ static NV_STATUS __nvoc_thunk_RsResource_clientresIsDuplicate(struct RsClientRes return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RsClientResource_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RsResource_clientresControlSerialization_Epilogue(struct RsClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + resControlSerialization_Epilogue((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RsClientResource_RsResource.offset), pCallContext, pParams); +} + static void __nvoc_thunk_RsResource_clientresControl_Epilogue(struct RsClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { resControl_Epilogue((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RsClientResource_RsResource.offset), pCallContext, pParams); } @@ -352,6 +369,8 @@ static void __nvoc_init_funcTable_RsClientResource_1(RsClientResource *pThis) { pThis->__clientresAddAdditionalDependants__ = &__nvoc_thunk_RsResource_clientresAddAdditionalDependants; + pThis->__clientresControlSerialization_Prologue__ = &__nvoc_thunk_RsResource_clientresControlSerialization_Prologue; + pThis->__clientresCanCopy__ = &__nvoc_thunk_RsResource_clientresCanCopy; pThis->__clientresControl_Prologue__ = &__nvoc_thunk_RsResource_clientresControl_Prologue; @@ -362,6 +381,8 @@ static void __nvoc_init_funcTable_RsClientResource_1(RsClientResource *pThis) { pThis->__clientresIsDuplicate__ = &__nvoc_thunk_RsResource_clientresIsDuplicate; + pThis->__clientresControlSerialization_Epilogue__ = &__nvoc_thunk_RsResource_clientresControlSerialization_Epilogue; + pThis->__clientresControl_Epilogue__ = &__nvoc_thunk_RsResource_clientresControl_Epilogue; pThis->__clientresControlLookup__ = &__nvoc_thunk_RsResource_clientresControlLookup; @@ -389,13 +410,16 @@ NV_STATUS __nvoc_objCreate_RsClientResource(RsClientResource **ppThis, Dynamic * Object *pParentObj; RsClientResource *pThis; - pThis = portMemAllocNonPaged(sizeof(RsClientResource)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RsClientResource), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(RsClientResource)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RsClientResource); + pThis->__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -411,11 +435,17 @@ NV_STATUS __nvoc_objCreate_RsClientResource(RsClientResource **ppThis, Dynamic * if (status != NV_OK) goto __nvoc_objCreate_RsClientResource_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_RsClientResource_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(RsClientResource)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_rs_client_nvoc.h b/src/nvidia/generated/g_rs_client_nvoc.h index 0607b2576..4eeda2d3c 100644 --- a/src/nvidia/generated/g_rs_client_nvoc.h +++ b/src/nvidia/generated/g_rs_client_nvoc.h @@ -94,6 +94,8 @@ struct RsClient { CLIENT_TYPE type; NvBool bActive; NvBool bResourceWarning; + NvBool bDisabled; + NvBool bHighPriorityFreeDone; RsRefMap resourceMap; AccessBackRefList accessBackRefList; NvHandle handleRangeStart; @@ -102,6 +104,7 @@ struct RsClient { NvHandle handleGenIdx; RsRefFreeList pendingFreeList; struct RS_FREE_STACK *pFreeStack; + struct ListNode disabledClientNode; }; #ifndef __NVOC_CLASS_RsClient_TYPEDEF__ @@ -392,6 +395,7 @@ static inline NV_STATUS clientSetRestrictedRange(struct RsClient *pClient, NvHan #undef PRIVATE_FIELD +MAKE_INTRUSIVE_LIST(RsDisabledClientList, RsClient, disabledClientNode); /** * Get an iterator to the elements in the client's resource map @@ -434,6 +438,14 @@ RS_ORDERED_ITERATOR clientRefOrderedIter(struct RsClient *pClient, RsResourceRef */ NvBool clientRefOrderedIterNext(struct RsClient *pClient, RS_ORDERED_ITERATOR *pIt); +/** + * Release all CPU address mappings for a resource + * + * @param[in] pClient Client that owns the resource + * @param[in] pCallContext Caller information (which includes the resource reference whose mappings will be freed) + * @param[in] pLockInfo Information about which locks are already held, for recursive calls + */ +NV_STATUS clientUnmapResourceRefMappings(struct RsClient *pClient, CALL_CONTEXT *pCallContext, RS_LOCK_INFO *pLockInfo); /** * RsResource interface to a RsClient @@ -467,11 +479,13 @@ struct RsClientResource { NvU32 (*__clientresGetRefCount__)(struct RsClientResource *); NV_STATUS (*__clientresControlFilter__)(struct RsClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__clientresAddAdditionalDependants__)(struct RsClient *, struct RsClientResource *, RsResourceRef *); + NV_STATUS (*__clientresControlSerialization_Prologue__)(struct RsClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__clientresCanCopy__)(struct RsClientResource *); NV_STATUS (*__clientresControl_Prologue__)(struct RsClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__clientresPreDestruct__)(struct RsClientResource *); NV_STATUS (*__clientresUnmapFrom__)(struct RsClientResource *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__clientresIsDuplicate__)(struct RsClientResource *, NvHandle, NvBool *); + void (*__clientresControlSerialization_Epilogue__)(struct RsClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__clientresControl_Epilogue__)(struct RsClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__clientresControlLookup__)(struct RsClientResource *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__clientresMap__)(struct RsClientResource *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -514,11 +528,13 @@ NV_STATUS __nvoc_objCreate_RsClientResource(RsClientResource**, Dynamic*, NvU32, #define clientresGetRefCount(pResource) clientresGetRefCount_DISPATCH(pResource) #define clientresControlFilter(pResource, pCallContext, pParams) clientresControlFilter_DISPATCH(pResource, pCallContext, pParams) #define clientresAddAdditionalDependants(pClient, pResource, pReference) clientresAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define clientresControlSerialization_Prologue(pResource, pCallContext, pParams) clientresControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define clientresCanCopy(pResource) clientresCanCopy_DISPATCH(pResource) #define clientresControl_Prologue(pResource, pCallContext, pParams) clientresControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define clientresPreDestruct(pResource) clientresPreDestruct_DISPATCH(pResource) #define clientresUnmapFrom(pResource, pParams) clientresUnmapFrom_DISPATCH(pResource, pParams) #define clientresIsDuplicate(pResource, hMemory, pDuplicate) clientresIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define clientresControlSerialization_Epilogue(pResource, pCallContext, pParams) clientresControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define clientresControl_Epilogue(pResource, pCallContext, pParams) clientresControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define clientresControlLookup(pResource, pParams, ppEntry) clientresControlLookup_DISPATCH(pResource, pParams, ppEntry) #define clientresMap(pResource, pCallContext, pParams, pCpuMapping) clientresMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -551,6 +567,10 @@ static inline void clientresAddAdditionalDependants_DISPATCH(struct RsClient *pC pResource->__clientresAddAdditionalDependants__(pClient, pResource, pReference); } +static inline NV_STATUS clientresControlSerialization_Prologue_DISPATCH(struct RsClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__clientresControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool clientresCanCopy_DISPATCH(struct RsClientResource *pResource) { return pResource->__clientresCanCopy__(pResource); } @@ -571,6 +591,10 @@ static inline NV_STATUS clientresIsDuplicate_DISPATCH(struct RsClientResource *p return pResource->__clientresIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void clientresControlSerialization_Epilogue_DISPATCH(struct RsClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__clientresControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline void clientresControl_Epilogue_DISPATCH(struct RsClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__clientresControl_Epilogue__(pResource, pCallContext, pParams); } @@ -604,6 +628,7 @@ struct RS_CLIENT_FREE_PARAMS_INTERNAL NvHandle hDomain; ///< [in] The parent domain NvHandle hClient; ///< [in] The client handle NvBool bHiPriOnly; ///< [in] Only free high priority resources + NvBool bDisableOnly; ///< [in] Only disable the listed clients, do not free them yet NvU32 state; ///< [in] User-defined state RS_RES_FREE_PARAMS_INTERNAL *pResFreeParams; ///< [in] Necessary for locking state diff --git a/src/nvidia/generated/g_rs_resource_nvoc.c b/src/nvidia/generated/g_rs_resource_nvoc.c index e0951164d..a5865a3a3 100644 --- a/src/nvidia/generated/g_rs_resource_nvoc.c +++ b/src/nvidia/generated/g_rs_resource_nvoc.c @@ -108,6 +108,10 @@ static void __nvoc_init_funcTable_RsResource_1(RsResource *pThis) { pThis->__resControlFilter__ = &resControlFilter_IMPL; + pThis->__resControlSerialization_Prologue__ = &resControlSerialization_Prologue_IMPL; + + pThis->__resControlSerialization_Epilogue__ = &resControlSerialization_Epilogue_IMPL; + pThis->__resControl_Prologue__ = &resControl_Prologue_IMPL; pThis->__resControl_Epilogue__ = &resControl_Epilogue_IMPL; @@ -146,13 +150,16 @@ NV_STATUS __nvoc_objCreate_RsResource(RsResource **ppThis, Dynamic *pParent, NvU Object *pParentObj; RsResource *pThis; - pThis = portMemAllocNonPaged(sizeof(RsResource)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RsResource), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(RsResource)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RsResource); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -168,11 +175,17 @@ NV_STATUS __nvoc_objCreate_RsResource(RsResource **ppThis, Dynamic *pParent, NvU if (status != NV_OK) goto __nvoc_objCreate_RsResource_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_RsResource_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(RsResource)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_rs_resource_nvoc.h b/src/nvidia/generated/g_rs_resource_nvoc.h index fc5d58903..433cb4632 100644 --- a/src/nvidia/generated/g_rs_resource_nvoc.h +++ b/src/nvidia/generated/g_rs_resource_nvoc.h @@ -159,6 +159,7 @@ struct RS_RES_FREE_PARAMS_INTERNAL // Internal use only NvBool bHiPriOnly; ///< [in] Only free if this is a high priority resources + NvBool bDisableOnly; ///< [in] Disable the target instead of freeing it (only applies to clients) RS_LOCK_INFO *pLockInfo; ///< [inout] Locking flags and state NvU32 freeFlags; ///< [in] Flags for the free operation NvU32 freeState; ///< [inout] Free state @@ -249,6 +250,8 @@ struct RsResource { NV_STATUS (*__resControlLookup__)(struct RsResource *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__resControl__)(struct RsResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__resControlFilter__)(struct RsResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__resControlSerialization_Prologue__)(struct RsResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__resControlSerialization_Epilogue__)(struct RsResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__resControl_Prologue__)(struct RsResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__resControl_Epilogue__)(struct RsResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__resMap__)(struct RsResource *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -298,6 +301,8 @@ NV_STATUS __nvoc_objCreate_RsResource(RsResource**, Dynamic*, NvU32, struct CALL #define resControlLookup(pResource, pParams, ppEntry) resControlLookup_DISPATCH(pResource, pParams, ppEntry) #define resControl(pResource, pCallContext, pParams) resControl_DISPATCH(pResource, pCallContext, pParams) #define resControlFilter(pResource, pCallContext, pParams) resControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define resControlSerialization_Prologue(pResource, pCallContext, pParams) resControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define resControlSerialization_Epilogue(pResource, pCallContext, pParams) resControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define resControl_Prologue(pResource, pCallContext, pParams) resControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define resControl_Epilogue(pResource, pCallContext, pParams) resControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define resMap(pResource, pCallContext, pParams, pCpuMapping) resMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -344,6 +349,18 @@ static inline NV_STATUS resControlFilter_DISPATCH(struct RsResource *pResource, return pResource->__resControlFilter__(pResource, pCallContext, pParams); } +NV_STATUS resControlSerialization_Prologue_IMPL(struct RsResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); + +static inline NV_STATUS resControlSerialization_Prologue_DISPATCH(struct RsResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__resControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +void resControlSerialization_Epilogue_IMPL(struct RsResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); + +static inline void resControlSerialization_Epilogue_DISPATCH(struct RsResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__resControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + NV_STATUS resControl_Prologue_IMPL(struct RsResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); static inline NV_STATUS resControl_Prologue_DISPATCH(struct RsResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { diff --git a/src/nvidia/generated/g_rs_server_nvoc.c b/src/nvidia/generated/g_rs_server_nvoc.c index 2af2871c4..b6306ee35 100644 --- a/src/nvidia/generated/g_rs_server_nvoc.c +++ b/src/nvidia/generated/g_rs_server_nvoc.c @@ -114,13 +114,16 @@ NV_STATUS __nvoc_objCreate_RsShared(RsShared **ppThis, Dynamic *pParent, NvU32 c Object *pParentObj; RsShared *pThis; - pThis = portMemAllocNonPaged(sizeof(RsShared)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RsShared), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(RsShared)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RsShared); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -136,11 +139,17 @@ NV_STATUS __nvoc_objCreate_RsShared(RsShared **ppThis, Dynamic *pParent, NvU32 c if (status != NV_OK) goto __nvoc_objCreate_RsShared_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_RsShared_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(RsShared)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -273,13 +282,16 @@ NV_STATUS __nvoc_objCreate_RsSession(RsSession **ppThis, Dynamic *pParent, NvU32 Object *pParentObj; RsSession *pThis; - pThis = portMemAllocNonPaged(sizeof(RsSession)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RsSession), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(RsSession)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RsSession); + pThis->__nvoc_base_RsShared.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -295,11 +307,17 @@ NV_STATUS __nvoc_objCreate_RsSession(RsSession **ppThis, Dynamic *pParent, NvU32 if (status != NV_OK) goto __nvoc_objCreate_RsSession_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_RsSession_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(RsSession)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_rs_server_nvoc.h b/src/nvidia/generated/g_rs_server_nvoc.h index 71c01dcb6..5b32c882c 100644 --- a/src/nvidia/generated/g_rs_server_nvoc.h +++ b/src/nvidia/generated/g_rs_server_nvoc.h @@ -36,6 +36,7 @@ extern "C" { #include "nvport/nvport.h" #include "resserv/resserv.h" +#include "resserv/rs_client.h" #include "nvoc/runtime.h" #ifdef __cplusplus @@ -135,8 +136,8 @@ struct RsSession { struct Object *__nvoc_pbase_Object; struct RsShared *__nvoc_pbase_RsShared; struct RsSession *__nvoc_pbase_RsSession; - void (*__sessionRemoveDependant__)(struct RsSession *, RsResourceRef *); - void (*__sessionRemoveDependency__)(struct RsSession *, RsResourceRef *); + void (*__sessionRemoveDependant__)(struct RsSession *, struct RsResourceRef *); + void (*__sessionRemoveDependency__)(struct RsSession *, struct RsResourceRef *); PORT_RWLOCK *pLock; NvBool bValid; RsResourceRefList dependencies; @@ -173,15 +174,15 @@ NV_STATUS __nvoc_objCreate_RsSession(RsSession**, Dynamic*, NvU32); #define sessionRemoveDependant(pSession, pResourceRef) sessionRemoveDependant_DISPATCH(pSession, pResourceRef) #define sessionRemoveDependency(pSession, pResourceRef) sessionRemoveDependency_DISPATCH(pSession, pResourceRef) -void sessionRemoveDependant_IMPL(struct RsSession *pSession, RsResourceRef *pResourceRef); +void sessionRemoveDependant_IMPL(struct RsSession *pSession, struct RsResourceRef *pResourceRef); -static inline void sessionRemoveDependant_DISPATCH(struct RsSession *pSession, RsResourceRef *pResourceRef) { +static inline void sessionRemoveDependant_DISPATCH(struct RsSession *pSession, struct RsResourceRef *pResourceRef) { pSession->__sessionRemoveDependant__(pSession, pResourceRef); } -void sessionRemoveDependency_IMPL(struct RsSession *pSession, RsResourceRef *pResourceRef); +void sessionRemoveDependency_IMPL(struct RsSession *pSession, struct RsResourceRef *pResourceRef); -static inline void sessionRemoveDependency_DISPATCH(struct RsSession *pSession, RsResourceRef *pResourceRef) { +static inline void sessionRemoveDependency_DISPATCH(struct RsSession *pSession, struct RsResourceRef *pResourceRef) { pSession->__sessionRemoveDependency__(pSession, pResourceRef); } @@ -191,10 +192,10 @@ NV_STATUS sessionConstruct_IMPL(struct RsSession *arg_pSession); void sessionDestruct_IMPL(struct RsSession *pSession); #define __nvoc_sessionDestruct(pSession) sessionDestruct_IMPL(pSession) -NV_STATUS sessionAddDependant_IMPL(struct RsSession *pSession, RsResourceRef *pResourceRef); +NV_STATUS sessionAddDependant_IMPL(struct RsSession *pSession, struct RsResourceRef *pResourceRef); #ifdef __nvoc_rs_server_h_disabled -static inline NV_STATUS sessionAddDependant(struct RsSession *pSession, RsResourceRef *pResourceRef) { +static inline NV_STATUS sessionAddDependant(struct RsSession *pSession, struct RsResourceRef *pResourceRef) { NV_ASSERT_FAILED_PRECOMP("RsSession was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -202,10 +203,10 @@ static inline NV_STATUS sessionAddDependant(struct RsSession *pSession, RsResour #define sessionAddDependant(pSession, pResourceRef) sessionAddDependant_IMPL(pSession, pResourceRef) #endif //__nvoc_rs_server_h_disabled -NV_STATUS sessionAddDependency_IMPL(struct RsSession *pSession, RsResourceRef *pResourceRef); +NV_STATUS sessionAddDependency_IMPL(struct RsSession *pSession, struct RsResourceRef *pResourceRef); #ifdef __nvoc_rs_server_h_disabled -static inline NV_STATUS sessionAddDependency(struct RsSession *pSession, RsResourceRef *pResourceRef) { +static inline NV_STATUS sessionAddDependency(struct RsSession *pSession, struct RsResourceRef *pResourceRef) { NV_ASSERT_FAILED_PRECOMP("RsSession was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -213,10 +214,10 @@ static inline NV_STATUS sessionAddDependency(struct RsSession *pSession, RsResou #define sessionAddDependency(pSession, pResourceRef) sessionAddDependency_IMPL(pSession, pResourceRef) #endif //__nvoc_rs_server_h_disabled -NV_STATUS sessionCheckLocksForAdd_IMPL(struct RsSession *pSession, RsResourceRef *pResourceRef); +NV_STATUS sessionCheckLocksForAdd_IMPL(struct RsSession *pSession, struct RsResourceRef *pResourceRef); #ifdef __nvoc_rs_server_h_disabled -static inline NV_STATUS sessionCheckLocksForAdd(struct RsSession *pSession, RsResourceRef *pResourceRef) { +static inline NV_STATUS sessionCheckLocksForAdd(struct RsSession *pSession, struct RsResourceRef *pResourceRef) { NV_ASSERT_FAILED_PRECOMP("RsSession was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -224,10 +225,10 @@ static inline NV_STATUS sessionCheckLocksForAdd(struct RsSession *pSession, RsRe #define sessionCheckLocksForAdd(pSession, pResourceRef) sessionCheckLocksForAdd_IMPL(pSession, pResourceRef) #endif //__nvoc_rs_server_h_disabled -void sessionCheckLocksForRemove_IMPL(struct RsSession *pSession, RsResourceRef *pResourceRef); +void sessionCheckLocksForRemove_IMPL(struct RsSession *pSession, struct RsResourceRef *pResourceRef); #ifdef __nvoc_rs_server_h_disabled -static inline void sessionCheckLocksForRemove(struct RsSession *pSession, RsResourceRef *pResourceRef) { +static inline void sessionCheckLocksForRemove(struct RsSession *pSession, struct RsResourceRef *pResourceRef) { NV_ASSERT_FAILED_PRECOMP("RsSession was disabled!"); } #else //__nvoc_rs_server_h_disabled @@ -318,6 +319,11 @@ struct RsServer NvU32 activeClientCount; NvU64 activeResourceCount; + + /// List of clients that are de-activated and pending free + RsDisabledClientList disabledClientList; + struct RsClient *pNextDisabledClient; + PORT_SPINLOCK *pDisabledClientListLock; }; /** @@ -399,20 +405,35 @@ NV_STATUS serverAllocClient(RsServer *pServer, RS_RES_ALLOC_PARAMS_INTERNAL *pPa NV_STATUS serverFreeClient(RsServer *pServer, RS_CLIENT_FREE_PARAMS* pParams); /** - * Free a list of client handles. All resources references owned by the client will be - * freed. All priority resources will be freed first across all listed clients. + * Mark a list of client handles as disabled. All CPU mappings owned by that + * client will be unmapped immediate, and the client will be marked as disabled. + * A call to @ref serverFreeDisabledClients will then free all such clients. * * It is invalid to attempt to free a client from a user other than the one * that allocated it. * * @param[in] pServer This server instance - * @param[in] phClientList The list of client handles to free + * @param[in] phClientList The list of client handles to disable * @param[in] numClients The number of clients in the list * @param[in] freeState User-defined free state * @param[in] pSecInfo Security Info * */ -NV_STATUS serverFreeClientList(RsServer *pServer, NvHandle *phClientList, NvU32 numClients, NvU32 freeState, API_SECURITY_INFO *pSecInfo); +NV_STATUS serverMarkClientListDisabled(RsServer *pServer, NvHandle *phClientList, NvU32 numClients, NvU32 freeState, API_SECURITY_INFO *pSecInfo); + +/** + * Frees all currently disabled clients. All resources references owned by + * any of the clients will be freed. + * All priority resources will be freed first across all listed clients. + * + * NOTE: may return NV_WARN_MORE_PROCESSING_REQUIRED if not all clients were freed + * + * @param[in] pServer This server instance + * @param[in] freeState User-defined free state + * @param[in] limit Max number of iterations to make returning; 0 means no limit + * + */ +NV_STATUS serverFreeDisabledClients(RsServer *pServer, NvU32 freeState, NvU32 limit); /** * Allocate a resource. @@ -488,8 +509,67 @@ NvBool serverShareIterNext(RS_SHARE_ITERATOR*); * @param[in] pServer * @param[in] clientHandleBase */ - NV_STATUS serverSetClientHandleBase(RsServer *pServer, NvU32 clientHandleBase); +NV_STATUS serverSetClientHandleBase(RsServer *pServer, NvU32 clientHandleBase); +/** + * Deserialize parameters for servicing command + * + * @param[in] pCallContext + * @param[in] cmd + * @param[in] pParams + * @param[in] paramsSize + * @param[in] flags + */ +NV_STATUS serverDeserializeCtrlDown(CALL_CONTEXT *pCallContext, NvU32 cmd, void *pParams, NvU32 paramsSize, NvU32 *flags); + +/** + * Serialize parameters for servicing command + * + * @param[in] pCallContext + * @param[in] cmd + * @param[in] pParams + * @param[in] paramsSize + * @param[in] flags + */ +NV_STATUS serverSerializeCtrlDown(CALL_CONTEXT *pCallContext, NvU32 cmd, void *pParams, NvU32 paramsSize, NvU32 *flags); + +/** + * Deserialize parameters for returning from command + * + * @param[in] pCallContext + * @param[in] cmd + * @param[in] pParams + * @param[in] paramsSize + * @param[in] flags + */ +NV_STATUS serverDeserializeCtrlUp(CALL_CONTEXT *pCallContext, NvU32 cmd, void *pParams, NvU32 paramsSize, NvU32 *flags); + +/** + * Serialize parameters for returning from command + * + * @param[in] pCallContext + * @param[in] cmd + * @param[in] pParams + * @param[in] paramsSize + * @param[in] flags + */ +NV_STATUS serverSerializeCtrlUp(CALL_CONTEXT *pCallContext, NvU32 cmd, void *pParams, NvU32 paramsSize, NvU32 *flags); + +/** + * Unset flag for reserializing control before going to GSP + * Used if kernel control servicing passes params to GSP without changing them + * + * @param[in] pCallContext + */ +void serverDisableReserializeControl(CALL_CONTEXT *pCallContext); + +/** + * Free finn structures allocated for serializing/deserializing + * + * @param[in] pCallContext + * @param[in] pParams + */ +void serverFreeSerializeStructures(CALL_CONTEXT *pCallContext, void *pParams); /** * Return an available client handle for new client allocation diff --git a/src/nvidia/generated/g_sdk-structures.h b/src/nvidia/generated/g_sdk-structures.h index 8ec3dea1f..ecef5154d 100644 --- a/src/nvidia/generated/g_sdk-structures.h +++ b/src/nvidia/generated/g_sdk-structures.h @@ -464,6 +464,17 @@ typedef struct NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_v21_0A typedef NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_v21_0A NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_v; +typedef struct NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_v22_01 +{ + NvBool bIsLinkUp; + NvU32 nrLinks; + NvU32 linkMask; + NvU32 perLinkBwMBps; + NvU32 remoteType; +} NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_v22_01; + +typedef NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_v22_01 NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_v; + typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI_v21_04 { NvU32 sensorId; diff --git a/src/nvidia/generated/g_standard_mem_nvoc.c b/src/nvidia/generated/g_standard_mem_nvoc.c index f72c41d16..5a572934d 100644 --- a/src/nvidia/generated/g_standard_mem_nvoc.c +++ b/src/nvidia/generated/g_standard_mem_nvoc.c @@ -101,6 +101,46 @@ static NV_STATUS __nvoc_thunk_Memory_stdmemCheckMemInterUnmap(struct StandardMem return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), bSubdeviceHandleProvided); } +static NvBool __nvoc_thunk_RmResource_stdmemShareCallback(struct StandardMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RsResource_stdmemMapTo(struct StandardMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_stdmemGetMapAddrSpace(struct StandardMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_stdmemGetRefCount(struct StandardMemory *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_stdmemAddAdditionalDependants(struct RsClient *pClient, struct StandardMemory *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_stdmemControl_Prologue(struct StandardMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_Memory_stdmemIsGpuMapAllowed(struct StandardMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), pGpu); +} + +static NV_STATUS __nvoc_thunk_RsResource_stdmemUnmapFrom(struct StandardMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_stdmemControl_Epilogue(struct StandardMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_stdmemControlLookup(struct StandardMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RsResource.offset), pParams, ppEntry); +} + static NV_STATUS __nvoc_thunk_Memory_stdmemControl(struct StandardMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), pCallContext, pParams); } @@ -117,36 +157,12 @@ static NV_STATUS __nvoc_thunk_Memory_stdmemGetMemoryMappingDescriptor(struct Sta return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_Memory_stdmemGetMapAddrSpace(struct StandardMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvBool __nvoc_thunk_RmResource_stdmemShareCallback(struct StandardMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); -} - static NV_STATUS __nvoc_thunk_RsResource_stdmemControlFilter(struct StandardMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_stdmemAddAdditionalDependants(struct RsClient *pClient, struct StandardMemory *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_stdmemGetRefCount(struct StandardMemory *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RsResource_stdmemMapTo(struct StandardMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_stdmemControl_Prologue(struct StandardMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RmResource.offset), pCallContext, pParams); -} - -static NvBool __nvoc_thunk_Memory_stdmemIsGpuMapAllowed(struct StandardMemory *pMemory, struct OBJGPU *pGpu) { - return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), pGpu); +static NV_STATUS __nvoc_thunk_RmResource_stdmemControlSerialization_Prologue(struct StandardMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_stdmemIsReady(struct StandardMemory *pMemory, NvBool bCopyConstructorContext) { @@ -165,16 +181,8 @@ static NV_STATUS __nvoc_thunk_Memory_stdmemIsDuplicate(struct StandardMemory *pM return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), hMemory, pDuplicate); } -static NV_STATUS __nvoc_thunk_RsResource_stdmemUnmapFrom(struct StandardMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RmResource_stdmemControl_Epilogue(struct StandardMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_stdmemControlLookup(struct StandardMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_stdmemControlSerialization_Epilogue(struct StandardMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_stdmemMap(struct StandardMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -229,6 +237,26 @@ static void __nvoc_init_funcTable_StandardMemory_1(StandardMemory *pThis) { pThis->__stdmemCheckMemInterUnmap__ = &__nvoc_thunk_Memory_stdmemCheckMemInterUnmap; + pThis->__stdmemShareCallback__ = &__nvoc_thunk_RmResource_stdmemShareCallback; + + pThis->__stdmemMapTo__ = &__nvoc_thunk_RsResource_stdmemMapTo; + + pThis->__stdmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_stdmemGetMapAddrSpace; + + pThis->__stdmemGetRefCount__ = &__nvoc_thunk_RsResource_stdmemGetRefCount; + + pThis->__stdmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_stdmemAddAdditionalDependants; + + pThis->__stdmemControl_Prologue__ = &__nvoc_thunk_RmResource_stdmemControl_Prologue; + + pThis->__stdmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_stdmemIsGpuMapAllowed; + + pThis->__stdmemUnmapFrom__ = &__nvoc_thunk_RsResource_stdmemUnmapFrom; + + pThis->__stdmemControl_Epilogue__ = &__nvoc_thunk_RmResource_stdmemControl_Epilogue; + + pThis->__stdmemControlLookup__ = &__nvoc_thunk_RsResource_stdmemControlLookup; + pThis->__stdmemControl__ = &__nvoc_thunk_Memory_stdmemControl; pThis->__stdmemUnmap__ = &__nvoc_thunk_Memory_stdmemUnmap; @@ -237,21 +265,9 @@ static void __nvoc_init_funcTable_StandardMemory_1(StandardMemory *pThis) { pThis->__stdmemGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_stdmemGetMemoryMappingDescriptor; - pThis->__stdmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_stdmemGetMapAddrSpace; - - pThis->__stdmemShareCallback__ = &__nvoc_thunk_RmResource_stdmemShareCallback; - pThis->__stdmemControlFilter__ = &__nvoc_thunk_RsResource_stdmemControlFilter; - pThis->__stdmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_stdmemAddAdditionalDependants; - - pThis->__stdmemGetRefCount__ = &__nvoc_thunk_RsResource_stdmemGetRefCount; - - pThis->__stdmemMapTo__ = &__nvoc_thunk_RsResource_stdmemMapTo; - - pThis->__stdmemControl_Prologue__ = &__nvoc_thunk_RmResource_stdmemControl_Prologue; - - pThis->__stdmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_stdmemIsGpuMapAllowed; + pThis->__stdmemControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_stdmemControlSerialization_Prologue; pThis->__stdmemIsReady__ = &__nvoc_thunk_Memory_stdmemIsReady; @@ -261,11 +277,7 @@ static void __nvoc_init_funcTable_StandardMemory_1(StandardMemory *pThis) { pThis->__stdmemIsDuplicate__ = &__nvoc_thunk_Memory_stdmemIsDuplicate; - pThis->__stdmemUnmapFrom__ = &__nvoc_thunk_RsResource_stdmemUnmapFrom; - - pThis->__stdmemControl_Epilogue__ = &__nvoc_thunk_RmResource_stdmemControl_Epilogue; - - pThis->__stdmemControlLookup__ = &__nvoc_thunk_RsResource_stdmemControlLookup; + pThis->__stdmemControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_stdmemControlSerialization_Epilogue; pThis->__stdmemMap__ = &__nvoc_thunk_Memory_stdmemMap; @@ -293,13 +305,16 @@ NV_STATUS __nvoc_objCreate_StandardMemory(StandardMemory **ppThis, Dynamic *pPar Object *pParentObj; StandardMemory *pThis; - pThis = portMemAllocNonPaged(sizeof(StandardMemory)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(StandardMemory), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(StandardMemory)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_StandardMemory); + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -315,11 +330,17 @@ NV_STATUS __nvoc_objCreate_StandardMemory(StandardMemory **ppThis, Dynamic *pPar if (status != NV_OK) goto __nvoc_objCreate_StandardMemory_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_StandardMemory_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(StandardMemory)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_standard_mem_nvoc.h b/src/nvidia/generated/g_standard_mem_nvoc.h index f85ce18a7..a7bfad91d 100644 --- a/src/nvidia/generated/g_standard_mem_nvoc.h +++ b/src/nvidia/generated/g_standard_mem_nvoc.h @@ -71,25 +71,27 @@ struct StandardMemory { struct StandardMemory *__nvoc_pbase_StandardMemory; NvBool (*__stdmemCanCopy__)(struct StandardMemory *); NV_STATUS (*__stdmemCheckMemInterUnmap__)(struct StandardMemory *, NvBool); + NvBool (*__stdmemShareCallback__)(struct StandardMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__stdmemMapTo__)(struct StandardMemory *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__stdmemGetMapAddrSpace__)(struct StandardMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__stdmemGetRefCount__)(struct StandardMemory *); + void (*__stdmemAddAdditionalDependants__)(struct RsClient *, struct StandardMemory *, RsResourceRef *); + NV_STATUS (*__stdmemControl_Prologue__)(struct StandardMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__stdmemIsGpuMapAllowed__)(struct StandardMemory *, struct OBJGPU *); + NV_STATUS (*__stdmemUnmapFrom__)(struct StandardMemory *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__stdmemControl_Epilogue__)(struct StandardMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__stdmemControlLookup__)(struct StandardMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__stdmemControl__)(struct StandardMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__stdmemUnmap__)(struct StandardMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__stdmemGetMemInterMapParams__)(struct StandardMemory *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__stdmemGetMemoryMappingDescriptor__)(struct StandardMemory *, MEMORY_DESCRIPTOR **); - NV_STATUS (*__stdmemGetMapAddrSpace__)(struct StandardMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvBool (*__stdmemShareCallback__)(struct StandardMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__stdmemControlFilter__)(struct StandardMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__stdmemAddAdditionalDependants__)(struct RsClient *, struct StandardMemory *, RsResourceRef *); - NvU32 (*__stdmemGetRefCount__)(struct StandardMemory *); - NV_STATUS (*__stdmemMapTo__)(struct StandardMemory *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__stdmemControl_Prologue__)(struct StandardMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvBool (*__stdmemIsGpuMapAllowed__)(struct StandardMemory *, struct OBJGPU *); + NV_STATUS (*__stdmemControlSerialization_Prologue__)(struct StandardMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__stdmemIsReady__)(struct StandardMemory *, NvBool); NV_STATUS (*__stdmemCheckCopyPermissions__)(struct StandardMemory *, struct OBJGPU *, NvHandle); void (*__stdmemPreDestruct__)(struct StandardMemory *); NV_STATUS (*__stdmemIsDuplicate__)(struct StandardMemory *, NvHandle, NvBool *); - NV_STATUS (*__stdmemUnmapFrom__)(struct StandardMemory *, RS_RES_UNMAP_FROM_PARAMS *); - void (*__stdmemControl_Epilogue__)(struct StandardMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__stdmemControlLookup__)(struct StandardMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__stdmemControlSerialization_Epilogue__)(struct StandardMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__stdmemMap__)(struct StandardMemory *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__stdmemAccessCallback__)(struct StandardMemory *, struct RsClient *, void *, RsAccessRight); }; @@ -124,25 +126,27 @@ NV_STATUS __nvoc_objCreate_StandardMemory(StandardMemory**, Dynamic*, NvU32, CAL #define stdmemCanCopy(pStandardMemory) stdmemCanCopy_DISPATCH(pStandardMemory) #define stdmemCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) stdmemCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define stdmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) stdmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define stdmemMapTo(pResource, pParams) stdmemMapTo_DISPATCH(pResource, pParams) +#define stdmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) stdmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define stdmemGetRefCount(pResource) stdmemGetRefCount_DISPATCH(pResource) +#define stdmemAddAdditionalDependants(pClient, pResource, pReference) stdmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define stdmemControl_Prologue(pResource, pCallContext, pParams) stdmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define stdmemIsGpuMapAllowed(pMemory, pGpu) stdmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define stdmemUnmapFrom(pResource, pParams) stdmemUnmapFrom_DISPATCH(pResource, pParams) +#define stdmemControl_Epilogue(pResource, pCallContext, pParams) stdmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define stdmemControlLookup(pResource, pParams, ppEntry) stdmemControlLookup_DISPATCH(pResource, pParams, ppEntry) #define stdmemControl(pMemory, pCallContext, pParams) stdmemControl_DISPATCH(pMemory, pCallContext, pParams) #define stdmemUnmap(pMemory, pCallContext, pCpuMapping) stdmemUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define stdmemGetMemInterMapParams(pMemory, pParams) stdmemGetMemInterMapParams_DISPATCH(pMemory, pParams) #define stdmemGetMemoryMappingDescriptor(pMemory, ppMemDesc) stdmemGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define stdmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) stdmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) -#define stdmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) stdmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define stdmemControlFilter(pResource, pCallContext, pParams) stdmemControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define stdmemAddAdditionalDependants(pClient, pResource, pReference) stdmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define stdmemGetRefCount(pResource) stdmemGetRefCount_DISPATCH(pResource) -#define stdmemMapTo(pResource, pParams) stdmemMapTo_DISPATCH(pResource, pParams) -#define stdmemControl_Prologue(pResource, pCallContext, pParams) stdmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define stdmemIsGpuMapAllowed(pMemory, pGpu) stdmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define stdmemControlSerialization_Prologue(pResource, pCallContext, pParams) stdmemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define stdmemIsReady(pMemory, bCopyConstructorContext) stdmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define stdmemCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) stdmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) #define stdmemPreDestruct(pResource) stdmemPreDestruct_DISPATCH(pResource) #define stdmemIsDuplicate(pMemory, hMemory, pDuplicate) stdmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) -#define stdmemUnmapFrom(pResource, pParams) stdmemUnmapFrom_DISPATCH(pResource, pParams) -#define stdmemControl_Epilogue(pResource, pCallContext, pParams) stdmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define stdmemControlLookup(pResource, pParams, ppEntry) stdmemControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define stdmemControlSerialization_Epilogue(pResource, pCallContext, pParams) stdmemControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define stdmemMap(pMemory, pCallContext, pParams, pCpuMapping) stdmemMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define stdmemAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) stdmemAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvU32 stdmemGetSysmemPageSize_IMPL(struct OBJGPU *pGpu, struct StandardMemory *pMemory); @@ -169,6 +173,46 @@ static inline NV_STATUS stdmemCheckMemInterUnmap_DISPATCH(struct StandardMemory return pMemory->__stdmemCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } +static inline NvBool stdmemShareCallback_DISPATCH(struct StandardMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__stdmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS stdmemMapTo_DISPATCH(struct StandardMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__stdmemMapTo__(pResource, pParams); +} + +static inline NV_STATUS stdmemGetMapAddrSpace_DISPATCH(struct StandardMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__stdmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 stdmemGetRefCount_DISPATCH(struct StandardMemory *pResource) { + return pResource->__stdmemGetRefCount__(pResource); +} + +static inline void stdmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct StandardMemory *pResource, RsResourceRef *pReference) { + pResource->__stdmemAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS stdmemControl_Prologue_DISPATCH(struct StandardMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__stdmemControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool stdmemIsGpuMapAllowed_DISPATCH(struct StandardMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__stdmemIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline NV_STATUS stdmemUnmapFrom_DISPATCH(struct StandardMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__stdmemUnmapFrom__(pResource, pParams); +} + +static inline void stdmemControl_Epilogue_DISPATCH(struct StandardMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__stdmemControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS stdmemControlLookup_DISPATCH(struct StandardMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__stdmemControlLookup__(pResource, pParams, ppEntry); +} + static inline NV_STATUS stdmemControl_DISPATCH(struct StandardMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pMemory->__stdmemControl__(pMemory, pCallContext, pParams); } @@ -185,36 +229,12 @@ static inline NV_STATUS stdmemGetMemoryMappingDescriptor_DISPATCH(struct Standar return pMemory->__stdmemGetMemoryMappingDescriptor__(pMemory, ppMemDesc); } -static inline NV_STATUS stdmemGetMapAddrSpace_DISPATCH(struct StandardMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pMemory->__stdmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvBool stdmemShareCallback_DISPATCH(struct StandardMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pResource->__stdmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); -} - static inline NV_STATUS stdmemControlFilter_DISPATCH(struct StandardMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__stdmemControlFilter__(pResource, pCallContext, pParams); } -static inline void stdmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct StandardMemory *pResource, RsResourceRef *pReference) { - pResource->__stdmemAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 stdmemGetRefCount_DISPATCH(struct StandardMemory *pResource) { - return pResource->__stdmemGetRefCount__(pResource); -} - -static inline NV_STATUS stdmemMapTo_DISPATCH(struct StandardMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__stdmemMapTo__(pResource, pParams); -} - -static inline NV_STATUS stdmemControl_Prologue_DISPATCH(struct StandardMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__stdmemControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NvBool stdmemIsGpuMapAllowed_DISPATCH(struct StandardMemory *pMemory, struct OBJGPU *pGpu) { - return pMemory->__stdmemIsGpuMapAllowed__(pMemory, pGpu); +static inline NV_STATUS stdmemControlSerialization_Prologue_DISPATCH(struct StandardMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__stdmemControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS stdmemIsReady_DISPATCH(struct StandardMemory *pMemory, NvBool bCopyConstructorContext) { @@ -233,16 +253,8 @@ static inline NV_STATUS stdmemIsDuplicate_DISPATCH(struct StandardMemory *pMemor return pMemory->__stdmemIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline NV_STATUS stdmemUnmapFrom_DISPATCH(struct StandardMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__stdmemUnmapFrom__(pResource, pParams); -} - -static inline void stdmemControl_Epilogue_DISPATCH(struct StandardMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__stdmemControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS stdmemControlLookup_DISPATCH(struct StandardMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__stdmemControlLookup__(pResource, pParams, ppEntry); +static inline void stdmemControlSerialization_Epilogue_DISPATCH(struct StandardMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__stdmemControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS stdmemMap_DISPATCH(struct StandardMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -265,7 +277,7 @@ void stdmemDumpInputAllocParams_IMPL(NV_MEMORY_ALLOCATION_PARAMS *pAllocData, CA void stdmemDumpOutputAllocParams_IMPL(NV_MEMORY_ALLOCATION_PARAMS *pAllocData); #define stdmemDumpOutputAllocParams(pAllocData) stdmemDumpOutputAllocParams_IMPL(pAllocData) -NvU32 stdmemQueryPageSize_IMPL(struct MemoryManager *pMemoryManager, NvHandle hClient, NV_MEMORY_ALLOCATION_PARAMS *pAllocData); +NvU64 stdmemQueryPageSize_IMPL(struct MemoryManager *pMemoryManager, NvHandle hClient, NV_MEMORY_ALLOCATION_PARAMS *pAllocData); #define stdmemQueryPageSize(pMemoryManager, hClient, pAllocData) stdmemQueryPageSize_IMPL(pMemoryManager, hClient, pAllocData) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_subdevice_diag_nvoc.c b/src/nvidia/generated/g_subdevice_diag_nvoc.c index f09a7e2ce..024ea06e2 100644 --- a/src/nvidia/generated/g_subdevice_diag_nvoc.c +++ b/src/nvidia/generated/g_subdevice_diag_nvoc.c @@ -123,16 +123,16 @@ static NvBool __nvoc_thunk_GpuResource_diagapiShareCallback(struct DiagApi *pGpu return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DiagApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_RsResource_diagapiMapTo(struct DiagApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DiagApi_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_diagapiCheckMemInterUnmap(struct DiagApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DiagApi_RmResource.offset), bSubdeviceHandleProvided); } static NV_STATUS __nvoc_thunk_Notifier_diagapiGetOrAllocNotifShare(struct DiagApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DiagApi_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); } -static NV_STATUS __nvoc_thunk_RmResource_diagapiCheckMemInterUnmap(struct DiagApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_DiagApi_RmResource.offset), bSubdeviceHandleProvided); +static NV_STATUS __nvoc_thunk_RsResource_diagapiMapTo(struct DiagApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DiagApi_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_GpuResource_diagapiGetMapAddrSpace(struct DiagApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -195,6 +195,10 @@ static NV_STATUS __nvoc_thunk_Notifier_diagapiUnregisterEvent(struct DiagApi *pN return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DiagApi_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_diagapiControlSerialization_Prologue(struct DiagApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DiagApi_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_diagapiCanCopy(struct DiagApi *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DiagApi_RsResource.offset)); } @@ -207,6 +211,10 @@ static NV_STATUS __nvoc_thunk_RsResource_diagapiIsDuplicate(struct DiagApi *pRes return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DiagApi_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_diagapiControlSerialization_Epilogue(struct DiagApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DiagApi_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_diagapiGetNotificationListPtr(struct DiagApi *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DiagApi_Notifier.offset)); } @@ -534,11 +542,11 @@ static void __nvoc_init_funcTable_DiagApi_1(DiagApi *pThis) { pThis->__diagapiShareCallback__ = &__nvoc_thunk_GpuResource_diagapiShareCallback; - pThis->__diagapiMapTo__ = &__nvoc_thunk_RsResource_diagapiMapTo; + pThis->__diagapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_diagapiCheckMemInterUnmap; pThis->__diagapiGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_diagapiGetOrAllocNotifShare; - pThis->__diagapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_diagapiCheckMemInterUnmap; + pThis->__diagapiMapTo__ = &__nvoc_thunk_RsResource_diagapiMapTo; pThis->__diagapiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_diagapiGetMapAddrSpace; @@ -570,12 +578,16 @@ static void __nvoc_init_funcTable_DiagApi_1(DiagApi *pThis) { pThis->__diagapiUnregisterEvent__ = &__nvoc_thunk_Notifier_diagapiUnregisterEvent; + pThis->__diagapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_diagapiControlSerialization_Prologue; + pThis->__diagapiCanCopy__ = &__nvoc_thunk_RsResource_diagapiCanCopy; pThis->__diagapiPreDestruct__ = &__nvoc_thunk_RsResource_diagapiPreDestruct; pThis->__diagapiIsDuplicate__ = &__nvoc_thunk_RsResource_diagapiIsDuplicate; + pThis->__diagapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_diagapiControlSerialization_Epilogue; + pThis->__diagapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_diagapiGetNotificationListPtr; pThis->__diagapiGetNotificationShare__ = &__nvoc_thunk_Notifier_diagapiGetNotificationShare; @@ -610,13 +622,16 @@ NV_STATUS __nvoc_objCreate_DiagApi(DiagApi **ppThis, Dynamic *pParent, NvU32 cre Object *pParentObj; DiagApi *pThis; - pThis = portMemAllocNonPaged(sizeof(DiagApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DiagApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(DiagApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DiagApi); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -632,11 +647,17 @@ NV_STATUS __nvoc_objCreate_DiagApi(DiagApi **ppThis, Dynamic *pParent, NvU32 cre if (status != NV_OK) goto __nvoc_objCreate_DiagApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_DiagApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(DiagApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_subdevice_diag_nvoc.h b/src/nvidia/generated/g_subdevice_diag_nvoc.h index 4a2a6b941..2b11179a7 100644 --- a/src/nvidia/generated/g_subdevice_diag_nvoc.h +++ b/src/nvidia/generated/g_subdevice_diag_nvoc.h @@ -77,9 +77,9 @@ struct DiagApi { NV_STATUS (*__diagapiCtrlCmdBifConfigRegWrite__)(struct DiagApi *, NV208F_CTRL_BIF_CONFIG_REG_WRITE_PARAMS *); NV_STATUS (*__diagapiCtrlCmdBifInfo__)(struct DiagApi *, NV208F_CTRL_BIF_INFO_PARAMS *); NvBool (*__diagapiShareCallback__)(struct DiagApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__diagapiMapTo__)(struct DiagApi *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__diagapiGetOrAllocNotifShare__)(struct DiagApi *, NvHandle, NvHandle, struct NotifShare **); NV_STATUS (*__diagapiCheckMemInterUnmap__)(struct DiagApi *, NvBool); + NV_STATUS (*__diagapiGetOrAllocNotifShare__)(struct DiagApi *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__diagapiMapTo__)(struct DiagApi *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__diagapiGetMapAddrSpace__)(struct DiagApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); void (*__diagapiSetNotificationShare__)(struct DiagApi *, struct NotifShare *); NvU32 (*__diagapiGetRefCount__)(struct DiagApi *); @@ -95,9 +95,11 @@ struct DiagApi { NV_STATUS (*__diagapiGetMemInterMapParams__)(struct DiagApi *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__diagapiGetMemoryMappingDescriptor__)(struct DiagApi *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__diagapiUnregisterEvent__)(struct DiagApi *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__diagapiControlSerialization_Prologue__)(struct DiagApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__diagapiCanCopy__)(struct DiagApi *); void (*__diagapiPreDestruct__)(struct DiagApi *); NV_STATUS (*__diagapiIsDuplicate__)(struct DiagApi *, NvHandle, NvBool *); + void (*__diagapiControlSerialization_Epilogue__)(struct DiagApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__diagapiGetNotificationListPtr__)(struct DiagApi *); struct NotifShare *(*__diagapiGetNotificationShare__)(struct DiagApi *); NV_STATUS (*__diagapiMap__)(struct DiagApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -149,9 +151,9 @@ NV_STATUS __nvoc_objCreate_DiagApi(DiagApi**, Dynamic*, NvU32, struct CALL_CONTE #define diagapiCtrlCmdBifConfigRegWrite(pDiagApi, pWriteConfigReg) diagapiCtrlCmdBifConfigRegWrite_DISPATCH(pDiagApi, pWriteConfigReg) #define diagapiCtrlCmdBifInfo(pDiagApi, pInfo) diagapiCtrlCmdBifInfo_DISPATCH(pDiagApi, pInfo) #define diagapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) diagapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define diagapiMapTo(pResource, pParams) diagapiMapTo_DISPATCH(pResource, pParams) -#define diagapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) diagapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) #define diagapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) diagapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define diagapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) diagapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define diagapiMapTo(pResource, pParams) diagapiMapTo_DISPATCH(pResource, pParams) #define diagapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) diagapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) #define diagapiSetNotificationShare(pNotifier, pNotifShare) diagapiSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define diagapiGetRefCount(pResource) diagapiGetRefCount_DISPATCH(pResource) @@ -167,9 +169,11 @@ NV_STATUS __nvoc_objCreate_DiagApi(DiagApi**, Dynamic*, NvU32, struct CALL_CONTE #define diagapiGetMemInterMapParams(pRmResource, pParams) diagapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define diagapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) diagapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define diagapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) diagapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define diagapiControlSerialization_Prologue(pResource, pCallContext, pParams) diagapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define diagapiCanCopy(pResource) diagapiCanCopy_DISPATCH(pResource) #define diagapiPreDestruct(pResource) diagapiPreDestruct_DISPATCH(pResource) #define diagapiIsDuplicate(pResource, hMemory, pDuplicate) diagapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define diagapiControlSerialization_Epilogue(pResource, pCallContext, pParams) diagapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define diagapiGetNotificationListPtr(pNotifier) diagapiGetNotificationListPtr_DISPATCH(pNotifier) #define diagapiGetNotificationShare(pNotifier) diagapiGetNotificationShare_DISPATCH(pNotifier) #define diagapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) diagapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -268,16 +272,16 @@ static inline NvBool diagapiShareCallback_DISPATCH(struct DiagApi *pGpuResource, return pGpuResource->__diagapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS diagapiMapTo_DISPATCH(struct DiagApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__diagapiMapTo__(pResource, pParams); +static inline NV_STATUS diagapiCheckMemInterUnmap_DISPATCH(struct DiagApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__diagapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } static inline NV_STATUS diagapiGetOrAllocNotifShare_DISPATCH(struct DiagApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return pNotifier->__diagapiGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); } -static inline NV_STATUS diagapiCheckMemInterUnmap_DISPATCH(struct DiagApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__diagapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline NV_STATUS diagapiMapTo_DISPATCH(struct DiagApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__diagapiMapTo__(pResource, pParams); } static inline NV_STATUS diagapiGetMapAddrSpace_DISPATCH(struct DiagApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -340,6 +344,10 @@ static inline NV_STATUS diagapiUnregisterEvent_DISPATCH(struct DiagApi *pNotifie return pNotifier->__diagapiUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS diagapiControlSerialization_Prologue_DISPATCH(struct DiagApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__diagapiControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool diagapiCanCopy_DISPATCH(struct DiagApi *pResource) { return pResource->__diagapiCanCopy__(pResource); } @@ -352,6 +360,10 @@ static inline NV_STATUS diagapiIsDuplicate_DISPATCH(struct DiagApi *pResource, N return pResource->__diagapiIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void diagapiControlSerialization_Epilogue_DISPATCH(struct DiagApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__diagapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *diagapiGetNotificationListPtr_DISPATCH(struct DiagApi *pNotifier) { return pNotifier->__diagapiGetNotificationListPtr__(pNotifier); } diff --git a/src/nvidia/generated/g_subdevice_nvoc.c b/src/nvidia/generated/g_subdevice_nvoc.c index bad622685..16564f350 100644 --- a/src/nvidia/generated/g_subdevice_nvoc.c +++ b/src/nvidia/generated/g_subdevice_nvoc.c @@ -127,16 +127,16 @@ static NvBool __nvoc_thunk_GpuResource_subdeviceShareCallback(struct Subdevice * return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Subdevice_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_RsResource_subdeviceMapTo(struct Subdevice *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Subdevice_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_subdeviceCheckMemInterUnmap(struct Subdevice *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Subdevice_RmResource.offset), bSubdeviceHandleProvided); } static NV_STATUS __nvoc_thunk_Notifier_subdeviceGetOrAllocNotifShare(struct Subdevice *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_Subdevice_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); } -static NV_STATUS __nvoc_thunk_RmResource_subdeviceCheckMemInterUnmap(struct Subdevice *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_Subdevice_RmResource.offset), bSubdeviceHandleProvided); +static NV_STATUS __nvoc_thunk_RsResource_subdeviceMapTo(struct Subdevice *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Subdevice_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_GpuResource_subdeviceGetMapAddrSpace(struct Subdevice *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -199,6 +199,10 @@ static NV_STATUS __nvoc_thunk_Notifier_subdeviceUnregisterEvent(struct Subdevice return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_Subdevice_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_subdeviceControlSerialization_Prologue(struct Subdevice *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Subdevice_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_subdeviceCanCopy(struct Subdevice *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Subdevice_RsResource.offset)); } @@ -207,6 +211,10 @@ static NV_STATUS __nvoc_thunk_RsResource_subdeviceIsDuplicate(struct Subdevice * return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Subdevice_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_subdeviceControlSerialization_Epilogue(struct Subdevice *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Subdevice_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_subdeviceGetNotificationListPtr(struct Subdevice *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_Subdevice_Notifier.offset)); } @@ -230,12 +238,12 @@ static NvBool __nvoc_thunk_RmResource_subdeviceAccessCallback(struct Subdevice * static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevice[] = { { /* [0] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetInfoV2_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) - /*flags=*/ 0x850u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200850u) + /*flags=*/ 0x200850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800102u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_INFO_V2_PARAMS), @@ -245,12 +253,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [1] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa12u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200a12u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetNameString_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa12u) - /*flags=*/ 0xa12u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200a12u) + /*flags=*/ 0x200a12u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800110u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS), @@ -305,12 +313,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [5] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4813u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetSimulationInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) - /*flags=*/ 0x813u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4813u) + /*flags=*/ 0x4813u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800119u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS), @@ -485,12 +493,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [17] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuQueryComputeModeRules_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) - /*flags=*/ 0x11u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800131u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS), @@ -575,12 +583,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [23] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetFermiZcullInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800139u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS), @@ -1115,6 +1123,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [59] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetVmmuSegmentSize_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4210u) + /*flags=*/ 0x4210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x2080017eu, + /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdGpuGetVmmuSegmentSize" +#endif + }, + { /* [60] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1129,7 +1152,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetPartitionCapacity" #endif }, - { /* [60] */ + { /* [61] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1144,7 +1167,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetCachedInfo" #endif }, - { /* [61] */ + { /* [62] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1159,7 +1182,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuSetPartitioningMode" #endif }, - { /* [62] */ + { /* [63] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1174,7 +1197,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuDescribePartitions" #endif }, - { /* [63] */ + { /* [64] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1189,7 +1212,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetMaxSupportedPageSize" #endif }, - { /* [64] */ + { /* [65] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1204,7 +1227,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetActivePartitionIds" #endif }, - { /* [65] */ + { /* [66] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1219,7 +1242,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetPids" #endif }, - { /* [66] */ + { /* [67] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1234,7 +1257,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetPidInfo" #endif }, - { /* [67] */ + { /* [68] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1249,13 +1272,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuHandleVfPriFault" #endif }, - { /* [68] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + { /* [69] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x807u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuSetComputePolicyConfig_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) - /*flags=*/ 0x4u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x807u) + /*flags=*/ 0x807u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800194u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS), @@ -1264,13 +1287,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuSetComputePolicyConfig" #endif }, - { /* [69] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [70] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetComputePolicyConfig_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*flags=*/ 0x813u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800195u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS), @@ -1279,7 +1302,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetComputePolicyConfig" #endif }, - { /* [70] */ + { /* [71] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1294,7 +1317,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetGfid" #endif }, - { /* [71] */ + { /* [72] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1309,13 +1332,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdUpdateGfidP2pCapability" #endif }, - { /* [72] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + { /* [73] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x840u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdValidateMemMapRequest_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) - /*flags=*/ 0x0u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x840u) + /*flags=*/ 0x840u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800198u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS), @@ -1324,7 +1347,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdValidateMemMapRequest" #endif }, - { /* [73] */ + { /* [74] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x12u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1339,7 +1362,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetEngineLoadTimes" #endif }, - { /* [74] */ + { /* [75] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1354,7 +1377,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetP2pCaps" #endif }, - { /* [75] */ + { /* [76] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1369,7 +1392,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetComputeProfiles" #endif }, - { /* [76] */ + { /* [77] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1384,7 +1407,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetGpuFabricProbeInfo" #endif }, - { /* [77] */ + { /* [78] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1399,7 +1422,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetChipDetails" #endif }, - { /* [78] */ + { /* [79] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1414,7 +1437,52 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuMigratableOps" #endif }, - { /* [79] */ + { /* [80] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetResetStatus_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x208001abu, + /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdGpuGetResetStatus" +#endif + }, + { /* [81] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetDrainAndResetStatus_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x208001aeu, + /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdGpuGetDrainAndResetStatus" +#endif + }, + { /* [82] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetNvencSwSessionInfoV2_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x208001afu, + /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdGpuGetNvencSwSessionInfoV2" +#endif + }, + { /* [83] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1429,7 +1497,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEventSetNotification" #endif }, - { /* [80] */ + { /* [84] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1444,7 +1512,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEventSetTrigger" #endif }, - { /* [81] */ + { /* [85] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1459,7 +1527,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEventSetMemoryNotifies" #endif }, - { /* [82] */ + { /* [86] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1474,7 +1542,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEventSetSemaphoreMemory" #endif }, - { /* [83] */ + { /* [87] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1489,7 +1557,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEventSetSemaMemValidation" #endif }, - { /* [84] */ + { /* [88] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1504,7 +1572,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEventSetTriggerFifo" #endif }, - { /* [85] */ + { /* [89] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1519,7 +1587,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdTimerSchedule" #endif }, - { /* [86] */ + { /* [90] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1534,7 +1602,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdTimerCancel" #endif }, - { /* [87] */ + { /* [91] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1549,7 +1617,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdTimerGetTime" #endif }, - { /* [88] */ + { /* [92] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1564,7 +1632,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdTimerGetRegisterOffset" #endif }, - { /* [89] */ + { /* [93] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1579,7 +1647,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdTimerGetGpuCpuTimeCorrelationInfo" #endif }, - { /* [90] */ + { /* [94] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2010u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1594,7 +1662,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdTimerSetGrTickFreq" #endif }, - { /* [91] */ + { /* [95] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1609,7 +1677,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdI2cReadBuffer" #endif }, - { /* [92] */ + { /* [96] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1624,7 +1692,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdI2cWriteBuffer" #endif }, - { /* [93] */ + { /* [97] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1639,7 +1707,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdI2cReadReg" #endif }, - { /* [94] */ + { /* [98] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1654,7 +1722,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdI2cWriteReg" #endif }, - { /* [95] */ + { /* [99] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1669,7 +1737,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBiosGetSKUInfo" #endif }, - { /* [96] */ + { /* [100] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1684,7 +1752,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBiosGetPostTime" #endif }, - { /* [97] */ + { /* [101] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1699,7 +1767,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBiosGetUefiSupport" #endif }, - { /* [98] */ + { /* [102] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1714,7 +1782,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBiosGetNbsiV2" #endif }, - { /* [99] */ + { /* [103] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1729,7 +1797,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBiosGetInfoV2" #endif }, - { /* [100] */ + { /* [104] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1744,7 +1812,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplayGetStaticInfo" #endif }, - { /* [101] */ + { /* [105] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1759,7 +1827,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMemSysGetStaticConfig" #endif }, - { /* [102] */ + { /* [106] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1774,7 +1842,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer" #endif }, - { /* [103] */ + { /* [107] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1789,7 +1857,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer" #endif }, - { /* [104] */ + { /* [108] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1804,7 +1872,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetCaps" #endif }, - { /* [105] */ + { /* [109] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1819,7 +1887,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalUvmServiceAccessCntrBuffer" #endif }, - { /* [106] */ + { /* [110] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1834,7 +1902,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetGlobalSmOrder" #endif }, - { /* [107] */ + { /* [111] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1849,7 +1917,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMsencGetCaps" #endif }, - { /* [108] */ + { /* [112] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1864,7 +1932,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetFloorsweepingMasks" #endif }, - { /* [109] */ + { /* [113] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x80000u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1879,7 +1947,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxBufferPtes" #endif }, - { /* [110] */ + { /* [114] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1894,7 +1962,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalUvmGetAccessCntrBufferSize" #endif }, - { /* [111] */ + { /* [115] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1909,7 +1977,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetInfo" #endif }, - { /* [112] */ + { /* [116] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1924,7 +1992,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetZcullInfo" #endif }, - { /* [113] */ + { /* [117] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1939,7 +2007,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetRopInfo" #endif }, - { /* [114] */ + { /* [118] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1954,7 +2022,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetPpcMasks" #endif }, - { /* [115] */ + { /* [119] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1969,7 +2037,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetContextBuffersInfo" #endif }, - { /* [116] */ + { /* [120] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1984,7 +2052,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetSmIssueRateModifier" #endif }, - { /* [117] */ + { /* [121] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1999,7 +2067,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetChipInfo" #endif }, - { /* [118] */ + { /* [122] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2014,7 +2082,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetFecsRecordSize" #endif }, - { /* [119] */ + { /* [123] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2029,7 +2097,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetFecsTraceDefines" #endif }, - { /* [120] */ + { /* [124] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2044,7 +2112,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetDeviceInfoTable" #endif }, - { /* [121] */ + { /* [125] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2059,7 +2127,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetUserRegisterAccessMap" #endif }, - { /* [122] */ + { /* [126] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2074,7 +2142,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetConstructedFalconInfo" #endif }, - { /* [123] */ + { /* [127] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2089,7 +2157,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetPdbProperties" #endif }, - { /* [124] */ + { /* [128] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2104,7 +2172,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplayWriteInstMem" #endif }, - { /* [125] */ + { /* [129] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2119,7 +2187,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalRecoverAllComputeContexts" #endif }, - { /* [126] */ + { /* [130] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2134,7 +2202,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplayGetIpVersion" #endif }, - { /* [127] */ + { /* [131] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2149,7 +2217,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetSmcMode" #endif }, - { /* [128] */ + { /* [132] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2164,7 +2232,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplaySetupRgLineIntr" #endif }, - { /* [129] */ + { /* [133] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2179,7 +2247,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMemSysSetPartitionableMem" #endif }, - { /* [130] */ + { /* [134] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2194,7 +2262,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalFifoPromoteRunlistBuffers" #endif }, - { /* [131] */ + { /* [135] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2209,7 +2277,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplaySetImportedImpData" #endif }, - { /* [132] */ + { /* [136] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalVmmuGetSpaForGpaEntries_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800a57u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalVmmuGetSpaForGpaEntries" +#endif + }, + { /* [137] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2224,7 +2307,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplaySetChannelPushbuffer" #endif }, - { /* [133] */ + { /* [138] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2239,7 +2322,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGmmuGetStaticInfo" #endif }, - { /* [134] */ + { /* [139] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2254,7 +2337,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetHeapReservationSize" #endif }, - { /* [135] */ + { /* [140] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2269,7 +2352,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdIntrGetKernelTable" #endif }, - { /* [136] */ + { /* [141] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2284,7 +2367,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplayGetDisplayMask" #endif }, - { /* [137] */ + { /* [142] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2299,7 +2382,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalFifoGetNumChannels" #endif }, - { /* [138] */ + { /* [143] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2314,7 +2397,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalStaticKMIGmgrGetProfiles" #endif }, - { /* [139] */ + { /* [144] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2329,7 +2412,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalStaticKMIGmgrGetPartitionableEngines" #endif }, - { /* [140] */ + { /* [145] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2344,7 +2427,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalStaticKMIGmgrGetSwizzIdFbMemPageRanges" #endif }, - { /* [141] */ + { /* [146] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2359,7 +2442,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKMemSysGetMIGMemoryConfig" #endif }, - { /* [142] */ + { /* [147] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2374,7 +2457,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetZbcReferenced" #endif }, - { /* [143] */ + { /* [148] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2389,7 +2472,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalRcWatchdogTimeout" #endif }, - { /* [144] */ + { /* [149] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2404,7 +2487,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMemSysGetMIGMemoryPartitionTable" #endif }, - { /* [145] */ + { /* [150] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2419,7 +2502,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMemSysL2InvalidateEvict" #endif }, - { /* [146] */ + { /* [151] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2434,7 +2517,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMemSysFlushL2AllRamsAndCaches" #endif }, - { /* [147] */ + { /* [152] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2449,7 +2532,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMemSysDisableNvlinkPeers" #endif }, - { /* [148] */ + { /* [153] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2464,7 +2547,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMemSysProgramRawCompressionMode" #endif }, - { /* [149] */ + { /* [154] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2479,7 +2562,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalBusFlushWithSysmembar" #endif }, - { /* [150] */ + { /* [155] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2494,7 +2577,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalBusSetupP2pMailboxLocal" #endif }, - { /* [151] */ + { /* [156] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2509,7 +2592,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalBusSetupP2pMailboxRemote" #endif }, - { /* [152] */ + { /* [157] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2524,7 +2607,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalBusDestroyP2pMailbox" #endif }, - { /* [153] */ + { /* [158] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2539,7 +2622,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalBusCreateC2cPeerMapping" #endif }, - { /* [154] */ + { /* [159] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2554,7 +2637,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalBusRemoveC2cPeerMapping" #endif }, - { /* [155] */ + { /* [160] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2569,7 +2652,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfCudaLimitDisable" #endif }, - { /* [156] */ + { /* [161] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2584,7 +2667,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit" #endif }, - { /* [157] */ + { /* [162] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2599,7 +2682,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfOptpCliClear" #endif }, - { /* [158] */ + { /* [163] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2614,7 +2697,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfGpuBoostSyncSetControl" #endif }, - { /* [159] */ + { /* [164] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2629,7 +2712,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfSyncGpuBoostSetLimits" #endif }, - { /* [160] */ + { /* [165] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2644,7 +2727,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfGpuBoostSyncGetInfo" #endif }, - { /* [161] */ + { /* [166] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2659,7 +2742,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfGetAuxPowerState" #endif }, - { /* [162] */ + { /* [167] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2674,7 +2757,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdHshubPeerConnConfig" #endif }, - { /* [163] */ + { /* [168] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2689,7 +2772,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdHshubFirstLinkPeerId" #endif }, - { /* [164] */ + { /* [169] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2704,7 +2787,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdHshubGetHshubIdForLinks" #endif }, - { /* [165] */ + { /* [170] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2719,7 +2802,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdHshubGetNumUnits" #endif }, - { /* [166] */ + { /* [171] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2734,7 +2817,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdHshubNextHshubId" #endif }, - { /* [167] */ + { /* [172] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2749,7 +2832,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfPerfmonClientReservationCheck" #endif }, - { /* [168] */ + { /* [173] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2764,7 +2847,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfPerfmonClientReservationSet" #endif }, - { /* [169] */ + { /* [174] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2779,7 +2862,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfBoostSet_2x" #endif }, - { /* [170] */ + { /* [175] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2794,7 +2877,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGmmuRegisterFaultBuffer" #endif }, - { /* [171] */ + { /* [176] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2809,7 +2892,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGmmuUnregisterFaultBuffer" #endif }, - { /* [172] */ + { /* [177] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2824,7 +2907,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGmmuRegisterClientShadowFaultBuffer" #endif }, - { /* [173] */ + { /* [178] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2833,13 +2916,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*flags=*/ 0x600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a9eu, - /*paramSize=*/ 0, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer" #endif }, - { /* [174] */ + { /* [179] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2854,7 +2937,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGmmuCopyReservedSplitGVASpacePdesServer" #endif }, - { /* [175] */ + { /* [180] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2869,7 +2952,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfBoostSet_3x" #endif }, - { /* [176] */ + { /* [181] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2884,7 +2967,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfBoostClear_3x" #endif }, - { /* [177] */ + { /* [182] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2899,7 +2982,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalKMIGmgrExportGPUInstance" #endif }, - { /* [178] */ + { /* [183] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2914,7 +2997,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance" #endif }, - { /* [179] */ + { /* [184] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2929,7 +3012,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBifGetStaticInfo" #endif }, - { /* [180] */ + { /* [185] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2944,7 +3027,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalNvlinkEnableComputePeerAddr" #endif }, - { /* [181] */ + { /* [186] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2959,7 +3042,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalNvlinkGetSetNvswitchFabricAddr" #endif }, - { /* [182] */ + { /* [187] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2974,7 +3057,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBifGetAspmL1Flags" #endif }, - { /* [183] */ + { /* [188] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2989,7 +3072,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfCfControllerSetMaxVGpuVMCount" #endif }, - { /* [184] */ + { /* [189] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3004,7 +3087,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCcuMap" #endif }, - { /* [185] */ + { /* [190] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3019,7 +3102,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCcuUnmap" #endif }, - { /* [186] */ + { /* [191] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3034,7 +3117,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalSetP2pCaps" #endif }, - { /* [187] */ + { /* [192] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3049,7 +3132,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalRemoveP2pCaps" #endif }, - { /* [188] */ + { /* [193] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3064,7 +3147,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetPcieP2pCaps" #endif }, - { /* [189] */ + { /* [194] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3079,7 +3162,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBifSetPcieRo" #endif }, - { /* [190] */ + { /* [195] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3094,7 +3177,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalStaticKMIGmgrGetComputeInstanceProfiles" #endif }, - { /* [191] */ + { /* [196] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3109,7 +3192,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCcuSetStreamState" #endif }, - { /* [192] */ + { /* [197] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3124,7 +3207,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalInitGpuIntr" #endif }, - { /* [193] */ + { /* [198] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3139,7 +3222,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGsyncOptimizeTiming" #endif }, - { /* [194] */ + { /* [199] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3154,7 +3237,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGsyncGetDisplayIds" #endif }, - { /* [195] */ + { /* [200] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3169,7 +3252,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGsyncSetStereoSync" #endif }, - { /* [196] */ + { /* [201] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3184,7 +3267,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalFbsrInit" #endif }, - { /* [197] */ + { /* [202] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3199,7 +3282,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalFbsrSendRegionInfo" #endif }, - { /* [198] */ + { /* [203] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3214,7 +3297,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGsyncGetVactiveLines" #endif }, - { /* [199] */ + { /* [204] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3229,7 +3312,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb" #endif }, - { /* [200] */ + { /* [205] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3244,7 +3327,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPostInitBrightcStateLoad" #endif }, - { /* [201] */ + { /* [206] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3259,7 +3342,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalNvlinkGetNumActiveLinksPerIoctrl" #endif }, - { /* [202] */ + { /* [207] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3274,7 +3357,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalNvlinkGetTotalNumLinksPerIoctrl" #endif }, - { /* [203] */ + { /* [208] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3289,7 +3372,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGsyncIsDisplayIdValid" #endif }, - { /* [204] */ + { /* [209] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3304,7 +3387,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGsyncSetOrRestoreGpioRasterSync" #endif }, - { /* [205] */ + { /* [210] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2610u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalFifoGetNumSecureChannels_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2610u) + /*flags=*/ 0x2610u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ad8u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalFifoGetNumSecureChannels" +#endif + }, + { /* [211] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3319,7 +3417,67 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetCoherentFbApertureSize" #endif }, - { /* [206] */ + { /* [212] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBifDisableSystemMemoryAccess_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800adbu, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdBifDisableSystemMemoryAccess" +#endif + }, + { /* [213] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdDisplayPinsetsToLockpins_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800adcu, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdDisplayPinsetsToLockpins" +#endif + }, + { /* [214] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalDetectHsVideoBridge_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800addu, + /*paramSize=*/ 0, + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalDetectHsVideoBridge" +#endif + }, + { /* [215] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdDisplaySetSliLinkGpioSwControl_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800adeu, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdDisplaySetSliLinkGpioSwControl" +#endif + }, + { /* [216] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3334,7 +3492,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdSetGpfifo" #endif }, - { /* [207] */ + { /* [217] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3349,7 +3507,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoBindEngines" #endif }, - { /* [208] */ + { /* [218] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3364,7 +3522,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdSetOperationalProperties" #endif }, - { /* [209] */ + { /* [219] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3379,13 +3537,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetPhysicalChannelCount" #endif }, - { /* [210] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [220] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200010u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFifoGetInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200010u) + /*flags=*/ 0x200010u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801109u, /*paramSize=*/ sizeof(NV2080_CTRL_FIFO_GET_INFO_PARAMS), @@ -3394,7 +3552,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetInfo" #endif }, - { /* [211] */ + { /* [221] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3409,7 +3567,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoDisableChannels" #endif }, - { /* [212] */ + { /* [222] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3424,7 +3582,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetChannelMemInfo" #endif }, - { /* [213] */ + { /* [223] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3439,7 +3597,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetUserdLocation" #endif }, - { /* [214] */ + { /* [224] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3454,7 +3612,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetDeviceInfoTable" #endif }, - { /* [215] */ + { /* [225] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3469,7 +3627,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoClearFaultedBit" #endif }, - { /* [216] */ + { /* [226] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2310u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3484,7 +3642,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoRunlistSetSchedPolicy" #endif }, - { /* [217] */ + { /* [227] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3499,7 +3657,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoUpdateChannelInfo" #endif }, - { /* [218] */ + { /* [228] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3514,7 +3672,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoDisableUsermodeChannels" #endif }, - { /* [219] */ + { /* [229] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3529,7 +3687,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoSetupVfZombieSubctxPdb" #endif }, - { /* [220] */ + { /* [230] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3544,7 +3702,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetAllocatedChannels" #endif }, - { /* [221] */ + { /* [231] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3559,7 +3717,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetInfo" #endif }, - { /* [222] */ + { /* [232] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3574,7 +3732,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswZcullMode" #endif }, - { /* [223] */ + { /* [233] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3589,7 +3747,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetZcullInfo" #endif }, - { /* [224] */ + { /* [234] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2010u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3604,7 +3762,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswPmMode" #endif }, - { /* [225] */ + { /* [235] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3619,7 +3777,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswZcullBind" #endif }, - { /* [226] */ + { /* [236] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3634,7 +3792,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswPmBind" #endif }, - { /* [227] */ + { /* [237] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3649,7 +3807,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrSetGpcTileMap" #endif }, - { /* [228] */ + { /* [238] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3664,7 +3822,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswSmpcMode" #endif }, - { /* [229] */ + { /* [239] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3679,7 +3837,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetSmToGpcTpcMappings" #endif }, - { /* [230] */ + { /* [240] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3694,7 +3852,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrSetCtxswPreemptionMode" #endif }, - { /* [231] */ + { /* [241] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3709,7 +3867,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswPreemptionBind" #endif }, - { /* [232] */ + { /* [242] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3724,7 +3882,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrPcSamplingMode" #endif }, - { /* [233] */ + { /* [243] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3739,7 +3897,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetROPInfo" #endif }, - { /* [234] */ + { /* [244] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3754,7 +3912,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxswStats" #endif }, - { /* [235] */ + { /* [245] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3769,7 +3927,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxBufferSize" #endif }, - { /* [236] */ + { /* [246] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x80000u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3784,7 +3942,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxBufferInfo" #endif }, - { /* [237] */ + { /* [247] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3799,7 +3957,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetGlobalSmOrder" #endif }, - { /* [238] */ + { /* [248] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3808,13 +3966,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*flags=*/ 0x2210u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080121cu, - /*paramSize=*/ sizeof(NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS), + /*paramSize=*/ sizeof(NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "subdeviceCtrlCmdKGrGetCurrentResidentChannel" #endif }, - { /* [239] */ + { /* [249] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3829,7 +3987,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetVatAlarmData" #endif }, - { /* [240] */ + { /* [250] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3844,7 +4002,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetAttributeBufferSize" #endif }, - { /* [241] */ + { /* [251] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3859,7 +4017,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGfxPoolQuerySize" #endif }, - { /* [242] */ + { /* [252] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3874,7 +4032,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGfxPoolInitialize" #endif }, - { /* [243] */ + { /* [253] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3889,7 +4047,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGfxPoolAddSlots" #endif }, - { /* [244] */ + { /* [254] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3904,7 +4062,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGfxPoolRemoveSlots" #endif }, - { /* [245] */ + { /* [255] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x812u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3919,7 +4077,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCapsV2" #endif }, - { /* [246] */ + { /* [256] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3934,7 +4092,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetInfoV2" #endif }, - { /* [247] */ + { /* [257] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3949,7 +4107,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetGpcMask" #endif }, - { /* [248] */ + { /* [258] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3964,7 +4122,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetTpcMask" #endif }, - { /* [249] */ + { /* [259] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3979,7 +4137,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrSetTpcPartitionMode" #endif }, - { /* [250] */ + { /* [260] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3994,7 +4152,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetEngineContextProperties" #endif }, - { /* [251] */ + { /* [261] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4009,7 +4167,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetSmIssueRateModifier" #endif }, - { /* [252] */ + { /* [262] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4024,7 +4182,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrFecsBindEvtbufForUid" #endif }, - { /* [253] */ + { /* [263] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4039,7 +4197,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetPhysGpcMask" #endif }, - { /* [254] */ + { /* [264] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4054,7 +4212,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetPpcMask" #endif }, - { /* [255] */ + { /* [265] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4069,7 +4227,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetNumTpcsForGpc" #endif }, - { /* [256] */ + { /* [266] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4084,7 +4242,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxswModes" #endif }, - { /* [257] */ + { /* [267] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4099,7 +4257,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetGpcTileMap" #endif }, - { /* [258] */ + { /* [268] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4114,7 +4272,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetZcullMask" #endif }, - { /* [259] */ + { /* [269] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8010u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4129,7 +4287,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrFecsBindEvtbufForUidV2" #endif }, - { /* [260] */ + { /* [270] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4144,7 +4302,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetGfxGpcAndTpcInfo" #endif }, - { /* [261] */ + { /* [271] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4159,7 +4317,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetInfo" #endif }, - { /* [262] */ + { /* [272] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4174,7 +4332,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetInfoV2" #endif }, - { /* [263] */ + { /* [273] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4189,7 +4347,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCarveoutAddressInfo" #endif }, - { /* [264] */ + { /* [274] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4204,7 +4362,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCalibrationLockFailed" #endif }, - { /* [265] */ + { /* [275] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4219,7 +4377,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbFlushGpuCache" #endif }, - { /* [266] */ + { /* [276] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4234,7 +4392,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetGpuCacheAllocPolicy" #endif }, - { /* [267] */ + { /* [277] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4249,7 +4407,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetBar1Offset" #endif }, - { /* [268] */ + { /* [278] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4264,7 +4422,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetGpuCacheAllocPolicy" #endif }, - { /* [269] */ + { /* [279] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4279,7 +4437,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbIsKind" #endif }, - { /* [270] */ + { /* [280] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4294,7 +4452,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetGpuCacheInfo" #endif }, - { /* [271] */ + { /* [281] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4309,7 +4467,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetGpuCacheAllocPolicyV2" #endif }, - { /* [272] */ + { /* [282] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4324,7 +4482,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetGpuCacheAllocPolicyV2" #endif }, - { /* [273] */ + { /* [283] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4339,7 +4497,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetFBRegionInfo" #endif }, - { /* [274] */ + { /* [284] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4354,7 +4512,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetOfflinedPages" #endif }, - { /* [275] */ + { /* [285] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4369,7 +4527,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetLTCInfoForFBP" #endif }, - { /* [276] */ + { /* [286] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4384,7 +4542,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbCBCOp" #endif }, - { /* [277] */ + { /* [287] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4399,7 +4557,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCtagsForCbcEviction" #endif }, - { /* [278] */ + { /* [288] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4414,7 +4572,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetupVprRegion" #endif }, - { /* [279] */ + { /* [289] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4429,7 +4587,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCliManagedOfflinedPages" #endif }, - { /* [280] */ + { /* [290] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4444,7 +4602,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCompBitCopyConstructInfo" #endif }, - { /* [281] */ + { /* [291] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4459,7 +4617,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetRrd" #endif }, - { /* [282] */ + { /* [292] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4474,7 +4632,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetReadLimit" #endif }, - { /* [283] */ + { /* [293] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4489,7 +4647,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetWriteLimit" #endif }, - { /* [284] */ + { /* [294] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4504,7 +4662,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbPatchPbrForMining" #endif }, - { /* [285] */ + { /* [295] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4519,7 +4677,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetMemAlignment" #endif }, - { /* [286] */ + { /* [296] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4534,7 +4692,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetRemappedRows" #endif }, - { /* [287] */ + { /* [297] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4549,7 +4707,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetFsInfo" #endif }, - { /* [288] */ + { /* [298] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4564,7 +4722,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetRowRemapperHistogram" #endif }, - { /* [289] */ + { /* [299] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4579,7 +4737,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetDynamicOfflinedPages" #endif }, - { /* [290] */ + { /* [300] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4594,7 +4752,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbUpdateNumaStatus" #endif }, - { /* [291] */ + { /* [301] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4609,13 +4767,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetNumaInfo" #endif }, - { /* [292] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x812u) + { /* [302] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4813u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdMcGetArchInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x812u) - /*flags=*/ 0x812u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4813u) + /*flags=*/ 0x4813u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801701u, /*paramSize=*/ sizeof(NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS), @@ -4624,13 +4782,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcGetArchInfo" #endif }, - { /* [293] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [303] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdMcServiceInterrupts_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801702u, /*paramSize=*/ sizeof(NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS), @@ -4639,7 +4797,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcServiceInterrupts" #endif }, - { /* [294] */ + { /* [304] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4654,7 +4812,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcGetManufacturer" #endif }, - { /* [295] */ + { /* [305] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4669,7 +4827,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcQueryHostclkSlowdownStatus" #endif }, - { /* [296] */ + { /* [306] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4684,7 +4842,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcSetHostclkSlowdownStatus" #endif }, - { /* [297] */ + { /* [307] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4699,13 +4857,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcChangeReplayableFaultOwnership" #endif }, - { /* [298] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + { /* [308] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusGetPciInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) - /*flags=*/ 0x850u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4850u) + /*flags=*/ 0x4850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801801u, /*paramSize=*/ sizeof(NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS), @@ -4714,7 +4872,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPciInfo" #endif }, - { /* [299] */ + { /* [309] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4729,13 +4887,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetInfo" #endif }, - { /* [300] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + { /* [310] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusGetPciBarInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) - /*flags=*/ 0x850u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4850u) + /*flags=*/ 0x4850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801803u, /*paramSize=*/ sizeof(NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS), @@ -4744,7 +4902,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPciBarInfo" #endif }, - { /* [301] */ + { /* [311] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4759,7 +4917,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetPcieLinkWidth" #endif }, - { /* [302] */ + { /* [312] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4774,7 +4932,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetPcieSpeed" #endif }, - { /* [303] */ + { /* [313] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4789,7 +4947,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetHwbcUpstreamPcieSpeed" #endif }, - { /* [304] */ + { /* [314] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4804,7 +4962,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetHwbcUpstreamPcieSpeed" #endif }, - { /* [305] */ + { /* [315] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4819,7 +4977,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusHWBCGetUpstreamBAR0" #endif }, - { /* [306] */ + { /* [316] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4834,7 +4992,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusServiceGpuMultifunctionState" #endif }, - { /* [307] */ + { /* [317] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4849,7 +5007,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPexCounters" #endif }, - { /* [308] */ + { /* [318] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4864,7 +5022,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusClearPexCounters" #endif }, - { /* [309] */ + { /* [319] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4879,7 +5037,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusFreezePexCounters" #endif }, - { /* [310] */ + { /* [320] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4894,7 +5052,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPexLaneCounters" #endif }, - { /* [311] */ + { /* [321] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4909,7 +5067,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPcieLtrLatency" #endif }, - { /* [312] */ + { /* [322] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4924,7 +5082,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetPcieLtrLatency" #endif }, - { /* [313] */ + { /* [323] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4939,7 +5097,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPexUtilCounters" #endif }, - { /* [314] */ + { /* [324] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4954,7 +5112,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusClearPexUtilCounters" #endif }, - { /* [315] */ + { /* [325] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4969,7 +5127,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetBFD" #endif }, - { /* [316] */ + { /* [326] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4984,13 +5142,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetAspmDisableFlags" #endif }, - { /* [317] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + { /* [327] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusGetInfoV2_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) - /*flags=*/ 0x850u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200850u) + /*flags=*/ 0x200850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801823u, /*paramSize=*/ sizeof(NV2080_CTRL_BUS_GET_INFO_V2_PARAMS), @@ -4999,7 +5157,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetInfoV2" #endif }, - { /* [318] */ + { /* [328] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5014,7 +5172,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusControlPublicAspmBits" #endif }, - { /* [319] */ + { /* [329] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5029,7 +5187,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetNvlinkPeerIdMask" #endif }, - { /* [320] */ + { /* [330] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5044,7 +5202,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetEomParameters" #endif }, - { /* [321] */ + { /* [331] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5059,7 +5217,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetUphyDlnCfgSpace" #endif }, - { /* [322] */ + { /* [332] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5074,7 +5232,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetEomStatus" #endif }, - { /* [323] */ + { /* [333] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x6210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5089,7 +5247,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPcieReqAtomicsCaps" #endif }, - { /* [324] */ + { /* [334] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x6210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5104,7 +5262,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics" #endif }, - { /* [325] */ + { /* [335] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5119,13 +5277,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetC2CInfo" #endif }, - { /* [326] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10200u) + { /* [336] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10000u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusSysmemAccess_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10200u) - /*flags=*/ 0x10200u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10000u) + /*flags=*/ 0x10000u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080182cu, /*paramSize=*/ sizeof(NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS), @@ -5134,7 +5292,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSysmemAccess" #endif }, - { /* [327] */ + { /* [337] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5149,7 +5307,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetC2CErrorInfo" #endif }, - { /* [328] */ + { /* [338] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5164,7 +5322,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetP2pMapping" #endif }, - { /* [329] */ + { /* [339] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5179,13 +5337,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusUnsetP2pMapping" #endif }, - { /* [330] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + { /* [340] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKPerfBoost_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) - /*flags=*/ 0x810u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080200au, /*paramSize=*/ sizeof(NV2080_CTRL_PERF_BOOST_PARAMS), @@ -5194,7 +5352,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKPerfBoost" #endif }, - { /* [331] */ + { /* [341] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5209,7 +5367,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfSetPowerstate" #endif }, - { /* [332] */ + { /* [342] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5224,7 +5382,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfRatedTdpGetControl" #endif }, - { /* [333] */ + { /* [343] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5239,7 +5397,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfRatedTdpSetControl" #endif }, - { /* [334] */ + { /* [344] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5254,13 +5412,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfSetAuxPowerState" #endif }, - { /* [335] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [345] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdPerfReservePerfmonHw_DISPATCH, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) + /*flags=*/ 0x50u, /*accessRight=*/0x0u, /*methodId=*/ 0x20802093u, /*paramSize=*/ sizeof(NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS), @@ -5269,7 +5427,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfReservePerfmonHw" #endif }, - { /* [336] */ + { /* [346] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5284,7 +5442,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2" #endif }, - { /* [337] */ + { /* [347] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5299,7 +5457,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcReadVirtualMem" #endif }, - { /* [338] */ + { /* [348] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5314,7 +5472,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcGetErrorCount" #endif }, - { /* [339] */ + { /* [349] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5329,7 +5487,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcSetCleanErrorHistory" #endif }, - { /* [340] */ + { /* [350] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5344,7 +5502,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcGetWatchdogInfo" #endif }, - { /* [341] */ + { /* [351] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5359,7 +5517,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcDisableWatchdog" #endif }, - { /* [342] */ + { /* [352] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5374,7 +5532,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcEnableWatchdog" #endif }, - { /* [343] */ + { /* [353] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5389,7 +5547,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcReleaseWatchdogRequests" #endif }, - { /* [344] */ + { /* [354] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5404,7 +5562,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdSetRcRecovery" #endif }, - { /* [345] */ + { /* [355] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5419,7 +5577,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetRcRecovery" #endif }, - { /* [346] */ + { /* [356] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5434,7 +5592,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcSoftDisableWatchdog" #endif }, - { /* [347] */ + { /* [357] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5449,7 +5607,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdSetRcInfo" #endif }, - { /* [348] */ + { /* [358] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5464,7 +5622,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetRcInfo" #endif }, - { /* [349] */ + { /* [359] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5479,7 +5637,67 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcGetErrorV2" #endif }, - { /* [350] */ + { /* [360] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalGpioProgramDirection_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20802300u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalGpioProgramDirection" +#endif + }, + { /* [361] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalGpioProgramOutput_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20802301u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalGpioProgramOutput" +#endif + }, + { /* [362] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalGpioReadInput_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20802302u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalGpioReadInput" +#endif + }, + { /* [363] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalGpioActivateHwFunction_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20802303u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalGpioActivateHwFunction" +#endif + }, + { /* [364] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5494,7 +5712,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvdGetDumpSize" #endif }, - { /* [351] */ + { /* [365] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5509,7 +5727,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvdGetDump" #endif }, - { /* [352] */ + { /* [366] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5524,7 +5742,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvdGetNocatJournalRpt" #endif }, - { /* [353] */ + { /* [367] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5539,7 +5757,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvdSetNocatJournalData" #endif }, - { /* [354] */ + { /* [368] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5554,7 +5772,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDmaInvalidateTLB" #endif }, - { /* [355] */ + { /* [369] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5569,7 +5787,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDmaGetInfo" #endif }, - { /* [356] */ + { /* [370] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5584,7 +5802,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPmgrGetModuleInfo" #endif }, - { /* [357] */ + { /* [371] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5599,7 +5817,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdLpwrDifrCtrl" #endif }, - { /* [358] */ + { /* [372] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5614,7 +5832,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdLpwrDifrPrefetchResponse" #endif }, - { /* [359] */ + { /* [373] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5629,13 +5847,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetCaps" #endif }, - { /* [360] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x211u) + { /* [374] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2211u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdCeGetCePceMask_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x211u) - /*flags=*/ 0x211u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2211u) + /*flags=*/ 0x2211u, /*accessRight=*/0x0u, /*methodId=*/ 0x20802a02u, /*paramSize=*/ sizeof(NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS), @@ -5644,13 +5862,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetCePceMask" #endif }, - { /* [361] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + { /* [375] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdCeGetCapsV2_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) - /*flags=*/ 0x850u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) + /*flags=*/ 0x2850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20802a03u, /*paramSize=*/ sizeof(NV2080_CTRL_CE_GET_CAPS_V2_PARAMS), @@ -5659,7 +5877,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetCapsV2" #endif }, - { /* [362] */ + { /* [376] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5674,7 +5892,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeUpdatePceLceMappings" #endif }, - { /* [363] */ + { /* [377] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5689,7 +5907,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeUpdateClassDB" #endif }, - { /* [364] */ + { /* [378] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100e40u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5704,7 +5922,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetPhysicalCaps" #endif }, - { /* [365] */ + { /* [379] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c0200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5719,7 +5937,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetFaultMethodBufferSize" #endif }, - { /* [366] */ + { /* [380] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5734,7 +5952,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetHubPceMask" #endif }, - { /* [367] */ + { /* [381] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5749,7 +5967,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetAllCaps" #endif }, - { /* [368] */ + { /* [382] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe40u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5764,7 +5982,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetAllPhysicalCaps" #endif }, - { /* [369] */ + { /* [383] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5779,7 +5997,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetNvlinkCaps" #endif }, - { /* [370] */ + { /* [384] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5794,7 +6012,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetNvlinkStatus" #endif }, - { /* [371] */ + { /* [385] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5809,7 +6027,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetNvlinkErrInfo" #endif }, - { /* [372] */ + { /* [386] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5824,7 +6042,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetNvlinkCounters" #endif }, - { /* [373] */ + { /* [387] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5839,7 +6057,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdClearNvlinkCounters" #endif }, - { /* [374] */ + { /* [388] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5854,7 +6072,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetLinkFatalErrorCounts" #endif }, - { /* [375] */ + { /* [389] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5869,7 +6087,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSetupEom" #endif }, - { /* [376] */ + { /* [390] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5884,7 +6102,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetPowerState" #endif }, - { /* [377] */ + { /* [391] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5899,7 +6117,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinGetLinkFomValues" #endif }, - { /* [378] */ + { /* [392] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5914,7 +6132,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetNvlinkEccErrors" #endif }, - { /* [379] */ + { /* [393] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5929,7 +6147,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkReadTpCounters" #endif }, - { /* [380] */ + { /* [394] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5944,7 +6162,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEnableNvlinkPeer" #endif }, - { /* [381] */ + { /* [395] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5959,7 +6177,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetLpCounters" #endif }, - { /* [382] */ + { /* [396] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5974,7 +6192,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkCoreCallback" #endif }, - { /* [383] */ + { /* [397] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5989,7 +6207,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetAliEnabled" #endif }, - { /* [384] */ + { /* [398] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6004,7 +6222,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdateRemoteLocalSid" #endif }, - { /* [385] */ + { /* [399] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6019,7 +6237,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdateHshubMux" #endif }, - { /* [386] */ + { /* [400] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6034,7 +6252,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkPreSetupNvlinkPeer" #endif }, - { /* [387] */ + { /* [401] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6049,7 +6267,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkPostSetupNvlinkPeer" #endif }, - { /* [388] */ + { /* [402] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6064,7 +6282,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkRemoveNvlinkMapping" #endif }, - { /* [389] */ + { /* [403] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6079,7 +6297,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSaveRestoreHshubState" #endif }, - { /* [390] */ + { /* [404] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6094,7 +6312,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkProgramBufferready" #endif }, - { /* [391] */ + { /* [405] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6109,7 +6327,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdateCurrentConfig" #endif }, - { /* [392] */ + { /* [406] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6124,7 +6342,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSetLoopbackMode" #endif }, - { /* [393] */ + { /* [407] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6139,7 +6357,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdatePeerLinkMask" #endif }, - { /* [394] */ + { /* [408] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6154,7 +6372,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdateLinkConnection" #endif }, - { /* [395] */ + { /* [409] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6169,7 +6387,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEnableLinksPostTopology" #endif }, - { /* [396] */ + { /* [410] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6184,7 +6402,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkPreLinkTrainAli" #endif }, - { /* [397] */ + { /* [411] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6199,7 +6417,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetRefreshCounters" #endif }, - { /* [398] */ + { /* [412] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6214,7 +6432,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkClearRefreshCounters" #endif }, - { /* [399] */ + { /* [413] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6229,7 +6447,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetLinkMaskPostRxDet" #endif }, - { /* [400] */ + { /* [414] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6244,7 +6462,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkLinkTrainAli" #endif }, - { /* [401] */ + { /* [415] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6259,7 +6477,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetNvlinkDeviceInfo" #endif }, - { /* [402] */ + { /* [416] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6274,7 +6492,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetIoctrlDeviceInfo" #endif }, - { /* [403] */ + { /* [417] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6289,7 +6507,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkProgramLinkSpeed" #endif }, - { /* [404] */ + { /* [418] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6304,7 +6522,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkAreLinksTrained" #endif }, - { /* [405] */ + { /* [419] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6319,7 +6537,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkResetLinks" #endif }, - { /* [406] */ + { /* [420] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6334,7 +6552,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkDisableDlInterrupts" #endif }, - { /* [407] */ + { /* [421] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6349,7 +6567,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetLinkAndClockInfo" #endif }, - { /* [408] */ + { /* [422] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6364,7 +6582,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSetupNvlinkSysmem" #endif }, - { /* [409] */ + { /* [423] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6379,7 +6597,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkProcessForcedConfigs" #endif }, - { /* [410] */ + { /* [424] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6394,7 +6612,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSyncLaneShutdownProps" #endif }, - { /* [411] */ + { /* [425] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6409,7 +6627,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEnableSysmemNvlinkAts" #endif }, - { /* [412] */ + { /* [426] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6424,7 +6642,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkHshubGetSysmemNvlinkMask" #endif }, - { /* [413] */ + { /* [427] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6439,7 +6657,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetSetNvswitchFlaAddr" #endif }, - { /* [414] */ + { /* [428] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6454,7 +6672,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSyncLinkMasksAndVbiosInfo" #endif }, - { /* [415] */ + { /* [429] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6469,7 +6687,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEnableLinks" #endif }, - { /* [416] */ + { /* [430] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6484,7 +6702,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkProcessInitDisabledLinks" #endif }, - { /* [417] */ + { /* [431] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6499,7 +6717,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEomControl" #endif }, - { /* [418] */ + { /* [432] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6514,7 +6732,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSetL1Threshold" #endif }, - { /* [419] */ + { /* [433] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6529,7 +6747,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetL1Threshold" #endif }, - { /* [420] */ + { /* [434] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1240u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6544,7 +6762,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkInbandSendData" #endif }, - { /* [421] */ + { /* [435] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6559,7 +6777,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkDirectConnectCheck" #endif }, - { /* [422] */ + { /* [436] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6574,7 +6792,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkPostFaultUp" #endif }, - { /* [423] */ + { /* [437] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6589,7 +6807,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetDmemUsage" #endif }, - { /* [424] */ + { /* [438] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6604,7 +6822,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetEngineArch" #endif }, - { /* [425] */ + { /* [439] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6619,7 +6837,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnUstreamerQueueInfo" #endif }, - { /* [426] */ + { /* [440] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6634,7 +6852,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnUstreamerControlGet" #endif }, - { /* [427] */ + { /* [441] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6649,7 +6867,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnUstreamerControlSet" #endif }, - { /* [428] */ + { /* [442] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6664,7 +6882,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetCtxBufferInfo" #endif }, - { /* [429] */ + { /* [443] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6679,7 +6897,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetCtxBufferSize" #endif }, - { /* [430] */ + { /* [444] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6694,7 +6912,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEccGetClientExposedCounters" #endif }, - { /* [431] */ + { /* [445] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6709,7 +6927,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaRange" #endif }, - { /* [432] */ + { /* [446] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6724,7 +6942,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaSetupInstanceMemBlock" #endif }, - { /* [433] */ + { /* [447] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100004u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6739,7 +6957,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaGetRange" #endif }, - { /* [434] */ + { /* [448] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6754,13 +6972,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaGetFabricMemStats" #endif }, - { /* [435] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x211u) + { /* [449] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4211u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGspGetFeatures_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x211u) - /*flags=*/ 0x211u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4211u) + /*flags=*/ 0x4211u, /*accessRight=*/0x0u, /*methodId=*/ 0x20803601u, /*paramSize=*/ sizeof(NV2080_CTRL_GSP_GET_FEATURES_PARAMS), @@ -6769,7 +6987,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGspGetFeatures" #endif }, - { /* [436] */ + { /* [450] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6784,7 +7002,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGrmgrGetGrFsInfo" #endif }, - { /* [437] */ + { /* [451] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x3u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6799,7 +7017,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixGc6BlockerRefCnt" #endif }, - { /* [438] */ + { /* [452] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6814,7 +7032,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixAllowDisallowGcoff" #endif }, - { /* [439] */ + { /* [453] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6829,7 +7047,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixAudioDynamicPower" #endif }, - { /* [440] */ + { /* [454] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6844,7 +7062,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixVidmemPersistenceStatus" #endif }, - { /* [441] */ + { /* [455] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6859,7 +7077,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixUpdateTgpStatus" #endif }, - { /* [442] */ + { /* [456] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6874,7 +7092,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask" #endif }, - { /* [443] */ + { /* [457] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6889,7 +7107,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask" #endif }, - { /* [444] */ + { /* [458] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6904,7 +7122,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType" #endif }, - { /* [445] */ + { /* [459] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6919,7 +7137,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalEnumerateVgpuPerPgpu" #endif }, - { /* [446] */ + { /* [460] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6934,7 +7152,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalClearGuestVmInfo" #endif }, - { /* [447] */ + { /* [461] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6949,7 +7167,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetVgpuFbUsage" #endif }, - { /* [448] */ + { /* [462] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6964,7 +7182,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalSetVgpuEncoderCapacity" #endif }, - { /* [449] */ + { /* [463] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6979,7 +7197,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalCleanupGspVgpuPluginResources" #endif }, - { /* [450] */ + { /* [464] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6994,7 +7212,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetPgpuFsEncoding" #endif }, - { /* [451] */ + { /* [465] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7009,7 +7227,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetPgpuMigrationSupport" #endif }, - { /* [452] */ + { /* [466] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7024,7 +7242,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig" #endif }, - { /* [453] */ + { /* [467] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7039,7 +7257,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetAvailableHshubMask" #endif }, - { /* [454] */ + { /* [468] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7059,7 +7277,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic const struct NVOC_EXPORT_INFO __nvoc_export_info_Subdevice = { - /*numEntries=*/ 455, + /*numEntries=*/ 469, /*pExportEntries=*/ __nvoc_exported_method_def_Subdevice }; @@ -7139,7 +7357,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdBiosGetUefiSupport__ = &subdeviceCtrlCmdBiosGetUefiSupport_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x812u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4813u) pThis->__subdeviceCtrlCmdMcGetArchInfo__ = &subdeviceCtrlCmdMcGetArchInfo_IMPL; #endif @@ -7159,7 +7377,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdMcChangeReplayableFaultOwnership__ = &subdeviceCtrlCmdMcChangeReplayableFaultOwnership_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdMcServiceInterrupts__ = &subdeviceCtrlCmdMcServiceInterrupts_IMPL; #endif @@ -7171,7 +7389,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdDmaGetInfo__ = &subdeviceCtrlCmdDmaGetInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4850u) pThis->__subdeviceCtrlCmdBusGetPciInfo__ = &subdeviceCtrlCmdBusGetPciInfo_IMPL; #endif @@ -7179,11 +7397,11 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdBusGetInfo__ = &subdeviceCtrlCmdBusGetInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200850u) pThis->__subdeviceCtrlCmdBusGetInfoV2__ = &subdeviceCtrlCmdBusGetInfoV2_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4850u) pThis->__subdeviceCtrlCmdBusGetPciBarInfo__ = &subdeviceCtrlCmdBusGetPciBarInfo_IMPL; #endif @@ -7287,7 +7505,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdBusGetC2CErrorInfo__ = &subdeviceCtrlCmdBusGetC2CErrorInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10200u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10000u) pThis->__subdeviceCtrlCmdBusSysmemAccess__ = &subdeviceCtrlCmdBusSysmemAccess_IMPL; #endif @@ -7567,7 +7785,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdPerfSetPowerstate__ = &subdeviceCtrlCmdPerfSetPowerstate_KERNEL; } -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdKPerfBoost__ = &subdeviceCtrlCmdKPerfBoost_IMPL; #endif @@ -7755,7 +7973,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGetPhysicalChannelCount__ = &subdeviceCtrlCmdGetPhysicalChannelCount_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200010u) pThis->__subdeviceCtrlCmdFifoGetInfo__ = &subdeviceCtrlCmdFifoGetInfo_IMPL; #endif @@ -7807,6 +8025,10 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdFifoGetAllocatedChannels__ = &subdeviceCtrlCmdFifoGetAllocatedChannels_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2610u) + pThis->__subdeviceCtrlCmdInternalFifoGetNumSecureChannels__ = &subdeviceCtrlCmdInternalFifoGetNumSecureChannels_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) pThis->__subdeviceCtrlCmdKGrGetInfo__ = &subdeviceCtrlCmdKGrGetInfo_IMPL; #endif @@ -8023,7 +8245,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGpuGetCachedInfo__ = &subdeviceCtrlCmdGpuGetCachedInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200850u) pThis->__subdeviceCtrlCmdGpuGetInfoV2__ = &subdeviceCtrlCmdGpuGetInfoV2_IMPL; #endif @@ -8043,7 +8265,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGpuSetOptimusInfo__ = &subdeviceCtrlCmdGpuSetOptimusInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa12u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200a12u) pThis->__subdeviceCtrlCmdGpuGetNameString__ = &subdeviceCtrlCmdGpuGetNameString_IMPL; #endif @@ -8063,6 +8285,10 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGpuGetNvencSwSessionInfo__ = &subdeviceCtrlCmdGpuGetNvencSwSessionInfo_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__subdeviceCtrlCmdGpuGetNvencSwSessionInfoV2__ = &subdeviceCtrlCmdGpuGetNvencSwSessionInfoV2_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__subdeviceCtrlCmdGpuGetNvfbcSwSessionStats__ = &subdeviceCtrlCmdGpuGetNvfbcSwSessionStats_IMPL; #endif @@ -8087,7 +8313,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGpuSetSdm__ = &subdeviceCtrlCmdGpuSetSdm_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4813u) pThis->__subdeviceCtrlCmdGpuGetSimulationInfo__ = &subdeviceCtrlCmdGpuGetSimulationInfo_IMPL; #endif @@ -8115,7 +8341,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGpuGetFermiTpcInfo__ = &subdeviceCtrlCmdGpuGetFermiTpcInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdGpuGetFermiZcullInfo__ = &subdeviceCtrlCmdGpuGetFermiZcullInfo_IMPL; #endif @@ -8162,14 +8388,6 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4210u) pThis->__subdeviceCtrlCmdGpuGetOEMInfo__ = &subdeviceCtrlCmdGpuGetOEMInfo_IMPL; #endif - -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) - pThis->__subdeviceCtrlCmdGpuHandleGpuSR__ = &subdeviceCtrlCmdGpuHandleGpuSR_IMPL; -#endif - -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x844u) - pThis->__subdeviceCtrlCmdGpuSetComputeModeRules__ = &subdeviceCtrlCmdGpuSetComputeModeRules_IMPL; -#endif } static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) { @@ -8180,7 +8398,15 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * PORT_UNREFERENCED_VARIABLE(rmVariantHal); PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) + pThis->__subdeviceCtrlCmdGpuHandleGpuSR__ = &subdeviceCtrlCmdGpuHandleGpuSR_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x844u) + pThis->__subdeviceCtrlCmdGpuSetComputeModeRules__ = &subdeviceCtrlCmdGpuSetComputeModeRules_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__subdeviceCtrlCmdGpuQueryComputeModeRules__ = &subdeviceCtrlCmdGpuQueryComputeModeRules_IMPL; #endif @@ -8264,6 +8490,10 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGpuGetHwEngineId__ = &subdeviceCtrlCmdGpuGetHwEngineId_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4210u) + pThis->__subdeviceCtrlCmdGpuGetVmmuSegmentSize__ = &subdeviceCtrlCmdGpuGetVmmuSegmentSize_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) pThis->__subdeviceCtrlCmdGpuGetMaxSupportedPageSize__ = &subdeviceCtrlCmdGpuGetMaxSupportedPageSize_IMPL; #endif @@ -8272,15 +8502,15 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGpuHandleVfPriFault__ = &subdeviceCtrlCmdGpuHandleVfPriFault_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x807u) pThis->__subdeviceCtrlCmdGpuSetComputePolicyConfig__ = &subdeviceCtrlCmdGpuSetComputePolicyConfig_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) pThis->__subdeviceCtrlCmdGpuGetComputePolicyConfig__ = &subdeviceCtrlCmdGpuGetComputePolicyConfig_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x840u) pThis->__subdeviceCtrlCmdValidateMemMapRequest__ = &subdeviceCtrlCmdValidateMemMapRequest_IMPL; #endif @@ -8304,6 +8534,14 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGetGpuFabricProbeInfo__ = &subdeviceCtrlCmdGetGpuFabricProbeInfo_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__subdeviceCtrlCmdGpuGetResetStatus__ = &subdeviceCtrlCmdGpuGetResetStatus_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__subdeviceCtrlCmdGpuGetDrainAndResetStatus__ = &subdeviceCtrlCmdGpuGetDrainAndResetStatus_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__subdeviceCtrlCmdEventSetTrigger__ = &subdeviceCtrlCmdEventSetTrigger_IMPL; #endif @@ -8440,7 +8678,7 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdCeGetCaps__ = &subdeviceCtrlCmdCeGetCaps_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x211u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2211u) pThis->__subdeviceCtrlCmdCeGetCePceMask__ = &subdeviceCtrlCmdCeGetCePceMask_IMPL; #endif @@ -8448,7 +8686,7 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdCeUpdatePceLceMappings__ = &subdeviceCtrlCmdCeUpdatePceLceMappings_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) pThis->__subdeviceCtrlCmdCeGetCapsV2__ = &subdeviceCtrlCmdCeGetCapsV2_IMPL; #endif @@ -8516,7 +8754,7 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdFlaGetFabricMemStats__ = &subdeviceCtrlCmdFlaGetFabricMemStats_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x211u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4211u) pThis->__subdeviceCtrlCmdGspGetFeatures__ = &subdeviceCtrlCmdGspGetFeatures_IMPL; #endif @@ -8624,6 +8862,30 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdDisplayGetDisplayMask__ = &subdeviceCtrlCmdDisplayGetDisplayMask_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdDisplayPinsetsToLockpins__ = &subdeviceCtrlCmdDisplayPinsetsToLockpins_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdDisplaySetSliLinkGpioSwControl__ = &subdeviceCtrlCmdDisplaySetSliLinkGpioSwControl_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalGpioProgramDirection__ = &subdeviceCtrlCmdInternalGpioProgramDirection_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalGpioProgramOutput__ = &subdeviceCtrlCmdInternalGpioProgramOutput_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalGpioReadInput__ = &subdeviceCtrlCmdInternalGpioReadInput_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalGpioActivateHwFunction__ = &subdeviceCtrlCmdInternalGpioActivateHwFunction_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) pThis->__subdeviceCtrlCmdMsencGetCaps__ = &subdeviceCtrlCmdMsencGetCaps_IMPL; #endif @@ -8692,6 +8954,10 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdInternalBusRemoveC2cPeerMapping__ = &subdeviceCtrlCmdInternalBusRemoveC2cPeerMapping_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalVmmuGetSpaForGpaEntries__ = &subdeviceCtrlCmdInternalVmmuGetSpaForGpaEntries_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) pThis->__subdeviceCtrlCmdGmmuGetStaticInfo__ = &subdeviceCtrlCmdGmmuGetStaticInfo_IMPL; #endif @@ -8800,6 +9066,10 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdBifSetPcieRo__ = &subdeviceCtrlCmdBifSetPcieRo_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdBifDisableSystemMemoryAccess__ = &subdeviceCtrlCmdBifDisableSystemMemoryAccess_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) pThis->__subdeviceCtrlCmdHshubPeerConnConfig__ = &subdeviceCtrlCmdHshubPeerConnConfig_IMPL; #endif @@ -8896,6 +9166,10 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit__ = &subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalDetectHsVideoBridge__ = &subdeviceCtrlCmdInternalDetectHsVideoBridge_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) pThis->__subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask__ = &subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask_IMPL; #endif @@ -8964,11 +9238,11 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceShareCallback__ = &__nvoc_thunk_GpuResource_subdeviceShareCallback; - pThis->__subdeviceMapTo__ = &__nvoc_thunk_RsResource_subdeviceMapTo; + pThis->__subdeviceCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_subdeviceCheckMemInterUnmap; pThis->__subdeviceGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_subdeviceGetOrAllocNotifShare; - pThis->__subdeviceCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_subdeviceCheckMemInterUnmap; + pThis->__subdeviceMapTo__ = &__nvoc_thunk_RsResource_subdeviceMapTo; pThis->__subdeviceGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_subdeviceGetMapAddrSpace; @@ -9000,10 +9274,14 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceUnregisterEvent__ = &__nvoc_thunk_Notifier_subdeviceUnregisterEvent; + pThis->__subdeviceControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_subdeviceControlSerialization_Prologue; + pThis->__subdeviceCanCopy__ = &__nvoc_thunk_RsResource_subdeviceCanCopy; pThis->__subdeviceIsDuplicate__ = &__nvoc_thunk_RsResource_subdeviceIsDuplicate; + pThis->__subdeviceControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_subdeviceControlSerialization_Epilogue; + pThis->__subdeviceGetNotificationListPtr__ = &__nvoc_thunk_Notifier_subdeviceGetNotificationListPtr; pThis->__subdeviceGetNotificationShare__ = &__nvoc_thunk_Notifier_subdeviceGetNotificationShare; @@ -9040,13 +9318,16 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice **ppThis, Dynamic *pParent, NvU32 Subdevice *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(Subdevice)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Subdevice), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(Subdevice)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Subdevice); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -9066,11 +9347,17 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice **ppThis, Dynamic *pParent, NvU32 if (status != NV_OK) goto __nvoc_objCreate_Subdevice_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_Subdevice_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(Subdevice)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_subdevice_nvoc.h b/src/nvidia/generated/g_subdevice_nvoc.h index 24b283ce6..0e89fa870 100644 --- a/src/nvidia/generated/g_subdevice_nvoc.h +++ b/src/nvidia/generated/g_subdevice_nvoc.h @@ -289,6 +289,7 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdInternalFifoPromoteRunlistBuffers__)(struct Subdevice *, NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalFifoGetNumChannels__)(struct Subdevice *, NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFifoGetAllocatedChannels__)(struct Subdevice *, NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalFifoGetNumSecureChannels__)(struct Subdevice *, NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKGrGetInfo__)(struct Subdevice *, NV2080_CTRL_GR_GET_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKGrGetInfoV2__)(struct Subdevice *, NV2080_CTRL_GR_GET_INFO_V2_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKGrGetCapsV2__)(struct Subdevice *, NV2080_CTRL_GR_GET_CAPS_V2_PARAMS *); @@ -310,7 +311,7 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdKGrGetCtxBufferSize__)(struct Subdevice *, NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKGrGetCtxBufferInfo__)(struct Subdevice *, NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKGrGetCtxBufferPtes__)(struct Subdevice *, NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS *); - NV_STATUS (*__subdeviceCtrlCmdKGrGetCurrentResidentChannel__)(struct Subdevice *, NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdKGrGetCurrentResidentChannel__)(struct Subdevice *, NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKGrGetVatAlarmData__)(struct Subdevice *, NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKGrGetAttributeBufferSize__)(struct Subdevice *, NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKGrGfxPoolQuerySize__)(struct Subdevice *, NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS *); @@ -353,6 +354,7 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdGpuGetEncoderCapacity__)(struct Subdevice *, NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetNvencSwSessionStats__)(struct Subdevice *, NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetNvencSwSessionInfo__)(struct Subdevice *, NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdGpuGetNvencSwSessionInfoV2__)(struct Subdevice *, NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetNvfbcSwSessionStats__)(struct Subdevice *, NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetNvfbcSwSessionInfo__)(struct Subdevice *, NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuSetFabricAddr__)(struct Subdevice *, NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS *); @@ -401,6 +403,7 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdGpuGetEngineFaultInfo__)(struct Subdevice *, NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetEngineRunlistPriBase__)(struct Subdevice *, NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetHwEngineId__)(struct Subdevice *, NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdGpuGetVmmuSegmentSize__)(struct Subdevice *, NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetMaxSupportedPageSize__)(struct Subdevice *, NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuHandleVfPriFault__)(struct Subdevice *, NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuSetComputePolicyConfig__)(struct Subdevice *, NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS *); @@ -411,6 +414,8 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdGpuGetEngineLoadTimes__)(struct Subdevice *, NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGetP2pCaps__)(struct Subdevice *, NV2080_CTRL_GET_P2P_CAPS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGetGpuFabricProbeInfo__)(struct Subdevice *, NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdGpuGetResetStatus__)(struct Subdevice *, NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdGpuGetDrainAndResetStatus__)(struct Subdevice *, NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdEventSetTrigger__)(struct Subdevice *); NV_STATUS (*__subdeviceCtrlCmdEventSetTriggerFifo__)(struct Subdevice *, NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdEventSetNotification__)(struct Subdevice *, NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS *); @@ -491,6 +496,12 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdDisplaySetupRgLineIntr__)(struct Subdevice *, NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdDisplaySetImportedImpData__)(struct Subdevice *, NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdDisplayGetDisplayMask__)(struct Subdevice *, NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdDisplayPinsetsToLockpins__)(struct Subdevice *, NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdDisplaySetSliLinkGpioSwControl__)(struct Subdevice *, NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalGpioProgramDirection__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalGpioProgramOutput__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalGpioReadInput__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalGpioActivateHwFunction__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdMsencGetCaps__)(struct Subdevice *, NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer__)(struct Subdevice *, NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer__)(struct Subdevice *); @@ -508,11 +519,12 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdInternalBusDestroyP2pMailbox__)(struct Subdevice *, NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalBusCreateC2cPeerMapping__)(struct Subdevice *, NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalBusRemoveC2cPeerMapping__)(struct Subdevice *, NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalVmmuGetSpaForGpaEntries__)(struct Subdevice *, NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGmmuGetStaticInfo__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalGmmuRegisterFaultBuffer__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalGmmuUnregisterFaultBuffer__)(struct Subdevice *); NV_STATUS (*__subdeviceCtrlCmdInternalGmmuRegisterClientShadowFaultBuffer__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS *); - NV_STATUS (*__subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer__)(struct Subdevice *); + NV_STATUS (*__subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalGmmuCopyReservedSplitGVASpacePdesServer__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdCeGetPhysicalCaps__)(struct Subdevice *, NV2080_CTRL_CE_GET_CAPS_V2_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdCeGetAllPhysicalCaps__)(struct Subdevice *, NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *); @@ -535,6 +547,7 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdBifGetStaticInfo__)(struct Subdevice *, NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBifGetAspmL1Flags__)(struct Subdevice *, NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBifSetPcieRo__)(struct Subdevice *, NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdBifDisableSystemMemoryAccess__)(struct Subdevice *, NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdHshubPeerConnConfig__)(struct Subdevice *, NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdHshubFirstLinkPeerId__)(struct Subdevice *, NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdHshubGetHshubIdForLinks__)(struct Subdevice *, NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS *); @@ -559,6 +572,7 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdInternalFbsrSendRegionInfo__)(struct Subdevice *, NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalPostInitBrightcStateLoad__)(struct Subdevice *, NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit__)(struct Subdevice *); + NV_STATUS (*__subdeviceCtrlCmdInternalDetectHsVideoBridge__)(struct Subdevice *); NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS *); @@ -575,9 +589,9 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdCcuUnmap__)(struct Subdevice *, NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdCcuSetStreamState__)(struct Subdevice *, NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS *); NvBool (*__subdeviceShareCallback__)(struct Subdevice *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__subdeviceMapTo__)(struct Subdevice *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__subdeviceGetOrAllocNotifShare__)(struct Subdevice *, NvHandle, NvHandle, struct NotifShare **); NV_STATUS (*__subdeviceCheckMemInterUnmap__)(struct Subdevice *, NvBool); + NV_STATUS (*__subdeviceGetOrAllocNotifShare__)(struct Subdevice *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__subdeviceMapTo__)(struct Subdevice *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__subdeviceGetMapAddrSpace__)(struct Subdevice *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); void (*__subdeviceSetNotificationShare__)(struct Subdevice *, struct NotifShare *); NvU32 (*__subdeviceGetRefCount__)(struct Subdevice *); @@ -593,8 +607,10 @@ struct Subdevice { NV_STATUS (*__subdeviceGetMemInterMapParams__)(struct Subdevice *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__subdeviceGetMemoryMappingDescriptor__)(struct Subdevice *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__subdeviceUnregisterEvent__)(struct Subdevice *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__subdeviceControlSerialization_Prologue__)(struct Subdevice *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__subdeviceCanCopy__)(struct Subdevice *); NV_STATUS (*__subdeviceIsDuplicate__)(struct Subdevice *, NvHandle, NvBool *); + void (*__subdeviceControlSerialization_Epilogue__)(struct Subdevice *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__subdeviceGetNotificationListPtr__)(struct Subdevice *); struct NotifShare *(*__subdeviceGetNotificationShare__)(struct Subdevice *); NV_STATUS (*__subdeviceMap__)(struct Subdevice *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -604,7 +620,7 @@ struct Subdevice { struct Device *pDevice; NvBool bMaxGrTickFreqRequested; NvU64 P2PfbMappedBytes; - NvU32 notifyActions[178]; + NvU32 notifyActions[179]; NvHandle hNotifierMemory; struct Memory *pNotifierMemory; NvHandle hSemMemory; @@ -834,6 +850,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdInternalFifoPromoteRunlistBuffers(pSubdevice, pParams) subdeviceCtrlCmdInternalFifoPromoteRunlistBuffers_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalFifoGetNumChannels(pSubdevice, pNumChannelsParams) subdeviceCtrlCmdInternalFifoGetNumChannels_DISPATCH(pSubdevice, pNumChannelsParams) #define subdeviceCtrlCmdFifoGetAllocatedChannels(pSubdevice, pParams) subdeviceCtrlCmdFifoGetAllocatedChannels_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalFifoGetNumSecureChannels(pSubdevice, pNumSecureChannelsParams) subdeviceCtrlCmdInternalFifoGetNumSecureChannels_DISPATCH(pSubdevice, pNumSecureChannelsParams) #define subdeviceCtrlCmdKGrGetInfo(pSubdevice, pParams) subdeviceCtrlCmdKGrGetInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdKGrGetInfoV2(pSubdevice, pParams) subdeviceCtrlCmdKGrGetInfoV2_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdKGrGetCapsV2(pSubdevice, pGrCapsParams) subdeviceCtrlCmdKGrGetCapsV2_DISPATCH(pSubdevice, pGrCapsParams) @@ -898,6 +915,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdGpuGetEncoderCapacity(pSubdevice, pEncoderCapacityParams) subdeviceCtrlCmdGpuGetEncoderCapacity_DISPATCH(pSubdevice, pEncoderCapacityParams) #define subdeviceCtrlCmdGpuGetNvencSwSessionStats(pSubdevice, pParams) subdeviceCtrlCmdGpuGetNvencSwSessionStats_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuGetNvencSwSessionInfo(pSubdevice, pParams) subdeviceCtrlCmdGpuGetNvencSwSessionInfo_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdGpuGetNvencSwSessionInfoV2(pSubdevice, pParams) subdeviceCtrlCmdGpuGetNvencSwSessionInfoV2_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuGetNvfbcSwSessionStats(pSubdevice, params) subdeviceCtrlCmdGpuGetNvfbcSwSessionStats_DISPATCH(pSubdevice, params) #define subdeviceCtrlCmdGpuGetNvfbcSwSessionInfo(pSubdevice, params) subdeviceCtrlCmdGpuGetNvfbcSwSessionInfo_DISPATCH(pSubdevice, params) #define subdeviceCtrlCmdGpuSetFabricAddr(pSubdevice, pParams) subdeviceCtrlCmdGpuSetFabricAddr_DISPATCH(pSubdevice, pParams) @@ -946,6 +964,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdGpuGetEngineFaultInfo(pSubdevice, pParams) subdeviceCtrlCmdGpuGetEngineFaultInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuGetEngineRunlistPriBase(pSubdevice, pParams) subdeviceCtrlCmdGpuGetEngineRunlistPriBase_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuGetHwEngineId(pSubdevice, pParams) subdeviceCtrlCmdGpuGetHwEngineId_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdGpuGetVmmuSegmentSize(pSubdevice, pParams) subdeviceCtrlCmdGpuGetVmmuSegmentSize_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuGetMaxSupportedPageSize(pSubdevice, pParams) subdeviceCtrlCmdGpuGetMaxSupportedPageSize_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuHandleVfPriFault(pSubdevice, pParams) subdeviceCtrlCmdGpuHandleVfPriFault_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuSetComputePolicyConfig(pSubdevice, pParams) subdeviceCtrlCmdGpuSetComputePolicyConfig_DISPATCH(pSubdevice, pParams) @@ -956,6 +975,8 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdGpuGetEngineLoadTimes(pSubdevice, pParams) subdeviceCtrlCmdGpuGetEngineLoadTimes_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGetP2pCaps(pSubdevice, pParams) subdeviceCtrlCmdGetP2pCaps_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGetGpuFabricProbeInfo(pSubdevice, pParams) subdeviceCtrlCmdGetGpuFabricProbeInfo_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdGpuGetResetStatus(pSubdevice, pParams) subdeviceCtrlCmdGpuGetResetStatus_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdGpuGetDrainAndResetStatus(pSubdevice, pParams) subdeviceCtrlCmdGpuGetDrainAndResetStatus_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdEventSetTrigger(pSubdevice) subdeviceCtrlCmdEventSetTrigger_DISPATCH(pSubdevice) #define subdeviceCtrlCmdEventSetTriggerFifo(pSubdevice, pTriggerFifoParams) subdeviceCtrlCmdEventSetTriggerFifo_DISPATCH(pSubdevice, pTriggerFifoParams) #define subdeviceCtrlCmdEventSetNotification(pSubdevice, pSetEventParams) subdeviceCtrlCmdEventSetNotification_DISPATCH(pSubdevice, pSetEventParams) @@ -1036,6 +1057,12 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdDisplaySetupRgLineIntr(pSubdevice, pParams) subdeviceCtrlCmdDisplaySetupRgLineIntr_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdDisplaySetImportedImpData(pSubdevice, pParams) subdeviceCtrlCmdDisplaySetImportedImpData_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdDisplayGetDisplayMask(pSubdevice, pParams) subdeviceCtrlCmdDisplayGetDisplayMask_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdDisplayPinsetsToLockpins(pSubdevice, pParams) subdeviceCtrlCmdDisplayPinsetsToLockpins_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdDisplaySetSliLinkGpioSwControl(pSubdevice, pParams) subdeviceCtrlCmdDisplaySetSliLinkGpioSwControl_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalGpioProgramDirection(pSubdevice, pParams) subdeviceCtrlCmdInternalGpioProgramDirection_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalGpioProgramOutput(pSubdevice, pParams) subdeviceCtrlCmdInternalGpioProgramOutput_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalGpioReadInput(pSubdevice, pParams) subdeviceCtrlCmdInternalGpioReadInput_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalGpioActivateHwFunction(pSubdevice, pParams) subdeviceCtrlCmdInternalGpioActivateHwFunction_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdMsencGetCaps(pSubdevice, pParams) subdeviceCtrlCmdMsencGetCaps_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer(pSubdevice, pParams) subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer(pSubdevice) subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer_DISPATCH(pSubdevice) @@ -1053,11 +1080,12 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdInternalBusDestroyP2pMailbox(pSubdevice, pParams) subdeviceCtrlCmdInternalBusDestroyP2pMailbox_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalBusCreateC2cPeerMapping(pSubdevice, pParams) subdeviceCtrlCmdInternalBusCreateC2cPeerMapping_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalBusRemoveC2cPeerMapping(pSubdevice, pParams) subdeviceCtrlCmdInternalBusRemoveC2cPeerMapping_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalVmmuGetSpaForGpaEntries(pSubdevice, pParams) subdeviceCtrlCmdInternalVmmuGetSpaForGpaEntries_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGmmuGetStaticInfo(pSubdevice, pParams) subdeviceCtrlCmdGmmuGetStaticInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalGmmuRegisterFaultBuffer(pSubdevice, pParams) subdeviceCtrlCmdInternalGmmuRegisterFaultBuffer_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalGmmuUnregisterFaultBuffer(pSubdevice) subdeviceCtrlCmdInternalGmmuUnregisterFaultBuffer_DISPATCH(pSubdevice) #define subdeviceCtrlCmdInternalGmmuRegisterClientShadowFaultBuffer(pSubdevice, pParams) subdeviceCtrlCmdInternalGmmuRegisterClientShadowFaultBuffer_DISPATCH(pSubdevice, pParams) -#define subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer(pSubdevice) subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer_DISPATCH(pSubdevice) +#define subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer(pSubdevice, pParams) subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalGmmuCopyReservedSplitGVASpacePdesServer(pSubdevice, pCopyServerReservedPdesParams) subdeviceCtrlCmdInternalGmmuCopyReservedSplitGVASpacePdesServer_DISPATCH(pSubdevice, pCopyServerReservedPdesParams) #define subdeviceCtrlCmdCeGetPhysicalCaps(pSubdevice, pCeCapsParams) subdeviceCtrlCmdCeGetPhysicalCaps_DISPATCH(pSubdevice, pCeCapsParams) #define subdeviceCtrlCmdCeGetAllPhysicalCaps(pSubdevice, pCeCapsParams) subdeviceCtrlCmdCeGetAllPhysicalCaps_DISPATCH(pSubdevice, pCeCapsParams) @@ -1080,6 +1108,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdBifGetStaticInfo(pSubdevice, pParams) subdeviceCtrlCmdBifGetStaticInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBifGetAspmL1Flags(pSubdevice, pParams) subdeviceCtrlCmdBifGetAspmL1Flags_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBifSetPcieRo(pSubdevice, pParams) subdeviceCtrlCmdBifSetPcieRo_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdBifDisableSystemMemoryAccess(pSubdevice, pParams) subdeviceCtrlCmdBifDisableSystemMemoryAccess_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdHshubPeerConnConfig(pSubdevice, pParams) subdeviceCtrlCmdHshubPeerConnConfig_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdHshubFirstLinkPeerId(pSubdevice, pParams) subdeviceCtrlCmdHshubFirstLinkPeerId_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdHshubGetHshubIdForLinks(pSubdevice, pParams) subdeviceCtrlCmdHshubGetHshubIdForLinks_DISPATCH(pSubdevice, pParams) @@ -1104,6 +1133,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdInternalFbsrSendRegionInfo(pSubdevice, pParams) subdeviceCtrlCmdInternalFbsrSendRegionInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalPostInitBrightcStateLoad(pSubdevice, pParams) subdeviceCtrlCmdInternalPostInitBrightcStateLoad_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit(pSubdevice) subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit_DISPATCH(pSubdevice) +#define subdeviceCtrlCmdInternalDetectHsVideoBridge(pSubdevice) subdeviceCtrlCmdInternalDetectHsVideoBridge_DISPATCH(pSubdevice) #define subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType_DISPATCH(pSubdevice, pParams) @@ -1120,9 +1150,9 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdCcuUnmap(pSubdevice, pParams) subdeviceCtrlCmdCcuUnmap_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdCcuSetStreamState(pSubdevice, pParams) subdeviceCtrlCmdCcuSetStreamState_DISPATCH(pSubdevice, pParams) #define subdeviceShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) subdeviceShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define subdeviceMapTo(pResource, pParams) subdeviceMapTo_DISPATCH(pResource, pParams) -#define subdeviceGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) subdeviceGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) #define subdeviceCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) subdeviceCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define subdeviceGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) subdeviceGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define subdeviceMapTo(pResource, pParams) subdeviceMapTo_DISPATCH(pResource, pParams) #define subdeviceGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) subdeviceGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) #define subdeviceSetNotificationShare(pNotifier, pNotifShare) subdeviceSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define subdeviceGetRefCount(pResource) subdeviceGetRefCount_DISPATCH(pResource) @@ -1138,8 +1168,10 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceGetMemInterMapParams(pRmResource, pParams) subdeviceGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define subdeviceGetMemoryMappingDescriptor(pRmResource, ppMemDesc) subdeviceGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define subdeviceUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) subdeviceUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define subdeviceControlSerialization_Prologue(pResource, pCallContext, pParams) subdeviceControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define subdeviceCanCopy(pResource) subdeviceCanCopy_DISPATCH(pResource) #define subdeviceIsDuplicate(pResource, hMemory, pDuplicate) subdeviceIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define subdeviceControlSerialization_Epilogue(pResource, pCallContext, pParams) subdeviceControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define subdeviceGetNotificationListPtr(pNotifier) subdeviceGetNotificationListPtr_DISPATCH(pNotifier) #define subdeviceGetNotificationShare(pNotifier) subdeviceGetNotificationShare_DISPATCH(pNotifier) #define subdeviceMap(pGpuResource, pCallContext, pParams, pCpuMapping) subdeviceMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -2184,6 +2216,12 @@ static inline NV_STATUS subdeviceCtrlCmdFifoGetAllocatedChannels_DISPATCH(struct return pSubdevice->__subdeviceCtrlCmdFifoGetAllocatedChannels__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdInternalFifoGetNumSecureChannels_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS *pNumSecureChannelsParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalFifoGetNumSecureChannels_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS *pNumSecureChannelsParams) { + return pSubdevice->__subdeviceCtrlCmdInternalFifoGetNumSecureChannels__(pSubdevice, pNumSecureChannelsParams); +} + NV_STATUS subdeviceCtrlCmdKGrGetInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GR_GET_INFO_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdKGrGetInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GR_GET_INFO_PARAMS *pParams) { @@ -2310,9 +2348,9 @@ static inline NV_STATUS subdeviceCtrlCmdKGrGetCtxBufferPtes_DISPATCH(struct Subd return pSubdevice->__subdeviceCtrlCmdKGrGetCtxBufferPtes__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdKGrGetCurrentResidentChannel_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS *pParams); +NV_STATUS subdeviceCtrlCmdKGrGetCurrentResidentChannel_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS *pParams); -static inline NV_STATUS subdeviceCtrlCmdKGrGetCurrentResidentChannel_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS *pParams) { +static inline NV_STATUS subdeviceCtrlCmdKGrGetCurrentResidentChannel_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS *pParams) { return pSubdevice->__subdeviceCtrlCmdKGrGetCurrentResidentChannel__(pSubdevice, pParams); } @@ -2568,6 +2606,12 @@ static inline NV_STATUS subdeviceCtrlCmdGpuGetNvencSwSessionInfo_DISPATCH(struct return pSubdevice->__subdeviceCtrlCmdGpuGetNvencSwSessionInfo__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdGpuGetNvencSwSessionInfoV2_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdGpuGetNvencSwSessionInfoV2_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdGpuGetNvencSwSessionInfoV2__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdGpuGetNvfbcSwSessionStats_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS *params); static inline NV_STATUS subdeviceCtrlCmdGpuGetNvfbcSwSessionStats_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS *params) { @@ -2856,6 +2900,12 @@ static inline NV_STATUS subdeviceCtrlCmdGpuGetHwEngineId_DISPATCH(struct Subdevi return pSubdevice->__subdeviceCtrlCmdGpuGetHwEngineId__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdGpuGetVmmuSegmentSize_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdGpuGetVmmuSegmentSize_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdGpuGetVmmuSegmentSize__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdGpuGetMaxSupportedPageSize_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdGpuGetMaxSupportedPageSize_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS *pParams) { @@ -2916,6 +2966,18 @@ static inline NV_STATUS subdeviceCtrlCmdGetGpuFabricProbeInfo_DISPATCH(struct Su return pSubdevice->__subdeviceCtrlCmdGetGpuFabricProbeInfo__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdGpuGetResetStatus_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdGpuGetResetStatus_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdGpuGetResetStatus__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdGpuGetDrainAndResetStatus_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdGpuGetDrainAndResetStatus_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdGpuGetDrainAndResetStatus__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdEventSetTrigger_IMPL(struct Subdevice *pSubdevice); static inline NV_STATUS subdeviceCtrlCmdEventSetTrigger_DISPATCH(struct Subdevice *pSubdevice) { @@ -3396,6 +3458,42 @@ static inline NV_STATUS subdeviceCtrlCmdDisplayGetDisplayMask_DISPATCH(struct Su return pSubdevice->__subdeviceCtrlCmdDisplayGetDisplayMask__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdDisplayPinsetsToLockpins_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdDisplayPinsetsToLockpins_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdDisplayPinsetsToLockpins__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdDisplaySetSliLinkGpioSwControl_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdDisplaySetSliLinkGpioSwControl_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdDisplaySetSliLinkGpioSwControl__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalGpioProgramDirection_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalGpioProgramDirection_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalGpioProgramDirection__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalGpioProgramOutput_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalGpioProgramOutput_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalGpioProgramOutput__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalGpioReadInput_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalGpioReadInput_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalGpioReadInput__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalGpioActivateHwFunction_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalGpioActivateHwFunction_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalGpioActivateHwFunction__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdMsencGetCaps_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdMsencGetCaps_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS *pParams) { @@ -3498,6 +3596,12 @@ static inline NV_STATUS subdeviceCtrlCmdInternalBusRemoveC2cPeerMapping_DISPATCH return pSubdevice->__subdeviceCtrlCmdInternalBusRemoveC2cPeerMapping__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdInternalVmmuGetSpaForGpaEntries_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalVmmuGetSpaForGpaEntries_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalVmmuGetSpaForGpaEntries__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdGmmuGetStaticInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdGmmuGetStaticInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pParams) { @@ -3522,10 +3626,10 @@ static inline NV_STATUS subdeviceCtrlCmdInternalGmmuRegisterClientShadowFaultBuf return pSubdevice->__subdeviceCtrlCmdInternalGmmuRegisterClientShadowFaultBuffer__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer_IMPL(struct Subdevice *pSubdevice); +NV_STATUS subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS *pParams); -static inline NV_STATUS subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer_DISPATCH(struct Subdevice *pSubdevice) { - return pSubdevice->__subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer__(pSubdevice); +static inline NV_STATUS subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer__(pSubdevice, pParams); } NV_STATUS subdeviceCtrlCmdInternalGmmuCopyReservedSplitGVASpacePdesServer_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS *pCopyServerReservedPdesParams); @@ -3660,6 +3764,12 @@ static inline NV_STATUS subdeviceCtrlCmdBifSetPcieRo_DISPATCH(struct Subdevice * return pSubdevice->__subdeviceCtrlCmdBifSetPcieRo__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdBifDisableSystemMemoryAccess_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdBifDisableSystemMemoryAccess_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdBifDisableSystemMemoryAccess__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdHshubPeerConnConfig_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdHshubPeerConnConfig_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS *pParams) { @@ -3804,6 +3914,12 @@ static inline NV_STATUS subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit_DISPA return pSubdevice->__subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit__(pSubdevice); } +NV_STATUS subdeviceCtrlCmdInternalDetectHsVideoBridge_IMPL(struct Subdevice *pSubdevice); + +static inline NV_STATUS subdeviceCtrlCmdInternalDetectHsVideoBridge_DISPATCH(struct Subdevice *pSubdevice) { + return pSubdevice->__subdeviceCtrlCmdInternalDetectHsVideoBridge__(pSubdevice); +} + NV_STATUS subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS *pParams) { @@ -3898,16 +4014,16 @@ static inline NvBool subdeviceShareCallback_DISPATCH(struct Subdevice *pGpuResou return pGpuResource->__subdeviceShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS subdeviceMapTo_DISPATCH(struct Subdevice *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__subdeviceMapTo__(pResource, pParams); +static inline NV_STATUS subdeviceCheckMemInterUnmap_DISPATCH(struct Subdevice *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__subdeviceCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } static inline NV_STATUS subdeviceGetOrAllocNotifShare_DISPATCH(struct Subdevice *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return pNotifier->__subdeviceGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); } -static inline NV_STATUS subdeviceCheckMemInterUnmap_DISPATCH(struct Subdevice *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__subdeviceCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline NV_STATUS subdeviceMapTo_DISPATCH(struct Subdevice *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__subdeviceMapTo__(pResource, pParams); } static inline NV_STATUS subdeviceGetMapAddrSpace_DISPATCH(struct Subdevice *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -3970,6 +4086,10 @@ static inline NV_STATUS subdeviceUnregisterEvent_DISPATCH(struct Subdevice *pNot return pNotifier->__subdeviceUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS subdeviceControlSerialization_Prologue_DISPATCH(struct Subdevice *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__subdeviceControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool subdeviceCanCopy_DISPATCH(struct Subdevice *pResource) { return pResource->__subdeviceCanCopy__(pResource); } @@ -3978,6 +4098,10 @@ static inline NV_STATUS subdeviceIsDuplicate_DISPATCH(struct Subdevice *pResourc return pResource->__subdeviceIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void subdeviceControlSerialization_Epilogue_DISPATCH(struct Subdevice *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__subdeviceControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *subdeviceGetNotificationListPtr_DISPATCH(struct Subdevice *pNotifier) { return pNotifier->__subdeviceGetNotificationListPtr__(pNotifier); } diff --git a/src/nvidia/generated/g_sw_test_nvoc.c b/src/nvidia/generated/g_sw_test_nvoc.c index b49fe2604..5ca811151 100644 --- a/src/nvidia/generated/g_sw_test_nvoc.c +++ b/src/nvidia/generated/g_sw_test_nvoc.c @@ -120,7 +120,7 @@ const struct NVOC_CLASS_DEF __nvoc_class_def_SoftwareMethodTest = /*pExportInfo=*/ &__nvoc_export_info_SoftwareMethodTest }; -static NV_STATUS __nvoc_thunk_SoftwareMethodTest_chandesGetSwMethods(struct ChannelDescendant *pSwTest, METHOD **ppMethods, NvU32 *pNumMethods) { +static NV_STATUS __nvoc_thunk_SoftwareMethodTest_chandesGetSwMethods(struct ChannelDescendant *pSwTest, const METHOD **ppMethods, NvU32 *pNumMethods) { return swtestGetSwMethods((struct SoftwareMethodTest *)(((unsigned char *)pSwTest) - __nvoc_rtti_SoftwareMethodTest_ChannelDescendant.offset), ppMethods, pNumMethods); } @@ -212,6 +212,10 @@ static NV_STATUS __nvoc_thunk_Notifier_swtestUnregisterEvent(struct SoftwareMeth return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_SoftwareMethodTest_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_swtestControlSerialization_Prologue(struct SoftwareMethodTest *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SoftwareMethodTest_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_swtestCanCopy(struct SoftwareMethodTest *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SoftwareMethodTest_RsResource.offset)); } @@ -224,6 +228,10 @@ static NV_STATUS __nvoc_thunk_RsResource_swtestIsDuplicate(struct SoftwareMethod return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SoftwareMethodTest_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_swtestControlSerialization_Epilogue(struct SoftwareMethodTest *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SoftwareMethodTest_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_swtestGetNotificationListPtr(struct SoftwareMethodTest *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_SoftwareMethodTest_Notifier.offset)); } @@ -327,12 +335,16 @@ static void __nvoc_init_funcTable_SoftwareMethodTest_1(SoftwareMethodTest *pThis pThis->__swtestUnregisterEvent__ = &__nvoc_thunk_Notifier_swtestUnregisterEvent; + pThis->__swtestControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_swtestControlSerialization_Prologue; + pThis->__swtestCanCopy__ = &__nvoc_thunk_RsResource_swtestCanCopy; pThis->__swtestPreDestruct__ = &__nvoc_thunk_RsResource_swtestPreDestruct; pThis->__swtestIsDuplicate__ = &__nvoc_thunk_RsResource_swtestIsDuplicate; + pThis->__swtestControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_swtestControlSerialization_Epilogue; + pThis->__swtestGetNotificationListPtr__ = &__nvoc_thunk_Notifier_swtestGetNotificationListPtr; pThis->__swtestGetNotificationShare__ = &__nvoc_thunk_Notifier_swtestGetNotificationShare; @@ -367,13 +379,16 @@ NV_STATUS __nvoc_objCreate_SoftwareMethodTest(SoftwareMethodTest **ppThis, Dynam SoftwareMethodTest *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(SoftwareMethodTest)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(SoftwareMethodTest), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(SoftwareMethodTest)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_SoftwareMethodTest); + pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -393,11 +408,17 @@ NV_STATUS __nvoc_objCreate_SoftwareMethodTest(SoftwareMethodTest **ppThis, Dynam if (status != NV_OK) goto __nvoc_objCreate_SoftwareMethodTest_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_SoftwareMethodTest_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(SoftwareMethodTest)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_sw_test_nvoc.h b/src/nvidia/generated/g_sw_test_nvoc.h index b98b55845..82a71acb3 100644 --- a/src/nvidia/generated/g_sw_test_nvoc.h +++ b/src/nvidia/generated/g_sw_test_nvoc.h @@ -57,7 +57,7 @@ struct SoftwareMethodTest { struct Notifier *__nvoc_pbase_Notifier; struct ChannelDescendant *__nvoc_pbase_ChannelDescendant; struct SoftwareMethodTest *__nvoc_pbase_SoftwareMethodTest; - NV_STATUS (*__swtestGetSwMethods__)(struct SoftwareMethodTest *, METHOD **, NvU32 *); + NV_STATUS (*__swtestGetSwMethods__)(struct SoftwareMethodTest *, const METHOD **, NvU32 *); NV_STATUS (*__swtestCheckMemInterUnmap__)(struct SoftwareMethodTest *, NvBool); NvBool (*__swtestShareCallback__)(struct SoftwareMethodTest *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NvBool (*__swtestAccessCallback__)(struct SoftwareMethodTest *, struct RsClient *, void *, RsAccessRight); @@ -80,9 +80,11 @@ struct SoftwareMethodTest { NvBool (*__swtestIsSwMethodStalling__)(struct SoftwareMethodTest *, NvU32); NV_STATUS (*__swtestControlFilter__)(struct SoftwareMethodTest *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__swtestUnregisterEvent__)(struct SoftwareMethodTest *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__swtestControlSerialization_Prologue__)(struct SoftwareMethodTest *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__swtestCanCopy__)(struct SoftwareMethodTest *); void (*__swtestPreDestruct__)(struct SoftwareMethodTest *); NV_STATUS (*__swtestIsDuplicate__)(struct SoftwareMethodTest *, NvHandle, NvBool *); + void (*__swtestControlSerialization_Epilogue__)(struct SoftwareMethodTest *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__swtestGetNotificationListPtr__)(struct SoftwareMethodTest *); struct NotifShare *(*__swtestGetNotificationShare__)(struct SoftwareMethodTest *); NV_STATUS (*__swtestMap__)(struct SoftwareMethodTest *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -140,16 +142,18 @@ NV_STATUS __nvoc_objCreate_SoftwareMethodTest(SoftwareMethodTest**, Dynamic*, Nv #define swtestIsSwMethodStalling(pChannelDescendant, hHandle) swtestIsSwMethodStalling_DISPATCH(pChannelDescendant, hHandle) #define swtestControlFilter(pResource, pCallContext, pParams) swtestControlFilter_DISPATCH(pResource, pCallContext, pParams) #define swtestUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) swtestUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define swtestControlSerialization_Prologue(pResource, pCallContext, pParams) swtestControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define swtestCanCopy(pResource) swtestCanCopy_DISPATCH(pResource) #define swtestPreDestruct(pResource) swtestPreDestruct_DISPATCH(pResource) #define swtestIsDuplicate(pResource, hMemory, pDuplicate) swtestIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define swtestControlSerialization_Epilogue(pResource, pCallContext, pParams) swtestControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define swtestGetNotificationListPtr(pNotifier) swtestGetNotificationListPtr_DISPATCH(pNotifier) #define swtestGetNotificationShare(pNotifier) swtestGetNotificationShare_DISPATCH(pNotifier) #define swtestMap(pGpuResource, pCallContext, pParams, pCpuMapping) swtestMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define swtestGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) swtestGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) -NV_STATUS swtestGetSwMethods_IMPL(struct SoftwareMethodTest *pSwTest, METHOD **ppMethods, NvU32 *pNumMethods); +NV_STATUS swtestGetSwMethods_IMPL(struct SoftwareMethodTest *pSwTest, const METHOD **ppMethods, NvU32 *pNumMethods); -static inline NV_STATUS swtestGetSwMethods_DISPATCH(struct SoftwareMethodTest *pSwTest, METHOD **ppMethods, NvU32 *pNumMethods) { +static inline NV_STATUS swtestGetSwMethods_DISPATCH(struct SoftwareMethodTest *pSwTest, const METHOD **ppMethods, NvU32 *pNumMethods) { return pSwTest->__swtestGetSwMethods__(pSwTest, ppMethods, pNumMethods); } @@ -241,6 +245,10 @@ static inline NV_STATUS swtestUnregisterEvent_DISPATCH(struct SoftwareMethodTest return pNotifier->__swtestUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS swtestControlSerialization_Prologue_DISPATCH(struct SoftwareMethodTest *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__swtestControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool swtestCanCopy_DISPATCH(struct SoftwareMethodTest *pResource) { return pResource->__swtestCanCopy__(pResource); } @@ -253,6 +261,10 @@ static inline NV_STATUS swtestIsDuplicate_DISPATCH(struct SoftwareMethodTest *pR return pResource->__swtestIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void swtestControlSerialization_Epilogue_DISPATCH(struct SoftwareMethodTest *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__swtestControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *swtestGetNotificationListPtr_DISPATCH(struct SoftwareMethodTest *pNotifier) { return pNotifier->__swtestGetNotificationListPtr__(pNotifier); } diff --git a/src/nvidia/generated/g_swintr_nvoc.c b/src/nvidia/generated/g_swintr_nvoc.c index 7fdc26490..611bc93c3 100644 --- a/src/nvidia/generated/g_swintr_nvoc.c +++ b/src/nvidia/generated/g_swintr_nvoc.c @@ -75,7 +75,7 @@ const struct NVOC_CLASS_DEF __nvoc_class_def_SwIntr = /*pExportInfo=*/ &__nvoc_export_info_SwIntr }; -static void __nvoc_thunk_SwIntr_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pSwIntr, IntrServiceRecord pRecords[163]) { +static void __nvoc_thunk_SwIntr_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pSwIntr, IntrServiceRecord pRecords[166]) { swintrRegisterIntrService(pGpu, (struct SwIntr *)(((unsigned char *)pSwIntr) - __nvoc_rtti_SwIntr_IntrService.offset), pRecords); } @@ -83,10 +83,6 @@ static NvU32 __nvoc_thunk_SwIntr_intrservServiceInterrupt(OBJGPU *pGpu, struct I return swintrServiceInterrupt(pGpu, (struct SwIntr *)(((unsigned char *)pSwIntr) - __nvoc_rtti_SwIntr_IntrService.offset), pParams); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrReconcileTunableState(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrStateLoad(POBJGPU pGpu, struct SwIntr *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), arg0); } @@ -135,18 +131,6 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrStatePreInitUnlocked(POBJGPU pGp return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrGetTunableState(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrCompareTunableState(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_swintrFreeTunableState(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_IntrService_swintrClearInterrupt(OBJGPU *pGpu, struct SwIntr *pIntrService, IntrServiceClearInterruptArguments *pParams) { return intrservClearInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_SwIntr_IntrService.offset), pParams); } @@ -155,14 +139,6 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrStatePostLoad(POBJGPU pGpu, stru return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrAllocTunableState(POBJGPU pGpu, struct SwIntr *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrSetTunableState(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrConstructEngine(POBJGPU pGpu, struct SwIntr *pEngstate, ENGDESCRIPTOR arg0) { return engstateConstructEngine(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), arg0); } @@ -219,8 +195,6 @@ static void __nvoc_init_funcTable_SwIntr_1(SwIntr *pThis) { pThis->__nvoc_base_IntrService.__intrservServiceInterrupt__ = &__nvoc_thunk_SwIntr_intrservServiceInterrupt; - pThis->__swintrReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_swintrReconcileTunableState; - pThis->__swintrStateLoad__ = &__nvoc_thunk_OBJENGSTATE_swintrStateLoad; pThis->__swintrStateUnload__ = &__nvoc_thunk_OBJENGSTATE_swintrStateUnload; @@ -245,20 +219,10 @@ static void __nvoc_init_funcTable_SwIntr_1(SwIntr *pThis) { pThis->__swintrStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_swintrStatePreInitUnlocked; - pThis->__swintrGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_swintrGetTunableState; - - pThis->__swintrCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_swintrCompareTunableState; - - pThis->__swintrFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_swintrFreeTunableState; - pThis->__swintrClearInterrupt__ = &__nvoc_thunk_IntrService_swintrClearInterrupt; pThis->__swintrStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_swintrStatePostLoad; - pThis->__swintrAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_swintrAllocTunableState; - - pThis->__swintrSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_swintrSetTunableState; - pThis->__swintrConstructEngine__ = &__nvoc_thunk_OBJENGSTATE_swintrConstructEngine; pThis->__swintrIsPresent__ = &__nvoc_thunk_OBJENGSTATE_swintrIsPresent; @@ -285,13 +249,16 @@ NV_STATUS __nvoc_objCreate_SwIntr(SwIntr **ppThis, Dynamic *pParent, NvU32 creat Object *pParentObj; SwIntr *pThis; - pThis = portMemAllocNonPaged(sizeof(SwIntr)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(SwIntr), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(SwIntr)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_SwIntr); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -307,11 +274,17 @@ NV_STATUS __nvoc_objCreate_SwIntr(SwIntr **ppThis, Dynamic *pParent, NvU32 creat if (status != NV_OK) goto __nvoc_objCreate_SwIntr_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_SwIntr_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(SwIntr)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_swintr_nvoc.h b/src/nvidia/generated/g_swintr_nvoc.h index 4380dce53..421e15f38 100644 --- a/src/nvidia/generated/g_swintr_nvoc.h +++ b/src/nvidia/generated/g_swintr_nvoc.h @@ -59,7 +59,6 @@ struct SwIntr { struct SwIntr *__nvoc_pbase_SwIntr; void (*__swintrRegisterIntrService__)(OBJGPU *, struct SwIntr *, IntrServiceRecord *); NvU32 (*__swintrServiceInterrupt__)(OBJGPU *, struct SwIntr *, IntrServiceServiceInterruptArguments *); - NV_STATUS (*__swintrReconcileTunableState__)(POBJGPU, struct SwIntr *, void *); NV_STATUS (*__swintrStateLoad__)(POBJGPU, struct SwIntr *, NvU32); NV_STATUS (*__swintrStateUnload__)(POBJGPU, struct SwIntr *, NvU32); NV_STATUS (*__swintrServiceNotificationInterrupt__)(OBJGPU *, struct SwIntr *, IntrServiceServiceNotificationInterruptArguments *); @@ -72,13 +71,8 @@ struct SwIntr { void (*__swintrInitMissing__)(POBJGPU, struct SwIntr *); NV_STATUS (*__swintrStatePreInitLocked__)(POBJGPU, struct SwIntr *); NV_STATUS (*__swintrStatePreInitUnlocked__)(POBJGPU, struct SwIntr *); - NV_STATUS (*__swintrGetTunableState__)(POBJGPU, struct SwIntr *, void *); - NV_STATUS (*__swintrCompareTunableState__)(POBJGPU, struct SwIntr *, void *, void *); - void (*__swintrFreeTunableState__)(POBJGPU, struct SwIntr *, void *); NvBool (*__swintrClearInterrupt__)(OBJGPU *, struct SwIntr *, IntrServiceClearInterruptArguments *); NV_STATUS (*__swintrStatePostLoad__)(POBJGPU, struct SwIntr *, NvU32); - NV_STATUS (*__swintrAllocTunableState__)(POBJGPU, struct SwIntr *, void **); - NV_STATUS (*__swintrSetTunableState__)(POBJGPU, struct SwIntr *, void *); NV_STATUS (*__swintrConstructEngine__)(POBJGPU, struct SwIntr *, ENGDESCRIPTOR); NvBool (*__swintrIsPresent__)(POBJGPU, struct SwIntr *); }; @@ -115,7 +109,6 @@ NV_STATUS __nvoc_objCreate_SwIntr(SwIntr**, Dynamic*, NvU32); #define swintrRegisterIntrService(pGpu, pSwIntr, pRecords) swintrRegisterIntrService_DISPATCH(pGpu, pSwIntr, pRecords) #define swintrServiceInterrupt(pGpu, pSwIntr, pParams) swintrServiceInterrupt_DISPATCH(pGpu, pSwIntr, pParams) -#define swintrReconcileTunableState(pGpu, pEngstate, pTunableState) swintrReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define swintrStateLoad(pGpu, pEngstate, arg0) swintrStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define swintrStateUnload(pGpu, pEngstate, arg0) swintrStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define swintrServiceNotificationInterrupt(pGpu, pIntrService, pParams) swintrServiceNotificationInterrupt_DISPATCH(pGpu, pIntrService, pParams) @@ -128,18 +121,13 @@ NV_STATUS __nvoc_objCreate_SwIntr(SwIntr**, Dynamic*, NvU32); #define swintrInitMissing(pGpu, pEngstate) swintrInitMissing_DISPATCH(pGpu, pEngstate) #define swintrStatePreInitLocked(pGpu, pEngstate) swintrStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define swintrStatePreInitUnlocked(pGpu, pEngstate) swintrStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define swintrGetTunableState(pGpu, pEngstate, pTunableState) swintrGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define swintrCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) swintrCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define swintrFreeTunableState(pGpu, pEngstate, pTunableState) swintrFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define swintrClearInterrupt(pGpu, pIntrService, pParams) swintrClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define swintrStatePostLoad(pGpu, pEngstate, arg0) swintrStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define swintrAllocTunableState(pGpu, pEngstate, ppTunableState) swintrAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define swintrSetTunableState(pGpu, pEngstate, pTunableState) swintrSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define swintrConstructEngine(pGpu, pEngstate, arg0) swintrConstructEngine_DISPATCH(pGpu, pEngstate, arg0) #define swintrIsPresent(pGpu, pEngstate) swintrIsPresent_DISPATCH(pGpu, pEngstate) -void swintrRegisterIntrService_IMPL(OBJGPU *pGpu, struct SwIntr *pSwIntr, IntrServiceRecord pRecords[163]); +void swintrRegisterIntrService_IMPL(OBJGPU *pGpu, struct SwIntr *pSwIntr, IntrServiceRecord pRecords[166]); -static inline void swintrRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct SwIntr *pSwIntr, IntrServiceRecord pRecords[163]) { +static inline void swintrRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct SwIntr *pSwIntr, IntrServiceRecord pRecords[166]) { pSwIntr->__swintrRegisterIntrService__(pGpu, pSwIntr, pRecords); } @@ -149,10 +137,6 @@ static inline NvU32 swintrServiceInterrupt_DISPATCH(OBJGPU *pGpu, struct SwIntr return pSwIntr->__swintrServiceInterrupt__(pGpu, pSwIntr, pParams); } -static inline NV_STATUS swintrReconcileTunableState_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunableState) { - return pEngstate->__swintrReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS swintrStateLoad_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate, NvU32 arg0) { return pEngstate->__swintrStateLoad__(pGpu, pEngstate, arg0); } @@ -201,18 +185,6 @@ static inline NV_STATUS swintrStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct return pEngstate->__swintrStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS swintrGetTunableState_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunableState) { - return pEngstate->__swintrGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS swintrCompareTunableState_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__swintrCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void swintrFreeTunableState_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunableState) { - pEngstate->__swintrFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool swintrClearInterrupt_DISPATCH(OBJGPU *pGpu, struct SwIntr *pIntrService, IntrServiceClearInterruptArguments *pParams) { return pIntrService->__swintrClearInterrupt__(pGpu, pIntrService, pParams); } @@ -221,14 +193,6 @@ static inline NV_STATUS swintrStatePostLoad_DISPATCH(POBJGPU pGpu, struct SwIntr return pEngstate->__swintrStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS swintrAllocTunableState_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate, void **ppTunableState) { - return pEngstate->__swintrAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS swintrSetTunableState_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunableState) { - return pEngstate->__swintrSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS swintrConstructEngine_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate, ENGDESCRIPTOR arg0) { return pEngstate->__swintrConstructEngine__(pGpu, pEngstate, arg0); } diff --git a/src/nvidia/generated/g_syncgpuboost_nvoc.c b/src/nvidia/generated/g_syncgpuboost_nvoc.c index d26a2f24f..c66b76f8b 100644 --- a/src/nvidia/generated/g_syncgpuboost_nvoc.c +++ b/src/nvidia/generated/g_syncgpuboost_nvoc.c @@ -116,8 +116,12 @@ static void __nvoc_thunk_RsResource_syncgpuboostAddAdditionalDependants(struct R resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_syncgpuboostUnmap(struct SyncGpuBoost *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RsResource.offset), pCallContext, pCpuMapping); +static NV_STATUS __nvoc_thunk_RsResource_syncgpuboostUnmapFrom(struct SyncGpuBoost *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_syncgpuboostControlSerialization_Prologue(struct SyncGpuBoost *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_RmResource_syncgpuboostControl_Prologue(struct SyncGpuBoost *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -128,22 +132,26 @@ static NvBool __nvoc_thunk_RsResource_syncgpuboostCanCopy(struct SyncGpuBoost *p return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_syncgpuboostMapTo(struct SyncGpuBoost *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_syncgpuboostUnmap(struct SyncGpuBoost *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RsResource.offset), pCallContext, pCpuMapping); } static void __nvoc_thunk_RsResource_syncgpuboostPreDestruct(struct SyncGpuBoost *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_syncgpuboostUnmapFrom(struct SyncGpuBoost *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_syncgpuboostMapTo(struct SyncGpuBoost *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_RsResource_syncgpuboostIsDuplicate(struct SyncGpuBoost *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_syncgpuboostControlSerialization_Epilogue(struct SyncGpuBoost *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RmResource.offset), pCallContext, pParams); +} + static void __nvoc_thunk_RmResource_syncgpuboostControl_Epilogue(struct SyncGpuBoost *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RmResource.offset), pCallContext, pParams); } @@ -215,20 +223,24 @@ static void __nvoc_init_funcTable_SyncGpuBoost_1(SyncGpuBoost *pThis) { pThis->__syncgpuboostAddAdditionalDependants__ = &__nvoc_thunk_RsResource_syncgpuboostAddAdditionalDependants; - pThis->__syncgpuboostUnmap__ = &__nvoc_thunk_RsResource_syncgpuboostUnmap; + pThis->__syncgpuboostUnmapFrom__ = &__nvoc_thunk_RsResource_syncgpuboostUnmapFrom; + + pThis->__syncgpuboostControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_syncgpuboostControlSerialization_Prologue; pThis->__syncgpuboostControl_Prologue__ = &__nvoc_thunk_RmResource_syncgpuboostControl_Prologue; pThis->__syncgpuboostCanCopy__ = &__nvoc_thunk_RsResource_syncgpuboostCanCopy; - pThis->__syncgpuboostMapTo__ = &__nvoc_thunk_RsResource_syncgpuboostMapTo; + pThis->__syncgpuboostUnmap__ = &__nvoc_thunk_RsResource_syncgpuboostUnmap; pThis->__syncgpuboostPreDestruct__ = &__nvoc_thunk_RsResource_syncgpuboostPreDestruct; - pThis->__syncgpuboostUnmapFrom__ = &__nvoc_thunk_RsResource_syncgpuboostUnmapFrom; + pThis->__syncgpuboostMapTo__ = &__nvoc_thunk_RsResource_syncgpuboostMapTo; pThis->__syncgpuboostIsDuplicate__ = &__nvoc_thunk_RsResource_syncgpuboostIsDuplicate; + pThis->__syncgpuboostControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_syncgpuboostControlSerialization_Epilogue; + pThis->__syncgpuboostControl_Epilogue__ = &__nvoc_thunk_RmResource_syncgpuboostControl_Epilogue; pThis->__syncgpuboostControlLookup__ = &__nvoc_thunk_RsResource_syncgpuboostControlLookup; @@ -258,13 +270,16 @@ NV_STATUS __nvoc_objCreate_SyncGpuBoost(SyncGpuBoost **ppThis, Dynamic *pParent, Object *pParentObj; SyncGpuBoost *pThis; - pThis = portMemAllocNonPaged(sizeof(SyncGpuBoost)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(SyncGpuBoost), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(SyncGpuBoost)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_SyncGpuBoost); + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -280,11 +295,17 @@ NV_STATUS __nvoc_objCreate_SyncGpuBoost(SyncGpuBoost **ppThis, Dynamic *pParent, if (status != NV_OK) goto __nvoc_objCreate_SyncGpuBoost_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_SyncGpuBoost_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(SyncGpuBoost)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_syncgpuboost_nvoc.h b/src/nvidia/generated/g_syncgpuboost_nvoc.h index 69e6cfe31..ec656370e 100644 --- a/src/nvidia/generated/g_syncgpuboost_nvoc.h +++ b/src/nvidia/generated/g_syncgpuboost_nvoc.h @@ -60,13 +60,15 @@ struct SyncGpuBoost { NvU32 (*__syncgpuboostGetRefCount__)(struct SyncGpuBoost *); NV_STATUS (*__syncgpuboostControlFilter__)(struct SyncGpuBoost *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__syncgpuboostAddAdditionalDependants__)(struct RsClient *, struct SyncGpuBoost *, RsResourceRef *); - NV_STATUS (*__syncgpuboostUnmap__)(struct SyncGpuBoost *, struct CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__syncgpuboostUnmapFrom__)(struct SyncGpuBoost *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__syncgpuboostControlSerialization_Prologue__)(struct SyncGpuBoost *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__syncgpuboostControl_Prologue__)(struct SyncGpuBoost *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__syncgpuboostCanCopy__)(struct SyncGpuBoost *); - NV_STATUS (*__syncgpuboostMapTo__)(struct SyncGpuBoost *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__syncgpuboostUnmap__)(struct SyncGpuBoost *, struct CALL_CONTEXT *, RsCpuMapping *); void (*__syncgpuboostPreDestruct__)(struct SyncGpuBoost *); - NV_STATUS (*__syncgpuboostUnmapFrom__)(struct SyncGpuBoost *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__syncgpuboostMapTo__)(struct SyncGpuBoost *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__syncgpuboostIsDuplicate__)(struct SyncGpuBoost *, NvHandle, NvBool *); + void (*__syncgpuboostControlSerialization_Epilogue__)(struct SyncGpuBoost *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__syncgpuboostControl_Epilogue__)(struct SyncGpuBoost *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__syncgpuboostControlLookup__)(struct SyncGpuBoost *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__syncgpuboostMap__)(struct SyncGpuBoost *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -110,13 +112,15 @@ NV_STATUS __nvoc_objCreate_SyncGpuBoost(SyncGpuBoost**, Dynamic*, NvU32, struct #define syncgpuboostGetRefCount(pResource) syncgpuboostGetRefCount_DISPATCH(pResource) #define syncgpuboostControlFilter(pResource, pCallContext, pParams) syncgpuboostControlFilter_DISPATCH(pResource, pCallContext, pParams) #define syncgpuboostAddAdditionalDependants(pClient, pResource, pReference) syncgpuboostAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define syncgpuboostUnmap(pResource, pCallContext, pCpuMapping) syncgpuboostUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define syncgpuboostUnmapFrom(pResource, pParams) syncgpuboostUnmapFrom_DISPATCH(pResource, pParams) +#define syncgpuboostControlSerialization_Prologue(pResource, pCallContext, pParams) syncgpuboostControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define syncgpuboostControl_Prologue(pResource, pCallContext, pParams) syncgpuboostControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define syncgpuboostCanCopy(pResource) syncgpuboostCanCopy_DISPATCH(pResource) -#define syncgpuboostMapTo(pResource, pParams) syncgpuboostMapTo_DISPATCH(pResource, pParams) +#define syncgpuboostUnmap(pResource, pCallContext, pCpuMapping) syncgpuboostUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define syncgpuboostPreDestruct(pResource) syncgpuboostPreDestruct_DISPATCH(pResource) -#define syncgpuboostUnmapFrom(pResource, pParams) syncgpuboostUnmapFrom_DISPATCH(pResource, pParams) +#define syncgpuboostMapTo(pResource, pParams) syncgpuboostMapTo_DISPATCH(pResource, pParams) #define syncgpuboostIsDuplicate(pResource, hMemory, pDuplicate) syncgpuboostIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define syncgpuboostControlSerialization_Epilogue(pResource, pCallContext, pParams) syncgpuboostControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define syncgpuboostControl_Epilogue(pResource, pCallContext, pParams) syncgpuboostControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define syncgpuboostControlLookup(pResource, pParams, ppEntry) syncgpuboostControlLookup_DISPATCH(pResource, pParams, ppEntry) #define syncgpuboostMap(pResource, pCallContext, pParams, pCpuMapping) syncgpuboostMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -153,8 +157,12 @@ static inline void syncgpuboostAddAdditionalDependants_DISPATCH(struct RsClient pResource->__syncgpuboostAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS syncgpuboostUnmap_DISPATCH(struct SyncGpuBoost *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pResource->__syncgpuboostUnmap__(pResource, pCallContext, pCpuMapping); +static inline NV_STATUS syncgpuboostUnmapFrom_DISPATCH(struct SyncGpuBoost *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__syncgpuboostUnmapFrom__(pResource, pParams); +} + +static inline NV_STATUS syncgpuboostControlSerialization_Prologue_DISPATCH(struct SyncGpuBoost *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__syncgpuboostControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS syncgpuboostControl_Prologue_DISPATCH(struct SyncGpuBoost *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -165,22 +173,26 @@ static inline NvBool syncgpuboostCanCopy_DISPATCH(struct SyncGpuBoost *pResource return pResource->__syncgpuboostCanCopy__(pResource); } -static inline NV_STATUS syncgpuboostMapTo_DISPATCH(struct SyncGpuBoost *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__syncgpuboostMapTo__(pResource, pParams); +static inline NV_STATUS syncgpuboostUnmap_DISPATCH(struct SyncGpuBoost *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__syncgpuboostUnmap__(pResource, pCallContext, pCpuMapping); } static inline void syncgpuboostPreDestruct_DISPATCH(struct SyncGpuBoost *pResource) { pResource->__syncgpuboostPreDestruct__(pResource); } -static inline NV_STATUS syncgpuboostUnmapFrom_DISPATCH(struct SyncGpuBoost *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__syncgpuboostUnmapFrom__(pResource, pParams); +static inline NV_STATUS syncgpuboostMapTo_DISPATCH(struct SyncGpuBoost *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__syncgpuboostMapTo__(pResource, pParams); } static inline NV_STATUS syncgpuboostIsDuplicate_DISPATCH(struct SyncGpuBoost *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__syncgpuboostIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void syncgpuboostControlSerialization_Epilogue_DISPATCH(struct SyncGpuBoost *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__syncgpuboostControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline void syncgpuboostControl_Epilogue_DISPATCH(struct SyncGpuBoost *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__syncgpuboostControl_Epilogue__(pResource, pCallContext, pParams); } diff --git a/src/nvidia/generated/g_system_mem_nvoc.c b/src/nvidia/generated/g_system_mem_nvoc.c index 1d30bc59d..bc1945186 100644 --- a/src/nvidia/generated/g_system_mem_nvoc.c +++ b/src/nvidia/generated/g_system_mem_nvoc.c @@ -106,6 +106,46 @@ static NV_STATUS __nvoc_thunk_Memory_sysmemCheckMemInterUnmap(struct SystemMemor return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), bSubdeviceHandleProvided); } +static NvBool __nvoc_thunk_RmResource_sysmemShareCallback(struct SystemMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RsResource_sysmemMapTo(struct SystemMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_sysmemGetMapAddrSpace(struct SystemMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_sysmemGetRefCount(struct SystemMemory *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_sysmemAddAdditionalDependants(struct RsClient *pClient, struct SystemMemory *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_sysmemControl_Prologue(struct SystemMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_Memory_sysmemIsGpuMapAllowed(struct SystemMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), pGpu); +} + +static NV_STATUS __nvoc_thunk_RsResource_sysmemUnmapFrom(struct SystemMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_sysmemControl_Epilogue(struct SystemMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_sysmemControlLookup(struct SystemMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RsResource.offset), pParams, ppEntry); +} + static NV_STATUS __nvoc_thunk_Memory_sysmemControl(struct SystemMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), pCallContext, pParams); } @@ -122,42 +162,18 @@ static NV_STATUS __nvoc_thunk_Memory_sysmemGetMemoryMappingDescriptor(struct Sys return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_Memory_sysmemGetMapAddrSpace(struct SystemMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvBool __nvoc_thunk_RmResource_sysmemShareCallback(struct SystemMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); -} - static NV_STATUS __nvoc_thunk_RsResource_sysmemControlFilter(struct SystemMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_sysmemAddAdditionalDependants(struct RsClient *pClient, struct SystemMemory *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_sysmemGetRefCount(struct SystemMemory *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RsResource_sysmemMapTo(struct SystemMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_sysmemControlSerialization_Prologue(struct SystemMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_StandardMemory_sysmemCanCopy(struct SystemMemory *pStandardMemory) { return stdmemCanCopy((struct StandardMemory *)(((unsigned char *)pStandardMemory) + __nvoc_rtti_SystemMemory_StandardMemory.offset)); } -static NvBool __nvoc_thunk_Memory_sysmemIsGpuMapAllowed(struct SystemMemory *pMemory, struct OBJGPU *pGpu) { - return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), pGpu); -} - -static NV_STATUS __nvoc_thunk_RmResource_sysmemControl_Prologue(struct SystemMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RmResource.offset), pCallContext, pParams); -} - static NV_STATUS __nvoc_thunk_Memory_sysmemIsReady(struct SystemMemory *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), bCopyConstructorContext); } @@ -174,16 +190,8 @@ static NV_STATUS __nvoc_thunk_Memory_sysmemIsDuplicate(struct SystemMemory *pMem return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), hMemory, pDuplicate); } -static NV_STATUS __nvoc_thunk_RsResource_sysmemUnmapFrom(struct SystemMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RmResource_sysmemControl_Epilogue(struct SystemMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_sysmemControlLookup(struct SystemMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_sysmemControlSerialization_Epilogue(struct SystemMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_sysmemMap(struct SystemMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -281,6 +289,26 @@ static void __nvoc_init_funcTable_SystemMemory_1(SystemMemory *pThis) { pThis->__sysmemCheckMemInterUnmap__ = &__nvoc_thunk_Memory_sysmemCheckMemInterUnmap; + pThis->__sysmemShareCallback__ = &__nvoc_thunk_RmResource_sysmemShareCallback; + + pThis->__sysmemMapTo__ = &__nvoc_thunk_RsResource_sysmemMapTo; + + pThis->__sysmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_sysmemGetMapAddrSpace; + + pThis->__sysmemGetRefCount__ = &__nvoc_thunk_RsResource_sysmemGetRefCount; + + pThis->__sysmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_sysmemAddAdditionalDependants; + + pThis->__sysmemControl_Prologue__ = &__nvoc_thunk_RmResource_sysmemControl_Prologue; + + pThis->__sysmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_sysmemIsGpuMapAllowed; + + pThis->__sysmemUnmapFrom__ = &__nvoc_thunk_RsResource_sysmemUnmapFrom; + + pThis->__sysmemControl_Epilogue__ = &__nvoc_thunk_RmResource_sysmemControl_Epilogue; + + pThis->__sysmemControlLookup__ = &__nvoc_thunk_RsResource_sysmemControlLookup; + pThis->__sysmemControl__ = &__nvoc_thunk_Memory_sysmemControl; pThis->__sysmemUnmap__ = &__nvoc_thunk_Memory_sysmemUnmap; @@ -289,24 +317,12 @@ static void __nvoc_init_funcTable_SystemMemory_1(SystemMemory *pThis) { pThis->__sysmemGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_sysmemGetMemoryMappingDescriptor; - pThis->__sysmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_sysmemGetMapAddrSpace; - - pThis->__sysmemShareCallback__ = &__nvoc_thunk_RmResource_sysmemShareCallback; - pThis->__sysmemControlFilter__ = &__nvoc_thunk_RsResource_sysmemControlFilter; - pThis->__sysmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_sysmemAddAdditionalDependants; - - pThis->__sysmemGetRefCount__ = &__nvoc_thunk_RsResource_sysmemGetRefCount; - - pThis->__sysmemMapTo__ = &__nvoc_thunk_RsResource_sysmemMapTo; + pThis->__sysmemControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_sysmemControlSerialization_Prologue; pThis->__sysmemCanCopy__ = &__nvoc_thunk_StandardMemory_sysmemCanCopy; - pThis->__sysmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_sysmemIsGpuMapAllowed; - - pThis->__sysmemControl_Prologue__ = &__nvoc_thunk_RmResource_sysmemControl_Prologue; - pThis->__sysmemIsReady__ = &__nvoc_thunk_Memory_sysmemIsReady; pThis->__sysmemCheckCopyPermissions__ = &__nvoc_thunk_Memory_sysmemCheckCopyPermissions; @@ -315,11 +331,7 @@ static void __nvoc_init_funcTable_SystemMemory_1(SystemMemory *pThis) { pThis->__sysmemIsDuplicate__ = &__nvoc_thunk_Memory_sysmemIsDuplicate; - pThis->__sysmemUnmapFrom__ = &__nvoc_thunk_RsResource_sysmemUnmapFrom; - - pThis->__sysmemControl_Epilogue__ = &__nvoc_thunk_RmResource_sysmemControl_Epilogue; - - pThis->__sysmemControlLookup__ = &__nvoc_thunk_RsResource_sysmemControlLookup; + pThis->__sysmemControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_sysmemControlSerialization_Epilogue; pThis->__sysmemMap__ = &__nvoc_thunk_Memory_sysmemMap; @@ -348,13 +360,16 @@ NV_STATUS __nvoc_objCreate_SystemMemory(SystemMemory **ppThis, Dynamic *pParent, Object *pParentObj; SystemMemory *pThis; - pThis = portMemAllocNonPaged(sizeof(SystemMemory)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(SystemMemory), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(SystemMemory)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_SystemMemory); + pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -370,11 +385,17 @@ NV_STATUS __nvoc_objCreate_SystemMemory(SystemMemory **ppThis, Dynamic *pParent, if (status != NV_OK) goto __nvoc_objCreate_SystemMemory_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_SystemMemory_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(SystemMemory)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_system_mem_nvoc.h b/src/nvidia/generated/g_system_mem_nvoc.h index 1379cb0b9..f8b90e445 100644 --- a/src/nvidia/generated/g_system_mem_nvoc.h +++ b/src/nvidia/generated/g_system_mem_nvoc.h @@ -55,26 +55,28 @@ struct SystemMemory { NV_STATUS (*__sysmemCtrlCmdGetSurfaceNumPhysPages__)(struct SystemMemory *, NV003E_CTRL_GET_SURFACE_NUM_PHYS_PAGES_PARAMS *); NV_STATUS (*__sysmemCtrlCmdGetSurfacePhysPages__)(struct SystemMemory *, NV003E_CTRL_GET_SURFACE_PHYS_PAGES_PARAMS *); NV_STATUS (*__sysmemCheckMemInterUnmap__)(struct SystemMemory *, NvBool); + NvBool (*__sysmemShareCallback__)(struct SystemMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__sysmemMapTo__)(struct SystemMemory *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__sysmemGetMapAddrSpace__)(struct SystemMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__sysmemGetRefCount__)(struct SystemMemory *); + void (*__sysmemAddAdditionalDependants__)(struct RsClient *, struct SystemMemory *, RsResourceRef *); + NV_STATUS (*__sysmemControl_Prologue__)(struct SystemMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__sysmemIsGpuMapAllowed__)(struct SystemMemory *, struct OBJGPU *); + NV_STATUS (*__sysmemUnmapFrom__)(struct SystemMemory *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__sysmemControl_Epilogue__)(struct SystemMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__sysmemControlLookup__)(struct SystemMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__sysmemControl__)(struct SystemMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__sysmemUnmap__)(struct SystemMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__sysmemGetMemInterMapParams__)(struct SystemMemory *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__sysmemGetMemoryMappingDescriptor__)(struct SystemMemory *, MEMORY_DESCRIPTOR **); - NV_STATUS (*__sysmemGetMapAddrSpace__)(struct SystemMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvBool (*__sysmemShareCallback__)(struct SystemMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__sysmemControlFilter__)(struct SystemMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__sysmemAddAdditionalDependants__)(struct RsClient *, struct SystemMemory *, RsResourceRef *); - NvU32 (*__sysmemGetRefCount__)(struct SystemMemory *); - NV_STATUS (*__sysmemMapTo__)(struct SystemMemory *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__sysmemControlSerialization_Prologue__)(struct SystemMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__sysmemCanCopy__)(struct SystemMemory *); - NvBool (*__sysmemIsGpuMapAllowed__)(struct SystemMemory *, struct OBJGPU *); - NV_STATUS (*__sysmemControl_Prologue__)(struct SystemMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__sysmemIsReady__)(struct SystemMemory *, NvBool); NV_STATUS (*__sysmemCheckCopyPermissions__)(struct SystemMemory *, struct OBJGPU *, NvHandle); void (*__sysmemPreDestruct__)(struct SystemMemory *); NV_STATUS (*__sysmemIsDuplicate__)(struct SystemMemory *, NvHandle, NvBool *); - NV_STATUS (*__sysmemUnmapFrom__)(struct SystemMemory *, RS_RES_UNMAP_FROM_PARAMS *); - void (*__sysmemControl_Epilogue__)(struct SystemMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__sysmemControlLookup__)(struct SystemMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__sysmemControlSerialization_Epilogue__)(struct SystemMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__sysmemMap__)(struct SystemMemory *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__sysmemAccessCallback__)(struct SystemMemory *, struct RsClient *, void *, RsAccessRight); }; @@ -110,26 +112,28 @@ NV_STATUS __nvoc_objCreate_SystemMemory(SystemMemory**, Dynamic*, NvU32, CALL_CO #define sysmemCtrlCmdGetSurfaceNumPhysPages(pStandardMemory, pParams) sysmemCtrlCmdGetSurfaceNumPhysPages_DISPATCH(pStandardMemory, pParams) #define sysmemCtrlCmdGetSurfacePhysPages(pStandardMemory, pParams) sysmemCtrlCmdGetSurfacePhysPages_DISPATCH(pStandardMemory, pParams) #define sysmemCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) sysmemCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define sysmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) sysmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define sysmemMapTo(pResource, pParams) sysmemMapTo_DISPATCH(pResource, pParams) +#define sysmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) sysmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define sysmemGetRefCount(pResource) sysmemGetRefCount_DISPATCH(pResource) +#define sysmemAddAdditionalDependants(pClient, pResource, pReference) sysmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define sysmemControl_Prologue(pResource, pCallContext, pParams) sysmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define sysmemIsGpuMapAllowed(pMemory, pGpu) sysmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define sysmemUnmapFrom(pResource, pParams) sysmemUnmapFrom_DISPATCH(pResource, pParams) +#define sysmemControl_Epilogue(pResource, pCallContext, pParams) sysmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define sysmemControlLookup(pResource, pParams, ppEntry) sysmemControlLookup_DISPATCH(pResource, pParams, ppEntry) #define sysmemControl(pMemory, pCallContext, pParams) sysmemControl_DISPATCH(pMemory, pCallContext, pParams) #define sysmemUnmap(pMemory, pCallContext, pCpuMapping) sysmemUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define sysmemGetMemInterMapParams(pMemory, pParams) sysmemGetMemInterMapParams_DISPATCH(pMemory, pParams) #define sysmemGetMemoryMappingDescriptor(pMemory, ppMemDesc) sysmemGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define sysmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) sysmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) -#define sysmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) sysmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define sysmemControlFilter(pResource, pCallContext, pParams) sysmemControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define sysmemAddAdditionalDependants(pClient, pResource, pReference) sysmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define sysmemGetRefCount(pResource) sysmemGetRefCount_DISPATCH(pResource) -#define sysmemMapTo(pResource, pParams) sysmemMapTo_DISPATCH(pResource, pParams) +#define sysmemControlSerialization_Prologue(pResource, pCallContext, pParams) sysmemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define sysmemCanCopy(pStandardMemory) sysmemCanCopy_DISPATCH(pStandardMemory) -#define sysmemIsGpuMapAllowed(pMemory, pGpu) sysmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) -#define sysmemControl_Prologue(pResource, pCallContext, pParams) sysmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define sysmemIsReady(pMemory, bCopyConstructorContext) sysmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define sysmemCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) sysmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) #define sysmemPreDestruct(pResource) sysmemPreDestruct_DISPATCH(pResource) #define sysmemIsDuplicate(pMemory, hMemory, pDuplicate) sysmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) -#define sysmemUnmapFrom(pResource, pParams) sysmemUnmapFrom_DISPATCH(pResource, pParams) -#define sysmemControl_Epilogue(pResource, pCallContext, pParams) sysmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define sysmemControlLookup(pResource, pParams, ppEntry) sysmemControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define sysmemControlSerialization_Epilogue(pResource, pCallContext, pParams) sysmemControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define sysmemMap(pMemory, pCallContext, pParams, pCpuMapping) sysmemMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define sysmemAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) sysmemAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS sysmemInitAllocRequest_HMM(struct OBJGPU *pGpu, struct SystemMemory *pSystemMemory, MEMORY_ALLOCATION_REQUEST *pAllocRequest); @@ -162,6 +166,46 @@ static inline NV_STATUS sysmemCheckMemInterUnmap_DISPATCH(struct SystemMemory *p return pMemory->__sysmemCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } +static inline NvBool sysmemShareCallback_DISPATCH(struct SystemMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__sysmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS sysmemMapTo_DISPATCH(struct SystemMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__sysmemMapTo__(pResource, pParams); +} + +static inline NV_STATUS sysmemGetMapAddrSpace_DISPATCH(struct SystemMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__sysmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 sysmemGetRefCount_DISPATCH(struct SystemMemory *pResource) { + return pResource->__sysmemGetRefCount__(pResource); +} + +static inline void sysmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct SystemMemory *pResource, RsResourceRef *pReference) { + pResource->__sysmemAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS sysmemControl_Prologue_DISPATCH(struct SystemMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__sysmemControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool sysmemIsGpuMapAllowed_DISPATCH(struct SystemMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__sysmemIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline NV_STATUS sysmemUnmapFrom_DISPATCH(struct SystemMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__sysmemUnmapFrom__(pResource, pParams); +} + +static inline void sysmemControl_Epilogue_DISPATCH(struct SystemMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__sysmemControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS sysmemControlLookup_DISPATCH(struct SystemMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__sysmemControlLookup__(pResource, pParams, ppEntry); +} + static inline NV_STATUS sysmemControl_DISPATCH(struct SystemMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pMemory->__sysmemControl__(pMemory, pCallContext, pParams); } @@ -178,42 +222,18 @@ static inline NV_STATUS sysmemGetMemoryMappingDescriptor_DISPATCH(struct SystemM return pMemory->__sysmemGetMemoryMappingDescriptor__(pMemory, ppMemDesc); } -static inline NV_STATUS sysmemGetMapAddrSpace_DISPATCH(struct SystemMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pMemory->__sysmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvBool sysmemShareCallback_DISPATCH(struct SystemMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pResource->__sysmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); -} - static inline NV_STATUS sysmemControlFilter_DISPATCH(struct SystemMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__sysmemControlFilter__(pResource, pCallContext, pParams); } -static inline void sysmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct SystemMemory *pResource, RsResourceRef *pReference) { - pResource->__sysmemAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 sysmemGetRefCount_DISPATCH(struct SystemMemory *pResource) { - return pResource->__sysmemGetRefCount__(pResource); -} - -static inline NV_STATUS sysmemMapTo_DISPATCH(struct SystemMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__sysmemMapTo__(pResource, pParams); +static inline NV_STATUS sysmemControlSerialization_Prologue_DISPATCH(struct SystemMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__sysmemControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool sysmemCanCopy_DISPATCH(struct SystemMemory *pStandardMemory) { return pStandardMemory->__sysmemCanCopy__(pStandardMemory); } -static inline NvBool sysmemIsGpuMapAllowed_DISPATCH(struct SystemMemory *pMemory, struct OBJGPU *pGpu) { - return pMemory->__sysmemIsGpuMapAllowed__(pMemory, pGpu); -} - -static inline NV_STATUS sysmemControl_Prologue_DISPATCH(struct SystemMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__sysmemControl_Prologue__(pResource, pCallContext, pParams); -} - static inline NV_STATUS sysmemIsReady_DISPATCH(struct SystemMemory *pMemory, NvBool bCopyConstructorContext) { return pMemory->__sysmemIsReady__(pMemory, bCopyConstructorContext); } @@ -230,16 +250,8 @@ static inline NV_STATUS sysmemIsDuplicate_DISPATCH(struct SystemMemory *pMemory, return pMemory->__sysmemIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline NV_STATUS sysmemUnmapFrom_DISPATCH(struct SystemMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__sysmemUnmapFrom__(pResource, pParams); -} - -static inline void sysmemControl_Epilogue_DISPATCH(struct SystemMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__sysmemControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS sysmemControlLookup_DISPATCH(struct SystemMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__sysmemControlLookup__(pResource, pParams, ppEntry); +static inline void sysmemControlSerialization_Epilogue_DISPATCH(struct SystemMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__sysmemControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS sysmemMap_DISPATCH(struct SystemMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_system_nvoc.c b/src/nvidia/generated/g_system_nvoc.c index 4aa948989..85bd55a3c 100644 --- a/src/nvidia/generated/g_system_nvoc.c +++ b/src/nvidia/generated/g_system_nvoc.c @@ -90,8 +90,12 @@ void __nvoc_init_dataField_OBJSYS(OBJSYS *pThis) { pThis->setProperty(pThis, PDB_PROP_SYS_IS_AGGRESSIVE_GC6_ENABLED, (0)); pThis->setProperty(pThis, PDB_PROP_SYS_PRIORITY_BOOST, (0)); pThis->setProperty(pThis, PDB_PROP_SYS_PRIORITY_THROTTLE_DELAY_US, 16 * 1000); - pThis->setProperty(pThis, PDB_PROP_SYS_CLIENT_HANDLE_LOOKUP, ((NvBool)(0 != 0))); + pThis->setProperty(pThis, PDB_PROP_SYS_CLIENT_HANDLE_LOOKUP, ((NvBool)(0 == 0))); pThis->setProperty(pThis, PDB_PROP_SYS_ROUTE_TO_PHYSICAL_LOCK_BYPASS, ((NvBool)(0 == 0))); + + pThis->bUseDeferredClientListFree = ((NvBool)(0 != 0)); + + pThis->clientListDeferredFreeLimit = 0; } NV_STATUS __nvoc_ctor_Object(Object* ); @@ -144,13 +148,16 @@ NV_STATUS __nvoc_objCreate_OBJSYS(OBJSYS **ppThis, Dynamic *pParent, NvU32 creat Object *pParentObj; OBJSYS *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJSYS)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJSYS), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJSYS)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJSYS); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -166,11 +173,17 @@ NV_STATUS __nvoc_objCreate_OBJSYS(OBJSYS **ppThis, Dynamic *pParent, NvU32 creat if (status != NV_OK) goto __nvoc_objCreate_OBJSYS_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJSYS_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJSYS)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_system_nvoc.h b/src/nvidia/generated/g_system_nvoc.h index f309b2c27..b59afc878 100644 --- a/src/nvidia/generated/g_system_nvoc.h +++ b/src/nvidia/generated/g_system_nvoc.h @@ -401,7 +401,6 @@ struct OBJSYS { NvU32 gpuLockModuleMask; NvBool PDB_PROP_SYS_ROUTE_TO_PHYSICAL_LOCK_BYPASS; NvU32 pwrTransitionTimeoutOverride; - NvBool bMulticastFlaEnabled; SYS_STATIC_CONFIG staticConfig; NvU32 debugFlags; NvU32 backtraceStackDepth; @@ -415,6 +414,8 @@ struct OBJSYS { NvBool PDB_PROP_SYS_IS_QSYNC_FW_REVISION_CHECK_DISABLED; NvU64 rmInstanceId; NvU32 currentCid; + NvBool bUseDeferredClientListFree; + NvU32 clientListDeferredFreeLimit; OS_RM_CAPS *pOsRmCaps; struct OBJGPUMGR *pGpuMgr; struct OBJGSYNCMGR *pGsyncMgr; diff --git a/src/nvidia/generated/g_third_party_p2p_nvoc.c b/src/nvidia/generated/g_third_party_p2p_nvoc.c index b19185797..6d5027aee 100644 --- a/src/nvidia/generated/g_third_party_p2p_nvoc.c +++ b/src/nvidia/generated/g_third_party_p2p_nvoc.c @@ -124,13 +124,16 @@ NV_STATUS __nvoc_objCreate_P2PTokenShare(P2PTokenShare **ppThis, Dynamic *pParen Object *pParentObj; P2PTokenShare *pThis; - pThis = portMemAllocNonPaged(sizeof(P2PTokenShare)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(P2PTokenShare), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(P2PTokenShare)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_P2PTokenShare); + pThis->__nvoc_base_RsShared.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -146,11 +149,17 @@ NV_STATUS __nvoc_objCreate_P2PTokenShare(P2PTokenShare **ppThis, Dynamic *pParen if (status != NV_OK) goto __nvoc_objCreate_P2PTokenShare_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_P2PTokenShare_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(P2PTokenShare)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } @@ -252,6 +261,54 @@ static NvBool __nvoc_thunk_GpuResource_thirdpartyp2pShareCallback(struct ThirdPa return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ThirdPartyP2P_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } +static NV_STATUS __nvoc_thunk_RmResource_thirdpartyp2pCheckMemInterUnmap(struct ThirdPartyP2P *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ThirdPartyP2P_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_thirdpartyp2pMapTo(struct ThirdPartyP2P *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_thirdpartyp2pGetMapAddrSpace(struct ThirdPartyP2P *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ThirdPartyP2P_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_thirdpartyp2pGetRefCount(struct ThirdPartyP2P *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_thirdpartyp2pAddAdditionalDependants(struct RsClient *pClient, struct ThirdPartyP2P *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_thirdpartyp2pControl_Prologue(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_thirdpartyp2pGetRegBaseOffsetAndSize(struct ThirdPartyP2P *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ThirdPartyP2P_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_thirdpartyp2pInternalControlForward(struct ThirdPartyP2P *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ThirdPartyP2P_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_thirdpartyp2pUnmapFrom(struct ThirdPartyP2P *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_thirdpartyp2pControl_Epilogue(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_thirdpartyp2pControlLookup(struct ThirdPartyP2P *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset), pParams, ppEntry); +} + +static NvHandle __nvoc_thunk_GpuResource_thirdpartyp2pGetInternalObjectHandle(struct ThirdPartyP2P *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ThirdPartyP2P_GpuResource.offset)); +} + static NV_STATUS __nvoc_thunk_GpuResource_thirdpartyp2pControl(struct ThirdPartyP2P *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ThirdPartyP2P_GpuResource.offset), pCallContext, pParams); } @@ -268,68 +325,28 @@ static NV_STATUS __nvoc_thunk_RmResource_thirdpartyp2pGetMemoryMappingDescriptor return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ThirdPartyP2P_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_GpuResource_thirdpartyp2pGetMapAddrSpace(struct ThirdPartyP2P *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ThirdPartyP2P_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvHandle __nvoc_thunk_GpuResource_thirdpartyp2pGetInternalObjectHandle(struct ThirdPartyP2P *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ThirdPartyP2P_GpuResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_thirdpartyp2pControlFilter(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_thirdpartyp2pAddAdditionalDependants(struct RsClient *pClient, struct ThirdPartyP2P *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_thirdpartyp2pGetRefCount(struct ThirdPartyP2P *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RmResource_thirdpartyp2pCheckMemInterUnmap(struct ThirdPartyP2P *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ThirdPartyP2P_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_thirdpartyp2pMapTo(struct ThirdPartyP2P *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_thirdpartyp2pControl_Prologue(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_GpuResource_thirdpartyp2pGetRegBaseOffsetAndSize(struct ThirdPartyP2P *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ThirdPartyP2P_GpuResource.offset), pGpu, pOffset, pSize); +static NV_STATUS __nvoc_thunk_RmResource_thirdpartyp2pControlSerialization_Prologue(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_thirdpartyp2pCanCopy(struct ThirdPartyP2P *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_thirdpartyp2pInternalControlForward(struct ThirdPartyP2P *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ThirdPartyP2P_GpuResource.offset), command, pParams, size); -} - static void __nvoc_thunk_RsResource_thirdpartyp2pPreDestruct(struct ThirdPartyP2P *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_thirdpartyp2pUnmapFrom(struct ThirdPartyP2P *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_thirdpartyp2pIsDuplicate(struct ThirdPartyP2P *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset), hMemory, pDuplicate); } -static void __nvoc_thunk_RmResource_thirdpartyp2pControl_Epilogue(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_thirdpartyp2pControlLookup(struct ThirdPartyP2P *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_thirdpartyp2pControlSerialization_Epilogue(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_thirdpartyp2pMap(struct ThirdPartyP2P *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -485,6 +502,30 @@ static void __nvoc_init_funcTable_ThirdPartyP2P_1(ThirdPartyP2P *pThis) { pThis->__thirdpartyp2pShareCallback__ = &__nvoc_thunk_GpuResource_thirdpartyp2pShareCallback; + pThis->__thirdpartyp2pCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_thirdpartyp2pCheckMemInterUnmap; + + pThis->__thirdpartyp2pMapTo__ = &__nvoc_thunk_RsResource_thirdpartyp2pMapTo; + + pThis->__thirdpartyp2pGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_thirdpartyp2pGetMapAddrSpace; + + pThis->__thirdpartyp2pGetRefCount__ = &__nvoc_thunk_RsResource_thirdpartyp2pGetRefCount; + + pThis->__thirdpartyp2pAddAdditionalDependants__ = &__nvoc_thunk_RsResource_thirdpartyp2pAddAdditionalDependants; + + pThis->__thirdpartyp2pControl_Prologue__ = &__nvoc_thunk_RmResource_thirdpartyp2pControl_Prologue; + + pThis->__thirdpartyp2pGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_thirdpartyp2pGetRegBaseOffsetAndSize; + + pThis->__thirdpartyp2pInternalControlForward__ = &__nvoc_thunk_GpuResource_thirdpartyp2pInternalControlForward; + + pThis->__thirdpartyp2pUnmapFrom__ = &__nvoc_thunk_RsResource_thirdpartyp2pUnmapFrom; + + pThis->__thirdpartyp2pControl_Epilogue__ = &__nvoc_thunk_RmResource_thirdpartyp2pControl_Epilogue; + + pThis->__thirdpartyp2pControlLookup__ = &__nvoc_thunk_RsResource_thirdpartyp2pControlLookup; + + pThis->__thirdpartyp2pGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_thirdpartyp2pGetInternalObjectHandle; + pThis->__thirdpartyp2pControl__ = &__nvoc_thunk_GpuResource_thirdpartyp2pControl; pThis->__thirdpartyp2pUnmap__ = &__nvoc_thunk_GpuResource_thirdpartyp2pUnmap; @@ -493,37 +534,17 @@ static void __nvoc_init_funcTable_ThirdPartyP2P_1(ThirdPartyP2P *pThis) { pThis->__thirdpartyp2pGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_thirdpartyp2pGetMemoryMappingDescriptor; - pThis->__thirdpartyp2pGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_thirdpartyp2pGetMapAddrSpace; - - pThis->__thirdpartyp2pGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_thirdpartyp2pGetInternalObjectHandle; - pThis->__thirdpartyp2pControlFilter__ = &__nvoc_thunk_RsResource_thirdpartyp2pControlFilter; - pThis->__thirdpartyp2pAddAdditionalDependants__ = &__nvoc_thunk_RsResource_thirdpartyp2pAddAdditionalDependants; - - pThis->__thirdpartyp2pGetRefCount__ = &__nvoc_thunk_RsResource_thirdpartyp2pGetRefCount; - - pThis->__thirdpartyp2pCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_thirdpartyp2pCheckMemInterUnmap; - - pThis->__thirdpartyp2pMapTo__ = &__nvoc_thunk_RsResource_thirdpartyp2pMapTo; - - pThis->__thirdpartyp2pControl_Prologue__ = &__nvoc_thunk_RmResource_thirdpartyp2pControl_Prologue; - - pThis->__thirdpartyp2pGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_thirdpartyp2pGetRegBaseOffsetAndSize; + pThis->__thirdpartyp2pControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_thirdpartyp2pControlSerialization_Prologue; pThis->__thirdpartyp2pCanCopy__ = &__nvoc_thunk_RsResource_thirdpartyp2pCanCopy; - pThis->__thirdpartyp2pInternalControlForward__ = &__nvoc_thunk_GpuResource_thirdpartyp2pInternalControlForward; - pThis->__thirdpartyp2pPreDestruct__ = &__nvoc_thunk_RsResource_thirdpartyp2pPreDestruct; - pThis->__thirdpartyp2pUnmapFrom__ = &__nvoc_thunk_RsResource_thirdpartyp2pUnmapFrom; - pThis->__thirdpartyp2pIsDuplicate__ = &__nvoc_thunk_RsResource_thirdpartyp2pIsDuplicate; - pThis->__thirdpartyp2pControl_Epilogue__ = &__nvoc_thunk_RmResource_thirdpartyp2pControl_Epilogue; - - pThis->__thirdpartyp2pControlLookup__ = &__nvoc_thunk_RsResource_thirdpartyp2pControlLookup; + pThis->__thirdpartyp2pControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_thirdpartyp2pControlSerialization_Epilogue; pThis->__thirdpartyp2pMap__ = &__nvoc_thunk_GpuResource_thirdpartyp2pMap; @@ -551,13 +572,16 @@ NV_STATUS __nvoc_objCreate_ThirdPartyP2P(ThirdPartyP2P **ppThis, Dynamic *pParen Object *pParentObj; ThirdPartyP2P *pThis; - pThis = portMemAllocNonPaged(sizeof(ThirdPartyP2P)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ThirdPartyP2P), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(ThirdPartyP2P)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ThirdPartyP2P); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -573,11 +597,17 @@ NV_STATUS __nvoc_objCreate_ThirdPartyP2P(ThirdPartyP2P **ppThis, Dynamic *pParen if (status != NV_OK) goto __nvoc_objCreate_ThirdPartyP2P_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_ThirdPartyP2P_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(ThirdPartyP2P)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_third_party_p2p_nvoc.h b/src/nvidia/generated/g_third_party_p2p_nvoc.h index b24a13f9d..74f1ca3ce 100644 --- a/src/nvidia/generated/g_third_party_p2p_nvoc.h +++ b/src/nvidia/generated/g_third_party_p2p_nvoc.h @@ -262,26 +262,28 @@ struct ThirdPartyP2P { NV_STATUS (*__thirdpartyp2pCtrlCmdUnregisterVidmem__)(struct ThirdPartyP2P *, NV503C_CTRL_UNREGISTER_VIDMEM_PARAMS *); NV_STATUS (*__thirdpartyp2pCtrlCmdRegisterPid__)(struct ThirdPartyP2P *, NV503C_CTRL_REGISTER_PID_PARAMS *); NvBool (*__thirdpartyp2pShareCallback__)(struct ThirdPartyP2P *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__thirdpartyp2pCheckMemInterUnmap__)(struct ThirdPartyP2P *, NvBool); + NV_STATUS (*__thirdpartyp2pMapTo__)(struct ThirdPartyP2P *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__thirdpartyp2pGetMapAddrSpace__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__thirdpartyp2pGetRefCount__)(struct ThirdPartyP2P *); + void (*__thirdpartyp2pAddAdditionalDependants__)(struct RsClient *, struct ThirdPartyP2P *, RsResourceRef *); + NV_STATUS (*__thirdpartyp2pControl_Prologue__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__thirdpartyp2pGetRegBaseOffsetAndSize__)(struct ThirdPartyP2P *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__thirdpartyp2pInternalControlForward__)(struct ThirdPartyP2P *, NvU32, void *, NvU32); + NV_STATUS (*__thirdpartyp2pUnmapFrom__)(struct ThirdPartyP2P *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__thirdpartyp2pControl_Epilogue__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__thirdpartyp2pControlLookup__)(struct ThirdPartyP2P *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__thirdpartyp2pGetInternalObjectHandle__)(struct ThirdPartyP2P *); NV_STATUS (*__thirdpartyp2pControl__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__thirdpartyp2pUnmap__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__thirdpartyp2pGetMemInterMapParams__)(struct ThirdPartyP2P *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__thirdpartyp2pGetMemoryMappingDescriptor__)(struct ThirdPartyP2P *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__thirdpartyp2pGetMapAddrSpace__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__thirdpartyp2pGetInternalObjectHandle__)(struct ThirdPartyP2P *); NV_STATUS (*__thirdpartyp2pControlFilter__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__thirdpartyp2pAddAdditionalDependants__)(struct RsClient *, struct ThirdPartyP2P *, RsResourceRef *); - NvU32 (*__thirdpartyp2pGetRefCount__)(struct ThirdPartyP2P *); - NV_STATUS (*__thirdpartyp2pCheckMemInterUnmap__)(struct ThirdPartyP2P *, NvBool); - NV_STATUS (*__thirdpartyp2pMapTo__)(struct ThirdPartyP2P *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__thirdpartyp2pControl_Prologue__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__thirdpartyp2pGetRegBaseOffsetAndSize__)(struct ThirdPartyP2P *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__thirdpartyp2pControlSerialization_Prologue__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__thirdpartyp2pCanCopy__)(struct ThirdPartyP2P *); - NV_STATUS (*__thirdpartyp2pInternalControlForward__)(struct ThirdPartyP2P *, NvU32, void *, NvU32); void (*__thirdpartyp2pPreDestruct__)(struct ThirdPartyP2P *); - NV_STATUS (*__thirdpartyp2pUnmapFrom__)(struct ThirdPartyP2P *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__thirdpartyp2pIsDuplicate__)(struct ThirdPartyP2P *, NvHandle, NvBool *); - void (*__thirdpartyp2pControl_Epilogue__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__thirdpartyp2pControlLookup__)(struct ThirdPartyP2P *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__thirdpartyp2pControlSerialization_Epilogue__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__thirdpartyp2pMap__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__thirdpartyp2pAccessCallback__)(struct ThirdPartyP2P *, struct RsClient *, void *, RsAccessRight); NODE Node; @@ -335,26 +337,28 @@ NV_STATUS __nvoc_objCreate_ThirdPartyP2P(ThirdPartyP2P**, Dynamic*, NvU32, struc #define thirdpartyp2pCtrlCmdUnregisterVidmem(pThirdPartyP2P, pUnregisterVidmemParams) thirdpartyp2pCtrlCmdUnregisterVidmem_DISPATCH(pThirdPartyP2P, pUnregisterVidmemParams) #define thirdpartyp2pCtrlCmdRegisterPid(pThirdPartyP2P, pParams) thirdpartyp2pCtrlCmdRegisterPid_DISPATCH(pThirdPartyP2P, pParams) #define thirdpartyp2pShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) thirdpartyp2pShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define thirdpartyp2pCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) thirdpartyp2pCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define thirdpartyp2pMapTo(pResource, pParams) thirdpartyp2pMapTo_DISPATCH(pResource, pParams) +#define thirdpartyp2pGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) thirdpartyp2pGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define thirdpartyp2pGetRefCount(pResource) thirdpartyp2pGetRefCount_DISPATCH(pResource) +#define thirdpartyp2pAddAdditionalDependants(pClient, pResource, pReference) thirdpartyp2pAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define thirdpartyp2pControl_Prologue(pResource, pCallContext, pParams) thirdpartyp2pControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define thirdpartyp2pGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) thirdpartyp2pGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define thirdpartyp2pInternalControlForward(pGpuResource, command, pParams, size) thirdpartyp2pInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define thirdpartyp2pUnmapFrom(pResource, pParams) thirdpartyp2pUnmapFrom_DISPATCH(pResource, pParams) +#define thirdpartyp2pControl_Epilogue(pResource, pCallContext, pParams) thirdpartyp2pControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define thirdpartyp2pControlLookup(pResource, pParams, ppEntry) thirdpartyp2pControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define thirdpartyp2pGetInternalObjectHandle(pGpuResource) thirdpartyp2pGetInternalObjectHandle_DISPATCH(pGpuResource) #define thirdpartyp2pControl(pGpuResource, pCallContext, pParams) thirdpartyp2pControl_DISPATCH(pGpuResource, pCallContext, pParams) #define thirdpartyp2pUnmap(pGpuResource, pCallContext, pCpuMapping) thirdpartyp2pUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define thirdpartyp2pGetMemInterMapParams(pRmResource, pParams) thirdpartyp2pGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define thirdpartyp2pGetMemoryMappingDescriptor(pRmResource, ppMemDesc) thirdpartyp2pGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define thirdpartyp2pGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) thirdpartyp2pGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define thirdpartyp2pGetInternalObjectHandle(pGpuResource) thirdpartyp2pGetInternalObjectHandle_DISPATCH(pGpuResource) #define thirdpartyp2pControlFilter(pResource, pCallContext, pParams) thirdpartyp2pControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define thirdpartyp2pAddAdditionalDependants(pClient, pResource, pReference) thirdpartyp2pAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define thirdpartyp2pGetRefCount(pResource) thirdpartyp2pGetRefCount_DISPATCH(pResource) -#define thirdpartyp2pCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) thirdpartyp2pCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define thirdpartyp2pMapTo(pResource, pParams) thirdpartyp2pMapTo_DISPATCH(pResource, pParams) -#define thirdpartyp2pControl_Prologue(pResource, pCallContext, pParams) thirdpartyp2pControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define thirdpartyp2pGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) thirdpartyp2pGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define thirdpartyp2pControlSerialization_Prologue(pResource, pCallContext, pParams) thirdpartyp2pControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define thirdpartyp2pCanCopy(pResource) thirdpartyp2pCanCopy_DISPATCH(pResource) -#define thirdpartyp2pInternalControlForward(pGpuResource, command, pParams, size) thirdpartyp2pInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define thirdpartyp2pPreDestruct(pResource) thirdpartyp2pPreDestruct_DISPATCH(pResource) -#define thirdpartyp2pUnmapFrom(pResource, pParams) thirdpartyp2pUnmapFrom_DISPATCH(pResource, pParams) #define thirdpartyp2pIsDuplicate(pResource, hMemory, pDuplicate) thirdpartyp2pIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) -#define thirdpartyp2pControl_Epilogue(pResource, pCallContext, pParams) thirdpartyp2pControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define thirdpartyp2pControlLookup(pResource, pParams, ppEntry) thirdpartyp2pControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define thirdpartyp2pControlSerialization_Epilogue(pResource, pCallContext, pParams) thirdpartyp2pControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define thirdpartyp2pMap(pGpuResource, pCallContext, pParams, pCpuMapping) thirdpartyp2pMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define thirdpartyp2pAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) thirdpartyp2pAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS thirdpartyp2pCtrlCmdRegisterVaSpace_IMPL(struct ThirdPartyP2P *pThirdPartyP2P, NV503C_CTRL_REGISTER_VA_SPACE_PARAMS *pRegisterVaSpaceParams); @@ -391,6 +395,54 @@ static inline NvBool thirdpartyp2pShareCallback_DISPATCH(struct ThirdPartyP2P *p return pGpuResource->__thirdpartyp2pShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } +static inline NV_STATUS thirdpartyp2pCheckMemInterUnmap_DISPATCH(struct ThirdPartyP2P *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__thirdpartyp2pCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS thirdpartyp2pMapTo_DISPATCH(struct ThirdPartyP2P *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__thirdpartyp2pMapTo__(pResource, pParams); +} + +static inline NV_STATUS thirdpartyp2pGetMapAddrSpace_DISPATCH(struct ThirdPartyP2P *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__thirdpartyp2pGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 thirdpartyp2pGetRefCount_DISPATCH(struct ThirdPartyP2P *pResource) { + return pResource->__thirdpartyp2pGetRefCount__(pResource); +} + +static inline void thirdpartyp2pAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ThirdPartyP2P *pResource, RsResourceRef *pReference) { + pResource->__thirdpartyp2pAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS thirdpartyp2pControl_Prologue_DISPATCH(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__thirdpartyp2pControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS thirdpartyp2pGetRegBaseOffsetAndSize_DISPATCH(struct ThirdPartyP2P *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__thirdpartyp2pGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS thirdpartyp2pInternalControlForward_DISPATCH(struct ThirdPartyP2P *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__thirdpartyp2pInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS thirdpartyp2pUnmapFrom_DISPATCH(struct ThirdPartyP2P *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__thirdpartyp2pUnmapFrom__(pResource, pParams); +} + +static inline void thirdpartyp2pControl_Epilogue_DISPATCH(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__thirdpartyp2pControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS thirdpartyp2pControlLookup_DISPATCH(struct ThirdPartyP2P *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__thirdpartyp2pControlLookup__(pResource, pParams, ppEntry); +} + +static inline NvHandle thirdpartyp2pGetInternalObjectHandle_DISPATCH(struct ThirdPartyP2P *pGpuResource) { + return pGpuResource->__thirdpartyp2pGetInternalObjectHandle__(pGpuResource); +} + static inline NV_STATUS thirdpartyp2pControl_DISPATCH(struct ThirdPartyP2P *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pGpuResource->__thirdpartyp2pControl__(pGpuResource, pCallContext, pParams); } @@ -407,68 +459,28 @@ static inline NV_STATUS thirdpartyp2pGetMemoryMappingDescriptor_DISPATCH(struct return pRmResource->__thirdpartyp2pGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS thirdpartyp2pGetMapAddrSpace_DISPATCH(struct ThirdPartyP2P *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__thirdpartyp2pGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvHandle thirdpartyp2pGetInternalObjectHandle_DISPATCH(struct ThirdPartyP2P *pGpuResource) { - return pGpuResource->__thirdpartyp2pGetInternalObjectHandle__(pGpuResource); -} - static inline NV_STATUS thirdpartyp2pControlFilter_DISPATCH(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__thirdpartyp2pControlFilter__(pResource, pCallContext, pParams); } -static inline void thirdpartyp2pAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ThirdPartyP2P *pResource, RsResourceRef *pReference) { - pResource->__thirdpartyp2pAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 thirdpartyp2pGetRefCount_DISPATCH(struct ThirdPartyP2P *pResource) { - return pResource->__thirdpartyp2pGetRefCount__(pResource); -} - -static inline NV_STATUS thirdpartyp2pCheckMemInterUnmap_DISPATCH(struct ThirdPartyP2P *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__thirdpartyp2pCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS thirdpartyp2pMapTo_DISPATCH(struct ThirdPartyP2P *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__thirdpartyp2pMapTo__(pResource, pParams); -} - -static inline NV_STATUS thirdpartyp2pControl_Prologue_DISPATCH(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__thirdpartyp2pControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS thirdpartyp2pGetRegBaseOffsetAndSize_DISPATCH(struct ThirdPartyP2P *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__thirdpartyp2pGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +static inline NV_STATUS thirdpartyp2pControlSerialization_Prologue_DISPATCH(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__thirdpartyp2pControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool thirdpartyp2pCanCopy_DISPATCH(struct ThirdPartyP2P *pResource) { return pResource->__thirdpartyp2pCanCopy__(pResource); } -static inline NV_STATUS thirdpartyp2pInternalControlForward_DISPATCH(struct ThirdPartyP2P *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__thirdpartyp2pInternalControlForward__(pGpuResource, command, pParams, size); -} - static inline void thirdpartyp2pPreDestruct_DISPATCH(struct ThirdPartyP2P *pResource) { pResource->__thirdpartyp2pPreDestruct__(pResource); } -static inline NV_STATUS thirdpartyp2pUnmapFrom_DISPATCH(struct ThirdPartyP2P *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__thirdpartyp2pUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS thirdpartyp2pIsDuplicate_DISPATCH(struct ThirdPartyP2P *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__thirdpartyp2pIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline void thirdpartyp2pControl_Epilogue_DISPATCH(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__thirdpartyp2pControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS thirdpartyp2pControlLookup_DISPATCH(struct ThirdPartyP2P *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__thirdpartyp2pControlLookup__(pResource, pParams, ppEntry); +static inline void thirdpartyp2pControlSerialization_Epilogue_DISPATCH(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__thirdpartyp2pControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS thirdpartyp2pMap_DISPATCH(struct ThirdPartyP2P *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_timed_sema_nvoc.c b/src/nvidia/generated/g_timed_sema_nvoc.c index 83e44aae0..68969079c 100644 --- a/src/nvidia/generated/g_timed_sema_nvoc.c +++ b/src/nvidia/generated/g_timed_sema_nvoc.c @@ -120,7 +120,7 @@ const struct NVOC_CLASS_DEF __nvoc_class_def_TimedSemaSwObject = /*pExportInfo=*/ &__nvoc_export_info_TimedSemaSwObject }; -static NV_STATUS __nvoc_thunk_TimedSemaSwObject_chandesGetSwMethods(struct ChannelDescendant *pTimedSemSw, METHOD **ppMethods, NvU32 *pNumMethods) { +static NV_STATUS __nvoc_thunk_TimedSemaSwObject_chandesGetSwMethods(struct ChannelDescendant *pTimedSemSw, const METHOD **ppMethods, NvU32 *pNumMethods) { return tsemaGetSwMethods((struct TimedSemaSwObject *)(((unsigned char *)pTimedSemSw) - __nvoc_rtti_TimedSemaSwObject_ChannelDescendant.offset), ppMethods, pNumMethods); } @@ -212,6 +212,10 @@ static NV_STATUS __nvoc_thunk_Notifier_tsemaUnregisterEvent(struct TimedSemaSwOb return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_TimedSemaSwObject_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_tsemaControlSerialization_Prologue(struct TimedSemaSwObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimedSemaSwObject_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_tsemaCanCopy(struct TimedSemaSwObject *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimedSemaSwObject_RsResource.offset)); } @@ -224,6 +228,10 @@ static NV_STATUS __nvoc_thunk_RsResource_tsemaIsDuplicate(struct TimedSemaSwObje return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimedSemaSwObject_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_tsemaControlSerialization_Epilogue(struct TimedSemaSwObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimedSemaSwObject_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_tsemaGetNotificationListPtr(struct TimedSemaSwObject *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_TimedSemaSwObject_Notifier.offset)); } @@ -393,12 +401,16 @@ static void __nvoc_init_funcTable_TimedSemaSwObject_1(TimedSemaSwObject *pThis) pThis->__tsemaUnregisterEvent__ = &__nvoc_thunk_Notifier_tsemaUnregisterEvent; + pThis->__tsemaControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_tsemaControlSerialization_Prologue; + pThis->__tsemaCanCopy__ = &__nvoc_thunk_RsResource_tsemaCanCopy; pThis->__tsemaPreDestruct__ = &__nvoc_thunk_RsResource_tsemaPreDestruct; pThis->__tsemaIsDuplicate__ = &__nvoc_thunk_RsResource_tsemaIsDuplicate; + pThis->__tsemaControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_tsemaControlSerialization_Epilogue; + pThis->__tsemaGetNotificationListPtr__ = &__nvoc_thunk_Notifier_tsemaGetNotificationListPtr; pThis->__tsemaGetNotificationShare__ = &__nvoc_thunk_Notifier_tsemaGetNotificationShare; @@ -433,13 +445,16 @@ NV_STATUS __nvoc_objCreate_TimedSemaSwObject(TimedSemaSwObject **ppThis, Dynamic TimedSemaSwObject *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(TimedSemaSwObject)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(TimedSemaSwObject), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(TimedSemaSwObject)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_TimedSemaSwObject); + pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -459,11 +474,17 @@ NV_STATUS __nvoc_objCreate_TimedSemaSwObject(TimedSemaSwObject **ppThis, Dynamic if (status != NV_OK) goto __nvoc_objCreate_TimedSemaSwObject_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_TimedSemaSwObject_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(TimedSemaSwObject)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_timed_sema_nvoc.h b/src/nvidia/generated/g_timed_sema_nvoc.h index 21eef5ffd..85418732b 100644 --- a/src/nvidia/generated/g_timed_sema_nvoc.h +++ b/src/nvidia/generated/g_timed_sema_nvoc.h @@ -69,7 +69,7 @@ struct TimedSemaSwObject { struct Notifier *__nvoc_pbase_Notifier; struct ChannelDescendant *__nvoc_pbase_ChannelDescendant; struct TimedSemaSwObject *__nvoc_pbase_TimedSemaSwObject; - NV_STATUS (*__tsemaGetSwMethods__)(struct TimedSemaSwObject *, METHOD **, NvU32 *); + NV_STATUS (*__tsemaGetSwMethods__)(struct TimedSemaSwObject *, const METHOD **, NvU32 *); NV_STATUS (*__tsemaCtrlCmdFlush__)(struct TimedSemaSwObject *, NV9074_CTRL_CMD_FLUSH_PARAMS *); NV_STATUS (*__tsemaCtrlCmdGetTime__)(struct TimedSemaSwObject *, NV9074_CTRL_CMD_GET_TIME_PARAMS *); NV_STATUS (*__tsemaCtrlCmdRelease__)(struct TimedSemaSwObject *, NV9074_CTRL_CMD_RELEASE_PARAMS *); @@ -95,9 +95,11 @@ struct TimedSemaSwObject { NvBool (*__tsemaIsSwMethodStalling__)(struct TimedSemaSwObject *, NvU32); NV_STATUS (*__tsemaControlFilter__)(struct TimedSemaSwObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__tsemaUnregisterEvent__)(struct TimedSemaSwObject *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__tsemaControlSerialization_Prologue__)(struct TimedSemaSwObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__tsemaCanCopy__)(struct TimedSemaSwObject *); void (*__tsemaPreDestruct__)(struct TimedSemaSwObject *); NV_STATUS (*__tsemaIsDuplicate__)(struct TimedSemaSwObject *, NvHandle, NvBool *); + void (*__tsemaControlSerialization_Epilogue__)(struct TimedSemaSwObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__tsemaGetNotificationListPtr__)(struct TimedSemaSwObject *); struct NotifShare *(*__tsemaGetNotificationShare__)(struct TimedSemaSwObject *); NV_STATUS (*__tsemaMap__)(struct TimedSemaSwObject *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -171,9 +173,11 @@ NV_STATUS __nvoc_objCreate_TimedSemaSwObject(TimedSemaSwObject**, Dynamic*, NvU3 #define tsemaIsSwMethodStalling(pChannelDescendant, hHandle) tsemaIsSwMethodStalling_DISPATCH(pChannelDescendant, hHandle) #define tsemaControlFilter(pResource, pCallContext, pParams) tsemaControlFilter_DISPATCH(pResource, pCallContext, pParams) #define tsemaUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) tsemaUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define tsemaControlSerialization_Prologue(pResource, pCallContext, pParams) tsemaControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define tsemaCanCopy(pResource) tsemaCanCopy_DISPATCH(pResource) #define tsemaPreDestruct(pResource) tsemaPreDestruct_DISPATCH(pResource) #define tsemaIsDuplicate(pResource, hMemory, pDuplicate) tsemaIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define tsemaControlSerialization_Epilogue(pResource, pCallContext, pParams) tsemaControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define tsemaGetNotificationListPtr(pNotifier) tsemaGetNotificationListPtr_DISPATCH(pNotifier) #define tsemaGetNotificationShare(pNotifier) tsemaGetNotificationShare_DISPATCH(pNotifier) #define tsemaMap(pGpuResource, pCallContext, pParams, pCpuMapping) tsemaMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -184,9 +188,9 @@ NV_STATUS tsemaRelease_KERNEL(struct OBJGPU *pGpu, NvU64 semaphoreVA, NvU64 noti #define tsemaRelease(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, hClient) tsemaRelease_KERNEL(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, hClient) #define tsemaRelease_HAL(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, hClient) tsemaRelease(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, hClient) -NV_STATUS tsemaGetSwMethods_IMPL(struct TimedSemaSwObject *pTimedSemSw, METHOD **ppMethods, NvU32 *pNumMethods); +NV_STATUS tsemaGetSwMethods_IMPL(struct TimedSemaSwObject *pTimedSemSw, const METHOD **ppMethods, NvU32 *pNumMethods); -static inline NV_STATUS tsemaGetSwMethods_DISPATCH(struct TimedSemaSwObject *pTimedSemSw, METHOD **ppMethods, NvU32 *pNumMethods) { +static inline NV_STATUS tsemaGetSwMethods_DISPATCH(struct TimedSemaSwObject *pTimedSemSw, const METHOD **ppMethods, NvU32 *pNumMethods) { return pTimedSemSw->__tsemaGetSwMethods__(pTimedSemSw, ppMethods, pNumMethods); } @@ -296,6 +300,10 @@ static inline NV_STATUS tsemaUnregisterEvent_DISPATCH(struct TimedSemaSwObject * return pNotifier->__tsemaUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS tsemaControlSerialization_Prologue_DISPATCH(struct TimedSemaSwObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__tsemaControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool tsemaCanCopy_DISPATCH(struct TimedSemaSwObject *pResource) { return pResource->__tsemaCanCopy__(pResource); } @@ -308,6 +316,10 @@ static inline NV_STATUS tsemaIsDuplicate_DISPATCH(struct TimedSemaSwObject *pRes return pResource->__tsemaIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void tsemaControlSerialization_Epilogue_DISPATCH(struct TimedSemaSwObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__tsemaControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *tsemaGetNotificationListPtr_DISPATCH(struct TimedSemaSwObject *pNotifier) { return pNotifier->__tsemaGetNotificationListPtr__(pNotifier); } diff --git a/src/nvidia/generated/g_tmr_nvoc.c b/src/nvidia/generated/g_tmr_nvoc.c index e9cd7ba6f..564a7904b 100644 --- a/src/nvidia/generated/g_tmr_nvoc.c +++ b/src/nvidia/generated/g_tmr_nvoc.c @@ -119,16 +119,16 @@ static NvBool __nvoc_thunk_GpuResource_tmrapiShareCallback(struct TimerApi *pGpu return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_TimerApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_RsResource_tmrapiMapTo(struct TimerApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimerApi_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_tmrapiCheckMemInterUnmap(struct TimerApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_TimerApi_RmResource.offset), bSubdeviceHandleProvided); } static NV_STATUS __nvoc_thunk_Notifier_tmrapiGetOrAllocNotifShare(struct TimerApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_TimerApi_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); } -static NV_STATUS __nvoc_thunk_RmResource_tmrapiCheckMemInterUnmap(struct TimerApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_TimerApi_RmResource.offset), bSubdeviceHandleProvided); +static NV_STATUS __nvoc_thunk_RsResource_tmrapiMapTo(struct TimerApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimerApi_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_GpuResource_tmrapiGetMapAddrSpace(struct TimerApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -195,6 +195,10 @@ static NV_STATUS __nvoc_thunk_Notifier_tmrapiUnregisterEvent(struct TimerApi *pN return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_TimerApi_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_tmrapiControlSerialization_Prologue(struct TimerApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimerApi_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_tmrapiCanCopy(struct TimerApi *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimerApi_RsResource.offset)); } @@ -207,6 +211,10 @@ static NV_STATUS __nvoc_thunk_RsResource_tmrapiIsDuplicate(struct TimerApi *pRes return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimerApi_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_tmrapiControlSerialization_Epilogue(struct TimerApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimerApi_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_tmrapiGetNotificationListPtr(struct TimerApi *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_TimerApi_Notifier.offset)); } @@ -303,11 +311,11 @@ static void __nvoc_init_funcTable_TimerApi_1(TimerApi *pThis) { pThis->__tmrapiShareCallback__ = &__nvoc_thunk_GpuResource_tmrapiShareCallback; - pThis->__tmrapiMapTo__ = &__nvoc_thunk_RsResource_tmrapiMapTo; + pThis->__tmrapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_tmrapiCheckMemInterUnmap; pThis->__tmrapiGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_tmrapiGetOrAllocNotifShare; - pThis->__tmrapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_tmrapiCheckMemInterUnmap; + pThis->__tmrapiMapTo__ = &__nvoc_thunk_RsResource_tmrapiMapTo; pThis->__tmrapiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_tmrapiGetMapAddrSpace; @@ -341,12 +349,16 @@ static void __nvoc_init_funcTable_TimerApi_1(TimerApi *pThis) { pThis->__tmrapiUnregisterEvent__ = &__nvoc_thunk_Notifier_tmrapiUnregisterEvent; + pThis->__tmrapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_tmrapiControlSerialization_Prologue; + pThis->__tmrapiCanCopy__ = &__nvoc_thunk_RsResource_tmrapiCanCopy; pThis->__tmrapiPreDestruct__ = &__nvoc_thunk_RsResource_tmrapiPreDestruct; pThis->__tmrapiIsDuplicate__ = &__nvoc_thunk_RsResource_tmrapiIsDuplicate; + pThis->__tmrapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_tmrapiControlSerialization_Epilogue; + pThis->__tmrapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_tmrapiGetNotificationListPtr; pThis->__tmrapiGetNotificationShare__ = &__nvoc_thunk_Notifier_tmrapiGetNotificationShare; @@ -381,13 +393,16 @@ NV_STATUS __nvoc_objCreate_TimerApi(TimerApi **ppThis, Dynamic *pParent, NvU32 c Object *pParentObj; TimerApi *pThis; - pThis = portMemAllocNonPaged(sizeof(TimerApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(TimerApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(TimerApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_TimerApi); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -403,11 +418,17 @@ NV_STATUS __nvoc_objCreate_TimerApi(TimerApi **ppThis, Dynamic *pParent, NvU32 c if (status != NV_OK) goto __nvoc_objCreate_TimerApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_TimerApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(TimerApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_tmr_nvoc.h b/src/nvidia/generated/g_tmr_nvoc.h index ac9e24803..a75b6cc58 100644 --- a/src/nvidia/generated/g_tmr_nvoc.h +++ b/src/nvidia/generated/g_tmr_nvoc.h @@ -100,9 +100,9 @@ struct TimerApi { NV_STATUS (*__tmrapiGetRegBaseOffsetAndSize__)(struct TimerApi *, struct OBJGPU *, NvU32 *, NvU32 *); NV_STATUS (*__tmrapiCtrlCmdTmrSetAlarmNotify__)(struct TimerApi *, NV0004_CTRL_TMR_SET_ALARM_NOTIFY_PARAMS *); NvBool (*__tmrapiShareCallback__)(struct TimerApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__tmrapiMapTo__)(struct TimerApi *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__tmrapiGetOrAllocNotifShare__)(struct TimerApi *, NvHandle, NvHandle, struct NotifShare **); NV_STATUS (*__tmrapiCheckMemInterUnmap__)(struct TimerApi *, NvBool); + NV_STATUS (*__tmrapiGetOrAllocNotifShare__)(struct TimerApi *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__tmrapiMapTo__)(struct TimerApi *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__tmrapiGetMapAddrSpace__)(struct TimerApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); void (*__tmrapiSetNotificationShare__)(struct TimerApi *, struct NotifShare *); NvU32 (*__tmrapiGetRefCount__)(struct TimerApi *); @@ -119,9 +119,11 @@ struct TimerApi { NV_STATUS (*__tmrapiGetMemoryMappingDescriptor__)(struct TimerApi *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__tmrapiControlFilter__)(struct TimerApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__tmrapiUnregisterEvent__)(struct TimerApi *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__tmrapiControlSerialization_Prologue__)(struct TimerApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__tmrapiCanCopy__)(struct TimerApi *); void (*__tmrapiPreDestruct__)(struct TimerApi *); NV_STATUS (*__tmrapiIsDuplicate__)(struct TimerApi *, NvHandle, NvBool *); + void (*__tmrapiControlSerialization_Epilogue__)(struct TimerApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__tmrapiGetNotificationListPtr__)(struct TimerApi *); struct NotifShare *(*__tmrapiGetNotificationShare__)(struct TimerApi *); NV_STATUS (*__tmrapiMap__)(struct TimerApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -159,9 +161,9 @@ NV_STATUS __nvoc_objCreate_TimerApi(TimerApi**, Dynamic*, NvU32, struct CALL_CON #define tmrapiGetRegBaseOffsetAndSize(pTimerApi, pGpu, pOffset, pSize) tmrapiGetRegBaseOffsetAndSize_DISPATCH(pTimerApi, pGpu, pOffset, pSize) #define tmrapiCtrlCmdTmrSetAlarmNotify(pTimerApi, pParams) tmrapiCtrlCmdTmrSetAlarmNotify_DISPATCH(pTimerApi, pParams) #define tmrapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) tmrapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define tmrapiMapTo(pResource, pParams) tmrapiMapTo_DISPATCH(pResource, pParams) -#define tmrapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) tmrapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) #define tmrapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) tmrapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define tmrapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) tmrapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define tmrapiMapTo(pResource, pParams) tmrapiMapTo_DISPATCH(pResource, pParams) #define tmrapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) tmrapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) #define tmrapiSetNotificationShare(pNotifier, pNotifShare) tmrapiSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define tmrapiGetRefCount(pResource) tmrapiGetRefCount_DISPATCH(pResource) @@ -178,9 +180,11 @@ NV_STATUS __nvoc_objCreate_TimerApi(TimerApi**, Dynamic*, NvU32, struct CALL_CON #define tmrapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) tmrapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define tmrapiControlFilter(pResource, pCallContext, pParams) tmrapiControlFilter_DISPATCH(pResource, pCallContext, pParams) #define tmrapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) tmrapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define tmrapiControlSerialization_Prologue(pResource, pCallContext, pParams) tmrapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define tmrapiCanCopy(pResource) tmrapiCanCopy_DISPATCH(pResource) #define tmrapiPreDestruct(pResource) tmrapiPreDestruct_DISPATCH(pResource) #define tmrapiIsDuplicate(pResource, hMemory, pDuplicate) tmrapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define tmrapiControlSerialization_Epilogue(pResource, pCallContext, pParams) tmrapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define tmrapiGetNotificationListPtr(pNotifier) tmrapiGetNotificationListPtr_DISPATCH(pNotifier) #define tmrapiGetNotificationShare(pNotifier) tmrapiGetNotificationShare_DISPATCH(pNotifier) #define tmrapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) tmrapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -201,16 +205,16 @@ static inline NvBool tmrapiShareCallback_DISPATCH(struct TimerApi *pGpuResource, return pGpuResource->__tmrapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS tmrapiMapTo_DISPATCH(struct TimerApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__tmrapiMapTo__(pResource, pParams); +static inline NV_STATUS tmrapiCheckMemInterUnmap_DISPATCH(struct TimerApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__tmrapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } static inline NV_STATUS tmrapiGetOrAllocNotifShare_DISPATCH(struct TimerApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return pNotifier->__tmrapiGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); } -static inline NV_STATUS tmrapiCheckMemInterUnmap_DISPATCH(struct TimerApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__tmrapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline NV_STATUS tmrapiMapTo_DISPATCH(struct TimerApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__tmrapiMapTo__(pResource, pParams); } static inline NV_STATUS tmrapiGetMapAddrSpace_DISPATCH(struct TimerApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -277,6 +281,10 @@ static inline NV_STATUS tmrapiUnregisterEvent_DISPATCH(struct TimerApi *pNotifie return pNotifier->__tmrapiUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS tmrapiControlSerialization_Prologue_DISPATCH(struct TimerApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__tmrapiControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool tmrapiCanCopy_DISPATCH(struct TimerApi *pResource) { return pResource->__tmrapiCanCopy__(pResource); } @@ -289,6 +297,10 @@ static inline NV_STATUS tmrapiIsDuplicate_DISPATCH(struct TimerApi *pResource, N return pResource->__tmrapiIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void tmrapiControlSerialization_Epilogue_DISPATCH(struct TimerApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__tmrapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *tmrapiGetNotificationListPtr_DISPATCH(struct TimerApi *pNotifier) { return pNotifier->__tmrapiGetNotificationListPtr__(pNotifier); } diff --git a/src/nvidia/generated/g_usermode_api_nvoc.c b/src/nvidia/generated/g_usermode_api_nvoc.c index 766b49bee..f753e3051 100644 --- a/src/nvidia/generated/g_usermode_api_nvoc.c +++ b/src/nvidia/generated/g_usermode_api_nvoc.c @@ -101,6 +101,46 @@ static NV_STATUS __nvoc_thunk_Memory_usrmodeCheckMemInterUnmap(struct UserModeAp return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), bSubdeviceHandleProvided); } +static NvBool __nvoc_thunk_RmResource_usrmodeShareCallback(struct UserModeApi *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RsResource_usrmodeMapTo(struct UserModeApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_usrmodeGetMapAddrSpace(struct UserModeApi *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_usrmodeGetRefCount(struct UserModeApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_usrmodeAddAdditionalDependants(struct RsClient *pClient, struct UserModeApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_usrmodeControl_Prologue(struct UserModeApi *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_Memory_usrmodeIsGpuMapAllowed(struct UserModeApi *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), pGpu); +} + +static NV_STATUS __nvoc_thunk_RsResource_usrmodeUnmapFrom(struct UserModeApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_usrmodeControl_Epilogue(struct UserModeApi *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_usrmodeControlLookup(struct UserModeApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RsResource.offset), pParams, ppEntry); +} + static NV_STATUS __nvoc_thunk_Memory_usrmodeControl(struct UserModeApi *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), pCallContext, pParams); } @@ -117,36 +157,12 @@ static NV_STATUS __nvoc_thunk_Memory_usrmodeGetMemoryMappingDescriptor(struct Us return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_Memory_usrmodeGetMapAddrSpace(struct UserModeApi *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvBool __nvoc_thunk_RmResource_usrmodeShareCallback(struct UserModeApi *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); -} - static NV_STATUS __nvoc_thunk_RsResource_usrmodeControlFilter(struct UserModeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_usrmodeAddAdditionalDependants(struct RsClient *pClient, struct UserModeApi *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_usrmodeGetRefCount(struct UserModeApi *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RsResource_usrmodeMapTo(struct UserModeApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_usrmodeControl_Prologue(struct UserModeApi *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RmResource.offset), pCallContext, pParams); -} - -static NvBool __nvoc_thunk_Memory_usrmodeIsGpuMapAllowed(struct UserModeApi *pMemory, struct OBJGPU *pGpu) { - return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), pGpu); +static NV_STATUS __nvoc_thunk_RmResource_usrmodeControlSerialization_Prologue(struct UserModeApi *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_usrmodeIsReady(struct UserModeApi *pMemory, NvBool bCopyConstructorContext) { @@ -165,16 +181,8 @@ static NV_STATUS __nvoc_thunk_Memory_usrmodeIsDuplicate(struct UserModeApi *pMem return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), hMemory, pDuplicate); } -static NV_STATUS __nvoc_thunk_RsResource_usrmodeUnmapFrom(struct UserModeApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RmResource_usrmodeControl_Epilogue(struct UserModeApi *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_usrmodeControlLookup(struct UserModeApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_usrmodeControlSerialization_Epilogue(struct UserModeApi *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_usrmodeMap(struct UserModeApi *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -249,6 +257,26 @@ static void __nvoc_init_funcTable_UserModeApi_1(UserModeApi *pThis, RmHalspecOwn pThis->__usrmodeCheckMemInterUnmap__ = &__nvoc_thunk_Memory_usrmodeCheckMemInterUnmap; + pThis->__usrmodeShareCallback__ = &__nvoc_thunk_RmResource_usrmodeShareCallback; + + pThis->__usrmodeMapTo__ = &__nvoc_thunk_RsResource_usrmodeMapTo; + + pThis->__usrmodeGetMapAddrSpace__ = &__nvoc_thunk_Memory_usrmodeGetMapAddrSpace; + + pThis->__usrmodeGetRefCount__ = &__nvoc_thunk_RsResource_usrmodeGetRefCount; + + pThis->__usrmodeAddAdditionalDependants__ = &__nvoc_thunk_RsResource_usrmodeAddAdditionalDependants; + + pThis->__usrmodeControl_Prologue__ = &__nvoc_thunk_RmResource_usrmodeControl_Prologue; + + pThis->__usrmodeIsGpuMapAllowed__ = &__nvoc_thunk_Memory_usrmodeIsGpuMapAllowed; + + pThis->__usrmodeUnmapFrom__ = &__nvoc_thunk_RsResource_usrmodeUnmapFrom; + + pThis->__usrmodeControl_Epilogue__ = &__nvoc_thunk_RmResource_usrmodeControl_Epilogue; + + pThis->__usrmodeControlLookup__ = &__nvoc_thunk_RsResource_usrmodeControlLookup; + pThis->__usrmodeControl__ = &__nvoc_thunk_Memory_usrmodeControl; pThis->__usrmodeUnmap__ = &__nvoc_thunk_Memory_usrmodeUnmap; @@ -257,21 +285,9 @@ static void __nvoc_init_funcTable_UserModeApi_1(UserModeApi *pThis, RmHalspecOwn pThis->__usrmodeGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_usrmodeGetMemoryMappingDescriptor; - pThis->__usrmodeGetMapAddrSpace__ = &__nvoc_thunk_Memory_usrmodeGetMapAddrSpace; - - pThis->__usrmodeShareCallback__ = &__nvoc_thunk_RmResource_usrmodeShareCallback; - pThis->__usrmodeControlFilter__ = &__nvoc_thunk_RsResource_usrmodeControlFilter; - pThis->__usrmodeAddAdditionalDependants__ = &__nvoc_thunk_RsResource_usrmodeAddAdditionalDependants; - - pThis->__usrmodeGetRefCount__ = &__nvoc_thunk_RsResource_usrmodeGetRefCount; - - pThis->__usrmodeMapTo__ = &__nvoc_thunk_RsResource_usrmodeMapTo; - - pThis->__usrmodeControl_Prologue__ = &__nvoc_thunk_RmResource_usrmodeControl_Prologue; - - pThis->__usrmodeIsGpuMapAllowed__ = &__nvoc_thunk_Memory_usrmodeIsGpuMapAllowed; + pThis->__usrmodeControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_usrmodeControlSerialization_Prologue; pThis->__usrmodeIsReady__ = &__nvoc_thunk_Memory_usrmodeIsReady; @@ -281,11 +297,7 @@ static void __nvoc_init_funcTable_UserModeApi_1(UserModeApi *pThis, RmHalspecOwn pThis->__usrmodeIsDuplicate__ = &__nvoc_thunk_Memory_usrmodeIsDuplicate; - pThis->__usrmodeUnmapFrom__ = &__nvoc_thunk_RsResource_usrmodeUnmapFrom; - - pThis->__usrmodeControl_Epilogue__ = &__nvoc_thunk_RmResource_usrmodeControl_Epilogue; - - pThis->__usrmodeControlLookup__ = &__nvoc_thunk_RsResource_usrmodeControlLookup; + pThis->__usrmodeControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_usrmodeControlSerialization_Epilogue; pThis->__usrmodeMap__ = &__nvoc_thunk_Memory_usrmodeMap; @@ -314,13 +326,16 @@ NV_STATUS __nvoc_objCreate_UserModeApi(UserModeApi **ppThis, Dynamic *pParent, N UserModeApi *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(UserModeApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(UserModeApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(UserModeApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_UserModeApi); + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -340,11 +355,17 @@ NV_STATUS __nvoc_objCreate_UserModeApi(UserModeApi **ppThis, Dynamic *pParent, N if (status != NV_OK) goto __nvoc_objCreate_UserModeApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_UserModeApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(UserModeApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_usermode_api_nvoc.h b/src/nvidia/generated/g_usermode_api_nvoc.h index 86ca62e17..19b4cb860 100644 --- a/src/nvidia/generated/g_usermode_api_nvoc.h +++ b/src/nvidia/generated/g_usermode_api_nvoc.h @@ -61,25 +61,27 @@ struct UserModeApi { NV_STATUS (*__usrmodeConstructHal__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); NvBool (*__usrmodeCanCopy__)(struct UserModeApi *); NV_STATUS (*__usrmodeCheckMemInterUnmap__)(struct UserModeApi *, NvBool); + NvBool (*__usrmodeShareCallback__)(struct UserModeApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__usrmodeMapTo__)(struct UserModeApi *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__usrmodeGetMapAddrSpace__)(struct UserModeApi *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__usrmodeGetRefCount__)(struct UserModeApi *); + void (*__usrmodeAddAdditionalDependants__)(struct RsClient *, struct UserModeApi *, RsResourceRef *); + NV_STATUS (*__usrmodeControl_Prologue__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__usrmodeIsGpuMapAllowed__)(struct UserModeApi *, struct OBJGPU *); + NV_STATUS (*__usrmodeUnmapFrom__)(struct UserModeApi *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__usrmodeControl_Epilogue__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__usrmodeControlLookup__)(struct UserModeApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__usrmodeControl__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__usrmodeUnmap__)(struct UserModeApi *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__usrmodeGetMemInterMapParams__)(struct UserModeApi *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__usrmodeGetMemoryMappingDescriptor__)(struct UserModeApi *, MEMORY_DESCRIPTOR **); - NV_STATUS (*__usrmodeGetMapAddrSpace__)(struct UserModeApi *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvBool (*__usrmodeShareCallback__)(struct UserModeApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__usrmodeControlFilter__)(struct UserModeApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__usrmodeAddAdditionalDependants__)(struct RsClient *, struct UserModeApi *, RsResourceRef *); - NvU32 (*__usrmodeGetRefCount__)(struct UserModeApi *); - NV_STATUS (*__usrmodeMapTo__)(struct UserModeApi *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__usrmodeControl_Prologue__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NvBool (*__usrmodeIsGpuMapAllowed__)(struct UserModeApi *, struct OBJGPU *); + NV_STATUS (*__usrmodeControlSerialization_Prologue__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__usrmodeIsReady__)(struct UserModeApi *, NvBool); NV_STATUS (*__usrmodeCheckCopyPermissions__)(struct UserModeApi *, struct OBJGPU *, NvHandle); void (*__usrmodePreDestruct__)(struct UserModeApi *); NV_STATUS (*__usrmodeIsDuplicate__)(struct UserModeApi *, NvHandle, NvBool *); - NV_STATUS (*__usrmodeUnmapFrom__)(struct UserModeApi *, RS_RES_UNMAP_FROM_PARAMS *); - void (*__usrmodeControl_Epilogue__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__usrmodeControlLookup__)(struct UserModeApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__usrmodeControlSerialization_Epilogue__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__usrmodeMap__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__usrmodeAccessCallback__)(struct UserModeApi *, struct RsClient *, void *, RsAccessRight); }; @@ -116,25 +118,27 @@ NV_STATUS __nvoc_objCreate_UserModeApi(UserModeApi**, Dynamic*, NvU32, CALL_CONT #define usrmodeConstructHal_HAL(pUserModeApi, pCallContext, pParams) usrmodeConstructHal_DISPATCH(pUserModeApi, pCallContext, pParams) #define usrmodeCanCopy(pUserModeApi) usrmodeCanCopy_DISPATCH(pUserModeApi) #define usrmodeCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) usrmodeCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define usrmodeShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) usrmodeShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define usrmodeMapTo(pResource, pParams) usrmodeMapTo_DISPATCH(pResource, pParams) +#define usrmodeGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) usrmodeGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define usrmodeGetRefCount(pResource) usrmodeGetRefCount_DISPATCH(pResource) +#define usrmodeAddAdditionalDependants(pClient, pResource, pReference) usrmodeAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define usrmodeControl_Prologue(pResource, pCallContext, pParams) usrmodeControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define usrmodeIsGpuMapAllowed(pMemory, pGpu) usrmodeIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define usrmodeUnmapFrom(pResource, pParams) usrmodeUnmapFrom_DISPATCH(pResource, pParams) +#define usrmodeControl_Epilogue(pResource, pCallContext, pParams) usrmodeControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define usrmodeControlLookup(pResource, pParams, ppEntry) usrmodeControlLookup_DISPATCH(pResource, pParams, ppEntry) #define usrmodeControl(pMemory, pCallContext, pParams) usrmodeControl_DISPATCH(pMemory, pCallContext, pParams) #define usrmodeUnmap(pMemory, pCallContext, pCpuMapping) usrmodeUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define usrmodeGetMemInterMapParams(pMemory, pParams) usrmodeGetMemInterMapParams_DISPATCH(pMemory, pParams) #define usrmodeGetMemoryMappingDescriptor(pMemory, ppMemDesc) usrmodeGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define usrmodeGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) usrmodeGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) -#define usrmodeShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) usrmodeShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define usrmodeControlFilter(pResource, pCallContext, pParams) usrmodeControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define usrmodeAddAdditionalDependants(pClient, pResource, pReference) usrmodeAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define usrmodeGetRefCount(pResource) usrmodeGetRefCount_DISPATCH(pResource) -#define usrmodeMapTo(pResource, pParams) usrmodeMapTo_DISPATCH(pResource, pParams) -#define usrmodeControl_Prologue(pResource, pCallContext, pParams) usrmodeControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define usrmodeIsGpuMapAllowed(pMemory, pGpu) usrmodeIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define usrmodeControlSerialization_Prologue(pResource, pCallContext, pParams) usrmodeControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define usrmodeIsReady(pMemory, bCopyConstructorContext) usrmodeIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define usrmodeCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) usrmodeCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) #define usrmodePreDestruct(pResource) usrmodePreDestruct_DISPATCH(pResource) #define usrmodeIsDuplicate(pMemory, hMemory, pDuplicate) usrmodeIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) -#define usrmodeUnmapFrom(pResource, pParams) usrmodeUnmapFrom_DISPATCH(pResource, pParams) -#define usrmodeControl_Epilogue(pResource, pCallContext, pParams) usrmodeControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define usrmodeControlLookup(pResource, pParams, ppEntry) usrmodeControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define usrmodeControlSerialization_Epilogue(pResource, pCallContext, pParams) usrmodeControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define usrmodeMap(pMemory, pCallContext, pParams, pCpuMapping) usrmodeMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define usrmodeAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) usrmodeAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS usrmodeConstructHal_GV100(struct UserModeApi *pUserModeApi, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); @@ -155,6 +159,46 @@ static inline NV_STATUS usrmodeCheckMemInterUnmap_DISPATCH(struct UserModeApi *p return pMemory->__usrmodeCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } +static inline NvBool usrmodeShareCallback_DISPATCH(struct UserModeApi *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__usrmodeShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS usrmodeMapTo_DISPATCH(struct UserModeApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__usrmodeMapTo__(pResource, pParams); +} + +static inline NV_STATUS usrmodeGetMapAddrSpace_DISPATCH(struct UserModeApi *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__usrmodeGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 usrmodeGetRefCount_DISPATCH(struct UserModeApi *pResource) { + return pResource->__usrmodeGetRefCount__(pResource); +} + +static inline void usrmodeAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct UserModeApi *pResource, RsResourceRef *pReference) { + pResource->__usrmodeAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS usrmodeControl_Prologue_DISPATCH(struct UserModeApi *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__usrmodeControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool usrmodeIsGpuMapAllowed_DISPATCH(struct UserModeApi *pMemory, struct OBJGPU *pGpu) { + return pMemory->__usrmodeIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline NV_STATUS usrmodeUnmapFrom_DISPATCH(struct UserModeApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__usrmodeUnmapFrom__(pResource, pParams); +} + +static inline void usrmodeControl_Epilogue_DISPATCH(struct UserModeApi *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__usrmodeControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS usrmodeControlLookup_DISPATCH(struct UserModeApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__usrmodeControlLookup__(pResource, pParams, ppEntry); +} + static inline NV_STATUS usrmodeControl_DISPATCH(struct UserModeApi *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pMemory->__usrmodeControl__(pMemory, pCallContext, pParams); } @@ -171,36 +215,12 @@ static inline NV_STATUS usrmodeGetMemoryMappingDescriptor_DISPATCH(struct UserMo return pMemory->__usrmodeGetMemoryMappingDescriptor__(pMemory, ppMemDesc); } -static inline NV_STATUS usrmodeGetMapAddrSpace_DISPATCH(struct UserModeApi *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pMemory->__usrmodeGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvBool usrmodeShareCallback_DISPATCH(struct UserModeApi *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pResource->__usrmodeShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); -} - static inline NV_STATUS usrmodeControlFilter_DISPATCH(struct UserModeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__usrmodeControlFilter__(pResource, pCallContext, pParams); } -static inline void usrmodeAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct UserModeApi *pResource, RsResourceRef *pReference) { - pResource->__usrmodeAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 usrmodeGetRefCount_DISPATCH(struct UserModeApi *pResource) { - return pResource->__usrmodeGetRefCount__(pResource); -} - -static inline NV_STATUS usrmodeMapTo_DISPATCH(struct UserModeApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__usrmodeMapTo__(pResource, pParams); -} - -static inline NV_STATUS usrmodeControl_Prologue_DISPATCH(struct UserModeApi *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__usrmodeControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NvBool usrmodeIsGpuMapAllowed_DISPATCH(struct UserModeApi *pMemory, struct OBJGPU *pGpu) { - return pMemory->__usrmodeIsGpuMapAllowed__(pMemory, pGpu); +static inline NV_STATUS usrmodeControlSerialization_Prologue_DISPATCH(struct UserModeApi *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__usrmodeControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NV_STATUS usrmodeIsReady_DISPATCH(struct UserModeApi *pMemory, NvBool bCopyConstructorContext) { @@ -219,16 +239,8 @@ static inline NV_STATUS usrmodeIsDuplicate_DISPATCH(struct UserModeApi *pMemory, return pMemory->__usrmodeIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline NV_STATUS usrmodeUnmapFrom_DISPATCH(struct UserModeApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__usrmodeUnmapFrom__(pResource, pParams); -} - -static inline void usrmodeControl_Epilogue_DISPATCH(struct UserModeApi *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__usrmodeControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS usrmodeControlLookup_DISPATCH(struct UserModeApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__usrmodeControlLookup__(pResource, pParams, ppEntry); +static inline void usrmodeControlSerialization_Epilogue_DISPATCH(struct UserModeApi *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__usrmodeControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS usrmodeMap_DISPATCH(struct UserModeApi *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_uvm_channel_retainer_nvoc.c b/src/nvidia/generated/g_uvm_channel_retainer_nvoc.c index 368d52345..8d5b50368 100644 --- a/src/nvidia/generated/g_uvm_channel_retainer_nvoc.c +++ b/src/nvidia/generated/g_uvm_channel_retainer_nvoc.c @@ -97,6 +97,54 @@ static NvBool __nvoc_thunk_GpuResource_uvmchanrtnrShareCallback(struct UvmChanne return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_UvmChannelRetainer_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } +static NV_STATUS __nvoc_thunk_RmResource_uvmchanrtnrCheckMemInterUnmap(struct UvmChannelRetainer *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_UvmChannelRetainer_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_uvmchanrtnrMapTo(struct UvmChannelRetainer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_uvmchanrtnrGetMapAddrSpace(struct UvmChannelRetainer *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_UvmChannelRetainer_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_uvmchanrtnrGetRefCount(struct UvmChannelRetainer *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_uvmchanrtnrAddAdditionalDependants(struct RsClient *pClient, struct UvmChannelRetainer *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_uvmchanrtnrControl_Prologue(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_uvmchanrtnrGetRegBaseOffsetAndSize(struct UvmChannelRetainer *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_UvmChannelRetainer_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_uvmchanrtnrInternalControlForward(struct UvmChannelRetainer *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_UvmChannelRetainer_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_uvmchanrtnrUnmapFrom(struct UvmChannelRetainer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_uvmchanrtnrControl_Epilogue(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_uvmchanrtnrControlLookup(struct UvmChannelRetainer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset), pParams, ppEntry); +} + +static NvHandle __nvoc_thunk_GpuResource_uvmchanrtnrGetInternalObjectHandle(struct UvmChannelRetainer *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_UvmChannelRetainer_GpuResource.offset)); +} + static NV_STATUS __nvoc_thunk_GpuResource_uvmchanrtnrControl(struct UvmChannelRetainer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_UvmChannelRetainer_GpuResource.offset), pCallContext, pParams); } @@ -113,68 +161,28 @@ static NV_STATUS __nvoc_thunk_RmResource_uvmchanrtnrGetMemoryMappingDescriptor(s return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_UvmChannelRetainer_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_GpuResource_uvmchanrtnrGetMapAddrSpace(struct UvmChannelRetainer *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_UvmChannelRetainer_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvHandle __nvoc_thunk_GpuResource_uvmchanrtnrGetInternalObjectHandle(struct UvmChannelRetainer *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_UvmChannelRetainer_GpuResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_uvmchanrtnrControlFilter(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_uvmchanrtnrAddAdditionalDependants(struct RsClient *pClient, struct UvmChannelRetainer *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_uvmchanrtnrGetRefCount(struct UvmChannelRetainer *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RmResource_uvmchanrtnrCheckMemInterUnmap(struct UvmChannelRetainer *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_UvmChannelRetainer_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_uvmchanrtnrMapTo(struct UvmChannelRetainer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_uvmchanrtnrControl_Prologue(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_GpuResource_uvmchanrtnrGetRegBaseOffsetAndSize(struct UvmChannelRetainer *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_UvmChannelRetainer_GpuResource.offset), pGpu, pOffset, pSize); +static NV_STATUS __nvoc_thunk_RmResource_uvmchanrtnrControlSerialization_Prologue(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_uvmchanrtnrCanCopy(struct UvmChannelRetainer *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_uvmchanrtnrInternalControlForward(struct UvmChannelRetainer *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_UvmChannelRetainer_GpuResource.offset), command, pParams, size); -} - static void __nvoc_thunk_RsResource_uvmchanrtnrPreDestruct(struct UvmChannelRetainer *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_uvmchanrtnrUnmapFrom(struct UvmChannelRetainer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_uvmchanrtnrIsDuplicate(struct UvmChannelRetainer *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset), hMemory, pDuplicate); } -static void __nvoc_thunk_RmResource_uvmchanrtnrControl_Epilogue(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_uvmchanrtnrControlLookup(struct UvmChannelRetainer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_uvmchanrtnrControlSerialization_Epilogue(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_uvmchanrtnrMap(struct UvmChannelRetainer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -236,6 +244,30 @@ static void __nvoc_init_funcTable_UvmChannelRetainer_1(UvmChannelRetainer *pThis pThis->__uvmchanrtnrShareCallback__ = &__nvoc_thunk_GpuResource_uvmchanrtnrShareCallback; + pThis->__uvmchanrtnrCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_uvmchanrtnrCheckMemInterUnmap; + + pThis->__uvmchanrtnrMapTo__ = &__nvoc_thunk_RsResource_uvmchanrtnrMapTo; + + pThis->__uvmchanrtnrGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_uvmchanrtnrGetMapAddrSpace; + + pThis->__uvmchanrtnrGetRefCount__ = &__nvoc_thunk_RsResource_uvmchanrtnrGetRefCount; + + pThis->__uvmchanrtnrAddAdditionalDependants__ = &__nvoc_thunk_RsResource_uvmchanrtnrAddAdditionalDependants; + + pThis->__uvmchanrtnrControl_Prologue__ = &__nvoc_thunk_RmResource_uvmchanrtnrControl_Prologue; + + pThis->__uvmchanrtnrGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_uvmchanrtnrGetRegBaseOffsetAndSize; + + pThis->__uvmchanrtnrInternalControlForward__ = &__nvoc_thunk_GpuResource_uvmchanrtnrInternalControlForward; + + pThis->__uvmchanrtnrUnmapFrom__ = &__nvoc_thunk_RsResource_uvmchanrtnrUnmapFrom; + + pThis->__uvmchanrtnrControl_Epilogue__ = &__nvoc_thunk_RmResource_uvmchanrtnrControl_Epilogue; + + pThis->__uvmchanrtnrControlLookup__ = &__nvoc_thunk_RsResource_uvmchanrtnrControlLookup; + + pThis->__uvmchanrtnrGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_uvmchanrtnrGetInternalObjectHandle; + pThis->__uvmchanrtnrControl__ = &__nvoc_thunk_GpuResource_uvmchanrtnrControl; pThis->__uvmchanrtnrUnmap__ = &__nvoc_thunk_GpuResource_uvmchanrtnrUnmap; @@ -244,37 +276,17 @@ static void __nvoc_init_funcTable_UvmChannelRetainer_1(UvmChannelRetainer *pThis pThis->__uvmchanrtnrGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_uvmchanrtnrGetMemoryMappingDescriptor; - pThis->__uvmchanrtnrGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_uvmchanrtnrGetMapAddrSpace; - - pThis->__uvmchanrtnrGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_uvmchanrtnrGetInternalObjectHandle; - pThis->__uvmchanrtnrControlFilter__ = &__nvoc_thunk_RsResource_uvmchanrtnrControlFilter; - pThis->__uvmchanrtnrAddAdditionalDependants__ = &__nvoc_thunk_RsResource_uvmchanrtnrAddAdditionalDependants; - - pThis->__uvmchanrtnrGetRefCount__ = &__nvoc_thunk_RsResource_uvmchanrtnrGetRefCount; - - pThis->__uvmchanrtnrCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_uvmchanrtnrCheckMemInterUnmap; - - pThis->__uvmchanrtnrMapTo__ = &__nvoc_thunk_RsResource_uvmchanrtnrMapTo; - - pThis->__uvmchanrtnrControl_Prologue__ = &__nvoc_thunk_RmResource_uvmchanrtnrControl_Prologue; - - pThis->__uvmchanrtnrGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_uvmchanrtnrGetRegBaseOffsetAndSize; + pThis->__uvmchanrtnrControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_uvmchanrtnrControlSerialization_Prologue; pThis->__uvmchanrtnrCanCopy__ = &__nvoc_thunk_RsResource_uvmchanrtnrCanCopy; - pThis->__uvmchanrtnrInternalControlForward__ = &__nvoc_thunk_GpuResource_uvmchanrtnrInternalControlForward; - pThis->__uvmchanrtnrPreDestruct__ = &__nvoc_thunk_RsResource_uvmchanrtnrPreDestruct; - pThis->__uvmchanrtnrUnmapFrom__ = &__nvoc_thunk_RsResource_uvmchanrtnrUnmapFrom; - pThis->__uvmchanrtnrIsDuplicate__ = &__nvoc_thunk_RsResource_uvmchanrtnrIsDuplicate; - pThis->__uvmchanrtnrControl_Epilogue__ = &__nvoc_thunk_RmResource_uvmchanrtnrControl_Epilogue; - - pThis->__uvmchanrtnrControlLookup__ = &__nvoc_thunk_RsResource_uvmchanrtnrControlLookup; + pThis->__uvmchanrtnrControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_uvmchanrtnrControlSerialization_Epilogue; pThis->__uvmchanrtnrMap__ = &__nvoc_thunk_GpuResource_uvmchanrtnrMap; @@ -303,13 +315,16 @@ NV_STATUS __nvoc_objCreate_UvmChannelRetainer(UvmChannelRetainer **ppThis, Dynam UvmChannelRetainer *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(UvmChannelRetainer)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(UvmChannelRetainer), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(UvmChannelRetainer)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_UvmChannelRetainer); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -329,11 +344,17 @@ NV_STATUS __nvoc_objCreate_UvmChannelRetainer(UvmChannelRetainer **ppThis, Dynam if (status != NV_OK) goto __nvoc_objCreate_UvmChannelRetainer_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_UvmChannelRetainer_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(UvmChannelRetainer)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_uvm_channel_retainer_nvoc.h b/src/nvidia/generated/g_uvm_channel_retainer_nvoc.h index 413ec9ed5..7d1bb23e7 100644 --- a/src/nvidia/generated/g_uvm_channel_retainer_nvoc.h +++ b/src/nvidia/generated/g_uvm_channel_retainer_nvoc.h @@ -69,26 +69,28 @@ struct UvmChannelRetainer { struct GpuResource *__nvoc_pbase_GpuResource; struct UvmChannelRetainer *__nvoc_pbase_UvmChannelRetainer; NvBool (*__uvmchanrtnrShareCallback__)(struct UvmChannelRetainer *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__uvmchanrtnrCheckMemInterUnmap__)(struct UvmChannelRetainer *, NvBool); + NV_STATUS (*__uvmchanrtnrMapTo__)(struct UvmChannelRetainer *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__uvmchanrtnrGetMapAddrSpace__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__uvmchanrtnrGetRefCount__)(struct UvmChannelRetainer *); + void (*__uvmchanrtnrAddAdditionalDependants__)(struct RsClient *, struct UvmChannelRetainer *, RsResourceRef *); + NV_STATUS (*__uvmchanrtnrControl_Prologue__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__uvmchanrtnrGetRegBaseOffsetAndSize__)(struct UvmChannelRetainer *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__uvmchanrtnrInternalControlForward__)(struct UvmChannelRetainer *, NvU32, void *, NvU32); + NV_STATUS (*__uvmchanrtnrUnmapFrom__)(struct UvmChannelRetainer *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__uvmchanrtnrControl_Epilogue__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__uvmchanrtnrControlLookup__)(struct UvmChannelRetainer *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__uvmchanrtnrGetInternalObjectHandle__)(struct UvmChannelRetainer *); NV_STATUS (*__uvmchanrtnrControl__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__uvmchanrtnrUnmap__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__uvmchanrtnrGetMemInterMapParams__)(struct UvmChannelRetainer *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__uvmchanrtnrGetMemoryMappingDescriptor__)(struct UvmChannelRetainer *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__uvmchanrtnrGetMapAddrSpace__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__uvmchanrtnrGetInternalObjectHandle__)(struct UvmChannelRetainer *); NV_STATUS (*__uvmchanrtnrControlFilter__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__uvmchanrtnrAddAdditionalDependants__)(struct RsClient *, struct UvmChannelRetainer *, RsResourceRef *); - NvU32 (*__uvmchanrtnrGetRefCount__)(struct UvmChannelRetainer *); - NV_STATUS (*__uvmchanrtnrCheckMemInterUnmap__)(struct UvmChannelRetainer *, NvBool); - NV_STATUS (*__uvmchanrtnrMapTo__)(struct UvmChannelRetainer *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__uvmchanrtnrControl_Prologue__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__uvmchanrtnrGetRegBaseOffsetAndSize__)(struct UvmChannelRetainer *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__uvmchanrtnrControlSerialization_Prologue__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__uvmchanrtnrCanCopy__)(struct UvmChannelRetainer *); - NV_STATUS (*__uvmchanrtnrInternalControlForward__)(struct UvmChannelRetainer *, NvU32, void *, NvU32); void (*__uvmchanrtnrPreDestruct__)(struct UvmChannelRetainer *); - NV_STATUS (*__uvmchanrtnrUnmapFrom__)(struct UvmChannelRetainer *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__uvmchanrtnrIsDuplicate__)(struct UvmChannelRetainer *, NvHandle, NvBool *); - void (*__uvmchanrtnrControl_Epilogue__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__uvmchanrtnrControlLookup__)(struct UvmChannelRetainer *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__uvmchanrtnrControlSerialization_Epilogue__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__uvmchanrtnrMap__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__uvmchanrtnrAccessCallback__)(struct UvmChannelRetainer *, struct RsClient *, void *, RsAccessRight); MEMORY_DESCRIPTOR *pInstMemDesc; @@ -125,26 +127,28 @@ NV_STATUS __nvoc_objCreate_UvmChannelRetainer(UvmChannelRetainer**, Dynamic*, Nv __nvoc_objCreate_UvmChannelRetainer((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) #define uvmchanrtnrShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) uvmchanrtnrShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define uvmchanrtnrCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) uvmchanrtnrCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define uvmchanrtnrMapTo(pResource, pParams) uvmchanrtnrMapTo_DISPATCH(pResource, pParams) +#define uvmchanrtnrGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) uvmchanrtnrGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define uvmchanrtnrGetRefCount(pResource) uvmchanrtnrGetRefCount_DISPATCH(pResource) +#define uvmchanrtnrAddAdditionalDependants(pClient, pResource, pReference) uvmchanrtnrAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define uvmchanrtnrControl_Prologue(pResource, pCallContext, pParams) uvmchanrtnrControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define uvmchanrtnrGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) uvmchanrtnrGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define uvmchanrtnrInternalControlForward(pGpuResource, command, pParams, size) uvmchanrtnrInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define uvmchanrtnrUnmapFrom(pResource, pParams) uvmchanrtnrUnmapFrom_DISPATCH(pResource, pParams) +#define uvmchanrtnrControl_Epilogue(pResource, pCallContext, pParams) uvmchanrtnrControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define uvmchanrtnrControlLookup(pResource, pParams, ppEntry) uvmchanrtnrControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define uvmchanrtnrGetInternalObjectHandle(pGpuResource) uvmchanrtnrGetInternalObjectHandle_DISPATCH(pGpuResource) #define uvmchanrtnrControl(pGpuResource, pCallContext, pParams) uvmchanrtnrControl_DISPATCH(pGpuResource, pCallContext, pParams) #define uvmchanrtnrUnmap(pGpuResource, pCallContext, pCpuMapping) uvmchanrtnrUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define uvmchanrtnrGetMemInterMapParams(pRmResource, pParams) uvmchanrtnrGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define uvmchanrtnrGetMemoryMappingDescriptor(pRmResource, ppMemDesc) uvmchanrtnrGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define uvmchanrtnrGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) uvmchanrtnrGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define uvmchanrtnrGetInternalObjectHandle(pGpuResource) uvmchanrtnrGetInternalObjectHandle_DISPATCH(pGpuResource) #define uvmchanrtnrControlFilter(pResource, pCallContext, pParams) uvmchanrtnrControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define uvmchanrtnrAddAdditionalDependants(pClient, pResource, pReference) uvmchanrtnrAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define uvmchanrtnrGetRefCount(pResource) uvmchanrtnrGetRefCount_DISPATCH(pResource) -#define uvmchanrtnrCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) uvmchanrtnrCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define uvmchanrtnrMapTo(pResource, pParams) uvmchanrtnrMapTo_DISPATCH(pResource, pParams) -#define uvmchanrtnrControl_Prologue(pResource, pCallContext, pParams) uvmchanrtnrControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define uvmchanrtnrGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) uvmchanrtnrGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define uvmchanrtnrControlSerialization_Prologue(pResource, pCallContext, pParams) uvmchanrtnrControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define uvmchanrtnrCanCopy(pResource) uvmchanrtnrCanCopy_DISPATCH(pResource) -#define uvmchanrtnrInternalControlForward(pGpuResource, command, pParams, size) uvmchanrtnrInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define uvmchanrtnrPreDestruct(pResource) uvmchanrtnrPreDestruct_DISPATCH(pResource) -#define uvmchanrtnrUnmapFrom(pResource, pParams) uvmchanrtnrUnmapFrom_DISPATCH(pResource, pParams) #define uvmchanrtnrIsDuplicate(pResource, hMemory, pDuplicate) uvmchanrtnrIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) -#define uvmchanrtnrControl_Epilogue(pResource, pCallContext, pParams) uvmchanrtnrControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define uvmchanrtnrControlLookup(pResource, pParams, ppEntry) uvmchanrtnrControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define uvmchanrtnrControlSerialization_Epilogue(pResource, pCallContext, pParams) uvmchanrtnrControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define uvmchanrtnrMap(pGpuResource, pCallContext, pParams, pCpuMapping) uvmchanrtnrMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define uvmchanrtnrAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) uvmchanrtnrAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool uvmchanrtnrIsAllocationAllowed_IMPL(struct UvmChannelRetainer *pUvmChannelRetainer, CALL_CONTEXT *pCallContext, struct KernelChannel *pKernelChannel); @@ -165,6 +169,54 @@ static inline NvBool uvmchanrtnrShareCallback_DISPATCH(struct UvmChannelRetainer return pGpuResource->__uvmchanrtnrShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } +static inline NV_STATUS uvmchanrtnrCheckMemInterUnmap_DISPATCH(struct UvmChannelRetainer *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__uvmchanrtnrCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS uvmchanrtnrMapTo_DISPATCH(struct UvmChannelRetainer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__uvmchanrtnrMapTo__(pResource, pParams); +} + +static inline NV_STATUS uvmchanrtnrGetMapAddrSpace_DISPATCH(struct UvmChannelRetainer *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__uvmchanrtnrGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 uvmchanrtnrGetRefCount_DISPATCH(struct UvmChannelRetainer *pResource) { + return pResource->__uvmchanrtnrGetRefCount__(pResource); +} + +static inline void uvmchanrtnrAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct UvmChannelRetainer *pResource, RsResourceRef *pReference) { + pResource->__uvmchanrtnrAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS uvmchanrtnrControl_Prologue_DISPATCH(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__uvmchanrtnrControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS uvmchanrtnrGetRegBaseOffsetAndSize_DISPATCH(struct UvmChannelRetainer *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__uvmchanrtnrGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS uvmchanrtnrInternalControlForward_DISPATCH(struct UvmChannelRetainer *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__uvmchanrtnrInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS uvmchanrtnrUnmapFrom_DISPATCH(struct UvmChannelRetainer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__uvmchanrtnrUnmapFrom__(pResource, pParams); +} + +static inline void uvmchanrtnrControl_Epilogue_DISPATCH(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__uvmchanrtnrControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS uvmchanrtnrControlLookup_DISPATCH(struct UvmChannelRetainer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__uvmchanrtnrControlLookup__(pResource, pParams, ppEntry); +} + +static inline NvHandle uvmchanrtnrGetInternalObjectHandle_DISPATCH(struct UvmChannelRetainer *pGpuResource) { + return pGpuResource->__uvmchanrtnrGetInternalObjectHandle__(pGpuResource); +} + static inline NV_STATUS uvmchanrtnrControl_DISPATCH(struct UvmChannelRetainer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pGpuResource->__uvmchanrtnrControl__(pGpuResource, pCallContext, pParams); } @@ -181,68 +233,28 @@ static inline NV_STATUS uvmchanrtnrGetMemoryMappingDescriptor_DISPATCH(struct Uv return pRmResource->__uvmchanrtnrGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS uvmchanrtnrGetMapAddrSpace_DISPATCH(struct UvmChannelRetainer *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__uvmchanrtnrGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvHandle uvmchanrtnrGetInternalObjectHandle_DISPATCH(struct UvmChannelRetainer *pGpuResource) { - return pGpuResource->__uvmchanrtnrGetInternalObjectHandle__(pGpuResource); -} - static inline NV_STATUS uvmchanrtnrControlFilter_DISPATCH(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__uvmchanrtnrControlFilter__(pResource, pCallContext, pParams); } -static inline void uvmchanrtnrAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct UvmChannelRetainer *pResource, RsResourceRef *pReference) { - pResource->__uvmchanrtnrAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 uvmchanrtnrGetRefCount_DISPATCH(struct UvmChannelRetainer *pResource) { - return pResource->__uvmchanrtnrGetRefCount__(pResource); -} - -static inline NV_STATUS uvmchanrtnrCheckMemInterUnmap_DISPATCH(struct UvmChannelRetainer *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__uvmchanrtnrCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS uvmchanrtnrMapTo_DISPATCH(struct UvmChannelRetainer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__uvmchanrtnrMapTo__(pResource, pParams); -} - -static inline NV_STATUS uvmchanrtnrControl_Prologue_DISPATCH(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__uvmchanrtnrControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS uvmchanrtnrGetRegBaseOffsetAndSize_DISPATCH(struct UvmChannelRetainer *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__uvmchanrtnrGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +static inline NV_STATUS uvmchanrtnrControlSerialization_Prologue_DISPATCH(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__uvmchanrtnrControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool uvmchanrtnrCanCopy_DISPATCH(struct UvmChannelRetainer *pResource) { return pResource->__uvmchanrtnrCanCopy__(pResource); } -static inline NV_STATUS uvmchanrtnrInternalControlForward_DISPATCH(struct UvmChannelRetainer *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__uvmchanrtnrInternalControlForward__(pGpuResource, command, pParams, size); -} - static inline void uvmchanrtnrPreDestruct_DISPATCH(struct UvmChannelRetainer *pResource) { pResource->__uvmchanrtnrPreDestruct__(pResource); } -static inline NV_STATUS uvmchanrtnrUnmapFrom_DISPATCH(struct UvmChannelRetainer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__uvmchanrtnrUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS uvmchanrtnrIsDuplicate_DISPATCH(struct UvmChannelRetainer *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__uvmchanrtnrIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline void uvmchanrtnrControl_Epilogue_DISPATCH(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__uvmchanrtnrControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS uvmchanrtnrControlLookup_DISPATCH(struct UvmChannelRetainer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__uvmchanrtnrControlLookup__(pResource, pParams, ppEntry); +static inline void uvmchanrtnrControlSerialization_Epilogue_DISPATCH(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__uvmchanrtnrControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS uvmchanrtnrMap_DISPATCH(struct UvmChannelRetainer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_uvm_nvoc.c b/src/nvidia/generated/g_uvm_nvoc.c index 7e4960d79..46a889887 100644 --- a/src/nvidia/generated/g_uvm_nvoc.c +++ b/src/nvidia/generated/g_uvm_nvoc.c @@ -83,7 +83,7 @@ static NV_STATUS __nvoc_thunk_OBJUVM_engstateStateInitUnlocked(OBJGPU *pGpu, str return uvmStateInitUnlocked(pGpu, (struct OBJUVM *)(((unsigned char *)pUvm) - __nvoc_rtti_OBJUVM_OBJENGSTATE.offset)); } -static void __nvoc_thunk_OBJUVM_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *pUvm, IntrServiceRecord arg1[163]) { +static void __nvoc_thunk_OBJUVM_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *pUvm, IntrServiceRecord arg1[166]) { uvmRegisterIntrService(arg0, (struct OBJUVM *)(((unsigned char *)pUvm) - __nvoc_rtti_OBJUVM_IntrService.offset), arg1); } @@ -91,10 +91,6 @@ static NvU32 __nvoc_thunk_OBJUVM_intrservServiceInterrupt(OBJGPU *arg0, struct I return uvmServiceInterrupt(arg0, (struct OBJUVM *)(((unsigned char *)pUvm) - __nvoc_rtti_OBJUVM_IntrService.offset), arg1); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_uvmReconcileTunableState(POBJGPU pGpu, struct OBJUVM *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJUVM_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_uvmStateLoad(POBJGPU pGpu, struct OBJUVM *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJUVM_OBJENGSTATE.offset), arg0); } @@ -135,18 +131,6 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_uvmStatePreInitUnlocked(POBJGPU pGpu, return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJUVM_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_uvmGetTunableState(POBJGPU pGpu, struct OBJUVM *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJUVM_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_uvmCompareTunableState(POBJGPU pGpu, struct OBJUVM *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJUVM_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_uvmFreeTunableState(POBJGPU pGpu, struct OBJUVM *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJUVM_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_IntrService_uvmClearInterrupt(OBJGPU *pGpu, struct OBJUVM *pIntrService, IntrServiceClearInterruptArguments *pParams) { return intrservClearInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_OBJUVM_IntrService.offset), pParams); } @@ -155,14 +139,6 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_uvmStatePostLoad(POBJGPU pGpu, struct return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJUVM_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_uvmAllocTunableState(POBJGPU pGpu, struct OBJUVM *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJUVM_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_uvmSetTunableState(POBJGPU pGpu, struct OBJUVM *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJUVM_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_uvmConstructEngine(POBJGPU pGpu, struct OBJUVM *pEngstate, ENGDESCRIPTOR arg0) { return engstateConstructEngine(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJUVM_OBJENGSTATE.offset), arg0); } @@ -245,8 +221,6 @@ static void __nvoc_init_funcTable_OBJUVM_1(OBJUVM *pThis, RmHalspecOwner *pRmhal pThis->__nvoc_base_IntrService.__intrservServiceInterrupt__ = &__nvoc_thunk_OBJUVM_intrservServiceInterrupt; - pThis->__uvmReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_uvmReconcileTunableState; - pThis->__uvmStateLoad__ = &__nvoc_thunk_OBJENGSTATE_uvmStateLoad; pThis->__uvmStateUnload__ = &__nvoc_thunk_OBJENGSTATE_uvmStateUnload; @@ -267,20 +241,10 @@ static void __nvoc_init_funcTable_OBJUVM_1(OBJUVM *pThis, RmHalspecOwner *pRmhal pThis->__uvmStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_uvmStatePreInitUnlocked; - pThis->__uvmGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_uvmGetTunableState; - - pThis->__uvmCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_uvmCompareTunableState; - - pThis->__uvmFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_uvmFreeTunableState; - pThis->__uvmClearInterrupt__ = &__nvoc_thunk_IntrService_uvmClearInterrupt; pThis->__uvmStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_uvmStatePostLoad; - pThis->__uvmAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_uvmAllocTunableState; - - pThis->__uvmSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_uvmSetTunableState; - pThis->__uvmConstructEngine__ = &__nvoc_thunk_OBJENGSTATE_uvmConstructEngine; pThis->__uvmIsPresent__ = &__nvoc_thunk_OBJENGSTATE_uvmIsPresent; @@ -308,13 +272,16 @@ NV_STATUS __nvoc_objCreate_OBJUVM(OBJUVM **ppThis, Dynamic *pParent, NvU32 creat OBJUVM *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(OBJUVM)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJUVM), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJUVM)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJUVM); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -334,11 +301,17 @@ NV_STATUS __nvoc_objCreate_OBJUVM(OBJUVM **ppThis, Dynamic *pParent, NvU32 creat if (status != NV_OK) goto __nvoc_objCreate_OBJUVM_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJUVM_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJUVM)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_uvm_nvoc.h b/src/nvidia/generated/g_uvm_nvoc.h index 6134e2738..14fef58fc 100644 --- a/src/nvidia/generated/g_uvm_nvoc.h +++ b/src/nvidia/generated/g_uvm_nvoc.h @@ -105,7 +105,6 @@ struct OBJUVM { NV_STATUS (*__uvmStateInitUnlocked__)(OBJGPU *, struct OBJUVM *); void (*__uvmRegisterIntrService__)(OBJGPU *, struct OBJUVM *, IntrServiceRecord *); NvU32 (*__uvmServiceInterrupt__)(OBJGPU *, struct OBJUVM *, IntrServiceServiceInterruptArguments *); - NV_STATUS (*__uvmReconcileTunableState__)(POBJGPU, struct OBJUVM *, void *); NV_STATUS (*__uvmStateLoad__)(POBJGPU, struct OBJUVM *, NvU32); NV_STATUS (*__uvmStateUnload__)(POBJGPU, struct OBJUVM *, NvU32); NV_STATUS (*__uvmServiceNotificationInterrupt__)(OBJGPU *, struct OBJUVM *, IntrServiceServiceNotificationInterruptArguments *); @@ -116,13 +115,8 @@ struct OBJUVM { void (*__uvmInitMissing__)(POBJGPU, struct OBJUVM *); NV_STATUS (*__uvmStatePreInitLocked__)(POBJGPU, struct OBJUVM *); NV_STATUS (*__uvmStatePreInitUnlocked__)(POBJGPU, struct OBJUVM *); - NV_STATUS (*__uvmGetTunableState__)(POBJGPU, struct OBJUVM *, void *); - NV_STATUS (*__uvmCompareTunableState__)(POBJGPU, struct OBJUVM *, void *, void *); - void (*__uvmFreeTunableState__)(POBJGPU, struct OBJUVM *, void *); NvBool (*__uvmClearInterrupt__)(OBJGPU *, struct OBJUVM *, IntrServiceClearInterruptArguments *); NV_STATUS (*__uvmStatePostLoad__)(POBJGPU, struct OBJUVM *, NvU32); - NV_STATUS (*__uvmAllocTunableState__)(POBJGPU, struct OBJUVM *, void **); - NV_STATUS (*__uvmSetTunableState__)(POBJGPU, struct OBJUVM *, void *); NV_STATUS (*__uvmConstructEngine__)(POBJGPU, struct OBJUVM *, ENGDESCRIPTOR); NvBool (*__uvmIsPresent__)(POBJGPU, struct OBJUVM *); struct ACCESS_CNTR_BUFFER accessCntrBuffer; @@ -165,7 +159,6 @@ NV_STATUS __nvoc_objCreate_OBJUVM(OBJUVM**, Dynamic*, NvU32); #define uvmStateInitUnlocked(pGpu, pUvm) uvmStateInitUnlocked_DISPATCH(pGpu, pUvm) #define uvmRegisterIntrService(arg0, pUvm, arg1) uvmRegisterIntrService_DISPATCH(arg0, pUvm, arg1) #define uvmServiceInterrupt(arg0, pUvm, arg1) uvmServiceInterrupt_DISPATCH(arg0, pUvm, arg1) -#define uvmReconcileTunableState(pGpu, pEngstate, pTunableState) uvmReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define uvmStateLoad(pGpu, pEngstate, arg0) uvmStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define uvmStateUnload(pGpu, pEngstate, arg0) uvmStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define uvmServiceNotificationInterrupt(pGpu, pIntrService, pParams) uvmServiceNotificationInterrupt_DISPATCH(pGpu, pIntrService, pParams) @@ -176,13 +169,8 @@ NV_STATUS __nvoc_objCreate_OBJUVM(OBJUVM**, Dynamic*, NvU32); #define uvmInitMissing(pGpu, pEngstate) uvmInitMissing_DISPATCH(pGpu, pEngstate) #define uvmStatePreInitLocked(pGpu, pEngstate) uvmStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define uvmStatePreInitUnlocked(pGpu, pEngstate) uvmStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define uvmGetTunableState(pGpu, pEngstate, pTunableState) uvmGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define uvmCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) uvmCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define uvmFreeTunableState(pGpu, pEngstate, pTunableState) uvmFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define uvmClearInterrupt(pGpu, pIntrService, pParams) uvmClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define uvmStatePostLoad(pGpu, pEngstate, arg0) uvmStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) -#define uvmAllocTunableState(pGpu, pEngstate, ppTunableState) uvmAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define uvmSetTunableState(pGpu, pEngstate, pTunableState) uvmSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define uvmConstructEngine(pGpu, pEngstate, arg0) uvmConstructEngine_DISPATCH(pGpu, pEngstate, arg0) #define uvmIsPresent(pGpu, pEngstate) uvmIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS uvmInitializeAccessCntrBuffer_IMPL(OBJGPU *pGpu, struct OBJUVM *pUvm); @@ -577,9 +565,9 @@ static inline NV_STATUS uvmStateInitUnlocked_DISPATCH(OBJGPU *pGpu, struct OBJUV return pUvm->__uvmStateInitUnlocked__(pGpu, pUvm); } -void uvmRegisterIntrService_IMPL(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceRecord arg1[163]); +void uvmRegisterIntrService_IMPL(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceRecord arg1[166]); -static inline void uvmRegisterIntrService_DISPATCH(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceRecord arg1[163]) { +static inline void uvmRegisterIntrService_DISPATCH(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceRecord arg1[166]) { pUvm->__uvmRegisterIntrService__(arg0, pUvm, arg1); } @@ -589,10 +577,6 @@ static inline NvU32 uvmServiceInterrupt_DISPATCH(OBJGPU *arg0, struct OBJUVM *pU return pUvm->__uvmServiceInterrupt__(arg0, pUvm, arg1); } -static inline NV_STATUS uvmReconcileTunableState_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate, void *pTunableState) { - return pEngstate->__uvmReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS uvmStateLoad_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate, NvU32 arg0) { return pEngstate->__uvmStateLoad__(pGpu, pEngstate, arg0); } @@ -633,18 +617,6 @@ static inline NV_STATUS uvmStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct OB return pEngstate->__uvmStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS uvmGetTunableState_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate, void *pTunableState) { - return pEngstate->__uvmGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS uvmCompareTunableState_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__uvmCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void uvmFreeTunableState_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate, void *pTunableState) { - pEngstate->__uvmFreeTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool uvmClearInterrupt_DISPATCH(OBJGPU *pGpu, struct OBJUVM *pIntrService, IntrServiceClearInterruptArguments *pParams) { return pIntrService->__uvmClearInterrupt__(pGpu, pIntrService, pParams); } @@ -653,14 +625,6 @@ static inline NV_STATUS uvmStatePostLoad_DISPATCH(POBJGPU pGpu, struct OBJUVM *p return pEngstate->__uvmStatePostLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS uvmAllocTunableState_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate, void **ppTunableState) { - return pEngstate->__uvmAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS uvmSetTunableState_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate, void *pTunableState) { - return pEngstate->__uvmSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS uvmConstructEngine_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate, ENGDESCRIPTOR arg0) { return pEngstate->__uvmConstructEngine__(pGpu, pEngstate, arg0); } diff --git a/src/nvidia/generated/g_uvm_sw_nvoc.c b/src/nvidia/generated/g_uvm_sw_nvoc.c index 8e2200a1a..465f13f11 100644 --- a/src/nvidia/generated/g_uvm_sw_nvoc.c +++ b/src/nvidia/generated/g_uvm_sw_nvoc.c @@ -120,7 +120,7 @@ const struct NVOC_CLASS_DEF __nvoc_class_def_UvmSwObject = /*pExportInfo=*/ &__nvoc_export_info_UvmSwObject }; -static NV_STATUS __nvoc_thunk_UvmSwObject_chandesGetSwMethods(struct ChannelDescendant *pUvmSw, METHOD **ppMethods, NvU32 *pNumMethods) { +static NV_STATUS __nvoc_thunk_UvmSwObject_chandesGetSwMethods(struct ChannelDescendant *pUvmSw, const METHOD **ppMethods, NvU32 *pNumMethods) { return uvmswGetSwMethods((struct UvmSwObject *)(((unsigned char *)pUvmSw) - __nvoc_rtti_UvmSwObject_ChannelDescendant.offset), ppMethods, pNumMethods); } @@ -212,6 +212,10 @@ static NV_STATUS __nvoc_thunk_Notifier_uvmswUnregisterEvent(struct UvmSwObject * return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_UvmSwObject_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_uvmswControlSerialization_Prologue(struct UvmSwObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmSwObject_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_uvmswCanCopy(struct UvmSwObject *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmSwObject_RsResource.offset)); } @@ -224,6 +228,10 @@ static NV_STATUS __nvoc_thunk_RsResource_uvmswIsDuplicate(struct UvmSwObject *pR return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmSwObject_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_uvmswControlSerialization_Epilogue(struct UvmSwObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmSwObject_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_uvmswGetNotificationListPtr(struct UvmSwObject *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_UvmSwObject_Notifier.offset)); } @@ -341,12 +349,16 @@ static void __nvoc_init_funcTable_UvmSwObject_1(UvmSwObject *pThis, RmHalspecOwn pThis->__uvmswUnregisterEvent__ = &__nvoc_thunk_Notifier_uvmswUnregisterEvent; + pThis->__uvmswControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_uvmswControlSerialization_Prologue; + pThis->__uvmswCanCopy__ = &__nvoc_thunk_RsResource_uvmswCanCopy; pThis->__uvmswPreDestruct__ = &__nvoc_thunk_RsResource_uvmswPreDestruct; pThis->__uvmswIsDuplicate__ = &__nvoc_thunk_RsResource_uvmswIsDuplicate; + pThis->__uvmswControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_uvmswControlSerialization_Epilogue; + pThis->__uvmswGetNotificationListPtr__ = &__nvoc_thunk_Notifier_uvmswGetNotificationListPtr; pThis->__uvmswGetNotificationShare__ = &__nvoc_thunk_Notifier_uvmswGetNotificationShare; @@ -381,13 +393,16 @@ NV_STATUS __nvoc_objCreate_UvmSwObject(UvmSwObject **ppThis, Dynamic *pParent, N UvmSwObject *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(UvmSwObject)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(UvmSwObject), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(UvmSwObject)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_UvmSwObject); + pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -407,11 +422,17 @@ NV_STATUS __nvoc_objCreate_UvmSwObject(UvmSwObject **ppThis, Dynamic *pParent, N if (status != NV_OK) goto __nvoc_objCreate_UvmSwObject_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_UvmSwObject_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(UvmSwObject)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_uvm_sw_nvoc.h b/src/nvidia/generated/g_uvm_sw_nvoc.h index d4c647737..21791d752 100644 --- a/src/nvidia/generated/g_uvm_sw_nvoc.h +++ b/src/nvidia/generated/g_uvm_sw_nvoc.h @@ -57,7 +57,7 @@ struct UvmSwObject { struct Notifier *__nvoc_pbase_Notifier; struct ChannelDescendant *__nvoc_pbase_ChannelDescendant; struct UvmSwObject *__nvoc_pbase_UvmSwObject; - NV_STATUS (*__uvmswGetSwMethods__)(struct UvmSwObject *, METHOD **, NvU32 *); + NV_STATUS (*__uvmswGetSwMethods__)(struct UvmSwObject *, const METHOD **, NvU32 *); NV_STATUS (*__uvmswCheckMemInterUnmap__)(struct UvmSwObject *, NvBool); NvBool (*__uvmswShareCallback__)(struct UvmSwObject *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NvBool (*__uvmswAccessCallback__)(struct UvmSwObject *, struct RsClient *, void *, RsAccessRight); @@ -80,9 +80,11 @@ struct UvmSwObject { NvBool (*__uvmswIsSwMethodStalling__)(struct UvmSwObject *, NvU32); NV_STATUS (*__uvmswControlFilter__)(struct UvmSwObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__uvmswUnregisterEvent__)(struct UvmSwObject *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__uvmswControlSerialization_Prologue__)(struct UvmSwObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__uvmswCanCopy__)(struct UvmSwObject *); void (*__uvmswPreDestruct__)(struct UvmSwObject *); NV_STATUS (*__uvmswIsDuplicate__)(struct UvmSwObject *, NvHandle, NvBool *); + void (*__uvmswControlSerialization_Epilogue__)(struct UvmSwObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__uvmswGetNotificationListPtr__)(struct UvmSwObject *); struct NotifShare *(*__uvmswGetNotificationShare__)(struct UvmSwObject *); NV_STATUS (*__uvmswMap__)(struct UvmSwObject *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -146,18 +148,20 @@ NV_STATUS __nvoc_objCreate_UvmSwObject(UvmSwObject**, Dynamic*, NvU32, struct CA #define uvmswIsSwMethodStalling(pChannelDescendant, hHandle) uvmswIsSwMethodStalling_DISPATCH(pChannelDescendant, hHandle) #define uvmswControlFilter(pResource, pCallContext, pParams) uvmswControlFilter_DISPATCH(pResource, pCallContext, pParams) #define uvmswUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) uvmswUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define uvmswControlSerialization_Prologue(pResource, pCallContext, pParams) uvmswControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define uvmswCanCopy(pResource) uvmswCanCopy_DISPATCH(pResource) #define uvmswPreDestruct(pResource) uvmswPreDestruct_DISPATCH(pResource) #define uvmswIsDuplicate(pResource, hMemory, pDuplicate) uvmswIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define uvmswControlSerialization_Epilogue(pResource, pCallContext, pParams) uvmswControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define uvmswGetNotificationListPtr(pNotifier) uvmswGetNotificationListPtr_DISPATCH(pNotifier) #define uvmswGetNotificationShare(pNotifier) uvmswGetNotificationShare_DISPATCH(pNotifier) #define uvmswMap(pGpuResource, pCallContext, pParams, pCpuMapping) uvmswMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define uvmswGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) uvmswGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) -static inline NV_STATUS uvmswGetSwMethods_56cd7a(struct UvmSwObject *pUvmSw, METHOD **ppMethods, NvU32 *pNumMethods) { +static inline NV_STATUS uvmswGetSwMethods_56cd7a(struct UvmSwObject *pUvmSw, const METHOD **ppMethods, NvU32 *pNumMethods) { return NV_OK; } -static inline NV_STATUS uvmswGetSwMethods_DISPATCH(struct UvmSwObject *pUvmSw, METHOD **ppMethods, NvU32 *pNumMethods) { +static inline NV_STATUS uvmswGetSwMethods_DISPATCH(struct UvmSwObject *pUvmSw, const METHOD **ppMethods, NvU32 *pNumMethods) { return pUvmSw->__uvmswGetSwMethods__(pUvmSw, ppMethods, pNumMethods); } @@ -249,6 +253,10 @@ static inline NV_STATUS uvmswUnregisterEvent_DISPATCH(struct UvmSwObject *pNotif return pNotifier->__uvmswUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS uvmswControlSerialization_Prologue_DISPATCH(struct UvmSwObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__uvmswControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool uvmswCanCopy_DISPATCH(struct UvmSwObject *pResource) { return pResource->__uvmswCanCopy__(pResource); } @@ -261,6 +269,10 @@ static inline NV_STATUS uvmswIsDuplicate_DISPATCH(struct UvmSwObject *pResource, return pResource->__uvmswIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void uvmswControlSerialization_Epilogue_DISPATCH(struct UvmSwObject *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__uvmswControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *uvmswGetNotificationListPtr_DISPATCH(struct UvmSwObject *pNotifier) { return pNotifier->__uvmswGetNotificationListPtr__(pNotifier); } diff --git a/src/nvidia/generated/g_vaspace_api_nvoc.c b/src/nvidia/generated/g_vaspace_api_nvoc.c index 27369a163..7b4211c95 100644 --- a/src/nvidia/generated/g_vaspace_api_nvoc.c +++ b/src/nvidia/generated/g_vaspace_api_nvoc.c @@ -101,6 +101,54 @@ static NvBool __nvoc_thunk_GpuResource_vaspaceapiShareCallback(struct VaSpaceApi return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VaSpaceApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } +static NV_STATUS __nvoc_thunk_RmResource_vaspaceapiCheckMemInterUnmap(struct VaSpaceApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VaSpaceApi_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_vaspaceapiMapTo(struct VaSpaceApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vaspaceapiGetMapAddrSpace(struct VaSpaceApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VaSpaceApi_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_vaspaceapiGetRefCount(struct VaSpaceApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_vaspaceapiAddAdditionalDependants(struct RsClient *pClient, struct VaSpaceApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_vaspaceapiControl_Prologue(struct VaSpaceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vaspaceapiGetRegBaseOffsetAndSize(struct VaSpaceApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VaSpaceApi_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vaspaceapiInternalControlForward(struct VaSpaceApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VaSpaceApi_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_vaspaceapiUnmapFrom(struct VaSpaceApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_vaspaceapiControl_Epilogue(struct VaSpaceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_vaspaceapiControlLookup(struct VaSpaceApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset), pParams, ppEntry); +} + +static NvHandle __nvoc_thunk_GpuResource_vaspaceapiGetInternalObjectHandle(struct VaSpaceApi *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VaSpaceApi_GpuResource.offset)); +} + static NV_STATUS __nvoc_thunk_GpuResource_vaspaceapiControl(struct VaSpaceApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VaSpaceApi_GpuResource.offset), pCallContext, pParams); } @@ -117,64 +165,24 @@ static NV_STATUS __nvoc_thunk_RmResource_vaspaceapiGetMemoryMappingDescriptor(st return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VaSpaceApi_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_GpuResource_vaspaceapiGetMapAddrSpace(struct VaSpaceApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VaSpaceApi_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvHandle __nvoc_thunk_GpuResource_vaspaceapiGetInternalObjectHandle(struct VaSpaceApi *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VaSpaceApi_GpuResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_vaspaceapiControlFilter(struct VaSpaceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_vaspaceapiAddAdditionalDependants(struct RsClient *pClient, struct VaSpaceApi *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_vaspaceapiGetRefCount(struct VaSpaceApi *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RmResource_vaspaceapiCheckMemInterUnmap(struct VaSpaceApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VaSpaceApi_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_vaspaceapiMapTo(struct VaSpaceApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_vaspaceapiControl_Prologue(struct VaSpaceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_GpuResource_vaspaceapiGetRegBaseOffsetAndSize(struct VaSpaceApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VaSpaceApi_GpuResource.offset), pGpu, pOffset, pSize); -} - -static NV_STATUS __nvoc_thunk_GpuResource_vaspaceapiInternalControlForward(struct VaSpaceApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VaSpaceApi_GpuResource.offset), command, pParams, size); +static NV_STATUS __nvoc_thunk_RmResource_vaspaceapiControlSerialization_Prologue(struct VaSpaceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RmResource.offset), pCallContext, pParams); } static void __nvoc_thunk_RsResource_vaspaceapiPreDestruct(struct VaSpaceApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_vaspaceapiUnmapFrom(struct VaSpaceApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_vaspaceapiIsDuplicate(struct VaSpaceApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset), hMemory, pDuplicate); } -static void __nvoc_thunk_RmResource_vaspaceapiControl_Epilogue(struct VaSpaceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_vaspaceapiControlLookup(struct VaSpaceApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_vaspaceapiControlSerialization_Epilogue(struct VaSpaceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_vaspaceapiMap(struct VaSpaceApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -334,6 +342,30 @@ static void __nvoc_init_funcTable_VaSpaceApi_1(VaSpaceApi *pThis) { pThis->__vaspaceapiShareCallback__ = &__nvoc_thunk_GpuResource_vaspaceapiShareCallback; + pThis->__vaspaceapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_vaspaceapiCheckMemInterUnmap; + + pThis->__vaspaceapiMapTo__ = &__nvoc_thunk_RsResource_vaspaceapiMapTo; + + pThis->__vaspaceapiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_vaspaceapiGetMapAddrSpace; + + pThis->__vaspaceapiGetRefCount__ = &__nvoc_thunk_RsResource_vaspaceapiGetRefCount; + + pThis->__vaspaceapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_vaspaceapiAddAdditionalDependants; + + pThis->__vaspaceapiControl_Prologue__ = &__nvoc_thunk_RmResource_vaspaceapiControl_Prologue; + + pThis->__vaspaceapiGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_vaspaceapiGetRegBaseOffsetAndSize; + + pThis->__vaspaceapiInternalControlForward__ = &__nvoc_thunk_GpuResource_vaspaceapiInternalControlForward; + + pThis->__vaspaceapiUnmapFrom__ = &__nvoc_thunk_RsResource_vaspaceapiUnmapFrom; + + pThis->__vaspaceapiControl_Epilogue__ = &__nvoc_thunk_RmResource_vaspaceapiControl_Epilogue; + + pThis->__vaspaceapiControlLookup__ = &__nvoc_thunk_RsResource_vaspaceapiControlLookup; + + pThis->__vaspaceapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_vaspaceapiGetInternalObjectHandle; + pThis->__vaspaceapiControl__ = &__nvoc_thunk_GpuResource_vaspaceapiControl; pThis->__vaspaceapiUnmap__ = &__nvoc_thunk_GpuResource_vaspaceapiUnmap; @@ -342,35 +374,15 @@ static void __nvoc_init_funcTable_VaSpaceApi_1(VaSpaceApi *pThis) { pThis->__vaspaceapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_vaspaceapiGetMemoryMappingDescriptor; - pThis->__vaspaceapiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_vaspaceapiGetMapAddrSpace; - - pThis->__vaspaceapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_vaspaceapiGetInternalObjectHandle; - pThis->__vaspaceapiControlFilter__ = &__nvoc_thunk_RsResource_vaspaceapiControlFilter; - pThis->__vaspaceapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_vaspaceapiAddAdditionalDependants; - - pThis->__vaspaceapiGetRefCount__ = &__nvoc_thunk_RsResource_vaspaceapiGetRefCount; - - pThis->__vaspaceapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_vaspaceapiCheckMemInterUnmap; - - pThis->__vaspaceapiMapTo__ = &__nvoc_thunk_RsResource_vaspaceapiMapTo; - - pThis->__vaspaceapiControl_Prologue__ = &__nvoc_thunk_RmResource_vaspaceapiControl_Prologue; - - pThis->__vaspaceapiGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_vaspaceapiGetRegBaseOffsetAndSize; - - pThis->__vaspaceapiInternalControlForward__ = &__nvoc_thunk_GpuResource_vaspaceapiInternalControlForward; + pThis->__vaspaceapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_vaspaceapiControlSerialization_Prologue; pThis->__vaspaceapiPreDestruct__ = &__nvoc_thunk_RsResource_vaspaceapiPreDestruct; - pThis->__vaspaceapiUnmapFrom__ = &__nvoc_thunk_RsResource_vaspaceapiUnmapFrom; - pThis->__vaspaceapiIsDuplicate__ = &__nvoc_thunk_RsResource_vaspaceapiIsDuplicate; - pThis->__vaspaceapiControl_Epilogue__ = &__nvoc_thunk_RmResource_vaspaceapiControl_Epilogue; - - pThis->__vaspaceapiControlLookup__ = &__nvoc_thunk_RsResource_vaspaceapiControlLookup; + pThis->__vaspaceapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_vaspaceapiControlSerialization_Epilogue; pThis->__vaspaceapiMap__ = &__nvoc_thunk_GpuResource_vaspaceapiMap; @@ -398,13 +410,16 @@ NV_STATUS __nvoc_objCreate_VaSpaceApi(VaSpaceApi **ppThis, Dynamic *pParent, NvU Object *pParentObj; VaSpaceApi *pThis; - pThis = portMemAllocNonPaged(sizeof(VaSpaceApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(VaSpaceApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(VaSpaceApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_VaSpaceApi); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -420,11 +435,17 @@ NV_STATUS __nvoc_objCreate_VaSpaceApi(VaSpaceApi **ppThis, Dynamic *pParent, NvU if (status != NV_OK) goto __nvoc_objCreate_VaSpaceApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_VaSpaceApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(VaSpaceApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_vaspace_api_nvoc.h b/src/nvidia/generated/g_vaspace_api_nvoc.h index caa2af86b..743eff4fa 100644 --- a/src/nvidia/generated/g_vaspace_api_nvoc.h +++ b/src/nvidia/generated/g_vaspace_api_nvoc.h @@ -74,25 +74,27 @@ struct VaSpaceApi { NV_STATUS (*__vaspaceapiCtrlCmdVaspaceReleaseEntries__)(struct VaSpaceApi *, NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS *); NV_STATUS (*__vaspaceapiCtrlCmdVaspaceCopyServerReservedPdes__)(struct VaSpaceApi *, NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS *); NvBool (*__vaspaceapiShareCallback__)(struct VaSpaceApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__vaspaceapiCheckMemInterUnmap__)(struct VaSpaceApi *, NvBool); + NV_STATUS (*__vaspaceapiMapTo__)(struct VaSpaceApi *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__vaspaceapiGetMapAddrSpace__)(struct VaSpaceApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__vaspaceapiGetRefCount__)(struct VaSpaceApi *); + void (*__vaspaceapiAddAdditionalDependants__)(struct RsClient *, struct VaSpaceApi *, RsResourceRef *); + NV_STATUS (*__vaspaceapiControl_Prologue__)(struct VaSpaceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vaspaceapiGetRegBaseOffsetAndSize__)(struct VaSpaceApi *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__vaspaceapiInternalControlForward__)(struct VaSpaceApi *, NvU32, void *, NvU32); + NV_STATUS (*__vaspaceapiUnmapFrom__)(struct VaSpaceApi *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__vaspaceapiControl_Epilogue__)(struct VaSpaceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vaspaceapiControlLookup__)(struct VaSpaceApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__vaspaceapiGetInternalObjectHandle__)(struct VaSpaceApi *); NV_STATUS (*__vaspaceapiControl__)(struct VaSpaceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vaspaceapiUnmap__)(struct VaSpaceApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__vaspaceapiGetMemInterMapParams__)(struct VaSpaceApi *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__vaspaceapiGetMemoryMappingDescriptor__)(struct VaSpaceApi *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__vaspaceapiGetMapAddrSpace__)(struct VaSpaceApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__vaspaceapiGetInternalObjectHandle__)(struct VaSpaceApi *); NV_STATUS (*__vaspaceapiControlFilter__)(struct VaSpaceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__vaspaceapiAddAdditionalDependants__)(struct RsClient *, struct VaSpaceApi *, RsResourceRef *); - NvU32 (*__vaspaceapiGetRefCount__)(struct VaSpaceApi *); - NV_STATUS (*__vaspaceapiCheckMemInterUnmap__)(struct VaSpaceApi *, NvBool); - NV_STATUS (*__vaspaceapiMapTo__)(struct VaSpaceApi *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__vaspaceapiControl_Prologue__)(struct VaSpaceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__vaspaceapiGetRegBaseOffsetAndSize__)(struct VaSpaceApi *, struct OBJGPU *, NvU32 *, NvU32 *); - NV_STATUS (*__vaspaceapiInternalControlForward__)(struct VaSpaceApi *, NvU32, void *, NvU32); + NV_STATUS (*__vaspaceapiControlSerialization_Prologue__)(struct VaSpaceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__vaspaceapiPreDestruct__)(struct VaSpaceApi *); - NV_STATUS (*__vaspaceapiUnmapFrom__)(struct VaSpaceApi *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__vaspaceapiIsDuplicate__)(struct VaSpaceApi *, NvHandle, NvBool *); - void (*__vaspaceapiControl_Epilogue__)(struct VaSpaceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__vaspaceapiControlLookup__)(struct VaSpaceApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__vaspaceapiControlSerialization_Epilogue__)(struct VaSpaceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vaspaceapiMap__)(struct VaSpaceApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__vaspaceapiAccessCallback__)(struct VaSpaceApi *, struct RsClient *, void *, RsAccessRight); struct OBJVASPACE *pVASpace; @@ -134,25 +136,27 @@ NV_STATUS __nvoc_objCreate_VaSpaceApi(VaSpaceApi**, Dynamic*, NvU32, struct CALL #define vaspaceapiCtrlCmdVaspaceReleaseEntries(pVaspaceApi, pReleaseEntriesParams) vaspaceapiCtrlCmdVaspaceReleaseEntries_DISPATCH(pVaspaceApi, pReleaseEntriesParams) #define vaspaceapiCtrlCmdVaspaceCopyServerReservedPdes(pVaspaceApi, pCopyServerReservedPdesParams) vaspaceapiCtrlCmdVaspaceCopyServerReservedPdes_DISPATCH(pVaspaceApi, pCopyServerReservedPdesParams) #define vaspaceapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) vaspaceapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define vaspaceapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) vaspaceapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define vaspaceapiMapTo(pResource, pParams) vaspaceapiMapTo_DISPATCH(pResource, pParams) +#define vaspaceapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) vaspaceapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define vaspaceapiGetRefCount(pResource) vaspaceapiGetRefCount_DISPATCH(pResource) +#define vaspaceapiAddAdditionalDependants(pClient, pResource, pReference) vaspaceapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define vaspaceapiControl_Prologue(pResource, pCallContext, pParams) vaspaceapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define vaspaceapiGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) vaspaceapiGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define vaspaceapiInternalControlForward(pGpuResource, command, pParams, size) vaspaceapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define vaspaceapiUnmapFrom(pResource, pParams) vaspaceapiUnmapFrom_DISPATCH(pResource, pParams) +#define vaspaceapiControl_Epilogue(pResource, pCallContext, pParams) vaspaceapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define vaspaceapiControlLookup(pResource, pParams, ppEntry) vaspaceapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define vaspaceapiGetInternalObjectHandle(pGpuResource) vaspaceapiGetInternalObjectHandle_DISPATCH(pGpuResource) #define vaspaceapiControl(pGpuResource, pCallContext, pParams) vaspaceapiControl_DISPATCH(pGpuResource, pCallContext, pParams) #define vaspaceapiUnmap(pGpuResource, pCallContext, pCpuMapping) vaspaceapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define vaspaceapiGetMemInterMapParams(pRmResource, pParams) vaspaceapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define vaspaceapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) vaspaceapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define vaspaceapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) vaspaceapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define vaspaceapiGetInternalObjectHandle(pGpuResource) vaspaceapiGetInternalObjectHandle_DISPATCH(pGpuResource) #define vaspaceapiControlFilter(pResource, pCallContext, pParams) vaspaceapiControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define vaspaceapiAddAdditionalDependants(pClient, pResource, pReference) vaspaceapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define vaspaceapiGetRefCount(pResource) vaspaceapiGetRefCount_DISPATCH(pResource) -#define vaspaceapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) vaspaceapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define vaspaceapiMapTo(pResource, pParams) vaspaceapiMapTo_DISPATCH(pResource, pParams) -#define vaspaceapiControl_Prologue(pResource, pCallContext, pParams) vaspaceapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define vaspaceapiGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) vaspaceapiGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) -#define vaspaceapiInternalControlForward(pGpuResource, command, pParams, size) vaspaceapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define vaspaceapiControlSerialization_Prologue(pResource, pCallContext, pParams) vaspaceapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define vaspaceapiPreDestruct(pResource) vaspaceapiPreDestruct_DISPATCH(pResource) -#define vaspaceapiUnmapFrom(pResource, pParams) vaspaceapiUnmapFrom_DISPATCH(pResource, pParams) #define vaspaceapiIsDuplicate(pResource, hMemory, pDuplicate) vaspaceapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) -#define vaspaceapiControl_Epilogue(pResource, pCallContext, pParams) vaspaceapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define vaspaceapiControlLookup(pResource, pParams, ppEntry) vaspaceapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define vaspaceapiControlSerialization_Epilogue(pResource, pCallContext, pParams) vaspaceapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define vaspaceapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) vaspaceapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define vaspaceapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) vaspaceapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool vaspaceapiCanCopy_IMPL(struct VaSpaceApi *pResource); @@ -195,6 +199,54 @@ static inline NvBool vaspaceapiShareCallback_DISPATCH(struct VaSpaceApi *pGpuRes return pGpuResource->__vaspaceapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } +static inline NV_STATUS vaspaceapiCheckMemInterUnmap_DISPATCH(struct VaSpaceApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__vaspaceapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS vaspaceapiMapTo_DISPATCH(struct VaSpaceApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__vaspaceapiMapTo__(pResource, pParams); +} + +static inline NV_STATUS vaspaceapiGetMapAddrSpace_DISPATCH(struct VaSpaceApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__vaspaceapiGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 vaspaceapiGetRefCount_DISPATCH(struct VaSpaceApi *pResource) { + return pResource->__vaspaceapiGetRefCount__(pResource); +} + +static inline void vaspaceapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct VaSpaceApi *pResource, RsResourceRef *pReference) { + pResource->__vaspaceapiAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS vaspaceapiControl_Prologue_DISPATCH(struct VaSpaceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vaspaceapiControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS vaspaceapiGetRegBaseOffsetAndSize_DISPATCH(struct VaSpaceApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__vaspaceapiGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS vaspaceapiInternalControlForward_DISPATCH(struct VaSpaceApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__vaspaceapiInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS vaspaceapiUnmapFrom_DISPATCH(struct VaSpaceApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__vaspaceapiUnmapFrom__(pResource, pParams); +} + +static inline void vaspaceapiControl_Epilogue_DISPATCH(struct VaSpaceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__vaspaceapiControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS vaspaceapiControlLookup_DISPATCH(struct VaSpaceApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__vaspaceapiControlLookup__(pResource, pParams, ppEntry); +} + +static inline NvHandle vaspaceapiGetInternalObjectHandle_DISPATCH(struct VaSpaceApi *pGpuResource) { + return pGpuResource->__vaspaceapiGetInternalObjectHandle__(pGpuResource); +} + static inline NV_STATUS vaspaceapiControl_DISPATCH(struct VaSpaceApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pGpuResource->__vaspaceapiControl__(pGpuResource, pCallContext, pParams); } @@ -211,64 +263,24 @@ static inline NV_STATUS vaspaceapiGetMemoryMappingDescriptor_DISPATCH(struct VaS return pRmResource->__vaspaceapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS vaspaceapiGetMapAddrSpace_DISPATCH(struct VaSpaceApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__vaspaceapiGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvHandle vaspaceapiGetInternalObjectHandle_DISPATCH(struct VaSpaceApi *pGpuResource) { - return pGpuResource->__vaspaceapiGetInternalObjectHandle__(pGpuResource); -} - static inline NV_STATUS vaspaceapiControlFilter_DISPATCH(struct VaSpaceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__vaspaceapiControlFilter__(pResource, pCallContext, pParams); } -static inline void vaspaceapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct VaSpaceApi *pResource, RsResourceRef *pReference) { - pResource->__vaspaceapiAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 vaspaceapiGetRefCount_DISPATCH(struct VaSpaceApi *pResource) { - return pResource->__vaspaceapiGetRefCount__(pResource); -} - -static inline NV_STATUS vaspaceapiCheckMemInterUnmap_DISPATCH(struct VaSpaceApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__vaspaceapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS vaspaceapiMapTo_DISPATCH(struct VaSpaceApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__vaspaceapiMapTo__(pResource, pParams); -} - -static inline NV_STATUS vaspaceapiControl_Prologue_DISPATCH(struct VaSpaceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__vaspaceapiControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS vaspaceapiGetRegBaseOffsetAndSize_DISPATCH(struct VaSpaceApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__vaspaceapiGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); -} - -static inline NV_STATUS vaspaceapiInternalControlForward_DISPATCH(struct VaSpaceApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__vaspaceapiInternalControlForward__(pGpuResource, command, pParams, size); +static inline NV_STATUS vaspaceapiControlSerialization_Prologue_DISPATCH(struct VaSpaceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vaspaceapiControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline void vaspaceapiPreDestruct_DISPATCH(struct VaSpaceApi *pResource) { pResource->__vaspaceapiPreDestruct__(pResource); } -static inline NV_STATUS vaspaceapiUnmapFrom_DISPATCH(struct VaSpaceApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__vaspaceapiUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS vaspaceapiIsDuplicate_DISPATCH(struct VaSpaceApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__vaspaceapiIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline void vaspaceapiControl_Epilogue_DISPATCH(struct VaSpaceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__vaspaceapiControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS vaspaceapiControlLookup_DISPATCH(struct VaSpaceApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__vaspaceapiControlLookup__(pResource, pParams, ppEntry); +static inline void vaspaceapiControlSerialization_Epilogue_DISPATCH(struct VaSpaceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__vaspaceapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS vaspaceapiMap_DISPATCH(struct VaSpaceApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_vaspace_nvoc.h b/src/nvidia/generated/g_vaspace_nvoc.h index 6369c1188..34120e8bf 100644 --- a/src/nvidia/generated/g_vaspace_nvoc.h +++ b/src/nvidia/generated/g_vaspace_nvoc.h @@ -255,7 +255,7 @@ struct OBJVASPACE { void (*__vaspaceUnmap__)(struct OBJVASPACE *, struct OBJGPU *, const NvU64, const NvU64); NV_STATUS (*__vaspaceReserveMempool__)(struct OBJVASPACE *, struct OBJGPU *, NvHandle, NvU64, NvU64, NvU32); struct OBJEHEAP *(*__vaspaceGetHeap__)(struct OBJVASPACE *); - NvU32 (*__vaspaceGetMapPageSize__)(struct OBJVASPACE *, struct OBJGPU *, EMEMBLOCK *); + NvU64 (*__vaspaceGetMapPageSize__)(struct OBJVASPACE *, struct OBJGPU *, EMEMBLOCK *); NvU32 (*__vaspaceGetBigPageSize__)(struct OBJVASPACE *); NvBool (*__vaspaceIsMirrored__)(struct OBJVASPACE *); NvBool (*__vaspaceIsFaultCapable__)(struct OBJVASPACE *); @@ -426,12 +426,12 @@ static inline struct OBJEHEAP *vaspaceGetHeap_DISPATCH(struct OBJVASPACE *pVAS) return pVAS->__vaspaceGetHeap__(pVAS); } -static inline NvU32 vaspaceGetMapPageSize_07238a(struct OBJVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { +static inline NvU64 vaspaceGetMapPageSize_07238a(struct OBJVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { NV_ASSERT_PRECOMP(((NvBool)(0 != 0))); return 0U; } -static inline NvU32 vaspaceGetMapPageSize_DISPATCH(struct OBJVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { +static inline NvU64 vaspaceGetMapPageSize_DISPATCH(struct OBJVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { return pVAS->__vaspaceGetMapPageSize__(pVAS, pGpu, pMemBlock); } diff --git a/src/nvidia/generated/g_vblank_callback_nvoc.c b/src/nvidia/generated/g_vblank_callback_nvoc.c index f718525c0..7c7333ba1 100644 --- a/src/nvidia/generated/g_vblank_callback_nvoc.c +++ b/src/nvidia/generated/g_vblank_callback_nvoc.c @@ -97,6 +97,54 @@ static NvBool __nvoc_thunk_GpuResource_vblcbShareCallback(struct VblankCallback return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VblankCallback_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } +static NV_STATUS __nvoc_thunk_RmResource_vblcbCheckMemInterUnmap(struct VblankCallback *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VblankCallback_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_vblcbMapTo(struct VblankCallback *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vblcbGetMapAddrSpace(struct VblankCallback *pGpuResource, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VblankCallback_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_vblcbGetRefCount(struct VblankCallback *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_vblcbAddAdditionalDependants(struct RsClient *pClient, struct VblankCallback *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_vblcbControl_Prologue(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vblcbGetRegBaseOffsetAndSize(struct VblankCallback *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VblankCallback_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vblcbInternalControlForward(struct VblankCallback *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VblankCallback_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_vblcbUnmapFrom(struct VblankCallback *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_vblcbControl_Epilogue(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_vblcbControlLookup(struct VblankCallback *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset), pParams, ppEntry); +} + +static NvHandle __nvoc_thunk_GpuResource_vblcbGetInternalObjectHandle(struct VblankCallback *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VblankCallback_GpuResource.offset)); +} + static NV_STATUS __nvoc_thunk_GpuResource_vblcbControl(struct VblankCallback *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VblankCallback_GpuResource.offset), pCallContext, pParams); } @@ -113,68 +161,28 @@ static NV_STATUS __nvoc_thunk_RmResource_vblcbGetMemoryMappingDescriptor(struct return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VblankCallback_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_GpuResource_vblcbGetMapAddrSpace(struct VblankCallback *pGpuResource, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VblankCallback_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvHandle __nvoc_thunk_GpuResource_vblcbGetInternalObjectHandle(struct VblankCallback *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VblankCallback_GpuResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_vblcbControlFilter(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_vblcbAddAdditionalDependants(struct RsClient *pClient, struct VblankCallback *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_vblcbGetRefCount(struct VblankCallback *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RmResource_vblcbCheckMemInterUnmap(struct VblankCallback *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VblankCallback_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_vblcbMapTo(struct VblankCallback *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_vblcbControl_Prologue(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_GpuResource_vblcbGetRegBaseOffsetAndSize(struct VblankCallback *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VblankCallback_GpuResource.offset), pGpu, pOffset, pSize); +static NV_STATUS __nvoc_thunk_RmResource_vblcbControlSerialization_Prologue(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_vblcbCanCopy(struct VblankCallback *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_vblcbInternalControlForward(struct VblankCallback *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VblankCallback_GpuResource.offset), command, pParams, size); -} - static void __nvoc_thunk_RsResource_vblcbPreDestruct(struct VblankCallback *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_vblcbUnmapFrom(struct VblankCallback *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_vblcbIsDuplicate(struct VblankCallback *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset), hMemory, pDuplicate); } -static void __nvoc_thunk_RmResource_vblcbControl_Epilogue(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_vblcbControlLookup(struct VblankCallback *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_vblcbControlSerialization_Epilogue(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_vblcbMap(struct VblankCallback *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -254,6 +262,30 @@ static void __nvoc_init_funcTable_VblankCallback_1(VblankCallback *pThis) { pThis->__vblcbShareCallback__ = &__nvoc_thunk_GpuResource_vblcbShareCallback; + pThis->__vblcbCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_vblcbCheckMemInterUnmap; + + pThis->__vblcbMapTo__ = &__nvoc_thunk_RsResource_vblcbMapTo; + + pThis->__vblcbGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_vblcbGetMapAddrSpace; + + pThis->__vblcbGetRefCount__ = &__nvoc_thunk_RsResource_vblcbGetRefCount; + + pThis->__vblcbAddAdditionalDependants__ = &__nvoc_thunk_RsResource_vblcbAddAdditionalDependants; + + pThis->__vblcbControl_Prologue__ = &__nvoc_thunk_RmResource_vblcbControl_Prologue; + + pThis->__vblcbGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_vblcbGetRegBaseOffsetAndSize; + + pThis->__vblcbInternalControlForward__ = &__nvoc_thunk_GpuResource_vblcbInternalControlForward; + + pThis->__vblcbUnmapFrom__ = &__nvoc_thunk_RsResource_vblcbUnmapFrom; + + pThis->__vblcbControl_Epilogue__ = &__nvoc_thunk_RmResource_vblcbControl_Epilogue; + + pThis->__vblcbControlLookup__ = &__nvoc_thunk_RsResource_vblcbControlLookup; + + pThis->__vblcbGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_vblcbGetInternalObjectHandle; + pThis->__vblcbControl__ = &__nvoc_thunk_GpuResource_vblcbControl; pThis->__vblcbUnmap__ = &__nvoc_thunk_GpuResource_vblcbUnmap; @@ -262,37 +294,17 @@ static void __nvoc_init_funcTable_VblankCallback_1(VblankCallback *pThis) { pThis->__vblcbGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_vblcbGetMemoryMappingDescriptor; - pThis->__vblcbGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_vblcbGetMapAddrSpace; - - pThis->__vblcbGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_vblcbGetInternalObjectHandle; - pThis->__vblcbControlFilter__ = &__nvoc_thunk_RsResource_vblcbControlFilter; - pThis->__vblcbAddAdditionalDependants__ = &__nvoc_thunk_RsResource_vblcbAddAdditionalDependants; - - pThis->__vblcbGetRefCount__ = &__nvoc_thunk_RsResource_vblcbGetRefCount; - - pThis->__vblcbCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_vblcbCheckMemInterUnmap; - - pThis->__vblcbMapTo__ = &__nvoc_thunk_RsResource_vblcbMapTo; - - pThis->__vblcbControl_Prologue__ = &__nvoc_thunk_RmResource_vblcbControl_Prologue; - - pThis->__vblcbGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_vblcbGetRegBaseOffsetAndSize; + pThis->__vblcbControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_vblcbControlSerialization_Prologue; pThis->__vblcbCanCopy__ = &__nvoc_thunk_RsResource_vblcbCanCopy; - pThis->__vblcbInternalControlForward__ = &__nvoc_thunk_GpuResource_vblcbInternalControlForward; - pThis->__vblcbPreDestruct__ = &__nvoc_thunk_RsResource_vblcbPreDestruct; - pThis->__vblcbUnmapFrom__ = &__nvoc_thunk_RsResource_vblcbUnmapFrom; - pThis->__vblcbIsDuplicate__ = &__nvoc_thunk_RsResource_vblcbIsDuplicate; - pThis->__vblcbControl_Epilogue__ = &__nvoc_thunk_RmResource_vblcbControl_Epilogue; - - pThis->__vblcbControlLookup__ = &__nvoc_thunk_RsResource_vblcbControlLookup; + pThis->__vblcbControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_vblcbControlSerialization_Epilogue; pThis->__vblcbMap__ = &__nvoc_thunk_GpuResource_vblcbMap; @@ -320,13 +332,16 @@ NV_STATUS __nvoc_objCreate_VblankCallback(VblankCallback **ppThis, Dynamic *pPar Object *pParentObj; VblankCallback *pThis; - pThis = portMemAllocNonPaged(sizeof(VblankCallback)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(VblankCallback), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(VblankCallback)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_VblankCallback); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -342,11 +357,17 @@ NV_STATUS __nvoc_objCreate_VblankCallback(VblankCallback **ppThis, Dynamic *pPar if (status != NV_OK) goto __nvoc_objCreate_VblankCallback_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_VblankCallback_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(VblankCallback)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_vblank_callback_nvoc.h b/src/nvidia/generated/g_vblank_callback_nvoc.h index 20d9556ea..1ed6806e8 100644 --- a/src/nvidia/generated/g_vblank_callback_nvoc.h +++ b/src/nvidia/generated/g_vblank_callback_nvoc.h @@ -64,26 +64,28 @@ struct VblankCallback { struct VblankCallback *__nvoc_pbase_VblankCallback; NV_STATUS (*__vblcbCtrlSetVBlankNotification__)(struct VblankCallback *, NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION_PARAMS *); NvBool (*__vblcbShareCallback__)(struct VblankCallback *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__vblcbCheckMemInterUnmap__)(struct VblankCallback *, NvBool); + NV_STATUS (*__vblcbMapTo__)(struct VblankCallback *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__vblcbGetMapAddrSpace__)(struct VblankCallback *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__vblcbGetRefCount__)(struct VblankCallback *); + void (*__vblcbAddAdditionalDependants__)(struct RsClient *, struct VblankCallback *, RsResourceRef *); + NV_STATUS (*__vblcbControl_Prologue__)(struct VblankCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vblcbGetRegBaseOffsetAndSize__)(struct VblankCallback *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__vblcbInternalControlForward__)(struct VblankCallback *, NvU32, void *, NvU32); + NV_STATUS (*__vblcbUnmapFrom__)(struct VblankCallback *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__vblcbControl_Epilogue__)(struct VblankCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vblcbControlLookup__)(struct VblankCallback *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__vblcbGetInternalObjectHandle__)(struct VblankCallback *); NV_STATUS (*__vblcbControl__)(struct VblankCallback *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vblcbUnmap__)(struct VblankCallback *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__vblcbGetMemInterMapParams__)(struct VblankCallback *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__vblcbGetMemoryMappingDescriptor__)(struct VblankCallback *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__vblcbGetMapAddrSpace__)(struct VblankCallback *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__vblcbGetInternalObjectHandle__)(struct VblankCallback *); NV_STATUS (*__vblcbControlFilter__)(struct VblankCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__vblcbAddAdditionalDependants__)(struct RsClient *, struct VblankCallback *, RsResourceRef *); - NvU32 (*__vblcbGetRefCount__)(struct VblankCallback *); - NV_STATUS (*__vblcbCheckMemInterUnmap__)(struct VblankCallback *, NvBool); - NV_STATUS (*__vblcbMapTo__)(struct VblankCallback *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__vblcbControl_Prologue__)(struct VblankCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__vblcbGetRegBaseOffsetAndSize__)(struct VblankCallback *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__vblcbControlSerialization_Prologue__)(struct VblankCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__vblcbCanCopy__)(struct VblankCallback *); - NV_STATUS (*__vblcbInternalControlForward__)(struct VblankCallback *, NvU32, void *, NvU32); void (*__vblcbPreDestruct__)(struct VblankCallback *); - NV_STATUS (*__vblcbUnmapFrom__)(struct VblankCallback *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__vblcbIsDuplicate__)(struct VblankCallback *, NvHandle, NvBool *); - void (*__vblcbControl_Epilogue__)(struct VblankCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__vblcbControlLookup__)(struct VblankCallback *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__vblcbControlSerialization_Epilogue__)(struct VblankCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vblcbMap__)(struct VblankCallback *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__vblcbAccessCallback__)(struct VblankCallback *, struct RsClient *, void *, RsAccessRight); VBLANKCALLBACK CallBack; @@ -123,26 +125,28 @@ NV_STATUS __nvoc_objCreate_VblankCallback(VblankCallback**, Dynamic*, NvU32, CAL #define vblcbCtrlSetVBlankNotification(pVblankCallback, pParams) vblcbCtrlSetVBlankNotification_DISPATCH(pVblankCallback, pParams) #define vblcbShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) vblcbShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define vblcbCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) vblcbCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define vblcbMapTo(pResource, pParams) vblcbMapTo_DISPATCH(pResource, pParams) +#define vblcbGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) vblcbGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define vblcbGetRefCount(pResource) vblcbGetRefCount_DISPATCH(pResource) +#define vblcbAddAdditionalDependants(pClient, pResource, pReference) vblcbAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define vblcbControl_Prologue(pResource, pCallContext, pParams) vblcbControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define vblcbGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) vblcbGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define vblcbInternalControlForward(pGpuResource, command, pParams, size) vblcbInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define vblcbUnmapFrom(pResource, pParams) vblcbUnmapFrom_DISPATCH(pResource, pParams) +#define vblcbControl_Epilogue(pResource, pCallContext, pParams) vblcbControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define vblcbControlLookup(pResource, pParams, ppEntry) vblcbControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define vblcbGetInternalObjectHandle(pGpuResource) vblcbGetInternalObjectHandle_DISPATCH(pGpuResource) #define vblcbControl(pGpuResource, pCallContext, pParams) vblcbControl_DISPATCH(pGpuResource, pCallContext, pParams) #define vblcbUnmap(pGpuResource, pCallContext, pCpuMapping) vblcbUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define vblcbGetMemInterMapParams(pRmResource, pParams) vblcbGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define vblcbGetMemoryMappingDescriptor(pRmResource, ppMemDesc) vblcbGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define vblcbGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) vblcbGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define vblcbGetInternalObjectHandle(pGpuResource) vblcbGetInternalObjectHandle_DISPATCH(pGpuResource) #define vblcbControlFilter(pResource, pCallContext, pParams) vblcbControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define vblcbAddAdditionalDependants(pClient, pResource, pReference) vblcbAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define vblcbGetRefCount(pResource) vblcbGetRefCount_DISPATCH(pResource) -#define vblcbCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) vblcbCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define vblcbMapTo(pResource, pParams) vblcbMapTo_DISPATCH(pResource, pParams) -#define vblcbControl_Prologue(pResource, pCallContext, pParams) vblcbControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define vblcbGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) vblcbGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define vblcbControlSerialization_Prologue(pResource, pCallContext, pParams) vblcbControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define vblcbCanCopy(pResource) vblcbCanCopy_DISPATCH(pResource) -#define vblcbInternalControlForward(pGpuResource, command, pParams, size) vblcbInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define vblcbPreDestruct(pResource) vblcbPreDestruct_DISPATCH(pResource) -#define vblcbUnmapFrom(pResource, pParams) vblcbUnmapFrom_DISPATCH(pResource, pParams) #define vblcbIsDuplicate(pResource, hMemory, pDuplicate) vblcbIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) -#define vblcbControl_Epilogue(pResource, pCallContext, pParams) vblcbControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define vblcbControlLookup(pResource, pParams, ppEntry) vblcbControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define vblcbControlSerialization_Epilogue(pResource, pCallContext, pParams) vblcbControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define vblcbMap(pGpuResource, pCallContext, pParams, pCpuMapping) vblcbMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define vblcbAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) vblcbAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS vblcbCtrlSetVBlankNotification_IMPL(struct VblankCallback *pVblankCallback, NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION_PARAMS *pParams); @@ -155,6 +159,54 @@ static inline NvBool vblcbShareCallback_DISPATCH(struct VblankCallback *pGpuReso return pGpuResource->__vblcbShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } +static inline NV_STATUS vblcbCheckMemInterUnmap_DISPATCH(struct VblankCallback *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__vblcbCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS vblcbMapTo_DISPATCH(struct VblankCallback *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__vblcbMapTo__(pResource, pParams); +} + +static inline NV_STATUS vblcbGetMapAddrSpace_DISPATCH(struct VblankCallback *pGpuResource, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__vblcbGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 vblcbGetRefCount_DISPATCH(struct VblankCallback *pResource) { + return pResource->__vblcbGetRefCount__(pResource); +} + +static inline void vblcbAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct VblankCallback *pResource, RsResourceRef *pReference) { + pResource->__vblcbAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS vblcbControl_Prologue_DISPATCH(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vblcbControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS vblcbGetRegBaseOffsetAndSize_DISPATCH(struct VblankCallback *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__vblcbGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS vblcbInternalControlForward_DISPATCH(struct VblankCallback *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__vblcbInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS vblcbUnmapFrom_DISPATCH(struct VblankCallback *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__vblcbUnmapFrom__(pResource, pParams); +} + +static inline void vblcbControl_Epilogue_DISPATCH(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__vblcbControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS vblcbControlLookup_DISPATCH(struct VblankCallback *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__vblcbControlLookup__(pResource, pParams, ppEntry); +} + +static inline NvHandle vblcbGetInternalObjectHandle_DISPATCH(struct VblankCallback *pGpuResource) { + return pGpuResource->__vblcbGetInternalObjectHandle__(pGpuResource); +} + static inline NV_STATUS vblcbControl_DISPATCH(struct VblankCallback *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pGpuResource->__vblcbControl__(pGpuResource, pCallContext, pParams); } @@ -171,68 +223,28 @@ static inline NV_STATUS vblcbGetMemoryMappingDescriptor_DISPATCH(struct VblankCa return pRmResource->__vblcbGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS vblcbGetMapAddrSpace_DISPATCH(struct VblankCallback *pGpuResource, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__vblcbGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvHandle vblcbGetInternalObjectHandle_DISPATCH(struct VblankCallback *pGpuResource) { - return pGpuResource->__vblcbGetInternalObjectHandle__(pGpuResource); -} - static inline NV_STATUS vblcbControlFilter_DISPATCH(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__vblcbControlFilter__(pResource, pCallContext, pParams); } -static inline void vblcbAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct VblankCallback *pResource, RsResourceRef *pReference) { - pResource->__vblcbAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 vblcbGetRefCount_DISPATCH(struct VblankCallback *pResource) { - return pResource->__vblcbGetRefCount__(pResource); -} - -static inline NV_STATUS vblcbCheckMemInterUnmap_DISPATCH(struct VblankCallback *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__vblcbCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS vblcbMapTo_DISPATCH(struct VblankCallback *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__vblcbMapTo__(pResource, pParams); -} - -static inline NV_STATUS vblcbControl_Prologue_DISPATCH(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__vblcbControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS vblcbGetRegBaseOffsetAndSize_DISPATCH(struct VblankCallback *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__vblcbGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +static inline NV_STATUS vblcbControlSerialization_Prologue_DISPATCH(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vblcbControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool vblcbCanCopy_DISPATCH(struct VblankCallback *pResource) { return pResource->__vblcbCanCopy__(pResource); } -static inline NV_STATUS vblcbInternalControlForward_DISPATCH(struct VblankCallback *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__vblcbInternalControlForward__(pGpuResource, command, pParams, size); -} - static inline void vblcbPreDestruct_DISPATCH(struct VblankCallback *pResource) { pResource->__vblcbPreDestruct__(pResource); } -static inline NV_STATUS vblcbUnmapFrom_DISPATCH(struct VblankCallback *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__vblcbUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS vblcbIsDuplicate_DISPATCH(struct VblankCallback *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__vblcbIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline void vblcbControl_Epilogue_DISPATCH(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__vblcbControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS vblcbControlLookup_DISPATCH(struct VblankCallback *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__vblcbControlLookup__(pResource, pParams, ppEntry); +static inline void vblcbControlSerialization_Epilogue_DISPATCH(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__vblcbControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS vblcbMap_DISPATCH(struct VblankCallback *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_vgpuconfigapi_nvoc.c b/src/nvidia/generated/g_vgpuconfigapi_nvoc.c index 87b139091..d74122436 100644 --- a/src/nvidia/generated/g_vgpuconfigapi_nvoc.c +++ b/src/nvidia/generated/g_vgpuconfigapi_nvoc.c @@ -115,16 +115,16 @@ static NvBool __nvoc_thunk_GpuResource_vgpuconfigapiShareCallback(struct VgpuCon return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VgpuConfigApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_RsResource_vgpuconfigapiMapTo(struct VgpuConfigApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuConfigApi_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_vgpuconfigapiCheckMemInterUnmap(struct VgpuConfigApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VgpuConfigApi_RmResource.offset), bSubdeviceHandleProvided); } static NV_STATUS __nvoc_thunk_Notifier_vgpuconfigapiGetOrAllocNotifShare(struct VgpuConfigApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_VgpuConfigApi_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); } -static NV_STATUS __nvoc_thunk_RmResource_vgpuconfigapiCheckMemInterUnmap(struct VgpuConfigApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VgpuConfigApi_RmResource.offset), bSubdeviceHandleProvided); +static NV_STATUS __nvoc_thunk_RsResource_vgpuconfigapiMapTo(struct VgpuConfigApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuConfigApi_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_GpuResource_vgpuconfigapiGetMapAddrSpace(struct VgpuConfigApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -195,6 +195,10 @@ static NV_STATUS __nvoc_thunk_Notifier_vgpuconfigapiUnregisterEvent(struct VgpuC return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_VgpuConfigApi_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static NV_STATUS __nvoc_thunk_RmResource_vgpuconfigapiControlSerialization_Prologue(struct VgpuConfigApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuConfigApi_RmResource.offset), pCallContext, pParams); +} + static NvBool __nvoc_thunk_RsResource_vgpuconfigapiCanCopy(struct VgpuConfigApi *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuConfigApi_RsResource.offset)); } @@ -207,6 +211,10 @@ static NV_STATUS __nvoc_thunk_RsResource_vgpuconfigapiIsDuplicate(struct VgpuCon return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuConfigApi_RsResource.offset), hMemory, pDuplicate); } +static void __nvoc_thunk_RmResource_vgpuconfigapiControlSerialization_Epilogue(struct VgpuConfigApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuConfigApi_RmResource.offset), pCallContext, pParams); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_vgpuconfigapiGetNotificationListPtr(struct VgpuConfigApi *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_VgpuConfigApi_Notifier.offset)); } @@ -622,11 +630,11 @@ static void __nvoc_init_funcTable_VgpuConfigApi_1(VgpuConfigApi *pThis) { pThis->__vgpuconfigapiShareCallback__ = &__nvoc_thunk_GpuResource_vgpuconfigapiShareCallback; - pThis->__vgpuconfigapiMapTo__ = &__nvoc_thunk_RsResource_vgpuconfigapiMapTo; + pThis->__vgpuconfigapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_vgpuconfigapiCheckMemInterUnmap; pThis->__vgpuconfigapiGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_vgpuconfigapiGetOrAllocNotifShare; - pThis->__vgpuconfigapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_vgpuconfigapiCheckMemInterUnmap; + pThis->__vgpuconfigapiMapTo__ = &__nvoc_thunk_RsResource_vgpuconfigapiMapTo; pThis->__vgpuconfigapiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_vgpuconfigapiGetMapAddrSpace; @@ -662,12 +670,16 @@ static void __nvoc_init_funcTable_VgpuConfigApi_1(VgpuConfigApi *pThis) { pThis->__vgpuconfigapiUnregisterEvent__ = &__nvoc_thunk_Notifier_vgpuconfigapiUnregisterEvent; + pThis->__vgpuconfigapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_vgpuconfigapiControlSerialization_Prologue; + pThis->__vgpuconfigapiCanCopy__ = &__nvoc_thunk_RsResource_vgpuconfigapiCanCopy; pThis->__vgpuconfigapiPreDestruct__ = &__nvoc_thunk_RsResource_vgpuconfigapiPreDestruct; pThis->__vgpuconfigapiIsDuplicate__ = &__nvoc_thunk_RsResource_vgpuconfigapiIsDuplicate; + pThis->__vgpuconfigapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_vgpuconfigapiControlSerialization_Epilogue; + pThis->__vgpuconfigapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_vgpuconfigapiGetNotificationListPtr; pThis->__vgpuconfigapiGetNotificationShare__ = &__nvoc_thunk_Notifier_vgpuconfigapiGetNotificationShare; @@ -702,13 +714,16 @@ NV_STATUS __nvoc_objCreate_VgpuConfigApi(VgpuConfigApi **ppThis, Dynamic *pParen Object *pParentObj; VgpuConfigApi *pThis; - pThis = portMemAllocNonPaged(sizeof(VgpuConfigApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(VgpuConfigApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(VgpuConfigApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_VgpuConfigApi); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -724,11 +739,17 @@ NV_STATUS __nvoc_objCreate_VgpuConfigApi(VgpuConfigApi **ppThis, Dynamic *pParen if (status != NV_OK) goto __nvoc_objCreate_VgpuConfigApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_VgpuConfigApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(VgpuConfigApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_vgpuconfigapi_nvoc.h b/src/nvidia/generated/g_vgpuconfigapi_nvoc.h index f1b3dde95..edb5e7b78 100644 --- a/src/nvidia/generated/g_vgpuconfigapi_nvoc.h +++ b/src/nvidia/generated/g_vgpuconfigapi_nvoc.h @@ -81,9 +81,9 @@ struct VgpuConfigApi { NV_STATUS (*__vgpuconfigapiCtrlCmdGetVgpuDriversCaps__)(struct VgpuConfigApi *, NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS *); NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigSetPgpuInfo__)(struct VgpuConfigApi *, NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS *); NvBool (*__vgpuconfigapiShareCallback__)(struct VgpuConfigApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__vgpuconfigapiMapTo__)(struct VgpuConfigApi *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__vgpuconfigapiGetOrAllocNotifShare__)(struct VgpuConfigApi *, NvHandle, NvHandle, struct NotifShare **); NV_STATUS (*__vgpuconfigapiCheckMemInterUnmap__)(struct VgpuConfigApi *, NvBool); + NV_STATUS (*__vgpuconfigapiGetOrAllocNotifShare__)(struct VgpuConfigApi *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__vgpuconfigapiMapTo__)(struct VgpuConfigApi *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__vgpuconfigapiGetMapAddrSpace__)(struct VgpuConfigApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); void (*__vgpuconfigapiSetNotificationShare__)(struct VgpuConfigApi *, struct NotifShare *); NvU32 (*__vgpuconfigapiGetRefCount__)(struct VgpuConfigApi *); @@ -101,9 +101,11 @@ struct VgpuConfigApi { NV_STATUS (*__vgpuconfigapiGetMemoryMappingDescriptor__)(struct VgpuConfigApi *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__vgpuconfigapiControlFilter__)(struct VgpuConfigApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vgpuconfigapiUnregisterEvent__)(struct VgpuConfigApi *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__vgpuconfigapiControlSerialization_Prologue__)(struct VgpuConfigApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__vgpuconfigapiCanCopy__)(struct VgpuConfigApi *); void (*__vgpuconfigapiPreDestruct__)(struct VgpuConfigApi *); NV_STATUS (*__vgpuconfigapiIsDuplicate__)(struct VgpuConfigApi *, NvHandle, NvBool *); + void (*__vgpuconfigapiControlSerialization_Epilogue__)(struct VgpuConfigApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__vgpuconfigapiGetNotificationListPtr__)(struct VgpuConfigApi *); struct NotifShare *(*__vgpuconfigapiGetNotificationShare__)(struct VgpuConfigApi *); NV_STATUS (*__vgpuconfigapiMap__)(struct VgpuConfigApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -158,9 +160,9 @@ NV_STATUS __nvoc_objCreate_VgpuConfigApi(VgpuConfigApi**, Dynamic*, NvU32, struc #define vgpuconfigapiCtrlCmdGetVgpuDriversCaps(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdGetVgpuDriversCaps_DISPATCH(pVgpuConfigApi, pParams) #define vgpuconfigapiCtrlCmdVgpuConfigSetPgpuInfo(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdVgpuConfigSetPgpuInfo_DISPATCH(pVgpuConfigApi, pParams) #define vgpuconfigapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) vgpuconfigapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define vgpuconfigapiMapTo(pResource, pParams) vgpuconfigapiMapTo_DISPATCH(pResource, pParams) -#define vgpuconfigapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) vgpuconfigapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) #define vgpuconfigapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) vgpuconfigapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define vgpuconfigapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) vgpuconfigapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define vgpuconfigapiMapTo(pResource, pParams) vgpuconfigapiMapTo_DISPATCH(pResource, pParams) #define vgpuconfigapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) vgpuconfigapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) #define vgpuconfigapiSetNotificationShare(pNotifier, pNotifShare) vgpuconfigapiSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define vgpuconfigapiGetRefCount(pResource) vgpuconfigapiGetRefCount_DISPATCH(pResource) @@ -178,9 +180,11 @@ NV_STATUS __nvoc_objCreate_VgpuConfigApi(VgpuConfigApi**, Dynamic*, NvU32, struc #define vgpuconfigapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) vgpuconfigapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define vgpuconfigapiControlFilter(pResource, pCallContext, pParams) vgpuconfigapiControlFilter_DISPATCH(pResource, pCallContext, pParams) #define vgpuconfigapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) vgpuconfigapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define vgpuconfigapiControlSerialization_Prologue(pResource, pCallContext, pParams) vgpuconfigapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define vgpuconfigapiCanCopy(pResource) vgpuconfigapiCanCopy_DISPATCH(pResource) #define vgpuconfigapiPreDestruct(pResource) vgpuconfigapiPreDestruct_DISPATCH(pResource) #define vgpuconfigapiIsDuplicate(pResource, hMemory, pDuplicate) vgpuconfigapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define vgpuconfigapiControlSerialization_Epilogue(pResource, pCallContext, pParams) vgpuconfigapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define vgpuconfigapiGetNotificationListPtr(pNotifier) vgpuconfigapiGetNotificationListPtr_DISPATCH(pNotifier) #define vgpuconfigapiGetNotificationShare(pNotifier) vgpuconfigapiGetNotificationShare_DISPATCH(pNotifier) #define vgpuconfigapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) vgpuconfigapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -297,16 +301,16 @@ static inline NvBool vgpuconfigapiShareCallback_DISPATCH(struct VgpuConfigApi *p return pGpuResource->__vgpuconfigapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS vgpuconfigapiMapTo_DISPATCH(struct VgpuConfigApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__vgpuconfigapiMapTo__(pResource, pParams); +static inline NV_STATUS vgpuconfigapiCheckMemInterUnmap_DISPATCH(struct VgpuConfigApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__vgpuconfigapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } static inline NV_STATUS vgpuconfigapiGetOrAllocNotifShare_DISPATCH(struct VgpuConfigApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return pNotifier->__vgpuconfigapiGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); } -static inline NV_STATUS vgpuconfigapiCheckMemInterUnmap_DISPATCH(struct VgpuConfigApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__vgpuconfigapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline NV_STATUS vgpuconfigapiMapTo_DISPATCH(struct VgpuConfigApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__vgpuconfigapiMapTo__(pResource, pParams); } static inline NV_STATUS vgpuconfigapiGetMapAddrSpace_DISPATCH(struct VgpuConfigApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -377,6 +381,10 @@ static inline NV_STATUS vgpuconfigapiUnregisterEvent_DISPATCH(struct VgpuConfigA return pNotifier->__vgpuconfigapiUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS vgpuconfigapiControlSerialization_Prologue_DISPATCH(struct VgpuConfigApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vgpuconfigapiControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool vgpuconfigapiCanCopy_DISPATCH(struct VgpuConfigApi *pResource) { return pResource->__vgpuconfigapiCanCopy__(pResource); } @@ -389,6 +397,10 @@ static inline NV_STATUS vgpuconfigapiIsDuplicate_DISPATCH(struct VgpuConfigApi * return pResource->__vgpuconfigapiIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void vgpuconfigapiControlSerialization_Epilogue_DISPATCH(struct VgpuConfigApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__vgpuconfigapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *vgpuconfigapiGetNotificationListPtr_DISPATCH(struct VgpuConfigApi *pNotifier) { return pNotifier->__vgpuconfigapiGetNotificationListPtr__(pNotifier); } diff --git a/src/nvidia/generated/g_video_mem_nvoc.c b/src/nvidia/generated/g_video_mem_nvoc.c index c65e26c7d..a8ea3e24a 100644 --- a/src/nvidia/generated/g_video_mem_nvoc.c +++ b/src/nvidia/generated/g_video_mem_nvoc.c @@ -110,6 +110,46 @@ static NV_STATUS __nvoc_thunk_Memory_vidmemCheckMemInterUnmap(struct VideoMemory return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset), bSubdeviceHandleProvided); } +static NvBool __nvoc_thunk_RmResource_vidmemShareCallback(struct VideoMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RsResource_vidmemMapTo(struct VideoMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_vidmemGetMapAddrSpace(struct VideoMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_vidmemGetRefCount(struct VideoMemory *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_vidmemAddAdditionalDependants(struct RsClient *pClient, struct VideoMemory *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_vidmemControl_Prologue(struct VideoMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_Memory_vidmemIsGpuMapAllowed(struct VideoMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset), pGpu); +} + +static NV_STATUS __nvoc_thunk_RsResource_vidmemUnmapFrom(struct VideoMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_vidmemControl_Epilogue(struct VideoMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_vidmemControlLookup(struct VideoMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RsResource.offset), pParams, ppEntry); +} + static NV_STATUS __nvoc_thunk_Memory_vidmemControl(struct VideoMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset), pCallContext, pParams); } @@ -126,42 +166,18 @@ static NV_STATUS __nvoc_thunk_Memory_vidmemGetMemoryMappingDescriptor(struct Vid return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_Memory_vidmemGetMapAddrSpace(struct VideoMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvBool __nvoc_thunk_RmResource_vidmemShareCallback(struct VideoMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); -} - static NV_STATUS __nvoc_thunk_RsResource_vidmemControlFilter(struct VideoMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_vidmemAddAdditionalDependants(struct RsClient *pClient, struct VideoMemory *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_vidmemGetRefCount(struct VideoMemory *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RsResource_vidmemMapTo(struct VideoMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RmResource_vidmemControlSerialization_Prologue(struct VideoMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_StandardMemory_vidmemCanCopy(struct VideoMemory *pStandardMemory) { return stdmemCanCopy((struct StandardMemory *)(((unsigned char *)pStandardMemory) + __nvoc_rtti_VideoMemory_StandardMemory.offset)); } -static NvBool __nvoc_thunk_Memory_vidmemIsGpuMapAllowed(struct VideoMemory *pMemory, struct OBJGPU *pGpu) { - return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset), pGpu); -} - -static NV_STATUS __nvoc_thunk_RmResource_vidmemControl_Prologue(struct VideoMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RmResource.offset), pCallContext, pParams); -} - static NV_STATUS __nvoc_thunk_Memory_vidmemIsReady(struct VideoMemory *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset), bCopyConstructorContext); } @@ -174,16 +190,8 @@ static NV_STATUS __nvoc_thunk_Memory_vidmemIsDuplicate(struct VideoMemory *pMemo return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset), hMemory, pDuplicate); } -static NV_STATUS __nvoc_thunk_RsResource_vidmemUnmapFrom(struct VideoMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RsResource.offset), pParams); -} - -static void __nvoc_thunk_RmResource_vidmemControl_Epilogue(struct VideoMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_vidmemControlLookup(struct VideoMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_vidmemControlSerialization_Epilogue(struct VideoMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_vidmemMap(struct VideoMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -239,6 +247,26 @@ static void __nvoc_init_funcTable_VideoMemory_1(VideoMemory *pThis) { pThis->__vidmemCheckMemInterUnmap__ = &__nvoc_thunk_Memory_vidmemCheckMemInterUnmap; + pThis->__vidmemShareCallback__ = &__nvoc_thunk_RmResource_vidmemShareCallback; + + pThis->__vidmemMapTo__ = &__nvoc_thunk_RsResource_vidmemMapTo; + + pThis->__vidmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_vidmemGetMapAddrSpace; + + pThis->__vidmemGetRefCount__ = &__nvoc_thunk_RsResource_vidmemGetRefCount; + + pThis->__vidmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_vidmemAddAdditionalDependants; + + pThis->__vidmemControl_Prologue__ = &__nvoc_thunk_RmResource_vidmemControl_Prologue; + + pThis->__vidmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_vidmemIsGpuMapAllowed; + + pThis->__vidmemUnmapFrom__ = &__nvoc_thunk_RsResource_vidmemUnmapFrom; + + pThis->__vidmemControl_Epilogue__ = &__nvoc_thunk_RmResource_vidmemControl_Epilogue; + + pThis->__vidmemControlLookup__ = &__nvoc_thunk_RsResource_vidmemControlLookup; + pThis->__vidmemControl__ = &__nvoc_thunk_Memory_vidmemControl; pThis->__vidmemUnmap__ = &__nvoc_thunk_Memory_vidmemUnmap; @@ -247,35 +275,19 @@ static void __nvoc_init_funcTable_VideoMemory_1(VideoMemory *pThis) { pThis->__vidmemGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_vidmemGetMemoryMappingDescriptor; - pThis->__vidmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_vidmemGetMapAddrSpace; - - pThis->__vidmemShareCallback__ = &__nvoc_thunk_RmResource_vidmemShareCallback; - pThis->__vidmemControlFilter__ = &__nvoc_thunk_RsResource_vidmemControlFilter; - pThis->__vidmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_vidmemAddAdditionalDependants; - - pThis->__vidmemGetRefCount__ = &__nvoc_thunk_RsResource_vidmemGetRefCount; - - pThis->__vidmemMapTo__ = &__nvoc_thunk_RsResource_vidmemMapTo; + pThis->__vidmemControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_vidmemControlSerialization_Prologue; pThis->__vidmemCanCopy__ = &__nvoc_thunk_StandardMemory_vidmemCanCopy; - pThis->__vidmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_vidmemIsGpuMapAllowed; - - pThis->__vidmemControl_Prologue__ = &__nvoc_thunk_RmResource_vidmemControl_Prologue; - pThis->__vidmemIsReady__ = &__nvoc_thunk_Memory_vidmemIsReady; pThis->__vidmemPreDestruct__ = &__nvoc_thunk_RsResource_vidmemPreDestruct; pThis->__vidmemIsDuplicate__ = &__nvoc_thunk_Memory_vidmemIsDuplicate; - pThis->__vidmemUnmapFrom__ = &__nvoc_thunk_RsResource_vidmemUnmapFrom; - - pThis->__vidmemControl_Epilogue__ = &__nvoc_thunk_RmResource_vidmemControl_Epilogue; - - pThis->__vidmemControlLookup__ = &__nvoc_thunk_RsResource_vidmemControlLookup; + pThis->__vidmemControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_vidmemControlSerialization_Epilogue; pThis->__vidmemMap__ = &__nvoc_thunk_Memory_vidmemMap; @@ -304,13 +316,16 @@ NV_STATUS __nvoc_objCreate_VideoMemory(VideoMemory **ppThis, Dynamic *pParent, N Object *pParentObj; VideoMemory *pThis; - pThis = portMemAllocNonPaged(sizeof(VideoMemory)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(VideoMemory), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(VideoMemory)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_VideoMemory); + pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -326,11 +341,17 @@ NV_STATUS __nvoc_objCreate_VideoMemory(VideoMemory **ppThis, Dynamic *pParent, N if (status != NV_OK) goto __nvoc_objCreate_VideoMemory_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_VideoMemory_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(VideoMemory)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_video_mem_nvoc.h b/src/nvidia/generated/g_video_mem_nvoc.h index 8ed8e8474..4b409885d 100644 --- a/src/nvidia/generated/g_video_mem_nvoc.h +++ b/src/nvidia/generated/g_video_mem_nvoc.h @@ -56,25 +56,27 @@ struct VideoMemory { struct VideoMemory *__nvoc_pbase_VideoMemory; NV_STATUS (*__vidmemCheckCopyPermissions__)(struct VideoMemory *, struct OBJGPU *, NvHandle); NV_STATUS (*__vidmemCheckMemInterUnmap__)(struct VideoMemory *, NvBool); + NvBool (*__vidmemShareCallback__)(struct VideoMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__vidmemMapTo__)(struct VideoMemory *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__vidmemGetMapAddrSpace__)(struct VideoMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__vidmemGetRefCount__)(struct VideoMemory *); + void (*__vidmemAddAdditionalDependants__)(struct RsClient *, struct VideoMemory *, RsResourceRef *); + NV_STATUS (*__vidmemControl_Prologue__)(struct VideoMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__vidmemIsGpuMapAllowed__)(struct VideoMemory *, struct OBJGPU *); + NV_STATUS (*__vidmemUnmapFrom__)(struct VideoMemory *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__vidmemControl_Epilogue__)(struct VideoMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vidmemControlLookup__)(struct VideoMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__vidmemControl__)(struct VideoMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vidmemUnmap__)(struct VideoMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__vidmemGetMemInterMapParams__)(struct VideoMemory *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__vidmemGetMemoryMappingDescriptor__)(struct VideoMemory *, MEMORY_DESCRIPTOR **); - NV_STATUS (*__vidmemGetMapAddrSpace__)(struct VideoMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvBool (*__vidmemShareCallback__)(struct VideoMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__vidmemControlFilter__)(struct VideoMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__vidmemAddAdditionalDependants__)(struct RsClient *, struct VideoMemory *, RsResourceRef *); - NvU32 (*__vidmemGetRefCount__)(struct VideoMemory *); - NV_STATUS (*__vidmemMapTo__)(struct VideoMemory *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__vidmemControlSerialization_Prologue__)(struct VideoMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__vidmemCanCopy__)(struct VideoMemory *); - NvBool (*__vidmemIsGpuMapAllowed__)(struct VideoMemory *, struct OBJGPU *); - NV_STATUS (*__vidmemControl_Prologue__)(struct VideoMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vidmemIsReady__)(struct VideoMemory *, NvBool); void (*__vidmemPreDestruct__)(struct VideoMemory *); NV_STATUS (*__vidmemIsDuplicate__)(struct VideoMemory *, NvHandle, NvBool *); - NV_STATUS (*__vidmemUnmapFrom__)(struct VideoMemory *, RS_RES_UNMAP_FROM_PARAMS *); - void (*__vidmemControl_Epilogue__)(struct VideoMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__vidmemControlLookup__)(struct VideoMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__vidmemControlSerialization_Epilogue__)(struct VideoMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vidmemMap__)(struct VideoMemory *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__vidmemAccessCallback__)(struct VideoMemory *, struct RsClient *, void *, RsAccessRight); }; @@ -109,25 +111,27 @@ NV_STATUS __nvoc_objCreate_VideoMemory(VideoMemory**, Dynamic*, NvU32, CALL_CONT #define vidmemCheckCopyPermissions(pVideoMemory, pDstGpu, hDstClientNvBool) vidmemCheckCopyPermissions_DISPATCH(pVideoMemory, pDstGpu, hDstClientNvBool) #define vidmemCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) vidmemCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define vidmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) vidmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define vidmemMapTo(pResource, pParams) vidmemMapTo_DISPATCH(pResource, pParams) +#define vidmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) vidmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define vidmemGetRefCount(pResource) vidmemGetRefCount_DISPATCH(pResource) +#define vidmemAddAdditionalDependants(pClient, pResource, pReference) vidmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define vidmemControl_Prologue(pResource, pCallContext, pParams) vidmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define vidmemIsGpuMapAllowed(pMemory, pGpu) vidmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define vidmemUnmapFrom(pResource, pParams) vidmemUnmapFrom_DISPATCH(pResource, pParams) +#define vidmemControl_Epilogue(pResource, pCallContext, pParams) vidmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define vidmemControlLookup(pResource, pParams, ppEntry) vidmemControlLookup_DISPATCH(pResource, pParams, ppEntry) #define vidmemControl(pMemory, pCallContext, pParams) vidmemControl_DISPATCH(pMemory, pCallContext, pParams) #define vidmemUnmap(pMemory, pCallContext, pCpuMapping) vidmemUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define vidmemGetMemInterMapParams(pMemory, pParams) vidmemGetMemInterMapParams_DISPATCH(pMemory, pParams) #define vidmemGetMemoryMappingDescriptor(pMemory, ppMemDesc) vidmemGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define vidmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) vidmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) -#define vidmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) vidmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define vidmemControlFilter(pResource, pCallContext, pParams) vidmemControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define vidmemAddAdditionalDependants(pClient, pResource, pReference) vidmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define vidmemGetRefCount(pResource) vidmemGetRefCount_DISPATCH(pResource) -#define vidmemMapTo(pResource, pParams) vidmemMapTo_DISPATCH(pResource, pParams) +#define vidmemControlSerialization_Prologue(pResource, pCallContext, pParams) vidmemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define vidmemCanCopy(pStandardMemory) vidmemCanCopy_DISPATCH(pStandardMemory) -#define vidmemIsGpuMapAllowed(pMemory, pGpu) vidmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) -#define vidmemControl_Prologue(pResource, pCallContext, pParams) vidmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define vidmemIsReady(pMemory, bCopyConstructorContext) vidmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define vidmemPreDestruct(pResource) vidmemPreDestruct_DISPATCH(pResource) #define vidmemIsDuplicate(pMemory, hMemory, pDuplicate) vidmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) -#define vidmemUnmapFrom(pResource, pParams) vidmemUnmapFrom_DISPATCH(pResource, pParams) -#define vidmemControl_Epilogue(pResource, pCallContext, pParams) vidmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define vidmemControlLookup(pResource, pParams, ppEntry) vidmemControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define vidmemControlSerialization_Epilogue(pResource, pCallContext, pParams) vidmemControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define vidmemMap(pMemory, pCallContext, pParams, pCpuMapping) vidmemMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define vidmemAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) vidmemAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS vidmemCheckCopyPermissions_IMPL(struct VideoMemory *pVideoMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool); @@ -140,6 +144,46 @@ static inline NV_STATUS vidmemCheckMemInterUnmap_DISPATCH(struct VideoMemory *pM return pMemory->__vidmemCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } +static inline NvBool vidmemShareCallback_DISPATCH(struct VideoMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__vidmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS vidmemMapTo_DISPATCH(struct VideoMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__vidmemMapTo__(pResource, pParams); +} + +static inline NV_STATUS vidmemGetMapAddrSpace_DISPATCH(struct VideoMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__vidmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 vidmemGetRefCount_DISPATCH(struct VideoMemory *pResource) { + return pResource->__vidmemGetRefCount__(pResource); +} + +static inline void vidmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct VideoMemory *pResource, RsResourceRef *pReference) { + pResource->__vidmemAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS vidmemControl_Prologue_DISPATCH(struct VideoMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vidmemControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool vidmemIsGpuMapAllowed_DISPATCH(struct VideoMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__vidmemIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline NV_STATUS vidmemUnmapFrom_DISPATCH(struct VideoMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__vidmemUnmapFrom__(pResource, pParams); +} + +static inline void vidmemControl_Epilogue_DISPATCH(struct VideoMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__vidmemControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS vidmemControlLookup_DISPATCH(struct VideoMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__vidmemControlLookup__(pResource, pParams, ppEntry); +} + static inline NV_STATUS vidmemControl_DISPATCH(struct VideoMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pMemory->__vidmemControl__(pMemory, pCallContext, pParams); } @@ -156,42 +200,18 @@ static inline NV_STATUS vidmemGetMemoryMappingDescriptor_DISPATCH(struct VideoMe return pMemory->__vidmemGetMemoryMappingDescriptor__(pMemory, ppMemDesc); } -static inline NV_STATUS vidmemGetMapAddrSpace_DISPATCH(struct VideoMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pMemory->__vidmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvBool vidmemShareCallback_DISPATCH(struct VideoMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pResource->__vidmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); -} - static inline NV_STATUS vidmemControlFilter_DISPATCH(struct VideoMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__vidmemControlFilter__(pResource, pCallContext, pParams); } -static inline void vidmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct VideoMemory *pResource, RsResourceRef *pReference) { - pResource->__vidmemAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 vidmemGetRefCount_DISPATCH(struct VideoMemory *pResource) { - return pResource->__vidmemGetRefCount__(pResource); -} - -static inline NV_STATUS vidmemMapTo_DISPATCH(struct VideoMemory *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__vidmemMapTo__(pResource, pParams); +static inline NV_STATUS vidmemControlSerialization_Prologue_DISPATCH(struct VideoMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vidmemControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool vidmemCanCopy_DISPATCH(struct VideoMemory *pStandardMemory) { return pStandardMemory->__vidmemCanCopy__(pStandardMemory); } -static inline NvBool vidmemIsGpuMapAllowed_DISPATCH(struct VideoMemory *pMemory, struct OBJGPU *pGpu) { - return pMemory->__vidmemIsGpuMapAllowed__(pMemory, pGpu); -} - -static inline NV_STATUS vidmemControl_Prologue_DISPATCH(struct VideoMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__vidmemControl_Prologue__(pResource, pCallContext, pParams); -} - static inline NV_STATUS vidmemIsReady_DISPATCH(struct VideoMemory *pMemory, NvBool bCopyConstructorContext) { return pMemory->__vidmemIsReady__(pMemory, bCopyConstructorContext); } @@ -204,16 +224,8 @@ static inline NV_STATUS vidmemIsDuplicate_DISPATCH(struct VideoMemory *pMemory, return pMemory->__vidmemIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline NV_STATUS vidmemUnmapFrom_DISPATCH(struct VideoMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__vidmemUnmapFrom__(pResource, pParams); -} - -static inline void vidmemControl_Epilogue_DISPATCH(struct VideoMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__vidmemControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS vidmemControlLookup_DISPATCH(struct VideoMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__vidmemControlLookup__(pResource, pParams, ppEntry); +static inline void vidmemControlSerialization_Epilogue_DISPATCH(struct VideoMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__vidmemControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS vidmemMap_DISPATCH(struct VideoMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.c b/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.c new file mode 100644 index 000000000..b3eeb6e37 --- /dev/null +++ b/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.c @@ -0,0 +1,457 @@ +#define NVOC_VIDMEM_ACCESS_BIT_BUFFER_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_vidmem_access_bit_buffer_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0xebb6da = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_VidmemAccessBitBuffer; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RsResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResourceCommon; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_GpuResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_INotifier; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Notifier; + +void __nvoc_init_VidmemAccessBitBuffer(VidmemAccessBitBuffer*, RmHalspecOwner* ); +void __nvoc_init_funcTable_VidmemAccessBitBuffer(VidmemAccessBitBuffer*, RmHalspecOwner* ); +NV_STATUS __nvoc_ctor_VidmemAccessBitBuffer(VidmemAccessBitBuffer*, RmHalspecOwner* , CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +void __nvoc_init_dataField_VidmemAccessBitBuffer(VidmemAccessBitBuffer*, RmHalspecOwner* ); +void __nvoc_dtor_VidmemAccessBitBuffer(VidmemAccessBitBuffer*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_VidmemAccessBitBuffer; + +static const struct NVOC_RTTI __nvoc_rtti_VidmemAccessBitBuffer_VidmemAccessBitBuffer = { + /*pClassDef=*/ &__nvoc_class_def_VidmemAccessBitBuffer, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_VidmemAccessBitBuffer, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_VidmemAccessBitBuffer_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(VidmemAccessBitBuffer, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_VidmemAccessBitBuffer_RsResource = { + /*pClassDef=*/ &__nvoc_class_def_RsResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(VidmemAccessBitBuffer, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_VidmemAccessBitBuffer_RmResourceCommon = { + /*pClassDef=*/ &__nvoc_class_def_RmResourceCommon, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(VidmemAccessBitBuffer, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon), +}; + +static const struct NVOC_RTTI __nvoc_rtti_VidmemAccessBitBuffer_RmResource = { + /*pClassDef=*/ &__nvoc_class_def_RmResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(VidmemAccessBitBuffer, __nvoc_base_GpuResource.__nvoc_base_RmResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_VidmemAccessBitBuffer_GpuResource = { + /*pClassDef=*/ &__nvoc_class_def_GpuResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(VidmemAccessBitBuffer, __nvoc_base_GpuResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_VidmemAccessBitBuffer_INotifier = { + /*pClassDef=*/ &__nvoc_class_def_INotifier, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(VidmemAccessBitBuffer, __nvoc_base_Notifier.__nvoc_base_INotifier), +}; + +static const struct NVOC_RTTI __nvoc_rtti_VidmemAccessBitBuffer_Notifier = { + /*pClassDef=*/ &__nvoc_class_def_Notifier, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(VidmemAccessBitBuffer, __nvoc_base_Notifier), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_VidmemAccessBitBuffer = { + /*numRelatives=*/ 8, + /*relatives=*/ { + &__nvoc_rtti_VidmemAccessBitBuffer_VidmemAccessBitBuffer, + &__nvoc_rtti_VidmemAccessBitBuffer_Notifier, + &__nvoc_rtti_VidmemAccessBitBuffer_INotifier, + &__nvoc_rtti_VidmemAccessBitBuffer_GpuResource, + &__nvoc_rtti_VidmemAccessBitBuffer_RmResource, + &__nvoc_rtti_VidmemAccessBitBuffer_RmResourceCommon, + &__nvoc_rtti_VidmemAccessBitBuffer_RsResource, + &__nvoc_rtti_VidmemAccessBitBuffer_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_VidmemAccessBitBuffer = +{ + /*classInfo=*/ { + /*size=*/ sizeof(VidmemAccessBitBuffer), + /*classId=*/ classId(VidmemAccessBitBuffer), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "VidmemAccessBitBuffer", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_VidmemAccessBitBuffer, + /*pCastInfo=*/ &__nvoc_castinfo_VidmemAccessBitBuffer, + /*pExportInfo=*/ &__nvoc_export_info_VidmemAccessBitBuffer +}; + +static NvBool __nvoc_thunk_GpuResource_vidmemAccessBitBufShareCallback(struct VidmemAccessBitBuffer *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VidmemAccessBitBuffer_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RmResource_vidmemAccessBitBufCheckMemInterUnmap(struct VidmemAccessBitBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VidmemAccessBitBuffer_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_Notifier_vidmemAccessBitBufGetOrAllocNotifShare(struct VidmemAccessBitBuffer *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { + return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_VidmemAccessBitBuffer_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); +} + +static NV_STATUS __nvoc_thunk_RsResource_vidmemAccessBitBufMapTo(struct VidmemAccessBitBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vidmemAccessBitBufGetMapAddrSpace(struct VidmemAccessBitBuffer *pGpuResource, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VidmemAccessBitBuffer_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static void __nvoc_thunk_Notifier_vidmemAccessBitBufSetNotificationShare(struct VidmemAccessBitBuffer *pNotifier, struct NotifShare *pNotifShare) { + notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_VidmemAccessBitBuffer_Notifier.offset), pNotifShare); +} + +static NvU32 __nvoc_thunk_RsResource_vidmemAccessBitBufGetRefCount(struct VidmemAccessBitBuffer *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_vidmemAccessBitBufAddAdditionalDependants(struct RsClient *pClient, struct VidmemAccessBitBuffer *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_vidmemAccessBitBufControl_Prologue(struct VidmemAccessBitBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vidmemAccessBitBufGetRegBaseOffsetAndSize(struct VidmemAccessBitBuffer *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VidmemAccessBitBuffer_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vidmemAccessBitBufInternalControlForward(struct VidmemAccessBitBuffer *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VidmemAccessBitBuffer_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_vidmemAccessBitBufUnmapFrom(struct VidmemAccessBitBuffer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_vidmemAccessBitBufControl_Epilogue(struct VidmemAccessBitBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_vidmemAccessBitBufControlLookup(struct VidmemAccessBitBuffer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RsResource.offset), pParams, ppEntry); +} + +static NvHandle __nvoc_thunk_GpuResource_vidmemAccessBitBufGetInternalObjectHandle(struct VidmemAccessBitBuffer *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VidmemAccessBitBuffer_GpuResource.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vidmemAccessBitBufControl(struct VidmemAccessBitBuffer *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VidmemAccessBitBuffer_GpuResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vidmemAccessBitBufUnmap(struct VidmemAccessBitBuffer *pGpuResource, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VidmemAccessBitBuffer_GpuResource.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_RmResource_vidmemAccessBitBufGetMemInterMapParams(struct VidmemAccessBitBuffer *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VidmemAccessBitBuffer_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_vidmemAccessBitBufGetMemoryMappingDescriptor(struct VidmemAccessBitBuffer *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VidmemAccessBitBuffer_RmResource.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_vidmemAccessBitBufControlFilter(struct VidmemAccessBitBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_Notifier_vidmemAccessBitBufUnregisterEvent(struct VidmemAccessBitBuffer *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { + return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_VidmemAccessBitBuffer_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); +} + +static NV_STATUS __nvoc_thunk_RmResource_vidmemAccessBitBufControlSerialization_Prologue(struct VidmemAccessBitBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_RsResource_vidmemAccessBitBufCanCopy(struct VidmemAccessBitBuffer *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_vidmemAccessBitBufPreDestruct(struct VidmemAccessBitBuffer *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_vidmemAccessBitBufIsDuplicate(struct VidmemAccessBitBuffer *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_vidmemAccessBitBufControlSerialization_Epilogue(struct VidmemAccessBitBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RmResource.offset), pCallContext, pParams); +} + +static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_vidmemAccessBitBufGetNotificationListPtr(struct VidmemAccessBitBuffer *pNotifier) { + return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_VidmemAccessBitBuffer_Notifier.offset)); +} + +static struct NotifShare *__nvoc_thunk_Notifier_vidmemAccessBitBufGetNotificationShare(struct VidmemAccessBitBuffer *pNotifier) { + return notifyGetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_VidmemAccessBitBuffer_Notifier.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vidmemAccessBitBufMap(struct VidmemAccessBitBuffer *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return gpuresMap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VidmemAccessBitBuffer_GpuResource.offset), pCallContext, pParams, pCpuMapping); +} + +static NvBool __nvoc_thunk_RmResource_vidmemAccessBitBufAccessCallback(struct VidmemAccessBitBuffer *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RmResource.offset), pInvokingClient, pAllocParams, accessRight); +} + +#if !defined(NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG) +#define NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(x) (0) +#endif + +static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_VidmemAccessBitBuffer[] = +{ + { /* [0] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x160200u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) vidmemAccessBitBufCtrlCmdVidmemAccessBitDump_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x160200u) + /*flags=*/ 0x160200u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xc7630103u, + /*paramSize=*/ sizeof(NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DUMP_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_VidmemAccessBitBuffer.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "vidmemAccessBitBufCtrlCmdVidmemAccessBitDump" +#endif + }, + +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_VidmemAccessBitBuffer = +{ + /*numEntries=*/ 1, + /*pExportEntries=*/ __nvoc_exported_method_def_VidmemAccessBitBuffer +}; + +void __nvoc_dtor_GpuResource(GpuResource*); +void __nvoc_dtor_Notifier(Notifier*); +void __nvoc_dtor_VidmemAccessBitBuffer(VidmemAccessBitBuffer *pThis) { + __nvoc_vidmemAccessBitBufDestruct(pThis); + __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); + __nvoc_dtor_Notifier(&pThis->__nvoc_base_Notifier); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_VidmemAccessBitBuffer(VidmemAccessBitBuffer *pThis, RmHalspecOwner *pRmhalspecowner) { + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); +} + +NV_STATUS __nvoc_ctor_GpuResource(GpuResource* , CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); +NV_STATUS __nvoc_ctor_Notifier(Notifier* , CALL_CONTEXT *); +NV_STATUS __nvoc_ctor_VidmemAccessBitBuffer(VidmemAccessBitBuffer *pThis, RmHalspecOwner *pRmhalspecowner, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_GpuResource(&pThis->__nvoc_base_GpuResource, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_VidmemAccessBitBuffer_fail_GpuResource; + status = __nvoc_ctor_Notifier(&pThis->__nvoc_base_Notifier, arg_pCallContext); + if (status != NV_OK) goto __nvoc_ctor_VidmemAccessBitBuffer_fail_Notifier; + __nvoc_init_dataField_VidmemAccessBitBuffer(pThis, pRmhalspecowner); + + status = __nvoc_vidmemAccessBitBufConstruct(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_VidmemAccessBitBuffer_fail__init; + goto __nvoc_ctor_VidmemAccessBitBuffer_exit; // Success + +__nvoc_ctor_VidmemAccessBitBuffer_fail__init: + __nvoc_dtor_Notifier(&pThis->__nvoc_base_Notifier); +__nvoc_ctor_VidmemAccessBitBuffer_fail_Notifier: + __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); +__nvoc_ctor_VidmemAccessBitBuffer_fail_GpuResource: +__nvoc_ctor_VidmemAccessBitBuffer_exit: + + return status; +} + +static void __nvoc_init_funcTable_VidmemAccessBitBuffer_1(VidmemAccessBitBuffer *pThis, RmHalspecOwner *pRmhalspecowner) { + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x160200u) + pThis->__vidmemAccessBitBufCtrlCmdVidmemAccessBitDump__ = &vidmemAccessBitBufCtrlCmdVidmemAccessBitDump_IMPL; +#endif + + pThis->__vidmemAccessBitBufShareCallback__ = &__nvoc_thunk_GpuResource_vidmemAccessBitBufShareCallback; + + pThis->__vidmemAccessBitBufCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_vidmemAccessBitBufCheckMemInterUnmap; + + pThis->__vidmemAccessBitBufGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_vidmemAccessBitBufGetOrAllocNotifShare; + + pThis->__vidmemAccessBitBufMapTo__ = &__nvoc_thunk_RsResource_vidmemAccessBitBufMapTo; + + pThis->__vidmemAccessBitBufGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_vidmemAccessBitBufGetMapAddrSpace; + + pThis->__vidmemAccessBitBufSetNotificationShare__ = &__nvoc_thunk_Notifier_vidmemAccessBitBufSetNotificationShare; + + pThis->__vidmemAccessBitBufGetRefCount__ = &__nvoc_thunk_RsResource_vidmemAccessBitBufGetRefCount; + + pThis->__vidmemAccessBitBufAddAdditionalDependants__ = &__nvoc_thunk_RsResource_vidmemAccessBitBufAddAdditionalDependants; + + pThis->__vidmemAccessBitBufControl_Prologue__ = &__nvoc_thunk_RmResource_vidmemAccessBitBufControl_Prologue; + + pThis->__vidmemAccessBitBufGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_vidmemAccessBitBufGetRegBaseOffsetAndSize; + + pThis->__vidmemAccessBitBufInternalControlForward__ = &__nvoc_thunk_GpuResource_vidmemAccessBitBufInternalControlForward; + + pThis->__vidmemAccessBitBufUnmapFrom__ = &__nvoc_thunk_RsResource_vidmemAccessBitBufUnmapFrom; + + pThis->__vidmemAccessBitBufControl_Epilogue__ = &__nvoc_thunk_RmResource_vidmemAccessBitBufControl_Epilogue; + + pThis->__vidmemAccessBitBufControlLookup__ = &__nvoc_thunk_RsResource_vidmemAccessBitBufControlLookup; + + pThis->__vidmemAccessBitBufGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_vidmemAccessBitBufGetInternalObjectHandle; + + pThis->__vidmemAccessBitBufControl__ = &__nvoc_thunk_GpuResource_vidmemAccessBitBufControl; + + pThis->__vidmemAccessBitBufUnmap__ = &__nvoc_thunk_GpuResource_vidmemAccessBitBufUnmap; + + pThis->__vidmemAccessBitBufGetMemInterMapParams__ = &__nvoc_thunk_RmResource_vidmemAccessBitBufGetMemInterMapParams; + + pThis->__vidmemAccessBitBufGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_vidmemAccessBitBufGetMemoryMappingDescriptor; + + pThis->__vidmemAccessBitBufControlFilter__ = &__nvoc_thunk_RsResource_vidmemAccessBitBufControlFilter; + + pThis->__vidmemAccessBitBufUnregisterEvent__ = &__nvoc_thunk_Notifier_vidmemAccessBitBufUnregisterEvent; + + pThis->__vidmemAccessBitBufControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_vidmemAccessBitBufControlSerialization_Prologue; + + pThis->__vidmemAccessBitBufCanCopy__ = &__nvoc_thunk_RsResource_vidmemAccessBitBufCanCopy; + + pThis->__vidmemAccessBitBufPreDestruct__ = &__nvoc_thunk_RsResource_vidmemAccessBitBufPreDestruct; + + pThis->__vidmemAccessBitBufIsDuplicate__ = &__nvoc_thunk_RsResource_vidmemAccessBitBufIsDuplicate; + + pThis->__vidmemAccessBitBufControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_vidmemAccessBitBufControlSerialization_Epilogue; + + pThis->__vidmemAccessBitBufGetNotificationListPtr__ = &__nvoc_thunk_Notifier_vidmemAccessBitBufGetNotificationListPtr; + + pThis->__vidmemAccessBitBufGetNotificationShare__ = &__nvoc_thunk_Notifier_vidmemAccessBitBufGetNotificationShare; + + pThis->__vidmemAccessBitBufMap__ = &__nvoc_thunk_GpuResource_vidmemAccessBitBufMap; + + pThis->__vidmemAccessBitBufAccessCallback__ = &__nvoc_thunk_RmResource_vidmemAccessBitBufAccessCallback; +} + +void __nvoc_init_funcTable_VidmemAccessBitBuffer(VidmemAccessBitBuffer *pThis, RmHalspecOwner *pRmhalspecowner) { + __nvoc_init_funcTable_VidmemAccessBitBuffer_1(pThis, pRmhalspecowner); +} + +void __nvoc_init_GpuResource(GpuResource*); +void __nvoc_init_Notifier(Notifier*); +void __nvoc_init_VidmemAccessBitBuffer(VidmemAccessBitBuffer *pThis, RmHalspecOwner *pRmhalspecowner) { + pThis->__nvoc_pbase_VidmemAccessBitBuffer = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; + pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource; + pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; + pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource; + pThis->__nvoc_pbase_GpuResource = &pThis->__nvoc_base_GpuResource; + pThis->__nvoc_pbase_INotifier = &pThis->__nvoc_base_Notifier.__nvoc_base_INotifier; + pThis->__nvoc_pbase_Notifier = &pThis->__nvoc_base_Notifier; + __nvoc_init_GpuResource(&pThis->__nvoc_base_GpuResource); + __nvoc_init_Notifier(&pThis->__nvoc_base_Notifier); + __nvoc_init_funcTable_VidmemAccessBitBuffer(pThis, pRmhalspecowner); +} + +NV_STATUS __nvoc_objCreate_VidmemAccessBitBuffer(VidmemAccessBitBuffer **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status; + Object *pParentObj; + VidmemAccessBitBuffer *pThis; + RmHalspecOwner *pRmhalspecowner; + + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(VidmemAccessBitBuffer), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + portMemSet(pThis, 0, sizeof(VidmemAccessBitBuffer)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_VidmemAccessBitBuffer); + + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; + } + + if ((pRmhalspecowner = dynamicCast(pParent, RmHalspecOwner)) == NULL) + pRmhalspecowner = objFindAncestorOfType(RmHalspecOwner, pParent); + NV_ASSERT_OR_RETURN(pRmhalspecowner != NULL, NV_ERR_INVALID_ARGUMENT); + + __nvoc_init_VidmemAccessBitBuffer(pThis, pRmhalspecowner); + status = __nvoc_ctor_VidmemAccessBitBuffer(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_objCreate_VidmemAccessBitBuffer_cleanup; + + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_VidmemAccessBitBuffer_cleanup: + // do not call destructors here since the constructor already called them + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(VidmemAccessBitBuffer)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_VidmemAccessBitBuffer(VidmemAccessBitBuffer **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + CALL_CONTEXT * arg_pCallContext = va_arg(args, CALL_CONTEXT *); + struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + + status = __nvoc_objCreate_VidmemAccessBitBuffer(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); + + return status; +} + diff --git a/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.h b/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.h index 946c03f26..ef9991398 100644 --- a/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.h +++ b/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.h @@ -93,12 +93,11 @@ struct VidmemAccessBitBuffer { struct INotifier *__nvoc_pbase_INotifier; struct Notifier *__nvoc_pbase_Notifier; struct VidmemAccessBitBuffer *__nvoc_pbase_VidmemAccessBitBuffer; - NV_STATUS (*__vidmemAccessBitBufCopyConstruct__)(struct VidmemAccessBitBuffer *, CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); NV_STATUS (*__vidmemAccessBitBufCtrlCmdVidmemAccessBitDump__)(struct VidmemAccessBitBuffer *, NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DUMP_PARAMS *); NvBool (*__vidmemAccessBitBufShareCallback__)(struct VidmemAccessBitBuffer *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__vidmemAccessBitBufMapTo__)(struct VidmemAccessBitBuffer *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__vidmemAccessBitBufGetOrAllocNotifShare__)(struct VidmemAccessBitBuffer *, NvHandle, NvHandle, struct NotifShare **); NV_STATUS (*__vidmemAccessBitBufCheckMemInterUnmap__)(struct VidmemAccessBitBuffer *, NvBool); + NV_STATUS (*__vidmemAccessBitBufGetOrAllocNotifShare__)(struct VidmemAccessBitBuffer *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__vidmemAccessBitBufMapTo__)(struct VidmemAccessBitBuffer *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__vidmemAccessBitBufGetMapAddrSpace__)(struct VidmemAccessBitBuffer *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); void (*__vidmemAccessBitBufSetNotificationShare__)(struct VidmemAccessBitBuffer *, struct NotifShare *); NvU32 (*__vidmemAccessBitBufGetRefCount__)(struct VidmemAccessBitBuffer *); @@ -116,9 +115,11 @@ struct VidmemAccessBitBuffer { NV_STATUS (*__vidmemAccessBitBufGetMemoryMappingDescriptor__)(struct VidmemAccessBitBuffer *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__vidmemAccessBitBufControlFilter__)(struct VidmemAccessBitBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vidmemAccessBitBufUnregisterEvent__)(struct VidmemAccessBitBuffer *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__vidmemAccessBitBufControlSerialization_Prologue__)(struct VidmemAccessBitBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__vidmemAccessBitBufCanCopy__)(struct VidmemAccessBitBuffer *); void (*__vidmemAccessBitBufPreDestruct__)(struct VidmemAccessBitBuffer *); NV_STATUS (*__vidmemAccessBitBufIsDuplicate__)(struct VidmemAccessBitBuffer *, NvHandle, NvBool *); + void (*__vidmemAccessBitBufControlSerialization_Epilogue__)(struct VidmemAccessBitBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__vidmemAccessBitBufGetNotificationListPtr__)(struct VidmemAccessBitBuffer *); struct NotifShare *(*__vidmemAccessBitBufGetNotificationShare__)(struct VidmemAccessBitBuffer *); NV_STATUS (*__vidmemAccessBitBufMap__)(struct VidmemAccessBitBuffer *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -153,13 +154,11 @@ NV_STATUS __nvoc_objCreate_VidmemAccessBitBuffer(VidmemAccessBitBuffer**, Dynami #define __objCreate_VidmemAccessBitBuffer(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ __nvoc_objCreate_VidmemAccessBitBuffer((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) -#define vidmemAccessBitBufCopyConstruct(pVidmemAccessBitBuffer, pCallContext, pParams) vidmemAccessBitBufCopyConstruct_DISPATCH(pVidmemAccessBitBuffer, pCallContext, pParams) -#define vidmemAccessBitBufCopyConstruct_HAL(pVidmemAccessBitBuffer, pCallContext, pParams) vidmemAccessBitBufCopyConstruct_DISPATCH(pVidmemAccessBitBuffer, pCallContext, pParams) #define vidmemAccessBitBufCtrlCmdVidmemAccessBitDump(pVidmemAccessBitBuffer, pParams) vidmemAccessBitBufCtrlCmdVidmemAccessBitDump_DISPATCH(pVidmemAccessBitBuffer, pParams) #define vidmemAccessBitBufShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) vidmemAccessBitBufShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) -#define vidmemAccessBitBufMapTo(pResource, pParams) vidmemAccessBitBufMapTo_DISPATCH(pResource, pParams) -#define vidmemAccessBitBufGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) vidmemAccessBitBufGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) #define vidmemAccessBitBufCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) vidmemAccessBitBufCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define vidmemAccessBitBufGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) vidmemAccessBitBufGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define vidmemAccessBitBufMapTo(pResource, pParams) vidmemAccessBitBufMapTo_DISPATCH(pResource, pParams) #define vidmemAccessBitBufGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) vidmemAccessBitBufGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) #define vidmemAccessBitBufSetNotificationShare(pNotifier, pNotifShare) vidmemAccessBitBufSetNotificationShare_DISPATCH(pNotifier, pNotifShare) #define vidmemAccessBitBufGetRefCount(pResource) vidmemAccessBitBufGetRefCount_DISPATCH(pResource) @@ -177,9 +176,11 @@ NV_STATUS __nvoc_objCreate_VidmemAccessBitBuffer(VidmemAccessBitBuffer**, Dynami #define vidmemAccessBitBufGetMemoryMappingDescriptor(pRmResource, ppMemDesc) vidmemAccessBitBufGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define vidmemAccessBitBufControlFilter(pResource, pCallContext, pParams) vidmemAccessBitBufControlFilter_DISPATCH(pResource, pCallContext, pParams) #define vidmemAccessBitBufUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) vidmemAccessBitBufUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define vidmemAccessBitBufControlSerialization_Prologue(pResource, pCallContext, pParams) vidmemAccessBitBufControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define vidmemAccessBitBufCanCopy(pResource) vidmemAccessBitBufCanCopy_DISPATCH(pResource) #define vidmemAccessBitBufPreDestruct(pResource) vidmemAccessBitBufPreDestruct_DISPATCH(pResource) #define vidmemAccessBitBufIsDuplicate(pResource, hMemory, pDuplicate) vidmemAccessBitBufIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define vidmemAccessBitBufControlSerialization_Epilogue(pResource, pCallContext, pParams) vidmemAccessBitBufControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define vidmemAccessBitBufGetNotificationListPtr(pNotifier) vidmemAccessBitBufGetNotificationListPtr_DISPATCH(pNotifier) #define vidmemAccessBitBufGetNotificationShare(pNotifier) vidmemAccessBitBufGetNotificationShare_DISPATCH(pNotifier) #define vidmemAccessBitBufMap(pGpuResource, pCallContext, pParams, pCpuMapping) vidmemAccessBitBufMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -204,14 +205,6 @@ static inline void vidmemAccessBitBufDestruct_b3696a(struct VidmemAccessBitBuffe #define __nvoc_vidmemAccessBitBufDestruct(pVidmemAccessBitBuffer) vidmemAccessBitBufDestruct_b3696a(pVidmemAccessBitBuffer) -static inline NV_STATUS vidmemAccessBitBufCopyConstruct_56cd7a(struct VidmemAccessBitBuffer *pVidmemAccessBitBuffer, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { - return NV_OK; -} - -static inline NV_STATUS vidmemAccessBitBufCopyConstruct_DISPATCH(struct VidmemAccessBitBuffer *pVidmemAccessBitBuffer, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { - return pVidmemAccessBitBuffer->__vidmemAccessBitBufCopyConstruct__(pVidmemAccessBitBuffer, pCallContext, pParams); -} - NV_STATUS vidmemAccessBitBufCtrlCmdVidmemAccessBitDump_IMPL(struct VidmemAccessBitBuffer *pVidmemAccessBitBuffer, NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DUMP_PARAMS *pParams); static inline NV_STATUS vidmemAccessBitBufCtrlCmdVidmemAccessBitDump_DISPATCH(struct VidmemAccessBitBuffer *pVidmemAccessBitBuffer, NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DUMP_PARAMS *pParams) { @@ -222,16 +215,16 @@ static inline NvBool vidmemAccessBitBufShareCallback_DISPATCH(struct VidmemAcces return pGpuResource->__vidmemAccessBitBufShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS vidmemAccessBitBufMapTo_DISPATCH(struct VidmemAccessBitBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__vidmemAccessBitBufMapTo__(pResource, pParams); +static inline NV_STATUS vidmemAccessBitBufCheckMemInterUnmap_DISPATCH(struct VidmemAccessBitBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__vidmemAccessBitBufCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } static inline NV_STATUS vidmemAccessBitBufGetOrAllocNotifShare_DISPATCH(struct VidmemAccessBitBuffer *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { return pNotifier->__vidmemAccessBitBufGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); } -static inline NV_STATUS vidmemAccessBitBufCheckMemInterUnmap_DISPATCH(struct VidmemAccessBitBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__vidmemAccessBitBufCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +static inline NV_STATUS vidmemAccessBitBufMapTo_DISPATCH(struct VidmemAccessBitBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__vidmemAccessBitBufMapTo__(pResource, pParams); } static inline NV_STATUS vidmemAccessBitBufGetMapAddrSpace_DISPATCH(struct VidmemAccessBitBuffer *pGpuResource, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -302,6 +295,10 @@ static inline NV_STATUS vidmemAccessBitBufUnregisterEvent_DISPATCH(struct Vidmem return pNotifier->__vidmemAccessBitBufUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); } +static inline NV_STATUS vidmemAccessBitBufControlSerialization_Prologue_DISPATCH(struct VidmemAccessBitBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vidmemAccessBitBufControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + static inline NvBool vidmemAccessBitBufCanCopy_DISPATCH(struct VidmemAccessBitBuffer *pResource) { return pResource->__vidmemAccessBitBufCanCopy__(pResource); } @@ -314,6 +311,10 @@ static inline NV_STATUS vidmemAccessBitBufIsDuplicate_DISPATCH(struct VidmemAcce return pResource->__vidmemAccessBitBufIsDuplicate__(pResource, hMemory, pDuplicate); } +static inline void vidmemAccessBitBufControlSerialization_Epilogue_DISPATCH(struct VidmemAccessBitBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__vidmemAccessBitBufControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline PEVENTNOTIFICATION *vidmemAccessBitBufGetNotificationListPtr_DISPATCH(struct VidmemAccessBitBuffer *pNotifier) { return pNotifier->__vidmemAccessBitBufGetNotificationListPtr__(pNotifier); } diff --git a/src/nvidia/generated/g_virt_mem_allocator_nvoc.c b/src/nvidia/generated/g_virt_mem_allocator_nvoc.c index 4064f00a1..41410c4b9 100644 --- a/src/nvidia/generated/g_virt_mem_allocator_nvoc.c +++ b/src/nvidia/generated/g_virt_mem_allocator_nvoc.c @@ -78,10 +78,6 @@ static NV_STATUS __nvoc_thunk_VirtMemAllocator_engstateStatePostLoad(struct OBJG return dmaStatePostLoad(pGpu, (struct VirtMemAllocator *)(((unsigned char *)pDma) - __nvoc_rtti_VirtMemAllocator_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_dmaReconcileTunableState(POBJGPU pGpu, struct VirtMemAllocator *pEngstate, void *pTunableState) { - return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_VirtMemAllocator_OBJENGSTATE.offset), pTunableState); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_dmaStateLoad(POBJGPU pGpu, struct VirtMemAllocator *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_VirtMemAllocator_OBJENGSTATE.offset), arg0); } @@ -122,26 +118,6 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_dmaStatePreInitUnlocked(POBJGPU pGpu, return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_VirtMemAllocator_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_dmaGetTunableState(POBJGPU pGpu, struct VirtMemAllocator *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_VirtMemAllocator_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_dmaCompareTunableState(POBJGPU pGpu, struct VirtMemAllocator *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_VirtMemAllocator_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static void __nvoc_thunk_OBJENGSTATE_dmaFreeTunableState(POBJGPU pGpu, struct VirtMemAllocator *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_VirtMemAllocator_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_dmaAllocTunableState(POBJGPU pGpu, struct VirtMemAllocator *pEngstate, void **ppTunableState) { - return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_VirtMemAllocator_OBJENGSTATE.offset), ppTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_dmaSetTunableState(POBJGPU pGpu, struct VirtMemAllocator *pEngstate, void *pTunableState) { - return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_VirtMemAllocator_OBJENGSTATE.offset), pTunableState); -} - static NvBool __nvoc_thunk_OBJENGSTATE_dmaIsPresent(POBJGPU pGpu, struct VirtMemAllocator *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_VirtMemAllocator_OBJENGSTATE.offset)); } @@ -266,8 +242,6 @@ static void __nvoc_init_funcTable_VirtMemAllocator_1(VirtMemAllocator *pThis, Rm pThis->__nvoc_base_OBJENGSTATE.__engstateStatePostLoad__ = &__nvoc_thunk_VirtMemAllocator_engstateStatePostLoad; - pThis->__dmaReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_dmaReconcileTunableState; - pThis->__dmaStateLoad__ = &__nvoc_thunk_OBJENGSTATE_dmaStateLoad; pThis->__dmaStateUnload__ = &__nvoc_thunk_OBJENGSTATE_dmaStateUnload; @@ -288,16 +262,6 @@ static void __nvoc_init_funcTable_VirtMemAllocator_1(VirtMemAllocator *pThis, Rm pThis->__dmaStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_dmaStatePreInitUnlocked; - pThis->__dmaGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_dmaGetTunableState; - - pThis->__dmaCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_dmaCompareTunableState; - - pThis->__dmaFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_dmaFreeTunableState; - - pThis->__dmaAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_dmaAllocTunableState; - - pThis->__dmaSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_dmaSetTunableState; - pThis->__dmaIsPresent__ = &__nvoc_thunk_OBJENGSTATE_dmaIsPresent; } @@ -320,13 +284,16 @@ NV_STATUS __nvoc_objCreate_VirtMemAllocator(VirtMemAllocator **ppThis, Dynamic * VirtMemAllocator *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(VirtMemAllocator)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(VirtMemAllocator), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(VirtMemAllocator)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_VirtMemAllocator); + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -346,11 +313,17 @@ NV_STATUS __nvoc_objCreate_VirtMemAllocator(VirtMemAllocator **ppThis, Dynamic * if (status != NV_OK) goto __nvoc_objCreate_VirtMemAllocator_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_VirtMemAllocator_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(VirtMemAllocator)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_virt_mem_allocator_nvoc.h b/src/nvidia/generated/g_virt_mem_allocator_nvoc.h index c607e4e06..1f40acc80 100644 --- a/src/nvidia/generated/g_virt_mem_allocator_nvoc.h +++ b/src/nvidia/generated/g_virt_mem_allocator_nvoc.h @@ -104,7 +104,6 @@ struct VirtMemAllocator { NV_STATUS (*__dmaAllocBar1P2PMapping__)(struct OBJGPU *, struct VirtMemAllocator *, DMA_BAR1P2P_MAPPING_PRARAMS *); void (*__dmaFreeBar1P2PMapping__)(struct VirtMemAllocator *, CLI_DMA_MAPPING_INFO *); NV_STATUS (*__dmaStatePostLoad__)(struct OBJGPU *, struct VirtMemAllocator *, NvU32); - NV_STATUS (*__dmaReconcileTunableState__)(POBJGPU, struct VirtMemAllocator *, void *); NV_STATUS (*__dmaStateLoad__)(POBJGPU, struct VirtMemAllocator *, NvU32); NV_STATUS (*__dmaStateUnload__)(POBJGPU, struct VirtMemAllocator *, NvU32); NV_STATUS (*__dmaStatePreLoad__)(POBJGPU, struct VirtMemAllocator *, NvU32); @@ -115,11 +114,6 @@ struct VirtMemAllocator { void (*__dmaInitMissing__)(POBJGPU, struct VirtMemAllocator *); NV_STATUS (*__dmaStatePreInitLocked__)(POBJGPU, struct VirtMemAllocator *); NV_STATUS (*__dmaStatePreInitUnlocked__)(POBJGPU, struct VirtMemAllocator *); - NV_STATUS (*__dmaGetTunableState__)(POBJGPU, struct VirtMemAllocator *, void *); - NV_STATUS (*__dmaCompareTunableState__)(POBJGPU, struct VirtMemAllocator *, void *, void *); - void (*__dmaFreeTunableState__)(POBJGPU, struct VirtMemAllocator *, void *); - NV_STATUS (*__dmaAllocTunableState__)(POBJGPU, struct VirtMemAllocator *, void **); - NV_STATUS (*__dmaSetTunableState__)(POBJGPU, struct VirtMemAllocator *, void *); NvBool (*__dmaIsPresent__)(POBJGPU, struct VirtMemAllocator *); NvBool PDB_PROP_DMA_MMU_INVALIDATE_DISABLE; NvBool PDB_PROP_DMA_ENFORCE_32BIT_POINTER; @@ -189,7 +183,6 @@ NV_STATUS __nvoc_objCreate_VirtMemAllocator(VirtMemAllocator**, Dynamic*, NvU32) #define dmaFreeBar1P2PMapping_HAL(pDma, arg0) dmaFreeBar1P2PMapping_DISPATCH(pDma, arg0) #define dmaStatePostLoad(pGpu, pDma, arg0) dmaStatePostLoad_DISPATCH(pGpu, pDma, arg0) #define dmaStatePostLoad_HAL(pGpu, pDma, arg0) dmaStatePostLoad_DISPATCH(pGpu, pDma, arg0) -#define dmaReconcileTunableState(pGpu, pEngstate, pTunableState) dmaReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define dmaStateLoad(pGpu, pEngstate, arg0) dmaStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define dmaStateUnload(pGpu, pEngstate, arg0) dmaStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define dmaStatePreLoad(pGpu, pEngstate, arg0) dmaStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) @@ -200,11 +193,6 @@ NV_STATUS __nvoc_objCreate_VirtMemAllocator(VirtMemAllocator**, Dynamic*, NvU32) #define dmaInitMissing(pGpu, pEngstate) dmaInitMissing_DISPATCH(pGpu, pEngstate) #define dmaStatePreInitLocked(pGpu, pEngstate) dmaStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define dmaStatePreInitUnlocked(pGpu, pEngstate) dmaStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define dmaGetTunableState(pGpu, pEngstate, pTunableState) dmaGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define dmaCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) dmaCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define dmaFreeTunableState(pGpu, pEngstate, pTunableState) dmaFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define dmaAllocTunableState(pGpu, pEngstate, ppTunableState) dmaAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) -#define dmaSetTunableState(pGpu, pEngstate, pTunableState) dmaSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define dmaIsPresent(pGpu, pEngstate) dmaIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS dmaInit_GM107(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma); @@ -284,11 +272,11 @@ static inline NV_STATUS dmaFreeMapping(struct OBJGPU *pGpu, struct VirtMemAlloca #define dmaFreeMapping_HAL(pGpu, pDma, arg0, arg1, arg2, arg3, arg4) dmaFreeMapping(pGpu, pDma, arg0, arg1, arg2, arg3, arg4) -NV_STATUS dmaUpdateVASpace_GF100(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, struct OBJVASPACE *pVAS, MEMORY_DESCRIPTOR *pMemDesc, NvU8 *tgtPteMem, NvU64 vAddr, NvU64 vAddrLimit, NvU32 flags, DMA_PAGE_ARRAY *pPageArray, NvU32 overmapPteMod, COMPR_INFO *pComprInfo, NvU64 surfaceOffset, NvU32 valid, NvU32 aperture, NvU32 peer, NvU64 fabricAddr, NvU32 deferInvalidate, NvBool bSparse, NvU32 pageSize); +NV_STATUS dmaUpdateVASpace_GF100(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, struct OBJVASPACE *pVAS, MEMORY_DESCRIPTOR *pMemDesc, NvU8 *tgtPteMem, NvU64 vAddr, NvU64 vAddrLimit, NvU32 flags, DMA_PAGE_ARRAY *pPageArray, NvU32 overmapPteMod, COMPR_INFO *pComprInfo, NvU64 surfaceOffset, NvU32 valid, NvU32 aperture, NvU32 peer, NvU64 fabricAddr, NvU32 deferInvalidate, NvBool bSparse, NvU64 pageSize); #ifdef __nvoc_virt_mem_allocator_h_disabled -static inline NV_STATUS dmaUpdateVASpace(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, struct OBJVASPACE *pVAS, MEMORY_DESCRIPTOR *pMemDesc, NvU8 *tgtPteMem, NvU64 vAddr, NvU64 vAddrLimit, NvU32 flags, DMA_PAGE_ARRAY *pPageArray, NvU32 overmapPteMod, COMPR_INFO *pComprInfo, NvU64 surfaceOffset, NvU32 valid, NvU32 aperture, NvU32 peer, NvU64 fabricAddr, NvU32 deferInvalidate, NvBool bSparse, NvU32 pageSize) { +static inline NV_STATUS dmaUpdateVASpace(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, struct OBJVASPACE *pVAS, MEMORY_DESCRIPTOR *pMemDesc, NvU8 *tgtPteMem, NvU64 vAddr, NvU64 vAddrLimit, NvU32 flags, DMA_PAGE_ARRAY *pPageArray, NvU32 overmapPteMod, COMPR_INFO *pComprInfo, NvU64 surfaceOffset, NvU32 valid, NvU32 aperture, NvU32 peer, NvU64 fabricAddr, NvU32 deferInvalidate, NvBool bSparse, NvU64 pageSize) { NV_ASSERT_FAILED_PRECOMP("VirtMemAllocator was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -421,10 +409,6 @@ static inline NV_STATUS dmaStatePostLoad_DISPATCH(struct OBJGPU *pGpu, struct Vi return pDma->__dmaStatePostLoad__(pGpu, pDma, arg0); } -static inline NV_STATUS dmaReconcileTunableState_DISPATCH(POBJGPU pGpu, struct VirtMemAllocator *pEngstate, void *pTunableState) { - return pEngstate->__dmaReconcileTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NV_STATUS dmaStateLoad_DISPATCH(POBJGPU pGpu, struct VirtMemAllocator *pEngstate, NvU32 arg0) { return pEngstate->__dmaStateLoad__(pGpu, pEngstate, arg0); } @@ -465,26 +449,6 @@ static inline NV_STATUS dmaStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct Vi return pEngstate->__dmaStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS dmaGetTunableState_DISPATCH(POBJGPU pGpu, struct VirtMemAllocator *pEngstate, void *pTunableState) { - return pEngstate->__dmaGetTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS dmaCompareTunableState_DISPATCH(POBJGPU pGpu, struct VirtMemAllocator *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__dmaCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline void dmaFreeTunableState_DISPATCH(POBJGPU pGpu, struct VirtMemAllocator *pEngstate, void *pTunableState) { - pEngstate->__dmaFreeTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS dmaAllocTunableState_DISPATCH(POBJGPU pGpu, struct VirtMemAllocator *pEngstate, void **ppTunableState) { - return pEngstate->__dmaAllocTunableState__(pGpu, pEngstate, ppTunableState); -} - -static inline NV_STATUS dmaSetTunableState_DISPATCH(POBJGPU pGpu, struct VirtMemAllocator *pEngstate, void *pTunableState) { - return pEngstate->__dmaSetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline NvBool dmaIsPresent_DISPATCH(POBJGPU pGpu, struct VirtMemAllocator *pEngstate) { return pEngstate->__dmaIsPresent__(pGpu, pEngstate); } diff --git a/src/nvidia/generated/g_virt_mem_mgr_nvoc.c b/src/nvidia/generated/g_virt_mem_mgr_nvoc.c index 4cb2434d4..2adccb09c 100644 --- a/src/nvidia/generated/g_virt_mem_mgr_nvoc.c +++ b/src/nvidia/generated/g_virt_mem_mgr_nvoc.c @@ -108,13 +108,16 @@ NV_STATUS __nvoc_objCreate_OBJVMM(OBJVMM **ppThis, Dynamic *pParent, NvU32 creat Object *pParentObj; OBJVMM *pThis; - pThis = portMemAllocNonPaged(sizeof(OBJVMM)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJVMM), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(OBJVMM)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJVMM); + pThis->__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -130,11 +133,17 @@ NV_STATUS __nvoc_objCreate_OBJVMM(OBJVMM **ppThis, Dynamic *pParent, NvU32 creat if (status != NV_OK) goto __nvoc_objCreate_OBJVMM_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_OBJVMM_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(OBJVMM)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_virt_mem_range_nvoc.c b/src/nvidia/generated/g_virt_mem_range_nvoc.c index bb47fc67d..2884982ae 100644 --- a/src/nvidia/generated/g_virt_mem_range_nvoc.c +++ b/src/nvidia/generated/g_virt_mem_range_nvoc.c @@ -119,32 +119,12 @@ static NV_STATUS __nvoc_thunk_VirtualMemory_vmrangeMapTo(struct VirtualMemoryRan return virtmemMapTo((struct VirtualMemory *)(((unsigned char *)pVirtualMemory) + __nvoc_rtti_VirtualMemoryRange_VirtualMemory.offset), pParams); } -static NV_STATUS __nvoc_thunk_Memory_vmrangeControl(struct VirtualMemoryRange *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_Memory_vmrangeGetMemInterMapParams(struct VirtualMemoryRange *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_Memory_vmrangeUnmap(struct VirtualMemoryRange *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), pCallContext, pCpuMapping); -} - -static NV_STATUS __nvoc_thunk_Memory_vmrangeGetMapAddrSpace(struct VirtualMemoryRange *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), pCallContext, mapFlags, pAddrSpace); -} - static NvBool __nvoc_thunk_RmResource_vmrangeShareCallback(struct VirtualMemoryRange *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); } -static NV_STATUS __nvoc_thunk_Memory_vmrangeGetMemoryMappingDescriptor(struct VirtualMemoryRange *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { - return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), ppMemDesc); -} - -static NV_STATUS __nvoc_thunk_RsResource_vmrangeControlFilter(struct VirtualMemoryRange *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RsResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_Memory_vmrangeGetMapAddrSpace(struct VirtualMemoryRange *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), pCallContext, mapFlags, pAddrSpace); } static NvU32 __nvoc_thunk_RsResource_vmrangeGetRefCount(struct VirtualMemoryRange *pResource) { @@ -155,38 +135,18 @@ static void __nvoc_thunk_RsResource_vmrangeAddAdditionalDependants(struct RsClie resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RsResource.offset), pReference); } -static NvBool __nvoc_thunk_StandardMemory_vmrangeCanCopy(struct VirtualMemoryRange *pStandardMemory) { - return stdmemCanCopy((struct StandardMemory *)(((unsigned char *)pStandardMemory) + __nvoc_rtti_VirtualMemoryRange_StandardMemory.offset)); +static NV_STATUS __nvoc_thunk_RmResource_vmrangeControl_Prologue(struct VirtualMemoryRange *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_Memory_vmrangeIsGpuMapAllowed(struct VirtualMemoryRange *pMemory, struct OBJGPU *pGpu) { return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), pGpu); } -static NV_STATUS __nvoc_thunk_RmResource_vmrangeControl_Prologue(struct VirtualMemoryRange *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_Memory_vmrangeIsReady(struct VirtualMemoryRange *pMemory, NvBool bCopyConstructorContext) { - return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), bCopyConstructorContext); -} - static NV_STATUS __nvoc_thunk_VirtualMemory_vmrangeUnmapFrom(struct VirtualMemoryRange *pVirtualMemory, struct RS_RES_UNMAP_FROM_PARAMS *pParams) { return virtmemUnmapFrom((struct VirtualMemory *)(((unsigned char *)pVirtualMemory) + __nvoc_rtti_VirtualMemoryRange_VirtualMemory.offset), pParams); } -static NV_STATUS __nvoc_thunk_Memory_vmrangeCheckCopyPermissions(struct VirtualMemoryRange *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), pDstGpu, hDstClientNvBool); -} - -static NV_STATUS __nvoc_thunk_Memory_vmrangeIsDuplicate(struct VirtualMemoryRange *pMemory, NvHandle hMemory, NvBool *pDuplicate) { - return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), hMemory, pDuplicate); -} - -static void __nvoc_thunk_RsResource_vmrangePreDestruct(struct VirtualMemoryRange *pResource) { - resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RsResource.offset)); -} - static void __nvoc_thunk_RmResource_vmrangeControl_Epilogue(struct VirtualMemoryRange *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RmResource.offset), pCallContext, pParams); } @@ -195,6 +155,54 @@ static NV_STATUS __nvoc_thunk_RsResource_vmrangeControlLookup(struct VirtualMemo return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RsResource.offset), pParams, ppEntry); } +static NV_STATUS __nvoc_thunk_Memory_vmrangeControl(struct VirtualMemoryRange *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_vmrangeUnmap(struct VirtualMemoryRange *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_Memory_vmrangeGetMemInterMapParams(struct VirtualMemoryRange *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_vmrangeGetMemoryMappingDescriptor(struct VirtualMemoryRange *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_vmrangeControlFilter(struct VirtualMemoryRange *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_vmrangeControlSerialization_Prologue(struct VirtualMemoryRange *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_StandardMemory_vmrangeCanCopy(struct VirtualMemoryRange *pStandardMemory) { + return stdmemCanCopy((struct StandardMemory *)(((unsigned char *)pStandardMemory) + __nvoc_rtti_VirtualMemoryRange_StandardMemory.offset)); +} + +static NV_STATUS __nvoc_thunk_Memory_vmrangeIsReady(struct VirtualMemoryRange *pMemory, NvBool bCopyConstructorContext) { + return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), bCopyConstructorContext); +} + +static NV_STATUS __nvoc_thunk_Memory_vmrangeCheckCopyPermissions(struct VirtualMemoryRange *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), pDstGpu, hDstClientNvBool); +} + +static void __nvoc_thunk_RsResource_vmrangePreDestruct(struct VirtualMemoryRange *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_Memory_vmrangeIsDuplicate(struct VirtualMemoryRange *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_vmrangeControlSerialization_Epilogue(struct VirtualMemoryRange *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RmResource.offset), pCallContext, pParams); +} + static NV_STATUS __nvoc_thunk_Memory_vmrangeMap(struct VirtualMemoryRange *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return memMap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), pCallContext, pParams, pCpuMapping); } @@ -245,44 +253,48 @@ static void __nvoc_init_funcTable_VirtualMemoryRange_1(VirtualMemoryRange *pThis pThis->__vmrangeMapTo__ = &__nvoc_thunk_VirtualMemory_vmrangeMapTo; - pThis->__vmrangeControl__ = &__nvoc_thunk_Memory_vmrangeControl; - - pThis->__vmrangeGetMemInterMapParams__ = &__nvoc_thunk_Memory_vmrangeGetMemInterMapParams; - - pThis->__vmrangeUnmap__ = &__nvoc_thunk_Memory_vmrangeUnmap; - - pThis->__vmrangeGetMapAddrSpace__ = &__nvoc_thunk_Memory_vmrangeGetMapAddrSpace; - pThis->__vmrangeShareCallback__ = &__nvoc_thunk_RmResource_vmrangeShareCallback; - pThis->__vmrangeGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_vmrangeGetMemoryMappingDescriptor; - - pThis->__vmrangeControlFilter__ = &__nvoc_thunk_RsResource_vmrangeControlFilter; + pThis->__vmrangeGetMapAddrSpace__ = &__nvoc_thunk_Memory_vmrangeGetMapAddrSpace; pThis->__vmrangeGetRefCount__ = &__nvoc_thunk_RsResource_vmrangeGetRefCount; pThis->__vmrangeAddAdditionalDependants__ = &__nvoc_thunk_RsResource_vmrangeAddAdditionalDependants; - pThis->__vmrangeCanCopy__ = &__nvoc_thunk_StandardMemory_vmrangeCanCopy; + pThis->__vmrangeControl_Prologue__ = &__nvoc_thunk_RmResource_vmrangeControl_Prologue; pThis->__vmrangeIsGpuMapAllowed__ = &__nvoc_thunk_Memory_vmrangeIsGpuMapAllowed; - pThis->__vmrangeControl_Prologue__ = &__nvoc_thunk_RmResource_vmrangeControl_Prologue; - - pThis->__vmrangeIsReady__ = &__nvoc_thunk_Memory_vmrangeIsReady; - pThis->__vmrangeUnmapFrom__ = &__nvoc_thunk_VirtualMemory_vmrangeUnmapFrom; - pThis->__vmrangeCheckCopyPermissions__ = &__nvoc_thunk_Memory_vmrangeCheckCopyPermissions; - - pThis->__vmrangeIsDuplicate__ = &__nvoc_thunk_Memory_vmrangeIsDuplicate; - - pThis->__vmrangePreDestruct__ = &__nvoc_thunk_RsResource_vmrangePreDestruct; - pThis->__vmrangeControl_Epilogue__ = &__nvoc_thunk_RmResource_vmrangeControl_Epilogue; pThis->__vmrangeControlLookup__ = &__nvoc_thunk_RsResource_vmrangeControlLookup; + pThis->__vmrangeControl__ = &__nvoc_thunk_Memory_vmrangeControl; + + pThis->__vmrangeUnmap__ = &__nvoc_thunk_Memory_vmrangeUnmap; + + pThis->__vmrangeGetMemInterMapParams__ = &__nvoc_thunk_Memory_vmrangeGetMemInterMapParams; + + pThis->__vmrangeGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_vmrangeGetMemoryMappingDescriptor; + + pThis->__vmrangeControlFilter__ = &__nvoc_thunk_RsResource_vmrangeControlFilter; + + pThis->__vmrangeControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_vmrangeControlSerialization_Prologue; + + pThis->__vmrangeCanCopy__ = &__nvoc_thunk_StandardMemory_vmrangeCanCopy; + + pThis->__vmrangeIsReady__ = &__nvoc_thunk_Memory_vmrangeIsReady; + + pThis->__vmrangeCheckCopyPermissions__ = &__nvoc_thunk_Memory_vmrangeCheckCopyPermissions; + + pThis->__vmrangePreDestruct__ = &__nvoc_thunk_RsResource_vmrangePreDestruct; + + pThis->__vmrangeIsDuplicate__ = &__nvoc_thunk_Memory_vmrangeIsDuplicate; + + pThis->__vmrangeControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_vmrangeControlSerialization_Epilogue; + pThis->__vmrangeMap__ = &__nvoc_thunk_Memory_vmrangeMap; pThis->__vmrangeAccessCallback__ = &__nvoc_thunk_RmResource_vmrangeAccessCallback; @@ -311,13 +323,16 @@ NV_STATUS __nvoc_objCreate_VirtualMemoryRange(VirtualMemoryRange **ppThis, Dynam Object *pParentObj; VirtualMemoryRange *pThis; - pThis = portMemAllocNonPaged(sizeof(VirtualMemoryRange)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(VirtualMemoryRange), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(VirtualMemoryRange)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_VirtualMemoryRange); + pThis->__nvoc_base_VirtualMemory.__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -333,11 +348,17 @@ NV_STATUS __nvoc_objCreate_VirtualMemoryRange(VirtualMemoryRange **ppThis, Dynam if (status != NV_OK) goto __nvoc_objCreate_VirtualMemoryRange_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_VirtualMemoryRange_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(VirtualMemoryRange)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_virt_mem_range_nvoc.h b/src/nvidia/generated/g_virt_mem_range_nvoc.h index cfe4a92eb..47ac972ac 100644 --- a/src/nvidia/generated/g_virt_mem_range_nvoc.h +++ b/src/nvidia/generated/g_virt_mem_range_nvoc.h @@ -60,25 +60,27 @@ struct VirtualMemoryRange { struct VirtualMemoryRange *__nvoc_pbase_VirtualMemoryRange; NV_STATUS (*__vmrangeCheckMemInterUnmap__)(struct VirtualMemoryRange *, NvBool); NV_STATUS (*__vmrangeMapTo__)(struct VirtualMemoryRange *, struct RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__vmrangeControl__)(struct VirtualMemoryRange *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__vmrangeGetMemInterMapParams__)(struct VirtualMemoryRange *, RMRES_MEM_INTER_MAP_PARAMS *); - NV_STATUS (*__vmrangeUnmap__)(struct VirtualMemoryRange *, CALL_CONTEXT *, RsCpuMapping *); - NV_STATUS (*__vmrangeGetMapAddrSpace__)(struct VirtualMemoryRange *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); NvBool (*__vmrangeShareCallback__)(struct VirtualMemoryRange *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); - NV_STATUS (*__vmrangeGetMemoryMappingDescriptor__)(struct VirtualMemoryRange *, MEMORY_DESCRIPTOR **); - NV_STATUS (*__vmrangeControlFilter__)(struct VirtualMemoryRange *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vmrangeGetMapAddrSpace__)(struct VirtualMemoryRange *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); NvU32 (*__vmrangeGetRefCount__)(struct VirtualMemoryRange *); void (*__vmrangeAddAdditionalDependants__)(struct RsClient *, struct VirtualMemoryRange *, RsResourceRef *); - NvBool (*__vmrangeCanCopy__)(struct VirtualMemoryRange *); - NvBool (*__vmrangeIsGpuMapAllowed__)(struct VirtualMemoryRange *, struct OBJGPU *); NV_STATUS (*__vmrangeControl_Prologue__)(struct VirtualMemoryRange *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__vmrangeIsReady__)(struct VirtualMemoryRange *, NvBool); + NvBool (*__vmrangeIsGpuMapAllowed__)(struct VirtualMemoryRange *, struct OBJGPU *); NV_STATUS (*__vmrangeUnmapFrom__)(struct VirtualMemoryRange *, struct RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__vmrangeCheckCopyPermissions__)(struct VirtualMemoryRange *, struct OBJGPU *, NvHandle); - NV_STATUS (*__vmrangeIsDuplicate__)(struct VirtualMemoryRange *, NvHandle, NvBool *); - void (*__vmrangePreDestruct__)(struct VirtualMemoryRange *); void (*__vmrangeControl_Epilogue__)(struct VirtualMemoryRange *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vmrangeControlLookup__)(struct VirtualMemoryRange *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__vmrangeControl__)(struct VirtualMemoryRange *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vmrangeUnmap__)(struct VirtualMemoryRange *, CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__vmrangeGetMemInterMapParams__)(struct VirtualMemoryRange *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__vmrangeGetMemoryMappingDescriptor__)(struct VirtualMemoryRange *, MEMORY_DESCRIPTOR **); + NV_STATUS (*__vmrangeControlFilter__)(struct VirtualMemoryRange *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vmrangeControlSerialization_Prologue__)(struct VirtualMemoryRange *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__vmrangeCanCopy__)(struct VirtualMemoryRange *); + NV_STATUS (*__vmrangeIsReady__)(struct VirtualMemoryRange *, NvBool); + NV_STATUS (*__vmrangeCheckCopyPermissions__)(struct VirtualMemoryRange *, struct OBJGPU *, NvHandle); + void (*__vmrangePreDestruct__)(struct VirtualMemoryRange *); + NV_STATUS (*__vmrangeIsDuplicate__)(struct VirtualMemoryRange *, NvHandle, NvBool *); + void (*__vmrangeControlSerialization_Epilogue__)(struct VirtualMemoryRange *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vmrangeMap__)(struct VirtualMemoryRange *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__vmrangeAccessCallback__)(struct VirtualMemoryRange *, struct RsClient *, void *, RsAccessRight); }; @@ -113,25 +115,27 @@ NV_STATUS __nvoc_objCreate_VirtualMemoryRange(VirtualMemoryRange**, Dynamic*, Nv #define vmrangeCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) vmrangeCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) #define vmrangeMapTo(pVirtualMemory, pParams) vmrangeMapTo_DISPATCH(pVirtualMemory, pParams) -#define vmrangeControl(pMemory, pCallContext, pParams) vmrangeControl_DISPATCH(pMemory, pCallContext, pParams) -#define vmrangeGetMemInterMapParams(pMemory, pParams) vmrangeGetMemInterMapParams_DISPATCH(pMemory, pParams) -#define vmrangeUnmap(pMemory, pCallContext, pCpuMapping) vmrangeUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) -#define vmrangeGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) vmrangeGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) #define vmrangeShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) vmrangeShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) -#define vmrangeGetMemoryMappingDescriptor(pMemory, ppMemDesc) vmrangeGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define vmrangeControlFilter(pResource, pCallContext, pParams) vmrangeControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define vmrangeGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) vmrangeGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) #define vmrangeGetRefCount(pResource) vmrangeGetRefCount_DISPATCH(pResource) #define vmrangeAddAdditionalDependants(pClient, pResource, pReference) vmrangeAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define vmrangeCanCopy(pStandardMemory) vmrangeCanCopy_DISPATCH(pStandardMemory) -#define vmrangeIsGpuMapAllowed(pMemory, pGpu) vmrangeIsGpuMapAllowed_DISPATCH(pMemory, pGpu) #define vmrangeControl_Prologue(pResource, pCallContext, pParams) vmrangeControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define vmrangeIsReady(pMemory, bCopyConstructorContext) vmrangeIsReady_DISPATCH(pMemory, bCopyConstructorContext) +#define vmrangeIsGpuMapAllowed(pMemory, pGpu) vmrangeIsGpuMapAllowed_DISPATCH(pMemory, pGpu) #define vmrangeUnmapFrom(pVirtualMemory, pParams) vmrangeUnmapFrom_DISPATCH(pVirtualMemory, pParams) -#define vmrangeCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) vmrangeCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) -#define vmrangeIsDuplicate(pMemory, hMemory, pDuplicate) vmrangeIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) -#define vmrangePreDestruct(pResource) vmrangePreDestruct_DISPATCH(pResource) #define vmrangeControl_Epilogue(pResource, pCallContext, pParams) vmrangeControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define vmrangeControlLookup(pResource, pParams, ppEntry) vmrangeControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define vmrangeControl(pMemory, pCallContext, pParams) vmrangeControl_DISPATCH(pMemory, pCallContext, pParams) +#define vmrangeUnmap(pMemory, pCallContext, pCpuMapping) vmrangeUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) +#define vmrangeGetMemInterMapParams(pMemory, pParams) vmrangeGetMemInterMapParams_DISPATCH(pMemory, pParams) +#define vmrangeGetMemoryMappingDescriptor(pMemory, ppMemDesc) vmrangeGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) +#define vmrangeControlFilter(pResource, pCallContext, pParams) vmrangeControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define vmrangeControlSerialization_Prologue(pResource, pCallContext, pParams) vmrangeControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define vmrangeCanCopy(pStandardMemory) vmrangeCanCopy_DISPATCH(pStandardMemory) +#define vmrangeIsReady(pMemory, bCopyConstructorContext) vmrangeIsReady_DISPATCH(pMemory, bCopyConstructorContext) +#define vmrangeCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) vmrangeCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define vmrangePreDestruct(pResource) vmrangePreDestruct_DISPATCH(pResource) +#define vmrangeIsDuplicate(pMemory, hMemory, pDuplicate) vmrangeIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) +#define vmrangeControlSerialization_Epilogue(pResource, pCallContext, pParams) vmrangeControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define vmrangeMap(pMemory, pCallContext, pParams, pCpuMapping) vmrangeMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define vmrangeAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) vmrangeAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) static inline NV_STATUS vmrangeCheckMemInterUnmap_DISPATCH(struct VirtualMemoryRange *pMemory, NvBool bSubdeviceHandleProvided) { @@ -142,32 +146,12 @@ static inline NV_STATUS vmrangeMapTo_DISPATCH(struct VirtualMemoryRange *pVirtua return pVirtualMemory->__vmrangeMapTo__(pVirtualMemory, pParams); } -static inline NV_STATUS vmrangeControl_DISPATCH(struct VirtualMemoryRange *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pMemory->__vmrangeControl__(pMemory, pCallContext, pParams); -} - -static inline NV_STATUS vmrangeGetMemInterMapParams_DISPATCH(struct VirtualMemoryRange *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pMemory->__vmrangeGetMemInterMapParams__(pMemory, pParams); -} - -static inline NV_STATUS vmrangeUnmap_DISPATCH(struct VirtualMemoryRange *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { - return pMemory->__vmrangeUnmap__(pMemory, pCallContext, pCpuMapping); -} - -static inline NV_STATUS vmrangeGetMapAddrSpace_DISPATCH(struct VirtualMemoryRange *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pMemory->__vmrangeGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); -} - static inline NvBool vmrangeShareCallback_DISPATCH(struct VirtualMemoryRange *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pResource->__vmrangeShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); } -static inline NV_STATUS vmrangeGetMemoryMappingDescriptor_DISPATCH(struct VirtualMemoryRange *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { - return pMemory->__vmrangeGetMemoryMappingDescriptor__(pMemory, ppMemDesc); -} - -static inline NV_STATUS vmrangeControlFilter_DISPATCH(struct VirtualMemoryRange *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__vmrangeControlFilter__(pResource, pCallContext, pParams); +static inline NV_STATUS vmrangeGetMapAddrSpace_DISPATCH(struct VirtualMemoryRange *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__vmrangeGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } static inline NvU32 vmrangeGetRefCount_DISPATCH(struct VirtualMemoryRange *pResource) { @@ -178,38 +162,18 @@ static inline void vmrangeAddAdditionalDependants_DISPATCH(struct RsClient *pCli pResource->__vmrangeAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NvBool vmrangeCanCopy_DISPATCH(struct VirtualMemoryRange *pStandardMemory) { - return pStandardMemory->__vmrangeCanCopy__(pStandardMemory); +static inline NV_STATUS vmrangeControl_Prologue_DISPATCH(struct VirtualMemoryRange *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vmrangeControl_Prologue__(pResource, pCallContext, pParams); } static inline NvBool vmrangeIsGpuMapAllowed_DISPATCH(struct VirtualMemoryRange *pMemory, struct OBJGPU *pGpu) { return pMemory->__vmrangeIsGpuMapAllowed__(pMemory, pGpu); } -static inline NV_STATUS vmrangeControl_Prologue_DISPATCH(struct VirtualMemoryRange *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__vmrangeControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS vmrangeIsReady_DISPATCH(struct VirtualMemoryRange *pMemory, NvBool bCopyConstructorContext) { - return pMemory->__vmrangeIsReady__(pMemory, bCopyConstructorContext); -} - static inline NV_STATUS vmrangeUnmapFrom_DISPATCH(struct VirtualMemoryRange *pVirtualMemory, struct RS_RES_UNMAP_FROM_PARAMS *pParams) { return pVirtualMemory->__vmrangeUnmapFrom__(pVirtualMemory, pParams); } -static inline NV_STATUS vmrangeCheckCopyPermissions_DISPATCH(struct VirtualMemoryRange *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { - return pMemory->__vmrangeCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); -} - -static inline NV_STATUS vmrangeIsDuplicate_DISPATCH(struct VirtualMemoryRange *pMemory, NvHandle hMemory, NvBool *pDuplicate) { - return pMemory->__vmrangeIsDuplicate__(pMemory, hMemory, pDuplicate); -} - -static inline void vmrangePreDestruct_DISPATCH(struct VirtualMemoryRange *pResource) { - pResource->__vmrangePreDestruct__(pResource); -} - static inline void vmrangeControl_Epilogue_DISPATCH(struct VirtualMemoryRange *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__vmrangeControl_Epilogue__(pResource, pCallContext, pParams); } @@ -218,6 +182,54 @@ static inline NV_STATUS vmrangeControlLookup_DISPATCH(struct VirtualMemoryRange return pResource->__vmrangeControlLookup__(pResource, pParams, ppEntry); } +static inline NV_STATUS vmrangeControl_DISPATCH(struct VirtualMemoryRange *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pMemory->__vmrangeControl__(pMemory, pCallContext, pParams); +} + +static inline NV_STATUS vmrangeUnmap_DISPATCH(struct VirtualMemoryRange *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pMemory->__vmrangeUnmap__(pMemory, pCallContext, pCpuMapping); +} + +static inline NV_STATUS vmrangeGetMemInterMapParams_DISPATCH(struct VirtualMemoryRange *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pMemory->__vmrangeGetMemInterMapParams__(pMemory, pParams); +} + +static inline NV_STATUS vmrangeGetMemoryMappingDescriptor_DISPATCH(struct VirtualMemoryRange *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return pMemory->__vmrangeGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +} + +static inline NV_STATUS vmrangeControlFilter_DISPATCH(struct VirtualMemoryRange *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vmrangeControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS vmrangeControlSerialization_Prologue_DISPATCH(struct VirtualMemoryRange *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vmrangeControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool vmrangeCanCopy_DISPATCH(struct VirtualMemoryRange *pStandardMemory) { + return pStandardMemory->__vmrangeCanCopy__(pStandardMemory); +} + +static inline NV_STATUS vmrangeIsReady_DISPATCH(struct VirtualMemoryRange *pMemory, NvBool bCopyConstructorContext) { + return pMemory->__vmrangeIsReady__(pMemory, bCopyConstructorContext); +} + +static inline NV_STATUS vmrangeCheckCopyPermissions_DISPATCH(struct VirtualMemoryRange *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { + return pMemory->__vmrangeCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +} + +static inline void vmrangePreDestruct_DISPATCH(struct VirtualMemoryRange *pResource) { + pResource->__vmrangePreDestruct__(pResource); +} + +static inline NV_STATUS vmrangeIsDuplicate_DISPATCH(struct VirtualMemoryRange *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return pMemory->__vmrangeIsDuplicate__(pMemory, hMemory, pDuplicate); +} + +static inline void vmrangeControlSerialization_Epilogue_DISPATCH(struct VirtualMemoryRange *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__vmrangeControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + static inline NV_STATUS vmrangeMap_DISPATCH(struct VirtualMemoryRange *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return pMemory->__vmrangeMap__(pMemory, pCallContext, pParams, pCpuMapping); } diff --git a/src/nvidia/generated/g_virtual_mem_nvoc.c b/src/nvidia/generated/g_virtual_mem_nvoc.c index 18d6798c3..be5ba6244 100644 --- a/src/nvidia/generated/g_virtual_mem_nvoc.c +++ b/src/nvidia/generated/g_virtual_mem_nvoc.c @@ -114,6 +114,38 @@ static NV_STATUS __nvoc_thunk_Memory_virtmemCheckMemInterUnmap(struct VirtualMem return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset), bSubdeviceHandleProvided); } +static NvBool __nvoc_thunk_RmResource_virtmemShareCallback(struct VirtualMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_Memory_virtmemGetMapAddrSpace(struct VirtualMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_virtmemGetRefCount(struct VirtualMemory *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_virtmemAddAdditionalDependants(struct RsClient *pClient, struct VirtualMemory *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_virtmemControl_Prologue(struct VirtualMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_Memory_virtmemIsGpuMapAllowed(struct VirtualMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset), pGpu); +} + +static void __nvoc_thunk_RmResource_virtmemControl_Epilogue(struct VirtualMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_virtmemControlLookup(struct VirtualMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RsResource.offset), pParams, ppEntry); +} + static NV_STATUS __nvoc_thunk_Memory_virtmemControl(struct VirtualMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset), pCallContext, pParams); } @@ -130,38 +162,18 @@ static NV_STATUS __nvoc_thunk_Memory_virtmemGetMemoryMappingDescriptor(struct Vi return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_Memory_virtmemGetMapAddrSpace(struct VirtualMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvBool __nvoc_thunk_RmResource_virtmemShareCallback(struct VirtualMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); -} - static NV_STATUS __nvoc_thunk_RsResource_virtmemControlFilter(struct VirtualMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_virtmemAddAdditionalDependants(struct RsClient *pClient, struct VirtualMemory *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_virtmemGetRefCount(struct VirtualMemory *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RsResource.offset)); +static NV_STATUS __nvoc_thunk_RmResource_virtmemControlSerialization_Prologue(struct VirtualMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_StandardMemory_virtmemCanCopy(struct VirtualMemory *pStandardMemory) { return stdmemCanCopy((struct StandardMemory *)(((unsigned char *)pStandardMemory) + __nvoc_rtti_VirtualMemory_StandardMemory.offset)); } -static NvBool __nvoc_thunk_Memory_virtmemIsGpuMapAllowed(struct VirtualMemory *pMemory, struct OBJGPU *pGpu) { - return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset), pGpu); -} - -static NV_STATUS __nvoc_thunk_RmResource_virtmemControl_Prologue(struct VirtualMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RmResource.offset), pCallContext, pParams); -} - static NV_STATUS __nvoc_thunk_Memory_virtmemIsReady(struct VirtualMemory *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset), bCopyConstructorContext); } @@ -178,12 +190,8 @@ static NV_STATUS __nvoc_thunk_Memory_virtmemIsDuplicate(struct VirtualMemory *pM return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset), hMemory, pDuplicate); } -static void __nvoc_thunk_RmResource_virtmemControl_Epilogue(struct VirtualMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_virtmemControlLookup(struct VirtualMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_virtmemControlSerialization_Epilogue(struct VirtualMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_Memory_virtmemMap(struct VirtualMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -243,6 +251,22 @@ static void __nvoc_init_funcTable_VirtualMemory_1(VirtualMemory *pThis) { pThis->__virtmemCheckMemInterUnmap__ = &__nvoc_thunk_Memory_virtmemCheckMemInterUnmap; + pThis->__virtmemShareCallback__ = &__nvoc_thunk_RmResource_virtmemShareCallback; + + pThis->__virtmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_virtmemGetMapAddrSpace; + + pThis->__virtmemGetRefCount__ = &__nvoc_thunk_RsResource_virtmemGetRefCount; + + pThis->__virtmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_virtmemAddAdditionalDependants; + + pThis->__virtmemControl_Prologue__ = &__nvoc_thunk_RmResource_virtmemControl_Prologue; + + pThis->__virtmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_virtmemIsGpuMapAllowed; + + pThis->__virtmemControl_Epilogue__ = &__nvoc_thunk_RmResource_virtmemControl_Epilogue; + + pThis->__virtmemControlLookup__ = &__nvoc_thunk_RsResource_virtmemControlLookup; + pThis->__virtmemControl__ = &__nvoc_thunk_Memory_virtmemControl; pThis->__virtmemUnmap__ = &__nvoc_thunk_Memory_virtmemUnmap; @@ -251,22 +275,12 @@ static void __nvoc_init_funcTable_VirtualMemory_1(VirtualMemory *pThis) { pThis->__virtmemGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_virtmemGetMemoryMappingDescriptor; - pThis->__virtmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_virtmemGetMapAddrSpace; - - pThis->__virtmemShareCallback__ = &__nvoc_thunk_RmResource_virtmemShareCallback; - pThis->__virtmemControlFilter__ = &__nvoc_thunk_RsResource_virtmemControlFilter; - pThis->__virtmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_virtmemAddAdditionalDependants; - - pThis->__virtmemGetRefCount__ = &__nvoc_thunk_RsResource_virtmemGetRefCount; + pThis->__virtmemControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_virtmemControlSerialization_Prologue; pThis->__virtmemCanCopy__ = &__nvoc_thunk_StandardMemory_virtmemCanCopy; - pThis->__virtmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_virtmemIsGpuMapAllowed; - - pThis->__virtmemControl_Prologue__ = &__nvoc_thunk_RmResource_virtmemControl_Prologue; - pThis->__virtmemIsReady__ = &__nvoc_thunk_Memory_virtmemIsReady; pThis->__virtmemCheckCopyPermissions__ = &__nvoc_thunk_Memory_virtmemCheckCopyPermissions; @@ -275,9 +289,7 @@ static void __nvoc_init_funcTable_VirtualMemory_1(VirtualMemory *pThis) { pThis->__virtmemIsDuplicate__ = &__nvoc_thunk_Memory_virtmemIsDuplicate; - pThis->__virtmemControl_Epilogue__ = &__nvoc_thunk_RmResource_virtmemControl_Epilogue; - - pThis->__virtmemControlLookup__ = &__nvoc_thunk_RsResource_virtmemControlLookup; + pThis->__virtmemControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_virtmemControlSerialization_Epilogue; pThis->__virtmemMap__ = &__nvoc_thunk_Memory_virtmemMap; @@ -306,13 +318,16 @@ NV_STATUS __nvoc_objCreate_VirtualMemory(VirtualMemory **ppThis, Dynamic *pParen Object *pParentObj; VirtualMemory *pThis; - pThis = portMemAllocNonPaged(sizeof(VirtualMemory)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(VirtualMemory), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(VirtualMemory)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_VirtualMemory); + pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -328,11 +343,17 @@ NV_STATUS __nvoc_objCreate_VirtualMemory(VirtualMemory **ppThis, Dynamic *pParen if (status != NV_OK) goto __nvoc_objCreate_VirtualMemory_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_VirtualMemory_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(VirtualMemory)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_virtual_mem_nvoc.h b/src/nvidia/generated/g_virtual_mem_nvoc.h index 68d565c39..cb02cb7e3 100644 --- a/src/nvidia/generated/g_virtual_mem_nvoc.h +++ b/src/nvidia/generated/g_virtual_mem_nvoc.h @@ -63,24 +63,26 @@ struct VirtualMemory { NV_STATUS (*__virtmemMapTo__)(struct VirtualMemory *, struct RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__virtmemUnmapFrom__)(struct VirtualMemory *, struct RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__virtmemCheckMemInterUnmap__)(struct VirtualMemory *, NvBool); + NvBool (*__virtmemShareCallback__)(struct VirtualMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__virtmemGetMapAddrSpace__)(struct VirtualMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__virtmemGetRefCount__)(struct VirtualMemory *); + void (*__virtmemAddAdditionalDependants__)(struct RsClient *, struct VirtualMemory *, RsResourceRef *); + NV_STATUS (*__virtmemControl_Prologue__)(struct VirtualMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__virtmemIsGpuMapAllowed__)(struct VirtualMemory *, struct OBJGPU *); + void (*__virtmemControl_Epilogue__)(struct VirtualMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__virtmemControlLookup__)(struct VirtualMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__virtmemControl__)(struct VirtualMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__virtmemUnmap__)(struct VirtualMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__virtmemGetMemInterMapParams__)(struct VirtualMemory *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__virtmemGetMemoryMappingDescriptor__)(struct VirtualMemory *, MEMORY_DESCRIPTOR **); - NV_STATUS (*__virtmemGetMapAddrSpace__)(struct VirtualMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvBool (*__virtmemShareCallback__)(struct VirtualMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__virtmemControlFilter__)(struct VirtualMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__virtmemAddAdditionalDependants__)(struct RsClient *, struct VirtualMemory *, RsResourceRef *); - NvU32 (*__virtmemGetRefCount__)(struct VirtualMemory *); + NV_STATUS (*__virtmemControlSerialization_Prologue__)(struct VirtualMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__virtmemCanCopy__)(struct VirtualMemory *); - NvBool (*__virtmemIsGpuMapAllowed__)(struct VirtualMemory *, struct OBJGPU *); - NV_STATUS (*__virtmemControl_Prologue__)(struct VirtualMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__virtmemIsReady__)(struct VirtualMemory *, NvBool); NV_STATUS (*__virtmemCheckCopyPermissions__)(struct VirtualMemory *, struct OBJGPU *, NvHandle); void (*__virtmemPreDestruct__)(struct VirtualMemory *); NV_STATUS (*__virtmemIsDuplicate__)(struct VirtualMemory *, NvHandle, NvBool *); - void (*__virtmemControl_Epilogue__)(struct VirtualMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__virtmemControlLookup__)(struct VirtualMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__virtmemControlSerialization_Epilogue__)(struct VirtualMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__virtmemMap__)(struct VirtualMemory *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__virtmemAccessCallback__)(struct VirtualMemory *, struct RsClient *, void *, RsAccessRight); NvHandle hVASpace; @@ -123,24 +125,26 @@ NV_STATUS __nvoc_objCreate_VirtualMemory(VirtualMemory**, Dynamic*, NvU32, CALL_ #define virtmemMapTo(pVirtualMemory, pParams) virtmemMapTo_DISPATCH(pVirtualMemory, pParams) #define virtmemUnmapFrom(pVirtualMemory, pParams) virtmemUnmapFrom_DISPATCH(pVirtualMemory, pParams) #define virtmemCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) virtmemCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define virtmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) virtmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define virtmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) virtmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define virtmemGetRefCount(pResource) virtmemGetRefCount_DISPATCH(pResource) +#define virtmemAddAdditionalDependants(pClient, pResource, pReference) virtmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define virtmemControl_Prologue(pResource, pCallContext, pParams) virtmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define virtmemIsGpuMapAllowed(pMemory, pGpu) virtmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define virtmemControl_Epilogue(pResource, pCallContext, pParams) virtmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define virtmemControlLookup(pResource, pParams, ppEntry) virtmemControlLookup_DISPATCH(pResource, pParams, ppEntry) #define virtmemControl(pMemory, pCallContext, pParams) virtmemControl_DISPATCH(pMemory, pCallContext, pParams) #define virtmemUnmap(pMemory, pCallContext, pCpuMapping) virtmemUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define virtmemGetMemInterMapParams(pMemory, pParams) virtmemGetMemInterMapParams_DISPATCH(pMemory, pParams) #define virtmemGetMemoryMappingDescriptor(pMemory, ppMemDesc) virtmemGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) -#define virtmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) virtmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) -#define virtmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) virtmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define virtmemControlFilter(pResource, pCallContext, pParams) virtmemControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define virtmemAddAdditionalDependants(pClient, pResource, pReference) virtmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define virtmemGetRefCount(pResource) virtmemGetRefCount_DISPATCH(pResource) +#define virtmemControlSerialization_Prologue(pResource, pCallContext, pParams) virtmemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define virtmemCanCopy(pStandardMemory) virtmemCanCopy_DISPATCH(pStandardMemory) -#define virtmemIsGpuMapAllowed(pMemory, pGpu) virtmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) -#define virtmemControl_Prologue(pResource, pCallContext, pParams) virtmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define virtmemIsReady(pMemory, bCopyConstructorContext) virtmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define virtmemCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) virtmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) #define virtmemPreDestruct(pResource) virtmemPreDestruct_DISPATCH(pResource) #define virtmemIsDuplicate(pMemory, hMemory, pDuplicate) virtmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) -#define virtmemControl_Epilogue(pResource, pCallContext, pParams) virtmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define virtmemControlLookup(pResource, pParams, ppEntry) virtmemControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define virtmemControlSerialization_Epilogue(pResource, pCallContext, pParams) virtmemControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define virtmemMap(pMemory, pCallContext, pParams, pCpuMapping) virtmemMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define virtmemAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) virtmemAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS virtmemMapTo_IMPL(struct VirtualMemory *pVirtualMemory, struct RS_RES_MAP_TO_PARAMS *pParams); @@ -159,6 +163,38 @@ static inline NV_STATUS virtmemCheckMemInterUnmap_DISPATCH(struct VirtualMemory return pMemory->__virtmemCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } +static inline NvBool virtmemShareCallback_DISPATCH(struct VirtualMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__virtmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS virtmemGetMapAddrSpace_DISPATCH(struct VirtualMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__virtmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 virtmemGetRefCount_DISPATCH(struct VirtualMemory *pResource) { + return pResource->__virtmemGetRefCount__(pResource); +} + +static inline void virtmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct VirtualMemory *pResource, RsResourceRef *pReference) { + pResource->__virtmemAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS virtmemControl_Prologue_DISPATCH(struct VirtualMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__virtmemControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool virtmemIsGpuMapAllowed_DISPATCH(struct VirtualMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__virtmemIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline void virtmemControl_Epilogue_DISPATCH(struct VirtualMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__virtmemControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS virtmemControlLookup_DISPATCH(struct VirtualMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__virtmemControlLookup__(pResource, pParams, ppEntry); +} + static inline NV_STATUS virtmemControl_DISPATCH(struct VirtualMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pMemory->__virtmemControl__(pMemory, pCallContext, pParams); } @@ -175,38 +211,18 @@ static inline NV_STATUS virtmemGetMemoryMappingDescriptor_DISPATCH(struct Virtua return pMemory->__virtmemGetMemoryMappingDescriptor__(pMemory, ppMemDesc); } -static inline NV_STATUS virtmemGetMapAddrSpace_DISPATCH(struct VirtualMemory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pMemory->__virtmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvBool virtmemShareCallback_DISPATCH(struct VirtualMemory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { - return pResource->__virtmemShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); -} - static inline NV_STATUS virtmemControlFilter_DISPATCH(struct VirtualMemory *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__virtmemControlFilter__(pResource, pCallContext, pParams); } -static inline void virtmemAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct VirtualMemory *pResource, RsResourceRef *pReference) { - pResource->__virtmemAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 virtmemGetRefCount_DISPATCH(struct VirtualMemory *pResource) { - return pResource->__virtmemGetRefCount__(pResource); +static inline NV_STATUS virtmemControlSerialization_Prologue_DISPATCH(struct VirtualMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__virtmemControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool virtmemCanCopy_DISPATCH(struct VirtualMemory *pStandardMemory) { return pStandardMemory->__virtmemCanCopy__(pStandardMemory); } -static inline NvBool virtmemIsGpuMapAllowed_DISPATCH(struct VirtualMemory *pMemory, struct OBJGPU *pGpu) { - return pMemory->__virtmemIsGpuMapAllowed__(pMemory, pGpu); -} - -static inline NV_STATUS virtmemControl_Prologue_DISPATCH(struct VirtualMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__virtmemControl_Prologue__(pResource, pCallContext, pParams); -} - static inline NV_STATUS virtmemIsReady_DISPATCH(struct VirtualMemory *pMemory, NvBool bCopyConstructorContext) { return pMemory->__virtmemIsReady__(pMemory, bCopyConstructorContext); } @@ -223,12 +239,8 @@ static inline NV_STATUS virtmemIsDuplicate_DISPATCH(struct VirtualMemory *pMemor return pMemory->__virtmemIsDuplicate__(pMemory, hMemory, pDuplicate); } -static inline void virtmemControl_Epilogue_DISPATCH(struct VirtualMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__virtmemControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS virtmemControlLookup_DISPATCH(struct VirtualMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__virtmemControlLookup__(pResource, pParams, ppEntry); +static inline void virtmemControlSerialization_Epilogue_DISPATCH(struct VirtualMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__virtmemControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS virtmemMap_DISPATCH(struct VirtualMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -245,10 +257,10 @@ NV_STATUS virtmemConstruct_IMPL(struct VirtualMemory *arg_pVirtualMemory, CALL_C void virtmemDestruct_IMPL(struct VirtualMemory *pVirtualMemory); #define __nvoc_virtmemDestruct(pVirtualMemory) virtmemDestruct_IMPL(pVirtualMemory) -NV_STATUS virtmemReserveMempool_IMPL(struct VirtualMemory *pVirtualMemory, struct OBJGPU *arg0, NvHandle hDevice, NvU64 size, NvU32 pageSizeMask); +NV_STATUS virtmemReserveMempool_IMPL(struct VirtualMemory *pVirtualMemory, struct OBJGPU *arg0, NvHandle hDevice, NvU64 size, NvU64 pageSizeMask); #ifdef __nvoc_virtual_mem_h_disabled -static inline NV_STATUS virtmemReserveMempool(struct VirtualMemory *pVirtualMemory, struct OBJGPU *arg0, NvHandle hDevice, NvU64 size, NvU32 pageSizeMask) { +static inline NV_STATUS virtmemReserveMempool(struct VirtualMemory *pVirtualMemory, struct OBJGPU *arg0, NvHandle hDevice, NvU64 size, NvU64 pageSizeMask) { NV_ASSERT_FAILED_PRECOMP("VirtualMemory was disabled!"); return NV_ERR_NOT_SUPPORTED; } diff --git a/src/nvidia/generated/g_zbc_api_nvoc.c b/src/nvidia/generated/g_zbc_api_nvoc.c index b7484670c..641523029 100644 --- a/src/nvidia/generated/g_zbc_api_nvoc.c +++ b/src/nvidia/generated/g_zbc_api_nvoc.c @@ -97,6 +97,54 @@ static NvBool __nvoc_thunk_GpuResource_zbcapiShareCallback(struct ZbcApi *pGpuRe return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ZbcApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); } +static NV_STATUS __nvoc_thunk_RmResource_zbcapiCheckMemInterUnmap(struct ZbcApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ZbcApi_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_zbcapiMapTo(struct ZbcApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_zbcapiGetMapAddrSpace(struct ZbcApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ZbcApi_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_zbcapiGetRefCount(struct ZbcApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_zbcapiAddAdditionalDependants(struct RsClient *pClient, struct ZbcApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_zbcapiControl_Prologue(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_zbcapiGetRegBaseOffsetAndSize(struct ZbcApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ZbcApi_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_zbcapiInternalControlForward(struct ZbcApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ZbcApi_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_zbcapiUnmapFrom(struct ZbcApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_zbcapiControl_Epilogue(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_zbcapiControlLookup(struct ZbcApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset), pParams, ppEntry); +} + +static NvHandle __nvoc_thunk_GpuResource_zbcapiGetInternalObjectHandle(struct ZbcApi *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ZbcApi_GpuResource.offset)); +} + static NV_STATUS __nvoc_thunk_GpuResource_zbcapiControl(struct ZbcApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ZbcApi_GpuResource.offset), pCallContext, pParams); } @@ -113,68 +161,28 @@ static NV_STATUS __nvoc_thunk_RmResource_zbcapiGetMemoryMappingDescriptor(struct return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ZbcApi_RmResource.offset), ppMemDesc); } -static NV_STATUS __nvoc_thunk_GpuResource_zbcapiGetMapAddrSpace(struct ZbcApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ZbcApi_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); -} - -static NvHandle __nvoc_thunk_GpuResource_zbcapiGetInternalObjectHandle(struct ZbcApi *pGpuResource) { - return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ZbcApi_GpuResource.offset)); -} - static NV_STATUS __nvoc_thunk_RsResource_zbcapiControlFilter(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset), pCallContext, pParams); } -static void __nvoc_thunk_RsResource_zbcapiAddAdditionalDependants(struct RsClient *pClient, struct ZbcApi *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset), pReference); -} - -static NvU32 __nvoc_thunk_RsResource_zbcapiGetRefCount(struct ZbcApi *pResource) { - return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset)); -} - -static NV_STATUS __nvoc_thunk_RmResource_zbcapiCheckMemInterUnmap(struct ZbcApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ZbcApi_RmResource.offset), bSubdeviceHandleProvided); -} - -static NV_STATUS __nvoc_thunk_RsResource_zbcapiMapTo(struct ZbcApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_zbcapiControl_Prologue(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_GpuResource_zbcapiGetRegBaseOffsetAndSize(struct ZbcApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ZbcApi_GpuResource.offset), pGpu, pOffset, pSize); +static NV_STATUS __nvoc_thunk_RmResource_zbcapiControlSerialization_Prologue(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RmResource.offset), pCallContext, pParams); } static NvBool __nvoc_thunk_RsResource_zbcapiCanCopy(struct ZbcApi *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_zbcapiInternalControlForward(struct ZbcApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ZbcApi_GpuResource.offset), command, pParams, size); -} - static void __nvoc_thunk_RsResource_zbcapiPreDestruct(struct ZbcApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_zbcapiUnmapFrom(struct ZbcApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RsResource_zbcapiIsDuplicate(struct ZbcApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset), hMemory, pDuplicate); } -static void __nvoc_thunk_RmResource_zbcapiControl_Epilogue(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RmResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_RsResource_zbcapiControlLookup(struct ZbcApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset), pParams, ppEntry); +static void __nvoc_thunk_RmResource_zbcapiControlSerialization_Epilogue(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RmResource.offset), pCallContext, pParams); } static NV_STATUS __nvoc_thunk_GpuResource_zbcapiMap(struct ZbcApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { @@ -378,6 +386,30 @@ static void __nvoc_init_funcTable_ZbcApi_1(ZbcApi *pThis, RmHalspecOwner *pRmhal pThis->__zbcapiShareCallback__ = &__nvoc_thunk_GpuResource_zbcapiShareCallback; + pThis->__zbcapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_zbcapiCheckMemInterUnmap; + + pThis->__zbcapiMapTo__ = &__nvoc_thunk_RsResource_zbcapiMapTo; + + pThis->__zbcapiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_zbcapiGetMapAddrSpace; + + pThis->__zbcapiGetRefCount__ = &__nvoc_thunk_RsResource_zbcapiGetRefCount; + + pThis->__zbcapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_zbcapiAddAdditionalDependants; + + pThis->__zbcapiControl_Prologue__ = &__nvoc_thunk_RmResource_zbcapiControl_Prologue; + + pThis->__zbcapiGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_zbcapiGetRegBaseOffsetAndSize; + + pThis->__zbcapiInternalControlForward__ = &__nvoc_thunk_GpuResource_zbcapiInternalControlForward; + + pThis->__zbcapiUnmapFrom__ = &__nvoc_thunk_RsResource_zbcapiUnmapFrom; + + pThis->__zbcapiControl_Epilogue__ = &__nvoc_thunk_RmResource_zbcapiControl_Epilogue; + + pThis->__zbcapiControlLookup__ = &__nvoc_thunk_RsResource_zbcapiControlLookup; + + pThis->__zbcapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_zbcapiGetInternalObjectHandle; + pThis->__zbcapiControl__ = &__nvoc_thunk_GpuResource_zbcapiControl; pThis->__zbcapiUnmap__ = &__nvoc_thunk_GpuResource_zbcapiUnmap; @@ -386,37 +418,17 @@ static void __nvoc_init_funcTable_ZbcApi_1(ZbcApi *pThis, RmHalspecOwner *pRmhal pThis->__zbcapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_zbcapiGetMemoryMappingDescriptor; - pThis->__zbcapiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_zbcapiGetMapAddrSpace; - - pThis->__zbcapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_zbcapiGetInternalObjectHandle; - pThis->__zbcapiControlFilter__ = &__nvoc_thunk_RsResource_zbcapiControlFilter; - pThis->__zbcapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_zbcapiAddAdditionalDependants; - - pThis->__zbcapiGetRefCount__ = &__nvoc_thunk_RsResource_zbcapiGetRefCount; - - pThis->__zbcapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_zbcapiCheckMemInterUnmap; - - pThis->__zbcapiMapTo__ = &__nvoc_thunk_RsResource_zbcapiMapTo; - - pThis->__zbcapiControl_Prologue__ = &__nvoc_thunk_RmResource_zbcapiControl_Prologue; - - pThis->__zbcapiGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_zbcapiGetRegBaseOffsetAndSize; + pThis->__zbcapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_zbcapiControlSerialization_Prologue; pThis->__zbcapiCanCopy__ = &__nvoc_thunk_RsResource_zbcapiCanCopy; - pThis->__zbcapiInternalControlForward__ = &__nvoc_thunk_GpuResource_zbcapiInternalControlForward; - pThis->__zbcapiPreDestruct__ = &__nvoc_thunk_RsResource_zbcapiPreDestruct; - pThis->__zbcapiUnmapFrom__ = &__nvoc_thunk_RsResource_zbcapiUnmapFrom; - pThis->__zbcapiIsDuplicate__ = &__nvoc_thunk_RsResource_zbcapiIsDuplicate; - pThis->__zbcapiControl_Epilogue__ = &__nvoc_thunk_RmResource_zbcapiControl_Epilogue; - - pThis->__zbcapiControlLookup__ = &__nvoc_thunk_RsResource_zbcapiControlLookup; + pThis->__zbcapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_zbcapiControlSerialization_Epilogue; pThis->__zbcapiMap__ = &__nvoc_thunk_GpuResource_zbcapiMap; @@ -445,13 +457,16 @@ NV_STATUS __nvoc_objCreate_ZbcApi(ZbcApi **ppThis, Dynamic *pParent, NvU32 creat ZbcApi *pThis; RmHalspecOwner *pRmhalspecowner; - pThis = portMemAllocNonPaged(sizeof(ZbcApi)); - if (pThis == NULL) return NV_ERR_NO_MEMORY; + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ZbcApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; portMemSet(pThis, 0, sizeof(ZbcApi)); __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ZbcApi); + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -471,11 +486,17 @@ NV_STATUS __nvoc_objCreate_ZbcApi(ZbcApi **ppThis, Dynamic *pParent, NvU32 creat if (status != NV_OK) goto __nvoc_objCreate_ZbcApi_cleanup; *ppThis = pThis; + return NV_OK; __nvoc_objCreate_ZbcApi_cleanup: // do not call destructors here since the constructor already called them - portMemFree(pThis); + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(ZbcApi)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] return status; } diff --git a/src/nvidia/generated/g_zbc_api_nvoc.h b/src/nvidia/generated/g_zbc_api_nvoc.h index 82829e7eb..9100ba561 100644 --- a/src/nvidia/generated/g_zbc_api_nvoc.h +++ b/src/nvidia/generated/g_zbc_api_nvoc.h @@ -64,26 +64,28 @@ struct ZbcApi { NV_STATUS (*__zbcapiCtrlCmdGetZbcClearTableSize__)(struct ZbcApi *, NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS *); NV_STATUS (*__zbcapiCtrlCmdGetZbcClearTableEntry__)(struct ZbcApi *, NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS *); NvBool (*__zbcapiShareCallback__)(struct ZbcApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__zbcapiCheckMemInterUnmap__)(struct ZbcApi *, NvBool); + NV_STATUS (*__zbcapiMapTo__)(struct ZbcApi *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__zbcapiGetMapAddrSpace__)(struct ZbcApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__zbcapiGetRefCount__)(struct ZbcApi *); + void (*__zbcapiAddAdditionalDependants__)(struct RsClient *, struct ZbcApi *, RsResourceRef *); + NV_STATUS (*__zbcapiControl_Prologue__)(struct ZbcApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__zbcapiGetRegBaseOffsetAndSize__)(struct ZbcApi *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__zbcapiInternalControlForward__)(struct ZbcApi *, NvU32, void *, NvU32); + NV_STATUS (*__zbcapiUnmapFrom__)(struct ZbcApi *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__zbcapiControl_Epilogue__)(struct ZbcApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__zbcapiControlLookup__)(struct ZbcApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__zbcapiGetInternalObjectHandle__)(struct ZbcApi *); NV_STATUS (*__zbcapiControl__)(struct ZbcApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__zbcapiUnmap__)(struct ZbcApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__zbcapiGetMemInterMapParams__)(struct ZbcApi *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__zbcapiGetMemoryMappingDescriptor__)(struct ZbcApi *, struct MEMORY_DESCRIPTOR **); - NV_STATUS (*__zbcapiGetMapAddrSpace__)(struct ZbcApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); - NvHandle (*__zbcapiGetInternalObjectHandle__)(struct ZbcApi *); NV_STATUS (*__zbcapiControlFilter__)(struct ZbcApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - void (*__zbcapiAddAdditionalDependants__)(struct RsClient *, struct ZbcApi *, RsResourceRef *); - NvU32 (*__zbcapiGetRefCount__)(struct ZbcApi *); - NV_STATUS (*__zbcapiCheckMemInterUnmap__)(struct ZbcApi *, NvBool); - NV_STATUS (*__zbcapiMapTo__)(struct ZbcApi *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__zbcapiControl_Prologue__)(struct ZbcApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__zbcapiGetRegBaseOffsetAndSize__)(struct ZbcApi *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__zbcapiControlSerialization_Prologue__)(struct ZbcApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__zbcapiCanCopy__)(struct ZbcApi *); - NV_STATUS (*__zbcapiInternalControlForward__)(struct ZbcApi *, NvU32, void *, NvU32); void (*__zbcapiPreDestruct__)(struct ZbcApi *); - NV_STATUS (*__zbcapiUnmapFrom__)(struct ZbcApi *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__zbcapiIsDuplicate__)(struct ZbcApi *, NvHandle, NvBool *); - void (*__zbcapiControl_Epilogue__)(struct ZbcApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__zbcapiControlLookup__)(struct ZbcApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + void (*__zbcapiControlSerialization_Epilogue__)(struct ZbcApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__zbcapiMap__)(struct ZbcApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__zbcapiAccessCallback__)(struct ZbcApi *, struct RsClient *, void *, RsAccessRight); NvBool bZbcUsed; @@ -125,26 +127,28 @@ NV_STATUS __nvoc_objCreate_ZbcApi(ZbcApi**, Dynamic*, NvU32, struct CALL_CONTEXT #define zbcapiCtrlCmdGetZbcClearTableSize(pZbcApi, pGetZBCClearTableSizeParams) zbcapiCtrlCmdGetZbcClearTableSize_DISPATCH(pZbcApi, pGetZBCClearTableSizeParams) #define zbcapiCtrlCmdGetZbcClearTableEntry(pZbcApi, pGetZBCClearTableEntryParams) zbcapiCtrlCmdGetZbcClearTableEntry_DISPATCH(pZbcApi, pGetZBCClearTableEntryParams) #define zbcapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) zbcapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define zbcapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) zbcapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define zbcapiMapTo(pResource, pParams) zbcapiMapTo_DISPATCH(pResource, pParams) +#define zbcapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) zbcapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define zbcapiGetRefCount(pResource) zbcapiGetRefCount_DISPATCH(pResource) +#define zbcapiAddAdditionalDependants(pClient, pResource, pReference) zbcapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define zbcapiControl_Prologue(pResource, pCallContext, pParams) zbcapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define zbcapiGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) zbcapiGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define zbcapiInternalControlForward(pGpuResource, command, pParams, size) zbcapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define zbcapiUnmapFrom(pResource, pParams) zbcapiUnmapFrom_DISPATCH(pResource, pParams) +#define zbcapiControl_Epilogue(pResource, pCallContext, pParams) zbcapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define zbcapiControlLookup(pResource, pParams, ppEntry) zbcapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define zbcapiGetInternalObjectHandle(pGpuResource) zbcapiGetInternalObjectHandle_DISPATCH(pGpuResource) #define zbcapiControl(pGpuResource, pCallContext, pParams) zbcapiControl_DISPATCH(pGpuResource, pCallContext, pParams) #define zbcapiUnmap(pGpuResource, pCallContext, pCpuMapping) zbcapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define zbcapiGetMemInterMapParams(pRmResource, pParams) zbcapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define zbcapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) zbcapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) -#define zbcapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) zbcapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) -#define zbcapiGetInternalObjectHandle(pGpuResource) zbcapiGetInternalObjectHandle_DISPATCH(pGpuResource) #define zbcapiControlFilter(pResource, pCallContext, pParams) zbcapiControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define zbcapiAddAdditionalDependants(pClient, pResource, pReference) zbcapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define zbcapiGetRefCount(pResource) zbcapiGetRefCount_DISPATCH(pResource) -#define zbcapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) zbcapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define zbcapiMapTo(pResource, pParams) zbcapiMapTo_DISPATCH(pResource, pParams) -#define zbcapiControl_Prologue(pResource, pCallContext, pParams) zbcapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define zbcapiGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) zbcapiGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define zbcapiControlSerialization_Prologue(pResource, pCallContext, pParams) zbcapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define zbcapiCanCopy(pResource) zbcapiCanCopy_DISPATCH(pResource) -#define zbcapiInternalControlForward(pGpuResource, command, pParams, size) zbcapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define zbcapiPreDestruct(pResource) zbcapiPreDestruct_DISPATCH(pResource) -#define zbcapiUnmapFrom(pResource, pParams) zbcapiUnmapFrom_DISPATCH(pResource, pParams) #define zbcapiIsDuplicate(pResource, hMemory, pDuplicate) zbcapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) -#define zbcapiControl_Epilogue(pResource, pCallContext, pParams) zbcapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define zbcapiControlLookup(pResource, pParams, ppEntry) zbcapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define zbcapiControlSerialization_Epilogue(pResource, pCallContext, pParams) zbcapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define zbcapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) zbcapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define zbcapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) zbcapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) static inline NV_STATUS zbcapiConstructHal_56cd7a(struct ZbcApi *pZbcApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { @@ -215,6 +219,54 @@ static inline NvBool zbcapiShareCallback_DISPATCH(struct ZbcApi *pGpuResource, s return pGpuResource->__zbcapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } +static inline NV_STATUS zbcapiCheckMemInterUnmap_DISPATCH(struct ZbcApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__zbcapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS zbcapiMapTo_DISPATCH(struct ZbcApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__zbcapiMapTo__(pResource, pParams); +} + +static inline NV_STATUS zbcapiGetMapAddrSpace_DISPATCH(struct ZbcApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__zbcapiGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 zbcapiGetRefCount_DISPATCH(struct ZbcApi *pResource) { + return pResource->__zbcapiGetRefCount__(pResource); +} + +static inline void zbcapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ZbcApi *pResource, RsResourceRef *pReference) { + pResource->__zbcapiAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS zbcapiControl_Prologue_DISPATCH(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__zbcapiControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS zbcapiGetRegBaseOffsetAndSize_DISPATCH(struct ZbcApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__zbcapiGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS zbcapiInternalControlForward_DISPATCH(struct ZbcApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__zbcapiInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS zbcapiUnmapFrom_DISPATCH(struct ZbcApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__zbcapiUnmapFrom__(pResource, pParams); +} + +static inline void zbcapiControl_Epilogue_DISPATCH(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__zbcapiControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS zbcapiControlLookup_DISPATCH(struct ZbcApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__zbcapiControlLookup__(pResource, pParams, ppEntry); +} + +static inline NvHandle zbcapiGetInternalObjectHandle_DISPATCH(struct ZbcApi *pGpuResource) { + return pGpuResource->__zbcapiGetInternalObjectHandle__(pGpuResource); +} + static inline NV_STATUS zbcapiControl_DISPATCH(struct ZbcApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pGpuResource->__zbcapiControl__(pGpuResource, pCallContext, pParams); } @@ -231,68 +283,28 @@ static inline NV_STATUS zbcapiGetMemoryMappingDescriptor_DISPATCH(struct ZbcApi return pRmResource->__zbcapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } -static inline NV_STATUS zbcapiGetMapAddrSpace_DISPATCH(struct ZbcApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { - return pGpuResource->__zbcapiGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); -} - -static inline NvHandle zbcapiGetInternalObjectHandle_DISPATCH(struct ZbcApi *pGpuResource) { - return pGpuResource->__zbcapiGetInternalObjectHandle__(pGpuResource); -} - static inline NV_STATUS zbcapiControlFilter_DISPATCH(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__zbcapiControlFilter__(pResource, pCallContext, pParams); } -static inline void zbcapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ZbcApi *pResource, RsResourceRef *pReference) { - pResource->__zbcapiAddAdditionalDependants__(pClient, pResource, pReference); -} - -static inline NvU32 zbcapiGetRefCount_DISPATCH(struct ZbcApi *pResource) { - return pResource->__zbcapiGetRefCount__(pResource); -} - -static inline NV_STATUS zbcapiCheckMemInterUnmap_DISPATCH(struct ZbcApi *pRmResource, NvBool bSubdeviceHandleProvided) { - return pRmResource->__zbcapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); -} - -static inline NV_STATUS zbcapiMapTo_DISPATCH(struct ZbcApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__zbcapiMapTo__(pResource, pParams); -} - -static inline NV_STATUS zbcapiControl_Prologue_DISPATCH(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__zbcapiControl_Prologue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS zbcapiGetRegBaseOffsetAndSize_DISPATCH(struct ZbcApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { - return pGpuResource->__zbcapiGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +static inline NV_STATUS zbcapiControlSerialization_Prologue_DISPATCH(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__zbcapiControlSerialization_Prologue__(pResource, pCallContext, pParams); } static inline NvBool zbcapiCanCopy_DISPATCH(struct ZbcApi *pResource) { return pResource->__zbcapiCanCopy__(pResource); } -static inline NV_STATUS zbcapiInternalControlForward_DISPATCH(struct ZbcApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { - return pGpuResource->__zbcapiInternalControlForward__(pGpuResource, command, pParams, size); -} - static inline void zbcapiPreDestruct_DISPATCH(struct ZbcApi *pResource) { pResource->__zbcapiPreDestruct__(pResource); } -static inline NV_STATUS zbcapiUnmapFrom_DISPATCH(struct ZbcApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__zbcapiUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS zbcapiIsDuplicate_DISPATCH(struct ZbcApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__zbcapiIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline void zbcapiControl_Epilogue_DISPATCH(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__zbcapiControl_Epilogue__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS zbcapiControlLookup_DISPATCH(struct ZbcApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__zbcapiControlLookup__(pResource, pParams, ppEntry); +static inline void zbcapiControlSerialization_Epilogue_DISPATCH(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__zbcapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); } static inline NV_STATUS zbcapiMap_DISPATCH(struct ZbcApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/rmconfig.h b/src/nvidia/generated/rmconfig.h index ccede6203..88d3ad973 100644 --- a/src/nvidia/generated/rmconfig.h +++ b/src/nvidia/generated/rmconfig.h @@ -244,6 +244,7 @@ #define RMCFG_FEATURE_ORIN_PHYSICAL_RM 1 // Physical layer of RM, disabled only on Orin #define RMCFG_FEATURE_VGPU_GSP_PLUGIN_OFFLOAD 1 // vGPU GSP plugin offload #define RMCFG_FEATURE_LIBOS_3_X 1 // Enable Libos-3.x feature +#define RMCFG_FEATURE_SLINEXT 1 #define RMCFG_FEATURE_NOTEBOOK 1 // Notebook support #define RMCFG_FEATURE_EXTDEV 1 // Daughter boards connected to Quadro GPUs #define RMCFG_FEATURE_EXTDEV_GSYNC 1 // Quadro Sync (QSYNC) board for Quadro GPUs @@ -253,7 +254,6 @@ #define RMCFG_FEATURE_ONSEMI_NB7NQ621M 1 // ONSEMI_NB7NQ621M Redriver Support #define RMCFG_FEATURE_DCB_0X 1 // Fallback DCB routines #define RMCFG_FEATURE_DCB_4X 1 // DCB4x (used on G8x and later) -#define RMCFG_FEATURE_XAPI 0 // Use XAPI for resman api calls #define RMCFG_FEATURE_RMAPI_GRAVEYARD 1 // Use RMAPI Graveyard to translate deprecated APIs #define RMCFG_FEATURE_HOTPLUG_POLLING 0 // HotPlug polling #define RMCFG_FEATURE_MULTI_GPU 1 // Multiple GPUs managed by same RM instance @@ -443,6 +443,7 @@ #define RMCFG_CLASS_MAXWELL_DMA_COPY_A 1 #define RMCFG_CLASS_ACCESS_COUNTER_NOTIFY_BUFFER 1 // Access Cntr Buffer for Gr #define RMCFG_CLASS_MMU_FAULT_BUFFER 1 // Volta Fault Buffer for Gr +#define RMCFG_CLASS_MMU_VIDMEM_ACCESS_BIT_BUFFER 1 // Ampere Vidmem Access Bit Buffer #define RMCFG_CLASS_TURING_A 1 // Turing Graphics #define RMCFG_CLASS_TURING_COMPUTE_A 1 // Turing Graphics Compute #define RMCFG_CLASS_AMPERE_A 1 // AmpereA (Graphics) @@ -481,7 +482,8 @@ #define RMCFG_MODULE_ENGSTATE 1 // Base class for engines with generic constructors, StateLoad, etc. #define RMCFG_MODULE_HOSTENG 1 // Base class for host engines #define RMCFG_MODULE_FLCNABLE 0 // Base class for engines requiring falcon -#define RMCFG_MODULE_PMUCLIENT 0 // Base class for engines that use PMU engine +#define RMCFG_MODULE_PMUCLIENT 0 // Base class for implementations of behavior to interact with the PMU engine +#define RMCFG_MODULE_PMU_CLIENT_IMPLEMENTER 0 // Base class for engines that use PMU engine #define RMCFG_MODULE_INTRABLE 0 // Base class to generate and service top-level interrupts #define RMCFG_MODULE_MUTEXABLE 0 // Base class for engines that implements mutex #define RMCFG_MODULE_GpuMutexMgr 0 // GPU Mutex Manager diff --git a/src/nvidia/inc/kernel/gpu/external_device/dac_p2060.h b/src/nvidia/inc/kernel/gpu/external_device/dac_p2060.h index e322f0bb0..617e24d7b 100644 --- a/src/nvidia/inc/kernel/gpu/external_device/dac_p2060.h +++ b/src/nvidia/inc/kernel/gpu/external_device/dac_p2060.h @@ -116,6 +116,7 @@ struct DACP2060EXTERNALDEVICE NvU32 tSwapRdyHiLsrMinTime; /* Value of LSR_MIN_TIME in accordance to the time (in us) * swap ready line will remain high.(Provided via a regkey) */ + NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS mulDivSettings; // Cached multiplier-divider settings NvU32 syncSkewResolutionInNs; // resolution in ns NvU32 syncSkewMax; // max syncSkew setting in raw units @@ -248,6 +249,8 @@ NV_STATUS gsyncGetStereoLockMode_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU3 NV_STATUS gsyncSetStereoLockMode_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32); NV_STATUS gsyncSetMosaic_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS *); NV_STATUS gsyncConfigFlashGsync_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32); +NV_STATUS gsyncGetMulDiv_P2060 (OBJGPU *, DACEXTERNALDEVICE *, NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS *); +NV_STATUS gsyncSetMulDiv_P2060 (OBJGPU *, DACEXTERNALDEVICE *, NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS *); NvBool gsyncSupportsLargeSyncSkew_P2060 (DACEXTERNALDEVICE *); #endif diff --git a/src/nvidia/inc/kernel/gpu/gpu_access.h b/src/nvidia/inc/kernel/gpu/gpu_access.h index 127c38a2e..c11c3e41c 100644 --- a/src/nvidia/inc/kernel/gpu/gpu_access.h +++ b/src/nvidia/inc/kernel/gpu/gpu_access.h @@ -1,381 +1,3 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2004-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef _GPU_ACCESS_H_ -#define _GPU_ACCESS_H_ -#include "ioaccess/ioaccess.h" -#include "gpu/gpu_device_mapping.h" +#include "g_gpu_access_nvoc.h" -// Go straight at the memory or hardware. -#define MEM_RD08(a) (*(const volatile NvU8 *)(a)) -#define MEM_RD16(a) (*(const volatile NvU16 *)(a)) -#define MEM_RD32(a) (*(const volatile NvU32 *)(a)) -#define MEM_WR08(a, d) do { *(volatile NvU8 *)(a) = (d); } while (0) -#define MEM_WR16(a, d) do { *(volatile NvU16 *)(a) = (d); } while (0) -#define MEM_WR32(a, d) do { *(volatile NvU32 *)(a) = (d); } while (0) -#define MEM_WR64(a, d) do { *(volatile NvU64 *)(a) = (d); } while (0) - -// -// Define the signature of the register filter callback function -// -// flags can be optionally used for filters to decide whether to actually -// touch HW or not. flags should be OR'ed every time a new filter is found. (see objgpu.c) -// -typedef void (*GpuWriteRegCallback)(OBJGPU *, void *, NvU32 addr, NvU32 val, NvU32 accessSize, NvU32 flags); -typedef NvU32 (*GpuReadRegCallback)(OBJGPU *, void *, NvU32 addr, NvU32 accessSize, NvU32 flags); - -union GPUHWREG -{ - volatile NvV8 Reg008[1]; - volatile NvV16 Reg016[1]; - volatile NvV32 Reg032[1]; -}; - -typedef union GPUHWREG GPUHWREG; - -// -// Register filter record -// -// If REGISTER_FILTER_FLAGS_READ is set, then that means that the base RegRead -// function will not read the register, so the provided read callback function -// is expected to read the register and return the value. -// -// If REGISTER_FILTER_FLAGS_WRITE is set, then that means that the base RegWrite -// function will not write the register, so the provided callback write function -// is expected to write the given value to the register. -// -// It is an error to specify REGISTER_FILTER_FLAGS_READ and not provide a -// read callback function. -// -// It is an error to specify REGISTER_FILTER_FLAGS_WRITE and not provide a -// write callback function. -// -#define REGISTER_FILTER_FLAGS_READ (NVBIT(0)) -#define REGISTER_FILTER_FLAGS_WRITE (NVBIT(1)) -// filter is in the list but it is invalid and should be removed -#define REGISTER_FILTER_FLAGS_INVALID (NVBIT(2)) - -#define REGISTER_FILTER_FLAGS_VIRTUAL (0) -#define REGISTER_FILTER_FLAGS_READ_WRITE (REGISTER_FILTER_FLAGS_READ | REGISTER_FILTER_FLAGS_WRITE) - -typedef struct REGISTER_FILTER REGISTER_FILTER; - -struct REGISTER_FILTER -{ - REGISTER_FILTER *pNext; //!< pointer to next filter - NvU32 flags; //!< attributes of this filter - DEVICE_INDEX devIndex; //!< filter device - NvU32 devInstance; //!< filter device instance - NvU32 rangeStart; //!< filter range start (can overlap) - NvU32 rangeEnd; //!< filter range end (can overlap) - GpuWriteRegCallback pWriteCallback; //!< callback for write - GpuReadRegCallback pReadCallback; //!< callback for read - void *pParam; //!< pointer to param which gets passed to callbacks -}; - -typedef struct { - REGISTER_FILTER *pRegFilterList; // Active filters - REGISTER_FILTER *pRegFilterRecycleList; // Inactive filters - PORT_SPINLOCK * pRegFilterLock; // Thread-safe list management - NvU32 regFilterRefCnt; // Thread-safe list management - NvBool bRegFilterNeedRemove; // Thread-safe list garbage collection -} DEVICE_REGFILTER_INFO; - -typedef struct DEVICE_MAPPING -{ - GPUHWREG *gpuNvAddr; // CPU Virtual Address - RmPhysAddr gpuNvPAddr; // Physical Base Address - NvU32 gpuNvLength; // Length of the Aperture - NvU32 gpuNvSaveLength; - NvU32 gpuDeviceEnum; // Device ID NV_DEVID_* - NvU32 refCount; // refCount for the device map. - DEVICE_REGFILTER_INFO devRegFilterInfo; // register filter range list -} DEVICE_MAPPING; - -typedef struct -{ - IO_DEVICE parent; - OBJGPU *pGpu; - DEVICE_INDEX deviceIndex; - NvU32 instance; - // The following members are initialized in objgpu.c, - // but are not used anywhere. gpuApertureReg* functions - // fall back to DEVICE_MAPPING instead - GPUHWREG *gpuNvAddr; // CPU Virtual Address - RmPhysAddr gpuNvPAddr; // Physical Base Address - NvU32 gpuNvLength; // Length of Aperture - NvU32 gpuDeviceEnum; // Device ID NV_DEVID_* - NvU32 refCount; // refCount for the device map. - DEVICE_REGFILTER_INFO devRegFilterInfo; // register filter range list -} GPU_IO_DEVICE; - -typedef struct -{ - // Pointer to GPU linked to this RegisterAccess object - OBJGPU *pGpu; - - // HW register access tools - GPUHWREG *gpuFbAddr; - GPUHWREG *gpuInstAddr; - - // Register access profiling - NvU32 regReadCount; - NvU32 regWriteCount; -} RegisterAccess; - -/*! Init register IO access path */ -NV_STATUS regAccessConstruct(RegisterAccess *, OBJGPU *pGpu); - -/*! Shutdown register IO access path */ -void regAccessDestruct(RegisterAccess *); - -/*! Writes to 8 bit register */ -void regWrite008(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32, NvV8); - -/*! Writes to 16 bit register */ -void regWrite016(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32, NvV16); - -/*! Writes to 32 bit register, with thread state on the stack */ -void regWrite032(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32, NvV32, THREAD_STATE_NODE *); - -/*! Unicast register access, with thread state on the stack */ -void regWrite032Unicast(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32, NvV32, THREAD_STATE_NODE *); - -/*! Reads from 8 bit register */ -NvU8 regRead008(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32); - -/*! Reads from 16 bit register */ -NvU16 regRead016(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32); - -/*! Reads from 32 bit register, with thread state on the stack */ -NvU32 regRead032(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32, THREAD_STATE_NODE *); - -/*! Reads from 32 bit register and checks bit mask, with thread state on the stack */ -NvU32 regCheckRead032(RegisterAccess *, NvU32, NvU32, THREAD_STATE_NODE *); - -/*! Reads 32 bit register and polls bit field for specific value */ -NV_STATUS regRead032_AndPoll(RegisterAccess *, DEVICE_INDEX, NvU32, NvU32, NvU32); - -/*! Adds a register filter */ -NV_STATUS regAddRegisterFilter(RegisterAccess *, NvU32, DEVICE_INDEX, NvU32, NvU32, NvU32, GpuWriteRegCallback, GpuReadRegCallback, void *, REGISTER_FILTER **); - -/*! Removes register filter */ -void regRemoveRegisterFilter(RegisterAccess *, REGISTER_FILTER *); - -/*! Check status of read return value for GPU/bus errors */ -void regCheckAndLogReadFailure(RegisterAccess *, NvU32 addr, NvU32 mask, NvU32 value); - -// -// GPU register I/O macros. -// - -// -// GPU neutral macros typically used for register I/O. -// -#define GPU_DRF_SHIFT(drf) ((0?drf) % 32) -#define GPU_DRF_MASK(drf) (0xFFFFFFFF>>(31-((1?drf) % 32)+((0?drf) % 32))) -#define GPU_DRF_DEF(d,r,f,c) ((NV ## d ## r ## f ## c)<>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) -#define GPU_DRF_SHIFTMASK(drf) (GPU_DRF_MASK(drf)<<(GPU_DRF_SHIFT(drf))) -#define GPU_DRF_WIDTH(drf) ((1?drf) - (0?drf) + 1) - - -// Device independent macros -// Multiple device instance macros - -#define REG_INST_RD08(g,dev,inst,a) regRead008(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a) -#define REG_INST_RD16(g,dev,inst,a) regRead016(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a) -#define REG_INST_RD32(g,dev,inst,a) regRead032(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a, NULL) - -#define REG_INST_WR08(g,dev,inst,a,v) regWrite008(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a, v) -#define REG_INST_WR16(g,dev,inst,a,v) regWrite016(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a, v) -#define REG_INST_WR32(g,dev,inst,a,v) regWrite032(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a, v, NULL) -#define REG_INST_WR32_UC(g,dev,inst,a,v) regWrite032Unicast(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a, v, NULL) - -#define REG_INST_RD32_EX(g,dev,inst,a,t) regRead032(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a, t) -#define REG_INST_WR32_EX(g,dev,inst,a,v,t) regWrite032(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, a, v, t) - -#define REG_INST_DEVIDX_RD32_EX(g,devidx,inst,a,t) regRead032(GPU_GET_REGISTER_ACCESS(g), devidx, inst, a, t) -#define REG_INST_DEVIDX_WR32_EX(g,devidx,inst,a,v,t) regWrite032(GPU_GET_REGISTER_ACCESS(g), devidx, inst, a, v, t) - -// GPU macros defined in terms of DEV_ macros -#define GPU_REG_RD08(g,a) REG_INST_RD08(g,GPU,0,a) -#define GPU_REG_RD16(g,a) REG_INST_RD16(g,GPU,0,a) -#define GPU_REG_RD32(g,a) REG_INST_RD32(g,GPU,0,a) -#define GPU_CHECK_REG_RD32(g,a,m) regCheckRead032(GPU_GET_REGISTER_ACCESS(g),a,m,NULL) -#define GPU_REG_RD32_AND_POLL(g,r,m,v) regRead032_AndPoll(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_GPU, r, m, v) - -#define GPU_REG_WR08(g,a,v) REG_INST_WR08(g,GPU,0,a,v) -#define GPU_REG_WR16(g,a,v) REG_INST_WR16(g,GPU,0,a,v) -#define GPU_REG_WR32(g,a,v) REG_INST_WR32(g,GPU,0,a,v) -#define GPU_REG_WR32_UC(g,a,v) REG_INST_WR32_UC(g,GPU,0,a,v) - -// GPU macros for SR-IOV -#define GPU_VREG_RD32(g, a) GPU_REG_RD32(g, g->sriovState.virtualRegPhysOffset + a) -#define GPU_VREG_WR32(g, a, v) GPU_REG_WR32(g, g->sriovState.virtualRegPhysOffset + a, v) -#define GPU_VREG_RD32_EX(g,a,t) REG_INST_RD32_EX(g, GPU, 0, g->sriovState.virtualRegPhysOffset + a, t) -#define GPU_VREG_WR32_EX(g,a,v,t) REG_INST_WR32_EX(g, GPU, 0, g->sriovState.virtualRegPhysOffset + a, v, t) -#define GPU_VREG_FLD_WR_DRF_DEF(g,d,r,f,c) GPU_VREG_WR32(g, NV##d##r,(GPU_VREG_RD32(g,NV##d##r)&~(GPU_DRF_MASK(NV##d##r##f)<>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) - -#define VREG_INST_RD32(g,dev,inst,a) regRead032(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, g->sriovState.virtualRegPhysOffset + a, NULL) -#define VREG_INST_WR32(g,dev,inst,a,v) regWrite032(GPU_GET_REGISTER_ACCESS(g), DEVICE_INDEX_##dev, inst, g->sriovState.virtualRegPhysOffset + a, v, NULL) -#define GPU_VREG_FLD_WR_DRF_NUM(g,d,r,f,n) VREG_INST_WR32(g,GPU,0,NV##d##r,(VREG_INST_RD32(g,GPU,0,NV##d##r)&~(GPU_DRF_MASK(NV##d##r##f)<sriovState.virtualRegPhysOffset + a) - -#define GPU_VREG_IDX_RD_DRF(g,d,r,i,f) (((GPU_VREG_RD32(g, NV ## d ## r(i)))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) -#define GPU_VREG_FLD_IDX_WR_DRF_DEF(g,d,r,i,f,c) GPU_VREG_WR32(g, NV##d##r(i),(GPU_VREG_RD32(g,NV##d##r(i))&~(GPU_DRF_MASK(NV##d##r##f)<sriovState.virtualRegPhysOffset + a) -#define GPU_VREG_WR32(g, a, v) gpuRegWr32_dumpinfo(__FUNCTION__,#a,"(VREG)",g, g->sriovState.virtualRegPhysOffset + a, v) - -#endif // GPU_REGISTER_ACCESS_DUMP - -// -// Macros for register I/O -// -#define GPU_FLD_WR_DRF_NUM(g,d,r,f,n) REG_INST_WR32(g,GPU,0,NV##d##r,(REG_INST_RD32(g,GPU,0,NV##d##r)&~(GPU_DRF_MASK(NV##d##r##f)<>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) -#define GPU_FLD_TEST_DRF_DEF(g,d,r,f,c) (GPU_REG_RD_DRF(g, d, r, f) == NV##d##r##f##c) -#define GPU_FLD_TEST_DRF_NUM(g,d,r,f,n) (GPU_REG_RD_DRF(g, d, r, f) == n) -#define GPU_FLD_IDX_TEST_DRF_DEF(g,d,r,f,c,i) (GPU_REG_IDX_RD_DRF(g, d, r, i, f) == NV##d##r##f##c) -#define GPU_FLD_2IDX_TEST_DRF_DEF(g,d,r,f,c,i,j) (GPU_REG_2IDX_RD_DRF(g, d, r, i, j, f) == NV##d##r##f##c) - -#define GPU_REG_RD_DRF_EX(g,d,r,f,t) (((GPU_REG_RD32_EX(g, NV ## d ## r, t))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) - -#define GPU_FLD_WR_DRF_NUM_EX(g,d,r,f,n,t) REG_INST_WR32_EX(g,GPU,0,NV##d##r,(REG_INST_RD32_EX(g,GPU,0,NV##d##r,t)&~(GPU_DRF_MASK(NV##d##r##f)<>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) -#define GPU_REG_2IDX_RD_DRF(g,d,r,i,j,f) (((GPU_REG_RD32(g, NV ## d ## r(i, j)))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) -#define GPU_REG_RD_DRF_IDX(g,d,r,f,i) (((GPU_REG_RD32(g, NV ## d ## r))>>GPU_DRF_SHIFT(NV ## d ## r ## f(i)))&GPU_DRF_MASK(NV ## d ## r ## f(i))) -#define GPU_REG_IDX_OFFSET_RD_DRF(g,d,r,i,o,f) (((GPU_REG_RD32(g, NV ## d ## r(i,o)))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f)) - -// -// Macros that abstract the use of bif object to access GPU bus config registers -// This is the preferred set >= NV50 -// -#define GPU_BUS_CFG_RD32(g,r,d) gpuReadBusConfigReg_HAL(g, r, d) -#define GPU_BUS_CFG_WR32(g,r,d) gpuWriteBusConfigReg_HAL(g, r, d) -#define GPU_BUS_CFG_FLD_WR_DRF_DEF(g,x,d,r,f,c) GPU_BUS_CFG_WR32(g, NV##d##r,(x &~(GPU_DRF_MASK(NV##d##r##f)<>(31-(1?sf)+(0?sf))) -#define SF_SHIFTMASK(sf) (SF_MASK(sf) << SF_SHIFT(sf)) -#define SF_DEF(s,f,c) ((NV ## s ## f ## c)<>SF_SHIFT(NV ## s ## f))&SF_MASK(NV ## s ## f)) -#define SF_WIDTH(sf) ((1?sf) - (0?sf) + 1) -// This macro parses multi-word/array defines -#define SF_ARR32_VAL(s,f,arr) \ - (((arr)[SF_INDEX(NV ## s ## f)] >> SF_SHIFT(NV ## s ## f)) & SF_MASK(NV ## s ## f)) -#define FLD_SF_DEF(s,f,d,l) ((l)&~(SF_MASK(NV##s##f) << SF_SHIFT(NV##s##f)))| SF_DEF(s,f,d) -#define FLD_SF_NUM(s,f,n,l) ((l)&~(SF_MASK(NV##s##f) << SF_SHIFT(NV##s##f)))| SF_NUM(s,f,n) -#define FLD_SF_IDX_DEF(s,f,c,i,l) (((l) & ~SF_SHIFTMASK(NV ## s ## f(i))) | SF_IDX_DEF(s,f,c,i)) -#define FLD_SF_IDX_NUM(s,f,n,i,l) (((l) & ~SF_SHIFTMASK(NV ## s ## f(i))) | SF_IDX_NUM(s,f,n,i)) - -#endif // _GPU_ACCESS_H_ diff --git a/src/nvidia/inc/kernel/gpu/gpu_acpi_data.h b/src/nvidia/inc/kernel/gpu/gpu_acpi_data.h index 762276424..a71d402d9 100644 --- a/src/nvidia/inc/kernel/gpu/gpu_acpi_data.h +++ b/src/nvidia/inc/kernel/gpu/gpu_acpi_data.h @@ -71,8 +71,9 @@ typedef struct DOD_METHOD_DATA typedef struct JT_METHOD_DATA { NV_STATUS status; - NvU16 jtRevId; NvU32 jtCaps; + NvU16 jtRevId; + NvBool bSBIOSCaps; } JT_METHOD_DATA; typedef struct MUX_METHOD_DATA_ELEMENT diff --git a/src/nvidia/inc/kernel/gpu/gpu_child_list.h b/src/nvidia/inc/kernel/gpu/gpu_child_list.h index 632013158..73ec4aa0f 100644 --- a/src/nvidia/inc/kernel/gpu/gpu_child_list.h +++ b/src/nvidia/inc/kernel/gpu/gpu_child_list.h @@ -53,252 +53,252 @@ #define GPU_CHILD_MODULE(_rmcfgModule) RMCFG_MODULE_ENABLED(_rmcfgModule) #endif - /* Class Name Accessor Name Max Instances bConstructEarly bAlwaysCreate OBJGPU Field */ + /* Class Name Accessor Name Max Instances bConstructEarly OBJGPU Field */ #if GPU_CHILD_MODULE(FUSE) - GPU_CHILD_SINGLE_INST( OBJFUSE, GPU_GET_FUSE, 1, NV_TRUE, NV_TRUE, pFuse ) + GPU_CHILD_SINGLE_INST( OBJFUSE, GPU_GET_FUSE, 1, NV_TRUE, pFuse ) #endif #if GPU_CHILD_MODULE(BIF) - GPU_CHILD_SINGLE_INST( OBJBIF, GPU_GET_BIF, 1, NV_TRUE, NV_FALSE, pBif ) + GPU_CHILD_SINGLE_INST( OBJBIF, GPU_GET_BIF, 1, NV_TRUE, pBif ) #endif #if GPU_CHILD_MODULE(KERNEL_BIF) - GPU_CHILD_SINGLE_INST( KernelBif, GPU_GET_KERNEL_BIF, 1, NV_TRUE, NV_FALSE, pKernelBif ) + GPU_CHILD_SINGLE_INST( KernelBif, GPU_GET_KERNEL_BIF, 1, NV_TRUE, pKernelBif ) #endif #if GPU_CHILD_MODULE(NNE) - GPU_CHILD_SINGLE_INST( OBJNNE, GPU_GET_NNE, 1, NV_TRUE, NV_FALSE, pNne ) + GPU_CHILD_SINGLE_INST( Nne, GPU_GET_NNE, 1, NV_TRUE, pNne ) #endif #if GPU_CHILD_MODULE(MC) - GPU_CHILD_SINGLE_INST( OBJMC, GPU_GET_MC, 1, NV_FALSE, NV_FALSE, pMc ) + GPU_CHILD_SINGLE_INST( OBJMC, GPU_GET_MC, 1, NV_FALSE, pMc ) #endif #if GPU_CHILD_MODULE(KERNEL_MC) - GPU_CHILD_SINGLE_INST( KernelMc, GPU_GET_KERNEL_MC, 1, NV_FALSE, NV_FALSE, pKernelMc ) + GPU_CHILD_SINGLE_INST( KernelMc, GPU_GET_KERNEL_MC, 1, NV_FALSE, pKernelMc ) #endif #if GPU_CHILD_MODULE(PRIV_RING) - GPU_CHILD_SINGLE_INST( PrivRing, GPU_GET_PRIV_RING, 1, NV_FALSE, NV_FALSE, pPrivRing ) + GPU_CHILD_SINGLE_INST( PrivRing, GPU_GET_PRIV_RING, 1, NV_FALSE, pPrivRing ) #endif #if GPU_CHILD_MODULE(INTR) - GPU_CHILD_SINGLE_INST( SwIntr, GPU_GET_SW_INTR, 1, NV_FALSE, NV_FALSE, pSwIntr ) + GPU_CHILD_SINGLE_INST( SwIntr, GPU_GET_SW_INTR, 1, NV_FALSE, pSwIntr ) #endif #if GPU_CHILD_MODULE(MEMORY_SYSTEM) - GPU_CHILD_SINGLE_INST( MemorySystem, GPU_GET_MEMORY_SYSTEM, 1, NV_FALSE, NV_FALSE, pMemorySystem ) + GPU_CHILD_SINGLE_INST( MemorySystem, GPU_GET_MEMORY_SYSTEM, 1, NV_FALSE, pMemorySystem ) #endif #if GPU_CHILD_MODULE(KERNEL_MEMORY_SYSTEM) - GPU_CHILD_SINGLE_INST( KernelMemorySystem, GPU_GET_KERNEL_MEMORY_SYSTEM, 1, NV_FALSE, NV_FALSE, pKernelMemorySystem ) + GPU_CHILD_SINGLE_INST( KernelMemorySystem, GPU_GET_KERNEL_MEMORY_SYSTEM, 1, NV_FALSE, pKernelMemorySystem ) #endif #if GPU_CHILD_MODULE(MEMORY_MANAGER) - GPU_CHILD_SINGLE_INST( MemoryManager, GPU_GET_MEMORY_MANAGER, 1, NV_FALSE, NV_FALSE, pMemoryManager ) + GPU_CHILD_SINGLE_INST( MemoryManager, GPU_GET_MEMORY_MANAGER, 1, NV_FALSE, pMemoryManager ) #endif #if GPU_CHILD_MODULE(FBFLCN) - GPU_CHILD_SINGLE_INST( OBJFBFLCN, GPU_GET_FBFLCN, 1, NV_FALSE, NV_FALSE, pFbflcn ) + GPU_CHILD_SINGLE_INST( OBJFBFLCN, GPU_GET_FBFLCN, 1, NV_FALSE, pFbflcn ) #endif #if GPU_CHILD_MODULE(HSHUBMANAGER) - GPU_CHILD_SINGLE_INST( OBJHSHUBMANAGER, GPU_GET_HSHUBMANAGER, 1, NV_FALSE, NV_FALSE, pHshMgr ) + GPU_CHILD_SINGLE_INST( OBJHSHUBMANAGER, GPU_GET_HSHUBMANAGER, 1, NV_FALSE, pHshMgr ) #endif #if GPU_CHILD_MODULE(HSHUB) - GPU_CHILD_MULTI_INST ( Hshub, GPU_GET_HSHUB, GPU_MAX_HSHUBS, NV_FALSE, NV_FALSE, pHshub ) + GPU_CHILD_MULTI_INST ( Hshub, GPU_GET_HSHUB, GPU_MAX_HSHUBS, NV_FALSE, pHshub ) #endif #if GPU_CHILD_MODULE(SEQ) - GPU_CHILD_SINGLE_INST( OBJSEQ, GPU_GET_SEQ, 1, NV_FALSE, NV_TRUE, pSeq ) + GPU_CHILD_SINGLE_INST( OBJSEQ, GPU_GET_SEQ, 1, NV_FALSE, pSeq ) #endif #if GPU_CHILD_MODULE(GpuMutexMgr) - GPU_CHILD_SINGLE_INST( GpuMutexMgr, GPU_GET_MUTEX_MGR, 1, NV_FALSE, NV_TRUE, pMutexMgr ) + GPU_CHILD_SINGLE_INST( GpuMutexMgr, GPU_GET_MUTEX_MGR, 1, NV_FALSE, pMutexMgr ) #endif #if GPU_CHILD_MODULE(KERNEL_DISPLAY) - GPU_CHILD_SINGLE_INST( KernelDisplay, GPU_GET_KERNEL_DISPLAY, 1, NV_FALSE, NV_FALSE, pKernelDisplay ) + GPU_CHILD_SINGLE_INST( KernelDisplay, GPU_GET_KERNEL_DISPLAY, 1, NV_FALSE, pKernelDisplay ) #endif #if GPU_CHILD_MODULE(DISP) - GPU_CHILD_SINGLE_INST( OBJDISP, GPU_GET_DISP, 1, NV_FALSE, NV_FALSE, pDisp ) + GPU_CHILD_SINGLE_INST( OBJDISP, GPU_GET_DISP, 1, NV_FALSE, pDisp ) #endif #if GPU_CHILD_MODULE(TMR) - GPU_CHILD_SINGLE_INST( OBJTMR, GPU_GET_TIMER, 1, NV_TRUE, NV_TRUE, pTmr ) + GPU_CHILD_SINGLE_INST( OBJTMR, GPU_GET_TIMER, 1, NV_TRUE, pTmr ) #endif #if GPU_CHILD_MODULE(BUS) - GPU_CHILD_SINGLE_INST( OBJBUS, GPU_GET_BUS, 1, NV_FALSE, NV_FALSE, pBus ) + GPU_CHILD_SINGLE_INST( OBJBUS, GPU_GET_BUS, 1, NV_FALSE, pBus ) #endif #if GPU_CHILD_MODULE(KERNEL_BUS) - GPU_CHILD_SINGLE_INST( KernelBus, GPU_GET_KERNEL_BUS, 1, NV_FALSE, NV_FALSE, pKernelBus ) + GPU_CHILD_SINGLE_INST( KernelBus, GPU_GET_KERNEL_BUS, 1, NV_FALSE, pKernelBus ) #endif #if GPU_CHILD_MODULE(GMMU) - GPU_CHILD_SINGLE_INST( OBJGMMU, GPU_GET_GMMU, 1, NV_FALSE, NV_FALSE, pGmmu ) + GPU_CHILD_SINGLE_INST( OBJGMMU, GPU_GET_GMMU, 1, NV_FALSE, pGmmu ) #endif #if GPU_CHILD_MODULE(KERNEL_GMMU) - GPU_CHILD_SINGLE_INST( KernelGmmu, GPU_GET_KERNEL_GMMU, 1, NV_FALSE, NV_FALSE, pKernelGmmu ) + GPU_CHILD_SINGLE_INST( KernelGmmu, GPU_GET_KERNEL_GMMU, 1, NV_FALSE, pKernelGmmu ) #endif #if GPU_CHILD_MODULE(KERNEL_SEC2) - GPU_CHILD_SINGLE_INST( KernelSec2, GPU_GET_KERNEL_SEC2, 1, NV_FALSE, NV_FALSE, pKernelSec2 ) + GPU_CHILD_SINGLE_INST( KernelSec2, GPU_GET_KERNEL_SEC2, 1, NV_FALSE, pKernelSec2 ) #endif #if GPU_CHILD_MODULE(KERNEL_GSP) - GPU_CHILD_SINGLE_INST( KernelGsp, GPU_GET_KERNEL_GSP, 1, NV_FALSE, NV_FALSE, pKernelGsp ) + GPU_CHILD_SINGLE_INST( KernelGsp, GPU_GET_KERNEL_GSP, 1, NV_FALSE, pKernelGsp ) #endif #if GPU_CHILD_MODULE(DCECLIENTRM) - GPU_CHILD_SINGLE_INST( OBJDCECLIENTRM, GPU_GET_DCECLIENTRM, 1, NV_FALSE, NV_FALSE, pDceclientrm ) + GPU_CHILD_SINGLE_INST( OBJDCECLIENTRM, GPU_GET_DCECLIENTRM, 1, NV_FALSE, pDceclientrm ) #endif #if GPU_CHILD_MODULE(VIRT_MEM_ALLOCATOR) - GPU_CHILD_SINGLE_INST( VirtMemAllocator, GPU_GET_DMA, 1, NV_FALSE, NV_FALSE, pDma ) + GPU_CHILD_SINGLE_INST( VirtMemAllocator, GPU_GET_DMA, 1, NV_FALSE, pDma ) #endif #if GPU_CHILD_MODULE(GRMGR) - GPU_CHILD_SINGLE_INST( GraphicsManager, GPU_GET_GRMGR, 1, NV_FALSE, NV_TRUE, pGrMgr ) + GPU_CHILD_SINGLE_INST( GraphicsManager, GPU_GET_GRMGR, 1, NV_FALSE, pGrMgr ) #endif #if GPU_CHILD_MODULE(MIG_MANAGER) - GPU_CHILD_SINGLE_INST( MIGManager, GPU_GET_MIG_MANAGER, 1, NV_FALSE, NV_TRUE, pMIGManager ) + GPU_CHILD_SINGLE_INST( MIGManager, GPU_GET_MIG_MANAGER, 1, NV_FALSE, pMIGManager ) #endif #if GPU_CHILD_MODULE(KERNEL_MIG_MANAGER) - GPU_CHILD_SINGLE_INST( KernelMIGManager, GPU_GET_KERNEL_MIG_MANAGER, 1, NV_FALSE, NV_TRUE, pKernelMIGManager ) + GPU_CHILD_SINGLE_INST( KernelMIGManager, GPU_GET_KERNEL_MIG_MANAGER, 1, NV_FALSE, pKernelMIGManager ) #endif #if GPU_CHILD_MODULE(KERNEL_GRAPHICS_MANAGER) - GPU_CHILD_SINGLE_INST( KernelGraphicsManager, GPU_GET_KERNEL_GRAPHICS_MANAGER, 1, NV_FALSE, NV_TRUE, pKernelGraphicsManager ) + GPU_CHILD_SINGLE_INST( KernelGraphicsManager, GPU_GET_KERNEL_GRAPHICS_MANAGER, 1, NV_FALSE, pKernelGraphicsManager ) #endif #if GPU_CHILD_MODULE(GR) - GPU_CHILD_MULTI_INST ( Graphics, GPU_GET_GR_UNSAFE, GPU_MAX_GRS, NV_FALSE, NV_FALSE, pGr ) + GPU_CHILD_MULTI_INST ( Graphics, GPU_GET_GR_UNSAFE, GPU_MAX_GRS, NV_FALSE, pGr ) #endif #if GPU_CHILD_MODULE(KERNEL_GRAPHICS) - GPU_CHILD_MULTI_INST ( KernelGraphics, GPU_GET_KERNEL_GRAPHICS, GPU_MAX_GRS, NV_FALSE, NV_FALSE, pKernelGraphics ) + GPU_CHILD_MULTI_INST ( KernelGraphics, GPU_GET_KERNEL_GRAPHICS, GPU_MAX_GRS, NV_FALSE, pKernelGraphics ) #endif #if GPU_CHILD_MODULE(ClockManager) - GPU_CHILD_SINGLE_INST( ClockManager, GPU_GET_CLK_MGR, 1, NV_FALSE, NV_FALSE, pClk ) + GPU_CHILD_SINGLE_INST( ClockManager, GPU_GET_CLK_MGR, 1, NV_FALSE, pClk ) #endif #if GPU_CHILD_MODULE(FAN) - GPU_CHILD_SINGLE_INST( Fan, GPU_GET_FAN, 1, NV_FALSE, NV_FALSE, pFan ) + GPU_CHILD_SINGLE_INST( Fan, GPU_GET_FAN, 1, NV_FALSE, pFan ) #endif #if GPU_CHILD_MODULE(PERF) - GPU_CHILD_SINGLE_INST( Perf, GPU_GET_PERF, 1, NV_FALSE, NV_FALSE, pPerf ) + GPU_CHILD_SINGLE_INST( Perf, GPU_GET_PERF, 1, NV_FALSE, pPerf ) #endif #if GPU_CHILD_MODULE(KERNEL_PERF) - GPU_CHILD_SINGLE_INST( KernelPerf, GPU_GET_KERNEL_PERF, 1, NV_FALSE, NV_FALSE, pKernelPerf ) + GPU_CHILD_SINGLE_INST( KernelPerf, GPU_GET_KERNEL_PERF, 1, NV_FALSE, pKernelPerf ) #endif #if GPU_CHILD_MODULE(THERM) - GPU_CHILD_SINGLE_INST( Therm, GPU_GET_THERM, 1, NV_FALSE, NV_FALSE, pTherm ) + GPU_CHILD_SINGLE_INST( Therm, GPU_GET_THERM, 1, NV_FALSE, pTherm ) #endif #if GPU_CHILD_MODULE(BSP) - GPU_CHILD_MULTI_INST ( OBJBSP, GPU_GET_BSP, GPU_MAX_NVDECS, NV_FALSE, NV_FALSE, pBsp ) + GPU_CHILD_MULTI_INST ( OBJBSP, GPU_GET_BSP, GPU_MAX_NVDECS, NV_FALSE, pBsp ) #endif #if GPU_CHILD_MODULE(CIPHER) - GPU_CHILD_SINGLE_INST( OBJCIPHER, GPU_GET_CIPHER, 1, NV_FALSE, NV_FALSE, pCipher ) + GPU_CHILD_SINGLE_INST( OBJCIPHER, GPU_GET_CIPHER, 1, NV_FALSE, pCipher ) #endif #if GPU_CHILD_MODULE(VBIOS) - GPU_CHILD_SINGLE_INST( OBJVBIOS, GPU_GET_VBIOS, 1, NV_FALSE, NV_TRUE, pVbios ) + GPU_CHILD_SINGLE_INST( OBJVBIOS, GPU_GET_VBIOS, 1, NV_FALSE, pVbios ) #endif #if GPU_CHILD_MODULE(DCB) - GPU_CHILD_SINGLE_INST( OBJDCB, GPU_GET_DCB, 1, NV_FALSE, NV_TRUE, pDcb ) + GPU_CHILD_SINGLE_INST( OBJDCB, GPU_GET_DCB, 1, NV_FALSE, pDcb ) #endif #if GPU_CHILD_MODULE(GPIO) - GPU_CHILD_SINGLE_INST( OBJGPIO, GPU_GET_GPIO, 1, NV_FALSE, NV_TRUE, pGpio ) + GPU_CHILD_SINGLE_INST( OBJGPIO, GPU_GET_GPIO, 1, NV_FALSE, pGpio ) #endif #if GPU_CHILD_MODULE(VOLT) - GPU_CHILD_SINGLE_INST( OBJVOLT, GPU_GET_VOLT, 1, NV_FALSE, NV_FALSE, pVolt ) + GPU_CHILD_SINGLE_INST( OBJVOLT, GPU_GET_VOLT, 1, NV_FALSE, pVolt ) #endif #if GPU_CHILD_MODULE(I2C) - GPU_CHILD_SINGLE_INST( I2c, GPU_GET_I2C, 1, NV_FALSE, NV_TRUE, pI2c ) + GPU_CHILD_SINGLE_INST( I2c, GPU_GET_I2C, 1, NV_FALSE, pI2c ) #endif #if GPU_CHILD_MODULE(SPI) - GPU_CHILD_SINGLE_INST( Spi, GPU_GET_SPI, 1, NV_FALSE, NV_TRUE, pSpi ) + GPU_CHILD_SINGLE_INST( Spi, GPU_GET_SPI, 1, NV_FALSE, pSpi ) #endif #if GPU_CHILD_MODULE(KERNEL_RC) - GPU_CHILD_SINGLE_INST( KernelRc, GPU_GET_KERNEL_RC, 1, NV_FALSE, NV_TRUE, pKernelRc ) + GPU_CHILD_SINGLE_INST( KernelRc, GPU_GET_KERNEL_RC, 1, NV_FALSE, pKernelRc ) #endif #if GPU_CHILD_MODULE(RC) - GPU_CHILD_SINGLE_INST( OBJRC, GPU_GET_RC, 1, NV_FALSE, NV_TRUE, pRC ) + GPU_CHILD_SINGLE_INST( OBJRC, GPU_GET_RC, 1, NV_FALSE, pRC ) #endif #if GPU_CHILD_MODULE(STEREO) - GPU_CHILD_SINGLE_INST( OBJSTEREO, GPU_GET_STEREO, 1, NV_FALSE, NV_TRUE, pStereo ) + GPU_CHILD_SINGLE_INST( OBJSTEREO, GPU_GET_STEREO, 1, NV_FALSE, pStereo ) #endif #if GPU_CHILD_MODULE(INTR) - GPU_CHILD_SINGLE_INST( Intr, GPU_GET_INTR, 1, NV_FALSE, NV_TRUE, pIntr ) + GPU_CHILD_SINGLE_INST( Intr, GPU_GET_INTR, 1, NV_FALSE, pIntr ) #endif #if GPU_CHILD_MODULE(DPAUX) - GPU_CHILD_SINGLE_INST( OBJDPAUX, GPU_GET_DPAUX, 1, NV_FALSE, NV_FALSE, pDpAux ) + GPU_CHILD_SINGLE_INST( OBJDPAUX, GPU_GET_DPAUX, 1, NV_FALSE, pDpAux ) #endif #if GPU_CHILD_MODULE(PMU) - GPU_CHILD_SINGLE_INST( Pmu, GPU_GET_PMU, 1, NV_FALSE, NV_FALSE, pPmu ) + GPU_CHILD_SINGLE_INST( Pmu, GPU_GET_PMU, 1, NV_FALSE, pPmu ) #endif #if GPU_CHILD_MODULE(KERNEL_PMU) - GPU_CHILD_SINGLE_INST( KernelPmu, GPU_GET_KERNEL_PMU, 1, NV_FALSE, NV_FALSE, pKernelPmu ) + GPU_CHILD_SINGLE_INST( KernelPmu, GPU_GET_KERNEL_PMU, 1, NV_FALSE, pKernelPmu ) #endif #if GPU_CHILD_MODULE(CE) - GPU_CHILD_MULTI_INST ( OBJCE, GPU_GET_CE, GPU_MAX_CES, NV_FALSE, NV_FALSE, pCe ) + GPU_CHILD_MULTI_INST ( OBJCE, GPU_GET_CE, GPU_MAX_CES, NV_FALSE, pCe ) #endif #if GPU_CHILD_MODULE(KERNEL_CE) - GPU_CHILD_MULTI_INST ( KernelCE, GPU_GET_KCE, GPU_MAX_CES, NV_FALSE, NV_FALSE, pKCe ) + GPU_CHILD_MULTI_INST ( KernelCE, GPU_GET_KCE, GPU_MAX_CES, NV_FALSE, pKCe ) #endif #if GPU_CHILD_MODULE(MSENC) - GPU_CHILD_MULTI_INST ( OBJMSENC, GPU_GET_MSENC, GPU_MAX_MSENCS, NV_FALSE, NV_FALSE, pMsenc ) + GPU_CHILD_MULTI_INST ( OBJMSENC, GPU_GET_MSENC, GPU_MAX_MSENCS, NV_FALSE, pMsenc ) #endif #if GPU_CHILD_MODULE(HDA) - GPU_CHILD_SINGLE_INST( OBJHDA, GPU_GET_HDA, 1, NV_FALSE, NV_FALSE, pHda ) + GPU_CHILD_SINGLE_INST( OBJHDA, GPU_GET_HDA, 1, NV_FALSE, pHda ) #endif #if GPU_CHILD_MODULE(HDACODEC) - GPU_CHILD_SINGLE_INST( OBJHDACODEC, GPU_GET_HDACODEC, 1, NV_FALSE, NV_FALSE, pHdacodec ) + GPU_CHILD_SINGLE_INST( OBJHDACODEC, GPU_GET_HDACODEC, 1, NV_FALSE, pHdacodec ) #endif #if GPU_CHILD_MODULE(LPWR) - GPU_CHILD_SINGLE_INST( Lpwr, GPU_GET_LPWR, 1, NV_FALSE, NV_FALSE, pLpwr ) + GPU_CHILD_SINGLE_INST( Lpwr, GPU_GET_LPWR, 1, NV_FALSE, pLpwr ) #endif #if GPU_CHILD_MODULE(KERNEL_FIFO) - GPU_CHILD_SINGLE_INST( KernelFifo, GPU_GET_KERNEL_FIFO_UC, 1, NV_FALSE, NV_FALSE, pKernelFifo ) + GPU_CHILD_SINGLE_INST( KernelFifo, GPU_GET_KERNEL_FIFO_UC, 1, NV_FALSE, pKernelFifo ) #endif #if GPU_CHILD_MODULE(FIFO) - GPU_CHILD_SINGLE_INST( OBJFIFO, GPU_GET_FIFO_UC, 1, NV_FALSE, NV_FALSE, pFifo ) + GPU_CHILD_SINGLE_INST( OBJFIFO, GPU_GET_FIFO_UC, 1, NV_FALSE, pFifo ) #endif #if GPU_CHILD_MODULE(INFOROM) - GPU_CHILD_SINGLE_INST( OBJINFOROM, GPU_GET_INFOROM, 1, NV_FALSE, NV_TRUE, pInforom ) + GPU_CHILD_SINGLE_INST( OBJINFOROM, GPU_GET_INFOROM, 1, NV_FALSE, pInforom ) #endif #if GPU_CHILD_MODULE(PMGR) - GPU_CHILD_SINGLE_INST( Pmgr, GPU_GET_PMGR, 1, NV_FALSE, NV_FALSE, pPmgr ) + GPU_CHILD_SINGLE_INST( Pmgr, GPU_GET_PMGR, 1, NV_FALSE, pPmgr ) #endif #if GPU_CHILD_MODULE(UVM) - GPU_CHILD_SINGLE_INST( OBJUVM, GPU_GET_UVM, 1, NV_FALSE, NV_FALSE, pUvm ) + GPU_CHILD_SINGLE_INST( OBJUVM, GPU_GET_UVM, 1, NV_FALSE, pUvm ) #endif #if GPU_CHILD_MODULE(NV_DEBUG_DUMP) - GPU_CHILD_SINGLE_INST( NvDebugDump, GPU_GET_NVD, 1, NV_FALSE, NV_TRUE, pNvd ) + GPU_CHILD_SINGLE_INST( NvDebugDump, GPU_GET_NVD, 1, NV_FALSE, pNvd ) #endif #if GPU_CHILD_MODULE(GRDBG) - GPU_CHILD_SINGLE_INST( SMDebugger, GPU_GET_GRDBG, 1, NV_FALSE, NV_TRUE, pGrdbg ) + GPU_CHILD_SINGLE_INST( SMDebugger, GPU_GET_GRDBG, 1, NV_FALSE, pGrdbg ) #endif #if GPU_CHILD_MODULE(SEC2) - GPU_CHILD_SINGLE_INST( OBJSEC2, GPU_GET_SEC2, 1, NV_FALSE, NV_FALSE, pSec2 ) + GPU_CHILD_SINGLE_INST( OBJSEC2, GPU_GET_SEC2, 1, NV_FALSE, pSec2 ) #endif #if GPU_CHILD_MODULE(LSFM) - GPU_CHILD_SINGLE_INST( OBJLSFM, GPU_GET_LSFM, 1, NV_FALSE, NV_FALSE, pLsfm ) + GPU_CHILD_SINGLE_INST( OBJLSFM, GPU_GET_LSFM, 1, NV_FALSE, pLsfm ) #endif #if GPU_CHILD_MODULE(ACR) - GPU_CHILD_SINGLE_INST( OBJACR, GPU_GET_ACR, 1, NV_FALSE, NV_FALSE, pAcr ) + GPU_CHILD_SINGLE_INST( OBJACR, GPU_GET_ACR, 1, NV_FALSE, pAcr ) #endif #if GPU_CHILD_MODULE(KERNEL_NVLINK) - GPU_CHILD_SINGLE_INST( KernelNvlink, GPU_GET_KERNEL_NVLINK, 1, NV_FALSE, NV_FALSE, pKernelNvlink ) + GPU_CHILD_SINGLE_INST( KernelNvlink, GPU_GET_KERNEL_NVLINK, 1, NV_FALSE, pKernelNvlink ) #endif #if GPU_CHILD_MODULE(NVLINK) - GPU_CHILD_SINGLE_INST( Nvlink, GPU_GET_NVLINK, 1, NV_FALSE, NV_FALSE, pNvLink ) + GPU_CHILD_SINGLE_INST( Nvlink, GPU_GET_NVLINK, 1, NV_FALSE, pNvLink ) #endif #if GPU_CHILD_MODULE(GPULOG) - GPU_CHILD_SINGLE_INST( OBJGPULOG, GPU_GET_GPULOG, 1, NV_FALSE, NV_TRUE, pGpuLog ) + GPU_CHILD_SINGLE_INST( OBJGPULOG, GPU_GET_GPULOG, 1, NV_FALSE, pGpuLog ) #endif #if GPU_CHILD_MODULE(GPUMON) - GPU_CHILD_SINGLE_INST( OBJGPUMON, GPU_GET_GPUMON, 1, NV_FALSE, NV_TRUE, pGpuMon ) + GPU_CHILD_SINGLE_INST( OBJGPUMON, GPU_GET_GPUMON, 1, NV_FALSE, pGpuMon ) #endif #if GPU_CHILD_MODULE(HWPM) - GPU_CHILD_SINGLE_INST( OBJHWPM, GPU_GET_HWPM, 1, NV_FALSE, NV_FALSE, pHwpm ) + GPU_CHILD_SINGLE_INST( OBJHWPM, GPU_GET_HWPM, 1, NV_FALSE, pHwpm ) #endif #if GPU_CHILD_MODULE(GRIDDISPLAYLESS) - GPU_CHILD_SINGLE_INST( OBJGRIDDISPLAYLESS, GPU_GET_GRIDDISPLAYLESS, 1, NV_FALSE, NV_FALSE, pGridDisplayless ) + GPU_CHILD_SINGLE_INST( OBJGRIDDISPLAYLESS, GPU_GET_GRIDDISPLAYLESS, 1, NV_FALSE, pGridDisplayless ) #endif #if GPU_CHILD_MODULE(SWENG) - GPU_CHILD_SINGLE_INST( OBJSWENG, GPU_GET_SWENG, 1, NV_FALSE, NV_FALSE, pSwEng ) + GPU_CHILD_SINGLE_INST( OBJSWENG, GPU_GET_SWENG, 1, NV_FALSE, pSwEng ) #endif #if GPU_CHILD_MODULE(VMMU) - GPU_CHILD_SINGLE_INST( OBJVMMU, GPU_GET_VMMU, 1, NV_FALSE, NV_FALSE, pVmmu ) + GPU_CHILD_SINGLE_INST( OBJVMMU, GPU_GET_VMMU, 1, NV_FALSE, pVmmu ) #endif #if GPU_CHILD_MODULE(NVJPG) - GPU_CHILD_MULTI_INST( OBJNVJPG, GPU_GET_NVJPG, GPU_MAX_NVJPGS, NV_FALSE, NV_FALSE, pNvjpg ) + GPU_CHILD_MULTI_INST( OBJNVJPG, GPU_GET_NVJPG, GPU_MAX_NVJPGS, NV_FALSE, pNvjpg ) #endif #if GPU_CHILD_MODULE(GSP) - GPU_CHILD_SINGLE_INST( Gsp, GPU_GET_GSP, 1, NV_FALSE, NV_FALSE, pGsp ) + GPU_CHILD_SINGLE_INST( Gsp, GPU_GET_GSP, 1, NV_FALSE, pGsp ) #endif #if RMCFG_MODULE_KERNEL_FSP && GPU_CHILD_MODULE(KERNEL_FSP) - GPU_CHILD_SINGLE_INST( KernelFsp, GPU_GET_KERNEL_FSP, 1, NV_FALSE, NV_FALSE, pKernelFsp ) + GPU_CHILD_SINGLE_INST( KernelFsp, GPU_GET_KERNEL_FSP, 1, NV_FALSE, pKernelFsp ) #endif #if GPU_CHILD_MODULE(OFA) - GPU_CHILD_SINGLE_INST( OBJOFA, GPU_GET_OFA, 1, NV_FALSE, NV_FALSE, pOfa ) + GPU_CHILD_SINGLE_INST( OBJOFA, GPU_GET_OFA, 1, NV_FALSE, pOfa ) #endif #if RMCFG_MODULE_KERNEL_CCU && GPU_CHILD_MODULE(KERNEL_CCU) - GPU_CHILD_SINGLE_INST( KernelCcu, GPU_GET_KERNEL_CCU, 1, NV_FALSE, NV_FALSE, pKernelCcu ) + GPU_CHILD_SINGLE_INST( KernelCcu, GPU_GET_KERNEL_CCU, 1, NV_FALSE, pKernelCcu ) #endif // Undefine the entry macros to simplify call sites diff --git a/src/nvidia/inc/kernel/gpu/gpu_shared_data_map.h b/src/nvidia/inc/kernel/gpu/gpu_shared_data_map.h index 817b1ef23..dbafe28af 100644 --- a/src/nvidia/inc/kernel/gpu/gpu_shared_data_map.h +++ b/src/nvidia/inc/kernel/gpu/gpu_shared_data_map.h @@ -41,7 +41,16 @@ typedef struct GpuSharedDataMap { NV00DE_SHARED_DATA data; } GpuSharedDataMap; -// Start data write, returns data struct to write into +typedef struct GspUserSharedData { + NvU32 gspAssertCount; +} GspUserSharedData; + +/** + * Start data write, returns data struct to write into + * + * After updating data in the returned NV00DE_SHARED_DATA struct, + * call gpushareddataWriteFinish to push the new data into the user mapping + */ NV00DE_SHARED_DATA * gpushareddataWriteStart(OBJGPU *pGpu); // Finish data write, pushes data cached by above into mapped data void gpushareddataWriteFinish(OBJGPU *pGpu); diff --git a/src/nvidia/inc/kernel/gpu/gsp/gsp_fw_heap.h b/src/nvidia/inc/kernel/gpu/gsp/gsp_fw_heap.h new file mode 100644 index 000000000..11d2ec220 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/gsp/gsp_fw_heap.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef GSP_FW_HEAP_H +#define GSP_FW_HEAP_H + +// Static defines for the GSP FW WPR Heap +#define GSP_FW_HEAP_SIZE_LIBOS2 (64u << 20) +#define GSP_FW_HEAP_SIZE_LIBOS3_BAREMETAL (84u << 20) +#define GSP_FW_HEAP_SIZE_LIBOS3_VGPU (549u << 20) + +#endif // GSP_FW_HEAP_H diff --git a/src/nvidia/inc/kernel/gpu/gsp/gsp_init_args.h b/src/nvidia/inc/kernel/gpu/gsp/gsp_init_args.h index 85f3d5c68..6e27a7e4b 100644 --- a/src/nvidia/inc/kernel/gpu/gsp/gsp_init_args.h +++ b/src/nvidia/inc/kernel/gpu/gsp/gsp_init_args.h @@ -35,6 +35,8 @@ typedef struct { NvU32 pageTableEntryCount; NvLength cmdQueueOffset; NvLength statQueueOffset; + NvLength locklessCmdQueueOffset; + NvLength locklessStatQueueOffset; } MESSAGE_QUEUE_INIT_ARGUMENTS; typedef struct { diff --git a/src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h b/src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h index 816318b0f..a1e625204 100644 --- a/src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h +++ b/src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h @@ -98,6 +98,8 @@ typedef struct GspStaticConfigInfo_t NvBool bIsTitan; NvBool bIsTesla; NvBool bIsMobile; + NvBool bIsGc6Rtd3Allowed; + NvBool bIsGcOffRtd3Allowed; NvU64 bar1PdeBase; NvU64 bar2PdeBase; diff --git a/src/nvidia/inc/kernel/gpu/gsp/message_queue.h b/src/nvidia/inc/kernel/gpu/gsp/message_queue.h index a6888b63d..1b96b7a73 100644 --- a/src/nvidia/inc/kernel/gpu/gsp/message_queue.h +++ b/src/nvidia/inc/kernel/gpu/gsp/message_queue.h @@ -27,12 +27,18 @@ #ifndef _MESSAGE_QUEUE_H_ #define _MESSAGE_QUEUE_H_ +// Used for indexing into the MESSAGE_QUEUE_COLLECTION array. +#define RPC_TASK_RM_QUEUE_IDX 0 +#define RPC_TASK_ISR_QUEUE_IDX 1 +#define RPC_QUEUE_COUNT 2 + typedef struct _message_queue_info MESSAGE_QUEUE_INFO; +typedef struct MESSAGE_QUEUE_COLLECTION MESSAGE_QUEUE_COLLECTION; // CPU-side calls -NV_STATUS GspMsgQueueInit(OBJGPU *pGpu, MESSAGE_QUEUE_INFO **ppMQI); +NV_STATUS GspMsgQueuesInit(OBJGPU *pGpu, MESSAGE_QUEUE_COLLECTION **ppMQCollection); +void GspMsgQueuesCleanup(MESSAGE_QUEUE_COLLECTION **ppMQCollection); NV_STATUS GspStatusQueueInit(OBJGPU *pGpu, MESSAGE_QUEUE_INFO **ppMQI); -void GspMsgQueueCleanup(MESSAGE_QUEUE_INFO **ppMQI); NV_STATUS GspMsgQueueSendCommand(MESSAGE_QUEUE_INFO *pMQI, OBJGPU *pGpu); NV_STATUS GspMsgQueueReceiveStatus(MESSAGE_QUEUE_INFO *pMQI); diff --git a/src/nvidia/inc/kernel/gpu/gsp/message_queue_priv.h b/src/nvidia/inc/kernel/gpu/gsp/message_queue_priv.h index a4607ee79..4319e71c6 100644 --- a/src/nvidia/inc/kernel/gpu/gsp/message_queue_priv.h +++ b/src/nvidia/inc/kernel/gpu/gsp/message_queue_priv.h @@ -50,21 +50,14 @@ typedef struct GSP_MSG_QUEUE_ELEMENT typedef struct _message_queue_info { // Parameters - NvLength pageTableEntryCount; - NvLength pageTableSize; NvLength commandQueueSize; NvLength statusQueueSize; // Shared memory area. - MEMORY_DESCRIPTOR *pSharedMemDesc; - RmPhysAddr sharedMemPA; // Page table for all of shared mem. void *pCommandQueue; void *pStatusQueue; rpc_message_header_v *pRpcMsgBuf; // RPC message buffer VA. - void *pInitMsgBuf; // RPC message buffer VA. - RmPhysAddr initMsgBufPA; // RPC message buffer PA. - // Other CPU-side fields void *pWorkArea; GSP_MSG_QUEUE_ELEMENT *pCmdQueueElement; // Working copy of command queue element. @@ -72,8 +65,22 @@ typedef struct _message_queue_info msgqHandle hQueue; // Do not allow requests when hQueue is null. NvU32 txSeqNum; // Next sequence number for tx. NvU32 rxSeqNum; // Next sequence number for rx. + NvU32 queueIdx; // QueueIndex used to identify which task the message is supposed to be sent to. } MESSAGE_QUEUE_INFO; +typedef struct MESSAGE_QUEUE_COLLECTION +{ + // Parameters + NvLength pageTableEntryCount; + NvLength pageTableSize; + + // Shared memory area. + MEMORY_DESCRIPTOR *pSharedMemDesc; + RmPhysAddr sharedMemPA; // Page table for all of shared mem. + + MESSAGE_QUEUE_INFO rpcQueues[RPC_QUEUE_COUNT]; +} MESSAGE_QUEUE_COLLECTION; + // // Most of the following defines resolve to compile-time constants. // diff --git a/src/nvidia/inc/kernel/gpu/intr/engine_idx.h b/src/nvidia/inc/kernel/gpu/intr/engine_idx.h index 4f12aaab4..1490585d5 100644 --- a/src/nvidia/inc/kernel/gpu/intr/engine_idx.h +++ b/src/nvidia/inc/kernel/gpu/intr/engine_idx.h @@ -133,7 +133,10 @@ #define MC_ENGINE_IDX_GR6_FECS_LOG 160 #define MC_ENGINE_IDX_GR7_FECS_LOG 161 #define MC_ENGINE_IDX_TMR_SWRL 162 -#define MC_ENGINE_IDX_MAX 163 // This must be kept as the max bit if +#define MC_ENGINE_IDX_DISP_GSP 163 +#define MC_ENGINE_IDX_REPLAYABLE_FAULT_CPU 164 +#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT_CPU 165 +#define MC_ENGINE_IDX_MAX 166 // This must be kept as the max bit if // we need to add more engines #define MC_ENGINE_IDX_INVALID 0xFFFFFFFF diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/virt_mem_allocator_common.h b/src/nvidia/inc/kernel/gpu/mem_mgr/virt_mem_allocator_common.h index 7b1ea5342..adee05c30 100644 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/virt_mem_allocator_common.h +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/virt_mem_allocator_common.h @@ -47,13 +47,14 @@ typedef struct EVENTNOTIFICATION EVENTNOTIFICATION; // for address mapping; the system page size can be larger. // //--------------------------------------------------------------------------- -#define RM_PAGE_SIZE 4096 -#define RM_PAGE_SIZE_64K (64 * 1024) -#define RM_PAGE_SIZE_128K (128 * 1024) -#define RM_PAGE_MASK 0x0FFF -#define RM_PAGE_SHIFT 12 -#define RM_PAGE_SHIFT_64K 16 -#define RM_PAGE_SHIFT_128K 17 +#define RM_PAGE_SIZE_INVALID 0 +#define RM_PAGE_SIZE 4096 +#define RM_PAGE_SIZE_64K (64 * 1024) +#define RM_PAGE_SIZE_128K (128 * 1024) +#define RM_PAGE_MASK 0x0FFF +#define RM_PAGE_SHIFT 12 +#define RM_PAGE_SHIFT_64K 16 +#define RM_PAGE_SHIFT_128K 17 // Huge page size is 2 MB #define RM_PAGE_SHIFT_HUGE 21 diff --git a/src/nvidia/inc/kernel/gpu/mmu/vidmem_access_bit_buffer.h b/src/nvidia/inc/kernel/gpu/mmu/vidmem_access_bit_buffer.h new file mode 100644 index 000000000..1a170874b --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/mmu/vidmem_access_bit_buffer.h @@ -0,0 +1,3 @@ + +#include "g_vidmem_access_bit_buffer_nvoc.h" + diff --git a/src/nvidia/inc/kernel/gpu_mgr/gpu_mgr_sli.h b/src/nvidia/inc/kernel/gpu_mgr/gpu_mgr_sli.h new file mode 100644 index 000000000..181d88d51 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu_mgr/gpu_mgr_sli.h @@ -0,0 +1,59 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _RMSLIGPUMGR_H_ +#define _RMSLIGPUMGR_H_ + +void gpumgrDetectSliLinkFromGpus(NvBool, NvU32, NvU32, NvU32 *, NvU32 *, NvBool *, NvU32 *, NvU32 *); +NvBool gpumgrDetectHighSpeedVideoBridges(NvU32 linkOutputMask); +NvBool gpumgrUpdateSliLinkRouting(OBJGPU *pGpuParent, OBJGPU *pGpuChild, + NvU32 bridgeType, + NvU32 parentPinsetIndex, NvU32 childPinsetIndex, + NvBool bForceUpdate); +NV_STATUS gpumgrPinsetToPinsetTableIndex(NvU32 pinset, NvU32 *pPinsetIndex); +NV_STATUS gpumgrGetSliLinks(NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS *); + +#define drPinSet_None 0x0 +#define drPinSet_A 0x1 +#define drPinSet_B 0x2 +#define DR_PINSET_COUNT 2 + +//// Broadcast device defines +// +// These next defines are for the OBJGPUMGR.gpuSliLinkRoute array. +#define NV_SLILINK_ROUTE_INPUT 1:0 +#define NV_SLILINK_ROUTE_INPUT_UNTESTED 0x00 +#define NV_SLILINK_ROUTE_INPUT_IDENTITY 0x01 +#define NV_SLILINK_ROUTE_INPUT_FAILED 0x02 +#define NV_SLILINK_ROUTE_INPUT_PASSED 0x03 +#define NV_SLILINK_ROUTE_OUTPUT 3:2 +#define NV_SLILINK_ROUTE_OUTPUT_UNTESTED 0x00 +#define NV_SLILINK_ROUTE_OUTPUT_IDENTITY 0x01 +#define NV_SLILINK_ROUTE_OUTPUT_FAILED 0x02 +#define NV_SLILINK_ROUTE_OUTPUT_PASSED 0x03 +#define NV_SLILINK_ROUTE_INPUT_CHILD_PORT 7:4 +#define NV_SLILINK_ROUTE_NVLINK 8:8 +#define NV_SLILINK_ROUTE_NVLINK_TRUE 0x01 +#define NV_SLILINK_ROUTE_NVLINK_FALSE 0x02 + +#endif //_RMSLIGPUMGR_H_ diff --git a/src/nvidia/inc/kernel/mem_mgr/ctx_buf_pool.h b/src/nvidia/inc/kernel/mem_mgr/ctx_buf_pool.h index 65bdee084..967bc948e 100644 --- a/src/nvidia/inc/kernel/mem_mgr/ctx_buf_pool.h +++ b/src/nvidia/inc/kernel/mem_mgr/ctx_buf_pool.h @@ -77,7 +77,7 @@ NV_STATUS ctxBufPoolFree(CTX_BUF_POOL_INFO *pCtxBufPool, PMEMORY_DESCRIPTOR pMem void ctxBufPoolRelease(CTX_BUF_POOL_INFO *pCtxBufPool); void ctxBufPoolDestroy(CTX_BUF_POOL_INFO **ppCtxBufPool); NvBool ctxBufPoolIsSupported(OBJGPU *pGpu); -NV_STATUS ctxBufPoolGetSizeAndPageSize(CTX_BUF_POOL_INFO *pCtxBufPool, OBJGPU *pGpu, NvU64 alignment, RM_ATTR_PAGE_SIZE attr, NvBool bContig, NvU64 *pSize, NvU32 *pPageSize); +NV_STATUS ctxBufPoolGetSizeAndPageSize(CTX_BUF_POOL_INFO *pCtxBufPool, OBJGPU *pGpu, NvU64 alignment, RM_ATTR_PAGE_SIZE attr, NvBool bContig, NvU64 *pSize, NvU64 *pPageSize); NV_STATUS ctxBufPoolGetGlobalPool(OBJGPU *pGpu, CTX_BUF_ID bufId, RM_ENGINE_TYPE rmEngineType, CTX_BUF_POOL_INFO **ppCtxBufPool); NvBool ctxBufPoolIsScrubSkipped(CTX_BUF_POOL_INFO *pCtxBufPool); void ctxBufPoolSetScrubSkip(CTX_BUF_POOL_INFO *pCtxBufPool, NvBool bSkipScrub); diff --git a/src/nvidia/inc/kernel/mem_mgr/pool_alloc.h b/src/nvidia/inc/kernel/mem_mgr/pool_alloc.h index 03f383669..8f9e36f57 100644 --- a/src/nvidia/inc/kernel/mem_mgr/pool_alloc.h +++ b/src/nvidia/inc/kernel/mem_mgr/pool_alloc.h @@ -196,7 +196,7 @@ NvBool rmMemPoolIsScrubSkipped(RM_POOL_ALLOC_MEM_RESERVE_INFO *pMemReserveInf * NV_ERR_INVALID_ARGUMENT * NV_OK */ -NV_STATUS rmMemPoolGetChunkAndPageSize(RM_POOL_ALLOC_MEM_RESERVE_INFO *pMemReserveInfo, NvU64*, NvU32*); +NV_STATUS rmMemPoolGetChunkAndPageSize(RM_POOL_ALLOC_MEM_RESERVE_INFO *pMemReserveInfo, NvU64*, NvU64*); /*! * @brief Indicate that pool should be allocated in protected video memory in diff --git a/src/nvidia/inc/kernel/os/os_stub.h b/src/nvidia/inc/kernel/os/os_stub.h index 66167bf38..4ddcf9faa 100644 --- a/src/nvidia/inc/kernel/os/os_stub.h +++ b/src/nvidia/inc/kernel/os/os_stub.h @@ -53,9 +53,6 @@ OSSimEscapeWriteBuffer stubOsSimEscapeWriteBuffer; OSSimEscapeRead stubOsSimEscapeRead; OSSimEscapeReadBuffer stubOsSimEscapeReadBuffer; OSSetSurfaceName stubOsSetSurfaceName; -OSCallACPI_MXMX stubOsCallACPI_MXMX; -OSCallACPI_DSM stubOsCallACPI_DSM; -OSCallACPI_DDC stubOsCallACPI_DDC; OSCallACPI_BCL stubOsCallACPI_BCL; OSCallACPI_ON stubOsCallACPI_ON; OSCallACPI_OFF stubOsCallACPI_OFF; @@ -65,9 +62,7 @@ OSCallACPI_NVHG_GPUSTA stubOsCallWMI_NVHG_GPUSTA; OSCallACPI_NVHG_MXDS stubOsCallWMI_NVHG_MXDS; OSCallACPI_NVHG_MXMX stubOsCallWMI_NVHG_MXMX; OSCallACPI_NVHG_DOS stubOsCallWMI_NVHG_DOS; -OSCallACPI_NVHG_ROM stubOsCallWMI_NVHG_ROM; OSCallACPI_NVHG_DCS stubOsCallWMI_NVHG_DCS; -OSCallACPI_DOD stubOsCallWMI_DOD; OSCheckCallback stubOsCheckCallback; OSRCCallback stubOsRCCallback; @@ -80,9 +75,6 @@ OSPageArrayGetPhysAddr stubOsPageArrayGetPhysAddr; OSInternalReserveFreeCallback stubOsInternalReserveFreeCallback; OSInternalReserveAllocCallback stubOsInternalReserveAllocCallback; OSGetUefiVariable stubOsGetUefiVariable; -OSCallACPI_MXDS stubOsCallACPI_MXDS; -OSCallACPI_MXDM stubOsCallACPI_MXDM; -OSCallACPI_MXID stubOsCallACPI_MXID; OSCallACPI_LRST stubOsCallACPI_LRST; #endif // OS_STUB_H diff --git a/src/nvidia/inc/kernel/platform/platform_request_handler_utils.h b/src/nvidia/inc/kernel/platform/platform_request_handler_utils.h index 092e03fe1..d9c594df2 100644 --- a/src/nvidia/inc/kernel/platform/platform_request_handler_utils.h +++ b/src/nvidia/inc/kernel/platform/platform_request_handler_utils.h @@ -159,7 +159,7 @@ typedef struct _NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS * Used for PPL and TRL calls, which have up to three input DWORDs and three * output DWORDs. */ -#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX_MAX_SZ (3) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX_MAX_SZ (3U) typedef struct _NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX { @@ -170,29 +170,29 @@ typedef struct _NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX NvU32 output[NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX_MAX_SZ]; } NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX; -#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_TYPE 8:0 -#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SUPPORT (GPS_FUNC_SUPPORT) -#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PCONTROL (GPS_FUNC_PCONTROL) -#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHARESTATUS (GPS_FUNC_PSHARESTATUS) -#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_GETPPL (GPS_FUNC_GETPPL) -#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SETPPL (GPS_FUNC_SETPPL) -#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_GETTRL (GPS_FUNC_GETTRL) -#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SETTRL (GPS_FUNC_SETTRL) -#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_GETPPM (GPS_FUNC_GETPPM) -#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SETPPM (GPS_FUNC_SETPPM) -#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHAREPARAMS (GPS_FUNC_PSHAREPARAMS) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_TYPE 8:0 +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SUPPORT (GPS_FUNC_SUPPORT) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PCONTROL (GPS_FUNC_PCONTROL) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHARESTATUS (GPS_FUNC_PSHARESTATUS) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_GETPPL (GPS_FUNC_GETPPL) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SETPPL (GPS_FUNC_SETPPL) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_GETTRL (GPS_FUNC_GETTRL) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SETTRL (GPS_FUNC_SETTRL) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_GETPPM (GPS_FUNC_GETPPM) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SETPPM (GPS_FUNC_SETPPM) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHAREPARAMS (GPS_FUNC_PSHAREPARAMS) // PFM_REQ_HNDLR_SUPPORT output -#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_SUPPORT_AVAIL 0:0 -#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_PCONTROL_AVAIL 28:28 -#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_PSHARESTATUS_AVAIL 32:32 -#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_GETPPL_AVAIL 36:36 -#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_SETPPL_AVAIL 37:37 -#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_GETTRL_AVAIL 38:38 -#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_SETTRL_AVAIL 39:39 -#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_GETPPM_AVAIL 40:40 -#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_SETPPM_AVAIL 41:41 -#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_PSHAREPARAMS_AVAIL 42:42 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_SUPPORT_AVAIL 0:0 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_PCONTROL_AVAIL 28:28 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_PSHARESTATUS_AVAIL 32:32 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_GETPPL_AVAIL 36:36 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_SETPPL_AVAIL 37:37 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_GETTRL_AVAIL 38:38 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_SETTRL_AVAIL 39:39 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_GETPPM_AVAIL 40:40 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_SETPPM_AVAIL 41:41 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_PSHAREPARAMS_AVAIL 42:42 // PFM_REQ_HNDLR_PCONTROL #define NV0000_CTRL_PFM_REQ_HNDLR_PCONTROL_REQ_TYPE 3:0 @@ -209,25 +209,25 @@ typedef struct _NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX // PFM_REQ_HNDLR_PSHARESTATUS #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_UPDATE_LIMIT 0:0 // output only -#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_UPDATE_LIMIT_NOT_PENDING (0) -#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_UPDATE_LIMIT_PENDING (1) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_UPDATE_LIMIT_NOT_PENDING (0) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_UPDATE_LIMIT_PENDING (1) #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_DO_NOT_USE 19:1 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLAT_USER_CONFIG_TGP_MODE_SUPPORT 20:20 // output only -#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLAT_USER_CONFIG_TGP_MODE_SUPPORT_DISABLE (0) -#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLAT_USER_CONFIG_TGP_MODE_SUPPORT_ENABLE (1) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLAT_USER_CONFIG_TGP_MODE_SUPPORT_DISABLE (0) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLAT_USER_CONFIG_TGP_MODE_SUPPORT_ENABLE (1) #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_EDPPEAK_LIMIT_UPDATE 21:21 // output only -#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_EDPPEAK_LIMIT_UPDATE_FALSE (0) -#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_EDPPEAK_LIMIT_UPDATE_TRUE (1) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_EDPPEAK_LIMIT_UPDATE_FALSE (0) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_EDPPEAK_LIMIT_UPDATE_TRUE (1) #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_USER_CONFIG_TGP_MODE 22:22 // output only -#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_USER_CONFIG_TGP_MODE_DISABLE (0) -#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_USER_CONFIG_TGP_MODE_ENABLE (1) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_USER_CONFIG_TGP_MODE_DISABLE (0) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_USER_CONFIG_TGP_MODE_ENABLE (1) // Shared by GETPPL, SETPPL #define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_COUNT (3) #define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_VERSION_IDX (0) -#define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARG0_VERSION_MINOR 15:0 // input & output -#define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARG0_VERSION_MAJOR 31:16 // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARG0_VERSION_MINOR 15:0 // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARG0_VERSION_MAJOR 31:16 // input & output #define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARG0_VERSION_MAJOR_V1 (1) // input & output #define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_LIMIT1_IDX (1) // input & output #define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_LIMIT2_IDX (2) // input & output @@ -235,19 +235,19 @@ typedef struct _NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX // Shared by GETTRL, SETTRL #define NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARGS_COUNT (2) #define NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARGS_VERSION_IDX (0) -#define NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARG0_VERSION_MINOR 15:0 // input & output -#define NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARG0_VERSION_MAJOR 31:16 // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARG0_VERSION_MINOR 15:0 // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARG0_VERSION_MAJOR 31:16 // input & output #define NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARG0_VERSION_MAJOR_V1 (1) // input & output #define NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARGS_FREQ_MHZ_IDX (1) // input & output // Shared by GETPPM, SETPPM #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_COUNT (2) #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_VERSION_IDX (0) -#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARG0_VERSION_MINOR 15:0 // input & output -#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARG0_VERSION_MAJOR 31:16 // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARG0_VERSION_MINOR 15:0 // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARG0_VERSION_MAJOR 31:16 // input & output #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARG0_VERSION_MAJOR_V1 (1) // input & output #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_IDX (1) // input & output -#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_INDEX 7:0 // output +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_INDEX 7:0 // output #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_AVAILABLE_MASK 15:8 // output // @@ -262,10 +262,10 @@ typedef struct _NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_TGPU_FALSE (0) #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_TGPU_TRUE (1) #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_DO_NOT_USE 14:9 // input & output -#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_CTGP 15:15 // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_CTGP 15:15 // input & output #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_CTGP_FALSE (0) #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_CTGP_TRUE (1) -#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_PPMD 16:16 // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_PPMD 16:16 // input & output #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_PPMD_FALSE (0) #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_PPMD_TRUE (1) diff --git a/src/nvidia/inc/kernel/platform/sli/sli.h b/src/nvidia/inc/kernel/platform/sli/sli.h index 969069ba9..79b3c60ca 100644 --- a/src/nvidia/inc/kernel/platform/sli/sli.h +++ b/src/nvidia/inc/kernel/platform/sli/sli.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2000-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2000-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -38,6 +38,8 @@ // Unlinked SLI is implemented in RM clients #define IsUnlinkedSLIEnabled(p) ((p)->getProperty((p), PDB_PROP_GPU_RM_UNLINKED_SLI)) +void RmInitScalability(OBJGPU *pGpu); + #define IsSLIEnabled(p) 0 #define NumSubDevices(p) 0 diff --git a/src/nvidia/inc/kernel/rmapi/control.h b/src/nvidia/inc/kernel/rmapi/control.h index ef13988b1..fb64b6fe1 100644 --- a/src/nvidia/inc/kernel/rmapi/control.h +++ b/src/nvidia/inc/kernel/rmapi/control.h @@ -37,8 +37,8 @@ typedef RS_RES_CONTROL_PARAMS_INTERNAL RmCtrlParams; // RMCTRL_API_COPPY_FLAGS is used to specify control api copy behavior. #define RMCTRL_API_COPY_FLAGS_NONE 0x00000000 -// skip memory copy in api copy in -#define RMCTRL_API_COPY_FLAGS_SKIP_COPYIN NVBIT(0) +// skip memory copy in api copy in and zero the buffer +#define RMCTRL_API_COPY_FLAGS_SKIP_COPYIN_ZERO_BUFFER NVBIT(0) // set control cache on api copy out #define RMCTRL_API_COPY_FLAGS_SET_CONTROL_CACHE NVBIT(1) @@ -291,6 +291,17 @@ NV_STATUS embeddedParamCopyOut(RMAPI_PARAM_COPY *pParamCopy, RmCtrlParams *pRmC // #define RMCTRL_FLAGS_GSP_PLUGIN_FOR_VGPU_GSP 0x000100000 +// +// This flag specifies that the control output depends on the input +// parameters but can be cached on receiving end. Since the control +// result depends on the input and the input varifies with controls, +// the cache should be handled in a per-control bases. +// +#define RMCTRL_FLAGS_CACHEABLE_BY_INPUT 0x000200000 + +// The combination of cacheable flags +#define RMCTRL_FLAGS_CACHEABLE_ANY (RMCTRL_FLAGS_CACHEABLE | RMCTRL_FLAGS_CACHEABLE_BY_INPUT) + // // 'ACCESS_RIGHTS' Attribute // ------------------------ diff --git a/src/nvidia/inc/kernel/rmapi/mapping_list.h b/src/nvidia/inc/kernel/rmapi/mapping_list.h index 16edf1823..fb15d680d 100644 --- a/src/nvidia/inc/kernel/rmapi/mapping_list.h +++ b/src/nvidia/inc/kernel/rmapi/mapping_list.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -50,7 +50,6 @@ typedef struct _def_client_dma_alloc_map_info CLI_DMA_ALLOC_MAP_INFO; // struct _def_client_dma_mapping_info { - NvHandle hDevice; NvU64 DmaOffset; void* KernelVAddr[NV_MAX_SUBDEVICES]; // Kernel's virtual address, if required void* KernelPriv; // Token required to unmap the kernel mapping @@ -60,11 +59,11 @@ struct _def_client_dma_mapping_info NvU32 Flags; NvBool bP2P; NvU32 gpuMask; + NvU64 mapPageSize; // Page size at which the memory is mapped. ADDRESS_TRANSLATION addressTranslation; MEMORY_DESCRIPTOR *pBar1P2PVirtMemDesc; // The peer GPU mapped BAR1 region MEMORY_DESCRIPTOR *pBar1P2PPhysMemDesc; // The peer GPU vidmem sub region - PCLI_DMA_MAPPING_INFO Next; - PCLI_DMA_MAPPING_INFO Prev; + CLI_DMA_MAPPING_INFO *pNext; }; // @@ -72,8 +71,7 @@ struct _def_client_dma_mapping_info // struct _def_client_dma_mapping_info_iterator { - PNODE pDmaMappingList; // list of hDevices - PNODE pCurrentList; // current hDevice list entry, is list of pDmaMappings + PNODE pDmaMappingList; // list of pDmaMappings PNODE pNextDmaMapping; // next pDmaMapping while iterating over the DmaOffsets }; @@ -159,16 +157,14 @@ CliUpdateDeviceMemoryMapping RsCpuMapping *CliFindMappingInClient (NvHandle, NvHandle, NvP64); // DMA Mappings -NV_STATUS intermapCreateDmaMapping (RsClient *, RsResourceRef *, NvHandle, NvHandle, PCLI_DMA_MAPPING_INFO *, NvU32); -NV_STATUS intermapRegisterDmaMapping (RsClient *, NvHandle, NvHandle, PCLI_DMA_MAPPING_INFO, NvU64, NvU32); -NV_STATUS intermapDelDmaMapping (RsClient *, NvHandle, NvHandle, NvU64, NvU32, NvBool*); +NV_STATUS intermapCreateDmaMapping (RsClient *, VirtualMemory *, PCLI_DMA_MAPPING_INFO *, NvU32); +NV_STATUS intermapRegisterDmaMapping (RsClient *, VirtualMemory *, PCLI_DMA_MAPPING_INFO, NvU64, NvU32); +NV_STATUS intermapDelDmaMapping (RsClient *, VirtualMemory *, NvU64, NvU32); void intermapFreeDmaMapping (PCLI_DMA_MAPPING_INFO); +CLI_DMA_MAPPING_INFO *intermapGetDmaMapping (VirtualMemory *pVirtualMemory, NvU64 dmaOffset, NvU32 gpuMask); NvBool CliGetDmaMappingInfo (NvHandle, NvHandle, NvHandle, NvU64, NvU32, PCLI_DMA_MAPPING_INFO*); void CliGetDmaMappingIterator (PCLI_DMA_MAPPING_INFO *, PCLI_DMA_MAPPING_INFO_ITERATOR, PNODE pDmaMappingList); void CliGetDmaMappingNext (PCLI_DMA_MAPPING_INFO *, PCLI_DMA_MAPPING_INFO_ITERATOR); -// Unmap all DMA mappings between a memory resource and any DynamicMemory -NV_STATUS intermapUnmapDeviceMemoryDma (RsClient *, RsResourceRef *, NvHandle); - #endif diff --git a/src/nvidia/inc/kernel/rmapi/nv_gpu_ops.h b/src/nvidia/inc/kernel/rmapi/nv_gpu_ops.h index c298257dd..1d80205ef 100644 --- a/src/nvidia/inc/kernel/rmapi/nv_gpu_ops.h +++ b/src/nvidia/inc/kernel/rmapi/nv_gpu_ops.h @@ -76,26 +76,26 @@ NV_STATUS nvGpuOpsMemoryAllocSys (gpuAddressSpaceHandle vaSpace, NV_STATUS nvGpuOpsPmaAllocPages(void *pPma, NvLength pageCount, - NvU32 pageSize, + NvU64 pageSize, gpuPmaAllocationOptions *pPmaAllocOptions, NvU64 *pPages); void nvGpuOpsPmaFreePages(void *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize, + NvU64 pageSize, NvU32 flags); NV_STATUS nvGpuOpsPmaPinPages(void *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize, + NvU64 pageSize, NvU32 flags); NV_STATUS nvGpuOpsPmaUnpinPages(void *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize); + NvU64 pageSize); NV_STATUS nvGpuOpsChannelAllocate(gpuAddressSpaceHandle vaSpace, const gpuChannelAllocParams *params, @@ -112,7 +112,7 @@ void nvGpuOpsMemoryFree(gpuAddressSpaceHandle vaSpace, NV_STATUS nvGpuOpsMemoryCpuMap(gpuAddressSpaceHandle vaSpace, NvU64 memory, NvLength length, - void **cpuPtr, NvU32 pageSize); + void **cpuPtr, NvU64 pageSize); void nvGpuOpsMemoryCpuUnMap(gpuAddressSpaceHandle vaSpace, void* cpuPtr); @@ -270,4 +270,6 @@ NV_STATUS nvGpuOpsPagingChannelPushStream(UvmGpuPagingChannel *channel, char *methodStream, NvU32 methodStreamSize); +NV_STATUS nvGpuOpsFlushReplayableFaultBuffer(struct gpuDevice *device); + #endif /* _NV_GPU_OPS_H_*/ diff --git a/src/nvidia/inc/kernel/rmapi/rmapi.h b/src/nvidia/inc/kernel/rmapi/rmapi.h index a82ba6385..9930189bd 100644 --- a/src/nvidia/inc/kernel/rmapi/rmapi.h +++ b/src/nvidia/inc/kernel/rmapi/rmapi.h @@ -63,6 +63,7 @@ void rmapiShutdown(void); // already held then return error #define RMAPI_LOCK_FLAGS_READ NVBIT(1) // Acquire API lock for READ #define RMAPI_LOCK_FLAGS_WRITE (0x00000000) // Acquire API lock for WRITE - Default +#define RMAPI_LOCK_FLAGS_LOW_PRIORITY NVBIT(2) // Deprioritize lock acquire /** * Acquire the RM API Lock @@ -147,11 +148,11 @@ struct _RM_API NV_STATUS (*FreeWithSecInfo)(struct _RM_API *pRmApi, NvHandle hClient, NvHandle hObject, NvU32 flags, API_SECURITY_INFO *pSecInfo); - // Free a list of clients with default security attributes - NV_STATUS (*FreeClientList)(struct _RM_API *pRmApi, NvHandle *phClientList, NvU32 numClients); + // Disables all clients in the list, with default security attributes + NV_STATUS (*DisableClients)(struct _RM_API *pRmApi, NvHandle *phClientList, NvU32 numClients); - // Free a list of clients - NV_STATUS (*FreeClientListWithSecInfo)(struct _RM_API *pRmApi, NvHandle *phClientList, + // Disables all clients in the list + NV_STATUS (*DisableClientsWithSecInfo)(struct _RM_API *pRmApi, NvHandle *phClientList, NvU32 numClients, API_SECURITY_INFO *pSecInfo); // Invoke a control with default security attributes and local pointers (no NvP64) @@ -269,7 +270,7 @@ NvBool rmapiCmdIsCacheable(NvU32 cmd, NvBool bAllowInternal); NV_STATUS rmapiControlCacheGet(NvHandle hClient, NvHandle hObject, NvU32 cmd, void* params, NvU32 paramsSize); NV_STATUS rmapiControlCacheSet(NvHandle hClient, NvHandle hObject, NvU32 cmd, - const void* params, NvU32 paramsSize); + void* params, NvU32 paramsSize); NV_STATUS rmapiControlCacheSetGpuInstForObject(NvHandle hClient, NvHandle hObject, NvU32 gpuInst); void rmapiControlCacheFreeAllCacheForGpu(NvU32 gpuInst); void rmapiControlCacheSetMode(NvU32 mode); diff --git a/src/nvidia/inc/kernel/virtualization/common_vgpu_mgr.h b/src/nvidia/inc/kernel/virtualization/common_vgpu_mgr.h index 8d771adb8..fb5f5a25e 100644 --- a/src/nvidia/inc/kernel/virtualization/common_vgpu_mgr.h +++ b/src/nvidia/inc/kernel/virtualization/common_vgpu_mgr.h @@ -83,6 +83,7 @@ vgpuMgrReserveSystemChannelIDs(OBJGPU *pGpu, VGPU_TYPE *vgpuTypeInfo, NvU32 gfid, NvU32 *pChidOffset, + NvU32 *pChannelCount, NvHandle hClient, NvU32 numChannels, NvU32 engineFifoListNumEntries, @@ -92,6 +93,7 @@ void vgpuMgrFreeSystemChannelIDs(OBJGPU *pGpu, NvU32 gfid, NvU32 *pChidOffset, + NvU32 *pChannelCount, NvHandle hClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *engineFifoList); diff --git a/src/nvidia/inc/lib/base_utils.h b/src/nvidia/inc/lib/base_utils.h index 27ab7b1a3..44e87b46d 100644 --- a/src/nvidia/inc/lib/base_utils.h +++ b/src/nvidia/inc/lib/base_utils.h @@ -68,6 +68,9 @@ NvU64 nvMsb64(NvU64); // char * nvU32ToStr(NvU32 value, char *string, NvU32 radix); +/*! Converts unsigned long long hex int to string */ +char * nvU64ToStr(NvU64 value, char *string, NvU32 targedStrLen); + // // Find the string length // diff --git a/src/nvidia/inc/lib/protobuf/prb_util.h b/src/nvidia/inc/lib/protobuf/prb_util.h index d8f2fb483..4289a1e52 100644 --- a/src/nvidia/inc/lib/protobuf/prb_util.h +++ b/src/nvidia/inc/lib/protobuf/prb_util.h @@ -70,13 +70,13 @@ typedef struct // #define PRB_REGS_MSG_OVERHEAD 13 -NV_STATUS prbEncGpuRegs(OBJGPU *pGpu, IO_APERTURE *pAperture, NvU64 offset, NvU32 numEntries, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); +NV_STATUS prbEncGpuRegs(OBJGPU *pGpu, IoAperture *pAperture, NvU64 offset, NvU32 numEntries, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); NV_STATUS prbEncGpuRegImm(OBJGPU *pGpu, NvU64 offset, NvU32 reg, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); -NV_STATUS prbEncGpuRegOffset(OBJGPU *pGpu, IO_APERTURE *pAperture, const NvU32 *pOffset, NvU32 numEntries, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); -NV_STATUS prbEncGpuRegSliceOffset(OBJGPU *pGpu, IO_APERTURE *pAperture, const NvU32 *pOffset, NvU32 numEntries, NvU32 base, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); -NV_STATUS prbEncGpuRegTbl(OBJGPU *pGpu, IO_APERTURE *pAperture, const PRB_GPU_REG_TABLE *pTbl, NvU32 numEntries, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); -NV_STATUS prbEncGpuRegSliceTbl(OBJGPU *pGpu, IO_APERTURE *pAperture, const PRB_GPU_REG_TABLE *pTbl, NvU32 numEntries, NvU32 base, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); -NV_STATUS prbEncGpuRegSliceIndexedTbl(OBJGPU *pGpu, IO_APERTURE *pAperture, const PRB_GPU_REG_INDEXED_TABLE *pTbl, NvU32 numEntries, NvU32 base, NvU32 index, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); +NV_STATUS prbEncGpuRegOffset(OBJGPU *pGpu, IoAperture *pAperture, const NvU32 *pOffset, NvU32 numEntries, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); +NV_STATUS prbEncGpuRegSliceOffset(OBJGPU *pGpu, IoAperture *pAperture, const NvU32 *pOffset, NvU32 numEntries, NvU32 base, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); +NV_STATUS prbEncGpuRegTbl(OBJGPU *pGpu, IoAperture *pAperture, const PRB_GPU_REG_TABLE *pTbl, NvU32 numEntries, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); +NV_STATUS prbEncGpuRegSliceTbl(OBJGPU *pGpu, IoAperture *pAperture, const PRB_GPU_REG_TABLE *pTbl, NvU32 numEntries, NvU32 base, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); +NV_STATUS prbEncGpuRegSliceIndexedTbl(OBJGPU *pGpu, IoAperture *pAperture, const PRB_GPU_REG_INDEXED_TABLE *pTbl, NvU32 numEntries, NvU32 base, NvU32 index, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); NV_STATUS prbEncMem(NvU64 offset, NvU32 numRegs, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); NV_STATUS prbEncInstMem(NvU64 physAddr, NvU8 *pVirtAddr, NvU32 numWords, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); NV_STATUS prbEncInstMemImm(NvU64 physAddr, NvU32 data, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc); diff --git a/src/nvidia/inc/libraries/ioaccess/ioaccess.h b/src/nvidia/inc/libraries/ioaccess/ioaccess.h index 42a36295b..6ca33d5ec 100644 --- a/src/nvidia/inc/libraries/ioaccess/ioaccess.h +++ b/src/nvidia/inc/libraries/ioaccess/ioaccess.h @@ -20,22 +20,18 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ +#if (defined(NVRM) || defined(RMCFG_FEATURE_PLATFORM_GSP)) && !defined(NVWATCH) +#include "g_ioaccess_nvoc.h" +#endif + #ifndef _IO_ACCESS_H_ #define _IO_ACCESS_H_ #include "nvtypes.h" #include "nvstatus.h" - -typedef struct IO_DEVICE IO_DEVICE, *PIO_DEVICE; -typedef struct IO_APERTURE IO_APERTURE, *PIO_APERTURE; - -typedef NvU8 ReadReg008Fn(PIO_APERTURE a, NvU32 addr); -typedef NvU16 ReadReg016Fn(PIO_APERTURE a, NvU32 addr); -typedef NvU32 ReadReg032Fn(PIO_APERTURE a, NvU32 addr); -typedef void WriteReg008Fn(PIO_APERTURE a, NvU32 addr, NvV8 value); -typedef void WriteReg016Fn(PIO_APERTURE a, NvU32 addr, NvV16 value); -typedef void WriteReg032Fn(PIO_APERTURE a, NvU32 addr, NvV32 value); -typedef NvBool ValidRegFn(PIO_APERTURE a, NvU32 addr); +#if (defined(NVRM) || defined(RMCFG_FEATURE_PLATFORM_GSP)) && !defined(NVWATCH) +#include "nvoc/prelude.h" +#endif #define REG_DRF_SHIFT(drf) ((0?drf) % 32) #define REG_DRF_MASK(drf) (0xFFFFFFFF>>(31-((1?drf) % 32)+((0?drf) % 32))) @@ -45,6 +41,48 @@ typedef NvBool ValidRegFn(PIO_APERTURE a, NvU32 addr); #define REG_DRF_SHIFTMASK(drf) (REG_DRF_MASK(drf)<<(REG_DRF_SHIFT(drf))) #define REG_DRF_WIDTH(drf) ((1?drf) - (0?drf) + 1) +#if (defined(NVRM) || defined(RMCFG_FEATURE_PLATFORM_GSP)) && !defined(NVWATCH) +#define REG_RD08(ap, addr) regaprtReadReg08 (staticCast(ap, RegisterAperture), addr) +#define REG_RD16(ap, addr) regaprtReadReg16 (staticCast(ap, RegisterAperture), addr) +#define REG_RD32(ap, addr) regaprtReadReg32 (staticCast(ap, RegisterAperture), addr) +#define REG_WR08(ap, addr, val) regaprtWriteReg08 (staticCast(ap, RegisterAperture), addr, val) +#define REG_WR16(ap, addr, val) regaprtWriteReg16 (staticCast(ap, RegisterAperture), addr, val) +#define REG_WR32(ap, addr, val) regaprtWriteReg32 (staticCast(ap, RegisterAperture), addr, val) +#define REG_WR32_UC(ap, addr, val) regaprtWriteReg32Uc(staticCast(ap, RegisterAperture), addr, val) +#define REG_VALID(ap, addr) regaprtIsRegValid (staticCast(ap, RegisterAperture), addr) + +NVOC_PREFIX(regaprt) +class RegisterAperture +{ +public: + virtual NvU8 regaprtReadReg08 (RegisterAperture *pAperture, NvU32 addr) = 0; + virtual NvU16 regaprtReadReg16 (RegisterAperture *pAperture, NvU32 addr) = 0; + virtual NvU32 regaprtReadReg32 (RegisterAperture *pAperture, NvU32 addr) = 0; + virtual void regaprtWriteReg08 (RegisterAperture *pAperture, NvU32 addr, NvV8 value) = 0; + virtual void regaprtWriteReg16 (RegisterAperture *pAperture, NvU32 addr, NvV16 value) = 0; + virtual void regaprtWriteReg32 (RegisterAperture *pAperture, NvU32 addr, NvV32 value) = 0; + virtual void regaprtWriteReg32Uc(RegisterAperture *pAperture, NvU32 addr, NvV32 value) = 0; + virtual NvBool regaprtIsRegValid (RegisterAperture *pAperture, NvU32 addr) = 0; +}; + +// +// TODO: Remove the wrapper structure WAR once NVOC supports in-place object construction +// The proxy structure was introduced to avoid major refactoring until the feature is implemented +// Also fix IoAperture getters +// Use the interface class in NVWATCH once NVOC is enabled there +// +#else // (defined(NVRM) || defined(RMCFG_FEATURE_PLATFORM_GSP)) && !defined(NVWATCH) +typedef struct IO_DEVICE IO_DEVICE; +typedef struct IO_APERTURE IO_APERTURE; + +typedef NvU8 ReadReg008Fn(IO_APERTURE *a, NvU32 addr); +typedef NvU16 ReadReg016Fn(IO_APERTURE *a, NvU32 addr); +typedef NvU32 ReadReg032Fn(IO_APERTURE *a, NvU32 addr); +typedef void WriteReg008Fn(IO_APERTURE *a, NvU32 addr, NvV8 value); +typedef void WriteReg016Fn(IO_APERTURE *a, NvU32 addr, NvV16 value); +typedef void WriteReg032Fn(IO_APERTURE *a, NvU32 addr, NvV32 value); +typedef NvBool ValidRegFn(IO_APERTURE *a, NvU32 addr); + #define REG_RD08(ap, addr) (ap)->pDevice->pReadReg008Fn((ap), (addr)) #define REG_RD16(ap, addr) (ap)->pDevice->pReadReg016Fn((ap), (addr)) #define REG_RD32(ap, addr) (ap)->pDevice->pReadReg032Fn((ap), (addr)) @@ -57,6 +95,36 @@ typedef NvBool ValidRegFn(PIO_APERTURE a, NvU32 addr); // Get the address of a register given the Aperture and offset. #define REG_GET_ADDR(ap, offset) ((ap)->baseAddress + (offset)) +struct IO_DEVICE +{ + ReadReg008Fn *pReadReg008Fn; + ReadReg016Fn *pReadReg016Fn; + ReadReg032Fn *pReadReg032Fn; + WriteReg008Fn *pWriteReg008Fn; + WriteReg016Fn *pWriteReg016Fn; + WriteReg032Fn *pWriteReg032Fn; + WriteReg032Fn *pWriteReg032UcFn; + ValidRegFn *pValidRegFn; +}; + +struct IO_APERTURE +{ + IO_DEVICE *pDevice; // Pointer to module specific IO_DEVICE + NvU32 baseAddress; // register base address + NvU32 length; // length of aperture +}; + +NV_STATUS ioaccessInitIOAperture +( + IO_APERTURE *pAperture, + IO_APERTURE *pParentAperture, + IO_DEVICE *pDevice, + NvU32 offset, + NvU32 length +); +#endif // (defined(NVRM) || defined(RMCFG_FEATURE_PLATFORM_GSP)) && !defined(NVWATCH) + + // // Macros for register I/O // @@ -77,49 +145,4 @@ typedef NvBool ValidRegFn(PIO_APERTURE a, NvU32 addr); #define REG_RD_DRF_IDX(ap,d,r,f,i) (((REG_RD32(ap,NV ## d ## r))>>REG_DRF_SHIFT(NV ## d ## r ## f(i)))®_DRF_MASK(NV ## d ## r ## f(i))) #define REG_IDX_OFFSET_RD_DRF(ap,d,r,i,o,f) (((REG_RD32(ap,NV ## d ## r(i,o)))>>REG_DRF_SHIFT(NV ## d ## r ## f))®_DRF_MASK(NV ## d ## r ## f)) -struct IO_DEVICE -{ - ReadReg008Fn *pReadReg008Fn; - ReadReg016Fn *pReadReg016Fn; - ReadReg032Fn *pReadReg032Fn; - WriteReg008Fn *pWriteReg008Fn; - WriteReg016Fn *pWriteReg016Fn; - WriteReg032Fn *pWriteReg032Fn; - WriteReg032Fn *pWriteReg032UcFn; - ValidRegFn *pValidRegFn; -}; - -struct IO_APERTURE -{ - PIO_DEVICE pDevice; // Pointer to module specific IO_DEVICE - NvU32 baseAddress; // register base address - NvU32 length; // length of aperture -}; - -//--------------------------------------------------------------------------- -// -// Function prototypes. -// -//--------------------------------------------------------------------------- - -NV_STATUS ioaccessCreateIOAperture -( - IO_APERTURE **ppAperture, - IO_APERTURE *pParentAperture, - IO_DEVICE *pDevice, - NvU32 offset, - NvU32 length -); - -NV_STATUS ioaccessInitIOAperture -( - IO_APERTURE *pAperture, - IO_APERTURE *pParentAperture, - IO_DEVICE *pDevice, - NvU32 offset, - NvU32 length -); - -void ioaccessDestroyIOAperture(IO_APERTURE *pAperture); - #endif // _IO_ACCESS_H_ diff --git a/src/nvidia/inc/libraries/nvoc/object.h b/src/nvidia/inc/libraries/nvoc/object.h index 285c00911..cd1231b1e 100644 --- a/src/nvidia/inc/libraries/nvoc/object.h +++ b/src/nvidia/inc/libraries/nvoc/object.h @@ -62,6 +62,9 @@ public: //! IP Version value. Temporary until NVOC-style HALs are rolled out. NvU32 ipVersion; + //! flags used to create the object. + NvU32 createFlags; + /*! * @brief Add pChild as a child of this object. * @@ -118,8 +121,6 @@ public: #define NV_ODB_IP_VER_MAJOR 31:24 /* R-IVF */ #define IPVersion(pObj) staticCast((pObj), Object)->ipVersion -#define IsIPVersionValid(pObj) (DRF_VAL(_ODB, _IP_VER, _MAJOR, IPVersion(pObj)) != 0) -#define IsIPVersionOrLater(pObj, v0) (IPVersion(pObj) >= (v0)) // v0 .. v1 inclusive #define IsIPVersionInRange(pObj, v0, v1) ((IPVersion(pObj) >= (v0)) && (IPVersion(pObj) <= (v1))) diff --git a/src/nvidia/inc/libraries/nvoc/prelude.h b/src/nvidia/inc/libraries/nvoc/prelude.h index 1e1b14b4c..a76ba1615 100644 --- a/src/nvidia/inc/libraries/nvoc/prelude.h +++ b/src/nvidia/inc/libraries/nvoc/prelude.h @@ -106,9 +106,13 @@ * Default behavior * NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY * Use halspec from parent without adding the new created object the child tree + * NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT + * Skip memory allocation on object create, assume the argument points to memory + * already allocated. */ #define NVOC_OBJ_CREATE_FLAGS_NONE 0x0000u #define NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY 0x0001u +#define NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT 0x0002u /*! * @brief Create and construct a new object by class name. diff --git a/src/nvidia/inc/libraries/nvoc/runtime.h b/src/nvidia/inc/libraries/nvoc/runtime.h index bf59317e4..4581d4774 100644 --- a/src/nvidia/inc/libraries/nvoc/runtime.h +++ b/src/nvidia/inc/libraries/nvoc/runtime.h @@ -44,6 +44,8 @@ const NVOC_CLASS_INFO *__nvoc_objGetClassInfo(Dynamic *pObj); void __nvoc_objDelete(Dynamic *pDynamic); +NV_STATUS __nvoc_handleObjCreateMemAlloc(NvU32 createFlags, NvU32 allocSize, void **ppLocalPtr, void **ppThis); + NV_STATUS __nvoc_objCreateDynamic( Dynamic **pNewObject, Dynamic *pParent, diff --git a/src/nvidia/inc/libraries/resserv/resserv.h b/src/nvidia/inc/libraries/resserv/resserv.h index 39b30f2c2..4091569fb 100644 --- a/src/nvidia/inc/libraries/resserv/resserv.h +++ b/src/nvidia/inc/libraries/resserv/resserv.h @@ -170,6 +170,7 @@ typedef void *PUID_TOKEN; #define RS_LOCK_FLAGS_NO_CUSTOM_LOCK_3 NVBIT(4) #define RS_LOCK_FLAGS_NO_DEPENDANT_SESSION_LOCK NVBIT(5) #define RS_LOCK_FLAGS_FREE_SESSION_LOCK NVBIT(6) +#define RS_LOCK_FLAGS_LOW_PRIORITY NVBIT(7) /// RS_LOCK_STATE #define RS_LOCK_STATE_TOP_LOCK_ACQUIRED NVBIT(0) @@ -276,6 +277,13 @@ struct CALL_CONTEXT RS_LOCK_INFO *pLockInfo; ///< Saved locking context information for the call API_SECURITY_INFO secInfo; RS_RES_CONTROL_PARAMS_INTERNAL *pControlParams; ///< parameters of the call [optional] + + void *pSerializedParams; ///< Serialized version of the params + void *pDeserializedParams; ///< Deserialized version of the params + NvU32 serializedSize; ///< Serialized size + NvU32 deserializedSize; ///< Deserialized size + NvBool bReserialize; ///< Reserialize before calling into GSP + NvBool bRestoreParams; ///< Need to restore pParams }; typedef enum { diff --git a/src/nvidia/inc/libraries/resserv/rs_client.h b/src/nvidia/inc/libraries/resserv/rs_client.h index 04a6ce76b..8a4e0f525 100644 --- a/src/nvidia/inc/libraries/resserv/rs_client.h +++ b/src/nvidia/inc/libraries/resserv/rs_client.h @@ -84,6 +84,16 @@ public: */ NvBool bResourceWarning; + /** + * True if client is disabled, awaiting free + */ + NvBool bDisabled; + + /** + * True if client's high priority resources were freed + */ + NvBool bHighPriorityFreeDone; + /** * Maps resource handle -> RsResourceRef */ @@ -140,6 +150,11 @@ public: */ RS_FREE_STACK *pFreeStack; + /** + * Node for a client's disabled client list + */ + ListNode disabledClientNode; + /** * Construct a client instance * @param[in] pClient This client @@ -412,6 +427,7 @@ public: */ NV_STATUS clientSetRestrictedRange(RsClient *pClient, NvHandle handleRangeStart, NvU32 handleRangeSize); }; +MAKE_INTRUSIVE_LIST(RsDisabledClientList, RsClient, disabledClientNode); /** * Get an iterator to the elements in the client's resource map @@ -454,6 +470,14 @@ RS_ORDERED_ITERATOR clientRefOrderedIter(RsClient *pClient, RsResourceRef *pScop */ NvBool clientRefOrderedIterNext(RsClient *pClient, RS_ORDERED_ITERATOR *pIt); +/** + * Release all CPU address mappings for a resource + * + * @param[in] pClient Client that owns the resource + * @param[in] pCallContext Caller information (which includes the resource reference whose mappings will be freed) + * @param[in] pLockInfo Information about which locks are already held, for recursive calls + */ +NV_STATUS clientUnmapResourceRefMappings(RsClient *pClient, CALL_CONTEXT *pCallContext, RS_LOCK_INFO *pLockInfo); /** * RsResource interface to a RsClient @@ -488,6 +512,7 @@ struct RS_CLIENT_FREE_PARAMS_INTERNAL NvHandle hDomain; ///< [in] The parent domain NvHandle hClient; ///< [in] The client handle NvBool bHiPriOnly; ///< [in] Only free high priority resources + NvBool bDisableOnly; ///< [in] Only disable the listed clients, do not free them yet NvU32 state; ///< [in] User-defined state RS_RES_FREE_PARAMS_INTERNAL *pResFreeParams; ///< [in] Necessary for locking state diff --git a/src/nvidia/inc/libraries/resserv/rs_resource.h b/src/nvidia/inc/libraries/resserv/rs_resource.h index eccebe706..6a36f674a 100644 --- a/src/nvidia/inc/libraries/resserv/rs_resource.h +++ b/src/nvidia/inc/libraries/resserv/rs_resource.h @@ -140,6 +140,7 @@ struct RS_RES_FREE_PARAMS_INTERNAL // Internal use only NvBool bHiPriOnly; ///< [in] Only free if this is a high priority resources + NvBool bDisableOnly; ///< [in] Disable the target instead of freeing it (only applies to clients) RS_LOCK_INFO *pLockInfo; ///< [inout] Locking flags and state NvU32 freeFlags; ///< [in] Flags for the free operation NvU32 freeState; ///< [inout] Free state @@ -296,6 +297,30 @@ public: virtual NV_STATUS resControlFilter(RsResource *pResource, CALL_CONTEXT *pCallContext, RS_RES_CONTROL_PARAMS_INTERNAL *pParams); + /** + * Serialize the control parameters if they are going to GSP/Host, not serialized, and support serialization + * Or + * Deserialize the control parameters if necessary and replace the inner params pointer with the deserialized params + * + * @param[in] pResource + * @param[in] pCallContext + * @param[in] pParams + */ + virtual NV_STATUS resControlSerialization_Prologue(RsResource *pResource, CALL_CONTEXT *pCallContext, + RS_RES_CONTROL_PARAMS_INTERNAL *pParams); + + /** + * Deserialize the parameters returned from GSP if client did not pass serialized params + * Or + * Serialize the control parameters if client expects it and restore the original inner params pointer + * + * @param[in] pResource + * @param[in] pCallContext + * @param[in] pParams + */ + virtual void resControlSerialization_Epilogue(RsResource *pResource, CALL_CONTEXT *pCallContext, + RS_RES_CONTROL_PARAMS_INTERNAL *pParams); + /** * Operations performed right before the control call is executed. Default stubbed. * diff --git a/src/nvidia/inc/libraries/resserv/rs_server.h b/src/nvidia/inc/libraries/resserv/rs_server.h index 3ef6515a0..17fa4153a 100644 --- a/src/nvidia/inc/libraries/resserv/rs_server.h +++ b/src/nvidia/inc/libraries/resserv/rs_server.h @@ -28,6 +28,7 @@ #include "nvport/nvport.h" #include "resserv/resserv.h" +#include "resserv/rs_client.h" #include "nvoc/runtime.h" #ifdef __cplusplus @@ -181,6 +182,11 @@ struct RsServer NvU32 activeClientCount; NvU64 activeResourceCount; + + /// List of clients that are de-activated and pending free + RsDisabledClientList disabledClientList; + RsClient *pNextDisabledClient; + PORT_SPINLOCK *pDisabledClientListLock; }; /** @@ -262,20 +268,35 @@ NV_STATUS serverAllocClient(RsServer *pServer, RS_RES_ALLOC_PARAMS_INTERNAL *pPa NV_STATUS serverFreeClient(RsServer *pServer, RS_CLIENT_FREE_PARAMS* pParams); /** - * Free a list of client handles. All resources references owned by the client will be - * freed. All priority resources will be freed first across all listed clients. + * Mark a list of client handles as disabled. All CPU mappings owned by that + * client will be unmapped immediate, and the client will be marked as disabled. + * A call to @ref serverFreeDisabledClients will then free all such clients. * * It is invalid to attempt to free a client from a user other than the one * that allocated it. * * @param[in] pServer This server instance - * @param[in] phClientList The list of client handles to free + * @param[in] phClientList The list of client handles to disable * @param[in] numClients The number of clients in the list * @param[in] freeState User-defined free state * @param[in] pSecInfo Security Info * */ -NV_STATUS serverFreeClientList(RsServer *pServer, NvHandle *phClientList, NvU32 numClients, NvU32 freeState, API_SECURITY_INFO *pSecInfo); +NV_STATUS serverMarkClientListDisabled(RsServer *pServer, NvHandle *phClientList, NvU32 numClients, NvU32 freeState, API_SECURITY_INFO *pSecInfo); + +/** + * Frees all currently disabled clients. All resources references owned by + * any of the clients will be freed. + * All priority resources will be freed first across all listed clients. + * + * NOTE: may return NV_WARN_MORE_PROCESSING_REQUIRED if not all clients were freed + * + * @param[in] pServer This server instance + * @param[in] freeState User-defined free state + * @param[in] limit Max number of iterations to make returning; 0 means no limit + * + */ +NV_STATUS serverFreeDisabledClients(RsServer *pServer, NvU32 freeState, NvU32 limit); /** * Allocate a resource. @@ -351,8 +372,67 @@ NvBool serverShareIterNext(RS_SHARE_ITERATOR*); * @param[in] pServer * @param[in] clientHandleBase */ - NV_STATUS serverSetClientHandleBase(RsServer *pServer, NvU32 clientHandleBase); +NV_STATUS serverSetClientHandleBase(RsServer *pServer, NvU32 clientHandleBase); +/** + * Deserialize parameters for servicing command + * + * @param[in] pCallContext + * @param[in] cmd + * @param[in] pParams + * @param[in] paramsSize + * @param[in] flags + */ +NV_STATUS serverDeserializeCtrlDown(CALL_CONTEXT *pCallContext, NvU32 cmd, void *pParams, NvU32 paramsSize, NvU32 *flags); + +/** + * Serialize parameters for servicing command + * + * @param[in] pCallContext + * @param[in] cmd + * @param[in] pParams + * @param[in] paramsSize + * @param[in] flags + */ +NV_STATUS serverSerializeCtrlDown(CALL_CONTEXT *pCallContext, NvU32 cmd, void *pParams, NvU32 paramsSize, NvU32 *flags); + +/** + * Deserialize parameters for returning from command + * + * @param[in] pCallContext + * @param[in] cmd + * @param[in] pParams + * @param[in] paramsSize + * @param[in] flags + */ +NV_STATUS serverDeserializeCtrlUp(CALL_CONTEXT *pCallContext, NvU32 cmd, void *pParams, NvU32 paramsSize, NvU32 *flags); + +/** + * Serialize parameters for returning from command + * + * @param[in] pCallContext + * @param[in] cmd + * @param[in] pParams + * @param[in] paramsSize + * @param[in] flags + */ +NV_STATUS serverSerializeCtrlUp(CALL_CONTEXT *pCallContext, NvU32 cmd, void *pParams, NvU32 paramsSize, NvU32 *flags); + +/** + * Unset flag for reserializing control before going to GSP + * Used if kernel control servicing passes params to GSP without changing them + * + * @param[in] pCallContext + */ +void serverDisableReserializeControl(CALL_CONTEXT *pCallContext); + +/** + * Free finn structures allocated for serializing/deserializing + * + * @param[in] pCallContext + * @param[in] pParams + */ +void serverFreeSerializeStructures(CALL_CONTEXT *pCallContext, void *pParams); /** * Return an available client handle for new client allocation diff --git a/src/nvidia/inc/libraries/tls/tls.h b/src/nvidia/inc/libraries/tls/tls.h index eb45c2dc9..f86055213 100644 --- a/src/nvidia/inc/libraries/tls/tls.h +++ b/src/nvidia/inc/libraries/tls/tls.h @@ -262,7 +262,7 @@ NvU32 tlsEntryUnreference(NvU64 entryId); #define TLS_ISR_ALLOCATOR_SIZE 512 #else #if defined(LOCK_VAL_ENABLED) - #define TLS_ISR_ALLOCATOR_SIZE 400 + #define TLS_ISR_ALLOCATOR_SIZE 512 #else #define TLS_ISR_ALLOCATOR_SIZE 256 #endif diff --git a/src/nvidia/interface/deprecated/rmapi_deprecated_vidheapctrl.c b/src/nvidia/interface/deprecated/rmapi_deprecated_vidheapctrl.c index 943d1d411..a191d3886 100644 --- a/src/nvidia/interface/deprecated/rmapi_deprecated_vidheapctrl.c +++ b/src/nvidia/interface/deprecated/rmapi_deprecated_vidheapctrl.c @@ -41,7 +41,6 @@ typedef struct { } RmVidHeapControlEntry; // forward declarations -static NV_STATUS _nvos32FunctionAllocDepthWidthHeight(DEPRECATED_CONTEXT *, NVOS32_PARAMETERS *); static NV_STATUS _nvos32FunctionAllocSize(DEPRECATED_CONTEXT *, NVOS32_PARAMETERS *); static NV_STATUS _nvos32FunctionAllocSizeRange(DEPRECATED_CONTEXT *, NVOS32_PARAMETERS *); static NV_STATUS _nvos32FunctionAllocTiledPitchHeight(DEPRECATED_CONTEXT *, NVOS32_PARAMETERS *); @@ -56,7 +55,6 @@ static NV_STATUS _nvos32FunctionAllocOsDesc(DEPRECATED_CONTEXT *, NVOS32_PARAMET static const RmVidHeapControlEntry rmVidHeapControlTable[] = { - { NVOS32_FUNCTION_ALLOC_DEPTH_WIDTH_HEIGHT, _nvos32FunctionAllocDepthWidthHeight }, { NVOS32_FUNCTION_ALLOC_SIZE, _nvos32FunctionAllocSize }, { NVOS32_FUNCTION_ALLOC_SIZE_RANGE, _nvos32FunctionAllocSizeRange }, { NVOS32_FUNCTION_ALLOC_TILED_PITCH_HEIGHT, _nvos32FunctionAllocTiledPitchHeight }, @@ -152,68 +150,6 @@ _rmVidHeapControlAllocCommon return status; } -static NV_STATUS -_nvos32FunctionAllocDepthWidthHeight -( - DEPRECATED_CONTEXT *pContext, - NVOS32_PARAMETERS *pArgs -) -{ - NV_MEMORY_ALLOCATION_PARAMS allocParams = {0}; - NvU32 byteWidth; - NV_STATUS status = NV_OK; - - // For NV3, scanline alignment is 32 bytes. - byteWidth = ((pArgs->data.AllocDepthWidthHeight.width * pArgs->data.AllocDepthWidthHeight.depth) + 7) >> 3; - pArgs->data.AllocDepthWidthHeight.size = pArgs->data.AllocDepthWidthHeight.height * ((byteWidth + 31) & ~31); - - // Range begin/end are captured only if the appropriate flag bit is set. - if (pArgs->data.AllocDepthWidthHeight.flags & NVOS32_ALLOC_FLAGS_USE_BEGIN_END) - { - allocParams.rangeLo = pArgs->data.AllocDepthWidthHeight.rangeBegin; - allocParams.rangeHi = pArgs->data.AllocDepthWidthHeight.rangeEnd; - } - else - { - allocParams.rangeLo = 0; - allocParams.rangeHi = 0; - } - - #define ALLOC_DEPTH_WIDTH_HEIGHT_PARAMS(_IN, _IN_OUT) \ - _IN(owner, AllocDepthWidthHeight.owner) \ - _IN(type, AllocDepthWidthHeight.type) \ - _IN(flags, AllocDepthWidthHeight.flags) \ - _IN(height, AllocDepthWidthHeight.height) \ - _IN(width, AllocDepthWidthHeight.width) \ - _IN_OUT(size, AllocDepthWidthHeight.size) \ - _IN(alignment, AllocDepthWidthHeight.alignment) \ - _IN_OUT(offset, AllocDepthWidthHeight.offset) \ - _IN_OUT(attr, AllocDepthWidthHeight.attr) \ - _IN_OUT(attr2, AllocDepthWidthHeight.attr2) \ - _IN_OUT(format, AllocDepthWidthHeight.format) \ - _IN_OUT(limit, AllocDepthWidthHeight.limit) \ - _IN_OUT(address, AllocDepthWidthHeight.address) \ - _IN_OUT(comprCovg, AllocDepthWidthHeight.comprCovg) \ - _IN_OUT(zcullCovg, AllocDepthWidthHeight.zcullCovg) \ - _IN_OUT(ctagOffset, AllocDepthWidthHeight.ctagOffset) - - ALLOC_DEPTH_WIDTH_HEIGHT_PARAMS(_COPY_IN, _COPY_IN); - - pArgs->data.AllocDepthWidthHeight.partitionStride = 256; - - // get memory - status = _rmVidHeapControlAllocCommon(pContext, - pArgs, - pArgs->hRoot, - pArgs->hObjectParent, - &pArgs->data.AllocDepthWidthHeight.hMemory, - &allocParams); - - ALLOC_DEPTH_WIDTH_HEIGHT_PARAMS(_NO_COPY, _COPY_OUT); - - return status; -} - static NV_STATUS _nvos32FunctionAllocSize ( diff --git a/src/nvidia/interface/deprecated/rmapi_gss_legacy_control.c b/src/nvidia/interface/deprecated/rmapi_gss_legacy_control.c index ba913d169..d44fd9c6f 100644 --- a/src/nvidia/interface/deprecated/rmapi_gss_legacy_control.c +++ b/src/nvidia/interface/deprecated/rmapi_gss_legacy_control.c @@ -22,10 +22,11 @@ */ #include "deprecated/rmapi_deprecated.h" -#include "finn_rm_api.h" #include "gpu/gpu.h" #include "core/locks.h" +#include "g_finn_rm_api.h" + /*! * Some clients are still making these legacy GSS controls. We no longer support these in RM, * but until all the numerous tools are updated to use alternative APIs, just forward all of them diff --git a/src/nvidia/interface/nv_sriov_defines.h b/src/nvidia/interface/nv_sriov_defines.h index 32bd4fcc6..07746f350 100644 --- a/src/nvidia/interface/nv_sriov_defines.h +++ b/src/nvidia/interface/nv_sriov_defines.h @@ -47,6 +47,15 @@ #define NV_DOORBELL_NOTIFY_LEAF_VF_MASK (NVBIT(NV_DOORBELL_NOTIFY_LEAF_VF_RPC_SETUP_HANDLE) | \ NVBIT(NV_DOORBELL_NOTIFY_LEAF_VF_RPC_MESSAGE_HANDLE)) +// Top half serviced interrupts (serviced by both guest and host) + +#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_REPLAYABLE_FAULT_FLUSH_REQUEST 2:2 +#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_REPLAYABLE_FAULT_FLUSH_REQUEST_EN (0x1) +#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_REPLAYABLE_FAULT_FLUSH_REQUEST_DIS (0x0) +#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_REPLAYABLE_FAULT_FLUSH_HANDLE (0 ? NV_DOORBELL_NOTIFY_LEAF_SERVICE_REPLAYABLE_FAULT_FLUSH_REQUEST) + +#define NV_DOORBELL_NOTIFY_LEAF_TOP_HALF_MASK NVBIT(NV_DOORBELL_NOTIFY_LEAF_SERVICE_REPLAYABLE_FAULT_FLUSH_HANDLE) + // Host PF interrupts #define NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_REQUEST 16:16 diff --git a/src/nvidia/interface/nv_uvm_types.h b/src/nvidia/interface/nv_uvm_types.h index 1a3d363aa..96b68979c 100644 --- a/src/nvidia/interface/nv_uvm_types.h +++ b/src/nvidia/interface/nv_uvm_types.h @@ -110,7 +110,7 @@ typedef struct UvmGpuMemoryInfo_tag NvBool deviceDescendant; // Out: Page size associated with the phys alloc. - NvU32 pageSize; + NvU64 pageSize; // Out: Set to TRUE, if the allocation is contiguous. NvBool contig; @@ -306,6 +306,7 @@ typedef struct UvmGpuChannelAllocParams_tag // interpreted as UVM_GPU_CHANNEL_ENGINE_TYPE NvU32 engineType; + } UvmGpuChannelAllocParams; typedef struct UvmGpuPagingChannelAllocParams_tag @@ -371,7 +372,6 @@ typedef enum UVM_LINK_TYPE_NVLINK_2, UVM_LINK_TYPE_NVLINK_3, UVM_LINK_TYPE_NVLINK_4, - UVM_LINK_TYPE_C2C, } UVM_LINK_TYPE; typedef struct UvmGpuCaps_tag @@ -409,7 +409,7 @@ typedef struct UvmGpuCaps_tag typedef struct UvmGpuAddressSpaceInfo_tag { - NvU32 bigPageSize; + NvU64 bigPageSize; NvBool atsEnabled; @@ -430,7 +430,7 @@ typedef struct UvmGpuAddressSpaceInfo_tag typedef struct UvmGpuAllocInfo_tag { NvU64 gpuPhysOffset; // Returns gpuPhysOffset if contiguous requested - NvU32 pageSize; // default is RM big page size - 64K or 128 K" else use 4K or 2M + NvU64 pageSize; // default is RM big page size - 64K or 128 K" else use 4K or 2M NvU64 alignment; // Virtual alignment NvBool bContiguousPhysAlloc; // Flag to request contiguous physical allocation NvBool bMemGrowsDown; // Causes RM to reserve physical heap from top of FB @@ -516,6 +516,13 @@ typedef struct UvmGpuExternalMappingInfo_tag // In: Size of the buffer to store PTEs (in bytes). NvU64 pteBufferSize; + // In: Page size for mapping + // If this field is passed as 0, the page size + // of the allocation is used for mapping. + // nvUvmInterfaceGetExternalAllocPtes must pass + // this field as zero. + NvU64 mappingPageSize; + // In: Pointer to a buffer to store PTEs. // Out: The interface will fill the buffer with PTEs NvU64 *pteBuffer; @@ -797,6 +804,7 @@ typedef struct UvmGpuFaultInfo_tag // Preallocated stack for functions called from the UVM isr bottom half void *isr_bh_sp; + } nonReplayable; NvHandle faultBufferHandle; } UvmGpuFaultInfo; diff --git a/src/nvidia/interface/nvrm_registry.h b/src/nvidia/interface/nvrm_registry.h index 232e2824c..367e18e30 100644 --- a/src/nvidia/interface/nvrm_registry.h +++ b/src/nvidia/interface/nvrm_registry.h @@ -442,12 +442,6 @@ #define NV_REG_STR_RM_INST_LOC_4_FECS_EVENT_BUF_NCOH NV_REG_STR_RM_INST_LOC_NCOH #define NV_REG_STR_RM_INST_LOC_4_FECS_EVENT_BUF_VID NV_REG_STR_RM_INST_LOC_VID -#define NV_REG_STR_RM_DISABLE_GSP_OFFLOAD "RmDisableGspOffload" -#define NV_REG_STR_RM_DISABLE_GSP_OFFLOAD_FALSE (0x00000000) -#define NV_REG_STR_RM_DISABLE_GSP_OFFLOAD_TRUE (0x00000001) -// Type DWORD (Boolean) -// Override any other settings and disable GSP-RM offload. - #define NV_REG_STR_RM_GSP_STATUS_QUEUE_SIZE "RmGspStatusQueueSize" // TYPE DWORD // Set the GSP status queue size in KB (for GSP to CPU RPC status and event communication) @@ -477,6 +471,17 @@ // 1 - Enable RM event tracing +#define NV_REG_STR_RM_ALLOC_CTX_BUFFERS_FROM_PMA "AllocCtxBuffersFromPMA" +#define NV_REG_STR_RM_ALLOC_CTX_BUFFERS_FROM_PMA_DISABLE 0 +#define NV_REG_STR_RM_ALLOC_CTX_BUFFERS_FROM_PMA_DEFAULT 0 +#define NV_REG_STR_RM_ALLOC_CTX_BUFFERS_FROM_PMA_ENABLE 1 +// Type DWORD +// Encoding boolean +// Enable/Disable context buffers from being allocated in PMA +// 0 - Disable PMA allocation for context buffers and allocate from reserved memory +// 1 - Enable PMA allocation for context buffers and do not allocate from reserved memory + + #define NV_REG_STR_RM_COMPUTE_MODE_RULES "RmComputeModeRules" // Type DWORD // Saves the last compute mode rule set by the client. @@ -726,6 +731,17 @@ // #define NV_REG_STR_RM_PARAM_COPY_NO_LOCK "RMParamCopyNoLock" +// +// Type DWORD +// Used to control RM API lock aging for low priority acquires. +// If 0, low priority acquires (e.g. from cleanup when a process dies) +// are disabled and treated like regular ones. +// Otherwise, they will yield the lock this many times to the higher priority +// threads before proceeding. +// Off by default; 3 would be a good starting value if the feature is desired. +// +#define NV_REG_STR_RM_LOCKING_LOW_PRIORITY_AGING "RMLockingLowPriorityAging" + // // Type DWORD // This regkey restricts profiling capabilities (creation of profiling objects @@ -986,7 +1002,7 @@ // RM aperture size. This can result in undefined beahvior in environments that // rely on a virtual bar2 aperture shared between RM and VBIOS for VESA support. -#if defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS) +#if defined(DEVELOP) || defined(DEBUG) || (defined(RMCFG_FEATURE_MODS_FEATURES) && RMCFG_FEATURE_MODS_FEATURES) // // TYPE DWORD // This setting will override the BAR1 Big page size @@ -995,7 +1011,7 @@ #define NV_REG_STR_RM_SET_BAR1_ADDRESS_SPACE_BIG_PAGE_SIZE "RMSetBAR1AddressSpaceBigPageSize" #define NV_REG_STR_RM_SET_BAR1_ADDRESS_SPACE_BIG_PAGE_SIZE_64k (64 * 1024) #define NV_REG_STR_RM_SET_BAR1_ADDRESS_SPACE_BIG_PAGE_SIZE_128k (128 * 1024) -#endif //DEVELOP || DEBUG || NV_MODS +#endif //DEVELOP || DEBUG || MODS_FEATURES // This regkey is to disable coherent path CPU->Nvlink/C2C->FB and force BAR path. #define NV_REG_STR_RM_FORCE_BAR_PATH "RMForceBarPath" @@ -1716,15 +1732,46 @@ // period for which swap lock window will remain HIGH for QSYNC III. // -#define NV_REG_STR_RM_MULTICAST_FLA "RMEnableMulticastFla" -#define NV_REG_STR_RM_MULTICAST_FLA_DISABLED 0x00000000 -#define NV_REG_STR_RM_MULTICAST_FLA_ENABLED 0x00000001 +#define NV_REG_STR_RM_NVLINK_BW "RmNvlinkBandwidth" +// Type String +// The option is in the string format. // -// Type: Dword -// Encoding: -// 1 - Multicast FLA Enabled on supported GPU -// 0 - Multicast FLA Disabled on specific GPU +// Possible string values: +// OFF: 0% bandwidth +// MIN: 15%-25% bandwidth depending on the system's NVLink topology +// HALF: 50% bandwidth +// 3QUARTER: 75% bandwidth +// FULL: 100% bandwidth (default) // +// This option is only for Hopper+ GPU with NVLINK version 4.0. + +#define NV_REG_STR_RM_CLIENT_HANDLE_LOOKUP "RmClientHandleLookup" +// Type DWORD (Boolean) +// 1 - Store active RM clients in a multimap to speed up lookups (currently only in thirdpartyp2p) +// 0 - (Default) Linear list search for clients + + +// +// Type: DWORD (Boolean) +// +// 1 - Only invalidate and free CPU mappings immediatelly, then collect GPU resources +// from individual clients under separate lock acquire/release sequences. +// 0 - (Default) Immediately free all clients resources when freeing a client list +#define NV_REG_STR_RM_CLIENT_LIST_DEFERRED_FREE "RMClientListDeferredFree" + +// +// Type: DWORD +// +// Number of clients to free in a single chunk before yielding and scheduling +// a work item to handle the rest. +// +// Only valid if NV_REG_STR_RM_CLIENT_LIST_DEFERRED_FREE is set. +// +// Value of 0 (default) means there is no limit and all clients will be freed +// at once before the process terminates. +// +#define NV_REG_STR_RM_CLIENT_LIST_DEFERRED_FREE_LIMIT "RMClientListDeferredFreeLimit" + // // TYPE Dword // Determines whether or not to emulate VF MMU TLB Invalidation register range @@ -1736,9 +1783,42 @@ #define NV_REG_STR_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE_DISABLE 0x00000000 #define NV_REG_STR_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE_DEFAULT NV_REG_STR_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE_ENABLE -#define NV_REG_STR_RM_CLIENT_HANDLE_LOOKUP "RmClientHandleLookup" +#define NV_REG_STR_RM_POWER_FEATURES "RMPowerFeature" + +// Type DWORD +// This Regkey controls inforom black box data recording. This can be used to +// restrict access to BBX. +// 0 - Enable BBX. (Default) +// COMPLETELY - Enable/Disable BBX access (read/write). +// WRITE_BY_RM - Enable/Disable writes by RM itself. +// WRITE_BY_CLIENT - Enable/Disable writes by clients to RM. +// PERIODIC FLUSH - Enable/Disable periodic flush to inforom (Also enables/disables Power data collection) +// +#define NV_REG_STR_RM_INFOROM_DISABLE_BBX "RmDisableInforomBBX" +#define NV_REG_STR_RM_INFOROM_DISABLE_BBX_NO (0x00000000) +#define NV_REG_STR_RM_INFOROM_DISABLE_BBX_YES (0x00000001) +#define NV_REG_STR_RM_INFOROM_DISABLE_BBX_COMPLETELY 0:0 +#define NV_REG_STR_RM_INFOROM_DISABLE_BBX_COMPLETELY_NO (0x00000000) +#define NV_REG_STR_RM_INFOROM_DISABLE_BBX_COMPLETELY_YES (0x00000001) +#define NV_REG_STR_RM_INFOROM_DISABLE_BBX_WRITE_BY_RM 1:1 +#define NV_REG_STR_RM_INFOROM_DISABLE_BBX_WRITE_BY_RM_NO (0x00000000) +#define NV_REG_STR_RM_INFOROM_DISABLE_BBX_WRITE_BY_RM_YES (0x00000001) +#define NV_REG_STR_RM_INFOROM_DISABLE_BBX_WRITE_BY_CLIENT 2:2 +#define NV_REG_STR_RM_INFOROM_DISABLE_BBX_WRITE_BY_CLIENT_NO (0x00000000) +#define NV_REG_STR_RM_INFOROM_DISABLE_BBX_WRITE_BY_CLIENT_YES (0x00000001) +#define NV_REG_STR_RM_INFOROM_DISABLE_BBX_PERIODIC_FLUSH 3:3 +#define NV_REG_STR_RM_INFOROM_DISABLE_BBX_PERIODIC_FLUSH_YES (0x00000000) +#define NV_REG_STR_RM_INFOROM_DISABLE_BBX_PERIODIC_FLUSH_NO (0x00000001) + +// // Type DWORD (Boolean) -// 1 - Store active RM clients in a multimap to speed up lookups (currently only in thirdpartyp2p) -// 0 - (Default) Linear list search for clients +// RmNvlinkEnablePrivErrorRc +// +// 0 - (default) does not do RC recovery when PRIV_ERROR +// 1 - enable FLA PRIV_ERROR RC recovery +// +#define NV_REG_STR_RM_NVLINK_ENABLE_PRIV_ERROR_RC "RmNvlinkEnablePrivErrorRc" +#define NV_REG_STR_RM_NVLINK_ENABLE_PRIV_ERROR_RC_NO 0 +#define NV_REG_STR_RM_NVLINK_ENABLE_PRIV_ERROR_RC_YES 1 #endif // NVRM_REGISTRY_H diff --git a/src/nvidia/interface/rmapi/src/finn_rm_api.c b/src/nvidia/interface/rmapi/src/finn_rm_api.c deleted file mode 100644 index 762519a91..000000000 --- a/src/nvidia/interface/rmapi/src/finn_rm_api.c +++ /dev/null @@ -1,7496 +0,0 @@ -#include "finn_rm_api.h" -#include "ctrl/ctrl0000/ctrl0000nvd.h" -#include "ctrl/ctrl0080/ctrl0080dma.h" -#include "ctrl/ctrl0080/ctrl0080fb.h" -#include "ctrl/ctrl0080/ctrl0080fifo.h" -#include "ctrl/ctrl0080/ctrl0080gpu.h" -#include "ctrl/ctrl0080/ctrl0080gr.h" -#include "ctrl/ctrl0080/ctrl0080host.h" -#include "ctrl/ctrl0080/ctrl0080msenc.h" -#include "ctrl/ctrl2080/ctrl2080ce.h" -#include "ctrl/ctrl2080/ctrl2080gpu.h" -#include "ctrl/ctrl2080/ctrl2080i2c.h" -#include "ctrl/ctrl2080/ctrl2080nvd.h" -#include "ctrl/ctrl2080/ctrl2080perf.h" -#include "ctrl/ctrl2080/ctrl2080rc.h" -#include "ctrl/ctrl2080/ctrl2080ucodefuzzer.h" -#include "ctrl/ctrl208f/ctrl208fgpu.h" -#include "ctrl/ctrl402c.h" -#include "ctrl/ctrl83de/ctrl83dedebug.h" -#include "ctrl/ctrlb06f.h" - -#if defined(NVRM) /* Kernel Mode */ -#include -#include -#include "nvport/nvport.h" -#elif defined(NV_LIBOS) /* LIBOS */ -#include -#include "nvport/nvport.h" -#else /* User Mode */ -#include -#include -#include -#include -#endif - - -// -// This file was generated with FINN, an NVIDIA coding tool. -// - -/* - * Serialization helper macros. These make field copying code more readable. - * Size is provided explicitly for cross-platform compatibility. - */ - -// Allocate memory. -#if defined(FINN_MALLOC) /* Use override from Makefile */ -#elif defined(NVRM) /* Kernel Mode */ -#define FINN_MALLOC(size) portMemAllocNonPaged(size) - -#elif defined(NV_LIBOS) /* LIBOS */ -#define FINN_MALLOC(size) portMemAllocNonPaged(size) - -#else /* User Mode */ -#define FINN_MALLOC(size) malloc(size) -#endif - -// Free allocated memory. -#if defined(FINN_FREE) /* Use override from Makefile */ -#elif defined(NVRM) /* Kernel Mode */ -#define FINN_FREE(buf) portMemFree(buf) - -#elif defined(NV_LIBOS) /* LIBOS */ -#define FINN_FREE(buf) portMemFree(buf) - -#else /* User Mode */ -#define FINN_FREE(buf) free(buf) -#endif - -// Set memory region to all zeroes. -#if defined(FINN_MEMZERO) /* Use override from Makefile */ -#elif defined(NVRM) /* Kernel Mode */ -#define FINN_MEMZERO(buf, size) portMemSet(buf, 0, size) - -#elif defined(NV_LIBOS) /* LIBOS */ -#define FINN_MEMZERO(buf, size) portMemSet(buf, 0, size) - -#else /* User Mode */ -#define FINN_MEMZERO(buf, size) memset(buf, 0, size) -#endif - -// Copy nonoverlapping memory region. -#if defined(FINN_MEMCPY) /* Use override from Makefile */ -#elif defined(NVRM) /* Kernel Mode */ -#define FINN_MEMCPY(dst, src, size) portMemCopy(dst, size, src, size) - -#elif defined(NV_LIBOS) /* LIBOS */ -#define FINN_MEMCPY(dst, src, size) portMemCopy(dst, size, src, size) - -#else /* User Mode */ -#define FINN_MEMCPY(dst, src, size) memcpy(dst, src, size) -#endif - -// Report an error. -#if defined(FINN_ERROR) /* Use override from Makefile */ -#elif defined(NVRM) /* Kernel Mode */ -#define FINN_ERROR(err) /* No-op */ - -#elif defined(NV_LIBOS) /* LIBOS */ -#define FINN_ERROR(err) /* No-op */ - -#else /* User Mode */ -#define FINN_ERROR(err) /* No-op */ -#endif - - - -// -// The purpose of the bit pump is to ensure 64-bit aligned access to the -// buffer while enabling arbitrary bits to be read/written. -// -typedef struct finn_bit_pump_for_read finn_bit_pump_for_read; - -struct finn_bit_pump_for_read -{ - uint64_t accumulator; // Bits not yet read from the data buffer - uint64_t checksum; // Checksum of data - const uint64_t *buffer_position; // Next word within data buffer to be read - const uint64_t *end_of_data; // End of data within buffer - uint8_t remaining_bit_count; // Number of bits remaining in the accumulator -}; - - -// -// Initialize bit pump for reading from the buffer. -// -// WARNING: The buffer start is assumed to be 64-bit aligned for optimal performance. -// `sod` (start of data) and `eod` (end of data) must be multiples of 64 bits -// since this logic is optimized for a 64-bit word size. Caller must check both -// `sod` and `eod`. -// -// `eod` points to the 64-bit word after the data (like most C++ `std` iterators). -// -static inline void finn_open_buffer_for_read(finn_bit_pump_for_read *bp, const uint64_t *sod, const uint64_t *eod) -{ - bp->accumulator = 0U; - bp->checksum = 0U; - bp->buffer_position = sod; - bp->end_of_data = eod; - bp->remaining_bit_count = 0U; -} - - -// -// Read the next several bits. -// -// `bit_size` must be in range of 0 to 64 inclusive; no check is made. -// When `bit_size` is zero, an unsupported use-case, it works as expected by -// returning zero without advancing the pointer. -// -static uint64_t finn_read_buffer(finn_bit_pump_for_read *bp, uint8_t bit_size) -{ - // Value to be deserialized and returned - uint64_t value; - - // Boundary crossing - // Accumulator does not have enough to satisfy the request, - if (bit_size > bp->remaining_bit_count) - { - // Number of bits not yet satisfied - bit_size -= bp->remaining_bit_count; - - // Shift the bits we have into place. - value = bp->accumulator; - - // Return zeroes for unsatisfied bits (if any) at end of data. - if (bp->buffer_position >= bp->end_of_data) - bp->accumulator = 0U; - - // Read the next word from the buffer. - else - bp->accumulator = *(bp->buffer_position++); - - // Update the checksum. - bp->checksum = ((bp->checksum << 1) ^ (bp->checksum & 1U)) ^ bp->accumulator; - - // - // This is the special case where we are reading an entire 64-bit word - // without crossing a boundary (when the accumulator is empty). The - // accumulator remains empty on exit. - // - // The bitwise operations in the normal flow do not work in this case. - // Shifts are not well-defined in C when the right operand exceeds the - // size of the left operand. Also, the right operand of the bitwise-and - // would exceed the 64-bit capacity. However, the needed logic is simple. - // - // 64 is the largest legal value for `bit_size`, so `>=` is equivalent to `==`. - // - if (bit_size >= 64) - { - // The value is the entire word. - value = bp->accumulator; - - // Discard the consumed data from the accumulator. - bp->accumulator = 0U; - - // Under the assumption that `bit_size` is never larger than 64, - // `bit_size == 64` implies `bp->remaining_bit_count == 0` because - // of the above `bit_size -= bp->remaining_bit_count`. As such, there - // is no need to do `bp->remaining_bit_count = 64U - bit_size`. - - // Done - return value; - } - - // OR in the bits since this was a boundary crossing. - // Shift it over by the number of bits we get from the prior word. - value |= (bp->accumulator - & (((uint64_t) 1U << bit_size) - 1U)) - << bp->remaining_bit_count; - - // Logic below subtracts off the bits consumed in the accumulator. - bp->remaining_bit_count = 64U; - } - - else - { - // The accumulator has enough to satisfy the request. - value = bp->accumulator & (((uint64_t) 1U << bit_size) - 1U); - } - - // Discard the consumed bits from the accumulator. - bp->accumulator >>= bit_size; - - // Keep track of the remaining available bits in the accumulator. - bp->remaining_bit_count -= bit_size; - - // Done - return value; -} - - -// Close the read buffer. -// Postcondition: `bp->checksum` is updated to end-of-data. -static inline void finn_close_buffer_for_read(finn_bit_pump_for_read *bp) -{ - // No need to update the bit pump buffer position, - // so use a local for optimal performance. - const uint64_t *p = bp->buffer_position; - - // Apply any unread words to the checksum. - while (p < bp->end_of_data) - bp->checksum = ((bp->checksum << 1U) ^ (bp->checksum & 1U)) ^ (*(p++)); -} - - -typedef struct finn_bit_pump_for_write finn_bit_pump_for_write; - -struct finn_bit_pump_for_write -{ - uint64_t accumulator; // Bits not yet written to the data buffer - uint64_t checksum; // Checksum of data - uint64_t *buffer_position; // Next word within the data buffer to be written - const uint64_t *end_of_buffer; // End of buffer (which may be after end of data) - uint8_t empty_bit_count; // Number of available bits in the accumulator -}; - - -// -// Initialize bit pump for writing to the buffer. -// -// In the general case for writing to the bit pump: -// -// WARNING: The buffer start is assumed to be 64-bit aligned for optimal performance. -// `sod` (start of data) and `eob` (end of buffer) must be multiples of 64 bits -// since this logic is optimized for a 64-bit word size. Caller must check both -// `sod` and `eod`. -// -// `eob` points to the 64-bit word after the buffer, an illegal access. -// -// -// Special case to get the serialized size without writing to the buffer: -// Both `sod` and `eob` are null. -// When closed, `bp->buffer_position` contains the byte count. -// -static inline void finn_open_buffer_for_write(finn_bit_pump_for_write *bp, uint64_t *sod, const uint64_t *eob) -{ - bp->accumulator = 0U; - bp->buffer_position = sod; - bp->end_of_buffer = eob; - bp->checksum = 0U; - bp->empty_bit_count = 64U; -} - -// -// Write several bits to the buffer. -// -// `bit_size` must be in range of 1 to 64 inclusive; no check is made. -// `value` must not have more 1 bits than specified by `bit_size`. -// In other words, bits that are left of `bit_size` must be 0s; no check is made. -// -// Return value is nonzero if the end of buffer is reached, an error. -// -// `bp->end_of_buffer` is null to disable writing to the buffer. -// -static int finn_write_buffer(finn_bit_pump_for_write *bp, uint64_t value, uint8_t bit_size) -{ - // Boundary crossing: Accumulator does not have enough to satisfy the request, - if (bit_size >= bp->empty_bit_count) - { - // Number of bits not yet satisfied - bit_size -= bp->empty_bit_count; - - // OR as many bits as will fit into the accumulator. - bp->accumulator |= value << (64U - bp->empty_bit_count); - - // Discard these bits by setting them to 0s. - // CAUTION: `value` may be unchanged when `bp->empty_bit_count` is 64 - // depending on the processor/ISA. - value >>= bp->empty_bit_count; - - // Write the word to the buffer unless writes are disabled. - if (bp->end_of_buffer) - { - *bp->buffer_position = bp->accumulator; - } - - // Advance to the next word in the buffer. - bp->buffer_position++; - - // Update the checksum. - bp->checksum = ((bp->checksum << 1) ^ (bp->checksum & 1U)) ^ bp->accumulator; - - // Re-initialize the accumulator and the bits filled. - bp->accumulator = 0U; - bp->empty_bit_count = 64U; - } - - // OR the data into the accumulator. - // When `bit_size` and `bp->empty_bit_count` are both 64 above, `bit_size` - // is assigned zero, but `value` may be unchanged. Check `bit_size` here so - // that stale `value` is not ORed into the accumulator again. - if (bit_size) - { - bp->accumulator |= (value << (64U - bp->empty_bit_count)); - } - - // Advance the bit count - bp->empty_bit_count -= bit_size; - - // Return nonzero on buffer overrun. - return bp->end_of_buffer && bp->buffer_position >= bp->end_of_buffer && bit_size; -} - - -// -// Close the write buffer and compute the checksum. -// -// Do NOT call this function if `finn_write_buffer` returned nonzero; no check is made. -// -// In the general case for writing to the bit pump: -// -// Postcondition: `bp->buffer_position` points to the word after the end of the data, -// which can be used to calculate the data size in 64-bit words by subtracting from -// `bp->end_of_buffer`. Buffer data at and after this point is set to zeroes. -// -// Special case to get the serialized size without writing to the buffer: -// Postcondition: ``bp->buffer_position` contains the byte count. -// -// All cases: -// Postcondition: `bp->checksum` contains the checksum of words written to the buffer. -// -static inline void finn_close_buffer_for_write(finn_bit_pump_for_write *bp) -{ - uint64_t *p; - - // The accumulator is not empty. - if (bp->empty_bit_count < 64U) - { - // Update the buffer with the last word. - if (bp->end_of_buffer) - { - *bp->buffer_position = bp->accumulator; - } - - // Advance to the next word to get an accurate word count. - bp->buffer_position++; - - // Update the checksum. - bp->checksum = ((bp->checksum << 1U) ^ (bp->checksum & 1U)) ^ bp->accumulator; - } - - // Zero out the rest of the buffer. - for (p = bp->buffer_position; p < bp->end_of_buffer; ++p) - { - *p = 0u; - } -} - - -static NV_STATUS FinnRmApiSerializeInternal(NvU64 interface, NvU64 message, const char *src, char **dst, size_t dst_size, NvBool seri_up); -static NV_STATUS FinnRmApiSerializeInterface(NvU64 interface, NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnRmApiDeserializeInternal(const char **src, NvLength src_size, char *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS FinnRmApiDeserializeInterface(NvU64 interface, NvU64 message, finn_bit_pump_for_read *bp, char *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS FinnNv01RootNvdSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv01RootNvdDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_ROOT_NVD *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv01RootNvdGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv01Device0DmaSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv01Device0DmaDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_DMA *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv01Device0DmaGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv01Device0FbSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv01Device0FbDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_FB *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv01Device0FbGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv01Device0FifoSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv01Device0FifoDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_FIFO *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv01Device0FifoGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv01Device0GpuSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv01Device0GpuDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_GPU *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv01Device0GpuGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv01Device0GrSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv01Device0GrDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_GR *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv01Device0GrGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv01Device0HostSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv01Device0HostDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_HOST *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv01Device0HostGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv01Device0MsencSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv01Device0MsencDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_MSENC *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv01Device0MsencGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv20Subdevice0CeSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv20Subdevice0CeDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_CE *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv20Subdevice0CeGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv20Subdevice0GpuSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv20Subdevice0GpuDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_GPU *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv20Subdevice0GpuGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv20Subdevice0I2cSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv20Subdevice0I2cDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_I2C *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv20Subdevice0I2cGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv20Subdevice0NvdSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv20Subdevice0NvdDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_NVD *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv20Subdevice0NvdGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv20Subdevice0PerfSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv20Subdevice0PerfDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_PERF *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv20Subdevice0PerfGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv20Subdevice0RcSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv20Subdevice0RcDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_RC *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv20Subdevice0RcGetUnserializedSize(NvU64 message); - -static NV_STATUS FinnNv20SubdeviceDiagGpuSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv20SubdeviceDiagGpuDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_DIAG_GPU *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv20SubdeviceDiagGpuGetUnserializedSize(NvU64 message); -static NV_STATUS FinnNv40I2cI2cSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnNv40I2cI2cDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV40_I2C_I2C *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnNv40I2cI2cGetUnserializedSize(NvU64 message); -static NV_STATUS FinnGt200DebuggerDebugSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnGt200DebuggerDebugDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_GT200_DEBUGGER_DEBUG *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnGt200DebuggerDebugGetUnserializedSize(NvU64 message); -static NV_STATUS FinnMaxwellChannelGpfifoAGpfifoSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnMaxwellChannelGpfifoAGpfifoDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO *dst, NvLength dst_size, NvBool deser_up); -static NvU64 FinnMaxwellChannelGpfifoAGpfifoGetUnserializedSize(NvU64 message); - -static NV_STATUS Nv0000CtrlNvdGetDumpParamsSerialize(const NV0000_CTRL_NVD_GET_DUMP_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv0000CtrlNvdGetDumpParamsDeserialize(finn_bit_pump_for_read *bp, NV0000_CTRL_NVD_GET_DUMP_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv0080CtrlDmaUpdatePde2PageTableParamsSerialize(const NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv0080CtrlDmaUpdatePde2PageTableParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv0080CtrlDmaUpdatePde2ParamsSerialize(const NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv0080CtrlDmaUpdatePde2ParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv0080CtrlFbGetCapsParamsSerialize(const NV0080_CTRL_FB_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv0080CtrlFbGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_FB_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv0080CtrlFifoGetCapsParamsSerialize(const NV0080_CTRL_FIFO_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv0080CtrlFifoGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv0080CtrlFifoChannelSerialize(const NV0080_CTRL_FIFO_CHANNEL *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv0080CtrlFifoChannelDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_CHANNEL *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv0080CtrlFifoStartSelectedChannelsParamsSerialize(const NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv0080CtrlFifoStartSelectedChannelsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv0080CtrlFifoGetChannellistParamsSerialize(const NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv0080CtrlFifoGetChannellistParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv0080CtrlGpuGetClasslistParamsSerialize(const NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv0080CtrlGpuGetClasslistParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv0080CtrlGrGetCapsParamsSerialize(const NV0080_CTRL_GR_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv0080CtrlGrGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_GR_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv0080CtrlHostGetCapsParamsSerialize(const NV0080_CTRL_HOST_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv0080CtrlHostGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_HOST_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv0080CtrlMsencGetCapsParamsSerialize(const NV0080_CTRL_MSENC_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv0080CtrlMsencGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_MSENC_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv2080CtrlCeGetCapsParamsSerialize(const NV2080_CTRL_CE_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv2080CtrlCeGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_CE_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv2080CtrlGpuGetEnginesParamsSerialize(const NV2080_CTRL_GPU_GET_ENGINES_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv2080CtrlGpuGetEnginesParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_GPU_GET_ENGINES_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv2080CtrlGpuGetEngineClasslistParamsSerialize(const NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv2080CtrlGpuGetEngineClasslistParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv2080CtrlGpumonSamplesSerialize(const NV2080_CTRL_GPUMON_SAMPLES *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv2080CtrlGpumonSamplesDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_GPUMON_SAMPLES *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv2080CtrlI2cAccessParamsSerialize(const NV2080_CTRL_I2C_ACCESS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv2080CtrlI2cAccessParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_I2C_ACCESS_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv2080CtrlNvdGetDumpParamsSerialize(const NV2080_CTRL_NVD_GET_DUMP_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv2080CtrlNvdGetDumpParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_NVD_GET_DUMP_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv2080CtrlRcReadVirtualMemParamsSerialize(const NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv2080CtrlRcReadVirtualMemParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *dst, NvLength dst_size, NvBool deser_up); - -static NV_STATUS Nv402cCtrlI2cIndexedParamsSerialize(const NV402C_CTRL_I2C_INDEXED_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cIndexedParamsDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_INDEXED_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv402cCtrlI2cTransactionTypeCheckEnum(NV402C_CTRL_I2C_TRANSACTION_TYPE id); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusQuickRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusQuickRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cByteRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cByteRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBlockRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBlockRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusByteRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusByteRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusWordRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusWordRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBufferRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBufferRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusProcessCallSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusProcessCallDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataReadEdidDdcSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataReadEdidDdcDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv402cCtrlI2cTransactionDataSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA *src, finn_bit_pump_for_write *bp, NvBool seri_up, NV402C_CTRL_I2C_TRANSACTION_TYPE transType); -static NV_STATUS Nv402cCtrlI2cTransactionDataDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA *dst, NvLength dst_size, NvBool deser_up, NV402C_CTRL_I2C_TRANSACTION_TYPE transType); -static NV_STATUS Nv402cCtrlI2cTransactionParamsSerialize(const NV402C_CTRL_I2C_TRANSACTION_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv402cCtrlI2cTransactionParamsDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv83deCtrlDebugReadMemoryParamsSerialize(const NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv83deCtrlDebugReadMemoryParamsDeserialize(finn_bit_pump_for_read *bp, NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nv83deCtrlDebugWriteMemoryParamsSerialize(const NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nv83deCtrlDebugWriteMemoryParamsDeserialize(finn_bit_pump_for_read *bp, NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nvb06fCtrlGetEngineCtxDataParamsSerialize(const NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nvb06fCtrlGetEngineCtxDataParamsDeserialize(finn_bit_pump_for_read *bp, NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nvb06fCtrlCmdMigrateEngineCtxDataFinnParamsSerialize(const NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nvb06fCtrlCmdMigrateEngineCtxDataFinnParamsDeserialize(finn_bit_pump_for_read *bp, NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nvb06fCtrlSaveEngineCtxDataParamsSerialize(const NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nvb06fCtrlSaveEngineCtxDataParamsDeserialize(finn_bit_pump_for_read *bp, NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *dst, NvLength dst_size, NvBool deser_up); -static NV_STATUS Nvb06fCtrlCmdRestoreEngineCtxDataFinnParamsSerialize(const NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS Nvb06fCtrlCmdRestoreEngineCtxDataFinnParamsDeserialize(finn_bit_pump_for_read *bp, NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *dst, NvLength dst_size, NvBool deser_up); - -NV_STATUS FinnRmApiSerializeUp(NvU64 interface, NvU64 message, const void *src, NvU8 **dst, NvLength dst_size) -{ - return FinnRmApiSerializeInternal(interface, message, (const char *) src, (char **) dst, dst_size / sizeof(NvU8), NV_TRUE); -} - -NV_STATUS FinnRmApiSerializeDown(NvU64 interface, NvU64 message, const void *src, NvU8 **dst, NvLength dst_size) -{ - return FinnRmApiSerializeInternal(interface, message, (const char *) src, (char **) dst, dst_size / sizeof(NvU8), NV_FALSE); -} - -NV_STATUS FinnRmApiDeserializeDown(NvU8 **src, NvLength src_size, void *dst, NvLength dst_size) -{ - return FinnRmApiDeserializeInternal((const char **) src, src_size / sizeof(NvU8), (char *) dst, dst_size, NV_FALSE); -} - -NV_STATUS FinnRmApiDeserializeUp(NvU8 **src, NvLength src_size, void *dst, NvLength dst_size) -{ - return FinnRmApiDeserializeInternal((const char **) src, src_size / sizeof(NvU8), (char *) dst, dst_size, NV_TRUE); -} - - -static NV_STATUS FinnRmApiSerializeInternal(NvU64 interface, NvU64 message, const char *src, char **dst, size_t dst_size, NvBool seri_up) -{ - // Header - FINN_RM_API *header; - - // Buffer end - // `char` is the C-standrd unit of measure for `sizeof` and `size_t`. - const char *dst_end; - - // Bit pump is used to fill the buffer with serialized data. - finn_bit_pump_for_write bp; - - // Error code returned from serialization - NV_STATUS error_code; - - // Input validation - // Null pointers are not permitted. - // Buffer must begin on an 8-byte boundary. - if (!src || !dst || !(*dst) || !dst_size || (uintptr_t) dst & 0x7u) - { - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - return NV_ERR_INVALID_ARGUMENT; - } - - // Header is at the start of the buffer. - header = (FINN_RM_API *) *dst; - - // Buffer must end on an 8-byte boundary, so round down. - dst_end = (const char *) ((uintptr_t) (*dst + dst_size) & ~ (uintptr_t) 0x7); - - // Set header data. - header->version = FINN_SERIALIZATION_VERSION; - header->payloadSize = 0; // Zero until completed successfully - header->interface = interface; - header->message = message; - - // Advance past header. - (*dst) += sizeof(FINN_RM_API); - - // Open the bit pump. - finn_open_buffer_for_write(&bp, (uint64_t *) *dst, (const uint64_t *) dst_end); - - // Call the serializer. - error_code = FinnRmApiSerializeInterface(interface, message, src, &bp, seri_up); - - // Close the bit pump. - finn_close_buffer_for_write(&bp); - - // Payload size in bytes - if (error_code == NV_OK) - header->payloadSize = (NvU64) (((const char *) bp.buffer_position) - ((const char *) header)); - - // Indicate the ending location. - *dst = (char *) bp.buffer_position; - - // Done - return error_code; -} - - -static NV_STATUS FinnRmApiSerializeInterface(NvU64 interface, NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - - - // Forward to interface-specific serialize routine - switch (interface) - { - case FINN_INTERFACE_ID(FINN_NV01_ROOT_NVD): - return FinnNv01RootNvdSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_DMA): - return FinnNv01Device0DmaSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_FB): - return FinnNv01Device0FbSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_FIFO): - return FinnNv01Device0FifoSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_GPU): - return FinnNv01Device0GpuSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_GR): - return FinnNv01Device0GrSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_HOST): - return FinnNv01Device0HostSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_MSENC): - return FinnNv01Device0MsencSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_CE): - return FinnNv20Subdevice0CeSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_GPU): - return FinnNv20Subdevice0GpuSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_I2C): - return FinnNv20Subdevice0I2cSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_NVD): - return FinnNv20Subdevice0NvdSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_PERF): - return FinnNv20Subdevice0PerfSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_RC): - return FinnNv20Subdevice0RcSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_DIAG_GPU): - return FinnNv20SubdeviceDiagGpuSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_NV40_I2C_I2C): - return FinnNv40I2cI2cSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_GT200_DEBUGGER_DEBUG): - return FinnGt200DebuggerDebugSerializeMessage(message, src, bp, seri_up); - case FINN_INTERFACE_ID(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO): - return FinnMaxwellChannelGpfifoAGpfifoSerializeMessage(message, src, bp, seri_up); - - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - - -static NV_STATUS FinnRmApiDeserializeInternal(const char **src, NvLength src_size, char *dst, NvLength dst_size, NvBool deser_up) -{ - // Header - const FINN_RM_API *header; - - // End of data - const char *src_max; - - // Bit pump is used to read the serialized data. - finn_bit_pump_for_read bp; - - // Error code - NV_STATUS status; - - // Input validation - // Null pointers are not permitted. - // Buffer must begin on an 8-byte boundary. - if (!src || !(*src) || !src_size || !dst || !dst_size || (uintptr_t) *src & 0x7u) - { - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - return NV_ERR_INVALID_ARGUMENT; - } - - // Header data comes first. - header = (const FINN_RM_API *) *src; - - // Check the version. - if (header->version != FINN_SERIALIZATION_VERSION) - { - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - return NV_ERR_LIB_RM_VERSION_MISMATCH; - } - - // Set src_max for buffer bounds checking. - src_max = *src + src_size; - - // Check that source buffer is large enough. - if (sizeof(FINN_RM_API) > src_size || - header->payloadSize > src_size || - header->payloadSize < sizeof(FINN_RM_API)) - { - *src = (const char *) &header->payloadSize; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - return NV_ERR_BUFFER_TOO_SMALL; - } - - // Open the bit punp, skipping past the header. - finn_open_buffer_for_read(&bp, (const uint64_t *) (*src + sizeof(FINN_RM_API)), (const uint64_t *) (src_max)); - - // Dispatch to interface-specific routine - status = FinnRmApiDeserializeInterface(header->interface, header->message, &bp, dst, dst_size, deser_up); - - // Update the buffer position, error or not. - *(src) = (const char *) bp.buffer_position; - - // Nothing more to do if there was an error. - if (status != NV_OK) - return status; - - // Update the checksum. - finn_close_buffer_for_read(&bp); - - // TODO: Check the checksum - - // Check that the declared size matches the serialization outcome. - if (header->payloadSize != (NvU64) (((const char *) bp.buffer_position) - ((const char *) header))) - { - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - return NV_ERR_INVALID_ARGUMENT; - } - - // All good - return NV_OK; -} - - -static NV_STATUS FinnRmApiDeserializeInterface(NvU64 interface, NvU64 message, finn_bit_pump_for_read *bp, char *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to interface-specific routine - switch (interface) - { - case FINN_INTERFACE_ID(FINN_NV01_ROOT_NVD): - return FinnNv01RootNvdDeserializeMessage(message, bp, (FINN_NV01_ROOT_NVD *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_DMA): - return FinnNv01Device0DmaDeserializeMessage(message, bp, (FINN_NV01_DEVICE_0_DMA *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_FB): - return FinnNv01Device0FbDeserializeMessage(message, bp, (FINN_NV01_DEVICE_0_FB *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_FIFO): - return FinnNv01Device0FifoDeserializeMessage(message, bp, (FINN_NV01_DEVICE_0_FIFO *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_GPU): - return FinnNv01Device0GpuDeserializeMessage(message, bp, (FINN_NV01_DEVICE_0_GPU *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_GR): - return FinnNv01Device0GrDeserializeMessage(message, bp, (FINN_NV01_DEVICE_0_GR *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_HOST): - return FinnNv01Device0HostDeserializeMessage(message, bp, (FINN_NV01_DEVICE_0_HOST *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_MSENC): - return FinnNv01Device0MsencDeserializeMessage(message, bp, (FINN_NV01_DEVICE_0_MSENC *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_CE): - return FinnNv20Subdevice0CeDeserializeMessage(message, bp, (FINN_NV20_SUBDEVICE_0_CE *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_GPU): - return FinnNv20Subdevice0GpuDeserializeMessage(message, bp, (FINN_NV20_SUBDEVICE_0_GPU *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_I2C): - return FinnNv20Subdevice0I2cDeserializeMessage(message, bp, (FINN_NV20_SUBDEVICE_0_I2C *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_NVD): - return FinnNv20Subdevice0NvdDeserializeMessage(message, bp, (FINN_NV20_SUBDEVICE_0_NVD *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_PERF): - return FinnNv20Subdevice0PerfDeserializeMessage(message, bp, (FINN_NV20_SUBDEVICE_0_PERF *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_RC): - return FinnNv20Subdevice0RcDeserializeMessage(message, bp, (FINN_NV20_SUBDEVICE_0_RC *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_DIAG_GPU): - return FinnNv20SubdeviceDiagGpuDeserializeMessage(message, bp, (FINN_NV20_SUBDEVICE_DIAG_GPU *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_NV40_I2C_I2C): - return FinnNv40I2cI2cDeserializeMessage(message, bp, (FINN_NV40_I2C_I2C *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_GT200_DEBUGGER_DEBUG): - return FinnGt200DebuggerDebugDeserializeMessage(message, bp, (FINN_GT200_DEBUGGER_DEBUG *) dst, dst_size, deser_up); - case FINN_INTERFACE_ID(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO): - return FinnMaxwellChannelGpfifoAGpfifoDeserializeMessage(message, bp, (FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO *) dst, dst_size, deser_up); - - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - - -NvU64 FinnRmApiGetSerializedSize(NvU64 interface, NvU64 message, const NvP64 src) -{ - // Bit pump with writing disabled. - finn_bit_pump_for_write bp; - finn_open_buffer_for_write(&bp, (uint64_t *) 0, (const uint64_t *) 0); - - // Call the serializer with write-suppressed bit pump. - // The size is the same in bith directions (up/down). - // Eeturn zero on error to indicate that this API is not serialized by FINN. - if (FinnRmApiSerializeInterface(interface, message, (const char *) NvP64_VALUE(src), &bp, 0) != NV_OK) - return 0; - - // Close the bit pump. - finn_close_buffer_for_write(&bp); - - // Add the header size in bytes to the amount of data serialzied. - // `buffer_position` is the payload size (not really the buffer position). - return (NvU64) NV_PTR_TO_NvP64(bp.buffer_position) + sizeof(FINN_RM_API); -} - - -NvU64 FinnRmApiGetUnserializedSize(NvU64 interface, NvU64 message) -{ - // Forward to interface-specific routine - switch (interface) - { - case FINN_INTERFACE_ID(FINN_NV01_ROOT_NVD): - return FinnNv01RootNvdGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_DMA): - return FinnNv01Device0DmaGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_FB): - return FinnNv01Device0FbGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_FIFO): - return FinnNv01Device0FifoGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_GPU): - return FinnNv01Device0GpuGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_GR): - return FinnNv01Device0GrGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_HOST): - return FinnNv01Device0HostGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_MSENC): - return FinnNv01Device0MsencGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_CE): - return FinnNv20Subdevice0CeGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_GPU): - return FinnNv20Subdevice0GpuGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_I2C): - return FinnNv20Subdevice0I2cGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_NVD): - return FinnNv20Subdevice0NvdGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_PERF): - return FinnNv20Subdevice0PerfGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_RC): - return FinnNv20Subdevice0RcGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_DIAG_GPU): - return FinnNv20SubdeviceDiagGpuGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_NV40_I2C_I2C): - return FinnNv40I2cI2cGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_GT200_DEBUGGER_DEBUG): - return FinnGt200DebuggerDebugGetUnserializedSize(message); - case FINN_INTERFACE_ID(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO): - return FinnMaxwellChannelGpfifoAGpfifoGetUnserializedSize(message); - default: - return 0; - } -} - -static NV_STATUS FinnNv01RootNvdSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0000_CTRL_NVD_GET_DUMP_PARAMS): - return Nv0000CtrlNvdGetDumpParamsSerialize((const NV0000_CTRL_NVD_GET_DUMP_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv01RootNvdDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_ROOT_NVD *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0000_CTRL_NVD_GET_DUMP_PARAMS): - return Nv0000CtrlNvdGetDumpParamsDeserialize(bp, (NV0000_CTRL_NVD_GET_DUMP_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv01RootNvdGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0000_CTRL_NVD_GET_DUMP_PARAMS): - return sizeof(NV0000_CTRL_NVD_GET_DUMP_PARAMS); - default: - return 0; - } -} - -static NV_STATUS FinnNv01Device0DmaSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS): - return Nv0080CtrlDmaUpdatePde2ParamsSerialize((const NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv01Device0DmaDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_DMA *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS): - return Nv0080CtrlDmaUpdatePde2ParamsDeserialize(bp, (NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv01Device0DmaGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS): - return sizeof(NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS); - default: - return 0; - } -} - -static NV_STATUS FinnNv01Device0FbSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_FB_GET_CAPS_PARAMS): - return Nv0080CtrlFbGetCapsParamsSerialize((const NV0080_CTRL_FB_GET_CAPS_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv01Device0FbDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_FB *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_FB_GET_CAPS_PARAMS): - return Nv0080CtrlFbGetCapsParamsDeserialize(bp, (NV0080_CTRL_FB_GET_CAPS_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv01Device0FbGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_FB_GET_CAPS_PARAMS): - return sizeof(NV0080_CTRL_FB_GET_CAPS_PARAMS); - default: - return 0; - } -} - -static NV_STATUS FinnNv01Device0FifoSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CAPS_PARAMS): - return Nv0080CtrlFifoGetCapsParamsSerialize((const NV0080_CTRL_FIFO_GET_CAPS_PARAMS *) src, bp, seri_up); - case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS): - return Nv0080CtrlFifoStartSelectedChannelsParamsSerialize((const NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *) src, bp, seri_up); - case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS): - return Nv0080CtrlFifoGetChannellistParamsSerialize((const NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv01Device0FifoDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_FIFO *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CAPS_PARAMS): - return Nv0080CtrlFifoGetCapsParamsDeserialize(bp, (NV0080_CTRL_FIFO_GET_CAPS_PARAMS *) dst, dst_size, deser_up); - case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS): - return Nv0080CtrlFifoStartSelectedChannelsParamsDeserialize(bp, (NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *) dst, dst_size, deser_up); - case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS): - return Nv0080CtrlFifoGetChannellistParamsDeserialize(bp, (NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv01Device0FifoGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CAPS_PARAMS): - return sizeof(NV0080_CTRL_FIFO_GET_CAPS_PARAMS); - case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS): - return sizeof(NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS); - case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS): - return sizeof(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS); - default: - return 0; - } -} - -static NV_STATUS FinnNv01Device0GpuSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS): - return Nv0080CtrlGpuGetClasslistParamsSerialize((const NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv01Device0GpuDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_GPU *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS): - return Nv0080CtrlGpuGetClasslistParamsDeserialize(bp, (NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv01Device0GpuGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS): - return sizeof(NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS); - default: - return 0; - } -} - -static NV_STATUS FinnNv01Device0GrSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_GR_GET_CAPS_PARAMS): - return Nv0080CtrlGrGetCapsParamsSerialize((const NV0080_CTRL_GR_GET_CAPS_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv01Device0GrDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_GR *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_GR_GET_CAPS_PARAMS): - return Nv0080CtrlGrGetCapsParamsDeserialize(bp, (NV0080_CTRL_GR_GET_CAPS_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv01Device0GrGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_GR_GET_CAPS_PARAMS): - return sizeof(NV0080_CTRL_GR_GET_CAPS_PARAMS); - default: - return 0; - } -} - -static NV_STATUS FinnNv01Device0HostSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_HOST_GET_CAPS_PARAMS): - return Nv0080CtrlHostGetCapsParamsSerialize((const NV0080_CTRL_HOST_GET_CAPS_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv01Device0HostDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_HOST *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_HOST_GET_CAPS_PARAMS): - return Nv0080CtrlHostGetCapsParamsDeserialize(bp, (NV0080_CTRL_HOST_GET_CAPS_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv01Device0HostGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_HOST_GET_CAPS_PARAMS): - return sizeof(NV0080_CTRL_HOST_GET_CAPS_PARAMS); - default: - return 0; - } -} - -static NV_STATUS FinnNv01Device0MsencSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_MSENC_GET_CAPS_PARAMS): - return Nv0080CtrlMsencGetCapsParamsSerialize((const NV0080_CTRL_MSENC_GET_CAPS_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv01Device0MsencDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_MSENC *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_MSENC_GET_CAPS_PARAMS): - return Nv0080CtrlMsencGetCapsParamsDeserialize(bp, (NV0080_CTRL_MSENC_GET_CAPS_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv01Device0MsencGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV0080_CTRL_MSENC_GET_CAPS_PARAMS): - return sizeof(NV0080_CTRL_MSENC_GET_CAPS_PARAMS); - default: - return 0; - } -} - -static NV_STATUS FinnNv20Subdevice0CeSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_CE_GET_CAPS_PARAMS): - return Nv2080CtrlCeGetCapsParamsSerialize((const NV2080_CTRL_CE_GET_CAPS_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv20Subdevice0CeDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_CE *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_CE_GET_CAPS_PARAMS): - return Nv2080CtrlCeGetCapsParamsDeserialize(bp, (NV2080_CTRL_CE_GET_CAPS_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv20Subdevice0CeGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_CE_GET_CAPS_PARAMS): - return sizeof(NV2080_CTRL_CE_GET_CAPS_PARAMS); - default: - return 0; - } -} - -static NV_STATUS FinnNv20Subdevice0GpuSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINES_PARAMS): - return Nv2080CtrlGpuGetEnginesParamsSerialize((const NV2080_CTRL_GPU_GET_ENGINES_PARAMS *) src, bp, seri_up); - case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS): - return Nv2080CtrlGpuGetEngineClasslistParamsSerialize((const NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv20Subdevice0GpuDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_GPU *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINES_PARAMS): - return Nv2080CtrlGpuGetEnginesParamsDeserialize(bp, (NV2080_CTRL_GPU_GET_ENGINES_PARAMS *) dst, dst_size, deser_up); - case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS): - return Nv2080CtrlGpuGetEngineClasslistParamsDeserialize(bp, (NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv20Subdevice0GpuGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINES_PARAMS): - return sizeof(NV2080_CTRL_GPU_GET_ENGINES_PARAMS); - case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS): - return sizeof(NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS); - default: - return 0; - } -} - -static NV_STATUS FinnNv20Subdevice0I2cSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_I2C_ACCESS_PARAMS): - return Nv2080CtrlI2cAccessParamsSerialize((const NV2080_CTRL_I2C_ACCESS_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv20Subdevice0I2cDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_I2C *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_I2C_ACCESS_PARAMS): - return Nv2080CtrlI2cAccessParamsDeserialize(bp, (NV2080_CTRL_I2C_ACCESS_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv20Subdevice0I2cGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_I2C_ACCESS_PARAMS): - return sizeof(NV2080_CTRL_I2C_ACCESS_PARAMS); - default: - return 0; - } -} - -static NV_STATUS FinnNv20Subdevice0NvdSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_NVD_GET_DUMP_PARAMS): - return Nv2080CtrlNvdGetDumpParamsSerialize((const NV2080_CTRL_NVD_GET_DUMP_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv20Subdevice0NvdDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_NVD *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_NVD_GET_DUMP_PARAMS): - return Nv2080CtrlNvdGetDumpParamsDeserialize(bp, (NV2080_CTRL_NVD_GET_DUMP_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv20Subdevice0NvdGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_NVD_GET_DUMP_PARAMS): - return sizeof(NV2080_CTRL_NVD_GET_DUMP_PARAMS); - default: - return 0; - } -} - -static NV_STATUS FinnNv20Subdevice0PerfSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM): - return Nv2080CtrlGpumonSamplesSerialize((const NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv20Subdevice0PerfDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_PERF *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM): - return Nv2080CtrlGpumonSamplesDeserialize(bp, (NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv20Subdevice0PerfGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM): - return sizeof(NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM); - default: - return 0; - } -} - -static NV_STATUS FinnNv20Subdevice0RcSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS): - return Nv2080CtrlRcReadVirtualMemParamsSerialize((const NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv20Subdevice0RcDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_RC *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS): - return Nv2080CtrlRcReadVirtualMemParamsDeserialize(bp, (NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv20Subdevice0RcGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS): - return sizeof(NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS); - default: - return 0; - } -} - -static NV_STATUS FinnNv20SubdeviceDiagGpuSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv20SubdeviceDiagGpuDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_DIAG_GPU *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv20SubdeviceDiagGpuGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - default: - return 0; - } -} - -static NV_STATUS FinnNv40I2cI2cSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV402C_CTRL_I2C_INDEXED_PARAMS): - return Nv402cCtrlI2cIndexedParamsSerialize((const NV402C_CTRL_I2C_INDEXED_PARAMS *) src, bp, seri_up); - case FINN_MESSAGE_ID(NV402C_CTRL_I2C_TRANSACTION_PARAMS): - return Nv402cCtrlI2cTransactionParamsSerialize((const NV402C_CTRL_I2C_TRANSACTION_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnNv40I2cI2cDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV40_I2C_I2C *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV402C_CTRL_I2C_INDEXED_PARAMS): - return Nv402cCtrlI2cIndexedParamsDeserialize(bp, (NV402C_CTRL_I2C_INDEXED_PARAMS *) dst, dst_size, deser_up); - case FINN_MESSAGE_ID(NV402C_CTRL_I2C_TRANSACTION_PARAMS): - return Nv402cCtrlI2cTransactionParamsDeserialize(bp, (NV402C_CTRL_I2C_TRANSACTION_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnNv40I2cI2cGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV402C_CTRL_I2C_INDEXED_PARAMS): - return sizeof(NV402C_CTRL_I2C_INDEXED_PARAMS); - case FINN_MESSAGE_ID(NV402C_CTRL_I2C_TRANSACTION_PARAMS): - return sizeof(NV402C_CTRL_I2C_TRANSACTION_PARAMS); - default: - return 0; - } -} - -static NV_STATUS FinnGt200DebuggerDebugSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS): - return Nv83deCtrlDebugReadMemoryParamsSerialize((const NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *) src, bp, seri_up); - case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS): - return Nv83deCtrlDebugWriteMemoryParamsSerialize((const NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnGt200DebuggerDebugDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_GT200_DEBUGGER_DEBUG *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS): - return Nv83deCtrlDebugReadMemoryParamsDeserialize(bp, (NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *) dst, dst_size, deser_up); - case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS): - return Nv83deCtrlDebugWriteMemoryParamsDeserialize(bp, (NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnGt200DebuggerDebugGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS): - return sizeof(NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS); - case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS): - return sizeof(NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS); - default: - return 0; - } -} - -static NV_STATUS FinnMaxwellChannelGpfifoAGpfifoSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS): - return Nvb06fCtrlGetEngineCtxDataParamsSerialize((const NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *) src, bp, seri_up); - case FINN_MESSAGE_ID(NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS): - return Nvb06fCtrlCmdMigrateEngineCtxDataFinnParamsSerialize((const NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS *) src, bp, seri_up); - case FINN_MESSAGE_ID(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS): - return Nvb06fCtrlSaveEngineCtxDataParamsSerialize((const NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *) src, bp, seri_up); - case FINN_MESSAGE_ID(NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS): - return Nvb06fCtrlCmdRestoreEngineCtxDataFinnParamsSerialize((const NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *) src, bp, seri_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NV_STATUS FinnMaxwellChannelGpfifoAGpfifoDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO *dst, NvLength dst_size, NvBool deser_up) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS): - return Nvb06fCtrlGetEngineCtxDataParamsDeserialize(bp, (NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *) dst, dst_size, deser_up); - case FINN_MESSAGE_ID(NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS): - return Nvb06fCtrlCmdMigrateEngineCtxDataFinnParamsDeserialize(bp, (NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS *) dst, dst_size, deser_up); - case FINN_MESSAGE_ID(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS): - return Nvb06fCtrlSaveEngineCtxDataParamsDeserialize(bp, (NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *) dst, dst_size, deser_up); - case FINN_MESSAGE_ID(NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS): - return Nvb06fCtrlCmdRestoreEngineCtxDataFinnParamsDeserialize(bp, (NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *) dst, dst_size, deser_up); - - // Everything else is unsupported. - default: - { - FINN_ERROR(NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; - } - } -} - -static NvU64 FinnMaxwellChannelGpfifoAGpfifoGetUnserializedSize(NvU64 message) -{ - // Forward to message-specific routine. - switch (message) - { - case FINN_MESSAGE_ID(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS): - return sizeof(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS); - case FINN_MESSAGE_ID(NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS): - return sizeof(NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS); - case FINN_MESSAGE_ID(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS): - return sizeof(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS); - case FINN_MESSAGE_ID(NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS): - return sizeof(NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS); - default: - return 0; - } -} - -static NV_STATUS Nv0000CtrlNvdGetDumpParamsSerialize(const NV0000_CTRL_NVD_GET_DUMP_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x7; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->component - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->component, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - if (src->size > NV0000_CTRL_NVD_MAX_DUMP_SIZE) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->size, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->pBuffer), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->pBuffer) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->size); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pBuffer))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->pBuffer) - FINN_FREE(NvP64_VALUE(src->pBuffer)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv0000CtrlNvdGetDumpParamsDeserialize(finn_bit_pump_for_read *bp, NV0000_CTRL_NVD_GET_DUMP_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV0000_CTRL_NVD_GET_DUMP_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x7) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->component = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->component - - - // Deserialize 4-byte NvU32 object. - dst->size = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->size > NV0000_CTRL_NVD_MAX_DUMP_SIZE) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->pBuffer = FINN_MALLOC((dst->size)); - if (!dst->pBuffer) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->pBuffer, (dst->size)); - } - - // Otherwise the pointer must be provided. - else if (!dst->pBuffer) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->size); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->pBuffer))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->pBuffer = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlDmaUpdatePde2PageTableParamsSerialize(const NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x7; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->physAddr - // Deserialize 8-byte NvU64 object. - if (finn_write_buffer(bp, src->physAddr, 8 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->numEntries - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->numEntries, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->aperture - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->aperture, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlDmaUpdatePde2PageTableParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x7) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 8-byte NvU64 object. - dst->physAddr = (NvU64) finn_read_buffer(bp, 8 * 8); - // No range check for dst->physAddr - - - // Deserialize 4-byte NvU32 object. - dst->numEntries = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->numEntries - - - // Deserialize 4-byte NvU32 object. - dst->aperture = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->aperture - - -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlDmaUpdatePde2ParamsSerialize(const NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x3f; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->pdeIndex - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->pdeIndex, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->flags - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->flags, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->hVASpace - // Deserialize 4-byte NvHandle object. - if (finn_write_buffer(bp, src->hVASpace, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->subDeviceId - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->subDeviceId, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Bounded nested fields - for (NvU64 i = 0; i < (NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE); ++i) - { - status = Nv0080CtrlDmaUpdatePde2PageTableParamsSerialize(&src->ptParams[i], bp, seri_up); - if (status != NV_OK) - goto exit; - } - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->pPdeBuffer), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->pPdeBuffer) - { - - // Serialize each 8-byte NvU64 element. - for (NvU64 j = 0; j < 1; ++j) - { - if (finn_write_buffer(bp, ((NvU64 *) NvP64_VALUE(src->pPdeBuffer))[j], 8 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->pPdeBuffer) - FINN_FREE(NvP64_VALUE(src->pPdeBuffer)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlDmaUpdatePde2ParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x3f) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->pdeIndex = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->pdeIndex - - - // Deserialize 4-byte NvU32 object. - dst->flags = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->flags - - - // Deserialize 4-byte NvHandle object. - dst->hVASpace = (NvHandle) finn_read_buffer(bp, 4 * 8); - // No range check for dst->hVASpace - - - // Deserialize 4-byte NvU32 object. - dst->subDeviceId = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->subDeviceId - - - // Bounded nested fields - for (NvU64 i = 0; i < (NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE); ++i) - { - status = Nv0080CtrlDmaUpdatePde2PageTableParamsDeserialize(bp, &dst->ptParams[i], dst_size, deser_up); - if (status != NV_OK) - goto exit; - } - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->pPdeBuffer = FINN_MALLOC(8); - if (!dst->pPdeBuffer) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->pPdeBuffer, 8); - } - - // Otherwise the pointer must be provided. - else if (!dst->pPdeBuffer) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 8-byte NvU64 element. - for (NvU64 j = 0; j < 1; ++j) - { - ((NvU64 *) NvP64_VALUE(dst->pPdeBuffer))[j] = (NvU64) finn_read_buffer(bp, 8 * 8); - } - } - else - { - if (!deser_up) - dst->pPdeBuffer = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlFbGetCapsParamsSerialize(const NV0080_CTRL_FB_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x3; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - if (src->capsTblSize > NV0080_CTRL_FB_CAPS_TBL_SIZE) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->capsTblSize, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->capsTbl), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->capsTbl) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->capsTblSize); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->capsTbl))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->capsTbl) - FINN_FREE(NvP64_VALUE(src->capsTbl)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlFbGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_FB_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV0080_CTRL_FB_GET_CAPS_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x3) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->capsTblSize = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->capsTblSize > NV0080_CTRL_FB_CAPS_TBL_SIZE) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->capsTbl = FINN_MALLOC((dst->capsTblSize)); - if (!dst->capsTbl) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->capsTbl, (dst->capsTblSize)); - } - - // Otherwise the pointer must be provided. - else if (!dst->capsTbl) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->capsTblSize); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->capsTbl))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->capsTbl = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlFifoGetCapsParamsSerialize(const NV0080_CTRL_FIFO_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x3; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - if (src->capsTblSize > NV0080_CTRL_FIFO_CAPS_TBL_SIZE) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->capsTblSize, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->capsTbl), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->capsTbl) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->capsTblSize); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->capsTbl))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->capsTbl) - FINN_FREE(NvP64_VALUE(src->capsTbl)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlFifoGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV0080_CTRL_FIFO_GET_CAPS_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x3) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->capsTblSize = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->capsTblSize > NV0080_CTRL_FIFO_CAPS_TBL_SIZE) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->capsTbl = FINN_MALLOC((dst->capsTblSize)); - if (!dst->capsTbl) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->capsTbl, (dst->capsTblSize)); - } - - // Otherwise the pointer must be provided. - else if (!dst->capsTbl) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->capsTblSize); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->capsTbl))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->capsTbl = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlFifoChannelSerialize(const NV0080_CTRL_FIFO_CHANNEL *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x1; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->hChannel - // Deserialize 4-byte NvHandle object. - if (finn_write_buffer(bp, src->hChannel, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlFifoChannelDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_CHANNEL *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV0080_CTRL_FIFO_CHANNEL) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x1) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvHandle object. - dst->hChannel = (NvHandle) finn_read_buffer(bp, 4 * 8); - // No range check for dst->hChannel - - -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlFifoStartSelectedChannelsParamsSerialize(const NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x7; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->fifoStartChannelListCount - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->fifoStartChannelListCount, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - for (NvU64 i = 0; i < (8); ++i) - { - // No range check for src->channelHandle[i] - // Deserialize 4-byte NvHandle object. - if (finn_write_buffer(bp, src->channelHandle[i], 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->fifoStartChannelList), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->fifoStartChannelList) - { - for (NvU64 i = 0; i < (src->fifoStartChannelListCount); ++i) - { - status = Nv0080CtrlFifoChannelSerialize(&(((const NV0080_CTRL_FIFO_CHANNEL *) (NvP64_VALUE(src->fifoStartChannelList)))[i]), bp, seri_up); - - if (status != NV_OK) - goto exit; - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->fifoStartChannelList) - FINN_FREE(src->fifoStartChannelList); - } - - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlFifoStartSelectedChannelsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x7) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->fifoStartChannelListCount = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->fifoStartChannelListCount - - - for (NvU64 i = 0; i < (8); ++i) - { - // Deserialize 4-byte NvHandle object. - dst->channelHandle[i] = (NvHandle) finn_read_buffer(bp, 4 * 8); - // No range check for dst->channelHandle[i] - } - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - // Caller must set up the pointers when deserializing down. - if (!deser_up) - { - // Data-presence indicator should be false if empty. - // Check for integer overflow in the element size variable. - if ((dst->fifoStartChannelListCount) < 1 || - (sizeof(NV0080_CTRL_FIFO_CHANNEL) * (dst->fifoStartChannelListCount)) < sizeof(NV0080_CTRL_FIFO_CHANNEL)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - dst->fifoStartChannelList = FINN_MALLOC((sizeof(NV0080_CTRL_FIFO_CHANNEL) * (dst->fifoStartChannelListCount))); - if (!dst->fifoStartChannelList) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->fifoStartChannelList, (sizeof(NV0080_CTRL_FIFO_CHANNEL) * (dst->fifoStartChannelListCount))); - } - - // Otherwise the pointer must be provided. - else if (!dst->fifoStartChannelList) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - for (NvU64 i = 0; i < (dst->fifoStartChannelListCount); ++i) - { - // Deserialize each element. - status = Nv0080CtrlFifoChannelDeserialize(bp, &(((NV0080_CTRL_FIFO_CHANNEL *) (NvP64_VALUE(dst->fifoStartChannelList)))[i]), sizeof(NV0080_CTRL_FIFO_CHANNEL), deser_up); - if (status != NV_OK) - goto exit; - } - } - - // Data is not present; set to NULL. - else - { - if (!deser_up) - dst->fifoStartChannelList = NULL; - } - - -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlFifoGetChannellistParamsSerialize(const NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x7; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->numChannels - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->numChannels, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->pChannelHandleList), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->pChannelHandleList) - { - - // Serialize each 4-byte NvU32 element. - for (NvU64 j = 0; j < (src->numChannels); ++j) - { - if (finn_write_buffer(bp, ((NvU32 *) NvP64_VALUE(src->pChannelHandleList))[j], 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->pChannelHandleList) - FINN_FREE(NvP64_VALUE(src->pChannelHandleList)); - } - - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->pChannelList), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->pChannelList) - { - - // Serialize each 4-byte NvU32 element. - for (NvU64 j = 0; j < (src->numChannels); ++j) - { - if (finn_write_buffer(bp, ((NvU32 *) NvP64_VALUE(src->pChannelList))[j], 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->pChannelList) - FINN_FREE(NvP64_VALUE(src->pChannelList)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlFifoGetChannellistParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x7) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->numChannels = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->numChannels - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->pChannelHandleList = FINN_MALLOC((dst->numChannels) * 4); - if (!dst->pChannelHandleList) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->pChannelHandleList, (dst->numChannels) * 4); - } - - // Otherwise the pointer must be provided. - else if (!dst->pChannelHandleList) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 4-byte NvU32 element. - for (NvU64 j = 0; j < (dst->numChannels); ++j) - { - ((NvU32 *) NvP64_VALUE(dst->pChannelHandleList))[j] = (NvU32) finn_read_buffer(bp, 4 * 8); - } - } - else - { - if (!deser_up) - dst->pChannelHandleList = NULL; - } - - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->pChannelList = FINN_MALLOC((dst->numChannels) * 4); - if (!dst->pChannelList) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->pChannelList, (dst->numChannels) * 4); - } - - // Otherwise the pointer must be provided. - else if (!dst->pChannelList) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 4-byte NvU32 element. - for (NvU64 j = 0; j < (dst->numChannels); ++j) - { - ((NvU32 *) NvP64_VALUE(dst->pChannelList))[j] = (NvU32) finn_read_buffer(bp, 4 * 8); - } - } - else - { - if (!deser_up) - dst->pChannelList = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlGpuGetClasslistParamsSerialize(const NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x3; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->numClasses - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->numClasses, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->classList), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->classList) - { - - // Serialize each 4-byte NvU32 element. - for (NvU64 j = 0; j < (src->numClasses); ++j) - { - if (finn_write_buffer(bp, ((NvU32 *) NvP64_VALUE(src->classList))[j], 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->classList) - FINN_FREE(NvP64_VALUE(src->classList)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlGpuGetClasslistParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x3) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->numClasses = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->numClasses - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->classList = FINN_MALLOC((dst->numClasses) * 4); - if (!dst->classList) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->classList, (dst->numClasses) * 4); - } - - // Otherwise the pointer must be provided. - else if (!dst->classList) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 4-byte NvU32 element. - for (NvU64 j = 0; j < (dst->numClasses); ++j) - { - ((NvU32 *) NvP64_VALUE(dst->classList))[j] = (NvU32) finn_read_buffer(bp, 4 * 8); - } - } - else - { - if (!deser_up) - dst->classList = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlGrGetCapsParamsSerialize(const NV0080_CTRL_GR_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x3; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->capsTblSize - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->capsTblSize, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->capsTbl), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->capsTbl) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->capsTblSize); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->capsTbl))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->capsTbl) - FINN_FREE(NvP64_VALUE(src->capsTbl)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlGrGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_GR_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV0080_CTRL_GR_GET_CAPS_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x3) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->capsTblSize = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->capsTblSize - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->capsTbl = FINN_MALLOC((dst->capsTblSize)); - if (!dst->capsTbl) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->capsTbl, (dst->capsTblSize)); - } - - // Otherwise the pointer must be provided. - else if (!dst->capsTbl) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->capsTblSize); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->capsTbl))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->capsTbl = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlHostGetCapsParamsSerialize(const NV0080_CTRL_HOST_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x3; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - if (src->capsTblSize > NV0080_CTRL_HOST_CAPS_TBL_SIZE) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->capsTblSize, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->capsTbl), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->capsTbl) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->capsTblSize); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->capsTbl))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->capsTbl) - FINN_FREE(NvP64_VALUE(src->capsTbl)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlHostGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_HOST_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV0080_CTRL_HOST_GET_CAPS_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x3) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->capsTblSize = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->capsTblSize > NV0080_CTRL_HOST_CAPS_TBL_SIZE) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->capsTbl = FINN_MALLOC((dst->capsTblSize)); - if (!dst->capsTbl) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->capsTbl, (dst->capsTblSize)); - } - - // Otherwise the pointer must be provided. - else if (!dst->capsTbl) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->capsTblSize); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->capsTbl))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->capsTbl = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlMsencGetCapsParamsSerialize(const NV0080_CTRL_MSENC_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x3; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - if (src->capsTblSize > NV0080_CTRL_MSENC_CAPS_TBL_SIZE) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->capsTblSize, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->capsTbl), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->capsTbl) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->capsTblSize); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->capsTbl))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->capsTbl) - FINN_FREE(NvP64_VALUE(src->capsTbl)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv0080CtrlMsencGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV0080_CTRL_MSENC_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV0080_CTRL_MSENC_GET_CAPS_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x3) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->capsTblSize = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->capsTblSize > NV0080_CTRL_MSENC_CAPS_TBL_SIZE) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->capsTbl = FINN_MALLOC((dst->capsTblSize)); - if (!dst->capsTbl) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->capsTbl, (dst->capsTblSize)); - } - - // Otherwise the pointer must be provided. - else if (!dst->capsTbl) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->capsTblSize); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->capsTbl))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->capsTbl = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv2080CtrlCeGetCapsParamsSerialize(const NV2080_CTRL_CE_GET_CAPS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x7; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->ceEngineType - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->ceEngineType, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - if (src->capsTblSize > NV2080_CTRL_CE_CAPS_TBL_SIZE) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->capsTblSize, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->capsTbl), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->capsTbl) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->capsTblSize); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->capsTbl))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->capsTbl) - FINN_FREE(NvP64_VALUE(src->capsTbl)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv2080CtrlCeGetCapsParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_CE_GET_CAPS_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV2080_CTRL_CE_GET_CAPS_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x7) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->ceEngineType = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->ceEngineType - - - // Deserialize 4-byte NvU32 object. - dst->capsTblSize = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->capsTblSize > NV2080_CTRL_CE_CAPS_TBL_SIZE) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->capsTbl = FINN_MALLOC((dst->capsTblSize)); - if (!dst->capsTbl) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->capsTbl, (dst->capsTblSize)); - } - - // Otherwise the pointer must be provided. - else if (!dst->capsTbl) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->capsTblSize); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->capsTbl))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->capsTbl = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv2080CtrlGpuGetEnginesParamsSerialize(const NV2080_CTRL_GPU_GET_ENGINES_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x3; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->engineCount - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->engineCount, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->engineList), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->engineList) - { - - // Serialize each 4-byte NvU32 element. - for (NvU64 j = 0; j < (src->engineCount); ++j) - { - if (finn_write_buffer(bp, ((NvU32 *) NvP64_VALUE(src->engineList))[j], 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->engineList) - FINN_FREE(NvP64_VALUE(src->engineList)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv2080CtrlGpuGetEnginesParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_GPU_GET_ENGINES_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV2080_CTRL_GPU_GET_ENGINES_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x3) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->engineCount = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->engineCount - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->engineList = FINN_MALLOC((dst->engineCount) * 4); - if (!dst->engineList) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->engineList, (dst->engineCount) * 4); - } - - // Otherwise the pointer must be provided. - else if (!dst->engineList) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 4-byte NvU32 element. - for (NvU64 j = 0; j < (dst->engineCount); ++j) - { - ((NvU32 *) NvP64_VALUE(dst->engineList))[j] = (NvU32) finn_read_buffer(bp, 4 * 8); - } - } - else - { - if (!deser_up) - dst->engineList = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv2080CtrlGpuGetEngineClasslistParamsSerialize(const NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x7; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->engineType - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->engineType, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->numClasses - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->numClasses, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->classList), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->classList) - { - - // Serialize each 4-byte NvU32 element. - for (NvU64 j = 0; j < (src->numClasses); ++j) - { - if (finn_write_buffer(bp, ((NvU32 *) NvP64_VALUE(src->classList))[j], 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->classList) - FINN_FREE(NvP64_VALUE(src->classList)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv2080CtrlGpuGetEngineClasslistParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x7) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->engineType = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->engineType - - - // Deserialize 4-byte NvU32 object. - dst->numClasses = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->numClasses - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->classList = FINN_MALLOC((dst->numClasses) * 4); - if (!dst->classList) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->classList, (dst->numClasses) * 4); - } - - // Otherwise the pointer must be provided. - else if (!dst->classList) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 4-byte NvU32 element. - for (NvU64 j = 0; j < (dst->numClasses); ++j) - { - ((NvU32 *) NvP64_VALUE(dst->classList))[j] = (NvU32) finn_read_buffer(bp, 4 * 8); - } - } - else - { - if (!deser_up) - dst->classList = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv2080CtrlGpumonSamplesSerialize(const NV2080_CTRL_GPUMON_SAMPLES *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x1f; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->bufSize - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->bufSize, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->count - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->count, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->tracker - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->tracker, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->type - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->type, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->pSamples), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->pSamples) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->bufSize); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pSamples))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->pSamples) - FINN_FREE(NvP64_VALUE(src->pSamples)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv2080CtrlGpumonSamplesDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_GPUMON_SAMPLES *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV2080_CTRL_GPUMON_SAMPLES) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x1f) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->bufSize = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->bufSize - - - // Deserialize 4-byte NvU32 object. - dst->count = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->count - - - // Deserialize 4-byte NvU32 object. - dst->tracker = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->tracker - - - // Deserialize 1-byte NvU8 object. - dst->type = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->type - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->pSamples = FINN_MALLOC((dst->bufSize)); - if (!dst->pSamples) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->pSamples, (dst->bufSize)); - } - - // Otherwise the pointer must be provided. - else if (!dst->pSamples) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->bufSize); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->pSamples))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->pSamples = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv2080CtrlI2cAccessParamsSerialize(const NV2080_CTRL_I2C_ACCESS_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x1ff; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->token - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->token, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->cmd - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->cmd, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->port - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->port, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->flags - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->flags, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->status - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->status, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - if (src->dataBuffSize > NV2080_CTRL_I2C_MAX_ENTRIES) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->dataBuffSize, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->speed - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->speed, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->encrClientID - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->encrClientID, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->data), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->data) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->dataBuffSize); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->data))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->data) - FINN_FREE(NvP64_VALUE(src->data)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv2080CtrlI2cAccessParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_I2C_ACCESS_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV2080_CTRL_I2C_ACCESS_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x1ff) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->token = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->token - - - // Deserialize 4-byte NvU32 object. - dst->cmd = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->cmd - - - // Deserialize 4-byte NvU32 object. - dst->port = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->port - - - // Deserialize 4-byte NvU32 object. - dst->flags = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->flags - - - // Deserialize 4-byte NvU32 object. - dst->status = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->status - - - // Deserialize 4-byte NvU32 object. - dst->dataBuffSize = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->dataBuffSize > NV2080_CTRL_I2C_MAX_ENTRIES) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - - - // Deserialize 4-byte NvU32 object. - dst->speed = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->speed - - - // Deserialize 4-byte NvU32 object. - dst->encrClientID = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->encrClientID - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->data = FINN_MALLOC((dst->dataBuffSize)); - if (!dst->data) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->data, (dst->dataBuffSize)); - } - - // Otherwise the pointer must be provided. - else if (!dst->data) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->dataBuffSize); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->data))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->data = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv2080CtrlNvdGetDumpParamsSerialize(const NV2080_CTRL_NVD_GET_DUMP_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x7; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->component - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->component, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->size - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->size, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->pBuffer), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->pBuffer) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->size); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pBuffer))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->pBuffer) - FINN_FREE(NvP64_VALUE(src->pBuffer)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv2080CtrlNvdGetDumpParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_NVD_GET_DUMP_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV2080_CTRL_NVD_GET_DUMP_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x7) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->component = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->component - - - // Deserialize 4-byte NvU32 object. - dst->size = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->size - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->pBuffer = FINN_MALLOC((dst->size)); - if (!dst->pBuffer) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->pBuffer, (dst->size)); - } - - // Otherwise the pointer must be provided. - else if (!dst->pBuffer) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->size); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->pBuffer))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->pBuffer = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv2080CtrlRcReadVirtualMemParamsSerialize(const NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0xf; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->virtAddress - // Deserialize 8-byte NvU64 object. - if (finn_write_buffer(bp, src->virtAddress, 8 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->hChannel - // Deserialize 4-byte NvHandle object. - if (finn_write_buffer(bp, src->hChannel, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->bufferSize - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->bufferSize, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->bufferPtr), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->bufferPtr) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->bufferSize); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->bufferPtr))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->bufferPtr) - FINN_FREE(NvP64_VALUE(src->bufferPtr)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv2080CtrlRcReadVirtualMemParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0xf) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 8-byte NvU64 object. - dst->virtAddress = (NvU64) finn_read_buffer(bp, 8 * 8); - // No range check for dst->virtAddress - - - // Deserialize 4-byte NvHandle object. - dst->hChannel = (NvHandle) finn_read_buffer(bp, 4 * 8); - // No range check for dst->hChannel - - - // Deserialize 4-byte NvU32 object. - dst->bufferSize = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->bufferSize - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->bufferPtr = FINN_MALLOC((dst->bufferSize)); - if (!dst->bufferPtr) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->bufferPtr, (dst->bufferSize)); - } - - // Otherwise the pointer must be provided. - else if (!dst->bufferPtr) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->bufferSize); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->bufferPtr))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->bufferPtr = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cIndexedParamsSerialize(const NV402C_CTRL_I2C_INDEXED_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0xff; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->flags - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->flags, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - if (src->indexLength > NV402C_CTRL_I2C_INDEX_LENGTH_MAX) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->indexLength, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->messageLength - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->messageLength, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->address - // Deserialize 2-byte NvU16 object. - if (finn_write_buffer(bp, src->address, 2 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->portId - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->portId, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->bIsWrite - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->bIsWrite, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - for (NvU64 i = 0; i < (NV402C_CTRL_I2C_INDEX_LENGTH_MAX); ++i) - { - // No range check for src->index[i] - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->index[i], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->pMessage), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->pMessage) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->messageLength); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pMessage))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->pMessage) - FINN_FREE(NvP64_VALUE(src->pMessage)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cIndexedParamsDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_INDEXED_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV402C_CTRL_I2C_INDEXED_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0xff) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->flags = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->flags - - - // Deserialize 4-byte NvU32 object. - dst->indexLength = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->indexLength > NV402C_CTRL_I2C_INDEX_LENGTH_MAX) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - - - // Deserialize 4-byte NvU32 object. - dst->messageLength = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->messageLength - - - // Deserialize 2-byte NvU16 object. - dst->address = (NvU16) finn_read_buffer(bp, 2 * 8); - // No range check for dst->address - - - // Deserialize 1-byte NvU8 object. - dst->portId = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->portId - - - // Deserialize 1-byte NvU8 object. - dst->bIsWrite = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->bIsWrite - - - for (NvU64 i = 0; i < (NV402C_CTRL_I2C_INDEX_LENGTH_MAX); ++i) - { - // Deserialize 1-byte NvU8 object. - dst->index[i] = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->index[i] - } - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->pMessage = FINN_MALLOC((dst->messageLength)); - if (!dst->pMessage) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->pMessage, (dst->messageLength)); - } - - // Otherwise the pointer must be provided. - else if (!dst->pMessage) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->messageLength); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->pMessage))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->pMessage = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionTypeCheckEnum(NV402C_CTRL_I2C_TRANSACTION_TYPE id) -{ - switch (id) - { - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW: - case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BYTE_RW: - case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW: - case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW: - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW: - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW: - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW: - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_PROCESS_CALL: - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_PROCESS_CALL: - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW: - case NV402C_CTRL_I2C_TRANSACTION_TYPE_READ_EDID_DDC: - return NV_OK; // okay - } - - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - return NV_ERR_INVALID_ARGUMENT; -} -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusQuickRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x3; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->warFlags - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->warFlags, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->bWrite - // Deserialize 1-byte NvBool object. - if (finn_write_buffer(bp, src->bWrite, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusQuickRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x3) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->warFlags = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->warFlags - - - // Deserialize 1-byte NvBool object. - dst->bWrite = (NvBool) finn_read_buffer(bp, 1 * 8); - // No range check for dst->bWrite - - -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cByteRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x3; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->bWrite - // Deserialize 1-byte NvBool object. - if (finn_write_buffer(bp, src->bWrite, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->message - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->message, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cByteRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x3) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 1-byte NvBool object. - dst->bWrite = (NvBool) finn_read_buffer(bp, 1 * 8); - // No range check for dst->bWrite - - - // Deserialize 1-byte NvU8 object. - dst->message = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->message - - -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBlockRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x7; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->messageLength - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->messageLength, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->bWrite - // Deserialize 1-byte NvBool object. - if (finn_write_buffer(bp, src->bWrite, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->pMessage), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->pMessage) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->messageLength); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pMessage))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->pMessage) - FINN_FREE(NvP64_VALUE(src->pMessage)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBlockRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x7) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->messageLength = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->messageLength - - - // Deserialize 1-byte NvBool object. - dst->bWrite = (NvBool) finn_read_buffer(bp, 1 * 8); - // No range check for dst->bWrite - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->pMessage = FINN_MALLOC((dst->messageLength)); - if (!dst->pMessage) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->pMessage, (dst->messageLength)); - } - - // Otherwise the pointer must be provided. - else if (!dst->pMessage) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->messageLength); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->pMessage))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->pMessage = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusByteRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x7; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->bWrite - // Deserialize 1-byte NvBool object. - if (finn_write_buffer(bp, src->bWrite, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->registerAddress - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->registerAddress, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->message - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->message, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusByteRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x7) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 1-byte NvBool object. - dst->bWrite = (NvBool) finn_read_buffer(bp, 1 * 8); - // No range check for dst->bWrite - - - // Deserialize 1-byte NvU8 object. - dst->registerAddress = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->registerAddress - - - // Deserialize 1-byte NvU8 object. - dst->message = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->message - - -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusWordRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x7; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->message - // Deserialize 2-byte NvU16 object. - if (finn_write_buffer(bp, src->message, 2 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->bWrite - // Deserialize 1-byte NvBool object. - if (finn_write_buffer(bp, src->bWrite, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->registerAddress - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->registerAddress, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusWordRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x7) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 2-byte NvU16 object. - dst->message = (NvU16) finn_read_buffer(bp, 2 * 8); - // No range check for dst->message - - - // Deserialize 1-byte NvBool object. - dst->bWrite = (NvBool) finn_read_buffer(bp, 1 * 8); - // No range check for dst->bWrite - - - // Deserialize 1-byte NvU8 object. - dst->registerAddress = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->registerAddress - - -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBufferRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x1f; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->warFlags - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->warFlags, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->messageLength - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->messageLength, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->bWrite - // Deserialize 1-byte NvBool object. - if (finn_write_buffer(bp, src->bWrite, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->registerAddress - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->registerAddress, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->pMessage), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->pMessage) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->messageLength); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pMessage))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->pMessage) - FINN_FREE(NvP64_VALUE(src->pMessage)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBufferRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x1f) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->warFlags = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->warFlags - - - // Deserialize 4-byte NvU32 object. - dst->messageLength = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->messageLength - - - // Deserialize 1-byte NvBool object. - dst->bWrite = (NvBool) finn_read_buffer(bp, 1 * 8); - // No range check for dst->bWrite - - - // Deserialize 1-byte NvU8 object. - dst->registerAddress = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->registerAddress - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->pMessage = FINN_MALLOC((dst->messageLength)); - if (!dst->pMessage) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->pMessage, (dst->messageLength)); - } - - // Otherwise the pointer must be provided. - else if (!dst->pMessage) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->messageLength); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->pMessage))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->pMessage = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0xf; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->messageLength - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->messageLength, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->bWrite - // Deserialize 1-byte NvBool object. - if (finn_write_buffer(bp, src->bWrite, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->registerAddress - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->registerAddress, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->pMessage), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->pMessage) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->messageLength); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pMessage))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->pMessage) - FINN_FREE(NvP64_VALUE(src->pMessage)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0xf) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->messageLength = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->messageLength - - - // Deserialize 1-byte NvBool object. - dst->bWrite = (NvBool) finn_read_buffer(bp, 1 * 8); - // No range check for dst->bWrite - - - // Deserialize 1-byte NvU8 object. - dst->registerAddress = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->registerAddress - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->pMessage = FINN_MALLOC((dst->messageLength)); - if (!dst->pMessage) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->pMessage, (dst->messageLength)); - } - - // Otherwise the pointer must be provided. - else if (!dst->pMessage) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->messageLength); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->pMessage))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->pMessage = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusProcessCallSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x7; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->writeMessage - // Deserialize 2-byte NvU16 object. - if (finn_write_buffer(bp, src->writeMessage, 2 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->readMessage - // Deserialize 2-byte NvU16 object. - if (finn_write_buffer(bp, src->readMessage, 2 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->registerAddress - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->registerAddress, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusProcessCallDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x7) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 2-byte NvU16 object. - dst->writeMessage = (NvU16) finn_read_buffer(bp, 2 * 8); - // No range check for dst->writeMessage - - - // Deserialize 2-byte NvU16 object. - dst->readMessage = (NvU16) finn_read_buffer(bp, 2 * 8); - // No range check for dst->readMessage - - - // Deserialize 1-byte NvU8 object. - dst->registerAddress = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->registerAddress - - -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x1f; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - if (src->writeMessageLength > NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->writeMessageLength, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - if (src->readMessageLength > NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->readMessageLength, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->registerAddress - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->registerAddress, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - for (NvU64 i = 0; i < (NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX); ++i) - { - // No range check for src->writeMessage[i] - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->writeMessage[i], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - - for (NvU64 i = 0; i < (NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX); ++i) - { - // No range check for src->readMessage[i] - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->readMessage[i], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x1f) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->writeMessageLength = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->writeMessageLength > NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - - - // Deserialize 4-byte NvU32 object. - dst->readMessageLength = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->readMessageLength > NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - - - // Deserialize 1-byte NvU8 object. - dst->registerAddress = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->registerAddress - - - for (NvU64 i = 0; i < (NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX); ++i) - { - // Deserialize 1-byte NvU8 object. - dst->writeMessage[i] = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->writeMessage[i] - } - - - for (NvU64 i = 0; i < (NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX); ++i) - { - // Deserialize 1-byte NvU8 object. - dst->readMessage[i] = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->readMessage[i] - } - - -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x3f; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->warFlags - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->warFlags, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - if (src->indexLength > NV402C_CTRL_I2C_INDEX_LENGTH_MAX) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->indexLength, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->messageLength - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->messageLength, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->bWrite - // Deserialize 1-byte NvBool object. - if (finn_write_buffer(bp, src->bWrite, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - for (NvU64 i = 0; i < (NV402C_CTRL_I2C_INDEX_LENGTH_MAX); ++i) - { - // No range check for src->index[i] - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->index[i], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->pMessage), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->pMessage) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->messageLength); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pMessage))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->pMessage) - FINN_FREE(NvP64_VALUE(src->pMessage)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x3f) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->warFlags = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->warFlags - - - // Deserialize 4-byte NvU32 object. - dst->indexLength = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->indexLength > NV402C_CTRL_I2C_INDEX_LENGTH_MAX) - { - status = NV_ERR_OUT_OF_RANGE; - FINN_ERROR(NV_ERR_OUT_OF_RANGE); - goto exit; - } - - - - // Deserialize 4-byte NvU32 object. - dst->messageLength = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->messageLength - - - // Deserialize 1-byte NvBool object. - dst->bWrite = (NvBool) finn_read_buffer(bp, 1 * 8); - // No range check for dst->bWrite - - - for (NvU64 i = 0; i < (NV402C_CTRL_I2C_INDEX_LENGTH_MAX); ++i) - { - // Deserialize 1-byte NvU8 object. - dst->index[i] = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->index[i] - } - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->pMessage = FINN_MALLOC((dst->messageLength)); - if (!dst->pMessage) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->pMessage, (dst->messageLength)); - } - - // Otherwise the pointer must be provided. - else if (!dst->pMessage) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->messageLength); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->pMessage))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->pMessage = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataReadEdidDdcSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0xf; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->messageLength - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->messageLength, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->segmentNumber - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->segmentNumber, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->registerAddress - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->registerAddress, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->pMessage), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->pMessage) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->messageLength); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pMessage))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->pMessage) - FINN_FREE(NvP64_VALUE(src->pMessage)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataReadEdidDdcDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0xf) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->messageLength = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->messageLength - - - // Deserialize 1-byte NvU8 object. - dst->segmentNumber = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->segmentNumber - - - // Deserialize 1-byte NvU8 object. - dst->registerAddress = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->registerAddress - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->pMessage = FINN_MALLOC((dst->messageLength)); - if (!dst->pMessage) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->pMessage, (dst->messageLength)); - } - - // Otherwise the pointer must be provided. - else if (!dst->pMessage) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->messageLength); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->pMessage))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->pMessage = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataSerialize(const NV402C_CTRL_I2C_TRANSACTION_DATA *src, finn_bit_pump_for_write *bp, NvBool seri_up, NV402C_CTRL_I2C_TRANSACTION_TYPE transType) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x7ff; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Field copying based on union selector - switch (transType) - { - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW: - { - status = Nv402cCtrlI2cTransactionDataSmbusQuickRwSerialize(&src->smbusQuickData, bp, seri_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BYTE_RW: - { - status = Nv402cCtrlI2cTransactionDataI2cByteRwSerialize(&src->i2cByteData, bp, seri_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW: - { - status = Nv402cCtrlI2cTransactionDataSmbusByteRwSerialize(&src->smbusByteData, bp, seri_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW: - { - status = Nv402cCtrlI2cTransactionDataSmbusWordRwSerialize(&src->smbusWordData, bp, seri_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_PROCESS_CALL: - { - status = Nv402cCtrlI2cTransactionDataSmbusProcessCallSerialize(&src->smbusProcessData, bp, seri_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_PROCESS_CALL: - { - status = Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallSerialize(&src->smbusBlockProcessData, bp, seri_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW: - { - status = Nv402cCtrlI2cTransactionDataI2cBlockRwSerialize(&src->i2cBlockData, bp, seri_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW: - { - status = Nv402cCtrlI2cTransactionDataI2cBufferRwSerialize(&src->i2cBufferData, bp, seri_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW: - { - status = Nv402cCtrlI2cTransactionDataSmbusBlockRwSerialize(&src->smbusBlockData, bp, seri_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW: - { - status = Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwSerialize(&src->smbusMultibyteRegisterData, bp, seri_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_READ_EDID_DDC: - { - status = Nv402cCtrlI2cTransactionDataReadEdidDdcSerialize(&src->edidData, bp, seri_up); - if (status != NV_OK) - goto exit; - - break; - } - default: - { - status = NV_ERR_INVALID_ARGUMENT; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionDataDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA *dst, NvLength dst_size, NvBool deser_up, NV402C_CTRL_I2C_TRANSACTION_TYPE transType) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x7ff) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Field copying based on union selector - switch (transType) - { - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW: - { - status = Nv402cCtrlI2cTransactionDataSmbusQuickRwDeserialize(bp, &dst->smbusQuickData, dst_size, deser_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BYTE_RW: - { - status = Nv402cCtrlI2cTransactionDataI2cByteRwDeserialize(bp, &dst->i2cByteData, dst_size, deser_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW: - { - status = Nv402cCtrlI2cTransactionDataSmbusByteRwDeserialize(bp, &dst->smbusByteData, dst_size, deser_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW: - { - status = Nv402cCtrlI2cTransactionDataSmbusWordRwDeserialize(bp, &dst->smbusWordData, dst_size, deser_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_PROCESS_CALL: - { - status = Nv402cCtrlI2cTransactionDataSmbusProcessCallDeserialize(bp, &dst->smbusProcessData, dst_size, deser_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_PROCESS_CALL: - { - status = Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallDeserialize(bp, &dst->smbusBlockProcessData, dst_size, deser_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW: - { - status = Nv402cCtrlI2cTransactionDataI2cBlockRwDeserialize(bp, &dst->i2cBlockData, dst_size, deser_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW: - { - status = Nv402cCtrlI2cTransactionDataI2cBufferRwDeserialize(bp, &dst->i2cBufferData, dst_size, deser_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW: - { - status = Nv402cCtrlI2cTransactionDataSmbusBlockRwDeserialize(bp, &dst->smbusBlockData, dst_size, deser_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW: - { - status = Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwDeserialize(bp, &dst->smbusMultibyteRegisterData, dst_size, deser_up); - if (status != NV_OK) - goto exit; - - break; - } - case NV402C_CTRL_I2C_TRANSACTION_TYPE_READ_EDID_DDC: - { - status = Nv402cCtrlI2cTransactionDataReadEdidDdcDeserialize(bp, &dst->edidData, dst_size, deser_up); - if (status != NV_OK) - goto exit; - - break; - } - default: - { - status = NV_ERR_INVALID_ARGUMENT; - FINN_ERROR(NV_ERR_INVALID_ARGUMENT); - goto exit; - } - } - -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionParamsSerialize(const NV402C_CTRL_I2C_TRANSACTION_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x1f; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->flags - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->flags, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->transType - status = Nv402cCtrlI2cTransactionTypeCheckEnum(src->transType); - if (status != NV_OK) - goto exit; - - // Deserialize 4-byte NV402C_CTRL_I2C_TRANSACTION_TYPE object. - if (finn_write_buffer(bp, src->transType, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->deviceAddress - // Deserialize 2-byte NvU16 object. - if (finn_write_buffer(bp, src->deviceAddress, 2 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->portId - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->portId, 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - status = Nv402cCtrlI2cTransactionDataSerialize(&src->transData, bp, seri_up, src->transType); - if (status != NV_OK) - goto exit; - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv402cCtrlI2cTransactionParamsDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV402C_CTRL_I2C_TRANSACTION_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x1f) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->flags = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->flags - - - // Deserialize 4-byte NV402C_CTRL_I2C_TRANSACTION_TYPE object. - dst->transType = (NV402C_CTRL_I2C_TRANSACTION_TYPE) finn_read_buffer(bp, 4 * 8); - // No range check for dst->transType - status = Nv402cCtrlI2cTransactionTypeCheckEnum(dst->transType); - if (status != NV_OK) - goto exit; - - - - // Deserialize 2-byte NvU16 object. - dst->deviceAddress = (NvU16) finn_read_buffer(bp, 2 * 8); - // No range check for dst->deviceAddress - - - // Deserialize 1-byte NvU8 object. - dst->portId = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->portId - - - // Unbounded fields - status = Nv402cCtrlI2cTransactionDataDeserialize(bp, &dst->transData, dst_size, deser_up, dst->transType); - if (status != NV_OK) - goto exit; - -exit: - return status; -} - - -static NV_STATUS Nv83deCtrlDebugReadMemoryParamsSerialize(const NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0xf; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->offset - // Deserialize 8-byte NvU64 object. - if (finn_write_buffer(bp, src->offset, 8 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->hMemory - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->hMemory, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->length - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->length, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->buffer), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->buffer) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->length); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->buffer))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->buffer) - FINN_FREE(NvP64_VALUE(src->buffer)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv83deCtrlDebugReadMemoryParamsDeserialize(finn_bit_pump_for_read *bp, NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0xf) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 8-byte NvU64 object. - dst->offset = (NvU64) finn_read_buffer(bp, 8 * 8); - // No range check for dst->offset - - - // Deserialize 4-byte NvU32 object. - dst->hMemory = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->hMemory - - - // Deserialize 4-byte NvU32 object. - dst->length = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->length - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->buffer = FINN_MALLOC((dst->length)); - if (!dst->buffer) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->buffer, (dst->length)); - } - - // Otherwise the pointer must be provided. - else if (!dst->buffer) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->length); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->buffer))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->buffer = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nv83deCtrlDebugWriteMemoryParamsSerialize(const NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0xf; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->offset - // Deserialize 8-byte NvU64 object. - if (finn_write_buffer(bp, src->offset, 8 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->hMemory - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->hMemory, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->length - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->length, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->buffer), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->buffer) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->length); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->buffer))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->buffer) - FINN_FREE(NvP64_VALUE(src->buffer)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nv83deCtrlDebugWriteMemoryParamsDeserialize(finn_bit_pump_for_read *bp, NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0xf) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 8-byte NvU64 object. - dst->offset = (NvU64) finn_read_buffer(bp, 8 * 8); - // No range check for dst->offset - - - // Deserialize 4-byte NvU32 object. - dst->hMemory = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->hMemory - - - // Deserialize 4-byte NvU32 object. - dst->length = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->length - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->buffer = FINN_MALLOC((dst->length)); - if (!dst->buffer) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->buffer, (dst->length)); - } - - // Otherwise the pointer must be provided. - else if (!dst->buffer) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->length); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->buffer))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->buffer = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nvb06fCtrlGetEngineCtxDataParamsSerialize(const NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x7; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->engineID - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->engineID, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->size - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->size, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // Unbounded fields - // Set data-presence indicator. - if (finn_write_buffer(bp, !!(src->pEngineCtxBuff), 1)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Skip if pointer is null. - if (src->pEngineCtxBuff) - { - - // Serialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (src->size); ++j) - { - if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pEngineCtxBuff))[j], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - // Free memory that was allocated during downward deserialization. - if (seri_up && src->pEngineCtxBuff) - FINN_FREE(NvP64_VALUE(src->pEngineCtxBuff)); - } - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nvb06fCtrlGetEngineCtxDataParamsDeserialize(finn_bit_pump_for_read *bp, NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x7) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->engineID = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->engineID - - - // Deserialize 4-byte NvU32 object. - dst->size = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->size - - - // Unbounded fields - // Skip if data is not present (null pointer). - if (finn_read_buffer(bp, 1)) - { - - // Allocate memory and set pointer when deserializing down. - // (Calling cods is expected to do so when deserializing up.) - if (!deser_up) - { - dst->pEngineCtxBuff = FINN_MALLOC((dst->size)); - if (!dst->pEngineCtxBuff) - { - status = NV_ERR_NO_MEMORY; - FINN_ERROR(NV_ERR_NO_MEMORY); - goto exit; - } - - FINN_MEMZERO(dst->pEngineCtxBuff, (dst->size)); - } - - // Otherwise the pointer must be provided. - else if (!dst->pEngineCtxBuff) - { - status = NV_ERR_INVALID_POINTER; - FINN_ERROR(NV_ERR_INVALID_POINTER); - goto exit; - } - - // Deserialize each 1-byte NvU8 element. - for (NvU64 j = 0; j < (dst->size); ++j) - { - ((NvU8 *) NvP64_VALUE(dst->pEngineCtxBuff))[j] = (NvU8) finn_read_buffer(bp, 1 * 8); - } - } - else - { - if (!deser_up) - dst->pEngineCtxBuff = NULL; - } - -exit: - return status; -} - - -static NV_STATUS Nvb06fCtrlCmdMigrateEngineCtxDataFinnParamsSerialize(const NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x1; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Unbounded fields - status = Nvb06fCtrlGetEngineCtxDataParamsSerialize(&src->params, bp, seri_up); - if (status != NV_OK) - goto exit; - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nvb06fCtrlCmdMigrateEngineCtxDataFinnParamsDeserialize(finn_bit_pump_for_read *bp, NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA_FINN_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x1) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Unbounded fields - status = Nvb06fCtrlGetEngineCtxDataParamsDeserialize(bp, &dst->params, dst_size, deser_up); - if (status != NV_OK) - goto exit; - -exit: - return status; -} - - -static NV_STATUS Nvb06fCtrlSaveEngineCtxDataParamsSerialize(const NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x7; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Statically sized fields - // No range check for src->engineID - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->engineID, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - // No range check for src->size - // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->size, 4 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - - for (NvU64 i = 0; i < (NVB06F_CTRL_ENGINE_CTX_BUFFER_SIZE_MAX); ++i) - { - // No range check for src->engineCtxBuff[i] - // Deserialize 1-byte NvU8 object. - if (finn_write_buffer(bp, src->engineCtxBuff[i], 1 * 8)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - } - - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nvb06fCtrlSaveEngineCtxDataParamsDeserialize(finn_bit_pump_for_read *bp, NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x7) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Statically sized fields - // Deserialize 4-byte NvU32 object. - dst->engineID = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->engineID - - - // Deserialize 4-byte NvU32 object. - dst->size = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->size - - - for (NvU64 i = 0; i < (NVB06F_CTRL_ENGINE_CTX_BUFFER_SIZE_MAX); ++i) - { - // Deserialize 1-byte NvU8 object. - dst->engineCtxBuff[i] = (NvU8) finn_read_buffer(bp, 1 * 8); - // No range check for dst->engineCtxBuff[i] - } - - -exit: - return status; -} - - -static NV_STATUS Nvb06fCtrlCmdRestoreEngineCtxDataFinnParamsSerialize(const NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up) -{ - // Local variables - NV_STATUS status = NV_OK; - uint64_t field_presence_mask; - - // Field bitmasks - field_presence_mask = 0x1; - - // Write field-presence indicators. - if (finn_write_buffer(bp, field_presence_mask, 64)) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Bounded nested fields - status = Nvb06fCtrlSaveEngineCtxDataParamsSerialize(&src->params, bp, seri_up); - if (status != NV_OK) - goto exit; - - goto exit; // Suppress potential not-used warning -exit: - return status; -} - - -static NV_STATUS Nvb06fCtrlCmdRestoreEngineCtxDataFinnParamsDeserialize(finn_bit_pump_for_read *bp, NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *dst, NvLength dst_size, NvBool deser_up) -{ - // Local variables - NV_STATUS status = NV_OK; - - // Check that the destination struct fits within the destination buffer - if (sizeof(NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS) > dst_size) - { - status = NV_ERR_BUFFER_TOO_SMALL; - FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); - goto exit; - } - - // Validate the field bitmasks, which must match the expected values for now. - if (finn_read_buffer(bp, 64) != 0x1) - { - status = NV_ERR_LIB_RM_VERSION_MISMATCH; - FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); - goto exit; - } - - // Bounded nested fields - status = Nvb06fCtrlSaveEngineCtxDataParamsDeserialize(bp, &dst->params, dst_size, deser_up); - if (status != NV_OK) - goto exit; - -exit: - return status; -} - - diff --git a/src/nvidia/interface/rmapi/src/g_finn_rm_api.c b/src/nvidia/interface/rmapi/src/g_finn_rm_api.c new file mode 100644 index 000000000..6d752d925 --- /dev/null +++ b/src/nvidia/interface/rmapi/src/g_finn_rm_api.c @@ -0,0 +1,8887 @@ +#include "g_finn_rm_api.h" +#include "ctrl/ctrl0000/ctrl0000nvd.h" +#include "ctrl/ctrl0080/ctrl0080dma.h" +#include "ctrl/ctrl0080/ctrl0080fb.h" +#include "ctrl/ctrl0080/ctrl0080fifo.h" +#include "ctrl/ctrl0080/ctrl0080gpu.h" +#include "ctrl/ctrl0080/ctrl0080gr.h" +#include "ctrl/ctrl0080/ctrl0080host.h" +#include "ctrl/ctrl0080/ctrl0080msenc.h" +#include "ctrl/ctrl2080/ctrl2080bios.h" +#include "ctrl/ctrl2080/ctrl2080ce.h" +#include "ctrl/ctrl2080/ctrl2080gpu.h" +#include "ctrl/ctrl2080/ctrl2080i2c.h" +#include "ctrl/ctrl2080/ctrl2080nvd.h" +#include "ctrl/ctrl2080/ctrl2080perf.h" +#include "ctrl/ctrl2080/ctrl2080rc.h" +#include "ctrl/ctrl2080/ctrl2080ucodefuzzer.h" +#include "ctrl/ctrl208f/ctrl208fgpu.h" +#include "ctrl/ctrl402c.h" +#include "ctrl/ctrl83de/ctrl83dedebug.h" +#include "ctrl/ctrlb06f.h" + +#if defined(NVRM) /* Kernel Mode */ +#include +#include +#include "nvport/nvport.h" +#elif defined(NV_LIBOS) /* LIBOS */ +#include +#include "nvport/nvport.h" +#else /* User Mode */ +#include +#include +#include +#include +#endif + + +// +// This file was generated with FINN, an NVIDIA coding tool. +// + +/* + * Serialization helper macros. These make field copying code more readable. + * Size is provided explicitly for cross-platform compatibility. + */ + +// Allocate memory. +#if defined(FINN_MALLOC) /* Use override from Makefile */ +#elif defined(NVRM) /* Kernel Mode */ +#define FINN_MALLOC(size) portMemAllocNonPaged(size) + +#elif defined(NV_LIBOS) /* LIBOS */ +#define FINN_MALLOC(size) portMemAllocNonPaged(size) + +#else /* User Mode */ +#define FINN_MALLOC(size) malloc(size) +#endif + +// Free allocated memory. +#if defined(FINN_FREE) /* Use override from Makefile */ +#elif defined(NVRM) /* Kernel Mode */ +#define FINN_FREE(buf) portMemFree(buf) + +#elif defined(NV_LIBOS) /* LIBOS */ +#define FINN_FREE(buf) portMemFree(buf) + +#else /* User Mode */ +#define FINN_FREE(buf) free(buf) +#endif + +// Set memory region to all zeroes. +#if defined(FINN_MEMZERO) /* Use override from Makefile */ +#elif defined(NVRM) /* Kernel Mode */ +#define FINN_MEMZERO(buf, size) portMemSet(buf, 0, size) + +#elif defined(NV_LIBOS) /* LIBOS */ +#define FINN_MEMZERO(buf, size) portMemSet(buf, 0, size) + +#else /* User Mode */ +#define FINN_MEMZERO(buf, size) memset(buf, 0, size) +#endif + +// Copy nonoverlapping memory region. +#if defined(FINN_MEMCPY) /* Use override from Makefile */ +#elif defined(NVRM) /* Kernel Mode */ +#define FINN_MEMCPY(dst, src, size) portMemCopy(dst, size, src, size) + +#elif defined(NV_LIBOS) /* LIBOS */ +#define FINN_MEMCPY(dst, src, size) portMemCopy(dst, size, src, size) + +#else /* User Mode */ +#define FINN_MEMCPY(dst, src, size) memcpy(dst, src, size) +#endif + +// Report an error. +#if defined(FINN_ERROR) /* Use override from Makefile */ +#elif defined(NVRM) /* Kernel Mode */ +#define FINN_ERROR(err) /* No-op */ + +#elif defined(NV_LIBOS) /* LIBOS */ +#define FINN_ERROR(err) /* No-op */ + +#else /* User Mode */ +#define FINN_ERROR(err) /* No-op */ +#endif + + + +// +// The purpose of the bit pump is to ensure 64-bit aligned access to the +// buffer while enabling arbitrary bits to be read/written. +// +typedef struct finn_bit_pump_for_read finn_bit_pump_for_read; + +struct finn_bit_pump_for_read +{ + uint64_t accumulator; // Bits not yet read from the data buffer + uint64_t checksum; // Checksum of data + const uint64_t *buffer_position; // Next word within data buffer to be read + const uint64_t *end_of_data; // End of data within buffer + uint8_t remaining_bit_count; // Number of bits remaining in the accumulator +}; + + +// +// Initialize bit pump for reading from the buffer. +// +// WARNING: The buffer start is assumed to be 64-bit aligned for optimal performance. +// `sod` (start of data) and `eod` (end of data) must be multiples of 64 bits +// since this logic is optimized for a 64-bit word size. Caller must check both +// `sod` and `eod`. +// +// `eod` points to the 64-bit word after the data (like most C++ `std` iterators). +// +static inline void finn_open_buffer_for_read(finn_bit_pump_for_read *bp, const uint64_t *sod, const uint64_t *eod) +{ + bp->accumulator = 0U; + bp->checksum = 0U; + bp->buffer_position = sod; + bp->end_of_data = eod; + bp->remaining_bit_count = 0U; +} + + +// +// Read the next several bits. +// +// `bit_size` must be in range of 0 to 64 inclusive; no check is made. +// When `bit_size` is zero, an unsupported use-case, it works as expected by +// returning zero without advancing the pointer. +// +static uint64_t finn_read_buffer(finn_bit_pump_for_read *bp, uint8_t bit_size) +{ + // Value to be deserialized and returned + uint64_t value; + + // Boundary crossing + // Accumulator does not have enough to satisfy the request, + if (bit_size > bp->remaining_bit_count) + { + // Number of bits not yet satisfied + bit_size -= bp->remaining_bit_count; + + // Shift the bits we have into place. + value = bp->accumulator; + + // Return zeroes for unsatisfied bits (if any) at end of data. + if (bp->buffer_position >= bp->end_of_data) + bp->accumulator = 0U; + + // Read the next word from the buffer. + else + bp->accumulator = *(bp->buffer_position++); + + // Update the checksum. + bp->checksum = ((bp->checksum << 1) ^ (bp->checksum & 1U)) ^ bp->accumulator; + + // + // This is the special case where we are reading an entire 64-bit word + // without crossing a boundary (when the accumulator is empty). The + // accumulator remains empty on exit. + // + // The bitwise operations in the normal flow do not work in this case. + // Shifts are not well-defined in C when the right operand exceeds the + // size of the left operand. Also, the right operand of the bitwise-and + // would exceed the 64-bit capacity. However, the needed logic is simple. + // + // 64 is the largest legal value for `bit_size`, so `>=` is equivalent to `==`. + // + if (bit_size >= 64) + { + // The value is the entire word. + value = bp->accumulator; + + // Discard the consumed data from the accumulator. + bp->accumulator = 0U; + + // Under the assumption that `bit_size` is never larger than 64, + // `bit_size == 64` implies `bp->remaining_bit_count == 0` because + // of the above `bit_size -= bp->remaining_bit_count`. As such, there + // is no need to do `bp->remaining_bit_count = 64U - bit_size`. + + // Done + return value; + } + + // OR in the bits since this was a boundary crossing. + // Shift it over by the number of bits we get from the prior word. + value |= (bp->accumulator + & (((uint64_t) 1U << bit_size) - 1U)) + << bp->remaining_bit_count; + + // Logic below subtracts off the bits consumed in the accumulator. + bp->remaining_bit_count = 64U; + } + + else + { + // The accumulator has enough to satisfy the request. + value = bp->accumulator & (((uint64_t) 1U << bit_size) - 1U); + } + + // Discard the consumed bits from the accumulator. + bp->accumulator >>= bit_size; + + // Keep track of the remaining available bits in the accumulator. + bp->remaining_bit_count -= bit_size; + + // Done + return value; +} + + +// Close the read buffer. +// Postcondition: `bp->checksum` is updated to end-of-data. +static inline void finn_close_buffer_for_read(finn_bit_pump_for_read *bp) +{ + // No need to update the bit pump buffer position, + // so use a local for optimal performance. + const uint64_t *p = bp->buffer_position; + + // Apply any unread words to the checksum. + while (p < bp->end_of_data) + bp->checksum = ((bp->checksum << 1U) ^ (bp->checksum & 1U)) ^ (*(p++)); +} + + +typedef struct finn_bit_pump_for_write finn_bit_pump_for_write; + +struct finn_bit_pump_for_write +{ + uint64_t accumulator; // Bits not yet written to the data buffer + uint64_t checksum; // Checksum of data + uint64_t *buffer_position; // Next word within the data buffer to be written + const uint64_t *end_of_buffer; // End of buffer (which may be after end of data) + uint8_t empty_bit_count; // Number of available bits in the accumulator +}; + + +// +// Initialize bit pump for writing to the buffer. +// +// In the general case for writing to the bit pump: +// +// WARNING: The buffer start is assumed to be 64-bit aligned for optimal performance. +// `sod` (start of data) and `eob` (end of buffer) must be multiples of 64 bits +// since this logic is optimized for a 64-bit word size. Caller must check both +// `sod` and `eod`. +// +// `eob` points to the 64-bit word after the buffer, an illegal access. +// +// +// Special case to get the serialized size without writing to the buffer: +// Both `sod` and `eob` are null. +// When closed, `bp->buffer_position` contains the byte count. +// +static inline void finn_open_buffer_for_write(finn_bit_pump_for_write *bp, uint64_t *sod, const uint64_t *eob) +{ + bp->accumulator = 0U; + bp->buffer_position = sod; + bp->end_of_buffer = eob; + bp->checksum = 0U; + bp->empty_bit_count = 64U; +} + +// +// Write several bits to the buffer. +// +// `bit_size` must be in range of 1 to 64 inclusive; no check is made. +// `value` must not have more 1 bits than specified by `bit_size`. +// In other words, bits that are left of `bit_size` must be 0s; no check is made. +// +// Return value is nonzero if the end of buffer is reached, an error. +// +// `bp->end_of_buffer` is null to disable writing to the buffer. +// +static int finn_write_buffer(finn_bit_pump_for_write *bp, uint64_t value, uint8_t bit_size) +{ + // Boundary crossing: Accumulator does not have enough to satisfy the request, + if (bit_size >= bp->empty_bit_count) + { + // Number of bits not yet satisfied + bit_size -= bp->empty_bit_count; + + // OR as many bits as will fit into the accumulator. + bp->accumulator |= value << (64U - bp->empty_bit_count); + + // Discard these bits by setting them to 0s. + // CAUTION: `value` may be unchanged when `bp->empty_bit_count` is 64 + // depending on the processor/ISA. + value >>= bp->empty_bit_count; + + // Write the word to the buffer unless writes are disabled. + if (bp->end_of_buffer) + { + *bp->buffer_position = bp->accumulator; + } + + // Advance to the next word in the buffer. + bp->buffer_position++; + + // Update the checksum. + bp->checksum = ((bp->checksum << 1) ^ (bp->checksum & 1U)) ^ bp->accumulator; + + // Re-initialize the accumulator and the bits filled. + bp->accumulator = 0U; + bp->empty_bit_count = 64U; + } + + // OR the data into the accumulator. + // When `bit_size` and `bp->empty_bit_count` are both 64 above, `bit_size` + // is assigned zero, but `value` may be unchanged. Check `bit_size` here so + // that stale `value` is not ORed into the accumulator again. + if (bit_size) + { + bp->accumulator |= (value << (64U - bp->empty_bit_count)); + } + + // Advance the bit count + bp->empty_bit_count -= bit_size; + + // Return nonzero on buffer overrun. + return bp->end_of_buffer && bp->buffer_position >= bp->end_of_buffer && bit_size; +} + + +// +// Close the write buffer and compute the checksum. +// +// Do NOT call this function if `finn_write_buffer` returned nonzero; no check is made. +// +// In the general case for writing to the bit pump: +// +// Postcondition: `bp->buffer_position` points to the word after the end of the data, +// which can be used to calculate the data size in 64-bit words by subtracting from +// `bp->end_of_buffer`. Buffer data at and after this point is set to zeroes. +// +// Special case to get the serialized size without writing to the buffer: +// Postcondition: ``bp->buffer_position` contains the byte count. +// +// All cases: +// Postcondition: `bp->checksum` contains the checksum of words written to the buffer. +// +static inline void finn_close_buffer_for_write(finn_bit_pump_for_write *bp) +{ + uint64_t *p; + + // The accumulator is not empty. + if (bp->empty_bit_count < 64U) + { + // Update the buffer with the last word. + if (bp->end_of_buffer) + { + *bp->buffer_position = bp->accumulator; + } + + // Advance to the next word to get an accurate word count. + bp->buffer_position++; + + // Update the checksum. + bp->checksum = ((bp->checksum << 1U) ^ (bp->checksum & 1U)) ^ bp->accumulator; + } + + // Zero out the rest of the buffer. + for (p = bp->buffer_position; p < bp->end_of_buffer; ++p) + { + *p = 0u; + } +} + + + + + +static NV_STATUS finnSerializeRoot_FINN_RM_API(NvU64 interface, NvU64 message, const char *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeRoot_FINN_RM_API(NvU64 interface, NvU64 message, finn_bit_pump_for_read *bp, char *api, NvLength dst_size, NvBool deser_up); +NvBool finnBadEnum_NV402C_CTRL_I2C_TRANSACTION_TYPE(NV402C_CTRL_I2C_TRANSACTION_TYPE value); +static NV_STATUS finnSerializeInterface_FINN_GT200_DEBUGGER_DEBUG(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_GT200_DEBUGGER_DEBUG(NvU64 message, finn_bit_pump_for_read *bp, FINN_GT200_DEBUGGER_DEBUG *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_GT200_DEBUGGER_DEBUG(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO(NvU64 message, finn_bit_pump_for_read *bp, FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_DMA(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_DMA(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_DMA *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_DMA(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_FB(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_FB(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_FB *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_FB(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_FIFO(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_FIFO(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_FIFO *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_FIFO(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_GPU(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_GPU(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_GPU *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_GPU(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_GR(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_GR(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_GR *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_GR(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_HOST(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_HOST(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_HOST *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_HOST(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_MSENC(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_MSENC(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_MSENC *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_MSENC(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV01_ROOT_NVD(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV01_ROOT_NVD(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_ROOT_NVD *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_ROOT_NVD(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_BIOS(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_BIOS(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_BIOS *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_BIOS(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_CE(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_CE(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_CE *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_CE(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_GPU(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_GPU(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_GPU *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_GPU(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_I2C(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_I2C(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_I2C *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_I2C(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_NVD(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_NVD(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_NVD *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_NVD(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_PERF(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_PERF(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_PERF *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_PERF(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_RC(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_RC(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_RC *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_RC(NvU64 message); + +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_DIAG_GPU(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_DIAG_GPU(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_DIAG_GPU *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_DIAG_GPU(NvU64 message); +static NV_STATUS finnSerializeInterface_FINN_NV40_I2C_I2C(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeInterface_FINN_NV40_I2C_I2C(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV40_I2C_I2C *api_intf, NvLength api_size, NvBool deser_up); +static NvU64 finnUnserializedInterfaceSize_FINN_NV40_I2C_I2C(NvU64 message); +static NV_STATUS finnSerializeMessage_NV0000_CTRL_NVD_GET_DUMP_PARAMS(const NV0000_CTRL_NVD_GET_DUMP_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV0000_CTRL_NVD_GET_DUMP_PARAMS(finn_bit_pump_for_read *bp, NV0000_CTRL_NVD_GET_DUMP_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS(const NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV0080_CTRL_FB_GET_CAPS_PARAMS(const NV0080_CTRL_FB_GET_CAPS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_FB_GET_CAPS_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_FB_GET_CAPS_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV0080_CTRL_FIFO_GET_CAPS_PARAMS(const NV0080_CTRL_FIFO_GET_CAPS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_FIFO_GET_CAPS_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_GET_CAPS_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS(const NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS(const NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS(const NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV0080_CTRL_GR_GET_CAPS_PARAMS(const NV0080_CTRL_GR_GET_CAPS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_GR_GET_CAPS_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_GR_GET_CAPS_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV0080_CTRL_HOST_GET_CAPS_PARAMS(const NV0080_CTRL_HOST_GET_CAPS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_HOST_GET_CAPS_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_HOST_GET_CAPS_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV0080_CTRL_MSENC_GET_CAPS_PARAMS(const NV0080_CTRL_MSENC_GET_CAPS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_MSENC_GET_CAPS_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_MSENC_GET_CAPS_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS(const NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS(finn_bit_pump_for_read *bp, NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV2080_CTRL_CE_GET_CAPS_PARAMS(const NV2080_CTRL_CE_GET_CAPS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV2080_CTRL_CE_GET_CAPS_PARAMS(finn_bit_pump_for_read *bp, NV2080_CTRL_CE_GET_CAPS_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV2080_CTRL_GPU_GET_ENGINES_PARAMS(const NV2080_CTRL_GPU_GET_ENGINES_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV2080_CTRL_GPU_GET_ENGINES_PARAMS(finn_bit_pump_for_read *bp, NV2080_CTRL_GPU_GET_ENGINES_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS(const NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS(finn_bit_pump_for_read *bp, NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV2080_CTRL_I2C_ACCESS_PARAMS(const NV2080_CTRL_I2C_ACCESS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV2080_CTRL_I2C_ACCESS_PARAMS(finn_bit_pump_for_read *bp, NV2080_CTRL_I2C_ACCESS_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV2080_CTRL_NVD_GET_DUMP_PARAMS(const NV2080_CTRL_NVD_GET_DUMP_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV2080_CTRL_NVD_GET_DUMP_PARAMS(finn_bit_pump_for_read *bp, NV2080_CTRL_NVD_GET_DUMP_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS(const NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS(finn_bit_pump_for_read *bp, NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *api, NvLength api_size, NvBool deser_up); + +static NV_STATUS finnSerializeMessage_NV402C_CTRL_I2C_INDEXED_PARAMS(const NV402C_CTRL_I2C_INDEXED_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV402C_CTRL_I2C_INDEXED_PARAMS(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_INDEXED_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV402C_CTRL_I2C_TRANSACTION_PARAMS(const NV402C_CTRL_I2C_TRANSACTION_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV402C_CTRL_I2C_TRANSACTION_PARAMS(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS(const NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS(finn_bit_pump_for_read *bp, NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS(const NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS(finn_bit_pump_for_read *bp, NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS(const NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS(finn_bit_pump_for_read *bp, NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS(const NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS(finn_bit_pump_for_read *bp, NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeMessage_NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS(const NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeMessage_NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS(finn_bit_pump_for_read *bp, NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeRecord_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS(const NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeRecord_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeRecord_NV0080_CTRL_FIFO_CHANNEL(const NV0080_CTRL_FIFO_CHANNEL *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeRecord_NV0080_CTRL_FIFO_CHANNEL(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_CHANNEL *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeRecord_NV2080_CTRL_GPUMON_SAMPLES(const NV2080_CTRL_GPUMON_SAMPLES *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeRecord_NV2080_CTRL_GPUMON_SAMPLES(finn_bit_pump_for_read *bp, NV2080_CTRL_GPUMON_SAMPLES *api, NvLength api_size, NvBool deser_up); + +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC(const NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW *api, NvLength api_size, NvBool deser_up); +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW *api, NvLength api_size, NvBool deser_up); + +static NV_STATUS finnSerializeUnion_NV402C_CTRL_I2C_TRANSACTION_DATA(const NV402C_CTRL_I2C_TRANSACTION_DATA *api, finn_bit_pump_for_write *bp, NvBool seri_up, NV402C_CTRL_I2C_TRANSACTION_TYPE transType); +static NV_STATUS finnDeserializeUnion_NV402C_CTRL_I2C_TRANSACTION_DATA(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA *api, NvLength dst_size, NvBool deser_up, NV402C_CTRL_I2C_TRANSACTION_TYPE transType); + +// Serialize this API. +NV_STATUS finnSerializeInternal_FINN_RM_API(NvU64 interface, NvU64 message, const char *api, char **dst, NvLength dst_size, NvBool seri_up) +{ + // Header + FINN_RM_API *header; + + // Buffer end + // `char` is the C-standrd unit of measure for `sizeof`. + const char *dst_end; + + // Bit pump is used to fill the buffer with serialized data. + finn_bit_pump_for_write bp; + + // Error code returned from serialization + NV_STATUS error_code; + + // Input validation + // Null pointers are not permitted. + // Buffer must begin on an 8-byte boundary. + if (!api || !dst || !(*dst) || !dst_size || (uintptr_t) dst & 0x7u) + { + FINN_ERROR(NV_ERR_INVALID_ARGUMENT); + return NV_ERR_INVALID_ARGUMENT; + } + + // Header is at the start of the buffer. + header = (FINN_RM_API *) *dst; + + // Buffer must end on an 8-byte boundary, so round down. + dst_end = (const char *) ((uintptr_t) (*dst + dst_size) & ~ (uintptr_t) 0x7); + + // Set header data. + header->version = FINN_SERIALIZATION_VERSION; + header->payloadSize = 0; // Zero until completed successfully + header->interface = interface; + header->message = message; + + // Advance past header. + (*dst) += sizeof(FINN_RM_API); + + // Open the bit pump. + finn_open_buffer_for_write(&bp, (uint64_t *) *dst, (const uint64_t *) dst_end); + + // Call the serializer. + error_code = finnSerializeRoot_FINN_RM_API(interface, message, api, &bp, seri_up); + + // Close the bit pump. + finn_close_buffer_for_write(&bp); + + // Payload size in bytes + if (error_code == NV_OK) + header->payloadSize = (NvU64) (((const char *) bp.buffer_position) - ((const char *) header)); + + // Indicate the ending location. + *dst = (char *) bp.buffer_position; + + // Done + return error_code; +} + +// Serialize this API to the bit pump. +static NV_STATUS finnSerializeRoot_FINN_RM_API(NvU64 interface, NvU64 message, const char *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize the specified interface. + switch (interface) + { + case FINN_INTERFACE_ID(FINN_NV01_ROOT_NVD): + return finnSerializeInterface_FINN_NV01_ROOT_NVD(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_DMA): + return finnSerializeInterface_FINN_NV01_DEVICE_0_DMA(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_FB): + return finnSerializeInterface_FINN_NV01_DEVICE_0_FB(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_FIFO): + return finnSerializeInterface_FINN_NV01_DEVICE_0_FIFO(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_GPU): + return finnSerializeInterface_FINN_NV01_DEVICE_0_GPU(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_GR): + return finnSerializeInterface_FINN_NV01_DEVICE_0_GR(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_HOST): + return finnSerializeInterface_FINN_NV01_DEVICE_0_HOST(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_MSENC): + return finnSerializeInterface_FINN_NV01_DEVICE_0_MSENC(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_BIOS): + return finnSerializeInterface_FINN_NV20_SUBDEVICE_0_BIOS(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_CE): + return finnSerializeInterface_FINN_NV20_SUBDEVICE_0_CE(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_GPU): + return finnSerializeInterface_FINN_NV20_SUBDEVICE_0_GPU(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_I2C): + return finnSerializeInterface_FINN_NV20_SUBDEVICE_0_I2C(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_NVD): + return finnSerializeInterface_FINN_NV20_SUBDEVICE_0_NVD(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_PERF): + return finnSerializeInterface_FINN_NV20_SUBDEVICE_0_PERF(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_RC): + return finnSerializeInterface_FINN_NV20_SUBDEVICE_0_RC(message, api, bp, seri_up); + + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_DIAG_GPU): + return finnSerializeInterface_FINN_NV20_SUBDEVICE_DIAG_GPU(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV40_I2C_I2C): + return finnSerializeInterface_FINN_NV40_I2C_I2C(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_GT200_DEBUGGER_DEBUG): + return finnSerializeInterface_FINN_GT200_DEBUGGER_DEBUG(message, api, bp, seri_up); + case FINN_INTERFACE_ID(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO): + return finnSerializeInterface_FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO(message, api, bp, seri_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} // end finnSerializeRoot_FINN_RM_API + + +// Deserialize this API. +NV_STATUS finnDeserializeInternal_FINN_RM_API(const char **src, NvLength src_size, char *api, NvLength api_size, NvBool deser_up) +{ + // Header + const FINN_RM_API *header; + + // End of data + const char *src_max; + + // Bit pump is used to read the serialized data. + finn_bit_pump_for_read bp; + + // Error code + NV_STATUS status; + + // Input validation + // Null pointers are not permitted. + // Buffer must begin on an 8-byte boundary. + if (!src || !(*src) || !src_size || !api || !api_size || (uintptr_t) *src & 0x7u) + { + FINN_ERROR(NV_ERR_INVALID_ARGUMENT); + return NV_ERR_INVALID_ARGUMENT; + } + + // Header data comes first. + header = (const FINN_RM_API *) *src; + + // Check the version. + if (header->version != FINN_SERIALIZATION_VERSION) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Set src_max for buffer bounds checking. + src_max = *src + src_size; + + // Check that source buffer is large enough. + if (sizeof(FINN_RM_API) > src_size || + header->payloadSize > src_size || + header->payloadSize < sizeof(FINN_RM_API)) + { + *src = (const char *) &header->payloadSize; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Open the bit punp, skipping past the header. + finn_open_buffer_for_read(&bp, (const uint64_t *) (*src + sizeof(FINN_RM_API)), (const uint64_t *) (src_max)); + + // Dispatch to interface-specific routine + status = finnDeserializeRoot_FINN_RM_API(header->interface, header->message, &bp, api, api_size, deser_up); + + // Update the buffer position, error or not. + *(src) = (const char *) bp.buffer_position; + + // Nothing more to do if there was an error. + if (status != NV_OK) + return status; + + // Update the checksum. + finn_close_buffer_for_read(&bp); + + // TODO: Check the checksum + + // Check that the declared size matches the serialization outcome. + if (header->payloadSize != (NvU64) (((const char *) bp.buffer_position) - ((const char *) header))) + { + FINN_ERROR(NV_ERR_INVALID_ARGUMENT); + return NV_ERR_INVALID_ARGUMENT; + } + + // All good + return NV_OK; +} + + +// Deserialize this API from the bit pump. +static NV_STATUS finnDeserializeRoot_FINN_RM_API(NvU64 interface, NvU64 message, finn_bit_pump_for_read *bp, char *api, NvLength api_size, NvBool deser_up) +{ + // Deserialize the specified interface. + switch (interface) + { + case FINN_INTERFACE_ID(FINN_NV01_ROOT_NVD): + return finnDeserializeInterface_FINN_NV01_ROOT_NVD(message, bp, (FINN_NV01_ROOT_NVD *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_DMA): + return finnDeserializeInterface_FINN_NV01_DEVICE_0_DMA(message, bp, (FINN_NV01_DEVICE_0_DMA *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_FB): + return finnDeserializeInterface_FINN_NV01_DEVICE_0_FB(message, bp, (FINN_NV01_DEVICE_0_FB *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_FIFO): + return finnDeserializeInterface_FINN_NV01_DEVICE_0_FIFO(message, bp, (FINN_NV01_DEVICE_0_FIFO *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_GPU): + return finnDeserializeInterface_FINN_NV01_DEVICE_0_GPU(message, bp, (FINN_NV01_DEVICE_0_GPU *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_GR): + return finnDeserializeInterface_FINN_NV01_DEVICE_0_GR(message, bp, (FINN_NV01_DEVICE_0_GR *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_HOST): + return finnDeserializeInterface_FINN_NV01_DEVICE_0_HOST(message, bp, (FINN_NV01_DEVICE_0_HOST *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_MSENC): + return finnDeserializeInterface_FINN_NV01_DEVICE_0_MSENC(message, bp, (FINN_NV01_DEVICE_0_MSENC *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_BIOS): + return finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_BIOS(message, bp, (FINN_NV20_SUBDEVICE_0_BIOS *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_CE): + return finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_CE(message, bp, (FINN_NV20_SUBDEVICE_0_CE *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_GPU): + return finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_GPU(message, bp, (FINN_NV20_SUBDEVICE_0_GPU *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_I2C): + return finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_I2C(message, bp, (FINN_NV20_SUBDEVICE_0_I2C *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_NVD): + return finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_NVD(message, bp, (FINN_NV20_SUBDEVICE_0_NVD *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_PERF): + return finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_PERF(message, bp, (FINN_NV20_SUBDEVICE_0_PERF *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_RC): + return finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_RC(message, bp, (FINN_NV20_SUBDEVICE_0_RC *) api, api_size, deser_up); + + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_DIAG_GPU): + return finnDeserializeInterface_FINN_NV20_SUBDEVICE_DIAG_GPU(message, bp, (FINN_NV20_SUBDEVICE_DIAG_GPU *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV40_I2C_I2C): + return finnDeserializeInterface_FINN_NV40_I2C_I2C(message, bp, (FINN_NV40_I2C_I2C *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_GT200_DEBUGGER_DEBUG): + return finnDeserializeInterface_FINN_GT200_DEBUGGER_DEBUG(message, bp, (FINN_GT200_DEBUGGER_DEBUG *) api, api_size, deser_up); + case FINN_INTERFACE_ID(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO): + return finnDeserializeInterface_FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO(message, bp, (FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO *) api, api_size, deser_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} // end finnDeserializeRoot_FINN_RM_API + + +// Size of the serialized format for this interface/message +NvU64 FinnRmApiGetSerializedSize(NvU64 interface, NvU64 message, const NvP64 src) +{ + // Bit pump with writing disabled. + finn_bit_pump_for_write bp; + finn_open_buffer_for_write(&bp, (uint64_t *) 0, (const uint64_t *) 0); + + // Call the serializer with write-suppressed bit pump. + // The size is the same in bith directions (up/down). + // Eeturn zero on error to indicate that this API is not serialized by FINN. + if (finnSerializeRoot_FINN_RM_API(interface, message, (const char *) NvP64_VALUE(src), &bp, 0) != NV_OK) + return 0; + + // Close the bit pump. + finn_close_buffer_for_write(&bp); + + // Add the header size in bytes to the amount of data serialzied. + // `buffer_position` is the payload size (not really the buffer position). + return (NvU64) NV_PTR_TO_NvP64(bp.buffer_position) + sizeof(FINN_RM_API); +} + + +// Size of the unserialized format for this interface/message +NvU64 FinnRmApiGetUnserializedSize(NvU64 interface, NvU64 message) +{ + // Forward to message-specific routine. + switch (interface) + { + case FINN_INTERFACE_ID(FINN_NV01_ROOT_NVD): + return finnUnserializedInterfaceSize_FINN_NV01_ROOT_NVD(message); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_DMA): + return finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_DMA(message); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_FB): + return finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_FB(message); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_FIFO): + return finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_FIFO(message); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_GPU): + return finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_GPU(message); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_GR): + return finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_GR(message); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_HOST): + return finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_HOST(message); + case FINN_INTERFACE_ID(FINN_NV01_DEVICE_0_MSENC): + return finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_MSENC(message); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_BIOS): + return finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_BIOS(message); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_CE): + return finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_CE(message); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_GPU): + return finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_GPU(message); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_I2C): + return finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_I2C(message); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_NVD): + return finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_NVD(message); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_PERF): + return finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_PERF(message); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_RC): + return finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_RC(message); + + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_DIAG_GPU): + return finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_DIAG_GPU(message); + case FINN_INTERFACE_ID(FINN_NV40_I2C_I2C): + return finnUnserializedInterfaceSize_FINN_NV40_I2C_I2C(message); + case FINN_INTERFACE_ID(FINN_GT200_DEBUGGER_DEBUG): + return finnUnserializedInterfaceSize_FINN_GT200_DEBUGGER_DEBUG(message); + case FINN_INTERFACE_ID(FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO): + return finnUnserializedInterfaceSize_FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO(message); + + // Zero indicates an unsupported interface (or message). + default: + return 0; + } +} // end FINN_RM_APIGetUnserializedSize +// Validate the enum value. +NvBool finnBadEnum_NV402C_CTRL_I2C_TRANSACTION_TYPE(NV402C_CTRL_I2C_TRANSACTION_TYPE value) +{ switch(value) + { + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW: + case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BYTE_RW: + case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW: + case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW: + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW: + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW: + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW: + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_PROCESS_CALL: + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_PROCESS_CALL: + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW: + case NV402C_CTRL_I2C_TRANSACTION_TYPE_READ_EDID_DDC: + return NV_FALSE; + + default: + return NV_TRUE; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_GT200_DEBUGGER_DEBUG(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 2 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS): + return finnSerializeMessage_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS((const NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *) api_intf, bp, seri_up); + case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS): + return finnSerializeMessage_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS((const NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *) api_intf, bp, seri_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_GT200_DEBUGGER_DEBUG(NvU64 message, finn_bit_pump_for_read *bp, FINN_GT200_DEBUGGER_DEBUG *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 2 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS): + return finnDeserializeMessage_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS(bp, (NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *) api_intf, api_size, deser_up); + case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS): + return finnDeserializeMessage_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS(bp, (NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *) api_intf, api_size, deser_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_GT200_DEBUGGER_DEBUG(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { + case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS): + return sizeof(NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS); + case FINN_MESSAGE_ID(NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS): + return sizeof(NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS); + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 3 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS): + return finnSerializeMessage_NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS((const NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *) api_intf, bp, seri_up); + case FINN_MESSAGE_ID(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS): + return finnSerializeMessage_NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS((const NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *) api_intf, bp, seri_up); + case FINN_MESSAGE_ID(NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS): + return finnSerializeMessage_NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS((const NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *) api_intf, bp, seri_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO(NvU64 message, finn_bit_pump_for_read *bp, FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 3 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS): + return finnDeserializeMessage_NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS(bp, (NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *) api_intf, api_size, deser_up); + case FINN_MESSAGE_ID(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS): + return finnDeserializeMessage_NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS(bp, (NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *) api_intf, api_size, deser_up); + case FINN_MESSAGE_ID(NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS): + return finnDeserializeMessage_NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS(bp, (NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *) api_intf, api_size, deser_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { + case FINN_MESSAGE_ID(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS): + return sizeof(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS); + case FINN_MESSAGE_ID(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS): + return sizeof(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS); + case FINN_MESSAGE_ID(NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS): + return sizeof(NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS); + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_DMA(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 1 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS): + return finnSerializeMessage_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS((const NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *) api_intf, bp, seri_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_DMA(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_DMA *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 1 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS): + return finnDeserializeMessage_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS(bp, (NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *) api_intf, api_size, deser_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_DMA(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { + case FINN_MESSAGE_ID(NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS): + return sizeof(NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS); + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_FB(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 1 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV0080_CTRL_FB_GET_CAPS_PARAMS): + return finnSerializeMessage_NV0080_CTRL_FB_GET_CAPS_PARAMS((const NV0080_CTRL_FB_GET_CAPS_PARAMS *) api_intf, bp, seri_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_FB(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_FB *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 1 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV0080_CTRL_FB_GET_CAPS_PARAMS): + return finnDeserializeMessage_NV0080_CTRL_FB_GET_CAPS_PARAMS(bp, (NV0080_CTRL_FB_GET_CAPS_PARAMS *) api_intf, api_size, deser_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_FB(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { + case FINN_MESSAGE_ID(NV0080_CTRL_FB_GET_CAPS_PARAMS): + return sizeof(NV0080_CTRL_FB_GET_CAPS_PARAMS); + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_FIFO(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 3 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CAPS_PARAMS): + return finnSerializeMessage_NV0080_CTRL_FIFO_GET_CAPS_PARAMS((const NV0080_CTRL_FIFO_GET_CAPS_PARAMS *) api_intf, bp, seri_up); + case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS): + return finnSerializeMessage_NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS((const NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *) api_intf, bp, seri_up); + case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS): + return finnSerializeMessage_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS((const NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *) api_intf, bp, seri_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_FIFO(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_FIFO *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 3 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CAPS_PARAMS): + return finnDeserializeMessage_NV0080_CTRL_FIFO_GET_CAPS_PARAMS(bp, (NV0080_CTRL_FIFO_GET_CAPS_PARAMS *) api_intf, api_size, deser_up); + case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS): + return finnDeserializeMessage_NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS(bp, (NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *) api_intf, api_size, deser_up); + case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS): + return finnDeserializeMessage_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS(bp, (NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *) api_intf, api_size, deser_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_FIFO(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { + case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CAPS_PARAMS): + return sizeof(NV0080_CTRL_FIFO_GET_CAPS_PARAMS); + case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS): + return sizeof(NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS); + case FINN_MESSAGE_ID(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS): + return sizeof(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS); + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_GPU(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 1 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS): + return finnSerializeMessage_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS((const NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *) api_intf, bp, seri_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_GPU(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_GPU *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 1 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS): + return finnDeserializeMessage_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS(bp, (NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *) api_intf, api_size, deser_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_GPU(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { + case FINN_MESSAGE_ID(NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS): + return sizeof(NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS); + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_GR(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 1 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV0080_CTRL_GR_GET_CAPS_PARAMS): + return finnSerializeMessage_NV0080_CTRL_GR_GET_CAPS_PARAMS((const NV0080_CTRL_GR_GET_CAPS_PARAMS *) api_intf, bp, seri_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_GR(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_GR *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 1 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV0080_CTRL_GR_GET_CAPS_PARAMS): + return finnDeserializeMessage_NV0080_CTRL_GR_GET_CAPS_PARAMS(bp, (NV0080_CTRL_GR_GET_CAPS_PARAMS *) api_intf, api_size, deser_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_GR(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { + case FINN_MESSAGE_ID(NV0080_CTRL_GR_GET_CAPS_PARAMS): + return sizeof(NV0080_CTRL_GR_GET_CAPS_PARAMS); + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_HOST(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 1 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV0080_CTRL_HOST_GET_CAPS_PARAMS): + return finnSerializeMessage_NV0080_CTRL_HOST_GET_CAPS_PARAMS((const NV0080_CTRL_HOST_GET_CAPS_PARAMS *) api_intf, bp, seri_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_HOST(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_HOST *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 1 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV0080_CTRL_HOST_GET_CAPS_PARAMS): + return finnDeserializeMessage_NV0080_CTRL_HOST_GET_CAPS_PARAMS(bp, (NV0080_CTRL_HOST_GET_CAPS_PARAMS *) api_intf, api_size, deser_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_HOST(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { + case FINN_MESSAGE_ID(NV0080_CTRL_HOST_GET_CAPS_PARAMS): + return sizeof(NV0080_CTRL_HOST_GET_CAPS_PARAMS); + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV01_DEVICE_0_MSENC(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 1 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV0080_CTRL_MSENC_GET_CAPS_PARAMS): + return finnSerializeMessage_NV0080_CTRL_MSENC_GET_CAPS_PARAMS((const NV0080_CTRL_MSENC_GET_CAPS_PARAMS *) api_intf, bp, seri_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV01_DEVICE_0_MSENC(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_DEVICE_0_MSENC *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 1 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV0080_CTRL_MSENC_GET_CAPS_PARAMS): + return finnDeserializeMessage_NV0080_CTRL_MSENC_GET_CAPS_PARAMS(bp, (NV0080_CTRL_MSENC_GET_CAPS_PARAMS *) api_intf, api_size, deser_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_DEVICE_0_MSENC(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { + case FINN_MESSAGE_ID(NV0080_CTRL_MSENC_GET_CAPS_PARAMS): + return sizeof(NV0080_CTRL_MSENC_GET_CAPS_PARAMS); + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV01_ROOT_NVD(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 1 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV0000_CTRL_NVD_GET_DUMP_PARAMS): + return finnSerializeMessage_NV0000_CTRL_NVD_GET_DUMP_PARAMS((const NV0000_CTRL_NVD_GET_DUMP_PARAMS *) api_intf, bp, seri_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV01_ROOT_NVD(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_ROOT_NVD *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 1 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV0000_CTRL_NVD_GET_DUMP_PARAMS): + return finnDeserializeMessage_NV0000_CTRL_NVD_GET_DUMP_PARAMS(bp, (NV0000_CTRL_NVD_GET_DUMP_PARAMS *) api_intf, api_size, deser_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV01_ROOT_NVD(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { + case FINN_MESSAGE_ID(NV0000_CTRL_NVD_GET_DUMP_PARAMS): + return sizeof(NV0000_CTRL_NVD_GET_DUMP_PARAMS); + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_BIOS(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 1 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS): + return finnSerializeMessage_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS((const NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS *) api_intf, bp, seri_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_BIOS(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_BIOS *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 1 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS): + return finnDeserializeMessage_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS(bp, (NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS *) api_intf, api_size, deser_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_BIOS(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { + case FINN_MESSAGE_ID(NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS): + return sizeof(NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS); + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_CE(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 1 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV2080_CTRL_CE_GET_CAPS_PARAMS): + return finnSerializeMessage_NV2080_CTRL_CE_GET_CAPS_PARAMS((const NV2080_CTRL_CE_GET_CAPS_PARAMS *) api_intf, bp, seri_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_CE(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_CE *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 1 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV2080_CTRL_CE_GET_CAPS_PARAMS): + return finnDeserializeMessage_NV2080_CTRL_CE_GET_CAPS_PARAMS(bp, (NV2080_CTRL_CE_GET_CAPS_PARAMS *) api_intf, api_size, deser_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_CE(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { + case FINN_MESSAGE_ID(NV2080_CTRL_CE_GET_CAPS_PARAMS): + return sizeof(NV2080_CTRL_CE_GET_CAPS_PARAMS); + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_GPU(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 2 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINES_PARAMS): + return finnSerializeMessage_NV2080_CTRL_GPU_GET_ENGINES_PARAMS((const NV2080_CTRL_GPU_GET_ENGINES_PARAMS *) api_intf, bp, seri_up); + case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS): + return finnSerializeMessage_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS((const NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *) api_intf, bp, seri_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_GPU(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_GPU *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 2 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINES_PARAMS): + return finnDeserializeMessage_NV2080_CTRL_GPU_GET_ENGINES_PARAMS(bp, (NV2080_CTRL_GPU_GET_ENGINES_PARAMS *) api_intf, api_size, deser_up); + case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS): + return finnDeserializeMessage_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS(bp, (NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *) api_intf, api_size, deser_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_GPU(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { + case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINES_PARAMS): + return sizeof(NV2080_CTRL_GPU_GET_ENGINES_PARAMS); + case FINN_MESSAGE_ID(NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS): + return sizeof(NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS); + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_I2C(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 1 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV2080_CTRL_I2C_ACCESS_PARAMS): + return finnSerializeMessage_NV2080_CTRL_I2C_ACCESS_PARAMS((const NV2080_CTRL_I2C_ACCESS_PARAMS *) api_intf, bp, seri_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_I2C(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_I2C *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 1 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV2080_CTRL_I2C_ACCESS_PARAMS): + return finnDeserializeMessage_NV2080_CTRL_I2C_ACCESS_PARAMS(bp, (NV2080_CTRL_I2C_ACCESS_PARAMS *) api_intf, api_size, deser_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_I2C(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { + case FINN_MESSAGE_ID(NV2080_CTRL_I2C_ACCESS_PARAMS): + return sizeof(NV2080_CTRL_I2C_ACCESS_PARAMS); + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_NVD(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 1 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV2080_CTRL_NVD_GET_DUMP_PARAMS): + return finnSerializeMessage_NV2080_CTRL_NVD_GET_DUMP_PARAMS((const NV2080_CTRL_NVD_GET_DUMP_PARAMS *) api_intf, bp, seri_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_NVD(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_NVD *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 1 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV2080_CTRL_NVD_GET_DUMP_PARAMS): + return finnDeserializeMessage_NV2080_CTRL_NVD_GET_DUMP_PARAMS(bp, (NV2080_CTRL_NVD_GET_DUMP_PARAMS *) api_intf, api_size, deser_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_NVD(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { + case FINN_MESSAGE_ID(NV2080_CTRL_NVD_GET_DUMP_PARAMS): + return sizeof(NV2080_CTRL_NVD_GET_DUMP_PARAMS); + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_PERF(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 1 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM): /* alias */ + return finnSerializeRecord_NV2080_CTRL_GPUMON_SAMPLES((const NV2080_CTRL_GPUMON_SAMPLES *) api_intf, bp, seri_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_PERF(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_PERF *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 1 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM): /* alias */ + return finnDeserializeRecord_NV2080_CTRL_GPUMON_SAMPLES(bp, (NV2080_CTRL_GPUMON_SAMPLES *) api_intf, api_size, deser_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_PERF(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { + case FINN_MESSAGE_ID(NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM): /* alias */ + return sizeof(NV2080_CTRL_GPUMON_SAMPLES); + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_0_RC(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 1 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS): + return finnSerializeMessage_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS((const NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *) api_intf, bp, seri_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_0_RC(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_RC *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 1 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS): + return finnDeserializeMessage_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS(bp, (NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *) api_intf, api_size, deser_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_0_RC(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { + case FINN_MESSAGE_ID(NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS): + return sizeof(NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS); + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV20_SUBDEVICE_DIAG_GPU(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 2 messages in this interface. + switch (message) + { + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV20_SUBDEVICE_DIAG_GPU(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_DIAG_GPU *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 2 messages in this interface. + switch (message) + { + + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV20_SUBDEVICE_DIAG_GPU(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { + + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + +// Serialize this interface. +static NV_STATUS finnSerializeInterface_FINN_NV40_I2C_I2C(NvU64 message, const char *api_intf, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize one of 2 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV402C_CTRL_I2C_INDEXED_PARAMS): + return finnSerializeMessage_NV402C_CTRL_I2C_INDEXED_PARAMS((const NV402C_CTRL_I2C_INDEXED_PARAMS *) api_intf, bp, seri_up); + case FINN_MESSAGE_ID(NV402C_CTRL_I2C_TRANSACTION_PARAMS): + return finnSerializeMessage_NV402C_CTRL_I2C_TRANSACTION_PARAMS((const NV402C_CTRL_I2C_TRANSACTION_PARAMS *) api_intf, bp, seri_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Deerialize this interface. +static NV_STATUS finnDeserializeInterface_FINN_NV40_I2C_I2C(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV40_I2C_I2C *api_intf, NvLength api_size, NvBool deser_up) +{ + // Deerialize one of 2 messages in this interface. + switch (message) + { + case FINN_MESSAGE_ID(NV402C_CTRL_I2C_INDEXED_PARAMS): + return finnDeserializeMessage_NV402C_CTRL_I2C_INDEXED_PARAMS(bp, (NV402C_CTRL_I2C_INDEXED_PARAMS *) api_intf, api_size, deser_up); + case FINN_MESSAGE_ID(NV402C_CTRL_I2C_TRANSACTION_PARAMS): + return finnDeserializeMessage_NV402C_CTRL_I2C_TRANSACTION_PARAMS(bp, (NV402C_CTRL_I2C_TRANSACTION_PARAMS *) api_intf, api_size, deser_up); + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + + +// Size of the unserialized format for this interface/message +static NvU64 finnUnserializedInterfaceSize_FINN_NV40_I2C_I2C(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { + case FINN_MESSAGE_ID(NV402C_CTRL_I2C_INDEXED_PARAMS): + return sizeof(NV402C_CTRL_I2C_INDEXED_PARAMS); + case FINN_MESSAGE_ID(NV402C_CTRL_I2C_TRANSACTION_PARAMS): + return sizeof(NV402C_CTRL_I2C_TRANSACTION_PARAMS); + + // Zero indicates an unsupported message (or interface). + default: + return 0; + } +} + + +// Serialize each of the 3 field(s). +// 2 out of 2 independent field(s) are reordered to be before 1 dependent field(s). +static NV_STATUS finnSerializeMessage_NV0000_CTRL_NVD_GET_DUMP_PARAMS(const NV0000_CTRL_NVD_GET_DUMP_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `component`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->component, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `size`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Reject source data if it is out of range. + if (api->size > NV0000_CTRL_NVD_MAX_DUMP_SIZE) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->size, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->pBuffer), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->pBuffer) + { + // Serialize each element in `pBuffer`. + { + NvLength i; + for (i = 0; i < (api->size); ++i) + { + // Serialize field-presence indicator for `pBuffer[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->pBuffer)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->pBuffer) + FINN_FREE(NvP64_VALUE(api->pBuffer)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 3 field(s). +// 2 out of 2 independent field(s) are reordered to be before 1 dependent field(s). +static NV_STATUS finnDeserializeMessage_NV0000_CTRL_NVD_GET_DUMP_PARAMS(finn_bit_pump_for_read *bp, NV0000_CTRL_NVD_GET_DUMP_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV0000_CTRL_NVD_GET_DUMP_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `component`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->component = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `size`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->size = (NvU32) finn_read_buffer(bp, 32); + + // Reject deserialized data if it is out of range. + if (api->size > NV0000_CTRL_NVD_MAX_DUMP_SIZE) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Check data-presence (nonnull pointer) indicator for `pBuffer`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->size) * (sizeof(NvU8) /*pBuffer[i]*/) /*pBuffer*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->pBuffer = NV_PTR_TO_NvP64(FINN_MALLOC((api->size) * (sizeof(NvU8) /*pBuffer[i]*/) /*pBuffer*/)); + if (!api->pBuffer) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->pBuffer), (api->size) * (sizeof(NvU8) /*pBuffer[i]*/) /*pBuffer*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->pBuffer) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `pBuffer`. + { + NvLength i; + for (i = 0; i < (api->size); ++i) + { + // Check field-presence indicator for `pBuffer[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->pBuffer)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->pBuffer = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 6 field(s). +// 2 out of 4 independent field(s) are reordered to be before 2 dependent field(s). +static NV_STATUS finnSerializeMessage_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS(const NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `pdeIndex`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->pdeIndex, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `flags`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->flags, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `hVASpace`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->hVASpace, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `subDeviceId`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->subDeviceId, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize each element in `ptParams`. + { + NvLength i; + for (i = 0; i < NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE; ++i) + { + // Serialize field-presence indicator for `ptParams[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Record has 3 field(s) to be serialized. + { + NV_STATUS status = finnSerializeRecord_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS((api->ptParams+(i)), bp, seri_up); + if (status != NV_OK) + return status; + } + + } + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->pPdeBuffer), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->pPdeBuffer) + { + // Serialize each element in `pPdeBuffer`. + { + NvLength i; + for (i = 0; i < 1; ++i) + { + // Serialize field-presence indicator for `pPdeBuffer[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 64-bit NvU64 primitive. + if (finn_write_buffer(bp, ((*(NvU64 (*) [1])(NvP64_VALUE(api->pPdeBuffer))))[i], 64)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->pPdeBuffer) + FINN_FREE(NvP64_VALUE(api->pPdeBuffer)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 6 field(s). +// 2 out of 4 independent field(s) are reordered to be before 2 dependent field(s). +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `pdeIndex`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->pdeIndex = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `flags`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->flags = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `hVASpace`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->hVASpace = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `subDeviceId`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->subDeviceId = (NvU32) finn_read_buffer(bp, 32); + + // Deserialize each element in `ptParams`. + { + NvLength i; + for (i = 0; i < NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE; ++i) + { + // Check field-presence indicator for `ptParams[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Record has 3 field(s) to be deserialized. + { + NV_STATUS status = finnDeserializeRecord_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS(bp, (api->ptParams+(i)), sizeof(NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS), deser_up); + if (status != NV_OK) + return status; + } + + } + } + + // Check data-presence (nonnull pointer) indicator for `pPdeBuffer`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if (1 * (sizeof(NvU64) /*pPdeBuffer[i]*/) /*pPdeBuffer*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->pPdeBuffer = NV_PTR_TO_NvP64(FINN_MALLOC(1 * (sizeof(NvU64) /*pPdeBuffer[i]*/) /*pPdeBuffer*/)); + if (!api->pPdeBuffer) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->pPdeBuffer), 1 * (sizeof(NvU64) /*pPdeBuffer[i]*/) /*pPdeBuffer*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->pPdeBuffer) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `pPdeBuffer`. + { + NvLength i; + for (i = 0; i < 1; ++i) + { + // Check field-presence indicator for `pPdeBuffer[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 64-bit NvU64 primitive. + ((*(NvU64 (*) [1])(NvP64_VALUE(api->pPdeBuffer))))[i] = (NvU64) finn_read_buffer(bp, 64); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->pPdeBuffer = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 2 field(s). +static NV_STATUS finnSerializeMessage_NV0080_CTRL_FB_GET_CAPS_PARAMS(const NV0080_CTRL_FB_GET_CAPS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `capsTblSize`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Reject source data if it is out of range. + if (api->capsTblSize > NV0080_CTRL_FB_CAPS_TBL_SIZE) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->capsTblSize, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->capsTbl), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->capsTbl) + { + // Serialize each element in `capsTbl`. + { + NvLength i; + for (i = 0; i < (api->capsTblSize); ++i) + { + // Serialize field-presence indicator for `capsTbl[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->capsTbl)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->capsTbl) + FINN_FREE(NvP64_VALUE(api->capsTbl)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 2 field(s). +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_FB_GET_CAPS_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_FB_GET_CAPS_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV0080_CTRL_FB_GET_CAPS_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `capsTblSize`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->capsTblSize = (NvU32) finn_read_buffer(bp, 32); + + // Reject deserialized data if it is out of range. + if (api->capsTblSize > NV0080_CTRL_FB_CAPS_TBL_SIZE) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Check data-presence (nonnull pointer) indicator for `capsTbl`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->capsTbl = NV_PTR_TO_NvP64(FINN_MALLOC((api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/)); + if (!api->capsTbl) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->capsTbl), (api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->capsTbl) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `capsTbl`. + { + NvLength i; + for (i = 0; i < (api->capsTblSize); ++i) + { + // Check field-presence indicator for `capsTbl[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->capsTbl)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->capsTbl = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 2 field(s). +static NV_STATUS finnSerializeMessage_NV0080_CTRL_FIFO_GET_CAPS_PARAMS(const NV0080_CTRL_FIFO_GET_CAPS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `capsTblSize`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Reject source data if it is out of range. + if (api->capsTblSize > NV0080_CTRL_FIFO_CAPS_TBL_SIZE) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->capsTblSize, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->capsTbl), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->capsTbl) + { + // Serialize each element in `capsTbl`. + { + NvLength i; + for (i = 0; i < (api->capsTblSize); ++i) + { + // Serialize field-presence indicator for `capsTbl[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->capsTbl)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->capsTbl) + FINN_FREE(NvP64_VALUE(api->capsTbl)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 2 field(s). +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_FIFO_GET_CAPS_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_GET_CAPS_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV0080_CTRL_FIFO_GET_CAPS_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `capsTblSize`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->capsTblSize = (NvU32) finn_read_buffer(bp, 32); + + // Reject deserialized data if it is out of range. + if (api->capsTblSize > NV0080_CTRL_FIFO_CAPS_TBL_SIZE) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Check data-presence (nonnull pointer) indicator for `capsTbl`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->capsTbl = NV_PTR_TO_NvP64(FINN_MALLOC((api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/)); + if (!api->capsTbl) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->capsTbl), (api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->capsTbl) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `capsTbl`. + { + NvLength i; + for (i = 0; i < (api->capsTblSize); ++i) + { + // Check field-presence indicator for `capsTbl[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->capsTbl)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->capsTbl = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 3 field(s). +static NV_STATUS finnSerializeMessage_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS(const NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `numChannels`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->numChannels, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->pChannelHandleList), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->pChannelHandleList) + { + // Serialize each element in `pChannelHandleList`. + { + NvLength i; + for (i = 0; i < (api->numChannels); ++i) + { + // Serialize field-presence indicator for `pChannelHandleList[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, ((NvU32 *)(NvP64_VALUE(api->pChannelHandleList)))[i], 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->pChannelHandleList) + FINN_FREE(NvP64_VALUE(api->pChannelHandleList)); + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->pChannelList), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->pChannelList) + { + // Serialize each element in `pChannelList`. + { + NvLength i; + for (i = 0; i < (api->numChannels); ++i) + { + // Serialize field-presence indicator for `pChannelList[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, ((NvU32 *)(NvP64_VALUE(api->pChannelList)))[i], 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->pChannelList) + FINN_FREE(NvP64_VALUE(api->pChannelList)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 3 field(s). +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `numChannels`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->numChannels = (NvU32) finn_read_buffer(bp, 32); + + // Check data-presence (nonnull pointer) indicator for `pChannelHandleList`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->numChannels) * (sizeof(NvU32) /*pChannelHandleList[i]*/) /*pChannelHandleList*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->pChannelHandleList = NV_PTR_TO_NvP64(FINN_MALLOC((api->numChannels) * (sizeof(NvU32) /*pChannelHandleList[i]*/) /*pChannelHandleList*/)); + if (!api->pChannelHandleList) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->pChannelHandleList), (api->numChannels) * (sizeof(NvU32) /*pChannelHandleList[i]*/) /*pChannelHandleList*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->pChannelHandleList) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `pChannelHandleList`. + { + NvLength i; + for (i = 0; i < (api->numChannels); ++i) + { + // Check field-presence indicator for `pChannelHandleList[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + ((NvU32 *)(NvP64_VALUE(api->pChannelHandleList)))[i] = (NvU32) finn_read_buffer(bp, 32); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->pChannelHandleList = NV_PTR_TO_NvP64(NULL); + } + + // Check data-presence (nonnull pointer) indicator for `pChannelList`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->numChannels) * (sizeof(NvU32) /*pChannelList[i]*/) /*pChannelList*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->pChannelList = NV_PTR_TO_NvP64(FINN_MALLOC((api->numChannels) * (sizeof(NvU32) /*pChannelList[i]*/) /*pChannelList*/)); + if (!api->pChannelList) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->pChannelList), (api->numChannels) * (sizeof(NvU32) /*pChannelList[i]*/) /*pChannelList*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->pChannelList) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `pChannelList`. + { + NvLength i; + for (i = 0; i < (api->numChannels); ++i) + { + // Check field-presence indicator for `pChannelList[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + ((NvU32 *)(NvP64_VALUE(api->pChannelList)))[i] = (NvU32) finn_read_buffer(bp, 32); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->pChannelList = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 3 field(s). +static NV_STATUS finnSerializeMessage_NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS(const NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `fifoStartChannelListCount`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->fifoStartChannelListCount, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize each element in `channelHandle`. + { + NvLength i; + for (i = 0; i < 8; ++i) + { + // Serialize field-presence indicator for `channelHandle[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, (api->channelHandle)[i], 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->fifoStartChannelList), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->fifoStartChannelList) + { + // Serialize each element in `fifoStartChannelList`. + { + NvLength i; + for (i = 0; i < (api->fifoStartChannelListCount); ++i) + { + // Serialize field-presence indicator for `fifoStartChannelList[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Record has 1 field(s) to be serialized. + { + NV_STATUS status = finnSerializeRecord_NV0080_CTRL_FIFO_CHANNEL(((NV0080_CTRL_FIFO_CHANNEL *)(NvP64_VALUE(api->fifoStartChannelList))+(i)), bp, seri_up); + if (status != NV_OK) + return status; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->fifoStartChannelList) + FINN_FREE(NvP64_VALUE(api->fifoStartChannelList)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 3 field(s). +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `fifoStartChannelListCount`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->fifoStartChannelListCount = (NvU32) finn_read_buffer(bp, 32); + + // Deserialize each element in `channelHandle`. + { + NvLength i; + for (i = 0; i < 8; ++i) + { + // Check field-presence indicator for `channelHandle[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + (api->channelHandle)[i] = (NvU32) finn_read_buffer(bp, 32); + + } + } + + // Check data-presence (nonnull pointer) indicator for `fifoStartChannelList`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->fifoStartChannelListCount) * (sizeof(NV0080_CTRL_FIFO_CHANNEL) /*fifoStartChannelList[i]*/) /*fifoStartChannelList*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->fifoStartChannelList = NV_PTR_TO_NvP64(FINN_MALLOC((api->fifoStartChannelListCount) * (sizeof(NV0080_CTRL_FIFO_CHANNEL) /*fifoStartChannelList[i]*/) /*fifoStartChannelList*/)); + if (!api->fifoStartChannelList) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->fifoStartChannelList), (api->fifoStartChannelListCount) * (sizeof(NV0080_CTRL_FIFO_CHANNEL) /*fifoStartChannelList[i]*/) /*fifoStartChannelList*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->fifoStartChannelList) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `fifoStartChannelList`. + { + NvLength i; + for (i = 0; i < (api->fifoStartChannelListCount); ++i) + { + // Check field-presence indicator for `fifoStartChannelList[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Record has 1 field(s) to be deserialized. + { + NV_STATUS status = finnDeserializeRecord_NV0080_CTRL_FIFO_CHANNEL(bp, ((NV0080_CTRL_FIFO_CHANNEL *)(NvP64_VALUE(api->fifoStartChannelList))+(i)), sizeof(NV0080_CTRL_FIFO_CHANNEL), deser_up); + if (status != NV_OK) + return status; + } + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->fifoStartChannelList = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 2 field(s). +static NV_STATUS finnSerializeMessage_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS(const NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `numClasses`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->numClasses, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->classList), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->classList) + { + // Serialize each element in `classList`. + { + NvLength i; + for (i = 0; i < (api->numClasses); ++i) + { + // Serialize field-presence indicator for `classList[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, ((NvU32 *)(NvP64_VALUE(api->classList)))[i], 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->classList) + FINN_FREE(NvP64_VALUE(api->classList)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 2 field(s). +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `numClasses`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->numClasses = (NvU32) finn_read_buffer(bp, 32); + + // Check data-presence (nonnull pointer) indicator for `classList`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->numClasses) * (sizeof(NvU32) /*classList[i]*/) /*classList*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->classList = NV_PTR_TO_NvP64(FINN_MALLOC((api->numClasses) * (sizeof(NvU32) /*classList[i]*/) /*classList*/)); + if (!api->classList) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->classList), (api->numClasses) * (sizeof(NvU32) /*classList[i]*/) /*classList*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->classList) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `classList`. + { + NvLength i; + for (i = 0; i < (api->numClasses); ++i) + { + // Check field-presence indicator for `classList[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + ((NvU32 *)(NvP64_VALUE(api->classList)))[i] = (NvU32) finn_read_buffer(bp, 32); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->classList = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 2 field(s). +static NV_STATUS finnSerializeMessage_NV0080_CTRL_GR_GET_CAPS_PARAMS(const NV0080_CTRL_GR_GET_CAPS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `capsTblSize`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->capsTblSize, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->capsTbl), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->capsTbl) + { + // Serialize each element in `capsTbl`. + { + NvLength i; + for (i = 0; i < (api->capsTblSize); ++i) + { + // Serialize field-presence indicator for `capsTbl[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->capsTbl)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->capsTbl) + FINN_FREE(NvP64_VALUE(api->capsTbl)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 2 field(s). +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_GR_GET_CAPS_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_GR_GET_CAPS_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV0080_CTRL_GR_GET_CAPS_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `capsTblSize`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->capsTblSize = (NvU32) finn_read_buffer(bp, 32); + + // Check data-presence (nonnull pointer) indicator for `capsTbl`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->capsTbl = NV_PTR_TO_NvP64(FINN_MALLOC((api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/)); + if (!api->capsTbl) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->capsTbl), (api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->capsTbl) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `capsTbl`. + { + NvLength i; + for (i = 0; i < (api->capsTblSize); ++i) + { + // Check field-presence indicator for `capsTbl[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->capsTbl)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->capsTbl = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 2 field(s). +static NV_STATUS finnSerializeMessage_NV0080_CTRL_HOST_GET_CAPS_PARAMS(const NV0080_CTRL_HOST_GET_CAPS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `capsTblSize`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Reject source data if it is out of range. + if (api->capsTblSize > NV0080_CTRL_HOST_CAPS_TBL_SIZE) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->capsTblSize, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->capsTbl), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->capsTbl) + { + // Serialize each element in `capsTbl`. + { + NvLength i; + for (i = 0; i < (api->capsTblSize); ++i) + { + // Serialize field-presence indicator for `capsTbl[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->capsTbl)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->capsTbl) + FINN_FREE(NvP64_VALUE(api->capsTbl)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 2 field(s). +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_HOST_GET_CAPS_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_HOST_GET_CAPS_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV0080_CTRL_HOST_GET_CAPS_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `capsTblSize`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->capsTblSize = (NvU32) finn_read_buffer(bp, 32); + + // Reject deserialized data if it is out of range. + if (api->capsTblSize > NV0080_CTRL_HOST_CAPS_TBL_SIZE) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Check data-presence (nonnull pointer) indicator for `capsTbl`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->capsTbl = NV_PTR_TO_NvP64(FINN_MALLOC((api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/)); + if (!api->capsTbl) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->capsTbl), (api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->capsTbl) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `capsTbl`. + { + NvLength i; + for (i = 0; i < (api->capsTblSize); ++i) + { + // Check field-presence indicator for `capsTbl[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->capsTbl)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->capsTbl = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 2 field(s). +static NV_STATUS finnSerializeMessage_NV0080_CTRL_MSENC_GET_CAPS_PARAMS(const NV0080_CTRL_MSENC_GET_CAPS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `capsTblSize`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Reject source data if it is out of range. + if (api->capsTblSize > NV0080_CTRL_MSENC_CAPS_TBL_SIZE) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->capsTblSize, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->capsTbl), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->capsTbl) + { + // Serialize each element in `capsTbl`. + { + NvLength i; + for (i = 0; i < (api->capsTblSize); ++i) + { + // Serialize field-presence indicator for `capsTbl[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->capsTbl)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->capsTbl) + FINN_FREE(NvP64_VALUE(api->capsTbl)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 2 field(s). +static NV_STATUS finnDeserializeMessage_NV0080_CTRL_MSENC_GET_CAPS_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_MSENC_GET_CAPS_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV0080_CTRL_MSENC_GET_CAPS_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `capsTblSize`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->capsTblSize = (NvU32) finn_read_buffer(bp, 32); + + // Reject deserialized data if it is out of range. + if (api->capsTblSize > NV0080_CTRL_MSENC_CAPS_TBL_SIZE) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Check data-presence (nonnull pointer) indicator for `capsTbl`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->capsTbl = NV_PTR_TO_NvP64(FINN_MALLOC((api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/)); + if (!api->capsTbl) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->capsTbl), (api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->capsTbl) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `capsTbl`. + { + NvLength i; + for (i = 0; i < (api->capsTblSize); ++i) + { + // Check field-presence indicator for `capsTbl[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->capsTbl)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->capsTbl = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 8 field(s). +// 3 out of 7 independent field(s) are reordered to be before 1 dependent field(s). +static NV_STATUS finnSerializeMessage_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS(const NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `globType`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 16-bit NvU16 primitive. + if (finn_write_buffer(bp, api->globType, 16)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `globIndex`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, api->globIndex, 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `globSource`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 16-bit NvU16 primitive. + if (finn_write_buffer(bp, api->globSource, 16)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `retBufOffset`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->retBufOffset, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `retSize`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->retSize, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `totalObjSize`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->totalObjSize, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `errorCode`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->errorCode, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->retBuf), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->retBuf) + { + // Serialize each element in `retBuf`. + { + NvLength i; + for (i = 0; i < (api->retSize); ++i) + { + // Serialize field-presence indicator for `retBuf[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->retBuf)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->retBuf) + FINN_FREE(NvP64_VALUE(api->retBuf)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 8 field(s). +// 3 out of 7 independent field(s) are reordered to be before 1 dependent field(s). +static NV_STATUS finnDeserializeMessage_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS(finn_bit_pump_for_read *bp, NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `globType`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 16-bit NvU16 primitive. + api->globType = (NvU16) finn_read_buffer(bp, 16); + + // Check field-presence indicator for `globIndex`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + api->globIndex = (NvU8) finn_read_buffer(bp, 8); + + // Check field-presence indicator for `globSource`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 16-bit NvU16 primitive. + api->globSource = (NvU16) finn_read_buffer(bp, 16); + + // Check field-presence indicator for `retBufOffset`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->retBufOffset = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `retSize`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->retSize = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `totalObjSize`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->totalObjSize = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `errorCode`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->errorCode = (NvU32) finn_read_buffer(bp, 32); + + // Check data-presence (nonnull pointer) indicator for `retBuf`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->retSize) * (sizeof(NvU8) /*retBuf[i]*/) /*retBuf*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->retBuf = NV_PTR_TO_NvP64(FINN_MALLOC((api->retSize) * (sizeof(NvU8) /*retBuf[i]*/) /*retBuf*/)); + if (!api->retBuf) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->retBuf), (api->retSize) * (sizeof(NvU8) /*retBuf[i]*/) /*retBuf*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->retBuf) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `retBuf`. + { + NvLength i; + for (i = 0; i < (api->retSize); ++i) + { + // Check field-presence indicator for `retBuf[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->retBuf)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->retBuf = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 3 field(s). +static NV_STATUS finnSerializeMessage_NV2080_CTRL_CE_GET_CAPS_PARAMS(const NV2080_CTRL_CE_GET_CAPS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `ceEngineType`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->ceEngineType, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `capsTblSize`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Reject source data if it is out of range. + if (api->capsTblSize > NV2080_CTRL_CE_CAPS_TBL_SIZE) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->capsTblSize, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->capsTbl), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->capsTbl) + { + // Serialize each element in `capsTbl`. + { + NvLength i; + for (i = 0; i < (api->capsTblSize); ++i) + { + // Serialize field-presence indicator for `capsTbl[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->capsTbl)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->capsTbl) + FINN_FREE(NvP64_VALUE(api->capsTbl)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 3 field(s). +static NV_STATUS finnDeserializeMessage_NV2080_CTRL_CE_GET_CAPS_PARAMS(finn_bit_pump_for_read *bp, NV2080_CTRL_CE_GET_CAPS_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV2080_CTRL_CE_GET_CAPS_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `ceEngineType`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->ceEngineType = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `capsTblSize`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->capsTblSize = (NvU32) finn_read_buffer(bp, 32); + + // Reject deserialized data if it is out of range. + if (api->capsTblSize > NV2080_CTRL_CE_CAPS_TBL_SIZE) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Check data-presence (nonnull pointer) indicator for `capsTbl`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->capsTbl = NV_PTR_TO_NvP64(FINN_MALLOC((api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/)); + if (!api->capsTbl) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->capsTbl), (api->capsTblSize) * (sizeof(NvU8) /*capsTbl[i]*/) /*capsTbl*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->capsTbl) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `capsTbl`. + { + NvLength i; + for (i = 0; i < (api->capsTblSize); ++i) + { + // Check field-presence indicator for `capsTbl[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->capsTbl)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->capsTbl = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 2 field(s). +static NV_STATUS finnSerializeMessage_NV2080_CTRL_GPU_GET_ENGINES_PARAMS(const NV2080_CTRL_GPU_GET_ENGINES_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `engineCount`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->engineCount, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->engineList), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->engineList) + { + // Serialize each element in `engineList`. + { + NvLength i; + for (i = 0; i < (api->engineCount); ++i) + { + // Serialize field-presence indicator for `engineList[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, ((NvU32 *)(NvP64_VALUE(api->engineList)))[i], 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->engineList) + FINN_FREE(NvP64_VALUE(api->engineList)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 2 field(s). +static NV_STATUS finnDeserializeMessage_NV2080_CTRL_GPU_GET_ENGINES_PARAMS(finn_bit_pump_for_read *bp, NV2080_CTRL_GPU_GET_ENGINES_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV2080_CTRL_GPU_GET_ENGINES_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `engineCount`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->engineCount = (NvU32) finn_read_buffer(bp, 32); + + // Check data-presence (nonnull pointer) indicator for `engineList`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->engineCount) * (sizeof(NvU32) /*engineList[i]*/) /*engineList*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->engineList = NV_PTR_TO_NvP64(FINN_MALLOC((api->engineCount) * (sizeof(NvU32) /*engineList[i]*/) /*engineList*/)); + if (!api->engineList) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->engineList), (api->engineCount) * (sizeof(NvU32) /*engineList[i]*/) /*engineList*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->engineList) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `engineList`. + { + NvLength i; + for (i = 0; i < (api->engineCount); ++i) + { + // Check field-presence indicator for `engineList[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + ((NvU32 *)(NvP64_VALUE(api->engineList)))[i] = (NvU32) finn_read_buffer(bp, 32); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->engineList = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 3 field(s). +static NV_STATUS finnSerializeMessage_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS(const NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `engineType`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->engineType, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `numClasses`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->numClasses, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->classList), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->classList) + { + // Serialize each element in `classList`. + { + NvLength i; + for (i = 0; i < (api->numClasses); ++i) + { + // Serialize field-presence indicator for `classList[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, ((NvU32 *)(NvP64_VALUE(api->classList)))[i], 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->classList) + FINN_FREE(NvP64_VALUE(api->classList)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 3 field(s). +static NV_STATUS finnDeserializeMessage_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS(finn_bit_pump_for_read *bp, NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `engineType`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->engineType = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `numClasses`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->numClasses = (NvU32) finn_read_buffer(bp, 32); + + // Check data-presence (nonnull pointer) indicator for `classList`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->numClasses) * (sizeof(NvU32) /*classList[i]*/) /*classList*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->classList = NV_PTR_TO_NvP64(FINN_MALLOC((api->numClasses) * (sizeof(NvU32) /*classList[i]*/) /*classList*/)); + if (!api->classList) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->classList), (api->numClasses) * (sizeof(NvU32) /*classList[i]*/) /*classList*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->classList) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `classList`. + { + NvLength i; + for (i = 0; i < (api->numClasses); ++i) + { + // Check field-presence indicator for `classList[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + ((NvU32 *)(NvP64_VALUE(api->classList)))[i] = (NvU32) finn_read_buffer(bp, 32); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->classList = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 9 field(s). +// 4 out of 8 independent field(s) are reordered to be before 1 dependent field(s). +static NV_STATUS finnSerializeMessage_NV2080_CTRL_I2C_ACCESS_PARAMS(const NV2080_CTRL_I2C_ACCESS_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `token`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->token, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `cmd`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->cmd, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `port`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->port, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `flags`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->flags, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `status`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->status, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `dataBuffSize`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Reject source data if it is out of range. + if (api->dataBuffSize > NV2080_CTRL_I2C_MAX_ENTRIES) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->dataBuffSize, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `speed`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->speed, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `encrClientID`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->encrClientID, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->data), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->data) + { + // Serialize each element in `data`. + { + NvLength i; + for (i = 0; i < (api->dataBuffSize); ++i) + { + // Serialize field-presence indicator for `data[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->data)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->data) + FINN_FREE(NvP64_VALUE(api->data)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 9 field(s). +// 4 out of 8 independent field(s) are reordered to be before 1 dependent field(s). +static NV_STATUS finnDeserializeMessage_NV2080_CTRL_I2C_ACCESS_PARAMS(finn_bit_pump_for_read *bp, NV2080_CTRL_I2C_ACCESS_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV2080_CTRL_I2C_ACCESS_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `token`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->token = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `cmd`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->cmd = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `port`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->port = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `flags`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->flags = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `status`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->status = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `dataBuffSize`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->dataBuffSize = (NvU32) finn_read_buffer(bp, 32); + + // Reject deserialized data if it is out of range. + if (api->dataBuffSize > NV2080_CTRL_I2C_MAX_ENTRIES) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Check field-presence indicator for `speed`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->speed = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `encrClientID`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->encrClientID = (NvU32) finn_read_buffer(bp, 32); + + // Check data-presence (nonnull pointer) indicator for `data`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->dataBuffSize) * (sizeof(NvU8) /*data[i]*/) /*data*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->data = NV_PTR_TO_NvP64(FINN_MALLOC((api->dataBuffSize) * (sizeof(NvU8) /*data[i]*/) /*data*/)); + if (!api->data) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->data), (api->dataBuffSize) * (sizeof(NvU8) /*data[i]*/) /*data*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->data) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `data`. + { + NvLength i; + for (i = 0; i < (api->dataBuffSize); ++i) + { + // Check field-presence indicator for `data[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->data)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->data = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 3 field(s). +// 2 out of 2 independent field(s) are reordered to be before 1 dependent field(s). +static NV_STATUS finnSerializeMessage_NV2080_CTRL_NVD_GET_DUMP_PARAMS(const NV2080_CTRL_NVD_GET_DUMP_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `component`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->component, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `size`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->size, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->pBuffer), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->pBuffer) + { + // Serialize each element in `pBuffer`. + { + NvLength i; + for (i = 0; i < (api->size); ++i) + { + // Serialize field-presence indicator for `pBuffer[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->pBuffer)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->pBuffer) + FINN_FREE(NvP64_VALUE(api->pBuffer)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 3 field(s). +// 2 out of 2 independent field(s) are reordered to be before 1 dependent field(s). +static NV_STATUS finnDeserializeMessage_NV2080_CTRL_NVD_GET_DUMP_PARAMS(finn_bit_pump_for_read *bp, NV2080_CTRL_NVD_GET_DUMP_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV2080_CTRL_NVD_GET_DUMP_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `component`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->component = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `size`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->size = (NvU32) finn_read_buffer(bp, 32); + + // Check data-presence (nonnull pointer) indicator for `pBuffer`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->size) * (sizeof(NvU8) /*pBuffer[i]*/) /*pBuffer*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->pBuffer = NV_PTR_TO_NvP64(FINN_MALLOC((api->size) * (sizeof(NvU8) /*pBuffer[i]*/) /*pBuffer*/)); + if (!api->pBuffer) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->pBuffer), (api->size) * (sizeof(NvU8) /*pBuffer[i]*/) /*pBuffer*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->pBuffer) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `pBuffer`. + { + NvLength i; + for (i = 0; i < (api->size); ++i) + { + // Check field-presence indicator for `pBuffer[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->pBuffer)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->pBuffer = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 4 field(s). +// 1 out of 3 independent field(s) are reordered to be before 1 dependent field(s). +static NV_STATUS finnSerializeMessage_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS(const NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `hChannel`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->hChannel, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `virtAddress`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 64-bit NvU64 primitive. + if (finn_write_buffer(bp, api->virtAddress, 64)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `bufferSize`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->bufferSize, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->bufferPtr), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->bufferPtr) + { + // Serialize each element in `bufferPtr`. + { + NvLength i; + for (i = 0; i < (api->bufferSize); ++i) + { + // Serialize field-presence indicator for `bufferPtr[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->bufferPtr)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->bufferPtr) + FINN_FREE(NvP64_VALUE(api->bufferPtr)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 4 field(s). +// 1 out of 3 independent field(s) are reordered to be before 1 dependent field(s). +static NV_STATUS finnDeserializeMessage_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS(finn_bit_pump_for_read *bp, NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `hChannel`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->hChannel = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `virtAddress`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 64-bit NvU64 primitive. + api->virtAddress = (NvU64) finn_read_buffer(bp, 64); + + // Check field-presence indicator for `bufferSize`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->bufferSize = (NvU32) finn_read_buffer(bp, 32); + + // Check data-presence (nonnull pointer) indicator for `bufferPtr`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->bufferSize) * (sizeof(NvU8) /*bufferPtr[i]*/) /*bufferPtr*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->bufferPtr = NV_PTR_TO_NvP64(FINN_MALLOC((api->bufferSize) * (sizeof(NvU8) /*bufferPtr[i]*/) /*bufferPtr*/)); + if (!api->bufferPtr) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->bufferPtr), (api->bufferSize) * (sizeof(NvU8) /*bufferPtr[i]*/) /*bufferPtr*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->bufferPtr) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `bufferPtr`. + { + NvLength i; + for (i = 0; i < (api->bufferSize); ++i) + { + // Check field-presence indicator for `bufferPtr[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->bufferPtr)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->bufferPtr = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 8 field(s). +// 1 out of 6 independent field(s) are reordered to be before 2 dependent field(s). +static NV_STATUS finnSerializeMessage_NV402C_CTRL_I2C_INDEXED_PARAMS(const NV402C_CTRL_I2C_INDEXED_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `portId`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, api->portId, 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `bIsWrite`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, api->bIsWrite, 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `address`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 16-bit NvU16 primitive. + if (finn_write_buffer(bp, api->address, 16)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `flags`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->flags, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `indexLength`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Reject source data if it is out of range. + if (api->indexLength > NV402C_CTRL_I2C_INDEX_LENGTH_MAX) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->indexLength, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `messageLength`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->messageLength, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize each element in `index`. + { + NvLength i; + for (i = 0; i < NV402C_CTRL_I2C_INDEX_LENGTH_MAX; ++i) + { + // Serialize field-presence indicator for `index[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, (api->index)[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->pMessage), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->pMessage) + { + // Serialize each element in `pMessage`. + { + NvLength i; + for (i = 0; i < (api->messageLength); ++i) + { + // Serialize field-presence indicator for `pMessage[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->pMessage)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->pMessage) + FINN_FREE(NvP64_VALUE(api->pMessage)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 8 field(s). +// 1 out of 6 independent field(s) are reordered to be before 2 dependent field(s). +static NV_STATUS finnDeserializeMessage_NV402C_CTRL_I2C_INDEXED_PARAMS(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_INDEXED_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV402C_CTRL_I2C_INDEXED_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `portId`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + api->portId = (NvU8) finn_read_buffer(bp, 8); + + // Check field-presence indicator for `bIsWrite`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + api->bIsWrite = (NvU8) finn_read_buffer(bp, 8); + + // Check field-presence indicator for `address`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 16-bit NvU16 primitive. + api->address = (NvU16) finn_read_buffer(bp, 16); + + // Check field-presence indicator for `flags`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->flags = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `indexLength`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->indexLength = (NvU32) finn_read_buffer(bp, 32); + + // Reject deserialized data if it is out of range. + if (api->indexLength > NV402C_CTRL_I2C_INDEX_LENGTH_MAX) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Check field-presence indicator for `messageLength`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->messageLength = (NvU32) finn_read_buffer(bp, 32); + + // Deserialize each element in `index`. + { + NvLength i; + for (i = 0; i < NV402C_CTRL_I2C_INDEX_LENGTH_MAX; ++i) + { + // Check field-presence indicator for `index[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + (api->index)[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + // Check data-presence (nonnull pointer) indicator for `pMessage`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->pMessage = NV_PTR_TO_NvP64(FINN_MALLOC((api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/)); + if (!api->pMessage) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->pMessage), (api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->pMessage) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `pMessage`. + { + NvLength i; + for (i = 0; i < (api->messageLength); ++i) + { + // Check field-presence indicator for `pMessage[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->pMessage)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->pMessage = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 5 field(s). +static NV_STATUS finnSerializeMessage_NV402C_CTRL_I2C_TRANSACTION_PARAMS(const NV402C_CTRL_I2C_TRANSACTION_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `portId`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, api->portId, 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `flags`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->flags, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `deviceAddress`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 16-bit NvU16 primitive. + if (finn_write_buffer(bp, api->deviceAddress, 16)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `transType`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Validate the enum value. + if (finnBadEnum_NV402C_CTRL_I2C_TRANSACTION_TYPE(api->transType)) + { + FINN_ERROR(NV_ERR_INVALID_ARGUMENT); + return NV_ERR_INVALID_ARGUMENT; + } + + // Serialize NV402C_CTRL_I2C_TRANSACTION_TYPE enum. + if (finn_write_buffer(bp, api->transType, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `transData`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // `transData` has 11 cases to serialize. + { + NV_STATUS status = finnSerializeUnion_NV402C_CTRL_I2C_TRANSACTION_DATA(&api->transData, bp, seri_up, api->transType); + if (status != NV_OK) + return status; + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 5 field(s). +static NV_STATUS finnDeserializeMessage_NV402C_CTRL_I2C_TRANSACTION_PARAMS(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `portId`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + api->portId = (NvU8) finn_read_buffer(bp, 8); + + // Check field-presence indicator for `flags`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->flags = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `deviceAddress`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 16-bit NvU16 primitive. + api->deviceAddress = (NvU16) finn_read_buffer(bp, 16); + + // Check field-presence indicator for `transType`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize NV402C_CTRL_I2C_TRANSACTION_TYPE enum. + api->transType = (NV402C_CTRL_I2C_TRANSACTION_TYPE) finn_read_buffer(bp, 32); + + // Validate the enum value. + if (finnBadEnum_NV402C_CTRL_I2C_TRANSACTION_TYPE(api->transType)) + { + FINN_ERROR(NV_ERR_INVALID_ARGUMENT); + return NV_ERR_INVALID_ARGUMENT; + } + + // Check field-presence indicator for `transData`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // `transData` has 11 cases to deserialize. + { + NV_STATUS status = finnDeserializeUnion_NV402C_CTRL_I2C_TRANSACTION_DATA(bp, &api->transData, api_size, deser_up, api->transType); + if (status != NV_OK) + return status; + } + + // Done + return NV_OK; +} + + +// Serialize each of the 4 field(s). +static NV_STATUS finnSerializeMessage_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS(const NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `hMemory`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->hMemory, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `length`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->length, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `offset`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 64-bit NvU64 primitive. + if (finn_write_buffer(bp, api->offset, 64)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->buffer), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->buffer) + { + // Serialize each element in `buffer`. + { + NvLength i; + for (i = 0; i < (api->length); ++i) + { + // Serialize field-presence indicator for `buffer[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->buffer)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->buffer) + FINN_FREE(NvP64_VALUE(api->buffer)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 4 field(s). +static NV_STATUS finnDeserializeMessage_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS(finn_bit_pump_for_read *bp, NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `hMemory`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->hMemory = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `length`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->length = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `offset`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 64-bit NvU64 primitive. + api->offset = (NvU64) finn_read_buffer(bp, 64); + + // Check data-presence (nonnull pointer) indicator for `buffer`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->length) * (sizeof(NvU8) /*buffer[i]*/) /*buffer*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->buffer = NV_PTR_TO_NvP64(FINN_MALLOC((api->length) * (sizeof(NvU8) /*buffer[i]*/) /*buffer*/)); + if (!api->buffer) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->buffer), (api->length) * (sizeof(NvU8) /*buffer[i]*/) /*buffer*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->buffer) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `buffer`. + { + NvLength i; + for (i = 0; i < (api->length); ++i) + { + // Check field-presence indicator for `buffer[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->buffer)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->buffer = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 4 field(s). +static NV_STATUS finnSerializeMessage_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS(const NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `hMemory`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->hMemory, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `length`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->length, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `offset`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 64-bit NvU64 primitive. + if (finn_write_buffer(bp, api->offset, 64)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->buffer), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->buffer) + { + // Serialize each element in `buffer`. + { + NvLength i; + for (i = 0; i < (api->length); ++i) + { + // Serialize field-presence indicator for `buffer[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->buffer)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->buffer) + FINN_FREE(NvP64_VALUE(api->buffer)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 4 field(s). +static NV_STATUS finnDeserializeMessage_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS(finn_bit_pump_for_read *bp, NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `hMemory`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->hMemory = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `length`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->length = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `offset`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 64-bit NvU64 primitive. + api->offset = (NvU64) finn_read_buffer(bp, 64); + + // Check data-presence (nonnull pointer) indicator for `buffer`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->length) * (sizeof(NvU8) /*buffer[i]*/) /*buffer*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->buffer = NV_PTR_TO_NvP64(FINN_MALLOC((api->length) * (sizeof(NvU8) /*buffer[i]*/) /*buffer*/)); + if (!api->buffer) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->buffer), (api->length) * (sizeof(NvU8) /*buffer[i]*/) /*buffer*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->buffer) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `buffer`. + { + NvLength i; + for (i = 0; i < (api->length); ++i) + { + // Check field-presence indicator for `buffer[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->buffer)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->buffer = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 1 field(s). +static NV_STATUS finnSerializeMessage_NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS(const NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `params`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Message has 3 field(s) to be serialized. + { + NV_STATUS status = finnSerializeMessage_NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS(&api->params, bp, seri_up); + if (status != NV_OK) + return status; + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 1 field(s). +static NV_STATUS finnDeserializeMessage_NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS(finn_bit_pump_for_read *bp, NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `params`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Message has 3 field(s) to be deserialized. + { + NV_STATUS status = finnDeserializeMessage_NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS(bp, &api->params, sizeof(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS), deser_up); + if (status != NV_OK) + return status; + } + + // Done + return NV_OK; +} + + +// Serialize each of the 3 field(s). +static NV_STATUS finnSerializeMessage_NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS(const NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `engineID`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->engineID, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `size`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->size, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->pEngineCtxBuff), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->pEngineCtxBuff) + { + // Serialize each element in `pEngineCtxBuff`. + { + NvLength i; + for (i = 0; i < (api->size); ++i) + { + // Serialize field-presence indicator for `pEngineCtxBuff[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->pEngineCtxBuff)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->pEngineCtxBuff) + FINN_FREE(NvP64_VALUE(api->pEngineCtxBuff)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 3 field(s). +static NV_STATUS finnDeserializeMessage_NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS(finn_bit_pump_for_read *bp, NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `engineID`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->engineID = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `size`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->size = (NvU32) finn_read_buffer(bp, 32); + + // Check data-presence (nonnull pointer) indicator for `pEngineCtxBuff`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->size) * (sizeof(NvU8) /*pEngineCtxBuff[i]*/) /*pEngineCtxBuff*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->pEngineCtxBuff = NV_PTR_TO_NvP64(FINN_MALLOC((api->size) * (sizeof(NvU8) /*pEngineCtxBuff[i]*/) /*pEngineCtxBuff*/)); + if (!api->pEngineCtxBuff) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->pEngineCtxBuff), (api->size) * (sizeof(NvU8) /*pEngineCtxBuff[i]*/) /*pEngineCtxBuff*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->pEngineCtxBuff) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `pEngineCtxBuff`. + { + NvLength i; + for (i = 0; i < (api->size); ++i) + { + // Check field-presence indicator for `pEngineCtxBuff[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->pEngineCtxBuff)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->pEngineCtxBuff = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 3 field(s). +static NV_STATUS finnSerializeMessage_NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS(const NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `engineID`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->engineID, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `size`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->size, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize each element in `engineCtxBuff`. + { + NvLength i; + for (i = 0; i < NVB06F_CTRL_ENGINE_CTX_BUFFER_SIZE_MAX; ++i) + { + // Serialize field-presence indicator for `engineCtxBuff[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, (api->engineCtxBuff)[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 3 field(s). +static NV_STATUS finnDeserializeMessage_NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS(finn_bit_pump_for_read *bp, NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NVB06F_CTRL_SAVE_ENGINE_CTX_DATA_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `engineID`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->engineID = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `size`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->size = (NvU32) finn_read_buffer(bp, 32); + + // Deserialize each element in `engineCtxBuff`. + { + NvLength i; + for (i = 0; i < NVB06F_CTRL_ENGINE_CTX_BUFFER_SIZE_MAX; ++i) + { + // Check field-presence indicator for `engineCtxBuff[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + (api->engineCtxBuff)[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + // Done + return NV_OK; +} + + +// Serialize each of the 3 field(s). +static NV_STATUS finnSerializeRecord_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS(const NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `physAddr`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 64-bit NvU64 primitive. + if (finn_write_buffer(bp, api->physAddr, 64)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `numEntries`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->numEntries, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `aperture`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->aperture, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 3 field(s). +static NV_STATUS finnDeserializeRecord_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS(finn_bit_pump_for_read *bp, NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `physAddr`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 64-bit NvU64 primitive. + api->physAddr = (NvU64) finn_read_buffer(bp, 64); + + // Check field-presence indicator for `numEntries`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->numEntries = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `aperture`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->aperture = (NvU32) finn_read_buffer(bp, 32); + + // Done + return NV_OK; +} + + +// Serialize each of the 1 field(s). +static NV_STATUS finnSerializeRecord_NV0080_CTRL_FIFO_CHANNEL(const NV0080_CTRL_FIFO_CHANNEL *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `hChannel`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->hChannel, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 1 field(s). +static NV_STATUS finnDeserializeRecord_NV0080_CTRL_FIFO_CHANNEL(finn_bit_pump_for_read *bp, NV0080_CTRL_FIFO_CHANNEL *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV0080_CTRL_FIFO_CHANNEL) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `hChannel`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->hChannel = (NvU32) finn_read_buffer(bp, 32); + + // Done + return NV_OK; +} + + +// Serialize each of the 5 field(s). +static NV_STATUS finnSerializeRecord_NV2080_CTRL_GPUMON_SAMPLES(const NV2080_CTRL_GPUMON_SAMPLES *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `type`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, api->type, 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `bufSize`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->bufSize, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `count`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->count, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `tracker`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->tracker, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->pSamples), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->pSamples) + { + // Serialize each element in `pSamples`. + { + NvLength i; + for (i = 0; i < (api->bufSize); ++i) + { + // Serialize field-presence indicator for `pSamples[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->pSamples)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->pSamples) + FINN_FREE(NvP64_VALUE(api->pSamples)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 5 field(s). +static NV_STATUS finnDeserializeRecord_NV2080_CTRL_GPUMON_SAMPLES(finn_bit_pump_for_read *bp, NV2080_CTRL_GPUMON_SAMPLES *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV2080_CTRL_GPUMON_SAMPLES) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `type`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + api->type = (NvU8) finn_read_buffer(bp, 8); + + // Check field-presence indicator for `bufSize`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->bufSize = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `count`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->count = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `tracker`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->tracker = (NvU32) finn_read_buffer(bp, 32); + + // Check data-presence (nonnull pointer) indicator for `pSamples`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->bufSize) * (sizeof(NvU8) /*pSamples[i]*/) /*pSamples*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->pSamples = NV_PTR_TO_NvP64(FINN_MALLOC((api->bufSize) * (sizeof(NvU8) /*pSamples[i]*/) /*pSamples*/)); + if (!api->pSamples) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->pSamples), (api->bufSize) * (sizeof(NvU8) /*pSamples[i]*/) /*pSamples*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->pSamples) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `pSamples`. + { + NvLength i; + for (i = 0; i < (api->bufSize); ++i) + { + // Check field-presence indicator for `pSamples[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->pSamples)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->pSamples = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 3 field(s). +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `bWrite`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 1-bit NvBool primitive. + if (finn_write_buffer(bp, api->bWrite, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `messageLength`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->messageLength, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->pMessage), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->pMessage) + { + // Serialize each element in `pMessage`. + { + NvLength i; + for (i = 0; i < (api->messageLength); ++i) + { + // Serialize field-presence indicator for `pMessage[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->pMessage)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->pMessage) + FINN_FREE(NvP64_VALUE(api->pMessage)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 3 field(s). +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `bWrite`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 1-bit NvBool primitive. + api->bWrite = (NvBool) finn_read_buffer(bp, 1); + + // Check field-presence indicator for `messageLength`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->messageLength = (NvU32) finn_read_buffer(bp, 32); + + // Check data-presence (nonnull pointer) indicator for `pMessage`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->pMessage = NV_PTR_TO_NvP64(FINN_MALLOC((api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/)); + if (!api->pMessage) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->pMessage), (api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->pMessage) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `pMessage`. + { + NvLength i; + for (i = 0; i < (api->messageLength); ++i) + { + // Check field-presence indicator for `pMessage[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->pMessage)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->pMessage = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 5 field(s). +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `bWrite`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 1-bit NvBool primitive. + if (finn_write_buffer(bp, api->bWrite, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `warFlags`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->warFlags, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `registerAddress`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, api->registerAddress, 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `messageLength`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->messageLength, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->pMessage), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->pMessage) + { + // Serialize each element in `pMessage`. + { + NvLength i; + for (i = 0; i < (api->messageLength); ++i) + { + // Serialize field-presence indicator for `pMessage[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->pMessage)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->pMessage) + FINN_FREE(NvP64_VALUE(api->pMessage)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 5 field(s). +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `bWrite`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 1-bit NvBool primitive. + api->bWrite = (NvBool) finn_read_buffer(bp, 1); + + // Check field-presence indicator for `warFlags`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->warFlags = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `registerAddress`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + api->registerAddress = (NvU8) finn_read_buffer(bp, 8); + + // Check field-presence indicator for `messageLength`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->messageLength = (NvU32) finn_read_buffer(bp, 32); + + // Check data-presence (nonnull pointer) indicator for `pMessage`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->pMessage = NV_PTR_TO_NvP64(FINN_MALLOC((api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/)); + if (!api->pMessage) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->pMessage), (api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->pMessage) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `pMessage`. + { + NvLength i; + for (i = 0; i < (api->messageLength); ++i) + { + // Check field-presence indicator for `pMessage[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->pMessage)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->pMessage = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 2 field(s). +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `bWrite`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 1-bit NvBool primitive. + if (finn_write_buffer(bp, api->bWrite, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `message`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, api->message, 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 2 field(s). +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `bWrite`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 1-bit NvBool primitive. + api->bWrite = (NvBool) finn_read_buffer(bp, 1); + + // Check field-presence indicator for `message`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + api->message = (NvU8) finn_read_buffer(bp, 8); + + // Done + return NV_OK; +} + + +// Serialize each of the 4 field(s). +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC(const NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `segmentNumber`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, api->segmentNumber, 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `registerAddress`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, api->registerAddress, 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `messageLength`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->messageLength, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->pMessage), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->pMessage) + { + // Serialize each element in `pMessage`. + { + NvLength i; + for (i = 0; i < (api->messageLength); ++i) + { + // Serialize field-presence indicator for `pMessage[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->pMessage)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->pMessage) + FINN_FREE(NvP64_VALUE(api->pMessage)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 4 field(s). +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `segmentNumber`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + api->segmentNumber = (NvU8) finn_read_buffer(bp, 8); + + // Check field-presence indicator for `registerAddress`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + api->registerAddress = (NvU8) finn_read_buffer(bp, 8); + + // Check field-presence indicator for `messageLength`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->messageLength = (NvU32) finn_read_buffer(bp, 32); + + // Check data-presence (nonnull pointer) indicator for `pMessage`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->pMessage = NV_PTR_TO_NvP64(FINN_MALLOC((api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/)); + if (!api->pMessage) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->pMessage), (api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->pMessage) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `pMessage`. + { + NvLength i; + for (i = 0; i < (api->messageLength); ++i) + { + // Check field-presence indicator for `pMessage[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->pMessage)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->pMessage = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 5 field(s). +// 1 out of 3 independent field(s) are reordered to be before 2 dependent field(s). +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `registerAddress`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, api->registerAddress, 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `writeMessageLength`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Reject source data if it is out of range. + if (api->writeMessageLength > NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->writeMessageLength, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `readMessageLength`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Reject source data if it is out of range. + if (api->readMessageLength > NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->readMessageLength, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize each element in `writeMessage`. + { + NvLength i; + for (i = 0; i < NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX; ++i) + { + // Serialize field-presence indicator for `writeMessage[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, (api->writeMessage)[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Serialize each element in `readMessage`. + { + NvLength i; + for (i = 0; i < NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX; ++i) + { + // Serialize field-presence indicator for `readMessage[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, (api->readMessage)[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 5 field(s). +// 1 out of 3 independent field(s) are reordered to be before 2 dependent field(s). +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `registerAddress`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + api->registerAddress = (NvU8) finn_read_buffer(bp, 8); + + // Check field-presence indicator for `writeMessageLength`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->writeMessageLength = (NvU32) finn_read_buffer(bp, 32); + + // Reject deserialized data if it is out of range. + if (api->writeMessageLength > NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Check field-presence indicator for `readMessageLength`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->readMessageLength = (NvU32) finn_read_buffer(bp, 32); + + // Reject deserialized data if it is out of range. + if (api->readMessageLength > NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Deserialize each element in `writeMessage`. + { + NvLength i; + for (i = 0; i < NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX; ++i) + { + // Check field-presence indicator for `writeMessage[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + (api->writeMessage)[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + // Deserialize each element in `readMessage`. + { + NvLength i; + for (i = 0; i < NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX; ++i) + { + // Check field-presence indicator for `readMessage[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + (api->readMessage)[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + // Done + return NV_OK; +} + + +// Serialize each of the 4 field(s). +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `bWrite`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 1-bit NvBool primitive. + if (finn_write_buffer(bp, api->bWrite, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `registerAddress`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, api->registerAddress, 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `messageLength`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->messageLength, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->pMessage), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->pMessage) + { + // Serialize each element in `pMessage`. + { + NvLength i; + for (i = 0; i < (api->messageLength); ++i) + { + // Serialize field-presence indicator for `pMessage[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->pMessage)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->pMessage) + FINN_FREE(NvP64_VALUE(api->pMessage)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 4 field(s). +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `bWrite`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 1-bit NvBool primitive. + api->bWrite = (NvBool) finn_read_buffer(bp, 1); + + // Check field-presence indicator for `registerAddress`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + api->registerAddress = (NvU8) finn_read_buffer(bp, 8); + + // Check field-presence indicator for `messageLength`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->messageLength = (NvU32) finn_read_buffer(bp, 32); + + // Check data-presence (nonnull pointer) indicator for `pMessage`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->pMessage = NV_PTR_TO_NvP64(FINN_MALLOC((api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/)); + if (!api->pMessage) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->pMessage), (api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->pMessage) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `pMessage`. + { + NvLength i; + for (i = 0; i < (api->messageLength); ++i) + { + // Check field-presence indicator for `pMessage[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->pMessage)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->pMessage = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 3 field(s). +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `bWrite`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 1-bit NvBool primitive. + if (finn_write_buffer(bp, api->bWrite, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `registerAddress`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, api->registerAddress, 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `message`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, api->message, 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 3 field(s). +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `bWrite`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 1-bit NvBool primitive. + api->bWrite = (NvBool) finn_read_buffer(bp, 1); + + // Check field-presence indicator for `registerAddress`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + api->registerAddress = (NvU8) finn_read_buffer(bp, 8); + + // Check field-presence indicator for `message`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + api->message = (NvU8) finn_read_buffer(bp, 8); + + // Done + return NV_OK; +} + + +// Serialize each of the 6 field(s). +// 1 out of 4 independent field(s) are reordered to be before 2 dependent field(s). +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `bWrite`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 1-bit NvBool primitive. + if (finn_write_buffer(bp, api->bWrite, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `warFlags`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->warFlags, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `indexLength`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Reject source data if it is out of range. + if (api->indexLength > NV402C_CTRL_I2C_INDEX_LENGTH_MAX) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->indexLength, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `messageLength`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->messageLength, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize each element in `index`. + { + NvLength i; + for (i = 0; i < NV402C_CTRL_I2C_INDEX_LENGTH_MAX; ++i) + { + // Serialize field-presence indicator for `index[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, (api->index)[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Serialize data-presence (nonnull pointer) indicator. + if (finn_write_buffer(bp, !!(api->pMessage), 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Skip if pointer is null. + if (api->pMessage) + { + // Serialize each element in `pMessage`. + { + NvLength i; + for (i = 0; i < (api->messageLength); ++i) + { + // Serialize field-presence indicator for `pMessage[i]`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, ((NvU8 *)(NvP64_VALUE(api->pMessage)))[i], 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + } + } + + // Free memory that was allocated during downward deserialization. + if (seri_up && api->pMessage) + FINN_FREE(NvP64_VALUE(api->pMessage)); + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 6 field(s). +// 1 out of 4 independent field(s) are reordered to be before 2 dependent field(s). +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `bWrite`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 1-bit NvBool primitive. + api->bWrite = (NvBool) finn_read_buffer(bp, 1); + + // Check field-presence indicator for `warFlags`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->warFlags = (NvU32) finn_read_buffer(bp, 32); + + // Check field-presence indicator for `indexLength`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->indexLength = (NvU32) finn_read_buffer(bp, 32); + + // Reject deserialized data if it is out of range. + if (api->indexLength > NV402C_CTRL_I2C_INDEX_LENGTH_MAX) + { + FINN_ERROR(NV_ERR_OUT_OF_RANGE); + return NV_ERR_OUT_OF_RANGE; + } + + // Check field-presence indicator for `messageLength`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->messageLength = (NvU32) finn_read_buffer(bp, 32); + + // Deserialize each element in `index`. + { + NvLength i; + for (i = 0; i < NV402C_CTRL_I2C_INDEX_LENGTH_MAX; ++i) + { + // Check field-presence indicator for `index[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + (api->index)[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + // Check data-presence (nonnull pointer) indicator for `pMessage`. + if (finn_read_buffer(bp, 1)) + { + // Allocate memory and set pointer when deserializing down. + // (Calling code is expected to do so when deserializing up.) + if (!deser_up) + { + // The data-presence indicator would have been false + // if there were no data to deserialize. + if ((api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/ < 1) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + api->pMessage = NV_PTR_TO_NvP64(FINN_MALLOC((api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/)); + if (!api->pMessage) + { + FINN_ERROR(NV_ERR_NO_MEMORY); + return NV_ERR_NO_MEMORY; + } + + FINN_MEMZERO(NvP64_VALUE(api->pMessage), (api->messageLength) * (sizeof(NvU8) /*pMessage[i]*/) /*pMessage*/); + } + + // Otherwise the pointer must be provided by caller. + else if (!api->pMessage) + { + FINN_ERROR(NV_ERR_INVALID_POINTER); + return NV_ERR_INVALID_POINTER; + } + + // Deserialize each element in `pMessage`. + { + NvLength i; + for (i = 0; i < (api->messageLength); ++i) + { + // Check field-presence indicator for `pMessage[i]`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + ((NvU8 *)(NvP64_VALUE(api->pMessage)))[i] = (NvU8) finn_read_buffer(bp, 8); + + } + } + + } + + // Nullify pointer only if FINN manages memory allocation. + else + { + if (!deser_up) + api->pMessage = NV_PTR_TO_NvP64(NULL); + } + + // Done + return NV_OK; +} + + +// Serialize each of the 3 field(s). +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `registerAddress`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, api->registerAddress, 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `writeMessage`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 16-bit NvU16 primitive. + if (finn_write_buffer(bp, api->writeMessage, 16)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `readMessage`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 16-bit NvU16 primitive. + if (finn_write_buffer(bp, api->readMessage, 16)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 3 field(s). +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `registerAddress`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + api->registerAddress = (NvU8) finn_read_buffer(bp, 8); + + // Check field-presence indicator for `writeMessage`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 16-bit NvU16 primitive. + api->writeMessage = (NvU16) finn_read_buffer(bp, 16); + + // Check field-presence indicator for `readMessage`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 16-bit NvU16 primitive. + api->readMessage = (NvU16) finn_read_buffer(bp, 16); + + // Done + return NV_OK; +} + + +// Serialize each of the 2 field(s). +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `bWrite`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 1-bit NvBool primitive. + if (finn_write_buffer(bp, api->bWrite, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `warFlags`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 32-bit NvU32 primitive. + if (finn_write_buffer(bp, api->warFlags, 32)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 2 field(s). +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `bWrite`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 1-bit NvBool primitive. + api->bWrite = (NvBool) finn_read_buffer(bp, 1); + + // Check field-presence indicator for `warFlags`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 32-bit NvU32 primitive. + api->warFlags = (NvU32) finn_read_buffer(bp, 32); + + // Done + return NV_OK; +} + + +// Serialize each of the 3 field(s). +static NV_STATUS finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW(const NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW *api, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Serialize field-presence indicator for `bWrite`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 1-bit NvBool primitive. + if (finn_write_buffer(bp, api->bWrite, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `registerAddress`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 8-bit NvU8 primitive. + if (finn_write_buffer(bp, api->registerAddress, 8)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize field-presence indicator for `message`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Serialize 16-bit NvU16 primitive. + if (finn_write_buffer(bp, api->message, 16)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + + // Done + return NV_OK; +} + + +// Deserialize each of the 3 field(s). +static NV_STATUS finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW *api, NvLength api_size, NvBool deser_up) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Check field-presence indicator for `bWrite`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 1-bit NvBool primitive. + api->bWrite = (NvBool) finn_read_buffer(bp, 1); + + // Check field-presence indicator for `registerAddress`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 8-bit NvU8 primitive. + api->registerAddress = (NvU8) finn_read_buffer(bp, 8); + + // Check field-presence indicator for `message`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Deserialize 16-bit NvU16 primitive. + api->message = (NvU16) finn_read_buffer(bp, 16); + + // Done + return NV_OK; +} + + +// Serialize selected field from 11 possible values. +static NV_STATUS finnSerializeUnion_NV402C_CTRL_I2C_TRANSACTION_DATA(const NV402C_CTRL_I2C_TRANSACTION_DATA *api, finn_bit_pump_for_write *bp, NvBool seri_up, NV402C_CTRL_I2C_TRANSACTION_TYPE transType) +{ + switch(transType) + { + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW: + { + // Serialize field-presence indicator for `api->smbusQuickData`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Record has 2 field(s) to be serialized. + { + NV_STATUS status = finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW(&api->smbusQuickData, bp, seri_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BYTE_RW: + { + // Serialize field-presence indicator for `api->i2cByteData`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Record has 2 field(s) to be serialized. + { + NV_STATUS status = finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW(&api->i2cByteData, bp, seri_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW: + { + // Serialize field-presence indicator for `api->i2cBlockData`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Record has 3 field(s) to be serialized. + { + NV_STATUS status = finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW(&api->i2cBlockData, bp, seri_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW: + { + // Serialize field-presence indicator for `api->i2cBufferData`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Record has 5 field(s) to be serialized. + { + NV_STATUS status = finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW(&api->i2cBufferData, bp, seri_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW: + { + // Serialize field-presence indicator for `api->smbusByteData`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Record has 3 field(s) to be serialized. + { + NV_STATUS status = finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW(&api->smbusByteData, bp, seri_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW: + { + // Serialize field-presence indicator for `api->smbusWordData`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Record has 3 field(s) to be serialized. + { + NV_STATUS status = finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW(&api->smbusWordData, bp, seri_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW: + { + // Serialize field-presence indicator for `api->smbusBlockData`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Record has 4 field(s) to be serialized. + { + NV_STATUS status = finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW(&api->smbusBlockData, bp, seri_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_PROCESS_CALL: + { + // Serialize field-presence indicator for `api->smbusProcessData`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Record has 3 field(s) to be serialized. + { + NV_STATUS status = finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL(&api->smbusProcessData, bp, seri_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_PROCESS_CALL: + { + // Serialize field-presence indicator for `api->smbusBlockProcessData`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Record has 5 field(s) to be serialized. + { + NV_STATUS status = finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL(&api->smbusBlockProcessData, bp, seri_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW: + { + // Serialize field-presence indicator for `api->smbusMultibyteRegisterData`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Record has 6 field(s) to be serialized. + { + NV_STATUS status = finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW(&api->smbusMultibyteRegisterData, bp, seri_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_READ_EDID_DDC: + { + // Serialize field-presence indicator for `api->edidData`. + if (finn_write_buffer(bp, 1, 1)) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + // Record has 4 field(s) to be serialized. + { + NV_STATUS status = finnSerializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC(&api->edidData, bp, seri_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + default: + { + FINN_ERROR(NV_ERR_INVALID_ARGUMENT); + return NV_ERR_INVALID_ARGUMENT; + } + } +} + + +// Deserialize selected field from 11 possible values. +static NV_STATUS finnDeserializeUnion_NV402C_CTRL_I2C_TRANSACTION_DATA(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_TRANSACTION_DATA *api, NvLength api_size, NvBool deser_up, NV402C_CTRL_I2C_TRANSACTION_TYPE transType) +{ + // Check that the destination struct fits within the destination buffer. + if (sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA) > api_size) + { + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + return NV_ERR_BUFFER_TOO_SMALL; + } + + switch(transType) + { + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW: + { + // Check field-presence indicator for `api->smbusQuickData`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Record has 2 field(s) to be deserialized. + { + NV_STATUS status = finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW(bp, &api->smbusQuickData, sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_QUICK_RW), deser_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BYTE_RW: + { + // Check field-presence indicator for `api->i2cByteData`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Record has 2 field(s) to be deserialized. + { + NV_STATUS status = finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW(bp, &api->i2cByteData, sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BYTE_RW), deser_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW: + { + // Check field-presence indicator for `api->i2cBlockData`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Record has 3 field(s) to be deserialized. + { + NV_STATUS status = finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW(bp, &api->i2cBlockData, sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BLOCK_RW), deser_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW: + { + // Check field-presence indicator for `api->i2cBufferData`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Record has 5 field(s) to be deserialized. + { + NV_STATUS status = finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW(bp, &api->i2cBufferData, sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_I2C_BUFFER_RW), deser_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW: + { + // Check field-presence indicator for `api->smbusByteData`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Record has 3 field(s) to be deserialized. + { + NV_STATUS status = finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW(bp, &api->smbusByteData, sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BYTE_RW), deser_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW: + { + // Check field-presence indicator for `api->smbusWordData`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Record has 3 field(s) to be deserialized. + { + NV_STATUS status = finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW(bp, &api->smbusWordData, sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_WORD_RW), deser_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW: + { + // Check field-presence indicator for `api->smbusBlockData`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Record has 4 field(s) to be deserialized. + { + NV_STATUS status = finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW(bp, &api->smbusBlockData, sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_RW), deser_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_PROCESS_CALL: + { + // Check field-presence indicator for `api->smbusProcessData`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Record has 3 field(s) to be deserialized. + { + NV_STATUS status = finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL(bp, &api->smbusProcessData, sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_PROCESS_CALL), deser_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_PROCESS_CALL: + { + // Check field-presence indicator for `api->smbusBlockProcessData`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Record has 5 field(s) to be deserialized. + { + NV_STATUS status = finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL(bp, &api->smbusBlockProcessData, sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_BLOCK_PROCESS_CALL), deser_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW: + { + // Check field-presence indicator for `api->smbusMultibyteRegisterData`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Record has 6 field(s) to be deserialized. + { + NV_STATUS status = finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW(bp, &api->smbusMultibyteRegisterData, sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_SMBUS_MULTIBYTE_REGISTER_BLOCK_RW), deser_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + case NV402C_CTRL_I2C_TRANSACTION_TYPE_READ_EDID_DDC: + { + // Check field-presence indicator for `api->edidData`. + if (!finn_read_buffer(bp, 1)) + { + FINN_ERROR(NV_ERR_LIB_RM_VERSION_MISMATCH); + return NV_ERR_LIB_RM_VERSION_MISMATCH; + } + + // Record has 4 field(s) to be deserialized. + { + NV_STATUS status = finnDeserializeRecord_NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC(bp, &api->edidData, sizeof(NV402C_CTRL_I2C_TRANSACTION_DATA_READ_EDID_DDC), deser_up); + if (status != NV_OK) + return status; + } + + return NV_OK; // Success + } + + default: + { + FINN_ERROR(NV_ERR_INVALID_ARGUMENT); + return NV_ERR_INVALID_ARGUMENT; + } + } +} + + diff --git a/src/nvidia/kernel/inc/dev_p2060.h b/src/nvidia/kernel/inc/dev_p2060.h index b7affde4c..bbac51487 100644 --- a/src/nvidia/kernel/inc/dev_p2060.h +++ b/src/nvidia/kernel/inc/dev_p2060.h @@ -303,4 +303,12 @@ #define NV_P2060_MOSAIC_MODE_ENABLE_TRUE 0x01 /* RW--V */ #define NV_P2060_MOSAIC_MODE_RESERVED 7:4 /* RWIVF */ +#define NV_P2060_MULTIPLIER_DIVIDER 0x2F /* RW-1R */ +#define NV_P2060_MULTIPLIER_DIVIDER_VALUE_MINUS_ONE 2:0 /* RWIVF */ +#define NV_P2060_MULTIPLIER_DIVIDER_VALUE_MINUS_ONE_MAX 0x7 +#define NV_P2060_MULTIPLIER_DIVIDER_MODE 7:7 /* RWIVF */ +#define NV_P2060_MULTIPLIER_DIVIDER_MODE_MULTIPLY 0x0 /* RWIVF */ +#define NV_P2060_MULTIPLIER_DIVIDER_MODE_DIVIDE 0x1 /* RWIVF */ + #endif //DEV_P2060_H + diff --git a/src/nvidia/kernel/inc/objrpc.h b/src/nvidia/kernel/inc/objrpc.h index 1fb06bd0c..d94330c91 100644 --- a/src/nvidia/kernel/inc/objrpc.h +++ b/src/nvidia/kernel/inc/objrpc.h @@ -70,13 +70,8 @@ struct OBJRPC{ NvU32 *message_buffer_priv_uvm; MEMORY_DESCRIPTOR *pMemDesc_mesg_uvm; - // Buffer for initial GSP message. - void *init_msg_buf; - RmPhysAddr init_msg_buf_pa; - /* Message Queue */ struct _message_queue_info *pMessageQueueInfo; - RmPhysAddr messageQueuePhysMem; RpcHistoryEntry rpcHistory[RPC_HISTORY_DEPTH]; NvU32 rpcHistoryCurrent; @@ -104,7 +99,6 @@ NV_STATUS freeRpcInfrastructure_VGPU(OBJGPU *pGpu); OBJRPC *initRpcObject(OBJGPU *pGpu); void rpcSetIpVersion(OBJGPU *pGpu, OBJRPC *pRpc, NvU32 ipVersion); void rpcObjIfacesSetup(OBJRPC *pRpc); -void rpcRmApiSetup(OBJGPU *pGpu); NV_STATUS rpcWriteCommonHeader(OBJGPU *pGpu, OBJRPC *pRpc, NvU32 func, NvU32 paramLength); NV_STATUS rpcWriteCommonHeaderSim(OBJGPU *pGpu); NV_STATUS _allocRpcMemDesc(OBJGPU *pGpu, NvU64 size, NvBool bContig, NV_ADDRESS_SPACE addrSpace, MEMORY_DESCRIPTOR **ppMemDesc, void **ppMemBuffer, void **ppMemBufferPriv); diff --git a/src/nvidia/kernel/inc/vgpu/rpc.h b/src/nvidia/kernel/inc/vgpu/rpc.h index f2d104af6..58a9db77c 100644 --- a/src/nvidia/kernel/inc/vgpu/rpc.h +++ b/src/nvidia/kernel/inc/vgpu/rpc.h @@ -62,7 +62,6 @@ static inline void NV_RM_RPC_ALLOC_EVENT(OBJGPU *pGpu, ...) { return; } static inline void NV_RM_RPC_CONTROL(OBJGPU *pGpu, ...) { return; } static inline void NV_RM_RPC_MANAGE_HW_RESOURCE_ALLOC(OBJGPU *pGpu, ...) { return; } static inline void NV_RM_RPC_MANAGE_HW_RESOURCE_FREE(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_MANAGE_HW_RESOURCE_BIND(OBJGPU *pGpu, ...) { return; } static inline void NV_RM_RPC_SET_GUEST_SYSTEM_INFO(OBJGPU *pGpu, ...) { return; } static inline void NV_RM_RPC_PERF_GET_PSTATE_INFO(OBJGPU *pGpu, ...) { return; } static inline void NV_RM_RPC_PERF_GET_VIRTUAL_PSTATE_INFO(OBJGPU *pGpu, ...) { return; } @@ -92,7 +91,6 @@ static inline void NV_RM_RPC_FREE_ON_ERROR(OBJGPU *pGpu, ...) { return; } // Simulation stubs static inline void NV_RM_RPC_SIM_LOAD_ESCAPE_FUNCTIONS(OBJOS *pOS, ...) { return; } -static inline void NV_RM_RPC_SIM_ADD_DISP_CONTEXT_DMA(OBJGPU *pGpu, ...) { return; } static inline void NV_RM_RPC_SIM_UPDATE_DISP_CONTEXT_DMA(OBJGPU *pGpu, ...) { return; } static inline void NV_RM_RPC_SIM_DELETE_DISP_CONTEXT_DMA(OBJGPU *pGpu, ...) { return; } static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { return; } @@ -440,19 +438,6 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r status = NV_ERR_INSUFFICIENT_RESOURCES; \ } while(0) -#define NV_RM_RPC_MANAGE_HW_RESOURCE_BIND(pGpu, hclient, hdevice, hresource, \ - virtaddr, physaddr, status) \ - do \ - { \ - OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ - NV_ASSERT(pRpc != NULL); \ - if ((status == NV_OK) && (pRpc != NULL)) \ - status = RmRpcHwResourceBind(pGpu, pRpc, hclient, hdevice, \ - hresource, virtaddr, physaddr); \ - if (pRpc == NULL) \ - status = NV_ERR_INSUFFICIENT_RESOURCES; \ - } while(0) - #define NV_RM_RPC_SIM_LOAD_ESCAPE_FUNCTIONS(pos) \ do \ { \ @@ -464,17 +449,6 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r while(0) /* outgoing updates to the plugin */ -#define NV_RM_RPC_SIM_ADD_DISP_CONTEXT_DMA(pGpu, hclient, pcontextdma, channelnum) \ - do \ - { \ - NV_STATUS status; \ - SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) \ - status = RmRpcSimAddDisplayContextDma(pGpu, hclient, pcontextdma, channelnum); \ - NV_ASSERT(status == NV_OK); \ - SLI_LOOP_END \ - } \ - while(0) - #define NV_RM_RPC_SIM_UPDATE_DISP_CONTEXT_DMA(pGpu, hclient, pcontextdma, physaddrnew, \ physlimitnew, pagesize, ptekind) \ do \ @@ -545,13 +519,13 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r status = NV_ERR_INSUFFICIENT_RESOURCES; \ } while(0) -#define NV_RM_RPC_UNLOADING_GUEST_DRIVER(pGpu, status, bSuspend, bGc6Entering, newPMLevel) \ +#define NV_RM_RPC_UNLOADING_GUEST_DRIVER(pGpu, status, bInPMTransition, bGc6Entering, newPMLevel) \ do \ { \ OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ NV_ASSERT(pRpc != NULL); \ if ((status == NV_OK) && (pRpc != NULL)) \ - status = rpcUnloadingGuestDriver_HAL(pGpu, pRpc, bSuspend, bGc6Entering, newPMLevel); \ + status = rpcUnloadingGuestDriver_HAL(pGpu, pRpc, bInPMTransition, bGc6Entering, newPMLevel); \ else if (pRpc == NULL) \ status = NV_ERR_INSUFFICIENT_RESOURCES; \ } \ @@ -703,13 +677,11 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r testData3, status) do {} while(0) static inline NV_STATUS RmRpcSimFreeInfra(OBJGPU *pGpu, ...) { return NV_OK; } -static inline NV_STATUS RmRpcSimAddDisplayContextDma(OBJGPU *pGpu, ...) { return NV_ERR_NOT_SUPPORTED; } static inline NV_STATUS RmRpcSimUpdateDisplayContextDma(OBJGPU *pGpu, ...) { return NV_ERR_NOT_SUPPORTED; } static inline NV_STATUS RmRpcSimDeleteDisplayContextDma(OBJGPU *pGpu, ...) { return NV_ERR_NOT_SUPPORTED; } static inline NV_STATUS RmRpcSimUpdateDispChannelInfo(OBJGPU *pGpu, ...) { return NV_ERR_NOT_SUPPORTED; } static inline NV_STATUS RmRpcHwResourceAlloc(OBJGPU *pGpu, ...) { return NV_ERR_NOT_SUPPORTED; } static inline NV_STATUS RmRpcHwResourceFree(OBJGPU *pGpu, ...) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS RmRpcHwResourceBind(OBJGPU *pGpu, ...) { return NV_ERR_NOT_SUPPORTED; } static inline NV_STATUS RmRpcPerfGetPstateInfo(OBJGPU *pGpu, ...) { return NV_ERR_NOT_SUPPORTED; } static inline NV_STATUS RmRpcPerfGetCurrentPstate(OBJGPU *pGpu, ...) { return NV_ERR_NOT_SUPPORTED; } static inline NV_STATUS RmRpcPerfGetVirtualPstateInfo(OBJGPU *pGpu, ...) { return NV_ERR_NOT_SUPPORTED; } diff --git a/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h b/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h index d4b1ea89e..a065ea900 100644 --- a/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h +++ b/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h @@ -205,7 +205,7 @@ enum { X(RM, CTRL_GET_TOTAL_HS_CREDITS) // 196 X(RM, CTRL_GET_HS_CREDITS) // 197 X(RM, CTRL_SET_HS_CREDITS) // 198 - X(RM, CTRL_PM_AREA_PC_SAMPLER) // 199 + X(RM, CTRL_PM_AREA_PC_SAMPLER) // 199 X(RM, NUM_FUNCTIONS) //END #ifdef DEFINING_X_IN_RPC_GLOBAL_ENUMS_H }; @@ -246,6 +246,7 @@ enum { E(TIMED_SEMAPHORE_RELEASE) // 0x1018 E(NVLINK_IS_GPU_DEGRADED) // 0x1019 E(PFM_REQ_HNDLR_STATE_SYNC_CALLBACK) // 0x101a + E(GSP_SEND_USER_SHARED_DATA) // 0x101b E(NVLINK_FAULT_UP) // 0x101c E(GSP_LOCKDOWN_NOTICE) // 0x101d E(NUM_EVENTS) // END diff --git a/src/nvidia/kernel/inc/vgpu/rpc_headers.h b/src/nvidia/kernel/inc/vgpu/rpc_headers.h index 4f355095f..bff16d54d 100644 --- a/src/nvidia/kernel/inc/vgpu/rpc_headers.h +++ b/src/nvidia/kernel/inc/vgpu/rpc_headers.h @@ -135,7 +135,6 @@ #define NV_VGPU_MSG_RESULT_RPC_UNKNOWN_RM_ERROR 0xFF100005 /* RW--V */ #define NV_VGPU_MSG_RESULT_RPC_UNKNOWN_VMIOP_ERROR 0xFF100006 /* RW--V */ #define NV_VGPU_MSG_RESULT_RPC_RESERVED_HANDLE 0xFF100007 /* RW--V */ -#define NV_VGPU_MSG_RESULT_RPC_CUDA_PROFILING_DISABLED 0xFF100008 /* RW--V */ /* RPC-specific code in result for incomplete request */ #define NV_VGPU_MSG_RESULT_RPC_PENDING 0xFFFFFFFF /* RW--V */ /* shared union field */ diff --git a/src/nvidia/kernel/inc/vgpu/sdk-structures.h b/src/nvidia/kernel/inc/vgpu/sdk-structures.h index e40207ba1..76e370825 100644 --- a/src/nvidia/kernel/inc/vgpu/sdk-structures.h +++ b/src/nvidia/kernel/inc/vgpu/sdk-structures.h @@ -122,6 +122,7 @@ typedef struct vmiopd_SM_info { #define NV0080_CTRL_GR_INFO_MAX_SIZE_1C_01 (0x00000030) #define NV0080_CTRL_GR_INFO_MAX_SIZE_1E_02 (0x00000032) #define NV0080_CTRL_GR_INFO_MAX_SIZE_21_01 (0x00000033) +#define NV0080_CTRL_GR_INFO_MAX_SIZE_22_02 (0x00000034) #define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04 8 #define NV2080_CTRL_INTERNAL_GR_MAX_SM_v1B_05 256 #define NV2080_CTRL_INTERNAL_GR_MAX_SM_v1E_03 240 @@ -132,8 +133,8 @@ typedef struct vmiopd_SM_info { #define NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX_v1E_09 32 #define NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL_v1F_0E 72 #define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE_v20_04 6 -#define NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX_v21_07 50 #define NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08 63 +#define NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX_v21_07 50 #define NV2080_CTRL_MAX_PCES_v21_0A 32 #define NV2080_CTRL_CE_CAPS_TBL_SIZE_v21_0A 2 #define NV2080_ENGINE_TYPE_COPY_SIZE_v21_0A 10 @@ -213,29 +214,6 @@ typedef struct VGPU_BSP_CAPS NvU8 capsTbl[NV0080_CTRL_BSP_CAPS_TBL_SIZE]; } VGPU_BSP_CAPS; -#define VGPU_PAGE_SIZE 4096 -#define NUM_MFN_PAGES 16 - -typedef struct HYPERV_SHARED_MEMORY_DESCRIPTOR -{ - union - { - struct - { - NvU32 shm_lock; - NvU64 vmbus_packet_id NV_ALIGN_BYTES(8); - }; - - char control_page[VGPU_PAGE_SIZE]; - }; - - NvU32 mfn_data[NUM_MFN_PAGES * VGPU_PAGE_SIZE / sizeof(NvU32)]; - -} HYPERV_SHARED_MEMORY_DESCRIPTOR; - -#define HYPERV_SHM_MFN_WRITE_WAIT 0 -#define HYPERV_SHM_MFN_WRITE_COMPLETE 1 - #define NV2080_CTRL_GPU_ECC_UNIT_COUNT_v15_01 (0x00000014) #define NV2080_CTRL_GPU_ECC_UNIT_COUNT_v1A_04 (0x00000014) #define NV2080_CTRL_GPU_ECC_UNIT_COUNT_v1C_09 (0x00000016) diff --git a/src/nvidia/kernel/inc/vgpu/vgpu_version.h b/src/nvidia/kernel/inc/vgpu/vgpu_version.h index 9839cf844..6a73571bd 100644 --- a/src/nvidia/kernel/inc/vgpu/vgpu_version.h +++ b/src/nvidia/kernel/inc/vgpu/vgpu_version.h @@ -30,9 +30,8 @@ #define RPC_VERSION_FROM_VGX_VERSION(major, minor) ( DRF_NUM(_RPC, _VERSION_NUMBER, _MAJOR, major) | \ DRF_NUM(_RPC, _VERSION_NUMBER, _MINOR, minor)) -#define VGX_MAJOR_VERSION_NUMBER 0x21 -#define VGX_MINOR_VERSION_NUMBER 0x0C - +#define VGX_MAJOR_VERSION_NUMBER 0x22 +#define VGX_MINOR_VERSION_NUMBER 0x02 #define VGX_MAJOR_VERSION_NUMBER_VGPU_12_0 0x1A #define VGX_MINOR_VERSION_NUMBER_VGPU_12_0 0x18 @@ -50,6 +49,7 @@ * 2. This is the first break in migration compatibility after a release. */ #define NV_VGPU_GRIDSW_INTERNAL_TO_EXTERNAL_VERSION_MAPPING \ + {{0x22, 0x0}, {0x22, 0x02}, {0x11, 0x1}}, \ {{0x21, 0x0}, {0x21, 0x0C}, {0x10, 0x1}}, \ {{0x20, 0x0}, {0x20, 0x04}, {0xF, 0x1}}, \ {{0x1F, 0x0}, {0x1F, 0xF}, {0xE, 0x1}}, \ @@ -94,7 +94,7 @@ /* WARNING: Should be updated with each vGPU release, if there is a break in * migration compatibility during the development of that release. */ -#define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR 0x10 +#define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR 0x11 #define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MINOR 0x1 /* WARNING: Should be updated with each vGPU release, if minimum supported diff --git a/src/nvidia/kernel/vgpu/nv/rpc.c b/src/nvidia/kernel/vgpu/nv/rpc.c index 30e9e5bf4..a97703907 100644 --- a/src/nvidia/kernel/vgpu/nv/rpc.c +++ b/src/nvidia/kernel/vgpu/nv/rpc.c @@ -33,6 +33,7 @@ #include "core/locks.h" #include "gpu/gpu.h" #include "gpu/bif/kernel_bif.h" +#include "gpu/subdevice/subdevice.h" #include "gpu/mem_mgr/mem_desc.h" #include "nvVer.h" #include "nvBldVer.h" @@ -50,7 +51,6 @@ #include "vgpu/rpc.h" #include "vgpu/vgpu_events.h" #include "virtualization/hypervisor/hypervisor.h" -#include "finn_rm_api.h" #include "os/os.h" #define SDK_ALL_CLASSES_INCLUDE_FULL_HEADER @@ -73,6 +73,7 @@ #include "g_rpc_private.h" +#include "g_finn_rm_api.h" #include "gpu/gsp/message_queue_priv.h" @@ -100,7 +101,6 @@ typedef struct rpc_vgx_version } RPC_VGX_VERSION; static RPC_VGX_VERSION rpcVgxVersion; -static NvBool bSkipRpcVersionHandshake = NV_FALSE; void rpcSetIpVersion(OBJGPU *pGpu, OBJRPC *pRpc, NvU32 ipVersion) { @@ -672,17 +672,10 @@ NV_STATUS RmRpcSetGuestSystemInfo(OBJGPU *pGpu, OBJRPC *pRpc) { if (rpcVgxVersion.majorNum != 0) { - if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_PM_RESUME_CODEPATH) && !bSkipRpcVersionHandshake) - { - bSkipRpcVersionHandshake = NV_TRUE; - } - else - { - NV_PRINTF(LEVEL_INFO, - "NVRM_RPC: Skipping RPC version handshake for instance 0x%x\n", - gpuGetInstance(pGpu)); - goto skip_ver_handshake; - } + NV_PRINTF(LEVEL_INFO, + "NVRM_RPC: Skipping RPC version handshake for instance 0x%x\n", + gpuGetInstance(pGpu)); + goto skip_ver_handshake; } else { @@ -828,7 +821,7 @@ skip_ver_handshake: return status; } -NV_STATUS rpcUnloadingGuestDriver_v03_00(OBJGPU *pGpu, OBJRPC *pRpc, NvBool bSuspend, NvBool bGc6Entering, NvU32 newPMLevel) +NV_STATUS rpcUnloadingGuestDriver_v03_00(OBJGPU *pGpu, OBJRPC *pRpc, NvBool bInPMTransition, NvBool bGc6Entering, NvU32 newPMLevel) { NV_STATUS status = NV_OK; @@ -842,7 +835,7 @@ NV_STATUS rpcUnloadingGuestDriver_v03_00(OBJGPU *pGpu, OBJRPC *pRpc, NvBool bSus } -NV_STATUS rpcUnloadingGuestDriver_v1F_07(OBJGPU *pGpu, OBJRPC *pRpc, NvBool bSuspend, NvBool bGc6Entering, NvU32 newPMLevel) +NV_STATUS rpcUnloadingGuestDriver_v1F_07(OBJGPU *pGpu, OBJRPC *pRpc, NvBool bInPMTransition, NvBool bGc6Entering, NvU32 newPMLevel) { NV_STATUS status = NV_OK; NvU32 headerLength = sizeof(rpc_message_header_v) + sizeof(rpc_unloading_guest_driver_v1F_07); @@ -859,7 +852,7 @@ NV_STATUS rpcUnloadingGuestDriver_v1F_07(OBJGPU *pGpu, OBJRPC *pRpc, NvBool bSus status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_UNLOADING_GUEST_DRIVER, sizeof(rpc_unloading_guest_driver_v1F_07)); if (status != NV_OK) return status; - rpc_message->unloading_guest_driver_v1F_07.bSuspend = bSuspend; + rpc_message->unloading_guest_driver_v1F_07.bInPMTransition = bInPMTransition; rpc_message->unloading_guest_driver_v1F_07.bGc6Entering = bGc6Entering; rpc_message->unloading_guest_driver_v1F_07.newLevel = newPMLevel; @@ -1334,7 +1327,7 @@ NV_STATUS rpcSetRegistry_v17_00 if (IS_GSP_CLIENT(pGpu)) { - NvU32 regTableSize; + NvU32 regTableSize = 0; NvU32 totalSize; NvU32 remainingMessageSize; PACKED_REGISTRY_TABLE *pRegTable; @@ -1380,18 +1373,20 @@ NV_STATUS rpcSetRegistry_v17_00 status = osPackageRegistry(pGpu, pRegTable, ®TableSize); if (status != NV_OK) - return status; + goto fail; if (largeRpcBuffer != NULL) { status = _issueRpcAsyncLarge(pGpu, pRpc, totalSize, largeRpcBuffer); - portMemFree(largeRpcBuffer); } else { vgpu_rpc_message_header_v->length = totalSize; status = _issueRpcAsync(pGpu, pRpc); } + + fail: + portMemFree(largeRpcBuffer); } return status; @@ -1524,17 +1519,17 @@ NV_STATUS rpcRmApiControl_GSP NvU32 rpc_params_size; NvU32 total_size; - const NvU32 interface_id = (DRF_VAL(XXXX, _CTRL_CMD, _CLASS, cmd) << 8) | - DRF_VAL(XXXX, _CTRL_CMD, _CATEGORY, cmd); - const NvU32 message_id = DRF_VAL(XXXX, _CTRL_CMD, _INDEX, cmd); - NvU8 *pSerBuffer = NULL; - NvU32 serializedSize = 0; NvU32 origParamsSize = paramsSize; NvU32 gpuMaskRelease = 0; NvU32 ctrlFlags = 0; NvU32 ctrlAccessRight = 0; NvBool bCacheable; + CALL_CONTEXT *pCallContext; + CALL_CONTEXT newContext; + NvU32 resCtrlFlags = NVOS54_FLAGS_NONE; + NvBool preSerialized = NV_FALSE; + if (!rmDeviceGpuLockIsOwner(pGpu->gpuInstance)) { NV_PRINTF(LEVEL_WARNING, "Calling RPC RmControl 0x%08x without adequate locks!\n", cmd); @@ -1548,15 +1543,37 @@ NV_STATUS rpcRmApiControl_GSP rmapiutilGetControlInfo(cmd, &ctrlFlags, &ctrlAccessRight); bCacheable = rmapiControlIsCacheable(ctrlFlags, ctrlAccessRight, NV_TRUE); - // Attempt to calculate the serialized size of the param struct using FINN. - serializedSize = FinnRmApiGetSerializedSize(interface_id, message_id, pParamStructPtr); - - // If successful, this is a serializable API and rpc_params->params is a serialized buffer. - // otherwise this is a flat API and paramsSize is the param struct size - if (serializedSize != 0) + pCallContext = resservGetTlsCallContext(); + if (pCallContext == NULL || pCallContext->bReserialize) { - // Allocate twice the amount to account for the return buffer - paramsSize = 2 * serializedSize; + // This should only happen when using the internal physical RMAPI + NV_ASSERT_OR_RETURN(pRmApi == GPU_GET_PHYSICAL_RMAPI(pGpu), NV_ERR_INVALID_STATE); + + portMemSet(&newContext, 0, sizeof(newContext)); + pCallContext = &newContext; + } + + if (pCallContext->pControlParams != NULL) + { + resCtrlFlags = pCallContext->pControlParams->flags; + } + + if (resCtrlFlags & NVOS54_FLAGS_FINN_SERIALIZED) + { + preSerialized = NV_TRUE; + } + else + { + status = serverSerializeCtrlDown(pCallContext, cmd, pParamStructPtr, paramsSize, &resCtrlFlags); + if (status != NV_OK) + goto done; + } + + // If this is a serializable API, rpc_params->params is a serialized buffer. + // otherwise this is a flat API and paramsSize is the param struct size + if (resCtrlFlags & NVOS54_FLAGS_FINN_SERIALIZED) + { + paramsSize = pCallContext->serializedSize; NV_ASSERT_OR_RETURN(!bCacheable, NV_ERR_INVALID_STATE); } @@ -1593,24 +1610,11 @@ NV_STATUS rpcRmApiControl_GSP message_buffer_remaining = total_size - fixed_param_size; } - // If this is a serializable API, attempt to serialize the param struct using FINN, - // otherwise do a flat memcpy - if (serializedSize != 0) + if (resCtrlFlags & NVOS54_FLAGS_FINN_SERIALIZED) { + // Copy in serialized buffer from the call context rpc_params->serialized = NV_TRUE; - pSerBuffer = (NvU8 *)rpc_params->params; - - // Serialize into the first half of the RPC buffer. - status = FinnRmApiSerializeDown(interface_id, message_id, pParamStructPtr, - &pSerBuffer, message_buffer_remaining); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "GspRmControl: Serialization failed for cmd 0x%x with status %s (0x%x) at index 0x%llx\n", - cmd, nvAssertStatusToString(status), status, - (NvUPtr)(pSerBuffer - (NvU8 *)rpc_params->params)); - goto done; - } + portMemCopy(rpc_params->params, message_buffer_remaining, pCallContext->pSerializedParams, pCallContext->serializedSize); } else { @@ -1677,22 +1681,21 @@ NV_STATUS rpcRmApiControl_GSP goto done; } - // If FINN was used to serialize the params, they must be deserialized on the way back, - // otherwise do a flat memcpy - if (serializedSize != 0) + if (resCtrlFlags & NVOS54_FLAGS_FINN_SERIALIZED) { - NvU8 *pRetBuffer = pSerBuffer; - - // Deserialize from the second half of the RPC buffer. - status = FinnRmApiDeserializeUp(&pSerBuffer, paramsSize / 2, - pParamStructPtr, origParamsSize); - if (status != NV_OK) + // + // If it was preserialized, copy it to call context for deserialization by caller + // Otherwise deserialize it because it was serialized here + // + if (preSerialized) { - NV_PRINTF(LEVEL_ERROR, - "GspRmControl: Deserialization failed for cmd 0x%x with status %s (0x%x) at index 0x%llx\n", - cmd, nvAssertStatusToString(status), status, - (NvUPtr)(pSerBuffer - pRetBuffer)); - goto done; + portMemCopy(pCallContext->pSerializedParams, pCallContext->serializedSize, rpc_params->params, rpc_params->paramsSize); + } + else + { + status = serverDeserializeCtrlUp(pCallContext, cmd, pParamStructPtr, origParamsSize, &resCtrlFlags); + if (status != NV_OK) + goto done; } } else @@ -1733,6 +1736,15 @@ done: // Free the local copy we might have allocated above portMemFree(large_message_copy); + // + // Free data structures if we serialized/deserialized here + // Also check for serialized flag here as we may be called directly from within another control call + // + if ((resCtrlFlags & NVOS54_FLAGS_FINN_SERIALIZED) && !preSerialized) + { + serverFreeSerializeStructures(pCallContext, pParamStructPtr); + } + return status; } diff --git a/src/nvidia/src/kernel/core/hal/hal.c b/src/nvidia/src/kernel/core/hal/hal.c index bbde4fb3f..9b1800cfd 100644 --- a/src/nvidia/src/kernel/core/hal/hal.c +++ b/src/nvidia/src/kernel/core/hal/hal.c @@ -68,54 +68,3 @@ registerHalModule(NvU32 halImpl, const HAL_IFACE_SETUP *pHalSetIfaces) return NV_OK; } - -// Helper to install IP_VERSIONS function pointers into pObj->hal fn ptr table -// based on IP_VER register value. -// Uses tables and code in g_FOO_private.h (generated by rmconfig) - -NV_STATUS ipVersionsSetupHal -( - OBJGPU *pGpu, - void * pDynamic_v, // eg: pDisp - IGrp_ipVersions_getInfo getInfoFn // eg: disp_iGrp_ipVersions_getInfo() -) -{ - IGRP_IP_VERSIONS_TABLE_INFO info; - const IGRP_IP_VERSIONS_ENTRY *pVer; - const IGRP_IP_VERSION_RANGE *pRange; - NV_STATUS rmStatus; - Dynamic *pDynamic = (Dynamic*)pDynamic_v; - Object *pObj = dynamicCast(pDynamic, Object); - - // nothing to do if IP_VERSION is invalid - if ( ! IsIPVersionValid(pObj)) - return NV_OK; - - info.pGpu = pGpu; - info.pDynamic = pDynamic; - - // call into the hal to finish filling in the table - rmStatus = getInfoFn(&info); - if (rmStatus != NV_OK) - return rmStatus; - - // perform setup for *all* matching variants - for (pVer = info.pTable; pVer < info.pTable + info.numEntries; pVer++) - { - // Each version has 1 or more "version ranges". - // Invoke this version's setup fn if any of it's ranges match. - for (pRange = pVer->pRanges; pRange < (pVer->pRanges + pVer->numRanges); pRange++) - { - if ((IPVersion(pObj) >= pRange->v0) && (IPVersion(pObj) <= pRange->v1)) - { - pVer->ifacesInstallFn(&info); - break; - } - } - } - - // invoke rmconfig-generated wrapup function to handle any overrides & verification - rmStatus = info.ifacesWrapupFn(&info); - - return rmStatus; -} diff --git a/src/nvidia/src/kernel/core/system.c b/src/nvidia/src/kernel/core/system.c index e18dec357..8f34ee4bd 100644 --- a/src/nvidia/src/kernel/core/system.c +++ b/src/nvidia/src/kernel/core/system.c @@ -325,6 +325,18 @@ _sysRegistryOverrideResourceServer { pSys->setProperty(pSys, PDB_PROP_SYS_CLIENT_HANDLE_LOOKUP, !!data32); } + + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_CLIENT_LIST_DEFERRED_FREE, + &data32) == NV_OK) + { + pSys->bUseDeferredClientListFree = !!data32; + } + + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_CLIENT_LIST_DEFERRED_FREE_LIMIT, + &data32) == NV_OK) + { + pSys->clientListDeferredFreeLimit = data32; + } } static void @@ -656,15 +668,6 @@ sysInitRegistryOverrides_IMPL pSys->setProperty(pSys, PDB_PROP_SYS_PRIORITY_THROTTLE_DELAY_US, data32); } - if (osReadRegistryDword(pGpu, NV_REG_STR_RM_MULTICAST_FLA, - &data32) == NV_OK) - { - if (data32 == NV_REG_STR_RM_MULTICAST_FLA_ENABLED) - { - pSys->bMulticastFlaEnabled = NV_TRUE; - } - } - _sysRegistryOverrideExternalFabricMgmt(pSys, pGpu); _sysRegistryOverrideResourceServer(pSys, pGpu); @@ -678,6 +681,8 @@ sysInitRegistryOverrides_IMPL { pSys->setProperty(pSys, PDB_PROP_SYS_ROUTE_TO_PHYSICAL_LOCK_BYPASS, !!data32); } + + gpumgrSetGpuNvlinkBwModeFromRegistry(pGpu); } void diff --git a/src/nvidia/src/kernel/gpu/arch/ada/kern_gpu_ad102.c b/src/nvidia/src/kernel/gpu/arch/ada/kern_gpu_ad102.c index b24c0d53d..f95a5c45d 100644 --- a/src/nvidia/src/kernel/gpu/arch/ada/kern_gpu_ad102.c +++ b/src/nvidia/src/kernel/gpu/arch/ada/kern_gpu_ad102.c @@ -46,12 +46,34 @@ static const GPUCHILDPRESENT gpuChildrenPresent_AD102[] = { + { classId(OBJFUSE), 1, }, + { classId(OBJSEQ), 1, }, + { classId(GpuMutexMgr), 1, }, + { classId(OBJTMR), 1, }, + { classId(GraphicsManager), 1, }, + { classId(MIGManager), 1, }, + { classId(KernelMIGManager), 1, }, + { classId(KernelGraphicsManager), 1, }, + { classId(OBJVBIOS), 1, }, + { classId(OBJDCB), 1, }, + { classId(OBJGPIO), 1, }, + { classId(I2c), 1, }, + { classId(Spi), 1, }, + { classId(KernelRc), 1, }, + { classId(OBJRC), 1, }, + { classId(OBJSTEREO), 1, }, + { classId(Intr), 1, }, + { classId(OBJINFOROM), 1, }, + { classId(NvDebugDump), 1, }, + { classId(SMDebugger), 1, }, + { classId(OBJGPULOG), 1, }, + { classId(OBJGPUMON), 1, }, {classId(OBJSWENG), 1}, {classId(OBJUVM), 1}, {classId(OBJACR), 1}, {classId(OBJBIF), 1}, {classId(KernelBif), 1}, - {classId(OBJNNE), 1}, + {classId(Nne), 1}, {classId(OBJBSP), 4}, {classId(OBJBUS), 1}, {classId(KernelBus), 1}, @@ -74,18 +96,10 @@ static const GPUCHILDPRESENT gpuChildrenPresent_AD102[] = {classId(OBJFIFO), 1}, {classId(OBJGMMU), 1}, {classId(KernelGmmu), 1}, - {classId(OBJGPULOG), 1}, - {classId(OBJGPUMON), 1}, - {classId(GraphicsManager), 1}, - {classId(MIGManager), 1}, - {classId(KernelMIGManager), 1}, - {classId(KernelGraphicsManager), 1}, {classId(Graphics), 1}, {classId(KernelGraphics), 1}, {classId(OBJHDACODEC), 1}, {classId(OBJHWPM), 1}, - {classId(OBJINFOROM), 1}, - {classId(Intr), 1}, {classId(Lpwr ), 1}, {classId(OBJLSFM), 1}, {classId(OBJMC), 1}, @@ -94,7 +108,6 @@ static const GPUCHILDPRESENT gpuChildrenPresent_AD102[] = {classId(SwIntr), 1}, {classId(OBJNVJPG), 4}, {classId(OBJMSENC), 3}, - {classId(NvDebugDump), 1}, {classId(KernelNvlink), 1}, {classId(Nvlink), 1}, {classId(Perf), 1}, @@ -105,10 +118,8 @@ static const GPUCHILDPRESENT gpuChildrenPresent_AD102[] = {classId(OBJSEC2), 1}, {classId(Gsp), 1}, {classId(Therm), 1}, - {classId(OBJTMR), 1}, {classId(OBJVOLT), 1}, {classId(OBJGRIDDISPLAYLESS), 1}, - {classId(OBJFAS), 1}, {classId(OBJVMMU), 1}, {classId(OBJOFA), 1 }, {classId(KernelSec2), 1}, diff --git a/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c b/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c index 5bffbc803..6726a7ded 100644 --- a/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c +++ b/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c @@ -98,7 +98,7 @@ gpuClearFbhubPoisonIntrForBug2924523_GA100_KERNEL NvU64 gpuGetFlaVasSize_GA100 ( - POBJGPU pGpu, + OBJGPU *pGpu, NvBool bNvswitchVirtualization ) { @@ -130,6 +130,28 @@ gpuGetFlaVasSize_GA100 static const GPUCHILDPRESENT gpuChildrenPresent_GA100[] = { + { classId(OBJFUSE), 1, }, + { classId(OBJSEQ), 1, }, + { classId(GpuMutexMgr), 1, }, + { classId(OBJTMR), 1, }, + { classId(GraphicsManager), 1, }, + { classId(MIGManager), 1, }, + { classId(KernelMIGManager), 1, }, + { classId(KernelGraphicsManager), 1, }, + { classId(OBJVBIOS), 1, }, + { classId(OBJDCB), 1, }, + { classId(OBJGPIO), 1, }, + { classId(I2c), 1, }, + { classId(Spi), 1, }, + { classId(KernelRc), 1, }, + { classId(OBJRC), 1, }, + { classId(OBJSTEREO), 1, }, + { classId(Intr), 1, }, + { classId(OBJINFOROM), 1, }, + { classId(NvDebugDump), 1, }, + { classId(SMDebugger), 1, }, + { classId(OBJGPULOG), 1, }, + { classId(OBJGPUMON), 1, }, { classId(OBJSWENG), 1 }, { classId(OBJUVM), 1 }, { classId(OBJACR), 1 }, @@ -157,18 +179,10 @@ static const GPUCHILDPRESENT gpuChildrenPresent_GA100[] = { classId(OBJFIFO), 1 }, { classId(OBJGMMU), 1 }, { classId(KernelGmmu), 1}, - { classId(OBJGPULOG), 1 }, - { classId(OBJGPUMON), 1 }, - { classId(GraphicsManager), 1 }, - { classId(MIGManager), 1}, - { classId(KernelMIGManager), 1 }, - { classId(KernelGraphicsManager), 1 }, { classId(Graphics), 8 }, { classId(KernelGraphics), 8 }, { classId(OBJHDACODEC), 1 }, { classId(OBJHWPM), 1 }, - { classId(OBJINFOROM), 1 }, - { classId(Intr), 1 }, { classId(Lpwr ), 1 }, { classId(OBJLSFM), 1 }, { classId(OBJMC), 1 }, @@ -176,7 +190,6 @@ static const GPUCHILDPRESENT gpuChildrenPresent_GA100[] = { classId(PrivRing), 1 }, { classId(SwIntr), 1 }, { classId(OBJNVJPG), 1 }, - { classId(NvDebugDump), 1 }, { classId(KernelNvlink), 1 }, { classId(Nvlink), 1 }, { classId(Perf), 1 }, @@ -187,10 +200,8 @@ static const GPUCHILDPRESENT gpuChildrenPresent_GA100[] = { classId(OBJSEC2), 1 }, { classId(Gsp), 1 }, { classId(Therm), 1 }, - { classId(OBJTMR), 1 }, { classId(OBJVOLT), 1 }, { classId(OBJGRIDDISPLAYLESS), 1 }, - { classId(OBJFAS), 1 }, { classId(OBJVMMU), 1 }, { classId(OBJOFA), 1 }, { classId(KernelSec2), 1 }, @@ -218,12 +229,34 @@ gpuGetChildrenPresent_GA100(OBJGPU *pGpu, NvU32 *pNumEntries) // static const GPUCHILDPRESENT gpuChildrenPresent_GA102[] = { + { classId(OBJFUSE), 1, }, + { classId(OBJSEQ), 1, }, + { classId(GpuMutexMgr), 1, }, + { classId(OBJTMR), 1, }, + { classId(GraphicsManager), 1, }, + { classId(MIGManager), 1, }, + { classId(KernelMIGManager), 1, }, + { classId(KernelGraphicsManager), 1, }, + { classId(OBJVBIOS), 1, }, + { classId(OBJDCB), 1, }, + { classId(OBJGPIO), 1, }, + { classId(I2c), 1, }, + { classId(Spi), 1, }, + { classId(KernelRc), 1, }, + { classId(OBJRC), 1, }, + { classId(OBJSTEREO), 1, }, + { classId(Intr), 1, }, + { classId(OBJINFOROM), 1, }, + { classId(NvDebugDump), 1, }, + { classId(SMDebugger), 1, }, + { classId(OBJGPULOG), 1, }, + { classId(OBJGPUMON), 1, }, {classId(OBJSWENG), 1}, {classId(OBJUVM), 1}, {classId(OBJACR), 1}, {classId(OBJBIF), 1}, {classId(KernelBif), 1}, - {classId(OBJNNE), 1}, + {classId(Nne), 1}, {classId(OBJBSP), 2}, {classId(OBJBUS), 1}, {classId(KernelBus), 1}, @@ -246,18 +279,10 @@ static const GPUCHILDPRESENT gpuChildrenPresent_GA102[] = {classId(OBJFIFO), 1}, {classId(OBJGMMU), 1}, {classId(KernelGmmu), 1}, - {classId(OBJGPULOG), 1}, - {classId(OBJGPUMON), 1}, - {classId(GraphicsManager), 1 }, - {classId(MIGManager), 1}, - {classId(KernelMIGManager), 1}, - {classId(KernelGraphicsManager), 1}, {classId(Graphics), 1}, {classId(KernelGraphics), 1}, {classId(OBJHDACODEC), 1}, {classId(OBJHWPM), 1}, - {classId(OBJINFOROM), 1}, - {classId(Intr), 1}, {classId(Lpwr ), 1}, {classId(OBJLSFM), 1}, {classId(OBJMC), 1}, @@ -265,7 +290,6 @@ static const GPUCHILDPRESENT gpuChildrenPresent_GA102[] = {classId(PrivRing), 1}, {classId(SwIntr), 1}, {classId(OBJMSENC), 1}, - {classId(NvDebugDump), 1}, {classId(KernelNvlink), 1}, {classId(Nvlink), 1}, {classId(Perf), 1}, @@ -276,10 +300,8 @@ static const GPUCHILDPRESENT gpuChildrenPresent_GA102[] = {classId(OBJSEC2), 1}, {classId(Gsp), 1}, {classId(Therm), 1}, - {classId(OBJTMR), 1}, {classId(OBJVOLT), 1}, {classId(OBJGRIDDISPLAYLESS), 1}, - {classId(OBJFAS), 1}, {classId(OBJVMMU), 1}, {classId(OBJOFA), 1 }, {classId(KernelSec2), 1}, diff --git a/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c b/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c index 6d5fdae27..d0accba9d 100644 --- a/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c +++ b/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c @@ -31,6 +31,8 @@ #include "published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h" #include "published/hopper/gh100/pri_nv_xal_ep.h" +#include "ctrl/ctrl2080/ctrl2080mc.h" + #include "gpu/gsp/gsp_static_config.h" /*! @@ -357,6 +359,28 @@ gpuGetFlaVasSize_GH100 static const GPUCHILDPRESENT gpuChildrenPresent_GH100[] = { + { classId(OBJFUSE), 1, }, + { classId(OBJSEQ), 1, }, + { classId(GpuMutexMgr), 1, }, + { classId(OBJTMR), 1, }, + { classId(GraphicsManager), 1, }, + { classId(MIGManager), 1, }, + { classId(KernelMIGManager), 1, }, + { classId(KernelGraphicsManager), 1, }, + { classId(OBJVBIOS), 1, }, + { classId(OBJDCB), 1, }, + { classId(OBJGPIO), 1, }, + { classId(I2c), 1, }, + { classId(Spi), 1, }, + { classId(KernelRc), 1, }, + { classId(OBJRC), 1, }, + { classId(OBJSTEREO), 1, }, + { classId(Intr), 1, }, + { classId(OBJINFOROM), 1, }, + { classId(NvDebugDump), 1, }, + { classId(SMDebugger), 1, }, + { classId(OBJGPULOG), 1, }, + { classId(OBJGPUMON), 1, }, { classId(OBJSWENG), 1 }, { classId(OBJUVM), 1 }, { classId(OBJACR), 1 }, @@ -384,18 +408,10 @@ static const GPUCHILDPRESENT gpuChildrenPresent_GH100[] = { classId(OBJFIFO), 1 }, { classId(OBJGMMU), 1 }, { classId(KernelGmmu), 1}, - { classId(OBJGPULOG), 1 }, - { classId(OBJGPUMON), 1 }, - { classId(GraphicsManager), 1 }, - { classId(MIGManager), 1 }, - { classId(KernelMIGManager), 1 }, - { classId(KernelGraphicsManager), 1 }, { classId(Graphics), 8 }, { classId(KernelGraphics), 8 }, { classId(OBJHDACODEC), 1 }, { classId(OBJHWPM), 1 }, - { classId(OBJINFOROM), 1 }, - { classId(Intr), 1 }, { classId(Lpwr ), 1 }, { classId(OBJLSFM), 1 }, { classId(OBJMC), 1 }, @@ -403,7 +419,6 @@ static const GPUCHILDPRESENT gpuChildrenPresent_GH100[] = { classId(PrivRing), 1 }, { classId(SwIntr), 1 }, { classId(OBJNVJPG), 8 }, - { classId(NvDebugDump), 1 }, { classId(KernelNvlink), 1 }, { classId(Nvlink), 1 }, { classId(Perf), 1 }, @@ -416,13 +431,12 @@ static const GPUCHILDPRESENT gpuChildrenPresent_GH100[] = { classId(OBJFSP), 1 }, { classId(KernelFsp), 1 }, { classId(Therm), 1 }, - { classId(OBJTMR), 1 }, { classId(OBJVOLT), 1 }, { classId(OBJGRIDDISPLAYLESS), 1 }, - { classId(OBJFAS), 1 }, { classId(OBJVMMU), 1 }, { classId(OBJOFA), 1 }, { classId(KernelGsp), 1}, + { classId(KernelSec2), 1}, { classId(KernelCcu), 1 }, }; diff --git a/src/nvidia/src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c b/src/nvidia/src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c index a852aa8cb..bfd299320 100644 --- a/src/nvidia/src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c +++ b/src/nvidia/src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -22,8 +22,9 @@ */ #include "gpu/gpu.h" +#include "gpu_mgr/gpu_mgr_sli.h" #include "gpu/bif/kernel_bif.h" - +#include "jt.h" #include "published/maxwell/gm107/dev_bus.h" #include "published/maxwell/gm107/dev_nv_xve.h" #include "published/maxwell/gm107/dev_nv_xve1.h" @@ -375,9 +376,10 @@ gpuGetIdInfo_GM107(OBJGPU *pGpu) static const GPUCHILDORDER gpuChildOrderList_GM200[] = { + {classId(Pxuc), GCO_ALL}, {classId(OBJBIF), GCO_ALL}, {classId(KernelBif), GCO_ALL}, - {classId(OBJNNE), GCO_ALL}, + {classId(Nne), GCO_ALL}, {classId(NvDebugDump), GCO_ALL}, {classId(ClockManager), GCO_ALL}, {classId(Pmgr), GCO_ALL}, @@ -487,6 +489,28 @@ gpuGetChildrenOrder_GM200(OBJGPU *pGpu, NvU32 *pNumEntries) // static const GPUCHILDPRESENT gpuChildrenPresent_GM200[] = { + { classId(OBJFUSE), 1, }, + { classId(OBJSEQ), 1, }, + { classId(GpuMutexMgr), 1, }, + { classId(OBJTMR), 1, }, + { classId(GraphicsManager), 1, }, + { classId(MIGManager), 1, }, + { classId(KernelMIGManager), 1, }, + { classId(KernelGraphicsManager), 1, }, + { classId(OBJVBIOS), 1, }, + { classId(OBJDCB), 1, }, + { classId(OBJGPIO), 1, }, + { classId(I2c), 1, }, + { classId(Spi), 1, }, + { classId(KernelRc), 1, }, + { classId(OBJRC), 1, }, + { classId(OBJSTEREO), 1, }, + { classId(Intr), 1, }, + { classId(OBJINFOROM), 1, }, + { classId(NvDebugDump), 1, }, + { classId(SMDebugger), 1, }, + { classId(OBJGPULOG), 1, }, + { classId(OBJGPUMON), 1, }, {classId(OBJSWENG), 1}, {classId(OBJACR), 1}, {classId(OBJBIF), 1}, @@ -512,19 +536,11 @@ static const GPUCHILDPRESENT gpuChildrenPresent_GM200[] = {classId(OBJFIFO), 1}, {classId(OBJGMMU), 1}, {classId(KernelGmmu), 1}, - {classId(OBJGPULOG), 1}, - {classId(OBJGPUMON), 1}, - {classId(GraphicsManager), 1}, - {classId(MIGManager), 1}, - {classId(KernelMIGManager), 1}, - {classId(KernelGraphicsManager), 1}, {classId(Graphics), 1}, {classId(KernelGraphics), 1}, {classId(OBJHDA), 1}, {classId(OBJHDACODEC), 1}, {classId(OBJHWPM), 1}, - {classId(OBJINFOROM), 1}, - {classId(Intr), 1}, {classId(Lpwr ), 1}, {classId(OBJLSFM), 1}, {classId(OBJMC), 1}, @@ -532,7 +548,6 @@ static const GPUCHILDPRESENT gpuChildrenPresent_GM200[] = {classId(PrivRing), 1}, {classId(SwIntr), 1}, {classId(OBJMSENC), 2}, - {classId(NvDebugDump), 1}, {classId(Perf), 1}, {classId(KernelPerf), 1}, {classId(Pmgr), 1}, @@ -540,7 +555,6 @@ static const GPUCHILDPRESENT gpuChildrenPresent_GM200[] = {classId(KernelPmu), 1}, {classId(OBJSEC2), 1}, {classId(Therm), 1}, - {classId(OBJTMR), 1}, {classId(OBJVOLT), 1}, {classId(OBJGRIDDISPLAYLESS), 1}, }; @@ -552,3 +566,115 @@ gpuGetChildrenPresent_GM200(OBJGPU *pGpu, NvU32 *pNumEntries) return gpuChildrenPresent_GM200; } +/*! + * @brief checks for each type of bridge to deterimne what is available, + * then selects the SLI bridge to use. + * + * @param[In] gpuCount The number of GPUs to be checked for SLI links. + * @param[In] gpuMaskArg A mask of the GPUs that are to be tested for SLI links. + * @param[Out] pSliLinkOutputMask a mask of the GPUs that are attached to the type of + * SLI link that is being used. + * @param[Out] pSliLinkCircular a boolean indicating if teh SLI link is circular. + * @param[Out] pSliLinkEndsMask a mask indicating the endpoints of the SLI link, + * if there are any. +.*/ +void +gpuDetectSliLinkFromGpus_GK104 +( + OBJGPU *pGpu, + NvU32 gpuCount, + NvU32 gpuMaskArg, + NvU32 *pSliLinkOutputMask, + NvBool *pSliLinkCircular, + NvU32 *pSliLinkEndsMask, + NvU32 *pVidLinkCount +) +{ + NvU32 i; + NvU32 sliLinkOutputMask[SLI_MAX_BRIDGE_TYPES] = {0, 0}; + NvBool bSliLinkCircular[SLI_MAX_BRIDGE_TYPES] = {NV_FALSE, NV_FALSE}; + NvU32 sliLinkEndsMask[SLI_MAX_BRIDGE_TYPES] = {0, 0}; + NvU32 vidLinkCount[SLI_MAX_BRIDGE_TYPES] = {0, 0}; + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + OBJGPU *pGpuLoop; + OBJGPU *pGpuSaved; + NvU32 gpuMask; + // Array to store the link detection HAL flag of GpuDetectVidLinkFromGpus_HAL and GpuDetectNvlinkLinkFromGpus_HAL. + NvU32 linkHalImpl[SLI_MAX_BRIDGE_TYPES]; + NvBool bFoundBridge = NV_FALSE; + + // set the return values assuming we will not find an SLI link. + *pSliLinkOutputMask = 0; + *pSliLinkCircular = NV_FALSE; + *pSliLinkEndsMask = 0; + + pGpuMgr->gpuBridgeType = SLI_BT_VIDLINK; + + // + // Link detection HAL should have same HAL implementation as HAL flag. + // This checks for mismatched HAL implementation flag. + // + NV_ASSERT_OR_RETURN_VOID(gpuGetSliLinkDetectionHalFlag_HAL(pGpu) == GPU_LINK_DETECTION_HAL_GK104); + + i = 0; + gpuMask = gpuMaskArg; + pGpuLoop = gpumgrGetNextGpu(gpuMask, &i); + if (pGpuLoop != NULL) + { + pGpuSaved = pGpuLoop; + linkHalImpl[SLI_BT_NVLINK] = gpuGetNvlinkLinkDetectionHalFlag_HAL(pGpuLoop); + + } + else + { + return; + } + + // run thru the GPUs and see if they are all using the same HAL functions. + // if they are different, we can't use the function to check for a bridge + pGpuLoop = gpumgrGetNextGpu(gpuMask, &i); + while (NULL != pGpuLoop) + { + if (linkHalImpl[SLI_BT_NVLINK] != gpuGetNvlinkLinkDetectionHalFlag_HAL(pGpuLoop)) + { + linkHalImpl[SLI_BT_NVLINK] = GPU_LINK_DETECTION_HAL_STUB; + } + pGpuLoop = gpumgrGetNextGpu(gpuMask, &i); + } + + if (linkHalImpl[SLI_BT_NVLINK] != GPU_LINK_DETECTION_HAL_STUB) + { + gpuDetectNvlinkLinkFromGpus_HAL(pGpuSaved, gpuCount, gpuMaskArg, + &sliLinkOutputMask[SLI_BT_NVLINK], + &bSliLinkCircular[SLI_BT_NVLINK], + &sliLinkEndsMask[SLI_BT_NVLINK], + &vidLinkCount[SLI_BT_NVLINK]); + } + + // + // Determine which type of bridge we are going to support. + // Currently we only support a single type of SLI bridge in the system. + // + for (i = 0; i < SLI_MAX_BRIDGE_TYPES; ++i) + { + if (sliLinkOutputMask[i] != 0) + { + if (bFoundBridge) + { + NV_PRINTF(LEVEL_ERROR, "More than one type of SLI bridge detected!\n"); + NV_ASSERT(0); + break; + } + else + { + pGpuMgr->gpuBridgeType = (NvU8)i; + *pSliLinkOutputMask = sliLinkOutputMask[i]; + *pSliLinkCircular = bSliLinkCircular[i]; + *pSliLinkEndsMask = sliLinkEndsMask[i]; + *pVidLinkCount = vidLinkCount[i]; + bFoundBridge = NV_TRUE; + } + } + } +} diff --git a/src/nvidia/src/kernel/gpu/arch/pascal/kern_gpu_gp100.c b/src/nvidia/src/kernel/gpu/arch/pascal/kern_gpu_gp100.c new file mode 100644 index 000000000..117e2b506 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/arch/pascal/kern_gpu_gp100.c @@ -0,0 +1,134 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "core/core.h" +#include "gpu/gpu.h" +#include "gpu/eng_desc.h" +#include "gpu/nvlink/kernel_nvlink.h" +#include "gpu_mgr/gpu_mgr_sli.h" + +/*! + * @brief checks for NvLink connections between the GPUs specified in the gpuMaskArg, + * and updates the routing information as appropriate. + * + * @param[In] gpuCount The number of GPUs to be checked for NvLink links. + * @param[In] gpuMaskArg A mask of the GPUs that are to be tested for NvLink links. + * @param[Out] pSliLinkOutputMask a mask of the GPUs that are attached to the NvLink link. + * @param[Out] pSliLinkCircular a boolean indicating if the NvLink link is circular + * (always FALSE). + * @param[Out] pSliLinkEndsMask a mask indicating the endpoints of the NvLink link. + * (always 0). + */ +void +gpuDetectNvlinkLinkFromGpus_GP100 +( + OBJGPU *pGpu, + NvU32 gpuCount, + NvU32 gpuMaskArg, + NvU32 *pSliLinkOutputMask, + NvBool *pSliLinkCircular, + NvU32 *pSliLinkEndsMask, + NvU32 *pVidLinkCount +) +{ + OBJGPU *pGpuLoop = NULL; + KernelNvlink *pKernelNvlink = NULL; + KernelNvlink *pKernelNvlinkChild = NULL; + OBJGPU *pGpuChild = NULL; + NvU32 gpuIndex = 0; + NvU32 gpuIndexChild = 0; + NvU32 parentPinsetIndex; + NvU32 childPinsetIndex; + NvU32 gpuMask = gpuMaskArg; + + *pSliLinkOutputMask = 0; + *pSliLinkCircular = NV_FALSE; + *pSliLinkEndsMask = 0; + *pVidLinkCount = 0; + + // + // Link detection HAL should have same HAL implementation as HAL flag. + // This checks for mismatched HAL implementation flag. + // + NV_ASSERT_OR_RETURN_VOID(gpuGetNvlinkLinkDetectionHalFlag_HAL(pGpu) == GPU_LINK_DETECTION_HAL_GP100); + + // Loop through GPU unique pairs + gpuIndex = 0; + pGpuLoop = gpumgrGetNextGpu(gpuMask, &gpuIndex); + while (pGpuLoop != NULL) + { + // determine if there is a connected NvLink on the GPU. + pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpuLoop); + if (NULL == pKernelNvlink) + { + pGpuLoop = gpumgrGetNextGpu(gpuMask, &gpuIndex); + continue; + } + + gpuIndexChild = gpuIndex; + pGpuChild = gpumgrGetNextGpu(gpuMask, &gpuIndexChild); + while (pGpuChild != NULL) + { + // determine if there is a connected NvLink on the GPU. + pKernelNvlinkChild = GPU_GET_KERNEL_NVLINK(pGpuChild); + if (NULL != pKernelNvlinkChild) + { + if (knvlinkIsNvlinkP2pSupported(pGpuLoop, pKernelNvlink, pGpuChild) == NV_FALSE) + { + pGpuChild = gpumgrGetNextGpu(gpuMask, &gpuIndexChild); + continue; + } + if (0 == knvlinkGetConnectedLinksMask_HAL(pGpuChild, pKernelNvlinkChild)) + { + pGpuChild = gpumgrGetNextGpu(gpuMask, &gpuIndexChild); + continue; + } + } + else + { + pGpuChild = gpumgrGetNextGpu(gpuMask, &gpuIndexChild); + continue; + } + // Loop through the parent pinsets + for (parentPinsetIndex = 0; parentPinsetIndex < DR_PINSET_COUNT; parentPinsetIndex++) + { + // Loop through the child pinsets + for (childPinsetIndex = 0; childPinsetIndex < DR_PINSET_COUNT; childPinsetIndex++) + { + if (gpumgrUpdateSliLinkRouting(pGpuLoop, pGpuChild, SLI_BT_NVLINK, + parentPinsetIndex, childPinsetIndex, NV_FALSE)) + { + // update link Output Mask + *pSliLinkOutputMask |= (NVBIT(pGpuLoop->gpuInstance) | NVBIT(pGpuChild->gpuInstance)); + + // Since we found the connection, don't even test any + // other ChildPinset for this connected ParentPinset. + break; + } + } // for (ChildPinset + } // for (ParentPinset + pGpuChild = gpumgrGetNextGpu(gpuMask, &gpuIndexChild); + } // while (pGpuChild) + pGpuLoop = gpumgrGetNextGpu(gpuMask, &gpuIndex); + } // while (pGpu) +} diff --git a/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c b/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c index 0014e9feb..a5c7ef6ed 100644 --- a/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c +++ b/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c @@ -23,6 +23,7 @@ #include "gpu/gpu.h" #include "published/turing/tu102/dev_vm.h" #include "published/turing/tu102/hwproject.h" +#include "jt.h" /*! * @brief Returns SR-IOV capabilities @@ -111,6 +112,28 @@ NvU32 gpuGetPhysAddrWidth_TU102 // static const GPUCHILDPRESENT gpuChildrenPresent_TU102[] = { + { classId(OBJFUSE), 1, }, + { classId(OBJSEQ), 1, }, + { classId(GpuMutexMgr), 1, }, + { classId(OBJTMR), 1, }, + { classId(GraphicsManager), 1, }, + { classId(MIGManager), 1, }, + { classId(KernelMIGManager), 1, }, + { classId(KernelGraphicsManager), 1, }, + { classId(OBJVBIOS), 1, }, + { classId(OBJDCB), 1, }, + { classId(OBJGPIO), 1, }, + { classId(I2c), 1, }, + { classId(Spi), 1, }, + { classId(KernelRc), 1, }, + { classId(OBJRC), 1, }, + { classId(OBJSTEREO), 1, }, + { classId(Intr), 1, }, + { classId(OBJINFOROM), 1, }, + { classId(NvDebugDump), 1, }, + { classId(SMDebugger), 1, }, + { classId(OBJGPULOG), 1, }, + { classId(OBJGPUMON), 1, }, {classId(OBJSWENG), 1}, {classId(OBJUVM), 1}, {classId(OBJACR), 1}, @@ -138,18 +161,10 @@ static const GPUCHILDPRESENT gpuChildrenPresent_TU102[] = {classId(OBJFIFO), 1}, {classId(OBJGMMU), 1}, {classId(KernelGmmu), 1}, - {classId(OBJGPULOG), 1}, - {classId(OBJGPUMON), 1}, - {classId(GraphicsManager), 1}, - {classId(MIGManager), 1}, - {classId(KernelMIGManager), 1}, - {classId(KernelGraphicsManager), 1}, {classId(Graphics), 1}, {classId(KernelGraphics), 1}, {classId(OBJHDACODEC), 1}, {classId(OBJHWPM), 1}, - {classId(OBJINFOROM), 1}, - {classId(Intr), 1}, {classId(Lpwr ), 1}, {classId(OBJLSFM), 1}, {classId(OBJMC), 1}, @@ -157,7 +172,6 @@ static const GPUCHILDPRESENT gpuChildrenPresent_TU102[] = {classId(PrivRing), 1}, {classId(SwIntr), 1}, {classId(OBJMSENC), 1}, - {classId(NvDebugDump), 1}, {classId(KernelNvlink), 1}, {classId(Nvlink), 1}, {classId(Perf), 1}, @@ -168,10 +182,8 @@ static const GPUCHILDPRESENT gpuChildrenPresent_TU102[] = {classId(OBJSEC2), 1}, {classId(Gsp), 1}, {classId(Therm), 1}, - {classId(OBJTMR), 1}, {classId(OBJVOLT), 1}, {classId(OBJGRIDDISPLAYLESS), 1}, - {classId(OBJFAS), 1}, {classId(OBJVMMU), 1}, {classId(KernelSec2), 1}, {classId(KernelGsp), 1}, @@ -179,6 +191,28 @@ static const GPUCHILDPRESENT gpuChildrenPresent_TU102[] = static const GPUCHILDPRESENT gpuChildrenPresent_TU104[] = { + { classId(OBJFUSE), 1, }, + { classId(OBJSEQ), 1, }, + { classId(GpuMutexMgr), 1, }, + { classId(OBJTMR), 1, }, + { classId(GraphicsManager), 1, }, + { classId(MIGManager), 1, }, + { classId(KernelMIGManager), 1, }, + { classId(KernelGraphicsManager), 1, }, + { classId(OBJVBIOS), 1, }, + { classId(OBJDCB), 1, }, + { classId(OBJGPIO), 1, }, + { classId(I2c), 1, }, + { classId(Spi), 1, }, + { classId(KernelRc), 1, }, + { classId(OBJRC), 1, }, + { classId(OBJSTEREO), 1, }, + { classId(Intr), 1, }, + { classId(OBJINFOROM), 1, }, + { classId(NvDebugDump), 1, }, + { classId(SMDebugger), 1, }, + { classId(OBJGPULOG), 1, }, + { classId(OBJGPUMON), 1, }, {classId(OBJSWENG), 1}, {classId(OBJUVM), 1}, {classId(OBJACR), 1}, @@ -206,18 +240,10 @@ static const GPUCHILDPRESENT gpuChildrenPresent_TU104[] = {classId(OBJFIFO), 1}, {classId(OBJGMMU), 1}, {classId(KernelGmmu), 1}, - {classId(OBJGPULOG), 1}, - {classId(OBJGPUMON), 1}, - {classId(GraphicsManager), 1}, - {classId(MIGManager), 1}, - {classId(KernelMIGManager), 1}, - {classId(KernelGraphicsManager), 1}, {classId(Graphics), 1}, {classId(KernelGraphics), 1}, {classId(OBJHDACODEC), 1}, {classId(OBJHWPM), 1}, - {classId(OBJINFOROM), 1}, - {classId(Intr), 1}, {classId(Lpwr ), 1}, {classId(OBJLSFM), 1}, {classId(OBJMC), 1}, @@ -225,7 +251,6 @@ static const GPUCHILDPRESENT gpuChildrenPresent_TU104[] = {classId(PrivRing), 1}, {classId(SwIntr), 1}, {classId(OBJMSENC), 1}, - {classId(NvDebugDump), 1}, {classId(KernelNvlink), 1}, {classId(Nvlink), 1}, {classId(Perf), 1}, @@ -236,10 +261,8 @@ static const GPUCHILDPRESENT gpuChildrenPresent_TU104[] = {classId(OBJSEC2), 1}, {classId(Gsp), 1}, {classId(Therm), 1}, - {classId(OBJTMR), 1}, {classId(OBJVOLT), 1}, {classId(OBJGRIDDISPLAYLESS), 1}, - {classId(OBJFAS), 1}, {classId(OBJVMMU), 1}, {classId(KernelSec2), 1}, {classId(KernelGsp), 1}, @@ -247,6 +270,28 @@ static const GPUCHILDPRESENT gpuChildrenPresent_TU104[] = static const GPUCHILDPRESENT gpuChildrenPresent_TU106[] = { + { classId(OBJFUSE), 1, }, + { classId(OBJSEQ), 1, }, + { classId(GpuMutexMgr), 1, }, + { classId(OBJTMR), 1, }, + { classId(GraphicsManager), 1, }, + { classId(MIGManager), 1, }, + { classId(KernelMIGManager), 1, }, + { classId(KernelGraphicsManager), 1, }, + { classId(OBJVBIOS), 1, }, + { classId(OBJDCB), 1, }, + { classId(OBJGPIO), 1, }, + { classId(I2c), 1, }, + { classId(Spi), 1, }, + { classId(KernelRc), 1, }, + { classId(OBJRC), 1, }, + { classId(OBJSTEREO), 1, }, + { classId(Intr), 1, }, + { classId(OBJINFOROM), 1, }, + { classId(NvDebugDump), 1, }, + { classId(SMDebugger), 1, }, + { classId(OBJGPULOG), 1, }, + { classId(OBJGPUMON), 1, }, {classId(OBJSWENG), 1}, {classId(OBJUVM), 1}, {classId(OBJACR), 1}, @@ -272,18 +317,10 @@ static const GPUCHILDPRESENT gpuChildrenPresent_TU106[] = {classId(OBJFIFO), 1}, {classId(OBJGMMU), 1}, {classId(KernelGmmu), 1}, - {classId(OBJGPULOG), 1}, - {classId(OBJGPUMON), 1}, - {classId(GraphicsManager), 1}, - {classId(MIGManager), 1}, - {classId(KernelMIGManager), 1}, - {classId(KernelGraphicsManager), 1}, {classId(Graphics), 1}, {classId(KernelGraphics), 1}, {classId(OBJHDACODEC), 1}, {classId(OBJHWPM), 1}, - {classId(OBJINFOROM), 1}, - {classId(Intr), 1}, {classId(Lpwr ), 1}, {classId(OBJLSFM), 1}, {classId(OBJMC), 1}, @@ -291,7 +328,6 @@ static const GPUCHILDPRESENT gpuChildrenPresent_TU106[] = {classId(PrivRing), 1}, {classId(SwIntr), 1}, {classId(OBJMSENC), 1}, - {classId(NvDebugDump), 1}, {classId(KernelNvlink), 1}, {classId(Nvlink), 1}, {classId(Perf), 1}, @@ -302,10 +338,8 @@ static const GPUCHILDPRESENT gpuChildrenPresent_TU106[] = {classId(OBJSEC2), 1}, {classId(Gsp), 1}, {classId(Therm), 1}, - {classId(OBJTMR), 1}, {classId(OBJVOLT), 1}, {classId(OBJGRIDDISPLAYLESS), 1}, - {classId(OBJFAS), 1}, {classId(OBJVMMU), 1}, {classId(KernelSec2), 1}, {classId(KernelGsp), 1}, @@ -332,3 +366,38 @@ gpuGetChildrenPresent_TU106(OBJGPU *pGpu, NvU32 *pNumEntries) return gpuChildrenPresent_TU106; } +/*! + * @brief Check if the DSM JT version is correct + * + * @param pGpu OBJGPU pointer + * + * @return NV_OK if DSM version matches otherwise NV_ERR_INVALID_PARAMETER + */ +NV_STATUS +gpuJtVersionSanityCheck_TU102 +( + OBJGPU *pGpu +) +{ + NV_STATUS status = NV_OK; + + if (!IS_SILICON(pGpu) || NV_IS_MODS) + { + goto gpuJtVersionSanityCheck_TU102_EXIT; + } + + if (FLD_TEST_DRF(_JT_FUNC, _CAPS, _JT_ENABLED, _TRUE, pGpu->acpiMethodData.jtMethodData.jtCaps)) + { + if (!(pGpu->acpiMethodData.jtMethodData.jtRevId == NV_JT_FUNC_CAPS_REVISION_ID_2_00)) + { + NV_PRINTF(LEVEL_ERROR, + "JT Version mismatch 0x%x\n", pGpu->acpiMethodData.jtMethodData.jtRevId); + DBG_BREAKPOINT(); + status = NV_ERR_INVALID_PARAMETER; + goto gpuJtVersionSanityCheck_TU102_EXIT; + } + } + +gpuJtVersionSanityCheck_TU102_EXIT: + return status; +} diff --git a/src/nvidia/src/kernel/gpu/pmu/arch/ada/kern_pmu_ad102.c b/src/nvidia/src/kernel/gpu/bif/arch/ada/kernel_bif_ad102.c similarity index 83% rename from src/nvidia/src/kernel/gpu/pmu/arch/ada/kern_pmu_ad102.c rename to src/nvidia/src/kernel/gpu/bif/arch/ada/kernel_bif_ad102.c index b7755d6b3..29fe907f5 100644 --- a/src/nvidia/src/kernel/gpu/pmu/arch/ada/kern_pmu_ad102.c +++ b/src/nvidia/src/kernel/gpu/bif/arch/ada/kernel_bif_ad102.c @@ -22,32 +22,31 @@ */ #include "os/os.h" -#include "gpu/pmu/kern_pmu.h" +#include "gpu/bif/kernel_bif.h" #include "published/ada/ad102/dev_bus.h" #include "published/ada/ad102/dev_bus_addendum.h" -static NvBool _kpmuPreOsCheckErotGrantAllowed_AD102(OBJGPU *pGpu, void *pVoid); +static NvBool _kbifPreOsCheckErotGrantAllowed_AD102(OBJGPU *pGpu, void *pVoid); /*! * Signals preOs to have eRoT hand over control of EEPROM to RM * * @param[in] pGpu OBJGPU pointer - * @param[in] pKernelPmu KernelPmu pointer + * @param[in] pKernelBif KernelBif pointer * * @returns NV_OK if RM has control of the EEPROM * @returns NV_ERR_TIMEOUT if preOs fails to hand over control of the EEPROM * */ NV_STATUS -kpmuPreOsGlobalErotGrantRequest_AD102 +kbifPreOsGlobalErotGrantRequest_AD102 ( OBJGPU *pGpu, - KernelPmu *pKernelPmu + KernelBif *pKernelBif ) { NV_STATUS status = NV_OK; - RMTIMEOUT timeout; NvU32 reg = GPU_REG_RD32(pGpu, NV_PBUS_SW_GLOBAL_EROT_GRANT); // Invalid value suggests that there is no ERoT @@ -57,7 +56,7 @@ kpmuPreOsGlobalErotGrantRequest_AD102 } // Check if grant has already been allowed - if (_kpmuPreOsCheckErotGrantAllowed_AD102(pGpu, NULL)) + if (_kbifPreOsCheckErotGrantAllowed_AD102(pGpu, NULL)) { return status; } @@ -65,8 +64,7 @@ kpmuPreOsGlobalErotGrantRequest_AD102 reg = FLD_SET_DRF(_PBUS, _SW_GLOBAL_EROT_GRANT, _REQUEST, _SET, reg); GPU_REG_WR32(pGpu, NV_PBUS_SW_GLOBAL_EROT_GRANT, reg); - gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); - status = gpuTimeoutCondWait(pGpu, _kpmuPreOsCheckErotGrantAllowed_AD102, NULL, &timeout); + status = gpuTimeoutCondWait(pGpu, _kbifPreOsCheckErotGrantAllowed_AD102, NULL, NULL); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Timed out waiting for preOs to grant access to EEPROM\n"); @@ -76,7 +74,7 @@ kpmuPreOsGlobalErotGrantRequest_AD102 } static NvBool -_kpmuPreOsCheckErotGrantAllowed_AD102 +_kbifPreOsCheckErotGrantAllowed_AD102 ( OBJGPU *pGpu, void *pVoid diff --git a/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c b/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c index 126f7a2f8..453adde3a 100644 --- a/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c +++ b/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c @@ -36,8 +36,6 @@ #include "os/os.h" -static void _kbifEnablePcieAtomics_GH100(OBJGPU *); - /*! * @brief Check if MSI is enabled in HW * @@ -272,7 +270,6 @@ kbifPcieConfigEnableRelaxedOrdering_GH100 KernelBif *pKernelBif ) { - NvU32 xveDevCtrlStatus; if (GPU_BUS_CFG_CYCLE_RD32(pGpu, @@ -339,7 +336,6 @@ kbifGetXveStatusBits_GH100 NvU32 *pStatus ) { - // control/status reg 0x68 NvU32 xtlDevCtrlStatus; @@ -419,7 +415,6 @@ kbifClearXveStatus_GH100 NvU32 *pStatus ) { - NvU32 xtlDevCtrlStatus; if (pStatus) @@ -462,7 +457,6 @@ kbifGetXveAerBits_GH100 NvU32 *pBits ) { - NvU32 xtlAerUncorr; NvU32 xtlAerCorr; @@ -538,7 +532,6 @@ kbifClearXveAer_GH100 NvU32 bits ) { - NvU32 xtlAerUncorr = 0; NvU32 xtlAerCorr = 0; @@ -611,7 +604,6 @@ kbifGetPciConfigSpacePriMirror_GH100 NvU32 *pSize ) { - *pBase = DEVICE_BASE(NV_EP_PCFGM); *pSize = DEVICE_EXTENT(NV_EP_PCFGM) - DEVICE_BASE(NV_EP_PCFGM) + 1; return NV_OK; @@ -658,7 +650,7 @@ kbifProbePcieReqAtomicCaps_GH100 pKernelBif->osPcieAtomicsOpMask = osAtomicsMask; // Program PCIe atomics register settings - _kbifEnablePcieAtomics_GH100(pGpu); + kbifEnablePcieAtomics_HAL(pGpu, pKernelBif); return; } @@ -666,12 +658,15 @@ kbifProbePcieReqAtomicCaps_GH100 /*! * @brief Enable PCIe atomics if PCIe hierarchy supports it * - * @param[in] pGpu GPU object pointer + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Kernel BIF object pointer + * */ -static void -_kbifEnablePcieAtomics_GH100 +void +kbifEnablePcieAtomics_GH100 ( - OBJGPU *pGpu + OBJGPU *pGpu, + KernelBif *pKernelBif ) { NvU32 regVal; diff --git a/src/nvidia/src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c b/src/nvidia/src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c index 08b974659..e94870e2c 100644 --- a/src/nvidia/src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c +++ b/src/nvidia/src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c @@ -631,3 +631,35 @@ kbifGetBusOptionsAddr_GM107 } return status; } + +NV_STATUS +kbifDisableSysmemAccess_GM107 +( + OBJGPU *pGpu, + KernelBif *pKernelBif, + NvBool bDisable +) +{ + NV_STATUS status = NV_OK; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS params = {0}; + + // Only support on Windows + NV_ASSERT_OR_RETURN(RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM, NV_ERR_NOT_SUPPORTED); + + params.bDisable = bDisable; + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS, + ¶ms, + sizeof(NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS)); + + // Only set the PDB in kernel if it was set in physical successfully + if (status == NV_OK) + { + pKernelBif->setProperty(pKernelBif, PDB_PROP_KBIF_SYSTEM_ACCESS_DISABLED, bDisable); + } + + return status; +} diff --git a/src/nvidia/src/kernel/gpu/bif/kernel_bif.c b/src/nvidia/src/kernel/gpu/bif/kernel_bif.c index fb93291b2..f1071457d 100644 --- a/src/nvidia/src/kernel/gpu/bif/kernel_bif.c +++ b/src/nvidia/src/kernel/gpu/bif/kernel_bif.c @@ -704,7 +704,6 @@ _kbifInitRegistryOverrides NV_PRINTF(LEVEL_INFO, "allow peermapping reg key = %d\n", data32); pKernelBif->peerMappingOverride = !!data32; } - } /*! @@ -780,7 +779,7 @@ kbifGetGpuLinkControlStatus static NvBool _doesBoardHaveMultipleGpusAndSwitch(OBJGPU *pGpu) { - if (((gpuIsMultiGpuBoard(pGpu, NULL)) || + if (((gpuIsMultiGpuBoard(pGpu)) || (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_GEMINI)))&& ((pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_PLX_PRESENT)) || (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_BR03_PRESENT)) || @@ -1114,3 +1113,41 @@ kbifControlGetPCIEInfo_IMPL pBusInfo->data = data; return NV_OK; } + +/*! + * @brief To ensure GPU is back on bus and accessible by polling device ID + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Kernel BIF object pointer + * + * @returns NV_OK + * @returns NV_ERR_TIMEOUT + */ +NV_STATUS +kbifPollDeviceOnBus_IMPL +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NV_STATUS status = NV_OK; + RMTIMEOUT timeout; + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + + while (osPciInitHandle(gpuGetDomain(pGpu), + gpuGetBus(pGpu), + gpuGetDevice(pGpu), 0, NULL, NULL) == NULL) + { + if (gpuCheckTimeout(pGpu, &timeout) == NV_ERR_TIMEOUT) + { + status = NV_ERR_TIMEOUT; + NV_PRINTF(LEVEL_ERROR, "Timeout polling GPU back on bus\n"); + DBG_BREAKPOINT(); + } + osDelayUs(100); + } + + return status; +} + diff --git a/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c b/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c index 9ea7f40b0..0b7591728 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c @@ -134,7 +134,6 @@ kbusSetBAR0WindowVidOffset_GH100 NvU64 vidOffset ) { - NV_ASSERT((vidOffset & 0xffff)==0); NV_ASSERT(kbusValidateBAR0WindowBase_HAL(pGpu, pKernelBus, vidOffset >> NV_XAL_EP_BAR0_WINDOW_BASE_SHIFT)); @@ -1402,12 +1401,8 @@ kbusAllocateFlaVaspace_GH100 inbandMsgCbParams.messageType = NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_RSP; inbandMsgCbParams.pCallback = &memorymulticastfabricTeamSetupResponseCallback; - - // - // Update this such that it indicates that Gpu lock shouldn't be taken - // when the callback is invoked - // - inbandMsgCbParams.wqItemFlags = 0; + inbandMsgCbParams.wqItemFlags = OS_QUEUE_WORKITEM_FLAGS_LOCK_SEMA | + OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW; status = knvlinkRegisterInbandCallback(pGpu, GPU_GET_KERNEL_NVLINK(pGpu), diff --git a/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c b/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c index f86741762..ebd867eb6 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c @@ -189,6 +189,7 @@ kbusSetupDefaultBar0Window kmemsysGetStaticConfig(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); NvU64 offsetBar0; + NV_ASSERT_OR_RETURN_VOID(!KBUS_BAR0_PRAMIN_DISABLED(pGpu)); // // Initialize BAR0 window to the last 1MB of FB. Since this is where it // should already be positioned by the vbios, this should not be an issue. @@ -282,7 +283,10 @@ kbusStateInitLockedKernel_GM107 } } - kbusSetupDefaultBar0Window(pGpu, pKernelBus); + if (!KBUS_BAR0_PRAMIN_DISABLED(pGpu)) + { + kbusSetupDefaultBar0Window(pGpu, pKernelBus); + } // // Initialize BAR2 before initializing BAR1. That way, we can use BAR2 @@ -324,6 +328,32 @@ kbusStateInitLocked_IMPL(OBJGPU *pGpu, KernelBus *pKernelBus) return NV_OK; } + if (KBUS_CPU_VISIBLE_BAR12_DISABLED(pGpu)) + { + NV_PRINTF(LEVEL_INFO, "C2C is being used, so disable CPU visible BAR1/2 now before they are setup\n"); + + pKernelBus->pciBarSizes[BUS_BAR_1] = 0; + pKernelBus->pciBarSizes[BUS_BAR_2] = 0; + + pKernelBus->bar1[GPU_GFID_PF].physAddr = 0; + pKernelBus->bar2[GPU_GFID_PF].physAddr = 0; + + pKernelBus->bar1[GPU_GFID_PF].apertureLength = 0; + pKernelBus->bar2[GPU_GFID_PF].cpuVisibleLimit = 0; + pKernelBus->bar2[GPU_GFID_PF].rmApertureLimit = 0; + + // + // For C2C case, there is no CPU visible BAR2. So CPU visible BAR2 + // window is removed and appended to CPU invisible BAR2 window. + // Only need to handle PF, since VF BAR1/2 is disabled for C2C case. + // + NV_ASSERT(pKernelBus->bar2[GPU_GFID_PF].cpuVisibleBase == 0); + pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleBase = pKernelBus->bar2[GPU_GFID_PF].cpuVisibleBase; + pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleBase = 0; + + pKernelBus->bUsePhysicalBar2InitPagetable = NV_FALSE; + } + if (RMCFG_FEATURE_PLATFORM_GSP) { NV_ASSERT_OK_OR_RETURN(kbusInitBar2_HAL(pGpu, pKernelBus, GPU_GFID_PF)); @@ -365,7 +395,8 @@ kbusStateLoad_GM107 if (!(flags & GPU_STATE_FLAGS_GC6_TRANSITION)) { - if (NULL == pKernelBus->virtualBar2[GPU_GFID_PF].pCpuMapping) + if (NULL == pKernelBus->virtualBar2[GPU_GFID_PF].pCpuMapping && + !KBUS_CPU_VISIBLE_BAR12_DISABLED(pGpu)) { NV_ASSERT_OK_OR_RETURN(kbusSetupBar2CpuAperture_HAL(pGpu, pKernelBus, GPU_GFID_PF)); } @@ -378,7 +409,7 @@ kbusStateLoad_GM107 // a hit on the GC6 exit times, so this verif only feature does not // come for free. // - if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING) && + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING) && !(IS_GPU_GC6_STATE_EXITING(pGpu) && pKernelBus->bSkipBar2TestOnGc6Exit)) { // Verify that BAR2 and the MMU actually works @@ -402,7 +433,8 @@ kbusStatePostLoad_GM107 NV_STATUS status = NV_OK; KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); - if ( ! IS_GPU_GC6_STATE_EXITING(pGpu)) + if ( ! IS_GPU_GC6_STATE_EXITING(pGpu) && + !KBUS_CPU_VISIBLE_BAR12_DISABLED(pGpu)) { // Bar1 is created once per Gpu on each Gpu call to kbusStatePostLoad_GM107 if ((status = kbusInitBar1_HAL(pGpu, pKernelBus, GPU_GFID_PF)) != NV_OK) @@ -460,9 +492,6 @@ kbusStateUnload_GM107 NV_STATUS status = NV_OK; KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); - if (IS_VIRTUAL(pGpu) && !(flags & GPU_STATE_FLAGS_PRESERVING)) - return NV_OK; - if ((pKernelBif != NULL) && (!pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_P2P_READS_DISABLED) || @@ -479,12 +508,9 @@ kbusStateUnload_GM107 { if (!IS_GPU_GC6_STATE_ENTERING(pGpu)) { - status = kbusTeardownBar2CpuAperture_HAL(pGpu, pKernelBus, GPU_GFID_PF); - if (!IS_VIRTUAL_WITH_SRIOV(pGpu)) - { - // Do not use BAR2 physical mode for bootstrapping BAR2 across S/R. - pKernelBus->bUsePhysicalBar2InitPagetable = NV_FALSE; - } + status = kbusTeardownBar2CpuAperture_HAL(pGpu, pKernelBus, GPU_GFID_PF); + // Do not use BAR2 physical mode for bootstrapping BAR2 across S/R. + pKernelBus->bUsePhysicalBar2InitPagetable = NV_FALSE; } } else @@ -539,6 +565,9 @@ kbusInitBar1_GM107(OBJGPU *pGpu, KernelBus *pKernelBus, NvU32 gfid) return rmStatus; } + if (IsT234(pGpu) && pGpu->getProperty(pGpu, PDB_PROP_GPU_ZERO_FB)) + return NV_OK; + // // For BAR address spaces, leave a valid PTE pointed to page 0. // According to page 196 of revision 2.1 of the PCI spec, prefetchable @@ -960,8 +989,11 @@ kbusInitBar2_GM107 return NV_OK; } - status = kbusSetupBar2CpuAperture_HAL(pGpu, pKernelBus, gfid); - NV_ASSERT_OR_GOTO(status == NV_OK, cleanup); + if (!KBUS_CPU_VISIBLE_BAR12_DISABLED(pGpu)) + { + status = kbusSetupBar2CpuAperture_HAL(pGpu, pKernelBus, gfid); + NV_ASSERT_OR_GOTO(status == NV_OK, cleanup); + } if (KBUS_BAR2_ENABLED(pKernelBus)) { @@ -1279,6 +1311,7 @@ kbusSetupBar2GpuVaSpace_GM107 OBJEHEAP *pVASpaceHeap; MEMORY_DESCRIPTOR *pPageLevelsMemDesc = NULL; NvU32 allocSize; + NvBool bUseStagingBuffer = NV_FALSE; // // Nothing to be done in guest in the paravirtualization case or if @@ -1326,7 +1359,8 @@ kbusSetupBar2GpuVaSpace_GM107 pKernelBus->bar2[gfid].pteBase += memmgrGetRsvdMemoryBase(pMemoryManager); } - if (IS_GFID_PF(gfid)) + if (IS_GFID_PF(gfid) && + !KBUS_BAR0_PRAMIN_DISABLED(pGpu)) { // Setup BAR0 window for page directory/table updates during BAR2 bootstrap status = kbusSetupBar0WindowBeforeBar2Bootstrap_HAL(pGpu, pKernelBus, &origVidOffset); @@ -1395,80 +1429,6 @@ kbusSetupBar2GpuVaSpace_GM107 } } - // Get the MMU format for BAR2. - pKernelBus->bar2[gfid].pFmt = kgmmuFmtGet(pKernelGmmu, GMMU_FMT_VERSION_DEFAULT, 0); - NV_ASSERT_OR_GOTO(NULL != pKernelBus->bar2[gfid].pFmt, cleanup); - walkFlags.bUseIterative = gpuIsIterativeMmuWalkerEnabled(pGpu); - - // - // Initialize/allocate walker staging buffer only if PTEs in FBMEM - // and we are currently bootstrapping BAR2. - // - if (pKernelBus->bar2[gfid].pWalkStagingBuffer == NULL && - pKernelBus->PTEBAR2Aperture == ADDR_FBMEM && - pKernelBus->bar2[gfid].bBootstrap) - { - pKernelBus->bar2[gfid].pWalkStagingBuffer = kbusCreateStagingMemdesc(pGpu); - } - - // Create the MMU_WALKER state - status = mmuWalkCreate(pKernelBus->bar2[gfid].pFmt->pRoot, - NULL, - &g_bar2WalkCallbacks, - walkFlags, - &pWalk, - (struct MMU_WALK_MEMDESC *) pKernelBus->bar2[gfid].pWalkStagingBuffer); - NV_ASSERT_OR_GOTO(NV_OK == status, cleanup); - pKernelBus->bar2[gfid].pWalk = pWalk; - - // We want to lock the small page table - pLevelFmt = mmuFmtFindLevelWithPageShift(pKernelBus->bar2[gfid].pFmt->pRoot, - RM_PAGE_SHIFT); - - // Setup walk user context. - userCtx.pGpu = pGpu; - userCtx.gfid = gfid; - - NV_ASSERT_OR_RETURN(pWalk != NULL, NV_ERR_INVALID_STATE); - - // Pre-reserve and init 4K tables through BAR0 window (bBootstrap) mode. - mmuWalkSetUserCtx(pWalk, &userCtx); - - if (pKernelBus->bar2[gfid].cpuVisibleLimit != 0) - { - status = mmuWalkReserveEntries(pWalk, pLevelFmt, pKernelBus->bar2[gfid].cpuVisibleBase, - pKernelBus->bar2[gfid].cpuVisibleLimit, NV_FALSE); - NV_ASSERT_OR_GOTO(NV_OK == status, cleanup); - status = mmuWalkSparsify(pWalk, pKernelBus->bar2[gfid].cpuVisibleBase, pKernelBus->bar2[gfid].cpuVisibleLimit, NV_TRUE); - NV_ASSERT_OR_GOTO(NV_OK == status, cleanup); - } - - if (pKernelBus->bar2[gfid].cpuInvisibleLimit != 0) - { - status = mmuWalkReserveEntries(pWalk, pLevelFmt, pKernelBus->bar2[gfid].cpuInvisibleBase, - pKernelBus->bar2[gfid].cpuInvisibleLimit, NV_FALSE); - NV_ASSERT_OR_GOTO(NV_OK == status, cleanup); - status = mmuWalkSparsify(pWalk, pKernelBus->bar2[gfid].cpuInvisibleBase, pKernelBus->bar2[gfid].cpuInvisibleLimit, NV_TRUE); - NV_ASSERT_OR_GOTO(NV_OK == status, cleanup); - } - - NV_PRINTF(LEVEL_INFO, "(BAR2 0x%llx, PDB 0x%llx): vaLimit = 0x%llx\n", - pKernelBus->bar2[gfid].instBlockBase, pKernelBus->bar2[gfid].pdeBase, - pKernelBus->bar2[gfid].vaLimit); - - if (NULL != pKernelBus->bar2[gfid].pPDEMemDescForBootstrap) - { - memdescSetPageSize(pKernelBus->bar2[gfid].pPDEMemDescForBootstrap, AT_GPU, - FERMI_SMALL_PAGESIZE); - pKernelBus->virtualBar2[gfid].pPDB = pKernelBus->bar2[gfid].pPDEMemDescForBootstrap; - } - else - { - memdescSetPageSize(pKernelBus->bar2[gfid].pPDEMemDesc, AT_GPU, - FERMI_SMALL_PAGESIZE); - pKernelBus->virtualBar2[gfid].pPDB = pKernelBus->bar2[gfid].pPDEMemDesc; - } - // // Setup a memdesc that covers all of BAR2's page levels. // @@ -1500,6 +1460,92 @@ kbusSetupBar2GpuVaSpace_GM107 break; } pKernelBus->virtualBar2[gfid].pPageLevelsMemDesc = pPageLevelsMemDesc; + + if (KBUS_BAR0_PRAMIN_DISABLED(pGpu)) + { + NV_ASSERT_OK_OR_GOTO(status, kbusInitVirtualBar2_HAL(pGpu, pKernelBus), cleanup); + } + } + + // Get the MMU format for BAR2. + pKernelBus->bar2[gfid].pFmt = kgmmuFmtGet(pKernelGmmu, GMMU_FMT_VERSION_DEFAULT, 0); + NV_ASSERT_OR_GOTO(NULL != pKernelBus->bar2[gfid].pFmt, cleanup); + walkFlags.bUseIterative = gpuIsIterativeMmuWalkerEnabled(pGpu); + + // + // Initialize/allocate walker staging buffer only if PTEs in FBMEM + // and we are currently bootstrapping BAR2. + // + if (pKernelBus->bar2[gfid].pWalkStagingBuffer == NULL && + pKernelBus->PTEBAR2Aperture == ADDR_FBMEM && + pKernelBus->bar2[gfid].bBootstrap) + { + bUseStagingBuffer = NV_TRUE; + pKernelBus->bar2[gfid].pWalkStagingBuffer = kbusCreateStagingMemdesc(pGpu); + } + + // Create the MMU_WALKER state + status = mmuWalkCreate(pKernelBus->bar2[gfid].pFmt->pRoot, + NULL, + &g_bar2WalkCallbacks, + walkFlags, + &pWalk, + (struct MMU_WALK_MEMDESC *) pKernelBus->bar2[gfid].pWalkStagingBuffer); + NV_ASSERT_OR_GOTO(NV_OK == status, cleanup); + pKernelBus->bar2[gfid].pWalk = pWalk; + + // We want to lock the small page table + pLevelFmt = mmuFmtFindLevelWithPageShift(pKernelBus->bar2[gfid].pFmt->pRoot, + RM_PAGE_SHIFT); + + // Setup walk user context. + userCtx.pGpu = pGpu; + userCtx.gfid = gfid; + + NV_ASSERT_OR_RETURN(pWalk != NULL, NV_ERR_INVALID_STATE); + + // Pre-reserve and init 4K tables through BAR0 window (bBootstrap) mode. + mmuWalkSetUserCtx(pWalk, &userCtx); + + if (pKernelBus->bar2[gfid].cpuVisibleLimit != 0) + { + status = mmuWalkReserveEntries(pWalk, pLevelFmt, pKernelBus->bar2[gfid].cpuVisibleBase, + pKernelBus->bar2[gfid].cpuVisibleLimit, NV_FALSE); + NV_ASSERT_OR_GOTO(NV_OK == status, cleanup); + status = mmuWalkSparsify(pWalk, + pKernelBus->bar2[gfid].cpuVisibleBase, + pKernelBus->bar2[gfid].cpuVisibleLimit, + bUseStagingBuffer); + NV_ASSERT_OR_GOTO(NV_OK == status, cleanup); + } + + if (pKernelBus->bar2[gfid].cpuInvisibleLimit != 0) + { + status = mmuWalkReserveEntries(pWalk, pLevelFmt, pKernelBus->bar2[gfid].cpuInvisibleBase, + pKernelBus->bar2[gfid].cpuInvisibleLimit, NV_FALSE); + NV_ASSERT_OR_GOTO(NV_OK == status, cleanup); + status = mmuWalkSparsify(pWalk, + pKernelBus->bar2[gfid].cpuInvisibleBase, + pKernelBus->bar2[gfid].cpuInvisibleLimit, + bUseStagingBuffer); + NV_ASSERT_OR_GOTO(NV_OK == status, cleanup); + } + + NV_PRINTF(LEVEL_INFO, "(BAR2 0x%llx, PDB 0x%llx): vaLimit = 0x%llx\n", + pKernelBus->bar2[gfid].instBlockBase, pKernelBus->bar2[gfid].pdeBase, + pKernelBus->bar2[gfid].vaLimit); + + if (NULL != pKernelBus->bar2[gfid].pPDEMemDescForBootstrap) + { + memdescSetPageSize(pKernelBus->bar2[gfid].pPDEMemDescForBootstrap, AT_GPU, + FERMI_SMALL_PAGESIZE); + pKernelBus->virtualBar2[gfid].pPDB = pKernelBus->bar2[gfid].pPDEMemDescForBootstrap; + } + else + { + memdescSetPageSize(pKernelBus->bar2[gfid].pPDEMemDesc, AT_GPU, + FERMI_SMALL_PAGESIZE); + pKernelBus->virtualBar2[gfid].pPDB = pKernelBus->bar2[gfid].pPDEMemDesc; } kbusPatchBar2Pdb_HAL(pGpu, pKernelBus); @@ -1519,7 +1565,8 @@ cleanup: mmuWalkSetUserCtx(pWalk, NULL); } - if (!kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus) && IS_GFID_PF(gfid)) + if (!kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus) && IS_GFID_PF(gfid) && + !KBUS_BAR0_PRAMIN_DISABLED(pGpu)) { // Restore BAR0 window after BAR2 bootstrap kbusRestoreBar0WindowAfterBar2Bootstrap_HAL(pGpu, pKernelBus, origVidOffset); @@ -1583,7 +1630,9 @@ kbusTeardownBar2GpuVaSpace_GM107 mmuWalkSetUserCtx(pKernelBus->bar2[gfid].pWalk, &userCtx); - if (kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus) || IS_GFID_VF(gfid)) + if (kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus) || + IS_GFID_VF(gfid) || + KBUS_BAR0_PRAMIN_DISABLED(pGpu)) { mmuWalkLevelInstancesForceFree(pKernelBus->bar2[gfid].pWalk); } @@ -1696,6 +1745,8 @@ kbusSetupBar0WindowBeforeBar2Bootstrap_GM107 { NV_STATUS status = NV_OK; + NV_ASSERT_OR_RETURN(!KBUS_BAR0_PRAMIN_DISABLED(pGpu), + NV_ERR_INVALID_STATE); // Check that Bar2 Page Dir starts at or after bar0 window vid offset if (ADDR_FBMEM == pKernelBus->PDEBAR2Aperture || ADDR_FBMEM == pKernelBus->PTEBAR2Aperture) @@ -1741,6 +1792,8 @@ kbusRestoreBar0WindowAfterBar2Bootstrap_GM107 NvU64 origVidOffset ) { + NV_ASSERT_OR_RETURN_VOID(!KBUS_BAR0_PRAMIN_DISABLED(pGpu)); + NV_ASSERT(pKernelBus->bar2[GPU_GFID_PF].bBootstrap); pKernelBus->bar2[GPU_GFID_PF].bBootstrap = NV_FALSE; @@ -1941,25 +1994,22 @@ _kbusWalkCBMapNextEntries_RmAperture else { // Use BAR0 or nvlink if available - sizeInDWord = (NvU32)NV_CEIL(pLevelFmt->entrySize, sizeof(NvU32)); NvU64 entryStart = memdescGetPhysAddr(pMemDesc, FORCE_VMMU_TRANSLATION(pMemDesc, AT_GPU), entryOffset); - NvU32 i; NvU8 *pMapping = NULL; - if (pKernelBus->coherentCpuMapping.bCoherentCpuMapping) + if (KBUS_BAR0_PRAMIN_DISABLED(pGpu)) { - NV_ASSERT_OR_RETURN_VOID(pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING)); pMapping = kbusMapCoherentCpuMapping_HAL(pGpu, pKernelBus, pMemDesc); NV_ASSERT_OR_RETURN_VOID(pMapping != NULL); - for (i = 0; i < sizeInDWord; i++) - { - MEM_WR32(pMapping + entryOffset + sizeof(NvU32)*i, - entryValue.v32[i]); - } + portMemCopy(pMapping + entryStart, + pLevelFmt->entrySize, entryValue.v8, + pLevelFmt->entrySize); kbusUnmapCoherentCpuMapping_HAL(pGpu, pKernelBus, pMemDesc); } else { + sizeInDWord = (NvU32)NV_CEIL(pLevelFmt->entrySize, sizeof(NvU32)); + NvU32 i; for (i = 0; i < sizeInDWord; i++) { // BAR0 write. @@ -3700,7 +3750,15 @@ NV_STATUS kbusSetBarsApertureSize_GM107 else { pKernelBus->bar2[gfid].cpuVisibleLimit = (BUS_BAR2_APERTURE_MB << 20) - 1; - pKernelBus->bar2[gfid].rmApertureLimit = (BUS_BAR2_RM_APERTURE_MB << 20) - 1; + + if (pKernelBus->bIsEntireBar2RegionVirtuallyAddressible) + { + pKernelBus->bar2[gfid].rmApertureLimit = pKernelBus->bar2[gfid].cpuVisibleLimit; + } + else + { + pKernelBus->bar2[gfid].rmApertureLimit = (BUS_BAR2_RM_APERTURE_MB << 20) - 1; + } } } diff --git a/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c b/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c index 1d73b55db..3be71c415 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c @@ -547,7 +547,7 @@ _kbusRemoveNvlinkPeerMapping status = knvlinkSyncLinkMasksAndVbiosInfo(pGpu0, pKernelNvlink0); if (status != NV_OK) { - NV_ASSERT(status == NV_OK); + NV_ASSERT(status != NV_OK); return status; } diff --git a/src/nvidia/src/kernel/gpu/bus/arch/volta/kern_bus_gv100.c b/src/nvidia/src/kernel/gpu/bus/arch/volta/kern_bus_gv100.c index 62ac954ae..bb1170777 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/volta/kern_bus_gv100.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/volta/kern_bus_gv100.c @@ -136,7 +136,7 @@ kbusMapCoherentCpuMapping_GV100 PMEMORY_DESCRIPTOR pMemDesc ) { - RmPhysAddr startAddr = memdescGetPhysAddr(pMemDesc, AT_GPU, 0); + RmPhysAddr startAddr = memdescGetPhysAddr(pMemDesc, FORCE_VMMU_TRANSLATION(pMemDesc, AT_GPU), 0); NvU64 size = memdescGetSize(pMemDesc); RmPhysAddr endAddr = startAddr + size - 1; RmPhysAddr rangeStart = 0; @@ -186,7 +186,7 @@ kbusUnmapCoherentCpuMapping_GV100 PMEMORY_DESCRIPTOR pMemDesc ) { - RmPhysAddr startAddr = pMemDesc->_pteArray[0] + pMemDesc->PteAdjust; + RmPhysAddr startAddr = memdescGetPhysAddr(pMemDesc, FORCE_VMMU_TRANSLATION(pMemDesc, AT_GPU), 0); NvU64 size = memdescGetSize(pMemDesc); RmPhysAddr endAddr = startAddr + size - 1; NvU32 i = 0; diff --git a/src/nvidia/src/kernel/gpu/bus/kern_bus.c b/src/nvidia/src/kernel/gpu/bus/kern_bus.c index 801b6f2a8..26f0caa6a 100644 --- a/src/nvidia/src/kernel/gpu/bus/kern_bus.c +++ b/src/nvidia/src/kernel/gpu/bus/kern_bus.c @@ -393,10 +393,12 @@ kbusCommitBar2_KERNEL NvU32 flags ) { - // we will initialize bar2 to the default big page size of the system - NV_ASSERT_OK_OR_RETURN(kbusInitVirtualBar2_HAL(pGpu, pKernelBus)); - NV_ASSERT_OK_OR_RETURN(kbusSetupCpuPointerForBusFlush_HAL(pGpu, pKernelBus)); - + if (!KBUS_BAR0_PRAMIN_DISABLED(pGpu)) + { + // we will initialize bar2 to the default big page size of the system + NV_ASSERT_OK_OR_RETURN(kbusInitVirtualBar2_HAL(pGpu, pKernelBus)); + NV_ASSERT_OK_OR_RETURN(kbusSetupCpuPointerForBusFlush_HAL(pGpu, pKernelBus)); + } return NV_OK; } @@ -768,9 +770,9 @@ kbusPatchBar2Pdb_GSPCLIENT NvBool kbusCheckEngine_KERNEL ( - OBJGPU *pGpu, - KernelBus *pKernelBus, - ENGDESCRIPTOR engDesc + OBJGPU *pGpu, + KernelBus *pKernelBus, + ENGDESCRIPTOR engDesc ) { NvU32 rmEngineCaps[NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX] = {0}; @@ -786,15 +788,17 @@ kbusCheckEngine_KERNEL return NV_FALSE; } - for (i=0; iengineCaps[i]; } } NV_CHECK_OK_OR_ELSE(status, LEVEL_ERROR, - gpuGetRmEngineTypeCapMask(nv2080EngineCaps, NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX, rmEngineCaps), - return NV_FALSE); + gpuGetRmEngineTypeCapMask(nv2080EngineCaps, + NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX, + rmEngineCaps), + return NV_FALSE); switch (engDesc) { @@ -810,10 +814,7 @@ kbusCheckEngine_KERNEL // (b) RM offload (Kernel RM) where display is supported. // case ENG_KERNEL_DISPLAY: - if (IS_GSP_CLIENT(pGpu)) - return NV_TRUE; - else - return NV_FALSE; + return IS_GSP_CLIENT(pGpu); case ENG_BIF: case ENG_KERNEL_BIF: @@ -833,67 +834,51 @@ kbusCheckEngine_KERNEL return NV_TRUE; case ENG_CE(0): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_COPY0) ? NV_TRUE: NV_FALSE); case ENG_CE(1): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_COPY1) ? NV_TRUE: NV_FALSE); case ENG_CE(2): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_COPY2) ? NV_TRUE: NV_FALSE); case ENG_CE(3): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_COPY3) ? NV_TRUE: NV_FALSE); case ENG_CE(4): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_COPY4) ? NV_TRUE: NV_FALSE); case ENG_CE(5): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_COPY5) ? NV_TRUE: NV_FALSE); case ENG_CE(6): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_COPY6) ? NV_TRUE: NV_FALSE); case ENG_CE(7): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_COPY7) ? NV_TRUE: NV_FALSE); case ENG_CE(8): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_COPY8) ? NV_TRUE: NV_FALSE); case ENG_CE(9): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_COPY9) ? NV_TRUE: NV_FALSE); + return !!NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, + RM_ENGINE_TYPE_COPY(GET_CE_IDX(engDesc))); + case ENG_MSENC(0): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVENC0) ? NV_TRUE: NV_FALSE); case ENG_MSENC(1): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVENC1) ? NV_TRUE: NV_FALSE); case ENG_MSENC(2): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVENC2) ? NV_TRUE: NV_FALSE); + return !!NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, + RM_ENGINE_TYPE_NVENC(GET_MSENC_IDX(engDesc))); case ENG_SEC2: - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_SEC2) ? NV_TRUE: NV_FALSE); + return !!NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, + RM_ENGINE_TYPE_SEC2); case ENG_NVDEC(0): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVDEC0) ? NV_TRUE: NV_FALSE); case ENG_NVDEC(1): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVDEC1) ? NV_TRUE: NV_FALSE); case ENG_NVDEC(2): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVDEC2) ? NV_TRUE: NV_FALSE); - case ENG_OFA: - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_OFA) ? NV_TRUE: NV_FALSE); case ENG_NVDEC(3): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVDEC3) ? NV_TRUE: NV_FALSE); case ENG_NVDEC(4): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVDEC4) ? NV_TRUE: NV_FALSE); case ENG_NVDEC(5): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVDEC5) ? NV_TRUE: NV_FALSE); case ENG_NVDEC(6): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVDEC6) ? NV_TRUE: NV_FALSE); case ENG_NVDEC(7): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVDEC7) ? NV_TRUE: NV_FALSE); + return !!NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, + RM_ENGINE_TYPE_NVDEC(GET_NVDEC_IDX(engDesc))); + + case ENG_OFA: + return !!NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, + RM_ENGINE_TYPE_OFA); case ENG_NVJPEG(0): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVJPEG0) ? NV_TRUE: NV_FALSE); case ENG_NVJPEG(1): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVJPEG1) ? NV_TRUE: NV_FALSE); case ENG_NVJPEG(2): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVJPEG2) ? NV_TRUE: NV_FALSE); case ENG_NVJPEG(3): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVJPEG3) ? NV_TRUE: NV_FALSE); case ENG_NVJPEG(4): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVJPEG4) ? NV_TRUE: NV_FALSE); case ENG_NVJPEG(5): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVJPEG5) ? NV_TRUE: NV_FALSE); case ENG_NVJPEG(6): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVJPEG6) ? NV_TRUE: NV_FALSE); case ENG_NVJPEG(7): - return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVJPEG7) ? NV_TRUE: NV_FALSE); + return !!NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, + RM_ENGINE_TYPE_NVJPEG(GET_NVJPEG_IDX(engDesc))); + case ENG_GR(1): case ENG_GR(2): case ENG_GR(3): @@ -906,10 +891,10 @@ kbusCheckEngine_KERNEL NV_ASSERT_OR_RETURN(pKernelFifo != NULL, NV_FALSE); - if (kfifoCheckEngine_HAL(pGpu, pKernelFifo, engDesc, &bSupported) == NV_OK) - return bSupported; - else - return NV_FALSE; + return (kfifoCheckEngine_HAL(pGpu, pKernelFifo, + engDesc, + &bSupported) == NV_OK && + bSupported); } case ENG_INVALID: @@ -956,21 +941,14 @@ kbusGetDeviceCaps_IMPL OBJSYS *pSys = SYS_GET_INSTANCE(); OBJCL *pCl = SYS_GET_CL(pSys); NvU8 tempCaps[NV0080_CTRL_HOST_CAPS_TBL_SIZE], temp; - NvBool bVirtualP2P; NvBool bExplicitCacheFlushRequired; NV_ASSERT(!gpumgrGetBcEnabledStatus(pGpu)); portMemSet(tempCaps, 0, NV0080_CTRL_HOST_CAPS_TBL_SIZE); - /*! On KEPLER+, mailbox protocol based P2P transactions goes through virtual to - * physical translation (on request side) */ - bVirtualP2P = IsdMAXWELLorBetter(pGpu); - if (bVirtualP2P) - RMCTRL_SET_CAP(tempCaps, NV0080_CTRL_HOST_CAPS, _VIRTUAL_P2P); - /*! DMAs to/from cached memory need to have the cache flushed explicitly */ - bExplicitCacheFlushRequired = NVCPU_IS_ARM && + bExplicitCacheFlushRequired = NVCPU_IS_ARM && (RMCFG_FEATURE_PLATFORM_UNIX || RMCFG_FEATURE_PLATFORM_MODS_UNIX); if (bExplicitCacheFlushRequired || (!pCl->getProperty(pCL, PDB_PROP_CL_IS_CHIPSET_IO_COHERENT))) @@ -999,8 +977,6 @@ kbusGetDeviceCaps_IMPL NV0080_CTRL_HOST_CAPS, _P2P_4_WAY); RMCTRL_AND_CAP(pHostCaps, tempCaps, temp, NV0080_CTRL_HOST_CAPS, _P2P_8_WAY); - RMCTRL_AND_CAP(pHostCaps, tempCaps, temp, - NV0080_CTRL_HOST_CAPS, _VIRTUAL_P2P); RMCTRL_AND_CAP(pHostCaps, tempCaps, temp, NV0080_CTRL_HOST_CAPS, _GPU_COHERENT_MAPPING_SUPPORTED); @@ -1242,12 +1218,3 @@ kbusIsGpuP2pAlive_IMPL { return (pKernelBus->totalP2pObjectsAliveRefCount > 0); } - -/** - * @brief Setup VF BAR2 during hibernate resume - * - * @param[in] pGpu - * @param[in] pKernelBus - * @param[in] flags - */ - diff --git a/src/nvidia/src/kernel/gpu/bus/kern_bus_ctrl.c b/src/nvidia/src/kernel/gpu/bus/kern_bus_ctrl.c index 36a22da9c..5f484c167 100644 --- a/src/nvidia/src/kernel/gpu/bus/kern_bus_ctrl.c +++ b/src/nvidia/src/kernel/gpu/bus/kern_bus_ctrl.c @@ -656,3 +656,15 @@ diagapiCtrlCmdBusIsBar1Virtual_IMPL return NV_OK; } +NV_STATUS +subdeviceCtrlCmdBusSysmemAccess_IMPL +( + Subdevice* pSubdevice, + NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS* pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + + return kbifDisableSysmemAccess_HAL(pGpu, pKernelBif, pParams->bDisable); +} diff --git a/src/nvidia/src/kernel/gpu/bus/kern_bus_vbar2.c b/src/nvidia/src/kernel/gpu/bus/kern_bus_vbar2.c index 2e272b2fc..143469132 100644 --- a/src/nvidia/src/kernel/gpu/bus/kern_bus_vbar2.c +++ b/src/nvidia/src/kernel/gpu/bus/kern_bus_vbar2.c @@ -870,7 +870,7 @@ kbusMapBar2Aperture_SCRATCH return NULL; } - return portMemAllocNonPaged((NvU32)pMemDesc->Size); + return portMemAllocNonPaged(pMemDesc->Size); } /*! diff --git a/src/nvidia/src/kernel/gpu/bus/p2p_api.c b/src/nvidia/src/kernel/gpu/bus/p2p_api.c index 8a18fe10c..9d7ef9796 100644 --- a/src/nvidia/src/kernel/gpu/bus/p2p_api.c +++ b/src/nvidia/src/kernel/gpu/bus/p2p_api.c @@ -36,6 +36,166 @@ #include "class/cl503b.h" #include //FERMI_VASPACE_A +/*! + * @brief Helper function to reserve peer ids in non-GSP offload vGPU case. + */ +static +NV_STATUS +_p2papiReservePeerID +( + OBJGPU *pLocalGpu, + KernelBus *pLocalKernelBus, + OBJGPU *pRemoteGpu, + KernelBus *pRemoteKernelBus, + NV503B_ALLOC_PARAMETERS *pNv503bAllocParams, + P2PApi *pP2PApi, + NvU32 *peer1, + NvU32 *peer2, + NvBool bSpaAccessOnly +) +{ + NvU32 gpu0Instance = gpuGetInstance(pLocalGpu); + NvU32 gpu1Instance = gpuGetInstance(pRemoteGpu); + + // loopback request + if ((pNv503bAllocParams->hSubDevice == pNv503bAllocParams->hPeerSubDevice)) + { + *peer1 = *peer2 = 0; + } + else + { + // Check if a peer ID is already allocated for P2P from pLocalGpu to pRemoteGpu + *peer1 = kbusGetPeerId_HAL(pLocalGpu, pLocalKernelBus, pRemoteGpu); + + // Check if a peer ID is already allocated for P2P from pRemoteGpu to pLocalGpu + *peer2 = kbusGetPeerId_HAL(pRemoteGpu, pRemoteKernelBus, pLocalGpu); + } + + if (*peer1 != BUS_INVALID_PEER && *peer2 != BUS_INVALID_PEER) + { + goto update_mask; + } + else if (*peer1 == BUS_INVALID_PEER && *peer2 == BUS_INVALID_PEER) + { + // Get the peer ID pGpu0 should use for P2P over NVLINK to pGpu1i + *peer1 = kbusGetUnusedPeerId_HAL(pLocalGpu, pLocalKernelBus); + // If could not find a free peer ID, return error + if (*peer1 == BUS_INVALID_PEER) + { + NV_PRINTF(LEVEL_ERROR, + "GPU%d: peerID not available for NVLink P2P\n", + gpu0Instance); + return NV_ERR_GENERIC; + } + + // Reserve the peer ID for NVLink use + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kbusReserveP2PPeerIds_HAL(pLocalGpu, pLocalKernelBus, NVBIT(*peer1))); + + // Get the peer ID pGpu1 should use for P2P over NVLINK to pGpu0 + *peer2 = kbusGetUnusedPeerId_HAL(pRemoteGpu, pRemoteKernelBus); + // If could not find a free peer ID, return error + if (*peer2 == BUS_INVALID_PEER) + { + NV_PRINTF(LEVEL_ERROR, + "GPU%d: peerID not available for NVLink P2P\n", + gpu1Instance); + return NV_ERR_GENERIC; + } + + // Reserve the peer ID for NVLink use + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kbusReserveP2PPeerIds_HAL(pRemoteGpu, pRemoteKernelBus, NVBIT(*peer2))); + } + else + { + NV_PRINTF(LEVEL_ERROR, + "Unexpected state, either of the peer ID is invalid \n"); + return NV_ERR_GENERIC; + } + +update_mask: + // + // Does the mapping already exist between the given pair of GPUs using the peerIDs + // peer1 and peer2 respectively ? + // + if ((pLocalKernelBus->p2p.busNvlinkPeerNumberMask[gpu1Instance] & NVBIT(*peer1)) && + (pRemoteKernelBus->p2p.busNvlinkPeerNumberMask[gpu0Instance] & NVBIT(*peer2))) + { + // + // Increment the mapping refcount per peerID - since there is another usage + // of a mapping that is using this peerID + // + pLocalKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[*peer1]++; + pRemoteKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[*peer2]++; + + // + // Increment the mapping refcount per GPU - since there is another usage of + // the mapping to the given remote GPU + // + pLocalKernelBus->p2p.busNvlinkMappingRefcountPerGpu[gpu1Instance]++; + pRemoteKernelBus->p2p.busNvlinkMappingRefcountPerGpu[gpu0Instance]++; + + if (bSpaAccessOnly) + { + pLocalKernelBus->p2p.busNvlinkMappingRefcountPerPeerIdSpa[*peer1]++; + pRemoteKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[*peer2]++; + } + + NV_PRINTF(LEVEL_INFO, + "- P2P: Peer mapping is already in use for gpu instances %x and %x " + "with peer id's %d and %d. Increasing the mapping refcounts for the" + " peer IDs to %d and %d respectively.\n", + gpu0Instance, gpu1Instance, *peer1, *peer2, + pLocalKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[*peer1], + pRemoteKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[*peer2]); + goto update_params; + } + + // + // Reached here implies the mapping between the given pair of GPUs using the peerIDs + // peer1 and peer2 does not exist. Create the mapping + // + + // Set the peer IDs in the corresponding peer number masks + pLocalKernelBus->p2p.busNvlinkPeerNumberMask[gpu1Instance] |= NVBIT(*peer1); + pRemoteKernelBus->p2p.busNvlinkPeerNumberMask[gpu0Instance] |= NVBIT(*peer2); + + // + // Increment the mapping refcount per peerID - since there is a new mapping that + // will use this peerID + // + pLocalKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[*peer1]++; + pRemoteKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[*peer2]++; + + if (bSpaAccessOnly) + { + pLocalKernelBus->p2p.busNvlinkMappingRefcountPerPeerIdSpa[*peer1]++; + pRemoteKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[*peer2]++; + } + + // + // Increment the mapping refcount per GPU - since there a new mapping now to the + // given remote GPU + // + pLocalKernelBus->p2p.busNvlinkMappingRefcountPerGpu[gpu1Instance]++; + pRemoteKernelBus->p2p.busNvlinkMappingRefcountPerGpu[gpu0Instance]++; + + NV_PRINTF(LEVEL_INFO, + "added NVLink P2P mapping between GPU%u (peer %u) and GPU%u (peer %u)\n", + gpu0Instance, *peer1, gpu1Instance, *peer2); + +update_params: + pNv503bAllocParams->subDevicePeerIdMask = NVBIT(*peer1); + pNv503bAllocParams->peerSubDevicePeerIdMask = NVBIT(*peer2); + + // Update connection type for SRIOV. + pP2PApi->attributes = FLD_SET_DRF(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, _NVLINK, pP2PApi->attributes); + + return NV_OK; +} + + NV_STATUS p2papiConstruct_IMPL ( @@ -322,144 +482,10 @@ p2papiConstruct_IMPL IS_VIRTUAL_WITH_SRIOV(pGpu) && gpuIsSplitVasManagementServerClientRmEnabled(pGpu)) { - NvU32 gpu0Instance = gpuGetInstance(pLocalGpu); - NvU32 gpu1Instance = gpuGetInstance(pRemoteGpu); - - // loopback request - if (pNv503bAllocParams->hSubDevice == pNv503bAllocParams->hPeerSubDevice) - { - peer1 = peer2 = 0; - } - else - { - // Check if a peer ID is already allocated for P2P from pLocalGpu to pRemoteGpu - peer1 = kbusGetPeerId_HAL(pLocalGpu, pLocalKernelBus, pRemoteGpu); - - // Check if a peer ID is already allocated for P2P from pRemoteGpu to pLocalGpu - peer2 = kbusGetPeerId_HAL(pRemoteGpu, pRemoteKernelBus, pLocalGpu); - } - - if (peer1 != BUS_INVALID_PEER && peer2 != BUS_INVALID_PEER) - { - goto update_mask; - } - else if (peer1 == BUS_INVALID_PEER && peer2 == BUS_INVALID_PEER) - { - // Get the peer ID pGpu0 should use for P2P over NVLINK to pGpu1i - peer1 = kbusGetUnusedPeerId_HAL(pLocalGpu, pLocalKernelBus); - // If could not find a free peer ID, return error - if (peer1 == BUS_INVALID_PEER) - { - NV_PRINTF(LEVEL_ERROR, - "GPU%d: peerID not available for NVLink P2P\n", - gpu0Instance); - return NV_ERR_GENERIC; - } - - // Reserve the peer ID for NVLink use - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kbusReserveP2PPeerIds_HAL(pLocalGpu, pLocalKernelBus, NVBIT(peer1))); - - // Get the peer ID pGpu1 should use for P2P over NVLINK to pGpu0 - peer2 = kbusGetUnusedPeerId_HAL(pRemoteGpu, pRemoteKernelBus); - // If could not find a free peer ID, return error - if (peer2 == BUS_INVALID_PEER) - { - NV_PRINTF(LEVEL_ERROR, - "GPU%d: peerID not available for NVLink P2P\n", - gpu1Instance); - return NV_ERR_GENERIC; - } - - // Reserve the peer ID for NVLink use - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kbusReserveP2PPeerIds_HAL(pRemoteGpu, pRemoteKernelBus, NVBIT(peer2))); - } - else - { - NV_PRINTF(LEVEL_ERROR, - "Unexpected state, either of the peer ID is invalid \n"); - return NV_ERR_GENERIC; - } - -update_mask: - // - // Does the mapping already exist between the given pair of GPUs using the peerIDs - // peer1 and peer2 respectively ? - // - if ((pLocalKernelBus->p2p.busNvlinkPeerNumberMask[gpu1Instance] & NVBIT(peer1)) && - (pRemoteKernelBus->p2p.busNvlinkPeerNumberMask[gpu0Instance] & NVBIT(peer2))) - { - // - // Increment the mapping refcount per peerID - since there is another usage - // of a mapping that is using this peerID - // - pLocalKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[peer1]++; - pRemoteKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[peer2]++; - - // - // Increment the mapping refcount per GPU - since there is another usage of - // the mapping to the given remote GPU - // - pLocalKernelBus->p2p.busNvlinkMappingRefcountPerGpu[gpu1Instance]++; - pRemoteKernelBus->p2p.busNvlinkMappingRefcountPerGpu[gpu0Instance]++; - - if (bSpaAccessOnly) - { - pLocalKernelBus->p2p.busNvlinkMappingRefcountPerPeerIdSpa[peer1]++; - pRemoteKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[peer2]++; - } - - NV_PRINTF(LEVEL_INFO, - "- P2P: Peer mapping is already in use for gpu instances %x and %x " - "with peer id's %d and %d. Increasing the mapping refcounts for the" - " peer IDs to %d and %d respectively.\n", - gpu0Instance, gpu1Instance, peer1, peer2, - pLocalKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[peer1], - pRemoteKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[peer2]); - - goto update_params; - } - - // - // Reached here implies the mapping between the given pair of GPUs using the peerIDs - // peer1 and peer2 does not exist. Create the mapping - // - - // Set the peer IDs in the corresponding peer number masks - pLocalKernelBus->p2p.busNvlinkPeerNumberMask[gpu1Instance] |= NVBIT(peer1); - pRemoteKernelBus->p2p.busNvlinkPeerNumberMask[gpu0Instance] |= NVBIT(peer2); - - // - // Increment the mapping refcount per peerID - since there is a new mapping that - // will use this peerID - // - pLocalKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[peer1]++; - pRemoteKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[peer2]++; - - if (bSpaAccessOnly) - { - pLocalKernelBus->p2p.busNvlinkMappingRefcountPerPeerIdSpa[peer1]++; - pRemoteKernelBus->p2p.busNvlinkMappingRefcountPerPeerId[peer2]++; - } - - // - // Increment the mapping refcount per GPU - since there a new mapping now to the - // given remote GPU - // - pLocalKernelBus->p2p.busNvlinkMappingRefcountPerGpu[gpu1Instance]++; - pRemoteKernelBus->p2p.busNvlinkMappingRefcountPerGpu[gpu0Instance]++; - - NV_PRINTF(LEVEL_INFO, - "added NVLink P2P mapping between GPU%u (peer %u) and GPU%u (peer %u)\n", - gpu0Instance, peer1, gpu1Instance, peer2); - -update_params: - pNv503bAllocParams->subDevicePeerIdMask = NVBIT(peer1); - pNv503bAllocParams->peerSubDevicePeerIdMask = NVBIT(peer2); - - // Update connection type for SRIOV. - pP2PApi->attributes = FLD_SET_DRF(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, _NVLINK, pP2PApi->attributes); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + _p2papiReservePeerID(pLocalGpu, pLocalKernelBus, pRemoteGpu, + pRemoteKernelBus, pNv503bAllocParams, pP2PApi, + &peer1, &peer2, bSpaAccessOnly)); } pP2PApi->peerId1 = peer1; diff --git a/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c b/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c index 2dc28bb4a..ff43b5834 100644 --- a/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c +++ b/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c @@ -115,6 +115,12 @@ _ceGetAlgorithmPceIndex NvU8 pHshubIdRequested; NvU32 i; + if ((pceIndex != NULL) && *pceIndex >= kceGetPce2lceConfigSize1_HAL(pKCe)) + { + NV_PRINTF(LEVEL_ERROR, "Invalid PCE request. pceIndex = %d pceCnt = %d\n", *pceIndex, kceGetPce2lceConfigSize1_HAL(pKCe)); + return; + } + if (!(NVBIT32(*pceIndex) & pceAvailableMaskPerHshub[*pHshubId])) { // @@ -201,8 +207,11 @@ kceMapPceLceForC2C_GH100 for (i = 0; i < selectPcePerHshub; i++) { pceIndex = CE_GET_LOWEST_AVAILABLE_IDX(pceAvailableMaskPerHshub[hshubId]); - pceAvailableMaskPerHshub[hshubId] &= (~(NVBIT32(pceIndex))); - pLocalPceLceMap[pceIndex] = lceIndex; + if (pceIndex < kceGetPce2lceConfigSize1_HAL(pKCe)) + { + pceAvailableMaskPerHshub[hshubId] &= (~(NVBIT32(pceIndex))); + pLocalPceLceMap[pceIndex] = lceIndex; + } } } @@ -215,8 +224,11 @@ kceMapPceLceForC2C_GH100 for (i = 0; i < selectPcePerHshub; i++) { pceIndex = CE_GET_LOWEST_AVAILABLE_IDX(pceAvailableMaskPerHshub[hshubId]); - pceAvailableMaskPerHshub[hshubId] &= (~(NVBIT32(pceIndex))); - pLocalPceLceMap[pceIndex] = lceIndex; + if (pceIndex < kceGetPce2lceConfigSize1_HAL(pKCe)) + { + pceAvailableMaskPerHshub[hshubId] &= (~(NVBIT32(pceIndex))); + pLocalPceLceMap[pceIndex] = lceIndex; + } } } } @@ -472,6 +484,8 @@ kceMapPceLceForNvlinkPeers_GH100 { NvU32 numLinksToPeer = knvlinkGetNumLinksToPeer(pGpu, pKernelNvlink, pRemoteGpu); + NvU32 maxLceCnt = NV_CE_MAX_LCE_MASK; + if (numLinksToPeer == 0) { continue; @@ -494,13 +508,16 @@ kceMapPceLceForNvlinkPeers_GH100 // Each peer gets 1 LCE lceIndex = CE_GET_LOWEST_AVAILABLE_IDX(peerAvailableLceMask); - lceMask |= NVBIT32(lceIndex); + HIGHESTBITIDX_32(maxLceCnt); + if (lceIndex < maxLceCnt) + { + lceMask |= NVBIT32(lceIndex); + // Clear out the chosen LCE + peerAvailableLceMask &= (~(NVBIT32(lceIndex))); + } pKCe->nvlinkNumPeers++; - // Clear out the chosen LCE - peerAvailableLceMask &= (~(NVBIT32(lceIndex))); - peerLinkMask = knvlinkGetLinkMaskToPeer(pGpu, pKernelNvlink, pRemoteGpu); if (peerLinkMask == 0) { @@ -615,6 +632,7 @@ kceMapAsyncLceDefault_GH100 NvU32 lceMask = 0; NvU32 pceMask = 0; NvU32 lceIndex, pceIndex, hshubId, i; + NvU32 maxLceCnt = NV_CE_MAX_LCE_MASK; peerAvailableLceMask = kceGetNvlinkPeerSupportedLceMask_HAL(pGpu, pKCe, peerAvailableLceMask); hshubId = 1; @@ -626,9 +644,13 @@ kceMapAsyncLceDefault_GH100 // Reference bug 3042556 // lceIndex = CE_GET_LOWEST_AVAILABLE_IDX(peerAvailableLceMask); - lceMask |= NVBIT32(lceIndex); - // Clear out the chosen LCE - peerAvailableLceMask &= (~(NVBIT32(lceIndex))); + HIGHESTBITIDX_32(maxLceCnt); + if (lceIndex < maxLceCnt) + { + lceMask |= NVBIT32(lceIndex); + // Clear out the chosen LCE + peerAvailableLceMask &= (~(NVBIT32(lceIndex))); + } // Assign PCEs to this LCE based on input request for (i = 0; i < numDefaultPces; i++) @@ -637,8 +659,11 @@ kceMapAsyncLceDefault_GH100 hshubId++; pceIndex = CE_GET_LOWEST_AVAILABLE_IDX(pceAvailableMaskPerHshub[hshubId]); - pceMask |= NVBIT32(pceIndex); - pceAvailableMaskPerHshub[hshubId] &= (~(NVBIT32(pceIndex))); + if (pceIndex < kceGetPce2lceConfigSize1_HAL(pKCe)) + { + pceMask |= NVBIT32(pceIndex); + pceAvailableMaskPerHshub[hshubId] &= (~(NVBIT32(pceIndex))); + } } FOR_EACH_INDEX_IN_MASK(32, pceIndex, pceMask) diff --git a/src/nvidia/src/kernel/gpu/ce/kernel_ce.c b/src/nvidia/src/kernel/gpu/ce/kernel_ce.c index df5f0cf89..419aa7d62 100644 --- a/src/nvidia/src/kernel/gpu/ce/kernel_ce.c +++ b/src/nvidia/src/kernel/gpu/ce/kernel_ce.c @@ -220,7 +220,7 @@ NV_STATUS kceUpdateClassDB_KERNEL(OBJGPU *pGpu, KernelCE *pKCe) { RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS params; + NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS params = {0}; NV_STATUS status = pRmApi->Control(pRmApi, pGpu->hInternalClient, @@ -372,7 +372,7 @@ NV_STATUS kceTopLevelPceLceMappingsUpdate_IMPL(OBJGPU *pGpu, KernelCE *pKCe) // exposeCeMask will be 0x0 when bUpdateNvlinkPceLce is NV_FALSE. // RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS params; + NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS params = {0}; if (bUpdateNvlinkPceLce) { @@ -418,7 +418,7 @@ NV_STATUS kceTopLevelPceLceMappingsUpdate_IMPL(OBJGPU *pGpu, KernelCE *pKCe) NV_STATUS kceGetFaultMethodBufferSize_IMPL(OBJGPU *pGpu, NvU32 *size) { RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS params; + NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS params = {0}; NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, NV2080_CTRL_CMD_CE_GET_FAULT_METHOD_BUFFER_SIZE, ¶ms, sizeof(params))); @@ -444,7 +444,7 @@ kceGetAvailableHubPceMask_IMPL ) { RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS params; + NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS params = {0}; NV_ASSERT_OR_RETURN(pTopoParams != NULL, NV_ERR_INVALID_ARGUMENT); ct_assert(NV_ARRAY_ELEMENTS(pTopoParams->pceAvailableMaskPerHshub) == NV_ARRAY_ELEMENTS(params.hshubPceMasks)); diff --git a/src/nvidia/src/kernel/gpu/ce/kernel_ce_ctrl.c b/src/nvidia/src/kernel/gpu/ce/kernel_ce_ctrl.c index 51d49efcc..053537d12 100644 --- a/src/nvidia/src/kernel/gpu/ce/kernel_ce_ctrl.c +++ b/src/nvidia/src/kernel/gpu/ce/kernel_ce_ctrl.c @@ -66,6 +66,11 @@ subdeviceCtrlCmdCeGetCaps_IMPL rmEngineType = gpuGetRmEngineType(pCeCapsParams->ceEngineType); + if (!RM_ENGINE_TYPE_IS_COPY(rmEngineType)) + { + return NV_ERR_NOT_SUPPORTED; + } + // // vGPU: // @@ -111,4 +116,4 @@ subdeviceCtrlCmdCeGetCaps_IMPL // now fill in caps for this CE return kceGetDeviceCaps(pGpu, pKCe, rmEngineType, NvP64_VALUE(pCeCapsParams->capsTbl)); -} \ No newline at end of file +} diff --git a/src/nvidia/src/kernel/gpu/ce/kernel_ce_shared.c b/src/nvidia/src/kernel/gpu/ce/kernel_ce_shared.c index 224712a54..f6786cd01 100644 --- a/src/nvidia/src/kernel/gpu/ce/kernel_ce_shared.c +++ b/src/nvidia/src/kernel/gpu/ce/kernel_ce_shared.c @@ -145,6 +145,11 @@ subdeviceCtrlCmdCeGetCapsV2_IMPL NV_PRINTF(LEVEL_INFO, "NV2080_CTRL_CE_GET_CAPS_V2 ceEngineType = %d\n", pCeCapsParams->ceEngineType); + if (!RM_ENGINE_TYPE_IS_COPY(rmEngineType)) + { + return NV_ERR_NOT_SUPPORTED; + } + NV_ASSERT_OK_OR_RETURN(ceIndexFromType(pGpu, RES_GET_CLIENT_HANDLE(pSubdevice), rmEngineType, &ceNumber)); { diff --git a/src/nvidia/src/kernel/gpu/deferred_api.c b/src/nvidia/src/kernel/gpu/deferred_api.c index 7c916dc0f..bb7c55489 100644 --- a/src/nvidia/src/kernel/gpu/deferred_api.c +++ b/src/nvidia/src/kernel/gpu/deferred_api.c @@ -45,7 +45,6 @@ static NV_STATUS _Class5080DelDeferredApi(DeferredApiObject *pDeferredApiObject, static NV_STATUS _class5080DeferredApiV2(OBJGPU *pGpu, ChannelDescendant *Object, - METHOD *pMethod, NvU32 Offset, NvU32 Data); @@ -469,7 +468,6 @@ _class5080DeferredApiV2 ( OBJGPU *pGpu, ChannelDescendant *Object, - METHOD *pMethod, NvU32 Offset, NvU32 Data ) @@ -702,7 +700,7 @@ cleanup: return rmStatus; } -static METHOD Nv50DeferredApi[] = +static const METHOD Nv50DeferredApi[] = { { mthdNoOperation, 0x0100, 0x0103 }, { _class5080DeferredApiV2, 0x0200, 0x0203 }, @@ -711,7 +709,7 @@ static METHOD Nv50DeferredApi[] = NV_STATUS defapiGetSwMethods_IMPL ( DeferredApiObject *pDeferredApi, - METHOD **ppMethods, + const METHOD **ppMethods, NvU32 *pNumMethods ) { diff --git a/src/nvidia/src/kernel/gpu/device.c b/src/nvidia/src/kernel/gpu/device.c index 7974f6f76..97e4c7415 100644 --- a/src/nvidia/src/kernel/gpu/device.c +++ b/src/nvidia/src/kernel/gpu/device.c @@ -195,8 +195,6 @@ deviceDestruct_IMPL NV_STATUS rmStatus = NV_OK; NV_STATUS tmpStatus; NvHandle hClient; - NODE *pNode; - RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); resGetFreeParams(staticCast(pDevice, RsResource), &pCallContext, &pParams); @@ -206,18 +204,6 @@ deviceDestruct_IMPL LOCK_METER_DATA(FREE_DEVICE, 0, 0, 0); - // Free all device memory - btreeEnumStart(0, &pNode, pDevice->DevMemoryTable); - while (pNode != NULL) - { - Memory *pMemory = pNode->Data; - btreeEnumNext(&pNode, pDevice->DevMemoryTable); - - tmpStatus = pRmApi->Free(pRmApi, hClient, RES_GET_HANDLE(pMemory)); - if ((tmpStatus != NV_OK) && (rmStatus == NV_OK)) - rmStatus = tmpStatus; - } - // free the device if (_deviceTeardownRef(pDevice, pCallContext) != NV_OK || _deviceTeardown(pDevice, pCallContext) != NV_OK) diff --git a/src/nvidia/src/kernel/gpu/device_ctrl.c b/src/nvidia/src/kernel/gpu/device_ctrl.c index b1b911318..28031504b 100644 --- a/src/nvidia/src/kernel/gpu/device_ctrl.c +++ b/src/nvidia/src/kernel/gpu/device_ctrl.c @@ -35,6 +35,7 @@ #include "gpu/gpu.h" #include "gpu_mgr/gpu_mgr.h" #include "kernel/gpu/rc/kernel_rc.h" +#include "virtualization/hypervisor/hypervisor.h" @@ -210,6 +211,29 @@ deviceCtrlCmdGpuGetVirtualizationMode_IMPL pParams->virtualizationMode = NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NMOS; } + else if (hypervisorIsVgxHyper() && (gpuIsSriovEnabled(pGpu) + )) + { + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU)) + { + pParams->virtualizationMode = + NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VGPU; + } + else if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VSGA)) + { + pParams->virtualizationMode = + NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VSGA; + } + else + { + NV_PRINTF(LEVEL_ERROR, + "invalid virtualization Mode: %x. Returning NONE!\n", + pParams->virtualizationMode); + + pParams->virtualizationMode = + NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NONE; + } + } else { pParams->virtualizationMode = diff --git a/src/nvidia/src/kernel/gpu/disp/arch/v02/kern_disp_0207.c b/src/nvidia/src/kernel/gpu/disp/arch/v02/kern_disp_0207.c index 050019c4d..9ce32c2c2 100644 --- a/src/nvidia/src/kernel/gpu/disp/arch/v02/kern_disp_0207.c +++ b/src/nvidia/src/kernel/gpu/disp/arch/v02/kern_disp_0207.c @@ -53,3 +53,59 @@ kdispComputeLsrMinTimeValue_v02_07 *computedLsrMinTime = swapRdyHiLsrMinTime * 1000; return NV_OK; } + +NV_STATUS +kdispGetRgScanLock_v02_01 +( + POBJGPU pGpu, + KernelDisplay *pKernelDisplay, + NvU32 head0, + POBJGPU pPeerGpu, + NvU32 head1, + NvBool *pMasterScanLock, + NvU32 *pMasterScanLockPin, + NvBool *pSlaveScanLock, + NvU32 *pSlaveScanLockPin +) +{ + NvU32 pinSetOut, pinSetIn; + NV_STATUS rmStatus = NV_OK; + + if (!pMasterScanLock || !pMasterScanLockPin || + !pSlaveScanLock || !pSlaveScanLockPin || head0 >= pKernelDisplay->numHeads || + ((pPeerGpu != NULL) && (head1 >= pKernelDisplay->numHeads))) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // + // The head parameters are not currently needed for G8X, but for more + // complicated setups or GT200 SLI, we may need to take them into + // consideration in the future. + // + rmStatus = gpumgrGetGpuLockAndDrPorts(pGpu, pPeerGpu, &pinSetOut, &pinSetIn); + if (rmStatus != NV_OK) + { + return rmStatus; + } + + NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS params = {0}; + params.pinSetIn = pinSetIn; + params.pinSetOut = pinSetOut; + + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_DISP_PINSETS_TO_LOCKPINS, + ¶ms, + sizeof(params))); + + *pMasterScanLock = params.bMasterScanLock; + *pMasterScanLockPin = params.masterScanLockPin; + + *pSlaveScanLock = params.bSlaveScanLock; + *pSlaveScanLockPin = params.slaveScanLockPin; + + return rmStatus; +} diff --git a/src/nvidia/src/kernel/gpu/disp/arch/v04/kern_disp_0400.c b/src/nvidia/src/kernel/gpu/disp/arch/v04/kern_disp_0400.c index 97ccba272..df869b774 100644 --- a/src/nvidia/src/kernel/gpu/disp/arch/v04/kern_disp_0400.c +++ b/src/nvidia/src/kernel/gpu/disp/arch/v04/kern_disp_0400.c @@ -35,6 +35,9 @@ #include "published/disp/v04_00/dev_disp.h" +#include "ctrl/ctrl2080/ctrl2080gpio.h" +#include "core/locks.h" + /*! * @brief Get the VGA workspace base address, if valid. * @@ -57,3 +60,209 @@ kdispGetVgaWorkspaceBase_v04_00 return NV_FALSE; } + +static NV_STATUS setSliLinkGpioSwControl(OBJGPU *pGpu, + NvU32 pinSet, NvU32 *pGpioFunction, NvU32 *pGpioPin, NvBool *pGpioDirection) +{ + NV_STATUS status = NV_OK; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS params = {0}; + params.pinSet = pinSet; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL, + ¶ms, + sizeof(params)); + + if (status == NV_OK) + { + *pGpioFunction = params.gpioFunction; + *pGpioPin = params.gpioPin; + *pGpioDirection = params.gpioDirection; + } + + return status; +} + +static NV_STATUS programGpioDirection(OBJGPU *pGpu, NvU32 gpioPin, NvBool bInput) +{ + NV_STATUS status = NV_OK; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS params = {0}; + params.gpioPin = gpioPin; + params.bInput = bInput; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_DIRECTION, + ¶ms, + sizeof(params)); + return status; +} + +static NV_STATUS programGpioOutput(OBJGPU *pGpu, NvU32 gpioPin, NvU32 value) +{ + NV_STATUS status = NV_OK; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS params = {0}; + params.gpioPin = gpioPin; + params.value = value; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_OUTPUT, + ¶ms, + sizeof(params)); + return status; +} + +static NV_STATUS readGpioInput(OBJGPU *pGpu, NvU32 gpioPin, NvU32 *value) +{ + NV_STATUS status = NV_OK; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS params = {0}; + params.gpioPin = gpioPin; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GPIO_READ_INPUT, + ¶ms, + sizeof(params)); + + if (status == NV_OK) + *value = params.value; + + return status; +} + +static NV_STATUS activateHwFunction(OBJGPU *pGpu, NvU32 gpioPin, NvU32 function) +{ + NV_STATUS status = NV_OK; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS params = {0}; + params.pin = gpioPin; + params.function = function; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION, + ¶ms, + sizeof(params)); + + return status; +} + +#define GPIO_INVALID_PIN 0xff + +NV_STATUS kdispDetectSliLink_v04_00(KernelDisplay *pKernelDisplay, OBJGPU *pParentGpu, OBJGPU *pChildGpu, NvU32 parentPinSet, NvU32 childPinSet) +{ + // Sanity check, this function should be called with pDisp of Parent GPU + NV_ASSERT(pKernelDisplay == GPU_GET_KERNEL_DISPLAY(pParentGpu)); + + NvU32 parentGpioFunction = 0; + NvU32 childGpioFunction = 0; + NvBool parentGpioDirection = NV_FALSE; + NvBool childGpioDirection = NV_FALSE; + + NvU32 parentGpioPin = GPIO_INVALID_PIN; + NvU32 childGpioPin = GPIO_INVALID_PIN; + NvU32 value = 0; + + NV_STATUS rmStatus; + + // Check the pinset info, needs to have only one bit set + if (!ONEBITSET(parentPinSet) || !ONEBITSET(childPinSet)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + NvU32 parentGpuLockMask = 0, childGpuLockMask = 0; + if (IS_GSP_CLIENT(pParentGpu) && !rmDeviceGpuLockIsOwner(pParentGpu->gpuInstance)) + NV_ASSERT_OK_OR_GOTO(rmStatus, rmGpuGroupLockAcquire(pParentGpu->gpuInstance, + GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_RPC, + &parentGpuLockMask), done); + + if (IS_GSP_CLIENT(pChildGpu) && !rmDeviceGpuLockIsOwner(pChildGpu->gpuInstance)) + NV_ASSERT_OK_OR_GOTO(rmStatus, rmGpuGroupLockAcquire(pChildGpu->gpuInstance, + GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_RPC, + &childGpuLockMask), done); + + // Set the gpio on parent gpu to sw control mode(aka normal) for twiddling + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_INFO, + setSliLinkGpioSwControl(pParentGpu, parentPinSet, + &parentGpioFunction, &parentGpioPin, &parentGpioDirection), done); + + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_INFO, + setSliLinkGpioSwControl(pChildGpu, childPinSet, + &childGpioFunction, &childGpioPin, &childGpioDirection), done); + + rmStatus = NV_ERR_NO_VALID_PATH; + + // Program the GPIO direction on parent and child + NV_ASSERT_OK_OR_GOTO(rmStatus, programGpioDirection(pParentGpu, parentGpioPin, NV_FALSE), done); + NV_ASSERT_OK_OR_GOTO(rmStatus, programGpioDirection(pChildGpu, childGpioPin, NV_TRUE), done); + + // Toggle GPIO on parent, and read from child + NV_ASSERT_OK_OR_GOTO(rmStatus, programGpioOutput(pParentGpu, parentGpioPin, 1), done); + NV_ASSERT_OK_OR_GOTO(rmStatus, readGpioInput(pChildGpu, childGpioPin, &value), done); + NV_ASSERT_OR_GOTO(value == 1, done); + + NV_ASSERT_OK_OR_GOTO(rmStatus, programGpioOutput(pParentGpu, parentGpioPin, 0), done); + NV_ASSERT_OK_OR_GOTO(rmStatus, readGpioInput(pChildGpu, childGpioPin, &value), done); + NV_ASSERT_OR_GOTO(value == 0, done); + + // Program the GPIO direction on parent and child + NV_ASSERT_OK_OR_GOTO(rmStatus, programGpioDirection(pParentGpu, parentGpioPin, NV_TRUE), done); + NV_ASSERT_OK_OR_GOTO(rmStatus, programGpioDirection(pChildGpu, childGpioPin, NV_FALSE), done); + + // Toggle GPIO on child, and read from parent + NV_ASSERT_OK_OR_GOTO(rmStatus, programGpioOutput(pChildGpu, childGpioPin, 1), done); + NV_ASSERT_OK_OR_GOTO(rmStatus, readGpioInput(pParentGpu, parentGpioPin, &value), done); + NV_ASSERT_OR_GOTO(value == 1, done); + + NV_ASSERT_OK_OR_GOTO(rmStatus, programGpioOutput(pChildGpu, childGpioPin, 0), done); + NV_ASSERT_OK_OR_GOTO(rmStatus, readGpioInput(pParentGpu, parentGpioPin, &value), done); + NV_ASSERT_OR_GOTO(value == 0, done); + + // Link in both direction is verified + rmStatus = NV_OK; + +done: + // Set the GPIOs on both GPUs to original direction and hw function state + if (parentGpioPin != GPIO_INVALID_PIN) + { + NV_ASSERT_OK(programGpioDirection(pParentGpu, parentGpioPin, parentGpioDirection)); + // restore the gpio to hw control mode. (aka non-normal mode) + NV_ASSERT_OK(activateHwFunction(pParentGpu, parentGpioPin, parentGpioFunction)); + } + + if (childGpioPin != GPIO_INVALID_PIN) + { + NV_ASSERT_OK(programGpioDirection(pChildGpu, childGpioPin, childGpioDirection)); + // restore the gpio to hw control mode. (aka non-normal mode) + NV_ASSERT_OK(activateHwFunction(pChildGpu, childGpioPin, childGpioFunction)); + } + + if (parentGpuLockMask != 0) + rmGpuGroupLockRelease(parentGpuLockMask, GPUS_LOCK_FLAGS_NONE); + + if (childGpuLockMask != 0) + rmGpuGroupLockRelease(childGpuLockMask, GPUS_LOCK_FLAGS_NONE); + + return rmStatus; +} diff --git a/src/nvidia/src/kernel/gpu/disp/disp_capabilities.c b/src/nvidia/src/kernel/gpu/disp/disp_capabilities.c index 41316cff6..fd2b8fd21 100644 --- a/src/nvidia/src/kernel/gpu/disp/disp_capabilities.c +++ b/src/nvidia/src/kernel/gpu/disp/disp_capabilities.c @@ -47,14 +47,6 @@ dispcapConstruct_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pDispCapabilities); KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); - if (pParams->pSecInfo->privLevel < RS_PRIV_LEVEL_USER_ROOT) - { - NV_PRINTF(LEVEL_ERROR, - "Failure allocating display class 0x%08x: Only root(admin)/kernel clients are allowed\n", - pParams->externalClassId); - - return NV_ERR_INSUFFICIENT_PERMISSIONS; - } // Set display caps RegBase offsets kdispGetDisplayCapsBaseAndSize_HAL(pGpu, pKernelDisplay, &pDispCapabilities->ControlOffset, diff --git a/src/nvidia/src/kernel/gpu/disp/disp_channel.c b/src/nvidia/src/kernel/gpu/disp/disp_channel.c index e24f07499..6ea87af44 100644 --- a/src/nvidia/src/kernel/gpu/disp/disp_channel.c +++ b/src/nvidia/src/kernel/gpu/disp/disp_channel.c @@ -129,6 +129,13 @@ dispchnConstruct_IMPL "Failure allocating display class 0x%08x: Only root(admin)/kernel clients are allowed\n", pParams->externalClassId); + // + // GPUSWSEC-1560 introduced a central object privilege check in RS. Please mark derived external classes + // of DispChannel privileged in their RS_ENTRY. Since DispChannel doesn't have an external class of its own + // and is used as a base class, leaving this check inline to catch future derivations. + // + osAssertFailed(); + return NV_ERR_INSUFFICIENT_PERMISSIONS; } diff --git a/src/nvidia/src/kernel/gpu/disp/disp_common_ctrl_acpi.c b/src/nvidia/src/kernel/gpu/disp/disp_common_ctrl_acpi.c index 2112260ad..42b40c6f4 100644 --- a/src/nvidia/src/kernel/gpu/disp/disp_common_ctrl_acpi.c +++ b/src/nvidia/src/kernel/gpu/disp/disp_common_ctrl_acpi.c @@ -181,7 +181,7 @@ dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL // get acpi id acpiId = pfmFindAcpiId(pPfm, pGpu, displayMask); - outStatus = pOS->osCallACPI_MXMX(pGpu, acpiId, pInOutData); + outStatus = osCallACPI_MXMX(pGpu, acpiId, pInOutData); break; } @@ -202,6 +202,7 @@ dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS: { + // // get acpi id from input buffer // acpi id is 4 byte long and available at byte 4 @@ -218,6 +219,7 @@ dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDS: { + // // get acpi id from input buffer // acpi id is 4 byte long and available at byte 4 @@ -229,11 +231,12 @@ dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL ((NvU8*) pInOutData) + NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDS_DISP_MASK_OFFSET, sizeof(NvU32)); - outStatus = pOS->osCallACPI_MXDS(pGpu, acpiId, (NvU32*) pInOutData); + outStatus = osCallACPI_MXDS(pGpu, acpiId, (NvU32*) pInOutData); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDM: { + // // get acpi id from input buffer // acpi id is 4 byte long and available at byte 4 @@ -245,21 +248,24 @@ dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL ((NvU8*) pInOutData) + NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDM_DISP_MASK_OFFSET, sizeof(NvU32)); - outStatus = pOS->osCallACPI_MXDM(pGpu, acpiId, (NvU32*) pInOutData); + outStatus = osCallACPI_MXDM(pGpu, acpiId, (NvU32*) pInOutData); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXID: { + // get acpi id from input buffer portMemCopy(&acpiId, sizeof(NvU32), ((NvU8*) pInOutData) + NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXID_DISP_MASK_OFFSET, sizeof(NvU32)); - outStatus = pOS->osCallACPI_MXID(pGpu, acpiId, (NvU32*) pInOutData); + + outStatus = osCallACPI_MXID(pGpu, acpiId, (NvU32*) pInOutData); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_LRST: { + portMemCopy(&acpiId, sizeof(NvU32), ((NvU8*) pInOutData) + NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_LRST_DISP_MASK_OFFSET, @@ -270,19 +276,21 @@ dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DDC_EDID: { + portMemCopy(&acpiId, sizeof(NvU32), ((NvU8*) pInOutData) + NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DDC_EDID_DISP_MASK_OFFSET, sizeof(NvU32)); NvU32 outSize = outDataSize; - outStatus = pOS->osCallACPI_DDC(pGpu, acpiId, (NvU8*) pInOutData, - &outSize, NV_TRUE /*bReadMultiBlock*/); + outStatus = osCallACPI_DDC(pGpu, acpiId, (NvU8*) pInOutData, + &outSize, NV_TRUE /*bReadMultiBlock*/); outDataSize = (NvU16) outSize; break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NVHG_MXMX: { + // // get acpi id from input buffer // acpi id is 4 byte long and available at byte 4 @@ -321,11 +329,12 @@ dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_ROM: { - outStatus = pGpu->pOS->osCallACPI_NVHG_ROM(pGpu, (NvU32*) pInOutData, (NvU32*) pInOutData); + outStatus = osCallACPI_NVHG_ROM(pGpu, (NvU32*) pInOutData, (NvU32*) pInOutData); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DCS: { + // get display mask from input buffer portMemCopy(&acpiId, sizeof(NvU32), pInOutData, sizeof(NvU32)); @@ -335,116 +344,116 @@ dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOD: { NvU32 size32 = inOutDataSize; - outStatus = pOS->osCallACPI_DOD(pGpu, (NvU32*) pInOutData, &size32); + outStatus = osCallACPI_DOD(pGpu, (NvU32*) pInOutData, &size32); outDataSize = (NvU16) size32; break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_SUPPORT: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_SUPPORT, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_SUPPORT, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HYBRIDCAPS: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HYBRIDCAPS, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HYBRIDCAPS, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_POLICYSELECT: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_POLICYSELECT, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_POLICYSELECT, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_POWERCONTROL: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_POWERCONTROL, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_POWERCONTROL, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_PLATPOLICY: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_PLATPOLICY, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_PLATPOLICY, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_DISPLAYSTATUS: { if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_MXM_3X)) - outStatus = pGpu->pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MXDP, (NvU32*)pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MXDP, (NvU32*)pInOutData, &outDataSize); else - outStatus = pGpu->pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_DISPLAYSTATUS, (NvU32*)pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_DISPLAYSTATUS, (NvU32*)pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MDTL: { if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_MXM_3X)) - outStatus = pGpu->pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MDTL, (NvU32*)pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MDTL, (NvU32*)pInOutData, &outDataSize); else - outStatus = pGpu->pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_MDTL, (NvU32*)pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_MDTL, (NvU32*)pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSMBLIST: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCSMBLIST, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCSMBLIST, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSMBADDR: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCSMBADDR, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCSMBADDR, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCREADBYTE: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCREADBYTE, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCREADBYTE, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSENDBYTE: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCSENDBYTE, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCSENDBYTE, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCGETSTATUS: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCGETSTATUS, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCGETSTATUS, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCTRIGDDC: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCTRIGDDC, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCTRIGDDC, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCGETDDC: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCGETDDC, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCGETDDC, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXSS: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MXSS, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MXSS, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXMI: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MXMI, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MXMI, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXMS: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MXMS, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MXMS, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXPP: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MXPP, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MXPP, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXDP: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MXDP, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MXDP, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MDTL: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MDTL, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MDTL, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXCB: @@ -454,27 +463,27 @@ dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_GETEVENTLIST: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_GETEVENTLIST, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_GETEVENTLIST, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETMEMTABLE: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_GETMEMTABLE, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_GETMEMTABLE, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETMEMCFG: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_GETMEMCFG, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_GETMEMCFG, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETOBJBYTYPE: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_GETOBJBYTYPE, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_GETOBJBYTYPE, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETALLOBJS: { - outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_GETALLOBJS, (NvU32*) pInOutData, &outDataSize); + outStatus = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_GETALLOBJS, (NvU32*) pInOutData, &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_GETSUPPORTEDFUNC: @@ -489,101 +498,101 @@ dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_DISPLAYSTATUS: { - outStatus = pOS->osCallACPI_DSM(pGpu, - pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_DISPLAYSTATUS-NV_ACPI_GENERIC_FUNC_START], - pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_DISPLAYSTATUS-NV_ACPI_GENERIC_FUNC_START], - (NvU32*) pInOutData, - &outDataSize); + outStatus = osCallACPI_DSM(pGpu, + pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_DISPLAYSTATUS-NV_ACPI_GENERIC_FUNC_START], + pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_DISPLAYSTATUS-NV_ACPI_GENERIC_FUNC_START], + (NvU32*) pInOutData, + &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_MDTL: { - outStatus = pOS->osCallACPI_DSM(pGpu, - pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_MDTL-NV_ACPI_GENERIC_FUNC_START], - pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_MDTL-NV_ACPI_GENERIC_FUNC_START], - (NvU32*) pInOutData, - &outDataSize); + outStatus = osCallACPI_DSM(pGpu, + pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_MDTL-NV_ACPI_GENERIC_FUNC_START], + pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_MDTL-NV_ACPI_GENERIC_FUNC_START], + (NvU32*) pInOutData, + &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_MSTL: { - outStatus = pOS->osCallACPI_DSM(pGpu, - pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_MSTL-NV_ACPI_GENERIC_FUNC_START], - pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_MSTL-NV_ACPI_GENERIC_FUNC_START], - (NvU32*) pInOutData, - &outDataSize); + outStatus = osCallACPI_DSM(pGpu, + pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_MSTL-NV_ACPI_GENERIC_FUNC_START], + pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_MSTL-NV_ACPI_GENERIC_FUNC_START], + (NvU32*) pInOutData, + &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETOBJBYTYPE: { - outStatus = pOS->osCallACPI_DSM(pGpu, - pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_GETOBJBYTYPE-NV_ACPI_GENERIC_FUNC_START], - pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_GETOBJBYTYPE-NV_ACPI_GENERIC_FUNC_START], - (NvU32*) pInOutData, - &outDataSize); + outStatus = osCallACPI_DSM(pGpu, + pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_GETOBJBYTYPE-NV_ACPI_GENERIC_FUNC_START], + pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_GETOBJBYTYPE-NV_ACPI_GENERIC_FUNC_START], + (NvU32*) pInOutData, + &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETALLOBJS: { - outStatus = pOS->osCallACPI_DSM(pGpu, - pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_GETALLOBJS-NV_ACPI_GENERIC_FUNC_START], - pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_GETALLOBJS-NV_ACPI_GENERIC_FUNC_START], - (NvU32*) pInOutData, - &outDataSize); + outStatus = osCallACPI_DSM(pGpu, + pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_GETALLOBJS-NV_ACPI_GENERIC_FUNC_START], + pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_GETALLOBJS-NV_ACPI_GENERIC_FUNC_START], + (NvU32*) pInOutData, + &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETEVENTLIST: { - outStatus = pOS->osCallACPI_DSM(pGpu, - pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_GETEVENTLIST-NV_ACPI_GENERIC_FUNC_START], - pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_GETEVENTLIST-NV_ACPI_GENERIC_FUNC_START], - (NvU32*) pInOutData, - &outDataSize); + outStatus = osCallACPI_DSM(pGpu, + pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_GETEVENTLIST-NV_ACPI_GENERIC_FUNC_START], + pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_GETEVENTLIST-NV_ACPI_GENERIC_FUNC_START], + (NvU32*) pInOutData, + &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETBACKLIGHT: { - outStatus = pOS->osCallACPI_DSM(pGpu, - pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_GETBACKLIGHT-NV_ACPI_GENERIC_FUNC_START], - pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_GETBACKLIGHT-NV_ACPI_GENERIC_FUNC_START], - (NvU32*) pInOutData, - &outDataSize); + outStatus = osCallACPI_DSM(pGpu, + pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_GETBACKLIGHT-NV_ACPI_GENERIC_FUNC_START], + pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_GETBACKLIGHT-NV_ACPI_GENERIC_FUNC_START], + (NvU32*) pInOutData, + &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETCALLBACKS: { - outStatus = pOS->osCallACPI_DSM(pGpu, - pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_CALLBACKS-NV_ACPI_GENERIC_FUNC_START], - pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_CALLBACKS-NV_ACPI_GENERIC_FUNC_START], - (NvU32*) pInOutData, - &outDataSize); + outStatus = osCallACPI_DSM(pGpu, + pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_CALLBACKS-NV_ACPI_GENERIC_FUNC_START], + pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_CALLBACKS-NV_ACPI_GENERIC_FUNC_START], + (NvU32*) pInOutData, + &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NBCI_SUPPORTFUNCS: { - outStatus = pOS->osCallACPI_DSM(pGpu, - ACPI_DSM_FUNCTION_NBCI, - NV_NBCI_FUNC_SUPPORT, - (NvU32*) pInOutData, - &outDataSize); + outStatus = osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_NBCI, + NV_NBCI_FUNC_SUPPORT, + (NvU32*) pInOutData, + &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NBCI_PLATCAPS: { - outStatus = pOS->osCallACPI_DSM(pGpu, - ACPI_DSM_FUNCTION_NBCI, - NV_NBCI_FUNC_PLATCAPS, - (NvU32*) pInOutData, - &outDataSize); + outStatus = osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_NBCI, + NV_NBCI_FUNC_PLATCAPS, + (NvU32*) pInOutData, + &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NBCI_PLATPOLICY: { - outStatus = pOS->osCallACPI_DSM(pGpu, - ACPI_DSM_FUNCTION_NBCI, - NV_NBCI_FUNC_PLATPOLICY, - (NvU32*) pInOutData, - &outDataSize); + outStatus = osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_NBCI, + NV_NBCI_FUNC_PLATPOLICY, + (NvU32*) pInOutData, + &outDataSize); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_WMMX_NVOP_GPUON: diff --git a/src/nvidia/src/kernel/gpu/disp/disp_object_kern_ctrl_minimal.c b/src/nvidia/src/kernel/gpu/disp/disp_object_kern_ctrl_minimal.c index 393f9eb17..43f3030bf 100644 --- a/src/nvidia/src/kernel/gpu/disp/disp_object_kern_ctrl_minimal.c +++ b/src/nvidia/src/kernel/gpu/disp/disp_object_kern_ctrl_minimal.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -23,12 +23,17 @@ #define RM_STRICT_CONFIG_EMIT_DISP_ENGINE_DEFINITIONS 0 -#include "gpu/disp/kern_disp.h" -#include "gpu/disp/disp_objs.h" #include "class/cl5070.h" -#include "mem_mgr/mem.h" +#include "gpu/device/device.h" +#include "gpu/disp/disp_objs.h" +#include "gpu/disp/kern_disp.h" #include "gpu/gpu.h" +#include "gpu/subdevice/subdevice.h" #include "gpu_mgr/gpu_mgr.h" +#include "mem_mgr/mem.h" +#include "rmapi/client_resource.h" +#include "rmapi/rmapi.h" +#include "rmapi/rs_utils.h" NV_STATUS dispobjCtrlCmdEventSetTrigger_IMPL @@ -96,3 +101,100 @@ dispobjCtrlCmdEventSetMemoryNotifies_IMPL return NV_OK; } + +static NV_STATUS getRgConnectedLockpin(OBJGPU *pGpu, + KernelDisplay *pKernelDisplay, NvU32 head, + OBJGPU *pPeerGpu, NvU32 peerHead, + NvU32 *pMasterScanLock, NvU32 *pSlaveScanLock) +{ + NvBool bMasterScanLock, bSlaveScanLock; + NvU32 masterScanLockPin, slaveScanLockPin; + + *pMasterScanLock = 0; + *pSlaveScanLock = 0; + + NV_STATUS status = kdispGetRgScanLock_HAL(pGpu, pKernelDisplay, + head, + pPeerGpu, + peerHead, + &bMasterScanLock, + &masterScanLockPin, + &bSlaveScanLock, + &slaveScanLockPin); + NV_ASSERT_OK_OR_RETURN(status); + + if (bMasterScanLock) + { + *pMasterScanLock = + FLD_SET_DRF(5070, _CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS, + _MASTER_SCAN_LOCK_CONNECTED, _YES, *pMasterScanLock); + + *pMasterScanLock = + FLD_SET_DRF_NUM(5070, _CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS, + _MASTER_SCAN_LOCK_PIN, masterScanLockPin, + *pMasterScanLock); + } + else + { + *pMasterScanLock = + FLD_SET_DRF(5070, _CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS, + _MASTER_SCAN_LOCK_CONNECTED, _NO, *pMasterScanLock); + } + + if (bSlaveScanLock) + { + *pSlaveScanLock = + FLD_SET_DRF(5070, _CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS, + _SLAVE_SCAN_LOCK_CONNECTED, _YES, *pSlaveScanLock); + + *pSlaveScanLock = + FLD_SET_DRF_NUM(5070, _CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS, + _SLAVE_SCAN_LOCK_PIN, slaveScanLockPin, + *pSlaveScanLock); + } + else + { + *pSlaveScanLock = + FLD_SET_DRF(5070, _CTRL_CMD_GET_RG_CONNECTED_LOCKPIN_STATELESS, + _SLAVE_SCAN_LOCK_CONNECTED, _NO, *pSlaveScanLock); + } + + return NV_OK; +} + +NV_STATUS +dispobjCtrlCmdGetRgConnectedLockpinStateless_IMPL +( + DispObject *pDispObject, + NV5070_CTRL_GET_RG_CONNECTED_LOCKPIN_STATELESS_PARAMS *pParams +) +{ + OBJGPU *pGpu = DISPAPI_GET_GPU(pDispObject); + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + NvHandle hClient = RES_GET_CLIENT_HANDLE(pDispObject); + DisplayApi *pDisplayApi; + OBJGPU *pPeerGpu; + + NV_ASSERT_OR_RETURN(pParams->head < pKernelDisplay->numHeads, NV_ERR_INVALID_ARGUMENT); + + if (!CliGetDispInfo(hClient, pParams->peer.hDisplay, &pDisplayApi) && + !CliGetDispCommonInfo(hClient, pParams->peer.hDisplay, &pDisplayApi)) + { + return NV_ERR_INVALID_OBJECT_HANDLE; + } + + RsResourceRef *pPeerDisplayRef; + NV_ASSERT_OK_OR_RETURN(serverutilGetResourceRef(hClient, pParams->peer.hDisplay, &pPeerDisplayRef)); + NV_ASSERT_OR_RETURN(pPeerDisplayRef->pParentRef != NULL, NV_ERR_INVALID_STATE); + + Subdevice *pPeerSubdevice; + NV_ASSERT_OK_OR_RETURN(subdeviceGetByInstance(RES_GET_CLIENT(pDispObject), pPeerDisplayRef->pParentRef->hResource, + pParams->peer.subdeviceIndex, &pPeerSubdevice)); + pPeerGpu = GPU_RES_GET_GPU(pPeerSubdevice); + + NV_ASSERT_OR_RETURN(pPeerGpu != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pParams->peer.head < GPU_GET_KERNEL_DISPLAY(pPeerGpu)->numHeads, NV_ERR_INVALID_ARGUMENT); + + return getRgConnectedLockpin(pGpu, pKernelDisplay, pParams->head, pPeerGpu, pParams->peer.head, + &pParams->masterScanLock, &pParams->slaveScanLock); +} diff --git a/src/nvidia/src/kernel/gpu/disp/disp_objs.c b/src/nvidia/src/kernel/gpu/disp/disp_objs.c index b67d83765..075b09d66 100644 --- a/src/nvidia/src/kernel/gpu/disp/disp_objs.c +++ b/src/nvidia/src/kernel/gpu/disp/disp_objs.c @@ -225,6 +225,13 @@ dispobjConstruct_IMPL "Failure allocating display class 0x%08x: Only root(admin)/kernel clients are allowed\n", pParams->externalClassId); + // + // GPUSWSEC-1560 introduced a central object privilege check in RS. Please mark derived external classes + // of DispObject privileged in their RS_ENTRY. Since DispObject doesn't have an external class of its own + // and is used as a base class, leaving this check inline to catch future derivations. + // + osAssertFailed(); + return NV_ERR_INSUFFICIENT_PERMISSIONS; } @@ -450,14 +457,6 @@ dispswobjConstruct_IMPL RS_RES_ALLOC_PARAMS_INTERNAL *pParams ) { - if (pParams->pSecInfo->privLevel < RS_PRIV_LEVEL_USER_ROOT) - { - NV_PRINTF(LEVEL_ERROR, - "Failure allocating display class 0x%08x: Only root(admin)/kernel clients are allowed\n", - pParams->externalClassId); - - return NV_ERR_INSUFFICIENT_PERMISSIONS; - } return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/disp/disp_sf_user.c b/src/nvidia/src/kernel/gpu/disp/disp_sf_user.c index 32e6cbea9..a5c260e07 100644 --- a/src/nvidia/src/kernel/gpu/disp/disp_sf_user.c +++ b/src/nvidia/src/kernel/gpu/disp/disp_sf_user.c @@ -47,15 +47,6 @@ dispsfConstruct_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pDispSfUser); KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); - if (pParams->pSecInfo->privLevel < RS_PRIV_LEVEL_USER_ROOT) - { - NV_PRINTF(LEVEL_ERROR, - "Failure allocating display class 0x%08x: Only root(admin)/kernel clients are allowed\n", - pParams->externalClassId); - - return NV_ERR_INSUFFICIENT_PERMISSIONS; - } - NV_CHECK_OR_RETURN(LEVEL_ERROR, pKernelDisplay != NULL, NV_ERR_NOT_SUPPORTED); // Set sf user RegBase offset diff --git a/src/nvidia/src/kernel/gpu/disp/kern_disp.c b/src/nvidia/src/kernel/gpu/disp/kern_disp.c index a750ba102..7af80569a 100644 --- a/src/nvidia/src/kernel/gpu/disp/kern_disp.c +++ b/src/nvidia/src/kernel/gpu/disp/kern_disp.c @@ -54,11 +54,8 @@ #include "class/cl5070.h" #include "class/cl917a.h" #include "class/cl917b.h" -#include "class/cl917c.h" -#include "class/cl917d.h" #include "class/cl917e.h" #include "class/cl927c.h" -#include "class/cl927d.h" #include "class/cl947d.h" #include "class/cl957d.h" #include "class/cl977d.h" @@ -258,9 +255,9 @@ kdispInitBrightcStateLoad_IMPL(OBJGPU *pGpu, { // Fill in the Backlight Method Data. pBrightcInfo->backLightDataSize = sizeof(pBrightcInfo->backLightData); - status = pGpu->pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_CURRENT, NV_ACPI_GENERIC_FUNC_GETBACKLIGHT, - (NvU32 *)(pBrightcInfo->backLightData), - &pBrightcInfo->backLightDataSize); + status = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_CURRENT, NV_ACPI_GENERIC_FUNC_GETBACKLIGHT, + (NvU32 *)(pBrightcInfo->backLightData), + &pBrightcInfo->backLightDataSize); pBrightcInfo->status = status; } @@ -449,13 +446,10 @@ kdispGetIntChnClsForHwCls_IMPL *pDispChnClass = dispChnClass_Ovim; break; - case NV917C_BASE_CHANNEL_DMA: case NV927C_BASE_CHANNEL_DMA: *pDispChnClass = dispChnClass_Base; break; - case NV917D_CORE_CHANNEL_DMA: - case NV927D_CORE_CHANNEL_DMA: case NV947D_CORE_CHANNEL_DMA: case NV957D_CORE_CHANNEL_DMA: case NV977D_CORE_CHANNEL_DMA: diff --git a/src/nvidia/src/kernel/gpu/disp/rg_line_callback/rg_line_callback.c b/src/nvidia/src/kernel/gpu/disp/rg_line_callback/rg_line_callback.c index d84e99708..4189d0a81 100644 --- a/src/nvidia/src/kernel/gpu/disp/rg_line_callback/rg_line_callback.c +++ b/src/nvidia/src/kernel/gpu/disp/rg_line_callback/rg_line_callback.c @@ -97,11 +97,6 @@ rglcbConstruct_IMPL { NV0092_RG_LINE_CALLBACK_ALLOCATION_PARAMETERS *pAllocParams = pParams->pAllocParams; - if (pCallContext->secInfo.privLevel < RS_PRIV_LEVEL_KERNEL) - { - return NV_ERR_INSUFFICIENT_PERMISSIONS; - } - pRgLineCallback->subDeviceInstance = pAllocParams->subDeviceInstance; pRgLineCallback->head = pAllocParams->head; pRgLineCallback->rgLineNum = pAllocParams->rgLineNum; diff --git a/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank_callback.c b/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank_callback.c index 4eaef1bd8..b523afdec 100644 --- a/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank_callback.c +++ b/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank_callback.c @@ -67,11 +67,6 @@ vblcbConstruct_IMPL NV_STATUS status = NV_OK; NV_VBLANK_CALLBACK_ALLOCATION_PARAMETERS *pAllocParams = pParams->pAllocParams; - if (pCallContext->secInfo.privLevel < RS_PRIV_LEVEL_KERNEL) - { - return NV_ERR_INSUFFICIENT_PERMISSIONS; - } - if (pKernelDisplay == NULL) { return NV_ERR_NOT_SUPPORTED; diff --git a/src/nvidia/src/kernel/gpu/eng_state.c b/src/nvidia/src/kernel/gpu/eng_state.c index 05de436f7..f6af2ca50 100644 --- a/src/nvidia/src/kernel/gpu/eng_state.c +++ b/src/nvidia/src/kernel/gpu/eng_state.c @@ -177,8 +177,6 @@ engstateDestruct_IMPL OBJENGSTATE *pEngstate ) { - portMemFree(pEngstate->pOriginalTunableState); - pEngstate->pOriginalTunableState = NULL; } /*! @@ -384,117 +382,6 @@ engstateStateDestroy_IMPL { } -/*! - * @brief allocates a tunable state structure - * - * @param[in] pGpu - * @param[in] pEngstate - * @param[out] ppTunableState - */ -NV_STATUS -engstateAllocTunableState_IMPL -( - OBJGPU *pGpu, - OBJENGSTATE *pEngstate, - void **ppTunableState -) -{ - *ppTunableState = NULL; - return NV_OK; -} - -/*! - * @brief frees a tunable state structure - * - * @param[in] pGpu - * @param[in] pEngstate - * @param[in] pTunableState - */ -void -engstateFreeTunableState_IMPL -( - OBJGPU *pGpu, - OBJENGSTATE *pEngstate, - void *pTunableState -) -{ - portMemFree(pTunableState); -} - -/*! - * @brief fills pTunableState with the current state - * - * @param[in] pGpu - * @param[in] pEngstate - * @param[out] pTunableState - */ -NV_STATUS -engstateGetTunableState_IMPL -( - OBJGPU *pGpu, - OBJENGSTATE *pEngstate, - void *pTunableState -) -{ - return NV_OK; -} - -/*! - * @brief sets the current state to values in pTunableState - * - * @param[in] pGpu - * @param[in,out] pEngstate - * @param[in] pTunableState - */ -NV_STATUS -engstateSetTunableState_IMPL -( - OBJGPU *pGpu, - OBJENGSTATE *pEngstate, - void *pTunableState -) -{ - return NV_OK; -} - -/*! - * @brief modifies pTunableState to be compatible with pEngstate->pOriginalTunableState - * - * @param[in] pGpu - * @param[in] pEngstate - * @param[in,out] pTunableState - */ -NV_STATUS -engstateReconcileTunableState_IMPL -( - OBJGPU *pGpu, - OBJENGSTATE *pEngstate, - void *pTunableState -) -{ - return NV_OK; -} - -/*! - * @brief returns NV_ERR_GENERIC if two tunable states are incompatible - * - * @param[in] pGpu - * @param[in] pEngstate - * @param[in] pTunables1 - * @param[in] pTunables2 - */ -NV_STATUS -engstateCompareTunableState_IMPL -( - OBJGPU *pGpu, - OBJENGSTATE *pEngstate, - void *pTunables1, - void *pTunables2 -) -{ - return NV_OK; -} - /*! * @brief returns the ENGDESCRIPTOR associated with this ENGSTATE * diff --git a/src/nvidia/src/kernel/gpu/external_device/arch/kepler/kern_gsync_p2060.c b/src/nvidia/src/kernel/gpu/external_device/arch/kepler/kern_gsync_p2060.c index 54eab8c3b..be59ebe09 100644 --- a/src/nvidia/src/kernel/gpu/external_device/arch/kepler/kern_gsync_p2060.c +++ b/src/nvidia/src/kernel/gpu/external_device/arch/kepler/kern_gsync_p2060.c @@ -79,10 +79,11 @@ static NV_STATUS gsyncFrameCountTimerService_P2060(OBJGPU *, OBJTMR *, void *); static NV_STATUS gsyncResetFrameCountData_P2060(OBJGPU *, PDACP2060EXTERNALDEVICE); static NV_STATUS gsyncGpuStereoHeadSync(OBJGPU *, NvU32, PDACEXTERNALDEVICE, NvU32); +static NvBool supportsMulDiv(DACEXTERNALDEVICE *); static NvBool needsMasterBarrierWar(PDACEXTERNALDEVICE); static NvBool isFirmwareRevMismatch(OBJGPU *, DAC_EXTERNAL_DEVICE_REVS); -static NvBool isBoardWithNvlinkQsyncContention(POBJGPU); +static NvBool isBoardWithNvlinkQsyncContention(OBJGPU *); static void _extdevService(NvU32 , void *); NvBool @@ -1113,7 +1114,7 @@ extdevWatchdog_P2060 static NV_STATUS gsyncApplyStereoPinAlwaysHiWar ( - POBJGPU pGpu, + OBJGPU *pGpu, PDACEXTERNALDEVICE pExtDev ) { @@ -1125,7 +1126,7 @@ gsyncApplyStereoPinAlwaysHiWar static NV_STATUS gsyncUnApplyStereoPinAlwaysHiWar ( - POBJGPU pGpu + OBJGPU *pGpu ) { @@ -4094,6 +4095,8 @@ gsyncGetRevision_P2060 return NV_ERR_GENERIC; // something more descriptive, perhaps? } + portMemSet(pParams, 0, sizeof(*pParams)); + pParams->revId = (NvU32)pExtDev->revId; pParams->boardId = (NvU32)deviceId; pParams->revision = (NvU32)deviceRev; @@ -4140,6 +4143,12 @@ gsyncGetRevision_P2060 { pParams->capFlags |= NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_NEED_MASTER_BARRIER_WAR; } + + if (supportsMulDiv(pExtDev)) + { + pParams->capFlags |= NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_MULTIPLY_DIVIDE_SYNC; + pParams->maxMulDivValue = (NV_P2060_MULTIPLIER_DIVIDER_VALUE_MINUS_ONE_MAX + 1); + } } else { @@ -5432,7 +5441,7 @@ isFirmwareRevMismatch static NvBool isBoardWithNvlinkQsyncContention ( - POBJGPU pGpu + OBJGPU *pGpu ) { NvU16 devIds[] = { @@ -5454,3 +5463,105 @@ isBoardWithNvlinkQsyncContention return NV_FALSE; } + +// Return NV_TRUE if the current Qsync revision supports sync multiply/divide +static NvBool +supportsMulDiv +( + DACEXTERNALDEVICE *pExtDev +) +{ + // Supported only for 2061 boards with >= 2.4 + if (pExtDev->deviceId == DAC_EXTERNAL_DEVICE_P2061) + { + if ((pExtDev->deviceRev >= DAC_EXTERNAL_DEVICE_REV_3) || + ((pExtDev->deviceRev == DAC_EXTERNAL_DEVICE_REV_2) && + (pExtDev->deviceExRev >= 4))) + { + return NV_TRUE; + } + } + return NV_FALSE; +} + +NV_STATUS +gsyncGetMulDiv_P2060 +( + OBJGPU *pGpu, + DACEXTERNALDEVICE *pExtDev, + NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS *pMulDivSettings +) +{ + DACP2060EXTERNALDEVICE *pThis = (DACP2060EXTERNALDEVICE *)pExtDev; + NvU8 reg; + + NV_ASSERT_OR_RETURN(pMulDivSettings != NULL, NV_ERR_INVALID_ARGUMENT); + NV_CHECK_OR_RETURN(LEVEL_INFO, supportsMulDiv(pExtDev), NV_ERR_NOT_SUPPORTED); + + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + readregu008_extdeviceTargeted(pGpu, pExtDev, NV_P2060_MULTIPLIER_DIVIDER, ®)); + + pMulDivSettings->multiplyDivideValue = + DRF_VAL(_P2060, _MULTIPLIER_DIVIDER, _VALUE_MINUS_ONE, reg) + 1; + pMulDivSettings->multiplyDivideMode = + FLD_TEST_DRF(_P2060, _MULTIPLIER_DIVIDER, _MODE, _DIVIDE, reg) ? + NV30F1_CTRL_GSYNC_SET_CONTROL_MULTIPLY_DIVIDE_MODE_DIVIDE : + NV30F1_CTRL_GSYNC_SET_CONTROL_MULTIPLY_DIVIDE_MODE_MULTIPLY; + + // Cache this for debugging + portMemCopy(&pThis->mulDivSettings, sizeof(pThis->mulDivSettings), + pMulDivSettings, sizeof(*pMulDivSettings)); + + return NV_OK; +} + +NV_STATUS +gsyncSetMulDiv_P2060 +( + OBJGPU *pGpu, + DACEXTERNALDEVICE *pExtDev, + NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS *pMulDivSettings +) +{ + DACP2060EXTERNALDEVICE *pThis = (DACP2060EXTERNALDEVICE *)pExtDev; + NvU8 reg; + + NV_ASSERT_OR_RETURN(pMulDivSettings != NULL, NV_ERR_INVALID_ARGUMENT); + NV_CHECK_OR_RETURN(LEVEL_INFO, supportsMulDiv(pExtDev), NV_ERR_NOT_SUPPORTED); + pGpu = GetP2060MasterableGpu(pGpu, (DACP2060EXTERNALDEVICE *)pExtDev); + NV_ASSERT_OR_RETURN(pGpu != NULL, NV_ERR_GENERIC); + + // + // Assume that there are no other fields inside NV_P2060_MULTIPLIER_DIVIDER + // to necessitate a read-modify-write + // + reg = 0; + + switch (pMulDivSettings->multiplyDivideMode) + { + case NV30F1_CTRL_GSYNC_SET_CONTROL_MULTIPLY_DIVIDE_MODE_MULTIPLY: + reg = FLD_SET_DRF(_P2060, _MULTIPLIER_DIVIDER, _MODE, _MULTIPLY, reg); + break; + case NV30F1_CTRL_GSYNC_SET_CONTROL_MULTIPLY_DIVIDE_MODE_DIVIDE: + reg = FLD_SET_DRF(_P2060, _MULTIPLIER_DIVIDER, _MODE, _DIVIDE, reg); + break; + default: + return NV_ERR_INVALID_PARAMETER; + } + + // The register is a 3-bit value ranging from 0-7 representing the integers from 1-8, so check the input param + if ((pMulDivSettings->multiplyDivideValue < 1) || + (pMulDivSettings->multiplyDivideValue > (NV_P2060_MULTIPLIER_DIVIDER_VALUE_MINUS_ONE_MAX + 1))) + return NV_ERR_INVALID_PARAMETER; + // Subtract 1 while packing the register + reg = FLD_SET_DRF_NUM(_P2060, _MULTIPLIER_DIVIDER, _VALUE_MINUS_ONE, + pMulDivSettings->multiplyDivideValue - 1, reg); + + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, writeregu008_extdeviceTargeted(pGpu, pExtDev, NV_P2060_MULTIPLIER_DIVIDER, reg)); + + // Cache this for debugging + portMemCopy(&pThis->mulDivSettings, sizeof(pThis->mulDivSettings), + pMulDivSettings, sizeof(*pMulDivSettings)); + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/external_device/gsync.c b/src/nvidia/src/kernel/gpu/external_device/gsync.c index 36fbdf74d..0b4a008ab 100644 --- a/src/nvidia/src/kernel/gpu/external_device/gsync.c +++ b/src/nvidia/src/kernel/gpu/external_device/gsync.c @@ -232,6 +232,8 @@ gsyncP2060StartupProvider(OBJGSYNC *pGsync) pGsync->gsyncHal.gsyncSetInterlaceMode = gsyncSetInterlaceMode_P2060; pGsync->gsyncHal.gsyncGetStereoLockMode = gsyncGetStereoLockMode_P2060; pGsync->gsyncHal.gsyncSetStereoLockMode = gsyncSetStereoLockMode_P2060; + pGsync->gsyncHal.gsyncGetMulDiv = gsyncGetMulDiv_P2060; + pGsync->gsyncHal.gsyncSetMulDiv = gsyncSetMulDiv_P2060; pGsync->gsyncHal.gsyncRefSwapBarrier = gsyncRefSwapBarrier_P2060; pGsync->gsyncHal.gsyncSetMosaic = gsyncSetMosaic_P2060; @@ -1230,34 +1232,39 @@ gsyncGetStatusParams(OBJGSYNC *pGsync, if ( pParams->which & NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_POLARITY ) { - status |= pGsync->gsyncHal.gsyncGetSyncPolarity(pGpu, pGsync->pExtDev, &SyncPolarity); + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_INFO, pGsync->gsyncHal.gsyncGetSyncPolarity(pGpu, pGsync->pExtDev, &SyncPolarity)); pParams->syncPolarity = (NvU32)SyncPolarity; } if ( pParams->which & NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE ) { - status |= pGsync->gsyncHal.gsyncGetVideoMode(pGpu, pGsync->pExtDev, &VideoMode); + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_INFO, pGsync->gsyncHal.gsyncGetVideoMode(pGpu, pGsync->pExtDev, &VideoMode)); pParams->syncVideoMode = (NvU32)VideoMode; } if ( pParams->which & NV30F1_CTRL_GSYNC_GET_CONTROL_NSYNC ) { - status |= pGsync->gsyncHal.gsyncGetNSync(pGpu, pGsync->pExtDev, &pParams->nSync); + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_INFO, pGsync->gsyncHal.gsyncGetNSync(pGpu, pGsync->pExtDev, &pParams->nSync)); } if ( pParams->which & NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_SKEW ) { - status |= pGsync->gsyncHal.gsyncGetSyncSkew(pGpu, pGsync->pExtDev, &pParams->syncSkew); + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_INFO, pGsync->gsyncHal.gsyncGetSyncSkew(pGpu, pGsync->pExtDev, &pParams->syncSkew)); } if ( pParams->which & NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_START_DELAY ) { - status |= pGsync->gsyncHal.gsyncGetSyncStartDelay(pGpu, pGsync->pExtDev, &pParams->syncStartDelay); + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_INFO, pGsync->gsyncHal.gsyncGetSyncStartDelay(pGpu, pGsync->pExtDev, &pParams->syncStartDelay)); } if ( pParams->which & NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_USE_HOUSE ) { - status |= pGsync->gsyncHal.gsyncGetUseHouse(pGpu, pGsync->pExtDev, &pParams->useHouseSync); + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_INFO, pGsync->gsyncHal.gsyncGetUseHouse(pGpu, pGsync->pExtDev, &pParams->useHouseSync)); + } + + if ( pParams->which & NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_MULTIPLY_DIVIDE ) + { + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_INFO, pGsync->gsyncHal.gsyncGetMulDiv(pGpu, pGsync->pExtDev, &pParams->syncMulDiv)); } return status; @@ -1308,6 +1315,11 @@ gsyncSetControlParams(OBJGSYNC *pGsync, status |= pGsync->gsyncHal.gsyncSetUseHouse(pGpu, pGsync->pExtDev, pParams->useHouseSync); } + if ( pParams->which & NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_MULTIPLY_DIVIDE ) + { + status |= pGsync->gsyncHal.gsyncSetMulDiv(pGpu, pGsync->pExtDev, &pParams->syncMulDiv); + } + return status; } @@ -2452,6 +2464,28 @@ gsyncNullSetHouseSyncMode return NV_ERR_GENERIC; } +static NV_STATUS +gsyncNullGetMulDiv +( + OBJGPU *pGpu, + DACEXTERNALDEVICE *pExtDev, + NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS *pMulDivSettings +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +static NV_STATUS +gsyncNullSetMulDiv +( + OBJGPU *pGpu, + DACEXTERNALDEVICE *pExtDev, + NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS *pMulDivSettings +) +{ + return NV_ERR_NOT_SUPPORTED; +} + static NV_STATUS gsyncSetupNullProvider(OBJGSYNCMGR *pGsyncMgr, NvU32 gsyncInst) { @@ -2496,6 +2530,8 @@ gsyncSetupNullProvider(OBJGSYNCMGR *pGsyncMgr, NvU32 gsyncInst) pGsync->gsyncHal.gsyncConfigFlashGsync = gsyncNullConfigFlashGsync; pGsync->gsyncHal.gsyncGetHouseSyncMode = gsyncNullGetHouseSyncMode; pGsync->gsyncHal.gsyncSetHouseSyncMode = gsyncNullSetHouseSyncMode; + pGsync->gsyncHal.gsyncGetMulDiv = gsyncNullGetMulDiv; + pGsync->gsyncHal.gsyncSetMulDiv = gsyncNullSetMulDiv; return status; } diff --git a/src/nvidia/src/kernel/gpu/falcon/kernel_falcon.c b/src/nvidia/src/kernel/gpu/falcon/kernel_falcon.c index fb2d1fcca..5c595b908 100644 --- a/src/nvidia/src/kernel/gpu/falcon/kernel_falcon.c +++ b/src/nvidia/src/kernel/gpu/falcon/kernel_falcon.c @@ -291,11 +291,6 @@ NV_STATUS gkflcnResetHw_IMPL(OBJGPU *pGpu, GenericKernelFalcon *pGenKernFlcn) NV_ASSERT_FAILED("This should only be called on full KernelFalcon implementations"); return NV_ERR_NOT_SUPPORTED; } -NvBool gkflcnIsEngineInReset_IMPL(OBJGPU *pGpu, GenericKernelFalcon *pGenKernFlcn) -{ - NV_ASSERT_FAILED("This should only be called on full KernelFalcon implementations"); - return NV_FALSE; -} void gkflcnRegisterIntrService_IMPL(OBJGPU *pGpu, GenericKernelFalcon *pGenericKernelFalcon, IntrServiceRecord pRecords[MC_ENGINE_IDX_MAX]) { diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/ampere/kernel_fifo_ga100.c b/src/nvidia/src/kernel/gpu/fifo/arch/ampere/kernel_fifo_ga100.c index 445946e56..de66191ef 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/ampere/kernel_fifo_ga100.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/ampere/kernel_fifo_ga100.c @@ -33,19 +33,7 @@ #include "published/ampere/ga100/dev_ram.h" #include "published/ampere/ga100/dev_ctrl.h" -/** - * @brief Translates between 2 engine values - * - * To iterate through a value for all engines call with inType of - * ENGINE_INFO_TYPE_INVALID for 0 through fifoGetNumEngines(). - * - * @param pGpu - * @param pKernelFifo - * @param[in] inType ENGINE_INFO_TYPE_* - * @param[in] inVal - * @param[in] outType ENGINE_INFO_TYPE_* - * @param[out] pOutVal - */ + NV_STATUS kfifoEngineInfoXlate_GA100 ( @@ -148,29 +136,6 @@ kfifoChannelGroupGetLocalMaxSubcontext_GA100 bLegacyMode); } -/*! - * @brief Clear USERD memory - */ -void -kfifoSetupUserD_GA100 -( - KernelFifo *pKernelFifo, - NvU8 *pUserD -) -{ - NV_ASSERT_OR_RETURN_VOID(pUserD != NULL); - - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_PUT ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_GET ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_REF ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_PUT_HI ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_TOP_LEVEL_GET ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_TOP_LEVEL_GET_HI ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_GET_HI ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_GP_GET ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_GP_PUT ), 0 ); -} - /*! * @brief Update the usermode doorbell register with work submit token to notify * host that work is available on this channel. diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_gm107.c b/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_gm107.c index 50a2f4ebe..38fdb9941 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_gm107.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_gm107.c @@ -48,43 +48,31 @@ static NV_STATUS _kchannelDestroyRMUserdMemDesc(OBJGPU *pGpu, KernelChannel *pKe NV_STATUS kchannelGetClassEngineID_GM107 ( - OBJGPU *pGpu, - KernelChannel *pKernelChannel, - NvHandle handle, - NvU32 *pClassEngineID, - NvU32 *pClassID, + OBJGPU *pGpu, + KernelChannel *pKernelChannel, + NvHandle handle, + NvU32 *pClassEngineID, + NvU32 *pClassID, RM_ENGINE_TYPE *pRmEngineID ) { - NV_STATUS status = NV_OK; - NvU32 halEngineTag = 0; - NvU32 hwEngineID = 0; - NvU32 classID; - KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); - ChannelDescendant *pObject = NULL; + NV_STATUS status = NV_OK; + NvU32 halEngineTag; + NvU32 classID; + ChannelDescendant *pObject = NULL; - NV_CHECK_OK_OR_RETURN(LEVEL_INFO, kchannelFindChildByHandle(pKernelChannel, handle, &pObject)); + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + kchannelFindChildByHandle(pKernelChannel, handle, &pObject)); NV_ASSERT_OR_RETURN(pObject != NULL, NV_ERR_OBJECT_NOT_FOUND); *pClassID = classID = RES_GET_EXT_CLASS_ID(pObject); halEngineTag = pObject->resourceDesc.engDesc; - status = kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, ENGINE_INFO_TYPE_ENG_DESC, - halEngineTag, ENGINE_INFO_TYPE_FIFO_TAG, &hwEngineID); - if (halEngineTag == ENG_SW) { classID = pObject->classID; } - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - ": Invalid Engine Tag %x associated with object handle = %x\n", - halEngineTag, handle); - return NV_ERR_OBJECT_NOT_FOUND; - } - status = gpuXlateEngDescToClientEngineId(pGpu, halEngineTag, pRmEngineID); if (status == NV_OK) @@ -93,8 +81,8 @@ kchannelGetClassEngineID_GM107 } NV_PRINTF(LEVEL_INFO, - "class ID: 0x%08x engine id 0x%08x classEngine ID: 0x%08x\n", - classID, hwEngineID, *pClassEngineID); + "class ID: 0x%08x classEngine ID: 0x%08x\n", + classID, *pClassEngineID); return status; } diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_group_gm107.c b/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_group_gm107.c deleted file mode 100644 index eb536beda..000000000 --- a/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_group_gm107.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "core/core.h" - -#include "kernel/gpu/fifo/kernel_channel_group.h" - -/** - * @brief Gets the default runlist id to use for TSGs allocated with no engines on them. - * - * @param[in] pGpu - * @param[in] pKernelChannelGroup - TSG to retrieve default runlist id for - */ -NvU32 -kchangrpGetDefaultRunlist_GM107 -( - OBJGPU *pGpu, - KernelChannelGroup *pKernelChannelGroup -) -{ - KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); - NvU32 runlistId = INVALID_RUNLIST_ID; - ENGDESCRIPTOR engDesc = ENG_GR(0); - - if (RM_ENGINE_TYPE_IS_VALID(pKernelChannelGroup->engineType)) - { - // if translation fails, default is GR0 - NV_ASSERT_OK(kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, - ENGINE_INFO_TYPE_RM_ENGINE_TYPE, - (NvU32)pKernelChannelGroup->engineType, - ENGINE_INFO_TYPE_ENG_DESC, - &engDesc)); - } - - // if translation fails, defualt is INVALID_RUNLIST_ID - NV_ASSERT_OK( - kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, - ENGINE_INFO_TYPE_ENG_DESC, engDesc, - ENGINE_INFO_TYPE_RUNLIST, &runlistId)); - - return runlistId; -} diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_fifo_gm107.c b/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_fifo_gm107.c index 311ee6414..d05d4bf76 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_fifo_gm107.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_fifo_gm107.c @@ -37,11 +37,16 @@ #include "published/maxwell/gm107/dev_ram.h" #include "published/maxwell/gm107/dev_mmu.h" + +static inline NvBool +_isEngineInfoTypeValidForOnlyHostDriven(ENGINE_INFO_TYPE type); + + /*! Construct kfifo object */ NV_STATUS kfifoConstructHal_GM107 ( - OBJGPU *pGpu, + OBJGPU *pGpu, KernelFifo *pKernelFifo ) { @@ -380,15 +385,19 @@ kfifoGetDefaultRunlist_GM107 // if translation fails, defualt is ENG_GR(0) NV_ASSERT_OK( kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, - ENGINE_INFO_TYPE_RM_ENGINE_TYPE, (NvU32)rmEngineType, - ENGINE_INFO_TYPE_ENG_DESC, &engDesc)); + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, (NvU32)rmEngineType, + ENGINE_INFO_TYPE_ENG_DESC, &engDesc)); } - // if translation fails, defualt is INVALID_RUNLIST_ID - NV_ASSERT_OK( - kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, - ENGINE_INFO_TYPE_ENG_DESC, engDesc, - ENGINE_INFO_TYPE_RUNLIST, &runlistId)); + // if translation fails, default is INVALID_RUNLIST_ID + if (kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, + ENGINE_INFO_TYPE_ENG_DESC, + engDesc, + ENGINE_INFO_TYPE_RUNLIST, + &runlistId) != NV_OK) + { + runlistId = INVALID_RUNLIST_ID; + } return runlistId; } @@ -661,34 +670,54 @@ kfifoConvertInstToKernelChannel_GM107 return NV_ERR_INVALID_CHANNEL; } -/** - * @brief Translates between 2 engine values - * - * To iterate through a value for all engines call with inType of - * ENGINE_INFO_TYPE_INVALID for 0 through fifoGetNumEngines(). - * - * @param pGpu - * @param pKernelFifo - * @param[in] inType ENGINE_INFO_TYPE_* - * @param[in] inVal - * @param[in] outType ENGINE_INFO_TYPE_* - * @param[out] pOutVal - */ +static inline NvBool +_isEngineInfoTypeValidForOnlyHostDriven(ENGINE_INFO_TYPE type) +{ + switch (type) + { + case ENGINE_INFO_TYPE_RUNLIST: + case ENGINE_INFO_TYPE_RUNLIST_PRI_BASE: + case ENGINE_INFO_TYPE_RUNLIST_ENGINE_ID: + case ENGINE_INFO_TYPE_PBDMA_ID: + case ENGINE_INFO_TYPE_CHRAM_PRI_BASE: + case ENGINE_INFO_TYPE_FIFO_TAG: + return NV_TRUE; + case ENGINE_INFO_TYPE_ENG_DESC: + case ENGINE_INFO_TYPE_RM_ENGINE_TYPE: + case ENGINE_INFO_TYPE_MMU_FAULT_ID: + case ENGINE_INFO_TYPE_RC_MASK: + case ENGINE_INFO_TYPE_RESET: + case ENGINE_INFO_TYPE_INTR: + case ENGINE_INFO_TYPE_MC: + case ENGINE_INFO_TYPE_DEV_TYPE_ENUM: + case ENGINE_INFO_TYPE_INSTANCE_ID: + case ENGINE_INFO_TYPE_IS_HOST_DRIVEN_ENGINE: + // The bool itself is valid for non-host-driven engines too. + case ENGINE_INFO_TYPE_INVALID: + return NV_FALSE; + default: + // Ensure that this function covers every value in ENGINE_INFO_TYPE + NV_ASSERT(0 && "check all ENGINE_INFO_TYPE are classified as host-driven or not"); + return NV_FALSE; + } +} + + NV_STATUS kfifoEngineInfoXlate_GM107 ( - OBJGPU *pGpu, - KernelFifo *pKernelFifo, - ENGINE_INFO_TYPE inType, - NvU32 inVal, - ENGINE_INFO_TYPE outType, - NvU32 *pOutVal + OBJGPU *pGpu, + KernelFifo *pKernelFifo, + ENGINE_INFO_TYPE inType, + NvU32 inVal, + ENGINE_INFO_TYPE outType, + NvU32 *pOutVal ) { - const ENGINE_INFO *pEngineInfo = kfifoGetEngineInfo(pKernelFifo); - NvU32 i; + const ENGINE_INFO *pEngineInfo = kfifoGetEngineInfo(pKernelFifo); + FIFO_ENGINE_LIST *pFoundInputEngine = NULL; - NV_ASSERT_OR_RETURN(pOutVal, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pOutVal != NULL, NV_ERR_INVALID_ARGUMENT); // PBDMA_ID can only be inType NV_ASSERT_OR_RETURN(outType != ENGINE_INFO_TYPE_PBDMA_ID, @@ -697,49 +726,70 @@ kfifoEngineInfoXlate_GM107 if (pEngineInfo == NULL) { NV_ASSERT_OK_OR_RETURN(kfifoConstructEngineList_HAL(pGpu, pKernelFifo)); - pEngineInfo = kfifoGetEngineInfo(pKernelFifo); - NV_ASSERT_OR_RETURN(pEngineInfo != NULL, NV_ERR_INVALID_STATE); } + NV_ASSERT_OR_RETURN(pEngineInfo != NULL, NV_ERR_INVALID_STATE); if (inType == ENGINE_INFO_TYPE_INVALID) { NV_ASSERT_OR_RETURN(inVal < pEngineInfo->engineInfoListSize, NV_ERR_INVALID_ARGUMENT); - *pOutVal = pEngineInfo->engineInfoList[inVal].engineData[outType]; - return NV_OK; + pFoundInputEngine = &pEngineInfo->engineInfoList[inVal]; } - - for (i = 0; i < pEngineInfo->engineInfoListSize; ++i) + else { - FIFO_ENGINE_LIST *pFifoEngineList = &pEngineInfo->engineInfoList[i]; - NvBool bFound = NV_FALSE; - - if (inType == ENGINE_INFO_TYPE_PBDMA_ID) + NvU32 i; + for (i = 0; + (i < pEngineInfo->engineInfoListSize) && + (pFoundInputEngine == NULL); + ++i) { - NvU32 j; - for (j = 0; j < pFifoEngineList->numPbdmas; ++j) + FIFO_ENGINE_LIST *pThisEngine = &pEngineInfo->engineInfoList[i]; + + if (inType == ENGINE_INFO_TYPE_PBDMA_ID) { - if (pFifoEngineList->pbdmaIds[j] == inVal) + NvU32 j; + for (j = 0; j < pThisEngine->numPbdmas; ++j) { - bFound = NV_TRUE; - break; + if (pThisEngine->pbdmaIds[j] == inVal) + { + pFoundInputEngine = pThisEngine; + break; + } } } - } - else if (pFifoEngineList->engineData[inType] == inVal) - { - bFound = NV_TRUE; - } - - if (bFound) - { - *pOutVal = pFifoEngineList->engineData[outType]; - return NV_OK; + else if (pThisEngine->engineData[inType] == inVal) + { + pFoundInputEngine = pThisEngine; + } } } - return NV_ERR_INVALID_ARGUMENT; + if (pFoundInputEngine == NULL) + { + return NV_ERR_OBJECT_NOT_FOUND; + } + + if (_isEngineInfoTypeValidForOnlyHostDriven(outType) && + !pFoundInputEngine->engineData[ENGINE_INFO_TYPE_IS_HOST_DRIVEN_ENGINE]) + { + // + // Bug 3748452 TODO + // Bug 3772199 TODO + // + // We can't easily just return an error here because hundreds of + // callsites would fail their asserts. The above two bugs track fixing + // all callsites after which, we can uncomment this. + // + // return NV_ERR_OBJECT_NOT_FOUND; + // + NV_PRINTF(LEVEL_ERROR, + "Asked for host-specific type(0x%x) for non-host engine type(0x%x),val(0x%08x)\n", + outType, inType, inVal); + } + + *pOutVal = pFoundInputEngine->engineData[outType]; + return NV_OK; } /** @@ -761,22 +811,15 @@ kfifoChannelGroupGetLocalMaxSubcontext_GM107 void kfifoSetupUserD_GM107 ( + OBJGPU *pGpu, KernelFifo *pKernelFifo, - NvU8 *pUserD + MEMORY_DESCRIPTOR *pMemDesc ) { - NV_ASSERT_OR_RETURN_VOID(pUserD != NULL); + TRANSFER_SURFACE tSurf = {.pMemDesc = pMemDesc, .offset = 0}; - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_PUT ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_GET ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_REF ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_PUT_HI ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_REF_THRESHOLD ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_GP_TOP_LEVEL_GET ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_GP_TOP_LEVEL_GET_HI ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_GET_HI ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_GP_GET ), 0 ); - MEM_WR32( pUserD + SF_OFFSET( NV_RAMUSERD_GP_PUT ), 0 ); + NV_ASSERT_OK(memmgrMemSet(GPU_GET_MEMORY_MANAGER(pGpu), &tSurf, 0, + NV_RAMUSERD_CHAN_SIZE, TRANSFER_FLAGS_NONE)); } /** * @brief return number of HW engines @@ -1492,14 +1535,14 @@ kfifoCheckEngine_GM107 NvBool *pPresent ) { - NvU32 tmp; + NvU32 bEschedDriven = NV_FALSE; NV_STATUS status; status = kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, - ENGINE_INFO_TYPE_ENG_DESC, engDesc, - ENGINE_INFO_TYPE_FIFO_TAG, &tmp); + ENGINE_INFO_TYPE_ENG_DESC, engDesc, + ENGINE_INFO_TYPE_IS_HOST_DRIVEN_ENGINE, &bEschedDriven); - *pPresent = (status == NV_OK); + *pPresent = (status == NV_OK) && bEschedDriven; return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_fifo_gv100.c b/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_fifo_gv100.c index c066661a7..eab81f5b0 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_fifo_gv100.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_fifo_gv100.c @@ -92,19 +92,6 @@ kfifoRmctrlGetWorkSubmitToken_GV100 return NV_OK; } -/** - * @brief Translates between 2 engine values - * - * To iterate through a value for all engines call with inType of - * ENGINE_INFO_TYPE_INVALID for 0 through fifoGetNumEngines(). - * - * @param pGpu - * @param pKernelFifo - * @param[in] inType ENGINE_INFO_TYPE_* - * @param[in] inVal - * @param[in] outType ENGINE_INFO_TYPE_* - * @param[out] pOutVal - */ NV_STATUS kfifoEngineInfoXlate_GV100 ( diff --git a/src/nvidia/src/kernel/gpu/fifo/channel_descendant.c b/src/nvidia/src/kernel/gpu/fifo/channel_descendant.c index 12d00f0c5..2cd991a04 100644 --- a/src/nvidia/src/kernel/gpu/fifo/channel_descendant.c +++ b/src/nvidia/src/kernel/gpu/fifo/channel_descendant.c @@ -282,7 +282,7 @@ NV_STATUS chandesGetSwMethods_IMPL ( ChannelDescendant *pChannelDescendant, - METHOD **ppMethods, + const METHOD **ppMethods, NvU32 *pNumMethods ) { @@ -301,7 +301,6 @@ NV_STATUS mthdNoOperation ( OBJGPU *pGpu, ChannelDescendant *Object, - PMETHOD Method, NvU32 Offset, NvU32 Data ) diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c b/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c index e82e62e00..de9e10062 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c @@ -1030,8 +1030,11 @@ kchannelDestruct_IMPL KernelGraphicsContext *pKernelGraphicsContext; // Perform GR ctx cleanup tasks on channel destruction - if (kgrctxFromKernelChannel(pKernelChannel, &pKernelGraphicsContext) == NV_OK) + if ((kgrctxFromKernelChannel(pKernelChannel, &pKernelGraphicsContext) == NV_OK) && + kgrctxIsValid(pGpu, pKernelGraphicsContext, pKernelChannel)) + { shrkgrctxDetach(pGpu, pKernelGraphicsContext->pShared, pKernelGraphicsContext, pKernelChannel); + } } _kchannelCleanupNotifyActions(pKernelChannel); @@ -2057,41 +2060,13 @@ _kchannelAllocOrDescribeInstMem NvBool bFullSriov = IS_VIRTUAL_WITH_SRIOV(pGpu) && !gpuIsWarBug200577889SriovHeavyEnabled(pGpu); - if (pUserdSubDeviceMemDesc && - (memdescGetAddressSpace(pUserdSubDeviceMemDesc) == ADDR_SYSMEM)) + // Clear Userd if it is in FB for SRIOV environment without BUG 200577889 or if in SYSMEM + if (pUserdSubDeviceMemDesc != NULL && + ((memdescGetAddressSpace(pUserdSubDeviceMemDesc) == ADDR_SYSMEM) + || ((memdescGetAddressSpace(pUserdSubDeviceMemDesc) == ADDR_FBMEM) && bFullSriov))) { - NvP64 pUserDMem = NvP64_NULL; - NvP64 pPriv = NvP64_NULL; - - NV_ASSERT_OK_OR_GOTO(status, - memdescMap(pUserdSubDeviceMemDesc, 0, - memdescGetSize(pUserdSubDeviceMemDesc), NV_TRUE, - NV_PROTECT_READ_WRITE, &pUserDMem, &pPriv), - failed); - - kfifoSetupUserD_HAL(pKernelFifo, KERNEL_POINTER_FROM_NvP64(NvU8 *, pUserDMem)); - - memdescUnmap(pUserdSubDeviceMemDesc, - NV_TRUE, - osGetCurrentProcess(), - pUserDMem, - pPriv); - } // Clear Userd if it is in FB for SRIOV environment without BUG 200577889 - else if (pUserdSubDeviceMemDesc && (memdescGetAddressSpace(pUserdSubDeviceMemDesc) == ADDR_FBMEM) - && bFullSriov) - { - NvU8 *pUserDMem; - - pUserDMem = kbusMapRmAperture_HAL(pGpu, - pKernelChannel->pUserdSubDeviceMemDesc[gpumgrGetSubDeviceInstanceFromGpu(pGpu)]); - - NV_ASSERT_OR_ELSE(pUserDMem != NULL, status = NV_ERR_INSUFFICIENT_RESOURCES; goto failed); - - kfifoSetupUserD_HAL(pKernelFifo, pUserDMem); - - kbusUnmapRmAperture_HAL(pGpu, pUserdSubDeviceMemDesc, &pUserDMem, - NV_TRUE); - } + kfifoSetupUserD_HAL(pGpu, pKernelFifo, pUserdSubDeviceMemDesc); + } } return NV_OK; @@ -3479,25 +3454,6 @@ kchannelSetEngineContextMemDesc_IMPL } // - // If the VAList is not managed by RM, remove all VAs here. - // If the VAList is managed by RM, unmap and remove all VAs in kchannelUnmapEngineCtxBuf() - // - if (!vaListGetManaged(&pEngCtxDesc->vaList)) - { - status = _kchannelClearVAList(pGpu, &pEngCtxDesc->vaList, NV_FALSE); - NV_ASSERT_OR_ELSE(status == NV_OK, SLI_LOOP_GOTO(fail)); - } - - // - // Free all subcontext headers in TSG. This usually happens while last channel in TSG is being freed. - // we make sure all GR objects have already been freed before this point(see kgrctxUnmapAssociatedCtxBuffers). - // Other cases where this is exercised are special cases like golden image init where ctx buffers are swapped, - // control calls which force ctx buffer unmap, re-initializing of virtual ctxs, evicting a ctx, fifoStateDestroy etc. - // - if(IS_GR(engDesc)) - { - status = kchangrpFreeGrSubcontextHdrs_HAL(pGpu, pKernelChannelGroup); - } } else { @@ -3580,15 +3536,8 @@ kchannelUnmapEngineCtxBuf_IMPL SLI_LOOP_CONTINUE; } - // Only unmaps if RM manages this VAList - if (!vaListGetManaged(&pEngCtxDesc->vaList)) - { - SLI_LOOP_CONTINUE; - } - - // Clear VA list, including unmap - NV_ASSERT(memdescGetAddressSpace(memdescGetMemDescFromGpu(pEngCtxDesc->pMemDesc, pGpu)) != ADDR_VIRTUAL); - status = _kchannelClearVAList(pGpu, &pEngCtxDesc->vaList, NV_TRUE); + // Clear VA list, including unmap if managed + status = _kchannelClearVAList(pGpu, &pEngCtxDesc->vaList, vaListGetManaged(&pEngCtxDesc->vaList)); NV_ASSERT_OR_ELSE(status == NV_OK, SLI_LOOP_GOTO(fail)); SLI_LOOP_END diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group.c b/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group.c index d01c66245..3cbdd2a34 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group.c @@ -147,7 +147,9 @@ kchangrpInit_IMPL } // Determine initial runlist for this TSG, using engine type if provided - pKernelChannelGroup->runlistId = kchangrpGetDefaultRunlist_HAL(pGpu, pKernelChannelGroup); + pKernelChannelGroup->runlistId = kfifoGetDefaultRunlist_HAL(pGpu, + pKernelFifo, + pKernelChannelGroup->engineType); if (kfifoIsPerRunlistChramEnabled(pKernelFifo)) { diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group_api.c b/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group_api.c index 15a77d21d..84af1d4f6 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group_api.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group_api.c @@ -167,8 +167,7 @@ kchangrpapiConstruct_IMPL // to determine runlistId from engineId passed by client. This // runlistId is used to associate all future channels in this TSG to // that runlist. Setting the engineType will cause the runlist - // corresponding to that engine to be chosen in - // kchangrpGetDefaultRunlist_HAL. + // corresponding to that engine to be chosen. // pKernelChannelGroup->engineType = rmEngineType; } @@ -273,20 +272,28 @@ kchangrpapiConstruct_IMPL // Memory needs to be reserved in the pool only for buffers for // engines in instance. // + + // + // Size of memory that will be calculated for ctxBufPool reservation if ctxBufPool is enabled and MIG is disabled + // or current engine belongs to this MIG instance and MIG is enabled + // if (pKernelChannelGroup->pCtxBufPool != NULL && - kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, pKernelChannelGroup->engineType, ref)) + (!bMIGInUse || kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, pKernelChannelGroup->engineType, ref))) { // GR Buffers if (RM_ENGINE_TYPE_IS_GR(pKernelChannelGroup->engineType)) { KernelGraphics *pKernelGraphics = GPU_GET_KERNEL_GRAPHICS(pGpu, RM_ENGINE_TYPE_GR_IDX(pKernelChannelGroup->engineType)); - NvU32 bufId; + NvU32 bufId = 0; portMemSet(&bufInfoList[0], 0, sizeof(CTX_BUF_INFO) * NV_ENUM_SIZE(GR_CTX_BUFFER)); bufCount = 0; + + kgraphicsDiscoverMaxLocalCtxBufferSize(pGpu, pKernelGraphics); + FOR_EACH_IN_ENUM(GR_CTX_BUFFER, bufId) { // TODO expose engine class capabilities to kernel RM - if (kgrmgrIsCtxBufSupported(bufId, !IS_MIG_ENABLED(pGpu))) + if (kgrmgrIsCtxBufSupported(bufId, NV_FALSE)) { const CTX_BUF_INFO *pBufInfo = kgraphicsGetCtxBufferInfo(pGpu, pKernelGraphics, bufId); bufInfoList[bufCount] = *pBufInfo; @@ -1073,7 +1080,8 @@ kchangrpapiCtrlCmdGpFifoSchedule_IMPL // If no channels have a runlist set, get the default and use it. if (runlistId == INVALID_RUNLIST_ID) { - runlistId = kchangrpGetDefaultRunlist_HAL(pGpu, pKernelChannelGroup); + runlistId = kfifoGetDefaultRunlist_HAL(pGpu, pKernelFifo, + pKernelChannelGroup->engineType); } // We can rewrite TSG runlist id just as we will do that for all TSG channels below diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_ctxshare.c b/src/nvidia/src/kernel/gpu/fifo/kernel_ctxshare.c index b67d5f3c6..ac62b16f6 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_ctxshare.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_ctxshare.c @@ -505,13 +505,11 @@ kctxshareDestroyCommon_IMPL ) { NV_STATUS status = NV_OK; - NvU32 subctxId, i; + NvU32 subctxId; + NvU32 i; KernelChannelGroup *pKernelChannelGroup; - NvU32 subDevInst; - ENGINE_CTX_DESCRIPTOR *pEngCtxDesc = NULL; NvU64 numMax = 0; NvBool bRelease = NV_TRUE; - NvU64 vaddr = 0; RsShared *pShared = NULL; NvS32 refcnt = 0; @@ -560,54 +558,6 @@ kctxshareDestroyCommon_IMPL } } - SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY | SLI_LOOP_FLAGS_IGNORE_REENTRANCY) - RsResourceRef *pParentRef = RES_GET_REF(pKernelCtxShareApi)->pParentRef; - KernelChannelGroupApi *pKernelChannelGroupApi = dynamicCast(pParentRef->pResource, KernelChannelGroupApi); - KernelGraphicsContext *pKernelGraphicsContext; - - subDevInst = gpumgrGetSubDeviceInstanceFromGpu(pGpu); - if ((pKernelChannelGroup->ppEngCtxDesc != NULL) && - kgrctxFromKernelChannelGroupApi(pKernelChannelGroupApi, &pKernelGraphicsContext) == NV_OK) - { - if (bRelease) - { - KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pKernelGraphicsContext); - NvHandle hParent = RES_GET_PARENT_HANDLE(pKernelGraphicsContext); - NV2080_CTRL_GR_ROUTE_INFO grRouteInfo; - KernelGraphics *pKernelGraphics; - - portMemSet(&grRouteInfo, 0, sizeof(grRouteInfo)); - kgrmgrCtrlSetChannelHandle(hParent, &grRouteInfo); - - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &grRouteInfo, &pKernelGraphics); - - pEngCtxDesc = pKernelChannelGroup->ppEngCtxDesc[subDevInst]; - if (pEngCtxDesc != NULL) - { - vaddr = 0; - if (vaListFindVa(&pEngCtxDesc->vaList, pKernelCtxShare->pVAS, &vaddr) == NV_OK) - { - NvU64 tmpVaddr = 0; - while (vaListFindVa(&pEngCtxDesc->vaList, pKernelCtxShare->pVAS, &tmpVaddr) == NV_OK) - { - status = vaListRemoveVa(&pEngCtxDesc->vaList, pKernelCtxShare->pVAS); - NV_ASSERT(status == NV_OK); - } - - if (vaListGetManaged(&pEngCtxDesc->vaList)) - { - dmaUnmapBuffer_HAL(pGpu, GPU_GET_DMA(pGpu), pKernelCtxShare->pVAS, vaddr); - } - } - } - } - } - SLI_LOOP_END - - - subDevInst = gpumgrGetSubDeviceInstanceFromGpu(pGpu); - status = kctxshareDestroy_HAL(pKernelCtxShare, pKernelCtxShareApi, pGpu, pKernelChannelGroupApi, bRelease); if (status != NV_OK) { diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c index ca4394814..b426bbb4c 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c @@ -64,6 +64,20 @@ static void _kfifoChidMgrDestroyChannelGroupMgr(CHID_MGR *pChidMgr); static NV_STATUS _kfifoChidMgrFreeIsolationId(CHID_MGR *pChidMgr, NvU32 ChID); + +NvU32 kfifoGetNumEschedDrivenEngines_IMPL +( + KernelFifo *pKernelFifo +) +{ + const ENGINE_INFO *pEngineInfo; + NV_ASSERT(kfifoGetNumEngines_HAL(ENG_GET_GPU(pKernelFifo), pKernelFifo) > + 0); + pEngineInfo = kfifoGetEngineInfo(pKernelFifo); + return pEngineInfo->numRunlists; +} + + NV_STATUS kfifoChidMgrConstruct_IMPL ( @@ -953,6 +967,7 @@ kfifoChidMgrFreeChid_IMPL pChidMgr->pFifoDataHeap, ChID, NV_FALSE); + NV_ASSERT_OR_RETURN(pFifoDataBlock != NULL, NV_ERR_OBJECT_NOT_FOUND); NV_ASSERT(pFifoDataBlock->refCount > 0); pFifoDataBlock->pData = NULL; @@ -999,6 +1014,7 @@ kfifoChidMgrReserveSystemChids_IMPL NvU32 flags, NvU32 gfid, NvU32 *pChidOffset, + NvU32 *pChannelCount, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList @@ -1063,8 +1079,8 @@ kfifoChidMgrReserveSystemChids_IMPL pIsolationIdBlock->pData = pIsolationID; status = kfifoSetChidOffset(pGpu, pKernelFifo, pChidMgr, (NvU32)offset, - numChannels, gfid, pChidOffset, hMigClient, - engineFifoListNumEntries, pEngineFifoList); + numChannels, gfid, pChidOffset, pChannelCount, + hMigClient, engineFifoListNumEntries, pEngineFifoList); if (status != NV_OK) { @@ -1102,7 +1118,7 @@ kfifoChidMgrReserveSystemChids_IMPL cleanup: portMemFree(pChidMgr->ppVirtualChIDHeap[gfid]); NV_ASSERT(kfifoSetChidOffset(pGpu, pKernelFifo, pChidMgr, 0, 0, - gfid, pChidOffset, hMigClient, + gfid, pChidOffset, pChannelCount, hMigClient, engineFifoListNumEntries, pEngineFifoList) == NV_OK); NV_ASSERT(pChidMgr->pGlobalChIDHeap->eheapFree(pChidMgr->pGlobalChIDHeap, offset) == NV_OK); portMemFree(pIsolationID); @@ -1118,6 +1134,7 @@ kfifoChidMgrFreeSystemChids_IMPL CHID_MGR *pChidMgr, NvU32 gfid, NvU32 *pChidOffset, + NvU32 *pChannelCount, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList @@ -1162,7 +1179,7 @@ kfifoChidMgrFreeSystemChids_IMPL } tmpStatus = kfifoSetChidOffset(pGpu, pKernelFifo, pChidMgr, 0, 0, - gfid, pChidOffset, hMigClient, + gfid, pChidOffset, pChannelCount, hMigClient, engineFifoListNumEntries, pEngineFifoList); if (tmpStatus != NV_OK) { @@ -1865,7 +1882,6 @@ kfifoGetHostDeviceInfoTable_KERNEL NvU32 numRunlists; NvU32 maxRunlistId; NvU32 maxPbdmaId; - NvU32 minPbdmaFaultId; NvU32 i; struct { NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS params; @@ -1960,7 +1976,6 @@ kfifoGetHostDeviceInfoTable_KERNEL numRunlists = 0; maxRunlistId = 0; maxPbdmaId = 0; - minPbdmaFaultId = NV_U32_MAX; for (entry = 0; entry < numEntries; ++entry) { portMemCopy(pEngineInfo->engineInfoList[entry].engineData, @@ -1984,7 +1999,7 @@ kfifoGetHostDeviceInfoTable_KERNEL (char *)pHostEntries[entry].engineName, FIFO_ENGINE_NAME_MAX_SIZE); - if (0 != pEngineInfo->engineInfoList[entry].engineData[ENGINE_INFO_TYPE_IS_ENGINE]) + if (pEngineInfo->engineInfoList[entry].engineData[ENGINE_INFO_TYPE_IS_HOST_DRIVEN_ENGINE] != 0) { numRunlists++; } @@ -2001,29 +2016,22 @@ kfifoGetHostDeviceInfoTable_KERNEL // if (pEngineInfo->engineInfoList[entry].engineData[ENGINE_INFO_TYPE_ENG_DESC] != ENG_SW) { - minPbdmaFaultId = NV_MIN(minPbdmaFaultId, pEngineInfo->engineInfoList[entry].pbdmaFaultIds[i]); + bitVectorSet(&pEngineInfo->validEngineIdsForPbdmas, pEngineInfo->engineInfoList[entry].pbdmaFaultIds[i]); } } } + NV_ASSERT_OR_GOTO(kfifoReservePbdmaFaultIds_HAL(pGpu, pKernelFifo, pEngineInfo->engineInfoList, + pEngineInfo->engineInfoListSize) == NV_OK, cleanup); + if (IS_VIRTUAL(pGpu)) { _kfifoLocalizeGuestEngineData(pGpu, pKernelFifo, pEngineInfo); } - // - // Host RM sends back a copy of their devinfo table, which includes the SW - // engine. This engine has no runlist, so decrement the runlist count. - // - if (numRunlists > 0) - { - --numRunlists; - } - pEngineInfo->numRunlists = numRunlists; pEngineInfo->maxNumRunlists = maxRunlistId + 1; pEngineInfo->maxNumPbdmas = maxPbdmaId + 1; - pEngineInfo->basePbdmaFaultId = minPbdmaFaultId; cleanup: portMemFree(pLocals); @@ -3071,6 +3079,7 @@ kfifoSetChidOffset_IMPL NvU32 numChannels, NvU32 gfid, NvU32 *pChidOffset, + NvU32 *pChannelCount, NvU32 hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList @@ -3094,6 +3103,7 @@ kfifoSetChidOffset_IMPL { NV_ASSERT_OR_ELSE(NV2080_ENGINE_TYPE_IS_VALID(pEngineIds[i]), status = NV_ERR_INVALID_STATE; goto cleanup); pChidOffset[pEngineIds[i]] = offset; + pChannelCount[pEngineIds[i]] = numChannels; } NV_ASSERT_OK_OR_GOTO(status, kfifoProgramChIdTable_HAL(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_ctrl.c b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_ctrl.c index 9fa61353f..b5fb057e4 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_ctrl.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_ctrl.c @@ -44,11 +44,7 @@ static NV_STATUS _kfifoGetCaps(OBJGPU *pGpu, NvU8 *pKfifoCaps); /*! - * * @brief deviceCtrlCmdFifoGetChannelList - * - * Lock Requirements: - * Assert that API lock and GPUs lock held on entry */ NV_STATUS deviceCtrlCmdFifoGetChannelList_IMPL @@ -62,8 +58,6 @@ deviceCtrlCmdFifoGetChannelList_IMPL NvU32 *pChannelList = NvP64_VALUE(pChannelParams->pChannelList); NvU32 counter; - LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); - // Validate input / Size / Args / Copy args if (pChannelParams->numChannels == 0) { @@ -484,11 +478,15 @@ subdeviceCtrlCmdFifoGetChannelMemInfo_IMPL // Get RAMFC mem Info pMemDesc = NULL; - kfifoChannelGetFifoContextMemDesc_HAL(pGpu, + rmStatus = kfifoChannelGetFifoContextMemDesc_HAL(pGpu, pKernelFifo, pKernelChannel, FIFO_CTX_RAMFC, &pMemDesc); + + if (rmStatus != NV_OK) + return rmStatus; + kfifoFillMemInfo(pKernelFifo, pMemDesc, &chMemInfo.ramfc); // Get Method buffer mem info diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_init.c b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_init.c index 66ee7c582..a65a0b077 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_init.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_init.c @@ -150,7 +150,7 @@ kfifoStateInitLocked_IMPL { krcInitRegistryOverridesDelayed(pGpu, pKernelRc); } - + return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c b/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c index ed3114efc..689ccaec0 100644 --- a/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c +++ b/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c @@ -32,8 +32,10 @@ #include "gpu/gsp/kernel_gsp.h" #include "published/hopper/gh100/dev_fsp_pri.h" -#include "published/hopper/gh100/dev_fsp_addendum.h" +#include "fsp/fsp_nvdm_format.h" #include "published/hopper/gh100/dev_gc6_island_addendum.h" +#include "published/hopper/gh100/dev_falcon_v4.h" +#include "published/hopper/gh100/dev_gsp.h" #include "published/hopper/gh100/dev_therm.h" #include "published/hopper/gh100/dev_therm_addendum.h" #include "os/os.h" @@ -170,7 +172,7 @@ kfspGetRmChannelSize_GH100 NvU8 kfspNvdmToSeid_GH100 ( - POBJGPU pGpu, + OBJGPU *pGpu, KernelFsp *pKernelFsp, NvU8 nvdmType ) @@ -657,7 +659,7 @@ kfspCheckGspSecureScratch_GH100 static const BINDATA_ARCHIVE * kfspGetGspUcodeArchive ( - POBJGPU pGpu, + OBJGPU *pGpu, KernelFsp *pKernelFsp ) { @@ -733,7 +735,7 @@ kfspGetGspUcodeArchive static NV_STATUS kfspGetGspBootArgs ( - POBJGPU pGpu, + OBJGPU *pGpu, KernelFsp *pKernelFsp, RmPhysAddr *pBootArgsGspSysmemOffset ) @@ -765,7 +767,7 @@ kfspGetGspBootArgs static NV_STATUS kfspSetupGspImages ( - POBJGPU pGpu, + OBJGPU *pGpu, KernelFsp *pKernelFsp, NVDM_PAYLOAD_COT *pCotPayload ) @@ -781,6 +783,12 @@ kfspSetupGspImages NvU32 pGspImageMapSize; NvP64 pVaKernel = NULL; NvP64 pPrivKernel = NULL; + NvU64 flags = MEMDESC_FLAGS_NONE; + + // + // On systems with SEV enabled, the GSP-FMC image has to be accessible + // to FSP (an unit inside GPU) and hence placed in unprotected sysmem + // // Detect the mode of operation for GSP and fetch the right image to boot pBinArchive = kfspGetGspUcodeArchive(pGpu, pKernelFsp); @@ -808,8 +816,7 @@ kfspSetupGspImages pGspImageMapSize = NV_ALIGN_UP(pGspImageSize, 0x1000); status = memdescCreate(&pKernelFsp->pGspFmcMemdesc, pGpu, pGspImageMapSize, - 0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_UNCACHED, - MEMDESC_FLAGS_NONE); + 0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_UNCACHED, flags); NV_ASSERT_OR_GOTO(status == NV_OK, failed); status = memdescAlloc(pKernelFsp->pGspFmcMemdesc); @@ -851,10 +858,58 @@ failed: return status; } +/*! + * Determine if PRIV target mask is unlocked for GSP and BAR0 Decoupler allows GSP access. + * + * This is temporary WAR for the PRIV target mask bug 3640831 until we have notification + * protocol in place (there is no HW mechanism for CPU to check if GSP is open other than + * reading 0xBADF41YY code). + * + * Until the programmed BAR0 decoupler settings are cleared, GSP access is blocked from + * the CPU so all reads will return 0. + */ +static NvBool +_kfspIsGspTargetMaskReleased +( + OBJGPU *pGpu, + void *pVoid +) +{ + const NvU32 privErrTargetLocked = 0xBADF4100U; + const NvU32 privErrTargetLockedMask = 0xFFFFFF00U; // Ignore LSB - it has extra error information + NvU32 reg; + + // + // This register is read with the raw OS read to avoid the 0xbadf sanity checking + // done by the usual register read utilities. + // + reg = osDevReadReg032(pGpu, gpuGetDeviceMapping(pGpu, DEVICE_INDEX_GPU, 0), + DRF_BASE(NV_PGSP) + NV_PFALCON_FALCON_HWCFG2); + + return ((reg != 0) && ((reg & privErrTargetLockedMask) != privErrTargetLocked)); +} + +/*! + * Determine if GSP's target mask is released. + */ +NV_STATUS +kfspWaitForGspTargetMaskReleased_GH100 +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp +) +{ + NV_STATUS status = NV_OK; + + status = gpuTimeoutCondWait(pGpu, _kfspIsGspTargetMaskReleased, NULL, NULL); + + return status; +} + static NV_STATUS _kfspCheckGspBootStatus ( - POBJGPU pGpu, + OBJGPU *pGpu, KernelFsp *pKernelFsp ) { @@ -890,6 +945,15 @@ _kfspCheckGspBootStatus return status; } + // Ensure that for GH100+ TM is released before polling for priv lockdown release + status = kfspWaitForGspTargetMaskReleased_HAL(pGpu, pKernelFsp); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Timed out waiting for GSP's target mask to be released.\n"); + DBG_BREAKPOINT(); + return status; + } + // Ensure priv lockdown is released before polling interrupts gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, GPU_TIMEOUT_FLAGS_OSTIMER | GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE); do @@ -1070,9 +1134,14 @@ kfspSendBootCommands_GH100 // Set up sysmem for FRTS copy if (!pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_DISABLE_FRTS_SYSMEM)) { + NvU64 flags = MEMDESC_FLAGS_NONE; + + // + // On systems with SEV enabled, the FRTS has to be accessible to + // FSP (an unit inside GPU) and hence placed in unprotected sysmem + // status = memdescCreate(&pKernelFsp->pSysmemFrtsMemdesc, pGpu, frtsSize, - 0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_UNCACHED, - MEMDESC_FLAGS_NONE); + 0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_UNCACHED, flags); NV_ASSERT_OR_GOTO(status == NV_OK, failed); status = memdescAlloc(pKernelFsp->pSysmemFrtsMemdesc); diff --git a/src/nvidia/src/kernel/gpu/gpu.c b/src/nvidia/src/kernel/gpu/gpu.c index 9a7239b6d..4d7aa96f9 100644 --- a/src/nvidia/src/kernel/gpu/gpu.c +++ b/src/nvidia/src/kernel/gpu/gpu.c @@ -46,6 +46,7 @@ #include "rmapi/rmapi_utils.h" #include "core/hal_mgr.h" #include "vgpu/rpc.h" +#include "jt.h" #include "gpu/gpu_fabric_probe.h" #include "vgpu/vgpu_events.h" @@ -104,7 +105,7 @@ static NV_STATUS gpuStatePostUnload(OBJGPU *, NvU32); static void gpuXlateHalImplToArchImpl(OBJGPU *, HAL_IMPLEMENTATION, NvU32 *, NvU32 *); static NvBool gpuSatisfiesTemporalOrder(OBJGPU *, HAL_IMPLEMENTATION); static NvBool gpuSatisfiesTemporalOrderMaskRev(OBJGPU *, HAL_IMPLEMENTATION, NvU32, NvU32, NvU32); -static NvBool gpuShouldCreateObject(PGPUCHILDINFO, PENGDESCRIPTOR, NvU32); +static NvBool gpuShouldCreateObject(OBJGPU *pGpu, GPUCHILDINFO *pChildInfo); static void gpuDestroyMissingEngine(OBJGPU *, OBJENGSTATE *); static void gpuRemoveMissingEngineClasses(OBJGPU *, NvU32); @@ -136,7 +137,7 @@ static inline void _setPlatformNoHostbridgeDetect(NvBool bValue) } // Forward declare all the class definitions so that we don't need to pull in all the headers -#define GPU_CHILD(className, accessorName, numInstances, bConstructEarly, bAlwaysCreate, gpuField) \ +#define GPU_CHILD(className, accessorName, numInstances, bConstructEarly, gpuField) \ extern const struct NVOC_CLASS_DEF NV_CONCATENATE(__nvoc_class_def_, className); #include "gpu/gpu_child_list.h" @@ -148,17 +149,16 @@ struct GPUCHILDTYPE NvBool bConstructEarly; // bConstructEarly objects are created in a separate step. FUSE must be created // before BIF since we need to know the OPSB fuse value for enabling/disabling // certain features in bifInitRegistryOverrides - NvBool bAlwaysCreate; NvU32 instances; NvU32 gpuChildPtrOffset; - const NVOC_CLASS_INFO *pClassInfo; // NULL if engine is disabled by chip-config + const NVOC_CLASS_INFO *pClassInfo; }; // List of all possible GPU offspring static GPUCHILDTYPE gpuChildTypeList[] = { - #define GPU_CHILD(className, accessorName, numInstances, bConstructEarly, bAlwaysCreate, gpuField) \ - { bConstructEarly, bAlwaysCreate, numInstances, NV_OFFSETOF(OBJGPU, gpuField), classInfo(className) }, + #define GPU_CHILD(className, accessorName, numInstances, bConstructEarly, gpuField) \ + { bConstructEarly, numInstances, NV_OFFSETOF(OBJGPU, gpuField), classInfo(className) }, #include "gpu/gpu_child_list.h" }; @@ -166,7 +166,6 @@ static GPUCHILDTYPE gpuChildTypeList[] = // Describes a child instance (e.g.: classId(OBJCE) instanceID #1) struct GPUCHILDINFO { - NvBool bAlwaysCreate; NvBool bConstructEarly; ENGDESCRIPTOR engDesc; NvU32 gpuChildPtrOffset; @@ -839,7 +838,7 @@ _gpuCreateEngineOrderList ct_assert(NV_ARRAY_ELEMENTS32(ppEngDescriptors) == NV_ARRAY_ELEMENTS32(listTypes)); -#define GPU_CHILD(a, b, numInstances, c, d, e) +numInstances +#define GPU_CHILD(a, b, numInstances, c, d) +numInstances struct ChildList { char children[ 0 + @@ -992,7 +991,6 @@ gpuGetChildInfo(NVOC_CLASS_ID classId, NvU32 instanceID, PGPUCHILDINFO pChildInf NV_ASSERT_OR_RETURN(pChildType && (instanceID < pChildType->instances), NV_ERR_INVALID_OBJECT); pChildInfoOut->engDesc = MKENGDESC(classId, instanceID); - pChildInfoOut->bAlwaysCreate = pChildType->bAlwaysCreate; pChildInfoOut->bConstructEarly = pChildType->bConstructEarly; pChildInfoOut->pClassInfo = pChildType->pClassInfo; pChildInfoOut->pChildType = pChildType; @@ -1016,7 +1014,7 @@ gpuGetChildType(NVOC_CLASS_ID classId) for (i = 0; i < GPU_NUM_CHILD_TYPES; i++) { - if (gpuChildTypeList[i].pClassInfo && gpuChildTypeList[i].pClassInfo->classId == classId) + if (gpuChildTypeList[i].pClassInfo->classId == classId) { return &gpuChildTypeList[i]; } @@ -1058,7 +1056,7 @@ gpuGetNextPossibleEngDescriptor(GPU_CHILD_ITER *pIt, ENGDESCRIPTOR *pEngDesc) pChildType = &gpuChildTypeList[pIt->childTypeIdx]; // Advance instance # - if (pIt->childInst < pChildType->instances && pChildType->pClassInfo) + if (pIt->childInst < pChildType->instances) { NV_STATUS status = gpuGetChildInfo(pChildType->pClassInfo->classId, pIt->childInst, &childInfo); @@ -1325,11 +1323,6 @@ gpuDestruct_IMPL { pChildTypeCur = &gpuChildTypeList[typeNum]; - if (!pChildTypeCur->pClassInfo) - { - continue; - } - for (instNum = pChildTypeCur->instances - 1; instNum >= 0; instNum--) { NV_STATUS status; @@ -1412,25 +1405,16 @@ gpuCreateChildObjects NvBool bConstructEarly ) { - PENGDESCRIPTOR pEngDescriptors; - NvU32 numEngDescriptors; PGPUCHILDTYPE pChildTypeCur; GPUCHILDINFO childInfoCur; NvU32 t, i; NV_STATUS rmStatus = NV_OK; - pEngDescriptors = gpuGetInitEngineDescriptors(pGpu); - numEngDescriptors = gpuGetNumEngDescriptors(pGpu); for (t = 0; t < GPU_NUM_CHILD_TYPES; t++) { pChildTypeCur = &gpuChildTypeList[t]; - if (!pChildTypeCur->pClassInfo) - { - continue; - } - for (i = 0; i < pChildTypeCur->instances; i++) { NVOC_CLASS_ID classId = pChildTypeCur->pClassInfo->classId; @@ -1440,9 +1424,8 @@ gpuCreateChildObjects NV_ASSERT(rmStatus == NV_OK); if ((bConstructEarly == childInfoCur.bConstructEarly) && - gpuShouldCreateObject(&childInfoCur, - pEngDescriptors, - numEngDescriptors)) + gpuShouldCreateObject(pGpu, + &childInfoCur)) { rmStatus = gpuCreateObject(pGpu, classId, i); @@ -1472,29 +1455,25 @@ gpuCreateChildObjects static NvBool gpuShouldCreateObject ( - PGPUCHILDINFO pChildInfo, - PENGDESCRIPTOR pEngDescriptors, - NvU32 numEngDescriptors + OBJGPU *pGpu, + GPUCHILDINFO *pChildInfo ) { NvBool retVal = NV_FALSE; - NvU32 curEngDescIdx; + NvU32 numChildPresent; + const GPUCHILDPRESENT *const pChildPresentList = + gpuGetChildrenPresent_HAL(pGpu, &numChildPresent); + NvU32 childIdx; - if (pChildInfo->bAlwaysCreate) + // Let the HAL confirm that we should create an object for this engine. + for (childIdx = 0; childIdx < numChildPresent; childIdx++) { - // For now all SW engines get created - retVal = NV_TRUE; - } - else - { - // Let the HAL confirm that we should create an object for this engine. - for (curEngDescIdx = 0; curEngDescIdx < numEngDescriptors; curEngDescIdx++) + if ((ENGDESC_FIELD(pChildInfo->engDesc, _CLASS) == + pChildPresentList[childIdx].classId)) { - if (pChildInfo->engDesc == pEngDescriptors[curEngDescIdx]) - { - retVal = NV_TRUE; - break; - } + retVal = (ENGDESC_FIELD(pChildInfo->engDesc, _INST) < + pChildPresentList[childIdx].instances); + break; } } @@ -2181,15 +2160,13 @@ gpuStateLoad_IMPL return status; } - if (!(flags & GPU_STATE_FLAGS_PRESERVING)) + // It is a no-op on baremetal and inside non SRIOV guest. + rmStatus = gpuCreateDefaultClientShare_HAL(pGpu); + if (rmStatus != NV_OK) { - // It is a no-op on baremetal and inside non SRIOV guest. - rmStatus = gpuCreateDefaultClientShare_HAL(pGpu); - if (rmStatus != NV_OK) - { - return rmStatus; - } + return rmStatus; } + NV_ASSERT(!gpumgrGetBcEnabledStatus(pGpu)); rmStatus = gpuStatePreLoad(pGpu, flags); @@ -2274,11 +2251,30 @@ gpuStateLoad_IMPL if (rmStatus != NV_OK) goto gpuStateLoad_exit; + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_PM_RESUME_CODEPATH) && + pGpu->bRecheckSliSupportAtResume) + { + NvU32 gpuAttachCnt, gpuAttachMask; + NvU32 gpuInstance = 0; + OBJGPU *gpuLoop; + NvU32 numPoweredOn = 1; // Include the current pGpu + gpumgrGetGpuAttachInfo(&gpuAttachCnt, &gpuAttachMask); + + while ((gpuLoop = gpumgrGetNextGpu(gpuAttachMask, &gpuInstance))) + { + if (gpuIsGpuFullPower(gpuLoop)) + numPoweredOn++; + } + if (numPoweredOn == gpuAttachCnt) + { + RmInitScalability(pGpu); + } + } } { NvBool bVgpuOnGspEnabled = IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && RMCFG_FEATURE_PLATFORM_GSP; - if ((hypervisorIsVgxHyper() || bVgpuOnGspEnabled) && + if ((hypervisorIsVgxHyper() || bVgpuOnGspEnabled) && !pGpu->getProperty(pGpu, PDB_PROP_GPU_ACCOUNTING_ON)) { OBJSYS *pSys = SYS_GET_INSTANCE(); @@ -2328,7 +2324,7 @@ _gpuRemoveP2pCapsFromPeerGpus NvU32 gpuCount; NvU32 gpuIndex; - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, gpumgrGetGpuAttachInfo(&gpuCount, &attachMask)); gpuIndex = 0; while ((pPeerGpu = gpumgrGetNextGpu(attachMask, &gpuIndex)) != NULL) @@ -2386,7 +2382,7 @@ _gpuPropagateP2PCapsToAllGpus peerGpuInstances != NULL, status = NV_ERR_NO_MEMORY; goto exit); - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, gpumgrGetGpuAttachInfo(&gpuCount, &attachMask), exit); @@ -2484,7 +2480,7 @@ fail: NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS, &removeP2PCapsParams, sizeof(removeP2PCapsParams))); } - + exit: portMemFree(pSetP2PCapsParams); pSetP2PCapsParams = NULL; @@ -2547,6 +2543,16 @@ gpuStatePostLoad NvU32 numEngDescriptors; NvU32 curEngDescIdx; NV_STATUS rmStatus = NV_OK; +#if RMCFG_FEATURE_SLINEXT && defined(DEBUG) + NvU32 numPoweredOn = 0; + + SLI_LOOP_START(SLI_LOOP_FLAGS_IGNORE_REENTRANCY) + numPoweredOn++; + SLI_LOOP_END + + // Ensure all GPUs are available + NV_ASSERT(gpumgrGetSubDeviceCountFromGpu(pGpu) == numPoweredOn); +#endif engDescriptorList = gpuGetLoadEngineDescriptors(pGpu); numEngDescriptors = gpuGetNumEngDescriptors(pGpu); @@ -2588,6 +2594,9 @@ gpuStatePostLoad goto gpuStatePostLoad_exit; } + // Caching GID data, the GID is generated by PMU and passed to RM during PMU INIT message. + //NV_ASSERT_OK(gpuGetGidInfo(pGpu, NULL, NULL, DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _TYPE, _SHA1))); + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_ERROR, _gpuSetVgpuMgrConfig(pGpu), @@ -2825,8 +2834,7 @@ gpuStateUnload_IMPL rmStatus = gpuStatePostUnload(pGpu, flags); NV_ASSERT_OK(rmStatus); - if(!(flags & GPU_STATE_FLAGS_PRESERVING)) - gpuDestroyDefaultClientShare_HAL(pGpu); + gpuDestroyDefaultClientShare_HAL(pGpu); // De-init SRIOV gpuDeinitSriov_HAL(pGpu); @@ -3053,12 +3061,16 @@ gpuIsImplementation_IMPL NV_STATUS gpuInitOptimusSettings_IMPL(OBJGPU *pGpu) { - OBJOS *pOS = GPU_GET_OS(pGpu); NV_STATUS status; NvU32 inOut; NvU32 data32; NvU16 rtnSize; + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_MOBILE)) + { + return NV_OK; + } + // Check regkey settings if (osReadRegistryDword(pGpu, NV_REG_STR_RM_D3_FEATURE, &data32) == NV_OK) @@ -3110,11 +3122,11 @@ gpuInitOptimusSettings_IMPL(OBJGPU *pGpu) // It doesn't matter if this was not successful as we will enable the driver side // save restore anyway. This call is to save some work for the SBIOS if possible. // - status = pOS->osCallACPI_DSM(pGpu, - ACPI_DSM_FUNCTION_NVOP, - NVOP_FUNC_OPTIMUSCAPS, - &inOut, - &rtnSize); + status = osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_NVOP, + NVOP_FUNC_OPTIMUSCAPS, + &inOut, + &rtnSize); if (status != NV_OK) { @@ -3137,11 +3149,15 @@ gpuInitOptimusSettings_IMPL(OBJGPU *pGpu) NV_STATUS gpuDeinitOptimusSettings_IMPL(OBJGPU *pGpu) { - OBJOS *pOS = GPU_GET_OS(pGpu); NV_STATUS status; NvU32 inOut; NvU16 rtnSize; + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_MOBILE)) + { + return NV_OK; + } + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE)) { rtnSize = (NvU16)sizeof(inOut); @@ -3149,11 +3165,11 @@ gpuDeinitOptimusSettings_IMPL(OBJGPU *pGpu) inOut = FLD_SET_DRF(OP_FUNC, _OPTIMUSCAPS, _CFG_SPACE_OWNER_WR_EN, _TRUE, inOut); inOut = FLD_SET_DRF(OP_FUNC, _OPTIMUSCAPS, _CFG_SPACE_OWNER_TARGET, _SBIOS, inOut); - status = pOS->osCallACPI_DSM(pGpu, - ACPI_DSM_FUNCTION_NVOP, - NVOP_FUNC_OPTIMUSCAPS, - &inOut, - &rtnSize); + status = osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_NVOP, + NVOP_FUNC_OPTIMUSCAPS, + &inOut, + &rtnSize); // NV_ASSERT_OR_RETURN(status == NV_OK, status); // NV_ASSERT_OR_RETURN(FLD_TEST_DRF(OP_FUNC, _OPTIMUSCAPS, _CFG_SPACE_OWNER_ACTUAL, // _SBIOS, inOut), @@ -3583,7 +3599,7 @@ gpuXlateHalImplToArchImpl // // default Logic: If halImpl is equal or greater than requested --> NV_TRUE // -// Arch and impl IDs are not guaranteed to be ordered. +// Arch and impl IDs are not guaranteed to be ordered. // "halImpl" is used here to match the ordering in chip-config/NVOC // // NOTE: only defined for gpus within same gpu series @@ -4486,17 +4502,6 @@ gpuGetNextInEngineOrderList(OBJGPU *pGpu, ENGLIST_ITER *pIt, PENGDESCRIPTOR pEng return NV_FALSE; } -/** - * Set SLI broadcast state in threadstate if SLI is enabled for the GPU - */ -void -gpuSetThreadBcState_IMPL(OBJGPU *pGpu, NvBool bcState) -{ - { - gpumgrSetBcEnabledStatus(pGpu, bcState); - } -} - NV_STATUS gpuInitDispIpHal_IMPL @@ -4766,3 +4771,99 @@ void gpuServiceInterruptsAllGpus_IMPL intrServiceStallListAllGpusCond(pGpu, pIntr, &engines, NV_TRUE); } } + + +NV_STATUS +gpuGetDeviceEntryByType_IMPL +( + OBJGPU *pGpu, + NvU32 deviceTypeEnum, + NvS32 groupId, + NvU32 instanceId, + const DEVICE_INFO2_ENTRY **ppDeviceEntry +) +{ + NvU32 i; + NV_ASSERT_OR_RETURN(ppDeviceEntry != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(groupId == DEVICE_INFO2_ENTRY_GROUP_ID_ANY || + groupId >= 0, + NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OK_OR_RETURN(gpuConstructDeviceInfoTable_HAL(pGpu)); + + *ppDeviceEntry = NULL; + + for (i = 0; i < pGpu->numDeviceInfoEntries; ++i) + { + const DEVICE_INFO2_ENTRY *pEntry = &pGpu->pDeviceInfoTable[i]; + if (pEntry->typeEnum == deviceTypeEnum && + (groupId == DEVICE_INFO2_ENTRY_GROUP_ID_ANY || + pEntry->groupId == (NvU32)groupId) && + pEntry->instanceId == instanceId) + { + *ppDeviceEntry = pEntry; + return NV_OK; + } + } + return NV_ERR_OBJECT_NOT_FOUND; +} + +/*! + * @brief Sets the GC6/JT SBIOS capability + * + * The capabilities are retrieved from the SBIOS through JT_FUNC_CAPS subfunction + * + * @param[in] pGpu GPU object pointer + * + * @return status bubble up the return status from osCallACPI_DSM + */ +NV_STATUS +gpuSetGC6SBIOSCapabilities_IMPL(OBJGPU *pGpu) +{ + NV_STATUS status; + + pGpu->acpiMethodData.jtMethodData.bSBIOSCaps = NV_FALSE; + + if ((!pGpu->acpiMethodData.bValid) || + (pGpu->acpiMethodData.jtMethodData.status != NV_OK)) + { + RMTRACE_SBIOS (_ACPI_DSM_ERROR, pGpu->gpuId, ACPI_DSM_FUNCTION_JT, JT_FUNC_CAPS, 0, 0, 0, 0, 0); + return NV_ERR_NOT_SUPPORTED; + } + + status = gpuJtVersionSanityCheck_HAL(pGpu); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Unsupported JT revision ID. GC6 is being disabled.\n"); + RMTRACE_SBIOS (_ACPI_DSM_ERROR, pGpu->gpuId, ACPI_DSM_FUNCTION_JT, JT_FUNC_CAPS, 0, 0, 0, 0, 0); + return status; + } + + if (FLD_TEST_DRF(_JT_FUNC, _CAPS, _JT_ENABLED, _TRUE, pGpu->acpiMethodData.jtMethodData.jtCaps)) + { + pGpu->acpiMethodData.jtMethodData.bSBIOSCaps = NV_TRUE; + + switch (pGpu->acpiMethodData.jtMethodData.jtRevId) + { + case NV_JT_FUNC_CAPS_REVISION_ID_1_03: + // GC6 2.0 production + break; + case NV_JT_FUNC_CAPS_REVISION_ID_2_00: + // GC6 3.0 and FGC6 production + break; + default: + NV_PRINTF(LEVEL_ERROR, + "Unsupported JT revision ID. GC6 is being disabled. Update the " + "board EC PIC FW. On Windows, update the SBIOS GC6 AML as well.\n"); + DBG_BREAKPOINT(); + pGpu->acpiMethodData.jtMethodData.bSBIOSCaps = NV_FALSE; + break; + } + + } + + RMTRACE_GPU(_GC6_SBIOS_CAP, pGpu->gpuId, pGpu->acpiMethodData.jtMethodData.jtCaps, pGpu->acpiMethodData.jtMethodData.jtRevId, pGpu->acpiMethodData.jtMethodData.bSBIOSCaps, 0, 0, 0, 0); + RMTRACE_SBIOS (_ACPI_DSM_METHOD, pGpu->gpuId, ACPI_DSM_FUNCTION_JT, JT_FUNC_CAPS, pGpu->acpiMethodData.jtMethodData.jtCaps, 0, 0, 0, 0); + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/gpu_access.c b/src/nvidia/src/kernel/gpu/gpu_access.c index b5c712c48..f0a73cd10 100644 --- a/src/nvidia/src/kernel/gpu/gpu_access.c +++ b/src/nvidia/src/kernel/gpu/gpu_access.c @@ -37,25 +37,15 @@ typedef enum { BAD_READ_UNKNOWN, } RMCD_BAD_READ_REASON; -static NV_STATUS _allocGpuIODevice(GPU_IO_DEVICE **ppIODevice); static void _gpuCleanRegisterFilterList(DEVICE_REGFILTER_INFO *); static NvU32 _gpuHandleReadRegisterFilter(OBJGPU *, DEVICE_INDEX devIndex, NvU32 devInstance, NvU32 addr, NvU32 accessSize, NvU32 *pFlags, THREAD_STATE_NODE *pThreadState); static void _gpuHandleWriteRegisterFilter(OBJGPU *, DEVICE_INDEX devIndex, NvU32 devInstance, NvU32 addr, NvU32 val, NvU32 accessSize, NvU32 *pFlags, THREAD_STATE_NODE *pThreadState); -static void _gpuApertureWriteRegUnicast(OBJGPU *, IO_APERTURE *pAperture, NvU32 addr, NvV32 val, NvU32 size); -static NvU32 _gpuApertureReadReg(IO_APERTURE *pAperture, NvU32 addr, NvU32 size); - -static NvU8 _gpuApertureReadReg008(IO_APERTURE *a, NvU32 addr); -static NvU16 _gpuApertureReadReg016(IO_APERTURE *a, NvU32 addr); -static NvU32 _gpuApertureReadReg032(IO_APERTURE *a, NvU32 addr); -static void _gpuApertureWriteReg008(IO_APERTURE *a, NvU32 addr, NvV8 value); -static void _gpuApertureWriteReg016(IO_APERTURE *a, NvU32 addr, NvV16 value); -static void _gpuApertureWriteReg032(IO_APERTURE *a, NvU32 addr, NvV32 value); -static void _gpuApertureWriteReg032Unicast(IO_APERTURE *a, NvU32 addr, NvV32 value); -static NvBool _gpuApertureValidReg(IO_APERTURE *a, NvU32 addr); +static void ioaprtWriteRegUnicast(OBJGPU *, IoAperture *pAperture, NvU32 addr, NvV32 val, NvU32 size); +static NvU32 ioaprtReadReg(IoAperture *pAperture, NvU32 addr, NvU32 size); static REGISTER_FILTER * _findGpuRegisterFilter(DEVICE_INDEX devIndex, NvU32 devInstance, NvU32 addr, REGISTER_FILTER *); -static NV_STATUS _gpuInitIODeviceAndAperture(OBJGPU *, NvU32, NvU32, RmPhysAddr, NvU32); +static NV_STATUS _gpuInitIOAperture(OBJGPU *pGpu, NvU32 deviceIndex, DEVICE_MAPPING *pMapping); NV_STATUS regAccessConstruct @@ -89,10 +79,7 @@ regAccessConstruct DEVICE_MAPPING *pMapping = gpuGetDeviceMapping(pGpu, deviceIndex, 0); if (pMapping != NULL) { - rmStatus = _gpuInitIODeviceAndAperture(pGpu, deviceIndex, - pMapping->gpuDeviceEnum, - pMapping->gpuNvPAddr, - pMapping->gpuNvLength); + rmStatus = _gpuInitIOAperture(pGpu, deviceIndex, pMapping); if (rmStatus != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -114,7 +101,7 @@ regAccessDestruct OBJGPU *pGpu = pRegisterAccess->pGpu; DEVICE_INDEX deviceIndex; NvU32 mappingNum; - IO_APERTURE *pIOAperture; + IoAperture *pIOAperture; REGISTER_FILTER *pNode; // Ignore attempt to destruct a not-fully-constructed RegisterAccess @@ -128,8 +115,7 @@ regAccessDestruct pIOAperture = pGpu->pIOApertures[deviceIndex]; if (pIOAperture != NULL) { - portMemFree(pIOAperture->pDevice); - ioaccessDestroyIOAperture(pIOAperture); + objDelete(pIOAperture); } } @@ -153,36 +139,6 @@ regAccessDestruct } } -/*! - * @brief Allocates GPU_IO_DEVICE object - * - * @param[in] ppIODevice Pointer to uninitialized GPU_IO_DEVICE - */ -static NV_STATUS -_allocGpuIODevice -( - GPU_IO_DEVICE **ppIODevice -) -{ - GPU_IO_DEVICE *pDevice; - - pDevice = portMemAllocNonPaged(sizeof(GPU_IO_DEVICE)); - if (pDevice == NULL) - { - NV_PRINTF(LEVEL_ERROR, - "memory allocation failed for GPU IO Device\n"); - DBG_BREAKPOINT(); - return NV_ERR_NO_MEMORY; - } - - portMemSet(pDevice, 0, sizeof(GPU_IO_DEVICE)); - - *ppIODevice = pDevice; - - return NV_OK; -} - - // // The following register I/O functions are organized into two groups; // a multi-chip unaware group and a multi-chip aware group. @@ -254,145 +210,195 @@ _regWriteUnicast } } +/*! + * @brief: Initialize an IoAperture instance in-place. + * + * @param[out] pAperture pointer to the IoAperture. + * @param[in] pParentAperture pointer to the parent of the new IoAperture. + * @param[in] offset offset from the parent APERTURE's baseAddress. + * @param[in] length length of the APERTURE. + * + * @return NV_OK upon success + * NV_ERR* otherwise. + */ +NV_STATUS +ioaprtInit +( + IoAperture *pAperture, + IoAperture *pParentAperture, + NvU32 offset, + NvU32 length +) +{ + return objCreateWithFlags(&pAperture, NVOC_NULL_OBJECT, IoAperture, NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT, pParentAperture, NULL, 0, 0, NULL, 0, offset, length); +} + +/*! + * Initialize an IoAperture instance. + * + * @param[in,out] pAperture pointer to IoAperture instance to be initialized. + * @param[in] pParentAperture pointer to parent of the new IoAperture. + * @param[in] deviceIndex device index + * @param[in] deviceInstance device instance + * @param[in] pMapping device register mapping + * @param[in] mappingStartAddr register address corresponding to the start of the mapping + * @param[in] offset offset from the parent APERTURE's baseAddress. + * @param[in] length length of the APERTURE. + * + * @return NV_OK when inputs are valid. + */ +NV_STATUS +ioaprtConstruct_IMPL +( + IoAperture *pAperture, + IoAperture *pParentAperture, + OBJGPU *pGpu, + NvU32 deviceIndex, + NvU32 deviceInstance, + DEVICE_MAPPING *pMapping, + NvU32 mappingStartAddr, + NvU32 offset, + NvU32 length +) +{ + if (pParentAperture != NULL) + { + NV_ASSERT_OR_RETURN(pMapping == NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pGpu == NULL || pGpu == pParentAperture->pGpu, NV_ERR_INVALID_ARGUMENT); + + pAperture->pGpu = pParentAperture->pGpu; + pAperture->deviceIndex = pParentAperture->deviceIndex; + pAperture->deviceInstance = pParentAperture->deviceInstance; + pAperture->pMapping = pParentAperture->pMapping; + pAperture->baseAddress = pParentAperture->baseAddress; + pAperture->mappingStartAddr = pParentAperture->mappingStartAddr; + + // Check if the child Aperture strides beyond the parent's boundary. + if ((length + offset) > pParentAperture->length) + { + NV_PRINTF(LEVEL_WARNING, + "Child aperture crosses parent's boundary, length %u offset %u, Parent's length %u\n", + length, offset, pParentAperture->length); + } + + } + else + { + NV_ASSERT_OR_RETURN(pMapping != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pGpu != NULL, NV_ERR_INVALID_ARGUMENT); + + pAperture->pGpu = pGpu; + pAperture->deviceIndex = deviceIndex; + pAperture->deviceInstance = deviceInstance; + pAperture->pMapping = pMapping; + pAperture->baseAddress = 0; + pAperture->mappingStartAddr = mappingStartAddr; + } + + pAperture->baseAddress += offset; + pAperture->length = length; + + return NV_OK; +} + static void -_gpuApertureWriteRegUnicast +ioaprtWriteRegUnicast ( OBJGPU *pGpu, - IO_APERTURE *pAperture, + IoAperture *pAperture, NvU32 addr, NvV32 val, NvU32 size ) { - NV_ASSERT_OR_RETURN_VOID(pAperture); - NV_ASSERT_OR_RETURN_VOID(pAperture->pDevice); - - GPU_IO_DEVICE *pDevice = (GPU_IO_DEVICE*) pAperture->pDevice; - NvU32 deviceIndex = pDevice->deviceIndex; - NvU32 instance = pDevice->instance; + NvU32 deviceIndex = pAperture->deviceIndex; + NvU32 instance = pAperture->deviceInstance; NvU32 regAddr = pAperture->baseAddress + addr; + NvU32 mappingRegAddr = regAddr - pAperture->mappingStartAddr; + DEVICE_MAPPING *pMapping = pAperture->pMapping; NvU32 flags = 0; NV_STATUS status; THREAD_STATE_NODE *pThreadState; - DEVICE_MAPPING *pMapping; - pMapping = gpuGetDeviceMapping(pGpu, deviceIndex, instance); - - if (pMapping == NULL) + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY)) { - NV_PRINTF(LEVEL_ERROR, - "Could not find mapping for reg %x, deviceIndex=0x%x instance=%d\n", - regAddr, deviceIndex, instance); - NV_ASSERT(0); - return; + status = gpuSanityCheckRegisterAccess(pGpu, regAddr, NULL); + if (status != NV_OK) + { + return; + } + + threadStateGetCurrentUnchecked(&pThreadState, pGpu); + + _gpuHandleWriteRegisterFilter(pGpu, deviceIndex, instance, regAddr, + val, size, &flags, pThreadState); } - status = gpuSanityCheckRegisterAccess(pGpu, regAddr, NULL); - if (status != NV_OK) - { - return; - } - - threadStateGetCurrentUnchecked(&pThreadState, pGpu); - - _gpuHandleWriteRegisterFilter(pGpu, deviceIndex, instance, regAddr, - val, size, &flags, pThreadState); - if (!(flags & REGISTER_FILTER_FLAGS_WRITE)) { switch (size) { case 8: - osDevWriteReg008(pGpu, pMapping, regAddr, 0xFFU & (val)); + osDevWriteReg008(pGpu, pMapping, mappingRegAddr, 0xFFU & (val)); break; case 16: - osDevWriteReg016(pGpu, pMapping, regAddr, 0xFFFFU & (val)); + osDevWriteReg016(pGpu, pMapping, mappingRegAddr, 0xFFFFU & (val)); break; case 32: - osDevWriteReg032(pGpu, pMapping, regAddr, val); + osDevWriteReg032(pGpu, pMapping, mappingRegAddr, val); break; } } } void -_gpuApertureWriteReg008 +ioaprtWriteReg08_IMPL ( - IO_APERTURE *pAperture, + IoAperture *pAperture, NvU32 addr, NvV8 val ) { - GPU_IO_DEVICE *pDevice = (GPU_IO_DEVICE*)pAperture->pDevice; - OBJGPU *pGpu = pDevice->pGpu; + NV_ASSERT(!gpumgrGetBcEnabledStatus(pAperture->pGpu)); - // - // NOTE: The SLI loop below reuses pAperture's values across all iterations - // OBJGPU's apertures are initialized to have the same baseAddress and length - // on all GPU device instances, so reusing the aperture here is fine. - // Device-specific instances are obtained via gpuGetDeviceMapping in the SLI loop. - // - SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY); - _gpuApertureWriteRegUnicast(pGpu, pAperture, addr, val, 8 /* size */); - SLI_LOOP_END; + ioaprtWriteRegUnicast(pAperture->pGpu, pAperture, addr, val, 8 /* size */); } void -_gpuApertureWriteReg016 +ioaprtWriteReg16_IMPL ( - IO_APERTURE *pAperture, + IoAperture *pAperture, NvU32 addr, NvV16 val ) { - GPU_IO_DEVICE *pDevice = (GPU_IO_DEVICE*)pAperture->pDevice; - OBJGPU *pGpu = pDevice->pGpu; + NV_ASSERT(!gpumgrGetBcEnabledStatus(pAperture->pGpu)); - // - // NOTE: The SLI loop below reuses pAperture's values across all iterations - // OBJGPU's apertures are initialized to have the same baseAddress and length - // on all GPU device instances, so reusing the aperture here is fine. - // Device-specific instances are obtained via gpuGetDeviceMapping in the SLI loop. - // - SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY); - _gpuApertureWriteRegUnicast(pGpu, pAperture, addr, val, 16 /* size */); - SLI_LOOP_END; + ioaprtWriteRegUnicast(pAperture->pGpu, pAperture, addr, val, 16 /* size */); } void -_gpuApertureWriteReg032 +ioaprtWriteReg32_IMPL ( - IO_APERTURE *pAperture, + IoAperture *pAperture, NvU32 addr, NvV32 val ) { - GPU_IO_DEVICE *pDevice = (GPU_IO_DEVICE*)pAperture->pDevice; - OBJGPU *pGpu = pDevice->pGpu; + NV_ASSERT(!gpumgrGetBcEnabledStatus(pAperture->pGpu)); - // - // NOTE: The SLI loop below reuses pAperture's values across all iterations - // OBJGPU's apertures are initialized to have the same baseAddress and length - // on all GPU device instances, so reusing the aperture here is fine. - // Device-specific instances are obtained via gpuGetDeviceMapping in the SLI loop. - // - SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY); - _gpuApertureWriteRegUnicast(pGpu, pAperture, addr, val, 32 /* size */); - SLI_LOOP_END; + ioaprtWriteRegUnicast(pAperture->pGpu, pAperture, addr, val, 32 /* size */); } void -_gpuApertureWriteReg032Unicast +ioaprtWriteReg32Uc_IMPL ( - IO_APERTURE *pAperture, + IoAperture *pAperture, NvU32 addr, NvV32 val ) { - GPU_IO_DEVICE *pDevice = (GPU_IO_DEVICE*)pAperture->pDevice; - OBJGPU *pGpu = pDevice->pGpu; - - _gpuApertureWriteRegUnicast(pGpu, pAperture, addr, val, 32 /* size */); + ioaprtWriteRegUnicast(pAperture->pGpu, pAperture, addr, val, 32 /* size */); } void @@ -462,114 +468,108 @@ regWrite032Unicast } static NvU32 -_gpuApertureReadReg +ioaprtReadReg ( - IO_APERTURE *pAperture, + IoAperture *pAperture, NvU32 addr, NvU32 size ) { - NV_ASSERT_OR_RETURN(pAperture, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(pAperture->pDevice, NV_ERR_INVALID_ARGUMENT); - NvU32 flags = 0; NvU32 returnValue = 0; - GPU_IO_DEVICE *pDevice = (GPU_IO_DEVICE*) pAperture->pDevice; - OBJGPU *pGpu = pDevice->pGpu; + OBJGPU *pGpu = pAperture->pGpu; NV_STATUS status = NV_OK; NvU32 regAddr = pAperture->baseAddress + addr; - NvU32 deviceIndex = pDevice->deviceIndex; - NvU32 instance = pDevice->instance; + NvU32 mappingRegAddr = regAddr - pAperture->mappingStartAddr; + NvU32 deviceIndex = pAperture->deviceIndex; + NvU32 instance = pAperture->deviceInstance; + DEVICE_MAPPING *pMapping = pAperture->pMapping; THREAD_STATE_NODE *pThreadState; pGpu->registerAccess.regReadCount++; - DEVICE_MAPPING *pMapping = gpuGetDeviceMapping(pGpu, deviceIndex, instance); - if (!pMapping) + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY)) { - NV_PRINTF(LEVEL_ERROR, - "Could not find mapping for reg %x, deviceIndex=0x%x instance=%d\n", - regAddr, deviceIndex, instance); - NV_ASSERT(0); - return 0xd0d0d0d0U; + status = gpuSanityCheckRegisterAccess(pGpu, regAddr, NULL); + if (status != NV_OK) + { + return (~0); + } + + threadStateGetCurrentUnchecked(&pThreadState, pGpu); + + returnValue = _gpuHandleReadRegisterFilter(pGpu, deviceIndex, instance, + regAddr, size, &flags, pThreadState); } - status = gpuSanityCheckRegisterAccess(pGpu, regAddr, NULL); - if (status != NV_OK) - { - return (~0); - } - - threadStateGetCurrentUnchecked(&pThreadState, pGpu); - - returnValue = _gpuHandleReadRegisterFilter(pGpu, deviceIndex, instance, - regAddr, size, &flags, pThreadState); - if (!(flags & REGISTER_FILTER_FLAGS_READ)) { switch (size) { case 8: - returnValue = osDevReadReg008(pGpu, pMapping, regAddr); + returnValue = osDevReadReg008(pGpu, pMapping, mappingRegAddr); break; case 16: - returnValue = osDevReadReg016(pGpu, pMapping, regAddr); + returnValue = osDevReadReg016(pGpu, pMapping, mappingRegAddr); break; case 32: - returnValue = osDevReadReg032(pGpu, pMapping, regAddr); + returnValue = osDevReadReg032(pGpu, pMapping, mappingRegAddr); break; } } - // Make sure the value read is sane before we party on it. - gpuSanityCheckRegRead(pGpu, regAddr, size, &returnValue); + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY)) + { + // Make sure the value read is sane before we party on it. + gpuSanityCheckRegRead(pGpu, regAddr, size, &returnValue); + } return returnValue; } NvU8 -_gpuApertureReadReg008 +ioaprtReadReg08_IMPL ( - IO_APERTURE *pAperture, + IoAperture *pAperture, NvU32 addr ) { - return (NvU8) _gpuApertureReadReg(pAperture, addr, 8 /* size */); + return (NvU8) ioaprtReadReg(pAperture, addr, 8 /* size */); } -static NvU16 -_gpuApertureReadReg016 +NvU16 +ioaprtReadReg16_IMPL ( - IO_APERTURE *pAperture, + IoAperture *pAperture, NvU32 addr ) { - return (NvU16) _gpuApertureReadReg(pAperture, addr, 16 /* size */); + return (NvU16) ioaprtReadReg(pAperture, addr, 16 /* size */); } -static NvU32 -_gpuApertureReadReg032 +NvU32 +ioaprtReadReg32_IMPL ( - IO_APERTURE *pAperture, + IoAperture *pAperture, NvU32 addr ) { - return _gpuApertureReadReg(pAperture, addr, 32 /* size */); + return ioaprtReadReg(pAperture, addr, 32 /* size */); } /*! * Checks if the register address is valid for a particular aperture * - * @param[in] pAperture IO_APERTURE pointer + * @param[in] pAperture IoAperture pointer * @param[in] addr register address * * @returns NV_TRUE Register offset is valid */ -static NvBool -_gpuApertureValidReg +NvBool +ioaprtIsRegValid_IMPL ( - IO_APERTURE *pAperture, + IoAperture *pAperture, NvU32 addr ) { @@ -748,57 +748,24 @@ regRead032 * @return NV_OK if IO Aperture is successfully initialized, error otherwise. */ static NV_STATUS -_gpuInitIODeviceAndAperture +_gpuInitIOAperture ( - OBJGPU *pGpu, - NvU32 deviceIndex, - NvU32 gpuDeviceEnum, - RmPhysAddr gpuNvPAddr, - NvU32 gpuNvLength + OBJGPU *pGpu, + NvU32 deviceIndex, + DEVICE_MAPPING *pMapping ) { NV_STATUS rmStatus; - GPU_IO_DEVICE *pIODevice = NULL; - // Initialize GPU IO Device - rmStatus = _allocGpuIODevice(&pIODevice); + rmStatus = objCreate(&pGpu->pIOApertures[deviceIndex], NVOC_NULL_OBJECT, IoAperture, + NULL, // no parent aperture + pGpu, + deviceIndex, + 0, // GPU register operations are always on instance 0 + pMapping, 0, // mapping, mappingStartAddr + 0, pMapping->gpuNvLength); // offset, length if (rmStatus != NV_OK) { - NV_PRINTF(LEVEL_ERROR, - "Failed to initialize pGpu IO device for devIdx %d.\n", - deviceIndex); - - return rmStatus; - } - - pIODevice->pGpu = pGpu; - pIODevice->deviceIndex = deviceIndex; - pIODevice->gpuDeviceEnum = gpuDeviceEnum; - pIODevice->gpuNvPAddr = gpuNvPAddr; - pIODevice->gpuNvLength = gpuNvLength; - pIODevice->refCount = 0; - - // GPU register operations are always on instance 0 - pIODevice->instance = 0; - - // Initialize register functions in IO_DEVICE - pIODevice->parent.pReadReg008Fn = (ReadReg008Fn*) &_gpuApertureReadReg008; - pIODevice->parent.pReadReg016Fn = (ReadReg016Fn*) &_gpuApertureReadReg016; - pIODevice->parent.pReadReg032Fn = (ReadReg032Fn*) &_gpuApertureReadReg032; - pIODevice->parent.pWriteReg008Fn = (WriteReg008Fn*) &_gpuApertureWriteReg008; - pIODevice->parent.pWriteReg016Fn = (WriteReg016Fn*) &_gpuApertureWriteReg016; - pIODevice->parent.pWriteReg032Fn = (WriteReg032Fn*) &_gpuApertureWriteReg032; - pIODevice->parent.pWriteReg032UcFn = (WriteReg032Fn*) &_gpuApertureWriteReg032Unicast; - pIODevice->parent.pValidRegFn = (ValidRegFn*) &_gpuApertureValidReg; - - rmStatus = ioaccessCreateIOAperture(&pGpu->pIOApertures[deviceIndex], - NULL, // no parent aperture - (IO_DEVICE*) pIODevice, - 0, gpuNvLength); // offset, length - if (rmStatus != NV_OK) - { - portMemFree(pIODevice); - NV_PRINTF(LEVEL_ERROR, "Failed to initialize pGpu IO aperture for devIdx %d.\n", deviceIndex); @@ -1777,3 +1744,148 @@ gpuSanityCheckRegRead_IMPL return NV_OK; } + + +NV_STATUS swbcaprtConstruct_IMPL +( + SwBcAperture *pAperture, + IoAperture *pApertures, + NvU32 numApertures +) +{ + NV_ASSERT_OR_RETURN(numApertures != 0, NV_ERR_INVALID_ARGUMENT); + + pAperture->pApertures = pApertures; + pAperture->numApertures = numApertures; + + return NV_OK; +} + +NvU8 +swbcaprtReadReg08_IMPL +( + SwBcAperture *pAperture, + NvU32 addr +) +{ + NvU8 val = REG_RD08(&pAperture->pApertures[0], addr); + +#if defined(DEBUG) + NvU32 i; + for (i = 1; i < pAperture->numApertures; i++) + NV_ASSERT(REG_RD08(&pAperture->pApertures[i], addr) == val); +#endif // defined(DEBUG) + + return val; +} + +NvU16 +swbcaprtReadReg16_IMPL +( + SwBcAperture *pAperture, + NvU32 addr +) +{ + NvU16 val = REG_RD16(&pAperture->pApertures[0], addr); + +#if defined(DEBUG) + NvU32 i; + for (i = 1; i < pAperture->numApertures; i++) + NV_ASSERT(REG_RD16(&pAperture->pApertures[i], addr) == val); +#endif // defined(DEBUG) + + return val; +} + +NvU32 +swbcaprtReadReg32_IMPL +( + SwBcAperture *pAperture, + NvU32 addr +) +{ + NvU32 val = REG_RD32(&pAperture->pApertures[0], addr); + +#if defined(DEBUG) + NvU32 i; + for (i = 1; i < pAperture->numApertures; i++) + NV_ASSERT(REG_RD32(&pAperture->pApertures[i], addr) == val); +#endif // defined(DEBUG) + + return val; +} + +void +swbcaprtWriteReg08_IMPL +( + SwBcAperture *pAperture, + NvU32 addr, + NvV8 value +) +{ + NvU32 i; + + for (i = 0; i < pAperture->numApertures; i++) + REG_WR08(&pAperture->pApertures[i], addr, value); +} + +void +swbcaprtWriteReg16_IMPL +( + SwBcAperture *pAperture, + NvU32 addr, + NvV16 value +) +{ + NvU32 i; + + for (i = 0; i < pAperture->numApertures; i++) + REG_WR16(&pAperture->pApertures[i], addr, value); +} + +void +swbcaprtWriteReg32_IMPL +( + SwBcAperture *pAperture, + NvU32 addr, + NvV32 value +) +{ + NvU32 i; + + for (i = 0; i < pAperture->numApertures; i++) + REG_WR32(&pAperture->pApertures[i], addr, value); +} + +void +swbcaprtWriteReg32Uc_IMPL +( + SwBcAperture *pAperture, + NvU32 addr, + NvV32 value +) +{ + NvU32 i; + + for (i = 0; i < pAperture->numApertures; i++) + REG_WR32_UC(&pAperture->pApertures[i], addr, value); +} + +NvBool +swbcaprtIsRegValid_IMPL +( + SwBcAperture *pAperture, + NvU32 addr +) +{ + + NvU32 i; + + for (i = 0; i < pAperture->numApertures; i++) + { + if (!REG_VALID(&pAperture->pApertures[i], addr)) + return NV_FALSE; + } + + return NV_TRUE; +} diff --git a/src/nvidia/src/kernel/gpu/gpu_fabric_probe.c b/src/nvidia/src/kernel/gpu/gpu_fabric_probe.c index 3a48a16ba..ef8c76b25 100644 --- a/src/nvidia/src/kernel/gpu/gpu_fabric_probe.c +++ b/src/nvidia/src/kernel/gpu/gpu_fabric_probe.c @@ -546,17 +546,24 @@ _gpuFabricProbeSetupFlaRange void _gpuFabricProbeReceive ( - OBJGPU *pGpu, + NvU32 gpuInstance, NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pInbandRcvParams ) { + OBJGPU *pGpu; + NvU32 gpuMaskUnused; nvlink_inband_gpu_probe_rsp_msg_t *pProbeRespMsg; GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo; nvlink_inband_gpu_probe_req_msg_t *pProbeReqMsg = NULL; NvU8 *pRsvd = NULL; - OBJSYS *pSys = SYS_GET_INSTANCE(); - NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); + if ((pGpu = gpumgrGetGpu(gpuInstance)) == NULL) + { + NV_ASSERT_FAILED("Invalid GPU instance"); + return; + } + + NV_ASSERT(rmGpuGroupLockIsOwner(gpuInstance, GPU_LOCK_GRP_SUBDEVICE, &gpuMaskUnused)); NV_ASSERT(pInbandRcvParams != NULL); @@ -570,7 +577,7 @@ _gpuFabricProbeReceive { NV_PRINTF(LEVEL_INFO, "GPU%u Probe resp invalid reqId %lld respId %lld\n", - gpuGetInstance(pGpu), + gpuInstance, pProbeReqMsg->msgHdr.requestId, pProbeRespMsg->msgHdr.requestId); return; @@ -596,15 +603,6 @@ _gpuFabricProbeReceive _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo) == NV_OK); _gpuFabricProbeSetupGpaRange(pGpu, pGpuFabricProbeInfo); _gpuFabricProbeSetupFlaRange(pGpu, pGpuFabricProbeInfo); - - // if MC FLA is disabled, reset the fmCaps - if (!pSys->bMulticastFlaEnabled) - { - pGpuFabricProbeInfo->probeResponseMsg.probeRsp.fmCaps &= - ~NVLINK_INBAND_FM_CAPS_MC_TEAM_SETUP_V1; - pGpuFabricProbeInfo->probeResponseMsg.probeRsp.fmCaps &= - ~NVLINK_INBAND_FM_CAPS_MC_TEAM_RELEASE_V1; - } } void diff --git a/src/nvidia/src/kernel/gpu/gpu_gspclient.c b/src/nvidia/src/kernel/gpu/gpu_gspclient.c index bad647402..75b8f7aed 100644 --- a/src/nvidia/src/kernel/gpu/gpu_gspclient.c +++ b/src/nvidia/src/kernel/gpu/gpu_gspclient.c @@ -208,6 +208,8 @@ void gpuInitProperties_FWCLIENT(OBJGPU *pGpu) { GspStaticConfigInfo *pGSCI = GPU_GET_GSP_STATIC_INFO(pGpu); pGpu->setProperty(pGpu, PDB_PROP_GPU_IS_MOBILE, pGSCI->bIsMobile); + pGpu->setProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_SUPPORTED, pGSCI->bIsGc6Rtd3Allowed); + pGpu->setProperty(pGpu, PDB_PROP_GPU_RTD3_GCOFF_SUPPORTED, pGSCI->bIsGcOffRtd3Allowed); } /*! @@ -254,28 +256,37 @@ gpuConstructDeviceInfoTable_FWCLIENT RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS *pParams; - const NvU32 cmd = NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE; if (pGpu->pDeviceInfoTable) // already initialized return NV_OK; - pParams = portMemAllocNonPaged(sizeof(*pParams)); + pParams = portMemAllocNonPaged(sizeof *pParams); NV_ASSERT_OR_RETURN(pParams != NULL, NV_ERR_NO_MEMORY); - status = pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, - cmd, pParams, sizeof(*pParams)); + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE, + pParams, + sizeof *pParams); if (status != NV_OK) goto done; if (pParams->numEntries == 0) goto done; - pGpu->pDeviceInfoTable = portMemAllocNonPaged(pParams->numEntries * sizeof(DEVICE_INFO2_TABLE)); - NV_ASSERT_TRUE_OR_GOTO(status, pGpu->pDeviceInfoTable != NULL, NV_ERR_NO_MEMORY, done); + pGpu->pDeviceInfoTable = portMemAllocNonPaged( + pParams->numEntries * (sizeof *pGpu->pDeviceInfoTable)); + NV_ASSERT_TRUE_OR_GOTO(status, + pGpu->pDeviceInfoTable != NULL, + NV_ERR_NO_MEMORY, + done); pGpu->numDeviceInfoEntries = pParams->numEntries; - portMemCopy(pGpu->pDeviceInfoTable, pGpu->numDeviceInfoEntries * sizeof(DEVICE_INFO2_TABLE), - pParams->deviceInfoTable, pParams->numEntries * sizeof(DEVICE_INFO2_TABLE)); + portMemCopy(pGpu->pDeviceInfoTable, + pGpu->numDeviceInfoEntries * (sizeof *pGpu->pDeviceInfoTable), + pParams->deviceInfoTable, + pParams->numEntries * (sizeof pParams->deviceInfoTable[0])); done: portMemFree(pParams); diff --git a/src/nvidia/src/kernel/gpu/gpu_registry.c b/src/nvidia/src/kernel/gpu/gpu_registry.c index 765f1b572..ea1b6c389 100644 --- a/src/nvidia/src/kernel/gpu/gpu_registry.c +++ b/src/nvidia/src/kernel/gpu/gpu_registry.c @@ -101,6 +101,19 @@ gpuInitRegistryOverrides_KERNEL } } + if (osReadRegistryDword(pGpu, + NV_REG_STR_RM_ALLOC_CTX_BUFFERS_FROM_PMA, &data32) == NV_OK) + { + if (data32 == NV_REG_STR_RM_ALLOC_CTX_BUFFERS_FROM_PMA_ENABLE) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_MOVE_CTX_BUFFERS_TO_PMA, NV_TRUE); + } + else + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_MOVE_CTX_BUFFERS_TO_PMA, NV_FALSE); + } + } + if (pGpu->bSriovCapable) { if (osReadRegistryDword(pGpu, NV_REG_STR_RM_SET_SRIOV_MODE, &data32) == NV_OK) diff --git a/src/nvidia/src/kernel/gpu/gpu_rmapi.c b/src/nvidia/src/kernel/gpu/gpu_rmapi.c index 50083ca3a..ee6a51853 100644 --- a/src/nvidia/src/kernel/gpu/gpu_rmapi.c +++ b/src/nvidia/src/kernel/gpu/gpu_rmapi.c @@ -504,6 +504,9 @@ gpuNotifySubDeviceEvent_IMPL Subdevice *pSubdevice = pGpu->pSubdeviceBackReferences[i]; NV_ASSERT_OR_RETURN_VOID(pSubdevice != NULL); INotifier *pNotifier = staticCast(pSubdevice, INotifier); + + if (inotifyGetNotificationShare(pNotifier) == NULL) + continue; GPU_RES_SET_THREAD_BC_STATE(pSubdevice); diff --git a/src/nvidia/src/kernel/gpu/gpu_suspend.c b/src/nvidia/src/kernel/gpu/gpu_suspend.c index 7c8078cb4..9ef134eb7 100644 --- a/src/nvidia/src/kernel/gpu/gpu_suspend.c +++ b/src/nvidia/src/kernel/gpu/gpu_suspend.c @@ -73,12 +73,40 @@ gpuPowerManagementEnter(OBJGPU *pGpu, NvU32 newLevel, NvU32 flags) { NV_ASSERT_OK_OR_GOTO(status, memmgrSavePowerMgmtState(pGpu, pMemoryManager), done); + KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); + + NV_RM_RPC_UNLOADING_GUEST_DRIVER(pGpu, status, NV_TRUE, IS_GPU_GC6_STATE_ENTERING(pGpu), newLevel); if (status != NV_OK) goto done; + // Wait for GSP-RM to suspend + kgspWaitForProcessorSuspend_HAL(pGpu, pKernelGsp); + + // Dump GSP-RM logs before resetting and invoking FWSEC-SB + kgspDumpGspLogs(pGpu, pKernelGsp, NV_FALSE); + + // Because of COT, RM cannot reset GSP-RISCV. + if (!(pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_COT_ENABLED))) + { + kflcnReset_HAL(pGpu, staticCast(pKernelGsp, KernelFalcon)); + } + + // Invoke FWSEC-SB to load back PreOsApps. + if (kgspExecuteFwsecSb_HAL(pGpu, pKernelGsp, pKernelGsp->pFwsecUcode) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed to execute FWSEC-SB for PreOsApps\n"); + } + kpmuFreeLibosLoggingStructures(pGpu, GPU_GET_KERNEL_PMU(pGpu)); + { + // Not called when kgspShouldBootWithBooter_HAL() is called and returns NV_FALSE + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kgspSavePowerMgmtState_HAL(pGpu, pKernelGsp), done); + + } + } done: @@ -135,13 +163,6 @@ gpuPowerManagementResume(OBJGPU *pGpu, NvU32 oldLevel, NvU32 flags) KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); - status = kpmuInitLibosLoggingStructures(pGpu, GPU_GET_KERNEL_PMU(pGpu)); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "cannot init libOS PMU logging structures: 0x%x\n", status); - goto done; - } - GSP_SR_INIT_ARGUMENTS gspSrInitArgs; gspSrInitArgs.oldLevel = oldLevel; @@ -150,18 +171,23 @@ gpuPowerManagementResume(OBJGPU *pGpu, NvU32 oldLevel, NvU32 flags) kgspPopulateGspRmInitArgs(pGpu, pKernelGsp, &gspSrInitArgs); - // - // GSP-TODO - Remove following line after the following is implemented - // JIRA CORERM-4274 - Open RM - Suspend & Resume - GSP Heap and FW save/restore - // - // Reset timeout due to long memmgrRestorePowerMgmtState() through BAR0 Window - // - threadStateResetTimeout(pGpu); - - status = kgspExecuteSequencerCommand_HAL(pGpu, pKernelGsp, GSP_SEQ_BUF_OPCODE_CORE_RESUME, NULL, 0); + // Wait for GFW_BOOT status + status = kgspWaitForGfwBootOk_HAL(pGpu, pKernelGsp); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "cannot resume riscv/gsp: 0x%x\n", status); + goto done; + } + + // Not called when kgspShouldBootWithBooter_HAL() is called and returns NV_FALSE + { + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kgspRestorePowerMgmtState_HAL(pGpu, pKernelGsp), done); + } + + status = kpmuInitLibosLoggingStructures(pGpu, GPU_GET_KERNEL_PMU(pGpu)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "cannot init libOS PMU logging structures: 0x%x\n", status); goto done; } @@ -198,7 +224,7 @@ NV_STATUS gpuEnterStandby_IMPL(OBJGPU *pGpu) { OBJSYS *pSys = SYS_GET_INSTANCE(); - POBJPFM pPfm = SYS_GET_PFM(pSys); + OBJPFM *pPfm = SYS_GET_PFM(pSys); NV_STATUS suspendStatus; if ((pPfm != NULL) && pPfm->getProperty(pPfm, PDB_PROP_PFM_SUPPORTS_ACPI)) @@ -241,7 +267,7 @@ NV_STATUS gpuResumeFromStandby_IMPL(OBJGPU *pGpu) { OBJSYS *pSys = SYS_GET_INSTANCE(); - POBJPFM pPfm = SYS_GET_PFM(pSys); + OBJPFM *pPfm = SYS_GET_PFM(pSys); NV_STATUS resumeStatus; NvU32 state = 0; @@ -288,7 +314,7 @@ gpuResumeFromStandby_IMPL(OBJGPU *pGpu) NV_STATUS gpuEnterHibernate_IMPL(OBJGPU *pGpu) { OBJSYS *pSys = SYS_GET_INSTANCE(); - POBJPFM pPfm = SYS_GET_PFM(pSys); + OBJPFM *pPfm = SYS_GET_PFM(pSys); NV_STATUS suspendStatus; if ((pPfm != NULL) && pPfm->getProperty(pPfm, PDB_PROP_PFM_SUPPORTS_ACPI)) @@ -321,7 +347,7 @@ NV_STATUS gpuEnterHibernate_IMPL(OBJGPU *pGpu) NV_STATUS gpuResumeFromHibernate_IMPL(OBJGPU *pGpu) { OBJSYS *pSys = SYS_GET_INSTANCE(); - POBJPFM pPfm = SYS_GET_PFM(pSys); + OBJPFM *pPfm = SYS_GET_PFM(pSys); NV_STATUS resumeStatus; NV_PRINTF(LEVEL_INFO, diff --git a/src/nvidia/src/kernel/gpu/gpu_timeout.c b/src/nvidia/src/kernel/gpu/gpu_timeout.c index ba9873dae..8fbb5e08b 100644 --- a/src/nvidia/src/kernel/gpu/gpu_timeout.c +++ b/src/nvidia/src/kernel/gpu/gpu_timeout.c @@ -314,8 +314,11 @@ _checkTimeout osGetCurrentTick(&timeInNs); if (timeInNs >= pTimeout->timeout) { - NV_PRINTF(LEVEL_INFO, "OS elapsed %llx >= %llx\n", - timeInNs, pTimeout->timeout); + if (!(pTimeout->flags & GPU_TIMEOUT_FLAGS_BYPASS_JOURNAL_LOG)) + { + NV_PRINTF(LEVEL_INFO, "OS elapsed %llx >= %llx\n", + timeInNs, pTimeout->timeout); + } status = NV_ERR_TIMEOUT; } } @@ -345,7 +348,10 @@ _checkTimeout if (pTimeout->timeout == 0) { - NV_PRINTF(LEVEL_INFO, "OS timeout == 0\n"); + if (!(pTimeout->flags & GPU_TIMEOUT_FLAGS_BYPASS_JOURNAL_LOG)) + { + NV_PRINTF(LEVEL_INFO, "OS timeout == 0\n"); + } status = NV_ERR_TIMEOUT; } } diff --git a/src/nvidia/src/kernel/gpu/gpu_user_shared_data.c b/src/nvidia/src/kernel/gpu/gpu_user_shared_data.c index 29161c337..e378ab2cf 100644 --- a/src/nvidia/src/kernel/gpu/gpu_user_shared_data.c +++ b/src/nvidia/src/kernel/gpu/gpu_user_shared_data.c @@ -62,7 +62,7 @@ gpushareddataConstruct_IMPL } status = memdescMap(pMemDesc, 0, pMemDesc->Size, - NV_TRUE, NV_PROTECT_READABLE, + NV_TRUE, NV_PROTECT_READ_WRITE, &pGpu->userSharedData.pMapBuffer, &pGpu->userSharedData.pMapBufferPriv); if (status != NV_OK) @@ -79,7 +79,7 @@ gpushareddataConstruct_IMPL portMemSet(pSharedData, 0, sizeof(*pSharedData)); // Initial write from cached data - gpushareddataWriteFinish(pGpu); + gpuUpdateUserSharedData_KERNEL(pGpu); } memdescAddRef(pGpu->userSharedData.pMemDesc); @@ -135,9 +135,9 @@ gpushareddataMap_IMPL if (status != NV_OK) return status; - // Only support read-only, fail early if writeable - if (pCpuMapping->pPrivate->protect & NV_PROTECT_WRITEABLE) - return NV_ERR_INVALID_PARAMETER; + // Only support read-only, fail early if flag is unset somehow + if (!(pGpu->userSharedData.pMemDesc->_flags & MEMDESC_FLAGS_USER_READ_ONLY)) + return NV_ERR_INVALID_STATE; pCpuMapping->processId = osGetCurrentProcess(); @@ -146,7 +146,7 @@ gpushareddataMap_IMPL 0, pGpu->userSharedData.pMemDesc->Size, NV_FALSE, - pCpuMapping->pPrivate->protect, + NV_PROTECT_READABLE, &pCpuMapping->pLinearAddress, &pCpuMapping->pPrivate->pPriv); @@ -227,6 +227,11 @@ NV00DE_SHARED_DATA * gpushareddataWriteStart(OBJGPU *pGpu) } void gpushareddataWriteFinish(OBJGPU *pGpu) +{ + gpuUpdateUserSharedData_HAL(pGpu); +} + +void gpuUpdateUserSharedData_KERNEL(OBJGPU *pGpu) { NV00DE_SHARED_DATA *pSharedData = (NV00DE_SHARED_DATA*)(pGpu->userSharedData.pMapBuffer); const NvU32 data_offset = sizeof(pSharedData->seq); diff --git a/src/nvidia/src/kernel/gpu/gr/arch/maxwell/kgraphics_gm200.c b/src/nvidia/src/kernel/gpu/gr/arch/maxwell/kgraphics_gm200.c index cd29b7773..b27f64435 100644 --- a/src/nvidia/src/kernel/gpu/gr/arch/maxwell/kgraphics_gm200.c +++ b/src/nvidia/src/kernel/gpu/gr/arch/maxwell/kgraphics_gm200.c @@ -165,6 +165,11 @@ kgraphicsAllocGrGlobalCtxBuffers_GM200 cbAllocFlags | MEMDESC_FLAGS_GPU_PRIVILEGED | MEMDESC_FLAGS_HIGH_PRIORITY)); memdescSetGpuCacheAttrib(*ppMemDesc, NV_MEMORY_CACHED); + if ((cbAllocFlags & MEMDESC_FLAGS_OWNED_BY_CTX_BUF_POOL) != 0) + { + memmgrSetMemDescPageSize_HAL(pGpu, pMemoryManager, *ppMemDesc, AT_GPU, RM_ATTR_PAGE_SIZE_4KB); + NV_ASSERT_OK_OR_RETURN(memdescSetCtxBufPool(*ppMemDesc, pCtxBufPool)); + } NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, memdescAllocList(*ppMemDesc, pCtxAttr[GR_GLOBALCTX_BUFFER_BUNDLE_CB].pAllocList)); } @@ -185,6 +190,11 @@ kgraphicsAllocGrGlobalCtxBuffers_GM200 cbAllocFlags | MEMDESC_FLAGS_GPU_PRIVILEGED)); memdescSetGpuCacheAttrib(*ppMemDesc, NV_MEMORY_CACHED); + if ((cbAllocFlags & MEMDESC_FLAGS_OWNED_BY_CTX_BUF_POOL) != 0) + { + memmgrSetMemDescPageSize_HAL(pGpu, pMemoryManager, *ppMemDesc, AT_GPU, RM_ATTR_PAGE_SIZE_4KB); + NV_ASSERT_OK_OR_RETURN(memdescSetCtxBufPool(*ppMemDesc, pCtxBufPool)); + } NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, memdescAllocList(*ppMemDesc, pCtxAttr[GR_GLOBALCTX_BUFFER_PAGEPOOL].pAllocList)); } @@ -205,6 +215,11 @@ kgraphicsAllocGrGlobalCtxBuffers_GM200 cbAllocFlags | MEMDESC_FLAGS_HIGH_PRIORITY)); memdescSetGpuCacheAttrib(*ppMemDesc, NV_MEMORY_CACHED); + if ((cbAllocFlags & MEMDESC_FLAGS_OWNED_BY_CTX_BUF_POOL) != 0) + { + memmgrSetMemDescPageSize_HAL(pGpu, pMemoryManager, *ppMemDesc, AT_GPU, RM_ATTR_PAGE_SIZE_4KB); + NV_ASSERT_OK_OR_RETURN(memdescSetCtxBufPool(*ppMemDesc, pCtxBufPool)); + } NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, memdescAllocList(*ppMemDesc, pCtxAttr[GR_GLOBALCTX_BUFFER_ATTRIBUTE_CB].pAllocList)); memdescSetName(pGpu, *ppMemDesc, NV_RM_SURF_NAME_GR_CIRCULAR_BUFFER, NULL); @@ -231,12 +246,15 @@ kgraphicsAllocGrGlobalCtxBuffers_GM200 pCtxAttr[GR_GLOBALCTX_BUFFER_PRIV_ACCESS_MAP].cpuAttr, flags)); - // - // Force page size to 4KB, we can change this later when RM - // access method support 64k pages - // - memmgrSetMemDescPageSize_HAL(pGpu, pMemoryManager, *ppMemDesc, AT_GPU, RM_ATTR_PAGE_SIZE_4KB); - NV_ASSERT_OK_OR_RETURN(memdescSetCtxBufPool(*ppMemDesc, pCtxBufPool)); + if ((flags & MEMDESC_FLAGS_OWNED_BY_CTX_BUF_POOL) != 0) + { + // + // Force page size to 4KB, we can change this later when RM + // access method support 64k pages + // + memmgrSetMemDescPageSize_HAL(pGpu, pMemoryManager, *ppMemDesc, AT_GPU, RM_ATTR_PAGE_SIZE_4KB); + NV_ASSERT_OK_OR_RETURN(memdescSetCtxBufPool(*ppMemDesc, pCtxBufPool)); + } NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, memdescAllocList(*ppMemDesc, pCtxAttr[GR_GLOBALCTX_BUFFER_PRIV_ACCESS_MAP].pAllocList)); } @@ -259,12 +277,15 @@ kgraphicsAllocGrGlobalCtxBuffers_GM200 pCtxAttr[GR_GLOBALCTX_BUFFER_UNRESTRICTED_PRIV_ACCESS_MAP].cpuAttr, flags)); - // - // Force page size to 4KB, we can change this later when RM - // access method support 64k pages - // - memmgrSetMemDescPageSize_HAL(pGpu, pMemoryManager, *ppMemDesc, AT_GPU, RM_ATTR_PAGE_SIZE_4KB); - NV_ASSERT_OK_OR_RETURN(memdescSetCtxBufPool(*ppMemDesc, pCtxBufPool)); + if ((flags & MEMDESC_FLAGS_OWNED_BY_CTX_BUF_POOL) != 0) + { + // + // Force page size to 4KB, we can change this later when RM + // access method support 64k pages + // + memmgrSetMemDescPageSize_HAL(pGpu, pMemoryManager, *ppMemDesc, AT_GPU, RM_ATTR_PAGE_SIZE_4KB); + NV_ASSERT_OK_OR_RETURN(memdescSetCtxBufPool(*ppMemDesc, pCtxBufPool)); + } NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, memdescAllocList(*ppMemDesc, diff --git a/src/nvidia/src/kernel/gpu/gr/arch/pascal/kgraphics_gp100.c b/src/nvidia/src/kernel/gpu/gr/arch/pascal/kgraphics_gp100.c index 7655876b4..582bea80f 100644 --- a/src/nvidia/src/kernel/gpu/gr/arch/pascal/kgraphics_gp100.c +++ b/src/nvidia/src/kernel/gpu/gr/arch/pascal/kgraphics_gp100.c @@ -22,6 +22,7 @@ */ #include "kernel/gpu/gr/kernel_graphics.h" +#include "kernel/gpu/mem_mgr/mem_mgr.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "kernel/gpu/intr/engine_idx.h" #include "nvRmReg.h" @@ -218,7 +219,13 @@ kgraphicsAllocGlobalCtxBuffers_GP100 if ((*ppMemDesc)->_addressSpace == ADDR_FBMEM) memdescSetGpuCacheAttrib(*ppMemDesc, NV_MEMORY_CACHED); - NV_ASSERT_OK_OR_RETURN(memdescSetCtxBufPool(*ppMemDesc, pCtxBufPool)); + if ((allocFlags & MEMDESC_FLAGS_OWNED_BY_CTX_BUF_POOL) != 0) + { + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + memmgrSetMemDescPageSize_HAL(pGpu, pMemoryManager, *ppMemDesc, AT_GPU, RM_ATTR_PAGE_SIZE_4KB); + NV_ASSERT_OK_OR_RETURN(memdescSetCtxBufPool(*ppMemDesc, pCtxBufPool)); + } NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, memdescAllocList(*ppMemDesc, pCtxAttr[GR_GLOBALCTX_BUFFER_FECS_EVENT].pAllocList)); diff --git a/src/nvidia/src/kernel/gpu/gr/arch/turing/kgraphics_tu102.c b/src/nvidia/src/kernel/gpu/gr/arch/turing/kgraphics_tu102.c index f64d9ee72..b4b305963 100644 --- a/src/nvidia/src/kernel/gpu/gr/arch/turing/kgraphics_tu102.c +++ b/src/nvidia/src/kernel/gpu/gr/arch/turing/kgraphics_tu102.c @@ -22,6 +22,7 @@ */ #include "kernel/gpu/gr/kernel_graphics.h" +#include "kernel/gpu/mem_mgr/mem_mgr.h" #include "ctrl/ctrl0080/ctrl0080fifo.h" @@ -52,6 +53,7 @@ kgraphicsAllocGrGlobalCtxBuffers_TU102 NvU32 rtvcbBufferAlign; NV_STATUS status; const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; + CTX_BUF_POOL_INFO *pCtxBufPool = NULL; NV_ASSERT_OR_RETURN(!gpumgrGetBcEnabledStatus(pGpu), NV_ERR_INVALID_STATE); @@ -97,6 +99,14 @@ kgraphicsAllocGrGlobalCtxBuffers_TU102 { pCtxBuffers = &pKernelGraphics->globalCtxBuffersInfo.pGlobalCtxBuffers[gfid]; pCtxAttr = pKernelGraphics->globalCtxBuffersInfo.globalCtxAttr; + NV_ASSERT_OK_OR_RETURN(ctxBufPoolGetGlobalPool(pGpu, CTX_BUF_ID_GR_GLOBAL, + RM_ENGINE_TYPE_GR(pKernelGraphics->instance), &pCtxBufPool)); + } + + // Don't use context buffer pool for VF allocations managed by host RM. + if (ctxBufPoolIsSupported(pGpu) && (pCtxBufPool != NULL)) + { + allocFlags |= MEMDESC_FLAGS_OWNED_BY_CTX_BUF_POOL; } if (IS_GFID_VF(gfid)) @@ -127,6 +137,13 @@ kgraphicsAllocGrGlobalCtxBuffers_TU102 allocFlags)); memdescSetGpuCacheAttrib(*ppMemDesc, NV_MEMORY_CACHED); + if ((allocFlags & MEMDESC_FLAGS_OWNED_BY_CTX_BUF_POOL) != 0) + { + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + memmgrSetMemDescPageSize_HAL(pGpu, pMemoryManager, *ppMemDesc, AT_GPU, RM_ATTR_PAGE_SIZE_4KB); + NV_ASSERT_OK_OR_RETURN(memdescSetCtxBufPool(*ppMemDesc, pCtxBufPool)); + } NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, memdescAllocList(*ppMemDesc, pCtxAttr[GR_GLOBALCTX_BUFFER_RTV_CB].pAllocList)); } diff --git a/src/nvidia/src/kernel/gpu/gr/fecs_event_list.c b/src/nvidia/src/kernel/gpu/gr/fecs_event_list.c index 336445f49..49b6391a9 100644 --- a/src/nvidia/src/kernel/gpu/gr/fecs_event_list.c +++ b/src/nvidia/src/kernel/gpu/gr/fecs_event_list.c @@ -48,6 +48,9 @@ #include "class/cl90cdtypes.h" #include "ctrl/ctrl90cd.h" +#define NV_FECS_TRACE_MAX_TIMESTAMPS 5 +#define NV_FECS_TRACE_MAGIC_INVALIDATED 0xdededede // magic number for entries that have been read + typedef struct { NvU32 magic_lo; @@ -56,12 +59,11 @@ typedef struct NvU32 context_ptr; NvU32 new_context_id; NvU32 new_context_ptr; - NvU64 ts[]; + NvU64 ts[NV_FECS_TRACE_MAX_TIMESTAMPS]; + NvU32 reserved[13]; + NvU32 seqno; } FECS_EVENT_RECORD; -#define NV_FECS_TRACE_MAX_TIMESTAMPS 5 -#define NV_FECS_TRACE_MAGIC_INVALIDATED 0xdededede // magic number for entries that have been read - /*! Opaque pointer to private data */ typedef struct VGPU_FECS_TRACE_STAGING_BUFFER VGPU_FECS_TRACE_STAGING_BUFFER; @@ -73,6 +75,7 @@ struct KGRAPHICS_FECS_TRACE_INFO NvU16 fecsTraceRdOffset; NvU16 fecsTraceCounter; NvU32 fecsCtxswLogIntrPending; + NvU32 fecsLastSeqno; #if PORT_IS_MODULE_SUPPORTED(crypto) PORT_CRYPTO_PRNG *pFecsLogPrng; @@ -224,6 +227,19 @@ formatAndNotifyFecsRecord pChannelRef = (pKernelChannel != NULL) ? kchannelGetMIGReference(pKernelChannel) : NULL; pNewChannelRef = (pKernelChannelNew != NULL) ? kchannelGetMIGReference(pKernelChannelNew) : NULL; + if (kgraphicsIsFecsRecordUcodeSeqnoSupported(pGpu, pKernelGraphics)) + { + KGRAPHICS_FECS_TRACE_INFO *pFecsTraceInfo = kgraphicsGetFecsTraceInfo(pGpu, pKernelGraphics); + + // Dropped at least 1 event + if ((pFecsTraceInfo->fecsLastSeqno + 1) != pRecord->seqno) + { + notifRecord.dropCount = pRecord->seqno - pFecsTraceInfo->fecsLastSeqno - 1; + } + + pFecsTraceInfo->fecsLastSeqno = pRecord->seqno; + } + for (timestampId = 0; timestampId < NV_FECS_TRACE_MAX_TIMESTAMPS; timestampId++) { NV_ASSERT_OK_OR_ELSE(status, @@ -345,6 +361,8 @@ formatAndNotifyFecsRecord pSubmap = multimapFindSubmap(&pGpu->fecsEventBufferBindingsUid, 0); notifyEventBuffers(pGpu, pSubmap, ¬ifRecord); + // Clear so we don't report drops for every event in this record + notifRecord.dropCount = 0; } } } @@ -1234,6 +1252,8 @@ fecsBufferReset (NvU8)(NV_FECS_TRACE_MAGIC_INVALIDATED & 0xff), memdescGetSize(pFecsMemDesc)); + pFecsTraceInfo->fecsLastSeqno = 0; + // Routing info is the same for all future calls in this series traceWrOffsetParams.grRouteInfo = getHwEnableParams.grRouteInfo; traceRdOffsetParams.grRouteInfo = getHwEnableParams.grRouteInfo; diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c b/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c index 076ea39c9..aba32ab14 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c @@ -1123,6 +1123,27 @@ cleanup: return status; } +/*! Return if GFX is supported for the given kernel graphics engine */ +NvBool +kgraphicsIsGFXSupported_IMPL +( + OBJGPU *pGpu, + KernelGraphics *pKernelGraphics +) +{ + const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); + NvU32 gfxCapabilites; + + NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo != NULL, NV_FALSE); + NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo->pGrInfo != NULL, NV_FALSE); + + gfxCapabilites = pKernelGraphicsStaticInfo->pGrInfo->infoList[NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES].data; + + return (FLD_TEST_DRF(2080_CTRL_GR, _INFO_GFX_CAPABILITIES, _2D, _TRUE, gfxCapabilites) && + FLD_TEST_DRF(2080_CTRL_GR, _INFO_GFX_CAPABILITIES, _3D, _TRUE, gfxCapabilites) && + FLD_TEST_DRF(2080_CTRL_GR, _INFO_GFX_CAPABILITIES, _I2M, _TRUE, gfxCapabilites)); +} + /*! Retrieve ctxbufpool parameters for given local ctx buffer */ const CTX_BUF_INFO * kgraphicsGetCtxBufferInfo_IMPL @@ -1672,6 +1693,8 @@ kgraphicsCreateGoldenImageChannel_IMPL NV_MEMORY_ALLOCATION_PARAMS memAllocParams; NV_CHANNEL_ALLOC_PARAMS channelGPFIFOAllocParams; NvU32 classNum; + MIG_INSTANCE_REF ref; + NvU32 objectType; // XXX This should be removed when braodcast SLI support is deprecated if (!gpumgrIsParentGPU(pGpu)) @@ -1718,11 +1741,9 @@ kgraphicsCreateGoldenImageChannel_IMPL if (bNeedMIGWar) { - KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); NvHandle hPartitionRef = 0xbaba0048; NvHandle hExecPartitionRef = 0xbaba004a; NVC637_ALLOCATION_PARAMETERS nvC637AllocParams = {0}; - MIG_INSTANCE_REF ref; // Get swizzId for this GR NV_ASSERT_OK_OR_GOTO(status, @@ -1875,7 +1896,6 @@ kgraphicsCreateGoldenImageChannel_IMPL if (bNeedMIGWar) { - MIG_INSTANCE_REF ref; RM_ENGINE_TYPE localRmEngineType; NV_ASSERT_OK_OR_GOTO(status, @@ -1941,19 +1961,20 @@ kgraphicsCreateGoldenImageChannel_IMPL bAcquireLock = NV_FALSE; pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - // Get KernelGraphicsObject class Id if (!bNeedMIGWar) { - NV_ASSERT_OK_OR_GOTO(status, - kgraphicsGetClassByType(pGpu, pKernelGraphics, GR_OBJECT_TYPE_3D, &classNum), - cleanup); + objectType = GR_OBJECT_TYPE_3D; } else { - NV_ASSERT_OK_OR_GOTO(status, - kgraphicsGetClassByType(pGpu, pKernelGraphics, GR_OBJECT_TYPE_COMPUTE, &classNum), - cleanup); + objectType = GR_OBJECT_TYPE_COMPUTE; + } + + // Get KernelGraphicsObject class Id + NV_ASSERT_OK_OR_GOTO(status, + kgraphicsGetClassByType(pGpu, pKernelGraphics, objectType, &classNum), + cleanup); NV_ASSERT_OR_GOTO(classNum != 0, cleanup); // Allocate a GR object on the channel @@ -2330,6 +2351,55 @@ deviceCtrlCmdKGrGetInfoV2_IMPL return NV_OK; } +NV_STATUS +kgraphicsDiscoverMaxLocalCtxBufferSize_IMPL +( + OBJGPU *pGpu, + KernelGraphics *pKernelGraphics +) +{ + NvU32 bufId = 0; + const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); + + if (IS_MODS_AMODEL(pGpu)) + return NV_OK; + + NV_ASSERT_OK_OR_RETURN( + kgraphicsInitializeDeferredStaticData(pGpu, pKernelGraphics, NV01_NULL_OBJECT, NV01_NULL_OBJECT)); + + NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo->pContextBuffersInfo != NULL, NV_ERR_INVALID_STATE); + + FOR_EACH_IN_ENUM(GR_CTX_BUFFER, bufId) + { + if (bufId == GR_CTX_BUFFER_MAIN) + { + NvU32 size; + + NV_ASSERT_OK_OR_RETURN(kgraphicsGetMainCtxBufferSize(pGpu, pKernelGraphics, NV_TRUE, &size)); + kgraphicsSetCtxBufferInfo(pGpu, pKernelGraphics, bufId, + size, + RM_PAGE_SIZE, + RM_ATTR_PAGE_SIZE_4KB, + kgraphicsShouldForceMainCtxContiguity_HAL(pGpu, pKernelGraphics)); + } + else + { + NvU32 fifoEngineId; + + NV_ASSERT_OK_OR_RETURN( + kgrctxCtxBufferToFifoEngineId(bufId, &fifoEngineId)); + + kgraphicsSetCtxBufferInfo(pGpu, pKernelGraphics, bufId, + pKernelGraphicsStaticInfo->pContextBuffersInfo->engine[fifoEngineId].size, + RM_PAGE_SIZE, + RM_ATTR_PAGE_SIZE_4KB, + ((bufId == GR_CTX_BUFFER_PATCH) || (bufId == GR_CTX_BUFFER_PM))); + } + } + FOR_EACH_IN_ENUM_END; + return NV_OK; +} + /*! * KernelGraphics RM SubDevice Controls */ diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_graphics_context.c b/src/nvidia/src/kernel/gpu/gr/kernel_graphics_context.c index 510478207..dedbc45ca 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_graphics_context.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_graphics_context.c @@ -547,14 +547,9 @@ NV_STATUS kgrctxGetUnicast_IMPL KernelGraphicsContextUnicast **ppKernelGraphicsContextUnicast ) { - NvU32 subdevInst = gpumgrGetSubDeviceInstanceFromGpu(pGpu); - + *ppKernelGraphicsContextUnicast = NULL; NV_ASSERT_OR_RETURN(pKernelGraphicsContext->pShared != NULL, NV_ERR_INVALID_STATE); - NV_ASSERT_OR_RETURN(pKernelGraphicsContext->pShared->pKernelGraphicsContextUnicast != NULL, - NV_ERR_INVALID_STATE); - - *ppKernelGraphicsContextUnicast = - &pKernelGraphicsContext->pShared->pKernelGraphicsContextUnicast[subdevInst]; + *ppKernelGraphicsContextUnicast = &pKernelGraphicsContext->pShared->kernelGraphicsContextUnicast; return NV_OK; } @@ -670,6 +665,43 @@ kgrctxRecordMmuFault_IMPL } } +/*! + * @brief Determine whether channels in this context are associated with GR engine + * + * @returns NV_TRUE if passed channel is allocated on GR, and is on GR runlist + */ +NvBool +kgrctxIsValid_IMPL +( + OBJGPU *pGpu, + KernelGraphicsContext *pKernelGraphicsContext, + KernelChannel *pKernelChannel +) +{ + NvU32 runlistId; + RM_ENGINE_TYPE engineType; + + // TODO remove pKernelChannel from params + + if (RM_ENGINE_TYPE_IS_VALID(kchannelGetEngineType(pKernelChannel)) && + !RM_ENGINE_TYPE_IS_GR(kchannelGetEngineType(pKernelChannel))) + { + return NV_FALSE; + } + + NV_CHECK_OR_RETURN(LEVEL_INFO, kchannelIsRunlistSet(pGpu, pKernelChannel), NV_FALSE); + + runlistId = kchannelGetRunlistId(pKernelChannel); + NV_ASSERT_OK( + kfifoEngineInfoXlate_HAL(pGpu, GPU_GET_KERNEL_FIFO(pGpu), + ENGINE_INFO_TYPE_RUNLIST, runlistId, + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, (NvU32 *) &engineType)); + + NV_CHECK_OR_RETURN(LEVEL_INFO, RM_ENGINE_TYPE_IS_GR(engineType), NV_FALSE); + + return NV_TRUE; +} + /*! * @brief returns if the main context buffer has been allocated * @@ -2266,7 +2298,7 @@ kgrctxUnmapAssociatedCtxBuffers_IMPL NvBool bRelease3d = NV_FALSE; NvU32 gfid = kchannelGetGfid(pKernelChannel); NvU32 status; - NvU64 refCount; + GR_GLOBALCTX_BUFFER registerMapBufferId = kgrctxGetRegisterAccessMapId_HAL(pGpu, pKernelGraphicsContext, pKernelChannel); NV_ASSERT(!gpumgrGetBcEnabledStatus(pGpu)); @@ -2299,27 +2331,51 @@ kgrctxUnmapAssociatedCtxBuffers_IMPL kgrctxUnmapGlobalCtxBuffers(pGpu, pKernelGraphicsContext, pKernelGraphics, pKernelChannel->pVAS, gfid); } + // + // If multiple channels sharing the same VAS exist, it is possible both + // channels could be using these mappings, and we must wait for both + // channels to be detached before we remove them. + // + { + RS_ORDERED_ITERATOR it; + RsResourceRef *pScopeRef = RES_GET_REF(pKernelChannel); + + // Iterate over all channels in this TSG and check for duplicate VAS + if (!pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup->bAllocatedByRm) + pScopeRef = RES_GET_REF(pKernelChannel->pKernelChannelGroupApi); + + it = kchannelGetIter(RES_GET_CLIENT(pKernelChannel), pScopeRef); + while (clientRefOrderedIterNext(it.pClient, &it)) + { + KernelChannel *pLoopKernelChannel = dynamicCast(it.pResourceRef->pResource, KernelChannel); + NV_ASSERT_OR_RETURN_VOID(pLoopKernelChannel != NULL); + + if (pLoopKernelChannel == pKernelChannel) + continue; + + NV_CHECK_OR_RETURN_VOID(LEVEL_SILENT, pLoopKernelChannel->pVAS != pKernelChannel->pVAS); + } + } + // Only unmap once the last channel using this VAS has gone - if ((kgraphicsGetGlobalCtxBuffers(pGpu, pKernelGraphics, gfid)->memDesc[GR_GLOBALCTX_BUFFER_FECS_EVENT] != NULL) && - (vaListGetRefCount(&pKernelGraphicsContextUnicast->globalCtxBufferVaList[GR_GLOBALCTX_BUFFER_FECS_EVENT], pKernelChannel->pVAS, &refCount) == NV_OK) && - (refCount == 1)) + if (kgraphicsGetGlobalCtxBuffers(pGpu, pKernelGraphics, gfid)->memDesc[GR_GLOBALCTX_BUFFER_FECS_EVENT] != NULL) { kgrctxUnmapGlobalCtxBuffer(pGpu, pKernelGraphicsContext, pKernelGraphics, pKernelChannel->pVAS, GR_GLOBALCTX_BUFFER_FECS_EVENT); } - if ((pKernelGraphicsContextUnicast->pmCtxswBuffer.pMemDesc != NULL) && - (vaListGetRefCount(&pKernelGraphicsContextUnicast->pmCtxswBuffer.vAddrList, pKernelChannel->pVAS, &refCount) == NV_OK) && - (refCount == 1)) + if (pKernelGraphicsContextUnicast->pmCtxswBuffer.pMemDesc != NULL) { kgrctxUnmapCtxPmBuffer(pGpu, pKernelGraphicsContext, pKernelGraphics, pKernelChannel->pVAS); } - // - // When sharing contexts across channels we need to defer this until all - // objects have been freed. - // - NV_CHECK_OR_RETURN_VOID(LEVEL_SILENT, - pKernelGraphicsContextUnicast->channelObjects == 0); + if (kgraphicsDoesUcodeSupportPrivAccessMap(pGpu, pKernelGraphics)) + { + kgrctxUnmapGlobalCtxBuffer(pGpu, + pKernelGraphicsContext, + pKernelGraphics, + pKernelChannel->pVAS, + registerMapBufferId); + } if (pKernelGraphicsContextUnicast->ctxPatchBuffer.pMemDesc != NULL) { @@ -2335,6 +2391,29 @@ kgrctxUnmapAssociatedCtxBuffers_IMPL // Release all preemption buffers if they were allocated kgrctxUnmapCtxPreemptionBuffers(pGpu, pKernelGraphicsContext, pKernelGraphics, pKernelChannel->pVAS); + // + // Cleanup lingering main ctx buffer mappings for this VAS + // TODO fix main ctx buffer refcounting + // TODO move setEngineContextMemDesc to FreeMainCtxBuffer, move this loop + // inside UnmapMainCtxBuffer + // + if (pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup->ppEngCtxDesc[gpumgrGetSubDeviceInstanceFromGpu(pGpu)] != NULL) + { + NvU32 subdevInst = gpumgrGetSubDeviceInstanceFromGpu(pGpu); + VA_LIST *pVAddrList = &pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup->ppEngCtxDesc[subdevInst]->vaList; + NvU64 vaddr; + + while (vaListFindVa(pVAddrList, pKernelChannel->pVAS, &vaddr) == NV_OK) + kgraphicsUnmapCtxBuffer(pGpu, pKernelGraphics, pKernelChannel->pVAS, pVAddrList); + } + + // + // When sharing contexts across channels we need to defer this until all + // objects have been freed. + // + NV_CHECK_OR_RETURN_VOID(LEVEL_SILENT, + pKernelGraphicsContextUnicast->channelObjects == 0); + kgrctxUnmapMainCtxBuffer(pGpu, pKernelGraphicsContext, pKernelGraphics, pKernelChannel); } @@ -2886,6 +2965,7 @@ kgrctxUnmapCtxBuffers_IMPL NvU32 objType; NvU32 gfid; NvU64 refCount; + GR_GLOBALCTX_BUFFER registerMapBufferId = kgrctxGetRegisterAccessMapId_HAL(pGpu, pKernelGraphicsContext, pChannelDescendant->pKernelChannel); NV_PRINTF(LEVEL_INFO, "gpu:%d isBC=%d\n", pGpu->gpuInstance, gpumgrGetBcEnabledStatus(pGpu)); @@ -2932,13 +3012,16 @@ kgrctxUnmapCtxBuffers_IMPL kgrctxUnmapCtxPmBuffer(pGpu, pKernelGraphicsContext, pKernelGraphics, pKernelChannel->pVAS); } - if (kgraphicsDoesUcodeSupportPrivAccessMap(pGpu, pKernelGraphics)) + // Defer releasing mapping if this would cause the buffer to be unmapped + if (kgraphicsDoesUcodeSupportPrivAccessMap(pGpu, pKernelGraphics) && + (vaListGetRefCount(&pKernelGraphicsContextUnicast->globalCtxBufferVaList[registerMapBufferId], pKernelChannel->pVAS, &refCount) == NV_OK) && + (refCount > 1)) { kgrctxUnmapGlobalCtxBuffer(pGpu, pKernelGraphicsContext, pKernelGraphics, pKernelChannel->pVAS, - kgrctxGetRegisterAccessMapId_HAL(pGpu, pKernelGraphicsContext, pChannelDescendant->pKernelChannel)); + registerMapBufferId); } // Defer releasing mapping if this would cause the buffer to be unmapped @@ -3289,21 +3372,13 @@ shrkgrctxInit_IMPL ) { NV_STATUS status = NV_OK; - NvU32 subdevCount = gpumgrGetSubDeviceMaxValuePlus1(pGpu); - - pKernelGraphicsContextShared->pKernelGraphicsContextUnicast = - portMemAllocNonPaged(subdevCount * sizeof(*pKernelGraphicsContextShared->pKernelGraphicsContextUnicast)); - if (pKernelGraphicsContextShared->pKernelGraphicsContextUnicast == NULL) - return NV_ERR_NO_MEMORY; - portMemSet(pKernelGraphicsContextShared->pKernelGraphicsContextUnicast, 0, - subdevCount * sizeof(*pKernelGraphicsContextShared->pKernelGraphicsContextUnicast)); SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) { + KernelGraphicsContextUnicast *pKernelGraphicsContextUnicast; KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); KernelGraphics *pKernelGraphics; NV2080_CTRL_GR_ROUTE_INFO grRouteInfo; - NvU32 subdevInst = gpumgrGetSubDeviceInstanceFromGpu(pGpu); NvHandle hClient = RES_GET_CLIENT_HANDLE(pKernelGraphicsContext); NvHandle hParent = RES_GET_PARENT_HANDLE(pKernelGraphicsContext); @@ -3316,14 +3391,14 @@ shrkgrctxInit_IMPL if (status != NV_OK) SLI_LOOP_BREAK; - NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_ERROR, - shrkgrctxConstructUnicast(pGpu, pKernelGraphicsContextShared, - pKernelGraphicsContext, - pKernelGraphics, - &pKernelGraphicsContextShared->pKernelGraphicsContextUnicast[subdevInst])); + if (kgrctxGetUnicast(pGpu, pKernelGraphicsContext, &pKernelGraphicsContextUnicast) == NV_OK) + { + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_ERROR, + shrkgrctxConstructUnicast(pGpu, pKernelGraphicsContextShared, pKernelGraphicsContext, pKernelGraphics, pKernelGraphicsContextUnicast)); - if (status != NV_OK) - SLI_LOOP_BREAK; + if (status != NV_OK) + SLI_LOOP_BREAK; + } } SLI_LOOP_END; @@ -3393,20 +3468,17 @@ shrkgrctxTeardown_IMPL KernelGraphicsContext *pKernelGraphicsContext ) { - if (pKernelGraphicsContextShared->pKernelGraphicsContextUnicast != NULL) - { - SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) - { - NvU32 subdevInst = gpumgrGetSubDeviceInstanceFromGpu(pGpu); - shrkgrctxDestructUnicast(pGpu, pKernelGraphicsContextShared, - pKernelGraphicsContext, - &pKernelGraphicsContextShared->pKernelGraphicsContextUnicast[subdevInst]); - } - SLI_LOOP_END; - } - portMemFree(pKernelGraphicsContextShared->pKernelGraphicsContextUnicast); - pKernelGraphicsContextShared->pKernelGraphicsContextUnicast = NULL; + SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) + { + KernelGraphicsContextUnicast *pKernelGraphicsContextUnicast; + + if (kgrctxGetUnicast(pGpu, pKernelGraphicsContext, &pKernelGraphicsContextUnicast) == NV_OK) + shrkgrctxDestructUnicast(pGpu, pKernelGraphicsContextShared, pKernelGraphicsContext, pKernelGraphicsContextUnicast); + } + SLI_LOOP_END; + + portMemSet(&pKernelGraphicsContext->pShared->kernelGraphicsContextUnicast, 0x0, sizeof(pKernelGraphicsContext->pShared->kernelGraphicsContextUnicast)); } /*! @@ -3503,17 +3575,13 @@ void shrkgrctxDetach_IMPL if (!kgrctxShouldCleanup(pGpu, pKernelGraphicsContext)) return; - - if (pKernelGraphicsContextShared->pKernelGraphicsContextUnicast != NULL) + SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) { - SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) - { - NvU32 subdevInst = gpumgrGetSubDeviceInstanceFromGpu(pGpu); - kgrctxUnmapBuffers_HAL(pGpu, pKernelGraphicsContext, - &pKernelGraphicsContextShared->pKernelGraphicsContextUnicast[subdevInst], - pKernelChannel); - } - SLI_LOOP_END; + KernelGraphicsContextUnicast *pKernelGraphicsContextUnicast; + + if (kgrctxGetUnicast(pGpu, pKernelGraphicsContext, &pKernelGraphicsContextUnicast) == NV_OK) + kgrctxUnmapBuffers_HAL(pGpu, pKernelGraphicsContext, pKernelGraphicsContextUnicast, pKernelChannel); } + SLI_LOOP_END; } diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_graphics_manager.c b/src/nvidia/src/kernel/gpu/gr/kernel_graphics_manager.c index 102a41ed5..08258b8a8 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_graphics_manager.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_graphics_manager.c @@ -796,8 +796,6 @@ kgrmgrDiscoverMaxLocalCtxBufInfo_IMPL ) { KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); - const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); - NvU32 bufId; // // Most of GR is stub'd so context related things are not needed in AMODEL. @@ -810,43 +808,7 @@ kgrmgrDiscoverMaxLocalCtxBufInfo_IMPL NV_CHECK_OR_RETURN(LEVEL_SILENT, kmigmgrIsMemoryPartitioningNeeded_HAL(pGpu, pKernelMIGManager, swizzId), NV_OK); - // Make sure sizes of all buffers are setup - NV_ASSERT_OK_OR_RETURN( - kgraphicsInitializeDeferredStaticData(pGpu, pKernelGraphics, NV01_NULL_OBJECT, NV01_NULL_OBJECT)); - - NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo->pContextBuffersInfo != NULL, NV_ERR_INVALID_STATE); - - // Get sizes of local ctx buffers - FOR_EACH_IN_ENUM(GR_CTX_BUFFER, bufId) - { - if (bufId == GR_CTX_BUFFER_MAIN) - { - NvU32 size; - - // Get size of main buffer including subctx headers - NV_ASSERT_OK_OR_RETURN(kgraphicsGetMainCtxBufferSize(pGpu, pKernelGraphics, NV_TRUE, &size)); - kgraphicsSetCtxBufferInfo(pGpu, pKernelGraphics, bufId, - size, - RM_PAGE_SIZE, - RM_ATTR_PAGE_SIZE_4KB, - kgraphicsShouldForceMainCtxContiguity_HAL(pGpu, pKernelGraphics)); - } - else - { - NvU32 fifoEngineId; - - NV_ASSERT_OK_OR_RETURN( - kgrctxCtxBufferToFifoEngineId(bufId, &fifoEngineId)); - - kgraphicsSetCtxBufferInfo(pGpu, pKernelGraphics, bufId, - pKernelGraphicsStaticInfo->pContextBuffersInfo->engine[fifoEngineId].size, - RM_PAGE_SIZE, - RM_ATTR_PAGE_SIZE_4KB, - ((bufId == GR_CTX_BUFFER_PATCH) || (bufId == GR_CTX_BUFFER_PM))); - } - } - FOR_EACH_IN_ENUM_END; - return NV_OK; + return kgraphicsDiscoverMaxLocalCtxBufferSize(pGpu, pKernelGraphics); } /*! diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/ada/kernel_gsp_ad102.c b/src/nvidia/src/kernel/gpu/gsp/arch/ada/kernel_gsp_ad102.c index 0ba69346f..f390dc60e 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/ada/kernel_gsp_ad102.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/ada/kernel_gsp_ad102.c @@ -85,27 +85,3 @@ kgspExecuteScrubberIfNeeded_AD102 return status; } -NvU64 -kgspGetWprHeapSize_AD102 -( - OBJGPU *pGpu, - KernelGsp *pKernelGsp -) -{ - if (pGpu->bVgpuGspPluginOffloadEnabled) - { - // - // Memory calculations which we used to size the WPR heap: - // Memory needed for libOS kernel - 10MB(RM) + 32MB(VF partitions) + 8MB(global page) = 50MB - // Memory needed from FW's Heap - 17MB for RM + 15MB * 32(VF) = 497MB - // Total Memory needed = 497MB + 50MB = 547MB - // (Added extra 2 Mb due to alignment) - // @TODO: Change total Heap size to 546MB once fix for making global page to 4MB submitted. - // - return 550 * 1024 * 1024; - } - else - { - return 80 * 1024 * 1024; - } -} \ No newline at end of file diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c b/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c index 09b628f7e..de207c4c3 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c @@ -142,13 +142,14 @@ kgspAllocBootArgs_GH100 NvP64 pVa = NvP64_NULL; NvP64 pPriv = NvP64_NULL; NV_STATUS nvStatus = NV_OK; + NvU64 flags = MEMDESC_FLAGS_NONE; // Allocate GSP-FMC arguments NV_ASSERT_OK_OR_GOTO(nvStatus, memdescCreate(&pKernelGsp->pGspFmcArgumentsDescriptor, pGpu, sizeof(GSP_FMC_BOOT_PARAMS), 0x1000, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, - MEMDESC_FLAGS_NONE), + flags), _kgspAllocBootArgs_exit_cleanup); NV_ASSERT_OK_OR_GOTO(nvStatus, @@ -302,6 +303,10 @@ kgspCalculateFbLayout_GH100 // pWprMeta->gspFwHeapSize = kgspGetWprHeapSize(pGpu, pKernelGsp); + // Number of VF partitions allocating sub-heaps from the WPR heap + pWprMeta->gspFwHeapVfPartitionCount = + pGpu->bVgpuGspPluginOffloadEnabled ? MAX_PARTITIONS_WITH_GFID : 0; + // Fill in the meta-metadata pWprMeta->revision = GSP_FW_WPR_META_REVISION; pWprMeta->magic = GSP_FW_WPR_META_MAGIC; @@ -372,38 +377,7 @@ _kgspIsLockdownReleased _UNLOCK, reg); } -/*! - * Determine if PRIV target mask is unlocked for GSP and BAR0 Decoupler allows GSP access. - * - * This is temporary WAR for the PRIV target mask bug 3640831 until we have notification - * protocol in place (there is no HW mechanism for CPU to check if GSP is open other than - * reading 0xBADF41YY code). - * - * Until the programmed BAR0 decoupler settings are cleared, GSP access is blocked from - * the CPU so all reads will return 0. - */ -static NvBool -_kgspIsTargetMaskReleased -( - OBJGPU *pGpu, - void *pVoid -) -{ - KernelGsp *pKernelGsp = reinterpretCast(pVoid, KernelGsp *); - KernelFalcon *pKernelFalcon = staticCast(pKernelGsp, KernelFalcon); - const NvU32 privErrTargetLocked = 0xBADF4100U; - const NvU32 privErrTargetLockedMask = 0xFFFFFF00U; // Ignore LSB - it has extra error information - NvU32 reg; - // - // This register is read with the raw OS read to avoid the 0xbadf sanity checking - // done by the usual register read utilities. - // - reg = osDevReadReg032(pGpu, gpuGetDeviceMapping(pGpu, DEVICE_INDEX_GPU, 0), - pKernelFalcon->registerBase + NV_PFALCON_FALCON_HWCFG2); - - return ((reg != 0) && ((reg & privErrTargetLockedMask) != privErrTargetLocked)); -} static void @@ -538,7 +512,7 @@ kgspBootstrapRiscvOSEarly_GH100 } // Wait for target mask to be released. - status = gpuTimeoutCondWait(pGpu, _kgspIsTargetMaskReleased, pKernelGsp, NULL); + status = kfspWaitForGspTargetMaskReleased_HAL(pGpu, pKernelFsp); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Timeout waiting for GSP target mask release. " diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_booter_tu102.c b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_booter_tu102.c index 1d64717d9..3fb965929 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_booter_tu102.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_booter_tu102.c @@ -88,7 +88,7 @@ kgspExecuteBooterLoad_TU102 ( OBJGPU *pGpu, KernelGsp *pKernelGsp, - const NvU64 gspFwWprMetaOffset + const NvU64 sysmemAddrOfData ) { NV_STATUS status; @@ -98,12 +98,15 @@ kgspExecuteBooterLoad_TU102 NV_ASSERT_OR_RETURN(pKernelGsp->pBooterLoadUcode != NULL, NV_ERR_INVALID_STATE); - // Provide gspFwWprMetaOffset in falcon SEC mailboxes 0 (low 32 bits) and 1 (high 32 bits) - mailbox0 = NvU64_LO32(gspFwWprMetaOffset); - mailbox1 = NvU64_HI32(gspFwWprMetaOffset); + // + // sysmemAddrOfData either represents the FW WPR MetaData or the FW SR Data as a physical address in SYSTEM + // Provide that data in falcon SEC mailboxes 0 (low 32 bits) and 1 (high 32 bits) + // + mailbox0 = NvU64_LO32(sysmemAddrOfData); + mailbox1 = NvU64_HI32(sysmemAddrOfData); - NV_PRINTF(LEVEL_INFO, "executing Booter Load, gspFwWprMetaOffset 0x%llx\n", - gspFwWprMetaOffset); + NV_PRINTF(LEVEL_INFO, "executing Booter Load, sysmemAddrOfData 0x%llx\n", + sysmemAddrOfData); kflcnReset_HAL(pGpu, staticCast(pKernelSec2, KernelFalcon)); @@ -124,11 +127,13 @@ NV_STATUS kgspExecuteBooterUnloadIfNeeded_TU102 ( OBJGPU *pGpu, - KernelGsp *pKernelGsp + KernelGsp *pKernelGsp, + const NvU64 sysmemAddrOfSuspendResumeData ) { NV_STATUS status; KernelSec2 *pKernelSec2 = GPU_GET_KERNEL_SEC2(pGpu); + NvU32 mailbox0 = 0xFF, mailbox1 = 0xFF; // skip actually executing Booter Unload if WPR2 is not up NvU32 data = GPU_REG_RD32(pGpu, NV_PFB_PRI_MMU_WPR2_ADDR_HI); @@ -143,10 +148,17 @@ kgspExecuteBooterUnloadIfNeeded_TU102 NV_ASSERT_OR_RETURN(pKernelGsp->pBooterUnloadUcode != NULL, NV_ERR_INVALID_STATE); kflcnReset_HAL(pGpu, staticCast(pKernelSec2, KernelFalcon)); + + // SR code + if (sysmemAddrOfSuspendResumeData != 0) + { + mailbox0 = NvU64_LO32(sysmemAddrOfSuspendResumeData); + mailbox1 = NvU64_HI32(sysmemAddrOfSuspendResumeData); + } status = s_executeBooterUcode_TU102(pGpu, pKernelGsp, pKernelGsp->pBooterUnloadUcode, staticCast(pKernelSec2, KernelFalcon), - 0xFF, 0xFF); + mailbox0, mailbox1); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "failed to execute Booter Unload: 0x%x\n", status); diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c index 3f4e42b3d..75f2cc7be 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c @@ -56,7 +56,6 @@ #undef RPC_STRUCTURES #undef RPC_GENERIC_UNION - void kgspConfigureFalcon_TU102 ( @@ -108,25 +107,26 @@ kgspAllocBootArgs_TU102 NvP64 pVa = NvP64_NULL; NvP64 pPriv = NvP64_NULL; NV_STATUS nvStatus = NV_OK; + NvU64 flags = MEMDESC_FLAGS_NONE; // Allocate WPR meta data NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescCreate(&pKernelGsp->pWprMetaDescriptor, - pGpu, 0x1000, 0x1000, - NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, - MEMDESC_FLAGS_NONE), - _kgspAllocBootArgs_exit_cleanup); + memdescCreate(&pKernelGsp->pWprMetaDescriptor, + pGpu, 0x1000, 0x1000, + NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, + flags), + _kgspAllocBootArgs_exit_cleanup); NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescAlloc(pKernelGsp->pWprMetaDescriptor), - _kgspAllocBootArgs_exit_cleanup); + memdescAlloc(pKernelGsp->pWprMetaDescriptor), + _kgspAllocBootArgs_exit_cleanup); NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescMap(pKernelGsp->pWprMetaDescriptor, 0, - memdescGetSize(pKernelGsp->pWprMetaDescriptor), - NV_TRUE, NV_PROTECT_READ_WRITE, - &pVa, &pPriv), - _kgspAllocBootArgs_exit_cleanup); + memdescMap(pKernelGsp->pWprMetaDescriptor, 0, + memdescGetSize(pKernelGsp->pWprMetaDescriptor), + NV_TRUE, NV_PROTECT_READ_WRITE, + &pVa, &pPriv), + _kgspAllocBootArgs_exit_cleanup); pKernelGsp->pWprMeta = (GspFwWprMeta *)NvP64_VALUE(pVa); pKernelGsp->pWprMetaMappingPriv = pPriv; @@ -135,24 +135,24 @@ kgspAllocBootArgs_TU102 // Setup libos arguments memory // NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescCreate(&pKernelGsp->pLibosInitArgumentsDescriptor, - pGpu, - LIBOS_INIT_ARGUMENTS_SIZE, - LIBOS_INIT_ARGUMENTS_SIZE, - NV_TRUE, ADDR_SYSMEM, NV_MEMORY_UNCACHED, - MEMDESC_FLAGS_NONE), - _kgspAllocBootArgs_exit_cleanup); + memdescCreate(&pKernelGsp->pLibosInitArgumentsDescriptor, + pGpu, + LIBOS_INIT_ARGUMENTS_SIZE, + LIBOS_INIT_ARGUMENTS_SIZE, + NV_TRUE, ADDR_SYSMEM, NV_MEMORY_UNCACHED, + flags), + _kgspAllocBootArgs_exit_cleanup); NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescAlloc(pKernelGsp->pLibosInitArgumentsDescriptor), - _kgspAllocBootArgs_exit_cleanup); + memdescAlloc(pKernelGsp->pLibosInitArgumentsDescriptor), + _kgspAllocBootArgs_exit_cleanup); NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescMap(pKernelGsp->pLibosInitArgumentsDescriptor, 0, - memdescGetSize(pKernelGsp->pLibosInitArgumentsDescriptor), - NV_TRUE, NV_PROTECT_READ_WRITE, + memdescMap(pKernelGsp->pLibosInitArgumentsDescriptor, 0, + memdescGetSize(pKernelGsp->pLibosInitArgumentsDescriptor), + NV_TRUE, NV_PROTECT_READ_WRITE, &pVa, &pPriv), - _kgspAllocBootArgs_exit_cleanup); + _kgspAllocBootArgs_exit_cleanup); pKernelGsp->pLibosInitArgumentsCached = (LibosMemoryRegionInitArgument *)NvP64_VALUE(pVa); pKernelGsp->pLibosInitArgumentsMappingPriv = pPriv; @@ -161,22 +161,22 @@ kgspAllocBootArgs_TU102 NV_ASSERT(sizeof(GSP_ARGUMENTS_CACHED) <= 0x1000); NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescCreate(&pKernelGsp->pGspArgumentsDescriptor, - pGpu, 0x1000, 0x1000, - NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, - MEMDESC_FLAGS_NONE), - _kgspAllocBootArgs_exit_cleanup); + memdescCreate(&pKernelGsp->pGspArgumentsDescriptor, + pGpu, 0x1000, 0x1000, + NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, + flags), + _kgspAllocBootArgs_exit_cleanup); NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescAlloc(pKernelGsp->pGspArgumentsDescriptor), - _kgspAllocBootArgs_exit_cleanup); + memdescAlloc(pKernelGsp->pGspArgumentsDescriptor), + _kgspAllocBootArgs_exit_cleanup); NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescMap(pKernelGsp->pGspArgumentsDescriptor, 0, - memdescGetSize(pKernelGsp->pGspArgumentsDescriptor), - NV_TRUE, NV_PROTECT_READ_WRITE, - &pVa, &pPriv), - _kgspAllocBootArgs_exit_cleanup); + memdescMap(pKernelGsp->pGspArgumentsDescriptor, 0, + memdescGetSize(pKernelGsp->pGspArgumentsDescriptor), + NV_TRUE, NV_PROTECT_READ_WRITE, + &pVa, &pPriv), + _kgspAllocBootArgs_exit_cleanup); pKernelGsp->pGspArgumentsCached = (GSP_ARGUMENTS_CACHED *)NvP64_VALUE(pVa); pKernelGsp->pGspArgumentsMappingPriv = pPriv; @@ -361,8 +361,11 @@ kgspBootstrapRiscvOSEarly_TU102 kflcnReset_HAL(pGpu, pKernelFalcon); NV_ASSERT_OK_OR_GOTO(status, - kgspExecuteFwsecFrts_HAL(pGpu, pKernelGsp, pKernelGsp->pFwsecUcode, - pKernelGsp->pWprMeta->frtsOffset), exit); + kgspExecuteFwsecFrts_HAL(pGpu, + pKernelGsp, + pKernelGsp->pFwsecUcode, + pKernelGsp->pWprMeta->frtsOffset), + exit); } } @@ -426,11 +429,13 @@ kgspBootstrapRiscvOSEarly_TU102 NV_PRINTF(LEVEL_INFO, "Waiting for GSP fw RM to be ready...\n"); // Link the status queue. - NV_ASSERT_OK_OR_GOTO(status, GspStatusQueueInit(pGpu, &pKernelGsp->pRpc->pMessageQueueInfo), - exit); + NV_ASSERT_OK_OR_GOTO(status, + GspStatusQueueInit(pGpu, &pKernelGsp->pRpc->pMessageQueueInfo), + exit); - NV_ASSERT_OK_OR_GOTO(status, kgspWaitForRmInitDone(pGpu, pKernelGsp), - exit); + NV_ASSERT_OK_OR_GOTO(status, + kgspWaitForRmInitDone(pGpu, pKernelGsp), + exit); NV_PRINTF(LEVEL_INFO, "GSP FW RM ready.\n"); @@ -559,24 +564,29 @@ kgspCalculateFbLayout_TU102 // // Compute the start of the ELF. Align to 64K to avoid issues with - // inherent alignment constraints (e.g. GC6 buffers which are allocated - // just below this offset). + // inherent alignment constraints. // pWprMeta->gspFwOffset = NV_ALIGN_DOWN64(pWprMeta->bootBinOffset - pWprMeta->sizeOfRadix3Elf, 0x10000); - NvU64 wprHeapSize = kgspGetWprHeapSize(pGpu, pKernelGsp); + const NvU64 wprHeapSize = kgspGetWprHeapSize(pGpu, pKernelGsp); - // Start of WPR region (1Mb aligned) - pWprMeta->gspFwWprStart = - NV_ALIGN_DOWN64(pWprMeta->gspFwOffset - wprHeapSize, 0x100000); - - // GSP-RM heap in WPR, align to 1Mb - pWprMeta->gspFwHeapOffset = NV_ALIGN_UP64(pWprMeta->gspFwWprStart + sizeof *pWprMeta, 0x100000); + // GSP-RM heap in WPR, align to 1MB + pWprMeta->gspFwHeapOffset = NV_ALIGN_DOWN64(pWprMeta->gspFwOffset - wprHeapSize, 0x100000); pWprMeta->gspFwHeapSize = NV_ALIGN_DOWN64(pWprMeta->gspFwOffset - pWprMeta->gspFwHeapOffset, 0x100000); - // Non WPR heap + // Number of VF partitions allocating sub-heaps from the WPR heap + pWprMeta->gspFwHeapVfPartitionCount = pGpu->bVgpuGspPluginOffloadEnabled ? MAX_PARTITIONS_WITH_GFID : 0; + + // + // Start of WPR region (128K alignment requirement, but 1MB aligned so that + // the extra padding sits in WPR instead of in between the end of the + // non-WPR heap and the start of WPR). + // + pWprMeta->gspFwWprStart = NV_ALIGN_DOWN64(pWprMeta->gspFwHeapOffset - sizeof *pWprMeta, 0x100000); + + // Non WPR heap (1MB aligned) pWprMeta->nonWprHeapSize = kgspGetNonWprHeapSize(pGpu, pKernelGsp); - pWprMeta->nonWprHeapOffset = pWprMeta->gspFwWprStart - pWprMeta->nonWprHeapSize; + pWprMeta->nonWprHeapOffset = NV_ALIGN_DOWN64(pWprMeta->gspFwWprStart - pWprMeta->nonWprHeapSize, 0x100000); pWprMeta->gspFwRsvdStart = pWprMeta->nonWprHeapOffset; @@ -604,15 +614,6 @@ kgspCalculateFbLayout_TU102 pWprMeta->revision = GSP_FW_WPR_META_REVISION; pWprMeta->magic = GSP_FW_WPR_META_MAGIC; - if (pGpu->bVgpuGspPluginOffloadEnabled) - { - pKernelGsp->pWprMeta->driverModel = 1; - } - else - { - pKernelGsp->pWprMeta->driverModel = 0; - } - #if 0 NV_PRINTF(LEVEL_ERROR, "WPR meta data offset: 0x%016llx\n", pWprMeta->gspFwWprStart); NV_PRINTF(LEVEL_ERROR, " magic: 0x%016llx\n", pWprMeta->magic); @@ -735,21 +736,6 @@ kgspResetHw_TU102 return NV_OK; } -/*! - * Return NV_OK along with the Engine Reset state. - */ -NvBool -kgspIsEngineInReset_TU102 -( - OBJGPU *pGpu, - KernelGsp *pKernelGsp -) -{ - NvU32 val = GPU_REG_RD32(pGpu, NV_PGSP_FALCON_ENGINE); - - return FLD_TEST_DRF(_PGSP_FALCON, _ENGINE, _RESET, _TRUE, val); -} - void kgspHealthCheck_TU102 ( @@ -940,3 +926,123 @@ kgspWaitForGfwBootOk_TU102 return status; } + +void +kgspFreeSuspendResumeData_TU102 +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp +) +{ + // release sr meta data resources + if (pKernelGsp->pSRMetaDescriptor != NULL) + { + memdescFree(pKernelGsp->pSRMetaDescriptor); + memdescDestroy(pKernelGsp->pSRMetaDescriptor); + pKernelGsp->pSRMetaDescriptor = NULL; + } + + // release sr meta data resources + if (pKernelGsp->pSRRadix3Descriptor != NULL) + { + memdescFree(pKernelGsp->pSRRadix3Descriptor); + memdescDestroy(pKernelGsp->pSRRadix3Descriptor); + pKernelGsp->pSRRadix3Descriptor = NULL; + } +} + +NV_STATUS +kgspSavePowerMgmtState_TU102 +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp +) +{ + GspFwSRMeta gspfwSRMeta; + NvP64 pVa = NvP64_NULL; + NvP64 pPriv = NvP64_NULL; + NV_STATUS nvStatus = NV_OK; + + // Fill in GspFwSRMeta structure + portMemSet(&gspfwSRMeta, 0, sizeof(gspfwSRMeta)); + gspfwSRMeta.magic = GSP_FW_SR_META_MAGIC; + gspfwSRMeta.revision = GSP_FW_SR_META_REVISION; + gspfwSRMeta.sizeOfSuspendResumeData = pKernelGsp->pWprMeta->gspFwWprEnd - pKernelGsp->pWprMeta->gspFwWprStart; + + + NV_ASSERT_OK_OR_GOTO(nvStatus, + kgspCreateRadix3(pGpu, + pKernelGsp, + &pKernelGsp->pSRRadix3Descriptor, + NULL, + NULL, + gspfwSRMeta.sizeOfSuspendResumeData), + exit_fail_cleanup); + + gspfwSRMeta.sysmemAddrOfSuspendResumeData = memdescGetPhysAddr(pKernelGsp->pSRRadix3Descriptor, AT_GPU, 0); + + // Create SR Metadata Area + NV_ASSERT_OK_OR_GOTO(nvStatus, + memdescCreate(&pKernelGsp->pSRMetaDescriptor, + pGpu, + sizeof(GspFwSRMeta), + 256, + NV_TRUE, + ADDR_SYSMEM, + NV_MEMORY_UNCACHED, + MEMDESC_FLAGS_NONE), + exit_fail_cleanup); + + NV_ASSERT_OK_OR_GOTO(nvStatus, + memdescAlloc(pKernelGsp->pSRMetaDescriptor), + exit_fail_cleanup); + + // Copy SR Metadata Structure + NV_ASSERT_OK_OR_GOTO(nvStatus, + memdescMap(pKernelGsp->pSRMetaDescriptor, + 0, + memdescGetSize(pKernelGsp->pSRMetaDescriptor), + NV_TRUE, + NV_PROTECT_WRITEABLE, + &pVa, + &pPriv), + exit_fail_cleanup); + + portMemCopy(pVa, sizeof(gspfwSRMeta), &gspfwSRMeta, sizeof(gspfwSRMeta)); + + memdescUnmap(pKernelGsp->pSRMetaDescriptor, + NV_TRUE, osGetCurrentProcess(), + pVa, pPriv); + + NV_ASSERT_OK_OR_GOTO(nvStatus, + kgspExecuteBooterUnloadIfNeeded_HAL(pGpu, + pKernelGsp, + memdescGetPhysAddr(pKernelGsp->pSRMetaDescriptor,AT_GPU, 0)), + exit_fail_cleanup); + + return nvStatus; + +exit_fail_cleanup: + kgspFreeSuspendResumeData_HAL(pGpu, pKernelGsp); + return nvStatus; +} + +NV_STATUS +kgspRestorePowerMgmtState_TU102 +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp +) +{ + NV_STATUS nvStatus = NV_OK; + + NV_ASSERT_OK_OR_GOTO(nvStatus, + kgspExecuteBooterLoad_HAL(pGpu, + pKernelGsp, + memdescGetPhysAddr(pKernelGsp->pSRMetaDescriptor, AT_GPU,0)), + exit_cleanup); + +exit_cleanup: + kgspFreeSuspendResumeData_HAL(pGpu, pKernelGsp); + return nvStatus; +} diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_vbios_tu102.c b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_vbios_tu102.c index 26efefcfe..d179af79f 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_vbios_tu102.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_vbios_tu102.c @@ -33,7 +33,7 @@ */ #include "gpu/gsp/kernel_gsp.h" -#include "gpu/pmu/kern_pmu.h" +#include "gpu/bif/kernel_bif.h" #include "platform/pci_exp_table.h" // PCI_EXP_ROM_* #include "gpu/gpu.h" @@ -452,7 +452,7 @@ kgspExtractVbiosFromRom_TU102 NV_STATUS status = NV_OK; KernelGspVbiosImg *pVbiosImg = NULL; - KernelPmu *pKernelPmu = GPU_GET_KERNEL_PMU(pGpu); + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); RomImgSrc src; NvU32 romSig; @@ -479,9 +479,9 @@ kgspExtractVbiosFromRom_TU102 src.maxOffset = biosSize; src.pGpu = pGpu; - if (pKernelPmu != NULL) + if (pKernelBif != NULL) { - status = kpmuPreOsGlobalErotGrantRequest_HAL(pGpu, pKernelPmu); + status = kbifPreOsGlobalErotGrantRequest_HAL(pGpu, pKernelBif); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "ERoT Req/Grant for EEPROM access failed, status=%u\n", diff --git a/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c b/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c index 5d9216495..a09729de0 100644 --- a/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c +++ b/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c @@ -88,6 +88,8 @@ static NV_STATUS _kgspInitRpcInfrastructure(OBJGPU *, KernelGsp *); static void _kgspFreeRpcInfrastructure(OBJGPU *, KernelGsp *); +static NV_STATUS _kgspConstructRpcObject(OBJGPU *, KernelGsp *, MESSAGE_QUEUE_INFO *, OBJRPC **); + static NV_STATUS _kgspRpcSendMessage(OBJGPU *, OBJRPC *); static NV_STATUS _kgspRpcRecvPoll(OBJGPU *, OBJRPC *, NvU32); static NV_STATUS _kgspRpcDrainEvents(OBJGPU *, KernelGsp *, NvU32); @@ -101,9 +103,6 @@ static void _kgspFreeBootBinaryImage(OBJGPU *pGpu, KernelGsp *pKernelGsp); static NV_STATUS _kgspPrepareGspRmBinaryImage(OBJGPU *pGpu, KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); -static NV_STATUS _kgspCreateRadix3(OBJGPU *pGpu, MEMORY_DESCRIPTOR **ppMemdescRadix3, - MEMORY_DESCRIPTOR *pMemdescData, const void *pData, NvU64 size); - static NV_STATUS _kgspCreateSignatureMemdesc(OBJGPU *pGpu, KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); @@ -181,12 +180,12 @@ _kgspRpcSendMessage nvStatus = GspMsgQueueSendCommand(pRpc->pMessageQueueInfo, pGpu); if (nvStatus != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "GspMsgQueueSendCommand failed: 0x%x\n", nvStatus); + NV_PRINTF(LEVEL_ERROR, "GspMsgQueueSendCommand failed on GPU%d: 0x%x\n", + gpuGetInstance(pGpu), nvStatus); return nvStatus; } - // GSPRM TODO: Use this call to pass the actual index. - kgspSetCmdQueueHead_HAL(pGpu, pKernelGsp, 0, 0); + kgspSetCmdQueueHead_HAL(pGpu, pKernelGsp, pRpc->pMessageQueueInfo->queueIdx, 0); // Add RPC history entry { @@ -504,6 +503,20 @@ _kgspRpcPerfBridgelessInfoUpdate kPerfGpuBoostSyncBridgelessUpdateInfo(pGpu, rpc_params->bBridgeless); } +static void +_kgspRpcNvlinkFaultUpCallback +( + OBJGPU *pGpu, + OBJRPC *pRpc +) +{ + RPC_PARAMS(nvlink_fault_up, _v17_00); + + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + + knvlinkHandleFaultUpInterrupt_HAL(pGpu, pKernelNvlink, rpc_params->linkId); +} + static void _kgspRpcNvlinkInbandReceivedData256Callback ( @@ -776,6 +789,23 @@ _kgspRpcGspExtdevIntrService return NV_OK; } +static void +_kgspRpcGspSendUserSharedData +( + OBJGPU *pGpu, + OBJRPC *pRpc +) +{ + RPC_PARAMS(gsp_send_user_shared_data, _v17_00); + NV00DE_SHARED_DATA *pSharedData = gpushareddataWriteStart(pGpu); + GspUserSharedData *pRpcData = (GspUserSharedData*)(&rpc_params->data); + + // Copy over all GSP-owned data + pSharedData->gspAssertCount = pRpcData->gspAssertCount; + + gpushareddataWriteFinish(pGpu); +} + static NV_STATUS _kgspRpcRgLineIntr ( @@ -866,8 +896,8 @@ _kgspProcessRpcEvent rpc_message_header_v *pMsgHdr = RPC_HDR; NV_STATUS nvStatus = NV_OK; - NV_PRINTF(LEVEL_INFO, "received event: 0x%x (%s) status: 0x%x size: %d\n", - pMsgHdr->function, _getRpcName(pMsgHdr->function), pMsgHdr->rpc_result, pMsgHdr->length); + NV_PRINTF(LEVEL_INFO, "received event from GPU%d: 0x%x (%s) status: 0x%x size: %d\n", + gpuGetInstance(pGpu), pMsgHdr->function, _getRpcName(pMsgHdr->function), pMsgHdr->rpc_result, pMsgHdr->length); switch(pMsgHdr->function) { @@ -919,6 +949,10 @@ _kgspProcessRpcEvent _kgspRpcTimedSemaphoreRelease(pGpu, pRpc); break; + case NV_VGPU_MSG_EVENT_NVLINK_FAULT_UP: + _kgspRpcNvlinkFaultUpCallback(pGpu, pRpc); + break; + case NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_256: _kgspRpcNvlinkInbandReceivedData256Callback(pGpu, pRpc); break; @@ -967,6 +1001,10 @@ _kgspProcessRpcEvent nvStatus = _kgspRpcEventPlatformRequestHandlerStateSyncCallback(pGpu, pRpc); break; + case NV_VGPU_MSG_EVENT_GSP_SEND_USER_SHARED_DATA: + _kgspRpcGspSendUserSharedData(pGpu, pRpc); + break; + case NV_VGPU_MSG_EVENT_GSP_LOCKDOWN_NOTICE: _kgspRpcGspLockdownNotice(pGpu, pRpc); break; @@ -979,8 +1017,8 @@ _kgspProcessRpcEvent // for the timeout has already happened, and returning an error here // causes subsequent messages to fail. So return NV_OK. // - NV_PRINTF(LEVEL_ERROR, "Unexpected RPC event 0x%x (%s)\n", - pMsgHdr->function, _getRpcName(pMsgHdr->function)); + NV_PRINTF(LEVEL_ERROR, "Unexpected RPC event from GPU%d: 0x%x (%s)\n", + gpuGetInstance(pGpu), pMsgHdr->function, _getRpcName(pMsgHdr->function)); break; } @@ -1024,8 +1062,8 @@ _kgspRpcDrainOneEvent if (nvStatus != NV_OK) { NV_PRINTF(LEVEL_ERROR, - "Failed to process received event 0x%x (%s): status=0x%x\n", - pMsgHdr->function, _getRpcName(pMsgHdr->function), nvStatus); + "Failed to process received event 0x%x (%s) from GPU%d: status=0x%x\n", + pMsgHdr->function, _getRpcName(pMsgHdr->function), gpuGetInstance(pGpu), nvStatus); } } @@ -1103,7 +1141,8 @@ _kgspLogXid119 &activeData[0], &activeData[1]); nvErrorLog_va((void*)pGpu, GSP_RPC_TIMEOUT, - "Timeout waiting for RPC from GSP! Expected function %d (%s) (0x%x 0x%x).", + "Timeout waiting for RPC from GSP%d! Expected function %d (%s) (0x%x 0x%x).", + gpuGetInstance(pGpu), expectedFunc, _getRpcName(expectedFunc), pRpc->rpcHistory[historyEntry].data[0], @@ -1126,7 +1165,7 @@ _kgspLogXid119 pRpc->rpcHistory[historyEntry].data[1]); } - NV_PRINTF(LEVEL_ERROR, "RPC history (CPU -> GSP):\n"); + NV_PRINTF(LEVEL_ERROR, "RPC history (CPU -> GSP%d):\n", gpuGetInstance(pGpu)); NV_PRINTF(LEVEL_ERROR, "\tentry\tfunc\t\t\t\tdata\n"); for (historyIndex = 0; historyIndex < RPC_HISTORY_DEPTH; historyIndex++) { @@ -1164,7 +1203,7 @@ _kgspRpcRecvPoll KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); NV_STATUS nvStatus; RMTIMEOUT timeout; - NvU32 timeoutUs; + NvU32 timeoutUs = GPU_TIMEOUT_DEFAULT; NvBool bSlowGspRpc = IS_EMULATION(pGpu) || IS_SIMULATION(pGpu); // @@ -1197,20 +1236,12 @@ _kgspRpcRecvPoll } else { + // We should only ever timeout this when GSP is in really bad state, so if it just + // happens to timeout on default timeout it should be OK for us to give it a little + // more time - make this timeout 1.5 of the default to allow some leeway. NvU32 defaultus = pGpu->timeoutData.defaultus; - if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) - { - // Ensure at least 3.1s for vGPU-GSP before adding leeway (Bug 3928607) - timeoutUs = NV_MAX(3100 * 1000, defaultus) + (defaultus / 2); - } - else - { - // We should only ever timeout this when GSP is in really bad state, so if it just - // happens to timeout on default timeout it should be OK for us to give it a little - // more time - make this timeout 1.5 of the default to allow some leeway. - timeoutUs = defaultus + defaultus / 2; - } + timeoutUs = defaultus + defaultus / 2; } NV_ASSERT(rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); @@ -1260,50 +1291,94 @@ done: } /*! - * Initialize stripped down version of RPC infra init for GSP clients. + * Initialize RPC objects required for interfacing with GSP. */ static NV_STATUS _kgspInitRpcInfrastructure ( - OBJGPU *pGpu, + OBJGPU *pGpu, KernelGsp *pKernelGsp ) { NV_STATUS nvStatus = NV_OK; + MESSAGE_QUEUE_COLLECTION *pMQCollection = NULL; - pKernelGsp->pRpc = initRpcObject(pGpu); - if (pKernelGsp->pRpc == NULL) + nvStatus = GspMsgQueuesInit(pGpu, &pMQCollection); + if (nvStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "GspMsgQueueInit failed\n"); + goto done; + } + + pKernelGsp->pMQCollection = pMQCollection; + + // Init RM RPC object + nvStatus = _kgspConstructRpcObject(pGpu, pKernelGsp, + &pMQCollection->rpcQueues[RPC_TASK_RM_QUEUE_IDX], + &pKernelGsp->pRpc); + if (nvStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "init task RM RPC infrastructure failed\n"); + goto done; + } + + // Init task_isr RPC object + if (pKernelGsp->bIsTaskIsrQueueRequired) + { + nvStatus = _kgspConstructRpcObject(pGpu, pKernelGsp, + &pMQCollection->rpcQueues[RPC_TASK_ISR_QUEUE_IDX], + &pKernelGsp->pLocklessRpc); + if (nvStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "init task ISR RPC infrastructure failed\n"); + goto done; + } + } + +done: + if (nvStatus != NV_OK) + { + _kgspFreeRpcInfrastructure(pGpu, pKernelGsp); + } + + return nvStatus; +} + + +/*! + * Initialize stripped down version of RPC infra init for GSP clients. + */ +static NV_STATUS +_kgspConstructRpcObject +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp, + MESSAGE_QUEUE_INFO *pMQI, + OBJRPC **ppRpc +) +{ + OBJRPC *pRpc; + + NV_ASSERT_OR_RETURN(pMQI != NULL, NV_ERR_INVALID_ARGUMENT); + + pRpc = initRpcObject(pGpu); + if (pRpc == NULL) { NV_PRINTF(LEVEL_ERROR, "initRpcObject failed\n"); return NV_ERR_INSUFFICIENT_RESOURCES; } - OBJRPC *pRpc = pKernelGsp->pRpc; + pRpc->pMessageQueueInfo = pMQI; portMemSet(&pRpc->rpcHistory, 0, sizeof(pRpc->rpcHistory)); pRpc->rpcHistoryCurrent = RPC_HISTORY_DEPTH - 1; + pRpc->message_buffer = (NvU32 *)pRpc->pMessageQueueInfo->pRpcMsgBuf; + pRpc->maxRpcSize = GSP_MSG_QUEUE_RPC_SIZE_MAX; - pRpc->pMessageQueueInfo = NULL; + rpcSendMessage_FNPTR(pRpc) = _kgspRpcSendMessage; + rpcRecvPoll_FNPTR(pRpc) = _kgspRpcRecvPoll; - nvStatus = GspMsgQueueInit(pGpu, &pRpc->pMessageQueueInfo); - if (nvStatus != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "GspMsgQueueInit failed\n"); - _kgspFreeRpcInfrastructure(pGpu, pKernelGsp); - return nvStatus; - } - - pRpc->messageQueuePhysMem = pRpc->pMessageQueueInfo->sharedMemPA; - pRpc->message_buffer = (NvU32 *)pRpc->pMessageQueueInfo->pRpcMsgBuf; - pRpc->maxRpcSize = GSP_MSG_QUEUE_RPC_SIZE_MAX; - pRpc->init_msg_buf = (NvU32 *)pRpc->pMessageQueueInfo->pInitMsgBuf; - pRpc->init_msg_buf_pa = pRpc->pMessageQueueInfo->initMsgBufPA; - - portMemSet(&pKernelGsp->gspStaticInfo, 0, - sizeof(pKernelGsp->gspStaticInfo)); - - rpcSendMessage_FNPTR(pKernelGsp->pRpc) = _kgspRpcSendMessage; - rpcRecvPoll_FNPTR(pKernelGsp->pRpc) = _kgspRpcRecvPoll; + *ppRpc = pRpc; return NV_OK; } @@ -1317,11 +1392,17 @@ _kgspFreeRpcInfrastructure { if (pKernelGsp->pRpc != NULL) { - GspMsgQueueCleanup(&pKernelGsp->pRpc->pMessageQueueInfo); rpcDestroy(pGpu, pKernelGsp->pRpc); portMemFree(pKernelGsp->pRpc); pKernelGsp->pRpc = NULL; } + if (pKernelGsp->pLocklessRpc != NULL) + { + rpcDestroy(pGpu, pKernelGsp->pLocklessRpc); + portMemFree(pKernelGsp->pLocklessRpc); + pKernelGsp->pLocklessRpc = NULL; + } + GspMsgQueuesCleanup(&pKernelGsp->pMQCollection); } /*! @@ -1640,6 +1721,7 @@ _kgspInitLibosLoggingStructures NV_STATUS nvStatus = NV_OK; NvU8 idx; + NvU64 flags = MEMDESC_FLAGS_NONE; libosLogCreate(&pKernelGsp->logDecode); @@ -1659,7 +1741,7 @@ _kgspInitLibosLoggingStructures logInitValues[idx].size, RM_PAGE_SIZE, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, - MEMDESC_FLAGS_NONE), + flags), error_cleanup); NV_ASSERT_OK_OR_GOTO(nvStatus, @@ -1829,19 +1911,23 @@ kgspConstructEngine_IMPL kgspConfigureFalcon_HAL(pGpu, pKernelGsp); + // Init RPC objects used to communicate with GSP. nvStatus = _kgspInitRpcInfrastructure(pGpu, pKernelGsp); if (nvStatus != NV_OK) { NV_PRINTF(LEVEL_ERROR, "init RPC infrastructure failed\n"); - return nvStatus; + goto done; } + // Clear out the gspStaticInfo. We will populate this once GSP-RM is up. + portMemSet(&pKernelGsp->gspStaticInfo, 0, + sizeof(pKernelGsp->gspStaticInfo)); + nvStatus = kgspAllocBootArgs_HAL(pGpu, pKernelGsp); if (nvStatus != NV_OK) { NV_PRINTF(LEVEL_ERROR, "boot arg alloc failed: 0x%x\n", nvStatus); - _kgspFreeRpcInfrastructure(pGpu, pKernelGsp); - return nvStatus; + goto done; } if (IS_SIMULATION(pGpu)) @@ -1850,13 +1936,18 @@ kgspConstructEngine_IMPL if (nvStatus != NV_OK) { NV_PRINTF(LEVEL_ERROR, "sim access buffer alloc failed: 0x%x\n", nvStatus); - kgspFreeBootArgs_HAL(pGpu, pKernelGsp); - _kgspFreeRpcInfrastructure(pGpu, pKernelGsp); - return nvStatus; + goto done; } } - return NV_OK; +done: + if (nvStatus != NV_OK) + { + kgspFreeBootArgs_HAL(pGpu, pKernelGsp); + _kgspFreeRpcInfrastructure(pGpu, pKernelGsp); + } + + return nvStatus; } /*! @@ -1987,7 +2078,7 @@ kgspInitRm_IMPL } // execute Booter Unload if needed to reset from unclean shutdown - kgspExecuteBooterUnloadIfNeeded_HAL(pGpu, pKernelGsp); + kgspExecuteBooterUnloadIfNeeded_HAL(pGpu, pKernelGsp, 0); } // Prepare boot binary image. @@ -2170,7 +2261,7 @@ kgspUnloadRm_IMPL else { // After instructing GSP-RM to unload itself, run Booter Unload to teardown WPR2 - status = kgspExecuteBooterUnloadIfNeeded_HAL(pGpu, pKernelGsp); + status = kgspExecuteBooterUnloadIfNeeded_HAL(pGpu, pKernelGsp, 0); } if (rpcStatus != NV_OK) @@ -2210,6 +2301,7 @@ kgspDestruct_IMPL _kgspFreeRpcInfrastructure(pGpu, pKernelGsp); _kgspFreeBootBinaryImage(pGpu, pKernelGsp); _kgspFreeSimAccessBuffer(pGpu, pKernelGsp); + kgspFreeSuspendResumeData_HAL(pGpu, pKernelGsp); } /*! @@ -2262,14 +2354,24 @@ kgspPopulateGspRmInitArgs_IMPL { GSP_ARGUMENTS_CACHED *pGspArgs = pKernelGsp->pGspArgumentsCached; MESSAGE_QUEUE_INIT_ARGUMENTS *pMQInitArgs = &pGspArgs->messageQueueInitArguments; - MESSAGE_QUEUE_INFO *pMQI = pKernelGsp->pRpc->pMessageQueueInfo; + MESSAGE_QUEUE_COLLECTION *pMQCollection = pKernelGsp->pMQCollection; GSP_SR_INIT_ARGUMENTS *pSrInitArgs = &pGspArgs->srInitArguments; // Setup the message queue arguments - pMQInitArgs->sharedMemPhysAddr = pKernelGsp->pRpc->messageQueuePhysMem; - pMQInitArgs->pageTableEntryCount = pMQI->pageTableEntryCount; - pMQInitArgs->cmdQueueOffset = pMQI->pageTableSize; - pMQInitArgs->statQueueOffset = pMQInitArgs->cmdQueueOffset + pMQI->commandQueueSize; + pMQInitArgs->sharedMemPhysAddr = pMQCollection->sharedMemPA; + pMQInitArgs->pageTableEntryCount = pMQCollection->pageTableEntryCount; + pMQInitArgs->cmdQueueOffset = pMQCollection->pageTableSize; + pMQInitArgs->statQueueOffset = pMQInitArgs->cmdQueueOffset + pMQCollection->rpcQueues[RPC_TASK_RM_QUEUE_IDX].commandQueueSize; + if (pKernelGsp->bIsTaskIsrQueueRequired) + { + pMQInitArgs->locklessCmdQueueOffset = pMQInitArgs->statQueueOffset + pMQCollection->rpcQueues[RPC_TASK_RM_QUEUE_IDX].statusQueueSize; + pMQInitArgs->locklessStatQueueOffset = pMQInitArgs->locklessCmdQueueOffset + pMQCollection->rpcQueues[RPC_TASK_ISR_QUEUE_IDX].commandQueueSize; + } + else + { + pMQInitArgs->locklessCmdQueueOffset = 0; + pMQInitArgs->locklessStatQueueOffset = 0; + } if (pGspInitArgs == NULL) { @@ -2308,6 +2410,7 @@ kgspPrepareBootBinaryImage_IMPL NvU8 *pDesc = NULL; NvP64 pVa = NvP64_NULL; NvP64 pPriv = NvP64_NULL; + NvU64 flags = MEMDESC_FLAGS_NONE; NV_ASSERT_OR_RETURN(pKernelGsp->pGspRmBootUcodeImage == NULL, NV_ERR_INVALID_STATE); NV_ASSERT_OR_RETURN(pKernelGsp->pGspRmBootUcodeDesc == NULL, NV_ERR_INVALID_STATE); @@ -2325,7 +2428,7 @@ kgspPrepareBootBinaryImage_IMPL bufSizeAligned, RM_PAGE_SIZE, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, - MEMDESC_FLAGS_NONE), + flags), fail); NV_ASSERT_OK_OR_GOTO(status, @@ -2411,12 +2514,13 @@ _kgspCreateSignatureMemdesc { NV_STATUS status = NV_OK; NvU8 *pSignatureVa = NULL; + NvU64 flags = MEMDESC_FLAGS_NONE; // NOTE: align to 256 because that's the alignment needed for Booter DMA NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, memdescCreate(&pKernelGsp->pSignatureMemdesc, pGpu, NV_ALIGN_UP(pGspFw->signatureSize, 256), 256, - NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, MEMDESC_FLAGS_NONE)); + NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, flags)); NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, memdescAlloc(pKernelGsp->pSignatureMemdesc), fail_create); @@ -2592,16 +2696,17 @@ _kgspPrepareGspRmBinaryImage pGspFw)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - _kgspCreateRadix3(pGpu, &pKernelGsp->pGspUCodeRadix3Descriptor, + kgspCreateRadix3(pGpu, pKernelGsp, &pKernelGsp->pGspUCodeRadix3Descriptor, NULL, pGspFw->pImageData, pGspFw->imageSize)); return NV_OK; } -static NV_STATUS -_kgspCreateRadix3 +NV_STATUS +kgspCreateRadix3_IMPL ( OBJGPU *pGpu, + KernelGsp *pKernelGsp, MEMORY_DESCRIPTOR **ppMemdescRadix3, MEMORY_DESCRIPTOR *pMemdescData, const void *pData, @@ -2618,6 +2723,7 @@ _kgspCreateRadix3 NvU64 dataOffset = 0; NvU32 i; NV_STATUS status = NV_OK; + NvU64 flags = MEMDESC_FLAGS_KERNEL_MODE; // radix3 working array. struct @@ -2627,8 +2733,8 @@ _kgspCreateRadix3 } radix3[4]; NV_ASSERT_OR_RETURN(ppMemdescRadix3 != NULL, NV_ERR_INVALID_PARAMETER); - NV_ASSERT_OR_ELSE_STR((pMemdescData != NULL) != (pData != NULL), - "Specify pMemdescData or pData, but not both", + NV_ASSERT_OR_ELSE_STR(!((pMemdescData != NULL) && (pData != NULL)), + "Specify pMemdescData or pData, or none, but not both", return NV_ERR_INVALID_PARAMETER); // If the size is not specified, get it from the memory descriptor. @@ -2659,7 +2765,7 @@ _kgspCreateRadix3 ptSize = nPages << LIBOS_MEMORY_REGION_RADIX_PAGE_LOG2; allocSize = ptSize; - if (pData != NULL) + if (pMemdescData == NULL) { // We don't have a separate descriptor for the data. We need PTEs, // so include space for data in the new descriptor. @@ -2672,7 +2778,7 @@ _kgspCreateRadix3 NV_MEMORY_NONCONTIGUOUS, ADDR_SYSMEM, NV_MEMORY_CACHED, - MEMDESC_FLAGS_KERNEL_MODE), + flags), done); NV_ASSERT_OK_OR_GOTO(status, memdescAlloc(*ppMemdescRadix3), error_ret); @@ -2706,10 +2812,10 @@ _kgspCreateRadix3 (RmPhysAddr *)(pRadix3Buf + radix3[i].offset)); // physical address table } + dataOffset = radix3[3].offset; + if (pData != NULL) { - dataOffset = radix3[3].offset; - // Optionally copy data into the radix3 buffer. portMemCopy(pRadix3Buf + dataOffset, size, pData, size); diff --git a/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c b/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c index fd8ff0c7a..bcd357249 100644 --- a/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c +++ b/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c @@ -54,22 +54,28 @@ ct_assert(GSP_MSG_QUEUE_HEADER_SIZE > sizeof(msgqTxHeader) + sizeof(msgqRxHeader)); +static void _gspMsgQueueCleanup(MESSAGE_QUEUE_INFO *pMQI); + static void _getMsgQueueParams ( OBJGPU *pGpu, - MESSAGE_QUEUE_INFO *pMQI + MESSAGE_QUEUE_COLLECTION *pMQCollection ) { + KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); NvLength queueSize; + MESSAGE_QUEUE_INFO *pRmQueueInfo = &pMQCollection->rpcQueues[RPC_TASK_RM_QUEUE_IDX]; + MESSAGE_QUEUE_INFO *pTaskIsrQueueInfo = &pMQCollection->rpcQueues[RPC_TASK_ISR_QUEUE_IDX]; NvU32 numPtes; const NvLength defaultCommandQueueSize = 0x40000; // 256 KB const NvLength defaultStatusQueueSize = 0x40000; // 256 KB NvU32 regStatusQueueSize; + // RmQueue sizes if (IS_SILICON(pGpu)) { - pMQI->commandQueueSize = defaultCommandQueueSize; + pRmQueueInfo->commandQueueSize = defaultCommandQueueSize; } else { @@ -77,7 +83,7 @@ _getMsgQueueParams // Pre-silicon platforms need a large command queue in order to send // the VBIOS image via RPC. // - pMQI->commandQueueSize = defaultCommandQueueSize * 6; + pRmQueueInfo->commandQueueSize = defaultCommandQueueSize * 6; } // Check for status queue size overried @@ -86,18 +92,31 @@ _getMsgQueueParams regStatusQueueSize *= 1024; // to bytes regStatusQueueSize = NV_MAX(GSP_MSG_QUEUE_ELEMENT_SIZE_MAX, regStatusQueueSize); regStatusQueueSize = NV_ALIGN_UP(regStatusQueueSize, 1 << GSP_MSG_QUEUE_ALIGN); - pMQI->statusQueueSize = regStatusQueueSize; + pRmQueueInfo->statusQueueSize = regStatusQueueSize; } else { - pMQI->statusQueueSize = defaultStatusQueueSize; + pRmQueueInfo->statusQueueSize = defaultStatusQueueSize; + } + + // TaskIsrQueue sizes + if (pKernelGsp->bIsTaskIsrQueueRequired) + { + pTaskIsrQueueInfo->commandQueueSize = defaultCommandQueueSize; + pTaskIsrQueueInfo->statusQueueSize = defaultStatusQueueSize; + } + else + { + pTaskIsrQueueInfo->commandQueueSize = 0; + pTaskIsrQueueInfo->statusQueueSize = 0; } // // Calculate the number of entries required to map both queues in addition // to the page table itself. // - queueSize = pMQI->commandQueueSize + pMQI->statusQueueSize; + queueSize = pRmQueueInfo->commandQueueSize + pRmQueueInfo->statusQueueSize + + pTaskIsrQueueInfo->commandQueueSize + pTaskIsrQueueInfo->statusQueueSize; NV_ASSERT((queueSize & RM_PAGE_MASK) == 0); numPtes = (queueSize >> RM_PAGE_SHIFT); @@ -108,124 +127,28 @@ _getMsgQueueParams // Align the page table size to RM_PAGE_SIZE, so that the command queue is // aligned. // - pMQI->pageTableSize = RM_PAGE_ALIGN_UP(numPtes * sizeof(RmPhysAddr)); - pMQI->pageTableEntryCount = numPtes; + pMQCollection->pageTableSize = RM_PAGE_ALIGN_UP(numPtes * sizeof(RmPhysAddr)); + pMQCollection->pageTableEntryCount = numPtes; } -/*! - * GspMsgQueueInit - * - * Initialize the command queue for CPU side. - * Must not be called before portInitialize. - */ -NV_STATUS -GspMsgQueueInit +static NV_STATUS +_gspMsgQueueInit ( - OBJGPU *pGpu, - MESSAGE_QUEUE_INFO **ppMQI + MESSAGE_QUEUE_INFO *pMQI ) { - MESSAGE_QUEUE_INFO *pMQI = NULL; - RmPhysAddr *pPageTbl; - int nRet; - NvP64 pVaKernel; - NvP64 pPrivKernel; - NV_STATUS nvStatus = NV_OK; - NvLength sharedBufSize; - NvLength firstCmdOffset; - NvU32 workAreaSize; - - if (*ppMQI != NULL) - { - NV_PRINTF(LEVEL_ERROR, "GSP message queue was already initialized.\n"); - return NV_ERR_INVALID_STATE; - } - - pMQI = portMemAllocNonPaged(sizeof *pMQI); - if (pMQI == NULL) - { - NV_PRINTF(LEVEL_ERROR, "Error allocating queue info area.\n"); - nvStatus = NV_ERR_NO_MEMORY; - goto done; - } - portMemSet(pMQI, 0, sizeof *pMQI); - - _getMsgQueueParams(pGpu, pMQI); - - sharedBufSize = pMQI->pageTableSize + - pMQI->commandQueueSize + - pMQI->statusQueueSize; - - // - // For now, put all shared queue memory in one block. - // - NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescCreate(&pMQI->pSharedMemDesc, pGpu, sharedBufSize, - RM_PAGE_SIZE, NV_MEMORY_NONCONTIGUOUS, ADDR_SYSMEM, NV_MEMORY_CACHED, - MEMDESC_FLAGS_NONE), - done); - - memdescSetFlag(pMQI->pSharedMemDesc, MEMDESC_FLAGS_KERNEL_MODE, NV_TRUE); - - NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescAlloc(pMQI->pSharedMemDesc), - error_ret); - - // Create kernel mapping for command queue. - NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescMap(pMQI->pSharedMemDesc, 0, sharedBufSize, - NV_TRUE, NV_PROTECT_WRITEABLE, - &pVaKernel, &pPrivKernel), - error_ret); - - memdescSetKernelMapping(pMQI->pSharedMemDesc, pVaKernel); - memdescSetKernelMappingPriv(pMQI->pSharedMemDesc, pPrivKernel); - - if (pVaKernel == NvP64_NULL) - { - NV_PRINTF(LEVEL_ERROR, "Error allocating message queue shared buffer\n"); - nvStatus = NV_ERR_NO_MEMORY; - goto error_ret; - } - - portMemSet((void *)pVaKernel, 0, sharedBufSize); - - pPageTbl = pVaKernel; - - // Shared memory layout. - // - // Each of the following are page aligned: - // Shared memory layout header (includes page table) - // Command queue header - // Command queue entries - // Status queue header - // Status queue entries - memdescGetPhysAddrs(pMQI->pSharedMemDesc, - AT_GPU, // addressTranslation - 0, // offset - RM_PAGE_SIZE, // stride - pMQI->pageTableEntryCount, // count - pPageTbl); // physical address table - - pMQI->pCommandQueue = NvP64_VALUE( - NvP64_PLUS_OFFSET(pVaKernel, pMQI->pageTableSize)); - - pMQI->pStatusQueue = NvP64_VALUE( - NvP64_PLUS_OFFSET(NV_PTR_TO_NvP64(pMQI->pCommandQueue), pMQI->commandQueueSize)); - - NV_ASSERT(NvP64_PLUS_OFFSET(pVaKernel, sharedBufSize) == - NvP64_PLUS_OFFSET(NV_PTR_TO_NvP64(pMQI->pStatusQueue), pMQI->statusQueueSize)); + NvU32 workAreaSize; + NV_STATUS nvStatus = NV_OK; + int nRet; // Allocate work area. workAreaSize = (1 << GSP_MSG_QUEUE_ELEMENT_ALIGN) + GSP_MSG_QUEUE_ELEMENT_SIZE_MAX + msgqGetMetaSize(); pMQI->pWorkArea = portMemAllocNonPaged(workAreaSize); - if (pMQI->pWorkArea == NULL) { NV_PRINTF(LEVEL_ERROR, "Error allocating pWorkArea.\n"); - nvStatus = NV_ERR_NO_MEMORY; - goto error_ret; + return NV_ERR_NO_MEMORY; } portMemSet(pMQI->pWorkArea, 0, workAreaSize); @@ -256,21 +179,165 @@ GspMsgQueueInit goto error_ret; } - NV_PRINTF(LEVEL_INFO, "Created command queue.\n"); - - *ppMQI = pMQI; - pMQI->sharedMemPA = pPageTbl[0]; pMQI->pRpcMsgBuf = &pMQI->pCmdQueueElement->rpc; - firstCmdOffset = pMQI->pageTableSize + GSP_MSG_QUEUE_HEADER_SIZE; - pMQI->pInitMsgBuf = NvP64_PLUS_OFFSET(pVaKernel, firstCmdOffset); - pMQI->initMsgBufPA = pPageTbl[firstCmdOffset >> RM_PAGE_SHIFT] + - (firstCmdOffset & RM_PAGE_MASK); + NV_PRINTF(LEVEL_INFO, "Created command queue.\n"); + return nvStatus; + +error_ret: + _gspMsgQueueCleanup(pMQI); + return nvStatus; +} + +/*! + * GspMsgQueueInit + * + * Initialize the command queues for CPU side. + * Must not be called before portInitialize. + */ +NV_STATUS +GspMsgQueuesInit +( + OBJGPU *pGpu, + MESSAGE_QUEUE_COLLECTION **ppMQCollection +) +{ + KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); + MESSAGE_QUEUE_COLLECTION *pMQCollection = NULL; + MESSAGE_QUEUE_INFO *pRmQueueInfo = NULL; + MESSAGE_QUEUE_INFO *pTaskIsrQueueInfo = NULL; + RmPhysAddr *pPageTbl; + NvP64 pVaKernel; + NvP64 pPrivKernel; + NV_STATUS nvStatus = NV_OK; + NvLength sharedBufSize; + NvP64 lastQueueVa; + NvLength lastQueueSize; + NvU64 flags = MEMDESC_FLAGS_NONE; + + if (*ppMQCollection != NULL) + { + NV_PRINTF(LEVEL_ERROR, "GSP message queue was already initialized.\n"); + return NV_ERR_INVALID_STATE; + } + + pMQCollection = portMemAllocNonPaged(sizeof *pMQCollection); + if (pMQCollection == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Error allocating queue info area.\n"); + nvStatus = NV_ERR_NO_MEMORY; + goto done; + } + portMemSet(pMQCollection, 0, sizeof *pMQCollection); + + _getMsgQueueParams(pGpu, pMQCollection); + + pRmQueueInfo = &pMQCollection->rpcQueues[RPC_TASK_RM_QUEUE_IDX]; + pTaskIsrQueueInfo = &pMQCollection->rpcQueues[RPC_TASK_ISR_QUEUE_IDX]; + + sharedBufSize = pMQCollection->pageTableSize + + pRmQueueInfo->commandQueueSize + + pRmQueueInfo->statusQueueSize + + pTaskIsrQueueInfo->commandQueueSize + + pTaskIsrQueueInfo->statusQueueSize; + + // + // For now, put all shared queue memory in one block. + // + NV_ASSERT_OK_OR_GOTO(nvStatus, + memdescCreate(&pMQCollection->pSharedMemDesc, pGpu, sharedBufSize, + RM_PAGE_SIZE, NV_MEMORY_NONCONTIGUOUS, ADDR_SYSMEM, NV_MEMORY_CACHED, + flags), + done); + + memdescSetFlag(pMQCollection->pSharedMemDesc, MEMDESC_FLAGS_KERNEL_MODE, NV_TRUE); + + NV_ASSERT_OK_OR_GOTO(nvStatus, + memdescAlloc(pMQCollection->pSharedMemDesc), + error_ret); + + // Create kernel mapping for command queue. + NV_ASSERT_OK_OR_GOTO(nvStatus, + memdescMap(pMQCollection->pSharedMemDesc, 0, sharedBufSize, + NV_TRUE, NV_PROTECT_WRITEABLE, + &pVaKernel, &pPrivKernel), + error_ret); + + memdescSetKernelMapping(pMQCollection->pSharedMemDesc, pVaKernel); + memdescSetKernelMappingPriv(pMQCollection->pSharedMemDesc, pPrivKernel); + + if (pVaKernel == NvP64_NULL) + { + NV_PRINTF(LEVEL_ERROR, "Error allocating message queue shared buffer\n"); + nvStatus = NV_ERR_NO_MEMORY; + goto error_ret; + } + + portMemSet((void *)pVaKernel, 0, sharedBufSize); + + pPageTbl = pVaKernel; + + // Shared memory layout. + // + // Each of the following are page aligned: + // Shared memory layout header (includes page table) + // RM Command queue header + // RM Command queue entries + // RM Status queue header + // RM Status queue entries + // TASKISR Command queue header + // TASKISR Command queue entries + // TASKISR Status queue header + // TASKISR Status queue entries + memdescGetPhysAddrs(pMQCollection->pSharedMemDesc, + AT_GPU, // addressTranslation + 0, // offset + RM_PAGE_SIZE, // stride + pMQCollection->pageTableEntryCount, // count + pPageTbl); // physical address table + + pRmQueueInfo->pCommandQueue = NvP64_VALUE( + NvP64_PLUS_OFFSET(pVaKernel, pMQCollection->pageTableSize)); + + pRmQueueInfo->pStatusQueue = NvP64_VALUE( + NvP64_PLUS_OFFSET(NV_PTR_TO_NvP64(pRmQueueInfo->pCommandQueue), pRmQueueInfo->commandQueueSize)); + + lastQueueVa = NV_PTR_TO_NvP64(pRmQueueInfo->pStatusQueue); + lastQueueSize = pRmQueueInfo->statusQueueSize; + + if (pKernelGsp->bIsTaskIsrQueueRequired) + { + pTaskIsrQueueInfo->pCommandQueue = NvP64_VALUE( + NvP64_PLUS_OFFSET(NV_PTR_TO_NvP64(pRmQueueInfo->pStatusQueue), pRmQueueInfo->statusQueueSize)); + + pTaskIsrQueueInfo->pStatusQueue = NvP64_VALUE( + NvP64_PLUS_OFFSET(NV_PTR_TO_NvP64(pTaskIsrQueueInfo->pCommandQueue), pTaskIsrQueueInfo->commandQueueSize)); + + lastQueueVa = NV_PTR_TO_NvP64(pTaskIsrQueueInfo->pStatusQueue); + lastQueueSize = pTaskIsrQueueInfo->statusQueueSize; + } + + // Assert that the last queue offset + size fits into the shared memory. + NV_ASSERT(NvP64_PLUS_OFFSET(pVaKernel, sharedBufSize) == + NvP64_PLUS_OFFSET(lastQueueVa, lastQueueSize)); + + NV_ASSERT_OK_OR_GOTO(nvStatus, _gspMsgQueueInit(pRmQueueInfo), error_ret); + pRmQueueInfo->queueIdx = RPC_TASK_RM_QUEUE_IDX; + + if (pKernelGsp->bIsTaskIsrQueueRequired) + { + NV_ASSERT_OK_OR_GOTO(nvStatus, _gspMsgQueueInit(pTaskIsrQueueInfo), error_ret); + pTaskIsrQueueInfo->queueIdx = RPC_TASK_ISR_QUEUE_IDX; + } + + *ppMQCollection = pMQCollection; + pMQCollection->sharedMemPA = pPageTbl[0]; + done: return nvStatus; error_ret: - GspMsgQueueCleanup(&pMQI); + GspMsgQueuesCleanup(&pMQCollection); return nvStatus; } @@ -341,50 +408,63 @@ NV_STATUS GspStatusQueueInit(OBJGPU *pGpu, MESSAGE_QUEUE_INFO **ppMQI) NV_PRINTF(LEVEL_ERROR, "msgqRxLink failed: %d, nvStatus 0x%08x, retries: %d\n", nRet, nvStatus, nRetries); - GspMsgQueueCleanup(ppMQI); + _gspMsgQueueCleanup(*ppMQI); } return nvStatus; } -void GspMsgQueueCleanup(MESSAGE_QUEUE_INFO **ppMQI) +static void +_gspMsgQueueCleanup(MESSAGE_QUEUE_INFO *pMQI) { - MESSAGE_QUEUE_INFO *pMQI = NULL; - - if ((ppMQI == NULL) || (*ppMQI == NULL)) - return; - - pMQI = *ppMQI; - pMQI->hQueue = NULL; - - if (pMQI->pWorkArea != NULL) + if (pMQI == NULL) { - portMemFree(pMQI->pWorkArea); - pMQI->pWorkArea = NULL; - pMQI->pCmdQueueElement = NULL; - pMQI->pMetaData = NULL; + return; } - if (pMQI->pSharedMemDesc != NULL) + portMemFree(pMQI->pWorkArea); + + pMQI->pWorkArea = NULL; + pMQI->pCmdQueueElement = NULL; + pMQI->pMetaData = NULL; +} + +void GspMsgQueuesCleanup(MESSAGE_QUEUE_COLLECTION **ppMQCollection) +{ + MESSAGE_QUEUE_COLLECTION *pMQCollection = NULL; + MESSAGE_QUEUE_INFO *pRmQueueInfo = NULL; + MESSAGE_QUEUE_INFO *pTaskIsrQueueInfo = NULL; + + if ((ppMQCollection == NULL) || (*ppMQCollection == NULL)) + return; + + pMQCollection = *ppMQCollection; + pRmQueueInfo = &pMQCollection->rpcQueues[RPC_TASK_RM_QUEUE_IDX]; + pTaskIsrQueueInfo = &pMQCollection->rpcQueues[RPC_TASK_ISR_QUEUE_IDX]; + + _gspMsgQueueCleanup(pRmQueueInfo); + _gspMsgQueueCleanup(pTaskIsrQueueInfo); + + if (pMQCollection->pSharedMemDesc != NULL) { - NvP64 pVaKernel = memdescGetKernelMapping(pMQI->pSharedMemDesc); - NvP64 pPrivKernel = memdescGetKernelMappingPriv(pMQI->pSharedMemDesc); + NvP64 pVaKernel = memdescGetKernelMapping(pMQCollection->pSharedMemDesc); + NvP64 pPrivKernel = memdescGetKernelMappingPriv(pMQCollection->pSharedMemDesc); // Destroy kernel mapping for command queue. if (pVaKernel != 0) { - memdescUnmap(pMQI->pSharedMemDesc, NV_TRUE, osGetCurrentProcess(), + memdescUnmap(pMQCollection->pSharedMemDesc, NV_TRUE, osGetCurrentProcess(), pVaKernel, pPrivKernel); } // Free command queue memory. - memdescFree(pMQI->pSharedMemDesc); - memdescDestroy(pMQI->pSharedMemDesc); - pMQI->pSharedMemDesc = NULL; + memdescFree(pMQCollection->pSharedMemDesc); + memdescDestroy(pMQCollection->pSharedMemDesc); + pMQCollection->pSharedMemDesc = NULL; } - portMemFree(pMQI); - *ppMQI = NULL; + portMemFree(pMQCollection); + *ppMQCollection = NULL; } /*! @@ -531,7 +611,7 @@ NV_STATUS GspMsgQueueReceiveStatus(MESSAGE_QUEUE_INFO *pMQI) int i; int nRetries; int nMaxRetries = 3; - int nElements = 1; // Assume record fits in one 256-byte queue element for now. + int nElements = 1; // Assume record fits in one queue element for now. NvU32 uElementSize = 0; NvU32 seqMismatchDiff = NV_U32_MAX; NV_STATUS nvStatus = NV_OK; @@ -540,7 +620,7 @@ NV_STATUS GspMsgQueueReceiveStatus(MESSAGE_QUEUE_INFO *pMQI) { pTgt = (NvU8 *)pMQI->pCmdQueueElement; nvStatus = NV_OK; - nElements = 1; // Assume record fits in one 256-byte queue element for now. + nElements = 1; // Assume record fits in one queue element for now. for (i = 0; i < nElements; i++) { diff --git a/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2_ctrl.c b/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2_ctrl.c index 712d9d6f9..e64575d76 100644 --- a/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2_ctrl.c +++ b/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2_ctrl.c @@ -22,9 +22,84 @@ */ #include "gpu/gpu.h" +#include "nvoc/prelude.h" +#include "nvstatuscodes.h" #include "rmapi/rs_utils.h" #include "gpu/hwpm/profiler_v2.h" #include "ctrl/ctrlb0cc/ctrlb0ccinternal.h" +#include "ctrl/ctrlb0cc/ctrlb0ccprofiler.h" +#include "mem_mgr/mem.h" + +NV_STATUS +profilerBaseCtrlCmdFreePmaStream_IMPL +( + ProfilerBase *pProfiler, + NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS *pParams +) +{ + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(GPU_RES_GET_GPU(pProfiler)); + NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS internalParams; + + portMemSet(&internalParams, 0, sizeof(NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS)); + internalParams.pmaChannelIdx = pParams->pmaChannelIdx; + + return pRmApi->Control(pRmApi, + RES_GET_CLIENT_HANDLE(pProfiler), + RES_GET_HANDLE(pProfiler), + NVB0CC_CTRL_CMD_INTERNAL_FREE_PMA_STREAM, + &internalParams, sizeof(internalParams)); +} + +NV_STATUS +profilerBaseCtrlCmdBindPmResources_IMPL +( + ProfilerBase *pProfiler +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pProfiler); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NvHandle hClient = RES_GET_CLIENT_HANDLE(pProfiler); + NvHandle hObject = RES_GET_HANDLE(pProfiler); + NV_STATUS status = NV_OK; + + status = pRmApi->Control(pRmApi, hClient, hObject, + NVB0CC_CTRL_CMD_INTERNAL_BIND_PM_RESOURCES, + NULL, 0); + return status; +} + +NV_STATUS +profilerBaseCtrlCmdUnbindPmResources_IMPL +( + ProfilerBase *pProfiler +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pProfiler); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NvHandle hClient = RES_GET_CLIENT_HANDLE(pProfiler); + NvHandle hObject = RES_GET_HANDLE(pProfiler); + + return pRmApi->Control(pRmApi, hClient, hObject, + NVB0CC_CTRL_CMD_INTERNAL_UNBIND_PM_RESOURCES, + NULL, 0); +} + +NV_STATUS +profilerBaseCtrlCmdReserveHwpmLegacy_IMPL +( + ProfilerBase *pProfiler, + NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pProfiler); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NvHandle hClient = RES_GET_CLIENT_HANDLE(pProfiler); + NvHandle hObject = RES_GET_HANDLE(pProfiler); + + return pRmApi->Control(pRmApi, hClient, hObject, + NVB0CC_CTRL_CMD_INTERNAL_RESERVE_HWPM_LEGACY, + pParams, sizeof(*pParams)); +} NV_STATUS profilerBaseCtrlCmdAllocPmaStream_IMPL @@ -41,39 +116,44 @@ profilerBaseCtrlCmdAllocPmaStream_IMPL NvHandle hObject = RES_GET_HANDLE(pProfiler); NvBool bMemPmaBufferRegistered = NV_FALSE; NvBool bMemPmaBytesAvailableRegistered = NV_FALSE; - + NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS internalParams; // // REGISTER MEMDESCs TO GSP // These are no-op with BareMetal/No GSP // - status = memdescRegisterToGSP(pGpu, hClient, hParent, pParams->hMemPmaBuffer); - if (status != NV_OK) - { - goto fail; - } + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + memdescRegisterToGSP(pGpu, hClient, hParent, pParams->hMemPmaBuffer), + fail); bMemPmaBufferRegistered = NV_TRUE; - status = memdescRegisterToGSP(pGpu, hClient, hParent, pParams->hMemPmaBytesAvailable); - if (status != NV_OK) - { - goto fail; - } + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + memdescRegisterToGSP(pGpu, hClient, hParent, pParams->hMemPmaBytesAvailable), + fail); bMemPmaBytesAvailableRegistered = NV_TRUE; - // - // With BareMetal/No GSP: this control is a direct call to - // profilerBaseCtrlCmdInternalReleaseHwpmLegacy_IMPL - // - status = pRmApi->Control(pRmApi, - hClient, - hObject, - NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM, - pParams, sizeof(*pParams)); - if (status != NV_OK) - { - goto fail; - } + portMemSet(&internalParams, 0, sizeof(NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS)); + internalParams.hMemPmaBuffer = pParams->hMemPmaBuffer; + internalParams.pmaBufferOffset = pParams->pmaBufferOffset; + internalParams.pmaBufferSize = pParams->pmaBufferSize; + internalParams.hMemPmaBytesAvailable = pParams->hMemPmaBytesAvailable; + internalParams.pmaBytesAvailableOffset = pParams->pmaBytesAvailableOffset; + internalParams.ctxsw = pParams->ctxsw; + internalParams.pmaChannelIdx = pParams->pmaChannelIdx; + internalParams.pmaBufferVA = pParams->pmaBufferVA; + internalParams.bInputPmaChIdx = NV_FALSE; + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + pRmApi->Control(pRmApi, + hClient, + hObject, + NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM, + &internalParams, sizeof(internalParams)), fail); + + pParams->pmaChannelIdx = internalParams.pmaChannelIdx; + + // Copy output params to external struct. + pParams->pmaBufferVA = internalParams.pmaBufferVA; + return status; fail: @@ -91,3 +171,4 @@ fail: return status; } + diff --git a/src/nvidia/src/kernel/gpu/intr/arch/ampere/intr_cpu_ga102.c b/src/nvidia/src/kernel/gpu/intr/arch/ampere/intr_cpu_ga102.c index 4e2ad3fc4..dc5111da6 100644 --- a/src/nvidia/src/kernel/gpu/intr/arch/ampere/intr_cpu_ga102.c +++ b/src/nvidia/src/kernel/gpu/intr/arch/ampere/intr_cpu_ga102.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -42,6 +42,12 @@ intrReadRegTopEnSet_GA102 THREAD_STATE_NODE *pThreadState ) { + // SW assumptions that there are two top-levels. + ct_assert(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1 <= 2); + if (regIndex >= NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1) + { + return 0x0; + } return GPU_VREG_RD32_EX(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET(regIndex), pThreadState); @@ -57,6 +63,12 @@ intrWriteRegTopEnSet_GA102 THREAD_STATE_NODE *pThreadState ) { + // SW assumptions that there are two top-levels. + ct_assert(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1 <= 2); + if (regIndex >= NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1) + { + return; + } GPU_VREG_WR32_EX(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET(regIndex), value, @@ -73,6 +85,12 @@ intrWriteRegTopEnClear_GA102 THREAD_STATE_NODE *pThreadState ) { + // SW assumptions that there are two top-levels. + ct_assert(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR__SIZE_1 <= 2); + if (regIndex >= NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR__SIZE_1) + { + return; + } GPU_VREG_WR32_EX(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR(regIndex), value, diff --git a/src/nvidia/src/kernel/gpu/intr/arch/ampere/intr_ga100.c b/src/nvidia/src/kernel/gpu/intr/arch/ampere/intr_ga100.c index 6eb9c7a2e..af187a198 100644 --- a/src/nvidia/src/kernel/gpu/intr/arch/ampere/intr_ga100.c +++ b/src/nvidia/src/kernel/gpu/intr/arch/ampere/intr_ga100.c @@ -59,6 +59,7 @@ intrGetUvmSharedLeafEnDisableMask_GA100 NvU32 intrVectorNonReplayableFault; NvU32 intrVectorTimerSwrl = NV_INTR_VECTOR_INVALID; NvU64 mask = 0; + NV2080_INTR_CATEGORY_SUBTREE_MAP uvmShared; // GSP RM services both MMU non-replayable fault and FIFO interrupts with // vgpu plugin offload enabled. Otherwise, GSP RM only services FIFO interrupts @@ -83,25 +84,30 @@ intrGetUvmSharedLeafEnDisableMask_GA100 NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(intrVectorTimerSwrl)); } + NV_ASSERT_OK(intrGetSubtreeRange(pIntr, + NV2080_INTR_CATEGORY_UVM_SHARED, + &uvmShared)); // - // Compile-time ascertain that we only have 1 client subtree (we assume - // this since we cache only 64 bits). + // Ascertain that we only have 1 client subtree (we assume this since we + // cache only 64 bits). // - ct_assert(NV_CPU_INTR_UVM_SHARED_SUBTREE_START == NV_CPU_INTR_UVM_SHARED_SUBTREE_LAST); + NV_ASSERT(uvmShared.subtreeStart == uvmShared.subtreeEnd); // - // Compile-time ascertain that we only have 2 subtrees as this is what we currently support - // by only caching 64 bits + // Ascertain that we only have 2 subtrees as this is what we currently + // support by only caching 64 bits // - ct_assert((NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(NV_CPU_INTR_UVM_SHARED_SUBTREE_LAST) - 1) == - NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(NV_CPU_INTR_UVM_SHARED_SUBTREE_START)); + NV_ASSERT( + (NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(uvmShared.subtreeEnd) - 1) == + NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(uvmShared.subtreeStart)); // On GSP we service non replayable faults in the bottom half, so we shouldn't mask them if (intrVectorNonReplayableFault != NV_INTR_VECTOR_INVALID) { // Ascertain that it's in the first leaf - NV_ASSERT(NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(intrVectorNonReplayableFault) == - NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(NV_CPU_INTR_UVM_SHARED_SUBTREE_START)); + NV_ASSERT( + NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(intrVectorNonReplayableFault) == + NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(uvmShared.subtreeStart)); mask |= NVBIT32(NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(intrVectorNonReplayableFault)); } @@ -109,8 +115,9 @@ intrGetUvmSharedLeafEnDisableMask_GA100 if (intrVectorTimerSwrl != NV_INTR_VECTOR_INVALID) { // Ascertain that it's in the first leaf - NV_ASSERT(NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(intrVectorTimerSwrl) == - NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(NV_CPU_INTR_UVM_SHARED_SUBTREE_START)); + NV_ASSERT( + NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(intrVectorTimerSwrl) == + NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(uvmShared.subtreeStart)); mask |= NVBIT32(NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(intrVectorTimerSwrl)); } diff --git a/src/nvidia/src/kernel/gpu/intr/arch/hopper/intr_gh100.c b/src/nvidia/src/kernel/gpu/intr/arch/hopper/intr_gh100.c index 7b4a8fc28..9267b9c55 100644 --- a/src/nvidia/src/kernel/gpu/intr/arch/hopper/intr_gh100.c +++ b/src/nvidia/src/kernel/gpu/intr/arch/hopper/intr_gh100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -31,32 +31,51 @@ // Compile time asserts to make sure we don't write beyond the leaf register array -ct_assert(NV_CPU_INTR_STALL_SUBTREE_START < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__SIZE_1); -ct_assert(NV_CPU_INTR_STALL_SUBTREE_LAST < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__SIZE_1); -ct_assert(NV_CPU_INTR_STALL_SUBTREE_START < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET__SIZE_1); -ct_assert(NV_CPU_INTR_STALL_SUBTREE_LAST < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET__SIZE_1); -ct_assert(NV_CPU_INTR_STALL_SUBTREE_START < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__SIZE_1); -ct_assert(NV_CPU_INTR_STALL_SUBTREE_LAST < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__SIZE_1); - ct_assert(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__SIZE_1 == NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET__SIZE_1); ct_assert(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__SIZE_1 == NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__SIZE_1); -/*! - * @brief Gets the stall subtree end index - */ -NvU32 -intrGetStallSubtreeLast_GH100(OBJGPU *pGpu, Intr *pIntr) + +NV_STATUS +intrInitSubtreeMap_GH100 +( + OBJGPU *pGpu, + Intr *pIntr +) { - if (pGpu->getProperty(pGpu, PDB_PROP_GPU_SWRL_GRANULAR_LOCKING)) - { - return NV_CPU_INTR_STALL_SUBTREE_LAST_SWRL; - } - else - { - return NV_CPU_INTR_STALL_SUBTREE_LAST; - } + NV2080_INTR_CATEGORY_SUBTREE_MAP *pCategoryEngine = + &pIntr->subtreeMap[NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE]; + pCategoryEngine->subtreeStart = NV_CPU_INTR_STALL_SUBTREE_START; + pCategoryEngine->subtreeEnd = NV_CPU_INTR_STALL_SUBTREE_START; + + NV2080_INTR_CATEGORY_SUBTREE_MAP *pCategoryEngineNotification = + &pIntr->subtreeMap[NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION]; + pCategoryEngineNotification->subtreeStart = NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(0); + pCategoryEngineNotification->subtreeEnd = NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(0); + + NV2080_INTR_CATEGORY_SUBTREE_MAP *pCategoryRunlistLocked = + &pIntr->subtreeMap[NV2080_INTR_CATEGORY_RUNLIST]; + pCategoryRunlistLocked->subtreeStart = NV_CPU_INTR_STALL_SUBTREE_LAST_SWRL; + pCategoryRunlistLocked->subtreeEnd = NV_CPU_INTR_STALL_SUBTREE_LAST_SWRL; + + NV2080_INTR_CATEGORY_SUBTREE_MAP *pCategoryRunlistNotification = + &pIntr->subtreeMap[NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION]; + pCategoryRunlistNotification->subtreeStart = NV_CPU_INTR_STALL_SUBTREE_LAST; + pCategoryRunlistNotification->subtreeEnd = NV_CPU_INTR_STALL_SUBTREE_LAST; + + NV2080_INTR_CATEGORY_SUBTREE_MAP *pCategoryUvmOwned = + &pIntr->subtreeMap[NV2080_INTR_CATEGORY_UVM_OWNED]; + pCategoryUvmOwned->subtreeStart = NV_CPU_INTR_UVM_SUBTREE_START; + pCategoryUvmOwned->subtreeEnd = NV_CPU_INTR_UVM_SUBTREE_LAST; + + NV2080_INTR_CATEGORY_SUBTREE_MAP *pCategoryUvmShared = + &pIntr->subtreeMap[NV2080_INTR_CATEGORY_UVM_SHARED]; + pCategoryUvmShared->subtreeStart = NV_CPU_INTR_UVM_SHARED_SUBTREE_START; + pCategoryUvmShared->subtreeEnd = NV_CPU_INTR_UVM_SHARED_SUBTREE_LAST; + + return NV_OK; } + /*! * @brief Gets the number of leaf registers used */ @@ -76,14 +95,15 @@ intrGetLeafSize_GH100(OBJGPU *pGpu, Intr *pIntr) return NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__SIZE_1; } -/*! - * @brief Gets the mask of INTR_TOP that covers nonstall interrupts - */ -NvU32 -intrGetIntrTopNonStallMask_GH100(OBJGPU *pGpu, Intr *pIntr) -{ - NvU32 nonStallMask; +NvU64 +intrGetIntrTopNonStallMask_GH100 +( + OBJGPU *pGpu, + Intr *pIntr +) +{ + // TODO Bug 3823562 Remove all these asserts // Compile-time assert against the highest set bit that will be returned #define NV_CPU_INTR_NOSTALL_SUBTREE_HIGHEST NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(5) @@ -91,16 +111,23 @@ intrGetIntrTopNonStallMask_GH100(OBJGPU *pGpu, Intr *pIntr) ct_assert(NV_CPU_INTR_NOSTALL_SUBTREE_HIGHEST < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET__SIZE_1); ct_assert(NV_CPU_INTR_NOSTALL_SUBTREE_HIGHEST < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__SIZE_1); - nonStallMask = NVBIT32(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(0)); + + NvU64 mask = 0; + mask |= intrGetIntrTopCategoryMask(pIntr, + NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION); if (pGpu->getProperty(pGpu, PDB_PROP_GPU_SWRL_GRANULAR_LOCKING)) { - nonStallMask |= NVBIT32(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(5)); + mask |= intrGetIntrTopCategoryMask(pIntr, + NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION); } - return nonStallMask; + // Sanity check that Intr.subtreeMap is initialized + NV_ASSERT(mask != 0); + return mask; } + /*! * @brief Sanity check that the given stall engine interrupt vector is in the right tree * diff --git a/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_cpu_tu102.c b/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_cpu_tu102.c index 40fabfec1..ab0cb2ee3 100644 --- a/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_cpu_tu102.c +++ b/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_cpu_tu102.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -70,6 +70,12 @@ intrReadRegTopEnSet_TU102 THREAD_STATE_NODE *pThreadState ) { + // SW assumptions that there are two top-levels. + ct_assert(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1 <= 2); + if (regIndex >= NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1) + { + return 0x0; + } return GPU_VREG_RD32_EX(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET(regIndex), pThreadState); @@ -84,6 +90,12 @@ intrReadRegTop_TU102 THREAD_STATE_NODE *pThreadState ) { + // SW assumptions that there are two top-levels. + ct_assert(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP__SIZE_1 <= 2); + if (regIndex >= NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP__SIZE_1) + { + return 0x0; + } return GPU_VREG_RD32_EX(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP(regIndex), pThreadState); @@ -147,6 +159,12 @@ intrWriteRegTopEnSet_TU102 THREAD_STATE_NODE *pThreadState ) { + // SW assumptions that there are two top-levels. + ct_assert(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1 <= 2); + if (regIndex >= NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1) + { + return; + } GPU_VREG_WR32_EX(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET(regIndex), value, @@ -163,6 +181,12 @@ intrWriteRegTopEnClear_TU102 THREAD_STATE_NODE *pThreadState ) { + // SW assumptions that there are two top-levels. + ct_assert(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR__SIZE_1 <= 2); + if (regIndex >= NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR__SIZE_1) + { + return; + } GPU_VREG_WR32_EX(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR(regIndex), value, diff --git a/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_nonstall_tu102.c b/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_nonstall_tu102.c index 379866364..e3c54231a 100644 --- a/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_nonstall_tu102.c +++ b/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_nonstall_tu102.c @@ -35,21 +35,19 @@ #include "published/turing/tu102/dev_vm.h" -/*! - * @brief Get the current non-stall interrupt enable status - */ + +/*! Get the current non-stall interrupt enable status. */ NvU32 intrGetNonStallEnable_TU102 ( - OBJGPU *pGpu, - Intr *pIntr, + OBJGPU *pGpu, + Intr *pIntr, THREAD_STATE_NODE *pThreadState ) { - NvU32 i; - NvU32 val; - NvU32 nonStallMask; - + NvU64 nonStallMask; + NvU32 maskLo; + NvU32 maskHi; NvU32 isNonStallEnabled = 0; if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu)) @@ -62,51 +60,40 @@ intrGetNonStallEnable_TU102 return INTERRUPT_TYPE_DISABLED; } - // - // We're doing an optimization below to read the TOP_EN_CLEAR register once - // after the for() loop that loops over the subtrees. It assumes that we - // only have one single top level enable register. HW has support for 2 top - // level registers, but until we get to using the second top level register, - // there's no need for us to write code that uses it (it should be a long - // time away, anyway). Use compile-time asserts to catch that this - // assumption has not changed. - // - ct_assert(sizeof(nonStallMask) == sizeof(NvU32)); - - val = intrReadRegTopEnSet_HAL(pGpu, pIntr, 0, pThreadState); - nonStallMask = intrGetIntrTopNonStallMask_HAL(pGpu, pIntr); - FOR_EACH_INDEX_IN_MASK(32, i, nonStallMask) - { - if (val & NVBIT(NV_CTRL_INTR_SUBTREE_TO_TOP_BIT(i))) + maskLo = NvU64_LO32(nonStallMask); + maskHi = NvU64_HI32(nonStallMask); + + // + // We rely on boolean operator short-circuiting here to avoid reading a + // TopEnSet register if not strictly necessary. + // + if ((maskLo != 0 && + (maskLo & intrReadRegTopEnSet_HAL(pGpu, pIntr, 0, pThreadState)) != 0) + || + (maskHi != 0 && + (maskHi & intrReadRegTopEnSet_HAL(pGpu, pIntr, 1, pThreadState)) != 0)) { // - // If any top-level subtree corresponding to non-stall interrupts - // is enabled, return that non-stall interrupts are enabled. We - // only support enabling or disabling all non-stall interrupts at - // once, not a subset. - // Note that INTERRUPT_TYPE_MULTI basically means that all kinds - // of non-stall interrupts are enabled. The legacy pre-Pascal code - // had support to only enable software-triggerable interrupts or - // hardware-triggerable interrupts or both. We're just continuing - // to the same enum, but the naming of MULTI in the new interrupt - // tree warrants some explanation, hence the detailed comment. + // If any top-level subtree corresponding to non-stall interrupts is + // enabled, return that non-stall interrupts are enabled. We only + // support enabling or disabling all non-stall interrupts at once, not a + // subset. + // Note that INTERRUPT_TYPE_MULTI basically means that all kinds of + // non-stall interrupts are enabled. The legacy pre-Pascal code had + // support to only enable software-triggerable interrupts or + // hardware-triggerable interrupts or both. We're just continuing to the + // same enum, but the naming of MULTI in the new interrupt tree warrants + // some explanation, hence the detailed comment. // return INTERRUPT_TYPE_MULTI; } - } - FOR_EACH_INDEX_IN_MASK_END; return INTERRUPT_TYPE_DISABLED; } -/*! - * @brief Enable all nonstall interrupts in dev_ctrl at top level - * - * @param[in] pGpu OBJGPU pointer - * @param[in] pIntr Intr pointer - * @param[in] pThreadState thread state node pointer - */ + +/*! Enable all nonstall interrupts in dev_ctrl at top level. */ void intrEnableTopNonstall_TU102 ( @@ -115,39 +102,27 @@ intrEnableTopNonstall_TU102 THREAD_STATE_NODE *pThreadState ) { - NvU32 i; - NvU32 val = 0; - NvU32 nonStallMask; - - // - // We're doing an optimization below to write the TOP_EN_CLEAR register once - // after the for() loop that loops over the subtrees. It assumes that we - // only have one single top level enable register. HW has support for 2 top - // level registers, but until we get to using the second top level register, - // there's no need for us to write code that uses it (it should be a long - // time away, anyway). Use compile-time asserts to catch that this - // assumption has not changed. - // - ct_assert(sizeof(nonStallMask) == sizeof(NvU32)); + NvU64 nonStallMask; nonStallMask = intrGetIntrTopNonStallMask_HAL(pGpu, pIntr); - FOR_EACH_INDEX_IN_MASK(32, i, nonStallMask) - { - val |= (NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE_ENABLE << (NV_CTRL_INTR_SUBTREE_TO_TOP_BIT(i))); - } - FOR_EACH_INDEX_IN_MASK_END; - // This optimization of one single register write - intrWriteRegTopEnSet_HAL(pGpu, pIntr, NV_CTRL_INTR_SUBTREE_TO_TOP_IDX(0), val, pThreadState); + if (NvU64_LO32(nonStallMask) != 0) + { + intrWriteRegTopEnSet_HAL(pGpu, pIntr, + 0, + NvU64_LO32(nonStallMask), + pThreadState); + } + if (NvU64_HI32(nonStallMask) != 0) + { + intrWriteRegTopEnSet_HAL(pGpu, pIntr, + 1, + NvU64_HI32(nonStallMask), + pThreadState); + } } -/*! - * @brief Disable all nonstall interrupts in dev_ctrl at top level - * - * @param[in] pGpu OBJGPU pointer - * @param[in] pIntr Intr pointer - * @param[in] pThreadState thread state node pointer - */ +/*! Disable all nonstall interrupts in dev_ctrl at top level. */ void intrDisableTopNonstall_TU102 ( @@ -156,29 +131,24 @@ intrDisableTopNonstall_TU102 THREAD_STATE_NODE *pThreadState ) { - NvU32 i; - NvU32 val = 0; - NvU32 nonStallMask; - - // - // We're doing an optimization below to write the TOP_EN_CLEAR register once - // after the for() loop that loops over the subtrees. It assumes that we - // only have one single top level enable register. HW has support for 2 top - // level registers, but until we get to using the second top level register, - // there's no need for us to write code that uses it (it should be a long - // time away, anyway). Use compile-time asserts to catch that this - // assumption has not changed. - // - ct_assert(sizeof(nonStallMask) == sizeof(NvU32)); + NvU64 nonStallMask; nonStallMask = intrGetIntrTopNonStallMask_HAL(pGpu, pIntr); - FOR_EACH_INDEX_IN_MASK(32, i, nonStallMask) - { - val |= (NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE_DISABLE << (NV_CTRL_INTR_SUBTREE_TO_TOP_BIT(i))); - } - FOR_EACH_INDEX_IN_MASK_END; - intrWriteRegTopEnClear_HAL(pGpu, pIntr, NV_CTRL_INTR_SUBTREE_TO_TOP_IDX(0), val, pThreadState); + if (NvU64_LO32(nonStallMask) != 0) + { + intrWriteRegTopEnClear_HAL(pGpu, pIntr, + 0, + NvU64_LO32(nonStallMask), + pThreadState); + } + if (NvU64_HI32(nonStallMask) != 0) + { + intrWriteRegTopEnClear_HAL(pGpu, pIntr, + 1, + NvU64_HI32(nonStallMask), + pThreadState); + } } void @@ -259,9 +229,10 @@ intrGetPendingNonStall_TU102 NV_ASSERT_OK_OR_RETURN(intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable, &intrTableSz)); - FOR_EACH_INDEX_IN_MASK(32, i, intrGetIntrTopNonStallMask_HAL(pGpu, pIntr)) + FOR_EACH_INDEX_IN_MASK(64, i, intrGetIntrTopNonStallMask_HAL(pGpu, pIntr)) { j = NV_CTRL_INTR_SUBTREE_TO_TOP_IDX(i); + // TODO Bug 3823562: optimize this and don't read on every loop pending = intrReadRegTop_HAL(pGpu, pIntr, j, pThreadState); if ((pending & (NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE_INTR_PENDING << NV_CTRL_INTR_SUBTREE_TO_TOP_BIT(i))) == 0) @@ -453,9 +424,10 @@ intrServiceNonStall_TU102 return vgpuServiceNonStall(pGpu, pEngines); } - FOR_EACH_INDEX_IN_MASK(32, i, intrGetIntrTopNonStallMask_HAL(pGpu, pIntr)) + FOR_EACH_INDEX_IN_MASK(64, i, intrGetIntrTopNonStallMask_HAL(pGpu, pIntr)) { NvU32 j = NV_CTRL_INTR_SUBTREE_TO_TOP_IDX(i); + // TODO Bug 3823562: optimize this and don't read on every loop pending = intrReadRegTop_HAL(pGpu, pIntr, j, pThreadState); if ((pending & (NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE_INTR_PENDING << NV_CTRL_INTR_SUBTREE_TO_TOP_BIT(i))) == 0) diff --git a/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_sriov_tu102.c b/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_sriov_tu102.c index c5783e898..45ee0464d 100644 --- a/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_sriov_tu102.c +++ b/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_sriov_tu102.c @@ -33,47 +33,6 @@ // Turing HAL routines required for hypervisor/guest support // -/*! - * @brief Enables virtual interrupts to be sent from a virtual function with - * the specified GFID. - * - * @param[in] pGpu OBJGPU pointer - * @param[in] pIntr Intr pointer - * @param[in] gfid GFID assigned to the virtual function - */ -NV_STATUS -intrEnableVirtualIntrLeaf_TU102 -( - OBJGPU *pGpu, - Intr *pIntr, - NvU32 gfid -) -{ - GFID_ALLOC_STATUS gfidState; - NvU32 reg = gfid / (DRF_SIZE(NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET_VALUE)); - NvU32 bit = gfid % (DRF_SIZE(NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET_VALUE)); - - NV_ASSERT_OK_OR_RETURN(gpuGetGfidState(pGpu, gfid, &gfidState)); - if (gfidState == GFID_FREE) - { - NV_PRINTF(LEVEL_ERROR, "Invalid GFID 0x%x\n", gfid); - DBG_BREAKPOINT(); - return NV_ERR_INVALID_ARGUMENT; - } - - if (reg >= NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET__SIZE_1) - { - NV_PRINTF(LEVEL_ERROR, "Computed register index exceeds valid available " - "range of NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET. reg idx = 0x%x\n", reg); - DBG_BREAKPOINT(); - return NV_ERR_INVALID_ARGUMENT; - } - - GPU_REG_WR32(pGpu, NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET(reg), - (NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET_VECTOR_ENABLE << bit)); - return NV_OK; -} - /*! * @brief Services virtual interrupts, i.e. interrupts triggered by PRIV_DOORBELL * writes from virtual functions diff --git a/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_tu102.c b/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_tu102.c index 36742ebe9..37ffb8c1c 100644 --- a/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_tu102.c +++ b/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_tu102.c @@ -183,6 +183,7 @@ intrStateUnload_TU102 // Disable all interrupts since we're unloading intrWriteRegTopEnClear_HAL(pGpu, pIntr, 0, 0xFFFFFFFF, NULL); + intrWriteRegTopEnClear_HAL(pGpu, pIntr, 1, 0xFFFFFFFF, NULL); _intrClearLeafEnables_TU102(pGpu, pIntr); @@ -203,39 +204,45 @@ intrCacheIntrFields_TU102 ) { NV_STATUS status = NV_OK; - NvU32 leafEnHi, leafEnLo; - NvU32 uvmSharedLeafIdxStart = NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(NV_CPU_INTR_UVM_SHARED_SUBTREE_START); - NvU32 uvmSharedLeafIdxEnd = NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(NV_CPU_INTR_UVM_SHARED_SUBTREE_LAST); - NvU32 stallSubtreeLast = intrGetStallSubtreeLast_HAL(pGpu, pIntr); - NvU32 i; - // - // Compile time assert to make sure we have only one client shared subtree. - // The below code assumes that. - // - ct_assert(NV_CPU_INTR_UVM_SHARED_SUBTREE_START == NV_CPU_INTR_UVM_SHARED_SUBTREE_LAST); - - // Now cache the leaf enable mask for the subtree shared with the client - leafEnHi = intrReadRegLeafEnSet_HAL(pGpu, pIntr, uvmSharedLeafIdxStart, NULL); - leafEnLo = intrReadRegLeafEnSet_HAL(pGpu, pIntr, uvmSharedLeafIdxEnd, NULL); - - pIntr->uvmSharedCpuLeafEn = ((NvU64)(leafEnHi) << 32) | leafEnLo; - pIntr->uvmSharedCpuLeafEnDisableMask = intrGetUvmSharedLeafEnDisableMask_HAL(pGpu, pIntr); - - // - // Cache the CPU_INTR_TOP_EN mask to clear when disabling stall interrupts - // (other interrupts are either not disabled or disabled selectively at leaf level) - // - for (i = NV_CPU_INTR_STALL_SUBTREE_START; i <= stallSubtreeLast; i++) { - pIntr->intrTopEnMask |= NVBIT(i); + NV2080_INTR_CATEGORY_SUBTREE_MAP uvmShared; + NV_ASSERT_OK_OR_RETURN( + intrGetSubtreeRange(pIntr, + NV2080_INTR_CATEGORY_UVM_SHARED, + &uvmShared)); + // + // Assert to make sure we have only one client shared subtree. + // The below code assumes that. + // + NV_ASSERT_OR_RETURN(uvmShared.subtreeStart == uvmShared.subtreeEnd, + NV_ERR_INVALID_STATE); + + // Now cache the leaf enable mask for the subtree shared with the client + NvU32 leafEnHi = intrReadRegLeafEnSet_HAL(pGpu, pIntr, + NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(uvmShared.subtreeStart), + NULL); + NvU32 leafEnLo = intrReadRegLeafEnSet_HAL(pGpu, pIntr, + NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(uvmShared.subtreeStart), + NULL); + + pIntr->uvmSharedCpuLeafEn = ((NvU64)(leafEnHi) << 32) | leafEnLo; + pIntr->uvmSharedCpuLeafEnDisableMask = + intrGetUvmSharedLeafEnDisableMask_HAL(pGpu, pIntr); } + // + // Cache the CPU_INTR_TOP_EN mask to clear when disabling stall + // interrupts (other interrupts are either not disabled or disabled + // selectively at leaf level) + // + pIntr->intrTopEnMask |= intrGetIntrTopLockedMask(pGpu, pIntr); + OBJDISP *pDisp = GPU_GET_DISP(pGpu); // Cache client owned, shared interrupt, and display vectors for ease of use later pIntr->accessCntrIntrVector = intrGetVectorFromEngineId(pGpu, pIntr, MC_ENGINE_IDX_ACCESS_CNTR, NV_FALSE); - if (!gpuIsCCFeatureEnabled(pGpu)) + if (!gpuIsCCFeatureEnabled(pGpu) || !gpuIsGspOwnedFaultBuffersEnabled(pGpu)) { pIntr->replayableFaultIntrVector = intrGetVectorFromEngineId(pGpu, pIntr, MC_ENGINE_IDX_REPLAYABLE_FAULT, NV_FALSE); } @@ -270,20 +277,30 @@ intrCacheIntrFields_TU102 } } - // - // Now ensure that they're in the expected subtree (check right now so we - // don't have to check later in latency critical paths where this is assumed - // to be true) - // - if (NV_CTRL_INTR_GPU_VECTOR_TO_SUBTREE(pIntr->accessCntrIntrVector) != NV_CPU_INTR_UVM_SUBTREE_START) { - NV_PRINTF(LEVEL_ERROR, "UVM interrupt vectors for replayable fault and " - "access counter are in an unexpected subtree. Expected = 0x%x, actual = 0x%x\n", - NV_CPU_INTR_UVM_SUBTREE_START, - NV_CTRL_INTR_GPU_VECTOR_TO_SUBTREE(pIntr->accessCntrIntrVector)); - DBG_BREAKPOINT(); - status = NV_ERR_GENERIC; - goto exit; + // + // Now ensure that they're in the expected subtree (check right now so + // we don't have to check later in latency critical paths where this is + // assumed to be true) + // + NV2080_INTR_CATEGORY_SUBTREE_MAP uvmOwned; + NvU32 accessCntrSubtree = NV_CTRL_INTR_GPU_VECTOR_TO_SUBTREE( + pIntr->accessCntrIntrVector); + NV_ASSERT_OK_OR_RETURN( + intrGetSubtreeRange(pIntr, + NV2080_INTR_CATEGORY_UVM_OWNED, + &uvmOwned)); + if (!(uvmOwned.subtreeStart <= accessCntrSubtree && + accessCntrSubtree <= uvmOwned.subtreeEnd)) + { + NV_PRINTF(LEVEL_ERROR, + "UVM owned interrupt vector for access counter is in an unexpected subtree\n" + "Expected range = [0x%x, 0x%x], actual = 0x%x\n", + uvmOwned.subtreeStart, uvmOwned.subtreeEnd, accessCntrSubtree); + DBG_BREAKPOINT(); + status = NV_ERR_GENERIC; + goto exit; + } } exit: @@ -439,13 +456,13 @@ _intrEnableStall_TU102 THREAD_STATE_NODE *pThreadState ) { - NvU32 val, idx; + NvU32 idx; // // 1. Enable the UVM interrupts that RM currently owns at INTR_LEAF // level. // - val = _intrGetUvmLeafMask_TU102(pGpu, pIntr); + NvU32 val = _intrGetUvmLeafMask_TU102(pGpu, pIntr); idx = NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(pIntr->accessCntrIntrVector); if (val != 0) { @@ -457,12 +474,18 @@ _intrEnableStall_TU102 // level, based on the cached value. // - // - // Compile time assert to make sure we have only one client shared subtree. - // The below code assumes that. - // - ct_assert(NV_CPU_INTR_UVM_SHARED_SUBTREE_START == NV_CPU_INTR_UVM_SHARED_SUBTREE_LAST); - idx = NV_CPU_INTR_UVM_SHARED_SUBTREE_START; + { + NV2080_INTR_CATEGORY_SUBTREE_MAP uvmShared; + NV_ASSERT_OK(intrGetSubtreeRange(pIntr, + NV2080_INTR_CATEGORY_UVM_SHARED, + &uvmShared)); + // + // Assert to make sure we have only one client shared subtree. + // The below code assumes that. + // + NV_ASSERT(uvmShared.subtreeStart == uvmShared.subtreeEnd); + idx = uvmShared.subtreeStart; + } if (NvU64_HI32(pIntr->uvmSharedCpuLeafEn) != 0) { @@ -482,15 +505,30 @@ _intrEnableStall_TU102 // We use the assumption that 1 == ENABLE below ct_assert(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE_ENABLE == 1); - // - // 3. Enable all interrupt subtrees (except nonstall) at top level. Nonstall - // enablement is handled by a different function. - // - val = 0xFFFFFFFF; + { + // + // 3. Enable all interrupt subtrees (except nonstall) at top level. + // Nonstall enablement is handled by a different function. + // + NvU64 mask = NV_U64_MAX; - val &= ~intrGetIntrTopNonStallMask_HAL(pGpu, pIntr); + mask &= ~intrGetIntrTopNonStallMask_HAL(pGpu, pIntr); - intrWriteRegTopEnSet_HAL(pGpu, pIntr, 0, val, pThreadState); + if (NvU64_LO32(mask) != 0) + { + intrWriteRegTopEnSet_HAL(pGpu, pIntr, + 0, + NvU64_LO32(mask), + pThreadState); + } + if (NvU64_HI32(mask) != 0) + { + intrWriteRegTopEnSet_HAL(pGpu, pIntr, + 1, + NvU64_HI32(mask), + pThreadState); + } + } } /*! @@ -525,12 +563,18 @@ _intrDisableStall_TU102 // level, except the ones that can be handled outside the GPU lock. // - // - // Compile time assert to make sure we have only one client shared subtree. - // The below code assumes that. - // - ct_assert(NV_CPU_INTR_UVM_SHARED_SUBTREE_START == NV_CPU_INTR_UVM_SHARED_SUBTREE_LAST); - idx = NV_CPU_INTR_UVM_SHARED_SUBTREE_START; + { + NV2080_INTR_CATEGORY_SUBTREE_MAP uvmShared; + NV_ASSERT_OK(intrGetSubtreeRange(pIntr, + NV2080_INTR_CATEGORY_UVM_SHARED, + &uvmShared)); + // + // Assert to make sure we have only one client shared subtree. + // The below code assumes that. + // + NV_ASSERT(uvmShared.subtreeStart == uvmShared.subtreeEnd); + idx = uvmShared.subtreeStart; + } if (!gpuIsStateLoaded(pGpu)) { @@ -588,7 +632,20 @@ _intrDisableStall_TU102 // 3. Disable some interrupt subtrees at top level (information about which // ones to disable is cached in pIntr->intrTopEnMask) // - intrWriteRegTopEnClear_HAL(pGpu, pIntr, 0, pIntr->intrTopEnMask, pThreadState); + if (NvU64_LO32(pIntr->intrTopEnMask) != 0) + { + intrWriteRegTopEnClear_HAL(pGpu, pIntr, + 0, + NvU64_LO32(pIntr->intrTopEnMask), + pThreadState); + } + if (NvU64_HI32(pIntr->intrTopEnMask) != 0) + { + intrWriteRegTopEnClear_HAL(pGpu, pIntr, + 1, + NvU64_HI32(pIntr->intrTopEnMask), + pThreadState); + } } /*! @@ -662,7 +719,7 @@ _intrGetUvmLeafMask_TU102 NvBool bRmOwnsReplayableFault = !!(pKernelGmmu->uvmSharedIntrRmOwnsMask & RM_UVM_SHARED_INTR_MASK_MMU_REPLAYABLE_FAULT_NOTIFY); NvBool bRmOwnsAccessCntr = !!(pKernelGmmu->uvmSharedIntrRmOwnsMask & RM_UVM_SHARED_INTR_MASK_HUB_ACCESS_COUNTER_NOTIFY); - if (bRmOwnsReplayableFault && !gpuIsCCFeatureEnabled(pGpu)) + if (bRmOwnsReplayableFault && (!gpuIsCCFeatureEnabled(pGpu) || !gpuIsGspOwnedFaultBuffersEnabled(pGpu))) { val |= NVBIT(NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(pIntr->replayableFaultIntrVector)); } @@ -696,6 +753,7 @@ intrGetUvmSharedLeafEnDisableMask_TU102 NvU32 intrVectorNonReplayableFault; NvU32 intrVectorFifoNonstall = NV_INTR_VECTOR_INVALID; NvU64 mask = 0; + NV2080_INTR_CATEGORY_SUBTREE_MAP uvmShared; // GSP RM services both MMU non-replayable fault and FIFO interrupts if (IS_GSP_CLIENT(pGpu)) @@ -719,22 +777,28 @@ intrGetUvmSharedLeafEnDisableMask_TU102 NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(intrVectorFifoNonstall)); } - // Ascertain that they're in the first leaf - NV_ASSERT(NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(intrVectorNonReplayableFault) == - NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(NV_CPU_INTR_UVM_SHARED_SUBTREE_START)); - + NV_ASSERT_OK(intrGetSubtreeRange(pIntr, + NV2080_INTR_CATEGORY_UVM_SHARED, + &uvmShared)); // - // Compile-time ascertain that we only have 1 client subtree (we assume + // Ascertain that we only have 1 client subtree (we assume // this since we cache only 64 bits). // - ct_assert(NV_CPU_INTR_UVM_SHARED_SUBTREE_START == NV_CPU_INTR_UVM_SHARED_SUBTREE_LAST); + NV_ASSERT(uvmShared.subtreeStart == uvmShared.subtreeEnd); // - // Compile-time ascertain that we only have 2 subtrees as this is what we currently support - // by only caching 64 bits + // Ascertain that we only have 2 subtrees as this is what we currently + // support by only caching 64 bits // - ct_assert((NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(NV_CPU_INTR_UVM_SHARED_SUBTREE_LAST) - 1) == - NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(NV_CPU_INTR_UVM_SHARED_SUBTREE_START)); + NV_ASSERT( + (NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(uvmShared.subtreeEnd) - 1) == + NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(uvmShared.subtreeStart)); + + + // Ascertain that they're in the first leaf + NV_ASSERT( + NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(intrVectorNonReplayableFault) == + NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(uvmShared.subtreeStart)); mask |= NVBIT64(NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(intrVectorNonReplayableFault)); @@ -770,12 +834,13 @@ intrGetPendingStallEngines_TU102 INTR_TABLE_ENTRY *pIntrTable; KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); NvU32 intrTableSz, i; - - NvU32 stallSubtreeLast = intrGetStallSubtreeLast_HAL(pGpu, pIntr); + NvU64 sanityCheckSubtreeMask = 0; NvU32 numIntrLeaves = intrGetNumLeaves_HAL(pGpu, pIntr); NV_ASSERT(numIntrLeaves <= NV_MAX_INTR_LEAVES); NvU32 intrLeafValues[NV_MAX_INTR_LEAVES]; + sanityCheckSubtreeMask = intrGetIntrTopLegacyStallMask(pIntr); + portMemSet(intrLeafValues, 0, numIntrLeaves * sizeof(NvU32)); bitVectorClrAll(pEngines); @@ -810,8 +875,9 @@ intrGetPendingStallEngines_TU102 // is only to catch issues during code development. Should never happen // in practice // - if ((leafIndex < NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(NV_CPU_INTR_UVM_SUBTREE_START)) || - (leafIndex > NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(stallSubtreeLast))) + + if ((sanityCheckSubtreeMask & + NVBIT64(NV_CTRL_INTR_LEAF_IDX_TO_SUBTREE(leafIndex))) == 0) { NV_PRINTF(LEVEL_ERROR, "MC_ENGINE_IDX %u has invalid stall intr vector %u\n", pIntrTable[i].mcEngine, intrVector); DBG_BREAKPOINT(); @@ -906,8 +972,7 @@ intrRetriggerTopLevel_TU102 Intr *pIntr ) { - NvU32 val = 0; - NvU32 i; + NvU64 mask = 0; // We use the assumption that 1 == DISABLE below ct_assert(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE_DISABLE == 1); @@ -923,28 +988,53 @@ intrRetriggerTopLevel_TU102 // 1. If the alternate tree (nonstall tree) is handled "lockless", it // is not disabled during RM lock acquire, so needs re-arming. // - val |= intrGetIntrTopNonStallMask_HAL(pGpu, pIntr); + mask |= intrGetIntrTopNonStallMask_HAL(pGpu, pIntr); } - // // 2. UVM-owned interrupt tree (never disabled at top level) + mask |= intrGetIntrTopCategoryMask(pIntr, NV2080_INTR_CATEGORY_UVM_OWNED); + // 3. UVM/RM shared interrupt tree (never disabled at top level) - // - for (i = NV_CPU_INTR_UVM_SUBTREE_START; i <= NV_CPU_INTR_UVM_SHARED_SUBTREE_LAST; i++) - { - val |= NVBIT(i); - } + mask |= intrGetIntrTopCategoryMask(pIntr, NV2080_INTR_CATEGORY_UVM_SHARED); // // Bypass GPU_REG_WR32 that requires the GPU lock to be held (for some // register filters) by using the OS interface directly. // - osGpuWriteReg032(pGpu, - GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR(0)), - val); - osGpuWriteReg032(pGpu, - GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET(0)), - val); + // Clear all first, then set + // + if (NvU64_LO32(mask) != 0 && + 0 < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR__SIZE_1) + { + osGpuWriteReg032(pGpu, + GPU_GET_VREG_OFFSET(pGpu, + NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR(0)), + NvU64_LO32(mask)); + } + if (NvU64_HI32(mask) != 0 && + 1 < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR__SIZE_1) + { + osGpuWriteReg032(pGpu, + GPU_GET_VREG_OFFSET(pGpu, + NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR(1)), + NvU64_HI32(mask)); + } + if (NvU64_LO32(mask) != 0 && + 0 < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1) + { + osGpuWriteReg032(pGpu, + GPU_GET_VREG_OFFSET(pGpu, + NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET(0)), + NvU64_LO32(mask)); + } + if (NvU64_HI32(mask) != 0 && + 1 < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1) + { + osGpuWriteReg032(pGpu, + GPU_GET_VREG_OFFSET(pGpu, + NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET(1)), + NvU64_HI32(mask)); + } } /*! @@ -967,11 +1057,8 @@ intrGetLeafStatus_TU102 NvU32 subtreeIndex; NvU32 leafIndex; - // Read all the stalling interrupt leaf status - NvU32 stallSubtreeLast = intrGetStallSubtreeLast_HAL(pGpu, pIntr); - NV_ASSERT_OR_RETURN(NV_CPU_INTR_UVM_SUBTREE_START <= stallSubtreeLast, NV_ERR_INVALID_STATE); - subtreeIndex = NV_CPU_INTR_UVM_SUBTREE_START; - for (; subtreeIndex <= stallSubtreeLast; subtreeIndex++) + FOR_EACH_INDEX_IN_MASK(64, subtreeIndex, + intrGetIntrTopLegacyStallMask(pIntr)) { leafIndex = NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(subtreeIndex); if (pIntr->getProperty(pIntr, PDB_PROP_INTR_READ_ONLY_EVEN_NUMBERED_INTR_LEAF_REGS)) @@ -989,7 +1076,7 @@ intrGetLeafStatus_TU102 pLeafVals[leafIndex] = intrReadRegLeaf_HAL(pGpu, pIntr, leafIndex, pThreadState); } } - } + } FOR_EACH_INDEX_IN_MASK_END return NV_OK; } @@ -1131,15 +1218,38 @@ intrDumpState_TU102 } } -/*! - * @brief Gets the stall subtree end index - */ -NvU32 -intrGetStallSubtreeLast_TU102(OBJGPU *pGpu, Intr *pIntr) + +NV_STATUS +intrInitSubtreeMap_TU102 +( + OBJGPU *pGpu, + Intr *pIntr +) { - return NV_CPU_INTR_STALL_SUBTREE_LAST; + NV2080_INTR_CATEGORY_SUBTREE_MAP *pCategoryEngine = + &pIntr->subtreeMap[NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE]; + pCategoryEngine->subtreeStart = NV_CPU_INTR_STALL_SUBTREE_START; + pCategoryEngine->subtreeEnd = NV_CPU_INTR_STALL_SUBTREE_LAST; + + NV2080_INTR_CATEGORY_SUBTREE_MAP *pCategoryEngineNotification = + &pIntr->subtreeMap[NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION]; + pCategoryEngineNotification->subtreeStart = NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(0); + pCategoryEngineNotification->subtreeEnd = NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(0); + + NV2080_INTR_CATEGORY_SUBTREE_MAP *pCategoryUvmOwned = + &pIntr->subtreeMap[NV2080_INTR_CATEGORY_UVM_OWNED]; + pCategoryUvmOwned->subtreeStart = NV_CPU_INTR_UVM_SUBTREE_START; + pCategoryUvmOwned->subtreeEnd = NV_CPU_INTR_UVM_SUBTREE_LAST; + + NV2080_INTR_CATEGORY_SUBTREE_MAP *pCategoryUvmShared = + &pIntr->subtreeMap[NV2080_INTR_CATEGORY_UVM_SHARED]; + pCategoryUvmShared->subtreeStart = NV_CPU_INTR_UVM_SHARED_SUBTREE_START; + pCategoryUvmShared->subtreeEnd = NV_CPU_INTR_UVM_SHARED_SUBTREE_LAST; + + return NV_OK; } + /*! * @brief Gets the number of leaf registers used */ @@ -1159,12 +1269,15 @@ intrGetLeafSize_TU102(OBJGPU *pGpu, Intr *pIntr) return NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__SIZE_1; } -/*! - * @brief Gets the mask of INTR_TOP that covers nonstall interrupts - */ -NvU32 -intrGetIntrTopNonStallMask_TU102(OBJGPU *pGpu, Intr *pIntr) + +NvU64 +intrGetIntrTopNonStallMask_TU102 +( + OBJGPU *pGpu, + Intr *pIntr +) { + // TODO Bug 3823562 Remove these asserts // Compile-time assert against the highest set bit that will be returned #define NV_CPU_INTR_NOSTALL_SUBTREE_HIGHEST NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(0) @@ -1172,9 +1285,20 @@ intrGetIntrTopNonStallMask_TU102(OBJGPU *pGpu, Intr *pIntr) ct_assert(NV_CPU_INTR_NOSTALL_SUBTREE_HIGHEST < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET__SIZE_1); ct_assert(NV_CPU_INTR_NOSTALL_SUBTREE_HIGHEST < NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__SIZE_1); - return NVBIT32(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(0)); + NvU64 mask = intrGetIntrTopCategoryMask(pIntr, + NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION); + + // + // On all Ampere+ that use this TU102 HAL, Esched notification interrupts + // are also included in this if PDB_PROP_GPU_SWRL_GRANULAR_LOCKING is set. + // + + // Sanity check that Intr.subtreeMap is initialized + NV_ASSERT(mask != 0); + return mask; } + /*! * @brief Decode the interrupt mode for SW to use * diff --git a/src/nvidia/src/kernel/gpu/intr/intr.c b/src/nvidia/src/kernel/gpu/intr/intr.c index abce1b9b1..59bd8b55d 100644 --- a/src/nvidia/src/kernel/gpu/intr/intr.c +++ b/src/nvidia/src/kernel/gpu/intr/intr.c @@ -41,6 +41,7 @@ #include "nv_ref.h" #include "nvRmReg.h" +#include "nvmisc.h" // @@ -56,6 +57,23 @@ static struct static NvBool _intrServiceStallExactList(OBJGPU *pGpu, Intr *pIntr, MC_ENGINE_BITVECTOR *pEngines); static void _intrInitServiceTable(OBJGPU *pGpu, Intr *pIntr); + +NV_STATUS +intrGetSubtreeRange_IMPL +( + Intr *pIntr, + NV2080_INTR_CATEGORY category, + NV2080_INTR_CATEGORY_SUBTREE_MAP *pRange +) +{ + NV_ASSERT_OR_RETURN(pRange != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(category < NV2080_INTR_CATEGORY_ENUM_COUNT, + NV_ERR_INVALID_ARGUMENT); + *pRange = pIntr->subtreeMap[category]; + return NV_OK; +} + + void intrServiceStall_IMPL(OBJGPU *pGpu, Intr *pIntr) { @@ -741,25 +759,36 @@ intrDestruct_IMPL NV_STATUS intrStateInitUnlocked_IMPL ( - OBJGPU *pGpu, - Intr *pIntr) + OBJGPU *pGpu, + Intr *pIntr +) { NvU32 data = 0; + NvU32 i; if (osReadRegistryDword(pGpu, NV_REG_STR_RM_INTR_DETAILED_LOGS, &data) == NV_OK) { if (data == NV_REG_STR_RM_INTR_DETAILED_LOGS_ENABLE) { - pIntr->setProperty(pIntr, PDB_PROP_INTR_ENABLE_DETAILED_LOGS, NV_TRUE); + pIntr->setProperty(pIntr, + PDB_PROP_INTR_ENABLE_DETAILED_LOGS, + NV_TRUE); } } _intrInitRegistryOverrides(pGpu, pIntr); + for (i = 0; i < NV_ARRAY_ELEMENTS(pIntr->subtreeMap); ++i) + { + pIntr->subtreeMap[i].subtreeStart = NV2080_INTR_INVALID_SUBTREE; + pIntr->subtreeMap[i].subtreeEnd = NV2080_INTR_INVALID_SUBTREE; + } + return NV_OK; } + NV_STATUS intrStateInitLocked_IMPL ( @@ -992,6 +1021,10 @@ intrInitInterruptTable_KERNEL pIntr->pIntrTable = pIntrTable; pIntr->intrTableSz = pParams->tableLen; pIntrTable = NULL; + + portMemCopy(pIntr->subtreeMap, sizeof pIntr->subtreeMap, + pParams->subtreeMap, sizeof pParams->subtreeMap); + status = NV_OK; exit: @@ -1650,3 +1683,78 @@ intrIsIntrEnabled_IMPL return NV_TRUE; } + + +NvU64 +intrGetIntrTopCategoryMask_IMPL +( + Intr *pIntr, + NV2080_INTR_CATEGORY category +) +{ + NvU32 subtreeStart = pIntr->subtreeMap[category].subtreeStart; + NvU32 subtreeEnd = pIntr->subtreeMap[category].subtreeStart; + NvU64 ret = 0x0; + NvU32 i; + + if (subtreeStart == NV2080_INTR_INVALID_SUBTREE || + subtreeEnd == NV2080_INTR_INVALID_SUBTREE) + { + return 0x0; + } + + for (i = subtreeStart; i <= subtreeEnd; ++i) + { + ret |= NVBIT64(i); + } + + return ret; +} + + +NvU64 +intrGetIntrTopLegacyStallMask_IMPL +( + Intr *pIntr +) +{ + OBJGPU *pGpu = ENG_GET_GPU(pIntr); + NvU64 ret = + intrGetIntrTopCategoryMask(pIntr, NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE) | + intrGetIntrTopCategoryMask(pIntr, NV2080_INTR_CATEGORY_RUNLIST) | + intrGetIntrTopCategoryMask(pIntr, NV2080_INTR_CATEGORY_UVM_OWNED) | + intrGetIntrTopCategoryMask(pIntr, NV2080_INTR_CATEGORY_UVM_SHARED); + + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_SWRL_GRANULAR_LOCKING)) + { + ret |= intrGetIntrTopCategoryMask(pIntr, + NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION); + } + + // Sanity check that Intr.subtreeMap is initialized + NV_ASSERT(ret != 0); + return ret; +} + + +NvU64 +intrGetIntrTopLockedMask_IMPL +( + OBJGPU *pGpu, + Intr *pIntr +) +{ + NvU64 ret = + intrGetIntrTopCategoryMask(pIntr, NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE) | + intrGetIntrTopCategoryMask(pIntr, NV2080_INTR_CATEGORY_RUNLIST); + + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_SWRL_GRANULAR_LOCKING)) + { + ret |= intrGetIntrTopCategoryMask(pIntr, + NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION); + } + + // Sanity check that Intr.subtreeMap is initialized + NV_ASSERT(ret != 0); + return ret; +} diff --git a/src/nvidia/src/kernel/gpu/mc/kernel_mc.c b/src/nvidia/src/kernel/gpu/mc/kernel_mc.c index 63df160b4..8ef4d3630 100644 --- a/src/nvidia/src/kernel/gpu/mc/kernel_mc.c +++ b/src/nvidia/src/kernel/gpu/mc/kernel_mc.c @@ -124,7 +124,7 @@ subdeviceCtrlCmdMcChangeReplayableFaultOwnership_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); - if (gpuIsCCFeatureEnabled(pGpu)) + if (gpuIsCCFeatureEnabled(pGpu) && gpuIsGspOwnedFaultBuffersEnabled(pGpu)) { return NV_ERR_NOT_SUPPORTED; } diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/mem_mgr_ga100.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/mem_mgr_ga100.c index 467823ec0..44917d7b9 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/mem_mgr_ga100.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/mem_mgr_ga100.c @@ -488,3 +488,18 @@ memmgrInsertUnprotectedRegionAtBottomOfFb_GA100 return NV_OK; } + +NvBool +memmgrIsApertureSupportedByFla_GA100 +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager, + NV_ADDRESS_SPACE aperture +) +{ + if (aperture == ADDR_FBMEM) + { + return NV_TRUE; + } + return NV_FALSE; +} diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c index b02833b03..bf8f96c78 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c @@ -467,9 +467,10 @@ memmgrAllocHal_GM107 // if (FLD_TEST_DRF(OS32, _ATTR2, _ZBC_SKIP_ZBCREFCOUNT, _NO, pFbAllocInfo->pageFormat->attr2)) { - if (memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_ZBC, pFbAllocInfo->pageFormat->kind) && - !(pFbAllocInfo->pageFormat->flags & NVOS32_ALLOC_FLAGS_VIRTUAL) && - !IS_MIG_ENABLED(pGpu)) + if ( + !IS_MIG_ENABLED(pGpu) && + memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_ZBC, pFbAllocInfo->pageFormat->kind) && + !(pFbAllocInfo->pageFormat->flags & NVOS32_ALLOC_FLAGS_VIRTUAL)) { retAttr2 = FLD_SET_DRF(OS32, _ATTR2, _ZBC, _PREFER_ZBC, retAttr2); if (!bAlignPhase) @@ -524,7 +525,7 @@ memmgrFreeHal_GM107 PRMTIMEOUT pTimeout ) { - NvU32 commitResId = pFbAllocInfo->hwResId; + NvU32 commitResId = pFbAllocInfo->hwResId; if (pFbAllocInfo->pageFormat->flags & NVOS32_ALLOC_FLAGS_SKIP_RESOURCE_ALLOC) { @@ -1131,10 +1132,10 @@ memmgrSetMemDescPageSize_GM107 RM_ATTR_PAGE_SIZE pageSizeAttr ) { - NvU32 newPageSize = RM_PAGE_SIZE; + NvU64 newPageSize = RM_PAGE_SIZE; KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); NV_ADDRESS_SPACE addrSpace = memdescGetAddressSpace(pMemDesc); - NvU32 oldPageSize; + NvU64 oldPageSize; // This policy is meaningless for virtual memdescs, so abort early. if (ADDR_VIRTUAL == addrSpace) @@ -1232,7 +1233,7 @@ memmgrSetMemDescPageSize_GM107 } // Only update the memory descriptor if it is unset - oldPageSize = memdescGetPageSize(pMemDesc, addressTranslation); + oldPageSize = memdescGetPageSize64(pMemDesc, addressTranslation); if (0 == oldPageSize) { memdescSetPageSize(pMemDesc, addressTranslation, newPageSize); diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_utils_gm107.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_utils_gm107.c index acf354922..491a1a7d2 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_utils_gm107.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_utils_gm107.c @@ -1523,10 +1523,10 @@ memmgrMemUtilsMemSetBlocking_GM107 if (timeoutStatus == NV_ERR_TIMEOUT) { NV_PRINTF(LEVEL_ERROR, - "Timed Out wating for CE semaphore in blocking scrub!\n"); + "Timed Out waiting for CE semaphore in blocking scrub!\n"); NV_PRINTF(LEVEL_ERROR, - "GET=0x%x, PUT=0x%x, GPGET=0x%x, GPPET=0x%x\n", + "GET=0x%x, PUT=0x%x, GPGET=0x%x, GPPUT=0x%x\n", pChannel->pControlGPFifo->Get, pChannel->pControlGPFifo->Put, pChannel->pControlGPFifo->GPGet, @@ -1586,10 +1586,10 @@ memmgrMemUtilsMemSetBatched_GM107 if (timeoutStatus == NV_ERR_TIMEOUT) { NV_PRINTF(LEVEL_ERROR, - "Timed Out wating for CE semaphore in blocking scrub!\n"); + "Timed Out waiting for CE semaphore in blocking scrub!\n"); NV_PRINTF(LEVEL_ERROR, - "GET=0x%x, PUT=0x%x, GPGET=0x%x, GPPET=0x%x\n", + "GET=0x%x, PUT=0x%x, GPGET=0x%x, GPPUT=0x%x\n", MEM_RD32(&pChannel->pControlGPFifo->Get), MEM_RD32(&pChannel->pControlGPFifo->Put), MEM_RD32(&pChannel->pControlGPFifo->GPGet), @@ -1663,7 +1663,7 @@ memmgrMemUtilsMemCopyBatched_GM107 MEM_RD32(semAddr), pChannel->finishPayload); NV_PRINTF(LEVEL_INFO, - "GET=0x%x, PUT=0x%x, GPGET=0x%x, GPPET=0x%x\n", + "GET=0x%x, PUT=0x%x, GPGET=0x%x, GPPUT=0x%x\n", MEM_RD32(&pChannel->pControlGPFifo->Get), MEM_RD32(&pChannel->pControlGPFifo->Put), MEM_RD32(&pChannel->pControlGPFifo->GPGet), @@ -1672,10 +1672,10 @@ memmgrMemUtilsMemCopyBatched_GM107 if (timeoutStatus == NV_ERR_TIMEOUT) { NV_PRINTF(LEVEL_ERROR, - "Timed Out wating for CE semaphore in blocking scrub!\n"); + "Timed Out waiting for CE semaphore in blocking scrub!\n"); NV_PRINTF(LEVEL_ERROR, - "GET=0x%x, PUT=0x%x, GPGET=0x%x, GPPET=0x%x\n", + "GET=0x%x, PUT=0x%x, GPGET=0x%x, GPPUT=0x%x\n", MEM_RD32(&pChannel->pControlGPFifo->Get), MEM_RD32(&pChannel->pControlGPFifo->Put), MEM_RD32(&pChannel->pControlGPFifo->GPGet), diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c index c0085172c..e58b48104 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -265,6 +265,7 @@ dmaAllocMapping_GM107 Memory *pMemory; NvU32 pageArrayGranularity; NvU8 pageShift; + NvU64 physPageSize; } *pLocals = portMemAllocNonPaged(sizeof(*pLocals)); // Heap Allocate to avoid stack overflow @@ -337,10 +338,43 @@ dmaAllocMapping_GM107 // Get pageSize pLocals->pTempMemDesc = memdescGetMemDescFromGpu(pAdjustedMemDesc, pGpu); - pLocals->pageSize = memdescGetPageSize(pLocals->pTempMemDesc, addressTranslation); - - // Get pte granularity + + // Get physical allocation granularity and page size. pLocals->pageArrayGranularity = pLocals->pTempMemDesc->pageArrayGranularity; + pLocals->physPageSize = memdescGetPageSize64(pLocals->pTempMemDesc, addressTranslation); + + // retrieve mapping page size from flags + switch(DRF_VAL(OS46, _FLAGS, _PAGE_SIZE, flags)) + { + case NVOS46_FLAGS_PAGE_SIZE_DEFAULT: + case NVOS46_FLAGS_PAGE_SIZE_BOTH: + pLocals->pageSize = memdescGetPageSize64(pLocals->pTempMemDesc, addressTranslation); + break; + case NVOS46_FLAGS_PAGE_SIZE_4KB: + pLocals->pageSize = RM_PAGE_SIZE; + break; + case NVOS46_FLAGS_PAGE_SIZE_BIG: + // case for arch specific 128K + pLocals->pageSize = pLocals->vaspaceBigPageSize; + break; + case NVOS46_FLAGS_PAGE_SIZE_HUGE: + pLocals->pageSize = RM_PAGE_SIZE_HUGE; + break; + default: + NV_PRINTF(LEVEL_ERROR, "Unknown page size flag encountered during mapping\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + NV_PRINTF(LEVEL_INFO, "Picked Page size based on flags: 0x%llx flagVal: 0x%x\n", + pLocals->pageSize, DRF_VAL(OS46, _FLAGS, _PAGE_SIZE, flags)); + + if (pLocals->physPageSize < pLocals->pageSize) + { + NV_PRINTF(LEVEL_WARNING, "Requested mapping at larger page size than the physical granularity " + "PhysPageSize = 0x%llx MapPageSize = 0x%llx. Overriding to physical page granularity...\n", + pLocals->physPageSize, pLocals->pageSize); + pLocals->pageSize = pLocals->physPageSize; + } if (memdescGetFlag(pLocals->pTempMemDesc, MEMDESC_FLAGS_DEVICE_READ_ONLY)) { @@ -348,30 +382,6 @@ dmaAllocMapping_GM107 status = NV_ERR_INVALID_ARGUMENT; goto cleanup); } - // For verify purposes we should allow small page override for mapping. - // This will be used for testing VASpace interop. - if (RMCFG_FEATURE_PLATFORM_MODS && - FLD_TEST_DRF(OS46, _FLAGS, _PAGE_SIZE, _4KB, flags) && - kgmmuIsVaspaceInteropSupported(pKernelGmmu)) - { - pLocals->pageSize = RM_PAGE_SIZE; - SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY | SLI_LOOP_FLAGS_IGNORE_REENTRANCY) - memdescSetPageSize(memdescGetMemDescFromGpu(pAdjustedMemDesc, pGpu), addressTranslation, (NvU32)pLocals->pageSize); - SLI_LOOP_END - } - else if (kgmmuIsPerVaspaceBigPageEn(pKernelGmmu) && - (pLocals->pageSize >= RM_PAGE_SIZE_64K)) - { - NV_ASSERT(pLocals->pageSize != RM_PAGE_SIZE_HUGE); - - // - // This is a temp WAR till the memdesc->_pageSize is cleaned up - // If the memdesc page size is >= the smallest big page size then - // we will correct it to the Big page size of the VASpace - // - pLocals->pageSize = pLocals->vaspaceBigPageSize; - } - // // Force BAR1 VA pageSize at bigPageSize only if total BAR1 size is less // than threshold(default: 256MB) to not waste BAR1. @@ -412,6 +422,18 @@ dmaAllocMapping_GM107 if (NV_OK != status) goto cleanup; + // + // When compression is enabled mapping at 4K is not supported due to + // RM allocating one comptagline per 64KB allocation (From Pascal to Turing). + // See bug 3909010 + // + if ((pLocals->pageSize == RM_PAGE_SIZE) && + memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_COMPRESSIBLE, pLocals->kind)) + { + NV_PRINTF(LEVEL_WARNING, "Requested 4K mapping on compressible sufrace. Overriding to physical page granularity..."); + pLocals->pageSize = pLocals->physPageSize; + } + #ifdef DEBUG // Check for subdevices consistency if broadcast memdesc is passed in if (memdescHasSubDeviceMemDescs(pAdjustedMemDesc)) @@ -458,7 +480,9 @@ dmaAllocMapping_GM107 { // FIXME: This is broken for page size > 4KB and page offset // that crosses a page boundary (can overrun pPteArray). - pLocals->pteCount = pLocals->pageCount; + // -- + // page count is one more than integral division in case of presence of offset hence being rounded up + pLocals->pteCount = RM_ALIGN_UP((pLocals->pTempMemDesc->Size + pLocals->pageOffset), pLocals->pageArrayGranularity) >> BIT_IDX_32(pLocals->pageArrayGranularity); } // Disable PLC Compression for FLA->PA Mapping because of the HW Bug: 3046774 @@ -496,7 +520,7 @@ dmaAllocMapping_GM107 if (pLocals->bIsMemContiguous) { - pLocals->overMap = pLocals->pageCount + NvU64_LO32((pLocals->pageOffset + (pLocals->pageArrayGranularity - 1)) / pLocals->pageArrayGranularity); + pLocals->overMap = pLocals->pageCount + NvU64_LO32((pLocals->pageOffset + (pLocals->pageSize - 1)) / pLocals->pageSize); } else { @@ -1017,9 +1041,15 @@ dmaAllocMapping_GM107 // *pVaddr = pLocals->vaLo + pLocals->pageOffset; + // Fill in the final mapping page size for client mappings. + if (pCliMapInfo != NULL) + { + pCliMapInfo->pDmaMappingInfo->mapPageSize = pLocals->pageSize; + } + SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY | SLI_LOOP_FLAGS_IGNORE_REENTRANCY) // This is needed for cliDB tracking of the map. - memdescSetPageSize(memdescGetMemDescFromGpu(pAdjustedMemDesc, pGpu), addressTranslation, NvU64_LO32(pLocals->pageSize)); + memdescSetPageSize(memdescGetMemDescFromGpu(pAdjustedMemDesc, pGpu), addressTranslation, pLocals->pageSize); SLI_LOOP_END } else @@ -1096,7 +1126,7 @@ dmaFreeMapping_GM107 SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY | SLI_LOOP_FLAGS_IGNORE_REENTRANCY) // ensure the page size has been set before continuing - NV_ASSERT(memdescGetPageSize(memdescGetMemDescFromGpu(pMemDesc, pGpu), VAS_ADDRESS_TRANSLATION(pVAS)) != 0); + NV_ASSERT(memdescGetPageSize64(memdescGetMemDescFromGpu(pMemDesc, pGpu), VAS_ADDRESS_TRANSLATION(pVAS)) != 0); SLI_LOOP_END if (pCliMapInfo) @@ -1128,7 +1158,11 @@ dmaFreeMapping_GM107 } pTempMemDesc = memdescGetMemDescFromGpu(pMemDesc, pGpu); - pageSize = memdescGetPageSize(pTempMemDesc, VAS_ADDRESS_TRANSLATION(pVAS)); + + NV_ASSERT_OR_RETURN(pCliMapInfo != NULL, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(pCliMapInfo->pDmaMappingInfo->mapPageSize != 0, NV_ERR_INVALID_STATE); + + pageSize = pCliMapInfo->pDmaMappingInfo->mapPageSize; pageOffset = memdescGetPhysAddr(pTempMemDesc, VAS_ADDRESS_TRANSLATION(pVAS), 0) & (pageSize - 1); mapLength = RM_ALIGN_UP(pageOffset + pTempMemDesc->Size, pageSize); vaLo = RM_ALIGN_DOWN(vAddr, pageSize); @@ -1155,7 +1189,7 @@ dmaFreeMapping_GM107 NVLINK_INVALID_FABRIC_ADDR, deferInvalidate, NV_FALSE, - pageSize); + pageSize); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "error updating VA space.\n"); @@ -1592,7 +1626,7 @@ dmaUpdateVASpace_GF100 NvU64 fabricAddr, NvU32 deferInvalidate, NvBool bSparse, - NvU32 pageSize + NvU64 pageSize ) { KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); @@ -1625,6 +1659,14 @@ dmaUpdateVASpace_GF100 readDisable = !!(flags & DMA_UPDATE_VASPACE_FLAGS_SHADER_WRITE_ONLY); bIsIndirectPeer = !!(flags & DMA_UPDATE_VASPACE_FLAGS_INDIRECT_PEER); + NV_ASSERT_OR_RETURN(pageSize, NV_ERR_INVALID_ARGUMENT); + + vaSpaceBigPageSize = vaspaceGetBigPageSize(pVAS); + if ((pageSize == RM_PAGE_SIZE_64K) || (pageSize == RM_PAGE_SIZE_128K)) + { + NV_ASSERT_OR_RETURN(pageSize == vaSpaceBigPageSize, NV_ERR_INVALID_STATE); + } + // // Determine whether we are invalidating or revoking privileges, so we know // whether to flush page accesses or not. ReadDisable and writeDisable have @@ -1662,27 +1704,6 @@ dmaUpdateVASpace_GF100 encrypted = (flags & DMA_UPDATE_VASPACE_FLAGS_DISABLE_ENCRYPTION) ? 0 : memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ENCRYPTED); - vaSpaceBigPageSize = vaspaceGetBigPageSize(pVAS); - pageSize = memdescGetPageSize(pMemDesc, VAS_ADDRESS_TRANSLATION(pVAS)); - NV_ASSERT_OR_RETURN(pageSize, NV_ERR_INVALID_ARGUMENT); - - if (kgmmuIsPerVaspaceBigPageEn(pKernelGmmu) && - (pageSize >= RM_PAGE_SIZE_64K)) - { - NV_ASSERT(pageSize != RM_PAGE_SIZE_HUGE); - NV_ASSERT(vaSpaceBigPageSize); - - // - // This is a temp WAR till the memdesc->_pageSize is cleaned up - // If the memdesc page size is >= the smallest big page size then - // we will correct it to the Big page size of the VASpace - // This will also set it to the correct size for the memDesc - // - pageSize = vaSpaceBigPageSize; - } - - NV_ASSERT_OR_RETURN(pageSize, NV_ERR_INVALID_ARGUMENT); - // Check this here so we don't have to in the loop(s) below as necessary. if ((flags & DMA_UPDATE_VASPACE_FLAGS_UPDATE_PADDR) && (pPageArray == NULL)) { @@ -1712,43 +1733,51 @@ dmaUpdateVASpace_GF100 } // - // VMM-TODO: Merge into PL1 traveral. + // If we have dynamic granularity page arrays enabled we will never + // encounter a case where a larger page granularity physical surface gets + // represented by a smaller granularity pageArray. // - // If the pageSize of the mapping != 4K then be sure that the 4k pages - // making up the big physical page are contiguous. This is currently - // necessary since pMemDesc->PteArray is always in terms of 4KB pages. - // Different large pages do not have to be contiguous with each other. - // This check isn't needed for contig allocations. - // - if (pPageArray && (pageSize != RM_PAGE_SIZE) && (pPageArray->count > 1) && - !(flags & DMA_UPDATE_VASPACE_FLAGS_SKIP_4K_PTE_CHECK)) + if (!pMemoryManager->bEnableDynamicGranularityPageArrays) { - NvU32 i, j; - RmPhysAddr pageAddr, pagePrevAddr; - - for (i = 0; i < pPageArray->count; i += j) + // + // VMM-TODO: Merge into PL1 traveral. + // + // If the pageSize of the mapping != 4K then be sure that the 4k pages + // making up the big physical page are contiguous. This is currently + // necessary since pMemDesc->PteArray is always in terms of 4KB pages. + // Different large pages do not have to be contiguous with each other. + // This check isn't needed for contig allocations. + // + if (pPageArray && (pageSize != RM_PAGE_SIZE) && (pPageArray->count > 1) && + !(flags & DMA_UPDATE_VASPACE_FLAGS_SKIP_4K_PTE_CHECK)) { - for (j = i + 1; j < pPageArray->count; j++) + NvU32 i, j; + RmPhysAddr pageAddr, pagePrevAddr; + + for (i = 0; i < pPageArray->count; i += j) { - pagePrevAddr = dmaPageArrayGetPhysAddr(pPageArray, j - 1); - pageAddr = dmaPageArrayGetPhysAddr(pPageArray, j); - - if ((1 + (pagePrevAddr/(RM_PAGE_SIZE))) != - (pageAddr/(RM_PAGE_SIZE))) + for (j = i + 1; j < pPageArray->count; j++) { - NV_PRINTF(LEVEL_ERROR, - "MMU: given non-contig 4KB pages for %dkB mapping\n", - pageSize / 1024); - DBG_BREAKPOINT(); - return NV_ERR_GENERIC; - } + pagePrevAddr = dmaPageArrayGetPhysAddr(pPageArray, j - 1); + pageAddr = dmaPageArrayGetPhysAddr(pPageArray, j); - // Are we at the pageSize boundary yet? - if ((pageAddr + RM_PAGE_SIZE) - % pageSize == 0) - { - j++; - break; + if ((1 + (pagePrevAddr/(RM_PAGE_SIZE))) != + (pageAddr/(RM_PAGE_SIZE))) + { + NV_PRINTF(LEVEL_ERROR, + "MMU: given non-contig 4KB pages for %lldkB mapping\n", + pageSize / 1024); + DBG_BREAKPOINT(); + return NV_ERR_GENERIC; + } + + // Are we at the pageSize boundary yet? + if ((pageAddr + RM_PAGE_SIZE) + % pageSize == 0) + { + j++; + break; + } } } } @@ -1803,7 +1832,7 @@ dmaUpdateVASpace_GF100 // MMU_MAP_CTX mapTarget.pLevelFmt = mmuFmtFindLevelWithPageShift(pFmt->pRoot, - BIT_IDX_32(pageSize)); + BIT_IDX_64(pageSize)); mapTarget.pIter = &mapIter; mapTarget.MapNextEntries = _gmmuWalkCBMapNextEntries_RmAperture; mapTarget.pageArrayGranularity = pMemDesc->pageArrayGranularity; diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/heap.c b/src/nvidia/src/kernel/gpu/mem_mgr/heap.c index 501085d45..9af7f9d49 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/heap.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/heap.c @@ -2984,7 +2984,7 @@ NV_STATUS heapHwAlloc_IMPL FB_ALLOC_INFO *pFbAllocInfo = NULL; FB_ALLOC_PAGE_FORMAT *pFbAllocPageFormat = NULL; NvU32 tiledAttr; - NvU32 pageSize = 0; + NvU64 pageSize = 0; NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS *pUserParams = pHwAlloc->pUserParams; // Ensure a valid allocation type was passed in @@ -3790,7 +3790,7 @@ _heapAllocNoncontig NvU32 pteIndexOffset = 0, i = 0; NvU32 blockId = 0; NV_STATUS status = NV_OK; - NvU32 pageSize = 0; + NvU64 pageSize = 0; NvS64 numPagesLeft; MEM_BLOCK *pCurrBlock; MEM_BLOCK *pNextBlock; @@ -3838,7 +3838,7 @@ _heapAllocNoncontig // numPagesLeft = RM_ALIGN_UP(pAllocData->allocSize, pageSize) / pageSize; NV_PRINTF(LEVEL_INFO, - "pageSize: 0x%x, numPagesLeft: 0x%llx, allocSize: 0x%llx\n", + "pageSize: 0x%llx, numPagesLeft: 0x%llx, allocSize: 0x%llx\n", pageSize / 1024, numPagesLeft, pAllocData->allocSize); for (pCurrBlock = pHeap->pNoncontigFreeBlockList; diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c index c93ec6c65..a77a279d2 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c @@ -261,7 +261,7 @@ memdescCreate } } - if (RMCFG_FEATURE_PLATFORM_MODS || IsT194(pGpu)) + if (RMCFG_FEATURE_PLATFORM_MODS || IsT194(pGpu) || IsT234(pGpu)) { if ( (AddressSpace == ADDR_FBMEM) && !(Flags & MEMDESC_ALLOC_FLAGS_PROTECTED) && @@ -2274,7 +2274,7 @@ memdescFillPages NvU32 pageIndex, NvU64 *pPages, NvU32 pageCount, - NvU32 pageSize + NvU64 pageSize ) { NvU32 i, j, k; @@ -2401,7 +2401,20 @@ memdescCreateSubMem pageOffset = memdescGetPhysAddr(pTempMemDesc, AT_CPU, Offset) & (pTempMemDesc->_pageSize - 1); + + // Check for integer overflow + if (!portSafeAddU64(pageOffset, Size, &tmpSize)) + { + return NV_ERR_INVALID_ARGUMENT; + } + tmpSize = RM_ALIGN_UP(pageOffset + Size, pTempMemDesc->_pageSize); + + // Check for integer overflow + if (tmpSize < pageOffset + Size) + { + return NV_ERR_INVALID_ARGUMENT; + } } // Allocate the new MEMORY_DESCRIPTOR @@ -3388,7 +3401,7 @@ void memdescPrintMemdesc NvU64 memdescGetPageOffset ( MEMORY_DESCRIPTOR *pMemDesc, - NvU32 pageSize + NvU64 pageSize ) { NV_ASSERT(!memdescHasSubDeviceMemDescs(pMemDesc)); @@ -3877,7 +3890,7 @@ NV_ADDRESS_SPACE memdescGetAddressSpace(PMEMORY_DESCRIPTOR pMemDesc) * * @returns Current page size. */ -NvU32 memdescGetPageSize +NvU64 memdescGetPageSize64 ( PMEMORY_DESCRIPTOR pMemDesc, ADDRESS_TRANSLATION addressTranslation @@ -3887,6 +3900,19 @@ NvU32 memdescGetPageSize return pMemDesc->_pageSize; } +NvU32 memdescGetPageSize +( + PMEMORY_DESCRIPTOR pMemDesc, + ADDRESS_TRANSLATION addressTranslation +) +{ + NV_ASSERT(!memdescHasSubDeviceMemDescs(pMemDesc)); + NV_ASSERT(pMemDesc->_pageSize <= NV_U32_MAX); + if (pMemDesc->_pageSize > NV_U32_MAX) + DBG_BREAKPOINT(); + return (NvU32)pMemDesc->_pageSize; +} + /*! * @brief Set page size * @@ -3900,7 +3926,7 @@ void memdescSetPageSize ( PMEMORY_DESCRIPTOR pMemDesc, ADDRESS_TRANSLATION addressTranslation, - NvU32 pageSize + NvU64 pageSize ) { NV_ASSERT(!memdescHasSubDeviceMemDescs(pMemDesc)); @@ -4183,7 +4209,7 @@ void memdescCheckSubDevicePageSizeConsistency SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) pTempMemDesc = memdescGetMemDescFromGpu(pMemDesc, pGpu); - tempPageSize = memdescGetPageSize(pTempMemDesc, VAS_ADDRESS_TRANSLATION(pVAS)); + tempPageSize = memdescGetPageSize64(pTempMemDesc, VAS_ADDRESS_TRANSLATION(pVAS)); tempPageOffset = memdescGetPhysAddr(pTempMemDesc, VAS_ADDRESS_TRANSLATION(pVAS), 0) & (tempPageSize - 1); // Assert if inconsistent @@ -4544,6 +4570,12 @@ memdescSendMemDescToGSP(OBJGPU *pGpu, MEMORY_DESCRIPTOR *pMemDesc, NvHandle *pHa RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); NV_MEMORY_LIST_ALLOCATION_PARAMS listAllocParams = {0}; + // Nothing to do without GSP + if (!IS_GSP_CLIENT(pGpu)) + { + return NV_OK; + } + switch (memdescGetAddressSpace(pMemDesc)) { diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c index 38ae20fec..bf4bd33cc 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c @@ -43,6 +43,7 @@ #include "class/cl0040.h" // NV01_MEMORY_LOCAL_USER #include "class/cl503c.h" #include "class/cl906f.h" // GF100_CHANNEL_GPFIFO +#include "os/os.h" static NV_STATUS _memmgrCreateFBSR(MemoryManager *pMemoryManager, NvU32); static NV_STATUS _memmgrCreateChildObjects(MemoryManager *pMemoryManager); @@ -108,7 +109,7 @@ _memmgrInitRegistryOverrides(OBJGPU *pGpu, MemoryManager *pMemoryManager) NvU32 data32; // Check for ram size override. - pMemoryManager->Ram.fbOverrideSizeMb = ~0; + pMemoryManager->Ram.fbOverrideSizeMb = (NvU64)~0; if ((osReadRegistryDword(pGpu, NV_REG_STR_OVERRIDE_FB_SIZE, &data32) == NV_OK) && (data32 != 0)) { @@ -266,6 +267,16 @@ memmgrStatePreInitLocked_IMPL MemoryManager *pMemoryManager ) { + if (IS_GSP_CLIENT(pGpu)) + { + // + // Temporary hack to get OpenRM working without breaking SLI + // After fixing CORERM-4078, memmgrInitFbRegions() call should be removed from memsysStateInitLocked() + // and only left here + // + NV_ASSERT_OK_OR_RETURN(memmgrInitFbRegions(pGpu, pMemoryManager)); + } + // Determine the size of reserved memory NV_ASSERT_OK_OR_RETURN(memmgrPreInitReservedMemory_HAL(pGpu, pMemoryManager)); @@ -283,19 +294,10 @@ memmgrStateInitLocked_IMPL NvU32 i; NvBool bDynamicPageOffliningDisable = NV_FALSE; - if (IS_GSP_CLIENT(pGpu)) - { - // - // Temporary hack to get OpenRM working without breaking SLI - // After fixing CORERM-4078, memmgrInitFbRegions() call should be removed from memsysStateInitLocked() - // and only left here - // - NV_ASSERT_OK_OR_RETURN(memmgrInitFbRegions(pGpu, pMemoryManager)); - } - NV_ASSERT_OK_OR_RETURN(memmgrInitReservedMemory_HAL(pGpu, pMemoryManager, pMemoryManager->Ram.fbAddrSpaceSizeMb << 20)); _memmgrInitRegistryOverrides(pGpu, pMemoryManager); + // // Enable dynamic page blacklisting at this point before we call CreateHeap // since it internally calls heapGetBlacklistPages which depends on this property @@ -430,6 +432,7 @@ memmgrStatePreUnload_IMPL NvU32 flags ) { + NV_ASSERT((flags & GPU_STATE_FLAGS_PRESERVING) || pMemoryManager->zbcSurfaces == 0); return NV_OK; @@ -1090,7 +1093,7 @@ memmgrFillMemdescForPhysAttr_IMPL return NV_OK; } -NvU32 +NvU64 memmgrDeterminePageSize_IMPL ( MemoryManager *pMemoryManager, @@ -1107,7 +1110,7 @@ memmgrDeterminePageSize_IMPL NV_ADDRESS_SPACE addrSpace; NvBool bIsBigPageSupported; RM_ATTR_PAGE_SIZE pageSizeAttr; - NvU32 pageSize = 0; + NvU64 pageSize = 0; if (pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY) || (pKernelGmmu == NULL)) { @@ -1670,6 +1673,7 @@ NV_STATUS memmgrFree_IMPL portMemSet(pFbAllocInfo, 0, sizeof(FB_ALLOC_INFO)); portMemSet(pFbAllocPageFormat, 0, sizeof(FB_ALLOC_PAGE_FORMAT)); + pFbAllocInfo->hClient = hClient; pFbAllocInfo->pageFormat = pFbAllocPageFormat; // @@ -1916,7 +1920,10 @@ memmgrSetPartitionableMem_IMPL NV_ASSERT_OR_RETURN(!rangeIsEmpty(pMemoryManager->MIGMemoryPartitioningInfo.partitionableMemoryRange), NV_ERR_INVALID_STATE); - NV_ASSERT_OK_OR_RETURN(memmgrSetMIGPartitionableBAR1Range(pGpu, pMemoryManager)); + if (!KBUS_CPU_VISIBLE_BAR12_DISABLED(pGpu)) + { + NV_ASSERT_OK_OR_RETURN(memmgrSetMIGPartitionableBAR1Range(pGpu, pMemoryManager)); + } if (IS_GSP_CLIENT(pGpu)) { @@ -1938,7 +1945,7 @@ memmgrFillComprInfo_IMPL ( OBJGPU *pGpu, MemoryManager *pMemoryManager, - NvU32 pageSize, + NvU64 pageSize, NvU32 pageCount, NvU32 kind, NvU64 surfOffset, @@ -1961,7 +1968,7 @@ memmgrFillComprInfo_IMPL pComprInfo->compPageShift = pMemorySystemConfig->comprPageShift; pComprInfo->compTagLineMin = compTagStartOffset; pComprInfo->compPageIndexLo = (NvU32)(surfOffset >> pComprInfo->compPageShift); - pComprInfo->compPageIndexHi = (NvU32)((surfOffset + (NvU64)pageSize * (NvU64)pageCount - 1) >> pComprInfo->compPageShift); + pComprInfo->compPageIndexHi = (NvU32)((surfOffset + pageSize * pageCount - 1) >> pComprInfo->compPageShift); pComprInfo->compTagLineMultiplier = 1; return NV_OK; @@ -2027,23 +2034,6 @@ memmgrGetKindComprFromMemDesc_IMPL offset, kind, pComprInfo); } -NvBool -memmgrIsCompressible_IMPL -( - MemoryManager *pMemoryManager, - MEMORY_DESCRIPTOR *pMemDesc -) -{ - COMPR_INFO comprInfo; - NvU32 kind; - - NV_CHECK_OR_RETURN(LEVEL_ERROR, - memmgrGetKindComprFromMemDesc(pMemoryManager, pMemDesc, 0, &kind, &comprInfo) == NV_OK, - NV_FALSE); - - return memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_COMPRESSIBLE, comprInfo.kind); -} - void memmgrSetMIGPartitionableMemoryRange_IMPL ( @@ -2077,12 +2067,17 @@ memmgrSetMIGPartitionableBAR1Range_IMPL { KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); OBJVASPACE *pBar1VAS = kbusGetBar1VASpace_HAL(pGpu, pKernelBus); - OBJEHEAP *pVASHeap = vaspaceGetHeap(pBar1VAS); + OBJEHEAP *pVASHeap; NvU64 largestFreeOffset = 0; NvU64 largestFreeSize = 0; NvU64 partitionableBar1Start; NvU64 partitionableBar1End; + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ZERO_FB)) + return NV_OK; + + pVASHeap = vaspaceGetHeap(pBar1VAS); + // Get partitionable BAR1 range pVASHeap->eheapInfo(pVASHeap, NULL, NULL, &largestFreeOffset, &largestFreeSize, NULL, NULL); @@ -2151,58 +2146,63 @@ memmgrAllocMIGGPUInstanceMemory_PF // // Only allocate memory for non swizzID-0 GPU instances as swizzID-0 owns full - // gpu and there is no need to pre-reserve memory for that + // gpu and there is no need to pre-reserve memory for that and non + // coherent systems. In coherent NUMA systems, NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE + // is not supported and the memory comes from the MIG partition memory + // NUMA node. // if (kmigmgrIsMemoryPartitioningNeeded_HAL(pGpu, pKernelMIGManager, swizzId)) { - // - // Allocate memory using vidHeapControl - // - // vidHeapControl calls should happen outside GPU locks - // This is a PMA requirement as memory allocation calls may invoke eviction - // which UVM could get stuck behind GPU lock - // See Bug 1735851-#24 - // - rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); - - // Allocate gpfifo entries - NV_MEMORY_ALLOCATION_PARAMS memAllocParams; - portMemSet(&memAllocParams, 0, sizeof(NV_MEMORY_ALLOCATION_PARAMS)); - memAllocParams.owner = HEAP_OWNER_RM_CLIENT_GENERIC; - memAllocParams.type = NVOS32_TYPE_IMAGE; - memAllocParams.size = rangeLength(*pAddrRange); - memAllocParams.attr = DRF_DEF(OS32, _ATTR, _LOCATION, _VIDMEM); - memAllocParams.attr |= DRF_DEF(OS32, _ATTR, _PHYSICALITY, _CONTIGUOUS); - memAllocParams.attr |= DRF_DEF(OS32, _ATTR, _PAGE_SIZE, _DEFAULT); - memAllocParams.attr2 = DRF_DEF(OS32, _ATTR2, _PAGE_OFFLINING, _OFF); // free the offlined pages - memAllocParams.flags |= NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE; - memAllocParams.rangeLo = 0; - memAllocParams.rangeHi = 0; - memAllocParams.offset = pAddrRange->lo; // Offset needed if fixed address allocation - memAllocParams.hVASpace = 0; // Physical allocation - memAllocParams.internalflags = NVOS32_ALLOC_INTERNAL_FLAGS_SKIP_SCRUB; - - rmStatus = pRmApi->Alloc(pRmApi, - pMemoryManager->MIGMemoryPartitioningInfo.hClient, - pMemoryManager->MIGMemoryPartitioningInfo.hSubdevice, - &hMemory, - NV01_MEMORY_LOCAL_USER, - &memAllocParams); - - // Reaquire the GPU locks - if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_MEM) != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "failed to grab RM-Lock\n"); - DBG_BREAKPOINT(); - rmStatus = NV_ERR_GENERIC; - goto cleanup; - } + // + // Allocate memory using vidHeapControl + // + // vidHeapControl calls should happen outside GPU locks + // This is a PMA requirement as memory allocation calls may invoke eviction + // which UVM could get stuck behind GPU lock + // See Bug 1735851-#24 + // + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); - if (rmStatus != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "Unable to allocate physical memory for GPU instance.\n"); - return rmStatus; + // Allocate gpfifo entries + NV_MEMORY_ALLOCATION_PARAMS memAllocParams; + portMemSet(&memAllocParams, 0, sizeof(NV_MEMORY_ALLOCATION_PARAMS)); + memAllocParams.owner = HEAP_OWNER_RM_CLIENT_GENERIC; + memAllocParams.type = NVOS32_TYPE_IMAGE; + memAllocParams.size = rangeLength(*pAddrRange); + memAllocParams.attr = DRF_DEF(OS32, _ATTR, _LOCATION, _VIDMEM); + memAllocParams.attr |= DRF_DEF(OS32, _ATTR, _PHYSICALITY, _CONTIGUOUS); + memAllocParams.attr |= DRF_DEF(OS32, _ATTR, _PAGE_SIZE, _DEFAULT); + memAllocParams.attr2 = DRF_DEF(OS32, _ATTR2, _PAGE_OFFLINING, _OFF); // free the offlined pages + memAllocParams.flags |= NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE; + memAllocParams.rangeLo = 0; + memAllocParams.rangeHi = 0; + memAllocParams.offset = pAddrRange->lo; // Offset needed if fixed address allocation + memAllocParams.hVASpace = 0; // Physical allocation + memAllocParams.internalflags = NVOS32_ALLOC_INTERNAL_FLAGS_SKIP_SCRUB; + + rmStatus = pRmApi->Alloc(pRmApi, + pMemoryManager->MIGMemoryPartitioningInfo.hClient, + pMemoryManager->MIGMemoryPartitioningInfo.hSubdevice, + &hMemory, + NV01_MEMORY_LOCAL_USER, + &memAllocParams); + + // Reaquire the GPU locks + if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_MEM) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed to grab RM-Lock\n"); + DBG_BREAKPOINT(); + rmStatus = NV_ERR_GENERIC; + goto cleanup; + } + + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to allocate physical memory for GPU instance.\n"); + return rmStatus; + } } } rmStatus = _memmgrInitMIGMemoryPartitionHeap(pGpu, pMemoryManager, swizzId, pAddrRange, ppMemoryPartitionHeap); @@ -2239,6 +2239,8 @@ _memmgrInitMIGMemoryPartitionHeap NV_STATUS status = NV_OK; KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); Heap *pMemoryPartitionHeap = NULL; + NvU64 partitionBaseAddr = pAddrRange->lo; + NvU64 partitionSize = rangeLength(*pAddrRange); // Use default heap for swizzID-0 as we don't prereserve memory for swizzID-0 NV_ASSERT_OR_RETURN(pKernelMIGManager != NULL, NV_ERR_INVALID_STATE); @@ -2267,12 +2269,13 @@ _memmgrInitMIGMemoryPartitionHeap status, memmgrPmaInitialize(pGpu, pMemoryManager, &pMemoryPartitionHeap->pmaObject), fail); + } NV_ASSERT_OK_OR_GOTO( status, - heapInit(pGpu, pMemoryPartitionHeap, pAddrRange->lo, - rangeLength(*pAddrRange), + heapInit(pGpu, pMemoryPartitionHeap, partitionBaseAddr, + partitionSize, HEAP_TYPE_PARTITION_LOCAL, GPU_GFID_PF, NULL), @@ -2332,7 +2335,6 @@ memmgrFreeMIGGPUInstanceMemory_IMPL KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); NV_ASSERT_OR_RETURN(pKernelMIGManager != NULL, NV_ERR_INVALID_STATE); - NV_CHECK_OR_RETURN(LEVEL_SILENT, hMemory != NV01_NULL_OBJECT, NV_OK); // Nothing to do for swizzId 0 as we neither allocate memory nor allocate new heap object if (!kmigmgrIsMemoryPartitioningNeeded_HAL(pGpu, pKernelMIGManager, swizzId)) @@ -2342,7 +2344,10 @@ memmgrFreeMIGGPUInstanceMemory_IMPL *ppMemoryPartitionHeap = NULL; // Free allocated memory - pRmApi->Free(pRmApi, pMemoryManager->MIGMemoryPartitioningInfo.hClient, hMemory); + if ((hMemory != NV01_NULL_OBJECT)) + { + pRmApi->Free(pRmApi, pMemoryManager->MIGMemoryPartitioningInfo.hClient, hMemory); + } return NV_OK; } @@ -2541,6 +2546,7 @@ memmgrPmaInitialize_IMPL if (bNumaEnabled) { + NvU32 numaSkipReclaimVal = NV_REG_STR_RM_NUMA_ALLOC_SKIP_RECLAIM_PERCENTAGE_DEFAULT; if (osReadRegistryDword(pGpu, NV_REG_STR_RM_NUMA_ALLOC_SKIP_RECLAIM_PERCENTAGE, &numaSkipReclaimVal) == NV_OK) @@ -2551,6 +2557,7 @@ memmgrPmaInitialize_IMPL } } pmaNumaSetReclaimSkipThreshold(pPma, numaSkipReclaimVal); + } return NV_OK; @@ -3077,4 +3084,4 @@ memmgrGetVgpuHostRmReservedFb_KERNEL ¶ms, sizeof(params))); return params.hostReservedFb; -} \ No newline at end of file +} diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_pwr_mgmt.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_pwr_mgmt.c index 3198a7775..a39f43d08 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_pwr_mgmt.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_pwr_mgmt.c @@ -43,7 +43,6 @@ memmgrSavePowerMgmtState_KERNEL ) { NvU32 fbsrStartMode = pMemoryManager->fbsrStartMode; - NvBool bGcOffState = NV_FALSE; NvU32 i; OBJFBSR *pFbsr; NV_STATUS rmStatus = NV_OK; @@ -63,12 +62,14 @@ memmgrSavePowerMgmtState_KERNEL // might fail is not enough non-paged memory available. // pMemoryManager->pActiveFbsr = NULL; + // // Iterate the heap at top level to avoid inconsistent between // several pFbsr instance. // - rmStatus = memmgrAddMemNodes(pGpu, pMemoryManager, bGcOffState); + rmStatus = memmgrAddMemNodes(pGpu, pMemoryManager, + pGpu->getProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERING)); if ((rmStatus == NV_OK) && memmgrIsPmaInitialized(pMemoryManager)) @@ -77,7 +78,7 @@ memmgrSavePowerMgmtState_KERNEL RANGELISTTYPE *pSaveList = NULL; RANGELISTTYPE *pSaveCurr; - if (bGcOffState) + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERING)) { rmStatus = pmaBuildAllocatedBlocksList(&pHeap->pmaObject, &pSaveList); } @@ -112,7 +113,7 @@ memmgrSavePowerMgmtState_KERNEL } } - if (bGcOffState) + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERING)) { pmaFreeAllocatedBlocksList(&pHeap->pmaObject, &pSaveList); } diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_utils.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_utils.c index 8caa66380..35f4acdd1 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_utils.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_utils.c @@ -615,8 +615,28 @@ memmgrMemBeginTransfer_IMPL switch (transferType) { case TRANSFER_TYPE_PROCESSOR: + if (flags & TRANSFER_FLAGS_USE_BAR1) + { + NvP64 pPriv; + NvU32 protect = NV_PROTECT_READ_WRITE; + + if (flags & TRANSFER_FLAGS_MAP_PROTECT_READABLE) + { + protect = NV_PROTECT_READABLE; + } + else if (flags & TRANSFER_FLAGS_MAP_PROTECT_WRITEABLE) + { + protect = NV_PROTECT_WRITEABLE; + } + + NV_ASSERT_OR_RETURN(memdescMap(pMemDesc, offset, memSz, NV_TRUE, protect, + (NvP64*) &pPtr, &pPriv) == NV_OK, NULL); + memdescSetKernelMappingPriv(pMemDesc, pPtr); + break; + } NV_ASSERT_OR_RETURN((pPtr = memdescMapInternal(pGpu, pMemDesc, flags)) != NULL, NULL); pPtr = &pPtr[offset]; + break; case TRANSFER_TYPE_GSP_DMA: case TRANSFER_TYPE_CE: @@ -669,6 +689,13 @@ memmgrMemEndTransfer_IMPL switch (transferType) { case TRANSFER_TYPE_PROCESSOR: + if (flags & TRANSFER_FLAGS_USE_BAR1) + { + NvP64 pPriv = memdescGetKernelMappingPriv(pMemDesc); + memdescSetKernelMappingPriv(pMemDesc, NULL); + memdescUnmap(pMemDesc, NV_TRUE, 0, pMapping, pPriv); + return; + } memdescUnmapInternal(pGpu, pMemDesc, flags); return; case TRANSFER_TYPE_GSP_DMA: @@ -743,7 +770,7 @@ memmgrAllocResources_IMPL NV_ADDRESS_SPACE addrSpace = memmgrAllocGetAddrSpace(pMemoryManager, pVidHeapAlloc->flags, pFbAllocInfo->retAttr); - NvU32 pageSize = 0; + NvU64 pageSize = 0; NvBool bAllocedHwRes = NV_FALSE; // IRQL TEST: must be running at equivalent of passive-level @@ -1003,6 +1030,15 @@ memUtilsMemSetNoBAR2(OBJGPU *pGpu, PMEMORY_DESCRIPTOR pMemDesc, NvU8 value) switch (memdescGetAddressSpace(pMemDesc)) { case ADDR_FBMEM: + if (KBUS_BAR0_PRAMIN_DISABLED(pGpu)) + { + NvU8 *pMap = kbusMapRmAperture_HAL(pGpu, pMemDesc); + NV_ASSERT_OR_RETURN(pMap != NULL, NV_ERR_INSUFFICIENT_RESOURCES); + portMemSet(pMap, value, pMemDesc->Size); + kbusUnmapRmAperture_HAL(pGpu, pMemDesc, &pMap, NV_TRUE); + + break; + } // // Set the BAR0 window to encompass the given surface while // saving off the location to where the BAR0 window was diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/method_notification.c b/src/nvidia/src/kernel/gpu/mem_mgr/method_notification.c index 12e512f37..be05353a7 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/method_notification.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/method_notification.c @@ -551,6 +551,7 @@ NV_STATUS semaphoreFillGPUVATimestamp ) { NvU64 semaphoreGPUVA; + NvU64 semaphoreGPUVAOffset; CLI_DMA_MAPPING_INFO *pDmaMappingInfo; NvU64 offset; NvU32 timeHi, timeLo; @@ -570,8 +571,11 @@ NV_STATUS semaphoreFillGPUVATimestamp if (status != NV_OK) return status; - if (!portSafeAddU64(SemaphoreGPUVABase, - (NvU64) (Index * sizeof(NvGpuSemaphore)), + if (!portSafeMulU64((NvU64) Index, + (NvU64) sizeof(NvGpuSemaphore), + &semaphoreGPUVAOffset) || + !portSafeAddU64(SemaphoreGPUVABase, + semaphoreGPUVAOffset, &semaphoreGPUVA)) { return NV_ERR_INVALID_ARGUMENT; diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c index 58e09cc7e..66da55152 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c @@ -471,17 +471,18 @@ NV_STATUS pmaNumaAllocate ) { NvU32 i; - NV_STATUS status = NV_OK; - NvU32 numaNodeId = pPma->numaNodeId; + NV_STATUS status = NV_OK; + NvU32 numaNodeId = pPma->numaNodeId; NvS32 regionList[PMA_REGION_SIZE]; - NvU32 flags = allocationOptions->flags; - NvLength allocSize = 0; - NvLength allocCount = 0; - NvU32 contigFlag = !!(flags & PMA_ALLOCATE_CONTIGUOUS); + NvU32 flags = allocationOptions->flags; + NvLength allocSize = 0; + NvLength allocCount = 0; + NvU32 contigFlag = !!(flags & PMA_ALLOCATE_CONTIGUOUS); // As per bug #2444368, kernel scrubbing is too slow. Use the GPU scrubber instead - NvBool bScrubOnAlloc = !(flags & PMA_ALLOCATE_NO_ZERO); - NvBool allowEvict = !(flags & PMA_ALLOCATE_DONT_EVICT); - NvBool partialFlag = !!(flags & PMA_ALLOCATE_ALLOW_PARTIAL); + NvBool bScrubOnAlloc = !(flags & PMA_ALLOCATE_NO_ZERO); + NvBool allowEvict = !(flags & PMA_ALLOCATE_DONT_EVICT); + NvBool partialFlag = !!(flags & PMA_ALLOCATE_ALLOW_PARTIAL); + NvBool bSkipScrubFlag = !!(flags & PMA_ALLOCATE_NO_ZERO); NvU64 finalAllocatedCount = 0; @@ -517,7 +518,13 @@ NV_STATUS pmaNumaAllocate // We are not changing the state. Can be outside the lock perhaps NV_CHECK_OK_OR_RETURN(LEVEL_FATAL, pmaSelector(pPma, allocationOptions, regionList)); - if (pPma->bScrubOnFree) + // + // Scrub on free is enabled for this allocation request if the feature is enabled and the + // caller does not want to skip scrubber. + // Caller may want to skip scrubber when it knows the memory is zero'ed or when we are + // initializing RM structures needed by the scrubber itself. + // + if (pPma->bScrubOnFree && !bSkipScrubFlag) { portSyncMutexAcquire(pPma->pAllocLock); portSyncRwLockAcquireRead(pPma->pScrubberValidLock); @@ -632,7 +639,7 @@ NV_STATUS pmaNumaAllocate portSyncSpinlockRelease(pPma->pPmaLock); - if (pPma->bScrubOnFree) + if (pPma->bScrubOnFree && !bSkipScrubFlag) { portSyncRwLockReleaseRead(pPma->pScrubberValidLock); portSyncMutexRelease(pPma->pAllocLock); diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c b/src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c index 576262a54..bff1ca062 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c @@ -43,7 +43,6 @@ /* ------------------ static and helper functions prototypes------------------*/ static NvU32 translateAllocFlagsToVASpaceFlags(NvU32 allocFlags, NvU32 *translatedFlags); static NvU32 translatePageSizeToVASpaceFlags(NV_VASPACE_ALLOCATION_PARAMETERS *pNvVASpaceAllocParams); -static void destroyMemDesc(Device *pDevice, NvHandle hVASpace); static NV_STATUS _vaspaceapiManagePageLevelsForSplitVaSpace(OBJGPU *pGpu, NvHandle hClient, NvU32 gpuMask, NvU32 flags, VASPACEAPI_MANAGE_PAGE_LEVELS_ACTION action); NvBool @@ -522,7 +521,6 @@ vaspaceapiDestruct_IMPL(VaSpaceApi *pVaspaceApi) VASPACEAPI_MANAGE_PAGE_LEVELS_RELEASE); } - destroyMemDesc(pDevice, hVASpace); if ((vaspaceGetFlags(pVaspaceApi->pVASpace) & VASPACE_FLAGS_FLA)) { if (GPU_GET_KERNEL_BUS(pGpu)->flaInfo.pFlaVAS == NULL) @@ -561,52 +559,6 @@ skip_destroy: pCallContext->pResourceRef->pParentRef); } -/*--------------------------static and helper functions ----------------------*/ -// move this to Device -/** - * @brief Destroy associated memory with this vaspace. - * - * @param[in] pDevice Pointer to Device instance - * @param[in] hVASpace VASpace handle of the vaspace that will be deleted - **/ -static void -destroyMemDesc -( - Device *pDevice, - NvHandle hVASpace -) -{ - VirtualMemory *pVirtualMemory = NULL; - RsClient *pClient = RES_GET_CLIENT(pDevice); - NODE *pNode = NULL; - RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - - // - // RS-TODO: Convert to resource server dependency tracking system. - // stdmemConstruct calls add refAddDependant() but does it work properly for - // sharing (?) - // - - // Check if any memory linked to this VASpace hasn't been freed. - btreeEnumStart(0, &pNode, pDevice->DevMemoryTable); - while (pNode != NULL) - { - Memory *pMemory = pNode->Data; - pVirtualMemory = dynamicCast(pMemory, VirtualMemory); - btreeEnumNext(&pNode, pDevice->DevMemoryTable); - - if ((pVirtualMemory != NULL) && - virtmemMatchesVASpace(pVirtualMemory, pClient->hClient, hVASpace)) - { - // Free hMemory - pRmApi->Free(pRmApi, pClient->hClient, RES_GET_HANDLE(pVirtualMemory)); - - // Restart iteration as memory will be freed. - btreeEnumStart(0, &pNode, pDevice->DevMemoryTable); - } - } -} - /** * @brief Translate flags to vaspace equivalent flags and perform error check. * diff --git a/src/nvidia/src/kernel/gpu/mem_sys/arch/ampere/kern_mem_sys_ga100.c b/src/nvidia/src/kernel/gpu/mem_sys/arch/ampere/kern_mem_sys_ga100.c index eda94d20f..4e1f9f509 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/arch/ampere/kern_mem_sys_ga100.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/arch/ampere/kern_mem_sys_ga100.c @@ -90,6 +90,8 @@ kmemsysInitFlushSysmemBuffer_GA100 // if (pKernelMemorySystem->pSysmemFlushBufferMemDesc == NULL) { + NvU64 flags = MEMDESC_FLAGS_NONE; + // // Sysmem flush buffer // The sysmembar flush does a zero byte read of sysmem if there was a @@ -103,7 +105,7 @@ kmemsysInitFlushSysmemBuffer_GA100 NV_TRUE, ADDR_SYSMEM, NV_MEMORY_UNCACHED, - MEMDESC_FLAGS_NONE); + flags); if (status != NV_OK) return status; diff --git a/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c b/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c index 268644cd3..8cbb874cf 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c @@ -171,6 +171,7 @@ kmemsysDestruct_IMPL KernelMemorySystem *pKernelMemorySystem ) { + pKernelMemorySystem->sysmemFlushBuffer = 0; memdescFree(pKernelMemorySystem->pSysmemFlushBufferMemDesc); memdescDestroy(pKernelMemorySystem->pSysmemFlushBufferMemDesc); @@ -582,35 +583,42 @@ kmemsysSetupCoherentCpuLink_IMPL NvU64 memblockSize = 0; NvU64 numaOnlineBase = 0; NvU64 numaOnlineSize = 0; + NvU64 fbSize = (pMemoryManager->Ram.fbTotalMemSizeMb << 20); NvU32 data32; NvBool bCpuMapping = NV_TRUE; // Default enable + NvS32 numaNodeId = NV0000_CTRL_NO_NUMA_NODE; { NV_ASSERT_OK_OR_RETURN(kmemsysGetFbNumaInfo_HAL(pGpu, pKernelMemorySystem, &pKernelMemorySystem->coherentCpuFbBase, - &pGpu->numaNodeId)); + &numaNodeId)); if (pKernelMemorySystem->coherentCpuFbBase != 0) { - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS params = {0}; + { + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS params = {0}; - NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, - pGpu->hInternalClient, - pGpu->hInternalSubdevice, - NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE, - ¶ms, - sizeof(NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS))); - pKernelMemorySystem->coherentCpuFbEnd = pKernelMemorySystem->coherentCpuFbBase + - params.coherentFbApertureSize; + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE, + ¶ms, + sizeof(NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS))); + // + // Indirect peer(uses P9 to reach other GV100) in P9+GV100 requires coherentCpuFbEnd to + // also include the entire FB AMAP range even when FB size is less than the FB AMAP size. + // + pKernelMemorySystem->coherentCpuFbEnd = pKernelMemorySystem->coherentCpuFbBase + + params.coherentFbApertureSize; + } } } if ((osReadRegistryDword(pGpu, NV_REG_STR_OVERRIDE_GPU_NUMA_NODE_ID, &data32)) == NV_OK) { - pGpu->numaNodeId = (NvS32)data32; - NV_PRINTF(LEVEL_ERROR, "Override GPU NUMA node ID %d!\n", - pGpu->numaNodeId); + numaNodeId = (NvS32)data32; + NV_PRINTF(LEVEL_ERROR, "Override GPU NUMA node ID %d!\n", numaNodeId); } // Parse regkey here @@ -629,6 +637,20 @@ kmemsysSetupCoherentCpuLink_IMPL return NV_OK; } + NV_ASSERT_OK_OR_RETURN(osNumaMemblockSize(&memblockSize)); + + // + // Online all of FB memory less the unaligned memblock chunk that also + // contains the RM reserved memory. + // + // TODO: make sure the onlineable memory is aligned to memblockSize + // Currently, if we have leftover memory, it'll just be wasted because no + // one can access it. If FB size itself is memblock size unaligned(because + // of CBC and row remapper deductions), then the memory wastage is unavoidable. + // + numaOnlineSize = NV_ALIGN_UP64(fbSize - memblockSize, memblockSize); + pGpu->numaNodeId = numaNodeId; + NV_ASSERT_OK_OR_RETURN(kbusCreateCoherentCpuMapping_HAL(pGpu, pKernelBus, bFlush)); // Switch the toggle for coherent link mapping only if migration is successful @@ -650,13 +672,11 @@ kmemsysSetupCoherentCpuLink_IMPL totalResvBytes += memmgrGetRsvdMemorySize(pMemoryManager); // - // Online all of FB memory less reserved memory, aligned to memblock + // Assumption: RM reserved memory fits within the last unaligned memblock + // size chunk and this assert check is to ensure the same. // - // TODO: make sure the onlineable memory is aligned to memblockSize - // Currently, if we have leftover memory, it'll just be wasted because no - // one can access it - // - numaOnlineSize = NV_ALIGN_DOWN(pMemoryManager->Ram.fbUsableMemSize - totalResvBytes, memblockSize); + NV_ASSERT_OR_RETURN(totalResvBytes < (fbSize - numaOnlineSize), NV_ERR_INVALID_STATE); + NV_PRINTF(LEVEL_INFO, "NUMA reserved memory size: 0x%llx online memory size: 0x%llx\n", totalResvBytes, numaOnlineSize); @@ -728,3 +748,4 @@ kmemsysGetUsableFbSize_KERNEL { return kmemsysReadUsableFbSize_HAL(pGpu, pKernelMemorySystem, pFbSize); } + diff --git a/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys_ctrl.c b/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys_ctrl.c index ab356cfef..24688c846 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys_ctrl.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys_ctrl.c @@ -1070,9 +1070,10 @@ subdeviceCtrlCmdFbSetZbcReferenced_IMPL NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS *pParams ) { - OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); NvU32 gfid; + NV_STATUS status = NV_OK; NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfid)); @@ -1081,7 +1082,6 @@ subdeviceCtrlCmdFbSetZbcReferenced_IMPL if (IS_VIRTUAL(pGpu) || IS_GSP_CLIENT(pGpu)) { RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; - NV_STATUS status = NV_OK; NV_RM_RPC_CONTROL(pGpu, pRmCtrlParams->hClient, @@ -1094,7 +1094,7 @@ subdeviceCtrlCmdFbSetZbcReferenced_IMPL return status; } - return NV_OK; + return status; } /*! diff --git a/src/nvidia/src/kernel/gpu/mig_mgr/gpu_instance_subscription.c b/src/nvidia/src/kernel/gpu/mig_mgr/gpu_instance_subscription.c index 9def54ebe..9261f1139 100644 --- a/src/nvidia/src/kernel/gpu/mig_mgr/gpu_instance_subscription.c +++ b/src/nvidia/src/kernel/gpu/mig_mgr/gpu_instance_subscription.c @@ -125,6 +125,12 @@ gisubscriptionConstruct_IMPL return NV_ERR_NOT_SUPPORTED; } + // + // Disable RMCTRL Cache before subscribe to GPU instance. + // RMCTRL-CACHE-TODO: remove the workaround when CORERM-5016 is done. + // + rmapiControlCacheSetMode(NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE); + // // Root-SwizzID is a special swizzID which doesn't have any GPU instance // associated with it. It can be subscribed to even without GPU instances diff --git a/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c b/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c index c884c5d11..6afb42b48 100644 --- a/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c +++ b/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c @@ -2223,14 +2223,15 @@ kmigmgrEnableAllLCEs_IMPL } /*! - * @brief Retrieves instance(s) associated with a client, if applicable + * @brief Retrieves instance(s) associated with a device, if applicable */ NV_STATUS -kmigmgrGetInstanceRefFromClient_IMPL +kmigmgrGetInstanceRefFromDevice_IMPL ( OBJGPU *pGpu, KernelMIGManager *pKernelMIGManager, NvHandle hClient, + NvHandle hDevice, MIG_INSTANCE_REF *pRef ) { @@ -2252,7 +2253,7 @@ kmigmgrGetInstanceRefFromClient_IMPL NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, hClient, &pRsClient)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - subdeviceGetByGpu(pRsClient, pGpu, &pSubdevice)); + subdeviceGetByInstance(pRsClient, hDevice, 0, &pSubdevice)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, gisubscriptionGetGPUInstanceSubscription(pRsClient, RES_GET_HANDLE(pSubdevice), @@ -2281,14 +2282,48 @@ kmigmgrGetInstanceRefFromClient_IMPL } /*! - * @brief Retrieves GPU instance heap associated with a client, if applicable + * @brief Retrieves instance(s) associated with a client, if applicable */ NV_STATUS -kmigmgrGetMemoryPartitionHeapFromClient_IMPL +kmigmgrGetInstanceRefFromClient_IMPL +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager, + NvHandle hClient, + MIG_INSTANCE_REF *pRef +) +{ + RsClient *pRsClient; + Device *pDevice; + + NV_ASSERT_OR_RETURN(pRef != NULL, NV_ERR_INVALID_ARGUMENT); + *pRef = kmigmgrMakeNoMIGReference(); + + if (!IS_MIG_IN_USE(pGpu)) + { + return NV_ERR_INVALID_STATE; + } + + NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, hClient, &pRsClient)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + deviceGetByGpu(pRsClient, pGpu, NV_TRUE, &pDevice)); + + return kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + hClient, RES_GET_HANDLE(pDevice), + pRef); +} + +/*! + * @brief Retrieves GPU instance heap associated with a device, if applicable + */ +NV_STATUS +kmigmgrGetMemoryPartitionHeapFromDevice_IMPL ( OBJGPU *pGpu, KernelMIGManager *pKernelMIGManager, NvHandle hClient, + NvHandle hDevice, Heap **ppMemoryPartitionHeap ) { @@ -2297,7 +2332,7 @@ kmigmgrGetMemoryPartitionHeapFromClient_IMPL NV_ASSERT_OR_RETURN(IS_MIG_IN_USE(pGpu), NV_ERR_INVALID_STATE); - rmStatus = kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref); + rmStatus = kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, hClient, hDevice, &ref); if ((rmStatus != NV_OK) || !kmigmgrIsMIGReferenceValid(&ref)) { RS_PRIV_LEVEL privLevel = rmclientGetCachedPrivilegeByHandle(hClient); @@ -2330,6 +2365,33 @@ kmigmgrGetMemoryPartitionHeapFromClient_IMPL return rmStatus; } +/*! + * @brief Retrieves GPU instance heap associated with a client, if applicable + */ +NV_STATUS +kmigmgrGetMemoryPartitionHeapFromClient_IMPL +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager, + NvHandle hClient, + Heap **ppMemoryPartitionHeap +) +{ + RsClient *pRsClient; + Device *pDevice; + + NV_ASSERT_OR_RETURN(IS_MIG_IN_USE(pGpu), NV_ERR_INVALID_STATE); + + NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, hClient, &pRsClient)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + deviceGetByGpu(pRsClient, pGpu, NV_TRUE, &pDevice)); + + return kmigmgrGetMemoryPartitionHeapFromDevice(pGpu, pKernelMIGManager, + hClient, RES_GET_HANDLE(pDevice), + ppMemoryPartitionHeap); +} + /*! * @brief Retrieves swizzid associated with a client, if applicable */ @@ -3222,6 +3284,8 @@ kmigmgrSaveComputeInstances_IMPL { pComputeInstanceSave->ciInfo.gpcMask = DRF_MASK(pMIGComputeInstance->resourceAllocation.gpcCount - 1 : 0); } + + pComputeInstanceSave->ciInfo.gfxGpcCount = pMIGComputeInstance->resourceAllocation.gfxGpcCount; pComputeInstanceSave->ciInfo.veidOffset = pMIGComputeInstance->resourceAllocation.veidOffset; pComputeInstanceSave->ciInfo.veidCount = pMIGComputeInstance->resourceAllocation.veidCount; pComputeInstanceSave->ciInfo.smCount = pMIGComputeInstance->resourceAllocation.smCount; @@ -3482,12 +3546,6 @@ kmigmgrCreateComputeInstances_VF (params.type == KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS_TYPE_REQUEST) ? params.inst.request.pReqComputeInstanceInfo[CIIdx].sharedEngFlag : params.inst.restore.pComputeInstanceSave->ciInfo.sharedEngFlags; - NvU32 grCount; - NvU32 ceCount; - NvU32 decCount; - NvU32 encCount; - NvU32 jpgCount; - NvU32 ofaCount; NvU32 spanStart; NvU32 ctsId; @@ -3592,112 +3650,214 @@ kmigmgrCreateComputeInstances_VF remainingGpcCount -= pCIProfile->gpcCount; } - if (params.type == KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS_TYPE_REQUEST) - { - grCount = 1; - ceCount = params.inst.request.pReqComputeInstanceInfo[CIIdx].ceCount; - decCount = params.inst.request.pReqComputeInstanceInfo[CIIdx].nvDecCount; - encCount = params.inst.request.pReqComputeInstanceInfo[CIIdx].nvEncCount; - jpgCount = params.inst.request.pReqComputeInstanceInfo[CIIdx].nvJpgCount; - ofaCount = params.inst.request.pReqComputeInstanceInfo[CIIdx].ofaCount; - } - else + if (params.type == KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS_TYPE_RESTORE) { ENGTYPE_BIT_VECTOR engines; + bitVectorClrAll(&pResourceAllocation->engines); - bitVectorFromRaw(&engines, + // Set engines requested directly in resource allocation mask + bitVectorFromRaw(&pResourceAllocation->engines, params.inst.restore.pComputeInstanceSave->ciInfo.enginesMask, sizeof(params.inst.restore.pComputeInstanceSave->ciInfo.enginesMask)); - grCount = kmigmgrCountEnginesOfType(&engines, - RM_ENGINE_TYPE_GR(0)); + // Sanity check that all engines requested exist in the GI engine mask + bitVectorClrAll(&engines); + bitVectorAnd(&engines, &pResourceAllocation->engines, &pKernelMIGGpuInstance->resourceAllocation.localEngines); + NV_CHECK_OR_ELSE(LEVEL_ERROR, + bitVectorTestEqual(&engines, &pResourceAllocation->engines), + status = NV_ERR_INVALID_ARGUMENT; goto done;); - ceCount = kmigmgrCountEnginesOfType(&engines, - RM_ENGINE_TYPE_COPY(0)); + // Set Shared/Exclusive Engine Masks for GRs restored + bitVectorClrAll(&engines); + bitVectorSetRange(&engines, RM_ENGINE_RANGE_GR()); + bitVectorAnd(&engines, &engines, &pResourceAllocation->engines); - decCount = kmigmgrCountEnginesOfType(&engines, - RM_ENGINE_TYPE_NVDEC(0)); + // Only 1 GR can be requested per compute instance + NV_CHECK_OR_ELSE(LEVEL_ERROR, + (kmigmgrCountEnginesOfType(&engines, RM_ENGINE_TYPE_GR(0)) == 1), + status = NV_ERR_INVALID_ARGUMENT; goto done;); - encCount = kmigmgrCountEnginesOfType(&engines, - RM_ENGINE_TYPE_NVENC(0)); + if ((pMIGComputeInstance->sharedEngFlag & NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NONE) != 0x0) + bitVectorOr(&shadowSharedEngMask, &shadowSharedEngMask, &engines); + else + { + ENGTYPE_BIT_VECTOR tempVector; - jpgCount = kmigmgrCountEnginesOfType(&engines, - RM_ENGINE_TYPE_NVJPEG(0)); + // Exclusive engine mask should not intersect with the current exclusive mask + bitVectorAnd(&tempVector, &engines, &shadowExclusiveEngMask); + NV_CHECK_OR_ELSE(LEVEL_ERROR, + bitVectorTestAllCleared(&tempVector), + status = NV_ERR_STATE_IN_USE; goto done;); + bitVectorOr(&shadowExclusiveEngMask, &shadowExclusiveEngMask, &engines); + } - ofaCount = kmigmgrCountEnginesOfType(&engines, - RM_ENGINE_TYPE_OFA); + // Set Shared/Exclusive Engine Masks for CEs restored + bitVectorClrAll(&engines); + bitVectorSetRange(&engines, RM_ENGINE_RANGE_COPY()); + bitVectorAnd(&engines, &engines, &pResourceAllocation->engines); + if ((pMIGComputeInstance->sharedEngFlag & NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_CE) != 0x0) + bitVectorOr(&shadowSharedEngMask, &shadowSharedEngMask, &engines); + else + { + ENGTYPE_BIT_VECTOR tempVector; - NV_ASSERT(grCount == 1); + // Exclusive engine mask should not intersect with the current exclusive mask + bitVectorAnd(&tempVector, &engines, &shadowExclusiveEngMask); + NV_CHECK_OR_ELSE(LEVEL_ERROR, + bitVectorTestAllCleared(&tempVector), + status = NV_ERR_STATE_IN_USE; goto done;); + bitVectorOr(&shadowExclusiveEngMask, &shadowExclusiveEngMask, &engines); + } + + // Set Shared/Exclusive Engine Masks for NVDECs restored + bitVectorClrAll(&engines); + bitVectorSetRange(&engines, RM_ENGINE_RANGE_NVDEC()); + bitVectorAnd(&engines, &engines, &pResourceAllocation->engines); + if ((pMIGComputeInstance->sharedEngFlag & NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NVDEC) != 0x0) + bitVectorOr(&shadowSharedEngMask, &shadowSharedEngMask, &engines); + else + { + ENGTYPE_BIT_VECTOR tempVector; + + // Exclusive engine mask should not intersect with the current exclusive mask + bitVectorAnd(&tempVector, &engines, &shadowExclusiveEngMask); + NV_CHECK_OR_ELSE(LEVEL_ERROR, + bitVectorTestAllCleared(&tempVector), + status = NV_ERR_STATE_IN_USE; goto done;); + bitVectorOr(&shadowExclusiveEngMask, &shadowExclusiveEngMask, &engines); + } + + // Set Shared/Exclusive Engine Masks for NVENCs restored + bitVectorClrAll(&engines); + bitVectorSetRange(&engines, RM_ENGINE_RANGE_NVENC()); + bitVectorAnd(&engines, &engines, &pResourceAllocation->engines); + if ((pMIGComputeInstance->sharedEngFlag & NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NVENC) != 0x0) + bitVectorOr(&shadowSharedEngMask, &shadowSharedEngMask, &engines); + else + { + ENGTYPE_BIT_VECTOR tempVector; + + // Exclusive engine mask should not intersect with the current exclusive mask + bitVectorAnd(&tempVector, &engines, &shadowExclusiveEngMask); + NV_CHECK_OR_ELSE(LEVEL_ERROR, + bitVectorTestAllCleared(&tempVector), + status = NV_ERR_STATE_IN_USE; goto done;); + bitVectorOr(&shadowExclusiveEngMask, &shadowExclusiveEngMask, &engines); + } + + // Set Shared/Exclusive Engine Masks for NVJPEGs restored + bitVectorClrAll(&engines); + bitVectorSetRange(&engines, RM_ENGINE_RANGE_NVJPEG()); + bitVectorAnd(&engines, &engines, &pResourceAllocation->engines); + if ((pMIGComputeInstance->sharedEngFlag & NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NVJPG) != 0x0) + bitVectorOr(&shadowSharedEngMask, &shadowSharedEngMask, &engines); + else + { + ENGTYPE_BIT_VECTOR tempVector; + + // Exclusive engine mask should not intersect with the current exclusive mask + bitVectorAnd(&tempVector, &engines, &shadowExclusiveEngMask); + NV_CHECK_OR_ELSE(LEVEL_ERROR, + bitVectorTestAllCleared(&tempVector), + status = NV_ERR_STATE_IN_USE; goto done;); + bitVectorOr(&shadowExclusiveEngMask, &shadowExclusiveEngMask, &engines); + } + + // Set Shared/Exclusive Engine Masks for OFAs restored + bitVectorClrAll(&engines); + bitVectorSetRange(&engines, rangeMake(RM_ENGINE_TYPE_OFA, RM_ENGINE_TYPE_OFA)); + bitVectorAnd(&engines, &engines, &pResourceAllocation->engines); + if ((pMIGComputeInstance->sharedEngFlag & NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_OFA) != 0x0) + bitVectorOr(&shadowSharedEngMask, &shadowSharedEngMask, &engines); + else + { + ENGTYPE_BIT_VECTOR tempVector; + + // Exclusive engine mask should not intersect with the current exclusive mask + bitVectorAnd(&tempVector, &engines, &shadowExclusiveEngMask); + NV_CHECK_OR_ELSE(LEVEL_ERROR, + bitVectorTestAllCleared(&tempVector), + status = NV_ERR_STATE_IN_USE; goto done;); + bitVectorOr(&shadowExclusiveEngMask, &shadowExclusiveEngMask, &engines); + } } + else + { + NvU32 grCount = 1; + NvU32 ceCount = params.inst.request.pReqComputeInstanceInfo[CIIdx].ceCount; + NvU32 decCount = params.inst.request.pReqComputeInstanceInfo[CIIdx].nvDecCount; + NvU32 encCount = params.inst.request.pReqComputeInstanceInfo[CIIdx].nvEncCount; + NvU32 jpgCount = params.inst.request.pReqComputeInstanceInfo[CIIdx].nvJpgCount; + NvU32 ofaCount = params.inst.request.pReqComputeInstanceInfo[CIIdx].ofaCount; - bitVectorClrAll(&pResourceAllocation->engines); + bitVectorClrAll(&pResourceAllocation->engines); - // Allocate the GR engines for this compute instance - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - kmigmgrAllocateInstanceEngines(&pKernelMIGGpuInstance->resourceAllocation.engines, - ((pMIGComputeInstance->sharedEngFlag & - NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NONE) != 0x0), - RM_ENGINE_RANGE_GR(), - grCount, - &pResourceAllocation->engines, - &shadowExclusiveEngMask, - &shadowSharedEngMask), done); + // Allocate the GR engines for this compute instance + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kmigmgrAllocateInstanceEngines(&pKernelMIGGpuInstance->resourceAllocation.engines, + ((pMIGComputeInstance->sharedEngFlag & + NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NONE) != 0x0), + RM_ENGINE_RANGE_GR(), + grCount, + &pResourceAllocation->engines, + &shadowExclusiveEngMask, + &shadowSharedEngMask), done); - // Allocate the Copy engines for this compute instance - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - kmigmgrAllocateInstanceEngines(&pKernelMIGGpuInstance->resourceAllocation.engines, - ((pMIGComputeInstance->sharedEngFlag & - NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_CE) != 0x0), - RM_ENGINE_RANGE_COPY(), - ceCount, - &pResourceAllocation->engines, - &shadowExclusiveEngMask, - &shadowSharedEngMask), done); + // Allocate the Copy engines for this compute instance + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kmigmgrAllocateInstanceEngines(&pKernelMIGGpuInstance->resourceAllocation.engines, + ((pMIGComputeInstance->sharedEngFlag & + NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_CE) != 0x0), + RM_ENGINE_RANGE_COPY(), + ceCount, + &pResourceAllocation->engines, + &shadowExclusiveEngMask, + &shadowSharedEngMask), done); - // Allocate the NVDEC engines for this compute instance - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - kmigmgrAllocateInstanceEngines(&pKernelMIGGpuInstance->resourceAllocation.engines, - ((pMIGComputeInstance->sharedEngFlag & - NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NVDEC) != 0x0), - RM_ENGINE_RANGE_NVDEC(), - decCount, - &pResourceAllocation->engines, - &shadowExclusiveEngMask, - &shadowSharedEngMask), done); + // Allocate the NVDEC engines for this compute instance + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kmigmgrAllocateInstanceEngines(&pKernelMIGGpuInstance->resourceAllocation.engines, + ((pMIGComputeInstance->sharedEngFlag & + NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NVDEC) != 0x0), + RM_ENGINE_RANGE_NVDEC(), + decCount, + &pResourceAllocation->engines, + &shadowExclusiveEngMask, + &shadowSharedEngMask), done); - // Allocate the NVENC engines for this compute instance - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - kmigmgrAllocateInstanceEngines(&pKernelMIGGpuInstance->resourceAllocation.engines, - ((pMIGComputeInstance->sharedEngFlag & - NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NVENC) != 0x0), - RM_ENGINE_RANGE_NVENC(), - encCount, - &pResourceAllocation->engines, - &shadowExclusiveEngMask, - &shadowSharedEngMask), done); + // Allocate the NVENC engines for this compute instance + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kmigmgrAllocateInstanceEngines(&pKernelMIGGpuInstance->resourceAllocation.engines, + ((pMIGComputeInstance->sharedEngFlag & + NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NVENC) != 0x0), + RM_ENGINE_RANGE_NVENC(), + encCount, + &pResourceAllocation->engines, + &shadowExclusiveEngMask, + &shadowSharedEngMask), done); - // Allocate the NVJPG engines for this compute instance - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - kmigmgrAllocateInstanceEngines(&pKernelMIGGpuInstance->resourceAllocation.engines, - ((pMIGComputeInstance->sharedEngFlag & - NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NVJPG) != 0x0), - RM_ENGINE_RANGE_NVJPEG(), - jpgCount, - &pResourceAllocation->engines, - &shadowExclusiveEngMask, - &shadowSharedEngMask), done); - - // Allocate the NVOFA engines for this compute instance - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - kmigmgrAllocateInstanceEngines(&pKernelMIGGpuInstance->resourceAllocation.engines, - ((pMIGComputeInstance->sharedEngFlag & - NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_OFA) != 0x0), - rangeMake(RM_ENGINE_TYPE_OFA, RM_ENGINE_TYPE_OFA), - ofaCount, - &pResourceAllocation->engines, - &shadowExclusiveEngMask, - &shadowSharedEngMask), done); + // Allocate the NVJPG engines for this compute instance + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kmigmgrAllocateInstanceEngines(&pKernelMIGGpuInstance->resourceAllocation.engines, + ((pMIGComputeInstance->sharedEngFlag & + NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NVJPG) != 0x0), + RM_ENGINE_RANGE_NVJPEG(), + jpgCount, + &pResourceAllocation->engines, + &shadowExclusiveEngMask, + &shadowSharedEngMask), done); + // Allocate the NVOFA engines for this compute instance + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kmigmgrAllocateInstanceEngines(&pKernelMIGGpuInstance->resourceAllocation.engines, + ((pMIGComputeInstance->sharedEngFlag & + NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_OFA) != 0x0), + rangeMake(RM_ENGINE_TYPE_OFA, RM_ENGINE_TYPE_OFA), + ofaCount, + &pResourceAllocation->engines, + &shadowExclusiveEngMask, + &shadowSharedEngMask), done); + } // Cache local mask of engine IDs for this compute instance kmigmgrGetLocalEngineMask(&pResourceAllocation->engines, @@ -4029,7 +4189,7 @@ kmigmgrCreateComputeInstances_FWCLIENT pComputeResourceAllocation->gpcIds[(pComputeResourceAllocation->gpcCount)++] = gpcIdx; tempGpcMask &= ~(NVBIT32(gpcIdx)); } - + pComputeResourceAllocation->gfxGpcCount = info.gfxGpcCount; pComputeResourceAllocation->veidCount = info.veidCount; pComputeResourceAllocation->veidOffset = info.veidOffset; pComputeResourceAllocation->smCount = info.smCount; @@ -6717,10 +6877,9 @@ kmigmgrGetNextComputeSize_IMPL for (i = 1; i < NV_ARRAY_ELEMENTS(computeSizeFlags) - 1; i++) if (computeSizeFlags[i] == computeSize) - return (bGetNextSmallest) ? computeSizeFlags[i + 1] : computeSizeFlags[i - 1]; + break; - // Requested input flag was not found - return KMIGMGR_COMPUTE_SIZE_INVALID; + return (bGetNextSmallest) ? computeSizeFlags[i + 1] : computeSizeFlags[i - 1]; } } @@ -7389,4 +7548,3 @@ kmigmgrIsCTSIdAvailable_IMPL FOR_EACH_INDEX_IN_MASK_END; return !!((ctsIdValidMask & ~invalidMask) & NVBIT64(ctsId)); } - diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_gh100.c b/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_gh100.c index bb47d1d37..57b1ae469 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_gh100.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_gh100.c @@ -25,6 +25,8 @@ #include "gpu/mmu/kern_gmmu.h" #include "gpu/mem_mgr/mem_mgr.h" +#include "vgpu/vgpu_events.h" +#include "nv_sriov_defines.h" #include "mmu/gmmu_fmt.h" #include "published/hopper/gh100/dev_mmu.h" @@ -340,3 +342,63 @@ kgmmuGetGraphicsEngineId_GH100 { return NV_PFAULT_MMU_ENG_ID_GRAPHICS; } + +NV_STATUS +kgmmuGetFaultRegisterMappings_GH100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU32 index, + NvP64 *pFaultBufferGet, + NvP64 *pFaultBufferPut, + NvP64 *pFaultBufferInfo, + NvP64 *pHubIntr, + NvP64 *pHubIntrEnSet, + NvP64 *pHubIntrEnClear, + NvU32 *faultMask, + NvP64 *pPrefetchCtrl +) +{ + return kgmmuGetFaultRegisterMappings_TU102(pGpu, pKernelGmmu, index, + pFaultBufferGet, pFaultBufferPut, + pFaultBufferInfo, pHubIntr, + pHubIntrEnSet, pHubIntrEnClear, + faultMask, pPrefetchCtrl); +} + +NV_STATUS +kgmmuFaultBufferAllocSharedMemory_GH100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + FAULT_BUFFER_TYPE index +) +{ + return NV_OK; +} + +void +kgmmuFaultBufferFreeSharedMemory_GH100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + FAULT_BUFFER_TYPE index +) +{ + return; +} + +/* + * @brief GSP client can use this function to initiate a replayable fault buffer flush when the + * HW fault buffer is owned by GSP. + */ +NV_STATUS +kgmmuIssueReplayableFaultBufferFlush_GH100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu +) +{ + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_tu102.c b/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_tu102.c index df95330a7..b65b95470 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_tu102.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_tu102.c @@ -420,7 +420,7 @@ kgmmuIsNonReplayableFaultPending_TU102 void kgmmuClearNonReplayableFaultIntr_TU102 ( - POBJGPU pGpu, + OBJGPU *pGpu, KernelGmmu *pKernelGmmu, THREAD_STATE_NODE *pThreadState ) diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/volta/kern_gmmu_gv100.c b/src/nvidia/src/kernel/gpu/mmu/arch/volta/kern_gmmu_gv100.c index c0fcb170c..1681a864b 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/volta/kern_gmmu_gv100.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/volta/kern_gmmu_gv100.c @@ -89,7 +89,7 @@ kgmmuChangeReplayableFaultOwnership_GV100(OBJGPU *pGpu, KernelGmmu *pKernelGmmu, } /*! - * @brief Creates the shadow fault buffer for client handling of non-replayable faults + * @brief Creates the shadow fault buffer for client handling of replayable/non-replayable faults * * @param[in] pGpu * @param[in] pKernelGmmu @@ -99,8 +99,9 @@ kgmmuChangeReplayableFaultOwnership_GV100(OBJGPU *pGpu, KernelGmmu *pKernelGmmu, NV_STATUS kgmmuClientShadowFaultBufferAlloc_GV100 ( - OBJGPU *pGpu, - KernelGmmu *pKernelGmmu + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + FAULT_BUFFER_TYPE index ) { if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu)) @@ -112,7 +113,7 @@ kgmmuClientShadowFaultBufferAlloc_GV100 NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_STATE); } - return kgmmuClientShadowFaultBufferNonreplayableAllocate(pGpu, pKernelGmmu); + return kgmmuClientShadowFaultBufferAllocate(pGpu, pKernelGmmu, index); } /*! @@ -126,14 +127,15 @@ kgmmuClientShadowFaultBufferAlloc_GV100 NV_STATUS kgmmuClientShadowFaultBufferFree_GV100 ( - OBJGPU *pGpu, - KernelGmmu *pKernelGmmu + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + FAULT_BUFFER_TYPE index ) { if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu)) return NV_OK; - return kgmmuClientShadowFaultBufferNonreplayableDestroy(pGpu, pKernelGmmu); + return kgmmuClientShadowFaultBufferDestroy(pGpu, pKernelGmmu, index); } /*! diff --git a/src/nvidia/src/kernel/gpu/mmu/bar2_walk.c b/src/nvidia/src/kernel/gpu/mmu/bar2_walk.c index a3064aed9..9ce9db3f5 100644 --- a/src/nvidia/src/kernel/gpu/mmu/bar2_walk.c +++ b/src/nvidia/src/kernel/gpu/mmu/bar2_walk.c @@ -398,7 +398,8 @@ _bar2WalkCBUpdatePde } } } - else if (pKernelBus->bar2[gfid].bMigrating || IS_GFID_VF(gfid)) + else if (pKernelBus->bar2[gfid].bMigrating || IS_GFID_VF(gfid) || + KBUS_BAR0_PRAMIN_DISABLED(pGpu)) { if (ADDR_FBMEM == pKernelBus->PDEBAR2Aperture) { @@ -487,7 +488,8 @@ _bar2WalkCBLevelAlloc } // Specify which Page Level we are initializing. - if (pKernelBus->bar2[gfid].bBootstrap || pKernelBus->bar2[gfid].bMigrating || IS_GFID_VF(gfid)) + if (pKernelBus->bar2[gfid].bBootstrap || pKernelBus->bar2[gfid].bMigrating || IS_GFID_VF(gfid) || + KBUS_BAR0_PRAMIN_DISABLED(pGpu)) { if (pLevelFmt == pKernelBus->bar2[gfid].pFmt->pRoot) { @@ -521,7 +523,8 @@ _bar2WalkCBLevelAlloc } else { - NV_ASSERT(pKernelBus->bar2[gfid].bBootstrap || IS_GFID_VF(gfid)); + NV_ASSERT(pKernelBus->bar2[gfid].bBootstrap || IS_GFID_VF(gfid) || + KBUS_BAR0_PRAMIN_DISABLED(pGpu)); pdeBase = pKernelBus->bar2[gfid].pdeBase; pteBase = pKernelBus->bar2[gfid].pteBase; } @@ -600,12 +603,14 @@ _bar2WalkCBLevelAlloc } else { - NV_ASSERT(pKernelBus->bar2[gfid].bBootstrap || IS_GFID_VF(gfid)); + NV_ASSERT(pKernelBus->bar2[gfid].bBootstrap || IS_GFID_VF(gfid) || + KBUS_BAR0_PRAMIN_DISABLED(pGpu)); pKernelBus->bar2[gfid].pdeBase = memdescGetPhysAddr(pMemDesc, AT_GPU, 0); pKernelBus->bar2[gfid].pPDEMemDesc = pMemDesc; } } - if (pKernelBus->bar2[gfid].bBootstrap || pKernelBus->bar2[gfid].bMigrating || IS_GFID_VF(gfid)) + if (pKernelBus->bar2[gfid].bBootstrap || pKernelBus->bar2[gfid].bMigrating || IS_GFID_VF(gfid) || + KBUS_BAR0_PRAMIN_DISABLED(pGpu)) { pKernelBus->bar2[gfid].pageDirInit++; } @@ -680,13 +685,15 @@ _bar2WalkCBLevelAlloc } else { - NV_ASSERT(pKernelBus->bar2[gfid].bBootstrap || IS_GFID_VF(gfid)); + NV_ASSERT(pKernelBus->bar2[gfid].bBootstrap || IS_GFID_VF(gfid) || + KBUS_BAR0_PRAMIN_DISABLED(pGpu)); pKernelBus->bar2[gfid].pteBase = memdescGetPhysAddr(pMemDesc, AT_GPU, 0); } pKernelBus->virtualBar2[gfid].pPTEMemDesc = pMemDesc; } - if (pKernelBus->bar2[gfid].bBootstrap || pKernelBus->bar2[gfid].bMigrating || IS_GFID_VF(gfid)) + if (pKernelBus->bar2[gfid].bBootstrap || pKernelBus->bar2[gfid].bMigrating || IS_GFID_VF(gfid) || + KBUS_BAR0_PRAMIN_DISABLED(pGpu)) { pKernelBus->bar2[gfid].pageTblInit++; } diff --git a/src/nvidia/src/kernel/gpu/mmu/fault_buffer_ctrl.c b/src/nvidia/src/kernel/gpu/mmu/fault_buffer_ctrl.c index 037c9cfe5..919e655ce 100644 --- a/src/nvidia/src/kernel/gpu/mmu/fault_buffer_ctrl.c +++ b/src/nvidia/src/kernel/gpu/mmu/fault_buffer_ctrl.c @@ -57,7 +57,7 @@ faultbufCtrlCmdFaultbufferGetRegisterMappings_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pMmuFaultBuffer); KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); - return kgmmuGetFaultRegisterMappings_HAL(pGpu, pKernelGmmu, REPLAYABLE_FAULT_BUFFER, + return kgmmuGetFaultRegisterMappings_HAL(pGpu, pKernelGmmu, pParams->faultBufferType, &pParams->pFaultBufferGet, &pParams->pFaultBufferPut, &pParams->pFaultBufferInfo, diff --git a/src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c b/src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c index 0919c390a..701505370 100644 --- a/src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c +++ b/src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c @@ -191,15 +191,15 @@ NV_STATUS kgmmuStateInitLocked_IMPL static NV_STATUS _kgmmuCreateGlobalVASpace ( - POBJGPU pGpu, + OBJGPU *pGpu, KernelGmmu *pKernelGmmu, NvU32 flags ) { NvU32 constructFlags = VASPACE_FLAGS_NONE; - POBJVASPACE pGlobalVAS = NULL; + OBJVASPACE *pGlobalVAS = NULL; NV_STATUS rmStatus; - POBJGPUGRP pGpuGrp = NULL; + OBJGPUGRP *pGpuGrp = NULL; // Bail out early on sleep/suspend cases if (flags & GPU_STATE_FLAGS_PRESERVING) @@ -235,12 +235,12 @@ _kgmmuCreateGlobalVASpace static NV_STATUS _kgmmuDestroyGlobalVASpace ( - POBJGPU pGpu, + OBJGPU *pGpu, KernelGmmu *pKernelGmmu, NvU32 flags ) { - POBJGPUGRP pGpuGrp = NULL; + OBJGPUGRP *pGpuGrp = NULL; if (flags & GPU_STATE_FLAGS_PRESERVING) return NV_OK; @@ -926,23 +926,29 @@ kgmmuFaultBufferGetAddressSpace_IMPL { NvU32 faultBufferAddrSpace = ADDR_UNKNOWN; NvU32 faultBufferAttr = 0; + NvBool bAllocInVidmem = NV_FALSE; NV_ASSERT_OR_RETURN((index < NUM_FAULT_BUFFERS), NV_ERR_INVALID_ARGUMENT); if (index == NON_REPLAYABLE_FAULT_BUFFER) { - faultBufferAddrSpace = ADDR_SYSMEM; - faultBufferAttr = NV_MEMORY_CACHED; + faultBufferAddrSpace = bAllocInVidmem ? ADDR_FBMEM : ADDR_SYSMEM; + faultBufferAttr = bAllocInVidmem ? NV_MEMORY_UNCACHED : NV_MEMORY_CACHED; memdescOverrideInstLoc(DRF_VAL(_REG_STR_RM, _INST_LOC_3, _UVM_FAULT_BUFFER_NONREPLAYABLE, pGpu->instLocOverrides3), "UVM non-replayable fault", &faultBufferAddrSpace, &faultBufferAttr); } else if (index == REPLAYABLE_FAULT_BUFFER) { - faultBufferAddrSpace = ADDR_SYSMEM; - faultBufferAttr = NV_MEMORY_CACHED; + faultBufferAddrSpace = bAllocInVidmem ? ADDR_FBMEM : ADDR_SYSMEM; + faultBufferAttr = bAllocInVidmem ? NV_MEMORY_UNCACHED : NV_MEMORY_CACHED; memdescOverrideInstLoc(DRF_VAL(_REG_STR_RM, _INST_LOC_4, _UVM_FAULT_BUFFER_REPLAYABLE, pGpu->instLocOverrides4), "UVM replayable fault", &faultBufferAddrSpace, &faultBufferAttr); } + if (bAllocInVidmem && (faultBufferAddrSpace == ADDR_SYSMEM)) + { + NV_ASSERT(0); + return NV_ERR_INVALID_ARGUMENT; + } if (pFaultBufferAddrSpace != NULL) { @@ -983,7 +989,8 @@ kgmmuFaultBufferCreateMemDesc_IMPL return status; } - if (IS_VIRTUAL(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu)) + if ((IS_VIRTUAL(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu)) + ) { // Allocate contiguous fault buffers for SR-IOV Heavy isContiguous = NV_TRUE; @@ -1009,6 +1016,8 @@ kgmmuFaultBufferCreateMemDesc_IMPL memdescSetGpuCacheAttrib(pMemDesc, NV_MEMORY_UNCACHED); } + memdescSetPageSize(pMemDesc, AT_GPU, RM_PAGE_SIZE); + *ppMemDesc = pMemDesc; return NV_OK; @@ -1355,15 +1364,16 @@ _kgmmuClientShadowBufferQueueCopyData static NV_STATUS _kgmmuClientShadowFaultBufferQueueAllocate ( - OBJGPU *pGpu, - KernelGmmu *pKernelGmmu + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + FAULT_BUFFER_TYPE index ) { NV_STATUS status; GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuffer; MEMORY_DESCRIPTOR *pQueueMemDesc; - pClientShadowFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].clientShadowFaultBuffer; + pClientShadowFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].clientShadowFaultBuffer[index]; status = memdescCreate(&pQueueMemDesc, pGpu, sizeof(GMMU_SHADOW_FAULT_BUF), RM_PAGE_SIZE, @@ -1403,15 +1413,16 @@ _kgmmuClientShadowFaultBufferQueueAllocate void kgmmuClientShadowFaultBufferQueueDestroy_IMPL ( - OBJGPU *pGpu, - KernelGmmu *pKernelGmmu, - NvBool bFreeQueue + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvBool bFreeQueue, + FAULT_BUFFER_TYPE index ) { GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuffer; MEMORY_DESCRIPTOR *pQueueMemDesc; - pClientShadowFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].clientShadowFaultBuffer; + pClientShadowFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].clientShadowFaultBuffer[index]; pQueueMemDesc = pClientShadowFaultBuffer->pQueueMemDesc; @@ -1429,23 +1440,25 @@ kgmmuClientShadowFaultBufferQueueDestroy_IMPL static NV_STATUS _kgmmuClientShadowFaultBufferPagesAllocate ( - OBJGPU *pGpu, - KernelGmmu *pKernelGmmu, - NvU32 shadowFaultBufferSize + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU32 shadowFaultBufferSize, + FAULT_BUFFER_TYPE index ) { NV_STATUS status; GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuffer; MEMORY_DESCRIPTOR *pMemDesc; + NvU64 flags = MEMDESC_FLAGS_NONE; - pClientShadowFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].clientShadowFaultBuffer; + pClientShadowFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].clientShadowFaultBuffer[index]; shadowFaultBufferSize = RM_PAGE_ALIGN_UP(shadowFaultBufferSize); status = memdescCreate(&pMemDesc, pGpu, shadowFaultBufferSize, RM_PAGE_SIZE, NV_FALSE, ADDR_SYSMEM, NV_MEMORY_CACHED, - MEMDESC_FLAGS_NONE); + flags); if (status != NV_OK) { return status; @@ -1478,9 +1491,10 @@ _kgmmuClientShadowFaultBufferPagesAllocate void kgmmuClientShadowFaultBufferPagesDestroy_IMPL ( - OBJGPU *pGpu, - KernelGmmu *pKernelGmmu, - NvBool bFreePages + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvBool bFreePages, + FAULT_BUFFER_TYPE index ) { MEMORY_DESCRIPTOR *pMemDesc; @@ -1488,7 +1502,7 @@ kgmmuClientShadowFaultBufferPagesDestroy_IMPL GMMU_FAULT_BUFFER_PAGE *pBufferPage; NvU32 i; - pClientShadowFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].clientShadowFaultBuffer; + pClientShadowFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].clientShadowFaultBuffer[index]; pMemDesc = pClientShadowFaultBuffer->pBufferMemDesc; if (bFreePages) @@ -1517,11 +1531,12 @@ kgmmuClientShadowFaultBufferPagesDestroy_IMPL NV_STATUS kgmmuClientShadowFaultBufferRegister_IMPL ( - OBJGPU *pGpu, - KernelGmmu *pKernelGmmu + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + FAULT_BUFFER_TYPE index ) { - NV_STATUS status; + NV_STATUS status = NV_OK; struct GMMU_FAULT_BUFFER *pFaultBuffer; GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuffer; GMMU_SHADOW_FAULT_BUF *pQueue; @@ -1530,28 +1545,44 @@ kgmmuClientShadowFaultBufferRegister_IMPL NvU32 queueCapacity, numBufferPages; NvU32 faultBufferSize; const NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pStaticInfo = kgmmuGetStaticInfo(pGpu, pKernelGmmu); + NvBool bQueueAllocated = NV_FALSE; pFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF]; - pClientShadowFaultBuffer = &pFaultBuffer->clientShadowFaultBuffer; - faultBufferSize = pStaticInfo->nonReplayableFaultBufferSize; + pClientShadowFaultBuffer = &pFaultBuffer->clientShadowFaultBuffer[index]; - pQueue = KERNEL_POINTER_FROM_NvP64(GMMU_SHADOW_FAULT_BUF *, - pClientShadowFaultBuffer->pQueueAddress); - queueCapacity = faultBufferSize / NVC369_BUF_SIZE; - - status = queueInitNonManaged(pQueue, queueCapacity); - if (status != NV_OK) + if (index == NON_REPLAYABLE_FAULT_BUFFER) { - return status; + faultBufferSize = pStaticInfo->nonReplayableFaultBufferSize; + } + else if (index == REPLAYABLE_FAULT_BUFFER) + { + faultBufferSize = pStaticInfo->replayableFaultBufferSize; + } + else + { + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_ARGUMENT); + } + + { + pQueue = KERNEL_POINTER_FROM_NvP64(GMMU_SHADOW_FAULT_BUF *, + pClientShadowFaultBuffer->pQueueAddress); + queueCapacity = faultBufferSize / NVC369_BUF_SIZE; + + status = queueInitNonManaged(pQueue, queueCapacity); + if (status != NV_OK) + { + return status; + } + bQueueAllocated = NV_TRUE; } if (!IS_GSP_CLIENT(pGpu)) { portSyncSpinlockAcquire(pFaultBuffer->pShadowFaultBufLock); - if (pFaultBuffer->pClientShadowFaultBuffer == NULL) + if (pFaultBuffer->pClientShadowFaultBuffer[index] == NULL) { - pFaultBuffer->pClientShadowFaultBuffer = pClientShadowFaultBuffer; + pFaultBuffer->pClientShadowFaultBuffer[index] = pClientShadowFaultBuffer; } else { @@ -1562,7 +1593,8 @@ kgmmuClientShadowFaultBufferRegister_IMPL if (status != NV_OK) { - queueDestroy(pQueue); + if (bQueueAllocated) + queueDestroy(pQueue); return status; } } @@ -1574,7 +1606,8 @@ kgmmuClientShadowFaultBufferRegister_IMPL pParams = portMemAllocNonPaged(sizeof(*pParams)); if (pParams == NULL) { - queueDestroy(pQueue); + if (bQueueAllocated) + queueDestroy(pQueue); return NV_ERR_NO_MEMORY; } portMemSet(pParams, 0, sizeof(*pParams)); @@ -1584,20 +1617,25 @@ kgmmuClientShadowFaultBufferRegister_IMPL if (numBufferPages > NV_ARRAY_ELEMENTS(pParams->shadowFaultBufferPteArray)) { portMemFree(pParams); - queueDestroy(pQueue); + if (bQueueAllocated) + queueDestroy(pQueue); return NV_ERR_BUFFER_TOO_SMALL; } - shadowFaultBufferQueuePhysAddr = memdescGetPhysAddr(pClientShadowFaultBuffer->pQueueMemDesc, - AT_GPU, 0); - memdescGetPhysAddrs(pBufferMemDesc, AT_GPU, 0, RM_PAGE_SIZE, numBufferPages, pParams->shadowFaultBufferPteArray); - pParams->shadowFaultBufferQueuePhysAddr = shadowFaultBufferQueuePhysAddr; - pParams->shadowFaultBufferSize = faultBufferSize; + { + shadowFaultBufferQueuePhysAddr = memdescGetPhysAddr(pClientShadowFaultBuffer->pQueueMemDesc, + AT_GPU, 0); + pParams->shadowFaultBufferQueuePhysAddr = shadowFaultBufferQueuePhysAddr; + } + pParams->shadowFaultBufferSize = faultBufferSize; + pParams->shadowFaultBufferType = (index == NON_REPLAYABLE_FAULT_BUFFER) ? + NV2080_CTRL_FAULT_BUFFER_NON_REPLAYABLE : + NV2080_CTRL_FAULT_BUFFER_REPLAYABLE; status = pRmApi->Control(pRmApi, pGpu->hInternalClient, @@ -1608,11 +1646,12 @@ kgmmuClientShadowFaultBufferRegister_IMPL portMemFree(pParams); if (status != NV_OK) { - queueDestroy(pQueue); + if (bQueueAllocated) + queueDestroy(pQueue); return status; } - pFaultBuffer->pClientShadowFaultBuffer = pClientShadowFaultBuffer; + pFaultBuffer->pClientShadowFaultBuffer[index] = pClientShadowFaultBuffer; } return NV_OK; @@ -1621,8 +1660,9 @@ kgmmuClientShadowFaultBufferRegister_IMPL void kgmmuClientShadowFaultBufferUnregister_IMPL ( - OBJGPU *pGpu, - KernelGmmu *pKernelGmmu + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + FAULT_BUFFER_TYPE index ) { NV_STATUS status = NV_OK; @@ -1636,52 +1676,65 @@ kgmmuClientShadowFaultBufferUnregister_IMPL { portSyncSpinlockAcquire(pFaultBuffer->pShadowFaultBufLock); - pFaultBuffer->pClientShadowFaultBuffer = NULL; + pFaultBuffer->pClientShadowFaultBuffer[index] = NULL; portSyncSpinlockRelease(pFaultBuffer->pShadowFaultBufLock); } else { RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS params; + + portMemSet(¶ms, 0, sizeof(params)); + + params.shadowFaultBufferType = (index == NON_REPLAYABLE_FAULT_BUFFER) ? + NV2080_CTRL_FAULT_BUFFER_NON_REPLAYABLE : + NV2080_CTRL_FAULT_BUFFER_REPLAYABLE; status = pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER, - NULL, 0); + ¶ms, sizeof(params)); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, - "Unregistering Replayable Fault buffer failed (status=0x%08x), proceeding...\n", + "Unregistering %s fault buffer failed (status=0x%08x), proceeding...\n", + (index == NON_REPLAYABLE_FAULT_BUFFER) ? "non-replayable" : "replayable", status); } - pFaultBuffer->pClientShadowFaultBuffer = NULL; + pFaultBuffer->pClientShadowFaultBuffer[index] = NULL; } - pClientShadowFaultBuffer = &pFaultBuffer->clientShadowFaultBuffer; - pQueue = KERNEL_POINTER_FROM_NvP64(GMMU_SHADOW_FAULT_BUF *, - pClientShadowFaultBuffer->pQueueAddress); - queueDestroy(pQueue); + { + pClientShadowFaultBuffer = &pFaultBuffer->clientShadowFaultBuffer[index]; + pQueue = KERNEL_POINTER_FROM_NvP64(GMMU_SHADOW_FAULT_BUF *, + pClientShadowFaultBuffer->pQueueAddress); + queueDestroy(pQueue); + } } /*! - * @brief Creates shadow fault buffer for client handling of non-replayable + * @brief Creates shadow fault buffer for client handling of replayable/non-replayable * faults in the CPU-RM, and registers it in the GSP-RM. * * @param[in] pGpu * @param[in] pKernelGmmu + * @param[in] index Replayable or non-replayable fault buffer * * @returns */ NV_STATUS -kgmmuClientShadowFaultBufferNonreplayableAllocate_IMPL +kgmmuClientShadowFaultBufferAllocate_IMPL ( - OBJGPU *pGpu, - KernelGmmu *pKernelGmmu + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + FAULT_BUFFER_TYPE index ) { NV_STATUS status; const NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pStaticInfo = kgmmuGetStaticInfo(pGpu, pKernelGmmu); + NvU32 faultBufferSize; ct_assert((RM_PAGE_SIZE % sizeof(struct GMMU_FAULT_PACKET)) == 0); @@ -1689,31 +1742,56 @@ kgmmuClientShadowFaultBufferNonreplayableAllocate_IMPL NV_ASSERT_OR_RETURN(pStaticInfo->nonReplayableFaultBufferSize != 0, NV_ERR_INVALID_STATE); - status = _kgmmuClientShadowFaultBufferQueueAllocate(pGpu, pKernelGmmu); + if (index == NON_REPLAYABLE_FAULT_BUFFER) + { + faultBufferSize = pStaticInfo->nonReplayableFaultBufferSize; + } + else if (index == REPLAYABLE_FAULT_BUFFER) + { + faultBufferSize = pStaticInfo->replayableFaultBufferSize; + } + else + { + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_ARGUMENT); + } + + status = _kgmmuClientShadowFaultBufferQueueAllocate(pGpu, pKernelGmmu, index); if (status != NV_OK) { return status; } status = _kgmmuClientShadowFaultBufferPagesAllocate(pGpu, pKernelGmmu, - pStaticInfo->nonReplayableFaultBufferSize); + faultBufferSize, + index); if (status != NV_OK) { goto destroy_queue_and_exit; } - status = kgmmuClientShadowFaultBufferRegister(pGpu, pKernelGmmu); + status = kgmmuFaultBufferAllocSharedMemory_HAL(pGpu, pKernelGmmu, index); if (status != NV_OK) { goto destroy_pages_and_exit; } + status = kgmmuClientShadowFaultBufferRegister(pGpu, pKernelGmmu, + index); + if (status != NV_OK) + { + goto destroy_shared_memory_and_exit; + } + return NV_OK; +destroy_shared_memory_and_exit: + kgmmuFaultBufferFreeSharedMemory_HAL(pGpu, pKernelGmmu, index); destroy_pages_and_exit: - kgmmuClientShadowFaultBufferPagesDestroy(pGpu, pKernelGmmu, NV_TRUE); + kgmmuClientShadowFaultBufferPagesDestroy(pGpu, pKernelGmmu, NV_TRUE, + index); destroy_queue_and_exit: - kgmmuClientShadowFaultBufferQueueDestroy(pGpu, pKernelGmmu, NV_TRUE); + kgmmuClientShadowFaultBufferQueueDestroy(pGpu, pKernelGmmu, NV_TRUE, + index); return status; } @@ -1727,23 +1805,30 @@ destroy_queue_and_exit: * @returns */ NV_STATUS -kgmmuClientShadowFaultBufferNonreplayableDestroy_IMPL +kgmmuClientShadowFaultBufferDestroy_IMPL ( - OBJGPU *pGpu, - KernelGmmu *pKernelGmmu + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + FAULT_BUFFER_TYPE index ) { GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuffer; NvBool bFreeMemory = !RMCFG_FEATURE_PLATFORM_GSP; - pClientShadowFaultBuffer = pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer; + pClientShadowFaultBuffer = + pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer[index]; if (pClientShadowFaultBuffer != NvP64_NULL) { - kgmmuClientShadowFaultBufferUnregister(pGpu, pKernelGmmu); + kgmmuClientShadowFaultBufferUnregister(pGpu, pKernelGmmu, + index); - kgmmuClientShadowFaultBufferPagesDestroy(pGpu, pKernelGmmu, bFreeMemory); - kgmmuClientShadowFaultBufferQueueDestroy(pGpu, pKernelGmmu, bFreeMemory); + kgmmuFaultBufferFreeSharedMemory_HAL(pGpu, pKernelGmmu, index); + + kgmmuClientShadowFaultBufferPagesDestroy(pGpu, pKernelGmmu, bFreeMemory, + index); + kgmmuClientShadowFaultBufferQueueDestroy(pGpu, pKernelGmmu, bFreeMemory, + index); } return NV_OK; @@ -1953,15 +2038,22 @@ kgmmuRegisterIntrService_IMPL ) { NvU32 engineIdx; + NvU16 *pEngineIdxList; + NvU32 listSize; static NvU16 engineIdxList[] = { MC_ENGINE_IDX_REPLAYABLE_FAULT, MC_ENGINE_IDX_REPLAYABLE_FAULT_ERROR, }; - for (NvU32 tableIdx = 0; tableIdx < NV_ARRAY_ELEMENTS32(engineIdxList); tableIdx++) { - engineIdx = engineIdxList[tableIdx]; + pEngineIdxList = engineIdxList; + listSize = NV_ARRAY_ELEMENTS32(engineIdxList); + } + + for (NvU32 tableIdx = 0; tableIdx < listSize; tableIdx++) + { + engineIdx = (pEngineIdxList)[tableIdx]; NV_ASSERT(pRecords[engineIdx].pInterruptService == NULL); pRecords[engineIdx].pInterruptService = staticCast(pKernelGmmu, IntrService); } diff --git a/src/nvidia/src/kernel/gpu/mmu/mmu_fault_buffer.c b/src/nvidia/src/kernel/gpu/mmu/mmu_fault_buffer.c index 438ebfc02..9ef6bc07d 100644 --- a/src/nvidia/src/kernel/gpu/mmu/mmu_fault_buffer.c +++ b/src/nvidia/src/kernel/gpu/mmu/mmu_fault_buffer.c @@ -54,12 +54,6 @@ faultbufConstruct_IMPL return NV_ERR_INVALID_CLASS; } - if (pCallContext->secInfo.privLevel < RS_PRIV_LEVEL_KERNEL) - { - NV_PRINTF(LEVEL_ERROR, "Client is not privileged\n"); - return NV_ERR_INSUFFICIENT_PERMISSIONS; - } - NV_ASSERT_OR_RETURN(pKernelGmmu != NULL, NV_ERR_NOT_SUPPORTED); status = kgmmuFaultBufferReplayableAllocate(pGpu, pKernelGmmu, diff --git a/src/nvidia/src/kernel/gpu/mmu/mmu_fault_buffer_ctrl.c b/src/nvidia/src/kernel/gpu/mmu/mmu_fault_buffer_ctrl.c index d9a7197f4..161def068 100644 --- a/src/nvidia/src/kernel/gpu/mmu/mmu_fault_buffer_ctrl.c +++ b/src/nvidia/src/kernel/gpu/mmu/mmu_fault_buffer_ctrl.c @@ -44,7 +44,8 @@ faultbufCtrlCmdMmuFaultBufferRegisterNonReplayBuf_IMPL const NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pStaticInfo = kgmmuGetStaticInfo(pGpu, pKernelGmmu); GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuffer; - pClientShadowFaultBuffer = pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer; + pClientShadowFaultBuffer = + pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer[NON_REPLAYABLE_FAULT_BUFFER]; // This call takes GpuLock, so shadowBuffer pointers can be accessed without grabbing lock protecting them if (pClientShadowFaultBuffer) @@ -56,7 +57,7 @@ faultbufCtrlCmdMmuFaultBufferRegisterNonReplayBuf_IMPL return NV_ERR_NOT_SUPPORTED; } - status = kgmmuClientShadowFaultBufferAlloc_HAL(pGpu, pKernelGmmu); + status = kgmmuClientShadowFaultBufferAlloc_HAL(pGpu, pKernelGmmu, NON_REPLAYABLE_FAULT_BUFFER); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -65,10 +66,13 @@ faultbufCtrlCmdMmuFaultBufferRegisterNonReplayBuf_IMPL return status; } - pClientShadowFaultBuffer = pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer; + pClientShadowFaultBuffer = + pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer[NON_REPLAYABLE_FAULT_BUFFER]; - pParams->pShadowBuffer = pClientShadowFaultBuffer->pQueueAddress; - pParams->pShadowBufferContext = (NvP64) &pClientShadowFaultBuffer->queueContext; + { + pParams->pShadowBuffer = pClientShadowFaultBuffer->pQueueAddress; + pParams->pShadowBufferContext = (NvP64) &pClientShadowFaultBuffer->queueContext; + } pParams->bufferSize = pStaticInfo->nonReplayableFaultBufferSize; return NV_OK; @@ -86,22 +90,23 @@ faultbufCtrlCmdMmuFaultBufferUnregisterNonReplayBuf_IMPL KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); // This call takes GpuLock, so shadowBuffer pointers can be accessed without grabbing lock protecting them - if (!pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer) + if (!pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer[NON_REPLAYABLE_FAULT_BUFFER]) { NV_PRINTF(LEVEL_ERROR, "Client shadow fault buffer for non-replayable faults does not exist\n"); return NV_OK; } - if (pParams->pShadowBuffer != - pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer->pQueueAddress) + if ((pParams->pShadowBuffer != + pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer[NON_REPLAYABLE_FAULT_BUFFER]->pQueueAddress) + ) { NV_PRINTF(LEVEL_ERROR, "Given client shadow fault buffer for non-replayable faults does not " "match with the actual\n"); } - status = kgmmuClientShadowFaultBufferFree_HAL(pGpu, pKernelGmmu); + status = kgmmuClientShadowFaultBufferFree_HAL(pGpu, pKernelGmmu, NON_REPLAYABLE_FAULT_BUFFER); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Error freeing client shadow fault buffer for non-replayable faults\n"); @@ -109,3 +114,82 @@ faultbufCtrlCmdMmuFaultBufferUnregisterNonReplayBuf_IMPL return status; } + +NV_STATUS +faultbufCtrlCmdMmuFaultBufferRegisterReplayBuf_IMPL +( + MmuFaultBuffer *pMmuFaultBuffer, + NVC369_CTRL_MMU_FAULT_BUFFER_REGISTER_REPLAY_BUF_PARAMS *pParams +) +{ + NV_STATUS status; + OBJGPU *pGpu = GPU_RES_GET_GPU(pMmuFaultBuffer); + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + const NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pStaticInfo = kgmmuGetStaticInfo(pGpu, pKernelGmmu); + GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuffer; + + pClientShadowFaultBuffer = + pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer[REPLAYABLE_FAULT_BUFFER]; + + // This call takes GpuLock, so shadowBuffer pointers can be accessed without grabbing lock protecting them + if (pClientShadowFaultBuffer != NULL) + { + NV_PRINTF(LEVEL_ERROR, + "Client shadow fault buffer for replayable faults already allocated\n"); + NV_ASSERT(0); + + return NV_ERR_NOT_SUPPORTED; + } + + status = kgmmuClientShadowFaultBufferAlloc_HAL(pGpu, pKernelGmmu, REPLAYABLE_FAULT_BUFFER); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Error allocating client shadow fault buffer for replayable faults\n"); + return status; + } + + pClientShadowFaultBuffer = + pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer[REPLAYABLE_FAULT_BUFFER]; + + pParams->pShadowBuffer = pClientShadowFaultBuffer->pBufferAddress; + pParams->bufferSize = pStaticInfo->replayableFaultBufferSize; + + return NV_OK; +} + +NV_STATUS +faultbufCtrlCmdMmuFaultBufferUnregisterReplayBuf_IMPL +( + MmuFaultBuffer *pMmuFaultBuffer, + NVC369_CTRL_MMU_FAULT_BUFFER_UNREGISTER_REPLAY_BUF_PARAMS *pParams +) +{ + NV_STATUS status; + OBJGPU *pGpu = GPU_RES_GET_GPU(pMmuFaultBuffer); + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + + // This call takes GpuLock, so shadowBuffer pointers can be accessed without grabbing lock protecting them + if (pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer[REPLAYABLE_FAULT_BUFFER] == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "Client shadow fault buffer for replayable faults does not exist\n"); + return NV_OK; + } + + if (pParams->pShadowBuffer != + pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer[REPLAYABLE_FAULT_BUFFER]->pBufferAddress) + { + NV_PRINTF(LEVEL_ERROR, + "Given client shadow fault buffer for replayable faults does not " + "match with the actual\n"); + } + + status = kgmmuClientShadowFaultBufferFree_HAL(pGpu, pKernelGmmu, REPLAYABLE_FAULT_BUFFER); + if (status != NV_OK) { + NV_PRINTF(LEVEL_ERROR, + "Error freeing client shadow fault buffer for replayable faults\n"); + } + + return status; +} diff --git a/src/nvidia/src/kernel/gpu/mmu/uvm_sw.c b/src/nvidia/src/kernel/gpu/mmu/uvm_sw.c index f4aa1493a..952253822 100644 --- a/src/nvidia/src/kernel/gpu/mmu/uvm_sw.c +++ b/src/nvidia/src/kernel/gpu/mmu/uvm_sw.c @@ -52,7 +52,7 @@ uvmswConstruct_IMPL RS_PRIV_LEVEL privLevel = pCallContext->secInfo.privLevel; if (!(rmclientIsAdmin(pRmClient, privLevel) || hypervisorCheckForObjectAccess(hClient))) - return NV_ERR_INVALID_CLIENT; + return NV_ERR_INSUFFICIENT_PERMISSIONS; uvmswInitSwMethodState(pUvmSw); diff --git a/src/nvidia/src/kernel/gpu/mmu/vidmem_access_bit_buffer_v2.c b/src/nvidia/src/kernel/gpu/mmu/vidmem_access_bit_buffer_v2.c new file mode 100644 index 000000000..a42f8c634 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/mmu/vidmem_access_bit_buffer_v2.c @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "core/core.h" +#include "os/os.h" +#include "gpu/mmu/vidmem_access_bit_buffer.h" +#include "gpu/device/device.h" +#include "gpu/gpu.h" + +NV_STATUS +vidmemAccessBitBufConstructHelper_KERNEL +( + VidmemAccessBitBuffer *pVidmemAccessBitBuffer, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pVidmemAccessBitBuffer); + return IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && !IS_VIRTUAL(pGpu)? NV_OK : NV_ERR_NOT_SUPPORTED; +} \ No newline at end of file diff --git a/src/nvidia/src/kernel/gpu/nvlink/arch/ampere/kernel_nvlink_ga100.c b/src/nvidia/src/kernel/gpu/nvlink/arch/ampere/kernel_nvlink_ga100.c index 0fb2f0bac..b2bc09b9b 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/arch/ampere/kernel_nvlink_ga100.c +++ b/src/nvidia/src/kernel/gpu/nvlink/arch/ampere/kernel_nvlink_ga100.c @@ -133,7 +133,7 @@ knvlinkRemoveMapping_GA100 { NV_STATUS status = NV_OK; NvU32 peerId; - NvBool bBufferReady; + NvBool bBufferReady = NV_FALSE; NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS params; portMemSet(¶ms, 0, sizeof(params)); @@ -166,7 +166,7 @@ knvlinkRemoveMapping_GA100 status = knvlinkSyncLinkMasksAndVbiosInfo(pGpu, pKernelNvlink); if (status != NV_OK) { - NV_ASSERT(status == NV_OK); + NV_ASSERT(status != NV_OK); return status; } @@ -184,6 +184,7 @@ knvlinkRemoveMapping_GA100 if (!bBufferReady) { status = knvlinkUpdateCurrentConfig(pGpu, pKernelNvlink); + } } else diff --git a/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c b/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c index dee4d997b..22fbe7b0e 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c +++ b/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c @@ -28,6 +28,7 @@ #include "gpu/mem_mgr/mem_mgr.h" #include "nverror.h" #include "objtmr.h" +#include "gpu_mgr/gpu_mgr.h" /*! * @brief Check if ALI is supported for the given device @@ -371,6 +372,197 @@ knvlinkLogAliDebugMessages_GH100 return NV_OK; } +/** + * @brief Check if the nvlink bandwidth setting is OFF + * + * @param[in] pKernelNvlink reference of KernelNvlink + */ +NvBool +knvlinkIsBandwidthModeOff_GH100 +( + KernelNvlink *pKernelNvlink +) +{ + return (gpumgrGetGpuNvlinkBwMode() == GPU_NVLINK_BW_MODE_OFF); +} + +/** + * @brief Calculate the number of active nvlinks needs to be reduced + * for direct connect GPU system + * + * @param[in] pKernelNvlink reference of KernelNvlink + */ +NvU32 +knvlinkGetNumLinksToBeReducedPerIoctrl_GH100 +( + KernelNvlink *pKernelNvlink +) +{ + NvU32 numlinks = 0; + NvU8 mode; + +#if defined(INCLUDE_NVLINK_LIB) + numlinks = pKernelNvlink->pNvlinkDev->numActiveLinksPerIoctrl; +#endif + + if (numlinks == 0) + goto out; + + mode = gpumgrGetGpuNvlinkBwMode(); + + switch (mode) + { + case GPU_NVLINK_BW_MODE_OFF: + NV_PRINTF(LEVEL_ERROR, "Cannot reach here %s %d mode=%d\n", + __func__, __LINE__, mode); + NV_ASSERT(0); + break; + case GPU_NVLINK_BW_MODE_MIN: + numlinks = numlinks - 1; // At least one is ative at this point. + break; + case GPU_NVLINK_BW_MODE_HALF: + numlinks = numlinks / 2; + break; + case GPU_NVLINK_BW_MODE_3QUARTER: + numlinks = numlinks / 4; + break; + default: // Treat as GPU_NVLINK_BW_MODE_FULL + numlinks = 0; + break; + } + +out: + return numlinks; +} + +/** + * @brief Calculate the effective peer link mask for HS_HUB configuration + * + * @param[in] pGpu OBJGPU pointer of local GPU + * @param[in] pKernelNvlink reference of KernelNvlink + * @param[in] pRemoteGpu OBJGPU pointer of remote GPU + * @param[in/out] pPeerLinkMask reference of peerLinkMask + */ +void +knvlinkGetEffectivePeerLinkMask_GH100 +( + OBJGPU *pGpu, + KernelNvlink *pKernelNvlink, + OBJGPU *pRemoteGpu, + NvU32 *pPeerLinkMask +) +{ + NvU32 peerLinkMask, remotePeerLinkMask, effectivePeerLinkMask, peerLinkMaskPerIoctrl; + NvU32 gpuInstance, remoteGpuInstance; + NvU32 numLinksPerIoctrl, numIoctrls; + KernelNvlink *pRemoteKernelNvlink; + NvU32 numLinksToBeReduced; + NvU32 linkId, count, i; + + gpuInstance = gpuGetInstance(pGpu); + remoteGpuInstance = gpuGetInstance(pRemoteGpu); + + // Do not support NVSwitch systems for now. + if (knvlinkIsGpuConnectedToNvswitch(pGpu, pKernelNvlink)) + { + return; + } + + peerLinkMask = pKernelNvlink->peerLinkMasks[remoteGpuInstance]; + if (peerLinkMask == 0) + { + return; + } + + // + // No need to check if remotePeerLinkMask and peerLinkMask are equal because + // RM will not enable P2P otherwise. Given that we have reached here means + // the masks must be equal. + // + pRemoteKernelNvlink = GPU_GET_KERNEL_NVLINK(pRemoteGpu); + remotePeerLinkMask = pRemoteKernelNvlink->peerLinkMasks[gpuInstance]; + NV_ASSERT(nvPopCount32(remotePeerLinkMask) == nvPopCount32(peerLinkMask)); + + // Find out number of active NVLinks between the two GPUs. + numLinksToBeReduced = knvlinkGetNumLinksToBeReducedPerIoctrl_HAL(pKernelNvlink); + effectivePeerLinkMask = peerLinkMask; + + if (numLinksToBeReduced == 0) + { + return; + } + + // Start reducing effectivePeerLinkMask... + + // + // To have deterministic approach, if local GPU ID is less than remote GPU + // ID, always trim peerLinkMask from the perspective of local GPU. + // Otherwise, use remote GPU for the same. + // +#if defined(INCLUDE_NVLINK_LIB) + numIoctrls = pKernelNvlink->pNvlinkDev->numIoctrls; + numLinksPerIoctrl = pKernelNvlink->pNvlinkDev->numLinksPerIoctrl; +#else + numIoctrls = 0; + numLinksPerIoctrl = 0; +#endif + + if (pGpu->gpuId < pRemoteGpu->gpuId) + { + for (i = 0; i < numIoctrls; i++) + { + count = 0; + peerLinkMaskPerIoctrl = peerLinkMask & + (((1 << numLinksPerIoctrl) - 1) << (i * numLinksPerIoctrl)); + + FOR_EACH_INDEX_IN_MASK(32, linkId, peerLinkMaskPerIoctrl) + { + if (count == numLinksToBeReduced) + { + break; + } + + effectivePeerLinkMask &= (~NVBIT(linkId)); + count++; + } + FOR_EACH_INDEX_IN_MASK_END; + } + } + else + { + for (i = 0; i < numIoctrls; i++) + { + count = 0; + peerLinkMaskPerIoctrl = remotePeerLinkMask & + (((1 << numLinksPerIoctrl) - 1) << (i * numLinksPerIoctrl)); + + FOR_EACH_INDEX_IN_MASK(32, linkId, peerLinkMaskPerIoctrl) + { + if (count == numLinksToBeReduced) + { + break; + } + +#if defined(INCLUDE_NVLINK_LIB) + effectivePeerLinkMask &= + (~NVBIT(pRemoteKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.linkNumber)); +#endif + count++; + } + FOR_EACH_INDEX_IN_MASK_END; + } + } + + // + // effectivePeerLinkMask can never be zero, otherwise we create inconsistent + // HW/SW state, where we say that NVLink P2P is supported, but we don't + // program HSHUB. + // + // So, if not enough NVLinks are present, then drop effectivePeerLinkMask. + // + *pPeerLinkMask = (effectivePeerLinkMask > 0) ? effectivePeerLinkMask : peerLinkMask; +} + /*! * @brief Set unique fabric address for NVSwitch enabled systems. * @@ -431,48 +623,6 @@ knvlinkSetUniqueFabricBaseAddress_GH100 return NV_OK; } -/*! - * @brief Check if floorsweeping is needed for this particular chip - * - * @param[in] pGpu OBJGPU pointer - * @param[in] pKernelNvlink KernelNvlink pointer - * - * @returns On success, sets unique fabric address and returns NV_OK. - * On failure, returns NV_ERR_XXX. - */ -NvBool -knvlinkIsFloorSweepingNeeded_GH100 -( - OBJGPU *pGpu, - KernelNvlink *pKernelNvlink, - NvU32 numActiveLinksPerIoctrl, - NvU32 numLinksPerIoctrl -) -{ - - // - // Only floorsweep down the given GPU if the following conditions are met: - // 1. The number of active links allowed for the IOCTRL is less then the - // total number of links for the IOCTRL. No reason to spend time in code - // if the exectution of it will be a NOP - // - // 2. If the GPU has never been floorswept. An optimization to make sure RM - // doesn't burn cycles repeatedly running running code that will be a NOP - // - // 3. (temporary) Run only on Silicon chips. Fmodel currently doesn't support - // this feature - // - - if (numActiveLinksPerIoctrl < numLinksPerIoctrl && - !pKernelNvlink->bFloorSwept && - IS_SILICON(pGpu)) - { - return NV_TRUE; - } - - return NV_FALSE; -} - /*! * @brief Check if system has enough active NVLinks and * enough NVLink bridges @@ -495,3 +645,49 @@ knvlinkDirectConnectCheck_GH100 (void *)¶ms, sizeof(params)); } + +/*! + * @brief Check if floorsweeping is needed for this particular chip + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelNvlink KernelNvlink pointer + * + * @returns On success, sets unique fabric address and returns NV_OK. + * On failure, returns NV_ERR_XXX. + */ +NvBool +knvlinkIsFloorSweepingNeeded_GH100 +( + OBJGPU *pGpu, + KernelNvlink *pKernelNvlink, + NvU32 numActiveLinksPerIoctrl, + NvU32 numLinksPerIoctrl +) +{ + + // + // Only floorsweep down the given GPU if the following conditions are met: + // 1. if the number of links for the IP is > 0 + // + // 2. The number of active links allowed for the IOCTRL is less then the + // total number of links for the IOCTRL. No reason to spend time in code + // if the exectution of it will be a NOP + // + // 3. If the GPU has never been floorswept. An optimization to make sure RM + // doesn't burn cycles repeatedly running running code that will be a NOP + // + // 4. (temporary) Run only on Silicon chips. Fmodel currently doesn't support + // this feature + // + + if ((numLinksPerIoctrl > 0 && numActiveLinksPerIoctrl > 0) && + numActiveLinksPerIoctrl < numLinksPerIoctrl && + !pKernelNvlink->bFloorSwept && + IS_SILICON(pGpu)) + { + return NV_TRUE; + } + + return NV_FALSE; +} + diff --git a/src/nvidia/src/kernel/gpu/nvlink/arch/pascal/kernel_nvlink_gp100.c b/src/nvidia/src/kernel/gpu/nvlink/arch/pascal/kernel_nvlink_gp100.c index 6491cb398..a7a1d4c0e 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/arch/pascal/kernel_nvlink_gp100.c +++ b/src/nvidia/src/kernel/gpu/nvlink/arch/pascal/kernel_nvlink_gp100.c @@ -275,6 +275,7 @@ knvlinkSetupPeerMapping_GP100 } peerLinkMask = pKernelNvlink->peerLinkMasks[gpuGetInstance(pRemoteGpu)]; + knvlinkGetEffectivePeerLinkMask_HAL(pGpu, pKernelNvlink, pRemoteGpu, &peerLinkMask); if (peerLinkMask != 0) { diff --git a/src/nvidia/src/kernel/gpu/nvlink/common_nvlinkapi.c b/src/nvidia/src/kernel/gpu/nvlink/common_nvlinkapi.c index 5b92cd2cb..1db199f56 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/common_nvlinkapi.c +++ b/src/nvidia/src/kernel/gpu/nvlink/common_nvlinkapi.c @@ -589,6 +589,7 @@ subdeviceCtrlCmdBusGetNvlinkStatus_IMPL NvBool bMIGNvLinkP2PSupported = ((pKernelMIGManager != NULL) && kmigmgrIsMIGNvlinkP2PSupported(pGpu, pKernelMIGManager)); NV_STATUS status = NV_OK; + NvBool bIsNvlinkReady = NV_TRUE; NvU8 i = 0; struct { @@ -696,12 +697,16 @@ subdeviceCtrlCmdBusGetNvlinkStatus_IMPL // as not ready // status = knvlinkCoreGetRemoteDeviceInfo(pGpu, pKernelNvlink); - if (status != NV_OK) + if (status == NV_ERR_NOT_READY) { NV_PRINTF(LEVEL_INFO, "Nvlink is not ready yet!\n"); - status = NV_ERR_NOT_READY; + bIsNvlinkReady = NV_FALSE; + } + else if (status != NV_OK) + { goto done; } + } // @@ -711,7 +716,8 @@ subdeviceCtrlCmdBusGetNvlinkStatus_IMPL // knvlinkFilterBridgeLinks_HAL(pGpu, pKernelNvlink); - pParams->enabledLinkMask = pKernelNvlink->enabledLinks; + // If nvlink is not ready don't report back any links as being enabled + pParams->enabledLinkMask = (bIsNvlinkReady) ? pKernelNvlink->enabledLinks : 0x0; pTmpData->nvlinkLinkAndClockInfoParams.linkMask = pParams->enabledLinkMask; pTmpData->nvlinkLinkAndClockInfoParams.bSublinkStateInst = pParams->bSublinkStateInst; diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c index 5d35cb3a8..985a2a715 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c @@ -204,6 +204,11 @@ knvlinkIsNvlinkP2pSupported_IMPL return NV_FALSE; } + if (knvlinkIsBandwidthModeOff(pKernelNvlink)) + { + return NV_FALSE; + } + // Get the Nvlink P2P connections from the core library status = knvlinkGetP2pConnectionStatus(pGpu, pKernelNvlink, pPeerGpu); @@ -367,7 +372,11 @@ knvlinkGetP2pConnectionStatus_IMPL } // Get the remote ends of the links of local GPU from the nvlink core - knvlinkCoreGetRemoteDeviceInfo(pGpu0, pKernelNvlink0); + status = knvlinkCoreGetRemoteDeviceInfo(pGpu0, pKernelNvlink0); + if (status != NV_OK) + { + return status; + } // Post topology link enable on links of local GPU status = knvlinkEnableLinksPostTopology_HAL(pGpu0, pKernelNvlink0, @@ -404,7 +413,11 @@ knvlinkGetP2pConnectionStatus_IMPL if (knvlinkGetNumLinksToPeer(pGpu1, pKernelNvlink1, pGpu0) != numPeerLinks) { // Get the remote ends of the links of remote GPU from the nvlink core - knvlinkCoreGetRemoteDeviceInfo(pGpu1, pKernelNvlink1); + status = knvlinkCoreGetRemoteDeviceInfo(pGpu1, pKernelNvlink1); + if (status != NV_OK) + { + return status; + } // Post topology link enable on links of remote GPU status = knvlinkEnableLinksPostTopology_HAL(pGpu1, pKernelNvlink1, @@ -635,7 +648,7 @@ knvlinkInbandMsgCallbackDispatcher_WORKITEM NV_ASSERT((pRsvd[0] == 0) && portMemCmp(pRsvd, pRsvd + 1, sizeof(pHeader->reserved) - 1) == 0); - pKernelNvlink->inbandCallback[pHeader->type].pCallback(pGpu, pData); + pKernelNvlink->inbandCallback[pHeader->type].pCallback(gpuInstance, pData); } NV_STATUS @@ -1156,10 +1169,6 @@ knvlinkSetPowerFeatures_IMPL { case NVLINK_VERSION_22: { - // Regkeys finally decide whether or not the power state is supported - pKernelNvlink->setProperty(pKernelNvlink, PDB_PROP_KNVLINK_SINGLE_LANE_POWER_STATE_ENABLED, - (pKernelNvlink->bDisableSingleLaneMode ? NV_FALSE : NV_TRUE)); - // NVLink L2 is supported only on MODS and Windows LDDM if (RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM || RMCFG_FEATURE_MODS_FEATURES) { @@ -1169,15 +1178,6 @@ knvlinkSetPowerFeatures_IMPL break; } - case NVLINK_VERSION_31: - case NVLINK_VERSION_30: - case NVLINK_VERSION_20: - { - // Regkeys finally decide whether or not the power state is supported - pKernelNvlink->setProperty(pKernelNvlink, PDB_PROP_KNVLINK_SINGLE_LANE_POWER_STATE_ENABLED, - (pKernelNvlink->bDisableSingleLaneMode ? NV_FALSE : NV_TRUE)); - break; - } default: break; } diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibcallback.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibcallback.c index 662429f76..4cefc6e10 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibcallback.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibcallback.c @@ -514,6 +514,9 @@ knvlinkCoreSetDlLinkModeCallback linkIndex = pNvlinkLink->linkId; pKernelIoctrl = KNVLINK_LINK_GET_IOCTRL(pKernelNvlink, linkIndex); + if (pKernelIoctrl == NULL) + return 0; + // If link training is disabled through regkey if (pKernelNvlink->bSkipLinkTraining) { @@ -1501,7 +1504,7 @@ knvlinkCoreAliTrainingCallback ) { KNVLINK_RM_LINK *pNvlinkLink = (KNVLINK_RM_LINK *) link->link_info; - POBJGPU pGpu = pNvlinkLink->pGpu; + OBJGPU *pGpu = pNvlinkLink->pGpu; KernelNvlink * pKernelNvlink = NULL; NV_STATUS status; diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c index ebb7186e4..144d9c414 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c @@ -80,7 +80,7 @@ knvlinkCoreGetRemoteDeviceInfo_IMPL NvBool bNvswitchProxyPresent = NV_FALSE; NvBool bUpdateConnStatus = NV_FALSE; NvBool bCheckDegradedMode = NV_FALSE; - nvlink_conn_info conn_info; + nvlink_conn_info conn_info = {0}; NvU32 linkId; NvU32 numActiveLinksPerIoctrl = 0; NvU32 numLinksPerIoctrl = 0; @@ -109,18 +109,11 @@ knvlinkCoreGetRemoteDeviceInfo_IMPL if (pKernelNvlink->ipVerNvlink >= NVLINK_VERSION_40 && !bNvswitchProxyPresent && !pSys->getProperty(pSys, PDB_PROP_SYS_FABRIC_IS_EXTERNALLY_MANAGED) && - pKernelNvlink->pNvlinkDev != NULL) + pKernelNvlink->pNvlinkDev != NULL && + !pKernelNvlink->bFloorSwept) { - // The path here is important not getting the connection info - FOR_EACH_INDEX_IN_MASK(32, linkId, pKernelNvlink->enabledLinks) - { - nvlink_lib_discover_and_get_remote_conn_info( - pKernelNvlink->nvlinkLinks[linkId].core_link, &conn_info, 0); - } - FOR_EACH_INDEX_IN_MASK_END; - numLinksPerIoctrl = knvlinkGetTotalNumLinksPerIoctrl(pGpu, pKernelNvlink); - status = knvlinkFloorSweep_IMPL(pGpu, pKernelNvlink, + status = knvlinkFloorSweep(pGpu, pKernelNvlink, numLinksPerIoctrl, &numActiveLinksPerIoctrl); if (status != NV_OK) @@ -160,7 +153,7 @@ knvlinkCoreGetRemoteDeviceInfo_IMPL // discover remote information explicitly. // nvlink_lib_discover_and_get_remote_conn_info( - pKernelNvlink->nvlinkLinks[linkId].core_link, &conn_info, 0); + pKernelNvlink->nvlinkLinks[linkId].core_link, &conn_info, flags); } else { @@ -1333,6 +1326,7 @@ knvlinkFloorSweep_IMPL NvU32 linkId; NvU32 tmpDisabledLinkMask = 0; NvU32 tmpEnabledLinkMask = 0; + nvlink_conn_info conn_info; *pNumActiveLinksPerIoctrl = knvlinkGetNumActiveLinksPerIoctrl(pGpu, pKernelNvlink); if (!knvlinkIsFloorSweepingNeeded_HAL(pGpu, pKernelNvlink, *pNumActiveLinksPerIoctrl, numLinksPerIoctrl)) @@ -1340,11 +1334,13 @@ knvlinkFloorSweep_IMPL return NV_OK; } - // - // This call must be before the floorswept to cache the NVLink bridge - // information in physical RM. - // - knvlinkDirectConnectCheck_HAL(pGpu, pKernelNvlink); + // The path here is important not getting the connection info + FOR_EACH_INDEX_IN_MASK(32, linkId, pKernelNvlink->enabledLinks) + { + nvlink_lib_discover_and_get_remote_conn_info( + pKernelNvlink->nvlinkLinks[linkId].core_link, &conn_info, 0); + } + FOR_EACH_INDEX_IN_MASK_END; // floorsweeping in corelib will update connection info that RM qill query below (void)nvlink_lib_powerdown_floorswept_links_to_off(pKernelNvlink->pNvlinkDev); diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkoverrides.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkoverrides.c index 71b2ffb84..fcaaa8355 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkoverrides.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkoverrides.c @@ -59,7 +59,6 @@ knvlinkApplyRegkeyOverrides_IMPL pKernelNvlink->nvlinkLinkSpeed = NV_REG_STR_RM_NVLINK_SPEED_CONTROL_SPEED_DEFAULT; // Power management settings - pKernelNvlink->bDisableSingleLaneMode = NV_FALSE; pKernelNvlink->bDisableL2Mode = NV_FALSE; // Debug Settings @@ -225,15 +224,6 @@ knvlinkApplyRegkeyOverrides_IMPL { NV_PRINTF(LEVEL_INFO, "RM NVLink Link PM controlled via regkey\n"); - // Whether one-eighth mode has been disabled by regkey - if (FLD_TEST_DRF(_REG_STR_RM, _NVLINK_LINK_PM_CONTROL, _SINGLE_LANE_MODE, - _DISABLE, regdata)) - { - NV_PRINTF(LEVEL_INFO, - "NVLink single-lane power state disabled via regkey\n"); - pKernelNvlink->bDisableSingleLaneMode = NV_TRUE; - } - // Whether L2 power state has been disabled by regkey if (FLD_TEST_DRF(_REG_STR_RM, _NVLINK_LINK_PM_CONTROL, _L2_MODE, _DISABLE, regdata)) diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkstate.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkstate.c index 30248304c..ddb8ab09d 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkstate.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkstate.c @@ -1096,7 +1096,7 @@ knvlinkSetDegradedMode_IMPL break; } } - + if (pRemoteGpu == NULL) { NV_PRINTF(LEVEL_ERROR, @@ -1119,9 +1119,6 @@ knvlinkSetDegradedMode_IMPL if (pRemoteKernelNvlink->bIsGpuDegraded == NV_FALSE) { pKernelNvlink->bIsGpuDegraded = NV_TRUE; - NV_PRINTF(LEVEL_ERROR, - "GPU%d marked Degraded for error on linkId %d \n", - pGpu->gpuInstance, linkId); // shutdown all the links on this GPU status = knvlinkCoreShutdownDeviceLinks(pGpu, pKernelNvlink, NV_TRUE); diff --git a/src/nvidia/src/kernel/gpu/perf/kern_perf_boost.c b/src/nvidia/src/kernel/gpu/perf/kern_perf_boost.c index d840c4c0b..8d1f0ff69 100644 --- a/src/nvidia/src/kernel/gpu/perf/kern_perf_boost.c +++ b/src/nvidia/src/kernel/gpu/perf/kern_perf_boost.c @@ -50,6 +50,8 @@ subdeviceCtrlCmdKPerfBoost_IMPL KernelPerf *pKernelPerf = GPU_GET_KERNEL_PERF(pGpu); NV_STATUS status = NV_OK; + NV_CHECK_OR_RETURN(LEVEL_INFO, (pKernelPerf != NULL), NV_ERR_NOT_SUPPORTED); + status = kperfBoostSet_HAL(pKernelPerf, pSubdevice, pBoostParams); return status; } diff --git a/src/nvidia/src/kernel/gpu/perf/kern_perf_pwr.c b/src/nvidia/src/kernel/gpu/perf/kern_perf_pwr.c index 7a9cb511d..91ffa3fb0 100644 --- a/src/nvidia/src/kernel/gpu/perf/kern_perf_pwr.c +++ b/src/nvidia/src/kernel/gpu/perf/kern_perf_pwr.c @@ -111,7 +111,6 @@ _kperfSendPostPowerStateCallback { NvU32 inOutData = 0; NvU16 outDataSize = sizeof(inOutData); - OBJOS *pOS = GPU_GET_OS(pGpu); NV_STATUS status = NV_OK; ACPI_DSM_FUNCTION func = gpuGetPerfPostPowerStateFunc(pGpu); RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); @@ -141,9 +140,9 @@ _kperfSendPostPowerStateCallback inOutData = FLD_SET_DRF_NUM(_ACPI, _CALLBACKS_ARG, _CURRENTPOWERSTATE, ctrlParams.powerState, inOutData); - status = pOS->osCallACPI_DSM(pGpu, func, - NV_ACPI_GENERIC_FUNC_CALLBACKS, - &inOutData, &outDataSize); + status = osCallACPI_DSM(pGpu, func, + NV_ACPI_GENERIC_FUNC_CALLBACKS, + &inOutData, &outDataSize); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "PostPState callback error:0x%x\n", status); @@ -192,7 +191,7 @@ subdeviceCtrlCmdPerfSetPowerstate_KERNEL NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS *pPowerInfoParams ) { - POBJGPU pGpu = GPU_RES_GET_GPU(pSubdevice); + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); KernelPerf *pKernelPerf = GPU_GET_KERNEL_PERF(pGpu); NV_STATUS status = NV_OK; diff --git a/src/nvidia/src/kernel/gpu/sec2/arch/turing/kernel_sec2_tu102.c b/src/nvidia/src/kernel/gpu/sec2/arch/turing/kernel_sec2_tu102.c index 286c125ed..14e939143 100644 --- a/src/nvidia/src/kernel/gpu/sec2/arch/turing/kernel_sec2_tu102.c +++ b/src/nvidia/src/kernel/gpu/sec2/arch/turing/kernel_sec2_tu102.c @@ -72,18 +72,6 @@ ksec2ResetHw_TU102 return NV_OK; } -NvBool -ksec2IsEngineInReset_TU102 -( - OBJGPU *pGpu, - KernelSec2 *pKernelSec2 -) -{ - NvU32 val = GPU_REG_RD32(pGpu, NV_PSEC_FALCON_ENGINE); - - return FLD_TEST_DRF(_PSEC_FALCON, _ENGINE, _RESET, _TRUE, val); -} - static NV_STATUS s_allocateGenericBlUcode ( diff --git a/src/nvidia/src/kernel/gpu/sec2/kernel_sec2.c b/src/nvidia/src/kernel/gpu/sec2/kernel_sec2.c index 75d43c4bf..519db89e2 100644 --- a/src/nvidia/src/kernel/gpu/sec2/kernel_sec2.c +++ b/src/nvidia/src/kernel/gpu/sec2/kernel_sec2.c @@ -27,6 +27,8 @@ #include "gpu/eng_desc.h" #include "gpu/falcon/kernel_falcon.h" #include "gpu/gpu.h" +#include "gpu/fifo/kernel_fifo.h" +#include "rmapi/event.h" NV_STATUS ksec2ConstructEngine_IMPL @@ -52,3 +54,42 @@ ksec2Destruct_IMPL portMemFree((void * /* const_cast */) pKernelSec2->pGenericBlUcodeImg); pKernelSec2->pGenericBlUcodeImg = NULL; } + +void +ksec2RegisterIntrService_IMPL +( + OBJGPU *pGpu, + KernelSec2 *pKernelSec2, + IntrServiceRecord pRecords[MC_ENGINE_IDX_MAX] +) +{ + KernelFalcon *pKernelFalcon = staticCast(pKernelSec2, KernelFalcon); + NV_ASSERT_OR_RETURN_VOID(pKernelFalcon); + + // Register to handle nonstalling interrupts + NV_ASSERT_OR_RETURN_VOID(pKernelFalcon->physEngDesc != ENG_INVALID); + + NvU32 mcIdx = MC_ENGINE_IDX_SEC2; + + NV_PRINTF(LEVEL_INFO, "Registering 0x%x/0x%x to handle SEC2 nonstall intr\n", pKernelFalcon->physEngDesc, mcIdx); + + NV_ASSERT(pRecords[mcIdx].pNotificationService == NULL); + pRecords[mcIdx].bFifoWaiveNotify = NV_FALSE; + pRecords[mcIdx].pNotificationService = staticCast(pKernelSec2, IntrService); + +} + +NV_STATUS +ksec2ServiceNotificationInterrupt_IMPL +( + OBJGPU *pGpu, + KernelSec2 *pKernelSec2, + IntrServiceServiceNotificationInterruptArguments *pParams +) +{ + NV_PRINTF(LEVEL_INFO, "servicing nonstall intr for SEC2 engine\n"); + + // Wake up channels waiting on this event + engineNonStallIntrNotify(pGpu, RM_ENGINE_TYPE_SEC2); + return NV_OK; +} \ No newline at end of file diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_fla.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_fla.c index adfaf8344..0dd00837b 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_fla.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_fla.c @@ -174,7 +174,7 @@ subdeviceCtrlCmdFlaRange_IMPL ) { NV_STATUS status = NV_OK; - POBJGPU pGpu = GPU_RES_GET_GPU(pSubdevice); + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); KernelMIGManager *pKernelMIGManager; NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c index de1f711f9..fe52daf9a 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c @@ -721,6 +721,19 @@ subdeviceCtrlCmdGpuGetNvencSwSessionStats_IMPL return NV_OK; } +NV_STATUS +_subdeviceCtrlCmdGpuGetNvencSwSessionInfo +( + OBJGPU *pGpu, + NvU32 sessionInfoTblEntry, + NV2080_CTRL_NVENC_SW_SESSION_INFO *pSessionInfo, + NvU32 *entryCount +) +{ + + return NV_OK; +} + // // subdeviceCtrlCmdGpuGetNvencSwSessionInfo // @@ -735,9 +748,23 @@ subdeviceCtrlCmdGpuGetNvencSwSessionInfo_IMPL NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS *pParams ) { + NV_STATUS status = NV_OK; pParams->sessionInfoTblEntry = 0; - return NV_OK; + return status; +} + +NV_STATUS +subdeviceCtrlCmdGpuGetNvencSwSessionInfoV2_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS *pParams +) +{ + NV_STATUS status = NV_OK; + pParams->sessionInfoTblEntry = 0; + + return status; } // @@ -1288,7 +1315,7 @@ subdeviceCtrlCmdGpuGetFermiZcullInfo_IMPL NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); NvHandle hSubdevice = RES_GET_HANDLE(pSubdevice); - LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(GPU_RES_GET_GPU(pSubdevice)->gpuInstance)); portMemSet(&zcullMaskParams, 0, sizeof(zcullMaskParams)); zcullMaskParams.gpcId = pParams->gpcId; @@ -2036,9 +2063,6 @@ subdeviceCtrlCmdGpuGetNumMmusPerGpc_IMPL /* * @brief Update/Set the compute policy config for a GPU * - * Lock Requirements: - * Assert that API and GPUs lock held on entry - * * @param[in] pSubdevice * @param[in] pParams pointer to control parameters * @@ -2060,8 +2084,6 @@ subdeviceCtrlCmdGpuSetComputePolicyConfig_IMPL NvU32 gidFlags; NV_STATUS status = NV_OK; - LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); - switch(pParams->config.type) { case NV2080_CTRL_GPU_COMPUTE_POLICY_TIMESLICE: @@ -2113,9 +2135,6 @@ ct_assert(NV2080_CTRL_GPU_COMPUTE_POLICY_MAX <= NV2080_CTRL_GPU_COMPUTE_POLICY_C /* * @brief Get all compute policy configs for a GPU * - * Lock Requirements: - * Assert that API and GPUs lock held on entry - * * @param[in] pSubdevice * @param[in] pParams pointer to control parameters * @@ -2136,8 +2155,6 @@ subdeviceCtrlCmdGpuGetComputePolicyConfig_IMPL NvU32 gidFlags; NV_STATUS status = NV_OK; - LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); - gidFlags = DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _TYPE, _SHA1) | DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _FORMAT, _BINARY); status = gpuGetGidInfo(pGpu, NULL, NULL, gidFlags); @@ -2240,7 +2257,7 @@ NV_STATUS subdeviceCtrlCmdValidateMemMapRequest_IMPL NvU32 bar0MapSize; NvU64 bar0MapOffset; - LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(GPU_RES_GET_GPU(pSubdevice)->gpuInstance)); pParams->protection = NV_PROTECT_READ_WRITE; diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_regops.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_regops.c index 33f2d4b3d..c544f3f37 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_regops.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_regops.c @@ -183,12 +183,12 @@ subdeviceCtrlCmdGpuExecRegOps_cmn } else { - NV_RM_RPC_GPU_EXEC_REG_OPS(pGpu, - pRmCtrlParams->hClient, - pRmCtrlParams->hObject, - pRmCtrlParams->pParams, - pRegOps, - status); + NV_RM_RPC_GPU_EXEC_REG_OPS(pGpu, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->pParams, + pRegOps, + status); } return status; } diff --git a/src/nvidia/src/kernel/gpu/sw_test.c b/src/nvidia/src/kernel/gpu/sw_test.c index 59cef7062..9e9ba79d9 100644 --- a/src/nvidia/src/kernel/gpu/sw_test.c +++ b/src/nvidia/src/kernel/gpu/sw_test.c @@ -45,7 +45,7 @@ swtestDestruct_IMPL chandesIsolateOnDestruct(pChannelDescendant); } -static METHOD Nv04SoftwareTestMethods[] = +static const METHOD Nv04SoftwareTestMethods[] = { {mthdNoOperation, 0x0100, 0x0103}, }; @@ -53,7 +53,7 @@ static METHOD Nv04SoftwareTestMethods[] = NV_STATUS swtestGetSwMethods_IMPL ( SoftwareMethodTest *pSwTest, - METHOD **ppMethods, + const METHOD **ppMethods, NvU32 *pNumMethods ) { diff --git a/src/nvidia/src/kernel/gpu/timed_semaphore.c b/src/nvidia/src/kernel/gpu/timed_semaphore.c index 84ae13585..c66017f01 100644 --- a/src/nvidia/src/kernel/gpu/timed_semaphore.c +++ b/src/nvidia/src/kernel/gpu/timed_semaphore.c @@ -339,7 +339,6 @@ static NV_STATUS _class9074SetNotifierHi ( OBJGPU *pGpu, ChannelDescendant *pObject, - PMETHOD pMethod, NvU32 Offset, NvU32 Data ) @@ -358,7 +357,6 @@ static NV_STATUS _class9074SetNotifierLo ( OBJGPU *pGpu, ChannelDescendant *pObject, - PMETHOD pMethod, NvU32 Offset, NvU32 Data ) @@ -394,7 +392,6 @@ static NV_STATUS _class9074SetSemaphoreHi ( OBJGPU *pGpu, ChannelDescendant *pObject, - PMETHOD pMethod, NvU32 Offset, NvU32 Data ) @@ -413,7 +410,6 @@ static NV_STATUS _class9074SetSemaphoreLo ( OBJGPU *pGpu, ChannelDescendant *pObject, - PMETHOD pMethod, NvU32 Offset, NvU32 Data ) @@ -449,7 +445,6 @@ static NV_STATUS _class9074SetWaitTimestampHi ( OBJGPU *pGpu, ChannelDescendant *pObject, - PMETHOD pMethod, NvU32 Offset, NvU32 Data ) @@ -468,7 +463,6 @@ static NV_STATUS _class9074SetWaitTimestampLo ( OBJGPU *pGpu, ChannelDescendant *pObject, - PMETHOD pMethod, NvU32 Offset, NvU32 Data ) @@ -497,7 +491,6 @@ static NV_STATUS _class9074SetSemaphoreReleaseValue ( OBJGPU *pGpu, ChannelDescendant *pObject, - PMETHOD pMethod, NvU32 Offset, NvU32 Data ) @@ -516,7 +509,6 @@ static NV_STATUS _class9074ScheduleSemaphoreRelease ( OBJGPU *pGpu, ChannelDescendant *pObject, - PMETHOD pMethod, NvU32 Offset, NvU32 Data ) @@ -599,7 +591,7 @@ static NV_STATUS _class9074TimerCallback } // end of _class9074TimerCallback // GF100_TIMED_SEMAPHORE_SW -static METHOD GF100TimedSemSwMethods[] = +static const METHOD GF100TimedSemSwMethods[] = { { mthdNoOperation, 0x0100, 0x0103 }, { _class9074SetNotifierHi, 0x0140, 0x0143 }, @@ -615,7 +607,7 @@ static METHOD GF100TimedSemSwMethods[] = NV_STATUS tsemaGetSwMethods_IMPL ( TimedSemaSwObject *pTimedSemSw, - METHOD **ppMethods, + const METHOD **ppMethods, NvU32 *pNumMethods ) { diff --git a/src/nvidia/src/kernel/gpu/timer/arch/ampere/timer_ga100.c b/src/nvidia/src/kernel/gpu/timer/arch/ampere/timer_ga100.c index 7cc163608..a1b7f144f 100644 --- a/src/nvidia/src/kernel/gpu/timer/arch/ampere/timer_ga100.c +++ b/src/nvidia/src/kernel/gpu/timer/arch/ampere/timer_ga100.c @@ -41,8 +41,8 @@ NV_STATUS tmrGetGpuPtimerOffset_GA100 ( - POBJGPU pGpu, - POBJTMR pTmr, + OBJGPU *pGpu, + OBJTMR *pTmr, NvU32 *pGpuTimestampOffsetLo, NvU32 *pGpuTimestampOffsetHi ) diff --git a/src/nvidia/src/kernel/gpu/timer/arch/hopper/timer_gh100.c b/src/nvidia/src/kernel/gpu/timer/arch/hopper/timer_gh100.c index 127515e36..9d62346de 100644 --- a/src/nvidia/src/kernel/gpu/timer/arch/hopper/timer_gh100.c +++ b/src/nvidia/src/kernel/gpu/timer/arch/hopper/timer_gh100.c @@ -71,8 +71,8 @@ NV_STATUS tmrSetCurrentTime_GH100 NV_STATUS tmrSetCountdown_GH100 ( - POBJGPU pGpu, - POBJTMR pTmr, + OBJGPU *pGpu, + OBJTMR *pTmr, NvU32 time, NvU32 tmrId, THREAD_STATE_NODE *pThreadState diff --git a/src/nvidia/src/kernel/gpu/timer/arch/maxwell/timer_gm107.c b/src/nvidia/src/kernel/gpu/timer/arch/maxwell/timer_gm107.c index 8554bc817..d092bbb56 100644 --- a/src/nvidia/src/kernel/gpu/timer/arch/maxwell/timer_gm107.c +++ b/src/nvidia/src/kernel/gpu/timer/arch/maxwell/timer_gm107.c @@ -89,8 +89,8 @@ tmrSetCurrentTime_GM107 NV_STATUS tmrGetGpuAndCpuTimestampPair_GM107 ( - POBJGPU pGpu, - POBJTMR pTmr, + OBJGPU *pGpu, + OBJTMR *pTmr, NvU64 *pGpuTime, NvU64 *pCpuTime ) @@ -165,8 +165,8 @@ tmrGetGpuAndCpuTimestampPair_GM107 NV_STATUS tmrGetGpuPtimerOffset_GM107 ( - POBJGPU pGpu, - POBJTMR pTmr, + OBJGPU *pGpu, + OBJTMR *pTmr, NvU32 *pGpuTimestampOffsetLo, NvU32 *pGpuTimestampOffsetHi ) diff --git a/src/nvidia/src/kernel/gpu/timer/arch/turing/timer_tu102.c b/src/nvidia/src/kernel/gpu/timer/arch/turing/timer_tu102.c index 818cde411..d8be48ea3 100644 --- a/src/nvidia/src/kernel/gpu/timer/arch/turing/timer_tu102.c +++ b/src/nvidia/src/kernel/gpu/timer/arch/turing/timer_tu102.c @@ -38,8 +38,8 @@ NV_STATUS tmrSetCountdown_TU102 ( - POBJGPU pGpu, - POBJTMR pTmr, + OBJGPU *pGpu, + OBJTMR *pTmr, NvU32 time, NvU32 tmrId, THREAD_STATE_NODE *pThreadState @@ -128,16 +128,14 @@ tmrGetGpuPtimerOffset_TU102 /* * @brief This function returns the PTIMER_TIME_0 register. This function will * work for both Physical function and virtual function in SR-IOV. - * @param[in] POBJGPU - GPU Object pointer - * @param[in] POBJTMR - Timer Object pointer * * @return NvU32 */ NvU32 tmrReadTimeLoReg_TU102 ( - POBJGPU pGpu, - POBJTMR pTmr, + OBJGPU *pGpu, + OBJTMR *pTmr, THREAD_STATE_NODE *pThreadState ) { @@ -147,16 +145,14 @@ tmrReadTimeLoReg_TU102 /* * @brief This function returns the PTIMER_TIME_1 register. This function will * work for both Physical function and virtual function in SR-IOV. - * @param[in] POBJGPU - GPU Object pointer - * @param[in] POBJTMR - Timer Object pointer * * @return NvU32 */ NvU32 tmrReadTimeHiReg_TU102 ( - POBJGPU pGpu, - POBJTMR pTmr, + OBJGPU *pGpu, + OBJTMR *pTmr, THREAD_STATE_NODE *pThreadState ) { diff --git a/src/nvidia/src/kernel/gpu/timer/arch/volta/timer_gv100.c b/src/nvidia/src/kernel/gpu/timer/arch/volta/timer_gv100.c index 85872be35..8b7623a07 100644 --- a/src/nvidia/src/kernel/gpu/timer/arch/volta/timer_gv100.c +++ b/src/nvidia/src/kernel/gpu/timer/arch/volta/timer_gv100.c @@ -91,8 +91,8 @@ tmrSetCurrentTime_GV100 NV_STATUS tmrGetGpuPtimerOffset_GV100 ( - POBJGPU pGpu, - POBJTMR pTmr, + OBJGPU *pGpu, + OBJTMR *pTmr, NvU32 *pGpuTimestampOffsetLo, NvU32 *pGpuTimestampOffsetHi ) diff --git a/src/nvidia/src/kernel/gpu/timer/timer.c b/src/nvidia/src/kernel/gpu/timer/timer.c index d48c55af0..1fa264141 100644 --- a/src/nvidia/src/kernel/gpu/timer/timer.c +++ b/src/nvidia/src/kernel/gpu/timer/timer.c @@ -37,6 +37,7 @@ /* ------------------------ Static Function Prototypes ---------------------- */ static PTMR_EVENT_PVT _tmrPullCallbackFromHead (OBJTMR *); static void _tmrScanCallback(OBJTMR *, void *); +static void _tmrScanCallbackOSTimer(OBJTMR *, PTMR_EVENT_PVT); static PTMR_EVENT_PVT _tmrGetNextFreeCallback(OBJTMR *); static NV_STATUS _tmrInsertCallback(OBJTMR *, PTMR_EVENT_PVT, NvU64); static void _tmrInsertCallbackInList(OBJGPU *pGpu, OBJTMR *pTmr, PTMR_EVENT_PVT pEvent); @@ -205,6 +206,13 @@ static NV_INLINE NvBool tmrEventsExist(OBJTMR *pTmr) return pTmr->pRmActiveEventList != NULL; } +static NV_INLINE NvBool tmrIsOSTimer(OBJTMR *pTmr, PTMR_EVENT pEventPublic) +{ + return ((pEventPublic != NULL) && + (pTmr->getProperty(pTmr, PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS) || + (pEventPublic->flags & TMR_FLAG_USE_OS_TIMER))); +} + /*! * Allocates the necessary memory for storing a callback in the timer. * @@ -235,8 +243,7 @@ NV_STATUS tmrEventCreate_IMPL (*ppEventPublic)->pUserData = pUserData; (*ppEventPublic)->flags = flags; - if (pTmr->getProperty(pTmr, PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS) || - (flags & TMR_FLAG_USE_OS_TIMER)) + if (tmrIsOSTimer(pTmr, *ppEventPublic)) { status = tmrEventCreateOSTimer_HAL(pTmr, *ppEventPublic); if (status != NV_OK) @@ -339,10 +346,10 @@ void tmrEventCancel_IMPL pEvent->bInUse = NV_FALSE; - if (pTmr->getProperty(pTmr, PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS) || - (pEventPublic->flags & TMR_FLAG_USE_OS_TIMER)) + if (tmrIsOSTimer(pTmr, pEventPublic)) { NV_STATUS status = NV_OK; + _tmrScanCallbackOSTimer(pTmr, pEvent); status = tmrEventCancelOSTimer_HAL(pTmr, pEventPublic); if (status != NV_OK) { @@ -398,9 +405,10 @@ void tmrEventDestroy_IMPL if (pEvent != NULL) { NV_ASSERT(!pEvent->bLegacy); - if (pTmr->getProperty(pTmr, PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS) || - (pEventPublic->flags & TMR_FLAG_USE_OS_TIMER)) + if (tmrIsOSTimer(pTmr, pEventPublic)) { + _tmrScanCallbackOSTimer(pTmr, pEvent); + // OS timer destroying will cancel the timer tmrEventDestroyOSTimer_HAL(pTmr, pEventPublic); } @@ -552,8 +560,7 @@ NV_STATUS tmrEventScheduleRel_IMPL if (rmStatus != NV_OK) return rmStatus; - if (pTmr->getProperty(pTmr, PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS) || - (pEvent->flags & TMR_FLAG_USE_OS_TIMER)) + if (tmrIsOSTimer(pTmr, pEvent)) { /*HR timer scheduled in relative mode*/ /*TBD : This condition needs to be moved to OS timer handling functions */ @@ -628,7 +635,9 @@ NvBool tmrEventOnList_IMPL ) { PTMR_EVENT_PVT pEvent = (PTMR_EVENT_PVT)pEventPublic; - PTMR_EVENT_PVT pScan = pTmr->pRmActiveEventList; + PTMR_EVENT_PVT pScan = tmrIsOSTimer(pTmr, pEventPublic) ? + pTmr->pRmActiveOSTimerEventList : + pTmr->pRmActiveEventList; while (pScan != NULL) { @@ -734,7 +743,9 @@ _tmrInsertCallback } /*! - * Insert (time sorted) a specific event into the callback queue. + * Insert (time sorted) a specific event into the callback queue in case + * of GPU Timer. Insert a specific event on the top of callback queue in + * case of OS timer. * * Handles setting the next alarm time as well as enabling alarm if needed * @@ -753,9 +764,16 @@ _tmrInsertCallbackInList NvU64 nextAlarmTime; NV_ASSERT(!pEvent->bInUse); - pEvent->bInUse = NV_TRUE; + if (tmrIsOSTimer(pTmr, (PTMR_EVENT)pEvent)) + { + pEvent->pNext = pTmr->pRmActiveOSTimerEventList; + pTmr->pRmActiveOSTimerEventList = pEvent; + pEvent->bInUse = NV_FALSE; + return; + } + if (pTmr->pRmActiveEventList == NULL) { // Enable PTIMER interrupt. @@ -838,11 +856,19 @@ NV_STATUS tmrEventScheduleAbs_IMPL NV_STATUS rmStatus = NV_OK; PTMR_EVENT_PVT pEvent = (PTMR_EVENT_PVT)pEventPublic; - if (pTmr->getProperty(pTmr, PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS) || - (pEventPublic->flags & TMR_FLAG_USE_OS_TIMER)) + if ((pEventPublic != NULL) && (tmrIsOSTimer(pTmr, pEventPublic))) { NV_CHECK_OK(rmStatus, LEVEL_ERROR, tmrEventScheduleAbsOSTimer_HAL(pTmr, pEventPublic, Time)); + // + // Capture system time here, this will help in scheduling callbacks + // if there is a state unload before receiving the OS timer callback. + // + osGetCurrentTick(&pEvent->startTimeNs); + if (!tmrEventOnList(pTmr, pEventPublic)) + { + _tmrInsertCallback(pTmr, pEvent, Time); + } return rmStatus; } @@ -1024,6 +1050,38 @@ static void _tmrScanCallback } } +/*! + * This function removes the timer callback from the OS timer list + * after it is serviced, cancelled, or destroyed. + */ +static void +_tmrScanCallbackOSTimer +( + OBJTMR *pTmr, + PTMR_EVENT_PVT pEvent +) +{ + PTMR_EVENT_PVT pCurrent = pTmr->pRmActiveOSTimerEventList; + + if (pCurrent == pEvent) + { + pTmr->pRmActiveOSTimerEventList = pCurrent->pNext; + pEvent->pNext = NULL; + return; + } + + while (pCurrent != NULL) + { + if (pCurrent->pNext == pEvent) + { + pCurrent->pNext = pEvent->pNext; + pEvent->pNext = NULL; + break; + } + pCurrent = pCurrent->pNext; + } +} + // determine which (if any) callback should determine the next alarm time static NV_STATUS _tmrGetNextAlarmTime @@ -1200,6 +1258,7 @@ _tmrStateLoadCallbacks ) { NvU64 nextAlarmTime = 0; + PTMR_EVENT_PVT pScan = pTmr->pRmActiveOSTimerEventList; if (tmrEventsExist(pTmr)) { @@ -1224,6 +1283,18 @@ _tmrStateLoadCallbacks tmrSetAlarmIntrEnable_HAL(pGpu, pTmr); } } + + // Schedule the timer callbacks which were paused during state unload + while (pScan != NULL) + { + // + // Capture system time here, this will help in scheduling callbacks + // if there is a state unload before receiving the OS timer callback. + // + osGetCurrentTick(&pScan->startTimeNs); + tmrEventScheduleAbsOSTimer_HAL(pTmr, (PTMR_EVENT)pScan, pScan->timens); + pScan = pScan->pNext; + } } /*! @@ -1344,6 +1415,7 @@ tmrInitCallbacks_IMPL // Initialize the timer callback lists. pTmr->pRmActiveEventList = NULL; + pTmr->pRmActiveOSTimerEventList = NULL; // Everything below this comment will be removed with new API pTmr->pRmCallbackFreeList_OBSOLETE = pTmr->rmCallbackTable_OBSOLETE; @@ -1488,10 +1560,36 @@ tmrStateUnload_IMPL NvU32 flags ) { + PTMR_EVENT_PVT pScan = pTmr->pRmActiveOSTimerEventList; + NvU64 currentSysTime, elapsedTime; + // Disable Timer interrupt. tmrSetAlarmIntrDisable_HAL(pGpu, pTmr); tmrSetCountdownIntrDisable_HAL(pGpu, pTmr); + // + // Cancel OS timers, and save the time remaining for callback + // in 'timens', to reschedule after state load. + // + while (pScan != NULL) + { + osGetCurrentTick(¤tSysTime); + // + // If somehow any of the time difference is negative, + // we will use the original time duration. + // + if (currentSysTime >= pScan->startTimeNs) + { + elapsedTime = currentSysTime - pScan->startTimeNs; + if (pScan->timens > elapsedTime) + { + pScan->timens -= elapsedTime; + } + } + + tmrEventCancelOSTimer_HAL(pTmr, (PTMR_EVENT)pScan); + pScan = pScan->pNext; + } return NV_OK; } @@ -1732,6 +1830,30 @@ tmrCtrlCmdEventDestroy return NV_OK; } +NV_STATUS tmrEventServiceTimer_IMPL +( + OBJGPU *pGpu, + OBJTMR *pTmr, + PTMR_EVENT pPublicEvent +) +{ + PTMR_EVENT_PVT pEvent = (PTMR_EVENT_PVT)pPublicEvent; + NV_STATUS status = NV_ERR_INVALID_REQUEST; + + if ((pEvent == NULL) || !tmrIsOSTimer(pTmr, (PTMR_EVENT)pEvent)) + { + return status; + } + + if (tmrEventOnList(pTmr, (PTMR_EVENT)pEvent)) + { + _tmrScanCallbackOSTimer(pTmr, pEvent); + status = tmrEventServiceOSTimerCallback_HAL(pGpu, pTmr, pPublicEvent); + } + + return status; +} + /** * @brief Provides an opportunity to register some IntrService during intrStateInit. * diff --git a/src/nvidia/src/kernel/gpu/uvm/arch/turing/uvm_tu102.c b/src/nvidia/src/kernel/gpu/uvm/arch/turing/uvm_tu102.c index 799e7cfb1..faa1dca2b 100644 --- a/src/nvidia/src/kernel/gpu/uvm/arch/turing/uvm_tu102.c +++ b/src/nvidia/src/kernel/gpu/uvm/arch/turing/uvm_tu102.c @@ -35,8 +35,8 @@ NV_STATUS uvmReadAccessCntrBufferPutPtr_TU102 ( - POBJGPU pGpu, - POBJUVM pUvm, + OBJGPU *pGpu, + OBJUVM *pUvm, NvU32 *putOffset ) { @@ -49,8 +49,8 @@ uvmReadAccessCntrBufferPutPtr_TU102 NV_STATUS uvmReadAccessCntrBufferGetPtr_TU102 ( - POBJGPU pGpu, - POBJUVM pUvm, + OBJGPU *pGpu, + OBJUVM *pUvm, NvU32 *getOffset ) { @@ -62,8 +62,8 @@ uvmReadAccessCntrBufferGetPtr_TU102 NV_STATUS uvmWriteAccessCntrBufferGetPtr_TU102 ( - POBJGPU pGpu, - POBJUVM pUvm, + OBJGPU *pGpu, + OBJUVM *pUvm, NvU32 getPtrValue ) { @@ -74,8 +74,8 @@ uvmWriteAccessCntrBufferGetPtr_TU102 NV_STATUS uvmEnableAccessCntr_TU102 ( - POBJGPU pGpu, - POBJUVM pUvm, + OBJGPU *pGpu, + OBJUVM *pUvm, NvBool bIsErrorRecovery ) { @@ -105,8 +105,8 @@ uvmEnableAccessCntr_TU102 NV_STATUS uvmGetAccessCntrRegisterMappings_TU102 ( - POBJGPU pGpu, - POBJUVM pUvm, + OBJGPU *pGpu, + OBJUVM *pUvm, NvP64 *pAccessCntrBufferGet, NvP64 *pAccessCntrBufferPut, NvP64 *pAccessCntrBufferFull, @@ -138,8 +138,8 @@ uvmGetAccessCntrRegisterMappings_TU102 NV_STATUS uvmReadAccessCntrBufferFullPtr_TU102 ( - POBJGPU pGpu, - POBJUVM pUvm, + OBJGPU *pGpu, + OBJUVM *pUvm, NvBool *fullFlag ) { @@ -158,7 +158,7 @@ uvmReadAccessCntrBufferFullPtr_TU102 } NV_STATUS -uvmAccessCntrSetThreshold_TU102(POBJGPU pGpu, POBJUVM pUvm, NvU32 threshold) +uvmAccessCntrSetThreshold_TU102(OBJGPU *pGpu, OBJUVM *pUvm, NvU32 threshold) { GPU_VREG_FLD_WR_DRF_NUM(pGpu, _VIRTUAL_FUNCTION_PRIV, _ACCESS_COUNTER_CONFIG, _THRESHOLD, threshold); @@ -166,7 +166,7 @@ uvmAccessCntrSetThreshold_TU102(POBJGPU pGpu, POBJUVM pUvm, NvU32 threshold) } // Note: This function returns zero for chips which do not support the access counter. -NvU32 uvmGetAccessCounterBufferSize_TU102(POBJGPU pGpu, POBJUVM pUvm) +NvU32 uvmGetAccessCounterBufferSize_TU102(OBJGPU *pGpu, OBJUVM *pUvm) { return GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_SIZE) * @@ -174,7 +174,7 @@ NvU32 uvmGetAccessCounterBufferSize_TU102(POBJGPU pGpu, POBJUVM pUvm) } NV_STATUS -uvmAccessCntrSetGranularity_TU102(POBJGPU pGpu, POBJUVM pUvm, ACCESS_CNTR_TYPE accessCntType, NvU32 granularity) +uvmAccessCntrSetGranularity_TU102(OBJGPU *pGpu, OBJUVM *pUvm, ACCESS_CNTR_TYPE accessCntType, NvU32 granularity) { if (accessCntType == MIMC) @@ -269,8 +269,8 @@ uvmIsAccessCntrBufferPushed_TU102 NV_STATUS uvmEnableAccessCntrIntr_TU102 ( - POBJGPU pGpu, - POBJUVM pUvm, + OBJGPU *pGpu, + OBJUVM *pUvm, NvU32 intrType ) { @@ -288,8 +288,8 @@ uvmEnableAccessCntrIntr_TU102 NV_STATUS uvmDisableAccessCntrIntr_TU102 ( - POBJGPU pGpu, - POBJUVM pUvm + OBJGPU *pGpu, + OBJUVM *pUvm ) { Intr *pIntr = GPU_GET_INTR(pGpu); @@ -302,8 +302,8 @@ uvmDisableAccessCntrIntr_TU102 NV_STATUS uvmAccessCntrService_TU102 ( - POBJGPU pGpu, - POBJUVM pUvm + OBJGPU *pGpu, + OBJUVM *pUvm ) { NvU64 accessCntrAddress = 0; diff --git a/src/nvidia/src/kernel/gpu/uvm/arch/volta/uvm_gv100.c b/src/nvidia/src/kernel/gpu/uvm/arch/volta/uvm_gv100.c index 457f79b11..bcfde68b2 100644 --- a/src/nvidia/src/kernel/gpu/uvm/arch/volta/uvm_gv100.c +++ b/src/nvidia/src/kernel/gpu/uvm/arch/volta/uvm_gv100.c @@ -138,9 +138,9 @@ uvmDisableAccessCntr_GV100 uvmReadAccessCntrBufferGetPtr_HAL(pGpu, pUvm, &getPtr); if (getPtr != putPtr) { - MEMORY_DESCRIPTOR *pMemDesc = IS_GSP_CLIENT(pGpu) ? - pUvm->accessCntrBuffer.pUvmAccessCntrAllocMemDesc : - pUvm->accessCntrBuffer.pUvmAccessCntrMemDesc; + MEMORY_DESCRIPTOR *pMemDesc = RMCFG_FEATURE_PLATFORM_GSP ? + pUvm->accessCntrBuffer.pUvmAccessCntrMemDesc : + pUvm->accessCntrBuffer.pUvmAccessCntrAllocMemDesc; NvU8 *pAccessCntrBufferPage; NvU32 entriesPerPage = RM_PAGE_SIZE / NVC365_NOTIFY_BUF_SIZE; NvU32 pageSizeModBufSize = RM_PAGE_SIZE % NVC365_NOTIFY_BUF_SIZE; @@ -156,7 +156,8 @@ uvmDisableAccessCntr_GV100 NV_TRUE, NV_PROTECT_READ_WRITE, &pAddr, &pPriv); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "Failed to map access counter buffer while disabling it.\n"); + NV_PRINTF(LEVEL_ERROR, "Failed to map access counter buffer while disabling it: %d\n", + status); return status; } @@ -180,7 +181,12 @@ uvmDisableAccessCntr_GV100 NV_TRUE, NV_PROTECT_READ_WRITE, &pAddr, &pPriv); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "Failed to map access counter buffer while disabling it.\n"); + NV_PRINTF(LEVEL_ERROR, "Failed to map access counter buffer while disabling it: %d\n", + status); + + // Write get progress so far, all entries in [get, put) + // are valid or will become valid. + uvmWriteAccessCntrBufferGetPtr_HAL(pGpu, pUvm, getPtr); return status; } } diff --git a/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c b/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c index 54e772752..15639c8a3 100644 --- a/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c +++ b/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -726,6 +726,9 @@ static NvBool _gpumgrIsRmFirmwareDefaultChip(NvU32 pmcBoot42) static NvBool _gpumgrIsVgxRmFirmwareDefaultChip(NvU32 pmcBoot42) { + if (DRF_VAL(_PMC, _BOOT_42, _ARCHITECTURE, pmcBoot42) == NV_PMC_BOOT_42_ARCHITECTURE_GH100) + return NV_TRUE; + if (DRF_VAL(_PMC, _BOOT_42, _ARCHITECTURE, pmcBoot42) == NV_PMC_BOOT_42_ARCHITECTURE_AD100) return NV_TRUE; @@ -764,14 +767,14 @@ NvBool gpumgrIsDeviceRmFirmwareCapable 0x25B6, // A16 0x20F5, // A800-80 0x20F6, // A800-40 + 0x20FD, // A100T RoyB 0x26B5, // L40 0x26B8, // L40G 0x26F5, // L40-CNX + 0x27B7, // L16 0x27B8, // L4 (both SKUs) }; - NvU32 count = NV_ARRAY_ELEMENTS(defaultGspRmGpus); - NvU32 i; *pbEnabledByDefault = NV_FALSE; @@ -791,7 +794,7 @@ NvBool gpumgrIsDeviceRmFirmwareCapable if (!hypervisorIsVgxHyper() || RMCFG_FEATURE_PLATFORM_GSP) { - for (i = 0; i < count; i++) + for (NvU32 i = 0; i < NV_ARRAY_ELEMENTS(defaultGspRmGpus); i++) { if (defaultGspRmGpus[i] == devId) { @@ -822,24 +825,12 @@ static NvBool gpumgrCheckRmFirmwarePolicy if (!bRequestFwClientRm) return NV_FALSE; - NvU32 data; - if (!_gpumgrIsRmFirmwareCapableChip(pmcBoot42)) { NV_PRINTF(LEVEL_ERROR, "Disabling GSP offload -- GPU not supported\n"); return NV_FALSE; } - // Disable if RM registry override set - if (osReadRegistryDword(NULL, NV_REG_STR_RM_DISABLE_GSP_OFFLOAD, &data) == NV_OK) - { - if (data != NV_REG_STR_RM_DISABLE_GSP_OFFLOAD_FALSE) - { - NV_PRINTF(LEVEL_NOTICE, "Disabling GSP offload -- registry entry\n"); - return NV_FALSE; - } - } - return NV_TRUE; } @@ -1920,7 +1911,7 @@ gpumgrGetGpuIdInfoV2(NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS *pGpuInfo) return NV_ERR_INVALID_ARGUMENT; } - LOCK_ASSERT_AND_RETURN(rmGpuLockIsOwner()); + NV_ASSERT_OR_RETURN(gpumgrIsSafeToReadGpuInfo(), NV_ERR_INVALID_LOCK_STATE); // // We have a valid gpuInstance, so now let's get the corresponding @@ -2264,7 +2255,7 @@ gpumgrServiceInterrupts_IMPL(NvU32 gpuMask, MC_ENGINE_BITVECTOR *engineMask, NvB if (gpuIsGpuFullPower(pGpu)) { Intr *pIntr = GPU_GET_INTR(pGpu); - + // // On SLI, one OBJGPU's StateInit functions could attempt to service // interrupts on another OBJGPU which has not yet started StateInit. @@ -2297,9 +2288,75 @@ gpumgrGetGpuLockAndDrPorts NvU32 *pPinsetIn ) { - *pPinsetOut = 0; - *pPinsetIn = 0; - return NV_OK; + + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + OBJGPUGRP *pGpuGrp = NULL; + NvU32 pinsetIndex = 0, childPinset = drPinSet_None; + NvU32 i; + NvU32 gpuInstance = pGpu->gpuInstance; + NV_STATUS rmStatus; + + *pPinsetOut = drPinSet_None; + *pPinsetIn = drPinSet_None; + + if (pPeerGpu == NULL) + { + pGpuGrp = gpumgrGetGpuGrpFromGpu(pGpu); + NV_ASSERT_OR_RETURN(pGpuGrp != NULL, NV_ERR_INVALID_DATA); + + for (i = 0; i < NV2080_MAX_SUBDEVICES; i++) + { + if (pGpuGrp->SliLinkOrder[i].gpuInstance == gpuInstance) + { + break; + } + } + + if (i == NV2080_MAX_SUBDEVICES) + { + *pPinsetOut = 0; + *pPinsetIn = 0; + } + else + { + *pPinsetOut = pGpuGrp->SliLinkOrder[i].ChildDrPort; + *pPinsetIn = pGpuGrp->SliLinkOrder[i].ParentDrPort; + } + + return NV_OK; + } + else + { + NvU32 childPinsetIndex; + + for (pinsetIndex = 0; pinsetIndex < DR_PINSET_COUNT; pinsetIndex++) + { + if (!FLD_TEST_DRF(_SLILINK, _ROUTE, _INPUT, _PASSED, + pGpuMgr->gpuSliLinkRoute[pGpuMgr->gpuBridgeType][gpuInstance][pPeerGpu->gpuInstance][pinsetIndex])) + { + continue; + } + + childPinset = DRF_VAL(_SLILINK, _ROUTE, _INPUT_CHILD_PORT, + pGpuMgr->gpuSliLinkRoute[pGpuMgr->gpuBridgeType][gpuInstance][pPeerGpu->gpuInstance][pinsetIndex]); + + rmStatus = gpumgrPinsetToPinsetTableIndex(childPinset, &childPinsetIndex); + if (rmStatus != NV_OK) + { + return rmStatus; + } + if (!FLD_TEST_DRF(_SLILINK, _ROUTE, _OUTPUT, _PASSED, + pGpuMgr->gpuSliLinkRoute[pGpuMgr->gpuBridgeType][pPeerGpu->gpuInstance][gpuInstance][childPinsetIndex])) + { + continue; + } + *pPinsetOut |= childPinset; + *pPinsetIn |= NVBIT(pinsetIndex); + } + return ((*pPinsetOut != drPinSet_None) && (*pPinsetIn != drPinSet_None)) ? NV_OK : NV_ERR_INVALID_ARGUMENT; + } + } // @@ -3015,6 +3072,128 @@ gpumgrGetGpuInitDisabledNvlinks_IMPL return status; } +/*! + * @brief Get nvlink bandwidth mode + * + * @return mode reduced bandwidth mode. + */ +NvU8 +gpumgrGetGpuNvlinkBwMode_IMPL(void) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + + return pGpuMgr->nvlinkBwMode; +} + +/*! + * @brief Set nvlink bandwidth mode from Registry + * + * @param[in] pGpu reference of OBJGPU + * + */ +void +gpumgrSetGpuNvlinkBwModeFromRegistry_IMPL +( + OBJGPU *pGpu +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + const char *pStrChar; + NvU32 strLength = 32; + NvU8 pStr[32]; + + // + // An RM client can set NVLink BW mode using + // NV0000_CTRL_CMD_GPU_SET_NVLINK_BW_MODE control call. + // If the value is not default i.e. `GPU_NVLINK_BW_MODE_FULL`, then skip. + // + if (pGpuMgr->nvlinkBwMode != GPU_NVLINK_BW_MODE_FULL) + { + return; + } + + // sysInitRegistryOverrides should pass in valid pGpu + NV_ASSERT (pGpu != NULL); + + if (osReadRegistryString(pGpu, NV_REG_STR_RM_NVLINK_BW, pStr, &strLength) != NV_OK) + { + goto out; + } + + pStrChar = (const char *)pStr; + strLength = portStringLength(pStrChar); + if (portStringCompare(pStrChar, "OFF", strLength) == 0) + { + pGpuMgr->nvlinkBwMode = GPU_NVLINK_BW_MODE_OFF; + } + else if (portStringCompare(pStrChar, "MIN", strLength) == 0) + { + pGpuMgr->nvlinkBwMode = GPU_NVLINK_BW_MODE_MIN; + } + else if (portStringCompare(pStrChar, "HALF", strLength) == 0) + { + pGpuMgr->nvlinkBwMode = GPU_NVLINK_BW_MODE_HALF; + } + else if (portStringCompare(pStrChar, "3QUARTER", strLength) == 0) + { + pGpuMgr->nvlinkBwMode = GPU_NVLINK_BW_MODE_3QUARTER; + } + +out: + NV_PRINTF(LEVEL_INFO, "nvlinkBwMode=%d\n", pGpuMgr->nvlinkBwMode); +} + +/*! + * @brief Set nvlink bandwidth mode + * + * @param[in] mode nvlink bandwidth mode + * + * @return NV_OK on success, appropriate error on failure. + */ +NV_STATUS +gpumgrSetGpuNvlinkBwMode_IMPL +( + NvU8 mode +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + NvU32 attachedGpuCount; + NvU32 attachedGpuMask; + KernelBus *pKernelBus; + NV_STATUS rmStatus; + NvU32 gpuIndex; + OBJGPU *pGpu; + + rmStatus = gpumgrGetGpuAttachInfo(&attachedGpuCount, &attachedGpuMask); + if (rmStatus != NV_OK) + { + return rmStatus; + } + + gpuIndex = 0; + for(pGpu = gpumgrGetNextGpu(attachedGpuMask, &gpuIndex); + pGpu != NULL; + pGpu = gpumgrGetNextGpu(attachedGpuMask, &gpuIndex)) + { + pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + if (pKernelBus->totalP2pObjectsAliveRefCount > 0) + { + return NV_ERR_IN_USE; + } + } + + if (mode > GPU_NVLINK_BW_MODE_3QUARTER) + { + return NV_ERR_INVALID_ARGUMENT; + } + + pGpuMgr->nvlinkBwMode = mode; + return NV_OK; +} + /*! * @brief Adds an entry in the system partition topology save for the given GPU * ID. Note that this does not create any saved partition topology. @@ -3044,7 +3223,7 @@ gpumgrAddSystemMIGInstanceTopo_IMPL { pGpuMgr->MIGTopologyInfo[i].bValid = NV_TRUE; pGpuMgr->MIGTopologyInfo[i].domainBusDevice = domainBusDevice; - + // Set MIG enablement to disabled by default pGpuMgr->MIGTopologyInfo[i].bMIGEnabled = NV_FALSE; break; @@ -3146,9 +3325,9 @@ gpumgrIsSystemMIGEnabled_IMPL * @returns NV_TRUE if entry found * NV_FALSE otherwise */ -void +void gpumgrSetSystemMIGEnabled_IMPL -( +( NvU64 domainBusDevice, NvBool bMIGEnabled ) @@ -3264,7 +3443,7 @@ gpumgrGetGpuBridgeType(void) { OBJSYS *pSys = SYS_GET_INSTANCE(); OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); - + return pGpuMgr->gpuBridgeType; } @@ -3286,7 +3465,7 @@ gpumgrInitPcieP2PCapsCache_IMPL(OBJGPUMGR* pGpuMgr) /** * @brief Destroy the PCIE P2P info cache */ -void +void gpumgrDestroyPcieP2PCapsCache_IMPL(OBJGPUMGR* pGpuMgr) { PCIEP2PCAPSINFO *pPcieCapsInfo, *pPcieCapsInfoNext; @@ -3313,7 +3492,7 @@ gpumgrDestroyPcieP2PCapsCache_IMPL(OBJGPUMGR* pGpuMgr) * @param[in] gpuMask NvU32 value * @param[in] p2pWriteCapsStatus NvU8 value * @param[in] pP2PReadCapsStatus NvU8 value - * + * * @return NV_OK or NV_ERR_NO_MEMORY */ NV_STATUS @@ -3463,7 +3642,7 @@ gpumgrGetPcieP2PCapsFromCache_IMPL OBJSYS *pSys = SYS_GET_INSTANCE(); OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); NvBool bFound; - + portSyncMutexAcquire(pGpuMgr->pcieP2PCapsInfoLock); bFound = _gpumgrGetPcieP2PCapsFromCache(gpuMask, pP2PWriteCapsStatus, pP2PReadCapsStatus); @@ -3522,3 +3701,20 @@ NvBool gpumgrAreAllGpusInOffloadMode(void) return pGpuMgr->gpuMonolithicRmMask == 0; } + +NvBool gpumgrIsSafeToReadGpuInfo(void) +{ + // + // A thread that tears down the GPU must own both the API lock for WRITE + // and all GPU locks. + // + // Conversely, if you hold the API lock (either READ or WRITE), or hold + // any GPU locks, you know that no GPUs will be freed from under you. + // + + // + // NOTE: Currently rmapiLockIsOwner() returns TRUE if you own the lock in + // either READ or WRITE modes + // + return rmapiLockIsOwner() || (rmGpuLocksGetOwnedMask() != 0); +} diff --git a/src/nvidia/src/kernel/gpu_mgr/gpu_mgr_sli.c b/src/nvidia/src/kernel/gpu_mgr/gpu_mgr_sli.c new file mode 100644 index 000000000..39e435b7a --- /dev/null +++ b/src/nvidia/src/kernel/gpu_mgr/gpu_mgr_sli.c @@ -0,0 +1,598 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/***************************** HW State Routines ***************************\ +* * +* SLI specific GPU Manager functions * +* * +\***************************************************************************/ + +#include "core/system.h" +#include "core/thread_state.h" +#include "core/locks.h" +#include "os/os.h" +#include "gpu/mem_mgr/mem_mgr.h" +#include "kernel/gpu/intr/intr.h" +#include "kernel/gpu/rc/kernel_rc.h" +#include "kernel/gpu/mig_mgr/kernel_mig_manager.h" +#include "gpu/disp/kern_disp.h" +#include "gpu/mem_mgr/mem_desc.h" +#include "platform/sli/sli.h" +#include "nvpcie.h" +#include "nvhybridacpi.h" +#include "platform/platform.h" +#include "gpu_mgr/gpu_mgr.h" +#include "gpu_mgr/gpu_mgr_sli.h" +#include "gpu_mgr/gpu_group.h" +#include "kernel/gpu/nvlink/kernel_nvlink.h" +#include "kernel/gpu/rc/kernel_rc.h" + +#include "nvRmReg.h" + +#include "ctrl/ctrl0000/ctrl0000gpu.h" +#include "nvlimits.h" + +static NV_STATUS gpumgrStateInitialized(void); + +void +gpumgrDetectSliLinkFromGpus +( + NvBool bForceDetection, + NvU32 gpuCount, + NvU32 gpuMaskArg, + NvU32 *pSliLinkTestDone, + NvU32 *pSliLinkOutputMask, + NvBool *pSliLinkCircular, + NvU32 *pSliLinkEndsMask, + NvU32 *pVidLinkCount +) +{ + OBJGPU *pGpu; + OBJGPU *pGpuSaved; + NvU32 gpuIndex = 0; + NvU32 EndsMask = 0; + NvU32 gpuMask = gpuMaskArg; + NvU32 linkTestDone = 0, linkOutputMask = 0; + NvBool bSliLinkCircular = NV_FALSE; + NvU32 vidLinkCount = 0; + NvU32 linkHalImpl; + NvBool *pBcState; + NvU32 gpuIndexInBcStateTable; + + *pSliLinkTestDone = *pSliLinkOutputMask = *pSliLinkEndsMask = 0; + + // Bail out early if all GPU'S haven't been loaded. + if (gpumgrStateInitialized() != NV_OK) + { + NV_PRINTF(LEVEL_WARNING, + "All GPUs do not have state initialized\n"); + return; + } + + // If there's only 1 bit set or no bits set here then this call + // is not going to help! + if (gpuCount < 2) + { + // If we've gotten here, then that means the caller is calling + // before more than one GPU is setup + NV_PRINTF(LEVEL_INFO, + "gpumgrDetectSliLinkFromGpus: Need >=2 GPUs to test SliLink.\n gpuMask = 0x%x\n", + gpuMask); + return; + } + + // If we've already done the detection on this set of gpus + // return the output mask. + + if ((linkTestDone == gpuMask) && !bForceDetection) + { + *pSliLinkTestDone = linkTestDone; + *pSliLinkOutputMask = linkOutputMask; + *pSliLinkCircular = bSliLinkCircular; + *pSliLinkEndsMask = EndsMask; + *pVidLinkCount = vidLinkCount; + return; + } + + // Bail early if one of the GPUs does not have a display engine + gpuIndex = 0; + while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex)) != NULL) + { + KernelDisplay *pKernelDisp = GPU_GET_KERNEL_DISPLAY(pGpu); + if ( + pKernelDisp == NULL) + { + *pSliLinkTestDone = gpuMask; + *pSliLinkOutputMask = 0; + return; + } + } + + // clear out linkTestDone, linkOutputMask, circularVideoBridge + linkTestDone = linkOutputMask = 0; + bSliLinkCircular = NV_FALSE; + + // Check that all GPUs have the same HAL + gpuIndex = 0; + pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex); + if (pGpu != NULL) + { + pGpuSaved = pGpu; + linkHalImpl = gpuGetSliLinkDetectionHalFlag_HAL(pGpu); + } + else + { + *pSliLinkTestDone = gpuMask; + *pSliLinkOutputMask = 0; + return; + } + + pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex); + while (pGpu != NULL) + { + if (linkHalImpl != gpuGetSliLinkDetectionHalFlag_HAL(pGpu)) + { + *pSliLinkTestDone = gpuMask; + *pSliLinkOutputMask = 0; + return; + } + pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex); + } + + // Make sure BC is disabled + pBcState = portMemAllocNonPaged(gpuCount * sizeof(NvBool)); + if (pBcState == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "gpumgrDetectSliLinkFromGpus: Insufficient resources.\n"); + return; + } + + gpuIndex = 0; + gpuIndexInBcStateTable = 0; + pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex); + while (pGpu != NULL) + { + if (IsSLIEnabled(pGpu)) + { + pBcState[gpuIndexInBcStateTable++] = gpumgrGetBcEnabledStatus(pGpu); + gpumgrSetBcEnabledStatus(pGpu, NV_FALSE); + } + pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex); + } + + // Call HAL function + gpuDetectSliLinkFromGpus_HAL(pGpuSaved, gpuCount, gpuMaskArg, + &linkOutputMask, + &bSliLinkCircular, + &EndsMask, + &vidLinkCount); + + // Restore BC settings + gpuIndex = 0; + gpuIndexInBcStateTable = 0; + pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex); + while (pGpu != NULL) + { + if (IsSLIEnabled(pGpu)) + { + gpumgrSetBcEnabledStatus(pGpu, pBcState[gpuIndexInBcStateTable++]); + } + + // Clear high speed bridge property here on all GPUs. + // We set it in gpumgrDetectHighSpeedVideoBridges() for the GPUs in the video link. + pGpu->setProperty(pGpu, PDB_PROP_GPU_HIGH_SPEED_BRIDGE_CONNECTED, NV_FALSE); + + pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex); + } + + portMemFree(pBcState); + + linkTestDone = gpuMaskArg; + + // See if we want to disable SLI Video Bridge - Bug 174307 + // Only need to read the regkey if we passed the detection code + if (linkOutputMask) + { + gpuMask = linkOutputMask; + + gpuIndex = 0; + for (pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex); + NULL != pGpu; + pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex)) + { + if (gpuIsVideoLinkDisabled(pGpu)) + { + // Remove all gpus if this regkey is found on any gpu + linkOutputMask = 0; + } + } + } + + gpumgrDetectHighSpeedVideoBridges(linkOutputMask); + + *pSliLinkOutputMask = linkOutputMask; + *pSliLinkTestDone = linkTestDone; + *pSliLinkCircular = bSliLinkCircular; + *pSliLinkEndsMask = EndsMask; + *pVidLinkCount = vidLinkCount; +} + + +// +// Return a status indicating whether all GPU's have been initialized via StateInit(). +// +static NV_STATUS gpumgrStateInitialized(void) +{ + OBJGPU *pGpu = NULL; + NvU32 gpuMask = 0; + NvU32 gpuCount = 0; + NvU32 gpuIndex = 0; + NV_STATUS status = NV_OK; + + gpumgrGetGpuAttachInfo(&gpuCount, &gpuMask); + + pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex); + if (pGpu == NULL) + { + return NV_ERR_INVALID_POINTER; + } + + do + { + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_STATE_INITIALIZED)) + { + status = NV_ERR_INVALID_STATE; + } + + pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex); + + } while (pGpu); + + return (status); +} + +/*! + * @brief Updates the GPU routing information for the + * 2 specified GPUs using the 2 Pinset Indices specified. + * + * @param[In] pGpuParent The 1st GPU to be tested for a connection. + * pGpuChild The 2nd GPU to be tested for a connection with the 1st GPU. + * bridgeType The type of bridge whose routing information + * should be updated withthe resiults of the testing. + * parentPinsetIndex The pinset index to be used on the GpuParent + * to test for an SLI connection. + * childPinsetIndex The pinset index to be used on the GpuChild + * to test for an SLI connection. + * bForceUpdate Will be NV_TRUE if we want to force update the SLI link even + * with no video link detected. + * + * @retun a boolen indicating if the SLI connection specified + * by the pinset indices is valid between the 2 specified GPUs. +.*/ +NvBool gpumgrUpdateSliLinkRouting +( + OBJGPU *pGpuParent, + OBJGPU *pGpuChild, + NvU32 bridgeType, + NvU32 parentPinsetIndex, + NvU32 childPinsetIndex, + NvBool bForceUpdate +) +{ + + NvBool linkFound = NV_FALSE; + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + KernelDisplay *pKernelDisp = GPU_GET_KERNEL_DISPLAY(pGpuParent); + + NV_ASSERT_OR_RETURN(!IS_GSP_CLIENT(pGpuParent) || pKernelDisp != NULL, NV_FALSE); + + // run the test. It is bidirectional + if (!bForceUpdate) + { + if (pKernelDisp != NULL) + linkFound = kdispDetectSliLink_HAL(pKernelDisp, pGpuParent, pGpuChild, NVBIT(parentPinsetIndex), NVBIT(childPinsetIndex)) == NV_OK; + } + + if (linkFound || bForceUpdate) + { + // Store off the input connection between Parent and Child here + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuParent->gpuInstance][pGpuChild->gpuInstance][parentPinsetIndex] = + FLD_SET_DRF(_SLILINK, _ROUTE, _INPUT, _PASSED, + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuParent->gpuInstance][pGpuChild->gpuInstance][parentPinsetIndex]); + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuChild->gpuInstance][pGpuParent->gpuInstance][childPinsetIndex] = + FLD_SET_DRF(_SLILINK, _ROUTE, _INPUT, _PASSED, + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuChild->gpuInstance][pGpuParent->gpuInstance][childPinsetIndex]); + + // Store off the output connection between Parent and Child here + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuParent->gpuInstance][pGpuChild->gpuInstance][parentPinsetIndex] = + FLD_SET_DRF(_SLILINK, _ROUTE, _OUTPUT, _PASSED, + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuParent->gpuInstance][pGpuChild->gpuInstance][parentPinsetIndex]); + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuChild->gpuInstance][pGpuParent->gpuInstance][childPinsetIndex] = + FLD_SET_DRF(_SLILINK, _ROUTE, _OUTPUT, _PASSED, + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuChild->gpuInstance][pGpuParent->gpuInstance][childPinsetIndex]); + + // Store off the Child Port used by the Parent + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuParent->gpuInstance][pGpuChild->gpuInstance][parentPinsetIndex] = + FLD_SET_DRF_NUM(_SLILINK, _ROUTE, _INPUT_CHILD_PORT, (NvU8) NVBIT(childPinsetIndex), + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuParent->gpuInstance][pGpuChild->gpuInstance][parentPinsetIndex]); + + // Store off the Parent Port used by the Child + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuChild->gpuInstance][pGpuParent->gpuInstance][childPinsetIndex] = + FLD_SET_DRF_NUM(_SLILINK, _ROUTE, _INPUT_CHILD_PORT, (NvU8) NVBIT(parentPinsetIndex), + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuChild->gpuInstance][pGpuParent->gpuInstance][childPinsetIndex]); + + // Setup GPUs to reference each other + pGpuParent->peer[parentPinsetIndex].pGpu = pGpuChild; + pGpuParent->peer[parentPinsetIndex].pinset = NVBIT(childPinsetIndex); + pGpuChild->peer[childPinsetIndex].pGpu = pGpuParent; + pGpuChild->peer[childPinsetIndex].pinset = NVBIT(parentPinsetIndex); + } + else + { + // Make sure to not override any passing cases with a failure + // Store off the failed input connection between Parent & Child here + if (!FLD_TEST_DRF(_SLILINK, _ROUTE, _INPUT, _PASSED, + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuParent->gpuInstance][pGpuChild->gpuInstance][parentPinsetIndex])) + { + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuParent->gpuInstance][pGpuChild->gpuInstance][parentPinsetIndex] = + FLD_SET_DRF(_SLILINK, _ROUTE, _INPUT, _FAILED, + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuParent->gpuInstance][pGpuChild->gpuInstance][parentPinsetIndex]); + } + if (!FLD_TEST_DRF(_SLILINK, _ROUTE, _INPUT, _PASSED, + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuChild->gpuInstance][pGpuParent->gpuInstance][childPinsetIndex])) + { + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuChild->gpuInstance][pGpuParent->gpuInstance][childPinsetIndex] = + FLD_SET_DRF(_SLILINK, _ROUTE, _INPUT, _FAILED, + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuChild->gpuInstance][pGpuParent->gpuInstance][childPinsetIndex ]); + } + // Store off the failed output connection between Child & Parent here + if (!FLD_TEST_DRF(_SLILINK, _ROUTE, _OUTPUT, _PASSED, + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuParent->gpuInstance][pGpuChild->gpuInstance][parentPinsetIndex])) + { + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuParent->gpuInstance][pGpuChild->gpuInstance][parentPinsetIndex] = + FLD_SET_DRF(_SLILINK, _ROUTE, _OUTPUT, _FAILED, + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuParent->gpuInstance][pGpuChild->gpuInstance][parentPinsetIndex]); + } + if (!FLD_TEST_DRF(_SLILINK, _ROUTE, _OUTPUT, _PASSED, + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuChild->gpuInstance][pGpuParent->gpuInstance][childPinsetIndex])) + { + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuChild->gpuInstance][pGpuParent->gpuInstance][childPinsetIndex] = + FLD_SET_DRF(_SLILINK, _ROUTE, _OUTPUT, _FAILED, + pGpuMgr->gpuSliLinkRoute[bridgeType][pGpuChild->gpuInstance][pGpuParent->gpuInstance][childPinsetIndex ]); + } + } + return linkFound; +} + +NvBool +gpumgrDetectHighSpeedVideoBridges(NvU32 linkOutputMask) +{ + OBJGPU *pGpu; + KernelDisplay *pKernelDisp; + NvU32 gpuIndex; + NvBool bHighSpeedBridgeConnected = NV_FALSE; + + gpuIndex = 0; + while ((pGpu = gpumgrGetNextGpu(linkOutputMask, &gpuIndex))) + { + pKernelDisp = GPU_GET_KERNEL_DISPLAY(pGpu); + + if ( + (pKernelDisp == NULL)) + { + NV_ASSERT(pKernelDisp != NULL); // This should not happen + continue; + } + + // + // Only one GPU in the link is able to detect a high speed bridge. + // 3-way SLI, bridged 4-way SLI are not supported, so it is OK. + // + pGpu->setProperty(pGpu, PDB_PROP_GPU_HIGH_SPEED_BRIDGE_CONNECTED, NV_FALSE); + + NvU32 gpuLockMask = 0; + if (IS_GSP_CLIENT(pGpu) && !rmDeviceGpuLockIsOwner(pGpu->gpuInstance)) + NV_ASSERT_OK_OR_RETURN(rmGpuGroupLockAcquire(pGpu->gpuInstance, + GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_RPC, + &gpuLockMask)); + + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV_STATUS status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_DETECT_HS_VIDEO_BRIDGE, + NULL, + 0); + + bHighSpeedBridgeConnected |= (status == NV_OK); + + if (gpuLockMask != 0) + rmGpuGroupLockRelease(gpuLockMask, GPUS_LOCK_FLAGS_NONE); + } + + if (bHighSpeedBridgeConnected) + { + // + // Update video bridge max pixelclock to the fast video bridge limit. + // We are here because no slow video bridge ic\s connected to any connectors, + // and a high speed video bridge is connected at least on one of the connectors. + // + gpuIndex = 0; + while ((pGpu = gpumgrGetNextGpu(linkOutputMask, &gpuIndex))) + { + pKernelDisp = GPU_GET_KERNEL_DISPLAY(pGpu); + + if ( + (pKernelDisp == NULL)) + { + NV_ASSERT(pKernelDisp != NULL); // This should not happen + continue; + } + + // Set high speed bridge property on all GPUs. + pGpu->setProperty(pGpu, PDB_PROP_GPU_HIGH_SPEED_BRIDGE_CONNECTED, NV_TRUE); + } + } + return bHighSpeedBridgeConnected; +} + +/*! + * @brief Returns the pinset index to be used in an array from the pinset definition + * + * @param[In] pinset NvU32, Pinset value. Should have only one bit set. + * @param[Out] pPinsetIndex NvU32*, Pinset index value to be used in an array. +.*/ +NV_STATUS +gpumgrPinsetToPinsetTableIndex(NvU32 pinset, NvU32 *pPinsetIndex) +{ + NvU32 pinsetIndex; + if (!ONEBITSET(pinset)) + { + NV_PRINTF(LEVEL_ERROR, "More than one bit set: 0x%x\n", pinset); + DBG_BREAKPOINT(); + return NV_ERR_INVALID_ARGUMENT; + } + + switch (pinset) + { + case drPinSet_A: + case drPinSet_B: + break; + case drPinSet_None: + default: + NV_PRINTF(LEVEL_ERROR, "Unknown pin set value: 0x%x\n", pinset); + DBG_BREAKPOINT(); + return NV_ERR_INVALID_ARGUMENT; + } + pinsetIndex = pinset - 1; + NUMSETBITS_32(pinsetIndex); + + *pPinsetIndex = pinsetIndex; + return NV_OK; +} + +// +// gpumgrGetSliLinks +// +// This routine services the NV0000_CTRL_CMD_GPU_GET_VIDEO_LINKS +// command. The passed in table is filled in with information +// about SLI connections (video bridge or NvLinks) between GPUs identified by their +// GPU IDs. Each row represents the connections, if any, for a +// single GPU. Peer GPUs are listed using their GPU IDs, invalid +// entries are filled with invalid ID values. +// +NV_STATUS +gpumgrGetSliLinks(NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS *pVideoLinksParams) +{ + NvU32 i, j; + NvU32 gpuIndex, peerGpuIndex; + NvU32 pinsetIndex, childDrPort, childDrPortIndex; + NV0000_CTRL_GPU_VIDEO_LINKS *pSliLinks; + OBJGPU *pGpu, *pPeerGpu; + OBJSYS *pSys; + OBJGPUMGR *pGpuMgr; + NvU32 gpuAttachCnt, gpuAttachMask; + NV_STATUS rmStatus = NV_OK; + + for (i = 0; i < NV0000_CTRL_GPU_MAX_ATTACHED_GPUS; i++) + { + pSliLinks = &pVideoLinksParams->links[i]; + + for (j = 0; j < NV0000_CTRL_GPU_MAX_VIDEO_LINKS; j++) + { + pSliLinks->connectedGpuIds[j] = NV0000_CTRL_GPU_INVALID_ID; + } + pSliLinks->gpuId = NV0000_CTRL_GPU_INVALID_ID; + } + + gpumgrGetGpuAttachInfo(&gpuAttachCnt, &gpuAttachMask); + if (gpuAttachCnt < 2) + { + return NV_OK; + } + + pSys = SYS_GET_INSTANCE(); + pGpuMgr = SYS_GET_GPUMGR(pSys); + + i = gpuIndex = 0; + while ((pGpu = gpumgrGetNextGpu(gpuAttachMask, &gpuIndex)) && + (i < NV0000_CTRL_GPU_MAX_ATTACHED_GPUS)) + { + if (pGpu->gpuInstance >= NV2080_MAX_SUBDEVICES) + { + NV_ASSERT(pGpu->gpuInstance < NV2080_MAX_SUBDEVICES); + continue; + } + + pSliLinks = &pVideoLinksParams->links[i++]; + pSliLinks->gpuId = pGpu->gpuId; + + j = peerGpuIndex = 0; + while ((pPeerGpu = gpumgrGetNextGpu(gpuAttachMask, &peerGpuIndex)) && + (j < NV0000_CTRL_GPU_MAX_VIDEO_LINKS)) + { + if ((peerGpuIndex == gpuIndex) || + (pPeerGpu->gpuInstance >= NV2080_MAX_SUBDEVICES)) + { + continue; + } + + for (pinsetIndex = 0; pinsetIndex < DR_PINSET_COUNT; pinsetIndex++) + { + if (!FLD_TEST_DRF(_SLILINK, _ROUTE, _INPUT, _PASSED, + pGpuMgr->gpuSliLinkRoute[pGpuMgr->gpuBridgeType][pGpu->gpuInstance][pPeerGpu->gpuInstance][pinsetIndex])) + { + continue; + } + + childDrPort = DRF_VAL(_SLILINK, _ROUTE, _INPUT_CHILD_PORT, + pGpuMgr->gpuSliLinkRoute[pGpuMgr->gpuBridgeType][pGpu->gpuInstance][pPeerGpu->gpuInstance][pinsetIndex]); + + if (SLI_BT_VIDLINK == pGpuMgr->gpuBridgeType) + { + rmStatus = gpumgrPinsetToPinsetTableIndex(childDrPort, &childDrPortIndex); + if (rmStatus != NV_OK) + { + return rmStatus; + } + + if (!FLD_TEST_DRF(_SLILINK, _ROUTE, _OUTPUT, _PASSED, + pGpuMgr->gpuSliLinkRoute[pGpuMgr->gpuBridgeType][pPeerGpu->gpuInstance][pGpu->gpuInstance][childDrPortIndex])) + { + continue; + } + } + + if (j < NV0000_CTRL_GPU_MAX_VIDEO_LINKS) + { + pSliLinks->connectedGpuIds[j++] = pPeerGpu->gpuId; + } + } + } + } + return NV_OK; +} diff --git a/src/nvidia/src/kernel/mem_mgr/ctx_buf_pool.c b/src/nvidia/src/kernel/mem_mgr/ctx_buf_pool.c index b25fc57b6..8b3297d46 100644 --- a/src/nvidia/src/kernel/mem_mgr/ctx_buf_pool.c +++ b/src/nvidia/src/kernel/mem_mgr/ctx_buf_pool.c @@ -244,7 +244,8 @@ ctxBufPoolReserve ) { NV_STATUS status = NV_OK; - NvU32 pageSize, i; + NvU64 pageSize; + NvU32 i; NvU64 totalSize[RM_ATTR_PAGE_SIZE_INVALID] = {0}; NvU64 size; @@ -280,10 +281,10 @@ ctxBufPoolReserve totalSize[RM_ATTR_PAGE_SIZE_512MB] += size; break; default: - NV_PRINTF(LEVEL_ERROR, "Unrecognized/unsupported page size = 0x%x\n", pageSize); + NV_PRINTF(LEVEL_ERROR, "Unrecognized/unsupported page size = 0x%llx\n", pageSize); NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_ARGUMENT); } - NV_PRINTF(LEVEL_INFO, "Reserving 0x%llx bytes for buf Id = 0x%x in pool with page size = 0x%x\n", size, i, pageSize); + NV_PRINTF(LEVEL_INFO, "Reserving 0x%llx bytes for buf Id = 0x%x in pool with page size = 0x%llx\n", size, i, pageSize); } for (i = 0; i < RM_ATTR_PAGE_SIZE_INVALID; i++) @@ -382,10 +383,10 @@ ctxBufPoolAllocate } // If page size is not set, then set it based on actual size of memdesc and its alignment - NvU32 pageSize = memdescGetPageSize(pMemDesc, AT_GPU); + NvU64 pageSize = memdescGetPageSize(pMemDesc, AT_GPU); if ((pageSize == 0) || (memdescGetContiguity(pMemDesc, AT_GPU))) { - NvU32 newPageSize; + NvU64 newPageSize; NV_ASSERT_OK_OR_RETURN(ctxBufPoolGetSizeAndPageSize(pCtxBufPool, pMemDesc->pGpu, pMemDesc->Alignment, RM_ATTR_PAGE_SIZE_DEFAULT, memdescGetContiguity(pMemDesc, AT_GPU), &pMemDesc->ActualSize, &newPageSize)); @@ -400,7 +401,7 @@ ctxBufPoolAllocate if (pageSize == 0) { memdescSetPageSize(pMemDesc, AT_GPU, newPageSize); - NV_PRINTF(LEVEL_INFO, "Ctx buffer page size set to 0x%x\n", newPageSize); + NV_PRINTF(LEVEL_INFO, "Ctx buffer page size set to 0x%llx\n", newPageSize); } pageSize = newPageSize; } @@ -422,11 +423,11 @@ ctxBufPoolAllocate pPool = pCtxBufPool->pMemPool[RM_ATTR_PAGE_SIZE_512MB]; break; default: - NV_PRINTF(LEVEL_ERROR, "Unsupported page size = 0x%x set for context buffer\n", pageSize); + NV_PRINTF(LEVEL_ERROR, "Unsupported page size = 0x%llx set for context buffer\n", pageSize); NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_ARGUMENT); } NV_ASSERT_OK_OR_RETURN(rmMemPoolAllocate(pPool, (RM_POOL_ALLOC_MEMDESC*)pMemDesc)); - NV_PRINTF(LEVEL_INFO, "Buffer allocated from ctx buf pool with page size = 0x%x\n", pageSize); + NV_PRINTF(LEVEL_INFO, "Buffer allocated from ctx buf pool with page size = 0x%llx\n", pageSize); return NV_OK; } @@ -449,7 +450,7 @@ ctxBufPoolFree NV_ASSERT_OR_RETURN(pCtxBufPool != NULL, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(pMemDesc != NULL, NV_ERR_INVALID_ARGUMENT); - NvU32 pageSize = memdescGetPageSize(pMemDesc, AT_GPU); + NvU64 pageSize = memdescGetPageSize(pMemDesc, AT_GPU); // // If buffer is contiguous, then it may or may not be allocated from the same pool @@ -502,7 +503,7 @@ ctxBufPoolFree } rmMemPoolFree(pPool, (RM_POOL_ALLOC_MEMDESC*)pMemDesc, 0); - NV_PRINTF(LEVEL_INFO, "Buffer freed from ctx buf pool with page size = 0x%x\n", pageSize); + NV_PRINTF(LEVEL_INFO, "Buffer freed from ctx buf pool with page size = 0x%llx\n", pageSize); return NV_OK; } @@ -572,12 +573,12 @@ ctxBufPoolGetSizeAndPageSize RM_ATTR_PAGE_SIZE attr, NvBool bContig, NvU64 *pSize, - NvU32 *pPageSize + NvU64 *pPageSize ) { MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); NV_STATUS status = NV_OK; - NvU32 pageSize = 0; + NvU64 pageSize = 0; NvU32 allocFlags = 0; NvU32 retAttr = 0; NvU32 retAttr2 = 0; @@ -679,7 +680,7 @@ ctxBufPoolGetSizeAndPageSize *pPageSize = pageSize; *pSize = size; - NV_PRINTF(LEVEL_INFO, "Buffer updated size = 0x%llx with page size = 0x%x\n", size, pageSize); + NV_PRINTF(LEVEL_INFO, "Buffer updated size = 0x%llx with page size = 0x%llx\n", size, pageSize); return status; } diff --git a/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c b/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c index 0cfc56059..f2284b8c1 100644 --- a/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c +++ b/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -52,6 +52,8 @@ #include "mem_mgr/virt_mem_mgr.h" #include "published/ampere/ga100/dev_mmu.h" +#include "vgpu/rpc.h" +#include "virtualization/hypervisor/hypervisor.h" @@ -708,17 +710,23 @@ fabricvaspaceGetGpaMemdesc_IMPL MEMORY_DESCRIPTOR **ppAdjustedMemdesc ) { - KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pMappingGpu); - MEMORY_DESCRIPTOR *pRootMemDesc = NULL; - NODE *pNode = NULL; - NV_STATUS status = NV_OK; - NvU64 rootOffset = 0; + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pMappingGpu); + MEMORY_DESCRIPTOR *pRootMemDesc = NULL; + NODE *pNode = NULL; + NV_STATUS status = NV_OK; + NvU64 rootOffset = 0; + NvBool bLoopbackSupported = NV_FALSE; NV_ASSERT_OR_RETURN(ppAdjustedMemdesc != NULL, NV_ERR_INVALID_ARGUMENT); + { + bLoopbackSupported = pKernelNvlink != NULL && + (knvlinkIsP2pLoopbackSupported(pMappingGpu, pKernelNvlink) || + knvlinkIsForcedConfig(pMappingGpu, pKernelNvlink)); + } + if (memdescGetAddressSpace(pFabricMemdesc) != ADDR_FABRIC_V2 || - (pKernelNvlink != NULL && - knvlinkIsP2pLoopbackSupported(pMappingGpu, pKernelNvlink))) + bLoopbackSupported) { *ppAdjustedMemdesc = pFabricMemdesc; return NV_OK; @@ -874,11 +882,11 @@ _fabricVaspaceValidateMapAttrs ( NvU64 fabricOffset, NvU64 fabricAllocSize, - NvU32 fabricPageSize, + NvU64 fabricPageSize, NvU64 physMapOffset, NvU64 physMapLength, NvU64 physAllocSize, - NvU32 physPageSize + NvU64 physPageSize ) { // Fabric mem offset should be at least phys page size aligned. @@ -1002,7 +1010,7 @@ fabricvaspaceUnmapPhysMemdesc_IMPL FABRIC_VASPACE_MAPPING_REGIONS regions; NvU32 numRegions; - fabricPageSize = memdescGetPageSize(pFabricMemDesc, AT_GPU); + fabricPageSize = memdescGetPageSize64(pFabricMemDesc, AT_GPU); NV_ASSERT_OR_RETURN_VOID(dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE) == \ pFabricVAS); @@ -1063,7 +1071,7 @@ fabricvaspaceMapPhysMemdesc_IMPL DMA_UPDATE_VASPACE_FLAGS_SKIP_4K_PTE_CHECK; NvU32 fabricPageCount; NvU64 fabricAddr; - NvU32 physPageSize; + NvU64 physPageSize; NvU64 fabricPageSize; NvU64 physAddr; NvU32 i, j; @@ -1072,6 +1080,7 @@ fabricvaspaceMapPhysMemdesc_IMPL FABRIC_VASPACE_MAPPING_REGIONS regions; NvU32 numRegions; MEMORY_DESCRIPTOR *pTempMemdesc; + NvU32 aperture; NV_ASSERT_OR_RETURN(pFabricMemDesc != NULL, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(pPhysMemDesc != NULL, NV_ERR_INVALID_ARGUMENT); @@ -1081,8 +1090,8 @@ fabricvaspaceMapPhysMemdesc_IMPL NV_ASSERT_OR_RETURN(dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE) == pFabricVAS, NV_ERR_INVALID_ARGUMENT); - physPageSize = memdescGetPageSize(pPhysMemDesc, AT_GPU); - fabricPageSize = memdescGetPageSize(pFabricMemDesc, AT_GPU); + physPageSize = memdescGetPageSize64(pPhysMemDesc, AT_GPU); + fabricPageSize = memdescGetPageSize64(pFabricMemDesc, AT_GPU); status = _fabricVaspaceValidateMapAttrs(fabricOffset, memdescGetSize(pFabricMemDesc), @@ -1157,14 +1166,36 @@ fabricvaspaceMapPhysMemdesc_IMPL pTempMemdesc = pPhysMemDesc; } + if (memdescGetAddressSpace(pPhysMemDesc) == ADDR_FBMEM) + { + aperture = NV_MMU_PTE_APERTURE_VIDEO_MEMORY; + } + else if (memdescGetAddressSpace(pPhysMemDesc) == ADDR_SYSMEM) + { + if (memdescGetCpuCacheAttrib(pPhysMemDesc) == NV_MEMORY_CACHED) + { + aperture = NV_MMU_PTE_APERTURE_SYSTEM_COHERENT_MEMORY; + } + else + { + aperture = NV_MMU_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY; + } + } + else + { + NV_PRINTF(LEVEL_ERROR, "Unsupported aperture\n"); + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_ARGUMENT); + } + // Map the memory fabric object at the given physical memory offset. status = dmaUpdateVASpace_HAL(pGpu, pDma, pFabricVAS->pGVAS, pTempMemdesc, NULL, fabricAddr, fabricAddr + mapLength - 1, mapFlags, &pageArray, 0, &comprInfo, 0, NV_MMU_PTE_VALID_TRUE, - NV_MMU_PTE_APERTURE_VIDEO_MEMORY, + aperture, BUS_INVALID_PEER, NVLINK_INVALID_FABRIC_ADDR, - DMA_DEFER_TLB_INVALIDATE, NV_FALSE, fabricPageSize); + DMA_DEFER_TLB_INVALIDATE, NV_FALSE, + memdescGetPageSize64(pTempMemdesc, AT_GPU)); if (pTempMemdesc != pPhysMemDesc) memdescDestroy(pTempMemdesc); diff --git a/src/nvidia/src/kernel/mem_mgr/fla_mem.c b/src/nvidia/src/kernel/mem_mgr/fla_mem.c index c7cb8f062..dcd8d830f 100644 --- a/src/nvidia/src/kernel/mem_mgr/fla_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/fla_mem.c @@ -55,7 +55,7 @@ flamemConstruct_IMPL NvBool bContig; NvU32 hwResId = 0; NvU32 format = 0; - NvU32 pageSize = 0; + NvU64 pageSize = 0; NvU64 pageCount = 0; NvU64 newBase = 0; NvU64 flaBaseAddr = 0; @@ -227,7 +227,7 @@ flamemConstruct_IMPL if(!NV_IS_ALIGNED(flaBaseAddr, pageSize)) { NV_PRINTF(LEVEL_ERROR, - "flaBaseAsddr: 0x%llx is not aligned to page size: 0x%x\n", + "flaBaseAsddr: 0x%llx is not aligned to page size: 0x%llx\n", flaBaseAddr, pageSize); return NV_ERR_INVALID_ARGUMENT; } @@ -236,7 +236,7 @@ flamemConstruct_IMPL || (flaSize < pageSize) ) { - NV_PRINTF(LEVEL_ERROR, "flaSize: %llx is either 0 or less than page size: %x, gpu: %x\n", + NV_PRINTF(LEVEL_ERROR, "flaSize: %llx is either 0 or less than page size: %llx, gpu: %x\n", flaSize, pageSize, pGpu->gpuInstance); return NV_ERR_INVALID_ARGUMENT; } diff --git a/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c b/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c index 86d6ce4d1..b28e8e136 100644 --- a/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c +++ b/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c @@ -59,7 +59,7 @@ #define GMMU_PD1_VADDR_BIT_LO 29 -static const NvU32 pageSizes[VAS_PAGESIZE_IDX_MAX] = { +static const NvU64 pageSizes[VAS_PAGESIZE_IDX_MAX] = { RM_PAGE_SIZE, RM_PAGE_SIZE_64K, RM_PAGE_SIZE_HUGE, @@ -895,7 +895,7 @@ _gvaspaceBar1VaSpaceDestruct static NV_STATUS _gvaspaceFlaVaspaceDestruct ( - POBJGVASPACE pGVAS, + OBJGVASPACE *pGVAS, OBJGPU *pGpu ) { @@ -2021,7 +2021,7 @@ gvaspaceGetHeap_IMPL(OBJGVASPACE *pGVAS) return pGVAS->pHeap; } -NvU32 +NvU64 gvaspaceGetMapPageSize_IMPL ( OBJGVASPACE *pGVAS, @@ -2034,11 +2034,7 @@ gvaspaceGetMapPageSize_IMPL const NvU64 pageSizeMask = mmuFmtAllPageSizes(pRootFmtLvl); NvU32 i; - // - // Though page size mask is 64 bits, we will loop only over 32 bits as the callers - // do not expect a pagsize more than 2^32 bytes - // - for (i = 0; i < 32; ++i) + for (i = 0; i < 64; ++i) { if (pageSizeMask & NVBIT64(i)) { @@ -2051,7 +2047,7 @@ gvaspaceGetMapPageSize_IMPL (const MMU_WALK_MEMDESC**)&pMemDesc, &memSize); if (NULL != pMemDesc) { - return NVBIT32(i); + return NVBIT64(i); } } } @@ -4100,7 +4096,7 @@ gvaspaceCopyServerRmReservedPdesToServerRm_IMPL NvBool bFreeNeeded = NV_FALSE; NvHandle hDevice; NvHandle hVASpace; - POBJGPUGRP pGpuGrp = gpumgrGetGpuGrpFromGpu(pGpu); + OBJGPUGRP *pGpuGrp = gpumgrGetGpuGrpFromGpu(pGpu); if (NULL != pContext) { diff --git a/src/nvidia/src/kernel/mem_mgr/mem.c b/src/nvidia/src/kernel/mem_mgr/mem.c index 582befdcc..a7ed2efad 100644 --- a/src/nvidia/src/kernel/mem_mgr/mem.c +++ b/src/nvidia/src/kernel/mem_mgr/mem.c @@ -891,7 +891,7 @@ memCopyConstruct_IMPL gpuSetThreadBcState(pDstGpu, NV_TRUE); SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) - if (memdescGetPageSize(memdescGetMemDescFromGpu(pMemoryDst->pMemDesc, pGpu), AT_GPU) == 0) + if (memdescGetPageSize64(memdescGetMemDescFromGpu(pMemoryDst->pMemDesc, pGpu), AT_GPU) == 0) { status = memmgrSetMemDescPageSize_HAL(pGpu, GPU_GET_MEMORY_MANAGER(pGpu), memdescGetMemDescFromGpu(pMemoryDst->pMemDesc, pGpu), diff --git a/src/nvidia/src/kernel/mem_mgr/mem_fabric.c b/src/nvidia/src/kernel/mem_mgr/mem_fabric.c index 4b4167bee..9fc7fc779 100644 --- a/src/nvidia/src/kernel/mem_mgr/mem_fabric.c +++ b/src/nvidia/src/kernel/mem_mgr/mem_fabric.c @@ -61,10 +61,10 @@ _memoryfabricMemDescGetNumAddr ) { OBJGPU *pGpu = pMemDesc->pGpu; - NvU32 pageSize = 0; + NvU64 pageSize = 0; // Get the page size from the memory descriptor. - pageSize = memdescGetPageSize(pMemDesc, + pageSize = memdescGetPageSize64(pMemDesc, VAS_ADDRESS_TRANSLATION(pGpu->pFabricVAS)); // Get the number of addresses associated with this memory descriptor. @@ -88,9 +88,10 @@ _memoryfabricValidatePhysMem MEMORY_DESCRIPTOR **ppPhysMemDesc ) { + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pOwnerGpu); RsResourceRef *pPhysmemRef; MEMORY_DESCRIPTOR *pPhysMemDesc; - NvU32 physPageSize; + NvU64 physPageSize; NV_STATUS status; if (hPhysMem == 0) @@ -111,7 +112,7 @@ _memoryfabricValidatePhysMem pPhysMemDesc = (dynamicCast(pPhysmemRef->pResource, Memory))->pMemDesc; - if ((memdescGetAddressSpace(pPhysMemDesc) != ADDR_FBMEM) || + if (!memmgrIsApertureSupportedByFla_HAL(pOwnerGpu, pMemoryManager, memdescGetAddressSpace(pPhysMemDesc)) || (pOwnerGpu != pPhysMemDesc->pGpu)) { NV_PRINTF(LEVEL_ERROR, "Invalid physmem handle passed\n"); @@ -119,7 +120,7 @@ _memoryfabricValidatePhysMem return NV_ERR_INVALID_ARGUMENT; } - physPageSize = memdescGetPageSize(pPhysMemDesc, AT_GPU); + physPageSize = memdescGetPageSize64(pPhysMemDesc, AT_GPU); if ((physPageSize != NV_MEMORY_FABRIC_PAGE_SIZE_2M) && (physPageSize != NV_MEMORY_FABRIC_PAGE_SIZE_512M)) { @@ -260,6 +261,7 @@ _memoryFabricAttachMem pNode->node.keyStart = pAttachInfo->offset; pNode->node.keyEnd = pAttachInfo->offset; + pNode->physMapOffset = pAttachInfo->mapOffset; pNode->physMapLength = pAttachInfo->mapLength; pNode->pPhysMemDesc = pPhysMemDesc; pNode->hDupedPhysMem = hDupedPhysMem; @@ -300,7 +302,7 @@ _memoryfabricMemDescDestroyCallback RmPhysAddr *pteArray; FABRIC_MEMDESC_DATA *pMemdescData; NvU32 numAddr; - NvU32 pageSize; + NvU64 pageSize; NV_ASSERT_OR_RETURN_VOID(pGpu->pFabricVAS != NULL); @@ -309,7 +311,7 @@ _memoryfabricMemDescDestroyCallback pteArray = memdescGetPteArrayForGpu(pMemDesc, pGpu, VAS_ADDRESS_TRANSLATION(pGpu->pFabricVAS)); numAddr = _memoryfabricMemDescGetNumAddr(pMemDesc); // Get the page size from the memory descriptor. - pageSize = memdescGetPageSize(pMemDesc, VAS_ADDRESS_TRANSLATION(pGpu->pFabricVAS)); + pageSize = memdescGetPageSize64(pMemDesc, VAS_ADDRESS_TRANSLATION(pGpu->pFabricVAS)); // Remove the fabric memory allocations from the map. fabricvaspaceVaToGpaMapRemove(pFabricVAS, pteArray[0]); @@ -576,15 +578,6 @@ memoryfabricConstruct_IMPL bFlexible = !!(pAllocParams->allocFlags & NV00F8_ALLOC_FLAGS_FLEXIBLE_FLA); - // We don't support flexible mappings yet. - if (bFlexible) - { - NV_PRINTF(LEVEL_ERROR, - "Only sticky mappings are supported\n"); - - return NV_ERR_INVALID_ARGUMENT; - } - if (pAllocParams->allocFlags & NV00F8_ALLOC_FLAGS_READ_ONLY) { #if !defined(DEVELOP) && !defined(DEBUG) && !RMCFG_FEATURE_MODS_FEATURES @@ -1020,3 +1013,96 @@ memoryfabricCtrlDetachMem_IMPL return NV_OK; } + +NV_STATUS +memoryfabricCtrlGetNumAttachedMem_IMPL +( + MemoryFabric *pMemoryFabric, + NV00F8_CTRL_GET_NUM_ATTACHED_MEM_PARAMS *pParams +) +{ + Memory *pMemory = staticCast(pMemoryFabric, Memory); + MEMORY_DESCRIPTOR *pFabricMemDesc = pMemory->pMemDesc; + FABRIC_MEMDESC_DATA *pMemdescData = \ + (FABRIC_MEMDESC_DATA *)memdescGetMemData(pFabricMemDesc); + NODE *pNode = NULL; + + pParams->numMemInfos = 0; + + btreeEnumStart(pParams->offsetStart, &pNode, pMemdescData->pAttachMemInfoTree); + while ((pNode != NULL) && (pNode->keyStart <= pParams->offsetEnd)) + { + pParams->numMemInfos++; + btreeEnumNext(&pNode, pMemdescData->pAttachMemInfoTree); + } + + return NV_OK; +} + +NV_STATUS +memoryfabricCtrlGetAttachedMem_IMPL +( + MemoryFabric *pMemoryFabric, + NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS *pParams +) +{ + NV_STATUS status; + Memory *pMemory = staticCast(pMemoryFabric, Memory); + MEMORY_DESCRIPTOR *pFabricMemDesc = pMemory->pMemDesc; + FABRIC_MEMDESC_DATA *pMemdescData = \ + (FABRIC_MEMDESC_DATA *)memdescGetMemData(pFabricMemDesc); + OBJGPU *pGpu = pMemory->pGpu; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + FABRIC_VASPACE *pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); + FABRIC_ATTCH_MEM_INFO_NODE *pAttachMemInfoNode; + NODE *pNode = NULL; + NvU16 i, count = 0; + + if ((pParams->numMemInfos == 0) || + (pParams->numMemInfos > NV00F8_MAX_ATTACHED_MEM_INFOS)) + return NV_ERR_INVALID_ARGUMENT; + + btreeEnumStart(pParams->offsetStart, &pNode, pMemdescData->pAttachMemInfoTree); + while (count < pParams->numMemInfos) + { + if (pNode == NULL) + { + status = NV_ERR_INVALID_ARGUMENT; + goto cleanup; + } + + pAttachMemInfoNode = (FABRIC_ATTCH_MEM_INFO_NODE *)pNode->Data; + + status = pRmApi->DupObject(pRmApi, RES_GET_CLIENT_HANDLE(pMemory), + RES_GET_HANDLE(pMemory->pDevice), + &pParams->memInfos[count].hMemory, + pFabricVAS->hClient, + pAttachMemInfoNode->hDupedPhysMem, 0); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to dup physmem handle\n"); + goto cleanup; + } + + pParams->memInfos[count].offset = pNode->keyStart; + pParams->memInfos[count].mapOffset = pAttachMemInfoNode->physMapOffset; + pParams->memInfos[count].mapLength = pAttachMemInfoNode->physMapLength; + + btreeEnumNext(&pNode, pMemdescData->pAttachMemInfoTree); + count++; + } + + return NV_OK; + +cleanup: + for (i = 0; i < count; i++) + { + NV_ASSERT_OK(pRmApi->Free(pRmApi, RES_GET_CLIENT_HANDLE(pMemory), + pParams->memInfos[i].hMemory)); + pParams->memInfos[i].offset = 0; + pParams->memInfos[i].mapOffset = 0; + pParams->memInfos[i].mapLength = 0; + } + + return status; +} diff --git a/src/nvidia/src/kernel/mem_mgr/mem_list.c b/src/nvidia/src/kernel/mem_mgr/mem_list.c index 0188ccc4f..6321a2bb7 100644 --- a/src/nvidia/src/kernel/mem_mgr/mem_list.c +++ b/src/nvidia/src/kernel/mem_mgr/mem_list.c @@ -310,7 +310,7 @@ continue_alloc_object: pPteArray = memdescGetPteArray(pMemDesc, AT_GPU); - if (!portSafeMulU32(sizeof(NvU64), pAllocParams->pageCount, &result)) + if (!portSafeMulU32(sizeof(NvU64), pAllocParams->pageCount, &result)) { memdescDestroy(pMemDesc); return NV_ERR_INVALID_ARGUMENT; diff --git a/src/nvidia/src/kernel/mem_mgr/mem_multicast_fabric.c b/src/nvidia/src/kernel/mem_mgr/mem_multicast_fabric.c index 3cc184366..c27242bcb 100644 --- a/src/nvidia/src/kernel/mem_mgr/mem_multicast_fabric.c +++ b/src/nvidia/src/kernel/mem_mgr/mem_multicast_fabric.c @@ -110,21 +110,15 @@ _memMulticastFabricDescriptorAllocUnderLock portMemSet(pMulticastFabricDesc, 0, sizeof(MEM_MULTICAST_FABRIC_DESCRIPTOR)); - portAtomicExSetU64(&pMulticastFabricDesc->refCount, 1); - listInit(&pMulticastFabricDesc->waitingClientsList, portMemAllocatorGetGlobalNonPaged()); - listInit(&pMulticastFabricDesc->attachMemInfoList, + listInit(&pMulticastFabricDesc->gpuInfoList, portMemAllocatorGetGlobalNonPaged()); - listInit(&pMulticastFabricDesc->gpuOsInfoList, - portMemAllocatorGetGlobalNonPaged()); - - portAtomicSetU32(&pMulticastFabricDesc->mcTeamStatus, NV_ERR_NOT_READY); - - portAtomicSetU32(&pMulticastFabricDesc->attachedGpusMask, 0); - + pMulticastFabricDesc->refCount = 1; + pMulticastFabricDesc->mcTeamStatus = NV_ERR_NOT_READY; + pMulticastFabricDesc->attachedGpusMask = 0; pMulticastFabricDesc->alignment = pAllocParams->alignment; pMulticastFabricDesc->allocSize = pAllocParams->allocSize; pMulticastFabricDesc->pageSize = pAllocParams->pageSize; @@ -225,166 +219,76 @@ _memMulticastFabricDescriptorDequeueWaitUnderLock } NV_STATUS -_memMulticastFabricGpuOsInfoAddUnderLock +_memMulticastFabricGpuInfoAddUnderLock ( MemoryMulticastFabric *pMemoryMulticastFabric, RS_RES_CONTROL_PARAMS_INTERNAL *pParams ) { - NV00FD_CTRL_ATTACH_MEM_PARAMS *pAttachParams = pParams->pParams; + NV00FD_CTRL_ATTACH_GPU_PARAMS *pAttachParams = pParams->pParams; Subdevice *pSubdevice = NULL; - MEM_MULTICAST_FABRIC_GPU_OS_INFO *pNode; + MEM_MULTICAST_FABRIC_GPU_INFO *pNode; MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = \ pMemoryMulticastFabric->pMulticastFabricDesc; + OBJGPU *pGpu; + MEM_MULTICAST_FABRIC_GPU_INFO *pNodeItr; NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, subdeviceGetByHandle(RES_GET_CLIENT(pMemoryMulticastFabric), pAttachParams->hSubdevice, &pSubdevice)); - if(!osMatchGpuOsInfo(GPU_RES_GET_GPU(pSubdevice), - pParams->secInfo.gpuOsInfo)) - { + pGpu = GPU_RES_GET_GPU(pSubdevice); + + if(!osMatchGpuOsInfo(pGpu, pParams->secInfo.gpuOsInfo)) return NV_ERR_INVALID_DEVICE; - } - pNode = listAppendNew(&pMulticastFabricDesc->gpuOsInfoList); - if (pNode == NULL) + for (pNodeItr = listHead(&pMulticastFabricDesc->gpuInfoList); + pNodeItr != NULL; + pNodeItr = listNext(&pMulticastFabricDesc->gpuInfoList, pNodeItr)) { - return NV_ERR_NO_MEMORY; + if (pNodeItr->pGpu == pGpu) + { + NV_PRINTF(LEVEL_ERROR, "GPU %x has already attached\n", + pGpu->gpuInstance); + return NV_ERR_IN_USE; + } } - pNode->gpuOsInfo = pParams->secInfo.gpuOsInfo; + pNode = listAppendNew(&pMulticastFabricDesc->gpuInfoList); + if (pNode == NULL) + return NV_ERR_NO_MEMORY; + + pNode->pGpuOsInfo = pParams->secInfo.gpuOsInfo; + pNode->pGpu = GPU_RES_GET_GPU(pSubdevice); + pNode->pAttachMemInfoTree = NULL; + pNode->bMcflaAlloc = NV_FALSE; return NV_OK; } static void -_memMulticastFabricGpuOsInfoRemoveUnderLock +_memMulticastFabricGpuInfoRemoveUnderLock ( MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc ) { - MEM_MULTICAST_FABRIC_GPU_OS_INFO *pNode = NULL; + MEM_MULTICAST_FABRIC_GPU_INFO *pNode = NULL; THREAD_STATE_NODE *pThreadNode = NULL; THREAD_STATE_FREE_CALLBACK freeCallback; NV_ASSERT_OK(threadStateGetCurrent(&pThreadNode, NULL)); - while ((pNode = listHead(&pMulticastFabricDesc->gpuOsInfoList)) != NULL) + while ((pNode = listHead(&pMulticastFabricDesc->gpuInfoList)) != NULL) { freeCallback.pCb = osReleaseGpuOsInfo; - freeCallback.pCbData = (void *)pNode->gpuOsInfo; + freeCallback.pCbData = (void *)pNode->pGpuOsInfo; NV_ASSERT_OK(threadStateEnqueueCallbackOnFree(pThreadNode, &freeCallback)); - listRemove(&pMulticastFabricDesc->gpuOsInfoList, pNode); - } -} - -// -// The caller must have acquired the pMulticastFabricOpsMutex lock. -// GPU lock is acquired as needed. -// -static void -_memMulticastFabricRemoveFabricMapping -( - OBJGPU *pGpu, - MEMORY_DESCRIPTOR *pMemDesc -) -{ - FABRIC_VASPACE *pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); - NvU64 mcAddressBase = pMemDesc->_pteArray[0]; - - NV_ASSERT_OK(rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, - RM_LOCK_MODULES_MEM_FLA)); - - fabricvaspaceBatchFree(pFabricVAS, &mcAddressBase, 1, 1); - - rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); -} - -static void -_memMulticastFabricBatchRemoveFabricMappingUnderLock -( - MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, - MEMORY_DESCRIPTOR *pMemDesc, - MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pEndNode -) -{ - MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pNode = NULL; - - for (pNode = listHead(&pMulticastFabricDesc->attachMemInfoList); - pNode != NULL; - pNode = listNext(&pMulticastFabricDesc->attachMemInfoList, pNode)) - { - if (pNode == pEndNode) - return; - - _memMulticastFabricRemoveFabricMapping(pNode->pGpu, pMemDesc); - } -} - -static void -_memMulticastFabricAttachMemInfoRemoveUnderLock -( - MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, - MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pNode -) -{ - pMulticastFabricDesc->numAttachedGpus--; - - portAtomicAndU32(&pMulticastFabricDesc->attachedGpusMask, - ~(NVBIT32(pNode->pGpu->gpuInstance))); - - listRemove(&pMulticastFabricDesc->attachMemInfoList, pNode); -} - -static void -_memMulticastFabricDetachMemInfoUnderLock -( - MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, - MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pNode -) -{ - RM_API *pRmApi; - OBJGPU *pGpu = pNode->pGpu; - FABRIC_VASPACE *pFabricVAS = \ - dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); - NvHandle hDupedPhysMem; - - pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - - hDupedPhysMem = pNode->hDupedPhysMem; - - _memMulticastFabricAttachMemInfoRemoveUnderLock(pMulticastFabricDesc, pNode); - - NV_ASSERT_OK(pRmApi->Free(pRmApi, pFabricVAS->hClient, hDupedPhysMem)); -} - -// -// The caller must have acquired the pMulticastFabricOpsMutex lock. -// GPU lock is acquired as needed. -// -static void -_memMulticastFabricBatchDetachMemInfo -( - MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc -) -{ - MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pNode = NULL; - - NV_ASSERT_OK(rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, - RM_LOCK_MODULES_MEM_FLA)); - - // - // _memMulticastFabricDetachMemInfoUnderLock internally trims down the - // attachMemInfoList where pNode is freed up - // - while ((pNode = listHead(&pMulticastFabricDesc->attachMemInfoList)) != NULL) - { - _memMulticastFabricDetachMemInfoUnderLock(pMulticastFabricDesc, pNode); + listRemove(&pMulticastFabricDesc->gpuInfoList, pNode); } - rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + pMulticastFabricDesc->attachedGpusMask = 0; + pMulticastFabricDesc->numAttachedGpus = 0; } NV_STATUS @@ -398,7 +302,7 @@ _memMulticastFabricSendInbandTeamSetupRequestV1UnderLock NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS *sendDataParams; nvlink_inband_mc_team_setup_req_msg_t *pMcTeamSetupReqMsg = NULL; nvlink_inband_mc_team_setup_req_t *pMcTeamSetupReq = NULL; - MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pNode; + MEM_MULTICAST_FABRIC_GPU_INFO *pNode; NvU64 requestId; NvU32 idx = 0; NvU32 payloadSize; @@ -406,7 +310,8 @@ _memMulticastFabricSendInbandTeamSetupRequestV1UnderLock NV_STATUS status = NV_OK; sendDataParams = \ - (NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS *)portMemAllocNonPaged(sizeof(NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS)); + (NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS *) + portMemAllocNonPaged(sizeof(NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS)); if (sendDataParams == NULL) return NV_ERR_NO_MEMORY; @@ -429,9 +334,9 @@ _memMulticastFabricSendInbandTeamSetupRequestV1UnderLock pMcTeamSetupReq->mcAllocSize = pMulticastFabricDesc->allocSize; pMcTeamSetupReq->numGpuHandles = pMulticastFabricDesc->numMaxGpus; - for (pNode = listHead(&pMulticastFabricDesc->attachMemInfoList); + for (pNode = listHead(&pMulticastFabricDesc->gpuInfoList); pNode != NULL; - pNode = listNext(&pMulticastFabricDesc->attachMemInfoList, pNode)) + pNode = listNext(&pMulticastFabricDesc->gpuInfoList, pNode)) pMcTeamSetupReq->gpuHandles[idx++] = pNode->gpuProbeHandle; NV_ASSERT(idx == pMcTeamSetupReq->numGpuHandles); @@ -519,12 +424,8 @@ done: return status; } -// -// The caller must have acquired the pMulticastFabricOpsMutex lock. -// GPU lock is acquired as needed. -// NV_STATUS -_memMulticastFabricSendInbandTeamSetupRequest +_memMulticastFabricSendInbandTeamSetupRequestUnderlock ( OBJGPU *pGpu, MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc @@ -533,31 +434,19 @@ _memMulticastFabricSendInbandTeamSetupRequest NvU64 fmCaps; NV_STATUS status = NV_OK; - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, - RM_LOCK_MODULES_MEM_FLA)); - status = gpuFabricProbeGetfmCaps(pGpu->pGpuFabricProbeInfo, &fmCaps); if (status != NV_OK) - goto done; + return status; if (!(fmCaps & NVLINK_INBAND_FM_CAPS_MC_TEAM_SETUP_V1)) - { - status = NV_ERR_NOT_SUPPORTED; - goto done; - } + return NV_ERR_NOT_SUPPORTED; - status = _memMulticastFabricSendInbandTeamSetupRequestV1UnderLock(pGpu, - pMulticastFabricDesc); - -done: - rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); - - return status; + return _memMulticastFabricSendInbandTeamSetupRequestV1UnderLock(pGpu, + pMulticastFabricDesc); } NV_STATUS -_memMulticastFabricSendInbandTeamReleaseRequest +_memMulticastFabricSendInbandTeamReleaseRequestUnderLock ( OBJGPU *pGpu, NvU64 mcTeamHandle @@ -566,56 +455,40 @@ _memMulticastFabricSendInbandTeamReleaseRequest NvU64 fmCaps; NV_STATUS status = NV_OK; - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, - RM_LOCK_MODULES_MEM_FLA)); - status = gpuFabricProbeGetfmCaps(pGpu->pGpuFabricProbeInfo, &fmCaps); if (status != NV_OK) - goto done; + return status; if (!(fmCaps & NVLINK_INBAND_FM_CAPS_MC_TEAM_RELEASE_V1)) - { - status = NV_ERR_NOT_SUPPORTED; - goto done; - } + return NV_ERR_NOT_SUPPORTED; - status = _memMulticastFabricSendInbandTeamReleaseRequestV1UnderLock(pGpu, - mcTeamHandle); - -done: - rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); - - return status; + return _memMulticastFabricSendInbandTeamReleaseRequestV1UnderLock(pGpu, + mcTeamHandle); } NV_STATUS _memMulticastFabricSendInbandRequestUnderLock ( + OBJGPU *pGpu, MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, MEM_MULTICAST_FABRIC_REQUEST_TYPE requestType ) { NV_STATUS status = NV_OK; - OBJGPU *pGpu; - // - // TODO: Implement the randomization of pGpu to be used for the inband - // communication. Currently we pick the first pGpu in the attachMemInfoList - // to send the inband request. - // - - pGpu = listHead(&pMulticastFabricDesc->attachMemInfoList)->pGpu; + // If pGpu is NULL, pick the first one attached to the object. + if (pGpu == NULL) + pGpu = listHead(&pMulticastFabricDesc->gpuInfoList)->pGpu; switch (requestType) { case MEM_MULTICAST_FABRIC_TEAM_SETUP_REQUEST: - status = _memMulticastFabricSendInbandTeamSetupRequest(pGpu, - pMulticastFabricDesc); + status = _memMulticastFabricSendInbandTeamSetupRequestUnderlock(pGpu, + pMulticastFabricDesc); break; case MEM_MULTICAST_FABRIC_TEAM_RELEASE_REQUEST: - status = _memMulticastFabricSendInbandTeamReleaseRequest(pGpu, - pMulticastFabricDesc->mcTeamHandle); + status = _memMulticastFabricSendInbandTeamReleaseRequestUnderLock(pGpu, + pMulticastFabricDesc->mcTeamHandle); break; default: status = NV_ERR_NOT_SUPPORTED; @@ -625,6 +498,77 @@ _memMulticastFabricSendInbandRequestUnderLock return status; } +static void +_memorymulticastfabricDetachMem +( + FABRIC_VASPACE *pFabricVAS, + MEMORY_DESCRIPTOR *pFabricMemDesc, + NODE *pMemNode +) +{ + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + MEMORY_DESCRIPTOR *pPhysMemDesc; + MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO_NODE *pAttachMemInfoNode; + + pAttachMemInfoNode = \ + (MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO_NODE *)pMemNode->Data; + pPhysMemDesc = pAttachMemInfoNode->pPhysMemDesc; + + fabricvaspaceUnmapPhysMemdesc(pFabricVAS, pFabricMemDesc, + pMemNode->keyStart, + pPhysMemDesc, + pAttachMemInfoNode->physMapLength); + + NV_ASSERT_OK(pRmApi->Free(pRmApi, pFabricVAS->hClient, + pAttachMemInfoNode->hDupedPhysMem)); +} + +static void +_memorymulticastfabricBatchDetachMem +( + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc +) +{ + MEMORY_DESCRIPTOR *pFabricMemDesc; + MEM_MULTICAST_FABRIC_GPU_INFO *pGpuNode; + NODE *pMemNode; + FABRIC_VASPACE *pFabricVAS; + + pFabricMemDesc = pMulticastFabricDesc->pMemDesc; + NV_ASSERT_OR_RETURN_VOID(pFabricMemDesc != NULL); + + for (pGpuNode = listHead(&pMulticastFabricDesc->gpuInfoList); + pGpuNode != NULL; + pGpuNode = listNext(&pMulticastFabricDesc->gpuInfoList, pGpuNode)) + { + pFabricVAS = dynamicCast(pGpuNode->pGpu->pFabricVAS, FABRIC_VASPACE); + if (pFabricVAS == NULL) + { + NV_ASSERT(0); + continue; + } + + btreeEnumStart(0, &pMemNode, pGpuNode->pAttachMemInfoTree); + while (pMemNode != NULL) + { + _memorymulticastfabricDetachMem(pFabricVAS, pFabricMemDesc, pMemNode); + + btreeUnlink(pMemNode, &pGpuNode->pAttachMemInfoTree); + portMemFree(pMemNode->Data); + + btreeEnumStart(0, &pMemNode, pGpuNode->pAttachMemInfoTree); + } + + // Everything is detached during object cleanup, free MCFLA now. + if (pGpuNode->bMcflaAlloc) + { + fabricvaspaceBatchFree(pFabricVAS, &pFabricMemDesc->_pteArray[0], + 1, 1); + pGpuNode->bMcflaAlloc = NV_FALSE; + } + } +} + static void _memMulticastFabricDescriptorFreeUnderLock ( @@ -634,16 +578,17 @@ _memMulticastFabricDescriptorFreeUnderLock if (pMulticastFabricDesc == NULL) return; - if (portAtomicExDecrementU64(&pMulticastFabricDesc->refCount) == 0) + pMulticastFabricDesc->refCount--; + + if (pMulticastFabricDesc->refCount == 0) { if (pMulticastFabricDesc->pMemDesc != NULL) { NV_ASSERT(pMulticastFabricDesc->bMemdescInstalled); - _memMulticastFabricBatchRemoveFabricMappingUnderLock(pMulticastFabricDesc, - pMulticastFabricDesc->pMemDesc, - NULL); - _memMulticastFabricSendInbandRequestUnderLock(pMulticastFabricDesc, + _memorymulticastfabricBatchDetachMem(pMulticastFabricDesc); + + _memMulticastFabricSendInbandRequestUnderLock(NULL, pMulticastFabricDesc, MEM_MULTICAST_FABRIC_TEAM_RELEASE_REQUEST); } @@ -674,17 +619,13 @@ _memMulticastFabricDescriptorFreeUnderLock } } - _memMulticastFabricGpuOsInfoRemoveUnderLock(pMulticastFabricDesc); + _memMulticastFabricGpuInfoRemoveUnderLock(pMulticastFabricDesc); - NV_ASSERT(listCount(&pMulticastFabricDesc->gpuOsInfoList) == 0); - listDestroy(&pMulticastFabricDesc->gpuOsInfoList); - - _memMulticastFabricBatchDetachMemInfo(pMulticastFabricDesc); + NV_ASSERT(listCount(&pMulticastFabricDesc->gpuInfoList) == 0); + listDestroy(&pMulticastFabricDesc->gpuInfoList); NV_ASSERT(pMulticastFabricDesc->numAttachedGpus == 0); - NV_ASSERT(portAtomicOrU32(&pMulticastFabricDesc->attachedGpusMask, 0) == 0); - NV_ASSERT(listCount(&pMulticastFabricDesc->attachMemInfoList) == 0); - listDestroy(&pMulticastFabricDesc->attachMemInfoList); + NV_ASSERT(pMulticastFabricDesc->attachedGpusMask == 0); NV_ASSERT(listCount(&pMulticastFabricDesc->waitingClientsList) == 0); listDestroy(&pMulticastFabricDesc->waitingClientsList); @@ -731,162 +672,6 @@ fail: return status; } -NV_STATUS -_memMulticastFabricAttachMemInfoAddUnderLock -( - MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, - OBJGPU *pGpu, - NV00FD_CTRL_ATTACH_MEM_PARAMS *pParams, - MEMORY_DESCRIPTOR *pPhysMemDesc, - NvHandle hDupedPhysMem, - NvU64 gpuProbeHandle, - MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO **pAttachMemNode -) -{ - MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pNode; - MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pNodeItr; - - for (pNodeItr = listHead(&pMulticastFabricDesc->attachMemInfoList); - pNodeItr != NULL; - pNodeItr = listNext(&pMulticastFabricDesc->attachMemInfoList, pNodeItr)) - { - if (pNodeItr->pGpu == pGpu) - { - NV_PRINTF(LEVEL_ERROR, "GPU %x has already attached to this multicast object\n", - pGpu->gpuInstance); - return NV_ERR_IN_USE; - } - } - - pNode = listAppendNew(&pMulticastFabricDesc->attachMemInfoList); - if (pNode == NULL) - return NV_ERR_NO_MEMORY; - - pNode->offset = pParams->offset; - pNode->mapOffset = pParams->mapOffset; - pNode->mapLength = pParams->mapLength; - pNode->flags = pParams->flags; - pNode->pGpu = pGpu; - pNode->pPhysMemDesc = pPhysMemDesc; - pNode->hDupedPhysMem = hDupedPhysMem; - pNode->gpuProbeHandle = gpuProbeHandle; - - portAtomicOrU32(&pMulticastFabricDesc->attachedGpusMask, - NVBIT32(pGpu->gpuInstance)); - - pMulticastFabricDesc->numAttachedGpus++; - - *pAttachMemNode = pNode; - - return NV_OK; -} - -// -// The caller must have acquired the pMulticastFabricOpsMutex lock. -// GPU lock is acquired as needed. -// -NV_STATUS -_memMulticastFabricSetupFabricMapping -( - OBJGPU *pGpu, - MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, - MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pAttachMemInfo, - MEMORY_DESCRIPTOR *pMemDesc -) -{ - FABRIC_VASPACE *pFabricVAS = NULL; - VAS_ALLOC_FLAGS flags = {0}; - NV_STATUS status = NV_OK; - NvU64 physMemPageSize; - NvU64 mcAddressBase = pMemDesc->_pteArray[0]; - - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, - RM_LOCK_MODULES_MEM_FLA)); - - pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); - - physMemPageSize = memdescGetPageSize(pAttachMemInfo->pPhysMemDesc, AT_GPU); - - status = fabricvaspaceAllocMulticast(pFabricVAS, physMemPageSize, - pMulticastFabricDesc->alignment, - flags, - mcAddressBase, - pMulticastFabricDesc->allocSize); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "Fabric VA space alloc failed! for GPU %x\n", - pGpu->gpuInstance); - goto releaseGpuLock; - } - - // - // For now MCFLA code assumes zero fabric offset. When a non-zero fabric - // offset supported, revisit map/unmap paths. - // - status = fabricvaspaceMapPhysMemdesc(pFabricVAS, - pMemDesc, - 0, - pAttachMemInfo->pPhysMemDesc, - pAttachMemInfo->mapOffset, - pAttachMemInfo->mapLength, - 0); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "Failed to map MC FLA at the given physical offset for GPU %x\n", - pGpu->gpuInstance); - goto freeFabricVa; - } - - // - // TODO: Handle the case to map remaining MC FLA range - // to dummy pages when physMemSize < mcAllocSize - // - - rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); - - return NV_OK; - -freeFabricVa: - fabricvaspaceBatchFree(pFabricVAS, &mcAddressBase, 1, 1); - -releaseGpuLock: - rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); - - return status; -} - -NV_STATUS -_memMulticastFabricBatchSetupFabricMappingUnderLock -( - MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, - MEMORY_DESCRIPTOR *pMemDesc -) -{ - MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pNode = NULL; - NV_STATUS status = NV_OK; - - for (pNode = listHead(&pMulticastFabricDesc->attachMemInfoList); - pNode != NULL; - pNode = listNext(&pMulticastFabricDesc->attachMemInfoList, pNode)) - { - status = _memMulticastFabricSetupFabricMapping(pNode->pGpu, pMulticastFabricDesc, - pNode, pMemDesc); - if (status != NV_OK) - goto batchRemoveMapping; - } - - return NV_OK; - -batchRemoveMapping: - _memMulticastFabricBatchRemoveFabricMappingUnderLock(pMulticastFabricDesc, - pMemDesc, pNode); - - return status; -} - NV_STATUS _memMulticastFabricCreateMemDescUnderLock ( @@ -937,23 +722,15 @@ _memMulticastFabricInstallMemDescUnderLock pMulticastFabricDesc->pMemDesc = pMemDesc; pMulticastFabricDesc->bMemdescInstalled = NV_TRUE; pMulticastFabricDesc->mcTeamHandle = mcTeamHandle; - - portAtomicMemoryFenceStore(); - - portAtomicSetU32(&pMulticastFabricDesc->mcTeamStatus, status); - - portAtomicMemoryFenceStore(); + pMulticastFabricDesc->mcTeamStatus = status; _memMulticastFabricDescriptorFlushClientsUnderLock(pMulticastFabricDesc); } -// -// TODO: This function will be invoked as part of the FM inband -// response handling once inband integration is complete. -// NV_STATUS -_memMulticastFabricAttachMemPostProcessorUnderLock +_memMulticastFabricAttachGpuPostProcessorUnderLock ( + OBJGPU *pGpu, MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, NV_STATUS mcTeamStatus, NvU64 mcTeamHandle, @@ -991,28 +768,16 @@ _memMulticastFabricAttachMemPostProcessorUnderLock status = _memMulticastFabricCreateMemDescUnderLock(pMulticastFabricDesc, mcAddressBase, &pMemDesc); - if (status != NV_OK) - goto installMemDesc; - - status = _memMulticastFabricBatchSetupFabricMappingUnderLock(pMulticastFabricDesc, - pMemDesc); - if (status != NV_OK) - goto cleanupMemdesc; - - goto installMemDesc; - -cleanupMemdesc: - memdescDestroy(pMemDesc); - pMemDesc = NULL; installMemDesc: _memMulticastFabricInstallMemDescUnderLock(pMulticastFabricDesc, pMemDesc, mcTeamHandle, status); + if ((status != NV_OK) && (mcTeamStatus == NV_OK)) - _memMulticastFabricSendInbandRequestUnderLock(pMulticastFabricDesc, - MEM_MULTICAST_FABRIC_TEAM_RELEASE_REQUEST); + _memMulticastFabricSendInbandRequestUnderLock(pGpu, pMulticastFabricDesc, + MEM_MULTICAST_FABRIC_TEAM_RELEASE_REQUEST); return status; } @@ -1037,7 +802,7 @@ _memorymulticastfabricDestructUnderLock void memorymulticastfabricTeamSetupResponseCallback ( - OBJGPU *pGpu, + NvU32 gpuInstance, NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pInbandRcvParams ) { @@ -1051,8 +816,17 @@ void memorymulticastfabricTeamSetupResponseCallback NvU64 mcAddressBase = 0; NvU64 mcAddressSize = 0; NvU8 *pRsvd = NULL; + NvU32 unused; + OBJGPU *pGpu; NV_ASSERT(pInbandRcvParams != NULL); + NV_ASSERT(rmGpuGroupLockIsOwner(gpuInstance, GPU_LOCK_GRP_SUBDEVICE, &unused)); + + if ((pGpu = gpumgrGetGpu(gpuInstance)) == NULL) + { + NV_ASSERT_FAILED("Invalid GPU instance"); + return; + } pMcTeamSetupRspMsg = \ (nvlink_inband_mc_team_setup_rsp_msg_t *)&pInbandRcvParams->data[0]; @@ -1090,7 +864,8 @@ void memorymulticastfabricTeamSetupResponseCallback fabricMulticastSetupCacheDeleteUnderLock_IMPL(pFabric, requestId); - (void)_memMulticastFabricAttachMemPostProcessorUnderLock(pMulticastFabricDesc, + (void)_memMulticastFabricAttachGpuPostProcessorUnderLock(pGpu, + pMulticastFabricDesc, mcTeamStatus, mcTeamHandle, mcAddressBase, @@ -1101,8 +876,8 @@ void memorymulticastfabricTeamSetupResponseCallback OS_WAIT_QUEUE *pWq; if (mcTeamStatus == NV_OK) - (void)_memMulticastFabricSendInbandTeamReleaseRequest(pGpu, - mcTeamHandle); + (void)_memMulticastFabricSendInbandTeamReleaseRequestUnderLock(pGpu, + mcTeamHandle); // // Check if there is any thread waiting for team release and @@ -1138,10 +913,6 @@ memorymulticastfabricConstruct_IMPL Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); NV00FD_ALLOCATION_PARAMETERS *pAllocParams = pParams->pAllocParams; NV_STATUS status = NV_OK; - OBJSYS *pSys = SYS_GET_INSTANCE(); - - if (!pSys->bMulticastFlaEnabled) - return NV_ERR_NOT_SUPPORTED; if (RS_IS_COPY_CTOR(pParams)) { @@ -1164,33 +935,33 @@ memorymulticastfabricConstruct_IMPL } NV_STATUS -memorymulticastfabricCtrlAttachMem_IMPL +memorymulticastfabricCtrlAttachGpu_IMPL ( MemoryMulticastFabric *pMemoryMulticastFabric, - NV00FD_CTRL_ATTACH_MEM_PARAMS *pParams + NV00FD_CTRL_ATTACH_GPU_PARAMS *pParams ) { MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = \ - pMemoryMulticastFabric->pMulticastFabricDesc; + pMemoryMulticastFabric->pMulticastFabricDesc; NV_STATUS status = NV_OK; - NvHandle hClient = RES_GET_CLIENT_HANDLE(pMemoryMulticastFabric); - RsResourceRef *pPhysMemRef = NULL; - MEMORY_DESCRIPTOR *pPhysMemDesc = NULL; - Subdevice *pSubdevice = NULL; - OBJGPU *pGpu = NULL; - FABRIC_VASPACE *pFabricVAS = NULL; - RM_API *pRmApi; - NvHandle hDupedPhysMem = 0; - NvU64 physMemPageSize; - NvU64 physMemSize; - MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pAttachMemNode = NULL; - NvU64 gpuProbeHandle = 0; + Subdevice *pSubdevice; + OBJGPU *pGpu; + FABRIC_VASPACE *pFabricVAS; + NvU64 gpuProbeHandle; + MEM_MULTICAST_FABRIC_GPU_INFO *pNode = \ + listTail(&pMulticastFabricDesc->gpuInfoList); + + if (pParams->flags != 0) + { + NV_PRINTF(LEVEL_ERROR, "flags passed for attach mem must be zero\n"); + status = NV_ERR_INVALID_ARGUMENT; + goto fail; + } // Check if the Multicast FLA object has any additional slots for GPUs if (pMulticastFabricDesc->numAttachedGpus == pMulticastFabricDesc->numMaxGpus) { - NV_PRINTF(LEVEL_ERROR, - "Max no. of GPUs for this multicast object have already attached!\n"); + NV_PRINTF(LEVEL_ERROR, "Max no. of GPUs have already attached!\n"); return NV_ERR_INVALID_OPERATION; } @@ -1200,12 +971,6 @@ memorymulticastfabricCtrlAttachMem_IMPL pGpu = GPU_RES_GET_GPU(pSubdevice); - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, - RM_LOCK_MODULES_MEM_FLA)); - - pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - if (RMCFG_FEATURE_PLATFORM_WINDOWS || IS_VIRTUAL(pGpu)) { @@ -1215,7 +980,8 @@ memorymulticastfabricCtrlAttachMem_IMPL goto fail; } - status = gpuFabricProbeGetGpuFabricHandle(pGpu->pGpuFabricProbeInfo, &gpuProbeHandle); + status = gpuFabricProbeGetGpuFabricHandle(pGpu->pGpuFabricProbeInfo, + &gpuProbeHandle); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -1223,14 +989,6 @@ memorymulticastfabricCtrlAttachMem_IMPL goto fail; } - status = serverutilGetResourceRef(hClient, pParams->hMemory, &pPhysMemRef); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "Failed to get resource in resserv for physmem handle\n"); - goto fail; - } - pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); if (pFabricVAS == NULL) { @@ -1241,112 +999,272 @@ memorymulticastfabricCtrlAttachMem_IMPL goto fail; } - pPhysMemDesc = (dynamicCast(pPhysMemRef->pResource, Memory))->pMemDesc; + pNode->gpuProbeHandle = gpuProbeHandle; - if ((memdescGetAddressSpace(pPhysMemDesc) != ADDR_FBMEM) || - (pGpu != pPhysMemDesc->pGpu)) + if ((pMulticastFabricDesc->numAttachedGpus + 1) == pMulticastFabricDesc->numMaxGpus) { - NV_PRINTF(LEVEL_ERROR, "Invalid physical physmem handle passed\n"); - status = NV_ERR_INVALID_ARGUMENT; - goto fail; - } - - physMemPageSize = memdescGetPageSize(pPhysMemDesc, AT_GPU); - - physMemSize = memdescGetSize(pPhysMemDesc); - - if (physMemPageSize != RM_PAGE_SIZE_HUGE) - { - NV_PRINTF(LEVEL_ERROR, "Physical physmem page size should be 2MB\n"); - status = NV_ERR_INVALID_ARGUMENT; - goto fail; - } - - if ((!NV_IS_ALIGNED64(pParams->mapOffset, physMemPageSize)) || - (!NV_IS_ALIGNED64(pParams->mapLength, physMemPageSize)) || - (pParams->mapOffset >= physMemSize) || - (pParams->mapLength > (physMemSize - pParams->mapOffset))) - { - NV_PRINTF(LEVEL_ERROR, - "Invalid mapOffset passed for the physical physmem handle\n"); - status = NV_ERR_INVALID_OFFSET; - goto fail; - } - - if (pParams->offset != 0) - { - NV_PRINTF(LEVEL_ERROR, "offset passed for attach mem must be zero\n"); - status = NV_ERR_INVALID_OFFSET; - goto fail; - } - - if (pParams->mapLength == 0) - { - NV_PRINTF(LEVEL_ERROR, "Invalid mapLength passed\n"); - status = NV_ERR_INVALID_ARGUMENT; - goto fail; - } - - if ((pParams->offset >= pMulticastFabricDesc->allocSize) || - (pParams->mapLength > (pMulticastFabricDesc->allocSize - pParams->offset))) - { - NV_PRINTF(LEVEL_ERROR, "Invalid multicast offset passed\n"); - status = NV_ERR_INVALID_OFFSET; - goto fail; - } - - if (pParams->flags != 0) - { - NV_PRINTF(LEVEL_ERROR, "flags passed for attach mem must be zero\n"); - status = NV_ERR_INVALID_ARGUMENT; - goto fail; - } - - status = pRmApi->DupObject(pRmApi, pFabricVAS->hClient, pFabricVAS->hDevice, - &hDupedPhysMem, hClient, pParams->hMemory, 0); - - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "Failed to dup physical physical memory handle\n"); - goto fail; - } - - status = _memMulticastFabricAttachMemInfoAddUnderLock(pMulticastFabricDesc, - pGpu, pParams, pPhysMemDesc, hDupedPhysMem, gpuProbeHandle, - &pAttachMemNode); - - rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); - - if (status != NV_OK) - goto addInfoFail; - - if (pMulticastFabricDesc->numAttachedGpus == pMulticastFabricDesc->numMaxGpus) - { - status = _memMulticastFabricSendInbandRequestUnderLock(pMulticastFabricDesc, - MEM_MULTICAST_FABRIC_TEAM_SETUP_REQUEST); + status = _memMulticastFabricSendInbandRequestUnderLock(NULL, pMulticastFabricDesc, + MEM_MULTICAST_FABRIC_TEAM_SETUP_REQUEST); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Inband request submission to FM for Multicast Team Setup failed!\n"); - goto inbandFail; + goto fail; } } + pMulticastFabricDesc->numAttachedGpus++; + pMulticastFabricDesc->attachedGpusMask |= NVBIT32(pGpu->gpuInstance); + + return NV_OK; + +fail: + // Remove GPU OS info added in the prologue. + listRemove(&pMulticastFabricDesc->gpuInfoList, pNode); + + return status; +} + +static MEM_MULTICAST_FABRIC_GPU_INFO* +_memorymulticastfabricGetAttchedGpuInfo +( + MemoryMulticastFabric *pMemoryMulticastFabric, + NvHandle hSubdevice +) +{ + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = \ + pMemoryMulticastFabric->pMulticastFabricDesc; + MEM_MULTICAST_FABRIC_GPU_INFO *pNodeItr; + Subdevice *pSubdevice = NULL; + NV_STATUS status; + + status = subdeviceGetByHandle(RES_GET_CLIENT(pMemoryMulticastFabric), + hSubdevice, &pSubdevice); + if (status != NV_OK) + return NULL; + + for (pNodeItr = listHead(&pMulticastFabricDesc->gpuInfoList); + pNodeItr != NULL; + pNodeItr = listNext(&pMulticastFabricDesc->gpuInfoList, pNodeItr)) + { + if (pNodeItr->pGpu == GPU_RES_GET_GPU(pSubdevice)) + return pNodeItr; + } + + return NULL; +} + +NV_STATUS +memorymulticastfabricCtrlDetachMem_IMPL +( + MemoryMulticastFabric *pMemoryMulticastFabric, + NV00FD_CTRL_DETACH_MEM_PARAMS *pParams +) +{ + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = \ + pMemoryMulticastFabric->pMulticastFabricDesc; + MEM_MULTICAST_FABRIC_GPU_INFO *pGpuInfo; + NODE *pNode; + MEMORY_DESCRIPTOR *pFabricMemDesc; + FABRIC_VASPACE *pFabricVAS; + NV_STATUS status; + + if (pParams->flags != 0) + return NV_ERR_INVALID_ARGUMENT; + + pGpuInfo = _memorymulticastfabricGetAttchedGpuInfo(pMemoryMulticastFabric, + pParams->hSubdevice); + if (pGpuInfo == NULL) + return NV_ERR_INVALID_DEVICE; + + status = btreeSearch(pParams->offset, &pNode, pGpuInfo->pAttachMemInfoTree); + if (status != NV_OK) + return status; + + pFabricMemDesc = pMulticastFabricDesc->pMemDesc; + NV_ASSERT_OR_RETURN(pFabricMemDesc != NULL, NV_ERR_INVALID_STATE); + + pFabricVAS = dynamicCast(pGpuInfo->pGpu->pFabricVAS, FABRIC_VASPACE); + NV_ASSERT_OR_RETURN(pFabricVAS != NULL, NV_ERR_INVALID_STATE); + + _memorymulticastfabricDetachMem(pFabricVAS, pFabricMemDesc, pNode); + + btreeUnlink(pNode, &pGpuInfo->pAttachMemInfoTree); + portMemFree(pNode->Data); + + return NV_OK; +} + +static NV_STATUS +_memorymulticastfabricValidatePhysMem +( + MemoryMulticastFabric *pMemoryMulticastFabric, + NvHandle hPhysMem, + OBJGPU *pAttachedGpu, + MEMORY_DESCRIPTOR **ppPhysMemDesc +) +{ + RsResourceRef *pPhysmemRef; + MEMORY_DESCRIPTOR *pPhysMemDesc; + NvU32 physPageSize; + NV_STATUS status; + + status = serverutilGetResourceRef(RES_GET_CLIENT_HANDLE(pMemoryMulticastFabric), + hPhysMem, &pPhysmemRef); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to get resource in resserv for physmem handle\n"); + + return status; + } + + pPhysMemDesc = (dynamicCast(pPhysmemRef->pResource, Memory))->pMemDesc; + + if (memdescGetAddressSpace(pPhysMemDesc) != ADDR_FBMEM || + (pAttachedGpu != pPhysMemDesc->pGpu)) + { + NV_PRINTF(LEVEL_ERROR, "Invalid physmem handle passed\n"); + + return NV_ERR_INVALID_ARGUMENT; + } + + physPageSize = memdescGetPageSize(pPhysMemDesc, AT_GPU); + if ((physPageSize != RM_PAGE_SIZE_HUGE) && + (physPageSize != RM_PAGE_SIZE_512M)) + { + NV_PRINTF(LEVEL_ERROR, "Physmem page size should be 2MB\n"); + + return NV_ERR_INVALID_ARGUMENT; + } + + *ppPhysMemDesc = pPhysMemDesc; + + return NV_OK; +} + +NV_STATUS +memorymulticastfabricCtrlAttachMem_IMPL +( + MemoryMulticastFabric *pMemoryMulticastFabric, + NV00FD_CTRL_ATTACH_MEM_PARAMS *pParams +) +{ + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = \ + pMemoryMulticastFabric->pMulticastFabricDesc; + MEM_MULTICAST_FABRIC_GPU_INFO *pGpuInfo; + NV_STATUS status; + MEMORY_DESCRIPTOR *pPhysMemDesc; + MEMORY_DESCRIPTOR *pFabricMemDesc; + NvHandle hDupedPhysMem = 0; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + FABRIC_VASPACE *pFabricVAS; + MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO_NODE *pNode; + + if (pParams->flags != 0) + return NV_ERR_INVALID_ARGUMENT; + + pGpuInfo = _memorymulticastfabricGetAttchedGpuInfo(pMemoryMulticastFabric, + pParams->hSubdevice); + if (pGpuInfo == NULL) + return NV_ERR_INVALID_DEVICE; + + status = _memorymulticastfabricValidatePhysMem(pMemoryMulticastFabric, + pParams->hMemory, + pGpuInfo->pGpu, + &pPhysMemDesc); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to validate physmem handle\n"); + return status; + } + + pFabricVAS = dynamicCast(pGpuInfo->pGpu->pFabricVAS, FABRIC_VASPACE); + NV_ASSERT_OR_RETURN(pFabricVAS != NULL, NV_ERR_INVALID_STATE); + + pFabricMemDesc = pMulticastFabricDesc->pMemDesc; + NV_ASSERT_OR_RETURN(pFabricMemDesc != NULL, NV_ERR_INVALID_STATE); + + // + // No need to cleanup this MCFLA state on any further failure. We expect + // to get this cleaned up on object destruction only. + // + if (!pGpuInfo->bMcflaAlloc) + { + VAS_ALLOC_FLAGS flags = { 0 }; + + status = fabricvaspaceAllocMulticast(pFabricVAS, + memdescGetPageSize(pFabricMemDesc, AT_GPU), + pMulticastFabricDesc->alignment, + flags, pFabricMemDesc->_pteArray[0], + pMulticastFabricDesc->allocSize); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Fabric VA space alloc failed! for GPU\n"); + return status; + } + + pGpuInfo->bMcflaAlloc = NV_TRUE; + } + + status = pRmApi->DupObject(pRmApi, pFabricVAS->hClient, + pFabricVAS->hDevice, &hDupedPhysMem, + RES_GET_CLIENT_HANDLE(pMemoryMulticastFabric), + pParams->hMemory, 0); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to dup physmem handle\n"); + return status; + } + + status = fabricvaspaceMapPhysMemdesc(pFabricVAS, + pFabricMemDesc, + pParams->offset, + pPhysMemDesc, + pParams->mapOffset, + pParams->mapLength, + 0); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to map FLA\n"); + goto freeDupedMem; + } + + pNode = portMemAllocNonPaged(sizeof(*pNode)); + if (pNode == NULL) + { + status = NV_ERR_NO_MEMORY; + goto unmapVas; + } + + portMemSet(pNode, 0, sizeof(*pNode)); + + pNode->node.keyStart = pParams->offset; + pNode->node.keyEnd = pParams->offset; + pNode->physMapLength = pParams->mapLength; + pNode->pPhysMemDesc = pPhysMemDesc; + pNode->hDupedPhysMem = hDupedPhysMem; + pNode->node.Data = pNode; + + status = btreeInsert(&pNode->node, &pGpuInfo->pAttachMemInfoTree); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to track attach mem info\n"); + goto freeNode; + } + return NV_OK; -goto inbandFail; -inbandFail: - _memMulticastFabricAttachMemInfoRemoveUnderLock(pMulticastFabricDesc, pAttachMemNode); +freeNode: + portMemFree(pNode); -addInfoFail: - // Take all GPU lock. This is enforced by the vidmem class - NV_ASSERT_OK(rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_MEM_FLA)); - NV_ASSERT(pRmApi->Free(pRmApi, pFabricVAS->hClient, hDupedPhysMem) == NV_OK); - rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); +unmapVas: + fabricvaspaceUnmapPhysMemdesc(pFabricVAS, pFabricMemDesc, pParams->offset, + pPhysMemDesc, pParams->mapLength); -fail: - if (rmDeviceGpuLockIsOwner(pGpu->gpuInstance)) - rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); +freeDupedMem: + NV_ASSERT_OK(pRmApi->Free(pRmApi, pFabricVAS->hClient, hDupedPhysMem)); return status; } @@ -1375,12 +1293,6 @@ memorymulticastfabricCanCopy_IMPL return NV_TRUE; } -// -// memorymulticastfabricCopyConstruct_IMPL does not take -// the multicast fabric mutex lock as it can be invoked -// with the GPU locks held which would result in a lock -// inversion. Hence we resort to portAtomics here. -// NV_STATUS memorymulticastfabricCopyConstruct_IMPL ( @@ -1390,6 +1302,9 @@ memorymulticastfabricCopyConstruct_IMPL ) { MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc; + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + + fabricMulticastFabricOpsMutexAcquire(pFabric); MemoryMulticastFabric *pSourceMemoryMulticastFabric = dynamicCast(pParams->pSrcRef->pResource, MemoryMulticastFabric); @@ -1398,7 +1313,9 @@ memorymulticastfabricCopyConstruct_IMPL pMemoryMulticastFabric->pMulticastFabricDesc = pMulticastFabricDesc; - portAtomicExIncrementU64(&pMulticastFabricDesc->refCount); + pMulticastFabricDesc->refCount++; + + fabricMulticastFabricOpsMutexRelease(pFabric); return NV_OK; } @@ -1423,12 +1340,6 @@ memorymulticastfabricCtrlGetInfo_IMPL return NV_OK; } -// -// memorymulticastfabricIsReady_IMPL does not take -// the multicast fabric mutex lock as it can be invoked -// with the GPU locks held which would result in a lock -// inversion. Hence we resort to portAtomics here. -// NV_STATUS memorymulticastfabricIsReady_IMPL ( @@ -1436,16 +1347,21 @@ memorymulticastfabricIsReady_IMPL NvBool bCopyConstructorContext ) { + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); Memory *pMemory = staticCast(pMemoryMulticastFabric, Memory); MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc; NV_STATUS mcTeamStatus; - pMulticastFabricDesc = pMemoryMulticastFabric->pMulticastFabricDesc; + fabricMulticastFabricOpsMutexAcquire(pFabric); - mcTeamStatus = portAtomicOrU32(&pMulticastFabricDesc->mcTeamStatus, 0); + pMulticastFabricDesc = pMemoryMulticastFabric->pMulticastFabricDesc; + mcTeamStatus = pMulticastFabricDesc->mcTeamStatus; if (bCopyConstructorContext && (mcTeamStatus == NV_ERR_NOT_READY)) + { + fabricMulticastFabricOpsMutexRelease(pFabric); return NV_OK; + } if (pMemory->pMemDesc != pMulticastFabricDesc->pMemDesc) { @@ -1457,6 +1373,8 @@ memorymulticastfabricIsReady_IMPL NVOS32_MEM_TAG_NONE, NULL)); } + fabricMulticastFabricOpsMutexRelease(pFabric); + return mcTeamStatus; } @@ -1486,10 +1404,10 @@ memorymulticastfabricControl_Prologue_IMPL RmResource *pResource = staticCast(pMemoryMulticastFabric, RmResource); // Other control calls, nothing to be validated. - if (pParams->cmd != NV00FD_CTRL_CMD_ATTACH_MEM) + if (pParams->cmd != NV00FD_CTRL_CMD_ATTACH_GPU) return rmresControl_Prologue_IMPL(pResource, pCallContext, pParams); - return _memMulticastFabricGpuOsInfoAddUnderLock(pMemoryMulticastFabric, pParams); + return _memMulticastFabricGpuInfoAddUnderLock(pMemoryMulticastFabric, pParams); } NV_STATUS @@ -1503,10 +1421,8 @@ memorymulticastfabricControl_IMPL Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); NV_STATUS status = NV_OK; - if (pParams->cmd != NV00FD_CTRL_CMD_ATTACH_MEM) - { + if (pParams->cmd != NV00FD_CTRL_CMD_ATTACH_GPU) status = memorymulticastfabricIsReady(pMemoryMulticastFabric, NV_FALSE); - } // // If clients try to register when the multicast object @@ -1514,7 +1430,7 @@ memorymulticastfabricControl_IMPL // descriptor is already installed. // // If the status is NV_ERR_NOT_READY then we are yet to - // receive the inband reponse and we register the event. + // receive the inband response and we register the event. // if (pParams->cmd == NV00FD_CTRL_CMD_REGISTER_EVENT) { @@ -1539,12 +1455,6 @@ memorymulticastfabricControl_IMPL return status; } -// -// memorymulticastfabricIsGpuMapAllowed_IMPL does not take -// the multicast fabric mutex lock as it can be invoked -// with the GPU locks held which would result in a lock -// inversion. Hence we resort to portAtomics here. -// NvBool memorymulticastfabricIsGpuMapAllowed_IMPL ( @@ -1552,12 +1462,17 @@ memorymulticastfabricIsGpuMapAllowed_IMPL OBJGPU *pGpu ) { + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc; NvU32 attachedGpusMask; + fabricMulticastFabricOpsMutexAcquire(pFabric); + pMulticastFabricDesc = pMemoryMulticastFabric->pMulticastFabricDesc; - attachedGpusMask = portAtomicOrU32(&pMulticastFabricDesc->attachedGpusMask, 0); + attachedGpusMask = pMulticastFabricDesc->attachedGpusMask; + + fabricMulticastFabricOpsMutexRelease(pFabric); return ((attachedGpusMask & NVBIT32(pGpu->gpuInstance)) != 0U); } diff --git a/src/nvidia/src/kernel/mem_mgr/pool_alloc.c b/src/nvidia/src/kernel/mem_mgr/pool_alloc.c index d4da7b36a..0874c1e5f 100644 --- a/src/nvidia/src/kernel/mem_mgr/pool_alloc.c +++ b/src/nvidia/src/kernel/mem_mgr/pool_alloc.c @@ -39,6 +39,7 @@ /* ------------------------------------ Local Defines ------------------------------ */ #define PMA_CHUNK_SIZE_512M (512 * 1024 * 1024) +#define PMA_CHUNK_SIZE_4M (4 * 1024 * 1024) #define PMA_CHUNK_SIZE_2M (2 * 1024 * 1024) #define PMA_CHUNK_SIZE_512K (512 * 1024) #define PMA_CHUNK_SIZE_256K (256 * 1024) @@ -95,17 +96,17 @@ typedef enum /*! * This array contains the alloction sizes (in bytes) of each pool. */ -static const NvU32 poolAllocSizes[] = {0x20000000, 0x200000, 0x40000, 0x20000, 0x10000, 0x2000, 0x1000, 0x100}; +static const NvU64 poolAllocSizes[] = {0x20000000, 0x200000, 0x40000, 0x20000, 0x10000, 0x2000, 0x1000, 0x100}; #define POOL_CONFIG_POOL_IDX 0 #define POOL_CONFIG_CHUNKSIZE_IDX 1 -static const int poolConfig[POOL_CONFIG_MAX_SUPPORTED][POOL_CONFIG_CHUNKSIZE_IDX + 1] = { +static const NvU64 poolConfig[POOL_CONFIG_MAX_SUPPORTED][POOL_CONFIG_CHUNKSIZE_IDX + 1] = { // page size // chunk size { RM_POOL_IDX_256K, PMA_CHUNK_SIZE_512K}, // pool with pageSize = 256K for GMMU_FMT_VERSION_1 { RM_POOL_IDX_4K, PMA_CHUNK_SIZE_64K }, // pool with pageSize = 4K for GMMU_FMT_VERSION_2 { RM_POOL_IDX_512M, PMA_CHUNK_SIZE_512M }, // pool with pageSize = 512MB for RM allocated buffers (unused as of ampere) - { RM_POOL_IDX_2M, PMA_CHUNK_SIZE_2M }, // pool with pageSize = 2MB for RM allocated buffers + { RM_POOL_IDX_2M, PMA_CHUNK_SIZE_4M }, // pool with pageSize = 2MB for RM allocated buffers { RM_POOL_IDX_64K, PMA_CHUNK_SIZE_256K }, // pool with pageSize = 64K for RM allocated buffers { RM_POOL_IDX_4K, PMA_CHUNK_SIZE_64K } // pool with pageSize = 4K for RM allocated buffers }; @@ -444,7 +445,7 @@ rmMemPoolSetup flags = FLD_SET_DRF(_RMPOOL, _FLAGS, _AUTO_POPULATE, _DISABLE, flags); } pMemReserveInfo->pPool[pMemReserveInfo->topmostPoolIndex] = poolInitialize( - (NvU32)pMemReserveInfo->pmaChunkSize, + pMemReserveInfo->pmaChunkSize, poolAllocSizes[pMemReserveInfo->topmostPoolIndex], allocUpstreamTopPool, freeUpstreamTopPool, @@ -611,7 +612,7 @@ rmMemPoolAllocate if (allocSize <= poolAllocSizes[poolIndex]) { NV_PRINTF(LEVEL_INFO, - "Allocating from pool with alloc size = 0x%x Bytes\n", + "Allocating from pool with alloc size = 0x%llx Bytes\n", poolAllocSizes[poolIndex]); break; } @@ -633,7 +634,7 @@ rmMemPoolAllocate NvU32 index; NV_PRINTF(LEVEL_INFO, - "Allocating from pool with alloc size = 0x%x Bytes\n", + "Allocating from pool with alloc size = 0x%llx Bytes\n", poolAllocSizes[topPool] * numPages); if (memdescGetContiguity(pMemDesc, AT_GPU)) @@ -981,7 +982,7 @@ rmMemPoolGetChunkAndPageSize ( RM_POOL_ALLOC_MEM_RESERVE_INFO *pMemReserveInfo, NvU64 *pChunkSize, - NvU32 *pPageSize + NvU64 *pPageSize ) { NV_ASSERT_OR_RETURN(pMemReserveInfo != NULL, NV_ERR_INVALID_ARGUMENT); diff --git a/src/nvidia/src/kernel/mem_mgr/standard_mem.c b/src/nvidia/src/kernel/mem_mgr/standard_mem.c index 932ea2c5d..6c0e67faf 100644 --- a/src/nvidia/src/kernel/mem_mgr/standard_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/standard_mem.c @@ -237,7 +237,7 @@ NvBool stdmemCanCopy_IMPL(StandardMemory *pStandardMemory) * @returns * The page size in bytes. */ -NvU32 +NvU64 stdmemQueryPageSize ( MemoryManager *pMemoryManager, diff --git a/src/nvidia/src/kernel/mem_mgr/system_mem.c b/src/nvidia/src/kernel/mem_mgr/system_mem.c index c2632f8ba..6c44fe41b 100644 --- a/src/nvidia/src/kernel/mem_mgr/system_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/system_mem.c @@ -46,7 +46,6 @@ * @brief * This routine provides common allocation services used by the * following heap allocation functions: - * NVOS32_FUNCTION_ALLOC_DEPTH_WIDTH_HEIGHT * NVOS32_FUNCTION_ALLOC_SIZE * NVOS32_FUNCTION_ALLOC_SIZE_RANGE * NVOS32_FUNCTION_ALLOC_TILED_PITCH_HEIGHT diff --git a/src/nvidia/src/kernel/mem_mgr/video_mem.c b/src/nvidia/src/kernel/mem_mgr/video_mem.c index c45b668b1..3ca0ef634 100644 --- a/src/nvidia/src/kernel/mem_mgr/video_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/video_mem.c @@ -448,7 +448,6 @@ vidmemCopyConstruct * @brief * This routine provides common allocation services used by the * following heap allocation functions: - * NVOS32_FUNCTION_ALLOC_DEPTH_WIDTH_HEIGHT * NVOS32_FUNCTION_ALLOC_SIZE * NVOS32_FUNCTION_ALLOC_SIZE_RANGE * NVOS32_FUNCTION_ALLOC_TILED_PITCH_HEIGHT @@ -1061,6 +1060,20 @@ vidmemAllocResources status = NV_ERR_INVALID_ARGUMENT; goto failed; } + // + // In NUMA systems, the memory allocation comes from kernel + // and kernel doesn't support fixed address allocation. + // + if ((pVidHeapAlloc->flags & NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE) && + bIsPmaOwned && + osNumaOnliningEnabled(pGpu->pOsGpuInfo)) + { + NV_PRINTF(LEVEL_WARNING, + "NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE for PMA cannot be " + "accommodated for NUMA systems\n"); + status = NV_ERR_INVALID_ARGUMENT; + goto failed; + } if (FLD_TEST_DRF(OS32, _ATTR2, _32BIT_POINTER, _ENABLE, pVidHeapAlloc->attr2)) { NV_PRINTF(LEVEL_WARNING, diff --git a/src/nvidia/src/kernel/mem_mgr/virtual_mem.c b/src/nvidia/src/kernel/mem_mgr/virtual_mem.c index 8459fedc0..66b8a45cb 100644 --- a/src/nvidia/src/kernel/mem_mgr/virtual_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/virtual_mem.c @@ -270,7 +270,6 @@ _virtmemCopyConstruct * @brief * This routine provides common allocation services used by the * following heap allocation functions: - * NVOS32_FUNCTION_ALLOC_DEPTH_WIDTH_HEIGHT * NVOS32_FUNCTION_ALLOC_SIZE * NVOS32_FUNCTION_ALLOC_SIZE_RANGE * NVOS32_FUNCTION_ALLOC_TILED_PITCH_HEIGHT @@ -947,7 +946,7 @@ NV_STATUS virtmemReserveMempool_IMPL OBJGPU *pGpu, NvHandle hDevice, NvU64 size, - NvU32 pageSizeMask + NvU64 pageSizeMask ) { RsClient *pClient = RES_GET_CLIENT(pVirtualMemory); @@ -1234,7 +1233,6 @@ virtmemMapTo_IMPL NvBool bDmaMapNeeded = pParams->bDmaMapNeeded; NvBool bDmaMapped = NV_FALSE; - NvBool bDmaUnmapped = NV_FALSE; NvBool bDmaMappingRegistered = NV_FALSE; NvBool bFlaMapping = pParams->bFlaMapping; NvBool bIsIndirectPeer = NV_FALSE; @@ -1270,7 +1268,7 @@ virtmemMapTo_IMPL if (offset + length > pSrcMemDesc->Size) return NV_ERR_INVALID_BASE; - status = intermapCreateDmaMapping(pClient, pMemoryRef, hBroadcastDevice, hVirtualMem, &pDmaMappingInfo, flags); + status = intermapCreateDmaMapping(pClient, pVirtualMemory, &pDmaMappingInfo, flags); if (status != NV_OK) return status; @@ -1328,14 +1326,6 @@ virtmemMapTo_IMPL (tgtAddressSpace == ADDR_FABRIC_MC) || (tgtAddressSpace == ADDR_FABRIC_V2)) { - // offset needs to be 0 when reusing a mapping. - if ((DRF_VAL(OS46, _FLAGS, _DMA_UNICAST_REUSE_ALLOC, flags) == NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_TRUE) && - (offset != 0)) - { - status = NV_ERR_INVALID_OFFSET; - goto done; - } - // // Create a MEMORY_DESCRIPTOR describing this region of the memory // alloc in question @@ -1415,7 +1405,7 @@ virtmemMapTo_IMPL if (status != NV_OK) goto done; - status = intermapRegisterDmaMapping(pClient, hBroadcastDevice, hVirtualMem, pDmaMappingInfo, pDmaMappingInfo->DmaOffset, gpuMask); + status = intermapRegisterDmaMapping(pClient, pVirtualMemory, pDmaMappingInfo, pDmaMappingInfo->DmaOffset, gpuMask); if (status != NV_OK) { dmaFreeMap(pGpu, pDma, pVas, @@ -1484,7 +1474,7 @@ virtmemMapTo_IMPL *pDmaOffset = pDmaMappingInfo->DmaOffset; - status = intermapRegisterDmaMapping(pClient, hBroadcastDevice, hVirtualMem, pDmaMappingInfo, pDmaMappingInfo->DmaOffset, gpuMask); + status = intermapRegisterDmaMapping(pClient, pVirtualMemory, pDmaMappingInfo, pDmaMappingInfo->DmaOffset, gpuMask); if (status != NV_OK) { dmaFreeMap(pGpu, pDma, pVas, @@ -1553,7 +1543,7 @@ vgpu_send_rpc: pDmaMappingInfo->DmaOffset = *pDmaOffset; - status = intermapRegisterDmaMapping(pClient, hBroadcastDevice, hVirtualMem, pDmaMappingInfo, + status = intermapRegisterDmaMapping(pClient, pVirtualMemory, pDmaMappingInfo, pDmaMappingInfo->DmaOffset, gpuMask); if (status != NV_OK) goto done; @@ -1630,11 +1620,11 @@ done: if (bDmaMappingRegistered) { - intermapDelDmaMapping(pClient, hBroadcastDevice, hVirtualMem, *pDmaOffset, gpuMask, &bDmaUnmapped); + NV_ASSERT_OK(intermapDelDmaMapping(pClient, pVirtualMemory, *pDmaOffset, gpuMask)); } - if (!bDmaUnmapped) + else { - // Explicitly free the DMA mapping if intermapDelDmaMapping was not able to clean up + // Explicitly free the DMA mapping if mapping was not yet registered intermapFreeDmaMapping(pDmaMappingInfo); } } @@ -1665,7 +1655,6 @@ virtmemUnmapFrom_IMPL OBJVASPACE *pVas = NULL; NV_STATUS status = NV_OK; NvBool bIsIndirectPeer = NV_FALSE; - NvBool bReturnStatus; CLI_DMA_MAPPING_INFO *pDmaMappingInfo = NULL; @@ -1702,9 +1691,8 @@ virtmemUnmapFrom_IMPL return status; // Get DMA mapping info. - bReturnStatus = CliGetDmaMappingInfo(hClient, hBroadcastDevice, hVirtualMem, dmaOffset, gpuMask, &pDmaMappingInfo); - if (!bReturnStatus) - return NV_ERR_INVALID_OBJECT_HANDLE; + pDmaMappingInfo = intermapGetDmaMapping(pVirtualMemory, dmaOffset, gpuMask); + NV_ASSERT_OR_RETURN(pDmaMappingInfo != NULL, NV_ERR_INVALID_OBJECT_HANDLE); // // if Kernel cookie exists and mapping is in sysmem, free sysmem mapping @@ -1756,19 +1744,13 @@ virtmemUnmapFrom_IMPL } } - while (bReturnStatus) - { - // free memory descriptor - memdescFree(pDmaMappingInfo->pMemDesc); - memdescDestroy(pDmaMappingInfo->pMemDesc); - pDmaMappingInfo->pMemDesc = NULL; + // free memory descriptor + memdescFree(pDmaMappingInfo->pMemDesc); + memdescDestroy(pDmaMappingInfo->pMemDesc); + pDmaMappingInfo->pMemDesc = NULL; - // delete client dma mapping - intermapDelDmaMapping(pClient, hBroadcastDevice, hVirtualMem, dmaOffset, gpuMask, NULL); - - // Get the next DMA mapping info for this offset and gpu mask - bReturnStatus = CliGetDmaMappingInfo(hClient, hBroadcastDevice, hVirtualMem, dmaOffset, gpuMask, &pDmaMappingInfo); - } + // delete client dma mapping + intermapDelDmaMapping(pClient, pVirtualMemory, dmaOffset, gpuMask); // // vGPU: diff --git a/src/nvidia/src/kernel/os/os_init.c b/src/nvidia/src/kernel/os/os_init.c index 3bedab158..4af417375 100644 --- a/src/nvidia/src/kernel/os/os_init.c +++ b/src/nvidia/src/kernel/os/os_init.c @@ -128,8 +128,6 @@ initWinNTStubOSFunctionPointers(OBJOS *pOS) pOS->osQueueWorkItem = stubOsQueueWorkItem; pOS->osQueueWorkItemWithFlags = stubOsQueueWorkItemWithFlags; pOS->osQueueSystemWorkItem = stubOsQueueSystemWorkItem; - pOS->osCallACPI_MXMX = stubOsCallACPI_MXMX; - pOS->osCallACPI_DDC = stubOsCallACPI_DDC; pOS->osCallACPI_BCL = stubOsCallACPI_BCL; pOS->osCallACPI_ON = stubOsCallACPI_ON; pOS->osCallACPI_OFF = stubOsCallACPI_OFF; @@ -139,18 +137,12 @@ initWinNTStubOSFunctionPointers(OBJOS *pOS) pOS->osCallACPI_NVHG_MXDS = stubOsCallWMI_NVHG_MXDS; pOS->osCallACPI_NVHG_MXMX = stubOsCallWMI_NVHG_MXMX; pOS->osCallACPI_NVHG_DOS = stubOsCallWMI_NVHG_DOS; - pOS->osCallACPI_NVHG_ROM = stubOsCallWMI_NVHG_ROM; pOS->osCallACPI_NVHG_DCS = stubOsCallWMI_NVHG_DCS; - pOS->osCallACPI_DOD = stubOsCallWMI_DOD; pOS->osSetupVBlank = stubOsSetupVBlank; pOS->osCallACPI_NBPS = stubOsCallACPI_NBPS; pOS->osCallACPI_NBSL = stubOsCallACPI_NBSL; - pOS->osCallACPI_DSM = stubOsCallACPI_DSM; pOS->osCallACPI_OPTM_GPUON = stubOsCallWMI_OPTM_GPUON; pOS->osGetUefiVariable = stubOsGetUefiVariable; - pOS->osCallACPI_MXDS = stubOsCallACPI_MXDS; - pOS->osCallACPI_MXDM = stubOsCallACPI_MXDM; - pOS->osCallACPI_MXID = stubOsCallACPI_MXID; pOS->osCallACPI_LRST = stubOsCallACPI_LRST; } @@ -163,8 +155,6 @@ initMacOSCoreOSFunctionPointers(OBJOS *pOS) pOS->osNv_rdmsr = stubOsnv_rdmsr; pOS->osNv_wrmsr = stubOsnv_wrmsr; pOS->osRobustChannelsDefaultState = stubOsRobustChannelsDefaultState; - pOS->osCallACPI_MXMX = stubOsCallACPI_MXMX; - pOS->osCallACPI_DDC = stubOsCallACPI_DDC; pOS->osCallACPI_BCL = stubOsCallACPI_BCL; pOS->osGetUefiVariable = stubOsGetUefiVariable; } diff --git a/src/nvidia/src/kernel/os/os_stubs.c b/src/nvidia/src/kernel/os/os_stubs.c index 8ea7a0329..5b1f42445 100644 --- a/src/nvidia/src/kernel/os/os_stubs.c +++ b/src/nvidia/src/kernel/os/os_stubs.c @@ -140,15 +140,8 @@ NV_STATUS stubOsSimEscapeReadBuffer(OBJGPU *pGpu, const char *path, NvU32 Index, return NV_ERR_GENERIC; } -NV_STATUS stubOsCallACPI_MXMX(OBJGPU *pGpu, NvU32 AcpiId, NvU8 *pInOut) +NV_STATUS osCallACPI_MXMX(OBJGPU *pGpu, NvU32 AcpiId, NvU8 *pInOut) { - STUB_CHECK(220); - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS stubOsCallACPI_DDC(OBJGPU *pGpu, NvU32 ulAcpiId, NvU8 *pOut, NvU32 *size, NvBool bReadMultiBlock) -{ - STUB_CHECK(221); return NV_ERR_NOT_SUPPORTED; } @@ -219,41 +212,13 @@ NV_STATUS stubOsCallWMI_NVHG_DOS(OBJGPU *pGpu, NvU32 AcpiId, NvU32 *pInOut) return NV_ERR_NOT_SUPPORTED; } -NV_STATUS stubOsCallWMI_NVHG_ROM(OBJGPU *pGpu, NvU32 *pIn, NvU32 *pOut) -{ - //STUB_CHECK(231); - return NV_ERR_NOT_SUPPORTED; -} - NV_STATUS stubOsCallWMI_NVHG_DCS(OBJGPU *pGpu, NvU32 AcpiId, NvU32 *pInOut) { //STUB_CHECK(232); return NV_ERR_NOT_SUPPORTED; } -NV_STATUS stubOsCallWMI_DOD(OBJGPU *pGpu, NvU32 *pInOut, NvU32 *pOutSize) -{ - //STUB_CHECK(233); - return NV_ERR_NOT_SUPPORTED; -} - - -NV_STATUS stubOsCallACPI_DSM(OBJGPU *pGpu, ACPI_DSM_FUNCTION acpiDSMFunction, NvU32 NVHGDSMSubfunction, NvU32 *pInOut, NvU16 *size) -{ - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS stubOsCallACPI_MXDS(OBJGPU *pGpu, NvU32 ulAcpiId, NvU32 *pInOut) -{ - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS stubOsCallACPI_MXDM(OBJGPU *pGpu, NvU32 ulAcpiId, NvU32 *pInOut) -{ - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS stubOsCallACPI_MXID(OBJGPU *pGpu, NvU32 ulAcpiId, NvU32 *pInOut) +NV_STATUS osCallACPI_MXID(OBJGPU *pGpu, NvU32 ulAcpiId, NvU32 *pInOut) { return NV_ERR_NOT_SUPPORTED; } @@ -474,15 +439,6 @@ osTegraSocParseFixedModeTimings } -NV_STATUS osVgpuAllocVmbusEventDpc(void **ppArg1) -{ - return NV_OK; -} - -void osVgpuScheduleVmbusEventDpc(void *pArg1, void *pArg2) -{ -} - NV_STATUS osLockPageableDataSection(RM_PAGEABLE_SECTION *pSection) { return NV_OK; @@ -692,6 +648,17 @@ stubOsGetUefiVariable return NV_ERR_NOT_SUPPORTED; } +NV_STATUS +osGetNvGlobalRegistryDword +( + OBJGPU *pGpu, + const char *pRegParmStr, + NvU32 *pData +) +{ + return NV_ERR_NOT_SUPPORTED; +} + NvU32 osGetDynamicPowerSupportMask(void) { return 0; @@ -839,6 +806,12 @@ osTegraSocFuseRegRead(NvU32 addr) return 0; } +NV_STATUS +osTegraSocHspSemaphoreAcquire(NvU32 ownerId, NvBool bAcquire, NvU64 timeout) +{ + return NV_ERR_NOT_SUPPORTED; +} + NV_STATUS osTegraSocDpUphyPllInit(OS_GPU_INFO *pOsGpuInfo, NvU32 link_rate, NvU32 lanes) { @@ -853,3 +826,4 @@ osTegraSocDpUphyPllDeInit(OS_GPU_INFO *pOsGpuInfo) #endif + diff --git a/src/nvidia/src/kernel/platform/acpi_common.c b/src/nvidia/src/kernel/platform/acpi_common.c index b1a7c8eff..2c2de6397 100644 --- a/src/nvidia/src/kernel/platform/acpi_common.c +++ b/src/nvidia/src/kernel/platform/acpi_common.c @@ -823,11 +823,11 @@ _acpiDsmSupportedFuncCacheInit // try package type for argument 3. pGpu->acpi.dsm[func].bArg3isInteger = NV_FALSE; rtnSize = sizeof(supportFuncs); - status = pGpu->pOS->osCallACPI_DSM(pGpu, - func, - NV_ACPI_ALL_FUNC_SUPPORT, - (NvU32 *) &supportFuncs, - &rtnSize); + status = osCallACPI_DSM(pGpu, + func, + NV_ACPI_ALL_FUNC_SUPPORT, + (NvU32 *) &supportFuncs, + &rtnSize); if (status != NV_OK) { if (status == NV_ERR_INVALID_ARGUMENT) @@ -835,11 +835,11 @@ _acpiDsmSupportedFuncCacheInit // maybe an older SBIOS, try integer type for argument 3. pGpu->acpi.dsm[func].bArg3isInteger = NV_TRUE; rtnSize = sizeof(supportFuncs); - status = pGpu->pOS->osCallACPI_DSM(pGpu, - func, - NV_ACPI_ALL_FUNC_SUPPORT, - (NvU32 *) &supportFuncs, - &rtnSize); + status = osCallACPI_DSM(pGpu, + func, + NV_ACPI_ALL_FUNC_SUPPORT, + (NvU32 *) &supportFuncs, + &rtnSize); } } if (_isDsmError(status, rtnSize, (NvU32 *) &supportFuncs)) @@ -908,11 +908,11 @@ _acpiDsmCallbackInit if (testIfDsmSubFunctionEnabled(pGpu, func, NV_ACPI_GENERIC_FUNC_CALLBACKS) == NV_OK) { - status = pGpu->pOS->osCallACPI_DSM(pGpu, - func, - NV_ACPI_GENERIC_FUNC_CALLBACKS, - &callbacks, - &rtnSize); + status = osCallACPI_DSM(pGpu, + func, + NV_ACPI_GENERIC_FUNC_CALLBACKS, + &callbacks, + &rtnSize); if (_isDsmError(status, rtnSize, &callbacks)) { @@ -981,11 +981,11 @@ _acpiDsmCapsInit if (testIfDsmSubFunctionEnabled(pGpu, func, asmDsmSubFunction) == NV_OK) { rtnSize = sizeof(platCaps); - status = pGpu->pOS->osCallACPI_DSM(pGpu, - func, - asmDsmSubFunction, - &platCaps, - &rtnSize); + status = osCallACPI_DSM(pGpu, + func, + asmDsmSubFunction, + &platCaps, + &rtnSize); if (_isDsmError(status, rtnSize, &platCaps)) { @@ -1108,7 +1108,6 @@ _acpiCacheMethodData ) { NV_STATUS status; - OBJOS *pOs = GPU_GET_OS(pGpu); NvU32 inOut = 0; NvU16 rtnSize = sizeof(inOut); NvU32 tableLen = 0, acpiidIndex = 0, mode = 0, muxPartId = 0; @@ -1119,16 +1118,17 @@ _acpiCacheMethodData // Fill in the DOD Method Data. pGpu->acpiMethodData.dodMethodData.acpiIdListLen = sizeof(pGpu->acpiMethodData.dodMethodData.acpiIdList); - status = pOs->osCallACPI_DOD(pGpu, pGpu->acpiMethodData.dodMethodData.acpiIdList, &pGpu->acpiMethodData.dodMethodData.acpiIdListLen); + status = osCallACPI_DOD(pGpu, pGpu->acpiMethodData.dodMethodData.acpiIdList, &pGpu->acpiMethodData.dodMethodData.acpiIdListLen); pGpu->acpiMethodData.dodMethodData.status = status; // Fill in the JT Method Data. - status = pOs->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_JT, JT_FUNC_CAPS, &inOut, &rtnSize); + status = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_JT, JT_FUNC_CAPS, &inOut, &rtnSize); pGpu->acpiMethodData.jtMethodData.status = status; pGpu->acpiMethodData.jtMethodData.jtCaps = inOut; - pGpu->acpiMethodData.jtMethodData.jtRevId = (NvU16)DRF_VAL(_JT_FUNC, _CAPS, _REVISION_ID, inOut); + pGpu->acpiMethodData.jtMethodData.jtRevId = (NvU16)DRF_VAL(_JT_FUNC, _CAPS, _REVISION_ID, inOut); + gpuSetGC6SBIOSCapabilities(pGpu); // Fill in the MUX Method Data. portMemSet(pGpu->acpiMethodData.muxMethodData.acpiIdMuxModeTable, 0, sizeof(pGpu->acpiMethodData.muxMethodData.acpiIdMuxModeTable)); @@ -1139,12 +1139,12 @@ _acpiCacheMethodData pGpu->acpiMethodData.muxMethodData.tableLen = tableLen; for (acpiidIndex = 0; acpiidIndex < tableLen; acpiidIndex++) { - status = pOs->osCallACPI_MXDM(pGpu, pGpu->acpiMethodData.dodMethodData.acpiIdList[acpiidIndex], &mode); + status = osCallACPI_MXDM(pGpu, pGpu->acpiMethodData.dodMethodData.acpiIdList[acpiidIndex], &mode); pGpu->acpiMethodData.muxMethodData.acpiIdMuxModeTable[acpiidIndex].acpiId = pGpu->acpiMethodData.dodMethodData.acpiIdList[acpiidIndex]; pGpu->acpiMethodData.muxMethodData.acpiIdMuxModeTable[acpiidIndex].mode = mode; pGpu->acpiMethodData.muxMethodData.acpiIdMuxModeTable[acpiidIndex].status = status; - status = pOs->osCallACPI_MXID(pGpu, pGpu->acpiMethodData.dodMethodData.acpiIdList[acpiidIndex], &muxPartId); + status = osCallACPI_MXID(pGpu, pGpu->acpiMethodData.dodMethodData.acpiIdList[acpiidIndex], &muxPartId); pGpu->acpiMethodData.muxMethodData.acpiIdMuxPartTable[acpiidIndex].acpiId = pGpu->acpiMethodData.dodMethodData.acpiIdList[acpiidIndex]; pGpu->acpiMethodData.muxMethodData.acpiIdMuxPartTable[acpiidIndex].mode = muxPartId; pGpu->acpiMethodData.muxMethodData.acpiIdMuxPartTable[acpiidIndex].status = status; @@ -1153,8 +1153,8 @@ _acpiCacheMethodData } // Fill in the Optimus caps Method Data. - status = pGpu->pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVOP, NVOP_FUNC_OPTIMUSCAPS, - &pGpu->acpiMethodData.capsMethodData.optimusCaps, &rtnSize); + status = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVOP, NVOP_FUNC_OPTIMUSCAPS, + &pGpu->acpiMethodData.capsMethodData.optimusCaps, &rtnSize); pGpu->acpiMethodData.capsMethodData.status = status; } diff --git a/src/nvidia/src/kernel/platform/chipset/chipset.c b/src/nvidia/src/kernel/platform/chipset/chipset.c index ce73e6864..0878531f1 100644 --- a/src/nvidia/src/kernel/platform/chipset/chipset.c +++ b/src/nvidia/src/kernel/platform/chipset/chipset.c @@ -133,7 +133,7 @@ clInitMappingPciBusDevice_IMPL NvU16 vendorID, deviceID; NvBool bFoundDevice = NV_FALSE; - if (IsT194(pGpu)) + if (IsT194(pGpu) || IsT234(pGpu)) return NV0000_CTRL_GPU_INVALID_ID; // do we already know our domain/bus/device? @@ -486,7 +486,7 @@ clFindFHBAndGetChipsetInfoIndex_IMPL } } - if (vendorID == PCI_INVALID_VENDORID) + if (!PCI_IS_VENDORID_VALID(vendorID)) break; // skip to the next device if ((osPciReadByte(handle, PCI_HEADER_TYPE0_BASECLASS)) != PCI_CLASS_BRIDGE_DEV) @@ -605,41 +605,6 @@ clIsL1MaskEnabledForUpstreamPort_IMPL return bEnable; } -// -// return the First Host Bridge's handle, VendorID and DeviceID -// -NV_STATUS -clGetFHBHandle_IMPL( - OBJCL *pCl, - void **Handle, - NvU16 *VendorID, - NvU16 *DeviceID -) -{ - NV_ASSERT(Handle && DeviceID && VendorID); // Avoid Null Pointer - - if (!pCl->FHBAddr.valid) - return NV_ERR_GENERIC; - - *Handle = pCl->FHBAddr.handle; - *DeviceID = pCl->FHBBusInfo.deviceID; - *VendorID = pCl->FHBBusInfo.vendorID; - - // can this happen, should this be #if 0 out? - if (*Handle == NULL) - { - *Handle = osPciInitHandle(pCl->FHBAddr.domain, - pCl->FHBAddr.bus, - pCl->FHBAddr.device, - pCl->FHBAddr.func, - VendorID, - DeviceID); - } - - return (*Handle ? NV_OK : NV_ERR_GENERIC); -} - - NV_STATUS clInit_IMPL( OBJGPU *pGpu, @@ -763,6 +728,7 @@ void clSyncWithGsp_IMPL(OBJCL *pCl, GspSystemInfo *pGSI) CL_SYNC_PDB(PDB_PROP_CL_ASPM_L1_CHIPSET_DISABLED); CL_SYNC_PDB(PDB_PROP_CL_ASPM_L0S_CHIPSET_ENABLED_MOBILE_ONLY); CL_SYNC_PDB(PDB_PROP_CL_ASPM_L1_CHIPSET_ENABLED_MOBILE_ONLY); + CL_SYNC_PDB(PDB_PROP_CL_ASPM_UPSTREAM_PORT_L1_MASK_ENABLED); CL_SYNC_PDB(PDB_PROP_CL_PCIE_GEN1_GEN2_SWITCH_CHIPSET_DISABLED); CL_SYNC_PDB(PDB_PROP_CL_PCIE_GEN1_GEN2_SWITCH_CHIPSET_DISABLED_GEFORCE); CL_SYNC_PDB(PDB_PROP_CL_EXTENDED_TAG_FIELD_NOT_CAPABLE); diff --git a/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c b/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c index 103c2e6e8..65c802ad7 100644 --- a/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c +++ b/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c @@ -782,6 +782,93 @@ _objClAdjustTcVcMap(OBJGPU *pGpu, OBJCL *pCl, PORTDATA *pPort) } } + +#define MAX_MULTI_GPU_BOARD_IDS 4 +typedef struct +{ + NvU16 gpuDevIds[MAX_MULTI_GPU_BOARD_IDS]; + NvU16 gpuSubVenIds[MAX_MULTI_GPU_BOARD_IDS]; + NvU16 gpuSubDevIds[MAX_MULTI_GPU_BOARD_IDS]; +} NV_MULTI_GPU_BOARD_CONFIGS; + +static const NV_MULTI_GPU_BOARD_CONFIGS multiGpuBoards[] = +{ +// gpuDevIds, gpuSubVenIds, gpuSubDevIds + +// A16 GPUs are 4xGPU boards with no nvlink +{{NV_PCI_DEVID_DEVICE_PG171_SKU200_PG179_SKU220, 0}, + {NV_PCI_SUBID_VENDOR_NVIDIA, + 0}, {NV_PCI_SUBID_DEVICE_PG171_SKU200, + 0}}, +}; + +/*! + * Searches through multiGpuBoards[] for the specified DEVID and possibly the + * SSVID and SSDID to determine if the GPU is in a multi GPU board. + * + * @param[in] gpuDevId DEVID of the GPU + * @param[in] gpuSubVenId The subdevice VENID of the GPU + * @param[in] gpuSubDevId The sbudevice DEVID of the GPU + * + * @return NV_TRUE if the GPU is in a multigpu board, NV_FALSE otherwise + */ +static NvBool +gpuDevIdIsMultiGpuBoard +( + NvU16 gpuDevId, + NvU16 gpuSubVenId, + NvU16 gpuSubDevId +) +{ + NvU32 i, j; + NvBool bFound = NV_FALSE, bInvalidSubIds = NV_FALSE; + + for (i = 0; i < sizeof(multiGpuBoards) / sizeof(NV_MULTI_GPU_BOARD_CONFIGS); + i++) + { + bInvalidSubIds = NV_FALSE; + + for (j = 0; j < MAX_MULTI_GPU_BOARD_IDS; j++) + { + // + // As soon as we see a NULL subvenid or subdevid, we stop checking them + // for this entry + // + if ((multiGpuBoards[i].gpuSubVenIds[j] == 0) || + (multiGpuBoards[i].gpuSubDevIds[j] == 0)) + { + bInvalidSubIds = NV_TRUE; + } + + // Arrays are NULL terminated + if (multiGpuBoards[i].gpuDevIds[j] == 0) + { + break; + } + // If the devid matches we might have a match + else if (multiGpuBoards[i].gpuDevIds[j] == gpuDevId) + { + // Do we need to also compare the subdevice ids? + if ((bInvalidSubIds) || + ((multiGpuBoards[i].gpuSubVenIds[j] == gpuSubVenId) && + (multiGpuBoards[i].gpuSubDevIds[j] == gpuSubDevId))) + { + bFound = NV_TRUE; + break; + } + } + } + + if (bFound) + { + break; + } + } + + return bFound; +} + + // // Determine if any updates are needed to the PCI Express // @@ -791,7 +878,6 @@ clUpdatePcieConfig_IMPL(OBJGPU *pGpu, OBJCL *pCl) OBJSYS *pSys = SYS_GET_INSTANCE(); OBJPFM *pPfm = SYS_GET_PFM(pSys); KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); - NvBool bIsGemini = NV_FALSE; NvBool bIsMultiGpu; NvU32 busIntfType = kbifGetBusIntfType_HAL(pKernelBif); @@ -850,24 +936,28 @@ clUpdatePcieConfig_IMPL(OBJGPU *pGpu, OBJCL *pCl) if (!pPfm->getProperty(pPfm, PDB_PROP_PFM_NO_HOSTBRIDGE_DETECT)) { - // - // MultiGpu board includes all Dagwood and Gemini boards - // A dagwood board would not have bIsGemini flag set but would have - // bIsMultiGpu flag set. - // - bIsMultiGpu = gpuIsMultiGpuBoard(pGpu, &bIsGemini); - if (bIsGemini) - { - pGpu->setProperty(pGpu, PDB_PROP_GPU_IS_GEMINI, NV_TRUE); - } + bIsMultiGpu = gpuIsMultiGpuBoard(pGpu); // Update the board ID only if the Gpu is a multiGpu board if (bIsMultiGpu) { gpumgrUpdateBoardId(pGpu); + + // All multi-GPU boards are Gemini boards. + pGpu->setProperty(pGpu, PDB_PROP_GPU_IS_GEMINI, NV_TRUE); } } + // Initialize ASPM L1 mask state for Upstream port + if (clIsL1MaskEnabledForUpstreamPort(pGpu, pCl)) + { + pCl->setProperty(pCl, PDB_PROP_CL_ASPM_UPSTREAM_PORT_L1_MASK_ENABLED, NV_TRUE); + } + else + { + pCl->setProperty(pCl, PDB_PROP_CL_ASPM_UPSTREAM_PORT_L1_MASK_ENABLED, NV_FALSE); + } + NV_PRINTF(LEVEL_INFO, "Chipset %X Domain %X Bus %X Device %X Func %X PCIE PTR %X\n", pCl->Chipset, @@ -1042,7 +1132,7 @@ objClInitGpuPortData if ((kbifGetBusIntfType_HAL(GPU_GET_KERNEL_BIF(pGpu)) != NV2080_CTRL_BUS_INFO_TYPE_FPCI) && (!pHypervisor || !pHypervisor->bDetected) && - !RMCFG_FEATURE_PLATFORM_MODS) + !RMCFG_FEATURE_MODS_FEATURES) { DBG_BREAKPOINT(); return NV_FALSE; @@ -1849,16 +1939,14 @@ objClFindRootPort // // clCountBR // -// Returns the count of cascaded BR03s and BR04s right under this GPU. +// Returns the count of cascaded BR04s right under this GPU. // void clCountBR_IMPL ( OBJGPU *pGpu, OBJCL *pCl, - NvU8 *pBR03Count, - NvU8 *pBR04Count, - NvU8 *pPLXCount + NvU8 *pBR04Count ) { void *handleUp; @@ -1866,9 +1954,7 @@ clCountBR_IMPL NvU8 bus = 0xff, busUp, deviceUp, funcUp; NvU32 domain; NvU8 downstreamPortBus; - NvU8 BR03Count = 0; NvU8 BR04Count = 0; - NvU8 PLXCount = 0; domain = gpuGetDomain(pGpu); handleUp = clFindBrdgUpstreamPort(pGpu, pCl, NV_TRUE, @@ -1878,18 +1964,10 @@ clCountBR_IMPL while (handleUp) { - if ((vendorIDUp == PCI_VENDOR_ID_NVIDIA) && (deviceIDUp == NV_BR03_XVU_DEV_ID_DEVICE_ID_BR03)) - { - BR03Count++; - } - else if((vendorIDUp == PCI_VENDOR_ID_NVIDIA) && IS_DEVID_BR04(deviceIDUp)) + if ((vendorIDUp == PCI_VENDOR_ID_NVIDIA) && IS_DEVID_BR04(deviceIDUp)) { BR04Count++; } - else if((vendorIDUp == PCI_VENDOR_ID_PLX) && IS_DEVID_SUPPORTED_PLX(deviceIDUp)) - { - PLXCount++; - } else { break; @@ -1908,9 +1986,7 @@ clCountBR_IMPL } } - *pBR03Count = BR03Count; *pBR04Count = BR04Count; - *pPLXCount = PLXCount; return ; } @@ -1980,6 +2056,17 @@ clSearchBR04_IMPL } pBusTopologyInfoBR04GPU = pBusTopologyInfoBR04GPU->next; } + if (pBusTopologyInfoBR04GPU) + { + // There is something + if ((pBusTopologyInfoBR04GPU->busInfo.vendorID == PCI_VENDOR_ID_NVIDIA) && + (gpuDevIdIsMultiGpuBoard(pBusTopologyInfoBR04GPU->busInfo.deviceID, 0, 0))) + { + // This is a BR04 in a Gemini, skip this DS port + pBusTopologyInfoBR04DS = pBusTopologyInfoBR04DS->next; + continue; + } + } BR04DSPorts++; } pBusTopologyInfoBR04DS = pBusTopologyInfoBR04DS->next; @@ -2020,7 +2107,7 @@ clSearchBR04_IMPL // Returns the bus number of a common bridge behind the 2 GPUs. // The returned values are 0xFF when no bridge is found. // This function finds the most upper bridge(s) if bScanAll is set to NV_TRUE. -// This function finds the first recognized bridge (BR04, BR03, PLX) under the GPUs if bScanAll is set to NV_FALSE. +// This function finds the first recognized bridge (BR04) under the GPUs if bScanAll is set to NV_FALSE. // void clFindCommonBR_IMPL @@ -2028,9 +2115,7 @@ clFindCommonBR_IMPL OBJGPU *pGpu1, OBJGPU *pGpu2, OBJCL *pCl, - NvU8 *pBR03Bus, NvU8 *pBR04Bus, - NvU8 *pPLXBus, NvBool bScanAll ) { @@ -2039,9 +2124,7 @@ clFindCommonBR_IMPL NvU8 bus1 = 0xff, busUp1, deviceUp1, funcUp1, bus2 = 0xff, busUp2, deviceUp2, funcUp2; NvU32 domain1, domain2; NvU8 downstreamPortBus1, downstreamPortBus2; - NvU8 BR03Bus = 0xFF; NvU8 BR04Bus = 0xFF; - NvU8 PLXBus = 0xFF; NV_ASSERT(pGpu1 != pGpu2); @@ -2051,16 +2134,14 @@ clFindCommonBR_IMPL if (domain1 != domain2) { // - //1. If two GPUs are from different PCI domains, then there can not be a common BR03/BR04 bridge + //1. If two GPUs are from different PCI domains, then there can not be a common BR04 bridge // that connects to both GPUs. Because a new domain will start form a host bridge. //2. Returning early when two GPUs are from different PCI domains save significant GPU initialization // time when we have more that 6 GPUs in the system connected to different domains. This function // is called multiple times while searching for 2-way 3-way and 4-way sli combination. (Bug 770154) // - *pBR03Bus = BR03Bus; *pBR04Bus = BR04Bus; - *pPLXBus = PLXBus; return; } @@ -2091,21 +2172,6 @@ clFindCommonBR_IMPL BR04Bus = busUp2; break; } - - if ((vendorIDUp2 == PCI_VENDOR_ID_NVIDIA) && - (deviceIDUp1 == NV_BR03_XVU_DEV_ID_DEVICE_ID_BR03) && - (deviceIDUp2 == NV_BR03_XVU_DEV_ID_DEVICE_ID_BR03)) - { - BR03Bus = busUp2; - break; - } - if ((vendorIDUp2 == PCI_VENDOR_ID_PLX) && - IS_DEVID_SUPPORTED_PLX(deviceIDUp1) && - IS_DEVID_SUPPORTED_PLX(deviceIDUp2)) - { - PLXBus = busUp2; - break; - } } bus2 = busUp2; @@ -2120,8 +2186,7 @@ clFindCommonBR_IMPL // If we requested to not scan all the devices up to the root port, // and we found one, stop right here. // - if (!bScanAll && - ((BR04Bus != 0xFF) || (BR03Bus != 0xFF) || (PLXBus != 0xFF))) + if (!bScanAll && (BR04Bus != 0xFF)) { break; } @@ -2133,9 +2198,7 @@ clFindCommonBR_IMPL &funcUp1, &vendorIDUp1, &deviceIDUp1); } - *pBR03Bus = BR03Bus; *pBR04Bus = BR04Bus; - *pPLXBus = PLXBus; return ; } @@ -2251,8 +2314,7 @@ clFindBR_IMPL NvU8 *pBR04Bus, NvBool *pBRNot3rdParty, NvBool *pNoUnsupportedBRFound, - NvBool *pNoOnboardBR04, - NvU8 *pPLXBus + NvBool *pNoOnboardBR04 ) { void *handleUp, *br04handle = NULL; @@ -2263,7 +2325,6 @@ clFindBR_IMPL NvU32 regValue = 0; NvU32 gpuBrNot3rdPartyCount = 0, gpuBrCount = 0; NvBool bGpuIsMultiGpuBoard = NV_FALSE; - NvBool bIsGemini = NV_FALSE; NvU32 gpuBR04Count = 0; NvU8 BR03Bus = 0xFF; NvU8 BR04Bus = 0xFF; @@ -2280,7 +2341,7 @@ clFindBR_IMPL &vendorIDUp, &deviceIDUp, &downstreamPortBus1); - bGpuIsMultiGpuBoard = gpuIsMultiGpuBoard(pGpu, &bIsGemini); + bGpuIsMultiGpuBoard = gpuIsMultiGpuBoard(pGpu); // Traverse the pci tree while (handleUp) @@ -2321,7 +2382,7 @@ clFindBR_IMPL PLXBus = busUp; } - // Do not count the BR04A03, PLX, and the bridges behind the dagwoods. + // Do not count the BR04A03, PLX, and the bridges behind the multi-GPU boards. if ((BR04Rev != 0x3) && (PLXBus == 0xFF) && ((gpuBrCount != 1) || (bGpuIsMultiGpuBoard == NV_FALSE))) { gpuBrNot3rdPartyCount++; @@ -2334,7 +2395,7 @@ clFindBR_IMPL &funcUp, &vendorIDUp, &deviceIDUp); } - if (bIsGemini && gpuBR04Count) + if (bGpuIsMultiGpuBoard && gpuBR04Count) { // Ignore one BR04 in case of Gemini gpuBR04Count--; @@ -2352,7 +2413,6 @@ clFindBR_IMPL *pBRNot3rdParty = brNot3rdParty; *pNoOnboardBR04 = bNoOnboardBR04 ; *pNoUnsupportedBRFound = bNoUnsupportedBRFound; - *pPLXBus = PLXBus; return ; } @@ -2439,7 +2499,7 @@ clStoreBusTopologyCache_IMPL } } - if (vendorID == PCI_INVALID_VENDORID) + if (!PCI_IS_VENDORID_VALID(vendorID)) { break; // skip to the next device } @@ -3421,76 +3481,25 @@ clPcieIsRelaxedOrderingSafe_IMPL return NV_OK; } -/** - * Compares two OBJGPUs to see if they are behind the same upstream bridge. - * Used for identifying GPUs behind the same lowest level BR04. - * - * @param[in] pGpu1 First gpu to compare - * @param[in] pGpu2 Second gpu to compare - * - * @return NV_TRUE if the two GPUs are behind the same bridge. - */ -NvBool -clAreGpusBehindSameBridge_IMPL -( - OBJCL *pCl, - OBJGPU *pGpu1, - OBJGPU *pGpu2 -) -{ - NV_ASSERT((pGpu1 != NULL) && - (pGpu2 != NULL)); - - if ((pGpu1->gpuClData.boardUpstreamPort.addr.valid) && - (pGpu2->gpuClData.boardUpstreamPort.addr.valid) && - (pGpu1->gpuClData.boardUpstreamPort.addr.domain - == pGpu2->gpuClData.boardUpstreamPort.addr.domain) && - (pGpu1->gpuClData.boardUpstreamPort.addr.bus - == pGpu2->gpuClData.boardUpstreamPort.addr.bus) && - (pGpu1->gpuClData.boardUpstreamPort.addr.device - == pGpu2->gpuClData.boardUpstreamPort.addr.device) && - (pGpu1->gpuClData.boardUpstreamPort.addr.func - == pGpu2->gpuClData.boardUpstreamPort.addr.func)) - { - return NV_TRUE; - } - - return NV_FALSE; -} - /*! * Pulls the devid info out of the pGpu to pass to gpuDevIdIsMultiGpuBoard(). * * @param[in] pGpu OBJGPU pointer - * @parma[out] pbIsGemini NvBool pointer in which to store whether GPU is a - * Gemini multiboard config. May be NULL if caller does - * not care to receive this information. * * @return NV_TRUE if the GPU is in a multigpu board, NV_FALSE otherwise */ NvBool gpuIsMultiGpuBoard ( - OBJGPU *pGpu, - NvBool *pbIsGemini + OBJGPU *pGpu ) { - if (pbIsGemini != NULL) - *pbIsGemini = NV_FALSE; - - if ((DRF_VAL(_PCI, _DEVID, _DEVICE, pGpu->idInfo.PCIDeviceID) == NV_PCI_DEVID_DEVICE_PG171_SKU200_PG179_SKU220) && - (DRF_VAL(_PCI, _SUBID, _DEVICE, pGpu->idInfo.PCISubDeviceID) == NV_PCI_SUBID_DEVICE_PG171_SKU200) && - (DRF_VAL(_PCI, _SUBID, _VENDOR, pGpu->idInfo.PCISubDeviceID) == NV_PCI_SUBID_VENDOR_NVIDIA)) - { - if (pbIsGemini != NULL) - *pbIsGemini = NV_TRUE; - - return NV_TRUE; - } - - return NV_FALSE; - + return pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_PLX_PRESENT) || + gpuDevIdIsMultiGpuBoard( + (NvU16) DRF_VAL(_PCI, _DEVID, _DEVICE, pGpu->idInfo.PCIDeviceID), + (NvU16) DRF_VAL(_PCI, _SUBID, _VENDOR, pGpu->idInfo.PCISubDeviceID), + (NvU16) DRF_VAL(_PCI, _SUBID, _DEVICE, pGpu->idInfo.PCISubDeviceID)); } /* diff --git a/src/nvidia/src/kernel/platform/cpu.c b/src/nvidia/src/kernel/platform/cpu.c index 7c30a5bd8..ce8854d26 100644 --- a/src/nvidia/src/kernel/platform/cpu.c +++ b/src/nvidia/src/kernel/platform/cpu.c @@ -183,9 +183,6 @@ void RmInitCpuInfo(void) case AARCH64_VENDOR_PART(ARM, CORTEX_A57): pSys->cpuInfo.type = NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC; break; - case AARCH64_VENDOR_PART(ARM, NEOVERSE_N2): - pSys->cpuInfo.type = NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV9A_GENERIC; - break; default: pSys->cpuInfo.type = NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC; portDbgPrintf( diff --git a/src/nvidia/src/kernel/platform/cpu_arm_def.h b/src/nvidia/src/kernel/platform/cpu_arm_def.h index 9c23b6726..dfa8da2a5 100644 --- a/src/nvidia/src/kernel/platform/cpu_arm_def.h +++ b/src/nvidia/src/kernel/platform/cpu_arm_def.h @@ -88,7 +88,6 @@ extern void CP_WRITE_CSSELR_REGISTER(NvU32 val); #define CP_MIDR_PRIMARY_PART_NUM_ALTRA 0x000 #define CP_MIDR_PRIMARY_PART_NUM_OCTEON_CN96XX 0x0b2 #define CP_MIDR_PRIMARY_PART_NUM_OCTEON_CN98XX 0x0b1 -#define CP_MIDR_PRIMARY_PART_NUM_NEOVERSE_N2 0xd49 // Cache Size Identification Register #define CP_CCSIDR "ccsidr_el1" diff --git a/src/nvidia/src/kernel/platform/hwbc.c b/src/nvidia/src/kernel/platform/hwbc.c index 9d2c29009..15b126363 100644 --- a/src/nvidia/src/kernel/platform/hwbc.c +++ b/src/nvidia/src/kernel/platform/hwbc.c @@ -744,7 +744,7 @@ objClSetupBR03 needRes[dev+1] = 1; total++; } else - if (!handle || vendorID == PCI_INVALID_VENDORID) + if (!handle || !PCI_IS_VENDORID_VALID(vendorID)) totalDevices--; } diff --git a/src/nvidia/src/kernel/platform/nbsi/nbsi_init.c b/src/nvidia/src/kernel/platform/nbsi/nbsi_init.c index ef16379f1..ad2ee912a 100644 --- a/src/nvidia/src/kernel/platform/nbsi/nbsi_init.c +++ b/src/nvidia/src/kernel/platform/nbsi/nbsi_init.c @@ -1346,27 +1346,32 @@ static NV_STATUS getNbsiObjFromCache // If we found it in cache... return it (if they have enough room) if (status == NV_OK) { + NvU32 rtnObjSizeWithOffset; + // return the full table size *pTotalObjSize = tempGlobSize; - // is rtnsize larger than remaining part of table? - if (*pRtnObjSize >= (*pTotalObjSize - rtnObjOffset)) + rtnObjSizeWithOffset = *pTotalObjSize - rtnObjOffset; { - // then we can return it all this time. - *pRtnObjSize = *pTotalObjSize - rtnObjOffset; - *globTypeRtnStatus = NV2080_CTRL_BIOS_GET_NBSI_SUCCESS; - } - else - { - // return what we can and indicate incomplete. - *globTypeRtnStatus = NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE; - } + if (*pRtnObjSize >= rtnObjSizeWithOffset) + { + // if rtnsize is larger than remaining part of table, + // then we can return it all this time. + *pRtnObjSize = rtnObjSizeWithOffset; + *globTypeRtnStatus = NV2080_CTRL_BIOS_GET_NBSI_SUCCESS; + } + else + { + // return what we can and indicate incomplete. + *globTypeRtnStatus = NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE; + } - if (*pRtnObjSize > 0) - { - bufPtr = (NvU8 *) pTempGlob; - bufPtr = &bufPtr[rtnObjOffset]; - portMemCopy(pRtnObj, *pRtnObjSize, bufPtr, *pRtnObjSize); + if (*pRtnObjSize > 0) + { + bufPtr = (NvU8 *) pTempGlob; + bufPtr = &bufPtr[rtnObjOffset]; + portMemCopy(pRtnObj, *pRtnObjSize, bufPtr, *pRtnObjSize); + } } } return status; @@ -1671,11 +1676,11 @@ static NV_STATUS nbsiObjTypeCallAcpi *(NvU32 *) inOutData = (globTypeWanted & 0xffff) << 16 | (curGlob & 0xf) << 12 | ((*sizeToRead/inOutDataSz) & 0xfff); - status = pGpu->pOS->osCallACPI_DSM(pGpu, - acpiFunction, - NV_ACPI_GENERIC_FUNC_GETOBJBYTYPE, - (NvU32 *)inOutData, - (NvU16 *)&acpiRtnSize); + status = osCallACPI_DSM(pGpu, + acpiFunction, + NV_ACPI_GENERIC_FUNC_GETOBJBYTYPE, + (NvU32 *)inOutData, + (NvU16 *)&acpiRtnSize); if ((acpiRtnSize == 0) || ((status == NV_OK) && @@ -2165,11 +2170,11 @@ static NV_STATUS getTableDataUsingAllObjectCall { // get page the data is in. *(NvU32 *) inOutData = curOffset / inOutDataSz; - status = pGpu->pOS->osCallACPI_DSM(pGpu, - acpiFunction, - NV_ACPI_GENERIC_FUNC_GETALLOBJS, - (NvU32 *)inOutData, - (NvU16 *)&rtnSize); + status = osCallACPI_DSM(pGpu, + acpiFunction, + NV_ACPI_GENERIC_FUNC_GETALLOBJS, + (NvU32 *)inOutData, + (NvU16 *)&rtnSize); if ((acpiRtnSize == 0) || ((status == NV_OK) && (acpiRtnSize==4) && @@ -2835,6 +2840,7 @@ NV_STATUS getNbsiObjByType if (globType == GLOB_TYPE_GET_NBSI_ACPI_RAW) { + // TODO: Add offset arg validation when ACPI calls get support from GSP firmware. NvU16 rtnSize; // // (IN) wantedRtnObjOffset = acpi function, @@ -2842,11 +2848,11 @@ NV_STATUS getNbsiObjByType // (IN/OUT) pSizeOfData In = size of inoutdata, Out = size returned // rtnSize = (NvU16) (*pRtnObjSize & 0xffff); - status = pGpu->pOS->osCallACPI_DSM(pGpu, - acpiFunction, - wantedRtnObjOffset, - (NvU32 *)pRtnObj, - (NvU16 *)&rtnSize); + status = osCallACPI_DSM(pGpu, + acpiFunction, + wantedRtnObjOffset, + (NvU32 *)pRtnObj, + (NvU16 *)&rtnSize); *pRtnObjSize = rtnSize; *pWantedGlobSource = (NBSI_SOURCE_LOC) status; @@ -3013,6 +3019,8 @@ NV_STATUS getNbsiObjByType if (bFound == NV_TRUE) { + NvU32 rtnObjSizeWithOffset; + // Currently only NBSI and NBCI objects are cached... if ((acpiFunction == ACPI_DSM_FUNCTION_NBSI) || (acpiFunction == ACPI_DSM_FUNCTION_NBCI)) @@ -3046,24 +3054,27 @@ NV_STATUS getNbsiObjByType // return the full table size *pTotalObjSize = testObjSize; - // is rtnsize larger than remaining part of table? - if (*pRtnObjSize >= (*pTotalObjSize - wantedRtnObjOffset)) + rtnObjSizeWithOffset = *pTotalObjSize - wantedRtnObjOffset; { - // then we can return it all this time. - *pRtnObjSize = *pTotalObjSize - wantedRtnObjOffset; - *pRtnGlobStatus = NV2080_CTRL_BIOS_GET_NBSI_SUCCESS; - } - else - { - // return what we can and indicate incomplete. - *pRtnGlobStatus = NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE; - } + if (*pRtnObjSize >= rtnObjSizeWithOffset) + { + // if rtnsize is larger than remaining part of table, + // then we can return it all this time. + *pRtnObjSize = rtnObjSizeWithOffset; + *pRtnGlobStatus = NV2080_CTRL_BIOS_GET_NBSI_SUCCESS; + } + else + { + // return what we can and indicate incomplete. + *pRtnGlobStatus = NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE; + } - if (*pRtnObjSize > 0) - { - bufPtr = (NvU8 *) pTestObj; - bufPtr = &bufPtr[wantedRtnObjOffset]; - portMemCopy(pRtnObj, *pRtnObjSize, bufPtr, *pRtnObjSize); + if (*pRtnObjSize > 0) + { + bufPtr = (NvU8 *) pTestObj; + bufPtr = &bufPtr[wantedRtnObjOffset]; + portMemCopy(pRtnObj, *pRtnObjSize, bufPtr, *pRtnObjSize); + } } } else diff --git a/src/nvidia/src/kernel/platform/p2p/p2p_caps.c b/src/nvidia/src/kernel/platform/p2p/p2p_caps.c index 4f703c109..2b9e7d410 100644 --- a/src/nvidia/src/kernel/platform/p2p/p2p_caps.c +++ b/src/nvidia/src/kernel/platform/p2p/p2p_caps.c @@ -943,7 +943,7 @@ subdeviceGetP2pCaps_VIRTUAL for (i = 0; i < pShimParams->peerGpuCount; i++) { NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO *pParamsPeerInfo = &pShimParams->peerGpuCaps[i]; - POBJGPU pRemoteGpu = gpumgrGetGpuFromId(pParamsPeerInfo->gpuId); + OBJGPU *pRemoteGpu = gpumgrGetGpuFromId(pParamsPeerInfo->gpuId); NV_CHECK_OR_ELSE(LEVEL_INFO, pRemoteGpu != NULL, status = NV_ERR_INVALID_ARGUMENT; goto done); diff --git a/src/nvidia/src/kernel/platform/sli/sli.c b/src/nvidia/src/kernel/platform/sli/sli.c new file mode 100644 index 000000000..3cd89ef39 --- /dev/null +++ b/src/nvidia/src/kernel/platform/sli/sli.c @@ -0,0 +1,287 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/******************* SLI Routines ******************************************\ +* SLI support * +****************************************************************************/ + +#include "core/core.h" +#include "gpu/gpu.h" +#include "gpu_mgr/gpu_mgr.h" +#include "kernel/gpu/nvlink/kernel_nvlink.h" +#include "nvpcie.h" +#include "os/os.h" +#include "platform/chipset/chipset.h" +#include "platform/platform.h" +#include "platform/sli/sli.h" +#include "gpu_mgr/gpu_mgr_sli.h" + +// Return smallest integer greater than mask with the same number of bits set. +static NvU32 rmSliNextMask(NvU32 mask) +{ + NvU32 r, l; + + r = mask & -(NvS32)mask; // lowest set bit + + mask += r; // replace lowest block by a one left to it + + l = mask & -(NvS32)mask;// first zero beyond lowest block + + l -= r; // lowest block + + while ( 0==(l&1) ) { l >>= 1; } // move block to low end of word + + return mask | (l>>1); // need one bit less of low block +} + +// rmSliSearchForSliCombination +// +// This function looks for all the nWay-SLI configurations with this +// GPU. It as all the valid and non-valid SLI configurations with +// their status. It returns the gpu specfic statuses, and the number +// of valid configs found. +// +static NV_INLINE NvU32 +rmSliSearchForSliCombination(OBJGPU *pGpu, NvU32 nWay, NvU32 numFoundValidConfigs, NvU32 *pGpuSliStatus) +{ + NvU32 gpuAttachCnt; + NvU32 gpuAttachMask; + NvU32 gpuMask; + NvU32 numValidConfigs = 0; + NvU32 mask; + NvU32 smallestMask; + NvU32 largestMask; + NvU32 bit; + NvU32 firstBit = ~0; + NvU32 lastBit = ~0; + NvBool bSliLinkCircular = NV_FALSE; + NvU32 sliLinkTestDone = 0; + NvU32 sliLinkOutputMask = 0; + NvU32 sliLinkEndsMask = 0; + NvU32 vidLinkCount = 0; + NvBool bAnyValid = NV_FALSE; + + // get gpu attach info + gpumgrGetGpuAttachInfo(&gpuAttachCnt, &gpuAttachMask); + + // return if we have less gpus than we request for + if (gpuAttachCnt < nWay) + { + numValidConfigs = 0; + goto rmSliSearchForSliCombination_exit; + } + + gpuAttachMask &= ~NVBIT(pGpu->gpuInstance); + + mask = gpuAttachMask; + // Get the first bit and the last bit set in the 32-bit mask. + for (bit = 0; mask; bit++) + { + if ((firstBit == (NvU32)~0) && (mask & 1)) + { + firstBit = lastBit = bit; + } + else if (mask & 1) + { + lastBit = bit; + } + mask >>= 1; + } + + NV_ASSERT(firstBit != (NvU32)~0); + NV_ASSERT(lastBit != (NvU32)~0); + + if ((firstBit == (NvU32)~0) || (lastBit == (NvU32)~0)) + { + numValidConfigs = 0; + goto rmSliSearchForSliCombination_exit; + } + + smallestMask = ((1 << ((nWay - 1) + firstBit)) - 1) & ~((1 << firstBit) - 1); + largestMask = smallestMask << (lastBit - firstBit - (nWay - 1) + 1); + mask = smallestMask; + + // Search for n-way configs with this gpu. + do + { + + // Look for a mask contained in the GPU mask, + if ((mask & gpuAttachMask) != mask) + { + // Last mask. Exit loop. + if (mask == largestMask) + { + break; + } + mask = rmSliNextMask(mask); + NV_ASSERT(mask); + continue; + } + + gpuMask = NVBIT(pGpu->gpuInstance) | mask; + + // Do Sli link detection + gpumgrDetectSliLinkFromGpus(NV_TRUE, nWay, gpuMask, + &sliLinkTestDone, + &sliLinkOutputMask, + &bSliLinkCircular, + &sliLinkEndsMask, + &vidLinkCount); + + // Last mask. Exit loop. + if (mask == largestMask) + { + break; + } + + mask = rmSliNextMask(mask); + NV_ASSERT(mask); + } while (1); + + if ((numValidConfigs == 0) && bAnyValid) + { + *pGpuSliStatus = NV0000_CTRL_SLI_STATUS_OK; + } + +rmSliSearchForSliCombination_exit: + + return numValidConfigs; +} + +// +// +// RmRunSLISupportCheck +// +// This function establishes the SLI possibilities for the specified GPU. +// The GPU is tested with each previously attached GPU to determine the +// set of valid SLI configurations to which it belongs. +// +static NvU32 RmRunSLISupportCheck +( + OBJGPU *pGpu +) +{ + NvU32 gpuSliStatus = NV0000_CTRL_SLI_STATUS_OK; + NvU32 gpuAttachCnt; + NvU32 gpuAttachMask; + NvU32 numValidConfigs = 0; + NvU32 numXWayValidConfigs; + NvU32 nWay = 0; + + // RMCONFIG: is SLI enabled in this build? + + if (IS_VIRTUAL(pGpu) || IS_GSP_CLIENT(pGpu)) + { + gpuSliStatus |= NV0000_CTRL_SLI_STATUS_GPU_NOT_SUPPORTED; + + // Detect SLI link before failing on GSP client RM + if (!IS_GSP_CLIENT(pGpu)) + goto done; + } + + // get gpu attach info + gpumgrGetGpuAttachInfo(&gpuAttachCnt, &gpuAttachMask); + + // Need more than one gpu to continue. + if (gpuAttachCnt <= 1) + { + // Do not cache this status in pGpu->sliStatus as it is dependent on the GPU count + gpuSliStatus |= NV0000_CTRL_SLI_STATUS_INVALID_GPU_COUNT; + goto done; + } + + // For 9 GPUs and above, we do not check the SLI configs + if(gpuAttachCnt <= 8) + { + for(nWay=2; nWay<=gpuAttachCnt; nWay++) + { + numXWayValidConfigs = rmSliSearchForSliCombination(pGpu, nWay, numValidConfigs, &gpuSliStatus); + numValidConfigs += numXWayValidConfigs; + } + + // + // Cache the gpu status in pGpu->sliStatus in case it has been cleared + // + // NOTE: rmSliSearchForSliCombination() clears gpuSliStatus in case of Base Mosaic and + // Base Mosaic also requires gpu specific slistatus to be OK. Hence gpuSlistatus + // is assigned to gpu specific status again. + // + if (gpuSliStatus == NV0000_CTRL_SLI_STATUS_OK) + { + pGpu->sliStatus = gpuSliStatus; + } + } +done: + NV_PRINTF(LEVEL_INFO, "gpuSliStatus 0x%x\n", gpuSliStatus); + + return numValidConfigs; +} + +// +// +// RmInitScalability +// +// This function calls to establish the SLI possibilities for the specified GPU. +// Then it initalizes any additional SLI attributes. +// +void RmInitScalability +( + OBJGPU *pGpu +) +{ + NvU32 numValidConfigs; + NvU32 gpuMask; + NvU32 idx = 0; + NvU32 gpuLockMask = 0; + + if (IS_GSP_CLIENT(pGpu) && !rmDeviceGpuLockIsOwner(pGpu->gpuInstance)) + NV_ASSERT_OR_RETURN_VOID(rmGpuGroupLockAcquire(pGpu->gpuInstance, + GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_RPC, + &gpuLockMask) == NV_OK); + + // determine the supported SLI configurations. + numValidConfigs = RmRunSLISupportCheck(pGpu); + + if (0 < numValidConfigs) + { + gpuMask = gpumgrGetVidLinkOutputMaskFromGpu(pGpu); + while ((pGpu = gpumgrGetNextGpu(gpuMask, &idx)) != NULL) + { + gpuInitSliIllumination(pGpu); + } + } + + if (gpuLockMask != 0) + rmGpuGroupLockRelease(gpuLockMask, GPUS_LOCK_FLAGS_NONE); +} + + +NV_STATUS RmShutdownScalability +( + OBJGPU *pGpu +) +{ + return NV_OK; +} diff --git a/src/nvidia/src/kernel/rmapi/alloc_free.c b/src/nvidia/src/kernel/rmapi/alloc_free.c index 58c150119..1d2e0913d 100644 --- a/src/nvidia/src/kernel/rmapi/alloc_free.c +++ b/src/nvidia/src/kernel/rmapi/alloc_free.c @@ -31,6 +31,7 @@ #include "gpu/disp/disp_objs.h" #include "gpu/disp/disp_channel.h" #include "nvsecurityinfo.h" +#include "virtualization/hypervisor/hypervisor.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" @@ -278,6 +279,9 @@ serverTopLock_Prologue if (access == LOCK_ACCESS_READ) flags |= RMAPI_LOCK_FLAGS_READ; + if (pLockInfo->flags & RS_LOCK_FLAGS_LOW_PRIORITY) + flags |= RMAPI_LOCK_FLAGS_LOW_PRIORITY; + if ((status = rmapiLockAcquire(flags, RM_LOCK_MODULES_CLIENT)) != NV_OK) { return status; @@ -616,6 +620,61 @@ _fixupAllocParams return NV_OK; } +static +NV_STATUS +_serverAllocValidatePrivilege +( + RS_RESOURCE_DESC *pResDesc, + RS_RES_ALLOC_PARAMS *pParams +) +{ + if (hypervisorIsVgxHyper()) + { + // Host CPU-RM context + // Don't check here, allow it to pass to the inline constructor check. + // TODO: GPUSWSEC-1552 Hypervisor + } + else + { + RS_PRIV_LEVEL privLevel = pParams->pSecInfo->privLevel; + + // Reject allocations for objects with no flags. + if (!(pResDesc->flags & RS_FLAGS_ALLOC_NON_PRIVILEGED) && + !(pResDesc->flags & RS_FLAGS_ALLOC_PRIVILEGED) && + !(pResDesc->flags & RS_FLAGS_ALLOC_KERNEL_PRIVILEGED)) + { + // See GPUSWSEC-1560 for more details on privilege flag requirements + NV_PRINTF(LEVEL_WARNING, "external class 0x%08x is missing its privilege flag in RS_ENTRY\n", pParams->externalClassId); + return NV_ERR_INSUFFICIENT_PERMISSIONS; + } + + // Default case, verify admin and kernel privileges + if (pResDesc->flags & RS_FLAGS_ALLOC_PRIVILEGED) + { + if (privLevel < RS_PRIV_LEVEL_USER_ROOT) + { + NV_PRINTF(LEVEL_WARNING, + "hClient: 0x%08x, externalClassId: 0x%08x: non-privileged context tried to allocate privileged object\n", + pParams->hClient, pParams->externalClassId); + return NV_ERR_INSUFFICIENT_PERMISSIONS; + } + } + + if (pResDesc->flags & RS_FLAGS_ALLOC_KERNEL_PRIVILEGED) + { + if (privLevel < RS_PRIV_LEVEL_KERNEL) + { + NV_PRINTF(LEVEL_WARNING, + "hClient: 0x%08x, externalClassId: 0x%08x: non-privileged context tried to allocate kernel privileged object\n", + pParams->hClient, pParams->externalClassId); + return NV_ERR_INSUFFICIENT_PERMISSIONS; + } + } + } + + return NV_OK; +} + NV_STATUS serverAllocResourceUnderLock ( @@ -656,6 +715,10 @@ serverAllocResourceUnderLock NV_ASSERT_OK_OR_RETURN(_fixupAllocParams(&pResDesc, pRmAllocParams)); rmapiResourceDescToLegacyFlags(pResDesc, &pLockInfo->flags, NULL); + status = _serverAllocValidatePrivilege(pResDesc, pRmAllocParams); + if (status != NV_OK) + goto done; + pLockInfo->traceOp = RS_LOCK_TRACE_ALLOC; pLockInfo->traceClassId = pRmAllocParams->externalClassId; hParent = pRmAllocParams->hParent; @@ -1392,7 +1455,7 @@ rmapiFreeWithSecInfoTls } NV_STATUS -rmapiFreeClientList +rmapiDisableClients ( RM_API *pRmApi, NvHandle *phClientList, @@ -1402,11 +1465,11 @@ rmapiFreeClientList if (!pRmApi->bHasDefaultSecInfo) return NV_ERR_NOT_SUPPORTED; - return pRmApi->FreeClientListWithSecInfo(pRmApi, phClientList, numClients, &pRmApi->defaultSecInfo); + return pRmApi->DisableClientsWithSecInfo(pRmApi, phClientList, numClients, &pRmApi->defaultSecInfo); } NV_STATUS -rmapiFreeClientListWithSecInfo +rmapiDisableClientsWithSecInfo ( RM_API *pRmApi, NvHandle *phClientList, @@ -1414,12 +1477,11 @@ rmapiFreeClientListWithSecInfo API_SECURITY_INFO *pSecInfo ) { - NV_STATUS status; OBJSYS *pSys = SYS_GET_INSTANCE(); NvU32 lockState = 0; NvU32 i; - NV_PRINTF(LEVEL_INFO, "Nv01FreeClientList: numClients: %d\n", numClients); + NV_PRINTF(LEVEL_INFO, "numClients: %d\n", numClients); if (!pRmApi->bRmSemaInternal && osAcquireRmSema(pSys->pSema) != NV_OK) return NV_ERR_INVALID_LOCK_STATE; @@ -1433,27 +1495,18 @@ rmapiFreeClientListWithSecInfo for (i = 0; i < numClients; ++i) rmapiControlCacheFreeClientEntry(phClientList[i]); - status = serverFreeClientList(&g_resServ, phClientList, numClients, lockState, pSecInfo); + serverMarkClientListDisabled(&g_resServ, phClientList, numClients, lockState, pSecInfo); if (!pRmApi->bRmSemaInternal) osReleaseRmSema(pSys->pSema, NULL); - if (status == NV_OK) - { - NV_PRINTF(LEVEL_INFO, "Nv01FreeClientList: free complete\n"); - } - else - { - NV_PRINTF(LEVEL_WARNING, - "Nv01FreeList: free failed; status: %s (0x%08x)\n", - nvstatusToString(status), status); - } + NV_PRINTF(LEVEL_INFO, "Disable clients complete\n"); - return status; + return NV_OK; } NV_STATUS -rmapiFreeClientListWithSecInfoTls +rmapiDisableClientsWithSecInfoTls ( RM_API *pRmApi, NvHandle *phClientList, @@ -1466,7 +1519,7 @@ rmapiFreeClientListWithSecInfoTls threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); - status = rmapiFreeClientListWithSecInfo(pRmApi, phClientList, numClients, pSecInfo); + status = rmapiDisableClientsWithSecInfo(pRmApi, phClientList, numClients, pSecInfo); threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); diff --git a/src/nvidia/src/kernel/rmapi/client.c b/src/nvidia/src/kernel/rmapi/client.c index ea4e70082..88b34609c 100644 --- a/src/nvidia/src/kernel/rmapi/client.c +++ b/src/nvidia/src/kernel/rmapi/client.c @@ -169,7 +169,7 @@ rmclientConstruct_IMPL PUID_TOKEN pUidToken = osGetCurrentUidToken(); UserInfo *pUserInfo = NULL; - if (RMCFG_FEATURE_PLATFORM_GSP && IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + if (RMCFG_FEATURE_PLATFORM_GSP) { pClient->pSecurityToken = pSecurityToken; } diff --git a/src/nvidia/src/kernel/rmapi/client_resource.c b/src/nvidia/src/kernel/rmapi/client_resource.c index 940412b95..2d55a722b 100644 --- a/src/nvidia/src/kernel/rmapi/client_resource.c +++ b/src/nvidia/src/kernel/rmapi/client_resource.c @@ -210,6 +210,31 @@ cliresShareCallback_IMPL return resShareCallback_IMPL(staticCast(pRmCliRes, RsResource), pInvokingClient, pParentRef, pSharePolicy); } +NV_STATUS +cliresControl_Prologue_IMPL +( + RmClientResource *pRmCliRes, + CALL_CONTEXT *pCallContext, + RS_RES_CONTROL_PARAMS_INTERNAL *pParams +) +{ + NV_STATUS status = serverDeserializeCtrlDown(pCallContext, pParams->cmd, pParams->pParams, pParams->paramsSize, &pParams->flags); + + return status; +} + +void +cliresControl_Epilogue_IMPL +( + RmClientResource *pRmCliRes, + CALL_CONTEXT *pCallContext, + RS_RES_CONTROL_PARAMS_INTERNAL *pParams +) +{ + NV_ASSERT_OK(serverSerializeCtrlUp(pCallContext, pParams->cmd, pParams->pParams, pParams->paramsSize, &pParams->flags)); + serverFreeSerializeStructures(pCallContext, pParams->pParams); +} + // **************************************************************************** // Helper functions // **************************************************************************** @@ -819,15 +844,12 @@ cliresCtrlCmdSystemExecuteAcpiMethod_IMPL NvBool bDoCopyOut = NV_FALSE; void* pInOutData = NULL; NV_STATUS status = NV_OK; - OBJOS *pOS = NULL; pGpu = gpumgrGetSomeGpu(); if (pGpu == NULL) { return NV_ERR_INVALID_REQUEST; } - pOS = GPU_GET_OS(pGpu); - inDataSize = pAcpiMethodParams->inDataSize; outDataSize = pAcpiMethodParams->outDataSize; inOutDataSize = (NvU32) NV_MAX(inDataSize, outDataSize); @@ -865,38 +887,38 @@ cliresCtrlCmdSystemExecuteAcpiMethod_IMPL { case NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS: { - outStatus = pOS->osCallACPI_DSM(pGpu, - ACPI_DSM_FUNCTION_NVOP, - NVOP_FUNC_OPTIMUSCAPS, - (NvU32*) pInOutData, - &outDataSize); + outStatus = osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_NVOP, + NVOP_FUNC_OPTIMUSCAPS, + (NvU32*) pInOutData, + &outDataSize); break; } case NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG: { - outStatus = pOS->osCallACPI_DSM(pGpu, - ACPI_DSM_FUNCTION_NVOP, - NVOP_FUNC_OPTIMUSFLAG, - (NvU32*) pInOutData, - (NvU16*) &outDataSize); + outStatus = osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_NVOP, + NVOP_FUNC_OPTIMUSFLAG, + (NvU32*) pInOutData, + (NvU16*) &outDataSize); break; } case NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS: { - outStatus = pOS->osCallACPI_DSM(pGpu, - ACPI_DSM_FUNCTION_JT, - JT_FUNC_CAPS, - (NvU32*) pInOutData, - (NvU16*) &outDataSize); + outStatus = osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_JT, + JT_FUNC_CAPS, + (NvU32*) pInOutData, + (NvU16*) &outDataSize); break; } case NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY: { - outStatus = pOS->osCallACPI_DSM(pGpu, - ACPI_DSM_FUNCTION_JT, - JT_FUNC_PLATPOLICY, - (NvU32*) pInOutData, - (NvU16*) &outDataSize); + outStatus = osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_JT, + JT_FUNC_PLATPOLICY, + (NvU32*) pInOutData, + (NvU16*) &outDataSize); break; } default: @@ -2500,8 +2522,6 @@ cliresCtrlCmdSystemNVPCFGetPowerModeInfo_IMPL NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS *pParams ) { - OBJSYS *pSys = NULL; - OBJOS *pOS = NULL; NvU32 rc = NV_OK; OBJGPU *pGpu = NULL; NV_STATUS status = NV_OK; @@ -2514,20 +2534,6 @@ cliresCtrlCmdSystemNVPCFGetPowerModeInfo_IMPL return NV_ERR_INVALID_REQUEST; } - pSys = SYS_GET_INSTANCE(); - if (pSys == NULL) - { - NV_ASSERT(pSys); - return NV_ERR_INVALID_REQUEST; - } - - pOS = SYS_GET_OS(pSys); - if (pOS == NULL) - { - NV_ASSERT(pOS); - return NV_ERR_INVALID_REQUEST; - } - pGpu = gpumgrGetGpuFromId(pParams->gpuId); if (pGpu == NULL) @@ -2547,11 +2553,11 @@ cliresCtrlCmdSystemNVPCFGetPowerModeInfo_IMPL NvU32 supportedFuncs; dsmDataSize = sizeof(supportedFuncs); - if ((rc = pOS->osCallACPI_DSM(pGpu, - acpiDsmFunction, - acpiDsmSubFunction, - &supportedFuncs, - &dsmDataSize)) != NV_OK) + if ((rc = osCallACPI_DSM(pGpu, + acpiDsmFunction, + acpiDsmSubFunction, + &supportedFuncs, + &dsmDataSize)) != NV_OK) { NV_PRINTF(LEVEL_WARNING, "Unable to retrieve NVPCF supported functions. Possibly not supported by SBIOS " @@ -2587,11 +2593,11 @@ cliresCtrlCmdSystemNVPCFGetPowerModeInfo_IMPL dynamicTable_1x.entries[0] = NVPCF0100_CTRL_DYNAMIC_TABLE_1X_INPUT_CMD_GET_TPP; dsmDataSize = sizeof(dynamicTable_1x); - if ((rc = pOS->osCallACPI_DSM(pGpu, - ACPI_DSM_FUNCTION_NVPCF, - NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS, - (NvU32*)(&dynamicTable_1x), - &dsmDataSize)) != NV_OK) + if ((rc = osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_NVPCF, + NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS, + (NvU32*)(&dynamicTable_1x), + &dsmDataSize)) != NV_OK) { NV_PRINTF(LEVEL_WARNING, "Unable to retrieve NVPCF dynamic data. Possibly not supported by SBIOS " @@ -2633,7 +2639,7 @@ cliresCtrlCmdSystemNVPCFGetPowerModeInfo_IMPL portMemCopy(pData + sizeof(header), sizeof(common), &common, sizeof(common)); portMemCopy(pData + sizeof(header) + sizeof(common), sizeof(entries), entries, sizeof(entries)); - if ((rc = pOS->osCallACPI_DSM(pGpu, + if ((rc = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVPCF_2X, NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_PARAMS, (NvU32 *)pData, @@ -2737,7 +2743,7 @@ nvpcf2xGetDynamicParams_exit: pData = portMemAllocNonPaged(dataSize); - if ((rc = pOS->osCallACPI_DSM(pGpu, + if ((rc = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVPCF_2X, NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CONFIG_TABLES, (NvU32 *)pData, @@ -3151,6 +3157,7 @@ cliresCtrlCmdSystemGetP2pCapsV2_IMPL ) { OBJGPU *pGpu; + NvBool bLoopback = pP2PParams->gpuCount == 2 && pP2PParams->gpuIds[0] == pP2PParams->gpuIds[1]; if (RMCFG_FEATURE_PLATFORM_GSP) { @@ -3171,7 +3178,7 @@ cliresCtrlCmdSystemGetP2pCapsV2_IMPL } return CliGetSystemP2pCaps(pP2PParams->gpuIds, - pP2PParams->gpuCount, + bLoopback ? 1 : pP2PParams->gpuCount, &pP2PParams->p2pCaps, &pP2PParams->p2pOptimalReadCEs, &pP2PParams->p2pOptimalWriteCEs, @@ -4141,6 +4148,27 @@ cliresCtrlCmdGpuDisableNvlinkInit_IMPL return gpumgrSetGpuInitDisabledNvlinks(pParams->gpuId, pParams->mask, pParams->bSkipHwNvlinkDisable); } +NV_STATUS +cliresCtrlCmdGpuSetNvlinkBwMode_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS *pParams +) +{ + return gpumgrSetGpuNvlinkBwMode(pParams->mode); +} + +NV_STATUS +cliresCtrlCmdGpuGetNvlinkBwMode_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS *pParams +) +{ + pParams->mode = gpumgrGetGpuNvlinkBwMode(); + return NV_OK; +} + /*! * @brief Get Rcerr Rpt. Returns an Rc Error report form the circular buffer. * diff --git a/src/nvidia/src/kernel/rmapi/client_resource_sli.c b/src/nvidia/src/kernel/rmapi/client_resource_sli.c new file mode 100644 index 000000000..d2b573d07 --- /dev/null +++ b/src/nvidia/src/kernel/rmapi/client_resource_sli.c @@ -0,0 +1,52 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "core/core.h" +#include "core/locks.h" +#include "rmapi/client_resource.h" + +#include "platform/sli/sli.h" +#include "resserv/rs_client.h" +#include "resserv/rs_server.h" +#include "resserv/rs_access_map.h" + +#include "ctrl/ctrl0000/ctrl0000gpu.h" + +// +// cliresCtrlCmdGpuGetVideoLinks +// +// Lock Requirements: +// Assert that API lock held on entry +// No GPUs lock +// +NV_STATUS +cliresCtrlCmdGpuGetVideoLinks_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS *pParams +) +{ + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); + + return gpumgrGetSliLinks(pParams); +} diff --git a/src/nvidia/src/kernel/rmapi/control.c b/src/nvidia/src/kernel/rmapi/control.c index 10ab2f8ab..c22d5c6b7 100644 --- a/src/nvidia/src/kernel/rmapi/control.c +++ b/src/nvidia/src/kernel/rmapi/control.c @@ -262,8 +262,11 @@ serverControlApiCopyIn RMAPI_PARAM_COPY_INIT(*pParamCopy, pRmCtrlParams->pParams, pUserParams, 1, paramsSize); - if (pCookie->apiCopyFlags & RMCTRL_API_COPY_FLAGS_SKIP_COPYIN) + if (pCookie->apiCopyFlags & RMCTRL_API_COPY_FLAGS_SKIP_COPYIN_ZERO_BUFFER) + { pParamCopy->flags |= RMAPI_PARAM_COPY_FLAGS_SKIP_COPYIN; + pParamCopy->flags |= RMAPI_PARAM_COPY_FLAGS_ZERO_BUFFER; + } rmStatus = rmapiParamsAcquire(pParamCopy, (pRmCtrlParams->secInfo.paramLocation == PARAM_LOCATION_USER)); if (rmStatus != NV_OK) @@ -396,6 +399,9 @@ _rmapiRmControl(NvHandle hClient, NvHandle hObject, NvU32 cmd, NvP64 pUserParams NvBool bInternalRequest; NV_STATUS rmStatus = NV_OK; RS_LOCK_INFO lockInfo = {0}; + NvU32 ctrlFlags = 0; + NvU32 ctrlAccessRight = 0; + NV_STATUS getCtrlInfoStatus; RMTRACE_RMAPI(_RMCTRL_ENTRY, cmd); @@ -514,6 +520,18 @@ _rmapiRmControl(NvHandle hClient, NvHandle hObject, NvU32 cmd, NvP64 pUserParams lockInfo.flags |= RM_LOCK_FLAGS_NO_API_LOCK; } + getCtrlInfoStatus = rmapiutilGetControlInfo(cmd, &ctrlFlags, &ctrlAccessRight); + if (getCtrlInfoStatus == NV_OK) + { + // + // The output of CACHEABLE RMCTRL do not depend on the input. + // Skip param copy and clear the buffer in case the uninitialized + // buffer leaks information to clients. + // + if (ctrlFlags & RMCTRL_FLAGS_CACHEABLE) + rmCtrlParams.pCookie->apiCopyFlags |= RMCTRL_API_COPY_FLAGS_SKIP_COPYIN_ZERO_BUFFER; + } + // // Three separate rmctrl command modes: // @@ -574,24 +592,30 @@ _rmapiRmControl(NvHandle hClient, NvHandle hObject, NvU32 cmd, NvP64 pUserParams // Normal rmctrl request. // - if (rmapiCmdIsCacheable(cmd, NV_FALSE)) + if (getCtrlInfoStatus == NV_OK) { - rmCtrlParams.pCookie->apiCopyFlags |= RMCTRL_API_COPY_FLAGS_SKIP_COPYIN; - rmCtrlParams.pCookie->apiCopyFlags |= RMCTRL_API_COPY_FLAGS_FORCE_SKIP_COPYOUT_ON_ERROR; - - serverControlApiCopyIn(&g_resServ, &rmCtrlParams, rmCtrlParams.pCookie); - rmStatus = rmapiControlCacheGet(hClient, hObject, cmd, rmCtrlParams.pParams, paramsSize); - serverControlApiCopyOut(&g_resServ, &rmCtrlParams, rmCtrlParams.pCookie, rmStatus); - - if (rmStatus == NV_OK) + if (rmapiControlIsCacheable(ctrlFlags, ctrlAccessRight, NV_FALSE)) { - goto done; - } - else - { - // reset cookie if cache get failed - portMemSet(rmCtrlParams.pCookie, 0, sizeof(RS_CONTROL_COOKIE)); - rmCtrlParams.pCookie->apiCopyFlags |= RMCTRL_API_COPY_FLAGS_SET_CONTROL_CACHE; + rmCtrlParams.pCookie->apiCopyFlags |= RMCTRL_API_COPY_FLAGS_FORCE_SKIP_COPYOUT_ON_ERROR; + + serverControlApiCopyIn(&g_resServ, &rmCtrlParams, rmCtrlParams.pCookie); + rmStatus = rmapiControlCacheGet(hClient, hObject, cmd, rmCtrlParams.pParams, paramsSize); + serverControlApiCopyOut(&g_resServ, &rmCtrlParams, rmCtrlParams.pCookie, rmStatus); + + if (rmStatus == NV_OK) + { + goto done; + } + else + { + // reset cookie if cache get failed + portMemSet(rmCtrlParams.pCookie, 0, sizeof(RS_CONTROL_COOKIE)); + rmCtrlParams.pCookie->apiCopyFlags |= RMCTRL_API_COPY_FLAGS_SET_CONTROL_CACHE; + + // re-initialize the flag if it's cleaned + if (ctrlFlags & RMCTRL_FLAGS_CACHEABLE) + rmCtrlParams.pCookie->apiCopyFlags |= RMCTRL_API_COPY_FLAGS_SKIP_COPYIN_ZERO_BUFFER; + } } } @@ -662,12 +686,6 @@ NV_STATUS serverControl_ValidateCookie OBJGPU *pGpu; CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); - if (pCallContext == NULL) - { - NV_PRINTF(LEVEL_ERROR, "Calling context is NULL!\n"); - return NV_ERR_INVALID_PARAMETER; - } - if (RMCFG_FEATURE_PLATFORM_GSP) { pGpu = gpumgrGetSomeGpu(); @@ -856,7 +874,7 @@ serverControlLookupLockFlags return NV_OK; } - if (pRmCtrlExecuteCookie->ctrlFlags & RMCTRL_FLAGS_API_LOCK_READONLY) + if (controlFlags & RMCTRL_FLAGS_API_LOCK_READONLY) { *pAccess = LOCK_ACCESS_READ; } @@ -883,7 +901,7 @@ serverControlLookupLockFlags // we already own the GPUs Lock. // if ((pLockInfo->state & RM_LOCK_STATES_GPUS_LOCK_ACQUIRED) || - (pRmCtrlExecuteCookie->ctrlFlags & RMCTRL_FLAGS_NO_GPUS_LOCK) || + (controlFlags & RMCTRL_FLAGS_NO_GPUS_LOCK) || (pRmCtrlParams->flags & NVOS54_FLAGS_IRQL_RAISED) || (pRmCtrlParams->flags & NVOS54_FLAGS_LOCK_BYPASS)) { @@ -892,7 +910,7 @@ serverControlLookupLockFlags } else { - if ((pRmCtrlExecuteCookie->ctrlFlags & RMCTRL_FLAGS_GPU_LOCK_DEVICE_ONLY) || + if ((controlFlags & RMCTRL_FLAGS_GPU_LOCK_DEVICE_ONLY) || (g_resServ.bRouteToPhysicalLockBypass && bUseGspLockingMode)) { pLockInfo->flags |= RM_LOCK_FLAGS_NO_GPUS_LOCK; @@ -904,7 +922,7 @@ serverControlLookupLockFlags pLockInfo->flags &= ~RM_LOCK_FLAGS_GPU_GROUP_LOCK; } - if (pRmCtrlExecuteCookie->ctrlFlags & RMCTRL_FLAGS_GPU_LOCK_READONLY) + if (controlFlags & RMCTRL_FLAGS_GPU_LOCK_READONLY) *pAccess = LOCK_ACCESS_READ; } diff --git a/src/nvidia/src/kernel/rmapi/embedded_param_copy.c b/src/nvidia/src/kernel/rmapi/embedded_param_copy.c index 2d9c200e6..695ee517d 100644 --- a/src/nvidia/src/kernel/rmapi/embedded_param_copy.c +++ b/src/nvidia/src/kernel/rmapi/embedded_param_copy.c @@ -218,7 +218,8 @@ NV_STATUS embeddedParamCopyIn(RMAPI_PARAM_COPY *paramCopies, RmCtrlParams *pRmCt NvU32 paramsCnt = 1; NvU32 i, j = 0; - if (pRmCtrlParams->secInfo.paramLocation == PARAM_LOCATION_KERNEL) + if ((pRmCtrlParams->secInfo.paramLocation == PARAM_LOCATION_KERNEL) || + (pRmCtrlParams->flags & NVOS54_FLAGS_FINN_SERIALIZED)) { return NV_OK; } @@ -334,6 +335,27 @@ NV_STATUS embeddedParamCopyIn(RMAPI_PARAM_COPY *paramCopies, RmCtrlParams *pRmCt break; } + case NV0073_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD: + { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS); + + RMAPI_PARAM_COPY_INIT(paramCopies[0], + ((NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS*)pParams)->inData, + ((NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS*)pParams)->inData, + ((NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS*)pParams)->inDataSize, 1); + paramCopies[0].flags |= RMAPI_PARAM_COPY_FLAGS_SKIP_COPYOUT; + + RMAPI_PARAM_COPY_INIT(paramCopies[1], + ((NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS*)pParams)->outData, + ((NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS*)pParams)->outData, + ((NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS*)pParams)->outDataSize, 1); + paramCopies[1].flags |= RMAPI_PARAM_COPY_FLAGS_SKIP_COPYIN; + paramCopies[1].flags |= RMAPI_PARAM_COPY_FLAGS_ZERO_BUFFER; + + paramsCnt++; + + break; + } case NV0080_CTRL_CMD_HOST_GET_CAPS: { CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV0080_CTRL_HOST_GET_CAPS_PARAMS); @@ -744,7 +766,8 @@ NV_STATUS embeddedParamCopyOut(RMAPI_PARAM_COPY *paramCopies, RmCtrlParams *pRmC NV_STATUS status = NV_OK; void* pParams = pRmCtrlParams->pParams; - if (pRmCtrlParams->secInfo.paramLocation == PARAM_LOCATION_KERNEL) + if ((pRmCtrlParams->secInfo.paramLocation == PARAM_LOCATION_KERNEL) || + (pRmCtrlParams->flags & NVOS54_FLAGS_FINN_SERIALIZED)) { return NV_OK; } @@ -840,6 +863,20 @@ NV_STATUS embeddedParamCopyOut(RMAPI_PARAM_COPY *paramCopies, RmCtrlParams *pRmC status = inParamsStatus; break; } + case NV0073_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD: + { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS); + + NV_STATUS inParamsStatus = rmapiParamsRelease(¶mCopies[0]); + ((NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS*)pParams)->inData = paramCopies[0].pUserParams; + + status = rmapiParamsRelease(¶mCopies[1]); + ((NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS*)pParams)->outData = paramCopies[1].pUserParams; + + if (inParamsStatus != NV_OK) + status = inParamsStatus; + break; + } case NV83DE_CTRL_CMD_DEBUG_READ_MEMORY: { CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS); diff --git a/src/nvidia/src/kernel/rmapi/entry_points.h b/src/nvidia/src/kernel/rmapi/entry_points.h index 75103d745..156c661f0 100644 --- a/src/nvidia/src/kernel/rmapi/entry_points.h +++ b/src/nvidia/src/kernel/rmapi/entry_points.h @@ -106,7 +106,7 @@ rmapiFreeWithSecInfoTls ); NV_STATUS -rmapiFreeClientList +rmapiDisableClients ( RM_API *pRmApi, NvHandle *phClientList, @@ -114,7 +114,7 @@ rmapiFreeClientList ); NV_STATUS -rmapiFreeClientListWithSecInfo +rmapiDisableClientsWithSecInfo ( RM_API *pRmApi, NvHandle *phClientList, @@ -123,7 +123,7 @@ rmapiFreeClientListWithSecInfo ); NV_STATUS -rmapiFreeClientListWithSecInfoTls +rmapiDisableClientsWithSecInfoTls ( RM_API *pRmApi, NvHandle *phClientList, diff --git a/src/nvidia/src/kernel/rmapi/event_buffer.c b/src/nvidia/src/kernel/rmapi/event_buffer.c index cbf6301a7..5706501e6 100644 --- a/src/nvidia/src/kernel/rmapi/event_buffer.c +++ b/src/nvidia/src/kernel/rmapi/event_buffer.c @@ -208,7 +208,7 @@ eventbufferConstruct_IMPL RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); NvHandle hMemory = RES_GET_HANDLE(pMemory); - if (!bKernel) + if ((!bKernel) && bUsingVgpuStagingBuffer) { status = pRmApi->DupObject(pRmApi, hMapperClient, @@ -269,7 +269,7 @@ eventbufferConstruct_IMPL RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); NvHandle hMemory = RES_GET_HANDLE(pMemory); - if (!bKernel) + if ((!bKernel) && bUsingVgpuStagingBuffer) { status = pRmApi->DupObject(pRmApi, hMapperClient, @@ -330,7 +330,7 @@ eventbufferConstruct_IMPL RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); NvHandle hMemory = RES_GET_HANDLE(pMemory); - if (!bKernel) + if ((!bKernel) && bUsingVgpuStagingBuffer) { status = pRmApi->DupObject(pRmApi, hMapperClient, diff --git a/src/nvidia/src/kernel/rmapi/mapping_cpu.c b/src/nvidia/src/kernel/rmapi/mapping_cpu.c index 4f147146a..02bf57820 100644 --- a/src/nvidia/src/kernel/rmapi/mapping_cpu.c +++ b/src/nvidia/src/kernel/rmapi/mapping_cpu.c @@ -331,7 +331,6 @@ memMap_IMPL } else { - NV_ASSERT(DRF_VAL(OS33, _FLAGS, _BUS, pMapParams->flags) == NVOS33_FLAGS_BUS_NVLINK_COHERENT); // // Allocating mapping for user mode client diff --git a/src/nvidia/src/kernel/rmapi/mapping_list.c b/src/nvidia/src/kernel/rmapi/mapping_list.c index 3e93bd79c..3335a1402 100644 --- a/src/nvidia/src/kernel/rmapi/mapping_list.c +++ b/src/nvidia/src/kernel/rmapi/mapping_list.c @@ -104,38 +104,35 @@ CliFindMappingInClient // allocates/initializes a new CLI_DMA_MAPPING_INFO. // // Ideally, we would know the dmaOffset by now but we typically don't. Thus the caller needs -// to call intermapRegisterDmaMapping() to record the dma mapping at the proper hDevice/dmaOffset location +// to call intermapRegisterDmaMapping() to record the dma mapping at the proper dmaOffset location // NV_STATUS intermapCreateDmaMapping ( RsClient *pClient, - RsResourceRef *pMemoryRef, - NvHandle hDevice, - NvHandle hMemCtx, + VirtualMemory *pVirtualMemory, PCLI_DMA_MAPPING_INFO *ppDmaMapping, NvU32 flags ) { - VirtualMemory *pVirtualMemory; Memory *pMemory = NULL; PCLI_DMA_MAPPING_INFO pDmaMapping; OBJVASPACE *pVAS = NULL; // Mapping is always virtual memory object - if (memGetByHandleAndDevice(pClient, hMemCtx, hDevice, &pMemory) != NV_OK) - { - return NV_ERR_INVALID_OBJECT_HANDLE; - } - - pVirtualMemory = dynamicCast(pMemory, VirtualMemory); - - if ((pMemory->pMemDesc == NULL) || (pVirtualMemory == NULL)) + if (pVirtualMemory == NULL) { return NV_ERR_INVALID_ARGUMENT; } - if (vaspaceGetByHandleOrDeviceDefault(pClient, hDevice, pVirtualMemory->hVASpace, &pVAS) != NV_OK) + pMemory = dynamicCast(pVirtualMemory, Memory); + + if (pMemory->pMemDesc == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if (vaspaceGetByHandleOrDeviceDefault(pClient, RES_GET_HANDLE(pMemory->pDevice), pVirtualMemory->hVASpace, &pVAS) != NV_OK) { return NV_ERR_INVALID_ARGUMENT; } @@ -149,7 +146,6 @@ intermapCreateDmaMapping // initialize the dma mapping info (not registered yet) portMemSet(pDmaMapping, 0, sizeof(CLI_DMA_MAPPING_INFO)); - pDmaMapping->hDevice = hDevice; pDmaMapping->DmaOffset = 0; pDmaMapping->bP2P = NV_FALSE; pDmaMapping->Flags = flags; // NV0S46_* @@ -160,191 +156,130 @@ intermapCreateDmaMapping } // -// registers/stores a pDmaMapping created by intermapCreateDmaMapping() at the hDevice/dmaOffset. +// registers/stores a pDmaMapping created by intermapCreateDmaMapping() at the dmaOffset. // -// important: we assume the hDevice/dmaOffset does NOT change (needs to be re-registerd) +// important: we assume the dmaOffset does NOT change (needs to be re-registerd) // NV_STATUS intermapRegisterDmaMapping ( RsClient *pClient, - NvHandle hDevice, - NvHandle hMemCtx, + VirtualMemory *pVirtualMemory, PCLI_DMA_MAPPING_INFO pDmaMapping, NvU64 dmaOffset, NvU32 gpuMask ) { NV_STATUS rmStatus = NV_OK; - VirtualMemory *pVirtualMemory = NULL; PNODE pNode; - PNODE *ppDmaMappingList; - PCLI_DMA_MAPPING_INFO pDmaMappingFirst, pDmaMappingNext; - - // eventually remove Next/Prev once all other linear list based on PCLI_DMA_MAPPING_INFO are gone... - NV_ASSERT(!pDmaMapping->Next && !pDmaMapping->Prev); - - NV_CHECK_OK_OR_RETURN(LEVEL_SILENT, - virtmemGetByHandleAndDevice(pClient, hMemCtx, hDevice, &pVirtualMemory)); - - // the top level consists of lists sorted by hDevice - already created the hDevice specific list? - if (btreeSearch(hDevice, &pNode, pVirtualMemory->pDmaMappingList) != NV_OK) - { - // create a NODE for all pDmaMappings of this hDevice - pNode = portMemAllocNonPaged(sizeof(NODE)); - if (NULL == pNode) - { - return NV_ERR_INSUFFICIENT_RESOURCES; - } - portMemSet(pNode, 0, sizeof(NODE)); - pNode->keyStart = hDevice; - pNode->keyEnd = hDevice; - pNode->Data = NULL; - - // register the hDevice list itself - rmStatus = btreeInsert(pNode, &pVirtualMemory->pDmaMappingList); - if (rmStatus != NV_OK) - { - portMemFree(pNode); - return rmStatus; - } - } - - NV_ASSERT(pNode); - ppDmaMappingList = (PNODE*)&pNode->Data; + NvU64 alignment = 0; pDmaMapping->gpuMask = gpuMask; - // the second level consists of CLI_DMA_MAPPING_INFO sorted by dmaOffset - - if (DRF_VAL(OS46, _FLAGS, _DMA_UNICAST_REUSE_ALLOC, pDmaMapping->Flags) == - NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_FALSE) + if (FLD_TEST_DRF(OS46, _FLAGS, _DMA_UNICAST_REUSE_ALLOC, _TRUE, pDmaMapping->Flags)) { - NvU64 alignment = 0; + CLI_DMA_MAPPING_INFO *pDmaMappingFirst; + CLI_DMA_MAPPING_INFO *pDmaMappingCurrent; - if (pDmaMapping->pMemDesc->pGpu != NULL) - { - OBJGPU *pGpu = pDmaMapping->pMemDesc->pGpu; - // - // For verify purposes we should allow small page override for mapping. - // This will be used for testing VASpace interop. - // However, this info is not captured in the DMA mapping info for guest. - // So explicitly check for this case in guest. - // - if (IS_VIRTUAL_WITH_SRIOV(pGpu) - && RMCFG_FEATURE_PLATFORM_MODS - && FLD_TEST_DRF(OS46, _FLAGS, _PAGE_SIZE, _4KB, pDmaMapping->Flags) - && kgmmuIsVaspaceInteropSupported(GPU_GET_KERNEL_GMMU(pGpu)) - ) - { - alignment = RM_PAGE_SIZE; - } - else - { - alignment = (NvU64)memdescGetPageSize(memdescGetMemDescFromGpu(pDmaMapping->pMemDesc, pGpu), - pDmaMapping->addressTranslation); - } - } - - // - // In some cases page size may not be set (e.g. NV50, AMODEL, VGPU). - // Ideally we should fix all paths for consistency, but for now - // allowing fallback to unaligned tracking (no worse than before). - // - // TODO: Revisit this with memdesc page size cleanup. - // - if (alignment == 0) - { - alignment = 1; - } - - // create the node for this dmaOffset - pNode = portMemAllocNonPaged(sizeof(NODE)); - if (NULL == pNode) - { - return NV_ERR_INSUFFICIENT_RESOURCES; - } - portMemSet(pNode, 0, sizeof(NODE)); - - // - // For normal GPU devices, track the mapping over its entire - // virtual range so overlapping mappings are caught. - // - // keyStart and keyEnd must be aligned to the physical page size to - // ensure no page can be mapped twice. - // (e.g. small pages mapped into the leftovers of a big page). - // - // NOTE: Unfortunately this check occurs after the internal mapping - // has already taken place, so the state is already corrupted. - // Failure here means "Oops, your're screwed." - // - // For Fermi+ we have added checks in the internal mapping code - // that will fail safely. - // - pNode->keyStart = RM_ALIGN_DOWN(dmaOffset, alignment); - pNode->keyEnd = RM_ALIGN_UP(dmaOffset + pDmaMapping->pMemDesc->Size, - alignment) - 1; - pNode->Data = pDmaMapping; - - // register the 'dmaOffset' list itself - rmStatus = btreeInsert(pNode, ppDmaMappingList); - if (rmStatus != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "Failed to insert new mapping node for range 0x%llX-0x%llX!\n", - pNode->keyStart, pNode->keyEnd); - DBG_BREAKPOINT(); - portMemFree(pNode); - return rmStatus; - } - } - else - { // The node for this DMA offset should be already created - rmStatus = btreeSearch(dmaOffset, &pNode, *ppDmaMappingList); - if (rmStatus != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "Failed to find existing mapping node for offset 0x%llX!\n", - dmaOffset); - DBG_BREAKPOINT(); - return rmStatus; - } + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, btreeSearch(dmaOffset, &pNode, pVirtualMemory->pDmaMappingList)); + pDmaMappingFirst = (CLI_DMA_MAPPING_INFO *)pNode->Data; - NV_ASSERT(pNode); - pDmaMappingFirst = (PCLI_DMA_MAPPING_INFO)pNode->Data; + NV_CHECK_OR_RETURN(LEVEL_ERROR, pDmaMappingFirst->DmaOffset == pDmaMapping->DmaOffset && + pDmaMappingFirst->pMemDesc->Size == pDmaMapping->pMemDesc->Size, + NV_ERR_INVALID_ARGUMENT); - // check that we do not exceed the original mapping length - if (pDmaMapping->pMemDesc->Size > pDmaMappingFirst->pMemDesc->Size) + // Check gpuMasks for consistency + NV_CHECK_OR_RETURN(LEVEL_ERROR, (pDmaMappingFirst->gpuMask & (pDmaMappingFirst->gpuMask - 1)) == 0, NV_ERR_INVALID_ARGUMENT); + NV_CHECK_OR_RETURN(LEVEL_ERROR, (pDmaMapping->gpuMask & (pDmaMapping->gpuMask - 1)) == 0, NV_ERR_INVALID_ARGUMENT); + pDmaMappingCurrent = pDmaMappingFirst; + while (pDmaMappingCurrent != NULL) { - NV_PRINTF(LEVEL_ERROR, - "Mapping length 0x%llX exceeds existing mapping length of 0x%llX!\n", - pDmaMapping->pMemDesc->Size, - pDmaMappingFirst->pMemDesc->Size); - DBG_BREAKPOINT(); - return NV_ERR_INVALID_LIMIT; + NV_CHECK_OR_RETURN(LEVEL_ERROR, (pDmaMapping->gpuMask & pDmaMappingCurrent->gpuMask) == 0, NV_ERR_INVALID_ARGUMENT); + pDmaMappingCurrent = pDmaMappingCurrent->pNext; } // Insert the gpuMask element to the list - pDmaMapping->Next = pDmaMappingFirst; - pDmaMappingFirst->Prev = pDmaMapping; + pDmaMapping->pNext = pDmaMappingFirst; pNode->Data = pDmaMapping; - // Change the other mappings to remove this gpuMask from them - pDmaMapping = pDmaMapping->Next; - while (pDmaMapping) + return NV_OK; + } + + if (pDmaMapping->pMemDesc->pGpu != NULL) + { + OBJGPU *pGpu = pDmaMapping->pMemDesc->pGpu; + // + // For verify purposes we should allow small page override for mapping. + // This will be used for testing VASpace interop. + // However, this info is not captured in the DMA mapping info for guest. + // So explicitly check for this case in guest. + // + if (IS_VIRTUAL_WITH_SRIOV(pGpu) + && RMCFG_FEATURE_PLATFORM_MODS + && FLD_TEST_DRF(OS46, _FLAGS, _PAGE_SIZE, _4KB, pDmaMapping->Flags) + && kgmmuIsVaspaceInteropSupported(GPU_GET_KERNEL_GMMU(pGpu)) + ) { - pDmaMappingNext = pDmaMapping->Next; - if (pDmaMapping->gpuMask & gpuMask) - { - pDmaMapping->gpuMask &= ~gpuMask; - if (pDmaMapping->gpuMask == 0) - { - // free the pDmaMapping itself - intermapFreeDmaMapping(pDmaMapping); - } - } - pDmaMapping = pDmaMappingNext; + alignment = RM_PAGE_SIZE; } + else + { + alignment = memdescGetPageSize64(memdescGetMemDescFromGpu(pDmaMapping->pMemDesc, pGpu), + pDmaMapping->addressTranslation); + } + } + + // + // In some cases page size may not be set (e.g. NV50, AMODEL, VGPU). + // Ideally we should fix all paths for consistency, but for now + // allowing fallback to unaligned tracking (no worse than before). + // + // TODO: Revisit this with memdesc page size cleanup. + // + if (alignment == 0) + { + alignment = 1; + } + + // create the node for this dmaOffset + pNode = portMemAllocNonPaged(sizeof(NODE)); + if (NULL == pNode) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + portMemSet(pNode, 0, sizeof(NODE)); + + // + // For normal GPU devices, track the mapping over its entire + // virtual range so overlapping mappings are caught. + // + // keyStart and keyEnd must be aligned to the physical page size to + // ensure no page can be mapped twice. + // (e.g. small pages mapped into the leftovers of a big page). + // + // NOTE: Unfortunately this check occurs after the internal mapping + // has already taken place, so the state is already corrupted. + // Failure here means "Oops, your're screwed." + // + // For Fermi+ we have added checks in the internal mapping code + // that will fail safely. + // + pNode->keyStart = RM_ALIGN_DOWN(dmaOffset, alignment); + pNode->keyEnd = RM_ALIGN_UP(dmaOffset + pDmaMapping->pMemDesc->Size, + alignment) - 1; + pNode->Data = pDmaMapping; + + // register the 'dmaOffset' list itself + rmStatus = btreeInsert(pNode, &pVirtualMemory->pDmaMappingList); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to insert new mapping node for range 0x%llX-0x%llX!\n", + pNode->keyStart, pNode->keyEnd); + DBG_BREAKPOINT(); + portMemFree(pNode); + return rmStatus; } return NV_OK; @@ -354,115 +289,52 @@ NV_STATUS intermapDelDmaMapping ( RsClient *pClient, - NvHandle hDevice, - NvHandle hMemCtx, + VirtualMemory *pVirtualMemory, NvU64 dmaOffset, - NvU32 gpuMask, - NvBool *pbUnmapped + NvU32 gpuMask ) { - NV_STATUS rmStatus = NV_OK; - VirtualMemory *pVirtualMemory = NULL; - PCLI_DMA_MAPPING_INFO pDmaMapping, pDmaMappingNext, pDmaMappingPrev; - PNODE pDeviceNode; - PNODE pOffsetNode; PNODE pNode; - - if (pbUnmapped != NULL) - *pbUnmapped = NV_FALSE; - - // Mapping is always virtual memory object - NV_CHECK_OK_OR_RETURN(LEVEL_SILENT, - virtmemGetByHandleAndDevice(pClient, hMemCtx, hDevice, &pVirtualMemory)); - - // first find the list specific to the hDevice - rmStatus = btreeSearch(hDevice, &pDeviceNode, pVirtualMemory->pDmaMappingList); - if (rmStatus != NV_OK) - { - return rmStatus; - } + CLI_DMA_MAPPING_INFO *pDmaMapping; + CLI_DMA_MAPPING_INFO *pDmaMappingPrev = NULL; // then get the node belonging to the search offset - rmStatus = btreeSearch(dmaOffset, &pOffsetNode, (PNODE)pDeviceNode->Data); - if (rmStatus != NV_OK) - { - return rmStatus; - } + NV_ASSERT_OK_OR_RETURN(btreeSearch(dmaOffset, &pNode, pVirtualMemory->pDmaMappingList)); - pDmaMapping = pOffsetNode->Data; - - // Remove the first dma mappings intersecting with this GPU mask + pDmaMapping = (CLI_DMA_MAPPING_INFO *)pNode->Data; while (pDmaMapping != NULL) { - pDmaMappingNext = pDmaMapping->Next; - if (pDmaMapping->gpuMask & gpuMask) { - // Remove the element - pDmaMappingPrev = pDmaMapping->Prev; + CLI_DMA_MAPPING_INFO *pDmaMappingNext = pDmaMapping->pNext; + NV_ASSERT_OR_RETURN(pDmaMapping->gpuMask == gpuMask, NV_ERR_INVALID_ARGUMENT); + + // Remove the element if (pDmaMappingPrev != NULL) { - pDmaMappingPrev->Next = pDmaMappingNext; + pDmaMappingPrev->pNext = pDmaMappingNext; + } + else if (pDmaMappingNext != NULL) + { + pNode->Data = pDmaMappingNext; } else { - pOffsetNode->Data = pDmaMappingNext; + NV_ASSERT_OK_OR_RETURN(btreeUnlink(pNode, &pVirtualMemory->pDmaMappingList)); + portMemFree(pNode); } - if (pDmaMappingNext != NULL) - { - pDmaMappingNext->Prev = pDmaMappingPrev; - } - - // free the pDmaMapping itself intermapFreeDmaMapping(pDmaMapping); - - if (pbUnmapped != NULL) - *pbUnmapped = NV_TRUE; - - break; + return NV_OK; } - - pDmaMapping = pDmaMappingNext; + pDmaMappingPrev = pDmaMapping; + pDmaMapping = pDmaMapping->pNext; } - // Is the list empty ? - if (pOffsetNode->Data == NULL) - { - // unlink the node - rmStatus = btreeSearch(dmaOffset, &pNode, (PNODE)pDeviceNode->Data); - if (rmStatus != NV_OK) - { - return rmStatus; - } - - rmStatus = btreeUnlink(pNode, (PNODE*)&pDeviceNode->Data); - if (rmStatus == NV_OK) - { - // free the node memory itself - portMemFree(pOffsetNode); - - // is our dmaOffset list empty now? - if (pDeviceNode->Data == NULL) - { - // remove the whole hDevice list - rmStatus = btreeSearch(hDevice, &pNode, pVirtualMemory->pDmaMappingList); - if (rmStatus != NV_OK) - { - return rmStatus; - } - - rmStatus = btreeUnlink(pNode, &pVirtualMemory->pDmaMappingList); - if (rmStatus == NV_OK) - { - portMemFree(pDeviceNode); - } - } - } - } - - return rmStatus; + // mapping with the right gpuMask was not found + NV_ASSERT(0); + return NV_ERR_OBJECT_NOT_FOUND; } void @@ -477,57 +349,41 @@ intermapFreeDmaMapping portMemFree(pDmaMapping); } -static NvBool -_getDmaMappingInfoFromMemory +/*! + * @brief Lookup mapping info in a virtual memory allocation + */ +CLI_DMA_MAPPING_INFO * +intermapGetDmaMapping ( VirtualMemory *pVirtualMemory, - NvHandle hDevice, NvU64 dmaOffset, - NvU32 gpuMask, - PCLI_DMA_MAPPING_INFO *ppDmaMappingInfo + NvU32 gpuMask ) { - PNODE pDmaMappingList; PNODE pNode; - PCLI_DMA_MAPPING_INFO pDmaMappingInfo; + CLI_DMA_MAPPING_INFO *pDmaMapping; - // first find the list specific to the hDevice - pDmaMappingList = pVirtualMemory->pDmaMappingList; - if (btreeSearch(hDevice, &pNode, pDmaMappingList) == NV_OK) + // get the node belonging to the search offset + if (btreeSearch(dmaOffset, &pNode, pVirtualMemory->pDmaMappingList) != NV_OK) + return NULL; + + pDmaMapping = pNode->Data; + + while (pDmaMapping != NULL) { - pDmaMappingList = (PNODE)pNode->Data; - NV_ASSERT(pDmaMappingList); + if (pDmaMapping->gpuMask & gpuMask) + return pDmaMapping; - // then get the node belonging to the search offset - if (btreeSearch(dmaOffset, &pNode, pDmaMappingList) == NV_OK) - { - // Then look for the GPU mask - pDmaMappingInfo = pNode->Data; - while (pDmaMappingInfo) - { - if (pDmaMappingInfo->gpuMask & gpuMask) - { - // Returns the first mapping that intersects with this gpu mask. - break; - } - pDmaMappingInfo = pDmaMappingInfo->Next; - } - if (pDmaMappingInfo != NULL) - { - *ppDmaMappingInfo = pDmaMappingInfo; - return NV_TRUE; - } - } + pDmaMapping = pDmaMapping->pNext; } - return NV_FALSE; + + return pDmaMapping; } /*! - * @brief Lookup mapping info in memory context or VA space + * @brief Lookup mapping info in VA space * - * This is useful when processing SW methods. We can find the hVASpace - * from the channel context uniquely. Previous lookup within the whole - * client could mistakenly find an alias on another device. + * This is useful for semaphores/notifiers when processing SW methods. */ NvBool CliGetDmaMappingInfo @@ -545,7 +401,6 @@ CliGetDmaMappingInfo Device *pDevice; NODE *pNode; NV_STATUS status; - NvBool bFound; status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); if (status != NV_OK) @@ -564,7 +419,9 @@ CliGetDmaMappingInfo pVirtualMemory = dynamicCast(pMemCtxRef->pResource, VirtualMemory); if (pVirtualMemory != NULL) { - return _getDmaMappingInfoFromMemory(pVirtualMemory, hDevice, dmaOffset, gpuMask, ppDmaMappingInfo); + + *ppDmaMappingInfo = intermapGetDmaMapping(pVirtualMemory, dmaOffset, gpuMask); + return *ppDmaMappingInfo != NULL; } } @@ -582,11 +439,10 @@ CliGetDmaMappingInfo if ((pVirtualMemory != NULL) && virtmemMatchesVASpace(pVirtualMemory, hClient, hMemCtx)) { - bFound = _getDmaMappingInfoFromMemory(pVirtualMemory, hDevice, - dmaOffset, gpuMask, - ppDmaMappingInfo); - if (bFound) - return bFound; + *ppDmaMappingInfo = intermapGetDmaMapping(pVirtualMemory, dmaOffset, gpuMask); + + if (*ppDmaMappingInfo != NULL) + return NV_TRUE; } } @@ -604,22 +460,19 @@ CliGetDmaMappingIterator // don't iterate if we didn't get a empty list *ppFirstDmaMapping = NULL; portMemSet(pIt, 0, sizeof(*pIt)); - if (pDmaMappingList != NULL) - { - // find the first hDevice list - pIt->pDmaMappingList = pDmaMappingList; - btreeEnumStart(0, &pIt->pCurrentList, pIt->pDmaMappingList); - if (pIt->pCurrentList != NULL) - { - // find the first pDmaMapping of the hDevice list (hDevice lists can't be empty *ever*) - NV_ASSERT(pIt->pCurrentList->Data); - btreeEnumStart(0, &pIt->pNextDmaMapping, pIt->pCurrentList->Data); - NV_ASSERT(pIt->pNextDmaMapping); - NV_ASSERT(pIt->pNextDmaMapping->Data); - CliGetDmaMappingNext(ppFirstDmaMapping, pIt); - } - } + if (pDmaMappingList == NULL) + return; + + // find the first pDmaMapping + pIt->pDmaMappingList = pDmaMappingList; + btreeEnumStart(0, &pIt->pNextDmaMapping, pIt->pDmaMappingList); + + if (pIt->pNextDmaMapping == NULL) + return; + + NV_ASSERT(pIt->pNextDmaMapping->Data); + CliGetDmaMappingNext(ppFirstDmaMapping, pIt); } void @@ -631,37 +484,23 @@ CliGetDmaMappingNext { PCLI_DMA_MAPPING_INFO pDmaMapping = NULL; - // are we done with all hDevice lists? - if ((pIt->pDmaMappingList != NULL) && - (pIt->pCurrentList != NULL) && - (pIt->pNextDmaMapping != NULL)) + if (pIt->pNextDmaMapping != NULL) { // return the current node. NV_ASSERT(pIt->pNextDmaMapping->Data); pDmaMapping = (PCLI_DMA_MAPPING_INFO)pIt->pNextDmaMapping->Data; - // iterate to the next DmaOffset (so the caller is free to delete the node) - btreeEnumNext(&pIt->pNextDmaMapping, pIt->pCurrentList); + // not supporting legacy _DMA_UNICAST_REUSE_ALLOC case + NV_ASSERT(pDmaMapping->pNext == NULL); - // reached the end of the hDevice list? move to next hDevice - if (pIt->pNextDmaMapping == NULL) - { - btreeEnumNext(&pIt->pCurrentList, pIt->pDmaMappingList); - if (pIt->pCurrentList != NULL) - { - // restart iteration process for the new list - NV_ASSERT(pIt->pCurrentList->Data); - btreeEnumStart(0, &pIt->pNextDmaMapping, pIt->pCurrentList->Data); - NV_ASSERT(pIt->pNextDmaMapping); - } - } + // iterate to the next DmaOffset (so the caller is free to delete the node) + btreeEnumNext(&pIt->pNextDmaMapping, pIt->pDmaMappingList); } // stop iterating once we hit the end of list [or something bad happened] if (pDmaMapping == NULL) { pIt->pDmaMappingList = NULL; - pIt->pCurrentList = NULL; pIt->pNextDmaMapping = NULL; } *ppDmaMapping = pDmaMapping; diff --git a/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c b/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c index 2b627d790..d0c979dd2 100644 --- a/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c +++ b/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c @@ -145,7 +145,7 @@ typedef struct typedef struct { - NvU32 pageSize; // default is 4k or 64k else use pagesize = 2M. + NvU64 pageSize; // default is 4k or 64k else use pagesize = 2M. NvU64 alignment; } gpuVaAllocInfo; @@ -405,9 +405,6 @@ static NvU32 getNvlinkConnectionToNpu(const NV2080_CTRL_CMD_NVLINK_GET_NVLINK_ST NvU32 *linkBandwidthMBps); static NvU32 getNvlinkConnectionToSwitch(const NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *nvlinkStatus, NvU32 *linkBandwidthMBps); -static NV_STATUS getC2CConnectionToCpu(struct gpuDevice *device, - NvBool *connectedToCpu, - NvU32 *linkBandwidthMBps); static NV_STATUS nvGpuOpsGetMemoryByHandle(NvHandle hClient, NvHandle hMemory, Memory **ppMemory); static void _nvGpuOpsReleaseChannel(gpuRetainedChannel *retainedChannel); static NV_STATUS _nvGpuOpsRetainChannelResources(struct gpuDevice *device, @@ -1582,8 +1579,8 @@ static NV_STATUS getPCIELinkRateMBps(struct gpuDevice *device, NvU32 *pcieLinkRa const NvU32 PCIE_4_ENCODING_RATIO_EFFECTIVE = 128; const NvU32 PCIE_5_ENCODING_RATIO_TOTAL = 130; const NvU32 PCIE_5_ENCODING_RATIO_EFFECTIVE = 128; - const NvU32 PCIE_6_ENCODING_RATIO_TOTAL = 130; - const NvU32 PCIE_6_ENCODING_RATIO_EFFECTIVE = 128; + const NvU32 PCIE_6_ENCODING_RATIO_TOTAL = 256; + const NvU32 PCIE_6_ENCODING_RATIO_EFFECTIVE = 242; RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); NV2080_CTRL_BUS_INFO busInfo = {0}; @@ -1780,24 +1777,6 @@ NV_STATUS nvGpuOpsDeviceCreate(struct gpuSession *session, nvlinkStatus = NULL; break; } - case NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_C2C: - { - NvBool c2cConnectedToCpu = NV_FALSE; - - status = getC2CConnectionToCpu(device, &c2cConnectedToCpu, &linkBandwidthMBps); - if (status != NV_OK) - goto cleanup_ecc; - - if (c2cConnectedToCpu == NV_FALSE) - { - NV_ASSERT(0); - status = NV_ERR_INVALID_STATE; - goto cleanup_ecc; - } - - sysmemLink = UVM_LINK_TYPE_C2C; - break; - } case NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_PCIE: { sysmemLink = UVM_LINK_TYPE_PCIE; @@ -2342,33 +2321,6 @@ static NvU32 getNvlinkConnectionToGpu(const NV2080_CTRL_CMD_NVLINK_GET_NVLINK_ST return version; } -static NV_STATUS getC2CConnectionToCpu(struct gpuDevice *device, - NvBool *connectedToCpu, - NvU32 *linkBandwidthMBps) -{ - NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS params = {0}; - RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); - - *connectedToCpu = NV_FALSE; - *linkBandwidthMBps = 0; - - NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, - device->session->handle, - device->subhandle, - NV2080_CTRL_CMD_BUS_GET_C2C_INFO, - ¶ms, - sizeof(params))); - - if (params.bIsLinkUp == NV_TRUE && - (params.remoteType == NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU)) - { - *connectedToCpu = NV_TRUE; - *linkBandwidthMBps = params.nrLinks * params.perLinkBwMBps; - } - - return NV_OK; -} - // If the given NvLink connection has a NPU device as an endpoint, return the // version of the NvLink connection with that NPU , and the maximum // unidirectional bandwidth in megabytes per second. Otherwise, return @@ -3009,10 +2961,10 @@ nvGpuOpsMemGetPageSize ( OBJGPU *pGpu, MEMORY_DESCRIPTOR *pMemDesc, - NvU32 *pPageSize + NvU64 *pPageSize ) { - NvU32 pageSize; + NvU64 pageSize; MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); NV_STATUS status; @@ -3062,7 +3014,8 @@ nvGpuOpsBuildExternalAllocPtes GMMU_ENTRY_VALUE pte = {{0}}; NvU64 fabricBaseAddress = NVLINK_INVALID_FABRIC_ADDR; - NvU32 kind, pageSize; + NvU32 kind; + NvU64 pageSize; NvU32 skipPteCount; NvBool vol, atomic, readOnly; NvBool encrypted, privileged; @@ -3077,6 +3030,7 @@ nvGpuOpsBuildExternalAllocPtes NvU64 gpaOffset; NvBool *isPLCable = NULL; NvU64 *guestPhysicalAddress = NULL; + NvU64 mappingPageSize = pGpuExternalMappingInfo->mappingPageSize; NV_ASSERT(!memdescHasSubDeviceMemDescs(pMemDesc)); @@ -3086,6 +3040,21 @@ nvGpuOpsBuildExternalAllocPtes if (status != NV_OK) return status; + // + // Default mappingPageSize to allocation's page size if passed as 0. + // If mappingPageSize is non-zero, it must be a multiple of pageSize. + // Also, mapping page size cannot be larger than alloc page size. + // + if (mappingPageSize == 0) + { + mappingPageSize = pageSize; + } + else if ((mappingPageSize > pageSize) || + (pageSize % mappingPageSize != 0)) + { + return NV_ERR_INVALID_ARGUMENT; + } + // memdescGetSize returns the requested size of the allocation. But, the // actual allocation size could be larger than the requested size due // to alignment requirement. So, make sure the correct size is used. @@ -3098,10 +3067,10 @@ nvGpuOpsBuildExternalAllocPtes if ((offset + size) > allocSize) return NV_ERR_INVALID_LIMIT; - if ((size & (pageSize - 1)) != 0) + if ((size & (mappingPageSize - 1)) != 0) return NV_ERR_INVALID_ARGUMENT; - if ((offset & (pageSize - 1)) != 0) + if ((offset & (mappingPageSize - 1)) != 0) return NV_ERR_INVALID_ARGUMENT; pGVAS = dynamicCast(pVAS, OBJGVASPACE); @@ -3109,7 +3078,7 @@ nvGpuOpsBuildExternalAllocPtes // Get the GMMU format pFmt = gvaspaceGetGmmuFmt(pGVAS, pMappingGpu); pPteFmt = (GMMU_FMT_PTE*)pFmt->pPte; - pLevelFmt = mmuFmtFindLevelWithPageShift(pFmt->pRoot, BIT_IDX_32(pageSize)); + pLevelFmt = mmuFmtFindLevelWithPageShift(pFmt->pRoot, BIT_IDX_64(mappingPageSize)); oldKind = newKind = memdescGetPteKindForGpu(pMemDesc, pMappingGpu); if (pMemory) @@ -3162,7 +3131,18 @@ nvGpuOpsBuildExternalAllocPtes isCompressedKind = memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_COMPRESSIBLE, kind); - pteCount = NV_MIN((pGpuExternalMappingInfo->pteBufferSize / pLevelFmt->entrySize), (mappingSize / pageSize)); + // + // Specifying mapping page size for compressed + // allocations is not yet supported. + // + if (isCompressedKind && (pGpuExternalMappingInfo->mappingPageSize != 0) && + (pGpuExternalMappingInfo->mappingPageSize != pageSize)) + { + return NV_ERR_NOT_SUPPORTED; + } + + pteCount = NV_MIN((pGpuExternalMappingInfo->pteBufferSize / pLevelFmt->entrySize), + (mappingSize / mappingPageSize)); if (!pteCount) return NV_ERR_BUFFER_TOO_SMALL; @@ -3274,7 +3254,8 @@ nvGpuOpsBuildExternalAllocPtes // it requires IOMMU mappings to be set up and these are different for each // GPU. The IOMMU mappings are currently added by nvGpuOpsDupMemory(). // - memdescGetPhysAddrsForGpu(pMemDesc, pMappingGpu, AT_GPU, offset, pageSize, pteCount, physicalAddresses); + memdescGetPhysAddrsForGpu(pMemDesc, pMappingGpu, AT_GPU, offset, mappingPageSize, + pteCount, physicalAddresses); kgmmuEncodePhysAddrs(pKernelGmmu, aperture, physicalAddresses, fabricBaseAddress, pteCount); @@ -3299,7 +3280,7 @@ nvGpuOpsBuildExternalAllocPtes for (iter = 0; iter < pteCount; iter++) { guestPhysicalAddress[iter] = gpaOffset; - gpaOffset += pageSize; + gpaOffset += mappingPageSize; } isPLCable = portMemAllocNonPaged((NvU32)pteCount * sizeof(*isPLCable)); @@ -3311,7 +3292,7 @@ nvGpuOpsBuildExternalAllocPtes portMemSet(isPLCable, 0, ((NvU32)pteCount * sizeof(*isPLCable))); - NV_RM_RPC_GET_PLCABLE_ADDRESS_KIND(pMappingGpu, guestPhysicalAddress, pageSize, (NvU32)pteCount, + NV_RM_RPC_GET_PLCABLE_ADDRESS_KIND(pMappingGpu, guestPhysicalAddress, mappingPageSize, (NvU32)pteCount, isPLCable, status); if (status != NV_OK) goto done; @@ -3356,7 +3337,8 @@ nvGpuOpsBuildExternalAllocPtes } else { - bEnablePlc = kmemsysIsPagePLCable_HAL(pMappingGpu, pKernelMemorySystem, offset, pageSize); + bEnablePlc = kmemsysIsPagePLCable_HAL(pMappingGpu, pKernelMemorySystem, + offset, mappingPageSize); } if (!bEnablePlc) @@ -3378,11 +3360,11 @@ nvGpuOpsBuildExternalAllocPtes portMemCopy(&pGpuExternalMappingInfo->pteBuffer[iter * skipPteCount], pLevelFmt->entrySize, pte.v8, pLevelFmt->entrySize); - offset += pageSize; + offset += mappingPageSize; } pGpuExternalMappingInfo->numWrittenPtes = pteCount; - pGpuExternalMappingInfo->numRemainingPtes = (mappingSize / pageSize) - pteCount; + pGpuExternalMappingInfo->numRemainingPtes = (mappingSize / mappingPageSize) - pteCount; pGpuExternalMappingInfo->pteSize = pLevelFmt->entrySize; done: @@ -3826,7 +3808,7 @@ done: static NV_STATUS nvGpuOpsMapGpuMemory(struct gpuAddressSpace *vaSpace, NvU64 vaOffset, NvLength length, - NvU32 pageSize, + NvU64 pageSize, NvU64 *gpuOffset, struct allocFlags flags) { @@ -3834,7 +3816,7 @@ static NV_STATUS nvGpuOpsMapGpuMemory(struct gpuAddressSpace *vaSpace, NV_STATUS status; NvU64 mappedVa = 0; NvU32 mapFlags = 0; - NvU32 mapPageSize = 0; + NvU64 mapPageSize = 0; RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); if (!vaSpace || !gpuOffset) @@ -4106,7 +4088,7 @@ cleanup_dup: return status; } -NV_STATUS nvGpuOpsPmaAllocPages(void *pPma, NvLength pageCount, NvU32 pageSize, +NV_STATUS nvGpuOpsPmaAllocPages(void *pPma, NvLength pageCount, NvU64 pageSize, gpuPmaAllocationOptions *pPmaAllocOptions, NvU64 *pPages) { @@ -4149,7 +4131,7 @@ NV_STATUS nvGpuOpsPmaAllocPages(void *pPma, NvLength pageCount, NvU32 pageSize, NV_STATUS nvGpuOpsPmaPinPages(void *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize, + NvU64 pageSize, NvU32 flags) { NV_STATUS status; @@ -4173,7 +4155,7 @@ NV_STATUS nvGpuOpsPmaPinPages(void *pPma, NV_STATUS nvGpuOpsPmaUnpinPages(void *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize) + NvU64 pageSize) { NV_STATUS status; THREAD_STATE_NODE threadState; @@ -4197,7 +4179,7 @@ NV_STATUS nvGpuOpsPmaUnpinPages(void *pPma, void nvGpuOpsPmaFreePages(void *pPma, NvU64 *pPages, NvLength pageCount, - NvU32 pageSize, + NvU64 pageSize, NvU32 flags) { THREAD_STATE_NODE threadState; @@ -4551,6 +4533,7 @@ static NV_STATUS channelAllocate(struct gpuAddressSpace *vaSpace, // sufficiently large to also accommodate any other channel // notifiers, and request a kernel VA and CPU caching. // + flags.bGetKernelVA = NV_TRUE; errorNotifierSize = sizeof(NvNotification) * NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1; @@ -4621,6 +4604,7 @@ static NV_STATUS channelAllocate(struct gpuAddressSpace *vaSpace, if (isDeviceVoltaPlus(device)) { + flags.bGetKernelVA = NV_FALSE; status = nvGpuOpsGpuMalloc(vaSpace, gpPutLoc == UVM_BUFFER_LOCATION_SYS, @@ -5037,7 +5021,7 @@ NV_STATUS nvGpuOpsMemoryCpuMap(struct gpuAddressSpace *vaSpace, NvU64 memory, NvLength length, void **cpuPtr, - NvU32 pageSize) + NvU64 pageSize) { gpuMemDesc *memDesc = NULL; cpuMappingDesc *cpuMapDesc = NULL; @@ -5224,7 +5208,7 @@ NV_STATUS nvGpuOpsQueryCaps(struct gpuDevice *device, gpuCaps *caps) THREAD_STATE_NODE threadState; OBJGPU *pGpu = NULL; KernelMemorySystem *pKernelMemorySystem; - NV0000_CTRL_GPU_GET_ID_INFO_PARAMS infoParams = {0}; + NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS infoParams = {0}; struct gpuSession *session = device->session; RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); @@ -5244,7 +5228,7 @@ NV_STATUS nvGpuOpsQueryCaps(struct gpuDevice *device, gpuCaps *caps) status = pRmApi->Control(pRmApi, session->handle, session->handle, - NV0000_CTRL_CMD_GPU_GET_ID_INFO, + NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2, &infoParams, sizeof(infoParams)); if (status != NV_OK) @@ -6865,7 +6849,8 @@ NV_STATUS nvGpuOpsInitFaultInfo(struct gpuDevice *device, NVB069_ALLOCATION_PARAMETERS faultBufferAllocParams = {0}; NVB069_CTRL_FAULTBUFFER_GET_SIZE_PARAMS sizeParams = {0}; NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS_PARAMS registermappingsParams = {0}; - void *bufferAddress; + void *bufferAddress = NULL; + NvU32 faultBufferSize = 0; RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); pFaultInfo->faultBufferHandle = NV01_NULL_OBJECT; @@ -6878,36 +6863,32 @@ NV_STATUS nvGpuOpsInitFaultInfo(struct gpuDevice *device, if (status != NV_OK) goto cleanup; - // Get the Size of the fault buffer - status = pRmApi->Control(pRmApi, - session->handle, - pFaultInfo->faultBufferHandle, - NVB069_CTRL_CMD_FAULTBUFFER_GET_SIZE, - &sizeParams, - sizeof(sizeParams)); - if (status != NV_OK) - goto cleanup_fault_buffer; - // Map the fault buffer pointer to CPU - status = pRmApi->MapToCpu(pRmApi, - session->handle, - device->subhandle, - pFaultInfo->faultBufferHandle, - 0, - pFaultInfo->replayable.bufferSize, - &bufferAddress, - 0); - if (status != NV_OK) - goto cleanup_fault_buffer; + { + // Get the Size of the fault buffer + status = pRmApi->Control(pRmApi, + session->handle, + pFaultInfo->faultBufferHandle, + NVB069_CTRL_CMD_FAULTBUFFER_GET_SIZE, + &sizeParams, + sizeof(sizeParams)); + if (status != NV_OK) + goto cleanup_fault_buffer; - status = pRmApi->Control(pRmApi, - session->handle, - pFaultInfo->faultBufferHandle, - NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS, - ®istermappingsParams, - sizeof(registermappingsParams)); - if (status != NV_OK) - goto cleanup_fault_buffer; + faultBufferSize = sizeParams.faultBufferSize; + + // Map the fault buffer pointer to CPU + status = pRmApi->MapToCpu(pRmApi, + session->handle, + device->subhandle, + pFaultInfo->faultBufferHandle, + 0, + pFaultInfo->replayable.bufferSize, + &bufferAddress, + 0); + if (status != NV_OK) + goto cleanup_fault_buffer; + } if (isDeviceVoltaPlus(device)) { @@ -6927,6 +6908,16 @@ NV_STATUS nvGpuOpsInitFaultInfo(struct gpuDevice *device, pFaultInfo->nonReplayable.bufferSize = nonReplayableFaultsParams.bufferSize; } + registermappingsParams.faultBufferType = NVB069_CTRL_FAULT_BUFFER_REPLAYABLE; + status = pRmApi->Control(pRmApi, + session->handle, + pFaultInfo->faultBufferHandle, + NVB069_CTRL_CMD_FAULTBUFFER_GET_REGISTER_MAPPINGS, + ®istermappingsParams, + sizeof(registermappingsParams)); + if (status != NV_OK) + goto cleanup_fault_buffer; + pFaultInfo->replayable.pFaultBufferGet = (NvU32*)(NvUPtr)registermappingsParams.pFaultBufferGet; pFaultInfo->replayable.pFaultBufferPut = (NvU32*)(NvUPtr)registermappingsParams.pFaultBufferPut; pFaultInfo->replayable.pFaultBufferInfo = (NvU32*)(NvUPtr)registermappingsParams.pFaultBufferInfo; @@ -6935,16 +6926,18 @@ NV_STATUS nvGpuOpsInitFaultInfo(struct gpuDevice *device, pFaultInfo->replayable.pPmcIntrEnClear = (NvU32*)(NvUPtr)registermappingsParams.pPmcIntrEnClear; pFaultInfo->replayable.replayableFaultMask = registermappingsParams.replayableFaultMask; pFaultInfo->replayable.pPrefetchCtrl = (NvU32*)(NvUPtr)registermappingsParams.pPrefetchCtrl; - pFaultInfo->replayable.bufferSize = sizeParams.faultBufferSize; + pFaultInfo->replayable.bufferSize = faultBufferSize; pFaultInfo->replayable.bufferAddress = bufferAddress; return NV_OK; cleanup_fault_buffer: - gpuDeviceUnmapCpuFreeHandle(device, - pFaultInfo->faultBufferHandle, - pFaultInfo->replayable.bufferAddress, - 0); + { + gpuDeviceUnmapCpuFreeHandle(device, + pFaultInfo->faultBufferHandle, + pFaultInfo->replayable.bufferAddress, + 0); + } cleanup: portMemSet(pFaultInfo, 0, sizeof(*pFaultInfo)); return status; @@ -7197,10 +7190,12 @@ NV_STATUS nvGpuOpsDestroyFaultInfo(struct gpuDevice *device, NV_ASSERT(status == NV_OK); } - gpuDeviceUnmapCpuFreeHandle(device, - pFaultInfo->faultBufferHandle, - pFaultInfo->replayable.bufferAddress, - 0); + { + gpuDeviceUnmapCpuFreeHandle(device, + pFaultInfo->faultBufferHandle, + pFaultInfo->replayable.bufferAddress, + 0); + } portMemSet(pFaultInfo, 0, sizeof(gpuFaultInfo)); return status; @@ -7244,6 +7239,31 @@ NV_STATUS nvGpuOpsGetNonReplayableFaults(gpuFaultInfo *pFaultInfo, return NV_OK; } +NV_STATUS nvGpuOpsFlushReplayableFaultBuffer(struct gpuDevice *device) +{ + NV_STATUS status; + NvHandle hClient = device->session->handle; + RsClient *pClient; + Device *pDevice; + OBJGPU *pGpu; + KernelGmmu *pKernelGmmu; + + status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); + if (status != NV_OK) + return NV_ERR_INVALID_ARGUMENT; + + status = deviceGetByHandle(pClient, device->handle, &pDevice); + if (status != NV_OK) + return NV_ERR_INVALID_ARGUMENT; + + GPU_RES_SET_THREAD_BC_STATE(pDevice); + + pGpu = GPU_RES_GET_GPU(pDevice); + pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + + return kgmmuIssueReplayableFaultBufferFlush_HAL(pGpu, pKernelGmmu); +} + static NV_STATUS nvGpuOpsVerifyChannel(struct gpuAddressSpace *vaSpace, NvHandle hClient, NvHandle hKernelChannel, @@ -7921,7 +7941,7 @@ _shadowMemdescCreate(gpuRetainedChannel *retainedChannel, MEMORY_DESCRIPTOR **ppMemDesc) { NvU32 j; - NvU32 pageSize = pCtxBufferInfo->pageSize; + NvU64 pageSize = pCtxBufferInfo->pageSize; NvU32 numBufferPages = NV_ROUNDUP(pCtxBufferInfo->size, pageSize) / pageSize; MEMORY_DESCRIPTOR *pMemDesc = NULL; MEMORY_DESCRIPTOR *pBufferHandle = (MEMORY_DESCRIPTOR *) pCtxBufferInfo->bufferHandle; @@ -8217,6 +8237,11 @@ NV_STATUS nvGpuOpsGetChannelResourcePtes(struct gpuAddressSpace *vaSpace, if (!vaSpace || !resourceDescriptor || !pGpuExternalMappingInfo) return NV_ERR_INVALID_ARGUMENT; + if (pGpuExternalMappingInfo->mappingPageSize != 0) + { + return NV_ERR_NOT_SUPPORTED; + } + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); status = _nvGpuOpsLocksAcquireAll(RMAPI_LOCK_FLAGS_READ, vaSpace->device->session->handle, diff --git a/src/nvidia/src/kernel/rmapi/param_copy.c b/src/nvidia/src/kernel/rmapi/param_copy.c index 7a9f9ea13..8c2415d7f 100644 --- a/src/nvidia/src/kernel/rmapi/param_copy.c +++ b/src/nvidia/src/kernel/rmapi/param_copy.c @@ -73,6 +73,10 @@ NV_STATUS rmapiParamsAcquire pParamCopy->flags |= RMAPI_PARAM_COPY_FLAGS_IS_DIRECT_USAGE; pKernelParams = NvP64_VALUE(pParamCopy->pUserParams); + + if (pParamCopy->flags & RMAPI_PARAM_COPY_FLAGS_ZERO_BUFFER) + portMemSet(pKernelParams, 0, pParamCopy->paramsSize); + goto done; } diff --git a/src/nvidia/src/kernel/rmapi/resource.c b/src/nvidia/src/kernel/rmapi/resource.c index de1900722..3fc137430 100644 --- a/src/nvidia/src/kernel/rmapi/resource.c +++ b/src/nvidia/src/kernel/rmapi/resource.c @@ -224,6 +224,62 @@ rmresGetMemoryMappingDescriptor_IMPL return NV_ERR_NOT_SUPPORTED; } +NV_STATUS +rmresControlSerialization_Prologue_IMPL +( + RmResource *pResource, + CALL_CONTEXT *pCallContext, + RS_RES_CONTROL_PARAMS_INTERNAL *pParams +) +{ + OBJGPU *pGpu = gpumgrGetGpu(pResource->rpcGpuInstance); + + if (pGpu != NULL && + ((IS_VIRTUAL(pGpu) && (pParams->pCookie->ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_VGPU_HOST)) || + (IS_GSP_CLIENT(pGpu) && (pParams->pCookie->ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_PHYSICAL)))) + { + return serverSerializeCtrlDown(pCallContext, pParams->cmd, pParams->pParams, pParams->paramsSize, &pParams->flags); + } + else + { + // Deserialize and replace the pParams->pParams if necessary + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, serverDeserializeCtrlDown(pCallContext, pParams->cmd, pParams->pParams, pParams->paramsSize, &pParams->flags)); + + if (pParams->flags & NVOS54_FLAGS_FINN_SERIALIZED) + { + pParams->pParams = pCallContext->pDeserializedParams; + pCallContext->bRestoreParams = NV_TRUE; + } + } + + return NV_OK; +} + +void +rmresControlSerialization_Epilogue_IMPL +( + RmResource *pResource, + CALL_CONTEXT *pCallContext, + RS_RES_CONTROL_PARAMS_INTERNAL *pParams +) +{ + OBJGPU *pGpu = gpumgrGetGpu(pResource->rpcGpuInstance); + + if (pGpu != NULL && + ((IS_VIRTUAL(pGpu) && (pParams->pCookie->ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_VGPU_HOST)) || + (IS_GSP_CLIENT(pGpu) && (pParams->pCookie->ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_PHYSICAL)))) + { + NV_ASSERT_OK(serverDeserializeCtrlUp(pCallContext, pParams->cmd, pParams->pParams, pParams->paramsSize, &pParams->flags)); + } + else if (pCallContext->bRestoreParams) + { + pParams->pParams = pCallContext->pSerializedParams; + } + + NV_ASSERT_OK(serverSerializeCtrlUp(pCallContext, pParams->cmd, pParams->pParams, pParams->paramsSize, &pParams->flags)); + serverFreeSerializeStructures(pCallContext, pParams->pParams); +} + NV_STATUS rmresControl_Prologue_IMPL ( @@ -235,11 +291,9 @@ rmresControl_Prologue_IMPL NV_STATUS status = NV_OK; OBJGPU *pGpu = gpumgrGetGpu(pResource->rpcGpuInstance); - if (pGpu == NULL) - return NV_OK; - - if ((IS_VIRTUAL(pGpu) && (pParams->pCookie->ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_VGPU_HOST)) || - (IS_GSP_CLIENT(pGpu) && (pParams->pCookie->ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_PHYSICAL))) + if (pGpu != NULL && + ((IS_VIRTUAL(pGpu) && (pParams->pCookie->ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_VGPU_HOST)) || + (IS_GSP_CLIENT(pGpu) && (pParams->pCookie->ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_PHYSICAL)))) { // // GPU lock is required to protect the RPC buffers. @@ -272,6 +326,7 @@ rmresControl_Prologue_IMPL return (status == NV_OK) ? NV_WARN_NOTHING_TO_DO : status; } + return NV_OK; } diff --git a/src/nvidia/src/kernel/rmapi/resource_desc.h b/src/nvidia/src/kernel/rmapi/resource_desc.h index 4750f50ad..73a384c08 100644 --- a/src/nvidia/src/kernel/rmapi/resource_desc.h +++ b/src/nvidia/src/kernel/rmapi/resource_desc.h @@ -26,32 +26,7 @@ #include "nvtypes.h" #include "nvoc/runtime.h" #include "resserv/rs_access_rights.h" - -// Flags for RS_ENTRY -#define RS_FLAGS_NONE 0 - -#define RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_ALLOC NVBIT(0) ///< GPUs Lock is acquired on allocation -#define RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE NVBIT(1) ///< GPUs Lock is acquired for free -#define RS_FLAGS_ACQUIRE_GPUS_LOCK (RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_ALLOC | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE) - -#define RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK_ON_ALLOC NVBIT(2) ///< GPU Group Lock is acquired on allocation -#define RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK_ON_FREE NVBIT(3) ///< GPU Group Lock is acquired for free -#define RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK (RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK_ON_ALLOC | RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK_ON_FREE) - -#define RS_FLAGS_ALLOC_RPC_TO_VGPU_HOST NVBIT(4) ///< Issue RPC to host to allocate resource for virtual GPUs - -#define RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC NVBIT(5) ///< Acquire the RO API lock for allocation, default is RW API lock - -#define RS_FLAGS_ALLOC_RPC_TO_PHYS_RM NVBIT(6) ///< Issue RPC to allocate resource in physical RM - -#define RS_FLAGS_ALLOC_RPC_TO_ALL (RS_FLAGS_ALLOC_RPC_TO_VGPU_HOST | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM) - -#define RS_FLAGS_INTERNAL_ONLY NVBIT(7) ///< Class cannot be allocated outside of RM - -#define RS_FLAGS_CHANNEL_DESCENDANT_COMMON (RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL) - -#define RS_FREE_PRIORITY_DEFAULT 0 -#define RS_FREE_PRIORITY_HIGH 1 ///< Resources with this priority will be freed ahead of others +#include "resource_desc_flags.h" /** * Information about a RsResource subclass. diff --git a/src/nvidia/src/kernel/rmapi/resource_desc_flags.h b/src/nvidia/src/kernel/rmapi/resource_desc_flags.h new file mode 100644 index 000000000..313d9f1bc --- /dev/null +++ b/src/nvidia/src/kernel/rmapi/resource_desc_flags.h @@ -0,0 +1,58 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef _RESOURCE_DESC_FLAGS_H_ +#define _RESOURCE_DESC_FLAGS_H_ + +// Flags for RS_ENTRY +#define RS_FLAGS_NONE 0 + +#define RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_ALLOC NVBIT(0) ///< GPUs Lock is acquired on allocation +#define RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE NVBIT(1) ///< GPUs Lock is acquired for free +#define RS_FLAGS_ACQUIRE_GPUS_LOCK (RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_ALLOC | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE) + +#define RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK_ON_ALLOC NVBIT(2) ///< GPU Group Lock is acquired on allocation +#define RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK_ON_FREE NVBIT(3) ///< GPU Group Lock is acquired for free +#define RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK (RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK_ON_ALLOC | RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK_ON_FREE) + +#define RS_FLAGS_ALLOC_RPC_TO_VGPU_HOST NVBIT(4) ///< Issue RPC to host to allocate resource for virtual GPUs + +#define RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC NVBIT(5) ///< Acquire the RO API lock for allocation, default is RW API lock + +#define RS_FLAGS_ALLOC_RPC_TO_PHYS_RM NVBIT(6) ///< Issue RPC to allocate resource in physical RM + +#define RS_FLAGS_ALLOC_RPC_TO_ALL (RS_FLAGS_ALLOC_RPC_TO_VGPU_HOST | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM) + +#define RS_FLAGS_INTERNAL_ONLY NVBIT(7) ///< Class cannot be allocated outside of RM + +#define RS_FLAGS_CHANNEL_DESCENDANT_COMMON (RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL) + +#define RS_FREE_PRIORITY_DEFAULT 0 +#define RS_FREE_PRIORITY_HIGH 1 ///< Resources with this priority will be freed ahead of others + +#define RS_FLAGS_ALLOC_NON_PRIVILEGED NVBIT(8) ///< Class is non privileged + +#define RS_FLAGS_ALLOC_PRIVILEGED NVBIT(9) ///< Class requires at least admin privilege + +#define RS_FLAGS_ALLOC_KERNEL_PRIVILEGED NVBIT(10) ///< Class requires at least kernel privilege + +#endif // _RESOURCE_DESC_FLAGS_H_ diff --git a/src/nvidia/src/kernel/rmapi/resource_list.h b/src/nvidia/src/kernel/rmapi/resource_list.h index 45adf1fda..28152ae6a 100644 --- a/src/nvidia/src/kernel/rmapi/resource_list.h +++ b/src/nvidia/src/kernel/rmapi/resource_list.h @@ -97,7 +97,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(RmClientResource)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_NONE, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -107,7 +107,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(RmClientResource)), /* Alloc Param Info */ RS_REQUIRED(NV000F_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -117,7 +117,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(RmClientResource)), /* Alloc Param Info */ RS_OPTIONAL(NvHandle), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -127,7 +127,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(RmClientResource)), /* Alloc Param Info */ RS_REQUIRED(NV_EVENT_BUFFER_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -137,7 +137,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(RmClientResource)), /* Alloc Param Info */ RS_REQUIRED(NV503B_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -147,7 +147,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(RmClientResource)), /* Alloc Param Info */ RS_REQUIRED(NV0060_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_NONE, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -157,7 +157,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(RmClientResource)), /* Alloc Param Info */ RS_OPTIONAL(NV0080_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -167,7 +167,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_REQUIRED(NV83DE_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -177,7 +177,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(RmClientResource)), /* Alloc Param Info */ RS_REQUIRED(NV30F1_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -187,7 +187,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Subdevice), classId(KernelChannel), classId(KernelChannelGroupApi)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -197,7 +197,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NVB2CC_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -207,7 +207,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -217,7 +217,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) /* Channels can have a CHANNEL_GROUP, a DEVICE, or a CONTEXT_SHARE (starting in Volta) as parents */ @@ -229,7 +229,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), /* Alloc Param Info */ RS_REQUIRED(NV_CHANNEL_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -239,7 +239,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), /* Alloc Param Info */ RS_REQUIRED(NV_CHANNEL_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -249,7 +249,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), /* Alloc Param Info */ RS_REQUIRED(NV_CHANNEL_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -259,7 +259,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), /* Alloc Param Info */ RS_REQUIRED(NV_CHANNEL_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -269,7 +269,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), /* Alloc Param Info */ RS_REQUIRED(NV_CHANNEL_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -279,7 +279,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), /* Alloc Param Info */ RS_REQUIRED(NV_CHANNEL_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -289,7 +289,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), /* Alloc Param Info */ RS_REQUIRED(NV_CHANNEL_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -299,7 +299,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), /* Alloc Param Info */ RS_REQUIRED(NV_CHANNEL_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -309,7 +309,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), /* Alloc Param Info */ RS_REQUIRED(NV_CHANNEL_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -319,7 +319,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), /* Alloc Param Info */ RS_REQUIRED(NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_KERNEL_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -329,7 +329,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannelGroupApi)), /* Alloc Param Info */ RS_REQUIRED(NV_CTXSHARE_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -339,7 +339,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannelGroupApi), classId(KernelChannel)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC | RS_FLAGS_INTERNAL_ONLY, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC | RS_FLAGS_INTERNAL_ONLY, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -349,7 +349,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_OPTIONAL(NV2080_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -359,7 +359,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_OPTIONAL(NV2081_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -369,7 +369,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_OPTIONAL(NV2082_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -379,7 +379,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_REQUIRED(NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -389,7 +389,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -399,7 +399,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device), classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NV_MEMORY_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -409,7 +409,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_REQUIRED(NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -419,7 +419,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_REQUIRED(NV_MEMORY_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -429,7 +429,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_REQUIRED(NV_MEMORY_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -439,7 +439,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_REQUIRED(NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -449,7 +449,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NV_MEMORY_MAPPER_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -459,7 +459,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_REQUIRED(NV_OS_DESC_MEMORY_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -469,7 +469,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(RmClientResource)), /* Alloc Param Info */ RS_REQUIRED(NV_MEMORY_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_NONE, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -479,7 +479,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -489,7 +489,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device), classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -499,7 +499,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device), classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NV_MEMORY_LIST_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -509,7 +509,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device), classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NV_MEMORY_LIST_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -519,7 +519,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device), classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NV_MEMORY_LIST_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -529,7 +529,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_REQUIRED(NV_FLA_MEMORY_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -539,7 +539,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NV00F8_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -549,7 +549,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device), classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NV_VASPACE_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -559,7 +559,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(RmClientResource)), /* Alloc Param Info */ RS_REQUIRED(NV00FD_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) /* Subdevice Children: */ @@ -570,7 +570,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -580,7 +580,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NVA084_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -590,7 +590,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_OPTIONAL(NV503C_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -600,7 +600,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -610,7 +610,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -620,7 +620,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -630,7 +630,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -640,7 +640,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -650,7 +650,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NV00DB_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -660,7 +660,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NV00DE_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -670,7 +670,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -680,7 +680,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -690,7 +690,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -700,7 +700,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_OPTIONAL(NV_HOPPER_USERMODE_A_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -710,7 +710,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -720,7 +720,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -730,7 +730,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -740,7 +740,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_KERNEL_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -750,7 +750,17 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Required Access Rights */ RS_ACCESS_NONE +) +RS_ENTRY( + /* External Class */ MMU_VIDMEM_ACCESS_BIT_BUFFER, + /* Internal Class */ VidmemAccessBitBuffer, + /* Multi-Instance */ NV_FALSE, + /* Parents */ RS_LIST(classId(Subdevice)), + /* Alloc Param Info */ RS_REQUIRED(NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -760,7 +770,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NVC637_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -770,7 +780,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(GPUInstanceSubscription)), /* Alloc Param Info */ RS_REQUIRED(NVC638_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -780,7 +790,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(RmClientResource)), /* Alloc Param Info */ RS_REQUIRED(NVC639_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_NONE, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -790,7 +800,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(RmClientResource)), /* Alloc Param Info */ RS_REQUIRED(NVC640_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_NONE, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED, /* Required Access Rights */ RS_ACCESS_NONE ) /* Display classes: */ @@ -801,7 +811,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -811,7 +821,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -821,7 +831,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -831,7 +841,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -841,7 +851,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -851,7 +861,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device), classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NV_VBLANK_CALLBACK_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_KERNEL_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -861,7 +871,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(DispCommon)), /* Alloc Param Info */ RS_REQUIRED(NV0092_RG_LINE_CALLBACK_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_KERNEL_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -871,7 +881,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(NvDispApi)), /* Alloc Param Info */ RS_REQUIRED(NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -881,7 +891,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(NvDispApi)), /* Alloc Param Info */ RS_REQUIRED(NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -891,7 +901,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(NvDispApi)), /* Alloc Param Info */ RS_REQUIRED(NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -901,7 +911,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(NvDispApi)), /* Alloc Param Info */ RS_REQUIRED(NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -911,7 +921,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(NvDispApi)), /* Alloc Param Info */ RS_REQUIRED(NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -921,7 +931,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(NvDispApi)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -931,7 +941,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(NvDispApi)), /* Alloc Param Info */ RS_REQUIRED(NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -941,10 +951,19 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(NvDispApi)), /* Alloc Param Info */ RS_REQUIRED(NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Required Access Rights */ RS_ACCESS_NONE +) +RS_ENTRY( + /* External Class */ NVC77D_CORE_CHANNEL_DMA, + /* Internal Class */ DispChannelDma, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(NvDispApi)), + /* Alloc Param Info */ RS_REQUIRED(NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) - RS_ENTRY( NVC77D_CORE_CHANNEL_DMA, DispChannelDma, NV_TRUE, RS_LIST(classId(NvDispApi)), RS_REQUIRED(NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS), RS_FREE_PRIORITY_DEFAULT, RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, RS_ACCESS_NONE ) RS_ENTRY( /* External Class */ NVC77F_ANY_CHANNEL_DMA, /* Internal Class */ DispChannelDma, @@ -952,7 +971,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(NvDispApi)), /* Alloc Param Info */ RS_REQUIRED(NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -962,7 +981,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(NvDispApi)), /* Alloc Param Info */ RS_REQUIRED(NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -972,7 +991,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(NvDispApi)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -982,7 +1001,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(NvDispApi)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) /* Classes allocated under channel: */ @@ -993,7 +1012,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_REQUIRED(NV9072_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON| RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1003,7 +1022,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1013,7 +1032,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV5080_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1023,7 +1042,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1033,7 +1052,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1043,7 +1062,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NVB0B5_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1053,7 +1072,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NVB0B5_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1063,7 +1082,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NVB0B5_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1073,7 +1092,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NVB0B5_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1083,7 +1102,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NVB0B5_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1093,7 +1112,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NVB0B5_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1103,7 +1122,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_BSP_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1113,7 +1132,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_BSP_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1123,7 +1142,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_BSP_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1133,7 +1152,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_BSP_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1143,7 +1162,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_BSP_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1153,7 +1172,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_NVJPG_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1163,7 +1182,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_NVJPG_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1173,7 +1192,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_NVJPG_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1183,7 +1202,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_OFA_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1193,7 +1212,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_OFA_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1203,7 +1222,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_OFA_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1213,7 +1232,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_OFA_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1223,7 +1242,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_MSENC_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1233,7 +1252,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_MSENC_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1243,7 +1262,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_MSENC_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1253,7 +1272,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_MSENC_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1263,7 +1282,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_GR_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1273,7 +1292,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_GR_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1283,7 +1302,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_GR_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1293,7 +1312,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_GR_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1303,7 +1322,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_GR_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1313,7 +1332,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_GR_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1323,7 +1342,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_GR_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1333,7 +1352,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_GR_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1343,7 +1362,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_GR_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1353,7 +1372,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_GR_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1363,7 +1382,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_GR_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1373,7 +1392,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_OPTIONAL(NV_GR_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1383,7 +1402,7 @@ RS_ENTRY( /* Parents */ RS_ANY_PARENT, /* Alloc Param Info */ RS_REQUIRED(NV_CONTEXT_DMA_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1393,7 +1412,7 @@ RS_ENTRY( /* Parents */ RS_ANY_PARENT, /* Alloc Param Info */ RS_REQUIRED(NV0005_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1403,7 +1422,7 @@ RS_ENTRY( /* Parents */ RS_ANY_PARENT, /* Alloc Param Info */ RS_REQUIRED(NV0005_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1413,7 +1432,7 @@ RS_ENTRY( /* Parents */ RS_ANY_PARENT, /* Alloc Param Info */ RS_REQUIRED(NV0005_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1423,7 +1442,7 @@ RS_ENTRY( /* Parents */ RS_ANY_PARENT, /* Alloc Param Info */ RS_REQUIRED(NV0005_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1433,7 +1452,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) diff --git a/src/nvidia/src/kernel/rmapi/rmapi.c b/src/nvidia/src/kernel/rmapi/rmapi.c index d8005aa5c..2ca7d1123 100644 --- a/src/nvidia/src/kernel/rmapi/rmapi.c +++ b/src/nvidia/src/kernel/rmapi/rmapi.c @@ -44,7 +44,8 @@ typedef struct NvU64 timestamp; LOCK_TRACE_INFO traceInfo; NvU64 tlsEntryId; - + volatile NvU32 contentionCount; + NvU32 lowPriorityAging; } RMAPI_LOCK; RsServer g_resServ; @@ -178,8 +179,8 @@ _rmapiInitInterface pRmApi->AllocWithHandle = rmapiAllocWithHandle; pRmApi->AllocWithSecInfo = pRmApi->bTlsInternal ? rmapiAllocWithSecInfo : rmapiAllocWithSecInfoTls; - pRmApi->FreeClientList = rmapiFreeClientList; - pRmApi->FreeClientListWithSecInfo = pRmApi->bTlsInternal ? rmapiFreeClientListWithSecInfo : rmapiFreeClientListWithSecInfoTls; + pRmApi->DisableClients = rmapiDisableClients; + pRmApi->DisableClientsWithSecInfo = pRmApi->bTlsInternal ? rmapiDisableClientsWithSecInfo : rmapiDisableClientsWithSecInfoTls; pRmApi->Free = rmapiFree; pRmApi->FreeWithSecInfo = pRmApi->bTlsInternal ? rmapiFreeWithSecInfo : rmapiFreeWithSecInfoTls; @@ -291,6 +292,14 @@ _rmapiLockAlloc(void) g_resServ.bUnlockedParamCopy = NV_TRUE; NvU32 val = 0; + + if ((osReadRegistryDword(NULL, + NV_REG_STR_RM_LOCKING_LOW_PRIORITY_AGING, + &val) == NV_OK)) + { + g_RmApiLock.lowPriorityAging = val; + } + if ((osReadRegistryDword(NULL, NV_REG_STR_RM_PARAM_COPY_NO_LOCK, &val) == NV_OK)) @@ -356,6 +365,7 @@ rmapiLockAcquire(NvU32 flags, NvU32 module) } else { + // Conditional acquires don't care about contention or priority if (portSyncRwLockAcquireWriteConditional(g_RmApiLock.pLock)) { g_RmApiLock.threadId = threadId; @@ -375,7 +385,23 @@ rmapiLockAcquire(NvU32 flags, NvU32 module) else { - portSyncRwLockAcquireWrite(g_RmApiLock.pLock); + if (flags & RMAPI_LOCK_FLAGS_LOW_PRIORITY) + { + NvS32 age = g_RmApiLock.lowPriorityAging; + portSyncRwLockAcquireWrite(g_RmApiLock.pLock); + while ((g_RmApiLock.contentionCount > 0) && (age--)) + { + portSyncRwLockReleaseWrite(g_RmApiLock.pLock); + osDelay(10); + portSyncRwLockAcquireWrite(g_RmApiLock.pLock); + } + } + else + { + portAtomicIncrementU32(&g_RmApiLock.contentionCount); + portSyncRwLockAcquireWrite(g_RmApiLock.pLock); + portAtomicDecrementU32(&g_RmApiLock.contentionCount); + } g_RmApiLock.threadId = threadId; } } diff --git a/src/nvidia/src/kernel/rmapi/rmapi_cache.c b/src/nvidia/src/kernel/rmapi/rmapi_cache.c index 289007b4f..a9fab785e 100644 --- a/src/nvidia/src/kernel/rmapi/rmapi_cache.c +++ b/src/nvidia/src/kernel/rmapi/rmapi_cache.c @@ -31,6 +31,9 @@ #include "rmapi/rmapi.h" #include "rmapi/rmapi_utils.h" #include "ctrl/ctrl0000/ctrl0000system.h" +#include "ctrl/ctrl2080/ctrl2080gpu.h" +#include "ctrl/ctrl2080/ctrl2080fifo.h" +#include "ctrl/ctrl2080/ctrl2080bus.h" typedef struct { @@ -81,12 +84,37 @@ static struct { PORT_RWLOCK *pLock; } RmapiControlCache; +enum CACHE_LOCK_TYPE +{ + LOCK_EXCLUSIVE, + LOCK_SHARED +}; + +static void _cacheLockAcquire(enum CACHE_LOCK_TYPE lockType) +{ + if (lockType == LOCK_EXCLUSIVE) + portSyncRwLockAcquireWrite(RmapiControlCache.pLock); + else + portSyncRwLockAcquireRead(RmapiControlCache.pLock); +} + +static void _cacheLockRelease(enum CACHE_LOCK_TYPE lockType) +{ + if (lockType == LOCK_EXCLUSIVE) + portSyncRwLockReleaseWrite(RmapiControlCache.pLock); + else + portSyncRwLockReleaseRead(RmapiControlCache.pLock); +} + +static RmapiControlCacheEntry* _getOrInitCacheEntry(NvU64 key1, NvU64 key2, NvBool bSet, + NvU32 allocSize, NvBool *pbParamAllocated); + NvBool rmapiControlIsCacheable(NvU32 flags, NvU32 accessRight, NvBool bAllowInternal) { if (RmapiControlCache.mode == NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE) return NV_FALSE; - if (!(flags & RMCTRL_FLAGS_CACHEABLE)) + if (!(flags & RMCTRL_FLAGS_CACHEABLE_ANY)) return NV_FALSE; // @@ -169,7 +197,7 @@ NV_STATUS rmapiControlCacheSetGpuInstForObject NV_PRINTF(LEVEL_INFO, "gpu inst set for 0x%x 0x%x: 0x%x\n", hClient, hObject, gpuInst); - portSyncRwLockAcquireWrite(RmapiControlCache.pLock); + _cacheLockAcquire(LOCK_EXCLUSIVE); entry = mapFind(&RmapiControlCache.objectToGpuInstMap, _handlesToGpuInstKey(hClient, hObject)); if (entry != NULL) @@ -193,7 +221,7 @@ NV_STATUS rmapiControlCacheSetGpuInstForObject *entry = gpuInst; done: - portSyncRwLockReleaseWrite(RmapiControlCache.pLock); + _cacheLockRelease(LOCK_EXCLUSIVE); return status; } @@ -258,7 +286,7 @@ static void _rmapiControlCacheFreeGpuInstForClient(NvHandle hClient) } } -NV_STATUS rmapiControlCacheGet +static NV_STATUS _rmapiControlCacheGet ( NvHandle hClient, NvHandle hObject, @@ -271,11 +299,14 @@ NV_STATUS rmapiControlCacheGet NvU32 gpuInst; NV_STATUS status = NV_OK; - if (RmapiControlCache.mode == NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY) - return NV_ERR_OBJECT_NOT_FOUND; + _cacheLockAcquire(LOCK_SHARED); - NV_PRINTF(LEVEL_INFO, "control cache lookup for 0x%x 0x%x 0x%x\n", hClient, hObject, cmd); - portSyncRwLockAcquireRead(RmapiControlCache.pLock); + if (rmapiControlCacheGetMode() == NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE) + { + // unexpected mode change. + status = NV_ERR_INVALID_STATE; + goto done; + } if (_isCmdSystemWide(cmd)) { @@ -288,7 +319,7 @@ NV_STATUS rmapiControlCacheGet goto done; } - entry = multimapFindItem(&RmapiControlCache.gpusControlCache, gpuInst, cmd); + entry = _getOrInitCacheEntry(gpuInst, cmd, NV_FALSE, 0, NULL); if (entry == NULL || entry->params == NULL) { status = NV_ERR_OBJECT_NOT_FOUND; @@ -296,13 +327,12 @@ NV_STATUS rmapiControlCacheGet } portMemCopy(params, paramsSize, entry->params, paramsSize); - NV_PRINTF(LEVEL_INFO, "control cache for 0x%x 0x%x 0x%x: entry %p\n", hClient, hObject, cmd, entry); done: - portSyncRwLockReleaseRead(RmapiControlCache.pLock); + _cacheLockRelease(LOCK_SHARED); return status; } -NV_STATUS rmapiControlCacheSet +static NV_STATUS _rmapiControlCacheSet ( NvHandle hClient, NvHandle hObject, @@ -313,12 +343,17 @@ NV_STATUS rmapiControlCacheSet { NV_STATUS status = NV_OK; RmapiControlCacheEntry* entry = NULL; - GpusControlCacheSubmap* insertedSubmap = NULL; NvU32 gpuInst; + NvBool bParamsAllocated; - NV_PRINTF(LEVEL_INFO, "control cache set for 0x%x 0x%x 0x%x\n", hClient, hObject, cmd); + _cacheLockAcquire(LOCK_EXCLUSIVE); - portSyncRwLockAcquireWrite(RmapiControlCache.pLock); + if (rmapiControlCacheGetMode() == NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE) + { + // unexpected mode change. + status = NV_ERR_INVALID_STATE; + goto done; + } if (_isCmdSystemWide(cmd)) { @@ -331,23 +366,7 @@ NV_STATUS rmapiControlCacheSet goto done; } - entry = multimapFindItem(&RmapiControlCache.gpusControlCache, gpuInst, cmd); - - if (entry == NULL) - { - if (multimapFindSubmap(&RmapiControlCache.gpusControlCache, gpuInst) == NULL) - { - insertedSubmap = multimapInsertSubmap(&RmapiControlCache.gpusControlCache, gpuInst); - if (insertedSubmap == NULL) - { - status = NV_ERR_NO_MEMORY; - goto done; - } - } - - entry = multimapInsertItemNew(&RmapiControlCache.gpusControlCache, gpuInst, cmd); - } - + entry = _getOrInitCacheEntry(gpuInst, cmd, NV_TRUE, paramsSize, &bParamsAllocated); if (entry == NULL) { status = NV_ERR_NO_MEMORY; @@ -355,13 +374,15 @@ NV_STATUS rmapiControlCacheSet } // - // Skip duplicated cache insertion. Duplicated cache set happens when + // A succeeded getOrInit call without params allocated implies + // duplicated cache insertion that should be skipped. + // Duplicated cache set happens when // 1. Parallel controls call into RM before first cache set. // All threads will attempt cache set after the control calls. // 2. Cache already set by RPC to GSP path // 3. Cache in verify only mode // - if (entry->params != NULL) + if (!bParamsAllocated) { if (RmapiControlCache.mode == NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY) { @@ -371,37 +392,623 @@ NV_STATUS rmapiControlCacheSet goto done; } - entry->params = portMemAllocNonPaged(paramsSize); + portMemCopy(entry->params, paramsSize, params, paramsSize); + +done: + _cacheLockRelease(LOCK_EXCLUSIVE); + return status; +} + +// +// Common function to find existing or generate new cache entry +// For cache get, we return the cache map query result directly +// For cache set, we generate new cache entry if there's no existing entry +// in the map. +// +// key1 [IN] +// First key for the multimap entry +// key2 [IN] +// Second key for the multimap entry +// bSet [IN] +// If the query is for cache set or cache get +// allocSize [IN] +// For cache set only. +// The size to allocate for new cache entry +// pbParamsAllocated [OUT] +// For cache set only. +// Indicate if we allocated new memory for cache entry +// A cache set without memory allocation implies there's an existng entry. +// +static RmapiControlCacheEntry* +_getOrInitCacheEntry +( + NvU64 key1, + NvU64 key2, + NvBool bSet, + NvU32 allocSize, + NvBool *pbParamsAllocated +) +{ + RmapiControlCacheEntry *entry = NULL; + GpusControlCacheSubmap *insertedSubmap = NULL; + + entry = multimapFindItem(&RmapiControlCache.gpusControlCache, key1, key2); + + // for cache get, return map find result directly + if (!bSet) + return entry; + + // for cache set, try to init entry if not valid + if (entry == NULL) + { + if (multimapFindSubmap(&RmapiControlCache.gpusControlCache, key1) == NULL) + { + insertedSubmap = multimapInsertSubmap(&RmapiControlCache.gpusControlCache, key1); + if (insertedSubmap == NULL) + goto failed; + } + + entry = multimapInsertItemNew(&RmapiControlCache.gpusControlCache, key1, key2); + } + + if (entry == NULL) + goto failed_free_submap; + if (entry->params == NULL) { - status = NV_ERR_NO_MEMORY; + entry->params = portMemAllocNonPaged(allocSize); + if (entry->params == NULL) + goto failed_free_entry; + + portMemSet(entry->params, 0, allocSize); + + if (pbParamsAllocated != NULL) + *pbParamsAllocated = NV_TRUE; + } + else if (pbParamsAllocated != NULL) + { + *pbParamsAllocated = NV_FALSE; + } + + return entry; + +failed_free_entry: + if (entry != NULL) + multimapRemoveItem(&RmapiControlCache.gpusControlCache, entry); +failed_free_submap: + if (insertedSubmap != NULL) + multimapRemoveSubmap(&RmapiControlCache.gpusControlCache, insertedSubmap); +failed: + return NULL; +} + +static NvBool _isGpuGetInfoIndexCacheable(NvU32 index) +{ + switch (index) + { + case NV2080_CTRL_GPU_INFO_INDEX_MINOR_REVISION_EXT: + case NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV0: + case NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV1: + case NV2080_CTRL_GPU_INFO_INDEX_SYSMEM_ACCESS: + case NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD: + case NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE: + case NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED: + case NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT: + case NV2080_CTRL_GPU_INFO_INDEX_SPLIT_VAS_MGMT_SERVER_CLIENT_RM: + case NV2080_CTRL_GPU_INFO_INDEX_GPU_SM_VERSION: + case NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED: + case NV2080_CTRL_GPU_INFO_INDEX_DISPLAY_ENABLED: + case NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED: + case NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY: + case NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY: + case NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU: + case NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY: + return NV_TRUE; + default: + return NV_FALSE; + } +} + +static NvBool _isFifoGetInfoIndexCacheable(NvU32 index) +{ + switch (index) + { + case NV2080_CTRL_FIFO_INFO_INDEX_INSTANCE_TOTAL: + case NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS: + case NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNELS_PER_GROUP: + case NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP: + case NV2080_CTRL_FIFO_INFO_INDEX_BAR1_USERD_START_OFFSET: + case NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE: + return NV_TRUE; + default: + return NV_FALSE; + } +} + +static NvBool _isBusGetInfoIndexCacheable(NvU32 index) +{ + switch (index) + { + case NV2080_CTRL_BUS_INFO_INDEX_TYPE: + case NV2080_CTRL_BUS_INFO_INDEX_INTLINE: + case NV2080_CTRL_BUS_INFO_INDEX_CAPS: + case NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CAPS: + case NV2080_CTRL_BUS_INFO_INDEX_COHERENT_DMA_FLAGS: + case NV2080_CTRL_BUS_INFO_INDEX_NONCOHERENT_DMA_FLAGS: + case NV2080_CTRL_BUS_INFO_INDEX_BUS_NUMBER: + case NV2080_CTRL_BUS_INFO_INDEX_DEVICE_NUMBER: + case NV2080_CTRL_BUS_INFO_INDEX_DOMAIN_NUMBER: + case NV2080_CTRL_BUS_INFO_INDEX_INTERFACE_TYPE: + case NV2080_CTRL_BUS_INFO_INDEX_GPU_INTERFACE_TYPE: + return NV_TRUE; + default: + return NV_FALSE; + } +} + +static NvBool _isGetInfoIndexCacheable(NvU32 cmd, NvU32 index) +{ + switch (cmd) + { + case NV2080_CTRL_CMD_GPU_GET_INFO_V2: + return _isGpuGetInfoIndexCacheable(index); + case NV2080_CTRL_CMD_FIFO_GET_INFO: + return _isFifoGetInfoIndexCacheable(index); + case NV2080_CTRL_CMD_BUS_GET_INFO_V2: + return _isBusGetInfoIndexCacheable(index); + } + + return NV_FALSE; +} + +// +// For GET_INFO controls, we use an array of getInfoCacheEntry to store the +// cached value. +// +// The length of the array is the max list length of each control and is +// enough to store the cached value of all indexes. +// +// The Nth item in the array, array[N], represent the cache state of the info +// whose index value is N. If the info is cached, array[N].valid is NV_TRUE +// and the cached value is stored in array[N].data. +// array[N].valid is NV_FALSE if the info is not cached. +// +typedef struct GetInfoCacheEntry { + NvBool valid; + NvU32 data; +} GetInfoCacheEntry; + +static NV_STATUS _getInfoCacheHandler +( + NvHandle hClient, + NvHandle hObject, + NvU32 cmd, + NVXXXX_CTRL_XXX_INFO *pInfo, + NvU32 listSize, + NvU32 listSizeLimit, + NvBool bSet +) +{ + NV_STATUS status = NV_OK; + NvU32 i = 0; + NvU32 gpuInst; + RmapiControlCacheEntry *entry = NULL; + GetInfoCacheEntry *cachedTable = NULL; + const NvU32 allocSize = sizeof(GetInfoCacheEntry) * listSizeLimit; + enum CACHE_LOCK_TYPE lockType = bSet ? LOCK_EXCLUSIVE : LOCK_SHARED; + + if (listSize <= 0 || listSize > listSizeLimit || pInfo == NULL) + { + return NV_ERR_INVALID_PARAMETER; + } + + _cacheLockAcquire(lockType); + + if (rmapiControlCacheGetMode() == NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE) + { + // unexpected mode change. + status = NV_ERR_INVALID_STATE; goto done; } - portMemCopy(entry->params, paramsSize, params, paramsSize); - NV_PRINTF(LEVEL_INFO, - "control cache set for 0x%x 0x%x 0x%x succeed, entry: %p\n", - hClient, hObject, cmd, entry); + status = _rmapiControlCacheGetGpuInstForObject(hClient, hObject, &gpuInst); + if (status != NV_OK) + goto done; + + entry = _getOrInitCacheEntry(gpuInst, cmd, bSet, allocSize, NULL); + + if (entry == NULL || entry->params == NULL) + { + status = bSet ? NV_ERR_NO_MEMORY : NV_ERR_OBJECT_NOT_FOUND; + goto done; + } + + cachedTable = (GetInfoCacheEntry*)entry->params; + + for (i = 0; i < listSize; ++i) + { + const NvU32 index = pInfo[i].index; + + if (index >= listSizeLimit) + { + status = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + if (bSet) + { + if (_isGetInfoIndexCacheable(cmd, index)) + { + if (cachedTable[index].valid) + { + NV_ASSERT(cachedTable[index].data == pInfo[i].data); + } + else + { + cachedTable[index].valid = NV_TRUE; + cachedTable[index].data = pInfo[i].data; + } + } + } + else + { + // if any of the entry is not cacheable or not in the cache, skip the whole cmd + if (!_isGetInfoIndexCacheable(cmd, index) || !cachedTable[index].valid) + { + status = NV_ERR_OBJECT_NOT_FOUND; + goto done; + } + } + } + + if (!bSet) + { + for (i = 0; i < listSize; ++i) + pInfo[i].data = cachedTable[pInfo[i].index].data; + } done: - if (status != NV_OK) + + if (status != NV_OK && bSet) { - /* To avoid leaking memory, remove the newly inserted empty submap and entry */ if (entry != NULL) { portMemFree(entry->params); multimapRemoveItem(&RmapiControlCache.gpusControlCache, entry); } - - if (insertedSubmap != NULL) - multimapRemoveSubmap(&RmapiControlCache.gpusControlCache, insertedSubmap); } - portSyncRwLockReleaseWrite(RmapiControlCache.pLock); + _cacheLockRelease(lockType); return status; } +typedef struct GpuNameStringCacheEntry +{ + NvBool bAsciiValid; + NvBool bUnicodeValid; + NvU8 ascii[NV2080_GPU_MAX_NAME_STRING_LENGTH]; + NvU16 unicode[NV2080_GPU_MAX_NAME_STRING_LENGTH]; +} GpuNameStringCacheEntry; + +NV_STATUS _gpuNameStringGet +( + NvHandle hClient, + NvHandle hObject, + NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS *pParams +) +{ + NvU32 gpuInst; + NV_STATUS status = NV_OK; + RmapiControlCacheEntry *entry = NULL; + GpuNameStringCacheEntry *cachedParams = NULL; + + _cacheLockAcquire(LOCK_SHARED); + + if (rmapiControlCacheGetMode() == NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE) + { + // unexpected mode change. + status = NV_ERR_INVALID_STATE; + goto done; + } + + status = _rmapiControlCacheGetGpuInstForObject(hClient, hObject, &gpuInst); + if (status != NV_OK) + goto done; + + entry = _getOrInitCacheEntry(gpuInst, NV2080_CTRL_CMD_GPU_GET_NAME_STRING, + NV_FALSE, 0, NULL); + if (entry == NULL || entry->params == NULL) + { + status = NV_ERR_OBJECT_NOT_FOUND; + goto done; + } + + cachedParams = (GpuNameStringCacheEntry *)entry->params; + + switch (pParams->gpuNameStringFlags) + { + case NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_ASCII: + if (!cachedParams->bAsciiValid) + { + status = NV_ERR_OBJECT_NOT_FOUND; + goto done; + } + portMemCopy(pParams->gpuNameString.ascii, + sizeof(pParams->gpuNameString.ascii), + cachedParams->ascii, + sizeof(pParams->gpuNameString.ascii)); + break; + + case NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_UNICODE: + if (!cachedParams->bUnicodeValid) + { + status = NV_ERR_OBJECT_NOT_FOUND; + goto done; + } + portMemCopy(pParams->gpuNameString.unicode, + sizeof(pParams->gpuNameString.unicode), + cachedParams->unicode, + sizeof(pParams->gpuNameString.unicode)); + break; + + default: + NV_PRINTF(LEVEL_ERROR, "Unknown gpu name string flag: %u\n", pParams->gpuNameStringFlags); + status = NV_ERR_OBJECT_NOT_FOUND; + goto done; + } +done: + _cacheLockRelease(LOCK_SHARED); + return status; +} + +NV_STATUS _gpuNameStringSet +( + NvHandle hClient, + NvHandle hObject, + const NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS *pParams +) +{ + NvU32 gpuInst; + NV_STATUS status; + RmapiControlCacheEntry *entry = NULL; + GpuNameStringCacheEntry *cachedParams = NULL; + + _cacheLockAcquire(LOCK_EXCLUSIVE); + + if (rmapiControlCacheGetMode() == NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE) + { + // unexpected mode change. + status = NV_ERR_INVALID_STATE; + goto done; + } + + status = _rmapiControlCacheGetGpuInstForObject(hClient, hObject, &gpuInst); + if (status != NV_OK) + goto done; + + entry = _getOrInitCacheEntry(gpuInst, NV2080_CTRL_CMD_GPU_GET_NAME_STRING, + NV_TRUE, sizeof(GpuNameStringCacheEntry), NULL); + if (entry == NULL) + { + status = NV_ERR_NO_MEMORY; + goto done; + } + + cachedParams = (GpuNameStringCacheEntry *)entry->params; + + switch (pParams->gpuNameStringFlags) + { + case NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_ASCII: + if (cachedParams->bAsciiValid) + { + NV_ASSERT( + portMemCmp(pParams->gpuNameString.ascii, + cachedParams->ascii, + sizeof(pParams->gpuNameString.ascii)) == 0); + } + else + { + portMemCopy(cachedParams->ascii, + sizeof(pParams->gpuNameString.ascii), + pParams->gpuNameString.ascii, + sizeof(pParams->gpuNameString.ascii)); + cachedParams->bAsciiValid = NV_TRUE; + } + break; + + case NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_UNICODE: + if (cachedParams->bUnicodeValid) + { + NV_ASSERT( + portMemCmp(pParams->gpuNameString.unicode, + cachedParams->unicode, + sizeof(pParams->gpuNameString.unicode)) == 0); + } + else + { + portMemCopy(cachedParams->unicode, + sizeof(pParams->gpuNameString.unicode), + pParams->gpuNameString.unicode, + sizeof(pParams->gpuNameString.unicode)); + cachedParams->bUnicodeValid = NV_TRUE; + } + break; + + default: + NV_PRINTF(LEVEL_ERROR, "Unknown gpu name string flag: %u\n", pParams->gpuNameStringFlags); + status = NV_ERR_INVALID_PARAMETER; + goto done; + } + +done: + if (status != NV_OK) + { + if (entry != NULL) + { + if (entry->params) + portMemFree(entry->params); + multimapRemoveItem(&RmapiControlCache.gpusControlCache, entry); + } + } + _cacheLockRelease(LOCK_EXCLUSIVE); + + return status; +} + +NV_STATUS _rmapiControlCacheGetByInput +( + NvHandle hClient, + NvHandle hObject, + NvU32 cmd, + void* params, + NvU32 paramsSize +) +{ + switch (cmd) + { + case NV2080_CTRL_CMD_GPU_GET_INFO_V2: + return _getInfoCacheHandler(hClient, hObject, cmd, + ((NV2080_CTRL_GPU_GET_INFO_V2_PARAMS*)params)->gpuInfoList, + ((NV2080_CTRL_GPU_GET_INFO_V2_PARAMS*)params)->gpuInfoListSize, + NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE, + NV_FALSE); + + case NV2080_CTRL_CMD_FIFO_GET_INFO: + return _getInfoCacheHandler(hClient, hObject, cmd, + ((NV2080_CTRL_FIFO_GET_INFO_PARAMS*)params)->fifoInfoTbl, + ((NV2080_CTRL_FIFO_GET_INFO_PARAMS*)params)->fifoInfoTblSize, + NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES, + NV_FALSE); + + case NV2080_CTRL_CMD_BUS_GET_INFO_V2: + return _getInfoCacheHandler(hClient, hObject, cmd, + ((NV2080_CTRL_BUS_GET_INFO_V2_PARAMS*)params)->busInfoList, + ((NV2080_CTRL_BUS_GET_INFO_V2_PARAMS*)params)->busInfoListSize, + NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE, + NV_FALSE); + + case NV2080_CTRL_CMD_GPU_GET_NAME_STRING: + return _gpuNameStringGet(hClient, hObject, params); + default: + NV_PRINTF(LEVEL_WARNING, "No implementation for cacheable by input cmd 0x%x\n", cmd); + return NV_ERR_OBJECT_NOT_FOUND; + } +} + +NV_STATUS _rmapiControlCacheSetByInput +( + NvHandle hClient, + NvHandle hObject, + NvU32 cmd, + void* params, + NvU32 paramsSize +) +{ + switch (cmd) + { + case NV2080_CTRL_CMD_GPU_GET_INFO_V2: + return _getInfoCacheHandler(hClient, hObject, cmd, + ((NV2080_CTRL_GPU_GET_INFO_V2_PARAMS*)params)->gpuInfoList, + ((NV2080_CTRL_GPU_GET_INFO_V2_PARAMS*)params)->gpuInfoListSize, + NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE, + NV_TRUE); + + case NV2080_CTRL_CMD_FIFO_GET_INFO: + return _getInfoCacheHandler(hClient, hObject, cmd, + ((NV2080_CTRL_FIFO_GET_INFO_PARAMS*)params)->fifoInfoTbl, + ((NV2080_CTRL_FIFO_GET_INFO_PARAMS*)params)->fifoInfoTblSize, + NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES, + NV_TRUE); + + case NV2080_CTRL_CMD_BUS_GET_INFO_V2: + return _getInfoCacheHandler(hClient, hObject, cmd, + ((NV2080_CTRL_BUS_GET_INFO_V2_PARAMS*)params)->busInfoList, + ((NV2080_CTRL_BUS_GET_INFO_V2_PARAMS*)params)->busInfoListSize, + NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE, + NV_TRUE); + + case NV2080_CTRL_CMD_GPU_GET_NAME_STRING: + return _gpuNameStringSet(hClient, hObject, params); + default: + NV_PRINTF(LEVEL_WARNING, "No implementation for cacheable by input cmd 0x%x\n", cmd); + return NV_ERR_OBJECT_NOT_FOUND; + } +} + +NV_STATUS rmapiControlCacheGet +( + NvHandle hClient, + NvHandle hObject, + NvU32 cmd, + void* params, + NvU32 paramsSize +) +{ + NV_STATUS status = NV_OK; + NvU32 flags = 0; + + if (RmapiControlCache.mode == NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY) + return NV_ERR_OBJECT_NOT_FOUND; + + status = rmapiutilGetControlInfo(cmd, &flags, NULL); + if (status != NV_OK) + goto done; + + switch ((flags & RMCTRL_FLAGS_CACHEABLE_ANY)) + { + case RMCTRL_FLAGS_CACHEABLE: + status = _rmapiControlCacheGet(hClient, hObject, cmd, params, paramsSize); + break; + case RMCTRL_FLAGS_CACHEABLE_BY_INPUT: + status = _rmapiControlCacheGetByInput(hClient, hObject, cmd, params, paramsSize); + break; + default: + NV_PRINTF(LEVEL_ERROR, "Invalid cacheable flag 0x%x for cmd 0x%x\n", flags, cmd); + status = NV_ERR_INVALID_PARAMETER; + goto done; + } + +done: + NV_PRINTF(LEVEL_INFO, "control cache get for 0x%x 0x%x 0x%x status: 0x%x\n", hClient, hObject, cmd, status); + return status; +} + +NV_STATUS rmapiControlCacheSet +( + NvHandle hClient, + NvHandle hObject, + NvU32 cmd, + void* params, + NvU32 paramsSize +) +{ + NV_STATUS status = NV_OK; + NvU32 flags = 0; + + status = rmapiutilGetControlInfo(cmd, &flags, NULL); + if (status != NV_OK) + goto done; + + switch ((flags & RMCTRL_FLAGS_CACHEABLE_ANY)) + { + case RMCTRL_FLAGS_CACHEABLE: + status = _rmapiControlCacheSet(hClient, hObject, cmd, params, paramsSize); + break; + case RMCTRL_FLAGS_CACHEABLE_BY_INPUT: + status = _rmapiControlCacheSetByInput(hClient, hObject, cmd, params, paramsSize); + break; + default: + NV_PRINTF(LEVEL_ERROR, "Invalid cacheable flag 0x%x for cmd 0x%x\n", flags, cmd); + status = NV_ERR_INVALID_PARAMETER; + goto done; + } + +done: + NV_PRINTF(LEVEL_INFO, "control cache set for 0x%x 0x%x 0x%x status: 0x%x\n", hClient, hObject, cmd, status); + return status; +} + // Need to hold rmapi control cache write lock static void _freeSubmap(GpusControlCacheSubmap* submap) { @@ -431,20 +1038,21 @@ void rmapiControlCacheFreeAllCacheForGpu { GpusControlCacheSubmap* submap; - portSyncRwLockAcquireWrite(RmapiControlCache.pLock); + _cacheLockAcquire(LOCK_EXCLUSIVE); + submap = multimapFindSubmap(&RmapiControlCache.gpusControlCache, gpuInst); if (submap != NULL) _freeSubmap(submap); - portSyncRwLockReleaseWrite(RmapiControlCache.pLock); + _cacheLockRelease(LOCK_EXCLUSIVE); } void rmapiControlCacheFreeClientEntry(NvHandle hClient) { - portSyncRwLockAcquireWrite(RmapiControlCache.pLock); + _cacheLockAcquire(LOCK_EXCLUSIVE); _rmapiControlCacheFreeGpuInstForClient(hClient); - portSyncRwLockReleaseWrite(RmapiControlCache.pLock); + _cacheLockRelease(LOCK_EXCLUSIVE); } void rmapiControlCacheFreeObjectEntry(NvHandle hClient, NvHandle hObject) @@ -455,9 +1063,9 @@ void rmapiControlCacheFreeObjectEntry(NvHandle hClient, NvHandle hObject) return; } - portSyncRwLockAcquireWrite(RmapiControlCache.pLock); + _cacheLockAcquire(LOCK_EXCLUSIVE); _rmapiControlCacheFreeGpuInstForObject(hClient, hObject); - portSyncRwLockReleaseWrite(RmapiControlCache.pLock); + _cacheLockRelease(LOCK_EXCLUSIVE); } void rmapiControlCacheFree(void) @@ -476,17 +1084,13 @@ void rmapiControlCacheFree(void) portSyncRwLockDestroy(RmapiControlCache.pLock); } -// -// Changing cache mode cause race conditions on cacheability check and cache get/set. -// When the race condition happens, we may -// 1. Skip cache access when cache enabled -// 2. Access cache when cache disabled -// In the current design, these do not cause any error to the control data. -// void rmapiControlCacheSetMode(NvU32 mode) { NV_PRINTF(LEVEL_INFO, "Set rmapi control cache mode to 0x%x\n", mode); + + _cacheLockAcquire(LOCK_EXCLUSIVE); RmapiControlCache.mode = mode; + _cacheLockRelease(LOCK_EXCLUSIVE); } NvU32 rmapiControlCacheGetMode(void) diff --git a/src/nvidia/src/kernel/rmapi/rmapi_finn.c b/src/nvidia/src/kernel/rmapi/rmapi_finn.c new file mode 100644 index 000000000..abb1bf625 --- /dev/null +++ b/src/nvidia/src/kernel/rmapi/rmapi_finn.c @@ -0,0 +1,334 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "resserv/resserv.h" + +#include "ctrl/ctrlxxxx.h" + +#include "g_finn_rm_api.h" + +/** + * Serialize parameters for servicing command + * + * If unserialized params are passed in, try to serialize into CALL_CONTEXT. + * If serialized params are passed in, set CALL_CONTEXT variables. + */ +NV_STATUS +serverSerializeCtrlDown +( + CALL_CONTEXT *pCallContext, + NvU32 cmd, + void *pParams, + NvU32 paramsSize, + NvU32 *flags +) +{ + if (!(*flags & NVOS54_FLAGS_FINN_SERIALIZED)) + { + NV_STATUS status; + NvU8 *pSerBuffer; + const NvU32 interface_id = (DRF_VAL(XXXX, _CTRL_CMD, _CLASS, cmd) << 8) | + DRF_VAL(XXXX, _CTRL_CMD, _CATEGORY, cmd); + const NvU32 message_id = DRF_VAL(XXXX, _CTRL_CMD, _INDEX, cmd); + NvU32 serializedSize = (NvU32)FinnRmApiGetSerializedSize(interface_id, message_id, pParams); + + pCallContext->pDeserializedParams = pParams; + pCallContext->deserializedSize = paramsSize; + + // Nothing to do if FINN doesn't support serializing this control + if (serializedSize == 0) + return NV_OK; + + // Assume we've already serialized if it exists + if (pCallContext->pSerializedParams != NULL) + { + NV_ASSERT_OR_RETURN(pCallContext->serializedSize == serializedSize, NV_ERR_INVALID_STATE); + return NV_OK; + } + else + { + pSerBuffer = portMemAllocNonPaged(serializedSize); + if (pSerBuffer == NULL) + return NV_ERR_INSUFFICIENT_RESOURCES; + + pCallContext->pSerializedParams = (FINN_RM_API *)pSerBuffer; + } + + status = FinnRmApiSerializeDown(interface_id, message_id, pParams, &pSerBuffer, serializedSize); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Serialization failed for cmd 0x%x with status %s (0x%x) at index 0x%llx\n", + cmd, nvAssertStatusToString(status), status, + (NvUPtr)(pSerBuffer - (NvU8 *)pCallContext->pSerializedParams)); + portMemFree(pCallContext->pSerializedParams); + pCallContext->pSerializedParams = NULL; + return status; + } + + pCallContext->serializedSize = serializedSize; + *flags |= NVOS54_FLAGS_FINN_SERIALIZED; + } + else + { + // Params are already serialized, just copy them in + pCallContext->pSerializedParams = pParams; + pCallContext->serializedSize = paramsSize; + } + + return NV_OK; +} + +/** + * Deserialize parameters for servicing command + * + * If serialized params are passed in, deserialize them into CALL_CONTEXT. + * If deserialized params are passed in, set CALL_CONTEXT variables. + */ +NV_STATUS +serverDeserializeCtrlDown +( + CALL_CONTEXT *pCallContext, + NvU32 cmd, + void *pParams, + NvU32 paramsSize, + NvU32 *flags +) +{ + if (*flags & NVOS54_FLAGS_FINN_SERIALIZED) + { + NV_STATUS status; + NvU8 *pSerBuffer; + void *pDeserParams; + const NvU32 interface_id = (DRF_VAL(XXXX, _CTRL_CMD, _CLASS, cmd) << 8) | + DRF_VAL(XXXX, _CTRL_CMD, _CATEGORY, cmd); + const NvU32 message_id = DRF_VAL(XXXX, _CTRL_CMD, _INDEX, cmd); + NvU32 unserializedSize = (NvU32)FinnRmApiGetUnserializedSize(interface_id, message_id); + + // Report error if FINN can't deserialize but RM is reporting the control as serialized + if (unserializedSize == 0) + return NV_ERR_LIB_RM_VERSION_MISMATCH; + + // Assume we've already deserialized if it exists + if (pCallContext->pDeserializedParams != NULL) + { + NV_ASSERT_OR_RETURN(pCallContext->deserializedSize == unserializedSize, NV_ERR_INVALID_STATE); + return NV_OK; + } + else + { + pDeserParams = portMemAllocNonPaged(unserializedSize); + if (pDeserParams == NULL) + return NV_ERR_INSUFFICIENT_RESOURCES; + + pCallContext->pDeserializedParams = pDeserParams; + } + + pSerBuffer = (NvU8 *)pParams; + + status = FinnRmApiDeserializeDown(&pSerBuffer, paramsSize, pDeserParams, unserializedSize); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Deserialization failed for cmd 0x%x with status %s (0x%x) at index 0x%llx\n", + cmd, nvAssertStatusToString(status), status, + (NvUPtr)(pSerBuffer - (NvU8 *)pParams)); + portMemFree(pCallContext->pDeserializedParams); + pCallContext->pDeserializedParams = NULL; + return status; + } + + pCallContext->deserializedSize = unserializedSize; + pCallContext->pSerializedParams = pParams; + pCallContext->serializedSize = paramsSize; + } + else + { + // Not serialized, copy into deser params + pCallContext->pDeserializedParams = pParams; + pCallContext->deserializedSize = paramsSize; + } + + // Automatically request reserialization in case the control goes to GSP + pCallContext->bReserialize = NV_TRUE; + + return NV_OK; +} + +/** + * Serialize parameters for returning from command + * + * If serialized params are passed in, serialize into them from CALL_CONTEXT deserialized params. + * If deserialized params are passed in, unset the serialized flag. We expect that this means that + * the parameters were serialized locally and not by the caller. + */ +NV_STATUS +serverSerializeCtrlUp +( + CALL_CONTEXT *pCallContext, + NvU32 cmd, + void *pParams, + NvU32 paramsSize, + NvU32 *flags +) +{ + // + // We add NVOS54_FLAGS_FINN_SERIALIZED if the control can be serialized but wasn't in serverSerializeCtrlDown + // We don't want to return a serialized buffer if one wasn't given to us in the first place + // Check if pSerializedParams matches pParams to make sure the caller expects serialized info returned + // + if ((*flags & NVOS54_FLAGS_FINN_SERIALIZED) && + (pCallContext->pSerializedParams == pParams)) + { + NV_STATUS status; + NvU8 *pSerBuffer; + void *pDeserBuffer; + const NvU32 interface_id = (DRF_VAL(XXXX, _CTRL_CMD, _CLASS, cmd) << 8) | + DRF_VAL(XXXX, _CTRL_CMD, _CATEGORY, cmd); + const NvU32 message_id = DRF_VAL(XXXX, _CTRL_CMD, _INDEX, cmd); + + // Should be serialized at this point. Expect that serializedSize is set otherwise something is wrong + if (pCallContext->serializedSize == 0) + return NV_ERR_INVALID_STATE; + + pSerBuffer = (NvU8 *) pCallContext->pSerializedParams; + pDeserBuffer = (NvU8 *) pCallContext->pDeserializedParams; + + if (pSerBuffer == NULL) + return NV_ERR_INVALID_STATE; + + // It's possible that we have nothing to do if we're just passing parameters along + if (pDeserBuffer == NULL) + return NV_OK; + + status = FinnRmApiSerializeUp(interface_id, message_id, pDeserBuffer, &pSerBuffer, pCallContext->serializedSize); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Serialization failed for cmd 0x%x with status %s (0x%x) at index 0x%llx\n", + cmd, nvAssertStatusToString(status), status, + (NvUPtr)(pSerBuffer - (NvU8 *)pCallContext->pSerializedParams)); + return status; + } + } + else if (*flags & NVOS54_FLAGS_FINN_SERIALIZED) + { + // We serialized the control. Unset the flag + *flags &= ~NVOS54_FLAGS_FINN_SERIALIZED; + } + + return NV_OK; +} + +/** + * Deserialize parameters for returning from command + * + * If serialized params are passed in with the serialized flag set, do nothing. We expect this means we are just + * passing along the parameters to another layer. + * If deserialized params are passed in with the serialized flag set, unset flag and deserialize into params. + * We expect that this means that the parameters were serialized locally and not by the caller. + * If deserialized params are passed in without the flag set just copy to CALL_CONTEXT + */ +NV_STATUS +serverDeserializeCtrlUp +( + CALL_CONTEXT *pCallContext, + NvU32 cmd, + void *pParams, + NvU32 paramsSize, + NvU32 *flags +) +{ + if (*flags & NVOS54_FLAGS_FINN_SERIALIZED) + { + NV_STATUS status; + NvU8 *pSerBuffer; + const NvU32 interface_id = (DRF_VAL(XXXX, _CTRL_CMD, _CLASS, cmd) << 8) | + DRF_VAL(XXXX, _CTRL_CMD, _CATEGORY, cmd); + const NvU32 message_id = DRF_VAL(XXXX, _CTRL_CMD, _INDEX, cmd); + NvU32 unserializedSize = (NvU32)FinnRmApiGetUnserializedSize(interface_id, message_id); + + if (pParams == pCallContext->pSerializedParams) + { + // Received serialized params from caller, no reason to deserialize up + return NV_OK; + } + else + { + // Serialized, but not passing back up serialized params, clear flag + *flags &= ~NVOS54_FLAGS_FINN_SERIALIZED; + } + + // Report error if FINN can't deserialize but RM is reporting the control as serialized + if (unserializedSize == 0) + return NV_ERR_LIB_RM_VERSION_MISMATCH; + + pCallContext->pDeserializedParams = pParams; + + // DeserializeUp expects pointers to be set up already + pSerBuffer = (NvU8 *) pCallContext->pSerializedParams; + if (pSerBuffer == NULL) + return NV_ERR_INVALID_STATE; + + status = FinnRmApiDeserializeUp(&pSerBuffer, pCallContext->serializedSize, pParams, unserializedSize); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Deserialization failed for cmd 0x%x with status %s (0x%x) at index 0x%llx\n", + cmd, nvAssertStatusToString(status), status, + (NvUPtr)(pSerBuffer - (NvU8 *)pCallContext->pSerializedParams)); + return status; + } + + pCallContext->deserializedSize = unserializedSize; + } + else + { + // already in deserialized state + pCallContext->pDeserializedParams = pParams; + pCallContext->deserializedSize = paramsSize; + } + + return NV_OK; +} + +void +serverFreeSerializeStructures +( + CALL_CONTEXT *pCallContext, + void *pParams +) +{ + if (pCallContext->pSerializedParams != pParams) + portMemFree(pCallContext->pSerializedParams); + if (pCallContext->pDeserializedParams != pParams) + portMemFree(pCallContext->pDeserializedParams); + + pCallContext->pSerializedParams = NULL; + pCallContext->pDeserializedParams = NULL; + pCallContext->serializedSize = 0; + pCallContext->deserializedSize = 0; +} diff --git a/src/nvidia/src/kernel/rmapi/rmapi_stubs.c b/src/nvidia/src/kernel/rmapi/rmapi_stubs.c index dabb2cba4..06834def9 100644 --- a/src/nvidia/src/kernel/rmapi/rmapi_stubs.c +++ b/src/nvidia/src/kernel/rmapi/rmapi_stubs.c @@ -53,12 +53,12 @@ static NV_STATUS _rmapiFreeWithSecInfo_STUB(RM_API *pRmApi, NvHandle hClient, Nv return NV_ERR_NOT_SUPPORTED; } -static NV_STATUS _rmapiFreeClientList_STUB(RM_API *pRmApi, NvHandle *phClientList, NvU32 numClients) +static NV_STATUS _rmapiDisableClients_STUB(RM_API *pRmApi, NvHandle *phClientList, NvU32 numClients) { return NV_ERR_NOT_SUPPORTED; } -static NV_STATUS _rmapiFreeClientListWithSecInfo_STUB(RM_API *pRmApi, NvHandle *phClientList, +static NV_STATUS _rmapiDisableClientsWithSecInfo_STUB(RM_API *pRmApi, NvHandle *phClientList, NvU32 numClients, API_SECURITY_INFO *pSecInfo) { return NV_ERR_NOT_SUPPORTED; @@ -163,8 +163,8 @@ void rmapiInitStubInterface(RM_API *pRmApi) pRmApi->AllocWithSecInfo = _rmapiAllocWithSecInfo_STUB; pRmApi->Free = _rmapiFree_STUB; pRmApi->FreeWithSecInfo = _rmapiFreeWithSecInfo_STUB; - pRmApi->FreeClientList = _rmapiFreeClientList_STUB; - pRmApi->FreeClientListWithSecInfo = _rmapiFreeClientListWithSecInfo_STUB; + pRmApi->DisableClients = _rmapiDisableClients_STUB; + pRmApi->DisableClientsWithSecInfo = _rmapiDisableClientsWithSecInfo_STUB; pRmApi->Control = _rmapiControl_STUB; pRmApi->ControlWithSecInfo = _rmapiControlWithSecInfo_STUB; pRmApi->ControlPrefetch = _rmapiControlPrefetch_STUB; diff --git a/src/nvidia/src/kernel/rmapi/rpc_common.c b/src/nvidia/src/kernel/rmapi/rpc_common.c index 399138feb..f88b5c9b5 100644 --- a/src/nvidia/src/kernel/rmapi/rpc_common.c +++ b/src/nvidia/src/kernel/rmapi/rpc_common.c @@ -49,7 +49,7 @@ #undef RPC_MESSAGE_STRUCTURES #undef RPC_MESSAGE_GENERIC_UNION -void rpcRmApiSetup(OBJGPU *pGpu) +static void rpcRmApiSetup(OBJGPU *pGpu) { // // Physical RMAPI is already initialized for monolithic, and this function diff --git a/src/nvidia/src/kernel/virtualization/common_vgpu_mgr.c b/src/nvidia/src/kernel/virtualization/common_vgpu_mgr.c index a6abaf64d..d87c3a381 100644 --- a/src/nvidia/src/kernel/virtualization/common_vgpu_mgr.c +++ b/src/nvidia/src/kernel/virtualization/common_vgpu_mgr.c @@ -36,6 +36,7 @@ vgpuMgrReserveSystemChannelIDs VGPU_TYPE *vgpuTypeInfo, NvU32 gfid, NvU32 *pChidOffset, + NvU32 *pChannelCount, NvHandle hClient, NvU32 numChannels, NvU32 engineFifoListNumEntries, @@ -51,6 +52,7 @@ vgpuMgrFreeSystemChannelIDs OBJGPU *pGpu, NvU32 gfid, NvU32 *pChidOffset, + NvU32 *pChannelCount, NvHandle hClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *engineFifoList diff --git a/src/nvidia/src/kernel/virtualization/kernel_hostvgpudeviceapi.c b/src/nvidia/src/kernel/virtualization/kernel_hostvgpudeviceapi.c index bcfb13910..446775720 100644 --- a/src/nvidia/src/kernel/virtualization/kernel_hostvgpudeviceapi.c +++ b/src/nvidia/src/kernel/virtualization/kernel_hostvgpudeviceapi.c @@ -197,3 +197,13 @@ kernelhostvgpudeviceapiCtrlCmdSetGuestId_IMPL { return NV_ERR_NOT_SUPPORTED; } + +NV_STATUS +kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges_IMPL +( + KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, + NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS *pParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} diff --git a/src/nvidia/src/lib/base_utils.c b/src/nvidia/src/lib/base_utils.c index 8210f13a0..27c4158f1 100644 --- a/src/nvidia/src/lib/base_utils.c +++ b/src/nvidia/src/lib/base_utils.c @@ -330,6 +330,44 @@ char * nvU32ToStr(NvU32 value, char *string, NvU32 radix) return string; } +/*! + * @brief Convert unsigned long long hex int to char* + * + * @param[in] value to be converted to string + * @param[in] targetStrLen Denoted the converted string Length + * @param[out] *string is the char array to be have the converted data + * + * @return the converted string + */ +char * +nvU64ToStr +( + NvU64 value, + char *string, + NvU32 targetStrLen +) +{ + char tempBuffer[65]; + NvU32 base = 16; + NvU32 rem = 0; + NvU32 inx = 0; + + for (inx = 0; inx < targetStrLen; inx++) + { + rem = value % base; + value = value / base; + tempBuffer[inx] = (rem > 9)? (rem - 10) + 'a' : rem + '0'; + } + + for(inx = 0; inx < targetStrLen; inx++) + { + string[inx] = tempBuffer[targetStrLen - inx - 1]; + } + + string[targetStrLen] = '\0'; + + return string; +} /** * @brief Get the string length diff --git a/src/nvidia/src/lib/protobuf/prbutil.c b/src/nvidia/src/lib/protobuf/prbutil.c index 2d35219c2..b9908a826 100644 --- a/src/nvidia/src/lib/protobuf/prbutil.c +++ b/src/nvidia/src/lib/protobuf/prbutil.c @@ -40,7 +40,7 @@ */ NV_STATUS -prbEncGpuRegs(POBJGPU pGpu, IO_APERTURE *pAperture, NvU64 offset, NvU32 numRegs, +prbEncGpuRegs(POBJGPU pGpu, IoAperture *pAperture, NvU64 offset, NvU32 numRegs, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc) { NV_STATUS status; @@ -137,7 +137,7 @@ done: */ NV_STATUS -prbEncGpuRegSliceTbl(POBJGPU pGpu, IO_APERTURE *pAperture, const PRB_GPU_REG_TABLE *pTbl, NvU32 numEntries, NvU32 base, +prbEncGpuRegSliceTbl(POBJGPU pGpu, IoAperture *pAperture, const PRB_GPU_REG_TABLE *pTbl, NvU32 numEntries, NvU32 base, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc) { NV_STATUS status = NV_OK; // Init keeps the Mac compiler quiet @@ -228,7 +228,7 @@ done: */ NV_STATUS -prbEncGpuRegSliceIndexedTbl(POBJGPU pGpu, IO_APERTURE *pAperture, const PRB_GPU_REG_INDEXED_TABLE *pTbl, NvU32 numEntries, +prbEncGpuRegSliceIndexedTbl(POBJGPU pGpu, IoAperture *pAperture, const PRB_GPU_REG_INDEXED_TABLE *pTbl, NvU32 numEntries, NvU32 base, NvU32 index, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc) { NV_STATUS status = NV_OK; // Init keeps the Mac compiler quiet @@ -316,7 +316,7 @@ done: */ NV_STATUS -prbEncGpuRegSliceOffset(POBJGPU pGpu, IO_APERTURE *pAperture, const NvU32 *pOffset, NvU32 numEntries, +prbEncGpuRegSliceOffset(POBJGPU pGpu, IoAperture *pAperture, const NvU32 *pOffset, NvU32 numEntries, NvU32 base, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *pFieldDesc) { NV_STATUS status = NV_OK; // if numEntries == 0 @@ -388,7 +388,7 @@ done: */ NV_STATUS -prbEncGpuRegOffset(POBJGPU pGpu, IO_APERTURE *pAperture, const NvU32 *pOffset, NvU32 numEntries, +prbEncGpuRegOffset(POBJGPU pGpu, IoAperture *pAperture, const NvU32 *pOffset, NvU32 numEntries, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *pFieldDesc) { return prbEncGpuRegSliceOffset(pGpu, pAperture, pOffset, numEntries, 0, pPrbEnc, pFieldDesc); @@ -406,7 +406,7 @@ prbEncGpuRegOffset(POBJGPU pGpu, IO_APERTURE *pAperture, const NvU32 *pOffset, N */ NV_STATUS -prbEncGpuRegTbl(POBJGPU pGpu, IO_APERTURE *pAperture, const PRB_GPU_REG_TABLE *pTbl, NvU32 numEntries, +prbEncGpuRegTbl(POBJGPU pGpu, IoAperture *pAperture, const PRB_GPU_REG_TABLE *pTbl, NvU32 numEntries, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc) { return prbEncGpuRegSliceTbl(pGpu, pAperture, pTbl, numEntries, 0, pPrbEnc, fieldDesc); diff --git a/src/nvidia/src/lib/zlib/inflate.c b/src/nvidia/src/lib/zlib/inflate.c index f7214c256..3c3103da4 100644 --- a/src/nvidia/src/lib/zlib/inflate.c +++ b/src/nvidia/src/lib/zlib/inflate.c @@ -892,7 +892,7 @@ static NV_STATUS utilGzInit(const NvU8 *zArray, NvU8* oBuffer, NvU32 numTotalBytes, NvU8* window, PGZ_INFLATE_STATE pGzState) { portMemSet(pGzState, 0, sizeof(GZ_INFLATE_STATE)); - portMemSet(window, 0, sizeof(GZ_SLIDE_WINDOW_SIZE)); + portMemSet(window, 0, GZ_SLIDE_WINDOW_SIZE); pGzState->inbuf = (NvU8*)zArray; pGzState->outbuf = oBuffer; diff --git a/src/nvidia/src/libraries/ioaccess/ioaccess.c b/src/nvidia/src/libraries/ioaccess/ioaccess.c index a05f00aaf..ea16ebe18 100644 --- a/src/nvidia/src/libraries/ioaccess/ioaccess.c +++ b/src/nvidia/src/libraries/ioaccess/ioaccess.c @@ -25,52 +25,7 @@ #include "utils/nvprintf.h" #include "nvport/nvport.h" -/*! - * @brief: Allocate and initialize an IO_APERTURE instance. - * - * @param[out] ppAperture pointer to the new IO_APERTURE. - * @param[in] pParentAperture pointer to the parent of the new IO_APERTURE. - * @param[in] pDevice pointer to IO_DEVICE of the APERTURE. - * @param[in] offset offset from the parent APERTURE's baseAddress. - * @param[in] length length of the APERTURE. - * - * @return NV_OK upon success - * NV_ERR* otherwise. - */ -NV_STATUS -ioaccessCreateIOAperture -( - IO_APERTURE **ppAperture, - IO_APERTURE *pParentAperture, - IO_DEVICE *pDevice, - NvU32 offset, - NvU32 length -) -{ - NV_STATUS status = NV_OK; - IO_APERTURE *pAperture = portMemAllocNonPaged(sizeof(IO_APERTURE)); - - if (pAperture == NULL) - { - return NV_ERR_NO_MEMORY; - } - - portMemSet(pAperture, 0, sizeof(IO_APERTURE)); - - status = ioaccessInitIOAperture(pAperture, pParentAperture, pDevice, offset, length); - if (status != NV_OK) - { - portMemFree(pAperture); - } - else - { - *ppAperture = pAperture; - } - - return status; -} - - +#if !((defined(NVRM) || defined(RMCFG_FEATURE_PLATFORM_GSP)) && !defined(NVWATCH)) /*! * Initialize an IO_APERTURE instance. This enables initialization for derived IO_APERTURE instances * that are not allocated via CreateIOAperture. @@ -135,12 +90,4 @@ ioaccessInitIOAperture return NV_OK; } - -void -ioaccessDestroyIOAperture -( - IO_APERTURE *pAperture -) -{ - portMemFree(pAperture); -} +#endif // !((defined(NVRM) || defined(RMCFG_FEATURE_PLATFORM_GSP)) && !defined(NVWATCH)) diff --git a/src/nvidia/src/libraries/mmu/gmmu_fmt.c b/src/nvidia/src/libraries/mmu/gmmu_fmt.c index db8545ece..b12e8d0bf 100644 --- a/src/nvidia/src/libraries/mmu/gmmu_fmt.c +++ b/src/nvidia/src/libraries/mmu/gmmu_fmt.c @@ -148,7 +148,7 @@ void gmmuFmtInitPteCompTags { NvU32 i, compPageIndex, endCompPageIndex; NvU64 offset = surfOffset; - const NvU32 pageSize = NvU64_LO32(mmuFmtLevelPageSize(pLevel)); + const NvU64 pageSize = mmuFmtLevelPageSize(pLevel); const NV_FIELD_DESC32 *pCtlSubIndexFld = &pFmt->pPte->fldCompTagSubIndex; NvU32 ctlSubIndexMask = 0; NvU32 ctlSubIndexShift = 0; diff --git a/src/nvidia/src/libraries/mmu/mmu_walk.c b/src/nvidia/src/libraries/mmu/mmu_walk.c index 0b26e353f..6086ef2c5 100644 --- a/src/nvidia/src/libraries/mmu/mmu_walk.c +++ b/src/nvidia/src/libraries/mmu/mmu_walk.c @@ -299,7 +299,7 @@ NV_STATUS mmuWalkProcessPdes NvU32 entryIndexHi = mmuFmtVirtAddrToEntryIndex(pLevel->pFmt, vaHi); NvU32 entryIndex; NvU32 index; - NvU32 entryIndexFillStart; + NvU32 entryIndexFillStart = 0; NvU32 entryIndexFillEnd; NvU32 pendingFillCount = 0; @@ -685,7 +685,7 @@ cleanupIter: NvU32 entryIndexHi = mmuFmtVirtAddrToEntryIndex(pLevel->pFmt, vaHi); NvU32 entryIndex; NvU32 index; - NvU32 entryIndexFillStart; + NvU32 entryIndexFillStart = 0; NvU32 entryIndexFillEnd; NvU32 pendingFillCount = 0; diff --git a/src/nvidia/src/libraries/mmu/mmu_walk_fill.c b/src/nvidia/src/libraries/mmu/mmu_walk_fill.c index 037b52d59..670107100 100644 --- a/src/nvidia/src/libraries/mmu/mmu_walk_fill.c +++ b/src/nvidia/src/libraries/mmu/mmu_walk_fill.c @@ -285,7 +285,7 @@ static NV_STATUS _mmuWalkPostFillPTETasks // if (pWalk->flags.bAtsEnabled && fillState == MMU_WALK_FILL_INVALID) { - const NvU32 pageSize = NvU64_LO32(mmuFmtLevelPageSize(pFmtLevel)); + const NvU64 pageSize = mmuFmtLevelPageSize(pFmtLevel); NvU32 progress = 0; NvU32 entryIndex = 0; diff --git a/src/nvidia/src/libraries/nvoc/src/runtime.c b/src/nvidia/src/libraries/nvoc/src/runtime.c index 8e4714494..ba7314c22 100644 --- a/src/nvidia/src/libraries/nvoc/src/runtime.c +++ b/src/nvidia/src/libraries/nvoc/src/runtime.c @@ -74,6 +74,34 @@ Dynamic *objFindAncestor_IMPL(Dynamic *pDynamic, NVOC_CLASS_ID classId) void objAddChild_IMPL(Object *pObj, Object *pChild) { NV_ASSERT(pChild->pParent == NULL); + +#if defined(DEBUG) + if (pChild->createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + { + // + // For objects constructed in place it is possible to call objCreate() twice without calling objDelete() + // This results in a loop in parent's child list, making it endless + // This check is supposed to make catching this issue easier without affecting perf + // + Object *pCurrentChild = pObj->childTree.pChild; + + while (pCurrentChild != NULL) + { + if (pCurrentChild == pChild) + { +#if NV_PRINTF_STRINGS_ALLOWED + portDbgPrintf("NVOC: %s: class %s called in-place objCreate() twice without calling objDelete()", + __FUNCTION__, + objGetClassInfo(pChild)->name); +#endif // NV_PRINTF_STRINGS_ALLOWED + PORT_BREAKPOINT_DEBUG(); + } + + pCurrentChild = pCurrentChild->childTree.pSibling; + } + } +#endif // defined(DEBUG) + pChild->pParent = pObj; pChild->childTree.pSibling = pObj->childTree.pChild; pObj->childTree.pChild = pChild; @@ -116,6 +144,25 @@ Object *objGetDirectParent_IMPL(Object *pObj) return pObj->pParent; } +NV_STATUS __nvoc_handleObjCreateMemAlloc(NvU32 createFlags, NvU32 allocSize, void **ppLocalPtr, void **ppThis) +{ + if (allocSize == 0 || ppThis == NULL || ppLocalPtr == NULL) + return NV_ERR_INVALID_PARAMETER; + + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + { + *ppLocalPtr = *ppThis; + } + else + { + *ppLocalPtr = portMemAllocNonPaged(allocSize); + if (*ppLocalPtr == NULL) + return NV_ERR_NO_MEMORY; + } + + return NV_OK; +} + //! Internal backing method for objDelete. void __nvoc_objDelete(Dynamic *pDynamic) { @@ -147,7 +194,8 @@ void __nvoc_objDelete(Dynamic *pDynamic) } pDerivedObj = __nvoc_fullyDerive(pDynamic); - portMemFree(pDerivedObj); + if (!(pObj->createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT)) + portMemFree(pDerivedObj); } //! Internal method to fill out an object's RTTI pointers from a class definition. diff --git a/src/nvidia/src/libraries/resserv/src/rs_client.c b/src/nvidia/src/libraries/resserv/src/rs_client.c index a8a02b035..5d5b20210 100644 --- a/src/nvidia/src/libraries/resserv/src/rs_client.c +++ b/src/nvidia/src/libraries/resserv/src/rs_client.c @@ -61,15 +61,6 @@ static NV_STATUS _clientAllocResourceHelper(RsClient *pClient, RsServer *pServer static NV_STATUS _clientConstructResourceRef(RsClient *pClient, RsServer *pServer, RsResourceRef *pParentRef, NvHandle hResource, NvU32 classId, RsResourceRef **ppResourceRef); -/** - * Release all CPU address mappings for a resource - * - * @param[in] pClient Client that owns the resource - * @param[in] pCallContext Caller information (which includes the resource reference whose mappings will be freed) - * @param[in] pLockInfo Information about which locks are already held, for recursive calls - */ -static NV_STATUS _clientUnmapResourceRefMappings(RsClient *pClient, CALL_CONTEXT *pCallContext, RS_LOCK_INFO *pLockInfo); - /** * Release all CPU address mappings that reference this resource * @@ -805,7 +796,7 @@ clientFreeResource_IMPL resPreDestruct(pResource); // Remove all CPU mappings - _clientUnmapResourceRefMappings(pClient, &callContext, pParams->pLockInfo); + clientUnmapResourceRefMappings(pClient, &callContext, pParams->pLockInfo); _clientUnmapBackRefMappings(pClient, &callContext, pParams->pLockInfo); // Remove all inter-mappings @@ -1080,7 +1071,7 @@ clientDestructResourceRef_IMPL } NV_STATUS -_clientUnmapResourceRefMappings +clientUnmapResourceRefMappings ( RsClient *pClient, CALL_CONTEXT *pCallContext, diff --git a/src/nvidia/src/libraries/resserv/src/rs_resource.c b/src/nvidia/src/libraries/resserv/src/rs_resource.c index 87e7e3402..f8234a3dd 100644 --- a/src/nvidia/src/libraries/resserv/src/rs_resource.c +++ b/src/nvidia/src/libraries/resserv/src/rs_resource.c @@ -184,6 +184,10 @@ resControl_IMPL if (status != NV_OK) return status; + status = resControlSerialization_Prologue(pResource, pCallContext, pRsParams); + if (status != NV_OK) + goto done; + status = resControl_Prologue(pResource, pCallContext, pRsParams); if ((status != NV_OK) && (status != NV_WARN_NOTHING_TO_DO)) goto done; @@ -207,13 +211,22 @@ resControl_IMPL else { CONTROL_EXPORT_FNPTR pFunc = ((CONTROL_EXPORT_FNPTR) pEntry->pFunc); - status = pFunc(pDynamicObj, pRsParams->pParams); + + if (pRsParams->flags & NVOS54_FLAGS_FINN_SERIALIZED) + { + status = pFunc(pDynamicObj, pCallContext->pDeserializedParams); + } + else + { + status = pFunc(pDynamicObj, pRsParams->pParams); + } } } resControl_Epilogue(pResource, pCallContext, pRsParams); done: + resControlSerialization_Epilogue(pResource, pCallContext, pRsParams); status = serverControl_Epilogue(pServer, pRsParams, access, &releaseFlags, status); return status; @@ -230,6 +243,27 @@ resControlFilter_IMPL return NV_OK; } +NV_STATUS +resControlSerialization_Prologue_IMPL +( + RsResource *pResource, + CALL_CONTEXT *pCallContext, + RS_RES_CONTROL_PARAMS_INTERNAL *pParams +) +{ + return NV_OK; +} + +void +resControlSerialization_Epilogue_IMPL +( + RsResource *pResource, + CALL_CONTEXT *pCallContext, + RS_RES_CONTROL_PARAMS_INTERNAL *pParams +) +{ +} + NV_STATUS resControl_Prologue_IMPL ( diff --git a/src/nvidia/src/libraries/resserv/src/rs_server.c b/src/nvidia/src/libraries/resserv/src/rs_server.c index 901e7b146..18dc2b62b 100644 --- a/src/nvidia/src/libraries/resserv/src/rs_server.c +++ b/src/nvidia/src/libraries/resserv/src/rs_server.c @@ -273,6 +273,9 @@ serverConstruct goto fail; } + listInitIntrusive(&pServer->disabledClientList); + pServer->pDisabledClientListLock = portSyncSpinlockCreate(pAllocator); + return NV_OK; fail: @@ -336,6 +339,9 @@ serverDestruct listDestroy(&pServer->pClientSortedList[i]); } + listDestroy(&pServer->disabledClientList); + portSyncSpinlockDestroy(pServer->pDisabledClientListLock); + PORT_FREE(pServer->pAllocator, pServer->pClientSortedList); mapDestroy(&pServer->shareMap); listDestroy(&pServer->defaultInheritedSharePolicyList); @@ -412,6 +418,13 @@ _serverFreeClient_underlock clientFreeAccessBackRefs(pClient, pServer); + if (pClient->bDisabled) + { + portSyncSpinlockAcquire(pServer->pDisabledClientListLock); + listRemove(&pServer->disabledClientList, pClient); + portSyncSpinlockRelease(pServer->pDisabledClientListLock); + } + objDelete(pClient); listRemoveFirstByValue(&pServer->pClientSortedList[hClient & RS_CLIENT_HANDLE_BUCKET_MASK], &pClientEntry); @@ -857,7 +870,7 @@ done: } NV_STATUS -serverFreeClientList +serverMarkClientListDisabled ( RsServer *pServer, NvHandle *phClientList, @@ -866,34 +879,121 @@ serverFreeClientList API_SECURITY_INFO *pSecInfo ) { - NvU32 i, j; - - // - // Call serverFreeClient twice; first for high priority resources - // then again for remaining resources - // - for (i = 0; i < 2; ++i) + NvU32 i; + for (i = 0; i < numClients; ++i) { - for (j = 0; j < numClients; ++j) - { - RS_CLIENT_FREE_PARAMS params; - portMemSet(¶ms, 0, sizeof(params)); + RS_CLIENT_FREE_PARAMS params; + portMemSet(¶ms, 0, sizeof(params)); - if (phClientList[j] == 0) - continue; + if (phClientList[i] == 0) + continue; - params.hClient = phClientList[j]; - params.bHiPriOnly = (i == 0); - params.state = freeState; - params.pSecInfo = pSecInfo; + params.hClient = phClientList[i]; + params.bDisableOnly = NV_TRUE; + params.state = freeState; + params.pSecInfo = pSecInfo; - serverFreeClient(pServer, ¶ms); - } + // If individual calls fail not much to do, just log error and move on + NV_ASSERT_OK(serverFreeClient(pServer, ¶ms)); } return NV_OK; } +// Returns pServer->pNextDisabledClient and advances it by one node ahead +static RsClient * +_getNextDisabledClient(RsServer *pServer) +{ + RsClient *pClient; + portSyncSpinlockAcquire(pServer->pDisabledClientListLock); + + pClient = + (pServer->pNextDisabledClient != NULL) ? + pServer->pNextDisabledClient : + listHead(&pServer->disabledClientList); + + pServer->pNextDisabledClient = + (pClient != NULL) ? + listNext(&pServer->disabledClientList, pClient) : + listHead(&pServer->disabledClientList); + + portSyncSpinlockRelease(pServer->pDisabledClientListLock); + return pClient; +} + +NV_STATUS serverFreeDisabledClients +( + RsServer *pServer, + NvU32 freeState, + NvU32 limit +) +{ + RsClient *pClient; + RS_RES_FREE_PARAMS params; + API_SECURITY_INFO secInfo; + RS_LOCK_INFO lockInfo; + NV_STATUS status = NV_OK; + + // + // Only allow one instance of this function at a time. + // Multiple calls can happen if one thread requested delayed free via worker, + // while another tries to flush disabled clients immediately. + // It doesn't matter which one ends up running, they all free everything + // + static volatile NvU32 inProgress; + if (!portAtomicCompareAndSwapU32(&inProgress, 1, 0)) + return NV_ERR_IN_USE; + + portMemSet(¶ms, 0, sizeof(params)); + portMemSet(&secInfo, 0, sizeof(secInfo)); + portMemSet(&lockInfo, 0, sizeof(lockInfo)); + + secInfo.privLevel = RS_PRIV_LEVEL_KERNEL; + secInfo.paramLocation = PARAM_LOCATION_KERNEL; + lockInfo.state = freeState; + params.pLockInfo = &lockInfo; + params.pSecInfo = &secInfo; + + while ((pClient = _getNextDisabledClient(pServer))) + { + NV_ASSERT(pClient->bDisabled); + + params.hClient = pClient->hClient; + params.hResource = pClient->hClient; + + // + // We call serverFreeClient twice; first for high priority resources + // then again for remaining resources + // + if (!pClient->bHighPriorityFreeDone) + { + params.bHiPriOnly = NV_TRUE; + pClient->bHighPriorityFreeDone = NV_TRUE; + } + else + { + params.bHiPriOnly = NV_FALSE; + } + + serverFreeResourceTree(pServer, ¶ms); + + // + // If limit is 0, it'll wrap-around and count down from 0xFFFFFFFF + // But RS_CLIENT_HANDLE_MAX is well below that, so it effectively + // means process all of them + // + if (--limit == 0) + { + status = NV_WARN_MORE_PROCESSING_REQUIRED; + break; + } + } + + portAtomicSetU32(&inProgress, 0); + return status; +} + + NV_STATUS serverFreeResourceTree ( @@ -960,6 +1060,44 @@ serverFreeResourceTree pParams->pResourceRef = pResourceRef; freeStack.pResourceRef = pResourceRef; + if (pParams->bDisableOnly) + { + if (!pClient->bDisabled) + { + pClient->bDisabled = NV_TRUE; + portSyncSpinlockAcquire(pServer->pDisabledClientListLock); + listAppendExisting(&pServer->disabledClientList, pClient); + portSyncSpinlockRelease(pServer->pDisabledClientListLock); + } + else + { + status = NV_ERR_INVALID_STATE; + goto done; + } + + pClient->bActive = NV_FALSE; + status = NV_OK; + + // Unmap all CPU mappings + { + CALL_CONTEXT callContext; + RS_ITERATOR it; + portMemSet(&callContext, 0, sizeof(callContext)); + callContext.pServer = pServer; + callContext.pClient = pClient; + callContext.pLockInfo = pLockInfo; + + it = clientRefIter(pClient, NULL, 0, RS_ITERATE_DESCENDANTS, NV_TRUE); + while (clientRefIterNext(pClient, &it)) + { + callContext.pResourceRef = it.pResourceRef; + clientUnmapResourceRefMappings(pClient, &callContext, pLockInfo); + } + } + + goto done; + } + if (pParams->bInvalidateOnly && pResourceRef->bInvalidated) { status = NV_OK; @@ -2653,12 +2791,15 @@ NV_STATUS serverFreeClient(RsServer *pServer, RS_CLIENT_FREE_PARAMS* pParams) portMemSet(&lockInfo, 0, sizeof(lockInfo)); portMemSet(¶ms, 0, sizeof(params)); - params.hClient = pParams->hClient; - params.hResource = pParams->hClient; - params.bHiPriOnly = pParams->bHiPriOnly; - lockInfo.state = pParams->state; - params.pLockInfo = &lockInfo; - params.pSecInfo = pParams->pSecInfo; + + lockInfo.state = pParams->state; + lockInfo.flags = RS_LOCK_FLAGS_LOW_PRIORITY; + params.pLockInfo = &lockInfo; + params.hClient = pParams->hClient; + params.hResource = pParams->hClient; + params.bHiPriOnly = pParams->bHiPriOnly; + params.bDisableOnly = pParams->bDisableOnly; + params.pSecInfo = pParams->pSecInfo; return serverFreeResourceTree(pServer, ¶ms); } @@ -3005,6 +3146,79 @@ serverShareIterNext return NV_FALSE; } +#if RS_STANDALONE +NV_STATUS +serverSerializeCtrlDown +( + CALL_CONTEXT *pCallContext, + NvU32 cmd, + void *pParams, + NvU32 paramsSize, + NvU32 *flags +) +{ + return NV_OK; +} + +NV_STATUS +serverDeserializeCtrlDown +( + CALL_CONTEXT *pCallContext, + NvU32 cmd, + void *pParams, + NvU32 paramsSize, + NvU32 *flags +) +{ + return NV_OK; +} + +NV_STATUS +serverSerializeCtrlUp +( + CALL_CONTEXT *pCallContext, + NvU32 cmd, + void *pParams, + NvU32 paramsSize, + NvU32 *flags +) +{ + return NV_OK; +} + +NV_STATUS +serverDeserializeCtrlUp +( + CALL_CONTEXT *pCallContext, + NvU32 cmd, + void *pParams, + NvU32 paramsSize, + NvU32 *flags +) +{ + return NV_OK; +} + +void +serverFreeSerializeStructures +( + CALL_CONTEXT *pCallContext, + void *pParams +) +{ +} +#endif // RS_STANDALONE + +void +serverDisableReserializeControl +( + CALL_CONTEXT *pCallContext +) +{ + NV_CHECK_OR_RETURN_VOID(LEVEL_INFO, pCallContext != NULL); + pCallContext->bReserialize = NV_FALSE; +} + #if (RS_PROVIDES_API_STATE) NV_STATUS serverAllocApiCopyIn diff --git a/src/nvidia/src/libraries/utils/nvassert.c b/src/nvidia/src/libraries/utils/nvassert.c index 69e92a4c5..fc8bd13e0 100644 --- a/src/nvidia/src/libraries/utils/nvassert.c +++ b/src/nvidia/src/libraries/utils/nvassert.c @@ -35,6 +35,9 @@ #include "os/os.h" #include "nvrm_registry.h" #include "rmconfig.h" +#include "gpu/gpu.h" +#include "gpu/gpu_user_shared_data.h" +#include "class/cl00de.h" #elif !defined(RMCFG_FEATURE_ENABLED) #define RMCFG_FEATURE_x 0 #endif @@ -55,18 +58,31 @@ void rcdbRmAssertStatus(NvU32 status, NvU32 lineNum, NvU64 ip); #if defined(GSP_PLUGIN_BUILD) || (defined(NVRM) && NVCPU_IS_RISCV64) #if NV_JOURNAL_ASSERT_ENABLE +static void +_logAssertCount(void) +{ + static NvU32 assertCount = 0; + NV00DE_SHARED_DATA *pSharedData = gpushareddataWriteStart(g_pGpu); + + pSharedData->gspAssertCount = ++assertCount; + + gpushareddataWriteFinish(g_pGpu); +} + /* * Helper function for NV_ASSERT_FAILED */ void nvAssertFailed(void) { + _logAssertCount(); NV_JOURNAL_ASSERT_FAILURE(NV_RM_ASSERT_UNKNOWN_LINE_NUM, portUtilGetReturnAddress()); } void nvAssertOkFailed(NvU32 status) { + _logAssertCount(); NV_JOURNAL_ASSERT_FAILURE_STATUS(NV_RM_ASSERT_UNKNOWN_LINE_NUM, portUtilGetReturnAddress(), status); } #endif diff --git a/src/nvidia/srcs.mk b/src/nvidia/srcs.mk index 64b96cc7b..767700973 100644 --- a/src/nvidia/srcs.mk +++ b/src/nvidia/srcs.mk @@ -32,6 +32,7 @@ SRCS += generated/g_fbsr_nvoc.c SRCS += generated/g_fla_mem_nvoc.c SRCS += generated/g_fm_session_api_nvoc.c SRCS += generated/g_generic_engine_nvoc.c +SRCS += generated/g_gpu_access_nvoc.c SRCS += generated/g_gpu_acct_nvoc.c SRCS += generated/g_gpu_boost_mgr_nvoc.c SRCS += generated/g_gpu_class_list.c @@ -59,6 +60,7 @@ SRCS += generated/g_i2c_api_nvoc.c SRCS += generated/g_intr_nvoc.c SRCS += generated/g_intr_service_nvoc.c SRCS += generated/g_io_vaspace_nvoc.c +SRCS += generated/g_ioaccess_nvoc.c SRCS += generated/g_journal_nvoc.c SRCS += generated/g_journal_pb.c SRCS += generated/g_kern_bus_nvoc.c @@ -157,6 +159,7 @@ SRCS += generated/g_vaspace_nvoc.c SRCS += generated/g_vblank_callback_nvoc.c SRCS += generated/g_vgpuconfigapi_nvoc.c SRCS += generated/g_video_mem_nvoc.c +SRCS += generated/g_vidmem_access_bit_buffer_nvoc.c SRCS += generated/g_virt_mem_allocator_nvoc.c SRCS += generated/g_virt_mem_mgr_nvoc.c SRCS += generated/g_virt_mem_range_nvoc.c @@ -203,6 +206,8 @@ SRCS += ../common/nvswitch/kernel/inforom/ifrecc_nvswitch.c SRCS += ../common/nvswitch/kernel/inforom/ifrnvlink_nvswitch.c SRCS += ../common/nvswitch/kernel/inforom/ifroms_nvswitch.c SRCS += ../common/nvswitch/kernel/inforom/ifrro_nvswitch.c +SRCS += ../common/nvswitch/kernel/inforom/inforom_nvl_v3_nvswitch.c +SRCS += ../common/nvswitch/kernel/inforom/inforom_nvl_v4_nvswitch.c SRCS += ../common/nvswitch/kernel/inforom/inforom_nvswitch.c SRCS += ../common/nvswitch/kernel/ipmi/fru_nvswitch.c SRCS += ../common/nvswitch/kernel/lr10/clock_lr10.c @@ -240,6 +245,7 @@ SRCS += ../common/nvswitch/kernel/soe/soe_nvswitch.c SRCS += ../common/nvswitch/kernel/spi_nvswitch.c SRCS += arch/nvalloc/unix/src/asm/x86/nv_cpuid.c SRCS += arch/nvalloc/unix/src/asm/x86/nv_rdcr.c +SRCS += arch/nvalloc/unix/src/dynamic-power.c SRCS += arch/nvalloc/unix/src/escape.c SRCS += arch/nvalloc/unix/src/exports-stubs.c SRCS += arch/nvalloc/unix/src/gcc_helper.c @@ -262,7 +268,7 @@ SRCS += interface/deprecated/rmapi_deprecated_misc.c SRCS += interface/deprecated/rmapi_deprecated_utils.c SRCS += interface/deprecated/rmapi_deprecated_vidheapctrl.c SRCS += interface/deprecated/rmapi_gss_legacy_control.c -SRCS += interface/rmapi/src/finn_rm_api.c +SRCS += interface/rmapi/src/g_finn_rm_api.c SRCS += kernel/nvd/nv/dbgbuffer.c SRCS += kernel/nvd/nv/nvdctrl.c SRCS += kernel/vgpu/nv/objvgpu.c @@ -291,8 +297,10 @@ SRCS += src/kernel/gpu/arch/ada/kern_gpu_ad102.c SRCS += src/kernel/gpu/arch/ampere/kern_gpu_ga100.c SRCS += src/kernel/gpu/arch/hopper/kern_gpu_gh100.c SRCS += src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c +SRCS += src/kernel/gpu/arch/pascal/kern_gpu_gp100.c SRCS += src/kernel/gpu/arch/turing/kern_gpu_tu102.c SRCS += src/kernel/gpu/audio/hda_codec_api.c +SRCS += src/kernel/gpu/bif/arch/ada/kernel_bif_ad102.c SRCS += src/kernel/gpu/bif/arch/ampere/kernel_bif_ga100.c SRCS += src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c SRCS += src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c @@ -366,7 +374,6 @@ SRCS += src/kernel/gpu/fifo/arch/hopper/kernel_channel_gh100.c SRCS += src/kernel/gpu/fifo/arch/hopper/kernel_fifo_gh100.c SRCS += src/kernel/gpu/fifo/arch/hopper/usermode_api_gh100.c SRCS += src/kernel/gpu/fifo/arch/maxwell/kernel_channel_gm107.c -SRCS += src/kernel/gpu/fifo/arch/maxwell/kernel_channel_group_gm107.c SRCS += src/kernel/gpu/fifo/arch/maxwell/kernel_fifo_gm107.c SRCS += src/kernel/gpu/fifo/arch/pascal/kernel_fifo_gp102.c SRCS += src/kernel/gpu/fifo/arch/turing/kernel_fifo_tu102.c @@ -529,6 +536,7 @@ SRCS += src/kernel/gpu/mmu/mmu_fault_buffer.c SRCS += src/kernel/gpu/mmu/mmu_fault_buffer_ctrl.c SRCS += src/kernel/gpu/mmu/mmu_trace.c SRCS += src/kernel/gpu/mmu/uvm_sw.c +SRCS += src/kernel/gpu/mmu/vidmem_access_bit_buffer_v2.c SRCS += src/kernel/gpu/nvdec/kernel_nvdec_ctx.c SRCS += src/kernel/gpu/nvdec/kernel_nvdec_engdesc.c SRCS += src/kernel/gpu/nvenc/kernel_nvenc_ctx.c @@ -558,7 +566,6 @@ SRCS += src/kernel/gpu/perf/kern_perf_gpuboostsync.c SRCS += src/kernel/gpu/perf/kern_perf_pm.c SRCS += src/kernel/gpu/perf/kern_perf_pwr.c SRCS += src/kernel/gpu/perf/kern_perfbuffer.c -SRCS += src/kernel/gpu/pmu/arch/ada/kern_pmu_ad102.c SRCS += src/kernel/gpu/pmu/kern_pmu.c SRCS += src/kernel/gpu/rc/kernel_rc.c SRCS += src/kernel/gpu/rc/kernel_rc_callback.c @@ -602,6 +609,7 @@ SRCS += src/kernel/gpu_mgr/gpu_db.c SRCS += src/kernel/gpu_mgr/gpu_group.c SRCS += src/kernel/gpu_mgr/gpu_mgmt_api.c SRCS += src/kernel/gpu_mgr/gpu_mgr.c +SRCS += src/kernel/gpu_mgr/gpu_mgr_sli.c SRCS += src/kernel/mem_mgr/console_mem.c SRCS += src/kernel/mem_mgr/ctx_buf_pool.c SRCS += src/kernel/mem_mgr/fabric_vaspace.c @@ -643,11 +651,13 @@ SRCS += src/kernel/platform/nbsi/nbsi_init.c SRCS += src/kernel/platform/nbsi/nbsi_osrg.c SRCS += src/kernel/platform/p2p/p2p_caps.c SRCS += src/kernel/platform/platform.c +SRCS += src/kernel/platform/sli/sli.c SRCS += src/kernel/power/gpu_boost_mgr.c SRCS += src/kernel/rmapi/alloc_free.c SRCS += src/kernel/rmapi/binary_api.c SRCS += src/kernel/rmapi/client.c SRCS += src/kernel/rmapi/client_resource.c +SRCS += src/kernel/rmapi/client_resource_sli.c SRCS += src/kernel/rmapi/control.c SRCS += src/kernel/rmapi/deprecated_context.c SRCS += src/kernel/rmapi/embedded_param_copy.c @@ -664,6 +674,7 @@ SRCS += src/kernel/rmapi/resource.c SRCS += src/kernel/rmapi/resource_desc.c SRCS += src/kernel/rmapi/rmapi.c SRCS += src/kernel/rmapi/rmapi_cache.c +SRCS += src/kernel/rmapi/rmapi_finn.c SRCS += src/kernel/rmapi/rmapi_stubs.c SRCS += src/kernel/rmapi/rmapi_utils.c SRCS += src/kernel/rmapi/rpc_common.c diff --git a/version.mk b/version.mk index f86e1b58a..f317cd646 100644 --- a/version.mk +++ b/version.mk @@ -1,4 +1,4 @@ -NVIDIA_VERSION = 525.89.02 +NVIDIA_VERSION = 530.30.02 # This file. VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST))