550.127.05

README.md

@@ -1,7 +1,7 @@
 # NVIDIA Linux Open GPU Kernel Module Source
 
 This is the source release of the NVIDIA Linux open GPU kernel modules,
-version 550.120.
+version 550.127.05.
 
 
 ## How to Build
@@ -17,7 +17,7 @@ as root:
 
 Note that the kernel modules built here must be used with GSP
 firmware and user-space NVIDIA GPU driver components from a corresponding
-550.120 driver release.  This can be achieved by installing
+550.127.05 driver release.  This can be achieved by installing
 the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
 option.  E.g.,
 
@@ -188,7 +188,7 @@ encountered specific to them.
 For details on feature support and limitations, see the NVIDIA GPU driver
 end user README here:
 
-https://us.download.nvidia.com/XFree86/Linux-x86_64/550.120/README/kernel_open.html
+https://us.download.nvidia.com/XFree86/Linux-x86_64/550.127.05/README/kernel_open.html
 
 For vGPU support, please refer to the README.vgpu packaged in the vGPU Host
 Package for more details.

kernel-open/Kbuild

@@ -72,7 +72,7 @@ EXTRA_CFLAGS += -I$(src)/common/inc
 EXTRA_CFLAGS += -I$(src)
 EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-format-extra-args
 EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM
-EXTRA_CFLAGS += -DNV_VERSION_STRING=\"550.120\"
+EXTRA_CFLAGS += -DNV_VERSION_STRING=\"550.127.05\"
 
 ifneq ($(SYSSRCHOST1X),)
  EXTRA_CFLAGS += -I$(SYSSRCHOST1X)

kernel-open/nvidia-uvm/uvm.h

@@ -379,6 +379,17 @@ NV_STATUS UvmIsPageableMemoryAccessSupportedOnGpu(const NvProcessorUuid *gpuUuid
 //         OS state required to register the GPU is malformed, or the partition
 //         identified by the user handles or its configuration changed.
 //
+//     NV_ERR_NVSWITCH_FABRIC_NOT_READY:
+//         (On NvSwitch-connected system) Indicates that the fabric has not been
+//         configured yet. Caller must retry GPU registration.
+//
+//     NV_ERR_NVSWITCH_FABRIC_FAILURE:
+//         (On NvSwitch-connected systems) Indicates that the NvLink fabric
+//         failed to be configured.
+//
+//     NV_ERR_GPU_MEMORY_ONLINING_FAULURE:
+//         (On coherent systems) The GPU's memory onlining failed.
+//
 //     NV_ERR_GENERIC:
 //         Unexpected error. We try hard to avoid returning this error code,
 //         because it is not very informative.

kernel-open/nvidia-uvm/uvm_gpu.c

@@ -138,6 +138,7 @@ static NV_STATUS get_gpu_caps(uvm_gpu_t *gpu)
 
     if (gpu_caps.numaEnabled) {
         UVM_ASSERT(uvm_parent_gpu_is_coherent(gpu->parent));
+
         gpu->mem_info.numa.enabled = true;
         gpu->mem_info.numa.node_id = gpu_caps.numaNodeId;
     }
@@ -1280,7 +1281,8 @@ static NV_STATUS init_gpu(uvm_gpu_t *gpu, const UvmGpuInfo *gpu_info)
 
     status = get_gpu_caps(gpu);
     if (status != NV_OK) {
-        UVM_ERR_PRINT("Failed to get GPU caps: %s, GPU %s\n", nvstatusToString(status), uvm_gpu_name(gpu));
+        if (status != NV_ERR_NVSWITCH_FABRIC_NOT_READY)
+            UVM_ERR_PRINT("Failed to get GPU caps: %s, GPU %s\n", nvstatusToString(status), uvm_gpu_name(gpu));
         return status;
     }
 

kernel-open/nvidia/nv-pci.c

@@ -40,6 +40,9 @@
 #if !defined(NV_BUS_TYPE_HAS_IOMMU_OPS)
 #include <linux/iommu.h>
 #endif
+#if NV_IS_EXPORT_SYMBOL_GPL_pci_ats_supported
+#include <linux/pci-ats.h>
+#endif
 
 static void
 nv_check_and_exclude_gpu(
@@ -781,10 +784,15 @@ next_bar:
     // PPC64LE platform where ATS is currently supported (IBM P9).
     nv_ats_supported &= nv_platform_supports_numa(nvl);
 #else
-#if defined(NV_PCI_DEV_HAS_ATS_ENABLED)
+#if NV_IS_EXPORT_SYMBOL_GPL_pci_ats_supported
+    nv_ats_supported &= pci_ats_supported(pci_dev);
+#elif defined(NV_PCI_DEV_HAS_ATS_ENABLED)
     nv_ats_supported &= pci_dev->ats_enabled;
+#else
+    nv_ats_supported = NV_FALSE;
 #endif
 #endif
+
     if (nv_ats_supported)
     {
         NV_DEV_PRINTF(NV_DBG_INFO, nv, "ATS supported by this GPU!\n");

kernel-open/nvidia/nv.c

@@ -188,11 +188,7 @@ struct semaphore nv_linux_devices_lock;
 
 // True if all the successfully probed devices support ATS
 // Assigned at device probe (module init) time
-NvBool nv_ats_supported = NVCPU_IS_PPC64LE
+NvBool nv_ats_supported = NV_TRUE;
-#if defined(NV_PCI_DEV_HAS_ATS_ENABLED)
-                          || NV_TRUE
-#endif
-;
 
 // allow an easy way to convert all debug printfs related to events
 // back and forth between 'info' and 'errors'

kernel-open/nvidia/nvidia.Kbuild

@@ -231,6 +231,7 @@ NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tsec_comms_free_gsc
 NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_memory_block_size_bytes
 NV_CONFTEST_SYMBOL_COMPILE_TESTS += crypto
 NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_follow_pte
+NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl_pci_ats_supported
 
 NV_CONFTEST_TYPE_COMPILE_TESTS += dma_ops
 NV_CONFTEST_TYPE_COMPILE_TESTS += swiotlb_dma_ops

src/common/inc/nvBldVer.h

@@ -36,25 +36,25 @@
 // and then checked back in. You cannot make changes to these sections without
 // corresponding changes to the buildmeister script
 #ifndef NV_BUILD_BRANCH
-    #define NV_BUILD_BRANCH             r550_00
+    #define NV_BUILD_BRANCH             r553_17
 #endif
 #ifndef NV_PUBLIC_BRANCH
-    #define NV_PUBLIC_BRANCH             r550_00
+    #define NV_PUBLIC_BRANCH             r553_17
 #endif
 
 #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
-#define NV_BUILD_BRANCH_VERSION         "rel/gpu_drv/r550/r550_00-410"
+#define NV_BUILD_BRANCH_VERSION         "rel/gpu_drv/r550/r553_17-429"
-#define NV_BUILD_CHANGELIST_NUM         (34843164)
+#define NV_BUILD_CHANGELIST_NUM         (34957518)
 #define NV_BUILD_TYPE                   "Official"
-#define NV_BUILD_NAME                   "rel/gpu_drv/r550/r550_00-410"
+#define NV_BUILD_NAME                   "rel/gpu_drv/r550/r553_17-429"
-#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34843164)
+#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34957518)
 
 #else     /* Windows builds */
-#define NV_BUILD_BRANCH_VERSION         "r550_00-390"
+#define NV_BUILD_BRANCH_VERSION         "r553_17-2"
-#define NV_BUILD_CHANGELIST_NUM         (34843164)
+#define NV_BUILD_CHANGELIST_NUM         (34902203)
 #define NV_BUILD_TYPE                   "Official"
-#define NV_BUILD_NAME                   "553.09"
+#define NV_BUILD_NAME                   "553.20"
-#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34843164)
+#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34902203)
 #define NV_BUILD_BRANCH_BASE_VERSION    R550
 #endif
 // End buildmeister python edited section

src/common/inc/nvUnixVersion.h

@@ -4,7 +4,7 @@
 #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
     (defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
 
-#define NV_VERSION_STRING               "550.120"
+#define NV_VERSION_STRING               "550.127.05"
 
 #else
 

src/common/inc/swref/published/nvswitch/ls10/dev_ctrl_ip_addendum.h

@@ -62,4 +62,14 @@
 #define NV_CTRL_CPU_INTR_UNITS_PRIV_RING                      15:15
 #define NV_CTRL_CPU_INTR_UNITS_FSP                            16:16
 
+#define NV_CTRL_CPU_INTR_TOP_LEAF_BIT(i)                      (i/2):(i/2)
+#define NV_CTRL_CPU_INTR_TOP_LEAF_INTR_UNITS                  NV_CTRL_CPU_INTR_TOP_LEAF_BIT(NV_CTRL_CPU_INTR_UNITS_IDX)
+#define NV_CTRL_CPU_INTR_TOP_LEAF_INTR_NPG_FATAL              NV_CTRL_CPU_INTR_TOP_LEAF_BIT(NV_CTRL_CPU_INTR_NPG_FATAL_IDX)
+#define NV_CTRL_CPU_INTR_TOP_LEAF_INTR_NPG_NON_FATAL          NV_CTRL_CPU_INTR_TOP_LEAF_BIT(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX)
+#define NV_CTRL_CPU_INTR_TOP_LEAF_INTR_NPG_CORRECTABLE        NV_CTRL_CPU_INTR_TOP_LEAF_BIT(NV_CTRL_CPU_INTR_NPG_CORRECTABLE_IDX)
+#define NV_CTRL_CPU_INTR_TOP_LEAF_INTR_NVLW_FATAL             NV_CTRL_CPU_INTR_TOP_LEAF_BIT(NV_CTRL_CPU_INTR_NVLW_FATAL_IDX)
+#define NV_CTRL_CPU_INTR_TOP_LEAF_INTR_NVLW_NON_FATAL         NV_CTRL_CPU_INTR_TOP_LEAF_BIT(NV_CTRL_CPU_INTR_NVLW_NON_FATAL_IDX)
+#define NV_CTRL_CPU_INTR_TOP_LEAF_INTR_NVLW_CORRECTABLE       NV_CTRL_CPU_INTR_TOP_LEAF_BIT(NV_CTRL_CPU_INTR_NVLW_CORRECTABLE_IDX)
+#define NV_CTRL_CPU_INTR_TOP_LEAF_INTR_NXBAR_FATAL            NV_CTRL_CPU_INTR_TOP_LEAF_BIT(NV_CTRL_CPU_INTR_NXBAR_FATAL_IDX)
+
 #endif // __ls10_dev_ctrl_ip_addendum_h__

src/common/nvswitch/kernel/ls10/intr_ls10.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -1348,6 +1348,13 @@ _nvswitch_service_route_nonfatal_ls10
         if (!(nvswitch_test_flags(report.raw_pending,
                 DRF_NUM(_ROUTE, _ERR_STATUS_0, _NVS_ECC_DBE_ERR, 1))))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _ROUTE, _ERR_NVS_ECC_ERROR_COUNTER);
             _nvswitch_collect_error_info_ls10(device, link,
                 NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME,
@@ -1372,6 +1379,13 @@ _nvswitch_service_route_nonfatal_ls10
         if (!(nvswitch_test_flags(report.raw_pending,
                 DRF_NUM(_ROUTE, _ERR_STATUS_0, _GLT_ECC_DBE_ERR, 1))))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _ROUTE, _ERR_GLT_ECC_ERROR_COUNTER);
             _nvswitch_collect_error_info_ls10(device, link,
                 NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME,
@@ -1396,6 +1410,13 @@ _nvswitch_service_route_nonfatal_ls10
         if (!(nvswitch_test_flags(report.raw_pending,
                 DRF_NUM(_ROUTE, _ERR_STATUS_0, _MCRID_ECC_DBE_ERR, 1))))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _ROUTE, _ERR_MCRID_ECC_ERROR_COUNTER);
             _nvswitch_collect_error_info_ls10(device, link,
                 NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME,
@@ -1420,6 +1441,13 @@ _nvswitch_service_route_nonfatal_ls10
         if (!(nvswitch_test_flags(report.raw_pending,
                 DRF_NUM(_ROUTE, _ERR_STATUS_0, _EXTMCRID_ECC_DBE_ERR, 1))))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _ROUTE, _ERR_EXTMCRID_ECC_ERROR_COUNTER);
             _nvswitch_collect_error_info_ls10(device, link,
                 NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME,
@@ -1444,6 +1472,13 @@ _nvswitch_service_route_nonfatal_ls10
         if (!(nvswitch_test_flags(report.raw_pending,
                 DRF_NUM(_ROUTE, _ERR_STATUS_0, _RAM_ECC_DBE_ERR, 1))))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _ROUTE, _ERR_RAM_ECC_ERROR_COUNTER);
             _nvswitch_collect_error_info_ls10(device, link,
                 NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME,
@@ -1584,6 +1619,13 @@ _nvswitch_service_ingress_fatal_ls10
         // Clear associated LIMIT_ERR interrupt
         if (report.raw_pending & DRF_NUM(_INGRESS, _ERR_STATUS_0, _NCISOC_HDR_ECC_LIMIT_ERR, 1))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             NVSWITCH_ENG_WR32(device, NPORT, , link, _INGRESS, _ERR_STATUS_0,
                 DRF_NUM(_INGRESS, _ERR_STATUS_0, _NCISOC_HDR_ECC_LIMIT_ERR, 1));
         }
@@ -1832,6 +1874,13 @@ _nvswitch_service_ingress_nonfatal_ls10
         if (!(nvswitch_test_flags(report.raw_pending,
                 DRF_NUM(_INGRESS, _ERR_STATUS_0, _NCISOC_HDR_ECC_DBE_ERR, 1))))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_NCISOC_HDR_ECC_ERROR_COUNTER);
             NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_NCISOC_HDR_ECC_LIMIT_ERR, "ingress header ECC");
             NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_NCISOC_HDR_ECC_LIMIT_ERR, data);
@@ -1878,6 +1927,13 @@ _nvswitch_service_ingress_nonfatal_ls10
         if (!(nvswitch_test_flags(report.raw_pending,
                 DRF_NUM(_INGRESS, _ERR_STATUS_0, _REMAPTAB_ECC_DBE_ERR, 1))))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_REMAPTAB_ECC_ERROR_COUNTER);
             NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_REMAPTAB_ECC_LIMIT_ERR, "ingress remap ECC");
             NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_REMAPTAB_ECC_LIMIT_ERR, data);
@@ -1899,6 +1955,13 @@ _nvswitch_service_ingress_nonfatal_ls10
         if (!(nvswitch_test_flags(report.raw_pending,
                 DRF_NUM(_INGRESS, _ERR_STATUS_0, _RIDTAB_ECC_DBE_ERR, 1))))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_RIDTAB_ECC_ERROR_COUNTER);
             NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_RIDTAB_ECC_LIMIT_ERR, "ingress RID ECC");
             NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_RIDTAB_ECC_LIMIT_ERR, data);
@@ -1920,6 +1983,13 @@ _nvswitch_service_ingress_nonfatal_ls10
         if (!(nvswitch_test_flags(report.raw_pending,
                 DRF_NUM(_INGRESS, _ERR_STATUS_0, _RLANTAB_ECC_DBE_ERR, 1))))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_RLANTAB_ECC_ERROR_COUNTER);
             NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_RLANTAB_ECC_LIMIT_ERR, "ingress RLAN ECC");
             NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_RLANTAB_ECC_LIMIT_ERR, data);
@@ -2087,6 +2157,13 @@ _nvswitch_service_ingress_nonfatal_ls10_err_status_1:
         if (!(nvswitch_test_flags(raw_pending_0,
                 DRF_NUM(_INGRESS, _ERR_STATUS_0, _EXTAREMAPTAB_ECC_DBE_ERR, 1))))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_EXTAREMAPTAB_ECC_ERROR_COUNTER);
             NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_EXTAREMAPTAB_ECC_LIMIT_ERR, "ingress ExtA remap ECC");
             NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_EXTAREMAPTAB_ECC_LIMIT_ERR, data);
@@ -2108,6 +2185,13 @@ _nvswitch_service_ingress_nonfatal_ls10_err_status_1:
         if (!(nvswitch_test_flags(raw_pending_0,
                 DRF_NUM(_INGRESS, _ERR_STATUS_0, _EXTBREMAPTAB_ECC_DBE_ERR, 1))))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_EXTBREMAPTAB_ECC_ERROR_COUNTER);
             NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_EXTBREMAPTAB_ECC_LIMIT_ERR, "ingress ExtB remap ECC");
             NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_EXTBREMAPTAB_ECC_LIMIT_ERR, data);
@@ -2129,6 +2213,13 @@ _nvswitch_service_ingress_nonfatal_ls10_err_status_1:
         if (!(nvswitch_test_flags(raw_pending_0,
                 DRF_NUM(_INGRESS, _ERR_STATUS_0, _MCREMAPTAB_ECC_DBE_ERR, 1))))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_MCREMAPTAB_ECC_ERROR_COUNTER);
             NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_MCREMAPTAB_ECC_LIMIT_ERR, "ingress MC remap ECC");
             NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_MCREMAPTAB_ECC_LIMIT_ERR, data);
@@ -2262,8 +2353,6 @@ _nvswitch_service_tstate_nonfatal_ls10
             }
 
             report.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _TSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER);
-            NVSWITCH_ENG_WR32(device, NPORT, , link, _TSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER,
-                DRF_DEF(_TSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT));
             NVSWITCH_REPORT_NONFATAL(_HW_NPORT_TSTATE_TAGPOOL_ECC_LIMIT_ERR, "TS tag store single-bit threshold");
             _nvswitch_collect_error_info_ls10(device, link,
                 NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_TIME |
@@ -2272,6 +2361,15 @@ _nvswitch_service_tstate_nonfatal_ls10
                 &data);
             NVSWITCH_REPORT_DATA(_HW_NPORT_TSTATE_TAGPOOL_ECC_LIMIT_ERR, data);
 
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+            NVSWITCH_ENG_WR32(device, NPORT, , link, _TSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER,
+                DRF_DEF(_TSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT));
+
             _nvswitch_construct_ecc_error_event_ls10(&err_event,
                 NVSWITCH_ERR_HW_NPORT_TSTATE_TAGPOOL_ECC_LIMIT_ERR, link,
                 bAddressValid, address, NV_FALSE, 1);
@@ -2303,8 +2401,6 @@ _nvswitch_service_tstate_nonfatal_ls10
             }
 
             report.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _TSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER);
-            NVSWITCH_ENG_WR32(device, NPORT, , link, _TSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER,
-                DRF_DEF(_TSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT));
             NVSWITCH_REPORT_NONFATAL(_HW_NPORT_TSTATE_CRUMBSTORE_ECC_LIMIT_ERR, "TS crumbstore single-bit threshold");
             _nvswitch_collect_error_info_ls10(device, link,
                 NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_TIME |
@@ -2313,6 +2409,15 @@ _nvswitch_service_tstate_nonfatal_ls10
                 &data);
             NVSWITCH_REPORT_DATA(_HW_NPORT_TSTATE_CRUMBSTORE_ECC_LIMIT_ERR, data);
 
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+            NVSWITCH_ENG_WR32(device, NPORT, , link, _TSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER,
+                DRF_DEF(_TSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT));
+
             _nvswitch_construct_ecc_error_event_ls10(&err_event,
                 NVSWITCH_ERR_HW_NPORT_TSTATE_CRUMBSTORE_ECC_LIMIT_ERR, link,
                 bAddressValid, address, NV_FALSE, 1);
@@ -2427,6 +2532,13 @@ _nvswitch_service_tstate_fatal_ls10
         // Clear associated LIMIT_ERR interrupt
         if (report.raw_pending & DRF_NUM(_TSTATE, _ERR_STATUS_0, _TAGPOOL_ECC_LIMIT_ERR, 1))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             NVSWITCH_ENG_WR32(device, NPORT, , link, _TSTATE, _ERR_STATUS_0,
                 DRF_NUM(_TSTATE, _ERR_STATUS_0, _TAGPOOL_ECC_LIMIT_ERR, 1));
         }
@@ -2482,6 +2594,13 @@ _nvswitch_service_tstate_fatal_ls10
         // Clear associated LIMIT_ERR interrupt
         if (report.raw_pending & DRF_NUM(_TSTATE, _ERR_STATUS_0, _CRUMBSTORE_ECC_LIMIT_ERR, 1))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             NVSWITCH_ENG_WR32(device, NPORT, , link, _TSTATE, _ERR_STATUS_0,
                 DRF_NUM(_TSTATE, _ERR_STATUS_0, _CRUMBSTORE_ECC_LIMIT_ERR, 1));
         }
@@ -2590,6 +2709,13 @@ _nvswitch_service_egress_nonfatal_ls10
         if (!(nvswitch_test_flags(report.raw_pending,
                 DRF_NUM(_EGRESS, _ERR_STATUS_0, _NXBAR_HDR_ECC_DBE_ERR, 1))))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _ERR_NXBAR_ECC_ERROR_COUNTER);
             NVSWITCH_REPORT_NONFATAL(_HW_NPORT_EGRESS_NXBAR_HDR_ECC_LIMIT_ERR, "egress input ECC error limit");
             NVSWITCH_REPORT_DATA(_HW_NPORT_EGRESS_NXBAR_HDR_ECC_LIMIT_ERR, data);
@@ -2629,6 +2755,13 @@ _nvswitch_service_egress_nonfatal_ls10
             NVSWITCH_REPORT_NONFATAL(_HW_NPORT_EGRESS_RAM_OUT_HDR_ECC_LIMIT_ERR, "egress output ECC error limit");
             NVSWITCH_REPORT_DATA(_HW_NPORT_EGRESS_RAM_OUT_HDR_ECC_LIMIT_ERR, data);
 
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             _nvswitch_construct_ecc_error_event_ls10(&err_event,
                 NVSWITCH_ERR_HW_NPORT_EGRESS_RAM_OUT_HDR_ECC_LIMIT_ERR, link, bAddressValid, address,
                 NV_FALSE, 1);
@@ -2695,6 +2828,16 @@ _nvswitch_service_egress_nonfatal_ls10_err_status_1:
         if (!(nvswitch_test_flags(report.raw_pending,
                 DRF_NUM(_EGRESS, _ERR_STATUS_1, _NXBAR_REDUCTION_HDR_ECC_DBE_ERR, 1))))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
+
+            NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_NXBAR_REDUCTION_ECC_ERROR_COUNTER, 0);
+
             NVSWITCH_REPORT_NONFATAL(_HW_NPORT_EGRESS_NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR, "egress reduction header ECC error limit");
             NVSWITCH_REPORT_DATA(_HW_NPORT_EGRESS_NXBAR_HDR_ECC_LIMIT_ERR, data);
 
@@ -2715,6 +2858,15 @@ _nvswitch_service_egress_nonfatal_ls10_err_status_1:
         if (!(nvswitch_test_flags(report.raw_pending,
                 DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCRSPCTRLSTORE_ECC_DBE_ERR, 1))))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
+            NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_MCRSPCTRLSTORE_ECC_ERROR_COUNTER, 0);
+
             NVSWITCH_REPORT_NONFATAL(_HW_NPORT_EGRESS_MCRSPCTRLSTORE_ECC_LIMIT_ERR, "egress MC response ECC error limit");
             NVSWITCH_REPORT_DATA(_HW_NPORT_EGRESS_MCRSPCTRLSTORE_ECC_LIMIT_ERR, data);
 
@@ -2735,6 +2887,15 @@ _nvswitch_service_egress_nonfatal_ls10_err_status_1:
         if (!(nvswitch_test_flags(report.raw_pending,
                 DRF_NUM(_EGRESS, _ERR_STATUS_1, _RBCTRLSTORE_ECC_DBE_ERR, 1))))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
+            NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_RBCTRLSTORE_ECC_ERROR_COUNTER, 0);
+
             NVSWITCH_REPORT_NONFATAL(_HW_NPORT_EGRESS_RBCTRLSTORE_ECC_LIMIT_ERR, "egress RB ECC error limit");
             NVSWITCH_REPORT_DATA(_HW_NPORT_EGRESS_RBCTRLSTORE_ECC_LIMIT_ERR, data);
 
@@ -2755,6 +2916,15 @@ _nvswitch_service_egress_nonfatal_ls10_err_status_1:
         if (!(nvswitch_test_flags(report.raw_pending,
                 DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCREDSGT_ECC_DBE_ERR, 1))))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
+            NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_MCREDSGT_ECC_ERROR_COUNTER, 0);
+
             NVSWITCH_REPORT_NONFATAL(_HW_NPORT_EGRESS_MCREDSGT_ECC_LIMIT_ERR, "egress RSG ECC error limit");
             NVSWITCH_REPORT_DATA(_HW_NPORT_EGRESS_MCREDSGT_ECC_LIMIT_ERR, data);
 
@@ -2775,6 +2945,15 @@ _nvswitch_service_egress_nonfatal_ls10_err_status_1:
         if (!(nvswitch_test_flags(report.raw_pending,
                 DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCREDBUF_ECC_DBE_ERR, 1))))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
+            NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_MCREDBUF_ECC_ERROR_COUNTER, 0);
+
             NVSWITCH_REPORT_NONFATAL(_HW_NPORT_EGRESS_MCREDBUF_ECC_LIMIT_ERR, "egress MCRB ECC error limit");
             NVSWITCH_REPORT_DATA(_HW_NPORT_EGRESS_MCREDBUF_ECC_LIMIT_ERR, data);
 
@@ -2795,6 +2974,15 @@ _nvswitch_service_egress_nonfatal_ls10_err_status_1:
         if (!(nvswitch_test_flags(report.raw_pending,
                 DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCRSP_RAM_HDR_ECC_DBE_ERR, 1))))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
+            NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_MCRSP_RAM_ECC_ERROR_COUNTER, 0);
+
             NVSWITCH_REPORT_NONFATAL(_HW_NPORT_EGRESS_MCRSP_RAM_HDR_ECC_LIMIT_ERR, "egress MC header ECC error limit");
             NVSWITCH_REPORT_DATA(_HW_NPORT_EGRESS_MCRSP_RAM_HDR_ECC_LIMIT_ERR, data);
 
@@ -2824,6 +3012,13 @@ _nvswitch_service_egress_nonfatal_ls10_err_status_1:
         // Clear associated LIMIT_ERR interrupt
         if (report.raw_pending & DRF_NUM(_EGRESS, _ERR_STATUS_1, _NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR, 1))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_STATUS_1,
                 DRF_NUM(_EGRESS, _ERR_STATUS_1, _NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR, 1));
         }
@@ -2861,6 +3056,13 @@ _nvswitch_service_egress_nonfatal_ls10_err_status_1:
         // Clear associated LIMIT_ERR interrupt
         if (report.raw_pending & DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCREDBUF_ECC_LIMIT_ERR, 1))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_STATUS_1,
                 DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCREDBUF_ECC_LIMIT_ERR, 1));
         }
@@ -3008,6 +3210,13 @@ _nvswitch_service_egress_fatal_ls10
         // Clear associated LIMIT_ERR interrupt
         if (report.raw_pending & DRF_NUM(_EGRESS, _ERR_STATUS_0, _NXBAR_HDR_ECC_LIMIT_ERR, 1))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_STATUS_0,
                 DRF_NUM(_EGRESS, _ERR_STATUS_0, _NXBAR_HDR_ECC_LIMIT_ERR, 1));
         }
@@ -3042,6 +3251,13 @@ _nvswitch_service_egress_fatal_ls10
         // Clear associated LIMIT_ERR interrupt
         if (report.raw_pending & DRF_NUM(_EGRESS, _ERR_STATUS_0, _RAM_OUT_HDR_ECC_LIMIT_ERR, 1))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_STATUS_0,
                 DRF_NUM(_EGRESS, _ERR_STATUS_0, _RAM_OUT_HDR_ECC_LIMIT_ERR, 1));
         }
@@ -3230,6 +3446,13 @@ _nvswitch_service_egress_fatal_ls10_err_status_1:
         // Clear associated LIMIT_ERR interrupt
         if (report.raw_pending & DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCRSPCTRLSTORE_ECC_LIMIT_ERR, 1))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_STATUS_1,
                 DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCRSPCTRLSTORE_ECC_LIMIT_ERR, 1));
         }
@@ -3251,6 +3474,13 @@ _nvswitch_service_egress_fatal_ls10_err_status_1:
         // Clear associated LIMIT_ERR interrupt
         if (report.raw_pending & DRF_NUM(_EGRESS, _ERR_STATUS_1, _RBCTRLSTORE_ECC_LIMIT_ERR, 1))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_STATUS_1,
                 DRF_NUM(_EGRESS, _ERR_STATUS_1, _RBCTRLSTORE_ECC_LIMIT_ERR, 1));
         }
@@ -3272,6 +3502,13 @@ _nvswitch_service_egress_fatal_ls10_err_status_1:
         // Clear associated LIMIT_ERR interrupt
         if (report.raw_pending & DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCREDSGT_ECC_LIMIT_ERR, 1))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_STATUS_1,
                 DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCREDSGT_ECC_LIMIT_ERR, 1));
         }
@@ -3293,6 +3530,13 @@ _nvswitch_service_egress_fatal_ls10_err_status_1:
         // Clear associated LIMIT_ERR interrupt
         if (report.raw_pending & DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCRSP_RAM_HDR_ECC_LIMIT_ERR, 1))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_STATUS_1,
                 DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCRSP_RAM_HDR_ECC_LIMIT_ERR, 1));
         }
@@ -3392,6 +3636,13 @@ _nvswitch_service_sourcetrack_nonfatal_ls10
             NVSWITCH_REPORT_NONFATAL(_HW_NPORT_SOURCETRACK_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR,
                                     "sourcetrack TCEN0 crumbstore ECC limit err");
 
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             _nvswitch_construct_ecc_error_event_ls10(&err_event,
                 NVSWITCH_ERR_HW_NPORT_SOURCETRACK_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR, link,
                 bAddressValid, address, NV_FALSE, 1);
@@ -3491,6 +3742,13 @@ _nvswitch_service_sourcetrack_fatal_ls10
         // Clear associated LIMIT_ERR interrupt
         if (report.raw_pending & DRF_NUM(_SOURCETRACK, _ERR_STATUS_0, _CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR, 1))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             NVSWITCH_ENG_WR32(device, NPORT, , link, _SOURCETRACK, _ERR_STATUS_0,
                 DRF_NUM(_SOURCETRACK, _ERR_STATUS_0, _CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR, 1));
         }
@@ -3619,11 +3877,19 @@ _nvswitch_service_multicast_nonfatal_ls10
             }
 
             report.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER);
-            NVSWITCH_ENG_WR32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER,
-                DRF_DEF(_MULTICASTTSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT));
             NVSWITCH_REPORT_NONFATAL(_HW_NPORT_MULTICASTTSTATE_TAGPOOL_ECC_LIMIT_ERR, "MC TS tag store single-bit threshold");
             NVSWITCH_REPORT_DATA(_HW_NPORT_MULTICASTTSTATE_TAGPOOL_ECC_LIMIT_ERR, data);
 
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
+            NVSWITCH_ENG_WR32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER,
+                DRF_DEF(_MULTICASTTSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT));
+
             _nvswitch_construct_ecc_error_event_ls10(&err_event,
                 NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_TAGPOOL_ECC_LIMIT_ERR, link,
                 bAddressValid, address, NV_FALSE, 1);
@@ -3655,11 +3921,19 @@ _nvswitch_service_multicast_nonfatal_ls10
             }
 
             report.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER);
-            NVSWITCH_ENG_WR32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER,
-                DRF_DEF(_MULTICASTTSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT));
             NVSWITCH_REPORT_NONFATAL(_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_ECC_LIMIT_ERR, "MC TS crumbstore single-bit threshold");
             NVSWITCH_REPORT_DATA(_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_ECC_LIMIT_ERR, data);
 
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
+            NVSWITCH_ENG_WR32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER,
+                DRF_DEF(_MULTICASTTSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT));
+
             _nvswitch_construct_ecc_error_event_ls10(&err_event,
                 NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_ECC_LIMIT_ERR, link,
                 bAddressValid, address, NV_FALSE, 1);
@@ -3772,6 +4046,13 @@ _nvswitch_service_multicast_fatal_ls10
         // Clear associated LIMIT_ERR interrupt
         if (report.raw_pending & DRF_NUM(_MULTICASTTSTATE, _ERR_STATUS_0, _TAGPOOL_ECC_LIMIT_ERR, 1))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             NVSWITCH_ENG_WR32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_STATUS_0,
                 DRF_NUM(_MULTICASTTSTATE, _ERR_STATUS_0, _TAGPOOL_ECC_LIMIT_ERR, 1));
         }
@@ -3809,6 +4090,13 @@ _nvswitch_service_multicast_fatal_ls10
         // Clear associated LIMIT_ERR interrupt
         if (report.raw_pending & DRF_NUM(_MULTICASTTSTATE, _ERR_STATUS_0, _CRUMBSTORE_ECC_LIMIT_ERR, 1))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             NVSWITCH_ENG_WR32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_STATUS_0,
                 DRF_NUM(_MULTICASTTSTATE, _ERR_STATUS_0, _CRUMBSTORE_ECC_LIMIT_ERR, 1));
         }
@@ -3910,11 +4198,19 @@ _nvswitch_service_reduction_nonfatal_ls10
             }
 
             report.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER);
-            NVSWITCH_ENG_WR32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER,
-                DRF_DEF(_REDUCTIONTSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT));
             NVSWITCH_REPORT_NONFATAL(_HW_NPORT_REDUCTIONTSTATE_TAGPOOL_ECC_LIMIT_ERR, "Red TS tag store single-bit threshold");
             NVSWITCH_REPORT_DATA(_HW_NPORT_REDUCTIONTSTATE_TAGPOOL_ECC_LIMIT_ERR, data);
 
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
+            NVSWITCH_ENG_WR32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER,
+                DRF_DEF(_REDUCTIONTSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT));
+
             _nvswitch_construct_ecc_error_event_ls10(&err_event,
                 NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_TAGPOOL_ECC_LIMIT_ERR, link,
                 bAddressValid, address, NV_FALSE, 1);
@@ -3946,11 +4242,19 @@ _nvswitch_service_reduction_nonfatal_ls10
             }
 
             report.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER);
-            NVSWITCH_ENG_WR32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER,
-                DRF_DEF(_REDUCTIONTSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT));
             NVSWITCH_REPORT_NONFATAL(_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_ECC_LIMIT_ERR, "Red TS crumbstore single-bit threshold");
             NVSWITCH_REPORT_DATA(_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_ECC_LIMIT_ERR, data);
 
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
+            NVSWITCH_ENG_WR32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER,
+                DRF_DEF(_REDUCTIONTSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT));
+
             _nvswitch_construct_ecc_error_event_ls10(&err_event,
                 NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_ECC_LIMIT_ERR, link,
                 bAddressValid, address, NV_FALSE, 1);
@@ -4063,6 +4367,13 @@ _nvswitch_service_reduction_fatal_ls10
         // Clear associated LIMIT_ERR interrupt
         if (report.raw_pending & DRF_NUM(_REDUCTIONTSTATE, _ERR_STATUS_0, _TAGPOOL_ECC_LIMIT_ERR, 1))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             NVSWITCH_ENG_WR32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_STATUS_0,
                 DRF_NUM(_REDUCTIONTSTATE, _ERR_STATUS_0, _TAGPOOL_ECC_LIMIT_ERR, 1));
         }
@@ -4105,6 +4416,13 @@ _nvswitch_service_reduction_fatal_ls10
         // Clear associated LIMIT_ERR interrupt
         if (report.raw_pending & DRF_NUM(_REDUCTIONTSTATE, _ERR_STATUS_0, _CRUMBSTORE_ECC_LIMIT_ERR, 1))
         {
+            //
+            // Driver WAR to disable NPG interrupt at GIN to prevent interrupt storm.
+            // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+            //
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX),
+                NVBIT(link / NVSWITCH_LINKS_PER_NPG_LS10));
+
             NVSWITCH_ENG_WR32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_STATUS_0,
                 DRF_NUM(_REDUCTIONTSTATE, _ERR_STATUS_0, _CRUMBSTORE_ECC_LIMIT_ERR, 1));
         }
@@ -4493,6 +4811,14 @@ _nvswitch_service_nvltlc_tx_sys_fatal_ls10
     {
         NVSWITCH_REPORT_FATAL(_HW_NVLTLC_TX_SYS_NCISOC_ECC_LIMIT_ERR, "NCISOC ECC Limit Error", NV_FALSE);
         nvswitch_clear_flags(&unhandled, bit);
+
+        //
+        // Driver WAR to disable ECC error and prevent an interrupt storm.
+        // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+        //
+        NVSWITCH_LINK_WR32_LS10(device, link, NVLTLC, _NVLTLC_TX_SYS, _ERR_FATAL_REPORT_EN_0,
+            report.raw_enable &
+            ~DRF_NUM(_NVLTLC_TX_SYS, _ERR_FATAL_REPORT_EN_0, _NCISOC_ECC_LIMIT_ERR, 1));
     }
 
     bit = DRF_NUM(_NVLTLC_TX_SYS, _ERR_STATUS_0, _TXPOISONDET, 1);
@@ -4603,6 +4929,14 @@ _nvswitch_service_nvltlc_rx_sys_fatal_ls10
     {
         NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_SYS_HDR_RAM_ECC_LIMIT_ERR, "HDR RAM ECC Limit Error", NV_FALSE);
         nvswitch_clear_flags(&unhandled, bit);
+
+        //
+        // Driver WAR to disable ECC error and prevent an interrupt storm.
+        // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+        //
+        NVSWITCH_LINK_WR32_LS10(device, link, NVLTLC, _NVLTLC_RX_SYS, _ERR_FATAL_REPORT_EN_0,
+            report.raw_enable &
+            ~DRF_NUM(_NVLTLC_RX_SYS, _ERR_FATAL_REPORT_EN_0, _HDR_RAM_ECC_LIMIT_ERR, 1));
     }
 
     bit = DRF_NUM(_NVLTLC_RX_SYS, _ERR_STATUS_0, _DAT0_RAM_ECC_DBE_ERR, 1);
@@ -4622,6 +4956,14 @@ _nvswitch_service_nvltlc_rx_sys_fatal_ls10
     {
         NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_SYS_DAT0_RAM_ECC_LIMIT_ERR, "DAT0 RAM ECC Limit Error", NV_FALSE);
         nvswitch_clear_flags(&unhandled, bit);
+
+        //
+        // Driver WAR to disable ECC error and prevent an interrupt storm.
+        // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+        //
+        NVSWITCH_LINK_WR32_LS10(device, link, NVLTLC, _NVLTLC_RX_SYS, _ERR_FATAL_REPORT_EN_0,
+            report.raw_enable &
+            ~DRF_NUM(_NVLTLC_RX_SYS, _ERR_FATAL_REPORT_EN_0, _DAT0_RAM_ECC_LIMIT_ERR, 1));
     }
 
     bit = DRF_NUM(_NVLTLC_RX_SYS, _ERR_STATUS_0, _DAT1_RAM_ECC_DBE_ERR, 1);
@@ -4641,6 +4983,14 @@ _nvswitch_service_nvltlc_rx_sys_fatal_ls10
     {
         NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_SYS_DAT1_RAM_ECC_LIMIT_ERR, "DAT1 RAM ECC Limit Error", NV_FALSE);
         nvswitch_clear_flags(&unhandled, bit);
+
+        //
+        // Driver WAR to disable ECC error and prevent an interrupt storm.
+        // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+        //
+        NVSWITCH_LINK_WR32_LS10(device, link, NVLTLC, _NVLTLC_RX_SYS, _ERR_FATAL_REPORT_EN_0,
+            report.raw_enable &
+            ~DRF_NUM(_NVLTLC_RX_SYS, _ERR_FATAL_REPORT_EN_0, _DAT1_RAM_ECC_LIMIT_ERR, 1));
     }
 
     if (report.raw_first & report.mask)
@@ -6305,6 +6655,14 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_0_ls10
     {
         NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_CREQ_RAM_ECC_LIMIT_ERR, "CREQ RAM DAT ECC Limit Error");
         nvswitch_clear_flags(&unhandled, bit);
+
+        //
+        // Driver WAR to disable ECC error and prevent an interrupt storm.
+        // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+        //
+        NVSWITCH_LINK_WR32_LS10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_FATAL_REPORT_EN_0,
+            report.raw_enable &
+            ~DRF_NUM(_NVLTLC_TX_LNK, _ERR_FATAL_REPORT_EN_0, _CREQ_RAM_ECC_LIMIT_ERR, 1));
     }
 
     bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_0, _RSP_RAM_DAT_ECC_DBE_ERR, 1);
@@ -6319,6 +6677,14 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_0_ls10
     {
         NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_RSP_RAM_ECC_LIMIT_ERR, "Response RAM ECC Limit Error");
         nvswitch_clear_flags(&unhandled, bit);
+
+        //
+        // Driver WAR to disable ECC error and prevent an interrupt storm.
+        // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+        //
+        NVSWITCH_LINK_WR32_LS10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_FATAL_REPORT_EN_0,
+            report.raw_enable &
+            ~DRF_NUM(_NVLTLC_TX_LNK, _ERR_FATAL_REPORT_EN_0, _RSP_RAM_ECC_LIMIT_ERR, 1));
     }
 
     bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_0, _COM_RAM_DAT_ECC_DBE_ERR, 1);
@@ -6338,6 +6704,14 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_0_ls10
     {
         NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_COM_RAM_ECC_LIMIT_ERR, "COM RAM ECC Limit Error");
         nvswitch_clear_flags(&unhandled, bit);
+
+        //
+        // Driver WAR to disable ECC error and prevent an interrupt storm.
+        // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+        //
+        NVSWITCH_LINK_WR32_LS10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_FATAL_REPORT_EN_0,
+            report.raw_enable &
+            ~DRF_NUM(_NVLTLC_TX_LNK, _ERR_FATAL_REPORT_EN_0, _COM_RAM_ECC_LIMIT_ERR, 1));
     }
 
     bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_0, _RSP1_RAM_ECC_LIMIT_ERR, 1);
@@ -6345,6 +6719,14 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_0_ls10
     {
         NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_RSP1_RAM_ECC_LIMIT_ERR, "RSP1 RAM ECC Limit Error");
         nvswitch_clear_flags(&unhandled, bit);
+
+        //
+        // Driver WAR to disable ECC error and prevent an interrupt storm.
+        // TODO: Clear ECC_ERROR_COUNTER by sending command to SOE and remove the WAR.
+        //
+        NVSWITCH_LINK_WR32_LS10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_FATAL_REPORT_EN_0,
+            report.raw_enable &
+            ~DRF_NUM(_NVLTLC_TX_LNK, _ERR_FATAL_REPORT_EN_0, _RSP1_RAM_ECC_LIMIT_ERR, 1));
     }
 
     NVSWITCH_UNHANDLED_CHECK(device, unhandled);
@@ -7417,206 +7799,238 @@ nvswitch_lib_service_interrupts_ls10
     NvlStatus   status = NVL_SUCCESS;
     NvlStatus   return_status = NVL_SUCCESS;
     NvU32 val;
+    NvU32 topEnable;
+    NvU32 topIntr;
     NvU32 i;
 
     //
     // Interrupt handler steps:
+    // 1. Read Top Interrupt
     // 1. Read Leaf interrupt
     // 2. Clear leaf interrupt
     // 3. Run leaf specific interrupt handler
     //
-    val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NVLW_NON_FATAL);
+
-    val = DRF_VAL(_CTRL, _CPU_INTR_NVLW_NON_FATAL, _MASK, val);
+    topEnable = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_TOP_EN_SET(0));
-    if (val != 0)
+    topIntr   = topEnable & NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_TOP(0));
+
+    if (FLD_TEST_DRF_NUM(_CTRL, _CPU_INTR_TOP_LEAF, _INTR_NVLW_NON_FATAL, 0x1, topIntr))
     {
-        NVSWITCH_PRINT(device, INFO, "%s: NVLW NON_FATAL interrupts pending = 0x%x\n",
+        val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NVLW_NON_FATAL);
-            __FUNCTION__, val);
+        val = DRF_VAL(_CTRL, _CPU_INTR_NVLW_NON_FATAL, _MASK, val);
-        NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NVLW_NON_FATAL_IDX), val);
+        if (val != 0)
-        for (i = 0; i < DRF_SIZE(NV_CTRL_CPU_INTR_NVLW_NON_FATAL_MASK); i++)
         {
-            if (val & NVBIT(i))
+            NVSWITCH_PRINT(device, INFO, "%s: NVLW NON_FATAL interrupts pending = 0x%x\n",
+                __FUNCTION__, val);
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NVLW_NON_FATAL_IDX), val);
+            for (i = 0; i < DRF_SIZE(NV_CTRL_CPU_INTR_NVLW_NON_FATAL_MASK); i++)
             {
-                status = _nvswitch_service_nvlw_nonfatal_ls10(device, i);
+                if (val & NVBIT(i))
-                if (status != NVL_SUCCESS)
                 {
-                    NVSWITCH_PRINT(device, INFO, "%s: NVLW[%d] NON_FATAL interrupt handling status = %d\n",
+                    status = _nvswitch_service_nvlw_nonfatal_ls10(device, i);
-                        __FUNCTION__, i, status);
+                    if (status != NVL_SUCCESS)
-                    return_status = status;
+                    {
+                        NVSWITCH_PRINT(device, INFO, "%s: NVLW[%d] NON_FATAL interrupt handling status = %d\n",
+                            __FUNCTION__, i, status);
+                        return_status = status;
+                    }
                 }
             }
         }
     }
 
-    val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NVLW_FATAL);
+    if (FLD_TEST_DRF_NUM(_CTRL, _CPU_INTR_TOP_LEAF, _INTR_NVLW_FATAL, 0x1, topIntr))
-    val = DRF_VAL(_CTRL, _CPU_INTR_NVLW_FATAL, _MASK, val);
-    if (val != 0)
     {
-        NVSWITCH_PRINT(device, INFO, "%s: NVLW FATAL interrupts pending = 0x%x\n",
+        val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NVLW_FATAL);
-            __FUNCTION__, val);
+        val = DRF_VAL(_CTRL, _CPU_INTR_NVLW_FATAL, _MASK, val);
-
+        if (val != 0)
-        NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NVLW_FATAL_IDX), val);
-
-        for (i = 0; i < DRF_SIZE(NV_CTRL_CPU_INTR_NVLW_FATAL_MASK); i++)
         {
-            if (val & NVBIT(i))
+            NVSWITCH_PRINT(device, INFO, "%s: NVLW FATAL interrupts pending = 0x%x\n",
+                __FUNCTION__, val);
+
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NVLW_FATAL_IDX), val);
+
+            for (i = 0; i < DRF_SIZE(NV_CTRL_CPU_INTR_NVLW_FATAL_MASK); i++)
             {
-                status = _nvswitch_service_nvlw_fatal_ls10(device, i);
+                if (val & NVBIT(i))
-                if (status != NVL_SUCCESS)
                 {
-                    NVSWITCH_PRINT(device, INFO, "%s: NVLW[%d] FATAL interrupt handling status = %d\n",
+                    status = _nvswitch_service_nvlw_fatal_ls10(device, i);
-                        __FUNCTION__, i, status);
+                    if (status != NVL_SUCCESS)
-                    return_status = status;
+                    {
+                        NVSWITCH_PRINT(device, INFO, "%s: NVLW[%d] FATAL interrupt handling status = %d\n",
+                            __FUNCTION__, i, status);
+                        return_status = status;
+                    }
                 }
             }
         }
     }
 
-    val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NVLW_CORRECTABLE);
+    if (FLD_TEST_DRF_NUM(_CTRL, _CPU_INTR_TOP_LEAF, _INTR_NVLW_CORRECTABLE, 0x1, topIntr))
-    val = DRF_VAL(_CTRL, _CPU_INTR_NVLW_CORRECTABLE, _MASK, val);
-    if (val != 0)
     {
-        NVSWITCH_PRINT(device, ERROR, "%s: NVLW CORRECTABLE interrupts pending = 0x%x\n",
+        val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NVLW_CORRECTABLE);
-            __FUNCTION__, val);
+        val = DRF_VAL(_CTRL, _CPU_INTR_NVLW_CORRECTABLE, _MASK, val);
-        return_status = -NVL_MORE_PROCESSING_REQUIRED;
+        if (val != 0)
+        {
+            NVSWITCH_PRINT(device, ERROR, "%s: NVLW CORRECTABLE interrupts pending = 0x%x\n",
+                __FUNCTION__, val);
+            return_status = -NVL_MORE_PROCESSING_REQUIRED;
+        }
     }
 
     // Check NPG
-    val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NPG_FATAL);
+    if (FLD_TEST_DRF_NUM(_CTRL, _CPU_INTR_TOP_LEAF, _INTR_NPG_FATAL, 0x1, topIntr))
-    val = DRF_VAL(_CTRL, _CPU_INTR_NPG_FATAL, _MASK, val);
-    if (val != 0)
     {
-        NVSWITCH_PRINT(device, INFO, "%s: NPG FATAL interrupts pending = 0x%x\n",
+        val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NPG_FATAL);
-            __FUNCTION__, val);
+        val = DRF_VAL(_CTRL, _CPU_INTR_NPG_FATAL, _MASK, val);
-        NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NPG_FATAL_IDX), val);
+        if (val != 0)
-        for (i = 0; i < DRF_SIZE(NV_CTRL_CPU_INTR_NPG_FATAL_MASK); i++)
         {
-            if (val & NVBIT(i))
+            NVSWITCH_PRINT(device, INFO, "%s: NPG FATAL interrupts pending = 0x%x\n",
+                __FUNCTION__, val);
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NPG_FATAL_IDX), val);
+            for (i = 0; i < DRF_SIZE(NV_CTRL_CPU_INTR_NPG_FATAL_MASK); i++)
             {
-                status = _nvswitch_service_npg_fatal_ls10(device, i);
+                if (val & NVBIT(i))
-                if (status != NVL_SUCCESS)
                 {
-                    NVSWITCH_PRINT(device, INFO, "%s: NPG[%d] FATAL interrupt handling status = %d\n",
+                    status = _nvswitch_service_npg_fatal_ls10(device, i);
-                        __FUNCTION__, i, status);
+                    if (status != NVL_SUCCESS)
-                    return_status = status;
+                    {
+                        NVSWITCH_PRINT(device, INFO, "%s: NPG[%d] FATAL interrupt handling status = %d\n",
+                            __FUNCTION__, i, status);
+                        return_status = status;
+                    }
                 }
             }
         }
     }
 
-    val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NPG_NON_FATAL);
+    // Check NPG
-    val = DRF_VAL(_CTRL, _CPU_INTR_NPG_NON_FATAL, _MASK, val);
+    if (FLD_TEST_DRF_NUM(_CTRL, _CPU_INTR_TOP_LEAF, _INTR_NPG_NON_FATAL, 0x1, topIntr))
-    if (val != 0)
     {
-        NVSWITCH_PRINT(device, INFO, "%s: NPG NON_FATAL interrupts pending = 0x%x\n",
+        val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NPG_NON_FATAL);
-            __FUNCTION__, val);
+        val = DRF_VAL(_CTRL, _CPU_INTR_NPG_NON_FATAL, _MASK, val);
-        NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX), val);
+        if (val != 0)
-        for (i = 0; i < DRF_SIZE(NV_CTRL_CPU_INTR_NPG_NON_FATAL_MASK); i++)
         {
-            if (val & NVBIT(i))
+            NVSWITCH_PRINT(device, INFO, "%s: NPG NON_FATAL interrupts pending = 0x%x\n",
+                __FUNCTION__, val);
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX), val);
+            for (i = 0; i < DRF_SIZE(NV_CTRL_CPU_INTR_NPG_NON_FATAL_MASK); i++)
             {
-                status = _nvswitch_service_npg_nonfatal_ls10(device, i);
+                if (val & NVBIT(i))
-                if (status != NVL_SUCCESS)
                 {
-                    NVSWITCH_PRINT(device, INFO, "%s: NPG[%d] NON_FATAL interrupt handling status = %d\n",
+                    status = _nvswitch_service_npg_nonfatal_ls10(device, i);
-                        __FUNCTION__, i, status);
+                    if (status != NVL_SUCCESS)
-                    return_status = status;
+                    {
+                        NVSWITCH_PRINT(device, INFO, "%s: NPG[%d] NON_FATAL interrupt handling status = %d\n",
+                            __FUNCTION__, i, status);
+                        return_status = status;
+                    }
                 }
             }
         }
     }
 
-    val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NPG_CORRECTABLE);
+    if (FLD_TEST_DRF_NUM(_CTRL, _CPU_INTR_TOP_LEAF, _INTR_NPG_CORRECTABLE, 0x1, topIntr))
-    val = DRF_VAL(_CTRL, _CPU_INTR_NPG_CORRECTABLE, _MASK, val);
-    if (val != 0)
     {
-        NVSWITCH_PRINT(device, ERROR, "%s: NPG CORRECTABLE interrupts pending = 0x%x\n",
+        val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NPG_CORRECTABLE);
-            __FUNCTION__, val);
+        val = DRF_VAL(_CTRL, _CPU_INTR_NPG_CORRECTABLE, _MASK, val);
-        return_status = -NVL_MORE_PROCESSING_REQUIRED;
+        if (val != 0)
+        {
+            NVSWITCH_PRINT(device, ERROR, "%s: NPG CORRECTABLE interrupts pending = 0x%x\n",
+                __FUNCTION__, val);
+            return_status = -NVL_MORE_PROCESSING_REQUIRED;
+        }
     }
 
     // Check NXBAR
-    val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NXBAR_FATAL);
+    if (FLD_TEST_DRF_NUM(_CTRL, _CPU_INTR_TOP_LEAF, _INTR_NXBAR_FATAL, 0x1, topIntr))
-    val = DRF_VAL(_CTRL, _CPU_INTR_NXBAR_FATAL, _MASK, val);
-    if (val != 0)
     {
-        NVSWITCH_PRINT(device, INFO, "%s: NXBAR FATAL interrupts pending = 0x%x\n",
+        val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NXBAR_FATAL);
-            __FUNCTION__, val);
+        val = DRF_VAL(_CTRL, _CPU_INTR_NXBAR_FATAL, _MASK, val);
-        NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NXBAR_FATAL_IDX), val);
+        if (val != 0)
-        for (i = 0; i < DRF_SIZE(NV_CTRL_CPU_INTR_NXBAR_FATAL_MASK); i++)
         {
-            if (val & NVBIT(i))
+            NVSWITCH_PRINT(device, INFO, "%s: NXBAR FATAL interrupts pending = 0x%x\n",
+                __FUNCTION__, val);
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NXBAR_FATAL_IDX), val);
+            for (i = 0; i < DRF_SIZE(NV_CTRL_CPU_INTR_NXBAR_FATAL_MASK); i++)
             {
-                status = _nvswitch_service_nxbar_fatal_ls10(device, i);
+                if (val & NVBIT(i))
-                if (status != NVL_SUCCESS)
                 {
-                    NVSWITCH_PRINT(device, INFO, "%s: NXBAR[%d] FATAL interrupt handling status = %d\n",
+                    status = _nvswitch_service_nxbar_fatal_ls10(device, i);
-                        __FUNCTION__, i, status);
+                    if (status != NVL_SUCCESS)
-                    return_status = status;
+                    {
+                        NVSWITCH_PRINT(device, INFO, "%s: NXBAR[%d] FATAL interrupt handling status = %d\n",
+                            __FUNCTION__, i, status);
+                        return_status = status;
+                    }
                 }
             }
         }
     }
 
     // Check UNITS
-    val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_UNITS);
+    if (FLD_TEST_DRF_NUM(_CTRL, _CPU_INTR_TOP_LEAF, _INTR_UNITS, 0x1, topIntr))
-    if (val != 0)
     {
-        NVSWITCH_PRINT(device, MMIO, "%s: UNIT interrupts pending = 0x%x\n",
+        val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_UNITS);
-            __FUNCTION__, val);
+        if (val != 0)
+        {
+            NVSWITCH_PRINT(device, MMIO, "%s: UNIT interrupts pending = 0x%x\n",
+                __FUNCTION__, val);
 
-        NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF(NV_CTRL_CPU_INTR_UNITS_IDX), val);
+            NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF(NV_CTRL_CPU_INTR_UNITS_IDX), val);
-        if (FLD_TEST_DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PMGR_HOST, 1, val))
+            if (FLD_TEST_DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PMGR_HOST, 1, val))
-        {
-            NVSWITCH_PRINT(device, ERROR, "%s: _PMGR_HOST interrupt pending\n",
-                __FUNCTION__);
-            return_status = -NVL_MORE_PROCESSING_REQUIRED;
-        }
-        if (FLD_TEST_DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PTIMER, 1, val))
-        {
-            NVSWITCH_PRINT(device, ERROR, "%s: _PTIMER interrupt pending\n",
-                __FUNCTION__);
-            return_status = -NVL_MORE_PROCESSING_REQUIRED;
-        }
-        if (FLD_TEST_DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PTIMER_ALARM, 1, val))
-        {
-            NVSWITCH_PRINT(device, ERROR, "%s: _PTIMER_ALARM interrupt pending\n",
-                __FUNCTION__);
-            return_status = -NVL_MORE_PROCESSING_REQUIRED;
-        }
-        if (FLD_TEST_DRF_NUM(_CTRL, _CPU_INTR_UNITS, _XTL_CPU, 1, val))
-        {
-            NVSWITCH_PRINT(device, ERROR, "%s: _XTL_CPU interrupt pending\n",
-                __FUNCTION__);
-            return_status = -NVL_MORE_PROCESSING_REQUIRED;
-        }
-        if (FLD_TEST_DRF_NUM(_CTRL, _CPU_INTR_UNITS, _XAL_EP, 1, val))
-        {
-            NVSWITCH_PRINT(device, ERROR, "%s: _XAL_EP interrupt pending\n",
-                __FUNCTION__);
-            return_status = -NVL_MORE_PROCESSING_REQUIRED;
-        }
-        if (FLD_TEST_DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PRIV_RING, 1, val))
-        {
-            status = _nvswitch_service_priv_ring_ls10(device);
-            if (status != NVL_SUCCESS)
             {
-                NVSWITCH_PRINT(device, ERROR, "%s: Problem handling PRI errors\n",
+                NVSWITCH_PRINT(device, ERROR, "%s: _PMGR_HOST interrupt pending\n",
                     __FUNCTION__);
-                return_status = status;
+                return_status = -NVL_MORE_PROCESSING_REQUIRED;
             }
-        }
+            if (FLD_TEST_DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PTIMER, 1, val))
-        if (!IS_RTLSIM(device) && !IS_FMODEL(device))
-        {
-            if (FLD_TEST_DRF_NUM(_CTRL, _CPU_INTR_UNITS, _SEC0_INTR0_0, 1, val))
             {
-                status = _nvswitch_service_soe_fatal_ls10(device);
+                NVSWITCH_PRINT(device, ERROR, "%s: _PTIMER interrupt pending\n",
+                    __FUNCTION__);
+                return_status = -NVL_MORE_PROCESSING_REQUIRED;
+            }
+            if (FLD_TEST_DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PTIMER_ALARM, 1, val))
+            {
+                NVSWITCH_PRINT(device, ERROR, "%s: _PTIMER_ALARM interrupt pending\n",
+                    __FUNCTION__);
+                return_status = -NVL_MORE_PROCESSING_REQUIRED;
+            }
+            if (FLD_TEST_DRF_NUM(_CTRL, _CPU_INTR_UNITS, _XTL_CPU, 1, val))
+            {
+                NVSWITCH_PRINT(device, ERROR, "%s: _XTL_CPU interrupt pending\n",
+                    __FUNCTION__);
+                return_status = -NVL_MORE_PROCESSING_REQUIRED;
+            }
+            if (FLD_TEST_DRF_NUM(_CTRL, _CPU_INTR_UNITS, _XAL_EP, 1, val))
+            {
+                NVSWITCH_PRINT(device, ERROR, "%s: _XAL_EP interrupt pending\n",
+                    __FUNCTION__);
+                return_status = -NVL_MORE_PROCESSING_REQUIRED;
+            }
+            if (FLD_TEST_DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PRIV_RING, 1, val))
+            {
+                status = _nvswitch_service_priv_ring_ls10(device);
                 if (status != NVL_SUCCESS)
                 {
-                    NVSWITCH_PRINT(device, ERROR, "%s: Problem servicing SOE",
+                    NVSWITCH_PRINT(device, ERROR, "%s: Problem handling PRI errors\n",
                         __FUNCTION__);
                     return_status = status;
                 }
             }
+            if (!IS_RTLSIM(device) && !IS_FMODEL(device))
+            {
+                if (FLD_TEST_DRF_NUM(_CTRL, _CPU_INTR_UNITS, _SEC0_INTR0_0, 1, val))
+                {
+                    status = _nvswitch_service_soe_fatal_ls10(device);
+                    if (status != NVL_SUCCESS)
+                    {
+                        NVSWITCH_PRINT(device, ERROR, "%s: Problem servicing SOE",
+                            __FUNCTION__);
+                        return_status = status;
+                    }
+                }
+            }
         }
     }
 

src/common/nvswitch/kernel/nvswitch.c

@@ -6138,26 +6138,66 @@ nvswitch_lib_ctrl_tnvl_lock_only
                 _nvswitch_ctrl_get_inforom_bbx_temp_samples,
                 NVSWITCH_GET_TEMP_SAMPLES_PARAMS,
                 osPrivate, flags);
-        NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
+        NVSWITCH_DEV_CMD_DISPATCH(
                 CTRL_NVSWITCH_GET_ATTESTATION_CERTIFICATE_CHAIN,
                 _nvswitch_ctrl_get_attestation_certificate_chain,
-                NVSWITCH_GET_ATTESTATION_CERTIFICATE_CHAIN_PARAMS,
+                NVSWITCH_GET_ATTESTATION_CERTIFICATE_CHAIN_PARAMS);
-                osPrivate, flags);
+        NVSWITCH_DEV_CMD_DISPATCH(
-        NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
                 CTRL_NVSWITCH_GET_ATTESTATION_REPORT,
                 _nvswitch_ctrl_get_attestation_report,
-                NVSWITCH_GET_ATTESTATION_REPORT_PARAMS,
+                NVSWITCH_GET_ATTESTATION_REPORT_PARAMS);
-                osPrivate, flags);
+        NVSWITCH_DEV_CMD_DISPATCH(
-        NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
                 CTRL_NVSWITCH_GET_TNVL_STATUS,
                 _nvswitch_ctrl_get_tnvl_status,
-                NVSWITCH_GET_TNVL_STATUS_PARAMS,
+                NVSWITCH_GET_TNVL_STATUS_PARAMS);
-                osPrivate, flags);
         NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
                 CTRL_NVSWITCH_SET_FM_DRIVER_STATE,
                 nvswitch_ctrl_set_fm_driver_state,
                 NVSWITCH_SET_FM_DRIVER_STATE_PARAMS,
                 osPrivate, flags);
+        NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_ERRORS,
+                nvswitch_ctrl_get_errors,
+                NVSWITCH_GET_ERRORS_PARAMS);
+        NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_BIOS_INFO,
+                _nvswitch_ctrl_get_bios_info,
+                NVSWITCH_GET_BIOS_INFO_PARAMS);
+        NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_TEMPERATURE,
+                _nvswitch_ctrl_therm_read_temperature,
+                NVSWITCH_CTRL_GET_TEMPERATURE_PARAMS);
+        NVSWITCH_DEV_CMD_DISPATCH(
+                CTRL_NVSWITCH_GET_TEMPERATURE_LIMIT,
+                _nvswitch_ctrl_therm_get_temperature_limit,
+                NVSWITCH_CTRL_GET_TEMPERATURE_LIMIT_PARAMS);
+        NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_FATAL_ERROR_SCOPE,
+                _nvswitch_ctrl_get_fatal_error_scope,
+                NVSWITCH_GET_FATAL_ERROR_SCOPE_PARAMS);
+        NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_INFO,
+                _nvswitch_ctrl_get_info,
+                NVSWITCH_GET_INFO);
+        NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_VOLTAGE,
+                _nvswitch_ctrl_therm_read_voltage,
+                NVSWITCH_CTRL_GET_VOLTAGE_PARAMS);
+        NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_POWER,
+                _nvswitch_ctrl_therm_read_power,
+                NVSWITCH_GET_POWER_PARAMS);
+        NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_NVLINK_STATUS,
+                _nvswitch_ctrl_get_nvlink_status,
+                NVSWITCH_GET_NVLINK_STATUS_PARAMS);
+        NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
+                CTRL_NVSWITCH_GET_NVLINK_ECC_ERRORS,
+                _nvswitch_ctrl_get_nvlink_ecc_errors,
+                NVSWITCH_GET_NVLINK_ECC_ERRORS_PARAMS,
+                osPrivate, flags);
+        NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_INTERNAL_LATENCY,
+                _nvswitch_ctrl_get_internal_latency,
+                NVSWITCH_GET_INTERNAL_LATENCY);
+        NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(CTRL_NVSWITCH_SET_NVLINK_ERROR_THRESHOLD,
+                _nvswitch_ctrl_set_nvlink_error_threshold,
+                NVSWITCH_SET_NVLINK_ERROR_THRESHOLD_PARAMS,
+                osPrivate, flags);
+        NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_NVLINK_ERROR_THRESHOLD,
+                _nvswitch_ctrl_get_nvlink_error_threshold,
+                NVSWITCH_GET_NVLINK_ERROR_THRESHOLD_PARAMS);
         default:
             nvswitch_os_print(NVSWITCH_DBG_LEVEL_INFO, "ioctl %x is not permitted when TNVL is locked\n", cmd);
             return -NVL_ERR_INSUFFICIENT_PERMISSIONS;

src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c

@@ -493,9 +493,8 @@ gpuIsProtectedPcieEnabledInHw_GH100
     OBJGPU *pGpu
 )
 {
-    NvU32 val = GPU_REG_RD32(pGpu, NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC);
+    // Bug 4870925: Disabled PPCIE
-    return FLD_TEST_DRF(_PGC6, _AON_SECURE_SCRATCH_GROUP_20_CC, _MULTI_GPU_MODE,
+    return NV_FALSE;
-                        _PROTECTED_PCIE, val);
 }
 
 /*!

src/nvidia/src/kernel/gpu/conf_compute/conf_compute_api.c

@@ -134,6 +134,8 @@ confComputeApiCtrlCmdSystemGetCapabilities_IMPL
 
     if (pCcCaps->bMultiGpuProtectedPcieModeEnabled)
     {
+        // Do not advertise HCC as ON to callers when PPCIe is ON
+        pParams->ccFeature = NV_CONF_COMPUTE_SYSTEM_FEATURE_DISABLED;
         pParams->multiGpuMode = NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_PROTECTED_PCIE;
     }
 

src/nvidia/src/kernel/virtualization/kernel_vgpu_mgr.c

@@ -2121,8 +2121,8 @@ kvgpumgrCreateRequestVgpu(NvU32 gpuPciId, const NvU8 *pMdevUuid,
 
     if (pGpu == NULL)
     {
-        NV_PRINTF(LEVEL_ERROR, "GPU handle is not valid \n");
+        NV_PRINTF(LEVEL_ERROR, "GPU %u is not initialized yet \n", gpuPciBdf);
-        return NV_ERR_INVALID_STATE;
+        return NV_ERR_TIMEOUT_RETRY;
     }
 
     if ((status = kvgpumgrGetPgpuIndex(pKernelVgpuMgr, gpuPciId, &pgpuIndex)) != NV_OK)

version.mk

@@ -1,4 +1,4 @@
-NVIDIA_VERSION = 550.120
+NVIDIA_VERSION = 550.127.05
 
 # This file.
 VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST))