mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2025-02-27 09:54:14 +01:00
535.154.05
This commit is contained in:
Bernhard Stoeckner
parent
7165299dee
commit
ee55481a49
@ -2,6 +2,8 @@
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## Release 535 Entries
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### [535.154.05] 2024-01-16
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### [535.146.02] 2023-12-07
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### [535.129.03] 2023-10-31
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12
README.md
12
README.md
@ -1,7 +1,7 @@
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# NVIDIA Linux Open GPU Kernel Module Source
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This is the source release of the NVIDIA Linux open GPU kernel modules,
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version 535.146.02.
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version 535.154.05.
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## How to Build
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@ -17,7 +17,7 @@ as root:
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Note that the kernel modules built here must be used with GSP
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firmware and user-space NVIDIA GPU driver components from a corresponding
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535.146.02 driver release. This can be achieved by installing
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535.154.05 driver release. This can be achieved by installing
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the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
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option. E.g.,
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@ -180,7 +180,7 @@ software applications.
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## Compatible GPUs
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The open-gpu-kernel-modules can be used on any Turing or later GPU
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(see the table below). However, in the 535.146.02 release,
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(see the table below). However, in the 535.154.05 release,
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GeForce and Workstation support is still considered alpha-quality.
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To enable use of the open kernel modules on GeForce and Workstation GPUs,
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@ -188,7 +188,7 @@ set the "NVreg_OpenRmEnableUnsupportedGpus" nvidia.ko kernel module
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parameter to 1. For more details, see the NVIDIA GPU driver end user
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README here:
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https://us.download.nvidia.com/XFree86/Linux-x86_64/535.146.02/README/kernel_open.html
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https://us.download.nvidia.com/XFree86/Linux-x86_64/535.154.05/README/kernel_open.html
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In the below table, if three IDs are listed, the first is the PCI Device
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ID, the second is the PCI Subsystem Vendor ID, and the third is the PCI
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@ -683,6 +683,7 @@ Subsystem Device ID.
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| NVIDIA A800 40GB Active | 20F6 103C 180A |
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| NVIDIA A800 40GB Active | 20F6 10DE 180A |
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| NVIDIA A800 40GB Active | 20F6 17AA 180A |
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| NVIDIA AX800 | 20FD 10DE 17F8 |
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| NVIDIA GeForce GTX 1660 Ti | 2182 |
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| NVIDIA GeForce GTX 1660 | 2184 |
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| NVIDIA GeForce GTX 1650 SUPER | 2187 |
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@ -836,6 +837,7 @@ Subsystem Device ID.
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| NVIDIA RTX A2000 Embedded GPU | 25FA |
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| NVIDIA RTX A500 Embedded GPU | 25FB |
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| NVIDIA GeForce RTX 4090 | 2684 |
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| NVIDIA GeForce RTX 4090 D | 2685 |
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| NVIDIA RTX 6000 Ada Generation | 26B1 1028 16A1 |
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| NVIDIA RTX 6000 Ada Generation | 26B1 103C 16A1 |
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| NVIDIA RTX 6000 Ada Generation | 26B1 10DE 16A1 |
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@ -849,6 +851,7 @@ Subsystem Device ID.
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| NVIDIA L40 | 26B5 10DE 17DA |
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| NVIDIA L40S | 26B9 10DE 1851 |
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| NVIDIA L40S | 26B9 10DE 18CF |
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| NVIDIA L20 | 26BA 10DE 1957 |
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| NVIDIA GeForce RTX 4080 | 2704 |
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| NVIDIA GeForce RTX 4090 Laptop GPU | 2717 |
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| NVIDIA RTX 5000 Ada Generation Laptop GPU | 2730 |
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@ -869,6 +872,7 @@ Subsystem Device ID.
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| NVIDIA RTX 4000 Ada Generation | 27B2 103C 181B |
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| NVIDIA RTX 4000 Ada Generation | 27B2 10DE 181B |
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| NVIDIA RTX 4000 Ada Generation | 27B2 17AA 181B |
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| NVIDIA L2 | 27B6 10DE 1933 |
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| NVIDIA L4 | 27B8 10DE 16CA |
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| NVIDIA L4 | 27B8 10DE 16EE |
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| NVIDIA RTX 4000 Ada Generation Laptop GPU | 27BA |
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@ -72,7 +72,7 @@ EXTRA_CFLAGS += -I$(src)/common/inc
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EXTRA_CFLAGS += -I$(src)
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EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-error -Wno-format-extra-args
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EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM
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EXTRA_CFLAGS += -DNV_VERSION_STRING=\"535.146.02\"
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EXTRA_CFLAGS += -DNV_VERSION_STRING=\"535.154.05\"
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ifneq ($(SYSSRCHOST1X),)
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EXTRA_CFLAGS += -I$(SYSSRCHOST1X)
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@ -2068,5 +2068,6 @@ typedef enum
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#endif
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#define NV_EXPORT_SYMBOL(symbol) EXPORT_SYMBOL_GPL(symbol)
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#define NV_CHECK_EXPORT_SYMBOL(symbol) NV_IS_EXPORT_SYMBOL_PRESENT_##symbol
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#endif /* _NV_LINUX_H_ */
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@ -316,7 +316,7 @@ export_symbol_present_conftest() {
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SYMBOL="$1"
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TAB=' '
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if grep -e "${TAB}${SYMBOL}${TAB}.*${TAB}EXPORT_SYMBOL.*\$" \
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if grep -e "${TAB}${SYMBOL}${TAB}.*${TAB}EXPORT_SYMBOL\(_GPL\)\?\s*\$" \
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"$OUTPUT/Module.symvers" >/dev/null 2>&1; then
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echo "#define NV_IS_EXPORT_SYMBOL_PRESENT_$SYMBOL 1" |
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append_conftest "symbols"
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@ -337,7 +337,7 @@ export_symbol_gpl_conftest() {
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SYMBOL="$1"
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TAB=' '
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if grep -e "${TAB}${SYMBOL}${TAB}.*${TAB}EXPORT_\(UNUSED_\)*SYMBOL_GPL\$" \
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if grep -e "${TAB}${SYMBOL}${TAB}.*${TAB}EXPORT_\(UNUSED_\)*SYMBOL_GPL\s*\$" \
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"$OUTPUT/Module.symvers" >/dev/null 2>&1; then
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echo "#define NV_IS_EXPORT_SYMBOL_GPL_$SYMBOL 1" |
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append_conftest "symbols"
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@ -6390,6 +6390,21 @@ compile_test() {
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compile_check_conftest "$CODE" "NV_MMU_INTERVAL_NOTIFIER" "" "types"
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;;
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drm_unlocked_ioctl_flag_present)
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# Determine if DRM_UNLOCKED IOCTL flag is present.
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#
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# DRM_UNLOCKED was removed by commit 2798ffcc1d6a ("drm: Remove
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# locking for legacy ioctls and DRM_UNLOCKED") in Linux
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# next-20231208.
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CODE="
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#if defined(NV_DRM_DRM_IOCTL_H_PRESENT)
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#include <drm/drm_ioctl.h>
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#endif
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int flags = DRM_UNLOCKED;"
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compile_check_conftest "$CODE" "NV_DRM_UNLOCKED_IOCTL_FLAG_PRESENT" "" "types"
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;;
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# When adding a new conftest entry, please use the correct format for
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# specifying the relevant upstream Linux kernel commit.
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#
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@ -1312,9 +1312,21 @@ static const struct drm_ioctl_desc nv_drm_ioctls[] = {
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DRM_RENDER_ALLOW|DRM_UNLOCKED),
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#endif
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/*
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* DRM_UNLOCKED is implicit for all non-legacy DRM driver IOCTLs since Linux
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* v4.10 commit fa5386459f06 "drm: Used DRM_LEGACY for all legacy functions"
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* (Linux v4.4 commit ea487835e887 "drm: Enforce unlocked ioctl operation
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* for kms driver ioctls" previously did it only for drivers that set the
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* DRM_MODESET flag), so this will race with SET_CLIENT_CAP. Linux v4.11
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* commit dcf727ab5d17 "drm: setclientcap doesn't need the drm BKL" also
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* removed locking from SET_CLIENT_CAP so there is no use attempting to lock
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* manually. The latter commit acknowledges that this can expose userspace
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* to inconsistent behavior when racing with itself, but accepts that risk.
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*/
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DRM_IOCTL_DEF_DRV(NVIDIA_GET_CLIENT_CAPABILITY,
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nv_drm_get_client_capability_ioctl,
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0),
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#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
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DRM_IOCTL_DEF_DRV(NVIDIA_GET_CRTC_CRC32,
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nv_drm_get_crtc_crc32_ioctl,
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@ -582,6 +582,19 @@ static inline int nv_drm_format_num_planes(uint32_t format)
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#endif /* defined(NV_DRM_FORMAT_MODIFIERS_PRESENT) */
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/*
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* DRM_UNLOCKED was removed with linux-next commit 2798ffcc1d6a ("drm: Remove
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* locking for legacy ioctls and DRM_UNLOCKED"), but it was previously made
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* implicit for all non-legacy DRM driver IOCTLs since Linux v4.10 commit
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* fa5386459f06 "drm: Used DRM_LEGACY for all legacy functions" (Linux v4.4
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* commit ea487835e887 "drm: Enforce unlocked ioctl operation for kms driver
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* ioctls" previously did it only for drivers that set the DRM_MODESET flag), so
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* it was effectively a no-op anyway.
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*/
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#if !defined(NV_DRM_UNLOCKED_IOCTL_FLAG_PRESENT)
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#define DRM_UNLOCKED 0
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#endif
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/*
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* drm_vma_offset_exact_lookup_locked() were added
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* by kernel commit 2225cfe46bcc which was Signed-off-by:
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@ -133,3 +133,4 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_lookup
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NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_put
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NV_CONFTEST_TYPE_COMPILE_TESTS += vm_area_struct_has_const_vm_flags
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NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_dumb_destroy
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NV_CONFTEST_TYPE_COMPILE_TESTS += drm_unlocked_ioctl_flag_present
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@ -216,6 +216,7 @@ NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_get_dram_num_channe
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NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tegra_dram_types
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NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_pxm_to_node
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NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_screen_info
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NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl_screen_info
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NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_i2c_bus_status
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NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tegra_fuse_control_read
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NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tegra_get_platform
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@ -1247,9 +1247,12 @@ void NV_API_CALL os_get_screen_info(
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* SYSFB_SIMPLEFB registers a dummy framebuffer which does not contain the
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* information required by os_get_screen_info(), therefore you need to
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* fall back onto the screen_info structure.
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*
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* After commit b8466fe82b79 ("efi: move screen_info into efi init code")
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* in v6.7, 'screen_info' is exported as GPL licensed symbol for ARM64.
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*/
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#if NV_IS_EXPORT_SYMBOL_PRESENT_screen_info
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#if NV_CHECK_EXPORT_SYMBOL(screen_info)
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/*
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* If there is not a framebuffer console, return 0 size.
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*
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@ -36,25 +36,25 @@
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// and then checked back in. You cannot make changes to these sections without
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// corresponding changes to the buildmeister script
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#ifndef NV_BUILD_BRANCH
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#define NV_BUILD_BRANCH r537_94
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#define NV_BUILD_BRANCH r538_10
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#endif
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#ifndef NV_PUBLIC_BRANCH
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#define NV_PUBLIC_BRANCH r537_94
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#define NV_PUBLIC_BRANCH r538_10
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#endif
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#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
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#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/r537_94-386"
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#define NV_BUILD_CHANGELIST_NUM (33606179)
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#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/r538_10-414"
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#define NV_BUILD_CHANGELIST_NUM (33694617)
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#define NV_BUILD_TYPE "Official"
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#define NV_BUILD_NAME "rel/gpu_drv/r535/r537_94-386"
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#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33606179)
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#define NV_BUILD_NAME "rel/gpu_drv/r535/r538_10-414"
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#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33694617)
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#else /* Windows builds */
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#define NV_BUILD_BRANCH_VERSION "r537_94-2"
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#define NV_BUILD_CHANGELIST_NUM (33602158)
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#define NV_BUILD_BRANCH_VERSION "r538_10-3"
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#define NV_BUILD_CHANGELIST_NUM (33691963)
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#define NV_BUILD_TYPE "Official"
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#define NV_BUILD_NAME "537.99"
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#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33602158)
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#define NV_BUILD_NAME "538.15"
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#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33691963)
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#define NV_BUILD_BRANCH_BASE_VERSION R535
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#endif
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// End buildmeister python edited section
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@ -4,7 +4,7 @@
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#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
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(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
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#define NV_VERSION_STRING "535.146.02"
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#define NV_VERSION_STRING "535.154.05"
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#else
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@ -630,6 +630,7 @@ enum {
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, CS_INTEL_1B81
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, CS_INTEL_18DC
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, CS_INTEL_7A04
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, CS_AMPERE_AMPEREONE
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, CS_MAX_PCIE
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};
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@ -89,6 +89,7 @@ CHIPSET_SETUP_FUNC(Amazon_Gravitron2_setupFunc)
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CHIPSET_SETUP_FUNC(Fujitsu_A64FX_setupFunc)
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CHIPSET_SETUP_FUNC(Ampere_Altra_setupFunc)
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CHIPSET_SETUP_FUNC(Arm_NeoverseN1_setupFunc)
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CHIPSET_SETUP_FUNC(Ampere_AmpereOne_setupFunc)
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CHIPSET_SETUP_FUNC(Nvidia_T210_setupFunc)
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CHIPSET_SETUP_FUNC(Nvidia_T194_setupFunc)
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CHIPSET_SETUP_FUNC(Nvidia_TH500_setupFunc)
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@ -265,6 +266,14 @@ CSINFO chipsetInfo[] =
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{PCI_VENDOR_ID_HYGON, 0x790E, CS_HYGON_C86, "Hygon-C86-7151", NULL},
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{PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN96XX, "Marvell Octeon CN96xx", ARMV8_generic_setupFunc},
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{PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN98XX, "Marvell Octeon CN98xx", ARMV8_generic_setupFunc},
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{PCI_VENDOR_ID_AMPERE, 0xE200, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc},
|
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{PCI_VENDOR_ID_AMPERE, 0xE201, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc},
|
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{PCI_VENDOR_ID_AMPERE, 0xE202, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc},
|
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{PCI_VENDOR_ID_AMPERE, 0xE203, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc},
|
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{PCI_VENDOR_ID_AMPERE, 0xE204, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc},
|
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{PCI_VENDOR_ID_AMPERE, 0xE205, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc},
|
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{PCI_VENDOR_ID_AMPERE, 0xE206, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc},
|
||||
{PCI_VENDOR_ID_AMPERE, 0xE207, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc},
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
@ -363,6 +372,14 @@ ARMCSALLOWLISTINFO armChipsetAllowListInfo[] =
|
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{PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN96XX}, // Marvell OCTEON CN96xx
|
||||
{PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN98XX}, // Marvell OCTEON CN98xx
|
||||
{PCI_VENDOR_ID_ALIBABA, 0x8000, CS_ALIBABA_YITIAN}, // Alibaba Yitian
|
||||
{PCI_VENDOR_ID_AMPERE, 0xE200, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne
|
||||
{PCI_VENDOR_ID_AMPERE, 0xE201, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne
|
||||
{PCI_VENDOR_ID_AMPERE, 0xE202, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne
|
||||
{PCI_VENDOR_ID_AMPERE, 0xE203, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne
|
||||
{PCI_VENDOR_ID_AMPERE, 0xE204, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne
|
||||
{PCI_VENDOR_ID_AMPERE, 0xE205, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne
|
||||
{PCI_VENDOR_ID_AMPERE, 0xE206, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne
|
||||
{PCI_VENDOR_ID_AMPERE, 0xE207, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne
|
||||
|
||||
// last element must have chipset CS_UNKNOWN (zero)
|
||||
{0, 0, CS_UNKNOWN}
|
||||
|
||||
@ -833,6 +833,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
|
||||
{ 0x20F6, 0x180a, 0x103c, "NVIDIA A800 40GB Active" },
|
||||
{ 0x20F6, 0x180a, 0x10de, "NVIDIA A800 40GB Active" },
|
||||
{ 0x20F6, 0x180a, 0x17aa, "NVIDIA A800 40GB Active" },
|
||||
{ 0x20FD, 0x17f8, 0x10de, "NVIDIA AX800" },
|
||||
{ 0x2182, 0x0000, 0x0000, "NVIDIA GeForce GTX 1660 Ti" },
|
||||
{ 0x2184, 0x0000, 0x0000, "NVIDIA GeForce GTX 1660" },
|
||||
{ 0x2187, 0x0000, 0x0000, "NVIDIA GeForce GTX 1650 SUPER" },
|
||||
@ -987,6 +988,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
|
||||
{ 0x25FA, 0x0000, 0x0000, "NVIDIA RTX A2000 Embedded GPU" },
|
||||
{ 0x25FB, 0x0000, 0x0000, "NVIDIA RTX A500 Embedded GPU" },
|
||||
{ 0x2684, 0x0000, 0x0000, "NVIDIA GeForce RTX 4090" },
|
||||
{ 0x2685, 0x0000, 0x0000, "NVIDIA GeForce RTX 4090 D" },
|
||||
{ 0x26B1, 0x16a1, 0x1028, "NVIDIA RTX 6000 Ada Generation" },
|
||||
{ 0x26B1, 0x16a1, 0x103c, "NVIDIA RTX 6000 Ada Generation" },
|
||||
{ 0x26B1, 0x16a1, 0x10de, "NVIDIA RTX 6000 Ada Generation" },
|
||||
@ -1000,6 +1002,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
|
||||
{ 0x26B5, 0x17da, 0x10de, "NVIDIA L40" },
|
||||
{ 0x26B9, 0x1851, 0x10de, "NVIDIA L40S" },
|
||||
{ 0x26B9, 0x18cf, 0x10de, "NVIDIA L40S" },
|
||||
{ 0x26BA, 0x1957, 0x10de, "NVIDIA L20" },
|
||||
{ 0x2704, 0x0000, 0x0000, "NVIDIA GeForce RTX 4080" },
|
||||
{ 0x2717, 0x0000, 0x0000, "NVIDIA GeForce RTX 4090 Laptop GPU" },
|
||||
{ 0x2730, 0x0000, 0x0000, "NVIDIA RTX 5000 Ada Generation Laptop GPU" },
|
||||
@ -1020,6 +1023,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
|
||||
{ 0x27B2, 0x181b, 0x103c, "NVIDIA RTX 4000 Ada Generation" },
|
||||
{ 0x27B2, 0x181b, 0x10de, "NVIDIA RTX 4000 Ada Generation" },
|
||||
{ 0x27B2, 0x181b, 0x17aa, "NVIDIA RTX 4000 Ada Generation" },
|
||||
{ 0x27B6, 0x1933, 0x10de, "NVIDIA L2" },
|
||||
{ 0x27B8, 0x16ca, 0x10de, "NVIDIA L4" },
|
||||
{ 0x27B8, 0x16ee, 0x10de, "NVIDIA L4" },
|
||||
{ 0x27BA, 0x0000, 0x0000, "NVIDIA RTX 4000 Ada Generation Laptop GPU" },
|
||||
@ -2046,6 +2050,78 @@ static const CHIPS_RELEASED sChipsReleased[] = {
|
||||
{ 0x26B9, 0x18af, 0x10DE, "NVIDIA L40S-16C" },
|
||||
{ 0x26B9, 0x18b0, 0x10DE, "NVIDIA L40S-24C" },
|
||||
{ 0x26B9, 0x18b1, 0x10DE, "NVIDIA L40S-48C" },
|
||||
{ 0x26BA, 0x1909, 0x10DE, "NVIDIA L20-1B" },
|
||||
{ 0x26BA, 0x190a, 0x10DE, "NVIDIA L20-2B" },
|
||||
{ 0x26BA, 0x190b, 0x10DE, "NVIDIA L20-1Q" },
|
||||
{ 0x26BA, 0x190c, 0x10DE, "NVIDIA L20-2Q" },
|
||||
{ 0x26BA, 0x190d, 0x10DE, "NVIDIA L20-3Q" },
|
||||
{ 0x26BA, 0x190e, 0x10DE, "NVIDIA L20-4Q" },
|
||||
{ 0x26BA, 0x190f, 0x10DE, "NVIDIA L20-6Q" },
|
||||
{ 0x26BA, 0x1910, 0x10DE, "NVIDIA L20-8Q" },
|
||||
{ 0x26BA, 0x1911, 0x10DE, "NVIDIA L20-12Q" },
|
||||
{ 0x26BA, 0x1912, 0x10DE, "NVIDIA L20-16Q" },
|
||||
{ 0x26BA, 0x1913, 0x10DE, "NVIDIA L20-24Q" },
|
||||
{ 0x26BA, 0x1914, 0x10DE, "NVIDIA L20-48Q" },
|
||||
{ 0x26BA, 0x1915, 0x10DE, "NVIDIA L20-1A" },
|
||||
{ 0x26BA, 0x1916, 0x10DE, "NVIDIA L20-2A" },
|
||||
{ 0x26BA, 0x1917, 0x10DE, "NVIDIA L20-3A" },
|
||||
{ 0x26BA, 0x1918, 0x10DE, "NVIDIA L20-4A" },
|
||||
{ 0x26BA, 0x1919, 0x10DE, "NVIDIA L20-6A" },
|
||||
{ 0x26BA, 0x191a, 0x10DE, "NVIDIA L20-8A" },
|
||||
{ 0x26BA, 0x191b, 0x10DE, "NVIDIA L20-12A" },
|
||||
{ 0x26BA, 0x191c, 0x10DE, "NVIDIA L20-16A" },
|
||||
{ 0x26BA, 0x191d, 0x10DE, "NVIDIA L20-24A" },
|
||||
{ 0x26BA, 0x191e, 0x10DE, "NVIDIA L20-48A" },
|
||||
{ 0x26BA, 0x191f, 0x10DE, "NVIDIA GeForce RTX 3050" },
|
||||
{ 0x26BA, 0x1920, 0x10DE, "NVIDIA GeForce RTX 3060" },
|
||||
{ 0x26BA, 0x1921, 0x10DE, "NVIDIA L20-1" },
|
||||
{ 0x26BA, 0x1922, 0x10DE, "NVIDIA L20-2" },
|
||||
{ 0x26BA, 0x1923, 0x10DE, "NVIDIA L20-3" },
|
||||
{ 0x26BA, 0x1924, 0x10DE, "NVIDIA L20-4" },
|
||||
{ 0x26BA, 0x1925, 0x10DE, "NVIDIA L20-6" },
|
||||
{ 0x26BA, 0x1926, 0x10DE, "NVIDIA L20-8" },
|
||||
{ 0x26BA, 0x1927, 0x10DE, "NVIDIA L20-12" },
|
||||
{ 0x26BA, 0x1928, 0x10DE, "NVIDIA L20-16" },
|
||||
{ 0x26BA, 0x1929, 0x10DE, "NVIDIA L20-24" },
|
||||
{ 0x26BA, 0x192a, 0x10DE, "NVIDIA L20-48" },
|
||||
{ 0x26BA, 0x192b, 0x10DE, "NVIDIA L20-4C" },
|
||||
{ 0x26BA, 0x192c, 0x10DE, "NVIDIA L20-6C" },
|
||||
{ 0x26BA, 0x192d, 0x10DE, "NVIDIA L20-8C" },
|
||||
{ 0x26BA, 0x192e, 0x10DE, "NVIDIA L20-12C" },
|
||||
{ 0x26BA, 0x192f, 0x10DE, "NVIDIA L20-16C" },
|
||||
{ 0x26BA, 0x1930, 0x10DE, "NVIDIA L20-24C" },
|
||||
{ 0x26BA, 0x1931, 0x10DE, "NVIDIA L20-48C" },
|
||||
{ 0x27B6, 0x1938, 0x10DE, "NVIDIA L2-1B" },
|
||||
{ 0x27B6, 0x1939, 0x10DE, "NVIDIA L2-2B" },
|
||||
{ 0x27B6, 0x193a, 0x10DE, "NVIDIA L2-1Q" },
|
||||
{ 0x27B6, 0x193b, 0x10DE, "NVIDIA L2-2Q" },
|
||||
{ 0x27B6, 0x193c, 0x10DE, "NVIDIA L2-3Q" },
|
||||
{ 0x27B6, 0x193d, 0x10DE, "NVIDIA L2-4Q" },
|
||||
{ 0x27B6, 0x193e, 0x10DE, "NVIDIA L2-6Q" },
|
||||
{ 0x27B6, 0x193f, 0x10DE, "NVIDIA L2-8Q" },
|
||||
{ 0x27B6, 0x1940, 0x10DE, "NVIDIA L2-12Q" },
|
||||
{ 0x27B6, 0x1941, 0x10DE, "NVIDIA L2-24Q" },
|
||||
{ 0x27B6, 0x1942, 0x10DE, "NVIDIA L2-1A" },
|
||||
{ 0x27B6, 0x1943, 0x10DE, "NVIDIA L2-2A" },
|
||||
{ 0x27B6, 0x1944, 0x10DE, "NVIDIA L2-3A" },
|
||||
{ 0x27B6, 0x1945, 0x10DE, "NVIDIA L2-4A" },
|
||||
{ 0x27B6, 0x1946, 0x10DE, "NVIDIA L2-6A" },
|
||||
{ 0x27B6, 0x1947, 0x10DE, "NVIDIA L2-8A" },
|
||||
{ 0x27B6, 0x1948, 0x10DE, "NVIDIA L2-12A" },
|
||||
{ 0x27B6, 0x1949, 0x10DE, "NVIDIA L2-24A" },
|
||||
{ 0x27B6, 0x194a, 0x10DE, "NVIDIA L2-1" },
|
||||
{ 0x27B6, 0x194b, 0x10DE, "NVIDIA L2-2" },
|
||||
{ 0x27B6, 0x194c, 0x10DE, "NVIDIA L2-3" },
|
||||
{ 0x27B6, 0x194d, 0x10DE, "NVIDIA L2-4" },
|
||||
{ 0x27B6, 0x194e, 0x10DE, "NVIDIA L2-6" },
|
||||
{ 0x27B6, 0x194f, 0x10DE, "NVIDIA L2-8" },
|
||||
{ 0x27B6, 0x1950, 0x10DE, "NVIDIA L2-12" },
|
||||
{ 0x27B6, 0x1951, 0x10DE, "NVIDIA L2-24" },
|
||||
{ 0x27B6, 0x1952, 0x10DE, "NVIDIA L2-4C" },
|
||||
{ 0x27B6, 0x1953, 0x10DE, "NVIDIA L2-6C" },
|
||||
{ 0x27B6, 0x1954, 0x10DE, "NVIDIA L2-8C" },
|
||||
{ 0x27B6, 0x1955, 0x10DE, "NVIDIA L2-12C" },
|
||||
{ 0x27B6, 0x1956, 0x10DE, "NVIDIA L2-24C" },
|
||||
{ 0x27B8, 0x172f, 0x10DE, "NVIDIA L4-1B" },
|
||||
{ 0x27B8, 0x1730, 0x10DE, "NVIDIA L4-2B" },
|
||||
{ 0x27B8, 0x1731, 0x10DE, "NVIDIA L4-1Q" },
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@ -25,6 +25,7 @@
|
||||
|
||||
#include "rmapi/rmapi.h"
|
||||
|
||||
|
||||
//
|
||||
// Alloc a client, device and subdevice handle for a gpu
|
||||
//
|
||||
|
||||
@ -1919,4 +1919,14 @@
|
||||
#define NV_REG_STR_RM_DMA_ADJUST_PEER_MMIO_BF3_DISABLE 0
|
||||
#define NV_REG_STR_RM_DMA_ADJUST_PEER_MMIO_BF3_ENABLE 1
|
||||
|
||||
//
|
||||
// Type DWORD
|
||||
// This regkey force-disables write-combine iomap allocations, used for chipsets where
|
||||
// write-combine is broken.
|
||||
//
|
||||
#define NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC "RmForceDisableIomapWC"
|
||||
#define NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_YES 0x00000001
|
||||
#define NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_NO 0x00000000
|
||||
#define NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_DEFAULT NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_NO
|
||||
|
||||
#endif // NVRM_REGISTRY_H
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@ -82,6 +82,12 @@ clInitPropertiesFromRegistry_IMPL(OBJGPU *pGpu, OBJCL *pCl)
|
||||
}
|
||||
}
|
||||
|
||||
if ((osReadRegistryDword(pGpu, NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC, &data32) == NV_OK)
|
||||
&& (data32 == NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_YES))
|
||||
{
|
||||
pCl->setProperty(pCl, PDB_PROP_CL_DISABLE_IOMAP_WC, NV_TRUE);
|
||||
}
|
||||
|
||||
pOS->osQADbgRegistryInit(pOS);
|
||||
}
|
||||
|
||||
|
||||
@ -1301,6 +1301,18 @@ Arm_NeoverseN1_setupFunc
|
||||
return NV_OK;
|
||||
}
|
||||
|
||||
// Ampere AmpereOne Setup Function
|
||||
static NV_STATUS
|
||||
Ampere_AmpereOne_setupFunc
|
||||
(
|
||||
OBJCL *pCl
|
||||
)
|
||||
{
|
||||
// TODO Need to check if any more PDB properties should be set
|
||||
pCl->setProperty(pCl, PDB_PROP_CL_IS_CHIPSET_IO_COHERENT, NV_TRUE);
|
||||
return NV_OK;
|
||||
}
|
||||
|
||||
void
|
||||
csGetInfoStrings
|
||||
(
|
||||
|
||||
@ -186,6 +186,7 @@ void RmInitCpuInfo(void)
|
||||
break;
|
||||
case AARCH64_VENDOR_PART(ARM, NEOVERSE_N2):
|
||||
case AARCH64_VENDOR_PART(ARM, NEOVERSE_V2):
|
||||
case AARCH64_VENDOR_PART(AMPERE_2, AMPEREONE):
|
||||
pSys->cpuInfo.type = NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV9A_GENERIC;
|
||||
break;
|
||||
default:
|
||||
|
||||
@ -57,6 +57,7 @@ extern void CP_WRITE_CSSELR_REGISTER(NvU32 val);
|
||||
#define CP_MIDR_IMPLEMENTER_FUJITSU 0x46
|
||||
#define CP_MIDR_IMPLEMENTER_PHYTIUM 0x70
|
||||
#define CP_MIDR_IMPLEMENTER_AMPERE 0x81
|
||||
#define CP_MIDR_IMPLEMENTER_AMPERE_2 0XC0
|
||||
|
||||
#define CP_CSSELR_DATA_CACHE 0
|
||||
#define CP_CSSELR_INSTRUCTION_CACHE 1
|
||||
@ -91,6 +92,7 @@ extern void CP_WRITE_CSSELR_REGISTER(NvU32 val);
|
||||
#define CP_MIDR_PRIMARY_PART_NUM_OCTEON_CN96XX 0x0b2
|
||||
#define CP_MIDR_PRIMARY_PART_NUM_OCTEON_CN98XX 0x0b1
|
||||
#define CP_MIDR_PRIMARY_PART_NUM_NEOVERSE_N2 0xd49
|
||||
#define CP_MIDR_PRIMARY_PART_NUM_AMPEREONE 0xac3
|
||||
|
||||
// Cache Size Identification Register
|
||||
#define CP_CCSIDR "ccsidr_el1"
|
||||
|
||||
@ -274,7 +274,9 @@ serverControlApiCopyIn
|
||||
|
||||
rmStatus = embeddedParamCopyIn(pEmbeddedParamCopies, pRmCtrlParams);
|
||||
if (rmStatus != NV_OK)
|
||||
{
|
||||
return rmStatus;
|
||||
}
|
||||
pCookie->bFreeEmbeddedCopy = NV_TRUE;
|
||||
|
||||
return NV_OK;
|
||||
@ -488,7 +490,8 @@ _rmapiRmControl(NvHandle hClient, NvHandle hObject, NvU32 cmd, NvP64 pUserParams
|
||||
|
||||
// error check parameters
|
||||
if (((paramsSize != 0) && (pUserParams == (NvP64) 0)) ||
|
||||
((paramsSize == 0) && (pUserParams != (NvP64) 0)))
|
||||
((paramsSize == 0) && (pUserParams != (NvP64) 0))
|
||||
)
|
||||
{
|
||||
NV_PRINTF(LEVEL_WARNING, "bad params: ptr " NvP64_fmt " size: 0x%x\n",
|
||||
pUserParams, paramsSize);
|
||||
@ -519,6 +522,7 @@ _rmapiRmControl(NvHandle hClient, NvHandle hObject, NvU32 cmd, NvP64 pUserParams
|
||||
}
|
||||
|
||||
getCtrlInfoStatus = rmapiutilGetControlInfo(cmd, &ctrlFlags, &ctrlAccessRight);
|
||||
|
||||
if (getCtrlInfoStatus == NV_OK)
|
||||
{
|
||||
//
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
NVIDIA_VERSION = 535.146.02
|
||||
NVIDIA_VERSION = 535.154.05
|
||||
|
||||
# This file.
|
||||
VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST))
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user