535.179

CHANGELOG.md

@@ -2,6 +2,8 @@
 
 ## Release 535 Entries
 
+### [535.179] 2024-05-09
+
 ### [535.171.04] 2024-03-21
 
 ### [535.161.08] 2024-03-18
@@ -62,10 +64,14 @@
 
 ## Release 525 Entries
 
+### [525.147.05] 2023-10-31
+
 #### Fixed
 
 - Fix nvidia_p2p_get_pages(): Fix double-free in register-callback error path, [#557](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/557) by @BrendanCunningham
 
+### [525.125.06] 2023-06-26
+
 ### [525.116.04] 2023-05-09
 
 ### [525.116.03] 2023-04-25

README.md

@@ -1,7 +1,7 @@
 # NVIDIA Linux Open GPU Kernel Module Source
 
 This is the source release of the NVIDIA Linux open GPU kernel modules,
-version 535.171.04.
+version 535.179.
 
 
 ## How to Build
@@ -17,7 +17,7 @@ as root:
 
 Note that the kernel modules built here must be used with GSP
 firmware and user-space NVIDIA GPU driver components from a corresponding
-535.171.04 driver release.  This can be achieved by installing
+535.179 driver release.  This can be achieved by installing
 the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
 option.  E.g.,
 
@@ -180,7 +180,7 @@ software applications.
 ## Compatible GPUs
 
 The open-gpu-kernel-modules can be used on any Turing or later GPU
-(see the table below). However, in the 535.171.04 release,
+(see the table below). However, in the 535.179 release,
 GeForce and Workstation support is still considered alpha-quality.
 
 To enable use of the open kernel modules on GeForce and Workstation GPUs,
@@ -188,7 +188,7 @@ set the "NVreg_OpenRmEnableUnsupportedGpus" nvidia.ko kernel module
 parameter to 1. For more details, see the NVIDIA GPU driver end user
 README here:
 
-https://us.download.nvidia.com/XFree86/Linux-x86_64/535.171.04/README/kernel_open.html
+https://us.download.nvidia.com/XFree86/Linux-x86_64/535.179/README/kernel_open.html
 
 In the below table, if three IDs are listed, the first is the PCI Device 
 ID, the second is the PCI Subsystem Vendor ID, and the third is the PCI
@@ -648,6 +648,7 @@ Subsystem Device ID.
 | NVIDIA T1000 8GB                                | 1FF0 17AA 1612 |
 | NVIDIA T400 4GB                                 | 1FF2 1028 1613 |
 | NVIDIA T400 4GB                                 | 1FF2 103C 1613 |
+| NVIDIA T400E                                    | 1FF2 103C 18FF |
 | NVIDIA T400 4GB                                 | 1FF2 103C 8A80 |
 | NVIDIA T400 4GB                                 | 1FF2 10DE 1613 |
 | NVIDIA T400 4GB                                 | 1FF2 17AA 1613 |

kernel-open/Kbuild

@@ -72,7 +72,7 @@ EXTRA_CFLAGS += -I$(src)/common/inc
 EXTRA_CFLAGS += -I$(src)
 EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-error -Wno-format-extra-args
 EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM
-EXTRA_CFLAGS += -DNV_VERSION_STRING=\"535.171.04\"
+EXTRA_CFLAGS += -DNV_VERSION_STRING=\"535.179\"
 
 ifneq ($(SYSSRCHOST1X),)
  EXTRA_CFLAGS += -I$(SYSSRCHOST1X)

kernel-open/conftest.sh

@@ -1354,6 +1354,42 @@ compile_test() {
             compile_check_conftest "$CODE" "NV_VFIO_REGISTER_EMULATED_IOMMU_DEV_PRESENT" "" "functions"
         ;;
 
+        bus_type_has_iommu_ops)
+            #
+            # Determine if 'bus_type' structure has a 'iommu_ops' field.
+            #
+            # This field was removed by commit 17de3f5fdd35 (iommu: Retire bus ops)
+            # in v6.8
+            #
+            CODE="
+            #include <linux/device.h>
+
+            int conftest_bus_type_has_iommu_ops(void) {
+                return offsetof(struct bus_type, iommu_ops);
+            }"
+
+            compile_check_conftest "$CODE" "NV_BUS_TYPE_HAS_IOMMU_OPS" "" "types"
+        ;;
+
+        eventfd_signal_has_counter_arg)
+            #
+            # Determine if eventfd_signal() function has an additional 'counter' argument.
+            #
+            # This argument was removed by commit 3652117f8548 (eventfd: simplify
+            # eventfd_signal()) in v6.8
+            #
+            CODE="
+            #include <linux/eventfd.h>
+
+            void conftest_eventfd_signal_has_counter_arg(void) {
+                struct eventfd_ctx *ctx;
+
+                eventfd_signal(ctx, 1);
+            }"
+
+            compile_check_conftest "$CODE" "NV_EVENTFD_SIGNAL_HAS_COUNTER_ARG" "" "types"
+        ;;
+
         drm_available)
             # Determine if the DRM subsystem is usable
             CODE="

kernel-open/nvidia/nv-pci.c

@@ -38,6 +38,10 @@
 #include <linux/kernfs.h>
 #endif
 
+#if !defined(NV_BUS_TYPE_HAS_IOMMU_OPS)
+#include <linux/iommu.h>
+#endif
+
 static void
 nv_check_and_exclude_gpu(
     nvidia_stack_t *sp,
@@ -376,7 +380,12 @@ nv_pci_probe
             goto failed;
         }
 
+#if defined(NV_BUS_TYPE_HAS_IOMMU_OPS)
         if (pci_dev->dev.bus->iommu_ops == NULL) 
+#else
+        if ((pci_dev->dev.iommu != NULL) && (pci_dev->dev.iommu->iommu_dev != NULL) &&
+            (pci_dev->dev.iommu->iommu_dev->ops == NULL))
+#endif
         {
             nv = NV_STATE_PTR(nvl);
             if (rm_is_iommu_needed_for_sriov(sp, nv))

kernel-open/nvidia/nvidia.Kbuild

@@ -251,6 +251,7 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += pci_driver_has_driver_managed_dma
 NV_CONFTEST_TYPE_COMPILE_TESTS += vm_area_struct_has_const_vm_flags
 NV_CONFTEST_TYPE_COMPILE_TESTS += memory_failure_has_trapno_arg
 NV_CONFTEST_TYPE_COMPILE_TESTS += foll_longterm_present
+NV_CONFTEST_TYPE_COMPILE_TESTS += bus_type_has_iommu_ops
 
 NV_CONFTEST_GENERIC_COMPILE_TESTS += dom0_kernel_present
 NV_CONFTEST_GENERIC_COMPILE_TESTS += nvidia_vgpu_kvm_build

src/common/displayport/src/dp_connectorimpl.cpp

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a

src/common/inc/nvBldVer.h

@@ -36,25 +36,25 @@
 // and then checked back in. You cannot make changes to these sections without
 // corresponding changes to the buildmeister script
 #ifndef NV_BUILD_BRANCH
-    #define NV_BUILD_BRANCH             r538_49
+    #define NV_BUILD_BRANCH             r535_00
 #endif
 #ifndef NV_PUBLIC_BRANCH
-    #define NV_PUBLIC_BRANCH             r538_49
+    #define NV_PUBLIC_BRANCH             r535_00
 #endif
 
 #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
-#define NV_BUILD_BRANCH_VERSION         "rel/gpu_drv/r535/r538_49-495"
+#define NV_BUILD_BRANCH_VERSION         "rel/gpu_drv/r535/r535_00-537"
-#define NV_BUILD_CHANGELIST_NUM         (34058561)
+#define NV_BUILD_CHANGELIST_NUM         (34218726)
 #define NV_BUILD_TYPE                   "Official"
-#define NV_BUILD_NAME                   "rel/gpu_drv/r535/r538_49-495"
+#define NV_BUILD_NAME                   "rel/gpu_drv/r535/r535_00-537"
-#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34058561)
+#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34218726)
 
 #else     /* Windows builds */
-#define NV_BUILD_BRANCH_VERSION         "r538_49-2"
+#define NV_BUILD_BRANCH_VERSION         "r535_00-549"
-#define NV_BUILD_CHANGELIST_NUM         (34058561)
+#define NV_BUILD_CHANGELIST_NUM         (34218726)
 #define NV_BUILD_TYPE                   "Official"
-#define NV_BUILD_NAME                   "538.52"
+#define NV_BUILD_NAME                   "538.62"
-#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34058561)
+#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34218726)
 #define NV_BUILD_BRANCH_BASE_VERSION    R535
 #endif
 // End buildmeister python edited section

src/common/inc/nvUnixVersion.h

@@ -4,7 +4,7 @@
 #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
     (defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
 
-#define NV_VERSION_STRING               "535.171.04"
+#define NV_VERSION_STRING               "535.179"
 
 #else
 

src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h

@@ -824,6 +824,19 @@ typedef NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS NV2080
 
 #define NV2080_CTRL_CMD_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a43) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */
 
+
+
+#define NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID (0x45U)
+
+typedef struct NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS {
+    NvBool bTeardown;
+} NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS;
+
+#define NV2080_CTRL_CMD_INTERNAL_KGR_INIT_BUG4208224_WAR (0x20800a46) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID" */
+#define NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID (0x46U)
+
+typedef NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS;
+
 /**
  * Get GR PDB properties synchronized between Kernel and Physical
  *

src/common/sdk/nvidia/inc/nvos.h

@@ -2711,6 +2711,7 @@ typedef struct
 #define NV_VASPACE_ALLOCATION_FLAGS_SKIP_SCRUB_MEMPOOL                    BIT(10)
 #define NV_VASPACE_ALLOCATION_FLAGS_OPTIMIZE_PTETABLE_MEMPOOL_USAGE       BIT(11)
 #define NV_VASPACE_ALLOCATION_FLAGS_REQUIRE_FIXED_OFFSET                  BIT(12)
+#define NV_VASPACE_ALLOCATION_FLAGS_PTETABLE_HEAP_MANAGED                 BIT(13)
 
 #define NV_VASPACE_ALLOCATION_INDEX_GPU_NEW                                 0x00 //<! Create new VASpace, by default
 #define NV_VASPACE_ALLOCATION_INDEX_GPU_HOST                                0x01 //<! Acquire reference to BAR1 VAS.

src/nvidia/arch/nvalloc/common/inc/nvcst.h

@@ -247,7 +247,8 @@ CSINFO chipsetInfo[] =
     {PCI_VENDOR_ID_MELLANOX,    0xA2D0, CS_MELLANOX_BLUEFIELD, "Mellanox BlueField",  Mellanox_BlueField_setupFunc},
     {PCI_VENDOR_ID_MELLANOX,    0xA2D4, CS_MELLANOX_BLUEFIELD2, "Mellanox BlueField 2",  NULL},
     {PCI_VENDOR_ID_MELLANOX,    0xA2D5, CS_MELLANOX_BLUEFIELD2, "Mellanox BlueField 2 Crypto disabled",  NULL},
-    {PCI_VENDOR_ID_MELLANOX,    0xA2DB, CS_MELLANOX_BLUEFIELD3, "Mellanox BlueField 3",  Mellanox_BlueField3_setupFunc},
+    {PCI_VENDOR_ID_MELLANOX,    0xA2DA, CS_MELLANOX_BLUEFIELD3, "Mellanox BlueField 3 Crypto enabled",  Mellanox_BlueField3_setupFunc},
+    {PCI_VENDOR_ID_MELLANOX,    0xA2DB, CS_MELLANOX_BLUEFIELD3, "Mellanox BlueField 3 Crypto disabled",  Mellanox_BlueField3_setupFunc},
     {PCI_VENDOR_ID_AMAZON,      0x0200, CS_AMAZON_GRAVITRON2, "Amazon Gravitron2",  Amazon_Gravitron2_setupFunc},
     {PCI_VENDOR_ID_FUJITSU,     0x1952, CS_FUJITSU_A64FX,     "Fujitsu A64FX", Fujitsu_A64FX_setupFunc},
     {PCI_VENDOR_ID_CADENCE,     0xDC01, CS_PHYTIUM_S2500,  "Phytium S2500",  NULL},

src/nvidia/generated/g_nv_name_released.h

@@ -797,6 +797,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
     { 0x1FF0, 0x1612, 0x17aa, "NVIDIA T1000 8GB" },
     { 0x1FF2, 0x1613, 0x1028, "NVIDIA T400 4GB" },
     { 0x1FF2, 0x1613, 0x103c, "NVIDIA T400 4GB" },
+    { 0x1FF2, 0x18ff, 0x103c, "NVIDIA T400E" },
     { 0x1FF2, 0x8a80, 0x103c, "NVIDIA T400 4GB" },
     { 0x1FF2, 0x1613, 0x10de, "NVIDIA T400 4GB" },
     { 0x1FF2, 0x1613, 0x17aa, "NVIDIA T400 4GB" },

src/nvidia/generated/g_profiler_v2_nvoc.h

@@ -7,7 +7,7 @@ extern "C" {
 #endif
 
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2018-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a

src/nvidia/interface/nvrm_registry.h

@@ -1957,5 +1957,13 @@
 #define NV_REG_RM_GSP_WPR_END_MARGIN_APPLY_ON_RETRY         0x00000000
 #define NV_REG_RM_GSP_WPR_END_MARGIN_APPLY_ALWAYS           0x00000001
 
+//
+// Type: Dword
+// This regkey overrides the state of the GR scrubber channel and determines
+// whether it should be created or not.
+//
+#define NV_REG_STR_RM_FORCE_GR_SCRUBBER_CHANNEL             "RmForceGrScrubberChannel"
+#define NV_REG_STR_RM_FORCE_GR_SCRUBBER_CHANNEL_DISABLE     0x00000000
+#define NV_REG_STR_RM_FORCE_GR_SCRUBBER_CHANNEL_ENABLE      0x00000001
 #endif // NVRM_REGISTRY_H
 

src/nvidia/src/kernel/gpu/device.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a

src/nvidia/src/kernel/gpu/fifo/kernel_channel.c

@@ -822,7 +822,9 @@ kchannelConstruct_IMPL
         cleanup);
 
     // Set up pNotifyActions
-    _kchannelSetupNotifyActions(pKernelChannel, pResourceRef->externalClassId);
+    NV_ASSERT_OK_OR_GOTO(status,
+        _kchannelSetupNotifyActions(pKernelChannel, pResourceRef->externalClassId),
+        cleanup);
     bNotifyActionsSetup = NV_TRUE;
 
     // Initialize the userd length
@@ -4494,7 +4496,7 @@ kchannelCtrlRotateSecureChannelIv_PHYSICAL
 )
 {
     NV_STATUS status;
-    
+
     NV_PRINTF(LEVEL_INFO, "Rotating IV in GSP-RM.\n");
 
     // CPU-side encrypt IV corresponds to GPU-side decrypt IV.

src/nvidia/src/kernel/gpu/gr/arch/turing/kgraphics_tu102.c

@@ -23,11 +23,37 @@
 
 #define NVOC_KERNEL_GRAPHICS_H_PRIVATE_ACCESS_ALLOWED
 
-#include "kernel/gpu/gr/kernel_graphics.h"
+#include "gpu_mgr/gpu_mgr.h"
 #include "kernel/gpu/mem_mgr/mem_mgr.h"
+#include "kernel/gpu/gr/kernel_graphics_manager.h"
+#include "kernel/gpu/gr/kernel_graphics.h"
+#include "kernel/gpu/device/device.h"
+#include "kernel/gpu/subdevice/subdevice.h"
+#include "kernel/rmapi/rmapi_utils.h"
+#include "kernel/core/locks.h"
+#include "kernel/gpu/mem_sys/kern_mem_sys.h"
+#include "kernel/mem_mgr/gpu_vaspace.h"
+#include "kernel/gpu/mem_mgr/mem_mgr.h"
+#include "virtualization/hypervisor/hypervisor.h"
+#include "kernel/gpu/mem_mgr/heap.h"
+#include "gpu/mem_mgr/virt_mem_allocator.h"
+#include "gpu/mmu/kern_gmmu.h"
+#include "platform/sli/sli.h"
+#include "rmapi/rs_utils.h"
+#include "rmapi/client.h"
+#include "nvrm_registry.h"
+#include "gpu/mem_mgr/heap.h"
 
 #include "ctrl/ctrl0080/ctrl0080fifo.h"
 
+#include "class/cla06f.h"
+#include "class/cl90f1.h" // FERMI_VASPACE_A
+#include "class/cl003e.h" // NV01_MEMORY_SYSTEM
+#include "class/cl50a0.h" // NV50_MEMORY_VIRTUAL
+#include "class/cl0040.h" // NV01_MEMORY_LOCAL_USER
+#include "class/clc36f.h" // VOLTA_CHANNEL_GPFIFO_A
+#include "class/clc46f.h" // TURING_CHANNEL_GPFIFO_A
+
 /*!
  * @brief Allocate common local/global buffers that are required by the graphics context
  *

src/nvidia/src/kernel/gpu/gr/kernel_graphics.c

@@ -95,6 +95,12 @@ static NV_STATUS _kgraphicsMapGlobalCtxBuffer(OBJGPU *pGpu, KernelGraphics *pKer
                                        KernelGraphicsContext *, GR_GLOBALCTX_BUFFER, NvBool bIsReadOnly);
 static NV_STATUS _kgraphicsPostSchedulingEnableHandler(OBJGPU *, void *);
 
+static void
+_kgraphicsInitRegistryOverrides(OBJGPU *pGpu, KernelGraphics *pKernelGraphics)
+{
+    return;
+}
+
 NV_STATUS
 kgraphicsConstructEngine_IMPL
 (
@@ -213,6 +219,7 @@ kgraphicsConstructEngine_IMPL
 
     NV_ASSERT_OK_OR_RETURN(fecsCtxswLoggingInit(pGpu, pKernelGraphics, &pKernelGraphics->pFecsTraceInfo));
 
+    _kgraphicsInitRegistryOverrides(pGpu, pKernelGraphics);
     return NV_OK;
 }
 
@@ -349,6 +356,7 @@ kgraphicsStatePreUnload_IMPL
     NvU32 flags
 )
 {
+
     fecsBufferUnmap(pGpu, pKernelGraphics);
 
     // Release global buffers used as part of the gr context, when not in S/R

src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c

@@ -326,7 +326,8 @@ vaspaceapiConstruct_IMPL
             memmgrIsPmaInitialized(pMemoryManager) &&
             memmgrAreClientPageTablesPmaManaged(pMemoryManager) &&
             !(allocFlags & NV_VASPACE_ALLOCATION_FLAGS_IS_EXTERNALLY_OWNED) &&
-            !(allocFlags & NV_VASPACE_ALLOCATION_FLAGS_IS_FLA))
+            !(allocFlags & NV_VASPACE_ALLOCATION_FLAGS_IS_FLA) &&
+            !(allocFlags & NV_VASPACE_ALLOCATION_FLAGS_PTETABLE_HEAP_MANAGED))
         {
             flags |= VASPACE_FLAGS_PTETABLE_PMA_MANAGED;
         }

src/nvidia/src/kernel/rmapi/nv_gpu_ops.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2013-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -9585,8 +9585,7 @@ void nvGpuOpsPagingChannelsUnmap(struct gpuAddressSpace *srcVaSpace,
         return;
     }
 
-    status = _nvGpuOpsLocksAcquire(RMAPI_LOCK_FLAGS_NONE, hClient, NULL, 2,
+    status = _nvGpuOpsLocksAcquireAll(RMAPI_LOCK_FLAGS_NONE, hClient, NULL, &acquiredLocks);
-                                   device->deviceInstance, srcVaSpace->device->deviceInstance, &acquiredLocks);
     if (status != NV_OK)
     {
         NV_PRINTF(LEVEL_ERROR,

version.mk

@@ -1,4 +1,4 @@
-NVIDIA_VERSION = 535.171.04
+NVIDIA_VERSION = 535.179
 
 # This file.
 VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST))