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https://github.com/NVIDIA/open-gpu-kernel-modules.git
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302 lines
12 KiB
C
302 lines
12 KiB
C
/*******************************************************************************
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Copyright (c) 2016-2021 NVIDIA Corporation
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to
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deal in the Software without restriction, including without limitation the
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rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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sell copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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DEALINGS IN THE SOFTWARE.
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*******************************************************************************/
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#include "uvm_linux.h"
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#include "uvm_global.h"
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#include "uvm_gpu.h"
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#include "uvm_hal.h"
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#include "uvm_push.h"
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#include "hwref/pascal/gp100/dev_fault.h"
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#include "clb069.h"
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#include "uvm_pascal_fault_buffer.h"
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typedef struct {
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NvU8 bufferEntry[NVB069_FAULT_BUF_SIZE];
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} fault_buffer_entry_b069_t;
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void uvm_hal_pascal_clear_replayable_faults(uvm_parent_gpu_t *parent_gpu, NvU32 get)
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{
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// No-op, this function is only used by pulse-based interrupt GPUs.
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}
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void uvm_hal_pascal_enable_replayable_faults(uvm_parent_gpu_t *parent_gpu)
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{
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volatile NvU32 *reg;
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NvU32 mask;
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reg = parent_gpu->fault_buffer_info.rm_info.replayable.pPmcIntrEnSet;
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mask = parent_gpu->fault_buffer_info.rm_info.replayable.replayableFaultMask;
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UVM_GPU_WRITE_ONCE(*reg, mask);
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}
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void uvm_hal_pascal_disable_replayable_faults(uvm_parent_gpu_t *parent_gpu)
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{
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volatile NvU32 *reg;
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NvU32 mask;
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reg = parent_gpu->fault_buffer_info.rm_info.replayable.pPmcIntrEnClear;
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mask = parent_gpu->fault_buffer_info.rm_info.replayable.replayableFaultMask;
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UVM_GPU_WRITE_ONCE(*reg, mask);
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}
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NvU32 uvm_hal_pascal_fault_buffer_read_put(uvm_parent_gpu_t *parent_gpu)
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{
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NvU32 put = UVM_GPU_READ_ONCE(*parent_gpu->fault_buffer_info.rm_info.replayable.pFaultBufferPut);
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UVM_ASSERT(put < parent_gpu->fault_buffer_info.replayable.max_faults);
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return put;
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}
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NvU32 uvm_hal_pascal_fault_buffer_read_get(uvm_parent_gpu_t *parent_gpu)
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{
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NvU32 get = UVM_GPU_READ_ONCE(*parent_gpu->fault_buffer_info.rm_info.replayable.pFaultBufferGet);
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UVM_ASSERT(get < parent_gpu->fault_buffer_info.replayable.max_faults);
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return get;
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}
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void uvm_hal_pascal_fault_buffer_write_get(uvm_parent_gpu_t *parent_gpu, NvU32 index)
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{
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UVM_ASSERT(index < parent_gpu->fault_buffer_info.replayable.max_faults);
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UVM_GPU_WRITE_ONCE(*parent_gpu->fault_buffer_info.rm_info.replayable.pFaultBufferGet, index);
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}
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static uvm_fault_access_type_t get_fault_access_type(const NvU32 *fault_entry)
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{
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NvU32 hw_access_type_value = READ_HWVALUE_MW(fault_entry, B069, FAULT_BUF_ENTRY, ACCESS_TYPE);
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switch (hw_access_type_value)
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{
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case NV_PFAULT_ACCESS_TYPE_READ:
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return UVM_FAULT_ACCESS_TYPE_READ;
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case NV_PFAULT_ACCESS_TYPE_WRITE:
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return UVM_FAULT_ACCESS_TYPE_WRITE;
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case NV_PFAULT_ACCESS_TYPE_ATOMIC:
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return UVM_FAULT_ACCESS_TYPE_ATOMIC_STRONG;
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case NV_PFAULT_ACCESS_TYPE_PREFETCH:
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return UVM_FAULT_ACCESS_TYPE_PREFETCH;
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}
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UVM_ASSERT_MSG(false, "Invalid fault access type value: %d\n", hw_access_type_value);
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return UVM_FAULT_ACCESS_TYPE_COUNT;
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}
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static uvm_fault_type_t get_fault_type(const NvU32 *fault_entry)
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{
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NvU32 hw_fault_type_value = READ_HWVALUE_MW(fault_entry, B069, FAULT_BUF_ENTRY, FAULT_TYPE);
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switch (hw_fault_type_value)
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{
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case NV_PFAULT_FAULT_TYPE_PDE:
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return UVM_FAULT_TYPE_INVALID_PDE;
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case NV_PFAULT_FAULT_TYPE_PTE:
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return UVM_FAULT_TYPE_INVALID_PTE;
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case NV_PFAULT_FAULT_TYPE_RO_VIOLATION:
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return UVM_FAULT_TYPE_WRITE;
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case NV_PFAULT_FAULT_TYPE_ATOMIC_VIOLATION:
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return UVM_FAULT_TYPE_ATOMIC;
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case NV_PFAULT_FAULT_TYPE_PDE_SIZE:
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return UVM_FAULT_TYPE_PDE_SIZE;
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case NV_PFAULT_FAULT_TYPE_VA_LIMIT_VIOLATION:
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return UVM_FAULT_TYPE_VA_LIMIT_VIOLATION;
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case NV_PFAULT_FAULT_TYPE_UNBOUND_INST_BLOCK:
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return UVM_FAULT_TYPE_UNBOUND_INST_BLOCK;
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case NV_PFAULT_FAULT_TYPE_PRIV_VIOLATION:
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return UVM_FAULT_TYPE_PRIV_VIOLATION;
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case NV_PFAULT_FAULT_TYPE_PITCH_MASK_VIOLATION:
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return UVM_FAULT_TYPE_PITCH_MASK_VIOLATION;
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case NV_PFAULT_FAULT_TYPE_WORK_CREATION:
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return UVM_FAULT_TYPE_WORK_CREATION;
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case NV_PFAULT_FAULT_TYPE_UNSUPPORTED_APERTURE:
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return UVM_FAULT_TYPE_UNSUPPORTED_APERTURE;
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case NV_PFAULT_FAULT_TYPE_COMPRESSION_FAILURE:
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return UVM_FAULT_TYPE_COMPRESSION_FAILURE;
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case NV_PFAULT_FAULT_TYPE_UNSUPPORTED_KIND:
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return UVM_FAULT_TYPE_UNSUPPORTED_KIND;
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case NV_PFAULT_FAULT_TYPE_REGION_VIOLATION:
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return UVM_FAULT_TYPE_REGION_VIOLATION;
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case NV_PFAULT_FAULT_TYPE_POISONED:
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return UVM_FAULT_TYPE_POISONED;
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}
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UVM_ASSERT_MSG(false, "Invalid fault type value: %d\n", hw_fault_type_value);
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return UVM_FAULT_TYPE_COUNT;
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}
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static uvm_fault_client_type_t get_fault_client_type(const NvU32 *fault_entry)
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{
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NvU32 hw_client_type_value = READ_HWVALUE_MW(fault_entry, B069, FAULT_BUF_ENTRY, MMU_CLIENT_TYPE);
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switch (hw_client_type_value)
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{
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case NV_PFAULT_MMU_CLIENT_TYPE_GPC:
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return UVM_FAULT_CLIENT_TYPE_GPC;
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case NV_PFAULT_MMU_CLIENT_TYPE_HUB:
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return UVM_FAULT_CLIENT_TYPE_HUB;
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}
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UVM_ASSERT_MSG(false, "Invalid mmu client type value: %d\n", hw_client_type_value);
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return UVM_FAULT_CLIENT_TYPE_COUNT;
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}
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static uvm_aperture_t get_fault_inst_aperture(NvU32 *fault_entry)
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{
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NvU32 hw_aperture_value = READ_HWVALUE_MW(fault_entry, B069, FAULT_BUF_ENTRY, INST_APERTURE);
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switch (hw_aperture_value)
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{
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case NVB069_FAULT_BUF_ENTRY_INST_APERTURE_VID_MEM:
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return UVM_APERTURE_VID;
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case NVB069_FAULT_BUF_ENTRY_INST_APERTURE_SYS_MEM_COHERENT:
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case NVB069_FAULT_BUF_ENTRY_INST_APERTURE_SYS_MEM_NONCOHERENT:
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return UVM_APERTURE_SYS;
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}
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UVM_ASSERT_MSG(false, "Invalid inst aperture value: %d\n", hw_aperture_value);
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return UVM_APERTURE_MAX;
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}
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static NvU32 *get_fault_buffer_entry(uvm_parent_gpu_t *parent_gpu, NvU32 index)
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{
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fault_buffer_entry_b069_t *buffer_start;
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NvU32 *fault_entry;
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UVM_ASSERT(index < parent_gpu->fault_buffer_info.replayable.max_faults);
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buffer_start = (fault_buffer_entry_b069_t *)parent_gpu->fault_buffer_info.rm_info.replayable.bufferAddress;
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fault_entry = (NvU32 *)&buffer_start[index];
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return fault_entry;
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}
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void uvm_hal_pascal_fault_buffer_parse_entry(uvm_parent_gpu_t *parent_gpu,
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NvU32 index,
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uvm_fault_buffer_entry_t *buffer_entry)
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{
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NV_STATUS status;
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NvU32 *fault_entry;
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NvU64 addr_hi, addr_lo;
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NvU64 timestamp_hi, timestamp_lo;
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NvU16 gpc_utlb_id;
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NvU32 utlb_id;
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BUILD_BUG_ON(NVB069_FAULT_BUF_SIZE > UVM_GPU_MMU_MAX_FAULT_PACKET_SIZE);
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status = NV_OK;
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fault_entry = get_fault_buffer_entry(parent_gpu, index);
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// Valid bit must be set before this function is called
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UVM_ASSERT(parent_gpu->fault_buffer_hal->entry_is_valid(parent_gpu, index));
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addr_hi = READ_HWVALUE_MW(fault_entry, B069, FAULT_BUF_ENTRY, INST_HI);
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addr_lo = READ_HWVALUE_MW(fault_entry, B069, FAULT_BUF_ENTRY, INST_LO);
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buffer_entry->instance_ptr.address = addr_lo + (addr_hi << HWSIZE_MW(B069, FAULT_BUF_ENTRY, INST_LO));
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// HW value contains the 4K page number. Shift to build the full address
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buffer_entry->instance_ptr.address <<= 12;
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buffer_entry->instance_ptr.aperture = get_fault_inst_aperture(fault_entry);
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addr_hi = READ_HWVALUE_MW(fault_entry, B069, FAULT_BUF_ENTRY, ADDR_HI);
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addr_lo = READ_HWVALUE_MW(fault_entry, B069, FAULT_BUF_ENTRY, ADDR_LO);
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buffer_entry->fault_address = addr_lo + (addr_hi << HWSIZE_MW(B069, FAULT_BUF_ENTRY, ADDR_LO));
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buffer_entry->fault_address = uvm_parent_gpu_canonical_address(parent_gpu, buffer_entry->fault_address);
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timestamp_hi = READ_HWVALUE_MW(fault_entry, B069, FAULT_BUF_ENTRY, TIMESTAMP_HI);
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timestamp_lo = READ_HWVALUE_MW(fault_entry, B069, FAULT_BUF_ENTRY, TIMESTAMP_LO);
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buffer_entry->timestamp = timestamp_lo + (timestamp_hi << HWSIZE_MW(B069, FAULT_BUF_ENTRY, TIMESTAMP_LO));
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buffer_entry->fault_type = get_fault_type(fault_entry);
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buffer_entry->fault_access_type = get_fault_access_type(fault_entry);
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buffer_entry->fault_source.client_type = get_fault_client_type(fault_entry);
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if (buffer_entry->fault_source.client_type == UVM_FAULT_CLIENT_TYPE_HUB)
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UVM_ASSERT_MSG(false, "Invalid client type: HUB\n");
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buffer_entry->fault_source.client_id = READ_HWVALUE_MW(fault_entry, B069, FAULT_BUF_ENTRY, CLIENT);
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BUILD_BUG_ON(sizeof(buffer_entry->fault_source.client_id) * 8 < DRF_SIZE_MW(NVB069_FAULT_BUF_ENTRY_CLIENT));
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buffer_entry->fault_source.gpc_id = READ_HWVALUE_MW(fault_entry, B069, FAULT_BUF_ENTRY, GPC_ID);
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BUILD_BUG_ON(sizeof(buffer_entry->fault_source.gpc_id) * 8 < DRF_SIZE_MW(NVB069_FAULT_BUF_ENTRY_GPC_ID));
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gpc_utlb_id = parent_gpu->arch_hal->mmu_client_id_to_utlb_id(buffer_entry->fault_source.client_id);
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UVM_ASSERT(gpc_utlb_id < parent_gpu->utlb_per_gpc_count);
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// Compute global uTLB id
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utlb_id = buffer_entry->fault_source.gpc_id * parent_gpu->utlb_per_gpc_count + gpc_utlb_id;
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UVM_ASSERT(utlb_id < parent_gpu->fault_buffer_info.replayable.utlb_count);
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buffer_entry->fault_source.utlb_id = utlb_id;
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buffer_entry->is_replayable = true;
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buffer_entry->is_virtual = true;
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buffer_entry->in_protected_mode = false;
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buffer_entry->fault_source.mmu_engine_type = UVM_MMU_ENGINE_TYPE_GRAPHICS;
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buffer_entry->fault_source.mmu_engine_id = NV_PFAULT_MMU_ENG_ID_GRAPHICS;
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buffer_entry->fault_source.ve_id = 0;
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// Automatically clear valid bit for the entry in the fault buffer
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uvm_hal_pascal_fault_buffer_entry_clear_valid(parent_gpu, index);
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}
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bool uvm_hal_pascal_fault_buffer_entry_is_valid(uvm_parent_gpu_t *parent_gpu, NvU32 index)
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{
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NvU32 *fault_entry;
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bool is_valid;
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fault_entry = get_fault_buffer_entry(parent_gpu, index);
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is_valid = READ_HWVALUE_MW(fault_entry, B069, FAULT_BUF_ENTRY, VALID);
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return is_valid;
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}
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void uvm_hal_pascal_fault_buffer_entry_clear_valid(uvm_parent_gpu_t *parent_gpu, NvU32 index)
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{
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NvU32 *fault_entry;
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fault_entry = get_fault_buffer_entry(parent_gpu, index);
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WRITE_HWCONST_MW(fault_entry, B069, FAULT_BUF_ENTRY, VALID, FALSE);
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}
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NvU32 uvm_hal_pascal_fault_buffer_entry_size(uvm_parent_gpu_t *parent_gpu)
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{
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return NVB069_FAULT_BUF_SIZE;
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}
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void uvm_hal_pascal_fault_buffer_parse_non_replayable_entry_unsupported(uvm_parent_gpu_t *parent_gpu,
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void *fault_packet,
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uvm_fault_buffer_entry_t *buffer_entry)
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{
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UVM_ASSERT_MSG(false, "fault_buffer_parse_non_replayable_entry called on Pascal GPU\n");
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}
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