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https://github.com/NVIDIA/open-gpu-kernel-modules.git
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428 lines
14 KiB
C
428 lines
14 KiB
C
/*
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* SPDX-FileCopyrightText: Copyright (c) 2011-2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _NV_P2P_H_
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#define _NV_P2P_H_
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/*
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* NVIDIA P2P Structure Versioning
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*
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* For the nvidia_p2p_*_t structures allocated by the NVIDIA driver, it will
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* set the version field of the structure according to the definition used by
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* the NVIDIA driver. The "major" field of the version is defined as the upper
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* 16 bits, and the "minor" field of the version is defined as the lower 16
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* bits. The version field will always be the first 4 bytes of the structure,
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* and third-party drivers should check the value of this field in structures
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* allocated by the NVIDIA driver to ensure runtime compatibility.
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*
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* In general, version numbers will be incremented as follows:
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* - When a backwards-compatible change is made to the structure layout, the
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* minor version for that structure will be incremented. Third-party drivers
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* built against an older minor version will continue to work with the newer
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* minor version used by the NVIDIA driver, without recompilation.
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* - When a breaking change is made to the structure layout, the major version
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* will be incremented. Third-party drivers built against an older major
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* version require at least recompilation and potentially additional updates
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* to use the new API.
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*/
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#define NVIDIA_P2P_MAJOR_VERSION_MASK 0xffff0000
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#define NVIDIA_P2P_MINOR_VERSION_MASK 0x0000ffff
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#define NVIDIA_P2P_MAJOR_VERSION(v) \
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(((v) & NVIDIA_P2P_MAJOR_VERSION_MASK) >> 16)
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#define NVIDIA_P2P_MINOR_VERSION(v) \
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(((v) & NVIDIA_P2P_MINOR_VERSION_MASK))
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#define NVIDIA_P2P_MAJOR_VERSION_MATCHES(p, v) \
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(NVIDIA_P2P_MAJOR_VERSION((p)->version) == NVIDIA_P2P_MAJOR_VERSION(v))
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#define NVIDIA_P2P_VERSION_COMPATIBLE(p, v) \
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(NVIDIA_P2P_MAJOR_VERSION_MATCHES(p, v) && \
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(NVIDIA_P2P_MINOR_VERSION((p)->version) >= (NVIDIA_P2P_MINOR_VERSION(v))))
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enum {
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NVIDIA_P2P_ARCHITECTURE_TESLA = 0,
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NVIDIA_P2P_ARCHITECTURE_FERMI,
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NVIDIA_P2P_ARCHITECTURE_CURRENT = NVIDIA_P2P_ARCHITECTURE_FERMI
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};
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#define NVIDIA_P2P_PARAMS_VERSION 0x00010001
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enum {
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NVIDIA_P2P_PARAMS_ADDRESS_INDEX_GPU = 0,
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NVIDIA_P2P_PARAMS_ADDRESS_INDEX_THIRD_PARTY_DEVICE,
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NVIDIA_P2P_PARAMS_ADDRESS_INDEX_MAX = \
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NVIDIA_P2P_PARAMS_ADDRESS_INDEX_THIRD_PARTY_DEVICE
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};
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#define NVIDIA_P2P_GPU_UUID_LEN 16
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typedef
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struct nvidia_p2p_params {
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uint32_t version;
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uint32_t architecture;
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union nvidia_p2p_mailbox_addresses {
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struct {
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uint64_t wmb_addr;
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uint64_t wmb_data;
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uint64_t rreq_addr;
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uint64_t rcomp_addr;
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uint64_t reserved[2];
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} fermi;
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} addresses[NVIDIA_P2P_PARAMS_ADDRESS_INDEX_MAX+1];
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} nvidia_p2p_params_t;
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/*
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* Capability flag for users to detect
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* driver support for persistent pages.
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*/
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extern int nvidia_p2p_cap_persistent_pages;
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#define NVIDIA_P2P_CAP_PERSISTENT_PAGES
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/*
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* This API is not supported.
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*/
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int nvidia_p2p_init_mapping(uint64_t p2p_token,
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struct nvidia_p2p_params *params,
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void (*destroy_callback)(void *data),
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void *data);
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/*
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* This API is not supported.
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*/
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int nvidia_p2p_destroy_mapping(uint64_t p2p_token);
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enum nvidia_p2p_page_size_type {
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NVIDIA_P2P_PAGE_SIZE_4KB = 0,
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NVIDIA_P2P_PAGE_SIZE_64KB,
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NVIDIA_P2P_PAGE_SIZE_128KB,
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NVIDIA_P2P_PAGE_SIZE_COUNT
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};
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typedef
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struct nvidia_p2p_page {
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uint64_t physical_address;
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union nvidia_p2p_request_registers {
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struct {
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uint32_t wreqmb_h;
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uint32_t rreqmb_h;
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uint32_t rreqmb_0;
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uint32_t reserved[3];
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} fermi;
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} registers;
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} nvidia_p2p_page_t;
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#define NVIDIA_P2P_PAGE_TABLE_VERSION 0x00010002
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#define NVIDIA_P2P_PAGE_TABLE_VERSION_COMPATIBLE(p) \
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NVIDIA_P2P_VERSION_COMPATIBLE(p, NVIDIA_P2P_PAGE_TABLE_VERSION)
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typedef
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struct nvidia_p2p_page_table {
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uint32_t version;
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uint32_t page_size; /* enum nvidia_p2p_page_size_type */
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struct nvidia_p2p_page **pages;
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uint32_t entries;
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uint8_t *gpu_uuid;
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} nvidia_p2p_page_table_t;
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/*
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* @brief
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* Make the pages underlying a range of GPU virtual memory
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* accessible to a third-party device.
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*
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* This API only supports pinned, GPU-resident memory, such as that provided
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* by cudaMalloc().
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*
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* This API may sleep.
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*
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* @param[in] p2p_token
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* A token that uniquely identifies the P2P mapping.
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* @param[in] va_space
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* A GPU virtual address space qualifier.
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* @param[in] virtual_address
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* The start address in the specified virtual address space.
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* Address must be aligned to the 64KB boundary.
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* @param[in] length
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* The length of the requested P2P mapping.
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* Length must be a multiple of 64KB.
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* @param[out] page_table
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* A pointer to an array of structures with P2P PTEs.
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* @param[in] free_callback
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* A pointer to the function to be invoked when the pages
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* underlying the virtual address range are freed
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* implicitly.
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* If NULL, persistent pages will be returned.
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* This means the pages underlying the range of GPU virtual memory
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* will persist until explicitly freed by nvidia_p2p_put_pages().
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* Persistent GPU memory mappings are not supported on PowerPC,
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* MIG-enabled devices and vGPU.
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* @param[in] data
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* A non-NULL opaque pointer to private data to be passed to the
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* callback function.
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*
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* @return
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* 0 upon successful completion.
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* -EINVAL if an invalid argument was supplied.
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* -ENOTSUPP if the requested operation is not supported.
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* -ENOMEM if the driver failed to allocate memory or if
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* insufficient resources were available to complete the operation.
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* -EIO if an unknown error occurred.
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*/
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int nvidia_p2p_get_pages(uint64_t p2p_token, uint32_t va_space,
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uint64_t virtual_address,
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uint64_t length,
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struct nvidia_p2p_page_table **page_table,
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void (*free_callback)(void *data),
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void *data);
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#define NVIDIA_P2P_DMA_MAPPING_VERSION 0x00020003
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#define NVIDIA_P2P_DMA_MAPPING_VERSION_COMPATIBLE(p) \
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NVIDIA_P2P_VERSION_COMPATIBLE(p, NVIDIA_P2P_DMA_MAPPING_VERSION)
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struct pci_dev;
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typedef
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struct nvidia_p2p_dma_mapping {
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uint32_t version;
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enum nvidia_p2p_page_size_type page_size_type;
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uint32_t entries;
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uint64_t *dma_addresses;
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void *private;
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struct pci_dev *pci_dev;
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} nvidia_p2p_dma_mapping_t;
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/*
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* @brief
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* Make the physical pages retrieved using nvidia_p2p_get_pages accessible to
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* a third-party device.
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*
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* @param[in] peer
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* The struct pci_dev * of the peer device that needs to DMA to/from the
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* mapping.
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* @param[in] page_table
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* The page table outlining the physical pages underlying the mapping, as
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* retrieved with nvidia_p2p_get_pages().
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* @param[out] dma_mapping
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* The DMA mapping containing the DMA addresses to use on the third-party
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* device.
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*
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* @return
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* 0 upon successful completion.
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* -EINVAL if an invalid argument was supplied.
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* -ENOTSUPP if the requested operation is not supported.
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* -EIO if an unknown error occurred.
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*/
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int nvidia_p2p_dma_map_pages(struct pci_dev *peer,
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struct nvidia_p2p_page_table *page_table,
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struct nvidia_p2p_dma_mapping **dma_mapping);
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/*
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* @brief
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* Unmap the physical pages previously mapped to the third-party device by
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* nvidia_p2p_dma_map_pages().
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*
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* @param[in] peer
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* The struct pci_dev * of the peer device that the DMA mapping belongs to.
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* @param[in] page_table
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* The page table backing the DMA mapping to be unmapped.
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* @param[in] dma_mapping
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* The DMA mapping containing the DMA addresses used by the third-party
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* device, as retrieved with nvidia_p2p_dma_map_pages(). After this call
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* returns, neither this struct nor the addresses contained within will be
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* valid for use by the third-party device.
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*
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* @return
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* 0 upon successful completion.
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* -EINVAL if an invalid argument was supplied.
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* -EIO if an unknown error occurred.
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*/
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int nvidia_p2p_dma_unmap_pages(struct pci_dev *peer,
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struct nvidia_p2p_page_table *page_table,
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struct nvidia_p2p_dma_mapping *dma_mapping);
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/*
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* @brief
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* Release a set of pages previously made accessible to
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* a third-party device.
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*
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* @param[in] p2p_token
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* A token that uniquely identifies the P2P mapping.
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* @param[in] va_space
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* A GPU virtual address space qualifier.
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* @param[in] virtual_address
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* The start address in the specified virtual address space.
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* @param[in] page_table
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* A pointer to the array of structures with P2P PTEs.
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*
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* @return
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* 0 upon successful completion.
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* -EINVAL if an invalid argument was supplied.
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* -EIO if an unknown error occurred.
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*/
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int nvidia_p2p_put_pages(uint64_t p2p_token, uint32_t va_space,
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uint64_t virtual_address,
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struct nvidia_p2p_page_table *page_table);
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/*
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* @brief
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* Free a third-party P2P page table. (This function is a no-op.)
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*
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* @param[in] page_table
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* A pointer to the array of structures with P2P PTEs.
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*
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* @return
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* 0 upon successful completion.
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* -EINVAL if an invalid argument was supplied.
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*/
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int nvidia_p2p_free_page_table(struct nvidia_p2p_page_table *page_table);
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/*
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* @brief
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* Free a third-party P2P DMA mapping. (This function is a no-op.)
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*
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* @param[in] dma_mapping
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* A pointer to the DMA mapping structure.
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*
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* @return
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* 0 upon successful completion.
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* -EINVAL if an invalid argument was supplied.
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*/
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int nvidia_p2p_free_dma_mapping(struct nvidia_p2p_dma_mapping *dma_mapping);
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#define NVIDIA_P2P_RSYNC_DRIVER_VERSION 0x00010001
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#define NVIDIA_P2P_RSYNC_DRIVER_VERSION_COMPATIBLE(p) \
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NVIDIA_P2P_VERSION_COMPATIBLE(p, NVIDIA_P2P_RSYNC_DRIVER_VERSION)
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typedef
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struct nvidia_p2p_rsync_driver {
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uint32_t version;
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int (*get_relaxed_ordering_mode)(int *mode, void *data);
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void (*put_relaxed_ordering_mode)(int mode, void *data);
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void (*wait_for_rsync)(struct pci_dev *gpu, void *data);
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} nvidia_p2p_rsync_driver_t;
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/*
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* @brief
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* Registers the rsync driver.
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*
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* @param[in] driver
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* A pointer to the rsync driver structure. The NVIDIA driver would use,
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*
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* get_relaxed_ordering_mode to obtain a reference to the current relaxed
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* ordering mode (treated as a boolean) from the rsync driver.
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*
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* put_relaxed_ordering_mode to release a reference to the current relaxed
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* ordering mode back to the rsync driver. The NVIDIA driver will call this
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* function once for each successful call to get_relaxed_ordering_mode, and
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* the relaxed ordering mode must not change until the last reference is
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* released.
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*
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* wait_for_rsync to call into the rsync module to issue RSYNC. This callback
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* can't sleep or re-schedule as it may arrive under spinlocks.
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* @param[in] data
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* A pointer to the rsync driver's private data.
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*
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* @Returns
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* 0 upon successful completion.
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* -EINVAL parameters are incorrect.
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* -EBUSY if a module is already registered or GPU devices are in use.
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*/
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int nvidia_p2p_register_rsync_driver(nvidia_p2p_rsync_driver_t *driver,
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void *data);
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/*
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* @brief
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* Unregisters the rsync driver.
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*
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* @param[in] driver
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* A pointer to the rsync driver structure.
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* @param[in] data
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* A pointer to the rsync driver's private data.
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*/
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void nvidia_p2p_unregister_rsync_driver(nvidia_p2p_rsync_driver_t *driver,
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void *data);
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#define NVIDIA_P2P_RSYNC_REG_INFO_VERSION 0x00020001
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#define NVIDIA_P2P_RSYNC_REG_INFO_VERSION_COMPATIBLE(p) \
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NVIDIA_P2P_VERSION_COMPATIBLE(p, NVIDIA_P2P_RSYNC_REG_INFO_VERSION)
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typedef struct nvidia_p2p_rsync_reg {
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void *ptr;
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size_t size;
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struct pci_dev *ibmnpu;
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struct pci_dev *gpu;
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uint32_t cluster_id;
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uint32_t socket_id;
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} nvidia_p2p_rsync_reg_t;
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typedef struct nvidia_p2p_rsync_reg_info {
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uint32_t version;
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nvidia_p2p_rsync_reg_t *regs;
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size_t entries;
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} nvidia_p2p_rsync_reg_info_t;
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/*
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* @brief
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* Gets rsync (GEN-ID) register information associated with the supported
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* NPUs.
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*
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* The caller would use the returned information {GPU device, NPU device,
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* socket-id, cluster-id} to pick the optimal generation registers to issue
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* RSYNC (NVLink HW flush).
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*
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* The interface allocates structures to return the information, hence
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* nvidia_p2p_put_rsync_registers() must be called to free the structures.
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*
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* Note, cluster-id is hardcoded to zero as early system configurations would
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* only support cluster mode i.e. all devices would share the same cluster-id
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* (0). In the future, appropriate kernel support would be needed to query
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* cluster-ids.
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*
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* @param[out] reg_info
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* A pointer to the rsync reg info structure.
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*
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* @Returns
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* 0 Upon successful completion. Otherwise, returns negative value.
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*/
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int nvidia_p2p_get_rsync_registers(nvidia_p2p_rsync_reg_info_t **reg_info);
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/*
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* @brief
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* Frees the structures allocated by nvidia_p2p_get_rsync_registers().
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*
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* @param[in] reg_info
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* A pointer to the rsync reg info structure.
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*/
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void nvidia_p2p_put_rsync_registers(nvidia_p2p_rsync_reg_info_t *reg_info);
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#endif /* _NV_P2P_H_ */
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