open-gpu-kernel-modules/kernel-open/nvidia-uvm/uvm_pascal_fault_buffer.h
2022-05-09 13:18:59 -07:00

57 lines
2.5 KiB
C

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#ifndef __UVM_HAL_PASCAL_FAULT_BUFFER_H__
#define __UVM_HAL_PASCAL_FAULT_BUFFER_H__
#include "nvtypes.h"
#include "uvm_common.h"
#include "uvm_gpu.h"
// There are up to 5 TPCs per GPC in Pascal, and there is 1 LTP uTLB per TPC. Besides, there is one RGG uTLB per GPC.
// Each TPC has a number of clients that can make requests to its uTLB: 1xTPCCS, 1xPE, 2xT1. The client ids are local
// to their GPC and the id mapping is linear across TPCs:
// TPC_n has TPCCS_n, PE_n, T1_p, and T1_q, where p=2*n and q=p+1.
//
// NV_PFAULT_CLIENT_GPC_LTP_UTLB_n and NV_PFAULT_CLIENT_GPC_RGG_UTLB enums can be ignored. These will never be reported
// in a fault message, and should never be used in an invalidate. Therefore, we define our own values.
typedef enum {
UVM_PASCAL_GPC_UTLB_ID_RGG = 0,
UVM_PASCAL_GPC_UTLB_ID_LTP0 = 1,
UVM_PASCAL_GPC_UTLB_ID_LTP1 = 2,
UVM_PASCAL_GPC_UTLB_ID_LTP2 = 3,
UVM_PASCAL_GPC_UTLB_ID_LTP3 = 4,
UVM_PASCAL_GPC_UTLB_ID_LTP4 = 5,
UVM_PASCAL_GPC_UTLB_COUNT,
} uvm_pascal_gpc_utlb_id_t;
static NvU32 uvm_pascal_get_utlbs_per_gpc(uvm_parent_gpu_t *parent_gpu)
{
NvU32 utlbs = parent_gpu->rm_info.maxTpcPerGpcCount + 1;
UVM_ASSERT(utlbs <= UVM_PASCAL_GPC_UTLB_COUNT);
return utlbs;
}
#endif