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https://github.com/NVIDIA/open-gpu-kernel-modules.git
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234 lines
9.0 KiB
C
234 lines
9.0 KiB
C
/*******************************************************************************
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Copyright (c) 2018-2022 NVIDIA Corporation
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to
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deal in the Software without restriction, including without limitation the
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rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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sell copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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DEALINGS IN THE SOFTWARE.
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*******************************************************************************/
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#include "uvm_hal.h"
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#include "uvm_hal_types.h"
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#include "clc6b5.h"
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#include "clc7b5.h"
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#include "clc56f.h" // Needed because HAL ce_init pushes SET_OBJECT
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bool uvm_hal_ampere_ce_method_is_valid_c6b5(uvm_push_t *push, NvU32 method_address, NvU32 method_data)
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{
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if (!uvm_channel_is_proxy(push->channel))
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return true;
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switch (method_address) {
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case NVC56F_SET_OBJECT:
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case NVC6B5_SET_SEMAPHORE_A:
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case NVC6B5_SET_SEMAPHORE_B:
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case NVC6B5_SET_SEMAPHORE_PAYLOAD:
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case NVC6B5_SET_SRC_PHYS_MODE:
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case NVC6B5_SET_DST_PHYS_MODE:
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case NVC6B5_LAUNCH_DMA:
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case NVC6B5_OFFSET_IN_UPPER:
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case NVC6B5_OFFSET_IN_LOWER:
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case NVC6B5_OFFSET_OUT_UPPER:
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case NVC6B5_OFFSET_OUT_LOWER:
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case NVC6B5_LINE_LENGTH_IN:
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case NVC6B5_SET_REMAP_CONST_A:
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case NVC6B5_SET_REMAP_CONST_B:
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case NVC6B5_SET_REMAP_COMPONENTS:
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return true;
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}
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UVM_ERR_PRINT("Unsupported CE method 0x%x\n", method_address);
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return false;
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}
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static NvU32 ce_aperture(uvm_aperture_t aperture)
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{
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BUILD_BUG_ON(HWCONST(C6B5, SET_SRC_PHYS_MODE, TARGET, LOCAL_FB) !=
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HWCONST(C6B5, SET_DST_PHYS_MODE, TARGET, LOCAL_FB));
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BUILD_BUG_ON(HWCONST(C6B5, SET_SRC_PHYS_MODE, TARGET, COHERENT_SYSMEM) !=
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HWCONST(C6B5, SET_DST_PHYS_MODE, TARGET, COHERENT_SYSMEM));
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BUILD_BUG_ON(HWCONST(C6B5, SET_SRC_PHYS_MODE, TARGET, PEERMEM) !=
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HWCONST(C6B5, SET_DST_PHYS_MODE, TARGET, PEERMEM));
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if (aperture == UVM_APERTURE_SYS) {
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return HWCONST(C6B5, SET_SRC_PHYS_MODE, TARGET, COHERENT_SYSMEM);
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}
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else if (aperture == UVM_APERTURE_VID) {
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return HWCONST(C6B5, SET_SRC_PHYS_MODE, TARGET, LOCAL_FB);
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}
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else {
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return HWCONST(C6B5, SET_SRC_PHYS_MODE, TARGET, PEERMEM) |
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HWVALUE(C6B5, SET_SRC_PHYS_MODE, FLA, 0) |
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HWVALUE(C6B5, SET_SRC_PHYS_MODE, PEER_ID, UVM_APERTURE_PEER_ID(aperture));
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}
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}
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// Push SET_{SRC,DST}_PHYS mode if needed and return LAUNCH_DMA_{SRC,DST}_TYPE
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// flags
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NvU32 uvm_hal_ampere_ce_phys_mode(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src)
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{
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NvU32 launch_dma_src_dst_type = 0;
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if (src.is_virtual)
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launch_dma_src_dst_type |= HWCONST(C6B5, LAUNCH_DMA, SRC_TYPE, VIRTUAL);
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else
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launch_dma_src_dst_type |= HWCONST(C6B5, LAUNCH_DMA, SRC_TYPE, PHYSICAL);
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if (dst.is_virtual)
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launch_dma_src_dst_type |= HWCONST(C6B5, LAUNCH_DMA, DST_TYPE, VIRTUAL);
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else
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launch_dma_src_dst_type |= HWCONST(C6B5, LAUNCH_DMA, DST_TYPE, PHYSICAL);
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if (!src.is_virtual && !dst.is_virtual) {
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NV_PUSH_2U(C6B5, SET_SRC_PHYS_MODE, ce_aperture(src.aperture),
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SET_DST_PHYS_MODE, ce_aperture(dst.aperture));
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}
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else if (!src.is_virtual) {
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NV_PUSH_1U(C6B5, SET_SRC_PHYS_MODE, ce_aperture(src.aperture));
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}
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else if (!dst.is_virtual) {
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NV_PUSH_1U(C6B5, SET_DST_PHYS_MODE, ce_aperture(dst.aperture));
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}
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return launch_dma_src_dst_type;
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}
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NvU32 uvm_hal_ampere_ce_plc_mode_c7b5(void)
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{
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return HWCONST(C7B5, LAUNCH_DMA, DISABLE_PLC, TRUE);
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}
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bool uvm_hal_ampere_ce_memcopy_is_valid_c6b5(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src)
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{
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NvU64 push_begin_gpu_va;
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uvm_gpu_t *gpu = uvm_push_get_gpu(push);
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if (!uvm_gpu_is_virt_mode_sriov_heavy(gpu))
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return true;
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if (uvm_channel_is_proxy(push->channel)) {
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if (dst.is_virtual) {
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UVM_ERR_PRINT("Destination address of memcopy must be physical, not virtual\n");
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return false;
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}
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if (dst.aperture != UVM_APERTURE_VID) {
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UVM_ERR_PRINT("Destination address of memcopy must be in vidmem\n");
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return false;
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}
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// The source address is irrelevant, since it is a pushbuffer offset
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if (!IS_ALIGNED(dst.address, 8)){
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UVM_ERR_PRINT("Destination address of memcopy is not 8-byte aligned");
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return false;
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}
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if (!src.is_virtual) {
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UVM_ERR_PRINT("Source address of memcopy must be virtual\n");
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return false;
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}
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push_begin_gpu_va = uvm_pushbuffer_get_gpu_va_for_push(push->channel->pool->manager->pushbuffer, push);
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if ((src.address < push_begin_gpu_va) || (src.address >= push_begin_gpu_va + uvm_push_get_size(push))) {
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UVM_ERR_PRINT("Source address of memcopy must point to pushbuffer\n");
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return false;
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}
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}
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else {
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// TODO: Bug 3429418: When in SR-IOV heavy, a memcopy/memset pushed to a
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// UVM internal channel cannot use peer physical addresses.
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if (!dst.is_virtual && !uvm_aperture_is_peer(dst.aperture)) {
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UVM_ERR_PRINT("Destination address of memcopy must be virtual, not physical (aperture: %s)\n",
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uvm_gpu_address_aperture_string(dst));
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return false;
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}
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if (!src.is_virtual && !uvm_aperture_is_peer(src.aperture)) {
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UVM_ERR_PRINT("Source address of memcopy must be virtual, not physical (aperture: %s)\n",
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uvm_gpu_address_aperture_string(src));
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return false;
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}
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}
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return true;
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}
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// In SR-IOV heavy (GA100 only), the UVM driver is expected to push a patched
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// version of an inlined memcopy to the proxy channels. The patching consists in
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// passing the offset of the inlined data within the push as the source virtual
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// address, instead of passing its GPU VA.
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//
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// Copies pushed to internal channels use the GPU VA of the inlined data,
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// irrespective of the virtualization mode.
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void uvm_hal_ampere_ce_memcopy_patch_src_c6b5(uvm_push_t *push, uvm_gpu_address_t *src)
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{
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if (!uvm_channel_is_proxy(push->channel))
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return;
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src->address -= uvm_pushbuffer_get_gpu_va_for_push(push->channel->pool->manager->pushbuffer, push);
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}
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bool uvm_hal_ampere_ce_memset_is_valid_c6b5(uvm_push_t *push,
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uvm_gpu_address_t dst,
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size_t num_elements,
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size_t element_size)
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{
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uvm_gpu_t *gpu = uvm_push_get_gpu(push);
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if (!uvm_gpu_is_virt_mode_sriov_heavy(gpu))
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return true;
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if (uvm_channel_is_proxy(push->channel)) {
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if (dst.is_virtual) {
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UVM_ERR_PRINT("Destination address of memset must be physical, not virtual\n");
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return false;
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}
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if (dst.aperture != UVM_APERTURE_VID) {
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UVM_ERR_PRINT("Destination address of memset must be in vidmem\n");
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return false;
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}
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if (!IS_ALIGNED(dst.address, 8)){
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UVM_ERR_PRINT("Destination address of memset is not 8-byte aligned");
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return false;
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}
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// Disallow memsets that don't match the page table/directory entry
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// size. PDE0 entries are 16 bytes wide, but those are written using a
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// memcopy.
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//
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// The memset size is not checked to be a multiple of the element size
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// because the check is not exclusive of SR-IOV heavy, and it is already
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// present in the uvm_hal_*_memset_* functions.
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if (element_size != 8) {
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UVM_ERR_PRINT("Memset data must be 8 bytes wide, but found %zu instead\n", element_size);
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return false;
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}
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}
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// TODO: Bug 3429418: When in SR-IOV heavy, a memcopy/memset pushed to a
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// UVM internal channel cannot use peer physical addresses.
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else if (!dst.is_virtual && !uvm_aperture_is_peer(dst.aperture)) {
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UVM_ERR_PRINT("Destination address of memset must be virtual, not physical (aperture: %s)\n",
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uvm_gpu_address_aperture_string(dst));
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return false;
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}
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return true;
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}
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