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https://github.com/NVIDIA/open-gpu-kernel-modules.git
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107 lines
5.3 KiB
C
107 lines
5.3 KiB
C
/*******************************************************************************
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Copyright (c) 2017-2021 NVIDIA Corporation
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to
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deal in the Software without restriction, including without limitation the
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rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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sell copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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DEALINGS IN THE SOFTWARE.
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*******************************************************************************/
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#include "uvm_hal.h"
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#include "uvm_push.h"
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#include "uvm_user_channel.h"
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#include "clc46f.h"
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void uvm_hal_turing_host_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload)
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{
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NvU32 sem_lo;
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UVM_ASSERT(!(NvOffset_LO32(gpu_va) & ~HWSHIFTMASK(C46F, SEM_ADDR_LO, OFFSET)));
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sem_lo = READ_HWVALUE(NvOffset_LO32(gpu_va), C46F, SEM_ADDR_LO, OFFSET);
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uvm_hal_wfi_membar(push, uvm_push_get_and_reset_membar_flag(push));
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NV_PUSH_5U(C46F, SEM_ADDR_LO, HWVALUE(C46F, SEM_ADDR_LO, OFFSET, sem_lo),
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SEM_ADDR_HI, HWVALUE(C46F, SEM_ADDR_HI, OFFSET, NvOffset_HI32(gpu_va)),
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SEM_PAYLOAD_LO, payload,
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SEM_PAYLOAD_HI, 0,
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SEM_EXECUTE, HWCONST(C46F, SEM_EXECUTE, OPERATION, RELEASE) |
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HWCONST(C46F, SEM_EXECUTE, PAYLOAD_SIZE, 32BIT) |
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HWCONST(C46F, SEM_EXECUTE, RELEASE_TIMESTAMP, DIS) |
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HWCONST(C46F, SEM_EXECUTE, RELEASE_WFI, DIS));
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}
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void uvm_hal_turing_host_semaphore_acquire(uvm_push_t *push, NvU64 gpu_va, NvU32 payload)
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{
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NvU32 sem_lo;
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UVM_ASSERT(!(NvOffset_LO32(gpu_va) & ~HWSHIFTMASK(C46F, SEM_ADDR_LO, OFFSET)));
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sem_lo = READ_HWVALUE(NvOffset_LO32(gpu_va), C46F, SEM_ADDR_LO, OFFSET);
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NV_PUSH_5U(C46F, SEM_ADDR_LO, HWVALUE(C46F, SEM_ADDR_LO, OFFSET, sem_lo),
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SEM_ADDR_HI, HWVALUE(C46F, SEM_ADDR_HI, OFFSET, NvOffset_HI32(gpu_va)),
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SEM_PAYLOAD_LO, payload,
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SEM_PAYLOAD_HI, 0,
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SEM_EXECUTE, HWCONST(C46F, SEM_EXECUTE, OPERATION, ACQ_CIRC_GEQ) |
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HWCONST(C46F, SEM_EXECUTE, PAYLOAD_SIZE, 32BIT) |
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HWCONST(C46F, SEM_EXECUTE, ACQUIRE_SWITCH_TSG, EN));
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}
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void uvm_hal_turing_host_clear_faulted_channel_method(uvm_push_t *push,
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uvm_user_channel_t *user_channel,
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const uvm_fault_buffer_entry_t *fault)
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{
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NvU32 clear_type_value = 0;
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UVM_ASSERT(user_channel->gpu->parent->has_clear_faulted_channel_method);
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if (fault->fault_source.mmu_engine_type == UVM_MMU_ENGINE_TYPE_HOST) {
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clear_type_value = HWCONST(C46F, CLEAR_FAULTED, TYPE, PBDMA_FAULTED);
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}
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else if (fault->fault_source.mmu_engine_type == UVM_MMU_ENGINE_TYPE_CE) {
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clear_type_value = HWCONST(C46F, CLEAR_FAULTED, TYPE, ENG_FAULTED);
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}
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else {
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UVM_ASSERT_MSG(false, "Unsupported MMU engine type %s\n",
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uvm_mmu_engine_type_string(fault->fault_source.mmu_engine_type));
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}
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NV_PUSH_1U(C46F, CLEAR_FAULTED, HWVALUE(C46F, CLEAR_FAULTED, HANDLE, user_channel->clear_faulted_token) |
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clear_type_value);
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}
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// Direct copy of uvm_hal_maxwell_host_set_gpfifo_entry(). It removes
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// GP_ENTRY1_PRIV_KERNEL, which has been deprecated in Turing+.
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void uvm_hal_turing_host_set_gpfifo_entry(NvU64 *fifo_entry,
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NvU64 pushbuffer_va,
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NvU32 pushbuffer_length,
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uvm_gpfifo_sync_t sync_flag)
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{
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NvU64 fifo_entry_value;
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const NvU32 sync_value = (sync_flag == UVM_GPFIFO_SYNC_WAIT) ? HWCONST(C46F, GP_ENTRY1, SYNC, WAIT) :
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HWCONST(C46F, GP_ENTRY1, SYNC, PROCEED);
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UVM_ASSERT(!uvm_global_is_suspended());
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UVM_ASSERT_MSG(pushbuffer_va % 4 == 0, "pushbuffer va unaligned: %llu\n", pushbuffer_va);
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UVM_ASSERT_MSG(pushbuffer_length % 4 == 0, "pushbuffer length unaligned: %u\n", pushbuffer_length);
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fifo_entry_value = HWVALUE(C46F, GP_ENTRY0, GET, NvU64_LO32(pushbuffer_va) >> 2);
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fifo_entry_value |= (NvU64)(HWVALUE(C46F, GP_ENTRY1, GET_HI, NvU64_HI32(pushbuffer_va)) |
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HWVALUE(C46F, GP_ENTRY1, LENGTH, pushbuffer_length >> 2) |
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sync_value) << 32;
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*fifo_entry = fifo_entry_value;
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}
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