mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
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214 lines
9.5 KiB
C
214 lines
9.5 KiB
C
/*******************************************************************************
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Copyright (c) 2022-2023 NVIDIA Corporation
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to
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deal in the Software without restriction, including without limitation the
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rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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sell copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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DEALINGS IN THE SOFTWARE.
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*******************************************************************************/
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#include "uvm_hal.h"
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#include "uvm_hal_types.h"
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#include "uvm_push.h"
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#include "uvm_push_macros.h"
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#include "nv_uvm_types.h"
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#include "nv_uvm_interface.h"
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#include "clcba2.h"
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#include "clc86f.h"
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#include "clb06f.h"
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#define UVM_CSL_SIGN_AUTH_TAG_ALIGNMENT_BYTES (1 << HWSHIFT(CBA2, METHOD_STREAM_AUTH_TAG_ADDR_LO, DATA))
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static void sign_push(uvm_push_t *push, NvU32 *init_method, NvU8 *auth_tag)
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{
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NvU32 *sign_input_buf = push->begin + UVM_METHOD_SIZE / sizeof(*push->begin);
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NvU32 sign_size = 0;
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NV_STATUS status;
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UVM_ASSERT(init_method < push->next);
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while (init_method < push->next) {
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NvU8 subch = READ_HWVALUE(*init_method, B06F, DMA, METHOD_SUBCHANNEL);
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NvU32 count = READ_HWVALUE(*init_method, B06F, DMA, METHOD_COUNT);
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if (subch == UVM_SUBCHANNEL_CBA2) {
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NvU32 method_addr = READ_HWVALUE(*init_method, B06F, DMA, METHOD_ADDRESS) << 2;
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UVM_ASSERT(count == 1);
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UVM_ASSERT((sign_size + 2) * UVM_METHOD_SIZE <= UVM_CONF_COMPUTING_SIGN_BUF_MAX_SIZE);
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sign_input_buf[sign_size] = method_addr;
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sign_input_buf[sign_size + 1] = init_method[1];
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// We consume the method address and the method data from the input,
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// we advance the sign_input_buf by 2.
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sign_size += 2;
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}
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init_method += (count + 1);
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}
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UVM_ASSERT(sign_size > 0);
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status = nvUvmInterfaceCslSign(&push->channel->csl.ctx,
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sign_size * UVM_METHOD_SIZE,
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(NvU8 *)sign_input_buf,
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auth_tag);
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UVM_ASSERT_MSG(status == NV_OK,
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"Failure to sign method stream auth tag, err: %s, GPU: %s.\n",
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nvstatusToString(status),
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uvm_gpu_name(uvm_push_get_gpu(push)));
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}
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void uvm_hal_hopper_sec2_init(uvm_push_t *push)
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{
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// Commonly, we would push a SET_OBJECT HOPPER_SEC2_WORK_LAUNCH_A in the
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// init function. During channel initialization, this method would be sent
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// to ESCHED to notify the expected SEC2 class ID. ESCHED forwards this
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// method to the SEC2 engine. SEC2 is not guaranteed to support the
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// SET_OBJECT method, so we shouldn't submit it.
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}
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void uvm_hal_hopper_sec2_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload)
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{
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NvU32 sem_lo;
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NvU32 flush_value;
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NvU8 *sign_auth_tag_ptr;
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NvU32 sign_auth_tag_addr_lo;
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uvm_gpu_address_t sign_auth_tag_gpu_va;
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NvU32 *csl_sign_init = push->next;
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UVM_ASSERT(IS_ALIGNED(NvU64_LO32(gpu_va), 1 << HWSHIFT(CBA2, SEMAPHORE_B, LOWER)));
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sem_lo = READ_HWVALUE(NvU64_LO32(gpu_va), CBA2, SEMAPHORE_B, LOWER);
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flush_value = uvm_hal_membar_before_semaphore(push) ? HWCONST(CBA2, SEMAPHORE_D, FLUSH_DISABLE, FALSE) :
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HWCONST(CBA2, SEMAPHORE_D, FLUSH_DISABLE, TRUE);
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// The push and the method stream signature have the same lifetime, we
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// reserve space in the pushbuffer to store the signature. After the push is
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// processed by the GPU, the pushbuffer is recycled entirely, including the
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// signature buffer.
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sign_auth_tag_ptr = uvm_push_get_single_inline_buffer(push,
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UVM_CSL_SIGN_AUTH_TAG_SIZE_BYTES,
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UVM_CSL_SIGN_AUTH_TAG_ALIGNMENT_BYTES,
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&sign_auth_tag_gpu_va);
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NV_PUSH_1U(CBA2,
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METHOD_STREAM_AUTH_TAG_ADDR_HI,
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HWVALUE(CBA2, METHOD_STREAM_AUTH_TAG_ADDR_HI, DATA, NvU64_HI32(sign_auth_tag_gpu_va.address)));
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sign_auth_tag_addr_lo = READ_HWVALUE(NvU64_LO32(sign_auth_tag_gpu_va.address),
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CBA2,
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METHOD_STREAM_AUTH_TAG_ADDR_LO,
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DATA);
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NV_PUSH_1U(CBA2,
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METHOD_STREAM_AUTH_TAG_ADDR_LO,
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HWVALUE(CBA2, METHOD_STREAM_AUTH_TAG_ADDR_LO, DATA, sign_auth_tag_addr_lo));
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NV_PUSH_1U(CBA2, SEMAPHORE_A, HWVALUE(CBA2, SEMAPHORE_A, UPPER, NvU64_HI32(gpu_va)));
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NV_PUSH_1U(CBA2, SEMAPHORE_B, HWVALUE(CBA2, SEMAPHORE_B, LOWER, sem_lo));
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NV_PUSH_1U(CBA2, SET_SEMAPHORE_PAYLOAD_LOWER, payload);
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NV_PUSH_1U(CBA2, SEMAPHORE_D, HWCONST(CBA2, SEMAPHORE_D, TIMESTAMP, DISABLE) |
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HWCONST(CBA2, SEMAPHORE_D, PAYLOAD_SIZE, 32_BIT) |
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flush_value);
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sign_push(push, csl_sign_init, sign_auth_tag_ptr);
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}
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void uvm_hal_hopper_sec2_semaphore_timestamp_unsupported(uvm_push_t *push, NvU64 gpu_va)
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{
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// TODO: Bug 3804752: [uvm][HCC] Add support for Hopper SEC2 HAL in UVM.
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// Semaphore_timestamp is not implemented in the SEC2 engine yet. We will
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// add support in UVM when they become available.
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uvm_gpu_t *gpu = uvm_push_get_gpu(push);
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UVM_ASSERT_MSG(false, "SEC2 semaphore_timestamp is not supported on GPU: %s.\n", uvm_gpu_name(gpu));
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}
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static void execute_with_membar(uvm_push_t *push)
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{
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uvm_gpu_t *gpu = uvm_push_get_gpu(push);
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uvm_membar_t membar = uvm_push_get_and_reset_membar_flag(push);
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NvU32 flush_value = (membar == UVM_MEMBAR_SYS) ? HWCONST(CBA2, EXECUTE, FLUSH_DISABLE, FALSE) :
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HWCONST(CBA2, EXECUTE, FLUSH_DISABLE, TRUE);
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NV_PUSH_1U(CBA2, EXECUTE, flush_value |
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HWCONST(CBA2, EXECUTE, NOTIFY, DISABLE));
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if (membar == UVM_MEMBAR_GPU) {
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gpu->parent->host_hal->wait_for_idle(push);
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gpu->parent->host_hal->membar_gpu(push);
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}
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}
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void uvm_hal_hopper_sec2_decrypt(uvm_push_t *push, NvU64 dst_va, NvU64 src_va, NvU32 size, NvU64 auth_tag_va)
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{
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NvU8 *sign_auth_tag_ptr;
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NvU32 sign_auth_tag_addr_lo;
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uvm_gpu_address_t sign_auth_tag_gpu_va;
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NvU32 *csl_sign_init = push->next;
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// Check that the provided alignment matches HW
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BUILD_BUG_ON(UVM_CONF_COMPUTING_SEC2_BUF_ALIGNMENT != (1 << HWSHIFT(CBA2, DECRYPT_COPY_DST_ADDR_LO, DATA)));
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BUILD_BUG_ON(UVM_CONF_COMPUTING_BUF_ALIGNMENT < (1 << HWSHIFT(CBA2, DECRYPT_COPY_DST_ADDR_LO, DATA)));
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BUILD_BUG_ON(UVM_CONF_COMPUTING_BUF_ALIGNMENT % (1 << HWSHIFT(CBA2, DECRYPT_COPY_DST_ADDR_LO, DATA)) != 0);
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// No overlapping.
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UVM_ASSERT(!uvm_ranges_overlap(src_va, src_va + size - 1, dst_va, dst_va + size - 1));
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// Alignment requirements.
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UVM_ASSERT(IS_ALIGNED(NvU64_LO32(src_va), 1 << HWSHIFT(CBA2, DECRYPT_COPY_SRC_ADDR_LO, DATA)));
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UVM_ASSERT(IS_ALIGNED(NvU64_LO32(dst_va), 1 << HWSHIFT(CBA2, DECRYPT_COPY_DST_ADDR_LO, DATA)));
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UVM_ASSERT(IS_ALIGNED(NvU64_LO32(auth_tag_va), 1 << HWSHIFT(CBA2, DECRYPT_COPY_AUTH_TAG_ADDR_LO, DATA)));
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UVM_ASSERT(IS_ALIGNED(size, 1 << HWSHIFT(CBA2, DECRYPT_COPY_SIZE, DATA)));
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// See comments in SEC2 semaphore_release.
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sign_auth_tag_ptr = uvm_push_get_single_inline_buffer(push,
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UVM_CSL_SIGN_AUTH_TAG_SIZE_BYTES,
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UVM_CSL_SIGN_AUTH_TAG_ALIGNMENT_BYTES,
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&sign_auth_tag_gpu_va);
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NV_PUSH_1U(CBA2, DECRYPT_COPY_SRC_ADDR_HI, NvU64_HI32(src_va));
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NV_PUSH_1U(CBA2, DECRYPT_COPY_SRC_ADDR_LO, NvU64_LO32(src_va));
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NV_PUSH_1U(CBA2, DECRYPT_COPY_DST_ADDR_HI, NvU64_HI32(dst_va));
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NV_PUSH_1U(CBA2, DECRYPT_COPY_DST_ADDR_LO, NvU64_LO32(dst_va));
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NV_PUSH_1U(CBA2, DECRYPT_COPY_SIZE, size);
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NV_PUSH_1U(CBA2, DECRYPT_COPY_AUTH_TAG_ADDR_HI, NvU64_HI32(auth_tag_va));
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NV_PUSH_1U(CBA2, DECRYPT_COPY_AUTH_TAG_ADDR_LO, NvU64_LO32(auth_tag_va));
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NV_PUSH_1U(CBA2,
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METHOD_STREAM_AUTH_TAG_ADDR_HI,
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HWVALUE(CBA2, METHOD_STREAM_AUTH_TAG_ADDR_HI, DATA, NvU64_HI32(sign_auth_tag_gpu_va.address)));
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sign_auth_tag_addr_lo = READ_HWVALUE(NvU64_LO32(sign_auth_tag_gpu_va.address),
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CBA2,
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METHOD_STREAM_AUTH_TAG_ADDR_LO,
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DATA);
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NV_PUSH_1U(CBA2,
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METHOD_STREAM_AUTH_TAG_ADDR_LO,
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HWVALUE(CBA2, METHOD_STREAM_AUTH_TAG_ADDR_LO, DATA, sign_auth_tag_addr_lo));
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execute_with_membar(push);
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sign_push(push, csl_sign_init, sign_auth_tag_ptr);
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}
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