mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
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229 lines
9.2 KiB
C
229 lines
9.2 KiB
C
/*******************************************************************************
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Copyright (c) 2016-2021 NVIDIA Corporation
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to
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deal in the Software without restriction, including without limitation the
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rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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sell copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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DEALINGS IN THE SOFTWARE.
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*******************************************************************************/
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#include "uvm_linux.h"
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#include "uvm_global.h"
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#include "uvm_gpu.h"
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#include "uvm_hal.h"
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#include "clc365.h"
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#include "uvm_volta_fault_buffer.h"
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typedef struct {
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NvU8 bufferEntry[NVC365_NOTIFY_BUF_SIZE];
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} access_counter_buffer_entry_c365_t;
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void uvm_hal_volta_enable_access_counter_notifications(uvm_parent_gpu_t *parent_gpu)
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{
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volatile NvU32 *reg;
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NvU32 mask;
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reg = parent_gpu->access_counter_buffer_info.rm_info.pHubIntrEnSet;
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mask = parent_gpu->access_counter_buffer_info.rm_info.accessCounterMask;
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UVM_GPU_WRITE_ONCE(*reg, mask);
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}
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void uvm_hal_volta_disable_access_counter_notifications(uvm_parent_gpu_t *parent_gpu)
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{
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volatile NvU32 *reg;
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NvU32 mask;
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reg = parent_gpu->access_counter_buffer_info.rm_info.pHubIntrEnClear;
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mask = parent_gpu->access_counter_buffer_info.rm_info.accessCounterMask;
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UVM_GPU_WRITE_ONCE(*reg, mask);
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}
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void uvm_hal_volta_clear_access_counter_notifications(uvm_parent_gpu_t *parent_gpu, NvU32 get)
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{
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// No-op, this function is only used by pulse-based interrupt GPUs.
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}
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NvU32 uvm_hal_volta_access_counter_buffer_entry_size(uvm_parent_gpu_t *parent_gpu)
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{
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return NVC365_NOTIFY_BUF_SIZE;
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}
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static uvm_aperture_t get_access_counter_inst_aperture(NvU32 *access_counter_entry)
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{
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NvU32 hw_aperture_value = READ_HWVALUE_MW(access_counter_entry, C365, NOTIFY_BUF_ENTRY, INST_APERTURE);
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switch (hw_aperture_value) {
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case NVC365_NOTIFY_BUF_ENTRY_APERTURE_VID_MEM:
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return UVM_APERTURE_VID;
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case NVC365_NOTIFY_BUF_ENTRY_APERTURE_SYS_MEM_COHERENT:
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case NVC365_NOTIFY_BUF_ENTRY_APERTURE_SYS_MEM_NONCOHERENT:
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return UVM_APERTURE_SYS;
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}
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UVM_ASSERT_MSG(false, "Invalid inst aperture value: %d\n", hw_aperture_value);
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return UVM_APERTURE_MAX;
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}
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static uvm_aperture_t get_access_counter_aperture(NvU32 *access_counter_entry)
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{
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NvU32 hw_aperture_value = READ_HWVALUE_MW(access_counter_entry, C365, NOTIFY_BUF_ENTRY, APERTURE);
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NvU32 peer_id = READ_HWVALUE_MW(access_counter_entry, C365, NOTIFY_BUF_ENTRY, PEER_ID);
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switch (hw_aperture_value) {
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case NVC365_NOTIFY_BUF_ENTRY_APERTURE_VID_MEM:
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return UVM_APERTURE_VID;
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case NVC365_NOTIFY_BUF_ENTRY_APERTURE_PEER_MEM:
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return UVM_APERTURE_PEER(peer_id);
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case NVC365_NOTIFY_BUF_ENTRY_APERTURE_SYS_MEM_COHERENT:
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case NVC365_NOTIFY_BUF_ENTRY_APERTURE_SYS_MEM_NONCOHERENT:
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return UVM_APERTURE_SYS;
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}
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UVM_ASSERT_MSG(false, "Invalid aperture value: %d\n", hw_aperture_value);
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return UVM_APERTURE_MAX;
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}
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static uvm_gpu_address_t get_address(uvm_parent_gpu_t *parent_gpu, NvU32 *access_counter_entry)
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{
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NvU64 address;
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bool is_virtual;
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NvU64 addr_hi = READ_HWVALUE_MW(access_counter_entry, C365, NOTIFY_BUF_ENTRY, ADDR_HI);
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NvU64 addr_lo = READ_HWVALUE_MW(access_counter_entry, C365, NOTIFY_BUF_ENTRY, ADDR_LO);
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NvU32 addr_type_value = READ_HWVALUE_MW(access_counter_entry, C365, NOTIFY_BUF_ENTRY, ADDR_TYPE);
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address = addr_lo + (addr_hi << HWSIZE_MW(C365, NOTIFY_BUF_ENTRY, ADDR_LO));
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is_virtual = (addr_type_value == NVC365_NOTIFY_BUF_ENTRY_ADDR_TYPE_GVA);
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if (is_virtual) {
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address = uvm_parent_gpu_canonical_address(parent_gpu, address);
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return uvm_gpu_address_virtual(address);
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}
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else {
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uvm_aperture_t aperture = get_access_counter_aperture(access_counter_entry);
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UVM_ASSERT_MSG(addr_type_value == NVC365_NOTIFY_BUF_ENTRY_ADDR_TYPE_GPA,
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"Invalid address type%u\n", addr_type_value);
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return uvm_gpu_address_physical(aperture, address);
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}
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}
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static uvm_access_counter_type_t get_access_counter_type(NvU32 *access_counter_entry)
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{
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NvU32 type_value = READ_HWVALUE_MW(access_counter_entry, C365, NOTIFY_BUF_ENTRY, TYPE);
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if (type_value == NVC365_NOTIFY_BUF_ENTRY_TYPE_CPU)
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return UVM_ACCESS_COUNTER_TYPE_MOMC;
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else
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return UVM_ACCESS_COUNTER_TYPE_MIMC;
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}
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static NvU32 *get_access_counter_buffer_entry(uvm_parent_gpu_t *parent_gpu, NvU32 index)
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{
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access_counter_buffer_entry_c365_t *buffer_start;
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NvU32 *access_counter_entry;
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UVM_ASSERT(index < parent_gpu->access_counter_buffer_info.max_notifications);
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buffer_start = (access_counter_buffer_entry_c365_t *)parent_gpu->access_counter_buffer_info.rm_info.bufferAddress;
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access_counter_entry = (NvU32 *)&buffer_start[index];
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return access_counter_entry;
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}
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bool uvm_hal_volta_access_counter_buffer_entry_is_valid(uvm_parent_gpu_t *parent_gpu, NvU32 index)
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{
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NvU32 *access_counter_entry;
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bool is_valid;
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access_counter_entry = get_access_counter_buffer_entry(parent_gpu, index);
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is_valid = READ_HWVALUE_MW(access_counter_entry, C365, NOTIFY_BUF_ENTRY, VALID);
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return is_valid;
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}
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void uvm_hal_volta_access_counter_buffer_entry_clear_valid(uvm_parent_gpu_t *parent_gpu, NvU32 index)
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{
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NvU32 *access_counter_entry;
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access_counter_entry = get_access_counter_buffer_entry(parent_gpu, index);
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WRITE_HWCONST_MW(access_counter_entry, C365, NOTIFY_BUF_ENTRY, VALID, FALSE);
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}
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void uvm_hal_volta_access_counter_buffer_parse_entry(uvm_parent_gpu_t *parent_gpu,
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NvU32 index,
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uvm_access_counter_buffer_entry_t *buffer_entry)
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{
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NvU32 *access_counter_entry;
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// Valid bit must be set before this function is called
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UVM_ASSERT(uvm_hal_volta_access_counter_buffer_entry_is_valid(parent_gpu, index));
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access_counter_entry = get_access_counter_buffer_entry(parent_gpu, index);
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buffer_entry->counter_type = get_access_counter_type(access_counter_entry);
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buffer_entry->address = get_address(parent_gpu, access_counter_entry);
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if (buffer_entry->address.is_virtual) {
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NvU64 inst_hi, inst_lo;
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inst_hi = READ_HWVALUE_MW(access_counter_entry, C365, NOTIFY_BUF_ENTRY, INST_HI);
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inst_lo = READ_HWVALUE_MW(access_counter_entry, C365, NOTIFY_BUF_ENTRY, INST_LO);
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buffer_entry->virtual_info.instance_ptr.address =
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inst_lo + (inst_hi << HWSIZE_MW(C365, NOTIFY_BUF_ENTRY, INST_LO));
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// HW value contains the 4K page number. Shift to build the full address
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buffer_entry->virtual_info.instance_ptr.address <<= 12;
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buffer_entry->virtual_info.instance_ptr.aperture = get_access_counter_inst_aperture(access_counter_entry);
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buffer_entry->virtual_info.mmu_engine_id =
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READ_HWVALUE_MW(access_counter_entry, C365, NOTIFY_BUF_ENTRY, MMU_ENGINE_ID);
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// MMU engine id aligns with the fault buffer packets. Therefore, we
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// reuse the helpers to compute the MMU engine type and the VE ID from
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// the fault buffer class
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buffer_entry->virtual_info.mmu_engine_type =
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parent_gpu->arch_hal->mmu_engine_id_to_type(buffer_entry->virtual_info.mmu_engine_id);
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buffer_entry->virtual_info.ve_id =
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parent_gpu->fault_buffer_hal->get_ve_id(buffer_entry->virtual_info.mmu_engine_id,
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buffer_entry->virtual_info.mmu_engine_type);
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}
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else if (buffer_entry->counter_type == UVM_ACCESS_COUNTER_TYPE_MIMC) {
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// Ignore any set bit beyond 47 since it is the maximum physical address
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// supported by the GPU. See the definition of
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// uvm_gpu_t::dma_addressable_start for why higher bits might be set.
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const NvU64 mask_46_0 = (0x1UL << 47) - 1;
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buffer_entry->address.address &= mask_46_0;
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}
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buffer_entry->counter_value = READ_HWVALUE_MW(access_counter_entry, C365, NOTIFY_BUF_ENTRY, COUNTER_VAL);
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buffer_entry->sub_granularity = READ_HWVALUE_MW(access_counter_entry, C365, NOTIFY_BUF_ENTRY, SUB_GRANULARITY);
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buffer_entry->bank = READ_HWVALUE_MW(access_counter_entry, C365, NOTIFY_BUF_ENTRY, BANK);
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buffer_entry->tag = READ_HWVALUE_MW(access_counter_entry, C365, NOTIFY_BUF_ENTRY, NOTIFY_TAG);
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// Automatically clear valid bit for the entry in the access counter buffer
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uvm_hal_volta_access_counter_buffer_entry_clear_valid(parent_gpu, index);
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}
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