mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
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281 lines
11 KiB
C
281 lines
11 KiB
C
/*******************************************************************************
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Copyright (c) 2022 NVIDIA Corporation
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to
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deal in the Software without restriction, including without limitation the
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rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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sell copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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DEALINGS IN THE SOFTWARE.
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*******************************************************************************/
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#include "uvm_hal.h"
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#include "uvm_push.h"
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#include "clc3b5.h"
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// Return the flush type and the flush enablement.
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static NvU32 volta_get_flush_value(uvm_push_t *push)
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{
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NvU32 flush_value;
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uvm_membar_t membar = uvm_push_get_and_reset_membar_flag(push);
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if (membar == UVM_MEMBAR_NONE) {
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// No MEMBAR requested, don't use a flush.
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flush_value = HWCONST(C3B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE);
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}
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else {
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flush_value = HWCONST(C3B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE);
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if (membar == UVM_MEMBAR_GPU)
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flush_value |= HWCONST(C3B5, LAUNCH_DMA, FLUSH_TYPE, GL);
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else
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flush_value |= HWCONST(C3B5, LAUNCH_DMA, FLUSH_TYPE, SYS);
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}
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return flush_value;
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}
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void uvm_hal_volta_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload)
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{
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uvm_gpu_t *gpu = uvm_push_get_gpu(push);
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NvU32 launch_dma_plc_mode;
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NV_PUSH_3U(C3B5, SET_SEMAPHORE_A, HWVALUE(C3B5, SET_SEMAPHORE_A, UPPER, NvOffset_HI32(gpu_va)),
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SET_SEMAPHORE_B, HWVALUE(C3B5, SET_SEMAPHORE_B, LOWER, NvOffset_LO32(gpu_va)),
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SET_SEMAPHORE_PAYLOAD, payload);
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launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode();
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NV_PUSH_1U(C3B5, LAUNCH_DMA, volta_get_flush_value(push) |
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HWCONST(C3B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NONE) |
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HWCONST(C3B5, LAUNCH_DMA, SEMAPHORE_TYPE, RELEASE_ONE_WORD_SEMAPHORE) |
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launch_dma_plc_mode);
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}
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void uvm_hal_volta_ce_semaphore_reduction_inc(uvm_push_t *push, NvU64 gpu_va, NvU32 payload)
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{
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uvm_gpu_t *gpu = uvm_push_get_gpu(push);
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NvU32 launch_dma_plc_mode;
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NV_PUSH_3U(C3B5, SET_SEMAPHORE_A, HWVALUE(C3B5, SET_SEMAPHORE_A, UPPER, NvOffset_HI32(gpu_va)),
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SET_SEMAPHORE_B, HWVALUE(C3B5, SET_SEMAPHORE_B, LOWER, NvOffset_LO32(gpu_va)),
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SET_SEMAPHORE_PAYLOAD, payload);
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launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode();
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NV_PUSH_1U(C3B5, LAUNCH_DMA, volta_get_flush_value(push) |
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HWCONST(C3B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NONE) |
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HWCONST(C3B5, LAUNCH_DMA, SEMAPHORE_TYPE, RELEASE_ONE_WORD_SEMAPHORE) |
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HWCONST(C3B5, LAUNCH_DMA, SEMAPHORE_REDUCTION, INC) |
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HWCONST(C3B5, LAUNCH_DMA, SEMAPHORE_REDUCTION_SIGN, UNSIGNED) |
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HWCONST(C3B5, LAUNCH_DMA, SEMAPHORE_REDUCTION_ENABLE, TRUE) |
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launch_dma_plc_mode);
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}
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void uvm_hal_volta_ce_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va)
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{
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uvm_gpu_t *gpu;
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NvU32 launch_dma_plc_mode;
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NV_PUSH_3U(C3B5, SET_SEMAPHORE_A, HWVALUE(C3B5, SET_SEMAPHORE_A, UPPER, NvOffset_HI32(gpu_va)),
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SET_SEMAPHORE_B, HWVALUE(C3B5, SET_SEMAPHORE_B, LOWER, NvOffset_LO32(gpu_va)),
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SET_SEMAPHORE_PAYLOAD, 0xdeadbeef);
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gpu = uvm_push_get_gpu(push);
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launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode();
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NV_PUSH_1U(C3B5, LAUNCH_DMA, volta_get_flush_value(push) |
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HWCONST(C3B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NONE) |
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HWCONST(C3B5, LAUNCH_DMA, SEMAPHORE_TYPE, RELEASE_FOUR_WORD_SEMAPHORE) |
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launch_dma_plc_mode);
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}
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void uvm_hal_volta_ce_memcopy(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src, size_t size)
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{
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// If >4GB copies ever become an important use case, this function should
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// use multi-line transfers so we don't have to iterate (bug 1766588).
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static const size_t max_single_copy_size = 0xFFFFFFFF;
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uvm_gpu_t *gpu = uvm_push_get_gpu(push);
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NvU32 pipelined_value;
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NvU32 launch_dma_src_dst_type;
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NvU32 launch_dma_plc_mode;
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NvU32 flush_value = HWCONST(C3B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE);
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NvU32 copy_type_value = gpu->parent->ce_hal->memcopy_copy_type(push, dst, src);
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UVM_ASSERT_MSG(gpu->parent->ce_hal->memcopy_is_valid(push, dst, src),
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"Memcopy validation failed in channel %s, GPU %s.\n",
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push->channel->name,
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uvm_gpu_name(gpu));
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gpu->parent->ce_hal->memcopy_patch_src(push, &src);
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launch_dma_src_dst_type = gpu->parent->ce_hal->phys_mode(push, dst, src);
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launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode();
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if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED))
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pipelined_value = HWCONST(C3B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, PIPELINED);
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else
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pipelined_value = HWCONST(C3B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED);
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do {
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NvU32 copy_this_time = (NvU32)min(size, max_single_copy_size);
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// In the last operation, a flush/membar may be issued after the copy.
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if (size == copy_this_time)
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flush_value = volta_get_flush_value(push);
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gpu->parent->ce_hal->offset_in_out(push, src.address, dst.address);
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NV_PUSH_1U(C3B5, LINE_LENGTH_IN, copy_this_time);
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NV_PUSH_1U(C3B5, LAUNCH_DMA,
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HWCONST(C3B5, LAUNCH_DMA, SRC_MEMORY_LAYOUT, PITCH) |
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HWCONST(C3B5, LAUNCH_DMA, DST_MEMORY_LAYOUT, PITCH) |
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HWCONST(C3B5, LAUNCH_DMA, MULTI_LINE_ENABLE, FALSE) |
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HWCONST(C3B5, LAUNCH_DMA, REMAP_ENABLE, FALSE) |
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flush_value |
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launch_dma_src_dst_type |
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launch_dma_plc_mode |
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copy_type_value |
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pipelined_value);
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pipelined_value = HWCONST(C3B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, PIPELINED);
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dst.address += copy_this_time;
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src.address += copy_this_time;
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size -= copy_this_time;
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} while (size > 0);
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}
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static NvU32 ce_aperture(uvm_aperture_t aperture)
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{
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BUILD_BUG_ON(HWCONST(C3B5, SET_SRC_PHYS_MODE, TARGET, LOCAL_FB) !=
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HWCONST(C3B5, SET_DST_PHYS_MODE, TARGET, LOCAL_FB));
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BUILD_BUG_ON(HWCONST(C3B5, SET_SRC_PHYS_MODE, TARGET, COHERENT_SYSMEM) !=
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HWCONST(C3B5, SET_DST_PHYS_MODE, TARGET, COHERENT_SYSMEM));
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UVM_ASSERT_MSG(aperture == UVM_APERTURE_VID || aperture == UVM_APERTURE_SYS, "aperture 0x%x\n", aperture);
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if (aperture == UVM_APERTURE_SYS)
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return HWCONST(C3B5, SET_SRC_PHYS_MODE, TARGET, COHERENT_SYSMEM);
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else
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return HWCONST(C3B5, SET_SRC_PHYS_MODE, TARGET, LOCAL_FB);
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}
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static NvU32 volta_memset_push_phys_mode(uvm_push_t *push, uvm_gpu_address_t dst)
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{
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if (dst.is_virtual)
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return HWCONST(C3B5, LAUNCH_DMA, DST_TYPE, VIRTUAL);
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NV_PUSH_1U(C3B5, SET_DST_PHYS_MODE, ce_aperture(dst.aperture));
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return HWCONST(C3B5, LAUNCH_DMA, DST_TYPE, PHYSICAL);
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}
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static void memset_common(uvm_push_t *push, uvm_gpu_address_t dst, size_t size, size_t memset_element_size)
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{
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// If >4GB memsets ever become an important use case, this function should
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// use multi-line transfers so we don't have to iterate (bug 1766588).
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static const size_t max_single_memset_size = 0xFFFFFFFF;
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uvm_gpu_t *gpu = uvm_push_get_gpu(push);
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NvU32 pipelined_value;
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NvU32 launch_dma_dst_type;
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NvU32 launch_dma_plc_mode;
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NvU32 flush_value = HWCONST(C3B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE);
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UVM_ASSERT_MSG(gpu->parent->ce_hal->memset_is_valid(push, dst, size, memset_element_size),
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"Memset validation failed in channel %s, GPU %s.\n",
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push->channel->name,
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uvm_gpu_name(gpu));
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launch_dma_dst_type = volta_memset_push_phys_mode(push, dst);
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launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode();
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if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED))
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pipelined_value = HWCONST(C3B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, PIPELINED);
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else
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pipelined_value = HWCONST(C3B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED);
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do {
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NvU32 memset_this_time = (NvU32)min(size, max_single_memset_size);
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// In the last operation, a flush/membar may be issue after the memset.
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if (size == memset_this_time)
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flush_value = volta_get_flush_value(push);
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gpu->parent->ce_hal->offset_out(push, dst.address);
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NV_PUSH_1U(C3B5, LINE_LENGTH_IN, memset_this_time);
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NV_PUSH_1U(C3B5, LAUNCH_DMA,
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HWCONST(C3B5, LAUNCH_DMA, SRC_MEMORY_LAYOUT, PITCH) |
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HWCONST(C3B5, LAUNCH_DMA, DST_MEMORY_LAYOUT, PITCH) |
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HWCONST(C3B5, LAUNCH_DMA, MULTI_LINE_ENABLE, FALSE) |
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HWCONST(C3B5, LAUNCH_DMA, REMAP_ENABLE, TRUE) |
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flush_value |
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launch_dma_dst_type |
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launch_dma_plc_mode |
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pipelined_value);
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dst.address += memset_this_time * memset_element_size;
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size -= memset_this_time;
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pipelined_value = HWCONST(C3B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED);
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} while (size > 0);
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}
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void uvm_hal_volta_ce_memset_1(uvm_push_t *push, uvm_gpu_address_t dst, NvU8 value, size_t size)
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{
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NV_PUSH_2U(C3B5, SET_REMAP_CONST_B, (NvU32)value,
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SET_REMAP_COMPONENTS,
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HWCONST(C3B5, SET_REMAP_COMPONENTS, DST_X, CONST_B) |
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HWCONST(C3B5, SET_REMAP_COMPONENTS, COMPONENT_SIZE, ONE) |
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HWCONST(C3B5, SET_REMAP_COMPONENTS, NUM_DST_COMPONENTS, ONE));
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memset_common(push, dst, size, 1);
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}
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void uvm_hal_volta_ce_memset_4(uvm_push_t *push, uvm_gpu_address_t dst, NvU32 value, size_t size)
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{
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UVM_ASSERT_MSG(size % 4 == 0, "size: %zd\n", size);
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size /= 4;
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NV_PUSH_2U(C3B5, SET_REMAP_CONST_B, value,
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SET_REMAP_COMPONENTS,
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HWCONST(C3B5, SET_REMAP_COMPONENTS, DST_X, CONST_B) |
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HWCONST(C3B5, SET_REMAP_COMPONENTS, COMPONENT_SIZE, FOUR) |
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HWCONST(C3B5, SET_REMAP_COMPONENTS, NUM_DST_COMPONENTS, ONE));
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memset_common(push, dst, size, 4);
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}
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void uvm_hal_volta_ce_memset_8(uvm_push_t *push, uvm_gpu_address_t dst, NvU64 value, size_t size)
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{
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UVM_ASSERT_MSG(size % 8 == 0, "size: %zd\n", size);
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size /= 8;
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NV_PUSH_3U(C3B5, SET_REMAP_CONST_A, (NvU32)value,
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SET_REMAP_CONST_B, (NvU32)(value >> 32),
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SET_REMAP_COMPONENTS,
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HWCONST(C3B5, SET_REMAP_COMPONENTS, DST_X, CONST_A) |
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HWCONST(C3B5, SET_REMAP_COMPONENTS, DST_Y, CONST_B) |
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HWCONST(C3B5, SET_REMAP_COMPONENTS, COMPONENT_SIZE, FOUR) |
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HWCONST(C3B5, SET_REMAP_COMPONENTS, NUM_DST_COMPONENTS, TWO));
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memset_common(push, dst, size, 8);
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}
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