mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
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233 lines
9.2 KiB
C
233 lines
9.2 KiB
C
/*
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* Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _UAPI_NVIDIA_DRM_IOCTL_H_
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#define _UAPI_NVIDIA_DRM_IOCTL_H_
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#include <drm/drm.h>
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/*
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* We should do our best to keep these values constant. Any change to these will
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* be backwards incompatible with client applications that might be using them
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*/
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#define DRM_NVIDIA_GET_CRTC_CRC32 0x00
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#define DRM_NVIDIA_GEM_IMPORT_NVKMS_MEMORY 0x01
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#define DRM_NVIDIA_GEM_IMPORT_USERSPACE_MEMORY 0x02
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#define DRM_NVIDIA_GET_DEV_INFO 0x03
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#define DRM_NVIDIA_FENCE_SUPPORTED 0x04
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#define DRM_NVIDIA_FENCE_CONTEXT_CREATE 0x05
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#define DRM_NVIDIA_GEM_FENCE_ATTACH 0x06
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#define DRM_NVIDIA_GET_CLIENT_CAPABILITY 0x08
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#define DRM_NVIDIA_GEM_EXPORT_NVKMS_MEMORY 0x09
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#define DRM_NVIDIA_GEM_MAP_OFFSET 0x0a
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#define DRM_NVIDIA_GEM_ALLOC_NVKMS_MEMORY 0x0b
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#define DRM_NVIDIA_GET_CRTC_CRC32_V2 0x0c
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#define DRM_NVIDIA_GEM_EXPORT_DMABUF_MEMORY 0x0d
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#define DRM_NVIDIA_GEM_IDENTIFY_OBJECT 0x0e
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#define DRM_IOCTL_NVIDIA_GEM_IMPORT_NVKMS_MEMORY \
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DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_IMPORT_NVKMS_MEMORY), \
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struct drm_nvidia_gem_import_nvkms_memory_params)
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#define DRM_IOCTL_NVIDIA_GEM_IMPORT_USERSPACE_MEMORY \
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DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_IMPORT_USERSPACE_MEMORY), \
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struct drm_nvidia_gem_import_userspace_memory_params)
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#define DRM_IOCTL_NVIDIA_GET_DEV_INFO \
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DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_DEV_INFO), \
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struct drm_nvidia_get_dev_info_params)
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/*
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* XXX Solaris compiler has issues with DRM_IO. None of this is supported on
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* Solaris anyway, so just skip it.
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*
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* 'warning: suggest parentheses around arithmetic in operand of |'
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*/
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#if defined(NV_LINUX)
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#define DRM_IOCTL_NVIDIA_FENCE_SUPPORTED \
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DRM_IO(DRM_COMMAND_BASE + DRM_NVIDIA_FENCE_SUPPORTED)
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#else
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#define DRM_IOCTL_NVIDIA_FENCE_SUPPORTED 0
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#endif
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#define DRM_IOCTL_NVIDIA_FENCE_CONTEXT_CREATE \
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DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_FENCE_CONTEXT_CREATE), \
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struct drm_nvidia_fence_context_create_params)
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#define DRM_IOCTL_NVIDIA_GEM_FENCE_ATTACH \
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DRM_IOW((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_FENCE_ATTACH), \
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struct drm_nvidia_gem_fence_attach_params)
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#define DRM_IOCTL_NVIDIA_GET_CLIENT_CAPABILITY \
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DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CLIENT_CAPABILITY), \
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struct drm_nvidia_get_client_capability_params)
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#define DRM_IOCTL_NVIDIA_GET_CRTC_CRC32 \
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DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CRTC_CRC32), \
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struct drm_nvidia_get_crtc_crc32_params)
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#define DRM_IOCTL_NVIDIA_GET_CRTC_CRC32_V2 \
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DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CRTC_CRC32_V2), \
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struct drm_nvidia_get_crtc_crc32_v2_params)
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#define DRM_IOCTL_NVIDIA_GEM_EXPORT_NVKMS_MEMORY \
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DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_EXPORT_NVKMS_MEMORY), \
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struct drm_nvidia_gem_export_nvkms_memory_params)
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#define DRM_IOCTL_NVIDIA_GEM_MAP_OFFSET \
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DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_MAP_OFFSET), \
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struct drm_nvidia_gem_map_offset_params)
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#define DRM_IOCTL_NVIDIA_GEM_ALLOC_NVKMS_MEMORY \
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DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_ALLOC_NVKMS_MEMORY), \
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struct drm_nvidia_gem_alloc_nvkms_memory_params)
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#define DRM_IOCTL_NVIDIA_GEM_EXPORT_DMABUF_MEMORY \
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DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_EXPORT_DMABUF_MEMORY), \
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struct drm_nvidia_gem_export_dmabuf_memory_params)
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#define DRM_IOCTL_NVIDIA_GEM_IDENTIFY_OBJECT \
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DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_IDENTIFY_OBJECT), \
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struct drm_nvidia_gem_identify_object_params)
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struct drm_nvidia_gem_import_nvkms_memory_params {
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uint64_t mem_size; /* IN */
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uint64_t nvkms_params_ptr; /* IN */
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uint64_t nvkms_params_size; /* IN */
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uint32_t handle; /* OUT */
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uint32_t __pad;
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};
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struct drm_nvidia_gem_import_userspace_memory_params {
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uint64_t size; /* IN Size of memory in bytes */
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uint64_t address; /* IN Virtual address of userspace memory */
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uint32_t handle; /* OUT Handle to gem object */
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};
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struct drm_nvidia_get_dev_info_params {
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uint32_t gpu_id; /* OUT */
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uint32_t primary_index; /* OUT; the "card%d" value */
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/* See DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D definitions of these */
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uint32_t generic_page_kind; /* OUT */
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uint32_t page_kind_generation; /* OUT */
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uint32_t sector_layout; /* OUT */
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};
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struct drm_nvidia_fence_context_create_params {
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uint32_t handle; /* OUT GEM handle to fence context */
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uint32_t index; /* IN Index of semaphore to use for fencing */
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uint64_t size; /* IN Size of semaphore surface in bytes */
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/* Params for importing userspace semaphore surface */
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uint64_t import_mem_nvkms_params_ptr; /* IN */
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uint64_t import_mem_nvkms_params_size; /* IN */
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/* Params for creating software signaling event */
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uint64_t event_nvkms_params_ptr; /* IN */
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uint64_t event_nvkms_params_size; /* IN */
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};
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struct drm_nvidia_gem_fence_attach_params {
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uint32_t handle; /* IN GEM handle to attach fence to */
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uint32_t fence_context_handle; /* IN GEM handle to fence context on which fence is run on */
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uint32_t sem_thresh; /* IN Semaphore value to reach before signal */
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};
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struct drm_nvidia_get_client_capability_params {
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uint64_t capability; /* IN Client capability enum */
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uint64_t value; /* OUT Client capability value */
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};
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/* Struct that stores Crc value and if it is supported by hardware */
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struct drm_nvidia_crtc_crc32 {
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uint32_t value; /* Read value, undefined if supported is false */
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uint8_t supported; /* Supported boolean, true if readable by hardware */
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};
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struct drm_nvidia_crtc_crc32_v2_out {
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struct drm_nvidia_crtc_crc32 compositorCrc32; /* OUT compositor hardware CRC32 value */
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struct drm_nvidia_crtc_crc32 rasterGeneratorCrc32; /* OUT raster generator CRC32 value */
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struct drm_nvidia_crtc_crc32 outputCrc32; /* OUT SF/SOR CRC32 value */
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};
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struct drm_nvidia_get_crtc_crc32_v2_params {
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uint32_t crtc_id; /* IN CRTC identifier */
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struct drm_nvidia_crtc_crc32_v2_out crc32; /* OUT Crc32 output structure */
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};
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struct drm_nvidia_get_crtc_crc32_params {
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uint32_t crtc_id; /* IN CRTC identifier */
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uint32_t crc32; /* OUT CRC32 value */
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};
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struct drm_nvidia_gem_export_nvkms_memory_params {
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uint32_t handle; /* IN */
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uint32_t __pad;
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uint64_t nvkms_params_ptr; /* IN */
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uint64_t nvkms_params_size; /* IN */
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};
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struct drm_nvidia_gem_map_offset_params {
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uint32_t handle; /* IN Handle to gem object */
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uint32_t __pad;
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uint64_t offset; /* OUT Fake offset */
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};
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struct drm_nvidia_gem_alloc_nvkms_memory_params {
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uint32_t handle; /* OUT */
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uint8_t block_linear; /* IN */
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uint8_t compressible; /* IN/OUT */
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uint16_t __pad;
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uint64_t memory_size; /* IN */
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};
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struct drm_nvidia_gem_export_dmabuf_memory_params {
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uint32_t handle; /* IN GEM Handle*/
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uint32_t __pad;
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uint64_t nvkms_params_ptr; /* IN */
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uint64_t nvkms_params_size; /* IN */
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};
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typedef enum {
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NV_GEM_OBJECT_NVKMS,
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NV_GEM_OBJECT_DMABUF,
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NV_GEM_OBJECT_USERMEMORY,
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NV_GEM_OBJECT_UNKNOWN = 0x7fffffff /* Force size of 32-bits. */
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} drm_nvidia_gem_object_type;
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struct drm_nvidia_gem_identify_object_params {
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uint32_t handle; /* IN GEM handle*/
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drm_nvidia_gem_object_type object_type; /* OUT GEM object type */
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};
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#endif /* _UAPI_NVIDIA_DRM_IOCTL_H_ */
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