mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
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440 lines
15 KiB
C
440 lines
15 KiB
C
/*******************************************************************************
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Copyright (c) 2015-2020 NVIDIA Corporation
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to
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deal in the Software without restriction, including without limitation the
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rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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sell copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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DEALINGS IN THE SOFTWARE.
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*******************************************************************************/
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// For Pascal, UVM page tree 'depth' maps to hardware as follows:
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//
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// UVM depth HW level VA bits
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// 0 PDE3 48:47
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// 1 PDE2 46:38
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// 2 PDE1 37:29
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// 3 PDE0 (dual 64k/4k PDE, or 2M PTE) 28:21
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// 4 PTE_64K / PTE_4K 20:16 / 20:12
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#include "uvm_types.h"
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#include "uvm_forward_decl.h"
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#include "uvm_global.h"
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#include "uvm_gpu.h"
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#include "uvm_mmu.h"
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#include "uvm_push_macros.h"
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#include "uvm_pascal_fault_buffer.h"
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#include "hwref/pascal/gp100/dev_fault.h"
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#include "hwref/pascal/gp100/dev_fb.h"
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#include "hwref/pascal/gp100/dev_mmu.h"
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#define MMU_BIG 0
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#define MMU_SMALL 1
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static NvU32 entries_per_index_pascal(NvU32 depth)
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{
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UVM_ASSERT(depth < 5);
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if (depth == 3)
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return 2;
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return 1;
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}
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static NvLength entry_offset_pascal(NvU32 depth, NvU32 page_size)
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{
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UVM_ASSERT(depth < 5);
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if (page_size == UVM_PAGE_SIZE_4K && depth == 3)
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return MMU_SMALL;
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return MMU_BIG;
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}
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static NvU64 single_pde_pascal(uvm_mmu_page_table_alloc_t *phys_alloc)
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{
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NvU64 pde_bits = 0;
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if (phys_alloc != NULL) {
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NvU64 address = phys_alloc->addr.address >> NV_MMU_VER2_PDE_ADDRESS_SHIFT;
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pde_bits |= HWCONST64(_MMU_VER2, PDE, IS_PDE, TRUE) |
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HWCONST64(_MMU_VER2, PDE, VOL, TRUE);
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switch (phys_alloc->addr.aperture) {
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case UVM_APERTURE_SYS:
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pde_bits |= HWCONST64(_MMU_VER2, PDE, APERTURE, SYSTEM_COHERENT_MEMORY) |
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HWVALUE64(_MMU_VER2, PDE, ADDRESS_SYS, address);
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break;
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case UVM_APERTURE_VID:
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pde_bits |= HWCONST64(_MMU_VER2, PDE, APERTURE, VIDEO_MEMORY) |
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HWVALUE64(_MMU_VER2, PDE, ADDRESS_VID, address);
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break;
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default:
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UVM_ASSERT_MSG(0, "Invalid aperture: %d\n", phys_alloc->addr.aperture);
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break;
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}
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}
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return pde_bits;
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}
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static NvU64 big_half_pde_pascal(uvm_mmu_page_table_alloc_t *phys_alloc)
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{
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NvU64 pde_bits = 0;
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if (phys_alloc != NULL) {
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NvU64 address = phys_alloc->addr.address >> NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_SHIFT;
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pde_bits |= HWCONST64(_MMU_VER2, DUAL_PDE, VOL_BIG, TRUE);
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switch (phys_alloc->addr.aperture) {
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case UVM_APERTURE_SYS:
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pde_bits |= HWCONST64(_MMU_VER2, DUAL_PDE, APERTURE_BIG, SYSTEM_COHERENT_MEMORY) |
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HWVALUE64(_MMU_VER2, DUAL_PDE, ADDRESS_BIG_SYS, address);
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break;
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case UVM_APERTURE_VID:
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pde_bits |= HWCONST64(_MMU_VER2, DUAL_PDE, APERTURE_BIG, VIDEO_MEMORY) |
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HWVALUE64(_MMU_VER2, DUAL_PDE, ADDRESS_BIG_VID, address);
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break;
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default:
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UVM_ASSERT_MSG(0, "Invalid big aperture %d\n", phys_alloc->addr.aperture);
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break;
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}
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}
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return pde_bits;
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}
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static NvU64 small_half_pde_pascal(uvm_mmu_page_table_alloc_t *phys_alloc)
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{
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NvU64 pde_bits = 0;
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if (phys_alloc != NULL) {
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NvU64 address = phys_alloc->addr.address >> NV_MMU_VER2_DUAL_PDE_ADDRESS_SHIFT;
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pde_bits |= HWCONST64(_MMU_VER2, DUAL_PDE, VOL_SMALL, TRUE);
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switch (phys_alloc->addr.aperture) {
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case UVM_APERTURE_SYS:
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pde_bits |= HWCONST64(_MMU_VER2, DUAL_PDE, APERTURE_SMALL, SYSTEM_COHERENT_MEMORY);
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pde_bits |= HWVALUE64(_MMU_VER2, DUAL_PDE, ADDRESS_SMALL_SYS, address);
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break;
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case UVM_APERTURE_VID:
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pde_bits |= HWCONST64(_MMU_VER2, DUAL_PDE, APERTURE_SMALL, VIDEO_MEMORY);
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pde_bits |= HWVALUE64(_MMU_VER2, DUAL_PDE, ADDRESS_SMALL_VID, address);
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break;
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default:
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UVM_ASSERT_MSG(0, "Invalid small aperture %d\n", phys_alloc->addr.aperture);
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break;
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}
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}
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return pde_bits;
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}
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static void make_pde_pascal(void *entry, uvm_mmu_page_table_alloc_t **phys_allocs, NvU32 depth)
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{
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NvU32 entry_count = entries_per_index_pascal(depth);
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NvU64 *entry_bits = (NvU64 *)entry;
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if (entry_count == 1) {
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*entry_bits = single_pde_pascal(*phys_allocs);
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}
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else if (entry_count == 2) {
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entry_bits[MMU_BIG] = big_half_pde_pascal(phys_allocs[MMU_BIG]);
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entry_bits[MMU_SMALL] = small_half_pde_pascal(phys_allocs[MMU_SMALL]);
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// This entry applies to the whole dual PDE but is stored in the lower bits
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entry_bits[MMU_BIG] |= HWCONST64(_MMU_VER2, DUAL_PDE, IS_PDE, TRUE);
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}
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else {
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UVM_ASSERT_MSG(0, "Invalid number of entries per index: %d\n", entry_count);
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}
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}
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static NvLength entry_size_pascal(NvU32 depth)
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{
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UVM_ASSERT(depth < 5);
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if (depth == 3)
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return 16;
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else
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return 8;
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}
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static NvU32 index_bits_pascal(NvU32 depth, NvU32 page_size)
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{
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static const NvU32 bit_widths[] = {2, 9, 9, 8};
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// some code paths keep on querying this until they get a 0, meaning only the page offset remains.
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UVM_ASSERT(depth < 5);
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if (depth < 4) {
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return bit_widths[depth];
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}
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else if (depth == 4) {
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switch (page_size) {
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case UVM_PAGE_SIZE_4K:
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return 9;
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case UVM_PAGE_SIZE_64K:
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return 5;
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default:
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break;
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}
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}
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return 0;
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}
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static NvU32 num_va_bits_pascal(void)
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{
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return 49;
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}
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static NvLength allocation_size_pascal(NvU32 depth, NvU32 page_size)
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{
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UVM_ASSERT(depth < 5);
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if (depth == 4 && page_size == UVM_PAGE_SIZE_64K)
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return 256;
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// depth 0 requires only a 32 byte allocation, but it must be 4k aligned
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return 4096;
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}
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static NvU32 page_table_depth_pascal(NvU32 page_size)
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{
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if (page_size == UVM_PAGE_SIZE_2M)
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return 3;
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else
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return 4;
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}
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static NvU32 page_sizes_pascal(void)
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{
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return UVM_PAGE_SIZE_2M | UVM_PAGE_SIZE_64K | UVM_PAGE_SIZE_4K;
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}
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static NvU64 unmapped_pte_pascal(NvU32 page_size)
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{
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// Setting the privilege bit on an otherwise-zeroed big PTE causes the
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// corresponding 4k PTEs to be ignored. This allows the invalidation of a
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// mixed PDE range to be much faster.
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if (page_size != UVM_PAGE_SIZE_64K)
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return 0;
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// When VALID == 0, MMU still reads the VOL and PRIV fields. VOL == 1
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// indicates that the PTE is sparse, so make sure we don't use it.
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return HWCONST64(_MMU_VER2, PTE, VALID, FALSE) |
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HWCONST64(_MMU_VER2, PTE, VOL, FALSE) |
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HWCONST64(_MMU_VER2, PTE, PRIVILEGE, TRUE);
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}
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static NvU64 make_pte_pascal(uvm_aperture_t aperture, NvU64 address, uvm_prot_t prot, NvU64 flags)
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{
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NvU8 aperture_bits = 0;
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NvU64 pte_bits = 0;
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UVM_ASSERT(prot != UVM_PROT_NONE);
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UVM_ASSERT((flags & ~UVM_MMU_PTE_FLAGS_MASK) == 0);
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// valid 0:0
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pte_bits |= HWCONST64(_MMU_VER2, PTE, VALID, TRUE);
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// aperture 2:1
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if (aperture == UVM_APERTURE_SYS)
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aperture_bits = NV_MMU_VER2_PTE_APERTURE_SYSTEM_COHERENT_MEMORY;
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else if (aperture == UVM_APERTURE_VID)
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aperture_bits = NV_MMU_VER2_PTE_APERTURE_VIDEO_MEMORY;
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else if (aperture >= UVM_APERTURE_PEER_0 && aperture <= UVM_APERTURE_PEER_7)
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aperture_bits = NV_MMU_VER2_PTE_APERTURE_PEER_MEMORY;
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else
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UVM_ASSERT_MSG(0, "Invalid aperture: %d\n", aperture);
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pte_bits |= HWVALUE64(_MMU_VER2, PTE, APERTURE, aperture_bits);
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// volatile 3:3
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if (flags & UVM_MMU_PTE_FLAGS_CACHED)
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pte_bits |= HWCONST64(_MMU_VER2, PTE, VOL, FALSE);
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else
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pte_bits |= HWCONST64(_MMU_VER2, PTE, VOL, TRUE);
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// encrypted 4:4
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pte_bits |= HWCONST64(_MMU_VER2, PTE, ENCRYPTED, FALSE);
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// privilege 5:5
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pte_bits |= HWCONST64(_MMU_VER2, PTE, PRIVILEGE, FALSE);
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// read only 6:6
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if (prot == UVM_PROT_READ_ONLY)
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pte_bits |= HWCONST64(_MMU_VER2, PTE, READ_ONLY, TRUE);
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else
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pte_bits |= HWCONST64(_MMU_VER2, PTE, READ_ONLY, FALSE);
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// atomic disable 7:7
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if (prot == UVM_PROT_READ_WRITE_ATOMIC)
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pte_bits |= HWCONST64(_MMU_VER2, PTE, ATOMIC_DISABLE, FALSE);
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else
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pte_bits |= HWCONST64(_MMU_VER2, PTE, ATOMIC_DISABLE, TRUE);
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address >>= NV_MMU_VER2_PTE_ADDRESS_SHIFT;
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if (aperture == UVM_APERTURE_SYS) {
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// sys address 53:8
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pte_bits |= HWVALUE64(_MMU_VER2, PTE, ADDRESS_SYS, address);
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}
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else {
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// vid address 32:8
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pte_bits |= HWVALUE64(_MMU_VER2, PTE, ADDRESS_VID, address);
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// peer id 35:33
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if (aperture != UVM_APERTURE_VID)
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pte_bits |= HWVALUE64(_MMU_VER2, PTE, ADDRESS_VID_PEER, UVM_APERTURE_PEER_ID(aperture));
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// comptagline 53:36
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pte_bits |= HWVALUE64(_MMU_VER2, PTE, COMPTAGLINE, 0);
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}
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pte_bits |= HWVALUE64(_MMU_VER2, PTE, KIND, NV_MMU_PTE_KIND_PITCH);
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return pte_bits;
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}
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static NvU64 make_sked_reflected_pte_pascal(void)
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{
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NvU64 pte_bits = 0;
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pte_bits |= HWCONST64(_MMU_VER2, PTE, VALID, TRUE);
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pte_bits |= HWVALUE64(_MMU_VER2, PTE, KIND, NV_MMU_PTE_KIND_SMSKED_MESSAGE);
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return pte_bits;
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}
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static NvU64 make_sparse_pte_pascal(void)
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{
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return HWCONST64(_MMU_VER2, PTE, VALID, FALSE) |
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HWCONST64(_MMU_VER2, PTE, VOL, TRUE);
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}
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static NvU64 poisoned_pte_pascal(void)
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{
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// An invalid PTE won't be fatal from faultable units like SM, which is the
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// most likely source of bad PTE accesses.
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// Engines with priv accesses won't fault on the priv PTE, so add a backup
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// mechanism using an impossible memory address. MMU will trigger an
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// interrupt when it detects a bad physical address.
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//
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// This address has to fit within 37 bits (max address width of vidmem) and
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// be aligned to page_size.
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NvU64 phys_addr = 0x1bad000000ULL;
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NvU64 pte_bits = make_pte_pascal(UVM_APERTURE_VID, phys_addr, UVM_PROT_READ_ONLY, UVM_MMU_PTE_FLAGS_NONE);
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return WRITE_HWCONST64(pte_bits, _MMU_VER2, PTE, PRIVILEGE, TRUE);
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}
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static uvm_mmu_mode_hal_t pascal_mmu_mode_hal =
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{
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.make_pte = make_pte_pascal,
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.make_sked_reflected_pte = make_sked_reflected_pte_pascal,
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.make_sparse_pte = make_sparse_pte_pascal,
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.unmapped_pte = unmapped_pte_pascal,
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.poisoned_pte = poisoned_pte_pascal,
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.make_pde = make_pde_pascal,
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.entry_size = entry_size_pascal,
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.index_bits = index_bits_pascal,
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.entries_per_index = entries_per_index_pascal,
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.entry_offset = entry_offset_pascal,
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.num_va_bits = num_va_bits_pascal,
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.allocation_size = allocation_size_pascal,
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.page_table_depth = page_table_depth_pascal,
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.page_sizes = page_sizes_pascal
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};
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uvm_mmu_mode_hal_t *uvm_hal_mmu_mode_pascal(NvU32 big_page_size)
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{
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UVM_ASSERT(big_page_size == UVM_PAGE_SIZE_64K || big_page_size == UVM_PAGE_SIZE_128K);
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// TODO: Bug 1789555: RM should reject the creation of GPU VA spaces with
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// 128K big page size for Pascal+ GPUs
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if (big_page_size == UVM_PAGE_SIZE_128K)
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return NULL;
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return &pascal_mmu_mode_hal;
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}
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void uvm_hal_pascal_mmu_enable_prefetch_faults(uvm_parent_gpu_t *parent_gpu)
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{
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volatile NvU32 *prefetch_control;
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NvU32 prefetch_control_value;
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prefetch_control = parent_gpu->fault_buffer_info.rm_info.replayable.pPrefetchCtrl;
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prefetch_control_value = UVM_GPU_READ_ONCE(*prefetch_control);
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prefetch_control_value = WRITE_HWCONST(prefetch_control_value, _PFB_PRI_MMU_PAGE, FAULT_CTRL, PRF_FILTER, SEND_ALL);
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UVM_GPU_WRITE_ONCE(*prefetch_control, prefetch_control_value);
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}
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void uvm_hal_pascal_mmu_disable_prefetch_faults(uvm_parent_gpu_t *parent_gpu)
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{
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volatile NvU32 *prefetch_control;
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NvU32 prefetch_control_value;
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prefetch_control = parent_gpu->fault_buffer_info.rm_info.replayable.pPrefetchCtrl;
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prefetch_control_value = UVM_GPU_READ_ONCE(*prefetch_control);
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prefetch_control_value = WRITE_HWCONST(prefetch_control_value, _PFB_PRI_MMU_PAGE, FAULT_CTRL, PRF_FILTER, SEND_NONE);
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UVM_GPU_WRITE_ONCE(*prefetch_control, prefetch_control_value);
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}
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NvU16 uvm_hal_pascal_mmu_client_id_to_utlb_id(NvU16 client_id)
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{
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switch (client_id) {
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case NV_PFAULT_CLIENT_GPC_RAST:
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case NV_PFAULT_CLIENT_GPC_GCC:
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case NV_PFAULT_CLIENT_GPC_GPCCS:
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return UVM_PASCAL_GPC_UTLB_ID_RGG;
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case NV_PFAULT_CLIENT_GPC_PE_0:
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case NV_PFAULT_CLIENT_GPC_TPCCS_0:
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case NV_PFAULT_CLIENT_GPC_L1_0:
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case NV_PFAULT_CLIENT_GPC_T1_0:
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case NV_PFAULT_CLIENT_GPC_L1_1:
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case NV_PFAULT_CLIENT_GPC_T1_1:
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return UVM_PASCAL_GPC_UTLB_ID_LTP0;
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case NV_PFAULT_CLIENT_GPC_PE_1:
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case NV_PFAULT_CLIENT_GPC_TPCCS_1:
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case NV_PFAULT_CLIENT_GPC_L1_2:
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case NV_PFAULT_CLIENT_GPC_T1_2:
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case NV_PFAULT_CLIENT_GPC_L1_3:
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case NV_PFAULT_CLIENT_GPC_T1_3:
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return UVM_PASCAL_GPC_UTLB_ID_LTP1;
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case NV_PFAULT_CLIENT_GPC_PE_2:
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case NV_PFAULT_CLIENT_GPC_TPCCS_2:
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case NV_PFAULT_CLIENT_GPC_L1_4:
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case NV_PFAULT_CLIENT_GPC_T1_4:
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case NV_PFAULT_CLIENT_GPC_L1_5:
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case NV_PFAULT_CLIENT_GPC_T1_5:
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return UVM_PASCAL_GPC_UTLB_ID_LTP2;
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case NV_PFAULT_CLIENT_GPC_PE_3:
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case NV_PFAULT_CLIENT_GPC_TPCCS_3:
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case NV_PFAULT_CLIENT_GPC_L1_6:
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case NV_PFAULT_CLIENT_GPC_T1_6:
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case NV_PFAULT_CLIENT_GPC_L1_7:
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case NV_PFAULT_CLIENT_GPC_T1_7:
|
|
return UVM_PASCAL_GPC_UTLB_ID_LTP3;
|
|
case NV_PFAULT_CLIENT_GPC_PE_4:
|
|
case NV_PFAULT_CLIENT_GPC_TPCCS_4:
|
|
case NV_PFAULT_CLIENT_GPC_L1_8:
|
|
case NV_PFAULT_CLIENT_GPC_T1_8:
|
|
case NV_PFAULT_CLIENT_GPC_L1_9:
|
|
case NV_PFAULT_CLIENT_GPC_T1_9:
|
|
return UVM_PASCAL_GPC_UTLB_ID_LTP4;
|
|
default:
|
|
UVM_ASSERT_MSG(false, "Invalid client value: 0x%x\n", client_id);
|
|
}
|
|
|
|
return 0;
|
|
}
|