mirror of
https://github.com/Yours3lf/rpi-vk-driver.git
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259 lines
8.3 KiB
C
259 lines
8.3 KiB
C
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/*
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* Copyright © 2014 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef VC4_QPU_ENUMS_H
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#define VC4_QPU_ENUMS_H
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#include <assert.h>
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#include <stdint.h>
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typedef enum{
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QPU_ALU,
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QPU_SEM,
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QPU_BRANCH,
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QPU_LOAD_IMM
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} qpu_alu_type;
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typedef enum{
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QPU_LOAD32,
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QPU_LOAD16
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} qpu_load_type;
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//Condition Codes
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//The QPU keeps a set of N, Z and C flag bits per 16 SIMD element. These flags are updated based on the result
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//of the ADD ALU if the ‘sf’ bit is set. If the sf bit is set and the ADD ALU executes a NOP or its condition code was
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//NEVER, flags are set based upon the result of the MUL ALU result.
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typedef enum {
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QPU_COND_NEVER,
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QPU_COND_ALWAYS,
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QPU_COND_ZS, //set
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QPU_COND_ZC, //clear
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QPU_COND_NS,
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QPU_COND_NC,
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QPU_COND_CS,
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QPU_COND_CC,
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} qpu_cond;
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//ALU Input muxes
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//selects one register for input
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//The add_a, add_b, mul_a, and mul_b fields specify the input data for the A and B ports of the ADD and MUL
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//pipelines, respectively
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typedef enum {
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/* hardware mux values */
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QPU_MUX_R0,
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QPU_MUX_R1,
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QPU_MUX_R2,
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QPU_MUX_R3,
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QPU_MUX_R4, //special purpose, read only
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QPU_MUX_R5, //special purpose
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QPU_MUX_A,
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QPU_MUX_B,
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} qpu_mux;
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//Signaling Bits
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//The 4-bit signaling field signal is connected to the 3d pipeline and is set to indicate one of a number of
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//conditions to the 3d hardware. Values from this field are also used to encode a ‘BKPT’ instruction, and to
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//encode Branches and Load Immediate instructions.
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typedef enum {
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QPU_SIG_SW_BREAKPOINT,
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QPU_SIG_NONE,
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QPU_SIG_THREAD_SWITCH,
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QPU_SIG_PROG_END,
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QPU_SIG_WAIT_FOR_SCOREBOARD, //stall until this QPU can safely access tile buffer
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QPU_SIG_SCOREBOARD_UNLOCK,
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QPU_SIG_LAST_THREAD_SWITCH,
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QPU_SIG_COVERAGE_LOAD, //from tile buffer to r4
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QPU_SIG_COLOR_LOAD, //from tile buffer to r4
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QPU_SIG_COLOR_LOAD_END, //color load and program end
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QPU_SIG_LOAD_TMU0, //read data from TMU0 to r4
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QPU_SIG_LOAD_TMU1, //read data from TMU1 to r4
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QPU_SIG_ALPHA_MASK_LOAD, //from tile buffer to r4
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QPU_SIG_SMALL_IMM, //ALU instruction with raddr_b specifying small immediate or vector rotate
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QPU_SIG_LOAD_IMM, //load immediate instruction
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QPU_SIG_BRANCH
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} qpu_sig_bits;
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//QPU unpack values
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//(can be used to unpack from r4 too)
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typedef enum {
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QPU_UNPACK_NOP,
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QPU_UNPACK_16A, //from A reg: convert 16bit float to 32bit float, or 16bit int to 32bit int, depending on the instruction
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QPU_UNPACK_16B,
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QPU_UNPACK_8D_REP, //replicate most significant byte (alpha) across word: {a, a, a, a}
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QPU_UNPACK_8A, //convert 8bit color in range [0...1] to 32bit float or 32bit int, depending on the instruction
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QPU_UNPACK_8B,
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QPU_UNPACK_8C,
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QPU_UNPACK_8D,
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} qpu_unpack;
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//QPU pack regfile A
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typedef enum {
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QPU_PACK_A_NOP,
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QPU_PACK_A_16A, //convert to 16 bit float if float input, or to int16 (just takes least significant 16bits)
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QPU_PACK_A_16B,
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QPU_PACK_A_8888, //convert to 8bit uint (just takes least significant 8bits) and replicate across all bytes of 32bit word
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QPU_PACK_A_8A, // Convert to 8-bit unsigned int. (just takes least significant 8bits)
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QPU_PACK_A_8B,
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QPU_PACK_A_8C,
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QPU_PACK_A_8D,
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// Saturating variants of the previous instructions.
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QPU_PACK_A_32_SAT, //saturate signed 32bit number (takes into account overflow/carry flags)
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QPU_PACK_A_16A_SAT, //convert to 16bit float if float input, or int16, depending on input (with saturation)
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QPU_PACK_A_16B_SAT,
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QPU_PACK_A_8888_SAT, //convert to uint8 with saturation and replicate across all bytes of 32bit word
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QPU_PACK_A_8A_SAT, //conver to uint8 with saturation
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QPU_PACK_A_8B_SAT,
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QPU_PACK_A_8C_SAT,
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QPU_PACK_A_8D_SAT,
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} qpu_pack_a;
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//QPU pack MUL ALU values
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typedef enum {
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QPU_PACK_MUL_NOP,
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QPU_PACK_MUL_8888 = 3, // converts mul float result to 8bit color in range [0...1] and replicate across all bytes of 32bit word
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QPU_PACK_MUL_8A, // converts mul float result to 8bit color in range [0...1]
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QPU_PACK_MUL_8B,
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QPU_PACK_MUL_8C,
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QPU_PACK_MUL_8D,
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} qpu_pack_mul;
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typedef enum {
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QPU_COND_BRANCH_ALL_ZS, //all z flags set
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QPU_COND_BRANCH_ALL_ZC, //all z flags clear
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QPU_COND_BRANCH_ANY_ZS,
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QPU_COND_BRANCH_ANY_ZC,
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QPU_COND_BRANCH_ALL_NS,
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QPU_COND_BRANCH_ALL_NC,
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QPU_COND_BRANCH_ANY_NS,
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QPU_COND_BRANCH_ANY_NC,
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QPU_COND_BRANCH_ALL_CS,
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QPU_COND_BRANCH_ALL_CC,
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QPU_COND_BRANCH_ANY_CS,
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QPU_COND_BRANCH_ANY_CC,
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QPU_COND_BRANCH_ALWAYS = 15 //always execute
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} qpu_branch_cond;
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//QPU ADD instruction set
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typedef enum {
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QPU_A_NOP,
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QPU_A_FADD, //float add
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QPU_A_FSUB,
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QPU_A_FMIN,
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QPU_A_FMAX,
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QPU_A_FMINABS, //float min(abs(x))
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QPU_A_FMAXABS,
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QPU_A_FTOI, //convert float to int
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QPU_A_ITOF, //convert int to float
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QPU_A_ADD = 12, //int add
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QPU_A_SUB,
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QPU_A_SHR, //int shift right
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QPU_A_ASR, //int arithmetic shift right
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QPU_A_ROR, //int rotate right
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QPU_A_SHL, //int shift left
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QPU_A_MIN,
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QPU_A_MAX,
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QPU_A_AND,
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QPU_A_OR,
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QPU_A_XOR,
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QPU_A_NOT,
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QPU_A_CLZ, //int count leading zeroes
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QPU_A_V8ADDS = 30, //add with saturation per 8bit element
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QPU_A_V8SUBS = 31,
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} qpu_op_add;
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//QPU MUL instruction set
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typedef enum {
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QPU_M_NOP,
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QPU_M_FMUL, //float mul
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QPU_M_MUL24, //24bit int mul?
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QPU_M_V8MULD, //mul two vectors of 8bit ints in range [0...1]
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QPU_M_V8MIN,
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QPU_M_V8MAX,
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QPU_M_V8ADDS, //add two vectors of 8bit ints in range [0...1] with saturation
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QPU_M_V8SUBS,
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} qpu_op_mul;
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//read and write ops may mean different things...
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//hence two maps
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//QPU register address read map
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typedef enum {
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QPU_R_FRAG_PAYLOAD_ZW = 15, /* W for A file, Z for B file */
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/* 0-31 are the plain regfile a or b fields */
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QPU_R_UNIF = 32, //uniform read
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QPU_R_VARY = 35, //varying read
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QPU_R_ELEM_QPU = 38, //element number
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QPU_R_NOP,
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QPU_R_XY_PIXEL_COORD = 41, // X for regfile a, Y for regfile b
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QPU_R_MS_FLAGS = 42, //A reg
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QPU_R_REV_FLAG = 42, //B reg
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QPU_R_VPM = 48,
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QPU_R_VPM_LD_BUSY = 49, //load busy for reg A
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QPU_R_VPM_ST_BUSY = 49, //store busy for reg B
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QPU_R_VPM_LD_WAIT = 50, //load wait for reg A
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QPU_R_VPM_ST_WAIT = 50, //store wait for reg B
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QPU_R_MUTEX_ACQUIRE,
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} qpu_raddr;
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//QPU register address write map
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typedef enum {
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/* 0-31 are the plain regfile a or b fields */
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QPU_W_ACC0 = 32, //accumulation 0, aka r0
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QPU_W_ACC1,
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QPU_W_ACC2,
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QPU_W_ACC3,
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QPU_W_TMU_NOSWAP,
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QPU_W_ACC5, //replicate pixel0 per quad for reg A, replicate SIMD element0 for reg B
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QPU_W_HOST_INT, //host interrupt
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QPU_W_NOP,
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QPU_W_UNIFORMS_ADDRESS,
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QPU_W_QUAD_XY, // X for regfile a, Y for regfile b
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QPU_W_MS_FLAGS = 42, //A reg
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QPU_W_REV_FLAG = 42, //B reg
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QPU_W_TLB_STENCIL_SETUP = 43,
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QPU_W_TLB_Z,
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QPU_W_TLB_COLOR_MS,
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QPU_W_TLB_COLOR_ALL,
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QPU_W_TLB_ALPHA_MASK,
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QPU_W_VPM,
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QPU_W_VPMVCD_SETUP, /* LD for regfile a, ST for regfile b */
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QPU_W_VPM_ADDR, /* LD for regfile a, ST for regfile b */
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QPU_W_MUTEX_RELEASE,
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QPU_W_SFU_RECIP, //special function unit 1/x
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QPU_W_SFU_RECIPSQRT, //1/sqrt(x)
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QPU_W_SFU_EXP,
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QPU_W_SFU_LOG,
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QPU_W_TMU0_S,
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QPU_W_TMU0_T,
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QPU_W_TMU0_R,
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QPU_W_TMU0_B,
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QPU_W_TMU1_S,
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QPU_W_TMU1_T,
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QPU_W_TMU1_R,
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QPU_W_TMU1_B,
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} qpu_waddr;
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#endif /* VC4_QPU_ENUMS_H */
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