2018-05-13 16:29:43 +02:00
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#define _GNU_SOURCE
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#include "kernelInterface.h"
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2018-11-18 15:21:33 +01:00
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#include <stdatomic.h>
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atomic_int refCounter = 0;
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int controlFd = 0;
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//int renderFd = 0;
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2018-05-13 16:29:43 +02:00
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int openIoctl()
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{
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2018-11-18 15:21:33 +01:00
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if(!controlFd)
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{
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controlFd = open(DRM_IOCTL_CTRL_DEV_FILE_NAME, O_RDWR | O_CLOEXEC);
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if (controlFd < 0) {
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2019-09-07 18:41:46 +02:00
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fprintf(stderr, "Can't open device file: %s \nError: %s\n", DRM_IOCTL_CTRL_DEV_FILE_NAME, strerror(errno));
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2018-11-18 15:21:33 +01:00
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return -1;
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}
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2018-05-13 16:29:43 +02:00
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}
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2018-11-18 15:21:33 +01:00
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/*if(!renderFd)
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{
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renderFd = open(DRM_IOCTL_RENDER_DEV_FILE_NAME, O_RDWR | O_CLOEXEC);
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if (renderFd < 0) {
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printf("Can't open device file: %s \nError: %s\n", DRM_IOCTL_RENDER_DEV_FILE_NAME, strerror(errno));
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return -1;
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}
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2018-11-16 20:39:33 +01:00
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}*/
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2018-05-13 16:29:43 +02:00
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2018-11-18 15:21:33 +01:00
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++refCounter;
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return 0;
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2018-05-13 16:29:43 +02:00
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}
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2018-11-16 20:39:33 +01:00
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void closeIoctl(int fd)
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2018-05-13 16:29:43 +02:00
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{
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2018-11-18 15:21:33 +01:00
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if (--refCounter == 0)
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{
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close(fd);
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}
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2018-05-13 16:29:43 +02:00
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}
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2018-05-13 18:20:52 +02:00
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static uint32_t align(uint32_t num, uint32_t alignment)
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{
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uint32_t mod = num%alignment;
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if(!mod)
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{
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return num;
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}
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else
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{
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return num + alignment - mod;
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}
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}
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2020-02-21 00:51:59 +01:00
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int vc4_get_chip_info(int fd,
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uint32_t* technologyVersion,
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uint32_t* IDstrUINT,
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uint32_t* vpmMemorySize,
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uint32_t* hdrSupported,
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uint32_t* numSemaphores,
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uint32_t* numTMUperSlice,
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uint32_t* numQPUperSlice,
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uint32_t* numSlices,
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uint32_t* v3dRevision,
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uint32_t* tileBufferDoubleBufferModeSupported,
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uint32_t* tileBufferSize,
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uint32_t* vriMemorySize)
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2018-05-13 16:29:43 +02:00
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{
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2018-05-13 20:47:05 +02:00
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assert(fd);
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2020-02-21 00:51:59 +01:00
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assert(technologyVersion);
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assert(IDstrUINT);
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assert(vpmMemorySize);
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assert(hdrSupported);
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assert(numSemaphores);
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assert(numTMUperSlice);
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assert(numQPUperSlice);
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assert(numSlices);
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assert(v3dRevision);
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assert(tileBufferDoubleBufferModeSupported);
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assert(tileBufferSize);
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assert(vriMemorySize);
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2018-05-13 20:47:05 +02:00
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2018-05-13 20:29:47 +02:00
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struct drm_vc4_get_param ident0 = {
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.param = DRM_VC4_PARAM_V3D_IDENT0,
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};
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struct drm_vc4_get_param ident1 = {
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.param = DRM_VC4_PARAM_V3D_IDENT1,
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};
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2020-02-21 00:51:59 +01:00
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struct drm_vc4_get_param ident2 = {
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.param = DRM_VC4_PARAM_V3D_IDENT2,
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};
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2018-05-13 20:29:47 +02:00
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int ret;
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ret = drmIoctl(fd, DRM_IOCTL_VC4_GET_PARAM, &ident0);
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if (ret != 0) {
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if (errno == EINVAL) {
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/* Backwards compatibility with 2835 kernels which
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2018-05-13 16:29:43 +02:00
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* only do V3D 2.1.
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*/
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2020-02-21 00:51:59 +01:00
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return 0; //21
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2018-05-13 20:29:47 +02:00
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} else {
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2019-09-07 18:41:46 +02:00
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fprintf(stderr, "Couldn't get V3D IDENT0: %s\n",
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2018-05-13 20:29:47 +02:00
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strerror(errno));
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return 0;
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2018-05-13 16:29:43 +02:00
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}
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2018-05-13 20:29:47 +02:00
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}
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ret = drmIoctl(fd, DRM_IOCTL_VC4_GET_PARAM, &ident1);
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if (ret != 0) {
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2019-09-07 18:41:46 +02:00
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fprintf(stderr, "Couldn't get V3D IDENT1: %s\n",
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2018-05-13 20:29:47 +02:00
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strerror(errno));
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return 0;
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}
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2020-02-21 00:51:59 +01:00
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ret = drmIoctl(fd, DRM_IOCTL_VC4_GET_PARAM, &ident2);
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if (ret != 0) {
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fprintf(stderr, "Couldn't get V3D IDENT2: %s\n",
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strerror(errno));
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return 0;
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}
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2018-05-13 16:29:43 +02:00
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2020-02-21 00:51:59 +01:00
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*technologyVersion = (ident0.value >> 24) & 0xff;
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*IDstrUINT = (ident0.value >> 0) & 0x00ffffff;
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2018-05-13 16:29:43 +02:00
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2020-02-21 00:51:59 +01:00
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*vpmMemorySize = ((ident1.value >> 28) & 0xf) * 1024; //multiples of 1K
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*hdrSupported = (ident1.value >> 24) & 0xf;
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*numSemaphores = (ident1.value >> 16) & 0xff;
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*numTMUperSlice = (ident1.value >> 12) & 0xf;
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*numQPUperSlice = (ident1.value >> 8) & 0xf;
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*numSlices = (ident1.value >> 4) & 0xf;
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*v3dRevision = (ident1.value >> 0) & 0xf;
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*tileBufferDoubleBufferModeSupported = (ident2.value >> 8) & 0xf;
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*tileBufferSize = (ident2.value >> 4) & 0xf;
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*vriMemorySize = (ident2.value >> 0) & 0xf;
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uint32_t v3d_ver = (*technologyVersion) * 10 + (*v3dRevision);
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if(v3d_ver != 21 && v3d_ver != 26)
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{
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printf("v3d_ver unsupported: %u\n", v3d_ver);
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2018-05-13 20:29:47 +02:00
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return 0;
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}
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2018-05-13 16:29:43 +02:00
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2020-02-21 00:51:59 +01:00
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return 1;
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2018-05-13 16:29:43 +02:00
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}
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int vc4_has_feature(int fd, uint32_t feature)
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{
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2018-05-13 20:47:05 +02:00
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assert(fd);
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2018-05-13 20:29:47 +02:00
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struct drm_vc4_get_param p = {
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.param = feature,
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};
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int ret = drmIoctl(fd, DRM_IOCTL_VC4_GET_PARAM, &p);
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2018-05-13 16:29:43 +02:00
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2018-05-13 20:29:47 +02:00
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if (ret != 0)
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2018-08-22 22:20:29 +02:00
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{
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2019-09-07 18:41:46 +02:00
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fprintf(stderr, "Couldn't determine if VC4 has feature: %s\n", strerror(errno));
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2018-05-13 20:29:47 +02:00
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return 0;
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2018-08-22 22:20:29 +02:00
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}
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2018-05-13 16:29:43 +02:00
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2018-05-13 20:29:47 +02:00
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return p.value;
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2018-05-13 16:29:43 +02:00
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}
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int vc4_test_tiling(int fd)
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{
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2018-05-13 20:47:05 +02:00
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assert(fd);
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2018-05-13 16:29:43 +02:00
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/* Test if the kernel has GET_TILING; it will return -EINVAL if the
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* ioctl does not exist, but -ENOENT if we pass an impossible handle.
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* 0 cannot be a valid GEM object, so use that.
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*/
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struct drm_vc4_get_tiling get_tiling = {
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2018-05-13 20:29:47 +02:00
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.handle = 0x0,
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2018-05-13 16:29:43 +02:00
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};
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int ret = drmIoctl(fd, DRM_IOCTL_VC4_GET_TILING, &get_tiling);
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if (ret == -1 && errno == ENOENT)
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{
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return 1;
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}
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return 0;
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}
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2019-09-08 00:30:52 +02:00
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//TODO what is this supposed to do?
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//ask the kernel what is the buffer's tiling?
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2018-05-13 16:29:43 +02:00
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uint64_t vc4_bo_get_tiling(int fd, uint32_t bo, uint64_t mod)
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{
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2018-05-13 20:47:05 +02:00
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assert(fd);
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assert(bo);
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2018-05-13 16:29:43 +02:00
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struct drm_vc4_get_tiling get_tiling = {
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2018-05-13 20:29:47 +02:00
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.handle = bo,
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2018-05-13 16:29:43 +02:00
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};
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int ret = drmIoctl(fd, DRM_IOCTL_VC4_GET_TILING, &get_tiling);
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if (ret != 0) {
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2018-08-25 12:03:54 +02:00
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return DRM_FORMAT_MOD_LINEAR; //0
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2018-05-13 16:29:43 +02:00
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} else if (mod == DRM_FORMAT_MOD_INVALID) {
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2018-05-13 20:29:47 +02:00
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return get_tiling.modifier;
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2018-05-13 16:29:43 +02:00
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} else if (mod != get_tiling.modifier) {
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2019-09-07 18:41:46 +02:00
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fprintf(stderr, "Modifier 0x%llx vs. tiling (0x%llx) mismatch\n",
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2018-05-13 20:29:47 +02:00
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(long long)mod, get_tiling.modifier);
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2018-08-25 12:03:54 +02:00
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return -1;
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2018-05-13 16:29:43 +02:00
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}
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2018-05-13 20:47:05 +02:00
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2018-08-25 12:03:54 +02:00
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return -1;
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2018-05-13 16:29:43 +02:00
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}
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int vc4_bo_set_tiling(int fd, uint32_t bo, uint64_t mod)
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{
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2018-05-13 20:47:05 +02:00
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assert(fd);
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assert(bo);
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2018-05-13 16:29:43 +02:00
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struct drm_vc4_set_tiling set_tiling = {
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2018-05-13 20:29:47 +02:00
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.handle = bo,
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.modifier = mod,
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2018-05-13 16:29:43 +02:00
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};
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int ret = drmIoctl(fd, DRM_IOCTL_VC4_SET_TILING,
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2018-05-13 20:29:47 +02:00
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&set_tiling);
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2018-05-13 16:29:43 +02:00
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if (ret != 0)
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{
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2019-09-07 18:41:46 +02:00
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fprintf(stderr, "Couldn't set tiling: %s\n",
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2018-08-22 22:20:29 +02:00
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strerror(errno));
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2018-05-13 16:29:43 +02:00
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return 0;
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}
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return 1;
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}
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2020-02-22 20:59:19 +01:00
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uint32_t vc4_set_madvise(int fd, uint32_t bo, uint32_t needed, int hasMadvise)
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{
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assert(fd);
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assert(bo);
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//VC4_MADV_WILLNEED 0
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//VC4_MADV_DONTNEED 1
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struct drm_vc4_gem_madvise arg = {
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.handle = bo,
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.madv = !needed,
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};
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if (!hasMadvise)
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return 1;
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if (drmIoctl(fd, DRM_IOCTL_VC4_GEM_MADVISE, &arg))
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{
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fprintf(stderr, "BO madvise failed: %s\n",
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strerror(errno));
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return 0;
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}
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return arg.retained;
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}
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2018-09-09 16:45:07 +02:00
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void* vc4_bo_map_unsynchronized(int fd, uint32_t bo, uint32_t offset, uint32_t size)
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2018-05-13 16:29:43 +02:00
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{
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2018-05-13 20:47:05 +02:00
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assert(fd);
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assert(bo);
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assert(size);
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2018-05-13 20:29:47 +02:00
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int ret;
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2018-05-13 16:29:43 +02:00
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2018-05-13 20:29:47 +02:00
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//if (bo->map)
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// return bo->map;
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struct drm_vc4_mmap_bo map;
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memset(&map, 0, sizeof(map));
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map.handle = bo;
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ret = drmIoctl(fd, DRM_IOCTL_VC4_MMAP_BO, &map);
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if (ret != 0) {
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2019-09-07 18:41:46 +02:00
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fprintf(stderr, "Couldn't map unsync: %s\n", strerror(errno));
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2018-05-13 20:29:47 +02:00
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return 0;
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}
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void* mapPtr = mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_SHARED,
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2018-09-09 16:45:07 +02:00
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fd, map.offset + offset);
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2018-05-13 20:29:47 +02:00
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if (mapPtr == MAP_FAILED) {
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2019-09-07 18:41:46 +02:00
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fprintf(stderr, "mmap of bo %d (offset 0x%016llx, size %d) failed\n",
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2018-09-09 16:45:07 +02:00
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bo, (long long)map.offset + offset, size);
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2018-05-13 20:29:47 +02:00
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return 0;
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}
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//VG(VALGRIND_MALLOCLIKE_BLOCK(bo->map, bo->size, 0, false));
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2018-05-13 16:29:43 +02:00
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2018-05-13 20:29:47 +02:00
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return mapPtr;
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2018-05-13 16:29:43 +02:00
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}
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2018-09-09 16:45:07 +02:00
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void vc4_bo_unmap_unsynchronized(int fd, void* ptr, uint32_t size)
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{
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assert(fd);
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assert(ptr);
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assert(size);
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munmap(ptr, size);
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}
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2018-08-25 12:03:54 +02:00
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int vc4_bo_wait(int fd, uint32_t bo, uint64_t timeout_ns)
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2018-05-13 16:29:43 +02:00
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{
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2018-05-13 20:47:05 +02:00
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assert(fd);
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2018-08-25 12:03:54 +02:00
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assert(bo);
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2018-05-13 20:47:05 +02:00
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2018-05-13 20:29:47 +02:00
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struct drm_vc4_wait_bo wait = {
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2018-08-25 12:03:54 +02:00
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|
.handle = bo,
|
2018-05-13 16:29:43 +02:00
|
|
|
.timeout_ns = timeout_ns,
|
2018-05-13 20:29:47 +02:00
|
|
|
};
|
2018-05-13 16:29:43 +02:00
|
|
|
|
2020-05-01 20:38:13 +02:00
|
|
|
//printf("Wait for BO: %u\n", bo);
|
2018-05-13 20:47:05 +02:00
|
|
|
|
2018-08-25 12:03:54 +02:00
|
|
|
int ret = drmIoctl(fd, DRM_IOCTL_VC4_WAIT_BO, &wait);
|
2018-05-13 20:29:47 +02:00
|
|
|
if (ret) {
|
|
|
|
if (ret != -ETIME) {
|
2019-09-07 18:41:46 +02:00
|
|
|
fprintf(stderr, "BO wait failed: %s\n",
|
2018-08-22 22:20:29 +02:00
|
|
|
strerror(errno));
|
2018-05-13 18:20:52 +02:00
|
|
|
}
|
|
|
|
|
2018-05-13 20:29:47 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 1;
|
2018-05-13 18:20:52 +02:00
|
|
|
}
|
|
|
|
|
2018-10-17 21:56:13 +02:00
|
|
|
int vc4_seqno_wait(int fd, uint64_t* lastFinishedSeqno, uint64_t seqno, uint64_t* timeout_ns)
|
2018-05-13 16:29:43 +02:00
|
|
|
{
|
2018-05-13 20:47:05 +02:00
|
|
|
assert(fd);
|
2018-08-25 12:03:54 +02:00
|
|
|
assert(lastFinishedSeqno);
|
2018-10-17 21:56:13 +02:00
|
|
|
assert(timeout_ns);
|
2018-05-13 20:47:05 +02:00
|
|
|
|
2018-11-16 20:39:33 +01:00
|
|
|
if(!seqno)
|
|
|
|
return 1;
|
|
|
|
|
2018-08-25 12:03:54 +02:00
|
|
|
if (*lastFinishedSeqno >= seqno)
|
|
|
|
return 1;
|
|
|
|
|
2018-05-13 20:29:47 +02:00
|
|
|
struct drm_vc4_wait_seqno wait = {
|
|
|
|
.seqno = seqno,
|
2018-10-17 21:56:13 +02:00
|
|
|
.timeout_ns = *timeout_ns,
|
2018-05-13 20:29:47 +02:00
|
|
|
};
|
2018-05-13 20:47:05 +02:00
|
|
|
|
2020-05-01 20:38:13 +02:00
|
|
|
//printf("Wait for seqno: %llu\n", seqno);
|
2018-05-13 18:20:52 +02:00
|
|
|
|
2018-08-25 12:03:54 +02:00
|
|
|
int ret = drmIoctl(fd, DRM_IOCTL_VC4_WAIT_SEQNO, &wait);
|
2018-05-13 20:29:47 +02:00
|
|
|
if (ret) {
|
|
|
|
if (ret != -ETIME) {
|
2019-09-07 18:41:46 +02:00
|
|
|
fprintf(stderr, "Seqno wait failed: %s\n",
|
2018-08-22 22:20:29 +02:00
|
|
|
strerror(errno));
|
2020-02-24 22:45:47 +01:00
|
|
|
vc4_print_hang_state(controlFd);
|
2018-05-13 18:20:52 +02:00
|
|
|
}
|
2018-10-17 21:56:13 +02:00
|
|
|
else
|
|
|
|
{
|
|
|
|
//Timeout happened
|
2020-02-24 22:45:47 +01:00
|
|
|
vc4_print_hang_state(controlFd);
|
2018-10-17 21:56:13 +02:00
|
|
|
*timeout_ns = -1;
|
|
|
|
return -1;
|
|
|
|
}
|
2018-05-13 18:20:52 +02:00
|
|
|
|
2018-05-13 20:29:47 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-10-17 21:56:13 +02:00
|
|
|
*timeout_ns = wait.timeout_ns;
|
2018-05-13 20:29:47 +02:00
|
|
|
*lastFinishedSeqno = seqno;
|
|
|
|
return 1;
|
2018-05-13 16:29:43 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
int vc4_bo_flink(int fd, uint32_t bo, uint32_t *name)
|
|
|
|
{
|
2018-05-13 20:47:05 +02:00
|
|
|
assert(fd);
|
|
|
|
assert(bo);
|
|
|
|
assert(name);
|
|
|
|
|
2018-05-13 20:29:47 +02:00
|
|
|
struct drm_gem_flink flink = {
|
|
|
|
.handle = bo,
|
|
|
|
};
|
|
|
|
int ret = drmIoctl(fd, DRM_IOCTL_GEM_FLINK, &flink);
|
|
|
|
if (ret) {
|
2019-09-07 18:41:46 +02:00
|
|
|
fprintf(stderr, "Failed to flink bo %d: %s\n",
|
2018-05-13 20:29:47 +02:00
|
|
|
bo, strerror(errno));
|
|
|
|
//free(bo);
|
|
|
|
return 0;
|
|
|
|
}
|
2018-05-13 16:29:43 +02:00
|
|
|
|
2018-05-13 20:29:47 +02:00
|
|
|
//bo->private = false;
|
|
|
|
*name = flink.name;
|
2018-05-13 16:29:43 +02:00
|
|
|
|
2018-05-13 20:29:47 +02:00
|
|
|
return 1;
|
2018-05-13 16:29:43 +02:00
|
|
|
}
|
|
|
|
|
2019-09-08 00:30:52 +02:00
|
|
|
uint32_t getBOAlignedSize(uint32_t size, uint32_t alignment)
|
2018-09-09 16:45:07 +02:00
|
|
|
{
|
2019-09-08 00:30:52 +02:00
|
|
|
return align(size, alignment);
|
2018-09-09 16:45:07 +02:00
|
|
|
}
|
|
|
|
|
2018-05-13 16:29:43 +02:00
|
|
|
uint32_t vc4_bo_alloc_shader(int fd, const void *data, uint32_t* size)
|
|
|
|
{
|
2018-05-13 20:47:05 +02:00
|
|
|
assert(fd);
|
|
|
|
assert(data);
|
|
|
|
assert(size);
|
|
|
|
|
2018-05-13 20:29:47 +02:00
|
|
|
int ret;
|
2018-05-13 16:29:43 +02:00
|
|
|
|
2019-09-08 00:30:52 +02:00
|
|
|
//kernel only requires alignmnet to sizeof(uint64_t), not an entire page
|
|
|
|
uint32_t alignedSize = getBOAlignedSize(*size, sizeof(uint64_t));
|
2018-05-13 16:29:43 +02:00
|
|
|
|
2018-05-13 20:29:47 +02:00
|
|
|
struct drm_vc4_create_shader_bo create = {
|
2018-05-13 20:47:05 +02:00
|
|
|
.size = alignedSize,
|
2018-05-13 16:29:43 +02:00
|
|
|
.data = (uintptr_t)data,
|
2018-05-13 20:29:47 +02:00
|
|
|
};
|
2018-05-13 16:29:43 +02:00
|
|
|
|
2018-05-13 20:29:47 +02:00
|
|
|
ret = drmIoctl(fd, DRM_IOCTL_VC4_CREATE_SHADER_BO,
|
|
|
|
&create);
|
2018-05-13 16:29:43 +02:00
|
|
|
|
2018-05-13 20:29:47 +02:00
|
|
|
if (ret != 0) {
|
2019-09-07 18:41:46 +02:00
|
|
|
fprintf(stderr, "Couldn't create shader: %s\n",
|
2018-08-22 22:20:29 +02:00
|
|
|
strerror(errno));
|
2018-05-13 20:29:47 +02:00
|
|
|
return 0;
|
|
|
|
}
|
2018-05-13 16:29:43 +02:00
|
|
|
|
2018-05-13 20:29:47 +02:00
|
|
|
*size = alignedSize;
|
2018-05-13 16:29:43 +02:00
|
|
|
|
2018-05-13 20:29:47 +02:00
|
|
|
return create.handle;
|
2018-05-13 16:29:43 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t vc4_bo_open_name(int fd, uint32_t name)
|
|
|
|
{
|
2018-05-13 20:47:05 +02:00
|
|
|
assert(fd);
|
|
|
|
assert(name);
|
|
|
|
|
2018-05-13 20:29:47 +02:00
|
|
|
struct drm_gem_open o = {
|
|
|
|
.name = name
|
|
|
|
};
|
|
|
|
int ret = drmIoctl(fd, DRM_IOCTL_GEM_OPEN, &o);
|
|
|
|
if (ret) {
|
2019-09-07 18:41:46 +02:00
|
|
|
fprintf(stderr, "Failed to open bo %d: %s\n",
|
2018-05-13 20:29:47 +02:00
|
|
|
name, strerror(errno));
|
|
|
|
return 0;
|
|
|
|
}
|
2018-05-13 16:29:43 +02:00
|
|
|
|
2018-05-13 20:29:47 +02:00
|
|
|
return o.handle;
|
2018-05-13 16:29:43 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t vc4_bo_alloc(int fd, uint32_t size, const char *name)
|
|
|
|
{
|
2018-05-13 20:47:05 +02:00
|
|
|
assert(fd);
|
|
|
|
assert(size);
|
|
|
|
|
2018-05-13 20:29:47 +02:00
|
|
|
struct drm_vc4_create_bo create;
|
|
|
|
int ret;
|
2018-05-13 16:29:43 +02:00
|
|
|
|
2018-05-13 20:29:47 +02:00
|
|
|
/*bo = vc4_bo_from_cache(screen, size, name);
|
2018-05-13 16:29:43 +02:00
|
|
|
if (bo) {
|
|
|
|
if (dump_stats) {
|
|
|
|
fprintf(stderr, "Allocated %s %dkb from cache:\n",
|
|
|
|
name, size / 1024);
|
|
|
|
vc4_bo_dump_stats(screen);
|
|
|
|
}
|
|
|
|
return bo;
|
|
|
|
}*/
|
|
|
|
|
2018-05-13 20:29:47 +02:00
|
|
|
memset(&create, 0, sizeof(create));
|
2018-09-09 16:45:07 +02:00
|
|
|
create.size = size;
|
2018-05-13 16:29:43 +02:00
|
|
|
|
2018-05-13 20:29:47 +02:00
|
|
|
ret = drmIoctl(fd, DRM_IOCTL_VC4_CREATE_BO, &create);
|
|
|
|
uint32_t handle = create.handle;
|
2018-05-13 16:29:43 +02:00
|
|
|
|
2018-05-13 20:29:47 +02:00
|
|
|
if (ret != 0) {
|
2019-09-07 18:41:46 +02:00
|
|
|
fprintf(stderr, "Couldn't alloc BO: %s\n",
|
2018-08-22 22:20:29 +02:00
|
|
|
strerror(errno));
|
|
|
|
|
2018-05-13 20:29:47 +02:00
|
|
|
/*if (!list_empty(&screen->bo_cache.time_list) &&
|
2018-05-13 16:29:43 +02:00
|
|
|
!cleared_and_retried) {
|
|
|
|
cleared_and_retried = true;
|
|
|
|
vc4_bo_cache_free_all(&screen->bo_cache);
|
|
|
|
goto retry;
|
|
|
|
}
|
|
|
|
|
|
|
|
free(bo);*/
|
2018-05-13 20:29:47 +02:00
|
|
|
return 0;
|
|
|
|
}
|
2018-05-13 16:29:43 +02:00
|
|
|
|
2018-05-13 20:47:05 +02:00
|
|
|
vc4_bo_label(fd, handle, name);
|
2018-05-13 16:29:43 +02:00
|
|
|
|
2020-03-08 23:06:12 +01:00
|
|
|
//TODO debug stuff, not for release
|
|
|
|
void* ptr = vc4_bo_map(fd, handle, 0, size);
|
|
|
|
memset(ptr, 0, size);
|
|
|
|
|
2018-05-13 20:29:47 +02:00
|
|
|
return handle;
|
2018-05-13 16:29:43 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void vc4_bo_free(int fd, uint32_t bo, void* mappedAddr, uint32_t size)
|
|
|
|
{
|
2018-05-13 20:47:05 +02:00
|
|
|
assert(fd);
|
|
|
|
assert(bo);
|
|
|
|
assert(size);
|
|
|
|
|
2018-05-13 20:29:47 +02:00
|
|
|
if (mappedAddr) {
|
2018-09-09 16:45:07 +02:00
|
|
|
vc4_bo_unmap_unsynchronized(fd, mappedAddr, size);
|
2018-05-13 20:29:47 +02:00
|
|
|
//VG(VALGRIND_FREELIKE_BLOCK(bo->map, 0));
|
|
|
|
}
|
2018-05-13 16:29:43 +02:00
|
|
|
|
2018-05-13 20:29:47 +02:00
|
|
|
struct drm_gem_close c;
|
|
|
|
memset(&c, 0, sizeof(c));
|
|
|
|
c.handle = bo;
|
|
|
|
int ret = drmIoctl(fd, DRM_IOCTL_GEM_CLOSE, &c);
|
|
|
|
if (ret != 0)
|
|
|
|
{
|
2019-09-07 18:41:46 +02:00
|
|
|
fprintf(stderr, "couldn't close object %d: %s\n", bo, strerror(errno));
|
2018-05-13 20:29:47 +02:00
|
|
|
}
|
2018-05-13 16:29:43 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void vc4_bo_label(int fd, uint32_t bo, const char* name)
|
|
|
|
{
|
2018-05-13 20:47:05 +02:00
|
|
|
assert(fd);
|
|
|
|
assert(bo);
|
|
|
|
|
|
|
|
char* str = name;
|
|
|
|
if(!str) str = "";
|
|
|
|
|
2018-05-13 16:29:43 +02:00
|
|
|
//TODO don't use in release!
|
|
|
|
|
|
|
|
struct drm_vc4_label_bo label = {
|
2018-05-13 20:29:47 +02:00
|
|
|
.handle = bo,
|
2018-05-13 20:47:05 +02:00
|
|
|
.len = strlen(str),
|
|
|
|
.name = (uintptr_t)str,
|
2018-05-13 16:29:43 +02:00
|
|
|
};
|
2018-08-22 22:20:29 +02:00
|
|
|
int ret = drmIoctl(fd, DRM_IOCTL_VC4_LABEL_BO, &label);
|
|
|
|
if(ret)
|
|
|
|
{
|
2019-09-07 18:41:46 +02:00
|
|
|
fprintf(stderr, "BO label failed: %s\n",
|
2018-08-22 22:20:29 +02:00
|
|
|
strerror(errno));
|
|
|
|
}
|
2018-05-13 16:29:43 +02:00
|
|
|
}
|
2018-05-13 18:20:52 +02:00
|
|
|
|
|
|
|
int vc4_bo_get_dmabuf(int fd, uint32_t bo)
|
|
|
|
{
|
2018-05-13 20:47:05 +02:00
|
|
|
assert(fd);
|
|
|
|
assert(bo);
|
|
|
|
|
2018-05-13 20:29:47 +02:00
|
|
|
int boFd;
|
|
|
|
int ret = drmPrimeHandleToFD(fd, bo,
|
|
|
|
O_CLOEXEC, &boFd);
|
|
|
|
if (ret != 0) {
|
2019-09-07 18:41:46 +02:00
|
|
|
fprintf(stderr, "Failed to export gem bo %d to dmabuf: %s\n",
|
2018-08-22 22:20:29 +02:00
|
|
|
bo, strerror(errno));
|
2018-05-13 20:29:47 +02:00
|
|
|
return 0;
|
|
|
|
}
|
2018-05-13 18:20:52 +02:00
|
|
|
|
2018-05-13 20:29:47 +02:00
|
|
|
return boFd;
|
2018-05-13 18:20:52 +02:00
|
|
|
}
|
|
|
|
|
2018-09-09 16:45:07 +02:00
|
|
|
void* vc4_bo_map(int fd, uint32_t bo, uint32_t offset, uint32_t size)
|
2018-05-13 18:20:52 +02:00
|
|
|
{
|
2018-05-13 20:47:05 +02:00
|
|
|
assert(fd);
|
|
|
|
assert(bo);
|
|
|
|
assert(size);
|
|
|
|
|
2018-09-09 16:45:07 +02:00
|
|
|
void* map = vc4_bo_map_unsynchronized(fd, bo, offset, size);
|
2018-05-13 18:20:52 +02:00
|
|
|
|
2018-05-13 20:29:47 +02:00
|
|
|
//wait infinitely
|
|
|
|
int ok = vc4_bo_wait(fd, bo, WAIT_TIMEOUT_INFINITE);
|
|
|
|
if (!ok) {
|
2019-09-07 18:41:46 +02:00
|
|
|
fprintf(stderr, "BO wait for map failed: %s\n", strerror(errno));
|
2018-05-13 20:29:47 +02:00
|
|
|
return 0;
|
|
|
|
}
|
2018-05-13 18:20:52 +02:00
|
|
|
|
2018-05-13 20:29:47 +02:00
|
|
|
return map;
|
2018-05-13 18:20:52 +02:00
|
|
|
}
|
2018-05-13 20:28:29 +02:00
|
|
|
|
2018-05-13 20:47:05 +02:00
|
|
|
void vc4_cl_submit(int fd, struct drm_vc4_submit_cl* submit, uint64_t* lastEmittedSeqno, uint64_t* lastFinishedSeqno)
|
2018-05-13 20:28:29 +02:00
|
|
|
{
|
2018-05-13 20:47:05 +02:00
|
|
|
assert(fd);
|
|
|
|
assert(submit);
|
|
|
|
assert(lastEmittedSeqno);
|
|
|
|
assert(lastFinishedSeqno);
|
|
|
|
|
|
|
|
int ret = drmIoctl(fd, DRM_IOCTL_VC4_SUBMIT_CL, submit);
|
2018-05-13 20:29:47 +02:00
|
|
|
|
|
|
|
static int warned = 0;
|
|
|
|
if (ret && !warned) {
|
2019-09-07 18:41:46 +02:00
|
|
|
fprintf(stderr, "Draw call returned %s. "
|
2018-05-13 20:29:47 +02:00
|
|
|
"Expect corruption.\n", strerror(errno));
|
|
|
|
warned = 1;
|
2020-05-01 20:38:13 +02:00
|
|
|
assert(0);
|
2018-05-13 20:29:47 +02:00
|
|
|
} else if (!ret) {
|
2018-05-13 20:47:05 +02:00
|
|
|
*lastEmittedSeqno = submit->seqno;
|
2018-05-13 20:29:47 +02:00
|
|
|
}
|
2018-05-13 20:28:29 +02:00
|
|
|
|
2018-05-13 20:29:47 +02:00
|
|
|
if (*lastEmittedSeqno - *lastFinishedSeqno > 5) {
|
2018-10-17 21:56:13 +02:00
|
|
|
uint64_t timeout = WAIT_TIMEOUT_INFINITE;
|
2020-02-24 22:45:47 +01:00
|
|
|
//uint64_t timeout = 1000ull * 1000ull * 1000ull; //TODO waits too long...
|
2018-05-13 20:29:47 +02:00
|
|
|
if (!vc4_seqno_wait(fd,
|
2018-05-13 20:47:05 +02:00
|
|
|
lastFinishedSeqno,
|
2018-08-25 12:03:54 +02:00
|
|
|
*lastFinishedSeqno > 0 ? *lastEmittedSeqno - 5 : *lastEmittedSeqno,
|
2018-10-17 21:56:13 +02:00
|
|
|
&timeout))
|
2018-05-13 20:29:47 +02:00
|
|
|
{
|
2019-09-07 18:41:46 +02:00
|
|
|
fprintf(stderr, "Job throttling failed\n");
|
2018-05-13 20:28:29 +02:00
|
|
|
}
|
2018-05-13 20:29:47 +02:00
|
|
|
}
|
2018-05-13 20:28:29 +02:00
|
|
|
}
|
2020-02-22 20:59:19 +01:00
|
|
|
|
|
|
|
uint32_t vc4_create_perfmon(int fd, uint32_t* counters, uint32_t num_counters)
|
|
|
|
{
|
|
|
|
assert(fd);
|
|
|
|
assert(counters);
|
|
|
|
assert(num_counters > 0);
|
|
|
|
assert(num_counters <= DRM_VC4_MAX_PERF_COUNTERS);
|
|
|
|
|
|
|
|
struct drm_vc4_perfmon_create arg =
|
|
|
|
{
|
2020-02-24 20:45:11 +01:00
|
|
|
.id = 0,
|
2020-02-23 14:29:01 +01:00
|
|
|
.ncounters = num_counters,
|
2020-02-22 20:59:19 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
for(uint32_t c = 0; c < num_counters; ++c)
|
|
|
|
{
|
|
|
|
arg.events[c] = counters[c];
|
|
|
|
}
|
|
|
|
|
|
|
|
if (drmIoctl(fd, DRM_IOCTL_VC4_PERFMON_CREATE, &arg))
|
|
|
|
{
|
|
|
|
fprintf(stderr, "Perfmon create failed: %s\n",
|
|
|
|
strerror(errno));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-02-24 20:45:11 +01:00
|
|
|
if(!arg.id)
|
|
|
|
{
|
|
|
|
fprintf(stderr, "Perfmon create failed (invalid ID): %s\n",
|
|
|
|
strerror(errno));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-02-22 20:59:19 +01:00
|
|
|
return arg.id;
|
|
|
|
}
|
|
|
|
|
|
|
|
void vc4_destroy_perfmon(int fd, uint32_t id)
|
|
|
|
{
|
|
|
|
assert(fd);
|
|
|
|
assert(id);
|
|
|
|
|
|
|
|
struct drm_vc4_perfmon_destroy arg =
|
|
|
|
{
|
|
|
|
.id = id
|
|
|
|
};
|
|
|
|
|
|
|
|
if (drmIoctl(fd, DRM_IOCTL_VC4_PERFMON_DESTROY, &arg))
|
|
|
|
{
|
|
|
|
fprintf(stderr, "Perfmon destroy failed: %s\n",
|
|
|
|
strerror(errno));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Returns the values of the performance counters tracked by this
|
|
|
|
* perfmon (as an array of ncounters * u64 values).
|
|
|
|
*
|
|
|
|
* No implicit synchronization is performed, so the user has to
|
|
|
|
* guarantee that any jobs using this perfmon have already been
|
|
|
|
* completed (probably by blocking on the seqno returned by the
|
|
|
|
* last exec that used the perfmon).
|
|
|
|
*/
|
|
|
|
void vc4_perfmon_get_values(int fd, uint32_t id, void* ptr)
|
|
|
|
{
|
|
|
|
assert(fd);
|
|
|
|
assert(id);
|
|
|
|
assert(ptr);
|
|
|
|
|
|
|
|
struct drm_vc4_perfmon_get_values arg =
|
|
|
|
{
|
|
|
|
.id = id,
|
|
|
|
.values_ptr = ptr
|
|
|
|
};
|
|
|
|
|
|
|
|
if (drmIoctl(fd, DRM_IOCTL_VC4_PERFMON_GET_VALUES, &arg))
|
|
|
|
{
|
|
|
|
fprintf(stderr, "Perfmon get values failed: %s\n",
|
|
|
|
strerror(errno));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void vc4_print_hang_state(int fd)
|
|
|
|
{
|
|
|
|
assert(fd);
|
|
|
|
|
|
|
|
struct drm_vc4_get_hang_state_bo bo_states[128];
|
|
|
|
|
|
|
|
struct drm_vc4_get_hang_state arg =
|
|
|
|
{
|
|
|
|
/** Pointer to array of struct drm_vc4_get_hang_state_bo. */
|
|
|
|
.bo = bo_states,
|
|
|
|
/**
|
|
|
|
* On input, the size of the bo array. Output is the number
|
|
|
|
* of bos to be returned.
|
|
|
|
*/
|
|
|
|
.bo_count = 128
|
|
|
|
};
|
|
|
|
|
|
|
|
if (drmIoctl(fd, DRM_IOCTL_VC4_GET_HANG_STATE, &arg))
|
|
|
|
{
|
2020-02-24 22:45:47 +01:00
|
|
|
fprintf(stderr, "vc4 get hang state failed: %s\n",
|
2020-02-22 20:59:19 +01:00
|
|
|
strerror(errno));
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
fprintf(stderr, "--------------\n");
|
|
|
|
fprintf(stderr, "--------------\n");
|
|
|
|
fprintf(stderr, "GPU hang state\n");
|
|
|
|
for(uint32_t c = 0; c < arg.bo_count; ++c)
|
|
|
|
{
|
|
|
|
struct drm_vc4_get_hang_state_bo* bos = arg.bo;
|
|
|
|
fprintf(stderr, "BO: %u, Addr: %u, Size: %u\n", bos[c].handle, bos[c].paddr, bos[c].size);
|
|
|
|
}
|
|
|
|
|
|
|
|
fprintf(stderr, "Start bin: %u, Start render: %u\n", arg.start_bin, arg.start_render);
|
|
|
|
fprintf(stderr, "ct0ca: %u, ct0ea: %u\n", arg.ct0ca, arg.ct0ea);
|
|
|
|
fprintf(stderr, "ct1ca: %u, ct1ea: %u\n", arg.ct1ca, arg.ct1ea);
|
|
|
|
fprintf(stderr, "ct0cs: %u, ct1cs: %u\n", arg.ct0cs, arg.ct1cs);
|
|
|
|
fprintf(stderr, "ct0ra0: %u, ct1ra0: %u\n", arg.ct0ra0, arg.ct1ra0);
|
|
|
|
fprintf(stderr, "bpca: %u, bpcs: %u\n", arg.bpca, arg.bpcs);
|
|
|
|
fprintf(stderr, "bpoa: %u, bpos: %u\n", arg.bpoa, arg.bpos);
|
|
|
|
fprintf(stderr, "vpmbase: %u: %u\n", arg.vpmbase);
|
|
|
|
fprintf(stderr, "dbge: %u: %u\n", arg.dbge);
|
|
|
|
fprintf(stderr, "fdbgo: %u: %u\n", arg.fdbgo);
|
|
|
|
fprintf(stderr, "fdbgb: %u: %u\n", arg.fdbgb);
|
|
|
|
fprintf(stderr, "fdbgr: %u: %u\n", arg.fdbgr);
|
|
|
|
fprintf(stderr, "fdbgs: %u: %u\n", arg.fdbgs);
|
|
|
|
fprintf(stderr, "errstat: %u: %u\n", arg.errstat);
|
|
|
|
}
|
|
|
|
}
|