mirror of
https://github.com/Yours3lf/rpi-vk-driver.git
synced 2025-02-17 14:54:20 +01:00
added vertex attrib encoding, removed shader patching
This commit is contained in:
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f9ac2afe0c
commit
06382178ff
@ -148,8 +148,8 @@ uint64_t encode_alu(qpu_sig_bits sig_bits,
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uint8_t write_swap_flag, //0: add writes to A, mul to B, 1: add writes to B, mul to A
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qpu_waddr waddr_add,
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qpu_waddr waddr_mul,
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qpu_op_mul op_mul,
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qpu_op_add op_add,
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qpu_op_mul op_mul,
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qpu_raddr raddr_a,
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qpu_raddr raddr_b,
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qpu_mux add_a,
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@ -227,8 +227,8 @@ uint64_t encode_alu_small_imm(qpu_unpack unpack_mode,
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uint8_t write_swap_flag, //0: add writes to A, mul to B, 1: add writes to B, mul to A
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qpu_waddr waddr_add,
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qpu_waddr waddr_mul,
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qpu_op_mul op_mul,
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qpu_op_add op_add,
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qpu_op_mul op_mul,
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qpu_raddr raddr_a,
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uint8_t small_imm,
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qpu_mux add_a,
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@ -247,8 +247,8 @@ uint64_t encode_alu_small_imm(qpu_unpack unpack_mode,
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write_swap_flag,
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waddr_add,
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waddr_mul,
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op_mul,
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op_add,
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op_mul,
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raddr_a,
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small_imm,
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add_a,
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@ -1067,11 +1067,11 @@ void assemble_qpu_asm(char* str, uint64_t* instructions)
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{
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if(sig_bit == QPU_SIG_SMALL_IMM)
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{
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instructions[instruction_counter] = encode_alu_small_imm(unpack_mode, pack_unpack_select, pack_mode, cond_add, cond_mul, sf, ws, waddr_add, waddr_mul, op_mul, op_add, raddr_a, raddr_b, add_a, add_b, mul_a, mul_b);
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instructions[instruction_counter] = encode_alu_small_imm(unpack_mode, pack_unpack_select, pack_mode, cond_add, cond_mul, sf, ws, waddr_add, waddr_mul, op_add, op_mul, raddr_a, raddr_b, add_a, add_b, mul_a, mul_b);
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}
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else
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{
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instructions[instruction_counter] = encode_alu(sig_bit, unpack_mode, pack_unpack_select, pack_mode, cond_add, cond_mul, sf, ws, waddr_add, waddr_mul, op_mul, op_add, raddr_a, raddr_b, add_a, add_b, mul_a, mul_b);
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instructions[instruction_counter] = encode_alu(sig_bit, unpack_mode, pack_unpack_select, pack_mode, cond_add, cond_mul, sf, ws, waddr_add, waddr_mul, op_add, op_mul, raddr_a, raddr_b, add_a, add_b, mul_a, mul_b);
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}
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}
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else if(type == QPU_SEM)
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@ -20,8 +20,8 @@ uint64_t encode_alu(qpu_sig_bits sig_bits,
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uint8_t write_swap_flag, //0: add writes to A, mul to B, 1: add writes to B, mul to A
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qpu_waddr waddr_add,
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qpu_waddr waddr_mul,
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qpu_op_mul op_mul,
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qpu_op_add op_add,
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qpu_op_mul op_mul,
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qpu_raddr raddr_a,
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qpu_raddr raddr_b,
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qpu_mux add_a,
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@ -38,8 +38,8 @@ uint64_t encode_alu_small_imm(qpu_unpack unpack_mode,
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uint8_t write_swap_flag, //0: add writes to A, mul to B, 1: add writes to B, mul to A
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qpu_waddr waddr_add,
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qpu_waddr waddr_mul,
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qpu_op_mul op_mul,
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qpu_op_add op_add,
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qpu_op_mul op_mul,
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qpu_raddr raddr_a,
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uint8_t small_imm,
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qpu_mux add_a,
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@ -782,6 +782,25 @@ void encodeStencilValue(uint32_t *values, uint32_t* numValues, VkStencilOpState
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}
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}
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uint32_t encodeVPMSetup(uint8_t stride,
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uint8_t direction, //0 vertical, 1 horizontal
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uint8_t isLaned, //0 packed, 1 laned
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uint8_t size, //0 8bit, 1 16bit, 2 32bit
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uint8_t address, //see doc
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uint8_t vectorComponentsToRead //only used for VPM read setup
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)
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{
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uint32_t res = 0;
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res |= ((uint32_t)(vectorComponentsToRead) & 0xf) << 20;
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res |= ((uint32_t)(stride) & 0x3f) << 12;
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res |= ((uint32_t)(direction) & 0x1) << 11;
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res |= ((uint32_t)(isLaned) & 0x1) << 10;
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res |= ((uint32_t)(size) & 0x3) << 8;
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res |= (uint32_t)(address) & 0xff;
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return res;
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}
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uint8_t getTextureDataType(VkFormat format)
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{
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switch(format)
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@ -494,6 +494,12 @@ void encodeTextureUniform(uint32_t* params,
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uint8_t wrapS,
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uint8_t noAutoLod);
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void encodeStencilValue(uint32_t* values, uint32_t* numValues, VkStencilOpState front, VkStencilOpState back, uint8_t stencilTestEnable);
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uint32_t encodeVPMSetup(uint8_t stride,
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uint8_t direction,
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uint8_t isLaned,
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uint8_t size,
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uint8_t address,
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uint8_t vectorComponentsToRead);
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uint8_t getTextureDataType(VkFormat format);
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uint8_t getMinFilterType(VkFilter minFilter, VkSamplerMipmapMode mipFilter, float maxLod);
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uint8_t getWrapMode(VkSamplerAddressMode mode);
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@ -47,13 +47,13 @@ void patchShaderDepthStencilBlending(uint64_t** instructions, uint32_t* size, co
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for(uint32_t c = 0; c < numValues; ++c)
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{
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tmp[c] = encode_load_imm(0, 0, 1, 0, 0, 0, 32 + c, 39, values[c]); //r0 = load32.always(values[c])
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tmp[numValues + c] = encode_alu(1, 0, 0, 0, 1, 0, 0, 0, 43, 39, 0, 21, 0, 0, c, c, 0, 0); //tlb_stencil_setup = or.always(r0, r0)
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tmp[numValues + c] = encode_alu(1, 0, 0, 0, 1, 0, 0, 0, 43, 39, 21, 0, 0, 0, c, c, 0, 0); //tlb_stencil_setup = or.always(r0, r0)
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}
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///"sig_none ; tlb_z = or.always(b, b, nop, rb15) ; nop = nop(r0, r0) ;"
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if(dsi->depthWriteEnable || dsi->stencilTestEnable)
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{
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tmp[numValues*2] = encode_alu(1, 0, 0, 0, 1, 0, 0, 0, 44, 39, 0, 21, 0, 15, 7, 7, 0, 0);
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tmp[numValues*2] = encode_alu(1, 0, 0, 0, 1, 0, 0, 0, 44, 39, 21, 0, 0, 15, 7, 7, 0, 0);
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}
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@ -63,14 +63,18 @@ void patchShaderDepthStencilBlending(uint64_t** instructions, uint32_t* size, co
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if(bas->blendEnable)
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{
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/// find last instruction that wrote to tlb_color_all
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/// patch shader so that r0 will contain whatever would be written to tlb_color_all
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/// r0 contains sRGBA
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//"sig_none ; r0 = or.always(a, a, uni, nop) ; nop = nop(r0, r0) ;"
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uint64_t instruction;
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/// load dRGBA to r1
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/// load tbl color dRGBA to r4
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//"sig_color_load ; nop = nop(r0, r0) ; nop = nop(r0, r0) ;"
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//"sig_none ; nop = nop(r0, r0) ; r1 = v8min.always(r4, r4) ;"
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assemble_qpu_asm("sig_color_load ; nop = nop(r0, r0) ; nop = nop(r0, r0) ;", &instruction);
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assemble_qpu_asm("sig_none ; r1 = or.always(r4, r4) ; nop = nop(r0, r0) ;", &instruction);
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//if factors are not separate
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if(bas->srcAlphaBlendFactor == bas->srcColorBlendFactor &&
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@ -79,132 +83,60 @@ void patchShaderDepthStencilBlending(uint64_t** instructions, uint32_t* size, co
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switch(bas->srcAlphaBlendFactor)
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{
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case VK_BLEND_FACTOR_ZERO:
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/// if Sfactor is ZERO
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//"sig_small_imm ; r2 = or.always(b, b, nop, 0) ; nop = nop(r0, r0) ;"
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assemble_qpu_asm("sig_small_imm ; r2 = or.always(b, b, nop, 0) ; nop = nop(r0, r0) ;", &instruction);
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break;
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case VK_BLEND_FACTOR_ONE:
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/// if Sfactor is ONE
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//"sig_small_imm ; r2 = or.always(b, b, nop, -1) ; nop = nop(r0, r0) ;"
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assemble_qpu_asm("sig_small_imm ; r2 = or.always(b, b, nop, -1) ; nop = nop(r0, r0) ;", &instruction);
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break;
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case VK_BLEND_FACTOR_SRC_COLOR:
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/// if Sfactor is sCOLOR
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//"sig_none ; r2 = or.always(r0, r0) ; nop = nop(r0, r0) ;"
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assemble_qpu_asm("sig_none ; r2 = or.always(r0, r0) ; nop = nop(r0, r0) ;", &instruction);
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break;
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case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
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/// if Sfactor is 1-sCOLOR
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//"sig_none ; r2 = not.always(r0, r0) ; nop = nop(r0, r0) ;"
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assemble_qpu_asm("sig_none ; r2 = not.always(r0, r0) ; nop = nop(r0, r0) ;", &instruction);
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break;
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case VK_BLEND_FACTOR_DST_COLOR:
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/// if Sfactor is dCOLOR
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//"sig_none ; r2 = or.always(r1, r1) ; nop = nop(r0, r0) ;"
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assemble_qpu_asm("sig_none ; r2 = or.always(r1, r1) ; nop = nop(r0, r0) ;", &instruction);
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break;
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case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
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/// if Sfactor is 1-dCOLOR
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//"sig_none ; r2 = not.always(r1, r1) ; nop = nop(r0, r0) ;"
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assemble_qpu_asm("sig_none ; r2 = not.always(r1, r1) ; nop = nop(r0, r0) ;", &instruction);
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break;
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case VK_BLEND_FACTOR_SRC_ALPHA:
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/// if Sfactor is sALPHA
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//"sig_none ; r2.8888 = or.always.8d(r0, r0) ; nop = nop(r0, r0) ;"
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assemble_qpu_asm("sig_none ; r2.8888 = or.always.8d(r0, r0) ; nop = nop(r0, r0) ;", &instruction);
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break;
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case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
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/// if Sfactor is 1-sALPHA
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//"sig_none ; r2.8888 = or.always.8d(r0, r0) ; nop = nop(r0, r0) ;"
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//"sig_none ; r2 = not.always(r2, r2) ; nop = nop(r0, r0) ;"
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assemble_qpu_asm("sig_none ; r2.8888 = or.always.8d(r0, r0) ; nop = nop(r0, r0) ;", &instruction);
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assemble_qpu_asm("sig_none ; r2 = not.always(r2, r2) ; nop = nop(r0, r0) ;", &instruction);
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case VK_BLEND_FACTOR_DST_ALPHA:
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/// if Sfactor is dALPHA
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//"sig_none ; r2.8888 = or.always.8d(r1, r1) ; nop = nop(r0, r0) ;"
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assemble_qpu_asm("sig_none ; r2.8888 = or.always.8d(r1, r1) ; nop = nop(r0, r0) ;", &instruction);
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break;
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case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
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/// if Sfactor is 1-dALPHA
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//"sig_none ; r2.8888 = or.always.8d(r1, r1) ; nop = nop(r0, r0) ;"
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//"sig_none ; r2 = not.always(r2, r2) ; nop = nop(r0, r0) ;"
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assemble_qpu_asm("sig_none ; r2.8888 = or.always.8d(r1, r1) ; nop = nop(r0, r0) ;", &instruction);
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assemble_qpu_asm("sig_none ; r2 = not.always(r2, r2) ; nop = nop(r0, r0) ;", &instruction);
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break;
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case VK_BLEND_FACTOR_CONSTANT_COLOR:
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case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
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case VK_BLEND_FACTOR_CONSTANT_ALPHA:
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case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
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/// if Sfactor is cCOLOR, 1-cCOLOR, cALPHA, 1-cALPHA = 0xffffffff
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//"sig_load_imm ; r2 = load32.always(0xffffffff) ; nop = load32() ;"
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assemble_qpu_asm("sig_load_imm ; r2 = load32.always(0xffffffff) ; nop = load32() ;", &instruction);
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break;
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case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
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/// if Sfactor is sALPHASat
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//"sig_none ; r2.8888 = or.always.8d(r0, r0) ; nop = nop(r0, r0) ;" //sAAAA
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//"sig_none ; r3.8888 = or.always.8d(r1, r1) ; nop = nop(r0, r0) ;" //dAAAA
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//"sig_none ; r3 = not.always(r3, r3) ; nop = nop(r0, r0) ;" //1-dAAAA
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//"sig_none ; nop = nop(r0, r0) ; r2 = v8min.always(r2, r3) ;" //min(sAAAA, 1-dAAAA)
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//"sig_load_imm ; r3 = load32.always(0xff000000) ; nop = load32() ;" //load alpha = 1
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//"sig_small_imm ; r2 = or.always(r2, r3) ; nop = nop(r0, r0) ;" //set alpha to 1
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assemble_qpu_asm("sig_none ; r2.8888 = or.always.8d(r0, r0) ; nop = nop(r0, r0) ;", &instruction); //sAAAA
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assemble_qpu_asm("sig_none ; r3.8888 = or.always.8d(r1, r1) ; nop = nop(r0, r0) ;", &instruction); //dAAAA
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assemble_qpu_asm("sig_none ; r3 = not.always(r3, r3) ; nop = nop(r0, r0) ;", &instruction); //1-dAAAA
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assemble_qpu_asm("sig_none ; nop = nop(r0, r0) ; r2 = v8min.always(r2, r3) ;", &instruction); //min(sAAAA, 1-dAAAA)
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assemble_qpu_asm("sig_load_imm ; r3 = load32.always(0xff000000) ; nop = load32() ;", &instruction); //load alpha = 1
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assemble_qpu_asm("sig_small_imm ; r2 = or.always(r2, r3) ; nop = nop(r0, r0) ;", &instruction); //set alpha to 1
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break;
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}
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/// Multiply sRGBA and source factor
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//"sig_none ; nop = nop(r0, r0) ; r0 = v8muld.always(r0, r2) ;"
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assemble_qpu_asm("sig_none ; nop = nop(r0, r0) ; r0 = v8muld.always(r0, r2) ;", &instruction);
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switch(bas->dstAlphaBlendFactor)
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{
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case VK_BLEND_FACTOR_ZERO:
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/// if Dfactor is ZERO
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//"sig_small_imm ; r2 = or.always(b, b, nop, 0) ; nop = nop(r0, r0) ;"
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break;
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case VK_BLEND_FACTOR_ONE:
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/// if Dfactor is ONE
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//"sig_small_imm ; r2 = or.always(b, b, nop, -1) ; nop = nop(r0, r0) ;"
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break;
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case VK_BLEND_FACTOR_SRC_COLOR:
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/// if Dfactor is sCOLOR
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//"sig_none ; r2 = or.always(r0, r0) ; nop = nop(r0, r0) ;"
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break;
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case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
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/// if Dfactor is 1-sCOLOR
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//"sig_none ; r2 = not.always(r0, r0) ; nop = nop(r0, r0) ;"
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break;
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case VK_BLEND_FACTOR_DST_COLOR:
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/// if Dfactor is dCOLOR
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//"sig_none ; r2 = or.always(r1, r1) ; nop = nop(r0, r0) ;"
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break;
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case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
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/// if Dfactor is 1-dCOLOR
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//"sig_none ; r2 = not.always(r1, r1) ; nop = nop(r0, r0) ;"
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break;
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case VK_BLEND_FACTOR_SRC_ALPHA:
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/// if Dfactor is sALPHA
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//"sig_none ; r2.8888 = or.always.8d(r0, r0) ; nop = nop(r0, r0) ;"
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break;
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case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
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/// if Dfactor is 1-sALPHA
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//"sig_none ; r2.8888 = or.always.8d(r0, r0) ; nop = nop(r0, r0) ;"
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//"sig_none ; r2 = not.always(r2, r2) ; nop = nop(r0, r0) ;"
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case VK_BLEND_FACTOR_DST_ALPHA:
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/// if Dfactor is dALPHA
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//"sig_none ; r2.8888 = or.always.8d(r1, r1) ; nop = nop(r0, r0) ;"
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break;
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case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
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/// if Dfactor is 1-dALPHA
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//"sig_none ; r2.8888 = or.always.8d(r1, r1) ; nop = nop(r0, r0) ;"
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//"sig_none ; r2 = not.always(r2, r2) ; nop = nop(r0, r0) ;"
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break;
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case VK_BLEND_FACTOR_CONSTANT_COLOR:
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case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
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case VK_BLEND_FACTOR_CONSTANT_ALPHA:
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case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
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/// if Dfactor is cCOLOR, 1-cCOLOR, cALPHA, 1-cALPHA = 0xffffffff
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//"sig_load_imm ; r2 = load32.always(0xffffffff) ; nop = load32() ;"
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break;
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case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
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/// if Dfactor is sALPHASat
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//"sig_none ; r2.8888 = or.always.8d(r0, r0) ; nop = nop(r0, r0) ;" //sAAAA
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//"sig_none ; r3.8888 = or.always.8d(r1, r1) ; nop = nop(r0, r0) ;" //dAAAA
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//"sig_none ; r3 = not.always(r3, r3) ; nop = nop(r0, r0) ;" //1-dAAAA
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//"sig_none ; nop = nop(r0, r0) ; r2 = v8min.always(r2, r3) ;" //min(sAAAA, 1-dAAAA)
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//"sig_load_imm ; r3 = load32.always(0xff000000) ; nop = load32() ;" //load alpha = 1
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//"sig_small_imm ; r2 = or.always(r2, r3) ; nop = nop(r0, r0) ;" //set alpha to 1
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break;
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}
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///repeat for
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//bas->dstAlphaBlendFactor
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/// Multiply dRGBA and destination factor
|
||||
//"sig_none ; nop = nop(r0, r0) ; r1 = v8muld.always(r1, r2) ;"
|
||||
assemble_qpu_asm("sig_none ; nop = nop(r0, r0) ; r1 = v8muld.always(r1, r2) ;", &instruction);
|
||||
}
|
||||
else //separate factors
|
||||
{
|
||||
@ -214,31 +146,21 @@ void patchShaderDepthStencilBlending(uint64_t** instructions, uint32_t* size, co
|
||||
switch(bas->alphaBlendOp)
|
||||
{
|
||||
case VK_BLEND_OP_ADD:
|
||||
/// If Equation is ADD:
|
||||
//"sig_none ; nop = nop(r0, r0) ; tlb_color_all = v8adds.always(r0, r1) ;"
|
||||
assemble_qpu_asm("sig_none ; nop = nop(r0, r0) ; tlb_color_all = v8adds.always(r0, r1) ;", &instruction);
|
||||
break;
|
||||
case VK_BLEND_OP_SUBTRACT:
|
||||
/// If Equation is SUB:
|
||||
//"sig_none ; nop = nop(r0, r0) ; tlb_color_all = v8subs.always(r0, r1) ;"
|
||||
assemble_qpu_asm("sig_none ; nop = nop(r0, r0) ; tlb_color_all = v8subs.always(r0, r1) ;", &instruction);
|
||||
break;
|
||||
case VK_BLEND_OP_REVERSE_SUBTRACT:
|
||||
/// If Equation is rSUB:
|
||||
//"sig_none ; nop = nop(r0, r0) ; tlb_color_all = v8subs.always(r1, r0) ;"
|
||||
assemble_qpu_asm("sig_none ; nop = nop(r0, r0) ; tlb_color_all = v8subs.always(r1, r0) ;", &instruction);
|
||||
break;
|
||||
case VK_BLEND_OP_MIN:
|
||||
/// If Equation is MIN:
|
||||
//"sig_none ; nop = nop(r0, r0) ; tlb_color_all = v8min.always(r0, r1) ;"
|
||||
assemble_qpu_asm("sig_none ; nop = nop(r0, r0) ; tlb_color_all = v8min.always(r0, r1) ;", &instruction);
|
||||
break;
|
||||
case VK_BLEND_OP_MAX:
|
||||
/// If Equation is MAX:
|
||||
//"sig_none ; nop = nop(r0, r0) ; tlb_color_all = v8max.always(r0, r1) ;"
|
||||
assemble_qpu_asm("sig_none ; nop = nop(r0, r0) ; tlb_color_all = v8max.always(r0, r1) ;", &instruction);
|
||||
break;
|
||||
}
|
||||
|
||||
/// retain nops etc.
|
||||
//"sig_end ; nop = nop(r0, r0) ; nop = nop(r0, r0) ;"
|
||||
//"sig_none ; nop = nop(r0, r0) ; nop = nop(r0, r0) ;"
|
||||
//"sig_unlock_score ; nop = nop(r0, r0) ; nop = nop(r0, r0) ;"
|
||||
}
|
||||
|
||||
//replace instructions pointer
|
||||
@ -294,7 +216,9 @@ VkResult rpi_vkCreateGraphicsPipelines(VkDevice device, VkPipelineCache pipeline
|
||||
//patch fragment shader
|
||||
if(pCreateInfos[c].pStages[d].stage & VK_SHADER_STAGE_FRAGMENT_BIT)
|
||||
{
|
||||
patchShaderDepthStencilBlending(&s->instructions[RPI_ASSEMBLY_TYPE_FRAGMENT], &s->sizes[RPI_ASSEMBLY_TYPE_FRAGMENT], pCreateInfos[c].pDepthStencilState, pCreateInfos[c].pColorBlendState->pAttachments, pAllocator);
|
||||
//TODO we could patch the fragment shader, but it would have a lot of edge cases
|
||||
//since the user is writing assembly we can just let them have full control
|
||||
//patchShaderDepthStencilBlending(&s->instructions[RPI_ASSEMBLY_TYPE_FRAGMENT], &s->sizes[RPI_ASSEMBLY_TYPE_FRAGMENT], pCreateInfos[c].pDepthStencilState, pCreateInfos[c].pColorBlendState->pAttachments, pAllocator);
|
||||
|
||||
//TODO if debug...
|
||||
for(uint64_t e = 0; e < s->sizes[RPI_ASSEMBLY_TYPE_FRAGMENT] / 8; ++e)
|
||||
|
Loading…
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Reference in New Issue
Block a user