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added howto section for the qpu assembly
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@ -34,6 +34,109 @@
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write, SFU write, Mutex read or Semaphore access.
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*********************************************************************************************************************/
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/*
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Format:
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#comment
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sig_bit_opt ; dstAdd.pack_opt = add_op.pm_opt.sf_opt.cond.unpack_opt.ws_opt(srcA, srcB, raddr_a_opt, raddr_b_opt) ; dstMul.pack_opt = mul_op.cond(srcA, srcB) ;
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sig_small_imm ; dstAdd.pack_opt = add_op.pm_opt.sf_opt.cond.unpack_opt.ws_opt(srcA, srcB, raddr_a_opt, small_imm) ; dstMul.pack_opt = mul_op.cond(srcA, srcB) ;
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sig_branch ; dstAdd = branch.rel_opt.reg_opt.ws_opt(address, condition, raddr_a_opt) ; dstMul = branch() ;
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sig_load_imm ; dstAdd.pack_opt = sem_inc.pm_opt.sf_opt.cond.ws_opt(sem_number, 27bit_imm_opt) ; dstMul.pack_opt = sem_inc.cond() ;
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sig_load_imm ; dstAdd.pack_opt = load32.pm_opt.sf_opt.cond.ws_opt(immediate32bit_value) ; dstMul.pack_opt = load32.cond() ;
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sig_load_imm ; dstAdd.pack_opt = load16.pm_opt.signed_opt.sf_opt.cond.ws_opt(int16_imm, int16_imm) ; dstMul.pack_opt = load16.cond() ;
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==================================================================
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================How to formulate instructions:====================
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==================================================================
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1)
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You must specify the signal bits at the beginning of each instruction:
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sig_brk, sig_none, sig_switch, sig_end, sig_wait_score, sig_unlock_score, sig_thread_switch, sig_coverage_load,
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sig_color_load, sig_color_load_end, sig_load_tmu0, sig_load_tmu1, sig_alpha_mask_load, sig_small_imm, sig_load_imm, sig_branch
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2)
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Then you must specify the output register for the ADD pipeline.
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rx0-31, r0-3, r5, tmu_noswap, host_int, nop, uniforms_addr, quad_x, quad_y, ms_flags, rev_flags, tlb_stencil_setup
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tlb_z, tlb_color_ms, tlb_color_all, vpm, vr_setup, vr_addr, mutex_release, sfu_recip, sfu_recipsqrt, sfu_exp,
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sfu_log, tmu0_s, tmu0_t, tmu0_r, tmu0_b, tmu1_s, tmu1_t, tmu1_r, tmu1_b
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3)
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If the ADD instruction writes to regfile A (ie. you don't specify the WS flag later) and PM flag won't be specified,
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then you can specify the pack mode for regfile A here (omitting means nop)
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nop, 16a, 16b, 8888, 8a, 8b, 8c, 8d, sta, 16a.sat, 16b.sat, 8888.sat, 8a.sat, 8b.sat, 8c.sat, 8d.sat
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4)
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Then you must specify your operation for the ADD pipeline. If you are writing a non-ALU instruction, you can specify either
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branch, sem_inc, sem_dec, load32 or load16 here instead.
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Operations available:
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nop, fadd, fsub, fmin, fmax, fminabs, fmaxabs, ftoi, itof, add, sub, shr, asr, ror, shl, min, max, and, or, xor, not, clz, v8adds, v8subs
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5)
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Then you can specify a range of modifiers (order is not important):
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PM bit: pm
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SF bit: sf
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WS bit: ws
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REL bit: rel
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REG bit: reg
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SIGNED bit: signed
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Conditional execution for the ADD pipeline: never, always, zs, zc, ns, nc, cs, cc
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Unpack modes (from regfile A, or if PM is set from R4): nop, 16a, 16b, 8d_rep, 8a, 8b, 8c, 8d
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6)
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Then you must specify the arguments for the ALU operation.
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srcA, srcB can be: r0-r5 or a, b for regfiles A and B, or imm for the small immediate value.
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raddr_a and raddr_b can be specified afterwards as optional extra arguments (omitting means nop).
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raddr_a: ra0-31, pay_zw, uni, vary, elem, nop, x_pix, ms_flags, vpm_read, vpm_ld_busy, vpm_ld_wait, mutex_acq
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raddr_b: rb0-31, pay_zw, uni, vary, elem, nop, y_pix, rev_flag, vpm_read, vpm_st_busy, vpm_st_wait, mutex_acq
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For branch operation, you must specify:
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the jump address as a 32bit value (can be relative if REL is set)
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the branch condition: all_zs, all_zc, any_zs, any_zc, all_ns, all_nc, any_ns, any_nc, all_cs, all_cc, any_cs, any_cc, always
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and an optional raddr_a (if REG flag is set), see above
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For a semaphore instruction, you need to specify which semaphore (0-15) you want to modify, then an optional 27bit immediate value (ms 16bits might be usable...).
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7)
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Then you must specify the output register for the MUL pipeline.
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See above for options.
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8)
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If the MUL instruction writes to regfile A (ie. you specify the WS flag) then you can set the pack operation for regfile A here:
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nop, 16a, 16b, 8888, 8a, 8b, 8c, 8d, sta, 16a.sat, 16b.sat, 8888.sat, 8a.sat, 8b.sat, 8c.sat, 8d.sat
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OR
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You if specify the PM flag, then you can set the pack operation for the MUL output here:
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nop, 8888, 8a, 8b, 8c, 8d
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9)
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Then you must specify your operation for the MUL pipeline. If you are writing a non-ALU instruction, you can specify either
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branch, sem_inc, sem_dec, load32 or load16 here instead.
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Operations available:
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nop, fmul, mul24, v8muld, v8min, v8max, v8adds, v8subs
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10)
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Then you can specify a range of modifiers (order is not important):
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Conditional execution for the MUL pipeline: never, always, zs, zc, ns, nc, cs, cc
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11)
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Then you must specify the arguments for the ALU operation.
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srcA, srcB can be: r0-r5 or a, b for regfiles A and B, or imm for the small immediate value.
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==================================================================
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==================================================================
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dstAdd: rx0-31, r0-5, special regs
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raddr_a_opt: ra0-31, r0-5, special regs
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raddr_b_opt: rb0-31, r0-5, special regs
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Examples:
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sig_none ; rx0.nop = add.pm.sf.always(r0, r1, 0) ; rx0.nop = fmul.always(r2, r3) ;
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sig_branch ; rx0 = branch.pm.rel.reg.always(0xdeadbeef, ra1) ; rx0 = branch() ;
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sig_none ; rx0.nop = sem_inc.pm.sf.always(1, 0x7ffffff) ; rx0.nop = sem_inc.always() ;
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sig_load_imm ; rx0.nop = load32.pm.sf.always(0xdeadbeef) ; rx0.nop = load32.always() ;
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sig_load_imm ; rx0.nop = load16.pm.sf.signed.always(1, 2) ; rx0.nop = load16.always() ;
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#mov
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sig_none ; rx0.nop = or(r0, r0) ; rx0 = v8min(r1, r1) ;
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*/
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uint64_t encode_alu(qpu_sig_bits sig_bits,
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qpu_unpack unpack_mode,
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//If the pm bit is set, the unpack field programs the r4 unpack unit,
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@ -1338,33 +1441,6 @@ void disassemble_qpu_asm(uint64_t instruction)
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printf("\n");
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}
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/*
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Format:
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#comment
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sig_bit_opt ; dstAdd.pack_opt = add_op.pm_opt.sf_opt.cond.unpack_opt.ws_opt(srcA, srcB, raddr_a_opt, raddr_b_opt) ; dstMul.pack_opt = mul_op.cond(srcA, srcB) ;
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sig_small_imm ; dstAdd.pack_opt = add_op.pm_opt.sf_opt.cond.unpack_opt.ws_opt(srcA, srcB, raddr_a_opt, small_imm) ; dstMul.pack_opt = mul_op.cond(srcA, srcB) ;
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sig_branch ; dstAdd = branch.rel_opt.reg_opt.ws_opt(address, condition, srcA_opt) ; dstMul = branch() ;
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sig_load_imm ; dstAdd.pack_opt = sem_inc.pm_opt.sf_opt.cond.ws_opt(sem_number, 27bit_imm_opt) ; dstMul.pack_opt = sem_inc.cond() ;
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sig_load_imm ; dstAdd.pack_opt = load32.pm_opt.sf_opt.cond.ws_opt(immediate_value) ; dstMul.pack_opt = load32.cond() ;
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sig_load_imm ; dstAdd.pack_opt = load16.pm_opt.signed_opt.sf_opt.cond.ws_opt(int16_imm, in16_imm) ; dstMul.pack_opt = load16.cond() ;
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You can specify the signal bits at the beginning of each instruction.
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dstAdd: rx0-31, r0-5, special regs
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raddr_a_opt: ra0-31, r0-5, special regs
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raddr_b_opt: rb0-31, r0-5, special regs
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Examples:
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sig_none ; rx0.nop = add.pm.sf.always(r0, r1, 0) ; rx0.nop = fmul.always(r2, r3) ;
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sig_branch ; rx0 = branch.pm.rel.reg.always(0xdeadbeef, ra1) ; rx0 = branch() ;
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sig_none ; rx0.nop = sem_inc.pm.sf.always(1, 0x7ffffff) ; rx0.nop = sem_inc.always() ;
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sig_load_imm ; rx0.nop = load32.pm.sf.always(0xdeadbeef) ; rx0.nop = load32.always() ;
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sig_load_imm ; rx0.nop = load16.pm.sf.signed.always(1, 2) ; rx0.nop = load16.always() ;
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#mov
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sig_none ; rx0.nop = or(r0, r0) ; rx0 = v8min(r1, r1) ;
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*/
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int main()
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{
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char asm_code[] =
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@ -411,6 +411,7 @@ typedef enum {
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static const char *qpu_raddr_str[][52] = {
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{ //A
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//ra0-31
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[QPU_R_FRAG_PAYLOAD_ZW] = "pay_zw",
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[QPU_R_UNIF] = "uni",
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[QPU_R_VARY] = "vary",
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@ -424,6 +425,7 @@ static const char *qpu_raddr_str[][52] = {
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[QPU_R_MUTEX_ACQUIRE] = "mutex_acq"
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},
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{ //B
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//rb0-31
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[QPU_R_FRAG_PAYLOAD_ZW] = "pay_zw",
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[QPU_R_UNIF] = "uni",
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[QPU_R_VARY] = "vary",
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