From 7cdf8849b7de727ce1374a3164c990c65fe50f51 Mon Sep 17 00:00:00 2001 From: Unknown <0.tamas.marton@gmail.com> Date: Sun, 13 May 2018 15:28:52 +0100 Subject: [PATCH] updated externals --- external/include/drm/amdgpu_drm.h | 934 ------------------ external/include/drm/drm.h | 46 +- external/include/drm/drm_mode.h | 43 +- external/include/drm/drm_sarea.h | 92 -- external/include/drm/i915_drm.h | 1431 ---------------------------- external/include/drm/mach64_drm.h | 256 ----- external/include/drm/mga_drm.h | 427 --------- external/include/drm/nouveau_drm.h | 220 ----- external/include/drm/qxl_drm.h | 160 ---- external/include/drm/r128_drm.h | 336 ------- external/include/drm/radeon_drm.h | 1079 --------------------- external/include/drm/savage_drm.h | 220 ----- external/include/drm/sis_drm.h | 77 -- external/include/drm/tegra_drm.h | 209 ---- external/include/drm/vc4_drm.h | 138 ++- external/include/drm/via_drm.h | 283 ------ external/include/drm/virtgpu_drm.h | 174 ---- external/include/drm/vmwgfx_drm.h | 1099 --------------------- 18 files changed, 170 insertions(+), 7054 deletions(-) delete mode 100644 external/include/drm/amdgpu_drm.h delete mode 100644 external/include/drm/drm_sarea.h delete mode 100644 external/include/drm/i915_drm.h delete mode 100644 external/include/drm/mach64_drm.h delete mode 100644 external/include/drm/mga_drm.h delete mode 100644 external/include/drm/nouveau_drm.h delete mode 100644 external/include/drm/qxl_drm.h delete mode 100644 external/include/drm/r128_drm.h delete mode 100644 external/include/drm/radeon_drm.h delete mode 100644 external/include/drm/savage_drm.h delete mode 100644 external/include/drm/sis_drm.h delete mode 100644 external/include/drm/tegra_drm.h delete mode 100644 external/include/drm/via_drm.h delete mode 100644 external/include/drm/virtgpu_drm.h delete mode 100644 external/include/drm/vmwgfx_drm.h diff --git a/external/include/drm/amdgpu_drm.h b/external/include/drm/amdgpu_drm.h deleted file mode 100644 index a023b47..0000000 --- a/external/include/drm/amdgpu_drm.h +++ /dev/null @@ -1,934 +0,0 @@ -/* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- - * - * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Fremont, California. - * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. - * Copyright 2014 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Kevin E. Martin - * Gareth Hughes - * Keith Whitwell - */ - -#ifndef __AMDGPU_DRM_H__ -#define __AMDGPU_DRM_H__ - -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -#define DRM_AMDGPU_GEM_CREATE 0x00 -#define DRM_AMDGPU_GEM_MMAP 0x01 -#define DRM_AMDGPU_CTX 0x02 -#define DRM_AMDGPU_BO_LIST 0x03 -#define DRM_AMDGPU_CS 0x04 -#define DRM_AMDGPU_INFO 0x05 -#define DRM_AMDGPU_GEM_METADATA 0x06 -#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 -#define DRM_AMDGPU_GEM_VA 0x08 -#define DRM_AMDGPU_WAIT_CS 0x09 -#define DRM_AMDGPU_GEM_OP 0x10 -#define DRM_AMDGPU_GEM_USERPTR 0x11 -#define DRM_AMDGPU_WAIT_FENCES 0x12 -#define DRM_AMDGPU_VM 0x13 -#define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 -#define DRM_AMDGPU_SCHED 0x15 - -#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) -#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) -#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) -#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) -#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) -#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) -#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) -#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) -#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) -#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) -#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) -#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) -#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) -#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) -#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) -#define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) - -#define AMDGPU_GEM_DOMAIN_CPU 0x1 -#define AMDGPU_GEM_DOMAIN_GTT 0x2 -#define AMDGPU_GEM_DOMAIN_VRAM 0x4 -#define AMDGPU_GEM_DOMAIN_GDS 0x8 -#define AMDGPU_GEM_DOMAIN_GWS 0x10 -#define AMDGPU_GEM_DOMAIN_OA 0x20 - -/* Flag that CPU access will be required for the case of VRAM domain */ -#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) -/* Flag that CPU access will not work, this VRAM domain is invisible */ -#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) -/* Flag that USWC attributes should be used for GTT */ -#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) -/* Flag that the memory should be in VRAM and cleared */ -#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) -/* Flag that create shadow bo(GTT) while allocating vram bo */ -#define AMDGPU_GEM_CREATE_SHADOW (1 << 4) -/* Flag that allocating the BO should use linear VRAM */ -#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) -/* Flag that BO is always valid in this VM */ -#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) -/* Flag that BO sharing will be explicitly synchronized */ -#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) - -struct drm_amdgpu_gem_create_in { - /** the requested memory size */ - __u64 bo_size; - /** physical start_addr alignment in bytes for some HW requirements */ - __u64 alignment; - /** the requested memory domains */ - __u64 domains; - /** allocation flags */ - __u64 domain_flags; -}; - -struct drm_amdgpu_gem_create_out { - /** returned GEM object handle */ - __u32 handle; - __u32 _pad; -}; - -union drm_amdgpu_gem_create { - struct drm_amdgpu_gem_create_in in; - struct drm_amdgpu_gem_create_out out; -}; - -/** Opcode to create new residency list. */ -#define AMDGPU_BO_LIST_OP_CREATE 0 -/** Opcode to destroy previously created residency list */ -#define AMDGPU_BO_LIST_OP_DESTROY 1 -/** Opcode to update resource information in the list */ -#define AMDGPU_BO_LIST_OP_UPDATE 2 - -struct drm_amdgpu_bo_list_in { - /** Type of operation */ - __u32 operation; - /** Handle of list or 0 if we want to create one */ - __u32 list_handle; - /** Number of BOs in list */ - __u32 bo_number; - /** Size of each element describing BO */ - __u32 bo_info_size; - /** Pointer to array describing BOs */ - __u64 bo_info_ptr; -}; - -struct drm_amdgpu_bo_list_entry { - /** Handle of BO */ - __u32 bo_handle; - /** New (if specified) BO priority to be used during migration */ - __u32 bo_priority; -}; - -struct drm_amdgpu_bo_list_out { - /** Handle of resource list */ - __u32 list_handle; - __u32 _pad; -}; - -union drm_amdgpu_bo_list { - struct drm_amdgpu_bo_list_in in; - struct drm_amdgpu_bo_list_out out; -}; - -/* context related */ -#define AMDGPU_CTX_OP_ALLOC_CTX 1 -#define AMDGPU_CTX_OP_FREE_CTX 2 -#define AMDGPU_CTX_OP_QUERY_STATE 3 - -/* GPU reset status */ -#define AMDGPU_CTX_NO_RESET 0 -/* this the context caused it */ -#define AMDGPU_CTX_GUILTY_RESET 1 -/* some other context caused it */ -#define AMDGPU_CTX_INNOCENT_RESET 2 -/* unknown cause */ -#define AMDGPU_CTX_UNKNOWN_RESET 3 - -/* Context priority level */ -#define AMDGPU_CTX_PRIORITY_UNSET -2048 -#define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 -#define AMDGPU_CTX_PRIORITY_LOW -512 -#define AMDGPU_CTX_PRIORITY_NORMAL 0 -/* Selecting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER */ -#define AMDGPU_CTX_PRIORITY_HIGH 512 -#define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 - -struct drm_amdgpu_ctx_in { - /** AMDGPU_CTX_OP_* */ - __u32 op; - /** For future use, no flags defined so far */ - __u32 flags; - __u32 ctx_id; - __s32 priority; -}; - -union drm_amdgpu_ctx_out { - struct { - __u32 ctx_id; - __u32 _pad; - } alloc; - - struct { - /** For future use, no flags defined so far */ - __u64 flags; - /** Number of resets caused by this context so far. */ - __u32 hangs; - /** Reset status since the last call of the ioctl. */ - __u32 reset_status; - } state; -}; - -union drm_amdgpu_ctx { - struct drm_amdgpu_ctx_in in; - union drm_amdgpu_ctx_out out; -}; - -/* vm ioctl */ -#define AMDGPU_VM_OP_RESERVE_VMID 1 -#define AMDGPU_VM_OP_UNRESERVE_VMID 2 - -struct drm_amdgpu_vm_in { - /** AMDGPU_VM_OP_* */ - __u32 op; - __u32 flags; -}; - -struct drm_amdgpu_vm_out { - /** For future use, no flags defined so far */ - __u64 flags; -}; - -union drm_amdgpu_vm { - struct drm_amdgpu_vm_in in; - struct drm_amdgpu_vm_out out; -}; - -/* sched ioctl */ -#define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 - -struct drm_amdgpu_sched_in { - /* AMDGPU_SCHED_OP_* */ - __u32 op; - __u32 fd; - __s32 priority; - __u32 flags; -}; - -union drm_amdgpu_sched { - struct drm_amdgpu_sched_in in; -}; - -/* - * This is not a reliable API and you should expect it to fail for any - * number of reasons and have fallback path that do not use userptr to - * perform any operation. - */ -#define AMDGPU_GEM_USERPTR_READONLY (1 << 0) -#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) -#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) -#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) - -struct drm_amdgpu_gem_userptr { - __u64 addr; - __u64 size; - /* AMDGPU_GEM_USERPTR_* */ - __u32 flags; - /* Resulting GEM handle */ - __u32 handle; -}; - -/* SI-CI-VI: */ -/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ -#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 -#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf -#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 -#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f -#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 -#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 -#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 -#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 -#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 -#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 -#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 -#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 -#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 -#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 -#define AMDGPU_TILING_NUM_BANKS_SHIFT 21 -#define AMDGPU_TILING_NUM_BANKS_MASK 0x3 - -/* GFX9 and later: */ -#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 -#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f - -/* Set/Get helpers for tiling flags. */ -#define AMDGPU_TILING_SET(field, value) \ - (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) -#define AMDGPU_TILING_GET(value, field) \ - (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) - -#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 -#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 - -/** The same structure is shared for input/output */ -struct drm_amdgpu_gem_metadata { - /** GEM Object handle */ - __u32 handle; - /** Do we want get or set metadata */ - __u32 op; - struct { - /** For future use, no flags defined so far */ - __u64 flags; - /** family specific tiling info */ - __u64 tiling_info; - __u32 data_size_bytes; - __u32 data[64]; - } data; -}; - -struct drm_amdgpu_gem_mmap_in { - /** the GEM object handle */ - __u32 handle; - __u32 _pad; -}; - -struct drm_amdgpu_gem_mmap_out { - /** mmap offset from the vma offset manager */ - __u64 addr_ptr; -}; - -union drm_amdgpu_gem_mmap { - struct drm_amdgpu_gem_mmap_in in; - struct drm_amdgpu_gem_mmap_out out; -}; - -struct drm_amdgpu_gem_wait_idle_in { - /** GEM object handle */ - __u32 handle; - /** For future use, no flags defined so far */ - __u32 flags; - /** Absolute timeout to wait */ - __u64 timeout; -}; - -struct drm_amdgpu_gem_wait_idle_out { - /** BO status: 0 - BO is idle, 1 - BO is busy */ - __u32 status; - /** Returned current memory domain */ - __u32 domain; -}; - -union drm_amdgpu_gem_wait_idle { - struct drm_amdgpu_gem_wait_idle_in in; - struct drm_amdgpu_gem_wait_idle_out out; -}; - -struct drm_amdgpu_wait_cs_in { - /* Command submission handle - * handle equals 0 means none to wait for - * handle equals ~0ull means wait for the latest sequence number - */ - __u64 handle; - /** Absolute timeout to wait */ - __u64 timeout; - __u32 ip_type; - __u32 ip_instance; - __u32 ring; - __u32 ctx_id; -}; - -struct drm_amdgpu_wait_cs_out { - /** CS status: 0 - CS completed, 1 - CS still busy */ - __u64 status; -}; - -union drm_amdgpu_wait_cs { - struct drm_amdgpu_wait_cs_in in; - struct drm_amdgpu_wait_cs_out out; -}; - -struct drm_amdgpu_fence { - __u32 ctx_id; - __u32 ip_type; - __u32 ip_instance; - __u32 ring; - __u64 seq_no; -}; - -struct drm_amdgpu_wait_fences_in { - /** This points to uint64_t * which points to fences */ - __u64 fences; - __u32 fence_count; - __u32 wait_all; - __u64 timeout_ns; -}; - -struct drm_amdgpu_wait_fences_out { - __u32 status; - __u32 first_signaled; -}; - -union drm_amdgpu_wait_fences { - struct drm_amdgpu_wait_fences_in in; - struct drm_amdgpu_wait_fences_out out; -}; - -#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 -#define AMDGPU_GEM_OP_SET_PLACEMENT 1 - -/* Sets or returns a value associated with a buffer. */ -struct drm_amdgpu_gem_op { - /** GEM object handle */ - __u32 handle; - /** AMDGPU_GEM_OP_* */ - __u32 op; - /** Input or return value */ - __u64 value; -}; - -#define AMDGPU_VA_OP_MAP 1 -#define AMDGPU_VA_OP_UNMAP 2 -#define AMDGPU_VA_OP_CLEAR 3 -#define AMDGPU_VA_OP_REPLACE 4 - -/* Delay the page table update till the next CS */ -#define AMDGPU_VM_DELAY_UPDATE (1 << 0) - -/* Mapping flags */ -/* readable mapping */ -#define AMDGPU_VM_PAGE_READABLE (1 << 1) -/* writable mapping */ -#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) -/* executable mapping, new for VI */ -#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) -/* partially resident texture */ -#define AMDGPU_VM_PAGE_PRT (1 << 4) -/* MTYPE flags use bit 5 to 8 */ -#define AMDGPU_VM_MTYPE_MASK (0xf << 5) -/* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ -#define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) -/* Use NC MTYPE instead of default MTYPE */ -#define AMDGPU_VM_MTYPE_NC (1 << 5) -/* Use WC MTYPE instead of default MTYPE */ -#define AMDGPU_VM_MTYPE_WC (2 << 5) -/* Use CC MTYPE instead of default MTYPE */ -#define AMDGPU_VM_MTYPE_CC (3 << 5) -/* Use UC MTYPE instead of default MTYPE */ -#define AMDGPU_VM_MTYPE_UC (4 << 5) - -struct drm_amdgpu_gem_va { - /** GEM object handle */ - __u32 handle; - __u32 _pad; - /** AMDGPU_VA_OP_* */ - __u32 operation; - /** AMDGPU_VM_PAGE_* */ - __u32 flags; - /** va address to assign . Must be correctly aligned.*/ - __u64 va_address; - /** Specify offset inside of BO to assign. Must be correctly aligned.*/ - __u64 offset_in_bo; - /** Specify mapping size. Must be correctly aligned. */ - __u64 map_size; -}; - -#define AMDGPU_HW_IP_GFX 0 -#define AMDGPU_HW_IP_COMPUTE 1 -#define AMDGPU_HW_IP_DMA 2 -#define AMDGPU_HW_IP_UVD 3 -#define AMDGPU_HW_IP_VCE 4 -#define AMDGPU_HW_IP_UVD_ENC 5 -#define AMDGPU_HW_IP_VCN_DEC 6 -#define AMDGPU_HW_IP_VCN_ENC 7 -#define AMDGPU_HW_IP_NUM 8 - -#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 - -#define AMDGPU_CHUNK_ID_IB 0x01 -#define AMDGPU_CHUNK_ID_FENCE 0x02 -#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 -#define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 -#define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 - -struct drm_amdgpu_cs_chunk { - __u32 chunk_id; - __u32 length_dw; - __u64 chunk_data; -}; - -struct drm_amdgpu_cs_in { - /** Rendering context id */ - __u32 ctx_id; - /** Handle of resource list associated with CS */ - __u32 bo_list_handle; - __u32 num_chunks; - __u32 _pad; - /** this points to __u64 * which point to cs chunks */ - __u64 chunks; -}; - -struct drm_amdgpu_cs_out { - __u64 handle; -}; - -union drm_amdgpu_cs { - struct drm_amdgpu_cs_in in; - struct drm_amdgpu_cs_out out; -}; - -/* Specify flags to be used for IB */ - -/* This IB should be submitted to CE */ -#define AMDGPU_IB_FLAG_CE (1<<0) - -/* Preamble flag, which means the IB could be dropped if no context switch */ -#define AMDGPU_IB_FLAG_PREAMBLE (1<<1) - -/* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ -#define AMDGPU_IB_FLAG_PREEMPT (1<<2) - -struct drm_amdgpu_cs_chunk_ib { - __u32 _pad; - /** AMDGPU_IB_FLAG_* */ - __u32 flags; - /** Virtual address to begin IB execution */ - __u64 va_start; - /** Size of submission */ - __u32 ib_bytes; - /** HW IP to submit to */ - __u32 ip_type; - /** HW IP index of the same type to submit to */ - __u32 ip_instance; - /** Ring index to submit to */ - __u32 ring; -}; - -struct drm_amdgpu_cs_chunk_dep { - __u32 ip_type; - __u32 ip_instance; - __u32 ring; - __u32 ctx_id; - __u64 handle; -}; - -struct drm_amdgpu_cs_chunk_fence { - __u32 handle; - __u32 offset; -}; - -struct drm_amdgpu_cs_chunk_sem { - __u32 handle; -}; - -#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 -#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 -#define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 - -union drm_amdgpu_fence_to_handle { - struct { - struct drm_amdgpu_fence fence; - __u32 what; - __u32 pad; - } in; - struct { - __u32 handle; - } out; -}; - -struct drm_amdgpu_cs_chunk_data { - union { - struct drm_amdgpu_cs_chunk_ib ib_data; - struct drm_amdgpu_cs_chunk_fence fence_data; - }; -}; - -/** - * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU - * - */ -#define AMDGPU_IDS_FLAGS_FUSION 0x1 -#define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 - -/* indicate if acceleration can be working */ -#define AMDGPU_INFO_ACCEL_WORKING 0x00 -/* get the crtc_id from the mode object id? */ -#define AMDGPU_INFO_CRTC_FROM_ID 0x01 -/* query hw IP info */ -#define AMDGPU_INFO_HW_IP_INFO 0x02 -/* query hw IP instance count for the specified type */ -#define AMDGPU_INFO_HW_IP_COUNT 0x03 -/* timestamp for GL_ARB_timer_query */ -#define AMDGPU_INFO_TIMESTAMP 0x05 -/* Query the firmware version */ -#define AMDGPU_INFO_FW_VERSION 0x0e - /* Subquery id: Query VCE firmware version */ - #define AMDGPU_INFO_FW_VCE 0x1 - /* Subquery id: Query UVD firmware version */ - #define AMDGPU_INFO_FW_UVD 0x2 - /* Subquery id: Query GMC firmware version */ - #define AMDGPU_INFO_FW_GMC 0x03 - /* Subquery id: Query GFX ME firmware version */ - #define AMDGPU_INFO_FW_GFX_ME 0x04 - /* Subquery id: Query GFX PFP firmware version */ - #define AMDGPU_INFO_FW_GFX_PFP 0x05 - /* Subquery id: Query GFX CE firmware version */ - #define AMDGPU_INFO_FW_GFX_CE 0x06 - /* Subquery id: Query GFX RLC firmware version */ - #define AMDGPU_INFO_FW_GFX_RLC 0x07 - /* Subquery id: Query GFX MEC firmware version */ - #define AMDGPU_INFO_FW_GFX_MEC 0x08 - /* Subquery id: Query SMC firmware version */ - #define AMDGPU_INFO_FW_SMC 0x0a - /* Subquery id: Query SDMA firmware version */ - #define AMDGPU_INFO_FW_SDMA 0x0b - /* Subquery id: Query PSP SOS firmware version */ - #define AMDGPU_INFO_FW_SOS 0x0c - /* Subquery id: Query PSP ASD firmware version */ - #define AMDGPU_INFO_FW_ASD 0x0d -/* number of bytes moved for TTM migration */ -#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f -/* the used VRAM size */ -#define AMDGPU_INFO_VRAM_USAGE 0x10 -/* the used GTT size */ -#define AMDGPU_INFO_GTT_USAGE 0x11 -/* Information about GDS, etc. resource configuration */ -#define AMDGPU_INFO_GDS_CONFIG 0x13 -/* Query information about VRAM and GTT domains */ -#define AMDGPU_INFO_VRAM_GTT 0x14 -/* Query information about register in MMR address space*/ -#define AMDGPU_INFO_READ_MMR_REG 0x15 -/* Query information about device: rev id, family, etc. */ -#define AMDGPU_INFO_DEV_INFO 0x16 -/* visible vram usage */ -#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 -/* number of TTM buffer evictions */ -#define AMDGPU_INFO_NUM_EVICTIONS 0x18 -/* Query memory about VRAM and GTT domains */ -#define AMDGPU_INFO_MEMORY 0x19 -/* Query vce clock table */ -#define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A -/* Query vbios related information */ -#define AMDGPU_INFO_VBIOS 0x1B - /* Subquery id: Query vbios size */ - #define AMDGPU_INFO_VBIOS_SIZE 0x1 - /* Subquery id: Query vbios image */ - #define AMDGPU_INFO_VBIOS_IMAGE 0x2 -/* Query UVD handles */ -#define AMDGPU_INFO_NUM_HANDLES 0x1C -/* Query sensor related information */ -#define AMDGPU_INFO_SENSOR 0x1D - /* Subquery id: Query GPU shader clock */ - #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 - /* Subquery id: Query GPU memory clock */ - #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 - /* Subquery id: Query GPU temperature */ - #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 - /* Subquery id: Query GPU load */ - #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 - /* Subquery id: Query average GPU power */ - #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 - /* Subquery id: Query northbridge voltage */ - #define AMDGPU_INFO_SENSOR_VDDNB 0x6 - /* Subquery id: Query graphics voltage */ - #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 -/* Number of VRAM page faults on CPU access. */ -#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E -#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F - -#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 -#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff -#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 -#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff - -struct drm_amdgpu_query_fw { - /** AMDGPU_INFO_FW_* */ - __u32 fw_type; - /** - * Index of the IP if there are more IPs of - * the same type. - */ - __u32 ip_instance; - /** - * Index of the engine. Whether this is used depends - * on the firmware type. (e.g. MEC, SDMA) - */ - __u32 index; - __u32 _pad; -}; - -/* Input structure for the INFO ioctl */ -struct drm_amdgpu_info { - /* Where the return value will be stored */ - __u64 return_pointer; - /* The size of the return value. Just like "size" in "snprintf", - * it limits how many bytes the kernel can write. */ - __u32 return_size; - /* The query request id. */ - __u32 query; - - union { - struct { - __u32 id; - __u32 _pad; - } mode_crtc; - - struct { - /** AMDGPU_HW_IP_* */ - __u32 type; - /** - * Index of the IP if there are more IPs of the same - * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. - */ - __u32 ip_instance; - } query_hw_ip; - - struct { - __u32 dword_offset; - /** number of registers to read */ - __u32 count; - __u32 instance; - /** For future use, no flags defined so far */ - __u32 flags; - } read_mmr_reg; - - struct drm_amdgpu_query_fw query_fw; - - struct { - __u32 type; - __u32 offset; - } vbios_info; - - struct { - __u32 type; - } sensor_info; - }; -}; - -struct drm_amdgpu_info_gds { - /** GDS GFX partition size */ - __u32 gds_gfx_partition_size; - /** GDS compute partition size */ - __u32 compute_partition_size; - /** total GDS memory size */ - __u32 gds_total_size; - /** GWS size per GFX partition */ - __u32 gws_per_gfx_partition; - /** GSW size per compute partition */ - __u32 gws_per_compute_partition; - /** OA size per GFX partition */ - __u32 oa_per_gfx_partition; - /** OA size per compute partition */ - __u32 oa_per_compute_partition; - __u32 _pad; -}; - -struct drm_amdgpu_info_vram_gtt { - __u64 vram_size; - __u64 vram_cpu_accessible_size; - __u64 gtt_size; -}; - -struct drm_amdgpu_heap_info { - /** max. physical memory */ - __u64 total_heap_size; - - /** Theoretical max. available memory in the given heap */ - __u64 usable_heap_size; - - /** - * Number of bytes allocated in the heap. This includes all processes - * and private allocations in the kernel. It changes when new buffers - * are allocated, freed, and moved. It cannot be larger than - * heap_size. - */ - __u64 heap_usage; - - /** - * Theoretical possible max. size of buffer which - * could be allocated in the given heap - */ - __u64 max_allocation; -}; - -struct drm_amdgpu_memory_info { - struct drm_amdgpu_heap_info vram; - struct drm_amdgpu_heap_info cpu_accessible_vram; - struct drm_amdgpu_heap_info gtt; -}; - -struct drm_amdgpu_info_firmware { - __u32 ver; - __u32 feature; -}; - -#define AMDGPU_VRAM_TYPE_UNKNOWN 0 -#define AMDGPU_VRAM_TYPE_GDDR1 1 -#define AMDGPU_VRAM_TYPE_DDR2 2 -#define AMDGPU_VRAM_TYPE_GDDR3 3 -#define AMDGPU_VRAM_TYPE_GDDR4 4 -#define AMDGPU_VRAM_TYPE_GDDR5 5 -#define AMDGPU_VRAM_TYPE_HBM 6 -#define AMDGPU_VRAM_TYPE_DDR3 7 - -struct drm_amdgpu_info_device { - /** PCI Device ID */ - __u32 device_id; - /** Internal chip revision: A0, A1, etc.) */ - __u32 chip_rev; - __u32 external_rev; - /** Revision id in PCI Config space */ - __u32 pci_rev; - __u32 family; - __u32 num_shader_engines; - __u32 num_shader_arrays_per_engine; - /* in KHz */ - __u32 gpu_counter_freq; - __u64 max_engine_clock; - __u64 max_memory_clock; - /* cu information */ - __u32 cu_active_number; - /* NOTE: cu_ao_mask is INVALID, DON'T use it */ - __u32 cu_ao_mask; - __u32 cu_bitmap[4][4]; - /** Render backend pipe mask. One render backend is CB+DB. */ - __u32 enabled_rb_pipes_mask; - __u32 num_rb_pipes; - __u32 num_hw_gfx_contexts; - __u32 _pad; - __u64 ids_flags; - /** Starting virtual address for UMDs. */ - __u64 virtual_address_offset; - /** The maximum virtual address */ - __u64 virtual_address_max; - /** Required alignment of virtual addresses. */ - __u32 virtual_address_alignment; - /** Page table entry - fragment size */ - __u32 pte_fragment_size; - __u32 gart_page_size; - /** constant engine ram size*/ - __u32 ce_ram_size; - /** video memory type info*/ - __u32 vram_type; - /** video memory bit width*/ - __u32 vram_bit_width; - /* vce harvesting instance */ - __u32 vce_harvest_config; - /* gfx double offchip LDS buffers */ - __u32 gc_double_offchip_lds_buf; - /* NGG Primitive Buffer */ - __u64 prim_buf_gpu_addr; - /* NGG Position Buffer */ - __u64 pos_buf_gpu_addr; - /* NGG Control Sideband */ - __u64 cntl_sb_buf_gpu_addr; - /* NGG Parameter Cache */ - __u64 param_buf_gpu_addr; - __u32 prim_buf_size; - __u32 pos_buf_size; - __u32 cntl_sb_buf_size; - __u32 param_buf_size; - /* wavefront size*/ - __u32 wave_front_size; - /* shader visible vgprs*/ - __u32 num_shader_visible_vgprs; - /* CU per shader array*/ - __u32 num_cu_per_sh; - /* number of tcc blocks*/ - __u32 num_tcc_blocks; - /* gs vgt table depth*/ - __u32 gs_vgt_table_depth; - /* gs primitive buffer depth*/ - __u32 gs_prim_buffer_depth; - /* max gs wavefront per vgt*/ - __u32 max_gs_waves_per_vgt; - __u32 _pad1; - /* always on cu bitmap */ - __u32 cu_ao_bitmap[4][4]; - /** Starting high virtual address for UMDs. */ - __u64 high_va_offset; - /** The maximum high virtual address */ - __u64 high_va_max; -}; - -struct drm_amdgpu_info_hw_ip { - /** Version of h/w IP */ - __u32 hw_ip_version_major; - __u32 hw_ip_version_minor; - /** Capabilities */ - __u64 capabilities_flags; - /** command buffer address start alignment*/ - __u32 ib_start_alignment; - /** command buffer size alignment*/ - __u32 ib_size_alignment; - /** Bitmask of available rings. Bit 0 means ring 0, etc. */ - __u32 available_rings; - __u32 _pad; -}; - -struct drm_amdgpu_info_num_handles { - /** Max handles as supported by firmware for UVD */ - __u32 uvd_max_handles; - /** Handles currently in use for UVD */ - __u32 uvd_used_handles; -}; - -#define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 - -struct drm_amdgpu_info_vce_clock_table_entry { - /** System clock */ - __u32 sclk; - /** Memory clock */ - __u32 mclk; - /** VCE clock */ - __u32 eclk; - __u32 pad; -}; - -struct drm_amdgpu_info_vce_clock_table { - struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; - __u32 num_valid_entries; - __u32 pad; -}; - -/* - * Supported GPU families - */ -#define AMDGPU_FAMILY_UNKNOWN 0 -#define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ -#define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ -#define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ -#define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ -#define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ -#define AMDGPU_FAMILY_AI 141 /* Vega10 */ -#define AMDGPU_FAMILY_RV 142 /* Raven */ - -#if defined(__cplusplus) -} -#endif - -#endif diff --git a/external/include/drm/drm.h b/external/include/drm/drm.h index f0bd91d..6e65519 100644 --- a/external/include/drm/drm.h +++ b/external/include/drm/drm.h @@ -36,7 +36,13 @@ #ifndef _DRM_H_ #define _DRM_H_ -#if defined(__linux__) +#if defined(__KERNEL__) + +#include +#include +typedef unsigned int drm_handle_t; + +#elif defined(__linux__) #include #include @@ -63,6 +69,10 @@ typedef unsigned long drm_handle_t; extern "C" { #endif +#ifndef __user +#define __user +#endif + #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ @@ -135,11 +145,11 @@ struct drm_version { int version_minor; /**< Minor version */ int version_patchlevel; /**< Patch level */ __kernel_size_t name_len; /**< Length of name buffer */ - char *name; /**< Name of driver */ + char __user *name; /**< Name of driver */ __kernel_size_t date_len; /**< Length of date buffer */ - char *date; /**< User-space buffer to hold date */ + char __user *date; /**< User-space buffer to hold date */ __kernel_size_t desc_len; /**< Length of desc buffer */ - char *desc; /**< User-space buffer to hold desc */ + char __user *desc; /**< User-space buffer to hold desc */ }; /** @@ -149,12 +159,12 @@ struct drm_version { */ struct drm_unique { __kernel_size_t unique_len; /**< Length of unique */ - char *unique; /**< Unique name for driver instantiation */ + char __user *unique; /**< Unique name for driver instantiation */ }; struct drm_list { int count; /**< Length of user-space structures */ - struct drm_version *version; + struct drm_version __user *version; }; struct drm_block { @@ -349,7 +359,7 @@ struct drm_buf_desc { */ struct drm_buf_info { int count; /**< Entries in list */ - struct drm_buf_desc *list; + struct drm_buf_desc __user *list; }; /** @@ -357,7 +367,7 @@ struct drm_buf_info { */ struct drm_buf_free { int count; - int *list; + int __user *list; }; /** @@ -369,7 +379,7 @@ struct drm_buf_pub { int idx; /**< Index into the master buffer list */ int total; /**< Buffer size */ int used; /**< Amount of buffer in use (for DMA) */ - void *address; /**< Address of buffer */ + void __user *address; /**< Address of buffer */ }; /** @@ -378,11 +388,11 @@ struct drm_buf_pub { struct drm_buf_map { int count; /**< Length of the buffer list */ #ifdef __cplusplus - void *virt; + void __user *virt; #else - void *virtual; /**< Mmap'd area in user-virtual */ + void __user *virtual; /**< Mmap'd area in user-virtual */ #endif - struct drm_buf_pub *list; /**< Buffer information */ + struct drm_buf_pub __user *list; /**< Buffer information */ }; /** @@ -395,13 +405,13 @@ struct drm_buf_map { struct drm_dma { int context; /**< Context handle */ int send_count; /**< Number of buffers to send */ - int *send_indices; /**< List of handles to buffers */ - int *send_sizes; /**< Lengths of data to send */ + int __user *send_indices; /**< List of handles to buffers */ + int __user *send_sizes; /**< Lengths of data to send */ enum drm_dma_flags flags; /**< Flags */ int request_count; /**< Number of buffers requested */ int request_size; /**< Desired size for buffers */ - int *request_indices; /**< Buffer information */ - int *request_sizes; + int __user *request_indices; /**< Buffer information */ + int __user *request_sizes; int granted_count; /**< Number of buffers granted */ }; @@ -425,7 +435,7 @@ struct drm_ctx { */ struct drm_ctx_res { int count; - struct drm_ctx *contexts; + struct drm_ctx __user *contexts; }; /** @@ -939,6 +949,7 @@ struct drm_event_crtc_sequence { }; /* typedef area */ +#ifndef __KERNEL__ typedef struct drm_clip_rect drm_clip_rect_t; typedef struct drm_drawable_info drm_drawable_info_t; typedef struct drm_tex_region drm_tex_region_t; @@ -980,6 +991,7 @@ typedef struct drm_agp_binding drm_agp_binding_t; typedef struct drm_agp_info drm_agp_info_t; typedef struct drm_scatter_gather drm_scatter_gather_t; typedef struct drm_set_version drm_set_version_t; +#endif #if defined(__cplusplus) } diff --git a/external/include/drm/drm_mode.h b/external/include/drm/drm_mode.h index 5597a87..50bcf42 100644 --- a/external/include/drm/drm_mode.h +++ b/external/include/drm/drm_mode.h @@ -38,14 +38,18 @@ extern "C" { #define DRM_DISPLAY_MODE_LEN 32 #define DRM_PROP_NAME_LEN 32 -#define DRM_MODE_TYPE_BUILTIN (1<<0) -#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN) -#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN) +#define DRM_MODE_TYPE_BUILTIN (1<<0) /* deprecated */ +#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN) /* deprecated */ +#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN) /* deprecated */ #define DRM_MODE_TYPE_PREFERRED (1<<3) -#define DRM_MODE_TYPE_DEFAULT (1<<4) +#define DRM_MODE_TYPE_DEFAULT (1<<4) /* deprecated */ #define DRM_MODE_TYPE_USERDEF (1<<5) #define DRM_MODE_TYPE_DRIVER (1<<6) +#define DRM_MODE_TYPE_ALL (DRM_MODE_TYPE_PREFERRED | \ + DRM_MODE_TYPE_USERDEF | \ + DRM_MODE_TYPE_DRIVER) + /* Video mode flags */ /* bit compatible with the xrandr RR_ definitions (bits 0-13) * @@ -66,8 +70,8 @@ extern "C" { #define DRM_MODE_FLAG_PCSYNC (1<<7) #define DRM_MODE_FLAG_NCSYNC (1<<8) #define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */ -#define DRM_MODE_FLAG_BCAST (1<<10) -#define DRM_MODE_FLAG_PIXMUX (1<<11) +#define DRM_MODE_FLAG_BCAST (1<<10) /* deprecated */ +#define DRM_MODE_FLAG_PIXMUX (1<<11) /* deprecated */ #define DRM_MODE_FLAG_DBLCLK (1<<12) #define DRM_MODE_FLAG_CLKDIV2 (1<<13) /* @@ -99,6 +103,20 @@ extern "C" { #define DRM_MODE_FLAG_PIC_AR_16_9 \ (DRM_MODE_PICTURE_ASPECT_16_9<<19) +#define DRM_MODE_FLAG_ALL (DRM_MODE_FLAG_PHSYNC | \ + DRM_MODE_FLAG_NHSYNC | \ + DRM_MODE_FLAG_PVSYNC | \ + DRM_MODE_FLAG_NVSYNC | \ + DRM_MODE_FLAG_INTERLACE | \ + DRM_MODE_FLAG_DBLSCAN | \ + DRM_MODE_FLAG_CSYNC | \ + DRM_MODE_FLAG_PCSYNC | \ + DRM_MODE_FLAG_NCSYNC | \ + DRM_MODE_FLAG_HSKEW | \ + DRM_MODE_FLAG_DBLCLK | \ + DRM_MODE_FLAG_CLKDIV2 | \ + DRM_MODE_FLAG_3D_MASK) + /* DPMS flags */ /* bit compatible with the xorg definitions. */ #define DRM_MODE_DPMS_ON 0 @@ -173,6 +191,10 @@ extern "C" { DRM_MODE_REFLECT_X | \ DRM_MODE_REFLECT_Y) +/* Content Protection Flags */ +#define DRM_MODE_CONTENT_PROTECTION_UNDESIRED 0 +#define DRM_MODE_CONTENT_PROTECTION_DESIRED 1 +#define DRM_MODE_CONTENT_PROTECTION_ENABLED 2 struct drm_mode_modeinfo { __u32 clock; @@ -341,7 +363,7 @@ struct drm_mode_get_connector { __u32 pad; }; -#define DRM_MODE_PROP_PENDING (1<<0) +#define DRM_MODE_PROP_PENDING (1<<0) /* deprecated, do not use */ #define DRM_MODE_PROP_RANGE (1<<1) #define DRM_MODE_PROP_IMMUTABLE (1<<2) #define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */ @@ -576,8 +598,11 @@ struct drm_mode_crtc_lut { }; struct drm_color_ctm { - /* Conversion matrix in S31.32 format. */ - __s64 matrix[9]; + /* + * Conversion matrix in S31.32 sign-magnitude + * (not two's complement!) format. + */ + __u64 matrix[9]; }; struct drm_color_lut { diff --git a/external/include/drm/drm_sarea.h b/external/include/drm/drm_sarea.h deleted file mode 100644 index 93025be..0000000 --- a/external/include/drm/drm_sarea.h +++ /dev/null @@ -1,92 +0,0 @@ -/** - * \file drm_sarea.h - * \brief SAREA definitions - * - * \author Michel Dänzer - */ - -/* - * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DRM_SAREA_H_ -#define _DRM_SAREA_H_ - -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/* SAREA area needs to be at least a page */ -#if defined(__alpha__) -#define SAREA_MAX 0x2000U -#elif defined(__mips__) -#define SAREA_MAX 0x4000U -#elif defined(__ia64__) -#define SAREA_MAX 0x10000U /* 64kB */ -#else -/* Intel 830M driver needs at least 8k SAREA */ -#define SAREA_MAX 0x2000U -#endif - -/** Maximum number of drawables in the SAREA */ -#define SAREA_MAX_DRAWABLES 256 - -#define SAREA_DRAWABLE_CLAIMED_ENTRY 0x80000000 - -/** SAREA drawable */ -struct drm_sarea_drawable { - unsigned int stamp; - unsigned int flags; -}; - -/** SAREA frame */ -struct drm_sarea_frame { - unsigned int x; - unsigned int y; - unsigned int width; - unsigned int height; - unsigned int fullscreen; -}; - -/** SAREA */ -struct drm_sarea { - /** first thing is always the DRM locking structure */ - struct drm_hw_lock lock; - /** \todo Use readers/writer lock for drm_sarea::drawable_lock */ - struct drm_hw_lock drawable_lock; - struct drm_sarea_drawable drawableTable[SAREA_MAX_DRAWABLES]; /**< drawables */ - struct drm_sarea_frame frame; /**< frame */ - drm_context_t dummy_context; -}; - -typedef struct drm_sarea_drawable drm_sarea_drawable_t; -typedef struct drm_sarea_frame drm_sarea_frame_t; -typedef struct drm_sarea drm_sarea_t; - -#if defined(__cplusplus) -} -#endif - -#endif /* _DRM_SAREA_H_ */ diff --git a/external/include/drm/i915_drm.h b/external/include/drm/i915_drm.h deleted file mode 100644 index 5ebe046..0000000 --- a/external/include/drm/i915_drm.h +++ /dev/null @@ -1,1431 +0,0 @@ -/* - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _I915_DRM_H_ -#define _I915_DRM_H_ - -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/* Please note that modifications to all structs defined here are - * subject to backwards-compatibility constraints. - */ - -/** - * DOC: uevents generated by i915 on it's device node - * - * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch - * event from the gpu l3 cache. Additional information supplied is ROW, - * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep - * track of these events and if a specific cache-line seems to have a - * persistent error remap it with the l3 remapping tool supplied in - * intel-gpu-tools. The value supplied with the event is always 1. - * - * I915_ERROR_UEVENT - Generated upon error detection, currently only via - * hangcheck. The error detection event is a good indicator of when things - * began to go badly. The value supplied with the event is a 1 upon error - * detection, and a 0 upon reset completion, signifying no more error - * exists. NOTE: Disabling hangcheck or reset via module parameter will - * cause the related events to not be seen. - * - * I915_RESET_UEVENT - Event is generated just before an attempt to reset the - * the GPU. The value supplied with the event is always 1. NOTE: Disable - * reset via module parameter will cause this event to not be seen. - */ -#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" -#define I915_ERROR_UEVENT "ERROR" -#define I915_RESET_UEVENT "RESET" - -/* - * MOCS indexes used for GPU surfaces, defining the cacheability of the - * surface data and the coherency for this data wrt. CPU vs. GPU accesses. - */ -enum i915_mocs_table_index { - /* - * Not cached anywhere, coherency between CPU and GPU accesses is - * guaranteed. - */ - I915_MOCS_UNCACHED, - /* - * Cacheability and coherency controlled by the kernel automatically - * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current - * usage of the surface (used for display scanout or not). - */ - I915_MOCS_PTE, - /* - * Cached in all GPU caches available on the platform. - * Coherency between CPU and GPU accesses to the surface is not - * guaranteed without extra synchronization. - */ - I915_MOCS_CACHED, -}; - -/* Each region is a minimum of 16k, and there are at most 255 of them. - */ -#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use - * of chars for next/prev indices */ -#define I915_LOG_MIN_TEX_REGION_SIZE 14 - -typedef struct _drm_i915_init { - enum { - I915_INIT_DMA = 0x01, - I915_CLEANUP_DMA = 0x02, - I915_RESUME_DMA = 0x03 - } func; - unsigned int mmio_offset; - int sarea_priv_offset; - unsigned int ring_start; - unsigned int ring_end; - unsigned int ring_size; - unsigned int front_offset; - unsigned int back_offset; - unsigned int depth_offset; - unsigned int w; - unsigned int h; - unsigned int pitch; - unsigned int pitch_bits; - unsigned int back_pitch; - unsigned int depth_pitch; - unsigned int cpp; - unsigned int chipset; -} drm_i915_init_t; - -typedef struct _drm_i915_sarea { - struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; - int last_upload; /* last time texture was uploaded */ - int last_enqueue; /* last time a buffer was enqueued */ - int last_dispatch; /* age of the most recently dispatched buffer */ - int ctxOwner; /* last context to upload state */ - int texAge; - int pf_enabled; /* is pageflipping allowed? */ - int pf_active; - int pf_current_page; /* which buffer is being displayed? */ - int perf_boxes; /* performance boxes to be displayed */ - int width, height; /* screen size in pixels */ - - drm_handle_t front_handle; - int front_offset; - int front_size; - - drm_handle_t back_handle; - int back_offset; - int back_size; - - drm_handle_t depth_handle; - int depth_offset; - int depth_size; - - drm_handle_t tex_handle; - int tex_offset; - int tex_size; - int log_tex_granularity; - int pitch; - int rotation; /* 0, 90, 180 or 270 */ - int rotated_offset; - int rotated_size; - int rotated_pitch; - int virtualX, virtualY; - - unsigned int front_tiled; - unsigned int back_tiled; - unsigned int depth_tiled; - unsigned int rotated_tiled; - unsigned int rotated2_tiled; - - int pipeA_x; - int pipeA_y; - int pipeA_w; - int pipeA_h; - int pipeB_x; - int pipeB_y; - int pipeB_w; - int pipeB_h; - - /* fill out some space for old userspace triple buffer */ - drm_handle_t unused_handle; - __u32 unused1, unused2, unused3; - - /* buffer object handles for static buffers. May change - * over the lifetime of the client. - */ - __u32 front_bo_handle; - __u32 back_bo_handle; - __u32 unused_bo_handle; - __u32 depth_bo_handle; - -} drm_i915_sarea_t; - -/* due to userspace building against these headers we need some compat here */ -#define planeA_x pipeA_x -#define planeA_y pipeA_y -#define planeA_w pipeA_w -#define planeA_h pipeA_h -#define planeB_x pipeB_x -#define planeB_y pipeB_y -#define planeB_w pipeB_w -#define planeB_h pipeB_h - -/* Flags for perf_boxes - */ -#define I915_BOX_RING_EMPTY 0x1 -#define I915_BOX_FLIP 0x2 -#define I915_BOX_WAIT 0x4 -#define I915_BOX_TEXTURE_LOAD 0x8 -#define I915_BOX_LOST_CONTEXT 0x10 - -/* - * i915 specific ioctls. - * - * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie - * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset - * against DRM_COMMAND_BASE and should be between [0x0, 0x60). - */ -#define DRM_I915_INIT 0x00 -#define DRM_I915_FLUSH 0x01 -#define DRM_I915_FLIP 0x02 -#define DRM_I915_BATCHBUFFER 0x03 -#define DRM_I915_IRQ_EMIT 0x04 -#define DRM_I915_IRQ_WAIT 0x05 -#define DRM_I915_GETPARAM 0x06 -#define DRM_I915_SETPARAM 0x07 -#define DRM_I915_ALLOC 0x08 -#define DRM_I915_FREE 0x09 -#define DRM_I915_INIT_HEAP 0x0a -#define DRM_I915_CMDBUFFER 0x0b -#define DRM_I915_DESTROY_HEAP 0x0c -#define DRM_I915_SET_VBLANK_PIPE 0x0d -#define DRM_I915_GET_VBLANK_PIPE 0x0e -#define DRM_I915_VBLANK_SWAP 0x0f -#define DRM_I915_HWS_ADDR 0x11 -#define DRM_I915_GEM_INIT 0x13 -#define DRM_I915_GEM_EXECBUFFER 0x14 -#define DRM_I915_GEM_PIN 0x15 -#define DRM_I915_GEM_UNPIN 0x16 -#define DRM_I915_GEM_BUSY 0x17 -#define DRM_I915_GEM_THROTTLE 0x18 -#define DRM_I915_GEM_ENTERVT 0x19 -#define DRM_I915_GEM_LEAVEVT 0x1a -#define DRM_I915_GEM_CREATE 0x1b -#define DRM_I915_GEM_PREAD 0x1c -#define DRM_I915_GEM_PWRITE 0x1d -#define DRM_I915_GEM_MMAP 0x1e -#define DRM_I915_GEM_SET_DOMAIN 0x1f -#define DRM_I915_GEM_SW_FINISH 0x20 -#define DRM_I915_GEM_SET_TILING 0x21 -#define DRM_I915_GEM_GET_TILING 0x22 -#define DRM_I915_GEM_GET_APERTURE 0x23 -#define DRM_I915_GEM_MMAP_GTT 0x24 -#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 -#define DRM_I915_GEM_MADVISE 0x26 -#define DRM_I915_OVERLAY_PUT_IMAGE 0x27 -#define DRM_I915_OVERLAY_ATTRS 0x28 -#define DRM_I915_GEM_EXECBUFFER2 0x29 -#define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2 -#define DRM_I915_GET_SPRITE_COLORKEY 0x2a -#define DRM_I915_SET_SPRITE_COLORKEY 0x2b -#define DRM_I915_GEM_WAIT 0x2c -#define DRM_I915_GEM_CONTEXT_CREATE 0x2d -#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e -#define DRM_I915_GEM_SET_CACHING 0x2f -#define DRM_I915_GEM_GET_CACHING 0x30 -#define DRM_I915_REG_READ 0x31 -#define DRM_I915_GET_RESET_STATS 0x32 -#define DRM_I915_GEM_USERPTR 0x33 -#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 -#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 -#define DRM_I915_PERF_OPEN 0x36 - -#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) -#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) -#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) -#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) -#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) -#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) -#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) -#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) -#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) -#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) -#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) -#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) -#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) -#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) -#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) -#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) -#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) -#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) -#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) -#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) -#define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2) -#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) -#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) -#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) -#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) -#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) -#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) -#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) -#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) -#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) -#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) -#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) -#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) -#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) -#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) -#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) -#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) -#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) -#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) -#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) -#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) -#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) -#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) -#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) -#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) -#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) -#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) -#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) -#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) -#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) -#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) -#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) -#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) -#define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) - -/* Allow drivers to submit batchbuffers directly to hardware, relying - * on the security mechanisms provided by hardware. - */ -typedef struct drm_i915_batchbuffer { - int start; /* agp offset */ - int used; /* nr bytes in use */ - int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ - int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ - int num_cliprects; /* mulitpass with multiple cliprects? */ - struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */ -} drm_i915_batchbuffer_t; - -/* As above, but pass a pointer to userspace buffer which can be - * validated by the kernel prior to sending to hardware. - */ -typedef struct _drm_i915_cmdbuffer { - char *buf; /* pointer to userspace command buffer */ - int sz; /* nr bytes in buf */ - int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ - int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ - int num_cliprects; /* mulitpass with multiple cliprects? */ - struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */ -} drm_i915_cmdbuffer_t; - -/* Userspace can request & wait on irq's: - */ -typedef struct drm_i915_irq_emit { - int *irq_seq; -} drm_i915_irq_emit_t; - -typedef struct drm_i915_irq_wait { - int irq_seq; -} drm_i915_irq_wait_t; - -/* Ioctl to query kernel params: - */ -#define I915_PARAM_IRQ_ACTIVE 1 -#define I915_PARAM_ALLOW_BATCHBUFFER 2 -#define I915_PARAM_LAST_DISPATCH 3 -#define I915_PARAM_CHIPSET_ID 4 -#define I915_PARAM_HAS_GEM 5 -#define I915_PARAM_NUM_FENCES_AVAIL 6 -#define I915_PARAM_HAS_OVERLAY 7 -#define I915_PARAM_HAS_PAGEFLIPPING 8 -#define I915_PARAM_HAS_EXECBUF2 9 -#define I915_PARAM_HAS_BSD 10 -#define I915_PARAM_HAS_BLT 11 -#define I915_PARAM_HAS_RELAXED_FENCING 12 -#define I915_PARAM_HAS_COHERENT_RINGS 13 -#define I915_PARAM_HAS_EXEC_CONSTANTS 14 -#define I915_PARAM_HAS_RELAXED_DELTA 15 -#define I915_PARAM_HAS_GEN7_SOL_RESET 16 -#define I915_PARAM_HAS_LLC 17 -#define I915_PARAM_HAS_ALIASING_PPGTT 18 -#define I915_PARAM_HAS_WAIT_TIMEOUT 19 -#define I915_PARAM_HAS_SEMAPHORES 20 -#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 -#define I915_PARAM_HAS_VEBOX 22 -#define I915_PARAM_HAS_SECURE_BATCHES 23 -#define I915_PARAM_HAS_PINNED_BATCHES 24 -#define I915_PARAM_HAS_EXEC_NO_RELOC 25 -#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 -#define I915_PARAM_HAS_WT 27 -#define I915_PARAM_CMD_PARSER_VERSION 28 -#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 -#define I915_PARAM_MMAP_VERSION 30 -#define I915_PARAM_HAS_BSD2 31 -#define I915_PARAM_REVISION 32 -#define I915_PARAM_SUBSLICE_TOTAL 33 -#define I915_PARAM_EU_TOTAL 34 -#define I915_PARAM_HAS_GPU_RESET 35 -#define I915_PARAM_HAS_RESOURCE_STREAMER 36 -#define I915_PARAM_HAS_EXEC_SOFTPIN 37 -#define I915_PARAM_HAS_POOLED_EU 38 -#define I915_PARAM_MIN_EU_IN_POOL 39 -#define I915_PARAM_MMAP_GTT_VERSION 40 - -/* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution - * priorities and the driver will attempt to execute batches in priority order. - */ -#define I915_PARAM_HAS_SCHEDULER 41 -#define I915_PARAM_HUC_STATUS 42 - -/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of - * synchronisation with implicit fencing on individual objects. - * See EXEC_OBJECT_ASYNC. - */ -#define I915_PARAM_HAS_EXEC_ASYNC 43 - -/* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support - - * both being able to pass in a sync_file fd to wait upon before executing, - * and being able to return a new sync_file fd that is signaled when the - * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT. - */ -#define I915_PARAM_HAS_EXEC_FENCE 44 - -typedef struct drm_i915_getparam { - __s32 param; - /* - * WARNING: Using pointers instead of fixed-size u64 means we need to write - * compat32 code. Don't repeat this mistake. - */ - int *value; -} drm_i915_getparam_t; - -/* Ioctl to set kernel params: - */ -#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 -#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 -#define I915_SETPARAM_ALLOW_BATCHBUFFER 3 -#define I915_SETPARAM_NUM_USED_FENCES 4 - -typedef struct drm_i915_setparam { - int param; - int value; -} drm_i915_setparam_t; - -/* A memory manager for regions of shared memory: - */ -#define I915_MEM_REGION_AGP 1 - -typedef struct drm_i915_mem_alloc { - int region; - int alignment; - int size; - int *region_offset; /* offset from start of fb or agp */ -} drm_i915_mem_alloc_t; - -typedef struct drm_i915_mem_free { - int region; - int region_offset; -} drm_i915_mem_free_t; - -typedef struct drm_i915_mem_init_heap { - int region; - int size; - int start; -} drm_i915_mem_init_heap_t; - -/* Allow memory manager to be torn down and re-initialized (eg on - * rotate): - */ -typedef struct drm_i915_mem_destroy_heap { - int region; -} drm_i915_mem_destroy_heap_t; - -/* Allow X server to configure which pipes to monitor for vblank signals - */ -#define DRM_I915_VBLANK_PIPE_A 1 -#define DRM_I915_VBLANK_PIPE_B 2 - -typedef struct drm_i915_vblank_pipe { - int pipe; -} drm_i915_vblank_pipe_t; - -/* Schedule buffer swap at given vertical blank: - */ -typedef struct drm_i915_vblank_swap { - drm_drawable_t drawable; - enum drm_vblank_seq_type seqtype; - unsigned int sequence; -} drm_i915_vblank_swap_t; - -typedef struct drm_i915_hws_addr { - __u64 addr; -} drm_i915_hws_addr_t; - -struct drm_i915_gem_init { - /** - * Beginning offset in the GTT to be managed by the DRM memory - * manager. - */ - __u64 gtt_start; - /** - * Ending offset in the GTT to be managed by the DRM memory - * manager. - */ - __u64 gtt_end; -}; - -struct drm_i915_gem_create { - /** - * Requested size for the object. - * - * The (page-aligned) allocated size for the object will be returned. - */ - __u64 size; - /** - * Returned handle for the object. - * - * Object handles are nonzero. - */ - __u32 handle; - __u32 pad; -}; - -struct drm_i915_gem_pread { - /** Handle for the object being read. */ - __u32 handle; - __u32 pad; - /** Offset into the object to read from */ - __u64 offset; - /** Length of data to read */ - __u64 size; - /** - * Pointer to write the data into. - * - * This is a fixed-size type for 32/64 compatibility. - */ - __u64 data_ptr; -}; - -struct drm_i915_gem_pwrite { - /** Handle for the object being written to. */ - __u32 handle; - __u32 pad; - /** Offset into the object to write to */ - __u64 offset; - /** Length of data to write */ - __u64 size; - /** - * Pointer to read the data from. - * - * This is a fixed-size type for 32/64 compatibility. - */ - __u64 data_ptr; -}; - -struct drm_i915_gem_mmap { - /** Handle for the object being mapped. */ - __u32 handle; - __u32 pad; - /** Offset in the object to map. */ - __u64 offset; - /** - * Length of data to map. - * - * The value will be page-aligned. - */ - __u64 size; - /** - * Returned pointer the data was mapped at. - * - * This is a fixed-size type for 32/64 compatibility. - */ - __u64 addr_ptr; - - /** - * Flags for extended behaviour. - * - * Added in version 2. - */ - __u64 flags; -#define I915_MMAP_WC 0x1 -}; - -struct drm_i915_gem_mmap_gtt { - /** Handle for the object being mapped. */ - __u32 handle; - __u32 pad; - /** - * Fake offset to use for subsequent mmap call - * - * This is a fixed-size type for 32/64 compatibility. - */ - __u64 offset; -}; - -struct drm_i915_gem_set_domain { - /** Handle for the object */ - __u32 handle; - - /** New read domains */ - __u32 read_domains; - - /** New write domain */ - __u32 write_domain; -}; - -struct drm_i915_gem_sw_finish { - /** Handle for the object */ - __u32 handle; -}; - -struct drm_i915_gem_relocation_entry { - /** - * Handle of the buffer being pointed to by this relocation entry. - * - * It's appealing to make this be an index into the mm_validate_entry - * list to refer to the buffer, but this allows the driver to create - * a relocation list for state buffers and not re-write it per - * exec using the buffer. - */ - __u32 target_handle; - - /** - * Value to be added to the offset of the target buffer to make up - * the relocation entry. - */ - __u32 delta; - - /** Offset in the buffer the relocation entry will be written into */ - __u64 offset; - - /** - * Offset value of the target buffer that the relocation entry was last - * written as. - * - * If the buffer has the same offset as last time, we can skip syncing - * and writing the relocation. This value is written back out by - * the execbuffer ioctl when the relocation is written. - */ - __u64 presumed_offset; - - /** - * Target memory domains read by this operation. - */ - __u32 read_domains; - - /** - * Target memory domains written by this operation. - * - * Note that only one domain may be written by the whole - * execbuffer operation, so that where there are conflicts, - * the application will get -EINVAL back. - */ - __u32 write_domain; -}; - -/** @{ - * Intel memory domains - * - * Most of these just align with the various caches in - * the system and are used to flush and invalidate as - * objects end up cached in different domains. - */ -/** CPU cache */ -#define I915_GEM_DOMAIN_CPU 0x00000001 -/** Render cache, used by 2D and 3D drawing */ -#define I915_GEM_DOMAIN_RENDER 0x00000002 -/** Sampler cache, used by texture engine */ -#define I915_GEM_DOMAIN_SAMPLER 0x00000004 -/** Command queue, used to load batch buffers */ -#define I915_GEM_DOMAIN_COMMAND 0x00000008 -/** Instruction cache, used by shader programs */ -#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 -/** Vertex address cache */ -#define I915_GEM_DOMAIN_VERTEX 0x00000020 -/** GTT domain - aperture and scanout */ -#define I915_GEM_DOMAIN_GTT 0x00000040 -/** @} */ - -struct drm_i915_gem_exec_object { - /** - * User's handle for a buffer to be bound into the GTT for this - * operation. - */ - __u32 handle; - - /** Number of relocations to be performed on this buffer */ - __u32 relocation_count; - /** - * Pointer to array of struct drm_i915_gem_relocation_entry containing - * the relocations to be performed in this buffer. - */ - __u64 relocs_ptr; - - /** Required alignment in graphics aperture */ - __u64 alignment; - - /** - * Returned value of the updated offset of the object, for future - * presumed_offset writes. - */ - __u64 offset; -}; - -struct drm_i915_gem_execbuffer { - /** - * List of buffers to be validated with their relocations to be - * performend on them. - * - * This is a pointer to an array of struct drm_i915_gem_validate_entry. - * - * These buffers must be listed in an order such that all relocations - * a buffer is performing refer to buffers that have already appeared - * in the validate list. - */ - __u64 buffers_ptr; - __u32 buffer_count; - - /** Offset in the batchbuffer to start execution from. */ - __u32 batch_start_offset; - /** Bytes used in batchbuffer from batch_start_offset */ - __u32 batch_len; - __u32 DR1; - __u32 DR4; - __u32 num_cliprects; - /** This is a struct drm_clip_rect *cliprects */ - __u64 cliprects_ptr; -}; - -struct drm_i915_gem_exec_object2 { - /** - * User's handle for a buffer to be bound into the GTT for this - * operation. - */ - __u32 handle; - - /** Number of relocations to be performed on this buffer */ - __u32 relocation_count; - /** - * Pointer to array of struct drm_i915_gem_relocation_entry containing - * the relocations to be performed in this buffer. - */ - __u64 relocs_ptr; - - /** Required alignment in graphics aperture */ - __u64 alignment; - - /** - * When the EXEC_OBJECT_PINNED flag is specified this is populated by - * the user with the GTT offset at which this object will be pinned. - * When the I915_EXEC_NO_RELOC flag is specified this must contain the - * presumed_offset of the object. - * During execbuffer2 the kernel populates it with the value of the - * current GTT offset of the object, for future presumed_offset writes. - */ - __u64 offset; - -#define EXEC_OBJECT_NEEDS_FENCE (1<<0) -#define EXEC_OBJECT_NEEDS_GTT (1<<1) -#define EXEC_OBJECT_WRITE (1<<2) -#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3) -#define EXEC_OBJECT_PINNED (1<<4) -#define EXEC_OBJECT_PAD_TO_SIZE (1<<5) -/* The kernel implicitly tracks GPU activity on all GEM objects, and - * synchronises operations with outstanding rendering. This includes - * rendering on other devices if exported via dma-buf. However, sometimes - * this tracking is too coarse and the user knows better. For example, - * if the object is split into non-overlapping ranges shared between different - * clients or engines (i.e. suballocating objects), the implicit tracking - * by kernel assumes that each operation affects the whole object rather - * than an individual range, causing needless synchronisation between clients. - * The kernel will also forgo any CPU cache flushes prior to rendering from - * the object as the client is expected to be also handling such domain - * tracking. - * - * The kernel maintains the implicit tracking in order to manage resources - * used by the GPU - this flag only disables the synchronisation prior to - * rendering with this object in this execbuf. - * - * Opting out of implicit synhronisation requires the user to do its own - * explicit tracking to avoid rendering corruption. See, for example, - * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously. - */ -#define EXEC_OBJECT_ASYNC (1<<6) -/* All remaining bits are MBZ and RESERVED FOR FUTURE USE */ -#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_ASYNC<<1) - __u64 flags; - - union { - __u64 rsvd1; - __u64 pad_to_size; - }; - __u64 rsvd2; -}; - -struct drm_i915_gem_execbuffer2 { - /** - * List of gem_exec_object2 structs - */ - __u64 buffers_ptr; - __u32 buffer_count; - - /** Offset in the batchbuffer to start execution from. */ - __u32 batch_start_offset; - /** Bytes used in batchbuffer from batch_start_offset */ - __u32 batch_len; - __u32 DR1; - __u32 DR4; - __u32 num_cliprects; - /** This is a struct drm_clip_rect *cliprects */ - __u64 cliprects_ptr; -#define I915_EXEC_RING_MASK (7<<0) -#define I915_EXEC_DEFAULT (0<<0) -#define I915_EXEC_RENDER (1<<0) -#define I915_EXEC_BSD (2<<0) -#define I915_EXEC_BLT (3<<0) -#define I915_EXEC_VEBOX (4<<0) - -/* Used for switching the constants addressing mode on gen4+ RENDER ring. - * Gen6+ only supports relative addressing to dynamic state (default) and - * absolute addressing. - * - * These flags are ignored for the BSD and BLT rings. - */ -#define I915_EXEC_CONSTANTS_MASK (3<<6) -#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ -#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) -#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ - __u64 flags; - __u64 rsvd1; /* now used for context info */ - __u64 rsvd2; -}; - -/** Resets the SO write offset registers for transform feedback on gen7. */ -#define I915_EXEC_GEN7_SOL_RESET (1<<8) - -/** Request a privileged ("secure") batch buffer. Note only available for - * DRM_ROOT_ONLY | DRM_MASTER processes. - */ -#define I915_EXEC_SECURE (1<<9) - -/** Inform the kernel that the batch is and will always be pinned. This - * negates the requirement for a workaround to be performed to avoid - * an incoherent CS (such as can be found on 830/845). If this flag is - * not passed, the kernel will endeavour to make sure the batch is - * coherent with the CS before execution. If this flag is passed, - * userspace assumes the responsibility for ensuring the same. - */ -#define I915_EXEC_IS_PINNED (1<<10) - -/** Provide a hint to the kernel that the command stream and auxiliary - * state buffers already holds the correct presumed addresses and so the - * relocation process may be skipped if no buffers need to be moved in - * preparation for the execbuffer. - */ -#define I915_EXEC_NO_RELOC (1<<11) - -/** Use the reloc.handle as an index into the exec object array rather - * than as the per-file handle. - */ -#define I915_EXEC_HANDLE_LUT (1<<12) - -/** Used for switching BSD rings on the platforms with two BSD rings */ -#define I915_EXEC_BSD_SHIFT (13) -#define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT) -/* default ping-pong mode */ -#define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT) -#define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT) -#define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT) - -/** Tell the kernel that the batchbuffer is processed by - * the resource streamer. - */ -#define I915_EXEC_RESOURCE_STREAMER (1<<15) - -/* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent - * a sync_file fd to wait upon (in a nonblocking manner) prior to executing - * the batch. - * - * Returns -EINVAL if the sync_file fd cannot be found. - */ -#define I915_EXEC_FENCE_IN (1<<16) - -/* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd - * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given - * to the caller, and it should be close() after use. (The fd is a regular - * file descriptor and will be cleaned up on process termination. It holds - * a reference to the request, but nothing else.) - * - * The sync_file fd can be combined with other sync_file and passed either - * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip - * will only occur after this request completes), or to other devices. - * - * Using I915_EXEC_FENCE_OUT requires use of - * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written - * back to userspace. Failure to do so will cause the out-fence to always - * be reported as zero, and the real fence fd to be leaked. - */ -#define I915_EXEC_FENCE_OUT (1<<17) - -#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_OUT<<1)) - -#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) -#define i915_execbuffer2_set_context_id(eb2, context) \ - (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK -#define i915_execbuffer2_get_context_id(eb2) \ - ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) - -struct drm_i915_gem_pin { - /** Handle of the buffer to be pinned. */ - __u32 handle; - __u32 pad; - - /** alignment required within the aperture */ - __u64 alignment; - - /** Returned GTT offset of the buffer. */ - __u64 offset; -}; - -struct drm_i915_gem_unpin { - /** Handle of the buffer to be unpinned. */ - __u32 handle; - __u32 pad; -}; - -struct drm_i915_gem_busy { - /** Handle of the buffer to check for busy */ - __u32 handle; - - /** Return busy status - * - * A return of 0 implies that the object is idle (after - * having flushed any pending activity), and a non-zero return that - * the object is still in-flight on the GPU. (The GPU has not yet - * signaled completion for all pending requests that reference the - * object.) An object is guaranteed to become idle eventually (so - * long as no new GPU commands are executed upon it). Due to the - * asynchronous nature of the hardware, an object reported - * as busy may become idle before the ioctl is completed. - * - * Furthermore, if the object is busy, which engine is busy is only - * provided as a guide. There are race conditions which prevent the - * report of which engines are busy from being always accurate. - * However, the converse is not true. If the object is idle, the - * result of the ioctl, that all engines are idle, is accurate. - * - * The returned dword is split into two fields to indicate both - * the engines on which the object is being read, and the - * engine on which it is currently being written (if any). - * - * The low word (bits 0:15) indicate if the object is being written - * to by any engine (there can only be one, as the GEM implicit - * synchronisation rules force writes to be serialised). Only the - * engine for the last write is reported. - * - * The high word (bits 16:31) are a bitmask of which engines are - * currently reading from the object. Multiple engines may be - * reading from the object simultaneously. - * - * The value of each engine is the same as specified in the - * EXECBUFFER2 ioctl, i.e. I915_EXEC_RENDER, I915_EXEC_BSD etc. - * Note I915_EXEC_DEFAULT is a symbolic value and is mapped to - * the I915_EXEC_RENDER engine for execution, and so it is never - * reported as active itself. Some hardware may have parallel - * execution engines, e.g. multiple media engines, which are - * mapped to the same identifier in the EXECBUFFER2 ioctl and - * so are not separately reported for busyness. - * - * Caveat emptor: - * Only the boolean result of this query is reliable; that is whether - * the object is idle or busy. The report of which engines are busy - * should be only used as a heuristic. - */ - __u32 busy; -}; - -/** - * I915_CACHING_NONE - * - * GPU access is not coherent with cpu caches. Default for machines without an - * LLC. - */ -#define I915_CACHING_NONE 0 -/** - * I915_CACHING_CACHED - * - * GPU access is coherent with cpu caches and furthermore the data is cached in - * last-level caches shared between cpu cores and the gpu GT. Default on - * machines with HAS_LLC. - */ -#define I915_CACHING_CACHED 1 -/** - * I915_CACHING_DISPLAY - * - * Special GPU caching mode which is coherent with the scanout engines. - * Transparently falls back to I915_CACHING_NONE on platforms where no special - * cache mode (like write-through or gfdt flushing) is available. The kernel - * automatically sets this mode when using a buffer as a scanout target. - * Userspace can manually set this mode to avoid a costly stall and clflush in - * the hotpath of drawing the first frame. - */ -#define I915_CACHING_DISPLAY 2 - -struct drm_i915_gem_caching { - /** - * Handle of the buffer to set/get the caching level of. */ - __u32 handle; - - /** - * Cacheing level to apply or return value - * - * bits0-15 are for generic caching control (i.e. the above defined - * values). bits16-31 are reserved for platform-specific variations - * (e.g. l3$ caching on gen7). */ - __u32 caching; -}; - -#define I915_TILING_NONE 0 -#define I915_TILING_X 1 -#define I915_TILING_Y 2 -#define I915_TILING_LAST I915_TILING_Y - -#define I915_BIT_6_SWIZZLE_NONE 0 -#define I915_BIT_6_SWIZZLE_9 1 -#define I915_BIT_6_SWIZZLE_9_10 2 -#define I915_BIT_6_SWIZZLE_9_11 3 -#define I915_BIT_6_SWIZZLE_9_10_11 4 -/* Not seen by userland */ -#define I915_BIT_6_SWIZZLE_UNKNOWN 5 -/* Seen by userland. */ -#define I915_BIT_6_SWIZZLE_9_17 6 -#define I915_BIT_6_SWIZZLE_9_10_17 7 - -struct drm_i915_gem_set_tiling { - /** Handle of the buffer to have its tiling state updated */ - __u32 handle; - - /** - * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, - * I915_TILING_Y). - * - * This value is to be set on request, and will be updated by the - * kernel on successful return with the actual chosen tiling layout. - * - * The tiling mode may be demoted to I915_TILING_NONE when the system - * has bit 6 swizzling that can't be managed correctly by GEM. - * - * Buffer contents become undefined when changing tiling_mode. - */ - __u32 tiling_mode; - - /** - * Stride in bytes for the object when in I915_TILING_X or - * I915_TILING_Y. - */ - __u32 stride; - - /** - * Returned address bit 6 swizzling required for CPU access through - * mmap mapping. - */ - __u32 swizzle_mode; -}; - -struct drm_i915_gem_get_tiling { - /** Handle of the buffer to get tiling state for. */ - __u32 handle; - - /** - * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, - * I915_TILING_Y). - */ - __u32 tiling_mode; - - /** - * Returned address bit 6 swizzling required for CPU access through - * mmap mapping. - */ - __u32 swizzle_mode; - - /** - * Returned address bit 6 swizzling required for CPU access through - * mmap mapping whilst bound. - */ - __u32 phys_swizzle_mode; -}; - -struct drm_i915_gem_get_aperture { - /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ - __u64 aper_size; - - /** - * Available space in the aperture used by i915_gem_execbuffer, in - * bytes - */ - __u64 aper_available_size; -}; - -struct drm_i915_get_pipe_from_crtc_id { - /** ID of CRTC being requested **/ - __u32 crtc_id; - - /** pipe of requested CRTC **/ - __u32 pipe; -}; - -#define I915_MADV_WILLNEED 0 -#define I915_MADV_DONTNEED 1 -#define __I915_MADV_PURGED 2 /* internal state */ - -struct drm_i915_gem_madvise { - /** Handle of the buffer to change the backing store advice */ - __u32 handle; - - /* Advice: either the buffer will be needed again in the near future, - * or wont be and could be discarded under memory pressure. - */ - __u32 madv; - - /** Whether the backing store still exists. */ - __u32 retained; -}; - -/* flags */ -#define I915_OVERLAY_TYPE_MASK 0xff -#define I915_OVERLAY_YUV_PLANAR 0x01 -#define I915_OVERLAY_YUV_PACKED 0x02 -#define I915_OVERLAY_RGB 0x03 - -#define I915_OVERLAY_DEPTH_MASK 0xff00 -#define I915_OVERLAY_RGB24 0x1000 -#define I915_OVERLAY_RGB16 0x2000 -#define I915_OVERLAY_RGB15 0x3000 -#define I915_OVERLAY_YUV422 0x0100 -#define I915_OVERLAY_YUV411 0x0200 -#define I915_OVERLAY_YUV420 0x0300 -#define I915_OVERLAY_YUV410 0x0400 - -#define I915_OVERLAY_SWAP_MASK 0xff0000 -#define I915_OVERLAY_NO_SWAP 0x000000 -#define I915_OVERLAY_UV_SWAP 0x010000 -#define I915_OVERLAY_Y_SWAP 0x020000 -#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 - -#define I915_OVERLAY_FLAGS_MASK 0xff000000 -#define I915_OVERLAY_ENABLE 0x01000000 - -struct drm_intel_overlay_put_image { - /* various flags and src format description */ - __u32 flags; - /* source picture description */ - __u32 bo_handle; - /* stride values and offsets are in bytes, buffer relative */ - __u16 stride_Y; /* stride for packed formats */ - __u16 stride_UV; - __u32 offset_Y; /* offset for packet formats */ - __u32 offset_U; - __u32 offset_V; - /* in pixels */ - __u16 src_width; - __u16 src_height; - /* to compensate the scaling factors for partially covered surfaces */ - __u16 src_scan_width; - __u16 src_scan_height; - /* output crtc description */ - __u32 crtc_id; - __u16 dst_x; - __u16 dst_y; - __u16 dst_width; - __u16 dst_height; -}; - -/* flags */ -#define I915_OVERLAY_UPDATE_ATTRS (1<<0) -#define I915_OVERLAY_UPDATE_GAMMA (1<<1) -#define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2) -struct drm_intel_overlay_attrs { - __u32 flags; - __u32 color_key; - __s32 brightness; - __u32 contrast; - __u32 saturation; - __u32 gamma0; - __u32 gamma1; - __u32 gamma2; - __u32 gamma3; - __u32 gamma4; - __u32 gamma5; -}; - -/* - * Intel sprite handling - * - * Color keying works with a min/mask/max tuple. Both source and destination - * color keying is allowed. - * - * Source keying: - * Sprite pixels within the min & max values, masked against the color channels - * specified in the mask field, will be transparent. All other pixels will - * be displayed on top of the primary plane. For RGB surfaces, only the min - * and mask fields will be used; ranged compares are not allowed. - * - * Destination keying: - * Primary plane pixels that match the min value, masked against the color - * channels specified in the mask field, will be replaced by corresponding - * pixels from the sprite plane. - * - * Note that source & destination keying are exclusive; only one can be - * active on a given plane. - */ - -#define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ -#define I915_SET_COLORKEY_DESTINATION (1<<1) -#define I915_SET_COLORKEY_SOURCE (1<<2) -struct drm_intel_sprite_colorkey { - __u32 plane_id; - __u32 min_value; - __u32 channel_mask; - __u32 max_value; - __u32 flags; -}; - -struct drm_i915_gem_wait { - /** Handle of BO we shall wait on */ - __u32 bo_handle; - __u32 flags; - /** Number of nanoseconds to wait, Returns time remaining. */ - __s64 timeout_ns; -}; - -struct drm_i915_gem_context_create { - /* output: id of new context*/ - __u32 ctx_id; - __u32 pad; -}; - -struct drm_i915_gem_context_destroy { - __u32 ctx_id; - __u32 pad; -}; - -struct drm_i915_reg_read { - /* - * Register offset. - * For 64bit wide registers where the upper 32bits don't immediately - * follow the lower 32bits, the offset of the lower 32bits must - * be specified - */ - __u64 offset; - __u64 val; /* Return value */ -}; -/* Known registers: - * - * Render engine timestamp - 0x2358 + 64bit - gen7+ - * - Note this register returns an invalid value if using the default - * single instruction 8byte read, in order to workaround that use - * offset (0x2538 | 1) instead. - * - */ - -struct drm_i915_reset_stats { - __u32 ctx_id; - __u32 flags; - - /* All resets since boot/module reload, for all contexts */ - __u32 reset_count; - - /* Number of batches lost when active in GPU, for this context */ - __u32 batch_active; - - /* Number of batches lost pending for execution, for this context */ - __u32 batch_pending; - - __u32 pad; -}; - -struct drm_i915_gem_userptr { - __u64 user_ptr; - __u64 user_size; - __u32 flags; -#define I915_USERPTR_READ_ONLY 0x1 -#define I915_USERPTR_UNSYNCHRONIZED 0x80000000 - /** - * Returned handle for the object. - * - * Object handles are nonzero. - */ - __u32 handle; -}; - -struct drm_i915_gem_context_param { - __u32 ctx_id; - __u32 size; - __u64 param; -#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 -#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 -#define I915_CONTEXT_PARAM_GTT_SIZE 0x3 -#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 -#define I915_CONTEXT_PARAM_BANNABLE 0x5 - __u64 value; -}; - -enum drm_i915_oa_format { - I915_OA_FORMAT_A13 = 1, - I915_OA_FORMAT_A29, - I915_OA_FORMAT_A13_B8_C8, - I915_OA_FORMAT_B4_C8, - I915_OA_FORMAT_A45_B8_C8, - I915_OA_FORMAT_B4_C8_A16, - I915_OA_FORMAT_C4_B8, - - I915_OA_FORMAT_MAX /* non-ABI */ -}; - -enum drm_i915_perf_property_id { - /** - * Open the stream for a specific context handle (as used with - * execbuffer2). A stream opened for a specific context this way - * won't typically require root privileges. - */ - DRM_I915_PERF_PROP_CTX_HANDLE = 1, - - /** - * A value of 1 requests the inclusion of raw OA unit reports as - * part of stream samples. - */ - DRM_I915_PERF_PROP_SAMPLE_OA, - - /** - * The value specifies which set of OA unit metrics should be - * be configured, defining the contents of any OA unit reports. - */ - DRM_I915_PERF_PROP_OA_METRICS_SET, - - /** - * The value specifies the size and layout of OA unit reports. - */ - DRM_I915_PERF_PROP_OA_FORMAT, - - /** - * Specifying this property implicitly requests periodic OA unit - * sampling and (at least on Haswell) the sampling frequency is derived - * from this exponent as follows: - * - * 80ns * 2^(period_exponent + 1) - */ - DRM_I915_PERF_PROP_OA_EXPONENT, - - DRM_I915_PERF_PROP_MAX /* non-ABI */ -}; - -struct drm_i915_perf_open_param { - __u32 flags; -#define I915_PERF_FLAG_FD_CLOEXEC (1<<0) -#define I915_PERF_FLAG_FD_NONBLOCK (1<<1) -#define I915_PERF_FLAG_DISABLED (1<<2) - - /** The number of u64 (id, value) pairs */ - __u32 num_properties; - - /** - * Pointer to array of u64 (id, value) pairs configuring the stream - * to open. - */ - __u64 properties_ptr; -}; - -/** - * Enable data capture for a stream that was either opened in a disabled state - * via I915_PERF_FLAG_DISABLED or was later disabled via - * I915_PERF_IOCTL_DISABLE. - * - * It is intended to be cheaper to disable and enable a stream than it may be - * to close and re-open a stream with the same configuration. - * - * It's undefined whether any pending data for the stream will be lost. - */ -#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0) - -/** - * Disable data capture for a stream. - * - * It is an error to try and read a stream that is disabled. - */ -#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1) - -/** - * Common to all i915 perf records - */ -struct drm_i915_perf_record_header { - __u32 type; - __u16 pad; - __u16 size; -}; - -enum drm_i915_perf_record_type { - - /** - * Samples are the work horse record type whose contents are extensible - * and defined when opening an i915 perf stream based on the given - * properties. - * - * Boolean properties following the naming convention - * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in - * every sample. - * - * The order of these sample properties given by userspace has no - * affect on the ordering of data within a sample. The order is - * documented here. - * - * struct { - * struct drm_i915_perf_record_header header; - * - * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA - * }; - */ - DRM_I915_PERF_RECORD_SAMPLE = 1, - - /* - * Indicates that one or more OA reports were not written by the - * hardware. This can happen for example if an MI_REPORT_PERF_COUNT - * command collides with periodic sampling - which would be more likely - * at higher sampling frequencies. - */ - DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2, - - /** - * An error occurred that resulted in all pending OA reports being lost. - */ - DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3, - - DRM_I915_PERF_RECORD_MAX /* non-ABI */ -}; - -#if defined(__cplusplus) -} -#endif - -#endif /* _I915_DRM_H_ */ diff --git a/external/include/drm/mach64_drm.h b/external/include/drm/mach64_drm.h deleted file mode 100644 index 1f5fd84..0000000 --- a/external/include/drm/mach64_drm.h +++ /dev/null @@ -1,256 +0,0 @@ -/* mach64_drm.h -- Public header for the mach64 driver -*- linux-c -*- - * Created: Thu Nov 30 20:04:32 2000 by gareth@valinux.com - */ -/* - * Copyright 2000 Gareth Hughes - * Copyright 2002 Frank C. Earl - * Copyright 2002-2003 Leif Delgass - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Gareth Hughes - * Frank C. Earl - * Leif Delgass - */ - -#ifndef __MACH64_DRM_H__ -#define __MACH64_DRM_H__ - -/* WARNING: If you change any of these defines, make sure to change the - * defines in the Xserver file (mach64_sarea.h) - */ -#ifndef __MACH64_SAREA_DEFINES__ -#define __MACH64_SAREA_DEFINES__ - -/* What needs to be changed for the current vertex buffer? - * GH: We're going to be pedantic about this. We want the card to do as - * little as possible, so let's avoid having it fetch a whole bunch of - * register values that don't change all that often, if at all. - */ -#define MACH64_UPLOAD_DST_OFF_PITCH 0x0001 -#define MACH64_UPLOAD_Z_OFF_PITCH 0x0002 -#define MACH64_UPLOAD_Z_ALPHA_CNTL 0x0004 -#define MACH64_UPLOAD_SCALE_3D_CNTL 0x0008 -#define MACH64_UPLOAD_DP_FOG_CLR 0x0010 -#define MACH64_UPLOAD_DP_WRITE_MASK 0x0020 -#define MACH64_UPLOAD_DP_PIX_WIDTH 0x0040 -#define MACH64_UPLOAD_SETUP_CNTL 0x0080 -#define MACH64_UPLOAD_MISC 0x0100 -#define MACH64_UPLOAD_TEXTURE 0x0200 -#define MACH64_UPLOAD_TEX0IMAGE 0x0400 -#define MACH64_UPLOAD_TEX1IMAGE 0x0800 -#define MACH64_UPLOAD_CLIPRECTS 0x1000 /* handled client-side */ -#define MACH64_UPLOAD_CONTEXT 0x00ff -#define MACH64_UPLOAD_ALL 0x1fff - -/* DMA buffer size - */ -#define MACH64_BUFFER_SIZE 16384 - -/* Max number of swaps allowed on the ring - * before the client must wait - */ -#define MACH64_MAX_QUEUED_FRAMES 3U - -/* Byte offsets for host blit buffer data - */ -#define MACH64_HOSTDATA_BLIT_OFFSET 104 - -/* Keep these small for testing. - */ -#define MACH64_NR_SAREA_CLIPRECTS 8 - -#define MACH64_CARD_HEAP 0 -#define MACH64_AGP_HEAP 1 -#define MACH64_NR_TEX_HEAPS 2 -#define MACH64_NR_TEX_REGIONS 64 -#define MACH64_LOG_TEX_GRANULARITY 16 - -#define MACH64_TEX_MAXLEVELS 1 - -#define MACH64_NR_CONTEXT_REGS 15 -#define MACH64_NR_TEXTURE_REGS 4 - -#endif /* __MACH64_SAREA_DEFINES__ */ - -typedef struct { - unsigned int dst_off_pitch; - - unsigned int z_off_pitch; - unsigned int z_cntl; - unsigned int alpha_tst_cntl; - - unsigned int scale_3d_cntl; - - unsigned int sc_left_right; - unsigned int sc_top_bottom; - - unsigned int dp_fog_clr; - unsigned int dp_write_mask; - unsigned int dp_pix_width; - unsigned int dp_mix; - unsigned int dp_src; - - unsigned int clr_cmp_cntl; - unsigned int gui_traj_cntl; - - unsigned int setup_cntl; - - unsigned int tex_size_pitch; - unsigned int tex_cntl; - unsigned int secondary_tex_off; - unsigned int tex_offset; -} drm_mach64_context_regs_t; - -typedef struct drm_mach64_sarea { - /* The channel for communication of state information to the kernel - * on firing a vertex dma buffer. - */ - drm_mach64_context_regs_t context_state; - unsigned int dirty; - unsigned int vertsize; - - /* The current cliprects, or a subset thereof. - */ - struct drm_clip_rect boxes[MACH64_NR_SAREA_CLIPRECTS]; - unsigned int nbox; - - /* Counters for client-side throttling of rendering clients. - */ - unsigned int frames_queued; - - /* Texture memory LRU. - */ - struct drm_tex_region tex_list[MACH64_NR_TEX_HEAPS][MACH64_NR_TEX_REGIONS + - 1]; - unsigned int tex_age[MACH64_NR_TEX_HEAPS]; - int ctx_owner; -} drm_mach64_sarea_t; - -/* WARNING: If you change any of these defines, make sure to change the - * defines in the Xserver file (mach64_common.h) - */ - -/* Mach64 specific ioctls - * The device specific ioctl range is 0x40 to 0x79. - */ - -#define DRM_MACH64_INIT 0x00 -#define DRM_MACH64_IDLE 0x01 -#define DRM_MACH64_RESET 0x02 -#define DRM_MACH64_SWAP 0x03 -#define DRM_MACH64_CLEAR 0x04 -#define DRM_MACH64_VERTEX 0x05 -#define DRM_MACH64_BLIT 0x06 -#define DRM_MACH64_FLUSH 0x07 -#define DRM_MACH64_GETPARAM 0x08 - -#define DRM_IOCTL_MACH64_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_INIT, drm_mach64_init_t) -#define DRM_IOCTL_MACH64_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_IDLE ) -#define DRM_IOCTL_MACH64_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_RESET ) -#define DRM_IOCTL_MACH64_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_SWAP ) -#define DRM_IOCTL_MACH64_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_CLEAR, drm_mach64_clear_t) -#define DRM_IOCTL_MACH64_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_VERTEX, drm_mach64_vertex_t) -#define DRM_IOCTL_MACH64_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_BLIT, drm_mach64_blit_t) -#define DRM_IOCTL_MACH64_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_FLUSH ) -#define DRM_IOCTL_MACH64_GETPARAM DRM_IOWR( DRM_COMMAND_BASE + DRM_MACH64_GETPARAM, drm_mach64_getparam_t) - -/* Buffer flags for clears - */ -#define MACH64_FRONT 0x1 -#define MACH64_BACK 0x2 -#define MACH64_DEPTH 0x4 - -/* Primitive types for vertex buffers - */ -#define MACH64_PRIM_POINTS 0x00000000 -#define MACH64_PRIM_LINES 0x00000001 -#define MACH64_PRIM_LINE_LOOP 0x00000002 -#define MACH64_PRIM_LINE_STRIP 0x00000003 -#define MACH64_PRIM_TRIANGLES 0x00000004 -#define MACH64_PRIM_TRIANGLE_STRIP 0x00000005 -#define MACH64_PRIM_TRIANGLE_FAN 0x00000006 -#define MACH64_PRIM_QUADS 0x00000007 -#define MACH64_PRIM_QUAD_STRIP 0x00000008 -#define MACH64_PRIM_POLYGON 0x00000009 - -typedef enum _drm_mach64_dma_mode_t { - MACH64_MODE_DMA_ASYNC, - MACH64_MODE_DMA_SYNC, - MACH64_MODE_MMIO -} drm_mach64_dma_mode_t; - -typedef struct drm_mach64_init { - enum { - DRM_MACH64_INIT_DMA = 0x01, - DRM_MACH64_CLEANUP_DMA = 0x02 - } func; - - unsigned long sarea_priv_offset; - int is_pci; - drm_mach64_dma_mode_t dma_mode; - - unsigned int fb_bpp; - unsigned int front_offset, front_pitch; - unsigned int back_offset, back_pitch; - - unsigned int depth_bpp; - unsigned int depth_offset, depth_pitch; - - unsigned long fb_offset; - unsigned long mmio_offset; - unsigned long ring_offset; - unsigned long buffers_offset; - unsigned long agp_textures_offset; -} drm_mach64_init_t; - -typedef struct drm_mach64_clear { - unsigned int flags; - int x, y, w, h; - unsigned int clear_color; - unsigned int clear_depth; -} drm_mach64_clear_t; - -typedef struct drm_mach64_vertex { - int prim; - void *buf; /* Address of vertex buffer */ - unsigned long used; /* Number of bytes in buffer */ - int discard; /* Client finished with buffer? */ -} drm_mach64_vertex_t; - -typedef struct drm_mach64_blit { - void *buf; - int pitch; - int offset; - int format; - unsigned short x, y; - unsigned short width, height; -} drm_mach64_blit_t; - -typedef struct drm_mach64_getparam { - enum { - MACH64_PARAM_FRAMES_QUEUED = 0x01, - MACH64_PARAM_IRQ_NR = 0x02 - } param; - void *value; -} drm_mach64_getparam_t; - -#endif diff --git a/external/include/drm/mga_drm.h b/external/include/drm/mga_drm.h deleted file mode 100644 index 7930011..0000000 --- a/external/include/drm/mga_drm.h +++ /dev/null @@ -1,427 +0,0 @@ -/* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*- - * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com - * - * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Jeff Hartmann - * Keith Whitwell - * - * Rewritten by: - * Gareth Hughes - */ - -#ifndef __MGA_DRM_H__ -#define __MGA_DRM_H__ - -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/* WARNING: If you change any of these defines, make sure to change the - * defines in the Xserver file (mga_sarea.h) - */ - -#ifndef __MGA_SAREA_DEFINES__ -#define __MGA_SAREA_DEFINES__ - -/* WARP pipe flags - */ -#define MGA_F 0x1 /* fog */ -#define MGA_A 0x2 /* alpha */ -#define MGA_S 0x4 /* specular */ -#define MGA_T2 0x8 /* multitexture */ - -#define MGA_WARP_TGZ 0 -#define MGA_WARP_TGZF (MGA_F) -#define MGA_WARP_TGZA (MGA_A) -#define MGA_WARP_TGZAF (MGA_F|MGA_A) -#define MGA_WARP_TGZS (MGA_S) -#define MGA_WARP_TGZSF (MGA_S|MGA_F) -#define MGA_WARP_TGZSA (MGA_S|MGA_A) -#define MGA_WARP_TGZSAF (MGA_S|MGA_F|MGA_A) -#define MGA_WARP_T2GZ (MGA_T2) -#define MGA_WARP_T2GZF (MGA_T2|MGA_F) -#define MGA_WARP_T2GZA (MGA_T2|MGA_A) -#define MGA_WARP_T2GZAF (MGA_T2|MGA_A|MGA_F) -#define MGA_WARP_T2GZS (MGA_T2|MGA_S) -#define MGA_WARP_T2GZSF (MGA_T2|MGA_S|MGA_F) -#define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A) -#define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A) - -#define MGA_MAX_G200_PIPES 8 /* no multitex */ -#define MGA_MAX_G400_PIPES 16 -#define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES -#define MGA_WARP_UCODE_SIZE 32768 /* in bytes */ - -#define MGA_CARD_TYPE_G200 1 -#define MGA_CARD_TYPE_G400 2 -#define MGA_CARD_TYPE_G450 3 /* not currently used */ -#define MGA_CARD_TYPE_G550 4 - -#define MGA_FRONT 0x1 -#define MGA_BACK 0x2 -#define MGA_DEPTH 0x4 - -/* What needs to be changed for the current vertex dma buffer? - */ -#define MGA_UPLOAD_CONTEXT 0x1 -#define MGA_UPLOAD_TEX0 0x2 -#define MGA_UPLOAD_TEX1 0x4 -#define MGA_UPLOAD_PIPE 0x8 -#define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */ -#define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */ -#define MGA_UPLOAD_2D 0x40 -#define MGA_WAIT_AGE 0x80 /* handled client-side */ -#define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */ -#if 0 -#define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock - quiescent */ -#endif - -/* 32 buffers of 64k each, total 2 meg. - */ -#define MGA_BUFFER_SIZE (1 << 16) -#define MGA_NUM_BUFFERS 128 - -/* Keep these small for testing. - */ -#define MGA_NR_SAREA_CLIPRECTS 8 - -/* 2 heaps (1 for card, 1 for agp), each divided into up to 128 - * regions, subject to a minimum region size of (1<<16) == 64k. - * - * Clients may subdivide regions internally, but when sharing between - * clients, the region size is the minimum granularity. - */ - -#define MGA_CARD_HEAP 0 -#define MGA_AGP_HEAP 1 -#define MGA_NR_TEX_HEAPS 2 -#define MGA_NR_TEX_REGIONS 16 -#define MGA_LOG_MIN_TEX_REGION_SIZE 16 - -#define DRM_MGA_IDLE_RETRY 2048 - -#endif /* __MGA_SAREA_DEFINES__ */ - -/* Setup registers for 3D context - */ -typedef struct { - unsigned int dstorg; - unsigned int maccess; - unsigned int plnwt; - unsigned int dwgctl; - unsigned int alphactrl; - unsigned int fogcolor; - unsigned int wflag; - unsigned int tdualstage0; - unsigned int tdualstage1; - unsigned int fcol; - unsigned int stencil; - unsigned int stencilctl; -} drm_mga_context_regs_t; - -/* Setup registers for 2D, X server - */ -typedef struct { - unsigned int pitch; -} drm_mga_server_regs_t; - -/* Setup registers for each texture unit - */ -typedef struct { - unsigned int texctl; - unsigned int texctl2; - unsigned int texfilter; - unsigned int texbordercol; - unsigned int texorg; - unsigned int texwidth; - unsigned int texheight; - unsigned int texorg1; - unsigned int texorg2; - unsigned int texorg3; - unsigned int texorg4; -} drm_mga_texture_regs_t; - -/* General aging mechanism - */ -typedef struct { - unsigned int head; /* Position of head pointer */ - unsigned int wrap; /* Primary DMA wrap count */ -} drm_mga_age_t; - -typedef struct _drm_mga_sarea { - /* The channel for communication of state information to the kernel - * on firing a vertex dma buffer. - */ - drm_mga_context_regs_t context_state; - drm_mga_server_regs_t server_state; - drm_mga_texture_regs_t tex_state[2]; - unsigned int warp_pipe; - unsigned int dirty; - unsigned int vertsize; - - /* The current cliprects, or a subset thereof. - */ - struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS]; - unsigned int nbox; - - /* Information about the most recently used 3d drawable. The - * client fills in the req_* fields, the server fills in the - * exported_ fields and puts the cliprects into boxes, above. - * - * The client clears the exported_drawable field before - * clobbering the boxes data. - */ - unsigned int req_drawable; /* the X drawable id */ - unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */ - - unsigned int exported_drawable; - unsigned int exported_index; - unsigned int exported_stamp; - unsigned int exported_buffers; - unsigned int exported_nfront; - unsigned int exported_nback; - int exported_back_x, exported_front_x, exported_w; - int exported_back_y, exported_front_y, exported_h; - struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS]; - - /* Counters for aging textures and for client-side throttling. - */ - unsigned int status[4]; - unsigned int last_wrap; - - drm_mga_age_t last_frame; - unsigned int last_enqueue; /* last time a buffer was enqueued */ - unsigned int last_dispatch; /* age of the most recently dispatched buffer */ - unsigned int last_quiescent; /* */ - - /* LRU lists for texture memory in agp space and on the card. - */ - struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1]; - unsigned int texAge[MGA_NR_TEX_HEAPS]; - - /* Mechanism to validate card state. - */ - int ctxOwner; -} drm_mga_sarea_t; - -/* MGA specific ioctls - * The device specific ioctl range is 0x40 to 0x79. - */ -#define DRM_MGA_INIT 0x00 -#define DRM_MGA_FLUSH 0x01 -#define DRM_MGA_RESET 0x02 -#define DRM_MGA_SWAP 0x03 -#define DRM_MGA_CLEAR 0x04 -#define DRM_MGA_VERTEX 0x05 -#define DRM_MGA_INDICES 0x06 -#define DRM_MGA_ILOAD 0x07 -#define DRM_MGA_BLIT 0x08 -#define DRM_MGA_GETPARAM 0x09 - -/* 3.2: - * ioctls for operating on fences. - */ -#define DRM_MGA_SET_FENCE 0x0a -#define DRM_MGA_WAIT_FENCE 0x0b -#define DRM_MGA_DMA_BOOTSTRAP 0x0c - -#define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t) -#define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, struct drm_lock) -#define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET) -#define DRM_IOCTL_MGA_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MGA_SWAP) -#define DRM_IOCTL_MGA_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t) -#define DRM_IOCTL_MGA_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t) -#define DRM_IOCTL_MGA_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t) -#define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t) -#define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t) -#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t) -#define DRM_IOCTL_MGA_SET_FENCE DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, __u32) -#define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, __u32) -#define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t) - -typedef struct _drm_mga_warp_index { - int installed; - unsigned long phys_addr; - int size; -} drm_mga_warp_index_t; - -typedef struct drm_mga_init { - enum { - MGA_INIT_DMA = 0x01, - MGA_CLEANUP_DMA = 0x02 - } func; - - unsigned long sarea_priv_offset; - - int chipset; - int sgram; - - unsigned int maccess; - - unsigned int fb_cpp; - unsigned int front_offset, front_pitch; - unsigned int back_offset, back_pitch; - - unsigned int depth_cpp; - unsigned int depth_offset, depth_pitch; - - unsigned int texture_offset[MGA_NR_TEX_HEAPS]; - unsigned int texture_size[MGA_NR_TEX_HEAPS]; - - unsigned long fb_offset; - unsigned long mmio_offset; - unsigned long status_offset; - unsigned long warp_offset; - unsigned long primary_offset; - unsigned long buffers_offset; -} drm_mga_init_t; - -typedef struct drm_mga_dma_bootstrap { - /** - * \name AGP texture region - * - * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will - * be filled in with the actual AGP texture settings. - * - * \warning - * If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode - * is zero, it means that PCI memory (most likely through the use of - * an IOMMU) is being used for "AGP" textures. - */ - /*@{ */ - unsigned long texture_handle; /**< Handle used to map AGP textures. */ - __u32 texture_size; /**< Size of the AGP texture region. */ - /*@} */ - - /** - * Requested size of the primary DMA region. - * - * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be - * filled in with the actual AGP mode. If AGP was not available - */ - __u32 primary_size; - - /** - * Requested number of secondary DMA buffers. - * - * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be - * filled in with the actual number of secondary DMA buffers - * allocated. Particularly when PCI DMA is used, this may be - * (subtantially) less than the number requested. - */ - __u32 secondary_bin_count; - - /** - * Requested size of each secondary DMA buffer. - * - * While the kernel \b is free to reduce - * dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed - * to reduce dma_mga_dma_bootstrap::secondary_bin_size. - */ - __u32 secondary_bin_size; - - /** - * Bit-wise mask of AGPSTAT2_* values. Currently only \c AGPSTAT2_1X, - * \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported. If this value is - * zero, it means that PCI DMA should be used, even if AGP is - * possible. - * - * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be - * filled in with the actual AGP mode. If AGP was not available - * (i.e., PCI DMA was used), this value will be zero. - */ - __u32 agp_mode; - - /** - * Desired AGP GART size, measured in megabytes. - */ - __u8 agp_size; -} drm_mga_dma_bootstrap_t; - -typedef struct drm_mga_clear { - unsigned int flags; - unsigned int clear_color; - unsigned int clear_depth; - unsigned int color_mask; - unsigned int depth_mask; -} drm_mga_clear_t; - -typedef struct drm_mga_vertex { - int idx; /* buffer to queue */ - int used; /* bytes in use */ - int discard; /* client finished with buffer? */ -} drm_mga_vertex_t; - -typedef struct drm_mga_indices { - int idx; /* buffer to queue */ - unsigned int start; - unsigned int end; - int discard; /* client finished with buffer? */ -} drm_mga_indices_t; - -typedef struct drm_mga_iload { - int idx; - unsigned int dstorg; - unsigned int length; -} drm_mga_iload_t; - -typedef struct _drm_mga_blit { - unsigned int planemask; - unsigned int srcorg; - unsigned int dstorg; - int src_pitch, dst_pitch; - int delta_sx, delta_sy; - int delta_dx, delta_dy; - int height, ydir; /* flip image vertically */ - int source_pitch, dest_pitch; -} drm_mga_blit_t; - -/* 3.1: An ioctl to get parameters that aren't available to the 3d - * client any other way. - */ -#define MGA_PARAM_IRQ_NR 1 - -/* 3.2: Query the actual card type. The DDX only distinguishes between - * G200 chips and non-G200 chips, which it calls G400. It turns out that - * there are some very sublte differences between the G4x0 chips and the G550 - * chips. Using this parameter query, a client-side driver can detect the - * difference between a G4x0 and a G550. - */ -#define MGA_PARAM_CARD_TYPE 2 - -typedef struct drm_mga_getparam { - int param; - void *value; -} drm_mga_getparam_t; - -#if defined(__cplusplus) -} -#endif - -#endif diff --git a/external/include/drm/nouveau_drm.h b/external/include/drm/nouveau_drm.h deleted file mode 100644 index cb07782..0000000 --- a/external/include/drm/nouveau_drm.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Copyright 2005 Stephane Marchesin. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NOUVEAU_DRM_H__ -#define __NOUVEAU_DRM_H__ - -#define NOUVEAU_DRM_HEADER_PATCHLEVEL 16 - -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -struct drm_nouveau_channel_alloc { - uint32_t fb_ctxdma_handle; - uint32_t tt_ctxdma_handle; - - int channel; - uint32_t pushbuf_domains; - - /* Notifier memory */ - uint32_t notifier_handle; - - /* DRM-enforced subchannel assignments */ - struct { - uint32_t handle; - uint32_t grclass; - } subchan[8]; - uint32_t nr_subchan; -}; - -struct drm_nouveau_channel_free { - int channel; -}; - -struct drm_nouveau_grobj_alloc { - int channel; - uint32_t handle; - int class; -}; - -struct drm_nouveau_notifierobj_alloc { - uint32_t channel; - uint32_t handle; - uint32_t size; - uint32_t offset; -}; - -struct drm_nouveau_gpuobj_free { - int channel; - uint32_t handle; -}; - -/* FIXME : maybe unify {GET,SET}PARAMs */ -#define NOUVEAU_GETPARAM_PCI_VENDOR 3 -#define NOUVEAU_GETPARAM_PCI_DEVICE 4 -#define NOUVEAU_GETPARAM_BUS_TYPE 5 -#define NOUVEAU_GETPARAM_FB_PHYSICAL 6 -#define NOUVEAU_GETPARAM_AGP_PHYSICAL 7 -#define NOUVEAU_GETPARAM_FB_SIZE 8 -#define NOUVEAU_GETPARAM_AGP_SIZE 9 -#define NOUVEAU_GETPARAM_PCI_PHYSICAL 10 -#define NOUVEAU_GETPARAM_CHIPSET_ID 11 -#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12 -#define NOUVEAU_GETPARAM_GRAPH_UNITS 13 -#define NOUVEAU_GETPARAM_PTIMER_TIME 14 -#define NOUVEAU_GETPARAM_HAS_BO_USAGE 15 -#define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16 -struct drm_nouveau_getparam { - uint64_t param; - uint64_t value; -}; - -struct drm_nouveau_setparam { - uint64_t param; - uint64_t value; -}; - -#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) -#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) -#define NOUVEAU_GEM_DOMAIN_GART (1 << 2) -#define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3) -#define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4) - -#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00 -#define NOUVEAU_GEM_TILE_16BPP 0x00000001 -#define NOUVEAU_GEM_TILE_32BPP 0x00000002 -#define NOUVEAU_GEM_TILE_ZETA 0x00000004 -#define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008 - -struct drm_nouveau_gem_info { - __u32 handle; - __u32 domain; - __u64 size; - __u64 offset; - __u64 map_handle; - __u32 tile_mode; - __u32 tile_flags; -}; - -struct drm_nouveau_gem_new { - struct drm_nouveau_gem_info info; - __u32 channel_hint; - __u32 align; -}; - -#define NOUVEAU_GEM_MAX_BUFFERS 1024 -struct drm_nouveau_gem_pushbuf_bo_presumed { - __u32 valid; - __u32 domain; - __u64 offset; -}; - -struct drm_nouveau_gem_pushbuf_bo { - __u64 user_priv; - __u32 handle; - __u32 read_domains; - __u32 write_domains; - __u32 valid_domains; - struct drm_nouveau_gem_pushbuf_bo_presumed presumed; -}; - -#define NOUVEAU_GEM_RELOC_LOW (1 << 0) -#define NOUVEAU_GEM_RELOC_HIGH (1 << 1) -#define NOUVEAU_GEM_RELOC_OR (1 << 2) -#define NOUVEAU_GEM_MAX_RELOCS 1024 -struct drm_nouveau_gem_pushbuf_reloc { - __u32 reloc_bo_index; - __u32 reloc_bo_offset; - __u32 bo_index; - __u32 flags; - __u32 data; - __u32 vor; - __u32 tor; -}; - -#define NOUVEAU_GEM_MAX_PUSH 512 -struct drm_nouveau_gem_pushbuf_push { - __u32 bo_index; - __u32 pad; - __u64 offset; - __u64 length; -}; - -struct drm_nouveau_gem_pushbuf { - __u32 channel; - __u32 nr_buffers; - __u64 buffers; - __u32 nr_relocs; - __u32 nr_push; - __u64 relocs; - __u64 push; - __u32 suffix0; - __u32 suffix1; - __u64 vram_available; - __u64 gart_available; -}; - -#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001 -#define NOUVEAU_GEM_CPU_PREP_NOBLOCK 0x00000002 -#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004 -struct drm_nouveau_gem_cpu_prep { - __u32 handle; - __u32 flags; -}; - -struct drm_nouveau_gem_cpu_fini { - __u32 handle; -}; - -enum nouveau_bus_type { - NV_AGP = 0, - NV_PCI = 1, - NV_PCIE = 2, -}; - -struct drm_nouveau_sarea { -}; - -#define DRM_NOUVEAU_GETPARAM 0x00 -#define DRM_NOUVEAU_SETPARAM 0x01 -#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 -#define DRM_NOUVEAU_CHANNEL_FREE 0x03 -#define DRM_NOUVEAU_GROBJ_ALLOC 0x04 -#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 -#define DRM_NOUVEAU_GPUOBJ_FREE 0x06 -#define DRM_NOUVEAU_NVIF 0x07 -#define DRM_NOUVEAU_GEM_NEW 0x40 -#define DRM_NOUVEAU_GEM_PUSHBUF 0x41 -#define DRM_NOUVEAU_GEM_CPU_PREP 0x42 -#define DRM_NOUVEAU_GEM_CPU_FINI 0x43 -#define DRM_NOUVEAU_GEM_INFO 0x44 - -#if defined(__cplusplus) -} -#endif - -#endif /* __NOUVEAU_DRM_H__ */ diff --git a/external/include/drm/qxl_drm.h b/external/include/drm/qxl_drm.h deleted file mode 100644 index 38a0dbd..0000000 --- a/external/include/drm/qxl_drm.h +++ /dev/null @@ -1,160 +0,0 @@ -/* - * Copyright 2013 Red Hat - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef QXL_DRM_H -#define QXL_DRM_H - -#include -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/* Please note that modifications to all structs defined here are - * subject to backwards-compatibility constraints. - * - * Do not use pointers, use __u64 instead for 32 bit / 64 bit user/kernel - * compatibility Keep fields aligned to their size - */ - -#define QXL_GEM_DOMAIN_CPU 0 -#define QXL_GEM_DOMAIN_VRAM 1 -#define QXL_GEM_DOMAIN_SURFACE 2 - -#define DRM_QXL_ALLOC 0x00 -#define DRM_QXL_MAP 0x01 -#define DRM_QXL_EXECBUFFER 0x02 -#define DRM_QXL_UPDATE_AREA 0x03 -#define DRM_QXL_GETPARAM 0x04 -#define DRM_QXL_CLIENTCAP 0x05 - -#define DRM_QXL_ALLOC_SURF 0x06 - -struct drm_qxl_alloc { - __u32 size; - __u32 handle; /* 0 is an invalid handle */ -}; - -struct drm_qxl_map { - __u64 offset; /* use for mmap system call */ - __u32 handle; - __u32 pad; -}; - -/* - * dest is the bo we are writing the relocation into - * src is bo we are relocating. - * *(dest_handle.base_addr + dest_offset) = physical_address(src_handle.addr + - * src_offset) - */ -#define QXL_RELOC_TYPE_BO 1 -#define QXL_RELOC_TYPE_SURF 2 - -struct drm_qxl_reloc { - __u64 src_offset; /* offset into src_handle or src buffer */ - __u64 dst_offset; /* offset in dest handle */ - __u32 src_handle; /* dest handle to compute address from */ - __u32 dst_handle; /* 0 if to command buffer */ - __u32 reloc_type; - __u32 pad; -}; - -struct drm_qxl_command { - __u64 command; /* void* */ - __u64 relocs; /* struct drm_qxl_reloc* */ - __u32 type; - __u32 command_size; - __u32 relocs_num; - __u32 pad; -}; - -/* XXX: call it drm_qxl_commands? */ -struct drm_qxl_execbuffer { - __u32 flags; /* for future use */ - __u32 commands_num; - __u64 commands; /* struct drm_qxl_command* */ -}; - -struct drm_qxl_update_area { - __u32 handle; - __u32 top; - __u32 left; - __u32 bottom; - __u32 right; - __u32 pad; -}; - -#define QXL_PARAM_NUM_SURFACES 1 /* rom->n_surfaces */ -#define QXL_PARAM_MAX_RELOCS 2 -struct drm_qxl_getparam { - __u64 param; - __u64 value; -}; - -/* these are one bit values */ -struct drm_qxl_clientcap { - __u32 index; - __u32 pad; -}; - -struct drm_qxl_alloc_surf { - __u32 format; - __u32 width; - __u32 height; - __s32 stride; - __u32 handle; - __u32 pad; -}; - -#define DRM_IOCTL_QXL_ALLOC \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC, struct drm_qxl_alloc) - -#define DRM_IOCTL_QXL_MAP \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_MAP, struct drm_qxl_map) - -#define DRM_IOCTL_QXL_EXECBUFFER \ - DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_EXECBUFFER,\ - struct drm_qxl_execbuffer) - -#define DRM_IOCTL_QXL_UPDATE_AREA \ - DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_UPDATE_AREA,\ - struct drm_qxl_update_area) - -#define DRM_IOCTL_QXL_GETPARAM \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_GETPARAM,\ - struct drm_qxl_getparam) - -#define DRM_IOCTL_QXL_CLIENTCAP \ - DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_CLIENTCAP,\ - struct drm_qxl_clientcap) - -#define DRM_IOCTL_QXL_ALLOC_SURF \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC_SURF,\ - struct drm_qxl_alloc_surf) - -#if defined(__cplusplus) -} -#endif - -#endif diff --git a/external/include/drm/r128_drm.h b/external/include/drm/r128_drm.h deleted file mode 100644 index bf431a0..0000000 --- a/external/include/drm/r128_drm.h +++ /dev/null @@ -1,336 +0,0 @@ -/* r128_drm.h -- Public header for the r128 driver -*- linux-c -*- - * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com - */ -/* - * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Gareth Hughes - * Kevin E. Martin - */ - -#ifndef __R128_DRM_H__ -#define __R128_DRM_H__ - -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/* WARNING: If you change any of these defines, make sure to change the - * defines in the X server file (r128_sarea.h) - */ -#ifndef __R128_SAREA_DEFINES__ -#define __R128_SAREA_DEFINES__ - -/* What needs to be changed for the current vertex buffer? - */ -#define R128_UPLOAD_CONTEXT 0x001 -#define R128_UPLOAD_SETUP 0x002 -#define R128_UPLOAD_TEX0 0x004 -#define R128_UPLOAD_TEX1 0x008 -#define R128_UPLOAD_TEX0IMAGES 0x010 -#define R128_UPLOAD_TEX1IMAGES 0x020 -#define R128_UPLOAD_CORE 0x040 -#define R128_UPLOAD_MASKS 0x080 -#define R128_UPLOAD_WINDOW 0x100 -#define R128_UPLOAD_CLIPRECTS 0x200 /* handled client-side */ -#define R128_REQUIRE_QUIESCENCE 0x400 -#define R128_UPLOAD_ALL 0x7ff - -#define R128_FRONT 0x1 -#define R128_BACK 0x2 -#define R128_DEPTH 0x4 - -/* Primitive types - */ -#define R128_POINTS 0x1 -#define R128_LINES 0x2 -#define R128_LINE_STRIP 0x3 -#define R128_TRIANGLES 0x4 -#define R128_TRIANGLE_FAN 0x5 -#define R128_TRIANGLE_STRIP 0x6 - -/* Vertex/indirect buffer size - */ -#define R128_BUFFER_SIZE 16384 - -/* Byte offsets for indirect buffer data - */ -#define R128_INDEX_PRIM_OFFSET 20 -#define R128_HOSTDATA_BLIT_OFFSET 32 - -/* Keep these small for testing. - */ -#define R128_NR_SAREA_CLIPRECTS 12 - -/* There are 2 heaps (local/AGP). Each region within a heap is a - * minimum of 64k, and there are at most 64 of them per heap. - */ -#define R128_LOCAL_TEX_HEAP 0 -#define R128_AGP_TEX_HEAP 1 -#define R128_NR_TEX_HEAPS 2 -#define R128_NR_TEX_REGIONS 64 -#define R128_LOG_TEX_GRANULARITY 16 - -#define R128_NR_CONTEXT_REGS 12 - -#define R128_MAX_TEXTURE_LEVELS 11 -#define R128_MAX_TEXTURE_UNITS 2 - -#endif /* __R128_SAREA_DEFINES__ */ - -typedef struct { - /* Context state - can be written in one large chunk */ - unsigned int dst_pitch_offset_c; - unsigned int dp_gui_master_cntl_c; - unsigned int sc_top_left_c; - unsigned int sc_bottom_right_c; - unsigned int z_offset_c; - unsigned int z_pitch_c; - unsigned int z_sten_cntl_c; - unsigned int tex_cntl_c; - unsigned int misc_3d_state_cntl_reg; - unsigned int texture_clr_cmp_clr_c; - unsigned int texture_clr_cmp_msk_c; - unsigned int fog_color_c; - - /* Texture state */ - unsigned int tex_size_pitch_c; - unsigned int constant_color_c; - - /* Setup state */ - unsigned int pm4_vc_fpu_setup; - unsigned int setup_cntl; - - /* Mask state */ - unsigned int dp_write_mask; - unsigned int sten_ref_mask_c; - unsigned int plane_3d_mask_c; - - /* Window state */ - unsigned int window_xy_offset; - - /* Core state */ - unsigned int scale_3d_cntl; -} drm_r128_context_regs_t; - -/* Setup registers for each texture unit - */ -typedef struct { - unsigned int tex_cntl; - unsigned int tex_combine_cntl; - unsigned int tex_size_pitch; - unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS]; - unsigned int tex_border_color; -} drm_r128_texture_regs_t; - -typedef struct drm_r128_sarea { - /* The channel for communication of state information to the kernel - * on firing a vertex buffer. - */ - drm_r128_context_regs_t context_state; - drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS]; - unsigned int dirty; - unsigned int vertsize; - unsigned int vc_format; - - /* The current cliprects, or a subset thereof. - */ - struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS]; - unsigned int nbox; - - /* Counters for client-side throttling of rendering clients. - */ - unsigned int last_frame; - unsigned int last_dispatch; - - struct drm_tex_region tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1]; - unsigned int tex_age[R128_NR_TEX_HEAPS]; - int ctx_owner; - int pfAllowPageFlip; /* number of 3d windows (0,1,2 or more) */ - int pfCurrentPage; /* which buffer is being displayed? */ -} drm_r128_sarea_t; - -/* WARNING: If you change any of these defines, make sure to change the - * defines in the Xserver file (xf86drmR128.h) - */ - -/* Rage 128 specific ioctls - * The device specific ioctl range is 0x40 to 0x79. - */ -#define DRM_R128_INIT 0x00 -#define DRM_R128_CCE_START 0x01 -#define DRM_R128_CCE_STOP 0x02 -#define DRM_R128_CCE_RESET 0x03 -#define DRM_R128_CCE_IDLE 0x04 -/* 0x05 not used */ -#define DRM_R128_RESET 0x06 -#define DRM_R128_SWAP 0x07 -#define DRM_R128_CLEAR 0x08 -#define DRM_R128_VERTEX 0x09 -#define DRM_R128_INDICES 0x0a -#define DRM_R128_BLIT 0x0b -#define DRM_R128_DEPTH 0x0c -#define DRM_R128_STIPPLE 0x0d -/* 0x0e not used */ -#define DRM_R128_INDIRECT 0x0f -#define DRM_R128_FULLSCREEN 0x10 -#define DRM_R128_CLEAR2 0x11 -#define DRM_R128_GETPARAM 0x12 -#define DRM_R128_FLIP 0x13 - -#define DRM_IOCTL_R128_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INIT, drm_r128_init_t) -#define DRM_IOCTL_R128_CCE_START DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_START) -#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CCE_STOP, drm_r128_cce_stop_t) -#define DRM_IOCTL_R128_CCE_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_RESET) -#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_IDLE) -/* 0x05 not used */ -#define DRM_IOCTL_R128_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_RESET) -#define DRM_IOCTL_R128_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_R128_SWAP) -#define DRM_IOCTL_R128_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR, drm_r128_clear_t) -#define DRM_IOCTL_R128_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_R128_VERTEX, drm_r128_vertex_t) -#define DRM_IOCTL_R128_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INDICES, drm_r128_indices_t) -#define DRM_IOCTL_R128_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_BLIT, drm_r128_blit_t) -#define DRM_IOCTL_R128_DEPTH DRM_IOW( DRM_COMMAND_BASE + DRM_R128_DEPTH, drm_r128_depth_t) -#define DRM_IOCTL_R128_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_R128_STIPPLE, drm_r128_stipple_t) -/* 0x0e not used */ -#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_INDIRECT, drm_r128_indirect_t) -#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_R128_FULLSCREEN, drm_r128_fullscreen_t) -#define DRM_IOCTL_R128_CLEAR2 DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t) -#define DRM_IOCTL_R128_GETPARAM DRM_IOWR( DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t) -#define DRM_IOCTL_R128_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_R128_FLIP) - -typedef struct drm_r128_init { - enum { - R128_INIT_CCE = 0x01, - R128_CLEANUP_CCE = 0x02 - } func; - unsigned long sarea_priv_offset; - int is_pci; - int cce_mode; - int cce_secure; - int ring_size; - int usec_timeout; - - unsigned int fb_bpp; - unsigned int front_offset, front_pitch; - unsigned int back_offset, back_pitch; - unsigned int depth_bpp; - unsigned int depth_offset, depth_pitch; - unsigned int span_offset; - - unsigned long fb_offset; - unsigned long mmio_offset; - unsigned long ring_offset; - unsigned long ring_rptr_offset; - unsigned long buffers_offset; - unsigned long agp_textures_offset; -} drm_r128_init_t; - -typedef struct drm_r128_cce_stop { - int flush; - int idle; -} drm_r128_cce_stop_t; - -typedef struct drm_r128_clear { - unsigned int flags; - unsigned int clear_color; - unsigned int clear_depth; - unsigned int color_mask; - unsigned int depth_mask; -} drm_r128_clear_t; - -typedef struct drm_r128_vertex { - int prim; - int idx; /* Index of vertex buffer */ - int count; /* Number of vertices in buffer */ - int discard; /* Client finished with buffer? */ -} drm_r128_vertex_t; - -typedef struct drm_r128_indices { - int prim; - int idx; - int start; - int end; - int discard; /* Client finished with buffer? */ -} drm_r128_indices_t; - -typedef struct drm_r128_blit { - int idx; - int pitch; - int offset; - int format; - unsigned short x, y; - unsigned short width, height; -} drm_r128_blit_t; - -typedef struct drm_r128_depth { - enum { - R128_WRITE_SPAN = 0x01, - R128_WRITE_PIXELS = 0x02, - R128_READ_SPAN = 0x03, - R128_READ_PIXELS = 0x04 - } func; - int n; - int *x; - int *y; - unsigned int *buffer; - unsigned char *mask; -} drm_r128_depth_t; - -typedef struct drm_r128_stipple { - unsigned int *mask; -} drm_r128_stipple_t; - -typedef struct drm_r128_indirect { - int idx; - int start; - int end; - int discard; -} drm_r128_indirect_t; - -typedef struct drm_r128_fullscreen { - enum { - R128_INIT_FULLSCREEN = 0x01, - R128_CLEANUP_FULLSCREEN = 0x02 - } func; -} drm_r128_fullscreen_t; - -/* 2.3: An ioctl to get parameters that aren't available to the 3d - * client any other way. - */ -#define R128_PARAM_IRQ_NR 1 - -typedef struct drm_r128_getparam { - int param; - void *value; -} drm_r128_getparam_t; - -#if defined(__cplusplus) -} -#endif - -#endif diff --git a/external/include/drm/radeon_drm.h b/external/include/drm/radeon_drm.h deleted file mode 100644 index a1e385d..0000000 --- a/external/include/drm/radeon_drm.h +++ /dev/null @@ -1,1079 +0,0 @@ -/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*- - * - * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Fremont, California. - * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Kevin E. Martin - * Gareth Hughes - * Keith Whitwell - */ - -#ifndef __RADEON_DRM_H__ -#define __RADEON_DRM_H__ - -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/* WARNING: If you change any of these defines, make sure to change the - * defines in the X server file (radeon_sarea.h) - */ -#ifndef __RADEON_SAREA_DEFINES__ -#define __RADEON_SAREA_DEFINES__ - -/* Old style state flags, required for sarea interface (1.1 and 1.2 - * clears) and 1.2 drm_vertex2 ioctl. - */ -#define RADEON_UPLOAD_CONTEXT 0x00000001 -#define RADEON_UPLOAD_VERTFMT 0x00000002 -#define RADEON_UPLOAD_LINE 0x00000004 -#define RADEON_UPLOAD_BUMPMAP 0x00000008 -#define RADEON_UPLOAD_MASKS 0x00000010 -#define RADEON_UPLOAD_VIEWPORT 0x00000020 -#define RADEON_UPLOAD_SETUP 0x00000040 -#define RADEON_UPLOAD_TCL 0x00000080 -#define RADEON_UPLOAD_MISC 0x00000100 -#define RADEON_UPLOAD_TEX0 0x00000200 -#define RADEON_UPLOAD_TEX1 0x00000400 -#define RADEON_UPLOAD_TEX2 0x00000800 -#define RADEON_UPLOAD_TEX0IMAGES 0x00001000 -#define RADEON_UPLOAD_TEX1IMAGES 0x00002000 -#define RADEON_UPLOAD_TEX2IMAGES 0x00004000 -#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */ -#define RADEON_REQUIRE_QUIESCENCE 0x00010000 -#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */ -#define RADEON_UPLOAD_ALL 0x003effff -#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff - -/* New style per-packet identifiers for use in cmd_buffer ioctl with - * the RADEON_EMIT_PACKET command. Comments relate new packets to old - * state bits and the packet size: - */ -#define RADEON_EMIT_PP_MISC 0 /* context/7 */ -#define RADEON_EMIT_PP_CNTL 1 /* context/3 */ -#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */ -#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */ -#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */ -#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */ -#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */ -#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */ -#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */ -#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */ -#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */ -#define RADEON_EMIT_RE_MISC 11 /* misc/1 */ -#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */ -#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */ -#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */ -#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */ -#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */ -#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */ -#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */ -#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */ -#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */ -#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */ -#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */ -#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */ -#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */ -#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */ -#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */ -#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */ -#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */ -#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */ -#define R200_EMIT_TFACTOR_0 30 /* tf/7 */ -#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */ -#define R200_EMIT_VAP_CTL 32 /* vap/1 */ -#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */ -#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */ -#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */ -#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */ -#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */ -#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */ -#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */ -#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */ -#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */ -#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */ -#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */ -#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */ -#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */ -#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */ -#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */ -#define R200_EMIT_VTE_CNTL 48 /* vte/1 */ -#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */ -#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */ -#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */ -#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */ -#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */ -#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */ -#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */ -#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */ -#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */ -#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */ -#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */ -#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */ -#define R200_EMIT_PP_CUBIC_FACES_0 61 -#define R200_EMIT_PP_CUBIC_OFFSETS_0 62 -#define R200_EMIT_PP_CUBIC_FACES_1 63 -#define R200_EMIT_PP_CUBIC_OFFSETS_1 64 -#define R200_EMIT_PP_CUBIC_FACES_2 65 -#define R200_EMIT_PP_CUBIC_OFFSETS_2 66 -#define R200_EMIT_PP_CUBIC_FACES_3 67 -#define R200_EMIT_PP_CUBIC_OFFSETS_3 68 -#define R200_EMIT_PP_CUBIC_FACES_4 69 -#define R200_EMIT_PP_CUBIC_OFFSETS_4 70 -#define R200_EMIT_PP_CUBIC_FACES_5 71 -#define R200_EMIT_PP_CUBIC_OFFSETS_5 72 -#define RADEON_EMIT_PP_TEX_SIZE_0 73 -#define RADEON_EMIT_PP_TEX_SIZE_1 74 -#define RADEON_EMIT_PP_TEX_SIZE_2 75 -#define R200_EMIT_RB3D_BLENDCOLOR 76 -#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77 -#define RADEON_EMIT_PP_CUBIC_FACES_0 78 -#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79 -#define RADEON_EMIT_PP_CUBIC_FACES_1 80 -#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81 -#define RADEON_EMIT_PP_CUBIC_FACES_2 82 -#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83 -#define R200_EMIT_PP_TRI_PERF_CNTL 84 -#define R200_EMIT_PP_AFS_0 85 -#define R200_EMIT_PP_AFS_1 86 -#define R200_EMIT_ATF_TFACTOR 87 -#define R200_EMIT_PP_TXCTLALL_0 88 -#define R200_EMIT_PP_TXCTLALL_1 89 -#define R200_EMIT_PP_TXCTLALL_2 90 -#define R200_EMIT_PP_TXCTLALL_3 91 -#define R200_EMIT_PP_TXCTLALL_4 92 -#define R200_EMIT_PP_TXCTLALL_5 93 -#define R200_EMIT_VAP_PVS_CNTL 94 -#define RADEON_MAX_STATE_PACKETS 95 - -/* Commands understood by cmd_buffer ioctl. More can be added but - * obviously these can't be removed or changed: - */ -#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */ -#define RADEON_CMD_SCALARS 2 /* emit scalar data */ -#define RADEON_CMD_VECTORS 3 /* emit vector data */ -#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */ -#define RADEON_CMD_PACKET3 5 /* emit hw packet */ -#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */ -#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */ -#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note: - * doesn't make the cpu wait, just - * the graphics hardware */ -#define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */ - -typedef union { - int i; - struct { - unsigned char cmd_type, pad0, pad1, pad2; - } header; - struct { - unsigned char cmd_type, packet_id, pad0, pad1; - } packet; - struct { - unsigned char cmd_type, offset, stride, count; - } scalars; - struct { - unsigned char cmd_type, offset, stride, count; - } vectors; - struct { - unsigned char cmd_type, addr_lo, addr_hi, count; - } veclinear; - struct { - unsigned char cmd_type, buf_idx, pad0, pad1; - } dma; - struct { - unsigned char cmd_type, flags, pad0, pad1; - } wait; -} drm_radeon_cmd_header_t; - -#define RADEON_WAIT_2D 0x1 -#define RADEON_WAIT_3D 0x2 - -/* Allowed parameters for R300_CMD_PACKET3 - */ -#define R300_CMD_PACKET3_CLEAR 0 -#define R300_CMD_PACKET3_RAW 1 - -/* Commands understood by cmd_buffer ioctl for R300. - * The interface has not been stabilized, so some of these may be removed - * and eventually reordered before stabilization. - */ -#define R300_CMD_PACKET0 1 -#define R300_CMD_VPU 2 /* emit vertex program upload */ -#define R300_CMD_PACKET3 3 /* emit a packet3 */ -#define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */ -#define R300_CMD_CP_DELAY 5 -#define R300_CMD_DMA_DISCARD 6 -#define R300_CMD_WAIT 7 -# define R300_WAIT_2D 0x1 -# define R300_WAIT_3D 0x2 -/* these two defines are DOING IT WRONG - however - * we have userspace which relies on using these. - * The wait interface is backwards compat new - * code should use the NEW_WAIT defines below - * THESE ARE NOT BIT FIELDS - */ -# define R300_WAIT_2D_CLEAN 0x3 -# define R300_WAIT_3D_CLEAN 0x4 - -# define R300_NEW_WAIT_2D_3D 0x3 -# define R300_NEW_WAIT_2D_2D_CLEAN 0x4 -# define R300_NEW_WAIT_3D_3D_CLEAN 0x6 -# define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8 - -#define R300_CMD_SCRATCH 8 -#define R300_CMD_R500FP 9 - -typedef union { - unsigned int u; - struct { - unsigned char cmd_type, pad0, pad1, pad2; - } header; - struct { - unsigned char cmd_type, count, reglo, reghi; - } packet0; - struct { - unsigned char cmd_type, count, adrlo, adrhi; - } vpu; - struct { - unsigned char cmd_type, packet, pad0, pad1; - } packet3; - struct { - unsigned char cmd_type, packet; - unsigned short count; /* amount of packet2 to emit */ - } delay; - struct { - unsigned char cmd_type, buf_idx, pad0, pad1; - } dma; - struct { - unsigned char cmd_type, flags, pad0, pad1; - } wait; - struct { - unsigned char cmd_type, reg, n_bufs, flags; - } scratch; - struct { - unsigned char cmd_type, count, adrlo, adrhi_flags; - } r500fp; -} drm_r300_cmd_header_t; - -#define RADEON_FRONT 0x1 -#define RADEON_BACK 0x2 -#define RADEON_DEPTH 0x4 -#define RADEON_STENCIL 0x8 -#define RADEON_CLEAR_FASTZ 0x80000000 -#define RADEON_USE_HIERZ 0x40000000 -#define RADEON_USE_COMP_ZBUF 0x20000000 - -#define R500FP_CONSTANT_TYPE (1 << 1) -#define R500FP_CONSTANT_CLAMP (1 << 2) - -/* Primitive types - */ -#define RADEON_POINTS 0x1 -#define RADEON_LINES 0x2 -#define RADEON_LINE_STRIP 0x3 -#define RADEON_TRIANGLES 0x4 -#define RADEON_TRIANGLE_FAN 0x5 -#define RADEON_TRIANGLE_STRIP 0x6 - -/* Vertex/indirect buffer size - */ -#define RADEON_BUFFER_SIZE 65536 - -/* Byte offsets for indirect buffer data - */ -#define RADEON_INDEX_PRIM_OFFSET 20 - -#define RADEON_SCRATCH_REG_OFFSET 32 - -#define R600_SCRATCH_REG_OFFSET 256 - -#define RADEON_NR_SAREA_CLIPRECTS 12 - -/* There are 2 heaps (local/GART). Each region within a heap is a - * minimum of 64k, and there are at most 64 of them per heap. - */ -#define RADEON_LOCAL_TEX_HEAP 0 -#define RADEON_GART_TEX_HEAP 1 -#define RADEON_NR_TEX_HEAPS 2 -#define RADEON_NR_TEX_REGIONS 64 -#define RADEON_LOG_TEX_GRANULARITY 16 - -#define RADEON_MAX_TEXTURE_LEVELS 12 -#define RADEON_MAX_TEXTURE_UNITS 3 - -#define RADEON_MAX_SURFACES 8 - -/* Blits have strict offset rules. All blit offset must be aligned on - * a 1K-byte boundary. - */ -#define RADEON_OFFSET_SHIFT 10 -#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT) -#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) - -#endif /* __RADEON_SAREA_DEFINES__ */ - -typedef struct { - unsigned int red; - unsigned int green; - unsigned int blue; - unsigned int alpha; -} radeon_color_regs_t; - -typedef struct { - /* Context state */ - unsigned int pp_misc; /* 0x1c14 */ - unsigned int pp_fog_color; - unsigned int re_solid_color; - unsigned int rb3d_blendcntl; - unsigned int rb3d_depthoffset; - unsigned int rb3d_depthpitch; - unsigned int rb3d_zstencilcntl; - - unsigned int pp_cntl; /* 0x1c38 */ - unsigned int rb3d_cntl; - unsigned int rb3d_coloroffset; - unsigned int re_width_height; - unsigned int rb3d_colorpitch; - unsigned int se_cntl; - - /* Vertex format state */ - unsigned int se_coord_fmt; /* 0x1c50 */ - - /* Line state */ - unsigned int re_line_pattern; /* 0x1cd0 */ - unsigned int re_line_state; - - unsigned int se_line_width; /* 0x1db8 */ - - /* Bumpmap state */ - unsigned int pp_lum_matrix; /* 0x1d00 */ - - unsigned int pp_rot_matrix_0; /* 0x1d58 */ - unsigned int pp_rot_matrix_1; - - /* Mask state */ - unsigned int rb3d_stencilrefmask; /* 0x1d7c */ - unsigned int rb3d_ropcntl; - unsigned int rb3d_planemask; - - /* Viewport state */ - unsigned int se_vport_xscale; /* 0x1d98 */ - unsigned int se_vport_xoffset; - unsigned int se_vport_yscale; - unsigned int se_vport_yoffset; - unsigned int se_vport_zscale; - unsigned int se_vport_zoffset; - - /* Setup state */ - unsigned int se_cntl_status; /* 0x2140 */ - - /* Misc state */ - unsigned int re_top_left; /* 0x26c0 */ - unsigned int re_misc; -} drm_radeon_context_regs_t; - -typedef struct { - /* Zbias state */ - unsigned int se_zbias_factor; /* 0x1dac */ - unsigned int se_zbias_constant; -} drm_radeon_context2_regs_t; - -/* Setup registers for each texture unit - */ -typedef struct { - unsigned int pp_txfilter; - unsigned int pp_txformat; - unsigned int pp_txoffset; - unsigned int pp_txcblend; - unsigned int pp_txablend; - unsigned int pp_tfactor; - unsigned int pp_border_color; -} drm_radeon_texture_regs_t; - -typedef struct { - unsigned int start; - unsigned int finish; - unsigned int prim:8; - unsigned int stateidx:8; - unsigned int numverts:16; /* overloaded as offset/64 for elt prims */ - unsigned int vc_format; /* vertex format */ -} drm_radeon_prim_t; - -typedef struct { - drm_radeon_context_regs_t context; - drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; - drm_radeon_context2_regs_t context2; - unsigned int dirty; -} drm_radeon_state_t; - -typedef struct { - /* The channel for communication of state information to the - * kernel on firing a vertex buffer with either of the - * obsoleted vertex/index ioctls. - */ - drm_radeon_context_regs_t context_state; - drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; - unsigned int dirty; - unsigned int vertsize; - unsigned int vc_format; - - /* The current cliprects, or a subset thereof. - */ - struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS]; - unsigned int nbox; - - /* Counters for client-side throttling of rendering clients. - */ - unsigned int last_frame; - unsigned int last_dispatch; - unsigned int last_clear; - - struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + - 1]; - unsigned int tex_age[RADEON_NR_TEX_HEAPS]; - int ctx_owner; - int pfState; /* number of 3d windows (0,1,2ormore) */ - int pfCurrentPage; /* which buffer is being displayed? */ - int crtc2_base; /* CRTC2 frame offset */ - int tiling_enabled; /* set by drm, read by 2d + 3d clients */ -} drm_radeon_sarea_t; - -/* WARNING: If you change any of these defines, make sure to change the - * defines in the Xserver file (xf86drmRadeon.h) - * - * KW: actually it's illegal to change any of this (backwards compatibility). - */ - -/* Radeon specific ioctls - * The device specific ioctl range is 0x40 to 0x79. - */ -#define DRM_RADEON_CP_INIT 0x00 -#define DRM_RADEON_CP_START 0x01 -#define DRM_RADEON_CP_STOP 0x02 -#define DRM_RADEON_CP_RESET 0x03 -#define DRM_RADEON_CP_IDLE 0x04 -#define DRM_RADEON_RESET 0x05 -#define DRM_RADEON_FULLSCREEN 0x06 -#define DRM_RADEON_SWAP 0x07 -#define DRM_RADEON_CLEAR 0x08 -#define DRM_RADEON_VERTEX 0x09 -#define DRM_RADEON_INDICES 0x0A -#define DRM_RADEON_NOT_USED -#define DRM_RADEON_STIPPLE 0x0C -#define DRM_RADEON_INDIRECT 0x0D -#define DRM_RADEON_TEXTURE 0x0E -#define DRM_RADEON_VERTEX2 0x0F -#define DRM_RADEON_CMDBUF 0x10 -#define DRM_RADEON_GETPARAM 0x11 -#define DRM_RADEON_FLIP 0x12 -#define DRM_RADEON_ALLOC 0x13 -#define DRM_RADEON_FREE 0x14 -#define DRM_RADEON_INIT_HEAP 0x15 -#define DRM_RADEON_IRQ_EMIT 0x16 -#define DRM_RADEON_IRQ_WAIT 0x17 -#define DRM_RADEON_CP_RESUME 0x18 -#define DRM_RADEON_SETPARAM 0x19 -#define DRM_RADEON_SURF_ALLOC 0x1a -#define DRM_RADEON_SURF_FREE 0x1b -/* KMS ioctl */ -#define DRM_RADEON_GEM_INFO 0x1c -#define DRM_RADEON_GEM_CREATE 0x1d -#define DRM_RADEON_GEM_MMAP 0x1e -#define DRM_RADEON_GEM_PREAD 0x21 -#define DRM_RADEON_GEM_PWRITE 0x22 -#define DRM_RADEON_GEM_SET_DOMAIN 0x23 -#define DRM_RADEON_GEM_WAIT_IDLE 0x24 -#define DRM_RADEON_CS 0x26 -#define DRM_RADEON_INFO 0x27 -#define DRM_RADEON_GEM_SET_TILING 0x28 -#define DRM_RADEON_GEM_GET_TILING 0x29 -#define DRM_RADEON_GEM_BUSY 0x2a -#define DRM_RADEON_GEM_VA 0x2b -#define DRM_RADEON_GEM_OP 0x2c -#define DRM_RADEON_GEM_USERPTR 0x2d - -#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) -#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) -#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) -#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET) -#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE) -#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET) -#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t) -#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP) -#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t) -#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t) -#define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t) -#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t) -#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t) -#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t) -#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t) -#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t) -#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t) -#define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP) -#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t) -#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t) -#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t) -#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t) -#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) -#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) -#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) -#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t) -#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t) -/* KMS */ -#define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info) -#define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create) -#define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap) -#define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread) -#define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite) -#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain) -#define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle) -#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs) -#define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info) -#define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling) -#define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling) -#define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy) -#define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va) -#define DRM_IOCTL_RADEON_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_OP, struct drm_radeon_gem_op) -#define DRM_IOCTL_RADEON_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_USERPTR, struct drm_radeon_gem_userptr) - -typedef struct drm_radeon_init { - enum { - RADEON_INIT_CP = 0x01, - RADEON_CLEANUP_CP = 0x02, - RADEON_INIT_R200_CP = 0x03, - RADEON_INIT_R300_CP = 0x04, - RADEON_INIT_R600_CP = 0x05 - } func; - unsigned long sarea_priv_offset; - int is_pci; - int cp_mode; - int gart_size; - int ring_size; - int usec_timeout; - - unsigned int fb_bpp; - unsigned int front_offset, front_pitch; - unsigned int back_offset, back_pitch; - unsigned int depth_bpp; - unsigned int depth_offset, depth_pitch; - - unsigned long fb_offset; - unsigned long mmio_offset; - unsigned long ring_offset; - unsigned long ring_rptr_offset; - unsigned long buffers_offset; - unsigned long gart_textures_offset; -} drm_radeon_init_t; - -typedef struct drm_radeon_cp_stop { - int flush; - int idle; -} drm_radeon_cp_stop_t; - -typedef struct drm_radeon_fullscreen { - enum { - RADEON_INIT_FULLSCREEN = 0x01, - RADEON_CLEANUP_FULLSCREEN = 0x02 - } func; -} drm_radeon_fullscreen_t; - -#define CLEAR_X1 0 -#define CLEAR_Y1 1 -#define CLEAR_X2 2 -#define CLEAR_Y2 3 -#define CLEAR_DEPTH 4 - -typedef union drm_radeon_clear_rect { - float f[5]; - unsigned int ui[5]; -} drm_radeon_clear_rect_t; - -typedef struct drm_radeon_clear { - unsigned int flags; - unsigned int clear_color; - unsigned int clear_depth; - unsigned int color_mask; - unsigned int depth_mask; /* misnamed field: should be stencil */ - drm_radeon_clear_rect_t *depth_boxes; -} drm_radeon_clear_t; - -typedef struct drm_radeon_vertex { - int prim; - int idx; /* Index of vertex buffer */ - int count; /* Number of vertices in buffer */ - int discard; /* Client finished with buffer? */ -} drm_radeon_vertex_t; - -typedef struct drm_radeon_indices { - int prim; - int idx; - int start; - int end; - int discard; /* Client finished with buffer? */ -} drm_radeon_indices_t; - -/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices - * - allows multiple primitives and state changes in a single ioctl - * - supports driver change to emit native primitives - */ -typedef struct drm_radeon_vertex2 { - int idx; /* Index of vertex buffer */ - int discard; /* Client finished with buffer? */ - int nr_states; - drm_radeon_state_t *state; - int nr_prims; - drm_radeon_prim_t *prim; -} drm_radeon_vertex2_t; - -/* v1.3 - obsoletes drm_radeon_vertex2 - * - allows arbitrarily large cliprect list - * - allows updating of tcl packet, vector and scalar state - * - allows memory-efficient description of state updates - * - allows state to be emitted without a primitive - * (for clears, ctx switches) - * - allows more than one dma buffer to be referenced per ioctl - * - supports tcl driver - * - may be extended in future versions with new cmd types, packets - */ -typedef struct drm_radeon_cmd_buffer { - int bufsz; - char *buf; - int nbox; - struct drm_clip_rect *boxes; -} drm_radeon_cmd_buffer_t; - -typedef struct drm_radeon_tex_image { - unsigned int x, y; /* Blit coordinates */ - unsigned int width, height; - const void *data; -} drm_radeon_tex_image_t; - -typedef struct drm_radeon_texture { - unsigned int offset; - int pitch; - int format; - int width; /* Texture image coordinates */ - int height; - drm_radeon_tex_image_t *image; -} drm_radeon_texture_t; - -typedef struct drm_radeon_stipple { - unsigned int *mask; -} drm_radeon_stipple_t; - -typedef struct drm_radeon_indirect { - int idx; - int start; - int end; - int discard; -} drm_radeon_indirect_t; - -/* enum for card type parameters */ -#define RADEON_CARD_PCI 0 -#define RADEON_CARD_AGP 1 -#define RADEON_CARD_PCIE 2 - -/* 1.3: An ioctl to get parameters that aren't available to the 3d - * client any other way. - */ -#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */ -#define RADEON_PARAM_LAST_FRAME 2 -#define RADEON_PARAM_LAST_DISPATCH 3 -#define RADEON_PARAM_LAST_CLEAR 4 -/* Added with DRM version 1.6. */ -#define RADEON_PARAM_IRQ_NR 5 -#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */ -/* Added with DRM version 1.8. */ -#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ -#define RADEON_PARAM_STATUS_HANDLE 8 -#define RADEON_PARAM_SAREA_HANDLE 9 -#define RADEON_PARAM_GART_TEX_HANDLE 10 -#define RADEON_PARAM_SCRATCH_OFFSET 11 -#define RADEON_PARAM_CARD_TYPE 12 -#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */ -#define RADEON_PARAM_FB_LOCATION 14 /* FB location */ -#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */ -#define RADEON_PARAM_DEVICE_ID 16 -#define RADEON_PARAM_NUM_Z_PIPES 17 /* num Z pipes */ - -typedef struct drm_radeon_getparam { - int param; - void *value; -} drm_radeon_getparam_t; - -/* 1.6: Set up a memory manager for regions of shared memory: - */ -#define RADEON_MEM_REGION_GART 1 -#define RADEON_MEM_REGION_FB 2 - -typedef struct drm_radeon_mem_alloc { - int region; - int alignment; - int size; - int *region_offset; /* offset from start of fb or GART */ -} drm_radeon_mem_alloc_t; - -typedef struct drm_radeon_mem_free { - int region; - int region_offset; -} drm_radeon_mem_free_t; - -typedef struct drm_radeon_mem_init_heap { - int region; - int size; - int start; -} drm_radeon_mem_init_heap_t; - -/* 1.6: Userspace can request & wait on irq's: - */ -typedef struct drm_radeon_irq_emit { - int *irq_seq; -} drm_radeon_irq_emit_t; - -typedef struct drm_radeon_irq_wait { - int irq_seq; -} drm_radeon_irq_wait_t; - -/* 1.10: Clients tell the DRM where they think the framebuffer is located in - * the card's address space, via a new generic ioctl to set parameters - */ - -typedef struct drm_radeon_setparam { - unsigned int param; - __s64 value; -} drm_radeon_setparam_t; - -#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */ -#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */ -#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */ -#define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */ -#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */ -#define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */ -/* 1.14: Clients can allocate/free a surface - */ -typedef struct drm_radeon_surface_alloc { - unsigned int address; - unsigned int size; - unsigned int flags; -} drm_radeon_surface_alloc_t; - -typedef struct drm_radeon_surface_free { - unsigned int address; -} drm_radeon_surface_free_t; - -#define DRM_RADEON_VBLANK_CRTC1 1 -#define DRM_RADEON_VBLANK_CRTC2 2 - -/* - * Kernel modesetting world below. - */ -#define RADEON_GEM_DOMAIN_CPU 0x1 -#define RADEON_GEM_DOMAIN_GTT 0x2 -#define RADEON_GEM_DOMAIN_VRAM 0x4 - -struct drm_radeon_gem_info { - __u64 gart_size; - __u64 vram_size; - __u64 vram_visible; -}; - -#define RADEON_GEM_NO_BACKING_STORE (1 << 0) -#define RADEON_GEM_GTT_UC (1 << 1) -#define RADEON_GEM_GTT_WC (1 << 2) -/* BO is expected to be accessed by the CPU */ -#define RADEON_GEM_CPU_ACCESS (1 << 3) -/* CPU access is not expected to work for this BO */ -#define RADEON_GEM_NO_CPU_ACCESS (1 << 4) - -struct drm_radeon_gem_create { - __u64 size; - __u64 alignment; - __u32 handle; - __u32 initial_domain; - __u32 flags; -}; - -/* - * This is not a reliable API and you should expect it to fail for any - * number of reasons and have fallback path that do not use userptr to - * perform any operation. - */ -#define RADEON_GEM_USERPTR_READONLY (1 << 0) -#define RADEON_GEM_USERPTR_ANONONLY (1 << 1) -#define RADEON_GEM_USERPTR_VALIDATE (1 << 2) -#define RADEON_GEM_USERPTR_REGISTER (1 << 3) - -struct drm_radeon_gem_userptr { - __u64 addr; - __u64 size; - __u32 flags; - __u32 handle; -}; - -#define RADEON_TILING_MACRO 0x1 -#define RADEON_TILING_MICRO 0x2 -#define RADEON_TILING_SWAP_16BIT 0x4 -#define RADEON_TILING_R600_NO_SCANOUT RADEON_TILING_SWAP_16BIT -#define RADEON_TILING_SWAP_32BIT 0x8 -/* this object requires a surface when mapped - i.e. front buffer */ -#define RADEON_TILING_SURFACE 0x10 -#define RADEON_TILING_MICRO_SQUARE 0x20 -#define RADEON_TILING_EG_BANKW_SHIFT 8 -#define RADEON_TILING_EG_BANKW_MASK 0xf -#define RADEON_TILING_EG_BANKH_SHIFT 12 -#define RADEON_TILING_EG_BANKH_MASK 0xf -#define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16 -#define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf -#define RADEON_TILING_EG_TILE_SPLIT_SHIFT 24 -#define RADEON_TILING_EG_TILE_SPLIT_MASK 0xf -#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28 -#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf - -struct drm_radeon_gem_set_tiling { - __u32 handle; - __u32 tiling_flags; - __u32 pitch; -}; - -struct drm_radeon_gem_get_tiling { - __u32 handle; - __u32 tiling_flags; - __u32 pitch; -}; - -struct drm_radeon_gem_mmap { - __u32 handle; - __u32 pad; - __u64 offset; - __u64 size; - __u64 addr_ptr; -}; - -struct drm_radeon_gem_set_domain { - __u32 handle; - __u32 read_domains; - __u32 write_domain; -}; - -struct drm_radeon_gem_wait_idle { - __u32 handle; - __u32 pad; -}; - -struct drm_radeon_gem_busy { - __u32 handle; - __u32 domain; -}; - -struct drm_radeon_gem_pread { - /** Handle for the object being read. */ - __u32 handle; - __u32 pad; - /** Offset into the object to read from */ - __u64 offset; - /** Length of data to read */ - __u64 size; - /** Pointer to write the data into. */ - /* void *, but pointers are not 32/64 compatible */ - __u64 data_ptr; -}; - -struct drm_radeon_gem_pwrite { - /** Handle for the object being written to. */ - __u32 handle; - __u32 pad; - /** Offset into the object to write to */ - __u64 offset; - /** Length of data to write */ - __u64 size; - /** Pointer to read the data from. */ - /* void *, but pointers are not 32/64 compatible */ - __u64 data_ptr; -}; - -/* Sets or returns a value associated with a buffer. */ -struct drm_radeon_gem_op { - __u32 handle; /* buffer */ - __u32 op; /* RADEON_GEM_OP_* */ - __u64 value; /* input or return value */ -}; - -#define RADEON_GEM_OP_GET_INITIAL_DOMAIN 0 -#define RADEON_GEM_OP_SET_INITIAL_DOMAIN 1 - -#define RADEON_VA_MAP 1 -#define RADEON_VA_UNMAP 2 - -#define RADEON_VA_RESULT_OK 0 -#define RADEON_VA_RESULT_ERROR 1 -#define RADEON_VA_RESULT_VA_EXIST 2 - -#define RADEON_VM_PAGE_VALID (1 << 0) -#define RADEON_VM_PAGE_READABLE (1 << 1) -#define RADEON_VM_PAGE_WRITEABLE (1 << 2) -#define RADEON_VM_PAGE_SYSTEM (1 << 3) -#define RADEON_VM_PAGE_SNOOPED (1 << 4) - -struct drm_radeon_gem_va { - __u32 handle; - __u32 operation; - __u32 vm_id; - __u32 flags; - __u64 offset; -}; - -#define RADEON_CHUNK_ID_RELOCS 0x01 -#define RADEON_CHUNK_ID_IB 0x02 -#define RADEON_CHUNK_ID_FLAGS 0x03 -#define RADEON_CHUNK_ID_CONST_IB 0x04 - -/* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */ -#define RADEON_CS_KEEP_TILING_FLAGS 0x01 -#define RADEON_CS_USE_VM 0x02 -#define RADEON_CS_END_OF_FRAME 0x04 /* a hint from userspace which CS is the last one */ -/* The second dword of RADEON_CHUNK_ID_FLAGS is a uint32 that sets the ring type */ -#define RADEON_CS_RING_GFX 0 -#define RADEON_CS_RING_COMPUTE 1 -#define RADEON_CS_RING_DMA 2 -#define RADEON_CS_RING_UVD 3 -#define RADEON_CS_RING_VCE 4 -/* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */ -/* 0 = normal, + = higher priority, - = lower priority */ - -struct drm_radeon_cs_chunk { - __u32 chunk_id; - __u32 length_dw; - __u64 chunk_data; -}; - -/* drm_radeon_cs_reloc.flags */ -#define RADEON_RELOC_PRIO_MASK (0xf << 0) - -struct drm_radeon_cs_reloc { - __u32 handle; - __u32 read_domains; - __u32 write_domain; - __u32 flags; -}; - -struct drm_radeon_cs { - __u32 num_chunks; - __u32 cs_id; - /* this points to __u64 * which point to cs chunks */ - __u64 chunks; - /* updates to the limits after this CS ioctl */ - __u64 gart_limit; - __u64 vram_limit; -}; - -#define RADEON_INFO_DEVICE_ID 0x00 -#define RADEON_INFO_NUM_GB_PIPES 0x01 -#define RADEON_INFO_NUM_Z_PIPES 0x02 -#define RADEON_INFO_ACCEL_WORKING 0x03 -#define RADEON_INFO_CRTC_FROM_ID 0x04 -#define RADEON_INFO_ACCEL_WORKING2 0x05 -#define RADEON_INFO_TILING_CONFIG 0x06 -#define RADEON_INFO_WANT_HYPERZ 0x07 -#define RADEON_INFO_WANT_CMASK 0x08 /* get access to CMASK on r300 */ -#define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 /* clock crystal frequency */ -#define RADEON_INFO_NUM_BACKENDS 0x0a /* DB/backends for r600+ - need for OQ */ -#define RADEON_INFO_NUM_TILE_PIPES 0x0b /* tile pipes for r600+ */ -#define RADEON_INFO_FUSION_GART_WORKING 0x0c /* fusion writes to GTT were broken before this */ -#define RADEON_INFO_BACKEND_MAP 0x0d /* pipe to backend map, needed by mesa */ -/* virtual address start, va < start are reserved by the kernel */ -#define RADEON_INFO_VA_START 0x0e -/* maximum size of ib using the virtual memory cs */ -#define RADEON_INFO_IB_VM_MAX_SIZE 0x0f -/* max pipes - needed for compute shaders */ -#define RADEON_INFO_MAX_PIPES 0x10 -/* timestamp for GL_ARB_timer_query (OpenGL), returns the current GPU clock */ -#define RADEON_INFO_TIMESTAMP 0x11 -/* max shader engines (SE) - needed for geometry shaders, etc. */ -#define RADEON_INFO_MAX_SE 0x12 -/* max SH per SE */ -#define RADEON_INFO_MAX_SH_PER_SE 0x13 -/* fast fb access is enabled */ -#define RADEON_INFO_FASTFB_WORKING 0x14 -/* query if a RADEON_CS_RING_* submission is supported */ -#define RADEON_INFO_RING_WORKING 0x15 -/* SI tile mode array */ -#define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16 -/* query if CP DMA is supported on the compute ring */ -#define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17 -/* CIK macrotile mode array */ -#define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18 -/* query the number of render backends */ -#define RADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19 -/* max engine clock - needed for OpenCL */ -#define RADEON_INFO_MAX_SCLK 0x1a -/* version of VCE firmware */ -#define RADEON_INFO_VCE_FW_VERSION 0x1b -/* version of VCE feedback */ -#define RADEON_INFO_VCE_FB_VERSION 0x1c -#define RADEON_INFO_NUM_BYTES_MOVED 0x1d -#define RADEON_INFO_VRAM_USAGE 0x1e -#define RADEON_INFO_GTT_USAGE 0x1f -#define RADEON_INFO_ACTIVE_CU_COUNT 0x20 -#define RADEON_INFO_CURRENT_GPU_TEMP 0x21 -#define RADEON_INFO_CURRENT_GPU_SCLK 0x22 -#define RADEON_INFO_CURRENT_GPU_MCLK 0x23 -#define RADEON_INFO_READ_REG 0x24 -#define RADEON_INFO_VA_UNMAP_WORKING 0x25 -#define RADEON_INFO_GPU_RESET_COUNTER 0x26 - -struct drm_radeon_info { - __u32 request; - __u32 pad; - __u64 value; -}; - -/* Those correspond to the tile index to use, this is to explicitly state - * the API that is implicitly defined by the tile mode array. - */ -#define SI_TILE_MODE_COLOR_LINEAR_ALIGNED 8 -#define SI_TILE_MODE_COLOR_1D 13 -#define SI_TILE_MODE_COLOR_1D_SCANOUT 9 -#define SI_TILE_MODE_COLOR_2D_8BPP 14 -#define SI_TILE_MODE_COLOR_2D_16BPP 15 -#define SI_TILE_MODE_COLOR_2D_32BPP 16 -#define SI_TILE_MODE_COLOR_2D_64BPP 17 -#define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP 11 -#define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP 12 -#define SI_TILE_MODE_DEPTH_STENCIL_1D 4 -#define SI_TILE_MODE_DEPTH_STENCIL_2D 0 -#define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA 3 -#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3 -#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2 - -#define CIK_TILE_MODE_DEPTH_STENCIL_1D 5 - -#if defined(__cplusplus) -} -#endif - -#endif diff --git a/external/include/drm/savage_drm.h b/external/include/drm/savage_drm.h deleted file mode 100644 index 1a91234..0000000 --- a/external/include/drm/savage_drm.h +++ /dev/null @@ -1,220 +0,0 @@ -/* savage_drm.h -- Public header for the savage driver - * - * Copyright 2004 Felix Kuehling - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sub license, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF - * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef __SAVAGE_DRM_H__ -#define __SAVAGE_DRM_H__ - -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -#ifndef __SAVAGE_SAREA_DEFINES__ -#define __SAVAGE_SAREA_DEFINES__ - -/* 2 heaps (1 for card, 1 for agp), each divided into up to 128 - * regions, subject to a minimum region size of (1<<16) == 64k. - * - * Clients may subdivide regions internally, but when sharing between - * clients, the region size is the minimum granularity. - */ - -#define SAVAGE_CARD_HEAP 0 -#define SAVAGE_AGP_HEAP 1 -#define SAVAGE_NR_TEX_HEAPS 2 -#define SAVAGE_NR_TEX_REGIONS 16 -#define SAVAGE_LOG_MIN_TEX_REGION_SIZE 16 - -#endif /* __SAVAGE_SAREA_DEFINES__ */ - -typedef struct _drm_savage_sarea { - /* LRU lists for texture memory in agp space and on the card. - */ - struct drm_tex_region texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS + - 1]; - unsigned int texAge[SAVAGE_NR_TEX_HEAPS]; - - /* Mechanism to validate card state. - */ - int ctxOwner; -} drm_savage_sarea_t, *drm_savage_sarea_ptr; - -/* Savage-specific ioctls - */ -#define DRM_SAVAGE_BCI_INIT 0x00 -#define DRM_SAVAGE_BCI_CMDBUF 0x01 -#define DRM_SAVAGE_BCI_EVENT_EMIT 0x02 -#define DRM_SAVAGE_BCI_EVENT_WAIT 0x03 - -#define DRM_IOCTL_SAVAGE_BCI_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_INIT, drm_savage_init_t) -#define DRM_IOCTL_SAVAGE_BCI_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_CMDBUF, drm_savage_cmdbuf_t) -#define DRM_IOCTL_SAVAGE_BCI_EVENT_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_EMIT, drm_savage_event_emit_t) -#define DRM_IOCTL_SAVAGE_BCI_EVENT_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_WAIT, drm_savage_event_wait_t) - -#define SAVAGE_DMA_PCI 1 -#define SAVAGE_DMA_AGP 3 -typedef struct drm_savage_init { - enum { - SAVAGE_INIT_BCI = 1, - SAVAGE_CLEANUP_BCI = 2 - } func; - unsigned int sarea_priv_offset; - - /* some parameters */ - unsigned int cob_size; - unsigned int bci_threshold_lo, bci_threshold_hi; - unsigned int dma_type; - - /* frame buffer layout */ - unsigned int fb_bpp; - unsigned int front_offset, front_pitch; - unsigned int back_offset, back_pitch; - unsigned int depth_bpp; - unsigned int depth_offset, depth_pitch; - - /* local textures */ - unsigned int texture_offset; - unsigned int texture_size; - - /* physical locations of non-permanent maps */ - unsigned long status_offset; - unsigned long buffers_offset; - unsigned long agp_textures_offset; - unsigned long cmd_dma_offset; -} drm_savage_init_t; - -typedef union drm_savage_cmd_header drm_savage_cmd_header_t; -typedef struct drm_savage_cmdbuf { - /* command buffer in client's address space */ - drm_savage_cmd_header_t *cmd_addr; - unsigned int size; /* size of the command buffer in 64bit units */ - - unsigned int dma_idx; /* DMA buffer index to use */ - int discard; /* discard DMA buffer when done */ - /* vertex buffer in client's address space */ - unsigned int *vb_addr; - unsigned int vb_size; /* size of client vertex buffer in bytes */ - unsigned int vb_stride; /* stride of vertices in 32bit words */ - /* boxes in client's address space */ - struct drm_clip_rect *box_addr; - unsigned int nbox; /* number of clipping boxes */ -} drm_savage_cmdbuf_t; - -#define SAVAGE_WAIT_2D 0x1 /* wait for 2D idle before updating event tag */ -#define SAVAGE_WAIT_3D 0x2 /* wait for 3D idle before updating event tag */ -#define SAVAGE_WAIT_IRQ 0x4 /* emit or wait for IRQ, not implemented yet */ -typedef struct drm_savage_event { - unsigned int count; - unsigned int flags; -} drm_savage_event_emit_t, drm_savage_event_wait_t; - -/* Commands for the cmdbuf ioctl - */ -#define SAVAGE_CMD_STATE 0 /* a range of state registers */ -#define SAVAGE_CMD_DMA_PRIM 1 /* vertices from DMA buffer */ -#define SAVAGE_CMD_VB_PRIM 2 /* vertices from client vertex buffer */ -#define SAVAGE_CMD_DMA_IDX 3 /* indexed vertices from DMA buffer */ -#define SAVAGE_CMD_VB_IDX 4 /* indexed vertices client vertex buffer */ -#define SAVAGE_CMD_CLEAR 5 /* clear buffers */ -#define SAVAGE_CMD_SWAP 6 /* swap buffers */ - -/* Primitive types -*/ -#define SAVAGE_PRIM_TRILIST 0 /* triangle list */ -#define SAVAGE_PRIM_TRISTRIP 1 /* triangle strip */ -#define SAVAGE_PRIM_TRIFAN 2 /* triangle fan */ -#define SAVAGE_PRIM_TRILIST_201 3 /* reorder verts for correct flat - * shading on s3d */ - -/* Skip flags (vertex format) - */ -#define SAVAGE_SKIP_Z 0x01 -#define SAVAGE_SKIP_W 0x02 -#define SAVAGE_SKIP_C0 0x04 -#define SAVAGE_SKIP_C1 0x08 -#define SAVAGE_SKIP_S0 0x10 -#define SAVAGE_SKIP_T0 0x20 -#define SAVAGE_SKIP_ST0 0x30 -#define SAVAGE_SKIP_S1 0x40 -#define SAVAGE_SKIP_T1 0x80 -#define SAVAGE_SKIP_ST1 0xc0 -#define SAVAGE_SKIP_ALL_S3D 0x3f -#define SAVAGE_SKIP_ALL_S4 0xff - -/* Buffer names for clear command - */ -#define SAVAGE_FRONT 0x1 -#define SAVAGE_BACK 0x2 -#define SAVAGE_DEPTH 0x4 - -/* 64-bit command header - */ -union drm_savage_cmd_header { - struct { - unsigned char cmd; /* command */ - unsigned char pad0; - unsigned short pad1; - unsigned short pad2; - unsigned short pad3; - } cmd; /* generic */ - struct { - unsigned char cmd; - unsigned char global; /* need idle engine? */ - unsigned short count; /* number of consecutive registers */ - unsigned short start; /* first register */ - unsigned short pad3; - } state; /* SAVAGE_CMD_STATE */ - struct { - unsigned char cmd; - unsigned char prim; /* primitive type */ - unsigned short skip; /* vertex format (skip flags) */ - unsigned short count; /* number of vertices */ - unsigned short start; /* first vertex in DMA/vertex buffer */ - } prim; /* SAVAGE_CMD_DMA_PRIM, SAVAGE_CMD_VB_PRIM */ - struct { - unsigned char cmd; - unsigned char prim; - unsigned short skip; - unsigned short count; /* number of indices that follow */ - unsigned short pad3; - } idx; /* SAVAGE_CMD_DMA_IDX, SAVAGE_CMD_VB_IDX */ - struct { - unsigned char cmd; - unsigned char pad0; - unsigned short pad1; - unsigned int flags; - } clear0; /* SAVAGE_CMD_CLEAR */ - struct { - unsigned int mask; - unsigned int value; - } clear1; /* SAVAGE_CMD_CLEAR data */ -}; - -#if defined(__cplusplus) -} -#endif - -#endif diff --git a/external/include/drm/sis_drm.h b/external/include/drm/sis_drm.h deleted file mode 100644 index 8e51bb9..0000000 --- a/external/include/drm/sis_drm.h +++ /dev/null @@ -1,77 +0,0 @@ -/* sis_drv.h -- Private header for sis driver -*- linux-c -*- */ -/* - * Copyright 2005 Eric Anholt - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - */ - -#ifndef __SIS_DRM_H__ -#define __SIS_DRM_H__ - -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/* SiS specific ioctls */ -#define NOT_USED_0_3 -#define DRM_SIS_FB_ALLOC 0x04 -#define DRM_SIS_FB_FREE 0x05 -#define NOT_USED_6_12 -#define DRM_SIS_AGP_INIT 0x13 -#define DRM_SIS_AGP_ALLOC 0x14 -#define DRM_SIS_AGP_FREE 0x15 -#define DRM_SIS_FB_INIT 0x16 - -#define DRM_IOCTL_SIS_FB_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_FB_ALLOC, drm_sis_mem_t) -#define DRM_IOCTL_SIS_FB_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_FB_FREE, drm_sis_mem_t) -#define DRM_IOCTL_SIS_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_AGP_INIT, drm_sis_agp_t) -#define DRM_IOCTL_SIS_AGP_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_AGP_ALLOC, drm_sis_mem_t) -#define DRM_IOCTL_SIS_AGP_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_AGP_FREE, drm_sis_mem_t) -#define DRM_IOCTL_SIS_FB_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_FB_INIT, drm_sis_fb_t) -/* -#define DRM_IOCTL_SIS_FLIP DRM_IOW( 0x48, drm_sis_flip_t) -#define DRM_IOCTL_SIS_FLIP_INIT DRM_IO( 0x49) -#define DRM_IOCTL_SIS_FLIP_FINAL DRM_IO( 0x50) -*/ - -typedef struct { - int context; - unsigned int offset; - unsigned int size; - unsigned long free; -} drm_sis_mem_t; - -typedef struct { - unsigned int offset, size; -} drm_sis_agp_t; - -typedef struct { - unsigned int offset, size; -} drm_sis_fb_t; - -#if defined(__cplusplus) -} -#endif - -#endif /* __SIS_DRM_H__ */ diff --git a/external/include/drm/tegra_drm.h b/external/include/drm/tegra_drm.h deleted file mode 100644 index 12f9bf8..0000000 --- a/external/include/drm/tegra_drm.h +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _TEGRA_DRM_H_ -#define _TEGRA_DRM_H_ - -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -#define DRM_TEGRA_GEM_CREATE_TILED (1 << 0) -#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1) - -struct drm_tegra_gem_create { - __u64 size; - __u32 flags; - __u32 handle; -}; - -struct drm_tegra_gem_mmap { - __u32 handle; - __u32 pad; - __u64 offset; -}; - -struct drm_tegra_syncpt_read { - __u32 id; - __u32 value; -}; - -struct drm_tegra_syncpt_incr { - __u32 id; - __u32 pad; -}; - -struct drm_tegra_syncpt_wait { - __u32 id; - __u32 thresh; - __u32 timeout; - __u32 value; -}; - -#define DRM_TEGRA_NO_TIMEOUT (0xffffffff) - -struct drm_tegra_open_channel { - __u32 client; - __u32 pad; - __u64 context; -}; - -struct drm_tegra_close_channel { - __u64 context; -}; - -struct drm_tegra_get_syncpt { - __u64 context; - __u32 index; - __u32 id; -}; - -struct drm_tegra_get_syncpt_base { - __u64 context; - __u32 syncpt; - __u32 id; -}; - -struct drm_tegra_syncpt { - __u32 id; - __u32 incrs; -}; - -struct drm_tegra_cmdbuf { - __u32 handle; - __u32 offset; - __u32 words; - __u32 pad; -}; - -struct drm_tegra_reloc { - struct { - __u32 handle; - __u32 offset; - } cmdbuf; - struct { - __u32 handle; - __u32 offset; - } target; - __u32 shift; - __u32 pad; -}; - -struct drm_tegra_waitchk { - __u32 handle; - __u32 offset; - __u32 syncpt; - __u32 thresh; -}; - -struct drm_tegra_submit { - __u64 context; - __u32 num_syncpts; - __u32 num_cmdbufs; - __u32 num_relocs; - __u32 num_waitchks; - __u32 waitchk_mask; - __u32 timeout; - __u64 syncpts; - __u64 cmdbufs; - __u64 relocs; - __u64 waitchks; - __u32 fence; /* Return value */ - - __u32 reserved[5]; /* future expansion */ -}; - -#define DRM_TEGRA_GEM_TILING_MODE_PITCH 0 -#define DRM_TEGRA_GEM_TILING_MODE_TILED 1 -#define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2 - -struct drm_tegra_gem_set_tiling { - /* input */ - __u32 handle; - __u32 mode; - __u32 value; - __u32 pad; -}; - -struct drm_tegra_gem_get_tiling { - /* input */ - __u32 handle; - /* output */ - __u32 mode; - __u32 value; - __u32 pad; -}; - -#define DRM_TEGRA_GEM_BOTTOM_UP (1 << 0) -#define DRM_TEGRA_GEM_FLAGS (DRM_TEGRA_GEM_BOTTOM_UP) - -struct drm_tegra_gem_set_flags { - /* input */ - __u32 handle; - /* output */ - __u32 flags; -}; - -struct drm_tegra_gem_get_flags { - /* input */ - __u32 handle; - /* output */ - __u32 flags; -}; - -#define DRM_TEGRA_GEM_CREATE 0x00 -#define DRM_TEGRA_GEM_MMAP 0x01 -#define DRM_TEGRA_SYNCPT_READ 0x02 -#define DRM_TEGRA_SYNCPT_INCR 0x03 -#define DRM_TEGRA_SYNCPT_WAIT 0x04 -#define DRM_TEGRA_OPEN_CHANNEL 0x05 -#define DRM_TEGRA_CLOSE_CHANNEL 0x06 -#define DRM_TEGRA_GET_SYNCPT 0x07 -#define DRM_TEGRA_SUBMIT 0x08 -#define DRM_TEGRA_GET_SYNCPT_BASE 0x09 -#define DRM_TEGRA_GEM_SET_TILING 0x0a -#define DRM_TEGRA_GEM_GET_TILING 0x0b -#define DRM_TEGRA_GEM_SET_FLAGS 0x0c -#define DRM_TEGRA_GEM_GET_FLAGS 0x0d - -#define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create) -#define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap) -#define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read) -#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr) -#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait) -#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel) -#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel) -#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt) -#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit) -#define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base) -#define DRM_IOCTL_TEGRA_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_TILING, struct drm_tegra_gem_set_tiling) -#define DRM_IOCTL_TEGRA_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_TILING, struct drm_tegra_gem_get_tiling) -#define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags) -#define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags) - -#if defined(__cplusplus) -} -#endif - -#endif diff --git a/external/include/drm/vc4_drm.h b/external/include/drm/vc4_drm.h index 3d35f6c..b95a0e1 100644 --- a/external/include/drm/vc4_drm.h +++ b/external/include/drm/vc4_drm.h @@ -21,8 +21,8 @@ * IN THE SOFTWARE. */ -#ifndef _VC4_DRM_H_ -#define _VC4_DRM_H_ +#ifndef _UAPI_VC4_DRM_H_ +#define _UAPI_VC4_DRM_H_ #include "drm.h" @@ -42,6 +42,9 @@ extern "C" { #define DRM_VC4_GET_TILING 0x09 #define DRM_VC4_LABEL_BO 0x0a #define DRM_VC4_GEM_MADVISE 0x0b +#define DRM_VC4_PERFMON_CREATE 0x0c +#define DRM_VC4_PERFMON_DESTROY 0x0d +#define DRM_VC4_PERFMON_GET_VALUES 0x0e #define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) #define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) @@ -55,8 +58,11 @@ extern "C" { #define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling) #define DRM_IOCTL_VC4_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo) #define DRM_IOCTL_VC4_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GEM_MADVISE, struct drm_vc4_gem_madvise) +#define DRM_IOCTL_VC4_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_CREATE, struct drm_vc4_perfmon_create) +#define DRM_IOCTL_VC4_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_DESTROY, struct drm_vc4_perfmon_destroy) +#define DRM_IOCTL_VC4_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_GET_VALUES, struct drm_vc4_perfmon_get_values) -typedef struct drm_vc4_submit_rcl_surface { +struct drm_vc4_submit_rcl_surface { __u32 hindex; /* Handle index, or ~0 if not present. */ __u32 offset; /* Offset to start of buffer. */ /* @@ -67,7 +73,7 @@ typedef struct drm_vc4_submit_rcl_surface { #define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0) __u16 flags; -} drm_vc4_submit_rcl_surface; +}; /** * struct drm_vc4_submit_cl - ioctl argument for submitting commands to the 3D @@ -82,7 +88,7 @@ typedef struct drm_vc4_submit_rcl_surface { * data to its own address space, and then validates and stores it in a GPU * BO. */ -typedef struct drm_vc4_submit_cl { +struct drm_vc4_submit_cl { /* Pointer to the binner command list. * * This is the first set of commands executed, which runs the @@ -173,7 +179,16 @@ typedef struct drm_vc4_submit_cl { * wait ioctl). */ __u64 seqno; -} drm_vc4_submit_cl; + + /* ID of the perfmon to attach to this job. 0 means no perfmon. */ + __u32 perfmonid; + + /* Unused field to align this struct on 64 bits. Must be set to 0. + * If one ever needs to add an u32 field to this struct, this field + * can be used. + */ + __u32 pad2; +}; /** * struct drm_vc4_wait_seqno - ioctl argument for waiting for @@ -182,10 +197,10 @@ typedef struct drm_vc4_submit_cl { * timeout_ns is the timeout in nanoseconds, where "0" means "don't * block, just return the status." */ -typedef struct drm_vc4_wait_seqno { +struct drm_vc4_wait_seqno { __u64 seqno; __u64 timeout_ns; -} drm_vc4_wait_seqno; +}; /** * struct drm_vc4_wait_bo - ioctl argument for waiting for @@ -195,11 +210,11 @@ typedef struct drm_vc4_wait_seqno { * rendering to a BO and you want to wait for all rendering to be * completed. */ -typedef struct drm_vc4_wait_bo { +struct drm_vc4_wait_bo { __u32 handle; __u32 pad; __u64 timeout_ns; -} drm_vc4_wait_bo; +}; /** * struct drm_vc4_create_bo - ioctl argument for creating VC4 BOs. @@ -207,13 +222,13 @@ typedef struct drm_vc4_wait_bo { * There are currently no values for the flags argument, but it may be * used in a future extension. */ -typedef struct drm_vc4_create_bo { +struct drm_vc4_create_bo { __u32 size; __u32 flags; /** Returned GEM handle for the BO. */ __u32 handle; __u32 pad; -} drm_vc4_create_bo; +}; /** * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs. @@ -226,13 +241,13 @@ typedef struct drm_vc4_create_bo { * There are currently no values for the flags argument, but it may be * used in a future extension. */ -typedef struct drm_vc4_mmap_bo { +struct drm_vc4_mmap_bo { /** Handle for the object being mapped. */ __u32 handle; __u32 flags; /** offset into the drm node to use for subsequent mmap call. */ __u64 offset; -} drm_vc4_mmap_bo; +}; /** * struct drm_vc4_create_shader_bo - ioctl argument for creating VC4 @@ -242,7 +257,7 @@ typedef struct drm_vc4_mmap_bo { * executed from would allow privlege escalation, shaders must be * created using this ioctl, and they can't be mmapped later. */ -typedef struct drm_vc4_create_shader_bo { +struct drm_vc4_create_shader_bo { /* Size of the data argument. */ __u32 size; /* Flags, currently must be 0. */ @@ -255,20 +270,20 @@ typedef struct drm_vc4_create_shader_bo { __u32 handle; /* Pad, must be 0. */ __u32 pad; -} drm_vc4_create_shader_bo; +}; -typedef struct drm_vc4_get_hang_state_bo { +struct drm_vc4_get_hang_state_bo { __u32 handle; __u32 paddr; __u32 size; __u32 pad; -} drm_vc4_get_hang_state_bo; +}; /** * struct drm_vc4_hang_state - ioctl argument for collecting state * from a GPU hang for analysis. */ -typedef struct drm_vc4_get_hang_state { +struct drm_vc4_get_hang_state { /** Pointer to array of struct drm_vc4_get_hang_state_bo. */ __u64 bo; /** @@ -298,7 +313,7 @@ typedef struct drm_vc4_get_hang_state { /* Pad that we may save more registers into in the future. */ __u32 pad[16]; -} drm_vc4_get_hang_state; +}; #define DRM_VC4_PARAM_V3D_IDENT0 0 #define DRM_VC4_PARAM_V3D_IDENT1 1 @@ -308,33 +323,34 @@ typedef struct drm_vc4_get_hang_state { #define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5 #define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER 6 #define DRM_VC4_PARAM_SUPPORTS_MADVISE 7 +#define DRM_VC4_PARAM_SUPPORTS_PERFMON 8 -typedef struct drm_vc4_get_param { +struct drm_vc4_get_param { __u32 param; __u32 pad; __u64 value; -} drm_vc4_get_param; +}; -typedef struct drm_vc4_get_tiling { +struct drm_vc4_get_tiling { __u32 handle; __u32 flags; __u64 modifier; -} drm_vc4_get_tiling; +}; -typedef struct drm_vc4_set_tiling { +struct drm_vc4_set_tiling { __u32 handle; __u32 flags; __u64 modifier; -} drm_vc4_set_tiling; +}; /** * struct drm_vc4_label_bo - Attach a name to a BO for debug purposes. */ -typedef struct drm_vc4_label_bo { +struct drm_vc4_label_bo { __u32 handle; __u32 len; __u64 name; -} drm_vc4_label_bo; +}; /* * States prefixed with '__' are internal states and cannot be passed to the @@ -345,15 +361,75 @@ typedef struct drm_vc4_label_bo { #define __VC4_MADV_PURGED 2 #define __VC4_MADV_NOTSUPP 3 -typedef struct drm_vc4_gem_madvise { +struct drm_vc4_gem_madvise { __u32 handle; __u32 madv; __u32 retained; __u32 pad; -} drm_vc4_gem_madvise; +}; + +enum { + VC4_PERFCNT_FEP_VALID_PRIMS_NO_RENDER, + VC4_PERFCNT_FEP_VALID_PRIMS_RENDER, + VC4_PERFCNT_FEP_CLIPPED_QUADS, + VC4_PERFCNT_FEP_VALID_QUADS, + VC4_PERFCNT_TLB_QUADS_NOT_PASSING_STENCIL, + VC4_PERFCNT_TLB_QUADS_NOT_PASSING_Z_AND_STENCIL, + VC4_PERFCNT_TLB_QUADS_PASSING_Z_AND_STENCIL, + VC4_PERFCNT_TLB_QUADS_ZERO_COVERAGE, + VC4_PERFCNT_TLB_QUADS_NON_ZERO_COVERAGE, + VC4_PERFCNT_TLB_QUADS_WRITTEN_TO_COLOR_BUF, + VC4_PERFCNT_PLB_PRIMS_OUTSIDE_VIEWPORT, + VC4_PERFCNT_PLB_PRIMS_NEED_CLIPPING, + VC4_PERFCNT_PSE_PRIMS_REVERSED, + VC4_PERFCNT_QPU_TOTAL_IDLE_CYCLES, + VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_VERTEX_COORD_SHADING, + VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_FRAGMENT_SHADING, + VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_EXEC_VALID_INST, + VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_TMUS, + VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_SCOREBOARD, + VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_VARYINGS, + VC4_PERFCNT_QPU_TOTAL_INST_CACHE_HIT, + VC4_PERFCNT_QPU_TOTAL_INST_CACHE_MISS, + VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_HIT, + VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_MISS, + VC4_PERFCNT_TMU_TOTAL_TEXT_QUADS_PROCESSED, + VC4_PERFCNT_TMU_TOTAL_TEXT_CACHE_MISS, + VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VDW_STALLED, + VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VCD_STALLED, + VC4_PERFCNT_L2C_TOTAL_L2_CACHE_HIT, + VC4_PERFCNT_L2C_TOTAL_L2_CACHE_MISS, + VC4_PERFCNT_NUM_EVENTS, +}; + +#define DRM_VC4_MAX_PERF_COUNTERS 16 + +struct drm_vc4_perfmon_create { + __u32 id; + __u32 ncounters; + __u8 events[DRM_VC4_MAX_PERF_COUNTERS]; +}; + +struct drm_vc4_perfmon_destroy { + __u32 id; +}; + +/* + * Returns the values of the performance counters tracked by this + * perfmon (as an array of ncounters u64 values). + * + * No implicit synchronization is performed, so the user has to + * guarantee that any jobs using this perfmon have already been + * completed (probably by blocking on the seqno returned by the + * last exec that used the perfmon). + */ +struct drm_vc4_perfmon_get_values { + __u32 id; + __u64 values_ptr; +}; #if defined(__cplusplus) } #endif -#endif /* _VC4_DRM_H_ */ +#endif /* _UAPI_VC4_DRM_H_ */ diff --git a/external/include/drm/via_drm.h b/external/include/drm/via_drm.h deleted file mode 100644 index 8b69e81..0000000 --- a/external/include/drm/via_drm.h +++ /dev/null @@ -1,283 +0,0 @@ -/* - * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved. - * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sub license, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef _VIA_DRM_H_ -#define _VIA_DRM_H_ - -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/* WARNING: These defines must be the same as what the Xserver uses. - * if you change them, you must change the defines in the Xserver. - */ - -#ifndef _VIA_DEFINES_ -#define _VIA_DEFINES_ - -#include "via_drmclient.h" - -#define VIA_NR_SAREA_CLIPRECTS 8 -#define VIA_NR_XVMC_PORTS 10 -#define VIA_NR_XVMC_LOCKS 5 -#define VIA_MAX_CACHELINE_SIZE 64 -#define XVMCLOCKPTR(saPriv,lockNo) \ - ((__volatile__ struct drm_hw_lock *)(((((unsigned long) (saPriv)->XvMCLockArea) + \ - (VIA_MAX_CACHELINE_SIZE - 1)) & \ - ~(VIA_MAX_CACHELINE_SIZE - 1)) + \ - VIA_MAX_CACHELINE_SIZE*(lockNo))) - -/* Each region is a minimum of 64k, and there are at most 64 of them. - */ -#define VIA_NR_TEX_REGIONS 64 -#define VIA_LOG_MIN_TEX_REGION_SIZE 16 -#endif - -#define VIA_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */ -#define VIA_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */ -#define VIA_UPLOAD_CTX 0x4 -#define VIA_UPLOAD_BUFFERS 0x8 -#define VIA_UPLOAD_TEX0 0x10 -#define VIA_UPLOAD_TEX1 0x20 -#define VIA_UPLOAD_CLIPRECTS 0x40 -#define VIA_UPLOAD_ALL 0xff - -/* VIA specific ioctls */ -#define DRM_VIA_ALLOCMEM 0x00 -#define DRM_VIA_FREEMEM 0x01 -#define DRM_VIA_AGP_INIT 0x02 -#define DRM_VIA_FB_INIT 0x03 -#define DRM_VIA_MAP_INIT 0x04 -#define DRM_VIA_DEC_FUTEX 0x05 -#define NOT_USED -#define DRM_VIA_DMA_INIT 0x07 -#define DRM_VIA_CMDBUFFER 0x08 -#define DRM_VIA_FLUSH 0x09 -#define DRM_VIA_PCICMD 0x0a -#define DRM_VIA_CMDBUF_SIZE 0x0b -#define NOT_USED -#define DRM_VIA_WAIT_IRQ 0x0d -#define DRM_VIA_DMA_BLIT 0x0e -#define DRM_VIA_BLIT_SYNC 0x0f - -#define DRM_IOCTL_VIA_ALLOCMEM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_ALLOCMEM, drm_via_mem_t) -#define DRM_IOCTL_VIA_FREEMEM DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_FREEMEM, drm_via_mem_t) -#define DRM_IOCTL_VIA_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_AGP_INIT, drm_via_agp_t) -#define DRM_IOCTL_VIA_FB_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT, drm_via_fb_t) -#define DRM_IOCTL_VIA_MAP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT, drm_via_init_t) -#define DRM_IOCTL_VIA_DEC_FUTEX DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_DEC_FUTEX, drm_via_futex_t) -#define DRM_IOCTL_VIA_DMA_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT, drm_via_dma_init_t) -#define DRM_IOCTL_VIA_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t) -#define DRM_IOCTL_VIA_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_VIA_FLUSH) -#define DRM_IOCTL_VIA_PCICMD DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t) -#define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_CMDBUF_SIZE, \ - drm_via_cmdbuf_size_t) -#define DRM_IOCTL_VIA_WAIT_IRQ DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_WAIT_IRQ, drm_via_irqwait_t) -#define DRM_IOCTL_VIA_DMA_BLIT DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DMA_BLIT, drm_via_dmablit_t) -#define DRM_IOCTL_VIA_BLIT_SYNC DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_BLIT_SYNC, drm_via_blitsync_t) - -/* Indices into buf.Setup where various bits of state are mirrored per - * context and per buffer. These can be fired at the card as a unit, - * or in a piecewise fashion as required. - */ - -#define VIA_TEX_SETUP_SIZE 8 - -/* Flags for clear ioctl - */ -#define VIA_FRONT 0x1 -#define VIA_BACK 0x2 -#define VIA_DEPTH 0x4 -#define VIA_STENCIL 0x8 -#define VIA_MEM_VIDEO 0 /* matches drm constant */ -#define VIA_MEM_AGP 1 /* matches drm constant */ -#define VIA_MEM_SYSTEM 2 -#define VIA_MEM_MIXED 3 -#define VIA_MEM_UNKNOWN 4 - -typedef struct { - __u32 offset; - __u32 size; -} drm_via_agp_t; - -typedef struct { - __u32 offset; - __u32 size; -} drm_via_fb_t; - -typedef struct { - __u32 context; - __u32 type; - __u32 size; - unsigned long index; - unsigned long offset; -} drm_via_mem_t; - -typedef struct _drm_via_init { - enum { - VIA_INIT_MAP = 0x01, - VIA_CLEANUP_MAP = 0x02 - } func; - - unsigned long sarea_priv_offset; - unsigned long fb_offset; - unsigned long mmio_offset; - unsigned long agpAddr; -} drm_via_init_t; - -typedef struct _drm_via_futex { - enum { - VIA_FUTEX_WAIT = 0x00, - VIA_FUTEX_WAKE = 0X01 - } func; - __u32 ms; - __u32 lock; - __u32 val; -} drm_via_futex_t; - -typedef struct _drm_via_dma_init { - enum { - VIA_INIT_DMA = 0x01, - VIA_CLEANUP_DMA = 0x02, - VIA_DMA_INITIALIZED = 0x03 - } func; - - unsigned long offset; - unsigned long size; - unsigned long reg_pause_addr; -} drm_via_dma_init_t; - -typedef struct _drm_via_cmdbuffer { - char *buf; - unsigned long size; -} drm_via_cmdbuffer_t; - -/* Warning: If you change the SAREA structure you must change the Xserver - * structure as well */ - -typedef struct _drm_via_tex_region { - unsigned char next, prev; /* indices to form a circular LRU */ - unsigned char inUse; /* owned by a client, or free? */ - int age; /* tracked by clients to update local LRU's */ -} drm_via_tex_region_t; - -typedef struct _drm_via_sarea { - unsigned int dirty; - unsigned int nbox; - struct drm_clip_rect boxes[VIA_NR_SAREA_CLIPRECTS]; - drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1]; - int texAge; /* last time texture was uploaded */ - int ctxOwner; /* last context to upload state */ - int vertexPrim; - - /* - * Below is for XvMC. - * We want the lock integers alone on, and aligned to, a cache line. - * Therefore this somewhat strange construct. - */ - - char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)]; - - unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS]; - unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS]; - unsigned int XvMCCtxNoGrabbed; /* Last context to hold decoder */ - - /* Used by the 3d driver only at this point, for pageflipping: - */ - unsigned int pfCurrentOffset; -} drm_via_sarea_t; - -typedef struct _drm_via_cmdbuf_size { - enum { - VIA_CMDBUF_SPACE = 0x01, - VIA_CMDBUF_LAG = 0x02 - } func; - int wait; - __u32 size; -} drm_via_cmdbuf_size_t; - -typedef enum { - VIA_IRQ_ABSOLUTE = 0x0, - VIA_IRQ_RELATIVE = 0x1, - VIA_IRQ_SIGNAL = 0x10000000, - VIA_IRQ_FORCE_SEQUENCE = 0x20000000 -} via_irq_seq_type_t; - -#define VIA_IRQ_FLAGS_MASK 0xF0000000 - -enum drm_via_irqs { - drm_via_irq_hqv0 = 0, - drm_via_irq_hqv1, - drm_via_irq_dma0_dd, - drm_via_irq_dma0_td, - drm_via_irq_dma1_dd, - drm_via_irq_dma1_td, - drm_via_irq_num -}; - -struct drm_via_wait_irq_request { - unsigned irq; - via_irq_seq_type_t type; - __u32 sequence; - __u32 signal; -}; - -typedef union drm_via_irqwait { - struct drm_via_wait_irq_request request; - struct drm_wait_vblank_reply reply; -} drm_via_irqwait_t; - -typedef struct drm_via_blitsync { - __u32 sync_handle; - unsigned engine; -} drm_via_blitsync_t; - -/* - * Below,"flags" is currently unused but will be used for possible future - * extensions like kernel space bounce buffers for bad alignments and - * blit engine busy-wait polling for better latency in the absence of - * interrupts. - */ - -typedef struct drm_via_dmablit { - __u32 num_lines; - __u32 line_length; - - __u32 fb_addr; - __u32 fb_stride; - - unsigned char *mem_addr; - __u32 mem_stride; - - __u32 flags; - int to_fb; - - drm_via_blitsync_t sync; -} drm_via_dmablit_t; - -#if defined(__cplusplus) -} -#endif - -#endif /* _VIA_DRM_H_ */ diff --git a/external/include/drm/virtgpu_drm.h b/external/include/drm/virtgpu_drm.h deleted file mode 100644 index 91a31ff..0000000 --- a/external/include/drm/virtgpu_drm.h +++ /dev/null @@ -1,174 +0,0 @@ -/* - * Copyright 2013 Red Hat - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef VIRTGPU_DRM_H -#define VIRTGPU_DRM_H - -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/* Please note that modifications to all structs defined here are - * subject to backwards-compatibility constraints. - * - * Do not use pointers, use __u64 instead for 32 bit / 64 bit user/kernel - * compatibility Keep fields aligned to their size - */ - -#define DRM_VIRTGPU_MAP 0x01 -#define DRM_VIRTGPU_EXECBUFFER 0x02 -#define DRM_VIRTGPU_GETPARAM 0x03 -#define DRM_VIRTGPU_RESOURCE_CREATE 0x04 -#define DRM_VIRTGPU_RESOURCE_INFO 0x05 -#define DRM_VIRTGPU_TRANSFER_FROM_HOST 0x06 -#define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07 -#define DRM_VIRTGPU_WAIT 0x08 -#define DRM_VIRTGPU_GET_CAPS 0x09 - -struct drm_virtgpu_map { - __u64 offset; /* use for mmap system call */ - __u32 handle; - __u32 pad; -}; - -struct drm_virtgpu_execbuffer { - __u32 flags; /* for future use */ - __u32 size; - __u64 command; /* void* */ - __u64 bo_handles; - __u32 num_bo_handles; - __u32 pad; -}; - -#define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */ - -struct drm_virtgpu_getparam { - __u64 param; - __u64 value; -}; - -/* NO_BO flags? NO resource flag? */ -/* resource flag for y_0_top */ -struct drm_virtgpu_resource_create { - __u32 target; - __u32 format; - __u32 bind; - __u32 width; - __u32 height; - __u32 depth; - __u32 array_size; - __u32 last_level; - __u32 nr_samples; - __u32 flags; - __u32 bo_handle; /* if this is set - recreate a new resource attached to this bo ? */ - __u32 res_handle; /* returned by kernel */ - __u32 size; /* validate transfer in the host */ - __u32 stride; /* validate transfer in the host */ -}; - -struct drm_virtgpu_resource_info { - __u32 bo_handle; - __u32 res_handle; - __u32 size; - __u32 stride; -}; - -struct drm_virtgpu_3d_box { - __u32 x; - __u32 y; - __u32 z; - __u32 w; - __u32 h; - __u32 d; -}; - -struct drm_virtgpu_3d_transfer_to_host { - __u32 bo_handle; - struct drm_virtgpu_3d_box box; - __u32 level; - __u32 offset; -}; - -struct drm_virtgpu_3d_transfer_from_host { - __u32 bo_handle; - struct drm_virtgpu_3d_box box; - __u32 level; - __u32 offset; -}; - -#define VIRTGPU_WAIT_NOWAIT 1 /* like it */ -struct drm_virtgpu_3d_wait { - __u32 handle; /* 0 is an invalid handle */ - __u32 flags; -}; - -struct drm_virtgpu_get_caps { - __u32 cap_set_id; - __u32 cap_set_ver; - __u64 addr; - __u32 size; - __u32 pad; -}; - -#define DRM_IOCTL_VIRTGPU_MAP \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map) - -#define DRM_IOCTL_VIRTGPU_EXECBUFFER \ - DRM_IOW(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\ - struct drm_virtgpu_execbuffer) - -#define DRM_IOCTL_VIRTGPU_GETPARAM \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM,\ - struct drm_virtgpu_getparam) - -#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE, \ - struct drm_virtgpu_resource_create) - -#define DRM_IOCTL_VIRTGPU_RESOURCE_INFO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, \ - struct drm_virtgpu_resource_info) - -#define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, \ - struct drm_virtgpu_3d_transfer_from_host) - -#define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST, \ - struct drm_virtgpu_3d_transfer_to_host) - -#define DRM_IOCTL_VIRTGPU_WAIT \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT, \ - struct drm_virtgpu_3d_wait) - -#define DRM_IOCTL_VIRTGPU_GET_CAPS \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \ - struct drm_virtgpu_get_caps) - -#if defined(__cplusplus) -} -#endif - -#endif diff --git a/external/include/drm/vmwgfx_drm.h b/external/include/drm/vmwgfx_drm.h deleted file mode 100644 index d325a41..0000000 --- a/external/include/drm/vmwgfx_drm.h +++ /dev/null @@ -1,1099 +0,0 @@ -/************************************************************************** - * - * Copyright © 2009-2015 VMware, Inc., Palo Alto, CA., USA - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. - * - **************************************************************************/ - -#ifndef __VMWGFX_DRM_H__ -#define __VMWGFX_DRM_H__ - -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -#define DRM_VMW_MAX_SURFACE_FACES 6 -#define DRM_VMW_MAX_MIP_LEVELS 24 - - -#define DRM_VMW_GET_PARAM 0 -#define DRM_VMW_ALLOC_DMABUF 1 -#define DRM_VMW_UNREF_DMABUF 2 -#define DRM_VMW_CURSOR_BYPASS 3 -/* guarded by DRM_VMW_PARAM_NUM_STREAMS != 0*/ -#define DRM_VMW_CONTROL_STREAM 4 -#define DRM_VMW_CLAIM_STREAM 5 -#define DRM_VMW_UNREF_STREAM 6 -/* guarded by DRM_VMW_PARAM_3D == 1 */ -#define DRM_VMW_CREATE_CONTEXT 7 -#define DRM_VMW_UNREF_CONTEXT 8 -#define DRM_VMW_CREATE_SURFACE 9 -#define DRM_VMW_UNREF_SURFACE 10 -#define DRM_VMW_REF_SURFACE 11 -#define DRM_VMW_EXECBUF 12 -#define DRM_VMW_GET_3D_CAP 13 -#define DRM_VMW_FENCE_WAIT 14 -#define DRM_VMW_FENCE_SIGNALED 15 -#define DRM_VMW_FENCE_UNREF 16 -#define DRM_VMW_FENCE_EVENT 17 -#define DRM_VMW_PRESENT 18 -#define DRM_VMW_PRESENT_READBACK 19 -#define DRM_VMW_UPDATE_LAYOUT 20 -#define DRM_VMW_CREATE_SHADER 21 -#define DRM_VMW_UNREF_SHADER 22 -#define DRM_VMW_GB_SURFACE_CREATE 23 -#define DRM_VMW_GB_SURFACE_REF 24 -#define DRM_VMW_SYNCCPU 25 -#define DRM_VMW_CREATE_EXTENDED_CONTEXT 26 - -/*************************************************************************/ -/** - * DRM_VMW_GET_PARAM - get device information. - * - * DRM_VMW_PARAM_FIFO_OFFSET: - * Offset to use to map the first page of the FIFO read-only. - * The fifo is mapped using the mmap() system call on the drm device. - * - * DRM_VMW_PARAM_OVERLAY_IOCTL: - * Does the driver support the overlay ioctl. - */ - -#define DRM_VMW_PARAM_NUM_STREAMS 0 -#define DRM_VMW_PARAM_NUM_FREE_STREAMS 1 -#define DRM_VMW_PARAM_3D 2 -#define DRM_VMW_PARAM_HW_CAPS 3 -#define DRM_VMW_PARAM_FIFO_CAPS 4 -#define DRM_VMW_PARAM_MAX_FB_SIZE 5 -#define DRM_VMW_PARAM_FIFO_HW_VERSION 6 -#define DRM_VMW_PARAM_MAX_SURF_MEMORY 7 -#define DRM_VMW_PARAM_3D_CAPS_SIZE 8 -#define DRM_VMW_PARAM_MAX_MOB_MEMORY 9 -#define DRM_VMW_PARAM_MAX_MOB_SIZE 10 -#define DRM_VMW_PARAM_SCREEN_TARGET 11 -#define DRM_VMW_PARAM_DX 12 - -/** - * enum drm_vmw_handle_type - handle type for ref ioctls - * - */ -enum drm_vmw_handle_type { - DRM_VMW_HANDLE_LEGACY = 0, - DRM_VMW_HANDLE_PRIME = 1 -}; - -/** - * struct drm_vmw_getparam_arg - * - * @value: Returned value. //Out - * @param: Parameter to query. //In. - * - * Argument to the DRM_VMW_GET_PARAM Ioctl. - */ - -struct drm_vmw_getparam_arg { - __u64 value; - __u32 param; - __u32 pad64; -}; - -/*************************************************************************/ -/** - * DRM_VMW_CREATE_CONTEXT - Create a host context. - * - * Allocates a device unique context id, and queues a create context command - * for the host. Does not wait for host completion. - */ - -/** - * struct drm_vmw_context_arg - * - * @cid: Device unique context ID. - * - * Output argument to the DRM_VMW_CREATE_CONTEXT Ioctl. - * Input argument to the DRM_VMW_UNREF_CONTEXT Ioctl. - */ - -struct drm_vmw_context_arg { - __s32 cid; - __u32 pad64; -}; - -/*************************************************************************/ -/** - * DRM_VMW_UNREF_CONTEXT - Create a host context. - * - * Frees a global context id, and queues a destroy host command for the host. - * Does not wait for host completion. The context ID can be used directly - * in the command stream and shows up as the same context ID on the host. - */ - -/*************************************************************************/ -/** - * DRM_VMW_CREATE_SURFACE - Create a host suface. - * - * Allocates a device unique surface id, and queues a create surface command - * for the host. Does not wait for host completion. The surface ID can be - * used directly in the command stream and shows up as the same surface - * ID on the host. - */ - -/** - * struct drm_wmv_surface_create_req - * - * @flags: Surface flags as understood by the host. - * @format: Surface format as understood by the host. - * @mip_levels: Number of mip levels for each face. - * An unused face should have 0 encoded. - * @size_addr: Address of a user-space array of sruct drm_vmw_size - * cast to an __u64 for 32-64 bit compatibility. - * The size of the array should equal the total number of mipmap levels. - * @shareable: Boolean whether other clients (as identified by file descriptors) - * may reference this surface. - * @scanout: Boolean whether the surface is intended to be used as a - * scanout. - * - * Input data to the DRM_VMW_CREATE_SURFACE Ioctl. - * Output data from the DRM_VMW_REF_SURFACE Ioctl. - */ - -struct drm_vmw_surface_create_req { - __u32 flags; - __u32 format; - __u32 mip_levels[DRM_VMW_MAX_SURFACE_FACES]; - __u64 size_addr; - __s32 shareable; - __s32 scanout; -}; - -/** - * struct drm_wmv_surface_arg - * - * @sid: Surface id of created surface or surface to destroy or reference. - * @handle_type: Handle type for DRM_VMW_REF_SURFACE Ioctl. - * - * Output data from the DRM_VMW_CREATE_SURFACE Ioctl. - * Input argument to the DRM_VMW_UNREF_SURFACE Ioctl. - * Input argument to the DRM_VMW_REF_SURFACE Ioctl. - */ - -struct drm_vmw_surface_arg { - __s32 sid; - enum drm_vmw_handle_type handle_type; -}; - -/** - * struct drm_vmw_size ioctl. - * - * @width - mip level width - * @height - mip level height - * @depth - mip level depth - * - * Description of a mip level. - * Input data to the DRM_WMW_CREATE_SURFACE Ioctl. - */ - -struct drm_vmw_size { - __u32 width; - __u32 height; - __u32 depth; - __u32 pad64; -}; - -/** - * union drm_vmw_surface_create_arg - * - * @rep: Output data as described above. - * @req: Input data as described above. - * - * Argument to the DRM_VMW_CREATE_SURFACE Ioctl. - */ - -union drm_vmw_surface_create_arg { - struct drm_vmw_surface_arg rep; - struct drm_vmw_surface_create_req req; -}; - -/*************************************************************************/ -/** - * DRM_VMW_REF_SURFACE - Reference a host surface. - * - * Puts a reference on a host surface with a give sid, as previously - * returned by the DRM_VMW_CREATE_SURFACE ioctl. - * A reference will make sure the surface isn't destroyed while we hold - * it and will allow the calling client to use the surface ID in the command - * stream. - * - * On successful return, the Ioctl returns the surface information given - * in the DRM_VMW_CREATE_SURFACE ioctl. - */ - -/** - * union drm_vmw_surface_reference_arg - * - * @rep: Output data as described above. - * @req: Input data as described above. - * - * Argument to the DRM_VMW_REF_SURFACE Ioctl. - */ - -union drm_vmw_surface_reference_arg { - struct drm_vmw_surface_create_req rep; - struct drm_vmw_surface_arg req; -}; - -/*************************************************************************/ -/** - * DRM_VMW_UNREF_SURFACE - Unreference a host surface. - * - * Clear a reference previously put on a host surface. - * When all references are gone, including the one implicitly placed - * on creation, - * a destroy surface command will be queued for the host. - * Does not wait for completion. - */ - -/*************************************************************************/ -/** - * DRM_VMW_EXECBUF - * - * Submit a command buffer for execution on the host, and return a - * fence seqno that when signaled, indicates that the command buffer has - * executed. - */ - -/** - * struct drm_vmw_execbuf_arg - * - * @commands: User-space address of a command buffer cast to an __u64. - * @command-size: Size in bytes of the command buffer. - * @throttle-us: Sleep until software is less than @throttle_us - * microseconds ahead of hardware. The driver may round this value - * to the nearest kernel tick. - * @fence_rep: User-space address of a struct drm_vmw_fence_rep cast to an - * __u64. - * @version: Allows expanding the execbuf ioctl parameters without breaking - * backwards compatibility, since user-space will always tell the kernel - * which version it uses. - * @flags: Execbuf flags. None currently. - * - * Argument to the DRM_VMW_EXECBUF Ioctl. - */ - -#define DRM_VMW_EXECBUF_VERSION 2 - -struct drm_vmw_execbuf_arg { - __u64 commands; - __u32 command_size; - __u32 throttle_us; - __u64 fence_rep; - __u32 version; - __u32 flags; - __u32 context_handle; - __u32 pad64; -}; - -/** - * struct drm_vmw_fence_rep - * - * @handle: Fence object handle for fence associated with a command submission. - * @mask: Fence flags relevant for this fence object. - * @seqno: Fence sequence number in fifo. A fence object with a lower - * seqno will signal the EXEC flag before a fence object with a higher - * seqno. This can be used by user-space to avoid kernel calls to determine - * whether a fence has signaled the EXEC flag. Note that @seqno will - * wrap at 32-bit. - * @passed_seqno: The highest seqno number processed by the hardware - * so far. This can be used to mark user-space fence objects as signaled, and - * to determine whether a fence seqno might be stale. - * @error: This member should've been set to -EFAULT on submission. - * The following actions should be take on completion: - * error == -EFAULT: Fence communication failed. The host is synchronized. - * Use the last fence id read from the FIFO fence register. - * error != 0 && error != -EFAULT: - * Fence submission failed. The host is synchronized. Use the fence_seq member. - * error == 0: All is OK, The host may not be synchronized. - * Use the fence_seq member. - * - * Input / Output data to the DRM_VMW_EXECBUF Ioctl. - */ - -struct drm_vmw_fence_rep { - __u32 handle; - __u32 mask; - __u32 seqno; - __u32 passed_seqno; - __u32 pad64; - __s32 error; -}; - -/*************************************************************************/ -/** - * DRM_VMW_ALLOC_DMABUF - * - * Allocate a DMA buffer that is visible also to the host. - * NOTE: The buffer is - * identified by a handle and an offset, which are private to the guest, but - * useable in the command stream. The guest kernel may translate these - * and patch up the command stream accordingly. In the future, the offset may - * be zero at all times, or it may disappear from the interface before it is - * fixed. - * - * The DMA buffer may stay user-space mapped in the guest at all times, - * and is thus suitable for sub-allocation. - * - * DMA buffers are mapped using the mmap() syscall on the drm device. - */ - -/** - * struct drm_vmw_alloc_dmabuf_req - * - * @size: Required minimum size of the buffer. - * - * Input data to the DRM_VMW_ALLOC_DMABUF Ioctl. - */ - -struct drm_vmw_alloc_dmabuf_req { - __u32 size; - __u32 pad64; -}; - -/** - * struct drm_vmw_dmabuf_rep - * - * @map_handle: Offset to use in the mmap() call used to map the buffer. - * @handle: Handle unique to this buffer. Used for unreferencing. - * @cur_gmr_id: GMR id to use in the command stream when this buffer is - * referenced. See not above. - * @cur_gmr_offset: Offset to use in the command stream when this buffer is - * referenced. See note above. - * - * Output data from the DRM_VMW_ALLOC_DMABUF Ioctl. - */ - -struct drm_vmw_dmabuf_rep { - __u64 map_handle; - __u32 handle; - __u32 cur_gmr_id; - __u32 cur_gmr_offset; - __u32 pad64; -}; - -/** - * union drm_vmw_dmabuf_arg - * - * @req: Input data as described above. - * @rep: Output data as described above. - * - * Argument to the DRM_VMW_ALLOC_DMABUF Ioctl. - */ - -union drm_vmw_alloc_dmabuf_arg { - struct drm_vmw_alloc_dmabuf_req req; - struct drm_vmw_dmabuf_rep rep; -}; - -/*************************************************************************/ -/** - * DRM_VMW_UNREF_DMABUF - Free a DMA buffer. - * - */ - -/** - * struct drm_vmw_unref_dmabuf_arg - * - * @handle: Handle indicating what buffer to free. Obtained from the - * DRM_VMW_ALLOC_DMABUF Ioctl. - * - * Argument to the DRM_VMW_UNREF_DMABUF Ioctl. - */ - -struct drm_vmw_unref_dmabuf_arg { - __u32 handle; - __u32 pad64; -}; - -/*************************************************************************/ -/** - * DRM_VMW_CONTROL_STREAM - Control overlays, aka streams. - * - * This IOCTL controls the overlay units of the svga device. - * The SVGA overlay units does not work like regular hardware units in - * that they do not automaticaly read back the contents of the given dma - * buffer. But instead only read back for each call to this ioctl, and - * at any point between this call being made and a following call that - * either changes the buffer or disables the stream. - */ - -/** - * struct drm_vmw_rect - * - * Defines a rectangle. Used in the overlay ioctl to define - * source and destination rectangle. - */ - -struct drm_vmw_rect { - __s32 x; - __s32 y; - __u32 w; - __u32 h; -}; - -/** - * struct drm_vmw_control_stream_arg - * - * @stream_id: Stearm to control - * @enabled: If false all following arguments are ignored. - * @handle: Handle to buffer for getting data from. - * @format: Format of the overlay as understood by the host. - * @width: Width of the overlay. - * @height: Height of the overlay. - * @size: Size of the overlay in bytes. - * @pitch: Array of pitches, the two last are only used for YUV12 formats. - * @offset: Offset from start of dma buffer to overlay. - * @src: Source rect, must be within the defined area above. - * @dst: Destination rect, x and y may be negative. - * - * Argument to the DRM_VMW_CONTROL_STREAM Ioctl. - */ - -struct drm_vmw_control_stream_arg { - __u32 stream_id; - __u32 enabled; - - __u32 flags; - __u32 color_key; - - __u32 handle; - __u32 offset; - __s32 format; - __u32 size; - __u32 width; - __u32 height; - __u32 pitch[3]; - - __u32 pad64; - struct drm_vmw_rect src; - struct drm_vmw_rect dst; -}; - -/*************************************************************************/ -/** - * DRM_VMW_CURSOR_BYPASS - Give extra information about cursor bypass. - * - */ - -#define DRM_VMW_CURSOR_BYPASS_ALL (1 << 0) -#define DRM_VMW_CURSOR_BYPASS_FLAGS (1) - -/** - * struct drm_vmw_cursor_bypass_arg - * - * @flags: Flags. - * @crtc_id: Crtc id, only used if DMR_CURSOR_BYPASS_ALL isn't passed. - * @xpos: X position of cursor. - * @ypos: Y position of cursor. - * @xhot: X hotspot. - * @yhot: Y hotspot. - * - * Argument to the DRM_VMW_CURSOR_BYPASS Ioctl. - */ - -struct drm_vmw_cursor_bypass_arg { - __u32 flags; - __u32 crtc_id; - __s32 xpos; - __s32 ypos; - __s32 xhot; - __s32 yhot; -}; - -/*************************************************************************/ -/** - * DRM_VMW_CLAIM_STREAM - Claim a single stream. - */ - -/** - * struct drm_vmw_context_arg - * - * @stream_id: Device unique context ID. - * - * Output argument to the DRM_VMW_CREATE_CONTEXT Ioctl. - * Input argument to the DRM_VMW_UNREF_CONTEXT Ioctl. - */ - -struct drm_vmw_stream_arg { - __u32 stream_id; - __u32 pad64; -}; - -/*************************************************************************/ -/** - * DRM_VMW_UNREF_STREAM - Unclaim a stream. - * - * Return a single stream that was claimed by this process. Also makes - * sure that the stream has been stopped. - */ - -/*************************************************************************/ -/** - * DRM_VMW_GET_3D_CAP - * - * Read 3D capabilities from the FIFO - * - */ - -/** - * struct drm_vmw_get_3d_cap_arg - * - * @buffer: Pointer to a buffer for capability data, cast to an __u64 - * @size: Max size to copy - * - * Input argument to the DRM_VMW_GET_3D_CAP_IOCTL - * ioctls. - */ - -struct drm_vmw_get_3d_cap_arg { - __u64 buffer; - __u32 max_size; - __u32 pad64; -}; - -/*************************************************************************/ -/** - * DRM_VMW_FENCE_WAIT - * - * Waits for a fence object to signal. The wait is interruptible, so that - * signals may be delivered during the interrupt. The wait may timeout, - * in which case the calls returns -EBUSY. If the wait is restarted, - * that is restarting without resetting @cookie_valid to zero, - * the timeout is computed from the first call. - * - * The flags argument to the DRM_VMW_FENCE_WAIT ioctl indicates what to wait - * on: - * DRM_VMW_FENCE_FLAG_EXEC: All commands ahead of the fence in the command - * stream - * have executed. - * DRM_VMW_FENCE_FLAG_QUERY: All query results resulting from query finish - * commands - * in the buffer given to the EXECBUF ioctl returning the fence object handle - * are available to user-space. - * - * DRM_VMW_WAIT_OPTION_UNREF: If this wait option is given, and the - * fenc wait ioctl returns 0, the fence object has been unreferenced after - * the wait. - */ - -#define DRM_VMW_FENCE_FLAG_EXEC (1 << 0) -#define DRM_VMW_FENCE_FLAG_QUERY (1 << 1) - -#define DRM_VMW_WAIT_OPTION_UNREF (1 << 0) - -/** - * struct drm_vmw_fence_wait_arg - * - * @handle: Fence object handle as returned by the DRM_VMW_EXECBUF ioctl. - * @cookie_valid: Must be reset to 0 on first call. Left alone on restart. - * @kernel_cookie: Set to 0 on first call. Left alone on restart. - * @timeout_us: Wait timeout in microseconds. 0 for indefinite timeout. - * @lazy: Set to 1 if timing is not critical. Allow more than a kernel tick - * before returning. - * @flags: Fence flags to wait on. - * @wait_options: Options that control the behaviour of the wait ioctl. - * - * Input argument to the DRM_VMW_FENCE_WAIT ioctl. - */ - -struct drm_vmw_fence_wait_arg { - __u32 handle; - __s32 cookie_valid; - __u64 kernel_cookie; - __u64 timeout_us; - __s32 lazy; - __s32 flags; - __s32 wait_options; - __s32 pad64; -}; - -/*************************************************************************/ -/** - * DRM_VMW_FENCE_SIGNALED - * - * Checks if a fence object is signaled.. - */ - -/** - * struct drm_vmw_fence_signaled_arg - * - * @handle: Fence object handle as returned by the DRM_VMW_EXECBUF ioctl. - * @flags: Fence object flags input to DRM_VMW_FENCE_SIGNALED ioctl - * @signaled: Out: Flags signaled. - * @sequence: Out: Highest sequence passed so far. Can be used to signal the - * EXEC flag of user-space fence objects. - * - * Input/Output argument to the DRM_VMW_FENCE_SIGNALED and DRM_VMW_FENCE_UNREF - * ioctls. - */ - -struct drm_vmw_fence_signaled_arg { - __u32 handle; - __u32 flags; - __s32 signaled; - __u32 passed_seqno; - __u32 signaled_flags; - __u32 pad64; -}; - -/*************************************************************************/ -/** - * DRM_VMW_FENCE_UNREF - * - * Unreferences a fence object, and causes it to be destroyed if there are no - * other references to it. - * - */ - -/** - * struct drm_vmw_fence_arg - * - * @handle: Fence object handle as returned by the DRM_VMW_EXECBUF ioctl. - * - * Input/Output argument to the DRM_VMW_FENCE_UNREF ioctl.. - */ - -struct drm_vmw_fence_arg { - __u32 handle; - __u32 pad64; -}; - - -/*************************************************************************/ -/** - * DRM_VMW_FENCE_EVENT - * - * Queues an event on a fence to be delivered on the drm character device - * when the fence has signaled the DRM_VMW_FENCE_FLAG_EXEC flag. - * Optionally the approximate time when the fence signaled is - * given by the event. - */ - -/* - * The event type - */ -#define DRM_VMW_EVENT_FENCE_SIGNALED 0x80000000 - -struct drm_vmw_event_fence { - struct drm_event base; - __u64 user_data; - __u32 tv_sec; - __u32 tv_usec; -}; - -/* - * Flags that may be given to the command. - */ -/* Request fence signaled time on the event. */ -#define DRM_VMW_FE_FLAG_REQ_TIME (1 << 0) - -/** - * struct drm_vmw_fence_event_arg - * - * @fence_rep: Pointer to fence_rep structure cast to __u64 or 0 if - * the fence is not supposed to be referenced by user-space. - * @user_info: Info to be delivered with the event. - * @handle: Attach the event to this fence only. - * @flags: A set of flags as defined above. - */ -struct drm_vmw_fence_event_arg { - __u64 fence_rep; - __u64 user_data; - __u32 handle; - __u32 flags; -}; - - -/*************************************************************************/ -/** - * DRM_VMW_PRESENT - * - * Executes an SVGA present on a given fb for a given surface. The surface - * is placed on the framebuffer. Cliprects are given relative to the given - * point (the point disignated by dest_{x|y}). - * - */ - -/** - * struct drm_vmw_present_arg - * @fb_id: framebuffer id to present / read back from. - * @sid: Surface id to present from. - * @dest_x: X placement coordinate for surface. - * @dest_y: Y placement coordinate for surface. - * @clips_ptr: Pointer to an array of clip rects cast to an __u64. - * @num_clips: Number of cliprects given relative to the framebuffer origin, - * in the same coordinate space as the frame buffer. - * @pad64: Unused 64-bit padding. - * - * Input argument to the DRM_VMW_PRESENT ioctl. - */ - -struct drm_vmw_present_arg { - __u32 fb_id; - __u32 sid; - __s32 dest_x; - __s32 dest_y; - __u64 clips_ptr; - __u32 num_clips; - __u32 pad64; -}; - - -/*************************************************************************/ -/** - * DRM_VMW_PRESENT_READBACK - * - * Executes an SVGA present readback from a given fb to the dma buffer - * currently bound as the fb. If there is no dma buffer bound to the fb, - * an error will be returned. - * - */ - -/** - * struct drm_vmw_present_arg - * @fb_id: fb_id to present / read back from. - * @num_clips: Number of cliprects. - * @clips_ptr: Pointer to an array of clip rects cast to an __u64. - * @fence_rep: Pointer to a struct drm_vmw_fence_rep, cast to an __u64. - * If this member is NULL, then the ioctl should not return a fence. - */ - -struct drm_vmw_present_readback_arg { - __u32 fb_id; - __u32 num_clips; - __u64 clips_ptr; - __u64 fence_rep; -}; - -/*************************************************************************/ -/** - * DRM_VMW_UPDATE_LAYOUT - Update layout - * - * Updates the preferred modes and connection status for connectors. The - * command consists of one drm_vmw_update_layout_arg pointing to an array - * of num_outputs drm_vmw_rect's. - */ - -/** - * struct drm_vmw_update_layout_arg - * - * @num_outputs: number of active connectors - * @rects: pointer to array of drm_vmw_rect cast to an __u64 - * - * Input argument to the DRM_VMW_UPDATE_LAYOUT Ioctl. - */ -struct drm_vmw_update_layout_arg { - __u32 num_outputs; - __u32 pad64; - __u64 rects; -}; - - -/*************************************************************************/ -/** - * DRM_VMW_CREATE_SHADER - Create shader - * - * Creates a shader and optionally binds it to a dma buffer containing - * the shader byte-code. - */ - -/** - * enum drm_vmw_shader_type - Shader types - */ -enum drm_vmw_shader_type { - drm_vmw_shader_type_vs = 0, - drm_vmw_shader_type_ps, -}; - - -/** - * struct drm_vmw_shader_create_arg - * - * @shader_type: Shader type of the shader to create. - * @size: Size of the byte-code in bytes. - * where the shader byte-code starts - * @buffer_handle: Buffer handle identifying the buffer containing the - * shader byte-code - * @shader_handle: On successful completion contains a handle that - * can be used to subsequently identify the shader. - * @offset: Offset in bytes into the buffer given by @buffer_handle, - * - * Input / Output argument to the DRM_VMW_CREATE_SHADER Ioctl. - */ -struct drm_vmw_shader_create_arg { - enum drm_vmw_shader_type shader_type; - __u32 size; - __u32 buffer_handle; - __u32 shader_handle; - __u64 offset; -}; - -/*************************************************************************/ -/** - * DRM_VMW_UNREF_SHADER - Unreferences a shader - * - * Destroys a user-space reference to a shader, optionally destroying - * it. - */ - -/** - * struct drm_vmw_shader_arg - * - * @handle: Handle identifying the shader to destroy. - * - * Input argument to the DRM_VMW_UNREF_SHADER ioctl. - */ -struct drm_vmw_shader_arg { - __u32 handle; - __u32 pad64; -}; - -/*************************************************************************/ -/** - * DRM_VMW_GB_SURFACE_CREATE - Create a host guest-backed surface. - * - * Allocates a surface handle and queues a create surface command - * for the host on the first use of the surface. The surface ID can - * be used as the surface ID in commands referencing the surface. - */ - -/** - * enum drm_vmw_surface_flags - * - * @drm_vmw_surface_flag_shareable: Whether the surface is shareable - * @drm_vmw_surface_flag_scanout: Whether the surface is a scanout - * surface. - * @drm_vmw_surface_flag_create_buffer: Create a backup buffer if none is - * given. - */ -enum drm_vmw_surface_flags { - drm_vmw_surface_flag_shareable = (1 << 0), - drm_vmw_surface_flag_scanout = (1 << 1), - drm_vmw_surface_flag_create_buffer = (1 << 2) -}; - -/** - * struct drm_vmw_gb_surface_create_req - * - * @svga3d_flags: SVGA3d surface flags for the device. - * @format: SVGA3d format. - * @mip_level: Number of mip levels for all faces. - * @drm_surface_flags Flags as described above. - * @multisample_count Future use. Set to 0. - * @autogen_filter Future use. Set to 0. - * @buffer_handle Buffer handle of backup buffer. SVGA3D_INVALID_ID - * if none. - * @base_size Size of the base mip level for all faces. - * @array_size Must be zero for non-DX hardware, and if non-zero - * svga3d_flags must have proper bind flags setup. - * - * Input argument to the DRM_VMW_GB_SURFACE_CREATE Ioctl. - * Part of output argument for the DRM_VMW_GB_SURFACE_REF Ioctl. - */ -struct drm_vmw_gb_surface_create_req { - __u32 svga3d_flags; - __u32 format; - __u32 mip_levels; - enum drm_vmw_surface_flags drm_surface_flags; - __u32 multisample_count; - __u32 autogen_filter; - __u32 buffer_handle; - __u32 array_size; - struct drm_vmw_size base_size; -}; - -/** - * struct drm_vmw_gb_surface_create_rep - * - * @handle: Surface handle. - * @backup_size: Size of backup buffers for this surface. - * @buffer_handle: Handle of backup buffer. SVGA3D_INVALID_ID if none. - * @buffer_size: Actual size of the buffer identified by - * @buffer_handle - * @buffer_map_handle: Offset into device address space for the buffer - * identified by @buffer_handle. - * - * Part of output argument for the DRM_VMW_GB_SURFACE_REF ioctl. - * Output argument for the DRM_VMW_GB_SURFACE_CREATE ioctl. - */ -struct drm_vmw_gb_surface_create_rep { - __u32 handle; - __u32 backup_size; - __u32 buffer_handle; - __u32 buffer_size; - __u64 buffer_map_handle; -}; - -/** - * union drm_vmw_gb_surface_create_arg - * - * @req: Input argument as described above. - * @rep: Output argument as described above. - * - * Argument to the DRM_VMW_GB_SURFACE_CREATE ioctl. - */ -union drm_vmw_gb_surface_create_arg { - struct drm_vmw_gb_surface_create_rep rep; - struct drm_vmw_gb_surface_create_req req; -}; - -/*************************************************************************/ -/** - * DRM_VMW_GB_SURFACE_REF - Reference a host surface. - * - * Puts a reference on a host surface with a given handle, as previously - * returned by the DRM_VMW_GB_SURFACE_CREATE ioctl. - * A reference will make sure the surface isn't destroyed while we hold - * it and will allow the calling client to use the surface handle in - * the command stream. - * - * On successful return, the Ioctl returns the surface information given - * to and returned from the DRM_VMW_GB_SURFACE_CREATE ioctl. - */ - -/** - * struct drm_vmw_gb_surface_reference_arg - * - * @creq: The data used as input when the surface was created, as described - * above at "struct drm_vmw_gb_surface_create_req" - * @crep: Additional data output when the surface was created, as described - * above at "struct drm_vmw_gb_surface_create_rep" - * - * Output Argument to the DRM_VMW_GB_SURFACE_REF ioctl. - */ -struct drm_vmw_gb_surface_ref_rep { - struct drm_vmw_gb_surface_create_req creq; - struct drm_vmw_gb_surface_create_rep crep; -}; - -/** - * union drm_vmw_gb_surface_reference_arg - * - * @req: Input data as described above at "struct drm_vmw_surface_arg" - * @rep: Output data as described above at "struct drm_vmw_gb_surface_ref_rep" - * - * Argument to the DRM_VMW_GB_SURFACE_REF Ioctl. - */ -union drm_vmw_gb_surface_reference_arg { - struct drm_vmw_gb_surface_ref_rep rep; - struct drm_vmw_surface_arg req; -}; - - -/*************************************************************************/ -/** - * DRM_VMW_SYNCCPU - Sync a DMA buffer / MOB for CPU access. - * - * Idles any previously submitted GPU operations on the buffer and - * by default blocks command submissions that reference the buffer. - * If the file descriptor used to grab a blocking CPU sync is closed, the - * cpu sync is released. - * The flags argument indicates how the grab / release operation should be - * performed: - */ - -/** - * enum drm_vmw_synccpu_flags - Synccpu flags: - * - * @drm_vmw_synccpu_read: Sync for read. If sync is done for read only, it's a - * hint to the kernel to allow command submissions that references the buffer - * for read-only. - * @drm_vmw_synccpu_write: Sync for write. Block all command submissions - * referencing this buffer. - * @drm_vmw_synccpu_dontblock: Dont wait for GPU idle, but rather return - * -EBUSY should the buffer be busy. - * @drm_vmw_synccpu_allow_cs: Allow command submission that touches the buffer - * while the buffer is synced for CPU. This is similar to the GEM bo idle - * behavior. - */ -enum drm_vmw_synccpu_flags { - drm_vmw_synccpu_read = (1 << 0), - drm_vmw_synccpu_write = (1 << 1), - drm_vmw_synccpu_dontblock = (1 << 2), - drm_vmw_synccpu_allow_cs = (1 << 3) -}; - -/** - * enum drm_vmw_synccpu_op - Synccpu operations: - * - * @drm_vmw_synccpu_grab: Grab the buffer for CPU operations - * @drm_vmw_synccpu_release: Release a previous grab. - */ -enum drm_vmw_synccpu_op { - drm_vmw_synccpu_grab, - drm_vmw_synccpu_release -}; - -/** - * struct drm_vmw_synccpu_arg - * - * @op: The synccpu operation as described above. - * @handle: Handle identifying the buffer object. - * @flags: Flags as described above. - */ -struct drm_vmw_synccpu_arg { - enum drm_vmw_synccpu_op op; - enum drm_vmw_synccpu_flags flags; - __u32 handle; - __u32 pad64; -}; - -/*************************************************************************/ -/** - * DRM_VMW_CREATE_EXTENDED_CONTEXT - Create a host context. - * - * Allocates a device unique context id, and queues a create context command - * for the host. Does not wait for host completion. - */ -enum drm_vmw_extended_context { - drm_vmw_context_legacy, - drm_vmw_context_dx -}; - -/** - * union drm_vmw_extended_context_arg - * - * @req: Context type. - * @rep: Context identifier. - * - * Argument to the DRM_VMW_CREATE_EXTENDED_CONTEXT Ioctl. - */ -union drm_vmw_extended_context_arg { - enum drm_vmw_extended_context req; - struct drm_vmw_context_arg rep; -}; - -#if defined(__cplusplus) -} -#endif - -#endif