mirror of
https://github.com/Yours3lf/rpi-vk-driver.git
synced 2024-11-29 11:24:14 +01:00
640 lines
19 KiB
C
640 lines
19 KiB
C
/*
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* Copyright © 2014 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef VC4_QPU_DEFINES_H
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#define VC4_QPU_DEFINES_H
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#include <assert.h>
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#include <stdint.h>
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typedef enum{
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QPU_ALU,
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QPU_SEM,
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QPU_BRANCH,
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QPU_LOAD_IMM
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} qpu_alu_type;
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typedef enum{
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QPU_LOAD32,
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QPU_LOAD16
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} qpu_load_type;
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//Condition Codes
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//The QPU keeps a set of N, Z and C flag bits per 16 SIMD element. These flags are updated based on the result
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//of the ADD ALU if the ‘sf’ bit is set. If the sf bit is set and the ADD ALU executes a NOP or its condition code was
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//NEVER, flags are set based upon the result of the MUL ALU result.
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typedef enum {
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QPU_COND_NEVER,
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QPU_COND_ALWAYS,
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QPU_COND_ZS, //set
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QPU_COND_ZC, //clear
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QPU_COND_NS,
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QPU_COND_NC,
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QPU_COND_CS,
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QPU_COND_CC,
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} qpu_cond;
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static const char *qpu_cond_str[] = {
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[QPU_COND_NEVER] = "never",
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[QPU_COND_ALWAYS] = "always",
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[QPU_COND_ZS] = "zs",
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[QPU_COND_ZC] = "zc",
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[QPU_COND_NS] = "ns",
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[QPU_COND_NC] = "nc",
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[QPU_COND_CS] = "cs",
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[QPU_COND_CC] = "cc",
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};
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//ALU Input muxes
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//selects one register for input
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//The add_a, add_b, mul_a, and mul_b fields specify the input data for the A and B ports of the ADD and MUL
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//pipelines, respectively
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typedef enum {
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/* hardware mux values */
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QPU_MUX_R0,
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QPU_MUX_R1,
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QPU_MUX_R2,
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QPU_MUX_R3,
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QPU_MUX_R4, //special purpose, read only
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QPU_MUX_R5, //special purpose
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QPU_MUX_A,
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QPU_MUX_B,
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/**
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* Non-hardware mux value, stores a small immediate field to be
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* programmed into raddr_b in the qpu_reg.index.
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*/
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QPU_MUX_SMALL_IMM,
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} qpu_mux;
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static const char *qpu_mux_str[] = {
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[QPU_MUX_R0] = "r0",
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[QPU_MUX_R1] = "r1",
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[QPU_MUX_R2] = "r2",
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[QPU_MUX_R3] = "r3",
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[QPU_MUX_R4] = "r4",
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[QPU_MUX_R5] = "r5",
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[QPU_MUX_A] = "a",
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[QPU_MUX_B] = "b",
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[QPU_MUX_SMALL_IMM] = "imm",
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};
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//Signaling Bits
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//The 4-bit signaling field signal is connected to the 3d pipeline and is set to indicate one of a number of
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//conditions to the 3d hardware. Values from this field are also used to encode a ‘BKPT’ instruction, and to
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//encode Branches and Load Immediate instructions.
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typedef enum {
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QPU_SIG_SW_BREAKPOINT,
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QPU_SIG_NONE,
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QPU_SIG_THREAD_SWITCH,
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QPU_SIG_PROG_END,
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QPU_SIG_WAIT_FOR_SCOREBOARD, //stall until this QPU can safely access tile buffer
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QPU_SIG_SCOREBOARD_UNLOCK,
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QPU_SIG_LAST_THREAD_SWITCH,
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QPU_SIG_COVERAGE_LOAD, //from tile buffer to r4
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QPU_SIG_COLOR_LOAD, //from tile buffer to r4
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QPU_SIG_COLOR_LOAD_END, //color load and program end
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QPU_SIG_LOAD_TMU0, //read data from TMU0 to r4
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QPU_SIG_LOAD_TMU1, //read data from TMU1 to r4
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QPU_SIG_ALPHA_MASK_LOAD, //from tile buffer to r4
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QPU_SIG_SMALL_IMM, //ALU instruction with raddr_b specifying small immediate or vector rotate
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QPU_SIG_LOAD_IMM, //load immediate instruction
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QPU_SIG_BRANCH
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} qpu_sig_bits;
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static const char *qpu_sig_bits_str[] = {
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[QPU_SIG_SW_BREAKPOINT] = "sig_brk",
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[QPU_SIG_NONE] = "sig_none",
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[QPU_SIG_THREAD_SWITCH] = "sig_switch",
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[QPU_SIG_PROG_END] = "sig_end",
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[QPU_SIG_WAIT_FOR_SCOREBOARD] = "sig_wait_score",
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[QPU_SIG_SCOREBOARD_UNLOCK] = "sig_unlock_score",
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[QPU_SIG_LAST_THREAD_SWITCH] = "sig_thread_switch",
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[QPU_SIG_COVERAGE_LOAD] = "sig_coverage_load",
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[QPU_SIG_COLOR_LOAD] = "sig_color_load",
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[QPU_SIG_COLOR_LOAD_END] = "sig_color_load_end",
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[QPU_SIG_LOAD_TMU0] = "sig_load_tmu0",
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[QPU_SIG_LOAD_TMU1] = "sig_load_tmu1",
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[QPU_SIG_ALPHA_MASK_LOAD] = "sig_alpha_mask_load",
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[QPU_SIG_SMALL_IMM] = "sig_small_imm",
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[QPU_SIG_LOAD_IMM] = "sig_load_imm",
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[QPU_SIG_BRANCH] = "sig_branch",
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};
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//Small immediate encoding
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//Returns the small immediate value to be encoded in to the raddr b field if
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//the argument can be represented as one, or ~0 otherwise.
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//48: Small immediate value for rotate-by-r5, and 49-63 are "rotate by n channels"
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uint8_t qpu_encode_small_immediate(uint32_t i)
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{
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if (i <= 15)
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return i;
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if ((int)i < 0 && (int)i >= -16)
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return i + 32;
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switch (i) {
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case 0x3f800000:
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return 32;
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case 0x40000000:
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return 33;
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case 0x40800000:
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return 34;
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case 0x41000000:
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return 35;
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case 0x41800000:
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return 36;
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case 0x42000000:
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return 37;
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case 0x42800000:
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return 38;
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case 0x43000000:
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return 39;
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case 0x3b800000:
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return 40;
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case 0x3c000000:
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return 41;
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case 0x3c800000:
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return 42;
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case 0x3d000000:
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return 43;
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case 0x3d800000:
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return 44;
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case 0x3e000000:
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return 45;
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case 0x3e800000:
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return 46;
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case 0x3f000000:
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return 47;
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}
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return ~0;
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}
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//QPU unpack values
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//(can be used to unpack from r4 too)
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typedef enum {
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QPU_UNPACK_NOP,
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QPU_UNPACK_16A, //from A reg: convert 16bit float to 32bit float, or 16bit int to 32bit int, depending on the instruction
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QPU_UNPACK_16B,
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QPU_UNPACK_8D_REP, //replicate most significant byte (alpha) across word: {a, a, a, a}
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QPU_UNPACK_8A, //convert 8bit color in range [0...1] to 32bit float or 32bit int, depending on the instruction
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QPU_UNPACK_8B,
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QPU_UNPACK_8C,
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QPU_UNPACK_8D,
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} qpu_unpack;
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static const char *qpu_unpack_str[] = {
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[QPU_UNPACK_NOP] = "nop",
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[QPU_UNPACK_16A] = "16a",
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[QPU_UNPACK_16B] = "16b",
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[QPU_UNPACK_8D_REP] = "8d_rep",
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[QPU_UNPACK_8A] = "8a",
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[QPU_UNPACK_8B] = "8b",
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[QPU_UNPACK_8C] = "8c",
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[QPU_UNPACK_8D] = "8d",
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};
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//QPU pack regfile A
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typedef enum {
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QPU_PACK_A_NOP,
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QPU_PACK_A_16A, //convert to 16 bit float if float input, or to int16 (just takes least significant 16bits)
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QPU_PACK_A_16B,
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QPU_PACK_A_8888, //convert to 8bit uint (just takes least significant 8bits) and replicate across all bytes of 32bit word
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QPU_PACK_A_8A, // Convert to 8-bit unsigned int. (just takes least significant 8bits)
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QPU_PACK_A_8B,
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QPU_PACK_A_8C,
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QPU_PACK_A_8D,
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// Saturating variants of the previous instructions.
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QPU_PACK_A_32_SAT, //saturate signed 32bit number (takes into account overflow/carry flags)
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QPU_PACK_A_16A_SAT, //convert to 16bit float if float input, or int16, depending on input (with saturation)
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QPU_PACK_A_16B_SAT,
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QPU_PACK_A_8888_SAT, //convert to uint8 with saturation and replicate across all bytes of 32bit word
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QPU_PACK_A_8A_SAT, //conver to uint8 with saturation
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QPU_PACK_A_8B_SAT,
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QPU_PACK_A_8C_SAT,
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QPU_PACK_A_8D_SAT,
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} qpu_pack_a;
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static const char *qpu_pack_a_str[] = {
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[QPU_PACK_A_NOP] = "nop",
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[QPU_PACK_A_16A] = "16a",
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[QPU_PACK_A_16B] = "16b",
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[QPU_PACK_A_8888] = "8888",
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[QPU_PACK_A_8A] = "8a",
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[QPU_PACK_A_8B] = "8b",
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[QPU_PACK_A_8C] = "8c",
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[QPU_PACK_A_8D] = "8d",
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[QPU_PACK_A_32_SAT] = "sat",
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[QPU_PACK_A_16A_SAT] = "16a.sat",
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[QPU_PACK_A_16B_SAT] = "16b.sat",
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[QPU_PACK_A_8888_SAT] = "8888.sat",
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[QPU_PACK_A_8A_SAT] = "8a.sat",
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[QPU_PACK_A_8B_SAT] = "8b.sat",
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[QPU_PACK_A_8C_SAT] = "8c.sat",
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[QPU_PACK_A_8D_SAT] = "8d.sat",
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};
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//QPU pack MUL ALU values
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typedef enum {
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QPU_PACK_MUL_NOP,
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QPU_PACK_MUL_8888 = 3, // converts mul float result to 8bit color in range [0...1] and replicate across all bytes of 32bit word
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QPU_PACK_MUL_8A, // converts mul float result to 8bit color in range [0...1]
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QPU_PACK_MUL_8B,
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QPU_PACK_MUL_8C,
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QPU_PACK_MUL_8D,
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} qpu_pack_mul;
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static const char *qpu_pack_mul_str[] = {
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[QPU_PACK_MUL_NOP] = "nop",
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[QPU_PACK_MUL_8888] = "8888",
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[QPU_PACK_MUL_8A] = "8a",
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[QPU_PACK_MUL_8B] = "8b",
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[QPU_PACK_MUL_8C] = "8c",
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[QPU_PACK_MUL_8D] = "8d",
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};
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typedef enum {
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QPU_COND_BRANCH_ALL_ZS, //all z flags set
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QPU_COND_BRANCH_ALL_ZC, //all z flags clear
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QPU_COND_BRANCH_ANY_ZS,
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QPU_COND_BRANCH_ANY_ZC,
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QPU_COND_BRANCH_ALL_NS,
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QPU_COND_BRANCH_ALL_NC,
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QPU_COND_BRANCH_ANY_NS,
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QPU_COND_BRANCH_ANY_NC,
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QPU_COND_BRANCH_ALL_CS,
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QPU_COND_BRANCH_ALL_CC,
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QPU_COND_BRANCH_ANY_CS,
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QPU_COND_BRANCH_ANY_CC,
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QPU_COND_BRANCH_ALWAYS = 15 //always execute
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} qpu_branch_cond;
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static const char *qpu_branch_cond_str[] = {
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[QPU_COND_BRANCH_ALL_ZS] = "all_zs",
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[QPU_COND_BRANCH_ALL_ZC] = "all_zc",
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[QPU_COND_BRANCH_ANY_ZS] = "any_zs",
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[QPU_COND_BRANCH_ANY_ZC] = "any_zc",
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[QPU_COND_BRANCH_ALL_NS] = "all_ns",
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[QPU_COND_BRANCH_ALL_NC] = "all_nc",
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[QPU_COND_BRANCH_ANY_NS] = "any_ns",
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[QPU_COND_BRANCH_ANY_NC] = "any_nc",
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[QPU_COND_BRANCH_ALL_CS] = "all_cs",
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[QPU_COND_BRANCH_ALL_CC] = "all_cc",
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[QPU_COND_BRANCH_ANY_CS] = "any_cs",
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[QPU_COND_BRANCH_ANY_CC] = "any_cc",
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[QPU_COND_BRANCH_ALWAYS] = "always",
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};
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//QPU ADD instruction set
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typedef enum {
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QPU_A_NOP,
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QPU_A_FADD, //float add
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QPU_A_FSUB,
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QPU_A_FMIN,
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QPU_A_FMAX,
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QPU_A_FMINABS, //float min(abs(x))
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QPU_A_FMAXABS,
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QPU_A_FTOI, //convert float to int
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QPU_A_ITOF, //convert int to float
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QPU_A_ADD = 12, //int add
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QPU_A_SUB,
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QPU_A_SHR, //int shift right
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QPU_A_ASR, //int arithmetic shift right
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QPU_A_ROR, //int rotate right
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QPU_A_SHL, //int shift left
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QPU_A_MIN,
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QPU_A_MAX,
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QPU_A_AND,
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QPU_A_OR,
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QPU_A_XOR,
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QPU_A_NOT,
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QPU_A_CLZ, //int count leading zeroes
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QPU_A_V8ADDS = 30, //add with saturation per 8bit element
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QPU_A_V8SUBS = 31,
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} qpu_op_add;
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static const char *qpu_op_add_str[] = {
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[QPU_A_NOP] = "nop",
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[QPU_A_FADD] = "fadd",
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[QPU_A_FSUB] = "fsub",
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[QPU_A_FMIN] = "fmin",
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[QPU_A_FMAX] = "fmax",
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[QPU_A_FMINABS] = "fminabs",
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[QPU_A_FMAXABS] = "fmaxabs",
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[QPU_A_FTOI] = "ftoi",
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[QPU_A_ITOF] = "itof",
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[QPU_A_ADD] = "add",
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[QPU_A_SUB] = "sub",
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[QPU_A_SHR] = "shr",
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[QPU_A_ASR] = "asr",
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[QPU_A_ROR] = "ror",
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[QPU_A_SHL] = "shl",
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[QPU_A_MIN] = "min",
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[QPU_A_MAX] = "max",
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[QPU_A_AND] = "and",
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[QPU_A_OR] = "or",
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[QPU_A_XOR] = "xor",
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[QPU_A_NOT] = "not",
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[QPU_A_CLZ] = "clz",
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[QPU_A_V8ADDS] = "v8adds",
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[QPU_A_V8SUBS] = "v8subs",
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};
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//QPU MUL instruction set
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typedef enum {
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QPU_M_NOP,
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QPU_M_FMUL, //float mul
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QPU_M_MUL24, //24bit int mul?
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QPU_M_V8MULD, //mul two vectors of 8bit ints in range [0...1]
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QPU_M_V8MIN,
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QPU_M_V8MAX,
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QPU_M_V8ADDS, //add two vectors of 8bit ints in range [0...1] with saturation
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QPU_M_V8SUBS,
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} qpu_op_mul;
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static const char *qpu_op_mul_str[] = {
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[QPU_M_NOP] = "nop",
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[QPU_M_FMUL] = "fmul",
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[QPU_M_MUL24] = "mul24",
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[QPU_M_V8MULD] = "v8muld",
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[QPU_M_V8MIN] = "v8min",
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[QPU_M_V8MAX] = "v8max",
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[QPU_M_V8ADDS] = "v8adds",
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[QPU_M_V8SUBS] = "v8subs",
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};
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//read and write ops may mean different things...
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//hence two maps
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//QPU register address read map
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typedef enum {
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QPU_R_FRAG_PAYLOAD_ZW = 15, /* W for A file, Z for B file */
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/* 0-31 are the plain regfile a or b fields */
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QPU_R_UNIF = 32, //uniform read
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QPU_R_VARY = 35, //varying read
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QPU_R_ELEM_QPU = 38, //element number
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QPU_R_NOP,
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QPU_R_XY_PIXEL_COORD = 41, // X for regfile a, Y for regfile b
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QPU_R_MS_FLAGS = 42, //A reg
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QPU_R_REV_FLAG = 42, //B reg
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QPU_R_VPM = 48,
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QPU_R_VPM_LD_BUSY = 49, //load busy for reg A
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QPU_R_VPM_ST_BUSY = 49, //store busy for reg B
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QPU_R_VPM_LD_WAIT = 50, //load wait for reg A
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QPU_R_VPM_ST_WAIT = 50, //store wait for reg B
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QPU_R_MUTEX_ACQUIRE,
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} qpu_raddr;
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static const char *qpu_raddr_str[][52] = {
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{ //A
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[QPU_R_FRAG_PAYLOAD_ZW] = "pay_zw",
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[QPU_R_UNIF] = "uni",
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[QPU_R_VARY] = "vary",
|
||
[QPU_R_ELEM_QPU] = "elem",
|
||
[QPU_R_NOP] = "nop",
|
||
[QPU_R_XY_PIXEL_COORD] = "x_pix",
|
||
[QPU_R_MS_FLAGS] = "ms_flags",
|
||
[QPU_R_VPM] = "vpm_read",
|
||
[QPU_R_VPM_LD_BUSY] = "vpm_ld_busy",
|
||
[QPU_R_VPM_LD_WAIT] = "vpm_ld_wait",
|
||
[QPU_R_MUTEX_ACQUIRE] = "mutex_acq"
|
||
},
|
||
{ //B
|
||
[QPU_R_FRAG_PAYLOAD_ZW] = "pay_zw",
|
||
[QPU_R_UNIF] = "uni",
|
||
[QPU_R_VARY] = "vary",
|
||
[QPU_R_ELEM_QPU] = "elem",
|
||
[QPU_R_NOP] = "nop",
|
||
[QPU_R_XY_PIXEL_COORD] = "y_pix",
|
||
[QPU_R_REV_FLAG] = "rev_flag",
|
||
[QPU_R_VPM] = "vpm_read",
|
||
[QPU_R_VPM_ST_BUSY] = "vpm_st_busy",
|
||
[QPU_R_VPM_ST_WAIT] = "vpm_st_wait",
|
||
[QPU_R_MUTEX_ACQUIRE] = "mutex_acq"
|
||
}
|
||
};
|
||
|
||
//QPU register address write map
|
||
typedef enum {
|
||
/* 0-31 are the plain regfile a or b fields */
|
||
QPU_W_ACC0 = 32, //accumulation 0, aka r0
|
||
QPU_W_ACC1,
|
||
QPU_W_ACC2,
|
||
QPU_W_ACC3,
|
||
QPU_W_TMU_NOSWAP,
|
||
QPU_W_ACC5, //replicate pixel0 per quad for reg A, replicate SIMD element0 for reg B
|
||
QPU_W_HOST_INT, //host interrupt
|
||
QPU_W_NOP,
|
||
QPU_W_UNIFORMS_ADDRESS,
|
||
QPU_W_QUAD_XY, // X for regfile a, Y for regfile b
|
||
QPU_W_MS_FLAGS = 42, //A reg
|
||
QPU_W_REV_FLAG = 42, //B reg
|
||
QPU_W_TLB_STENCIL_SETUP = 43,
|
||
QPU_W_TLB_Z,
|
||
QPU_W_TLB_COLOR_MS,
|
||
QPU_W_TLB_COLOR_ALL,
|
||
QPU_W_TLB_ALPHA_MASK,
|
||
QPU_W_VPM,
|
||
QPU_W_VPMVCD_SETUP, /* LD for regfile a, ST for regfile b */
|
||
QPU_W_VPM_ADDR, /* LD for regfile a, ST for regfile b */
|
||
QPU_W_MUTEX_RELEASE,
|
||
QPU_W_SFU_RECIP, //special function unit 1/x
|
||
QPU_W_SFU_RECIPSQRT, //1/sqrt(x)
|
||
QPU_W_SFU_EXP,
|
||
QPU_W_SFU_LOG,
|
||
QPU_W_TMU0_S,
|
||
QPU_W_TMU0_T,
|
||
QPU_W_TMU0_R,
|
||
QPU_W_TMU0_B,
|
||
QPU_W_TMU1_S,
|
||
QPU_W_TMU1_T,
|
||
QPU_W_TMU1_R,
|
||
QPU_W_TMU1_B,
|
||
} qpu_waddr;
|
||
|
||
static const char *qpu_waddr_str[][64] = {
|
||
{ //A
|
||
[QPU_W_ACC0] = "r0",
|
||
[QPU_W_ACC1] = "r1",
|
||
[QPU_W_ACC2] = "r2",
|
||
[QPU_W_ACC3] = "r3",
|
||
[QPU_W_TMU_NOSWAP] = "tmu_noswap",
|
||
[QPU_W_ACC5] = "r5",
|
||
[QPU_W_HOST_INT] = "host_int",
|
||
[QPU_W_NOP] = "nop",
|
||
[QPU_W_UNIFORMS_ADDRESS] = "uniforms_addr",
|
||
[QPU_W_QUAD_XY] = "quad_x",
|
||
[QPU_W_MS_FLAGS] = "ms_flags",
|
||
[QPU_W_TLB_STENCIL_SETUP] = "tlb_stencil_setup",
|
||
[QPU_W_TLB_Z] = "tlb_z",
|
||
[QPU_W_TLB_COLOR_MS] = "tlb_color_ms",
|
||
[QPU_W_TLB_COLOR_ALL] = "tlb_color_all",
|
||
[QPU_W_VPM] = "vpm",
|
||
[QPU_W_VPMVCD_SETUP] = "vr_setup",
|
||
[QPU_W_VPM_ADDR] = "vr_addr",
|
||
[QPU_W_MUTEX_RELEASE] = "mutex_release",
|
||
[QPU_W_SFU_RECIP] = "sfu_recip",
|
||
[QPU_W_SFU_RECIPSQRT] = "sfu_recipsqrt",
|
||
[QPU_W_SFU_EXP] = "sfu_exp",
|
||
[QPU_W_SFU_LOG] = "sfu_log",
|
||
[QPU_W_TMU0_S] = "tmu0_s",
|
||
[QPU_W_TMU0_T] = "tmu0_t",
|
||
[QPU_W_TMU0_R] = "tmu0_r",
|
||
[QPU_W_TMU0_B] = "tmu0_b",
|
||
[QPU_W_TMU1_S] = "tmu1_s",
|
||
[QPU_W_TMU1_T] = "tmu1_t",
|
||
[QPU_W_TMU1_R] = "tmu1_r",
|
||
[QPU_W_TMU1_B] = "tmu1_b",
|
||
},
|
||
{ //B
|
||
[QPU_W_ACC0] = "r0",
|
||
[QPU_W_ACC1] = "r1",
|
||
[QPU_W_ACC2] = "r2",
|
||
[QPU_W_ACC3] = "r3",
|
||
[QPU_W_TMU_NOSWAP] = "tmu_noswap",
|
||
[QPU_W_ACC5] = "r5",
|
||
[QPU_W_HOST_INT] = "host_int",
|
||
[QPU_W_NOP] = "nop",
|
||
[QPU_W_UNIFORMS_ADDRESS] = "uniforms_addr",
|
||
[QPU_W_QUAD_XY] = "quad_y",
|
||
[QPU_W_REV_FLAG] = "rev_flags",
|
||
[QPU_W_TLB_STENCIL_SETUP] = "tlb_stencil_setup",
|
||
[QPU_W_TLB_Z] = "tlb_z",
|
||
[QPU_W_TLB_COLOR_MS] = "tlb_color_ms",
|
||
[QPU_W_TLB_COLOR_ALL] = "tlb_color_all",
|
||
[QPU_W_VPM] = "vpm",
|
||
[QPU_W_VPMVCD_SETUP] = "vw_setup",
|
||
[QPU_W_VPM_ADDR] = "vw_addr",
|
||
[QPU_W_MUTEX_RELEASE] = "mutex_release",
|
||
[QPU_W_SFU_RECIP] = "sfu_recip",
|
||
[QPU_W_SFU_RECIPSQRT] = "sfu_recipsqrt",
|
||
[QPU_W_SFU_EXP] = "sfu_exp",
|
||
[QPU_W_SFU_LOG] = "sfu_log",
|
||
[QPU_W_TMU0_S] = "tmu0_s",
|
||
[QPU_W_TMU0_T] = "tmu0_t",
|
||
[QPU_W_TMU0_R] = "tmu0_r",
|
||
[QPU_W_TMU0_B] = "tmu0_b",
|
||
[QPU_W_TMU1_S] = "tmu1_s",
|
||
[QPU_W_TMU1_T] = "tmu1_t",
|
||
[QPU_W_TMU1_R] = "tmu1_r",
|
||
[QPU_W_TMU1_B] = "tmu1_b",
|
||
}
|
||
};
|
||
|
||
#define QPU_MASK(high, low) ((((uint64_t)1<<((high)-(low)+1))-1)<<(low))
|
||
/* Using the GNU statement expression extension */
|
||
#define QPU_SET_FIELD(value, field) \
|
||
({ \
|
||
uint64_t fieldval = (uint64_t)(value) << field ## _SHIFT; \
|
||
assert((fieldval & ~ field ## _MASK) == 0); \
|
||
fieldval & field ## _MASK; \
|
||
})
|
||
|
||
#define QPU_GET_FIELD(word, field) ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT))
|
||
|
||
#define QPU_UPDATE_FIELD(inst, value, field) \
|
||
(((inst) & ~(field ## _MASK)) | QPU_SET_FIELD(value, field))
|
||
|
||
#define QPU_SIG_SHIFT 60
|
||
#define QPU_SIG_MASK QPU_MASK(63, 60)
|
||
|
||
#define QPU_UNPACK_SHIFT 57
|
||
#define QPU_UNPACK_MASK QPU_MASK(59, 57)
|
||
|
||
#define QPU_LOAD_IMM_MODE_SHIFT 57
|
||
#define QPU_LOAD_IMM_MODE_MASK QPU_MASK(59, 57)
|
||
# define QPU_LOAD_IMM_MODE_U32 0
|
||
# define QPU_LOAD_IMM_MODE_I2 1
|
||
# define QPU_LOAD_IMM_MODE_U2 3
|
||
|
||
/**
|
||
* If set, the pack field means PACK_MUL or R4 packing, instead of normal
|
||
* regfile a packing.
|
||
*/
|
||
#define QPU_PM ((uint64_t)1 << 56)
|
||
|
||
#define QPU_PACK_SHIFT 52
|
||
#define QPU_PACK_MASK QPU_MASK(55, 52)
|
||
|
||
#define QPU_COND_ADD_SHIFT 49
|
||
#define QPU_COND_ADD_MASK QPU_MASK(51, 49)
|
||
#define QPU_COND_MUL_SHIFT 46
|
||
#define QPU_COND_MUL_MASK QPU_MASK(48, 46)
|
||
|
||
|
||
#define QPU_BRANCH_COND_SHIFT 52
|
||
#define QPU_BRANCH_COND_MASK QPU_MASK(55, 52)
|
||
|
||
#define QPU_BRANCH_REL ((uint64_t)1 << 51)
|
||
#define QPU_BRANCH_REG ((uint64_t)1 << 50)
|
||
|
||
#define QPU_BRANCH_RADDR_A_SHIFT 45
|
||
#define QPU_BRANCH_RADDR_A_MASK QPU_MASK(49, 45)
|
||
|
||
#define QPU_SF ((uint64_t)1 << 45)
|
||
|
||
#define QPU_WADDR_ADD_SHIFT 38
|
||
#define QPU_WADDR_ADD_MASK QPU_MASK(43, 38)
|
||
#define QPU_WADDR_MUL_SHIFT 32
|
||
#define QPU_WADDR_MUL_MASK QPU_MASK(37, 32)
|
||
|
||
#define QPU_OP_MUL_SHIFT 29
|
||
#define QPU_OP_MUL_MASK QPU_MASK(31, 29)
|
||
|
||
#define QPU_RADDR_A_SHIFT 18
|
||
#define QPU_RADDR_A_MASK QPU_MASK(23, 18)
|
||
#define QPU_RADDR_B_SHIFT 12
|
||
#define QPU_RADDR_B_MASK QPU_MASK(17, 12)
|
||
#define QPU_SMALL_IMM_SHIFT 12
|
||
#define QPU_SMALL_IMM_MASK QPU_MASK(17, 12)
|
||
/* Small immediate value for rotate-by-r5, and 49-63 are "rotate by n
|
||
* channels"
|
||
*/
|
||
#define QPU_SMALL_IMM_MUL_ROT 48
|
||
|
||
#define QPU_ADD_A_SHIFT 9
|
||
#define QPU_ADD_A_MASK QPU_MASK(11, 9)
|
||
#define QPU_ADD_B_SHIFT 6
|
||
#define QPU_ADD_B_MASK QPU_MASK(8, 6)
|
||
#define QPU_MUL_A_SHIFT 3
|
||
#define QPU_MUL_A_MASK QPU_MASK(5, 3)
|
||
#define QPU_MUL_B_SHIFT 0
|
||
#define QPU_MUL_B_MASK QPU_MASK(2, 0)
|
||
|
||
#define QPU_WS ((uint64_t)1 << 44)
|
||
|
||
#define QPU_OP_ADD_SHIFT 24
|
||
#define QPU_OP_ADD_MASK QPU_MASK(28, 24)
|
||
|
||
#define QPU_LOAD_IMM_SHIFT 0
|
||
#define QPU_LOAD_IMM_MASK QPU_MASK(31, 0)
|
||
|
||
#define QPU_BRANCH_TARGET_SHIFT 0
|
||
#define QPU_BRANCH_TARGET_MASK QPU_MASK(31, 0)
|
||
|
||
#endif /* VC4_QPU_DEFINES_H */
|