2012-03-29 10:59:24 +02:00
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/*
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Copyright (c) 2012 Arduino. All right reserved.
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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2012-04-28 15:16:13 +02:00
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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2012-03-29 10:59:24 +02:00
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See the GNU Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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2012-03-29 21:11:05 +02:00
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#include "chip.h"
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2012-03-29 10:59:24 +02:00
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#if SAM3XA_SERIES
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2012-04-29 00:54:05 +02:00
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void USBD_InitEndpoints( uint32_t* puc_EndPoints, uint32_t ul_EndPoints )
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2012-04-28 15:16:13 +02:00
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{
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2012-04-29 00:54:05 +02:00
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uint32_t ul_EP ;
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for (ul_EP = 1; ul_EP < sizeof(_initEndpoints); ul_EP++)
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2012-04-28 20:15:23 +02:00
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{
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// Reset Endpoint Fifos
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2012-04-29 00:54:05 +02:00
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UOTGHS->UOTGHS_DEVEPTISR[ul_EP].UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_TOGGLESQ | UDPHS_EPTCLRSTA_FRCESTALL;
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UOTGHS->UOTGHS_DEVEPT = 1<<ul_EP;
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2012-04-28 20:15:23 +02:00
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//UECONX = 1;
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2012-04-29 00:54:05 +02:00
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//UECFG0X = pgm_read_byte(_initEndpoints+ul_EP);
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UOTGHS->UDPHS_EPT[ul_EP].UDPHS_EPTCFG = _initEndpoints[ul_EP];
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2012-04-28 20:15:23 +02:00
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2012-04-29 00:54:05 +02:00
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while( (signed int)UDPHS_EPTCFG_EPT_MAPD != (signed int)((UOTGHS->UDPHS_EPT[ul_EP].UDPHS_EPTCFG) & (unsigned int)UDPHS_EPTCFG_EPT_MAPD) )
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2012-04-28 20:15:23 +02:00
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;
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2012-04-29 00:54:05 +02:00
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UOTGHS->UDPHS_EPT[ul_EP].UDPHS_EPTCTLENB = UDPHS_EPTCTLENB_EPT_ENABL;
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2012-04-28 20:15:23 +02:00
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// UECFG1X = EP_DOUBLE_64;
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}
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2012-04-28 15:16:13 +02:00
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}
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uint32_t USBD_Init(void)
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{
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uint32_t ul ;
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// Enables the USB Clock
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pmc_enable_periph_clk(ID_UOTGHS);
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pmc_enable_upll_clock();
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pmc_switch_udpck_to_upllck(0); // div=0+1
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pmc_enable_udpck();
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// Configure interrupts
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NVIC_SetPriority((IRQn_Type) ID_UOTGHS, 0UL);
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NVIC_EnableIRQ((IRQn_Type) ID_UOTGHS);
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// Always authorize asynchrone USB interrupts to exit from sleep mode
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// for SAM3 USB wake up device except BACKUP mode
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pmc_set_fast_startup_input(PMC_FSMR_USBAL);
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// Enable USB macro
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UOTGHS->UOTGHS_CTRL |= UOTGHS_CTRL_USBE;
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// Automatic mode speed for device
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UOTGHS->UOTGHS_DEVCTRL &= ~UOTGHS_DEVCTRL_SPDCONF_Msk; // Normal mode
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UOTGHS->UOTGHS_DEVCTRL &= ~( UOTGHS_DEVCTRL_LS | UOTGHS_DEVCTRL_TSTJ | UOTGHS_DEVCTRL_TSTK |
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UOTGHS_DEVCTRL_TSTPCKT | UOTGHS_DEVCTRL_OPMODE2 ); // Normal mode
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UOTGHS->UOTGHS_DEVCTRL = 0;
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UOTGHS->UOTGHS_HSTCTRL = 0;
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// Enable OTG pad
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UOTGHS->UOTGHS_CTRL |= UOTGHS_CTRL_OTGPADE;
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// Enable clock OTG pad
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UOTGHS->UOTGHS_CTRL &= ~UOTGHS_CTRL_FRZCLK;
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// Usb disable
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UOTGHS->UOTGHS_CTRL &= ~UOTGHS_CTRL_USBE;
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UOTGHS->UOTGHS_CTRL &= ~UOTGHS_CTRL_OTGPADE;
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UOTGHS->UOTGHS_CTRL |= UOTGHS_CTRL_FRZCLK;
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// Usb enable
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UOTGHS->UOTGHS_CTRL |= UOTGHS_CTRL_USBE;
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UOTGHS->UOTGHS_CTRL |= UOTGHS_CTRL_OTGPADE;
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UOTGHS->UOTGHS_CTRL &= ~UOTGHS_CTRL_FRZCLK;
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// Usb select_device
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UOTGHS->UOTGHS_CTRL &= ~UOTGHS_CTRL_UIDE;
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UOTGHS->UOTGHS_CTRL |= UOTGHS_CTRL_UIMOD_Device;
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// Device is in the Attached state
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// deviceState = USBD_STATE_SUSPENDED;
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// previousDeviceState = USBD_STATE_POWERED;
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// Enable USB macro and clear all other bits
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UOTGHS->UOTGHS_DEVCTRL |= UOTGHS_CTRL_USBE;
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UOTGHS->UOTGHS_DEVCTRL = UOTGHS_CTRL_USBE;
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// Configure the pull-up on D+ and disconnect it
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USBD_Detach();
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// Clear General IT
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UOTGHS->UOTGHS_SCR = (UOTGHS_SCR_IDTIC|UOTGHS_SCR_VBUSTIC|UOTGHS_SCR_SRPIC|UOTGHS_SCR_VBERRIC|UOTGHS_SCR_BCERRIC|UOTGHS_SCR_ROLEEXIC|UOTGHS_SCR_HNPERRIC|UOTGHS_SCR_STOIC|UOTGHS_SCR_VBUSRQC);
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// Clear OTG Device IT
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UOTGHS->UOTGHS_DEVICR = (UOTGHS_DEVICR_SUSPC|UOTGHS_DEVICR_MSOFC|UOTGHS_DEVICR_SOFC|UOTGHS_DEVICR_EORSTC|UOTGHS_DEVICR_WAKEUPC|UOTGHS_DEVICR_EORSMC|UOTGHS_DEVICR_UPRSMC);
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// Clear OTG Host IT
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UOTGHS->UOTGHS_HSTICR = (UOTGHS_HSTICR_DCONNIC|UOTGHS_HSTICR_DDISCIC|UOTGHS_HSTICR_RSTIC|UOTGHS_HSTICR_RSMEDIC|UOTGHS_HSTICR_RXRSMIC|UOTGHS_HSTICR_HSOFIC|UOTGHS_HSTICR_HWUPIC);
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// Reset all Endpoints Fifos
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UOTGHS->UOTGHS_DEVEPT |= (UOTGHS_DEVEPT_EPRST0|UOTGHS_DEVEPT_EPRST1|UOTGHS_DEVEPT_EPRST2|UOTGHS_DEVEPT_EPRST3|UOTGHS_DEVEPT_EPRST4|
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UOTGHS_DEVEPT_EPRST5|UOTGHS_DEVEPT_EPRST6|UOTGHS_DEVEPT_EPRST7|UOTGHS_DEVEPT_EPRST8);
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UOTGHS->UOTGHS_DEVEPT &= ~(UOTGHS_DEVEPT_EPRST0|UOTGHS_DEVEPT_EPRST1|UOTGHS_DEVEPT_EPRST2|UOTGHS_DEVEPT_EPRST3|UOTGHS_DEVEPT_EPRST4|
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UOTGHS_DEVEPT_EPRST5|UOTGHS_DEVEPT_EPRST6|UOTGHS_DEVEPT_EPRST7|UOTGHS_DEVEPT_EPRST8);
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// Disable all endpoints
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UOTGHS->UOTGHS_DEVEPT &= ~(UOTGHS_DEVEPT_EPEN0|UOTGHS_DEVEPT_EPEN1|UOTGHS_DEVEPT_EPEN2|UOTGHS_DEVEPT_EPEN3|UOTGHS_DEVEPT_EPEN4|
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UOTGHS_DEVEPT_EPEN5|UOTGHS_DEVEPT_EPEN6|UOTGHS_DEVEPT_EPEN7|UOTGHS_DEVEPT_EPEN8);
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// Device is in the Attached state
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// deviceState = USBD_STATE_SUSPENDED;
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// previousDeviceState = USBD_STATE_POWERED;
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// Automatic mode speed for device
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UOTGHS->UOTGHS_DEVCTRL &= ~UOTGHS_DEVCTRL_SPDCONF_Msk;
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// Force Full Speed mode for device
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//UOTGHS->UOTGHS_DEVCTRL = UOTGHS_DEVCTRL_SPDCONF_FORCED_FS;
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// Force High Speed mode for device
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//UOTGHS->UOTGHS_DEVCTRL = UOTGHS_DEVCTRL_SPDCONF_HIGH_SPEED;
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UOTGHS->UOTGHS_DEVCTRL &= ~(UOTGHS_DEVCTRL_LS|UOTGHS_DEVCTRL_TSTJ| UOTGHS_DEVCTRL_TSTK|UOTGHS_DEVCTRL_TSTPCKT|UOTGHS_DEVCTRL_OPMODE2) ;
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// Enable USB macro
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UOTGHS->UOTGHS_DEVCTRL |= UOTGHS_CTRL_USBE;
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// Enable the UID pin select
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UOTGHS->UOTGHS_DEVCTRL |= UOTGHS_CTRL_UIDE;
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// Enable OTG pad
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UOTGHS->UOTGHS_DEVCTRL |= UOTGHS_CTRL_OTGPADE;
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// Enable clock OTG pad
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UOTGHS->UOTGHS_DEVCTRL &= ~UOTGHS_CTRL_FRZCLK;
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// With OR without DMA !!!
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// Initialization of DMA
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for( ul=1; ul<= UOTGHSDEVDMA_NUMBER ; ul++ )
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{
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// RESET endpoint canal DMA:
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// DMA stop channel command
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UOTGHS->UOTGHS_DEVDMA[ul].UOTGHS_DEVDMACONTROL = 0; // STOP command
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// Disable endpoint
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UOTGHS->UOTGHS_DEVEPTIDR[ul] = (UOTGHS_DEVEPTIDR_TXINEC|UOTGHS_DEVEPTIDR_RXOUTEC|UOTGHS_DEVEPTIDR_RXSTPEC|UOTGHS_DEVEPTIDR_UNDERFEC|UOTGHS_DEVEPTIDR_NAKOUTEC|
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UOTGHS_DEVEPTIDR_HBISOINERREC|UOTGHS_DEVEPTIDR_NAKINEC|UOTGHS_DEVEPTIDR_HBISOFLUSHEC|UOTGHS_DEVEPTIDR_OVERFEC|UOTGHS_DEVEPTIDR_STALLEDEC|
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UOTGHS_DEVEPTIDR_CRCERREC|UOTGHS_DEVEPTIDR_SHORTPACKETEC|UOTGHS_DEVEPTIDR_MDATEC|UOTGHS_DEVEPTIDR_DATAXEC|UOTGHS_DEVEPTIDR_ERRORTRANSEC|
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UOTGHS_DEVEPTIDR_NBUSYBKEC|UOTGHS_DEVEPTIDR_FIFOCONC|UOTGHS_DEVEPTIDR_EPDISHDMAC|UOTGHS_DEVEPTIDR_NYETDISC|UOTGHS_DEVEPTIDR_STALLRQC);
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// Reset endpoint config
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UOTGHS->UOTGHS_DEVEPTCFG[ul] = 0UL;
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// Reset DMA channel (Buff count and Control field)
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UOTGHS->UOTGHS_DEVDMA[ul].UOTGHS_DEVDMACONTROL = 0x02UL; // NON STOP command
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// Reset DMA channel 0 (STOP)
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UOTGHS->UOTGHS_DEVDMA[ul].UOTGHS_DEVDMACONTROL = 0UL; // STOP command
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// Clear DMA channel status (read the register to clear it)
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UOTGHS->UOTGHS_DEVDMA[ul].UOTGHS_DEVDMASTATUS = UOTGHS->UOTGHS_DEVDMA[ul].UOTGHS_DEVDMASTATUS;
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}
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UOTGHS->UOTGHS_DEVCTRL |= UOTGHS_CTRL_VBUSTE;
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UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_WAKEUPES;
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return 0UL ;
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}
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void USBD_Attach(void)
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{
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UOTGHS->UOTGHS_DEVCTRL &= ~(unsigned int)UOTGHS_DEVCTRL_DETACH;
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}
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void USBD_Detach(void)
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{
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UOTGHS->UOTGHS_DEVCTRL |= UOTGHS_DEVCTRL_DETACH;
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}
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2012-03-29 10:59:24 +02:00
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#endif /* SAM3XA_SERIES */
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