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Ensure minimum spi pulse width.

This commit is contained in:
Peter Van Hoyweghen 2015-07-14 21:20:39 +02:00
parent 5a04ab2a32
commit 50f9e539d8

View File

@ -114,6 +114,10 @@ class BitBangedSPI {
}
void begin() {
// slow enough for an attiny85 @ 1MHz
// (pulseWidth should be > 2 cpu cycles, so take 3 cycles:)
pulseWidth = 3;
pinMode(MISO, INPUT);
pinMode(RESET, OUTPUT);
pinMode(SCK, OUTPUT);
@ -126,11 +130,16 @@ class BitBangedSPI {
for (unsigned int i = 0; i < 8; ++i) {
digitalWrite(MOSI, b & 0x80);
digitalWrite(SCK, HIGH);
delayMicroseconds(pulseWidth);
b = (b << 1) | digitalRead(MISO);
digitalWrite(SCK, LOW); // slow pulse
delayMicroseconds(pulseWidth);
}
return b;
}
private:
unsigned long pulseWidth; // in microseconds
};
static BitBangedSPI SPI;