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[SAM] HID is working. Printf issue in UDD_Send8 function.
This commit is contained in:
Thibault RICHARD
parent
45a1d32e71
commit
b2c35a4e68
@ -127,7 +127,7 @@ extern const HIDDescriptor _hidInterface =
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{
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D_INTERFACE(HID_INTERFACE,1,3,0,0),
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D_HIDREPORT(sizeof(_hidReportDescriptor)),
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D_ENDPOINT(USB_ENDPOINT_IN (HID_ENDPOINT_INT),USB_ENDPOINT_TYPE_INTERRUPT,0x40,0x01)
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D_ENDPOINT(USB_ENDPOINT_IN(HID_ENDPOINT_INT),USB_ENDPOINT_TYPE_INTERRUPT,0x40,0x01)
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};
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_Pragma("pack()")
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@ -161,8 +161,12 @@ bool WEAK HID_Setup(Setup& setup)
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{
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uint8_t r = setup.bRequest;
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uint8_t requestType = setup.bmRequestType;
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printf("=> HID_Setup\r\n");
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if (REQUEST_DEVICETOHOST_CLASS_INTERFACE == requestType)
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{
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printf("=> REQUEST_DEVICETOHOST_CLASS_INTERFACE\r\n");
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if (HID_GET_REPORT == r)
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{
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//HID_GetReport();
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@ -177,6 +181,7 @@ bool WEAK HID_Setup(Setup& setup)
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if (REQUEST_HOSTTODEVICE_CLASS_INTERFACE == requestType)
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{
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printf("=> REQUEST_HOSTTODEVICE_CLASS_INTERFACE\r\n");
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if (HID_SET_PROTOCOL == r)
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{
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_hid_protocol = setup.wValueL;
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@ -502,12 +507,9 @@ void Keyboard_::releaseAll(void)
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size_t Keyboard_::write(uint8_t c)
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{
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/* TODO
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uint8_t p = press(c); // Keydown
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uint8_t r = release(c); // Keyup
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return (p); // just return the result of press() since release() almost always returns 1
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*/
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return 1 ;
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}
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#endif
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@ -18,7 +18,7 @@
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#include "USBAPI.h"
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#include <stdio.h>
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const uint32_t _initEndpoints[] =
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static const uint32_t EndPoints[] =
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{
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EP_TYPE_CONTROL,
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@ -59,7 +59,7 @@ const uint16_t STRING_IPRODUCT[17] = {
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#elif USB_PID == USB_PID_MICRO
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'A','r','d','u','i','n','o',' ','M','i','c','r','o',' ',' ',' '
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#elif USB_PID == USB_PID_DUE
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'A','r','d','u','i','n','o',' ','D','u','e',' ',' ',' ',' ',' '
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'A','r','d','u','i','n','o',' ','D','u','e',' ',' ',' ',' ','X'
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#else
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#error "Need an USB PID"
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#endif
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@ -101,7 +101,7 @@ class LockEP
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public:
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LockEP(uint32_t ep) : flags(cpu_irq_save())
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{
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UDD_SetEP(ep & 7);
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UDD_SetEP(ep & 0xF);
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}
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~LockEP()
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{
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@ -190,6 +190,7 @@ uint32_t USBD_Send(uint32_t ep, const void* d, uint32_t len)
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while (n--)
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UDD_Send8(*data++);
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}
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if (!UDD_ReadWriteAllowed() || ((len == 0) && (ep & TRANSFER_RELEASE))) // Release full buffer
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UDD_ReleaseTX();
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}
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@ -264,18 +265,20 @@ bool USBD_ClassInterfaceRequest(Setup& setup)
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{
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uint8_t i = setup.wIndex;
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printf("=> USBD_ClassInterfaceRequest\r\n");
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#ifdef CDC_ENABLED
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if ( CDC_ACM_INTERFACE == i )
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{
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{
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return CDC_Setup(setup);
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}
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}
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#endif
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#ifdef HID_ENABLED
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if ( HID_INTERFACE == i )
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{
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{
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return HID_Setup(setup);
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}
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}
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#endif
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return false ;
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@ -383,8 +386,6 @@ static bool USBD_SendDescriptor(Setup& setup)
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return true;
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}
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volatile int cpt = 0;
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// Endpoint 0 interrupt
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static void USB_ISR(void)
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{
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@ -397,24 +398,23 @@ static void USB_ISR(void)
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udd_enable_address();
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// Configure EP 0
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UDD_SetEP(0);
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UDD_InitEP(0, EP_TYPE_CONTROL);
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udd_allocate_memory(0);
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udd_enable_setup_received_interrupt(0);
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udd_enable_endpoint_interrupt(0);
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_usbConfiguration = 0;
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_cmark = 0;
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_cend = 0;
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udd_ack_reset(); /* /!\/!\/!\ TAKEN FROM ASF TO CLEAR ISR /!\/!\/!\ */
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}
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// Start of Frame - happens every millisecond so we use it for TX and RX LED one-shot timing, too
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if (Is_udd_sof())
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{
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printf(">>> Start of Frame\r\n");
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//printf(">>> Start of Frame\r\n");
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#ifdef CDC_ENABLED
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USBD_Flush(CDC_TX); // Send a tx frame if found
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USBD_Flush(CDC_TX); // Send a tx frame if found
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while (USBD_Available(CDC_RX)) // Handle received bytes (if any)
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Serial.accept();
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#endif
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// check whether the one-shot period has elapsed. if so, turn off the LED
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@ -429,7 +429,9 @@ static void USB_ISR(void)
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// EP 0 Interrupt
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if (Is_udd_endpoint_interrupt(0))
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{
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printf(">>> EP0 Int: 0x%x\r\n", UOTGHS->UOTGHS_DEVEPTISR[0]);
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UDD_SetEP(0);
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//printf(">>> EP0 Int: 0x%x\r\n", UOTGHS->UOTGHS_DEVEPTISR[0]);
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if ( !UDD_ReceivedSetupInt() )
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{
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@ -440,7 +442,7 @@ static void USB_ISR(void)
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UDD_Recv((uint8_t*)&setup,8);
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UDD_ClearSetupInt();
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printf(">>> EP0 Int: AP clear: 0x%x\r\n", UOTGHS->UOTGHS_DEVEPTISR[0]);
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//printf(">>> EP0 Int: AP clear: 0x%x\r\n", UOTGHS->UOTGHS_DEVEPTISR[0]);
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uint8_t requestType = setup.bmRequestType;
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if (requestType & REQUEST_DEVICETOHOST)
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@ -496,22 +498,26 @@ static void USB_ISR(void)
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}
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else if (SET_CONFIGURATION == r)
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{
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puts(">>> EP0 Int: SET_CONFIGURATION\r\n");
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if (REQUEST_DEVICE == (requestType & REQUEST_RECIPIENT))
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{
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UDD_InitEndpoints(_initEndpoints);
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printf(">>> EP0 Int: SET_CONFIGURATION REQUEST_DEVICE %d\r\n", setup.wValueL);
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UDD_InitEndpoints(EndPoints, (sizeof(EndPoints) / sizeof(EndPoints[0])));
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_usbConfiguration = setup.wValueL;
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}
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else
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{
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puts(">>> EP0 Int: SET_CONFIGURATION failed!\r\n");
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ok = false;
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}
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}
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else if (GET_INTERFACE == r)
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{
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puts(">>> EP0 Int: GET_INTERFACE\r\n");
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}
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else if (SET_INTERFACE == r)
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{
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puts(">>> EP0 Int: SET_INTERFACE\r\n");
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}
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}
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else
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@ -524,6 +530,7 @@ static void USB_ISR(void)
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if (ok)
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{
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puts(">>> EP0 Int: Send packet\r\n");
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UDD_ClearOUT(); // rajouté par moi, pe pas nécessaire car la fifo est suffisament grande
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UDD_ClearIN();
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}
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else
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@ -541,41 +548,6 @@ void USBD_Flush(uint32_t ep)
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UDD_ReleaseTX();
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}
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// General interrupt
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// USB device interrupt handler
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/*
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// Manages device resume, suspend, end of bus reset.
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// Forwards endpoint interrupts to the appropriate handler.
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// General interrupt
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ISR(USB_GEN_vect)
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{
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uint8_t udint = UDINT;
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UDINT = 0;
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// End of Reset
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if (udint & (1<<EORSTI))
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{
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InitEP(0,EP_TYPE_CONTROL,EP_SINGLE_64); // init ep0
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_usbConfiguration = 0; // not configured yet
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UEIENX = 1 << RXSTPE; // Enable interrupts for ep0
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}
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// Start of Frame - happens every millisecond so we use it for TX and RX LED one-shot timing, too
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if (udint & (1<<SOFI))
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{
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#ifdef CDC_ENABLED
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USB_Flush(CDC_TX); // Send a tx frame if found
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#endif
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// check whether the one-shot period has elapsed. if so, turn off the LED
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if (TxLEDPulse && !(--TxLEDPulse))
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TXLED0;
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if (RxLEDPulse && !(--RxLEDPulse))
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RXLED0;
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}
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}
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*/
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// VBUS or counting frames
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// Any frame counting?
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uint32_t USBD_Connected(void)
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@ -619,17 +591,15 @@ bool USB_::attach(void)
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bool USB_::detach(void)
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{
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return true;
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/* if ( _usbInitialized != 0UL )
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{
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UDD_Detach() ;
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return true ;
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}
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else
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{
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return false ;
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}*/
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if ( _usbInitialized != 0UL )
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{
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UDD_Detach() ;
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return true ;
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}
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else
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{
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return false ;
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}
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}
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// Check for interrupts
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@ -45,7 +45,7 @@
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#define REQUEST_INTERFACE 0x01
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#define REQUEST_ENDPOINT 0x02
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#define REQUEST_OTHER 0x03
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#define REQUEST_RECIPIENT 0x03
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#define REQUEST_RECIPIENT 0x1F
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#define REQUEST_DEVICETOHOST_CLASS_INTERFACE (REQUEST_DEVICETOHOST + REQUEST_CLASS + REQUEST_INTERFACE)
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#define REQUEST_HOSTTODEVICE_CLASS_INTERFACE (REQUEST_HOSTTODEVICE + REQUEST_CLASS + REQUEST_INTERFACE)
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@ -284,7 +284,7 @@ _Pragma("pack()")
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{ 18, 1, 0x200, _class,_subClass,_proto,_packetSize0,_vid,_pid,_version,_im,_ip,_is,_configs }
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#define D_CONFIG(_totalLength,_interfaces) \
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{ 9, 2, _totalLength,_interfaces, 1, 0, USB_CONFIG_BUS_POWERED, USB_CONFIG_POWER_MA(500) }
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{ 9, 2, _totalLength,_interfaces, 1, 0, USB_CONFIG_SELF_POWERED, USB_CONFIG_POWER_MA(500) }
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#define D_INTERFACE(_n,_numEndpoints,_class,_subClass,_protocol) \
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{ 9, 4, _n, 0, _numEndpoints, _class,_subClass, _protocol, 0 }
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@ -72,9 +72,9 @@ void loop() {
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Mouse.release(MOUSE_LEFT);
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}
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}*/
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Mouse.move(10, 10, 0);
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Mouse.move(10, 0, 0);
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// a delay so the mouse doesn't move too fast:
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delay(responseDelay);
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delay(1000);
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}
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@ -52,7 +52,7 @@ extern void UDD_Recv(volatile uint8_t* data, uint32_t count);
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extern void UDD_InitEndpoints(const uint32_t* eps);
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extern void UDD_InitEndpoints(const uint32_t* eps_table, const uint32_t ul_eps_table_size);
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extern void UDD_InitControl(int end) ;
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@ -22,27 +22,62 @@
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#define EP_SINGLE_64 (0x32UL) // EP0
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#define EP_DOUBLE_64 (0x36UL) // Other endpoints
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// Control Endpoint
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#define EP_TYPE_CONTROL (UOTGHS_DEVEPTCFG_EPSIZE_64_BYTE | UOTGHS_DEVEPTCFG_EPTYPE_CTRL | UOTGHS_DEVEPTCFG_EPBK_1_BANK | UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS)
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#define EP_TYPE_CONTROL (UOTGHS_DEVEPTCFG_EPSIZE_64_BYTE | \
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UOTGHS_DEVEPTCFG_EPTYPE_CTRL | \
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UOTGHS_DEVEPTCFG_EPBK_1_BANK | \
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UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS | \
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UOTGHS_DEVEPTCFG_ALLOC)
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// CDC Endpoints
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//#ifdef CDC_ENABLED
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#define EP_TYPE_BULK_IN (UOTGHS_DEVEPTCFG_EPSIZE_512_BYTE | UOTGHS_DEVEPTCFG_EPDIR_IN | UOTGHS_DEVEPTCFG_EPTYPE_BLK | UOTGHS_DEVEPTCFG_EPBK_2_BANK | UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS)
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#define EP_TYPE_BULK_OUT (UOTGHS_DEVEPTCFG_EPSIZE_512_BYTE | UOTGHS_DEVEPTCFG_EPTYPE_BLK | UOTGHS_DEVEPTCFG_EPBK_2_BANK | UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS)
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#define EP_TYPE_INTERRUPT_IN (UOTGHS_DEVEPTCFG_EPSIZE_64_BYTE | UOTGHS_DEVEPTCFG_EPDIR_IN | UOTGHS_DEVEPTCFG_EPTYPE_INTRPT | UOTGHS_DEVEPTCFG_EPBK_2_BANK | UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS)
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//#endif
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#define EP_TYPE_BULK_IN (UOTGHS_DEVEPTCFG_EPSIZE_512_BYTE | \
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UOTGHS_DEVEPTCFG_EPDIR_IN | \
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UOTGHS_DEVEPTCFG_EPTYPE_BLK | \
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UOTGHS_DEVEPTCFG_EPBK_2_BANK | \
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UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS | \
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UOTGHS_DEVEPTCFG_ALLOC)
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#define EP_TYPE_BULK_OUT (UOTGHS_DEVEPTCFG_EPSIZE_512_BYTE | \
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UOTGHS_DEVEPTCFG_EPTYPE_BLK | \
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UOTGHS_DEVEPTCFG_EPBK_2_BANK | \
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UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS | \
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UOTGHS_DEVEPTCFG_ALLOC)
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#define EP_TYPE_INTERRUPT_IN (UOTGHS_DEVEPTCFG_EPSIZE_64_BYTE | \
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UOTGHS_DEVEPTCFG_EPDIR_IN | \
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UOTGHS_DEVEPTCFG_EPTYPE_INTRPT | \
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UOTGHS_DEVEPTCFG_EPBK_2_BANK | \
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UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS | \
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UOTGHS_DEVEPTCFG_ALLOC)
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// HID Endpoints
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//#ifdef HID_ENABLED
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#define EP_TYPE_INTERRUPT_IN_HID (UOTGHS_DEVEPTCFG_EPSIZE_64_BYTE | UOTGHS_DEVEPTCFG_EPDIR_IN | UOTGHS_DEVEPTCFG_EPTYPE_INTRPT | UOTGHS_DEVEPTCFG_EPBK_2_BANK | UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS)
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//#endif
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#define EP_TYPE_INTERRUPT_IN_HID (UOTGHS_DEVEPTCFG_EPSIZE_64_BYTE | \
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UOTGHS_DEVEPTCFG_EPDIR_IN | \
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UOTGHS_DEVEPTCFG_EPTYPE_INTRPT | \
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UOTGHS_DEVEPTCFG_EPBK_2_BANK | \
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UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS | \
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UOTGHS_DEVEPTCFG_ALLOC)
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// Various definitions
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#define EP_TYPE_INTERRUPT_OUT (UOTGHS_DEVEPTCFG_EPSIZE_64_BYTE | UOTGHS_DEVEPTCFG_EPTYPE_INTRPT | UOTGHS_DEVEPTCFG_EPTYPE_INTRPT | UOTGHS_DEVEPTCFG_EPBK_1_BANK | UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS)
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#define EP_TYPE_ISOCHRONOUS_IN (UOTGHS_DEVEPTCFG_EPSIZE_1024_BYTE | UOTGHS_DEVEPTCFG_EPDIR_IN | UOTGHS_DEVEPTCFG_EPTYPE_ISO | UOTGHS_DEVEPTCFG_EPBK_3_BANK | UOTGHS_DEVEPTCFG_NBTRANS_3_TRANS)
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#define EP_TYPE_ISOCHRONOUS_OUT (UOTGHS_DEVEPTCFG_EPSIZE_1024_BYTE | UOTGHS_DEVEPTCFG_EPTYPE_ISO | UOTGHS_DEVEPTCFG_EPBK_3_BANK | UOTGHS_DEVEPTCFG_NBTRANS_3_TRANS)
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#define EP_TYPE_INTERRUPT_OUT (UOTGHS_DEVEPTCFG_EPSIZE_64_BYTE | \
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UOTGHS_DEVEPTCFG_EPTYPE_INTRPT | \
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UOTGHS_DEVEPTCFG_EPTYPE_INTRPT | \
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UOTGHS_DEVEPTCFG_EPBK_1_BANK | \
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UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS | \
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UOTGHS_DEVEPTCFG_ALLOC)
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#define EP_TYPE_ISOCHRONOUS_IN (UOTGHS_DEVEPTCFG_EPSIZE_1024_BYTE | \
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UOTGHS_DEVEPTCFG_EPDIR_IN | \
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UOTGHS_DEVEPTCFG_EPTYPE_ISO | \
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UOTGHS_DEVEPTCFG_EPBK_3_BANK | \
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UOTGHS_DEVEPTCFG_NBTRANS_3_TRANS | \
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UOTGHS_DEVEPTCFG_ALLOC)
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#define EP_TYPE_ISOCHRONOUS_OUT (UOTGHS_DEVEPTCFG_EPSIZE_1024_BYTE | \
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UOTGHS_DEVEPTCFG_EPTYPE_ISO | \
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UOTGHS_DEVEPTCFG_EPBK_3_BANK | \
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UOTGHS_DEVEPTCFG_NBTRANS_3_TRANS | \
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UOTGHS_DEVEPTCFG_ALLOC)
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//! \ingroup usb_device_group
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//! \defgroup udd_group USB Device Driver (UDD)
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@ -21,9 +21,11 @@
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#if SAM3XA_SERIES
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static void (*gpf_isr)(void)=(0UL);
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static void (*gpf_isr)(void) = (0UL);
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uint32_t ul_ep = 0;
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static volatile uint32_t ul_ep = (0UL);
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static volatile uint32_t ul_send_index = (0UL);
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static volatile uint32_t ul_recv_index = (0UL);
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void UDD_SetStack(void (*pf_isr)(void))
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{
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@ -54,9 +56,6 @@ uint32_t UDD_Init(void)
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||||
// for SAM3 USB wake up device except BACKUP mode
|
||||
//pmc_set_fast_startup_input(PMC_FSMR_USBAL);
|
||||
|
||||
|
||||
|
||||
|
||||
// ID pin not used then force device mode
|
||||
otg_disable_id_pin();
|
||||
otg_force_device_mode();
|
||||
@ -66,6 +65,7 @@ uint32_t UDD_Init(void)
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||||
otg_enable_pad();
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||||
otg_enable();
|
||||
otg_unfreeze_clock();
|
||||
|
||||
// Check USB clock
|
||||
while (!Is_otg_clock_usable())
|
||||
;
|
||||
@ -73,7 +73,6 @@ uint32_t UDD_Init(void)
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||||
udd_low_speed_disable();
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||||
udd_high_speed_disable();
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||||
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||||
|
||||
//otg_ack_vbus_transition();
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||||
// Force Vbus interrupt in case of Vbus always with a high level
|
||||
// This is possible with a short timing between a Host mode stop/start.
|
||||
@ -83,127 +82,6 @@ uint32_t UDD_Init(void)
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||||
otg_enable_vbus_interrupt();*/
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otg_freeze_clock();
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||||
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||||
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||||
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||||
// Enable USB
|
||||
/*UOTGHS->UOTGHS_CTRL |= UOTGHS_CTRL_USBE;
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||||
|
||||
// Automatic mode speed for device
|
||||
UOTGHS->UOTGHS_DEVCTRL &= ~UOTGHS_DEVCTRL_SPDCONF_Msk; // Normal mode
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||||
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||||
UOTGHS->UOTGHS_DEVCTRL &= ~( UOTGHS_DEVCTRL_LS | UOTGHS_DEVCTRL_TSTJ | UOTGHS_DEVCTRL_TSTK |
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||||
UOTGHS_DEVCTRL_TSTPCKT | UOTGHS_DEVCTRL_OPMODE2 ); // Normal mode
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||||
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||||
UOTGHS->UOTGHS_DEVCTRL = 0;
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||||
UOTGHS->UOTGHS_HSTCTRL = 0;
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||||
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||||
// Enable OTG pad
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||||
UOTGHS->UOTGHS_CTRL |= UOTGHS_CTRL_OTGPADE;
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||||
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||||
// Enable clock OTG pad
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||||
UOTGHS->UOTGHS_CTRL &= ~UOTGHS_CTRL_FRZCLK;
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||||
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||||
// Usb disable
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UOTGHS->UOTGHS_CTRL &= ~UOTGHS_CTRL_USBE;
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UOTGHS->UOTGHS_CTRL &= ~UOTGHS_CTRL_OTGPADE;
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UOTGHS->UOTGHS_CTRL |= UOTGHS_CTRL_FRZCLK;
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||||
// Usb enable
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||||
UOTGHS->UOTGHS_CTRL |= UOTGHS_CTRL_USBE;
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UOTGHS->UOTGHS_CTRL |= UOTGHS_CTRL_OTGPADE;
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||||
UOTGHS->UOTGHS_CTRL &= ~UOTGHS_CTRL_FRZCLK;
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// Usb select device mode
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||||
UOTGHS->UOTGHS_CTRL &= ~UOTGHS_CTRL_UIDE;
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UOTGHS->UOTGHS_CTRL |= UOTGHS_CTRL_UIMOD_Device;
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||||
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||||
// Device is in the Attached state
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// deviceState = USBD_STATE_SUSPENDED;
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||||
// previousDeviceState = USBD_STATE_POWERED;
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// Enable USB and clear all other bits
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||||
//UOTGHS->UOTGHS_DEVCTRL |= UOTGHS_CTRL_USBE;
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||||
//UOTGHS->UOTGHS_DEVCTRL = UOTGHS_CTRL_USBE;
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||||
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||||
// Configure the pull-up on D+ and disconnect it
|
||||
UDD_Detach();
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||||
// Clear General IT
|
||||
UOTGHS->UOTGHS_SCR = (UOTGHS_SCR_IDTIC|UOTGHS_SCR_VBUSTIC|UOTGHS_SCR_SRPIC|UOTGHS_SCR_VBERRIC|UOTGHS_SCR_BCERRIC|UOTGHS_SCR_ROLEEXIC|UOTGHS_SCR_HNPERRIC|UOTGHS_SCR_STOIC|UOTGHS_SCR_VBUSRQC);
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||||
|
||||
// Clear OTG Device IT
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||||
UOTGHS->UOTGHS_DEVICR = (UOTGHS_DEVICR_SUSPC|UOTGHS_DEVICR_MSOFC|UOTGHS_DEVICR_SOFC|UOTGHS_DEVICR_EORSTC|UOTGHS_DEVICR_WAKEUPC|UOTGHS_DEVICR_EORSMC|UOTGHS_DEVICR_UPRSMC);
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||||
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||||
// Clear OTG Host IT
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||||
UOTGHS->UOTGHS_HSTICR = (UOTGHS_HSTICR_DCONNIC|UOTGHS_HSTICR_DDISCIC|UOTGHS_HSTICR_RSTIC|UOTGHS_HSTICR_RSMEDIC|UOTGHS_HSTICR_RXRSMIC|UOTGHS_HSTICR_HSOFIC|UOTGHS_HSTICR_HWUPIC);
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||||
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// Reset all Endpoints Fifos
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||||
UOTGHS->UOTGHS_DEVEPT |= (UOTGHS_DEVEPT_EPRST0|UOTGHS_DEVEPT_EPRST1|UOTGHS_DEVEPT_EPRST2|UOTGHS_DEVEPT_EPRST3|UOTGHS_DEVEPT_EPRST4|
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||||
UOTGHS_DEVEPT_EPRST5|UOTGHS_DEVEPT_EPRST6|UOTGHS_DEVEPT_EPRST7|UOTGHS_DEVEPT_EPRST8);
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||||
UOTGHS->UOTGHS_DEVEPT &= ~(UOTGHS_DEVEPT_EPRST0|UOTGHS_DEVEPT_EPRST1|UOTGHS_DEVEPT_EPRST2|UOTGHS_DEVEPT_EPRST3|UOTGHS_DEVEPT_EPRST4|
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||||
UOTGHS_DEVEPT_EPRST5|UOTGHS_DEVEPT_EPRST6|UOTGHS_DEVEPT_EPRST7|UOTGHS_DEVEPT_EPRST8);
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||||
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||||
// Disable all endpoints
|
||||
UOTGHS->UOTGHS_DEVEPT &= ~(UOTGHS_DEVEPT_EPEN0|UOTGHS_DEVEPT_EPEN1|UOTGHS_DEVEPT_EPEN2|UOTGHS_DEVEPT_EPEN3|UOTGHS_DEVEPT_EPEN4|
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||||
UOTGHS_DEVEPT_EPEN5|UOTGHS_DEVEPT_EPEN6|UOTGHS_DEVEPT_EPEN7|UOTGHS_DEVEPT_EPEN8);
|
||||
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||||
// Device is in the Attached state
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||||
// deviceState = USBD_STATE_SUSPENDED;
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||||
// previousDeviceState = USBD_STATE_POWERED;
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||||
|
||||
// Automatic mode speed for device
|
||||
UOTGHS->UOTGHS_DEVCTRL &= ~UOTGHS_DEVCTRL_SPDCONF_Msk;
|
||||
// Force Full Speed mode for device
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||||
//UOTGHS->UOTGHS_DEVCTRL = UOTGHS_DEVCTRL_SPDCONF_FORCED_FS;
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||||
// Force High Speed mode for device
|
||||
//UOTGHS->UOTGHS_DEVCTRL = UOTGHS_DEVCTRL_SPDCONF_HIGH_SPEED;
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||||
|
||||
UOTGHS->UOTGHS_DEVCTRL &= ~(UOTGHS_DEVCTRL_LS|UOTGHS_DEVCTRL_TSTJ| UOTGHS_DEVCTRL_TSTK|UOTGHS_DEVCTRL_TSTPCKT|UOTGHS_DEVCTRL_OPMODE2) ;
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||||
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||||
// Enable USB macro
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||||
UOTGHS->UOTGHS_CTRL |= UOTGHS_CTRL_USBE;
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||||
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||||
// Enable the UID pin select
|
||||
UOTGHS->UOTGHS_CTRL |= UOTGHS_CTRL_UIDE;
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||||
|
||||
// Enable OTG pad
|
||||
UOTGHS->UOTGHS_CTRL |= UOTGHS_CTRL_OTGPADE;
|
||||
|
||||
// Enable clock OTG pad
|
||||
UOTGHS->UOTGHS_CTRL &= ~UOTGHS_CTRL_FRZCLK;
|
||||
|
||||
// With OR without DMA !!!
|
||||
// Initialization of DMA
|
||||
for( ul=1; ul<= UOTGHSDEVDMA_NUMBER ; ul++ )
|
||||
{
|
||||
// RESET endpoint canal DMA:
|
||||
// DMA stop channel command
|
||||
UOTGHS->UOTGHS_DEVDMA[ul].UOTGHS_DEVDMACONTROL = 0; // STOP command
|
||||
|
||||
// Disable endpoint
|
||||
UOTGHS->UOTGHS_DEVEPTIDR[ul] = (UOTGHS_DEVEPTIDR_TXINEC|UOTGHS_DEVEPTIDR_RXOUTEC|UOTGHS_DEVEPTIDR_RXSTPEC|UOTGHS_DEVEPTIDR_UNDERFEC|UOTGHS_DEVEPTIDR_NAKOUTEC|
|
||||
UOTGHS_DEVEPTIDR_HBISOINERREC|UOTGHS_DEVEPTIDR_NAKINEC|UOTGHS_DEVEPTIDR_HBISOFLUSHEC|UOTGHS_DEVEPTIDR_OVERFEC|UOTGHS_DEVEPTIDR_STALLEDEC|
|
||||
UOTGHS_DEVEPTIDR_CRCERREC|UOTGHS_DEVEPTIDR_SHORTPACKETEC|UOTGHS_DEVEPTIDR_MDATEC|UOTGHS_DEVEPTIDR_DATAXEC|UOTGHS_DEVEPTIDR_ERRORTRANSEC|
|
||||
UOTGHS_DEVEPTIDR_NBUSYBKEC|UOTGHS_DEVEPTIDR_FIFOCONC|UOTGHS_DEVEPTIDR_EPDISHDMAC|UOTGHS_DEVEPTIDR_NYETDISC|UOTGHS_DEVEPTIDR_STALLRQC);
|
||||
|
||||
// Reset endpoint config
|
||||
UOTGHS->UOTGHS_DEVEPTCFG[ul] = 0UL;
|
||||
|
||||
// Reset DMA channel (Buff count and Control field)
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||||
UOTGHS->UOTGHS_DEVDMA[ul].UOTGHS_DEVDMACONTROL = 0x02UL; // NON STOP command
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||||
|
||||
// Reset DMA channel 0 (STOP)
|
||||
UOTGHS->UOTGHS_DEVDMA[ul].UOTGHS_DEVDMACONTROL = 0UL; // STOP command
|
||||
|
||||
// Clear DMA channel status (read the register to clear it)
|
||||
UOTGHS->UOTGHS_DEVDMA[ul].UOTGHS_DEVDMASTATUS = UOTGHS->UOTGHS_DEVDMA[ul].UOTGHS_DEVDMASTATUS;
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||||
}
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||||
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||||
UOTGHS->UOTGHS_CTRL |= UOTGHS_CTRL_VBUSTE;
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||||
UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_WAKEUPES;
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||||
*/
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||||
return 0UL ;
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||||
}
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||||
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||||
@ -213,18 +91,9 @@ void UDD_Attach(void)
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||||
//UDIEN = (1<<EORSTE)|(1<<SOFE); // Enable interrupts for EOR (End of Reset) and SOF (start of frame)
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||||
//UDCON = 0; // enable attach resistor
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||||
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||||
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||||
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||||
|
||||
irqflags_t flags = cpu_irq_save();
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||||
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||||
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||||
printf("=> UDD_Attach\r\n");
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||||
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||||
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//printf("=> UDD_Attach\r\n");
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||||
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||||
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||||
otg_unfreeze_clock();
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@ -247,7 +116,6 @@ void UDD_Attach(void)
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||||
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// Reset following interupts flag
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||||
//udd_ack_reset();
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||||
//udd_ack_sof();
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@ -261,63 +129,54 @@ void UDD_Attach(void)
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||||
//otg_freeze_clock();
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||||
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||||
cpu_irq_restore(flags);
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||||
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||||
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||||
/*
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||||
otg_disable_id_pin();
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||||
otg_force_device_mode();
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||||
|
||||
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||||
UOTGHS->UOTGHS_CTRL &= ~UOTGHS_CTRL_OTGPADE;
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||||
UOTGHS->UOTGHS_CTRL |= UOTGHS_CTRL_OTGPADE;
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||||
UOTGHS->UOTGHS_CTRL |= UOTGHS_CTRL_USBE;
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||||
UOTGHS->UOTGHS_CTRL &= ~UOTGHS_CTRL_FRZCLK;
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||||
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||||
udd_low_speed_disable();
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||||
udd_high_speed_disable();
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||||
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||||
UOTGHS->UOTGHS_DEVIER = (UOTGHS_DEVIER_EORSTES | UOTGHS_DEVIER_SOFES);
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||||
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||||
otg_ack_vbus_transition();
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||||
// Force Vbus interrupt in case of Vbus always with a high level
|
||||
// This is possible with a short timing between a Host mode stop/start.
|
||||
if (Is_otg_vbus_high()) {
|
||||
otg_raise_vbus_transition();
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||||
}
|
||||
otg_enable_vbus_interrupt();
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||||
otg_freeze_clock();
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||||
*/
|
||||
|
||||
}
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||||
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||||
void UDD_Detach(void)
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||||
{
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||||
printf("=> UDD_Detach\r\n");
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//printf("=> UDD_Detach\r\n");
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||||
UOTGHS->UOTGHS_DEVCTRL |= UOTGHS_DEVCTRL_DETACH;
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||||
}
|
||||
|
||||
void UDD_InitEP( uint32_t ul_ep_nb, uint32_t ul_ep_cfg )
|
||||
{
|
||||
printf("=> UDD_InitEP\r\n");
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||||
|
||||
ul_ep_nb = ul_ep_nb & 0xF; // EP range is 0..9, hence mask is 0xF.
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||||
//printf("=> UDD_InitEP : init EP %d\r\n", ul_ep_nb);
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||||
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||||
// Reset EP
|
||||
UOTGHS->UOTGHS_DEVEPT = (UOTGHS_DEVEPT_EPRST0 << ul_ep_nb);
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||||
//UOTGHS->UOTGHS_DEVEPT = (UOTGHS_DEVEPT_EPRST0 << ul_ep_nb);
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||||
// Configure EP
|
||||
UOTGHS->UOTGHS_DEVEPTCFG[ul_ep_nb] = ul_ep_cfg;
|
||||
// Allocate memory
|
||||
//udd_allocate_memory(ul_ep_nb);
|
||||
// Enable EP
|
||||
UOTGHS->UOTGHS_DEVEPT = (UOTGHS_DEVEPT_EPEN0 << ul_ep_nb);
|
||||
// UOTGHS->UOTGHS_DEVEPT |= (UOTGHS_DEVEPT_EPEN0 << ul_ep_nb);
|
||||
udd_enable_endpoint(ul_ep_nb);
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||||
if (!Is_udd_endpoint_configured(ul_ep_nb)) {
|
||||
//printf("=> UDD_InitEP : ############################## ERROR FAILED TO INIT EP %d\r\n", ul_ep_nb);
|
||||
}
|
||||
}
|
||||
|
||||
void UDD_InitEndpoints(const uint32_t* eps_table)
|
||||
|
||||
void UDD_InitEndpoints(const uint32_t* eps_table, const uint32_t ul_eps_table_size)
|
||||
{
|
||||
uint32_t ul_ep_nb ;
|
||||
|
||||
printf("=> UDD_InitEndpoints\r\n");
|
||||
|
||||
for (ul_ep_nb = 1; ul_ep_nb < sizeof(eps_table); ul_ep_nb++)
|
||||
|
||||
|
||||
|
||||
for (ul_ep_nb = 1; ul_ep_nb < ul_eps_table_size; ul_ep_nb++)
|
||||
|
||||
|
||||
/*void UDD_InitEndpoints(const uint32_t eps_table[])
|
||||
{
|
||||
uint32_t ul_ep_nb ;
|
||||
|
||||
|
||||
//printf("=> UDD_InitEndpoints : Taille tableau %d %d\r\n", sizeof(eps_table), (sizeof(eps_table) / sizeof(eps_table[0])));
|
||||
|
||||
for (ul_ep_nb = 1; ul_ep_nb < sizeof(eps_table) / sizeof(eps_table[0]); ul_ep_nb++)*/
|
||||
{
|
||||
// Reset Endpoint Fifos
|
||||
/* UOTGHS->UOTGHS_DEVEPTISR[ul_EP].UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_TOGGLESQ | UDPHS_EPTCLRSTA_FRCESTALL;
|
||||
@ -334,18 +193,28 @@ void UDD_InitEndpoints(const uint32_t* eps_table)
|
||||
// UECFG1X = EP_DOUBLE_64;
|
||||
}*/
|
||||
|
||||
//printf("=> UDD_InitEndpoints : init EP %d\r\n", ul_ep_nb);
|
||||
|
||||
|
||||
// Reset EP
|
||||
UOTGHS->UOTGHS_DEVEPT = (UOTGHS_DEVEPT_EPRST0 << ul_ep_nb);
|
||||
//UOTGHS->UOTGHS_DEVEPT = (UOTGHS_DEVEPT_EPRST0 << ul_ep_nb);
|
||||
// Configure EP
|
||||
UOTGHS->UOTGHS_DEVEPTCFG[ul_ep_nb] = eps_table[ul_ep_nb];
|
||||
// Allocate memory
|
||||
//udd_allocate_memory(ul_ep_nb);
|
||||
// Enable EP
|
||||
UOTGHS->UOTGHS_DEVEPT = (UOTGHS_DEVEPT_EPEN0 << ul_ep_nb);
|
||||
//UOTGHS->UOTGHS_DEVEPT |= (UOTGHS_DEVEPT_EPEN0 << ul_ep_nb);
|
||||
udd_enable_endpoint(ul_ep_nb);
|
||||
if (!Is_udd_endpoint_configured(ul_ep_nb)) {
|
||||
//printf("=> UDD_InitEP : ############################## ERROR FAILED TO INIT EP %d\r\n", ul_ep_nb);
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void UDD_SetEP( uint32_t ep )
|
||||
{
|
||||
ul_ep = ep;
|
||||
ul_ep = ep & 0xF; // EP range is 0..9, hence mask is 0xF.
|
||||
}
|
||||
|
||||
// Wait until ready to accept IN packet.
|
||||
@ -363,13 +232,10 @@ void UDD_WaitOUT(void)
|
||||
;
|
||||
}
|
||||
|
||||
uint32_t ul_send_index = 0;
|
||||
uint32_t ul_rcv_index = 0;
|
||||
|
||||
// Send packet.
|
||||
void UDD_ClearIN(void)
|
||||
{
|
||||
printf("=> UDD_ClearIN: sent %d bytes\r\n", ul_send_index);
|
||||
//printf("=> UDD_ClearIN: sent %d bytes\r\n", ul_send_index);
|
||||
// UEINTX = ~(1<<TXINI);
|
||||
UOTGHS->UOTGHS_DEVEPTICR[ul_ep] = UOTGHS_DEVEPTICR_TXINIC;
|
||||
ul_send_index = 0;
|
||||
@ -379,7 +245,7 @@ void UDD_ClearOUT(void)
|
||||
{
|
||||
// UEINTX = ~(1<<RXOUTI);
|
||||
UOTGHS->UOTGHS_DEVEPTICR[ul_ep] = UOTGHS_DEVEPTICR_RXOUTIC;
|
||||
ul_rcv_index = 0;
|
||||
ul_recv_index = 0;
|
||||
}
|
||||
|
||||
// Wait for IN FIFO to be ready to accept data or OUT FIFO to receive data.
|
||||
@ -409,7 +275,7 @@ void UDD_Send8( uint8_t data )
|
||||
{
|
||||
uint8_t *ptr_dest = (uint8_t *) &udd_get_endpoint_fifo_access8(ul_ep);
|
||||
|
||||
printf("=> UDD_Send8 : ul_send_index=%d\r\n", ul_send_index);
|
||||
printf("=> UDD_Send8 : ul_send_index=%d data=0x%x\r\n", ul_send_index, data);
|
||||
ptr_dest[ul_send_index++] = data;
|
||||
}
|
||||
|
||||
@ -417,7 +283,8 @@ uint8_t UDD_Recv8(void)
|
||||
{
|
||||
uint8_t *ptr_dest = (uint8_t *) &udd_get_endpoint_fifo_access8(ul_ep);
|
||||
|
||||
return ptr_dest[ul_rcv_index++];
|
||||
////printf("=> UDD_Recv8 : ul_recv_index=%d\r\n", ul_recv_index);
|
||||
return ptr_dest[ul_recv_index++];
|
||||
}
|
||||
|
||||
void UDD_Recv(volatile uint8_t* data, uint32_t count)
|
||||
@ -425,7 +292,7 @@ void UDD_Recv(volatile uint8_t* data, uint32_t count)
|
||||
uint8_t *ptr_dest = (uint8_t *) &udd_get_endpoint_fifo_access8(ul_ep);
|
||||
|
||||
while (count--)
|
||||
*data++ = ptr_dest[ul_rcv_index++];
|
||||
*data++ = ptr_dest[ul_recv_index++];
|
||||
}
|
||||
|
||||
void UDD_Stall(void)
|
||||
@ -448,9 +315,10 @@ void UDD_ReleaseRX(void)
|
||||
nakouti a clearer
|
||||
rxouti/killbank a clearer*/
|
||||
|
||||
puts("=> UDD_ReleaseRX\r\n");
|
||||
//puts("=> UDD_ReleaseRX\r\n");
|
||||
UOTGHS->UOTGHS_DEVEPTICR[ul_ep] = (UOTGHS_DEVEPTICR_NAKOUTIC | UOTGHS_DEVEPTICR_RXOUTIC);
|
||||
UOTGHS->UOTGHS_DEVEPTIDR[ul_ep] = UOTGHS_DEVEPTIDR_FIFOCONC;
|
||||
ul_recv_index = 0;
|
||||
}
|
||||
|
||||
void UDD_ReleaseTX(void)
|
||||
@ -461,11 +329,13 @@ void UDD_ReleaseTX(void)
|
||||
rxouti/killbank a clearer
|
||||
txini a clearer*/
|
||||
|
||||
puts("=> UDD_ReleaseTX\r\n");
|
||||
//puts("=> UDD_ReleaseTX\r\n");
|
||||
UOTGHS->UOTGHS_DEVEPTICR[ul_ep] = (UOTGHS_DEVEPTICR_NAKINIC | UOTGHS_DEVEPTICR_RXOUTIC | UOTGHS_DEVEPTICR_TXINIC);
|
||||
UOTGHS->UOTGHS_DEVEPTIDR[ul_ep] = UOTGHS_DEVEPTIDR_FIFOCONC;
|
||||
ul_send_index = 0;
|
||||
}
|
||||
|
||||
// Return true if the current bank is not full.
|
||||
uint32_t UDD_ReadWriteAllowed(void)
|
||||
{
|
||||
return (UOTGHS->UOTGHS_DEVEPTISR[ul_ep] & UOTGHS_DEVEPTISR_RWALL);
|
||||
@ -473,7 +343,7 @@ uint32_t UDD_ReadWriteAllowed(void)
|
||||
|
||||
void UDD_SetAddress(uint32_t addr)
|
||||
{
|
||||
printf("=> UDD_SetAddress : setting address to %d\r\n", addr);
|
||||
//printf("=> UDD_SetAddress : setting address to %d\r\n", addr);
|
||||
udd_configure_address(addr);
|
||||
udd_enable_address();
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user