LibrePilot/flight/targets/boards/revoproto/board-info.mk

BOARD_TYPE          := 0x09
BOARD_REVISION      := 0x02
BOOTLOADER_VERSION  := 0x05
HW_TYPE             := 0x00

MCU                 := cortex-m4
CHIP                := STM32F405RGT
BOARD               := STM32F4xx_RP
MODEL               := HD
MODEL_SUFFIX        := 

OPENOCD_JTAG_CONFIG := stlink-v2.cfg
OPENOCD_CONFIG      := stm32f4xx.stlink.cfg

# Note: These must match the values in link_$(BOARD)_memory.ld
BL_BANK_BASE        := 0x08000000  # Start of bootloader flash
BL_BANK_SIZE        := 0x00008000  # Should include BD_INFO region

# 16KB for settings storage

EE_BANK_BASE        := 0x08008000  # EEPROM storage area
EE_BANK_SIZE        := 0x00008000  # Size of EEPROM storage area

# Leave the remaining 64KB sectors for other uses

FW_BANK_BASE        := 0x08020000  # Start of firmware flash
FW_BANK_SIZE        := 0x00060000  # Should include FW_DESC_SIZE

FW_DESC_SIZE        := 0x00000064

OSCILLATOR_FREQ     :=   8000000
SYSCLK_FREQ         := 168000000
Configuration tab for revo 2011-12-24 13:57:10 -06:00			`BOARD_TYPE := 0x09`
Update the bootloader hw version for the mpu6000 board and make the sensor code and initialization respond appropriately. Enable hte L3GD20 and BMA180. Let the board type determine which is used. 2012-03-21 02:00:32 -05:00			`BOARD_REVISION := 0x02`
OP-917 Extended the program flash size to 3 128k sectors for F4 targets +review OPReview-456 2013-04-30 18:26:25 +02:00			`BOOTLOADER_VERSION := 0x05`
Make new Revolution target 2011-11-01 01:10:54 -05:00			`HW_TYPE := 0x00`

			`MCU := cortex-m4`
Coyp over some of how the PH build system works 2011-11-01 01:36:52 -05:00			`CHIP := STM32F405RGT`
REVONANO - Allows per board linker scripts 2014-09-04 15:13:16 +02:00			`BOARD := STM32F4xx_RP`
Make new Revolution target 2011-11-01 01:10:54 -05:00			`MODEL := HD`
			`MODEL_SUFFIX :=`

build: use board-specific JTAG interface for openocd Removes hard-coding of JTAG interface config in the <board>_program make macros. This allows the use of STLINKv2 for F4 boards while continuing to use the FOSS JTAG revB on F1 boards. 2012-02-25 12:35:29 -05:00			`OPENOCD_JTAG_CONFIG := stlink-v2.cfg`
			`OPENOCD_CONFIG := stm32f4xx.stlink.cfg`
Make new Revolution target 2011-11-01 01:10:54 -05:00
			`# Note: These must match the values in link_$(BOARD)_memory.ld`
			`BL_BANK_BASE := 0x08000000 # Start of bootloader flash`
			`BL_BANK_SIZE := 0x00008000 # Should include BD_INFO region`
revo: move fw image into 128KB sectors This saves the more versatile 16KB and 64KB sectors for other purposes. 2012-03-25 17:49:39 -04:00
Uses Internal flash for system settings storage repourposing external flash for "User" storage 2013-05-11 22:06:30 +02:00			`# 16KB for settings storage`

			`EE_BANK_BASE := 0x08008000 # EEPROM storage area`
			`EE_BANK_SIZE := 0x00008000 # Size of EEPROM storage area`

			`# Leave the remaining 64KB sectors for other uses`
revo: move fw image into 128KB sectors This saves the more versatile 16KB and 64KB sectors for other purposes. 2012-03-25 17:49:39 -04:00
			`FW_BANK_BASE := 0x08020000 # Start of firmware flash`
OP-917 Extended the program flash size to 3 128k sectors for F4 targets +review OPReview-456 2013-04-30 18:26:25 +02:00			`FW_BANK_SIZE := 0x00060000 # Should include FW_DESC_SIZE`
Make new Revolution target 2011-11-01 01:10:54 -05:00
			`FW_DESC_SIZE := 0x00000064`

sysclk: pass in correct definition for HSE_VALUE The code in RCC_GetClocksFreq() uses HSE_VALUE to determine the tick rate of the SYSCLK. This in turn is used by the code in PIOS_DELAY_* to compute delays. ST Library defaults this to 25MHz for the F4. Our board actually has an 8MHz oscillator so delays were way off. Mostly affects the bootloaders since most FW code uses RTOS delays rather than busy-waiting using PIOS_DELAY_*. 2012-03-04 19:50:27 -05:00			`OSCILLATOR_FREQ := 8000000`
Make new Revolution target 2011-11-01 01:10:54 -05:00			`SYSCLK_FREQ := 168000000`