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Code Issues Releases Activity

Begin rewriting pios_overo to look like a standard com layer

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This commit is contained in:
James Cotton 2012-07-20 03:42:09 -05:00
parent 7492d34d25
commit 1c4c373b86
2 changed files with 199 additions and 190 deletions
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352
flight/PiOS/STM32F4xx/pios_overo.c
View File

@ -44,79 +44,156 @@
#define PACKET_SIZE 1024 #define PACKET_SIZE 1024
static void PIOS_OVERO_NSS_IRQHandler(); /* Provide a COM driver */
static void PIOS_OVERO_RegisterRxCallback(uint32_t overo_id, pios_com_callback rx_in_cb, uint32_t context);
static void PIOS_OVERO_RegisterTxCallback(uint32_t overo_id, pios_com_callback tx_out_cb, uint32_t context);
static void PIOS_OVERO_TxStart(uint32_t overo_id, uint16_t tx_bytes_avail);
static void PIOS_OVERO_RxStart(uint32_t overo_id, uint16_t rx_bytes_avail);
static const struct pios_exti_cfg pios_exti_overo_cfg __exti_config = { const struct pios_com_driver pios_overo_com_driver = {
.vector = PIOS_OVERO_NSS_IRQHandler, .set_baud = NULL,
.line = EXTI_Line15, .tx_start = PIOS_OVERO_TxStart,
.pin = { .rx_start = PIOS_OVERO_RxStart,
.gpio = GPIOA, .bind_tx_cb = PIOS_OVERO_RegisterTxCallback,
.init = { .bind_rx_cb = PIOS_OVERO_RegisterRxCallback,
.GPIO_Pin = GPIO_Pin_15,
.GPIO_Speed = GPIO_Speed_100MHz,
.GPIO_Mode = GPIO_Mode_IN,
.GPIO_OType = GPIO_OType_OD,
.GPIO_PuPd = GPIO_PuPd_NOPULL,
},
},
.irq = {
.init = {
.NVIC_IRQChannel = EXTI15_10_IRQn,
.NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_MID,
.NVIC_IRQChannelSubPriority = 0,
.NVIC_IRQChannelCmd = ENABLE,
},
},
.exti = {
.init = {
.EXTI_Line = EXTI_Line15, // matches above GPIO pin
.EXTI_Mode = EXTI_Mode_Interrupt,
.EXTI_Trigger = EXTI_Trigger_Rising,
.EXTI_LineCmd = ENABLE,
},
},
}; };
//! Data types
enum pios_overo_dev_magic {
PIOS_OVERO_DEV_MAGIC = 0x85A3834A,
};
static bool PIOS_OVERO_validate(struct pios_overo_dev * com_dev) struct pios_overo_dev {
enum pios_overo_dev_magic magic;
const struct pios_overo_cfg * cfg;
int8_t writing_buffer;
uint32_t writing_offset;
uint8_t tx_buffer[2][PACKET_SIZE];
uint8_t rx_buffer[2][PACKET_SIZE];
pios_com_callback rx_in_cb;
uint32_t rx_in_context;
pios_com_callback tx_out_cb;
uint32_t tx_out_context;
};
//! Private methods
static void PIOS_OVERO_WriteData(struct pios_overo_dev *overo_dev);
static bool PIOS_OVERO_validate(struct pios_overo_dev * overo_dev);
static struct pios_overo_dev * PIOS_OVERO_alloc(void);
static bool PIOS_OVERO_validate(struct pios_overo_dev * overo_dev)
{ {
/* Should check device magic here */ return (overo_dev->magic == PIOS_OVERO_DEV_MAGIC);
return(true);
} }
#if defined(PIOS_INCLUDE_FREERTOS) #if !defined(PIOS_INCLUDE_FREERTOS)
#error Requires FreeRTOS
#endif /* PIOS_INCLUDE_FREERTOS */
static struct pios_overo_dev * PIOS_OVERO_alloc(void) static struct pios_overo_dev * PIOS_OVERO_alloc(void)
{ {
return (malloc(sizeof(struct pios_overo_dev))); struct pios_overo_dev * overo_dev;
}
#else
#error Unsupported
#endif
//! Global variable overo_dev = (struct pios_overo_dev *)pvPortMalloc(sizeof(*overo_dev));
struct pios_overo_dev * overo_dev; if (!overo_dev) return(NULL);
overo_dev->rx_in_cb = 0;
overo_dev->rx_in_context = 0;
overo_dev->tx_out_cb = 0;
overo_dev->tx_out_context = 0;
overo_dev->magic = PIOS_OVERO_DEV_MAGIC;
return(overo_dev);
}
/** /**
* Initialises Overo pins * Take data from the PIOS_COM buffer and transfer it to the currently inactive DMA
* \param[in] mode currently only mode 0 supported * circular buffer
* \return < 0 if initialisation failed */
*/ static void PIOS_OVERO_WriteData(struct pios_overo_dev *overo_dev)
int32_t PIOS_Overo_Init(const struct pios_overo_cfg * cfg)
{ {
PIOS_Assert(cfg); // TODO: How do we protect against the DMA buffer swapping midway through adding data
// to this buffer. If we were writing at the beginning it could cause a weird race.
if (overo_dev->tx_out_cb) {
uint32_t max_bytes = PACKET_SIZE - overo_dev->writing_offset;
if (max_bytes > 0) {
bool tx_need_yield = false;
uint16_t bytes_added;
uint8_t *writing_pointer = &overo_dev->tx_buffer[overo_dev->writing_buffer][overo_dev->writing_offset];
bytes_added = (overo_dev->tx_out_cb)(overo_dev->tx_out_context, writing_pointer, max_bytes, NULL, &tx_need_yield);
if (tx_need_yield) {
vPortYieldFromISR();
}
overo_dev->writing_offset += bytes_added;
}
}
}
/**
* Called at the end of each DMA transaction. Refresh the flag indicating which
* DMA buffer to write new data from the PIOS_COM fifo into the buffer
*/
void PIOS_OVERO_DMA_irq_handler(uint32_t overo_id)
{
struct pios_overo_dev * overo_dev = (struct pios_overo_dev *) overo_id;
PIOS_Assert(PIOS_OVERO_validate(overo_dev));
overo_dev->writing_memory = 1 - DMA_GetCurMemoryTarget(overo_dev->cfg->dma.tx.channel);
// Get data from the Rx buffer and add to the fifo
(void) (overo_dev->rx_in_cb)(overo_dev->rx_in_context,
&overo_dev->rx_buffer[overo_dev->writing_buffer][0],
PACKET_SIZE, NULL, &rx_need_yield);
// Fill the buffer with known value to prevent rereading these bytes
memset(&overo_dev->rx_buffer[overo_dev->writing_buffer][0], 0xFF, PACKET_SIZE);
// Fill the buffer with known value to prevent resending any bytes
memset(&overo_dev->tx_buffer[overo_dev->writing_buffer][0], 0xFF, PACKET_SIZE);
// Load any pending bytes from TX fifo
PIOS_OVERO_WriteData(overo_dev);
}
/**
* Initialise a single Overo device
*/
int32_t PIOS_OVERO_Init(uint32_t * overo_id, const struct pios_overo_cfg * cfg)
{
PIOS_DEBUG_Assert(overo_id);
PIOS_DEBUG_Assert(cfg);
struct pios_overo_dev *overo_dev;
overo_dev = (struct pios_overo_dev *) PIOS_OVERO_alloc(); overo_dev = (struct pios_overo_dev *) PIOS_OVERO_alloc();
if (!overo_dev) goto out_fail; if (!overo_dev) goto out_fail;
/* Bind the configuration to the device instance */ /* Bind the configuration to the device instance */
overo_dev->cfg = cfg; overo_dev->cfg = cfg;
overo_dev->writing_buffer = 1; // First writes to second buffer
/* Disable callback function */ /* Put buffers to a known state */
overo_dev->callback = NULL; memset(&overo_dev->tx_buffer[0][0], 0xFF, PACKET_SIZE);
memset(&overo_dev->tx_buffer[1][0], 0xFF, PACKET_SIZE);
memset(&overo_dev->rx_buffer[0][0], 0xFF, PACKET_SIZE);
memset(&overo_dev->rx_buffer[1][0], 0xFF, PACKET_SIZE);
/* Set a null buffer initially */ /*
overo_dev->new_tx_buffer = 0; * Enable the SPI device
overo_dev->new_rx_buffer = 0; *
* 1. Enable the SPI port
* 2. Enable DMA with circular buffered DMA (validate config)
* 3. Enable the DMA Tx IRQ
*/
//PIOS_Assert(overo_dev->cfg->dma.tx-> == CIRCULAR);
//PIOS_Assert(overo_dev->cfg->dma.rx-> == CIRCULAR);
/* only legal for single-slave config */ /* only legal for single-slave config */
PIOS_Assert(overo_dev->cfg->slave_count == 1); PIOS_Assert(overo_dev->cfg->slave_count == 1);
@ -141,15 +218,24 @@ int32_t PIOS_Overo_Init(const struct pios_overo_cfg * cfg)
GPIO_Init(overo_dev->cfg->mosi.gpio, (GPIO_InitTypeDef*)&(overo_dev->cfg->mosi.init)); GPIO_Init(overo_dev->cfg->mosi.gpio, (GPIO_InitTypeDef*)&(overo_dev->cfg->mosi.init));
GPIO_Init(overo_dev->cfg->miso.gpio, (GPIO_InitTypeDef*)&(overo_dev->cfg->miso.init)); GPIO_Init(overo_dev->cfg->miso.gpio, (GPIO_InitTypeDef*)&(overo_dev->cfg->miso.init));
/* Configure DMA for SPI Rx */ /* Configure circular buffer targets. Configure 0 to be initially active */
DMA_DeInit(overo_dev->cfg->dma.rx.channel); DMA_InitTypeDef dma_init;
DMA_Cmd(overo_dev->cfg->dma.rx.channel, DISABLE);
DMA_Init(overo_dev->cfg->dma.rx.channel, (DMA_InitTypeDef*)&(overo_dev->cfg->dma.rx.init)); DMA_DeInit(overo_dev->cfg->dma.rx.channel);
dma_init = overo_dev->cfg->dma.rx.init;
dma_init.DMA_Memory0BaseAddr = (uin32_t) overo_dev->rx_buffer[0];
dma_init.DMA_MemoryInc = DMA_MemoryInc_Enable;
dma_init.DMA_BufferSize = PACKET_SIZE;
DMA_Init(overo_dev->cfg->dma.rx.channel, &dma_init);
DMA_DoubleBufferModeConfig(overo_dev->cfg->dma.rx.channel, (uin32_t) overo_dev->rx_buffer[1], DMA_Memory_0);
/* Configure DMA for SPI Tx */
DMA_DeInit(overo_dev->cfg->dma.tx.channel); DMA_DeInit(overo_dev->cfg->dma.tx.channel);
DMA_Cmd(overo_dev->cfg->dma.tx.channel, DISABLE); dma_init = overo_dev->cfg->dma.tx.init;
DMA_Init(overo_dev->cfg->dma.tx.channel, (DMA_InitTypeDef*)&(overo_dev->cfg->dma.tx.init)); dma_init.DMA_Memory0BaseAddr = (uin32_t) overo_dev->tx_buffer[0];
dma_init.DMA_MemoryInc = DMA_MemoryInc_Enable;
dma_init.DMA_BufferSize = PACKET_SIZE;
DMA_Init(overo_dev->cfg->dma.tx.channel, &dma_init);
DMA_DoubleBufferModeConfig(overo_dev->cfg->dma.tx.channel, (uin32_t) overo_dev->tx_buffer[1], DMA_Memory_0);
/* Initialize the SPI block */ /* Initialize the SPI block */
SPI_DeInit(overo_dev->cfg->regs); SPI_DeInit(overo_dev->cfg->regs);
@ -171,8 +257,9 @@ int32_t PIOS_Overo_Init(const struct pios_overo_cfg * cfg)
/* Configure DMA interrupt */ /* Configure DMA interrupt */
NVIC_Init((NVIC_InitTypeDef*)&(overo_dev->cfg->dma.irq.init)); NVIC_Init((NVIC_InitTypeDef*)&(overo_dev->cfg->dma.irq.init));
/* Configure the interrupt for rising edge of NSS */ /* Enable the DMA channels */
PIOS_EXTI_Init(&pios_exti_overo_cfg); DMA_Cmd(overo_dev->cfg->dma.tx.channel, ENABLE);
DMA_Cmd(overo_dev->cfg->dma.rx.channel, ENABLE);
return(0); return(0);
@ -180,126 +267,57 @@ out_fail:
return(-1); return(-1);
} }
/** static void PIOS_OVERO_RxStart(uint32_t overo_id, uint16_t rx_bytes_avail)
* Transfers a block of bytes via DMA.
* \param[in] overo_id SPI device handle
* \param[in] send_buffer pointer to buffer which should be sent.<BR>
* If NULL, 0xff (all-one) will be sent.
* \param[in] receive_buffer pointer to buffer which should get the received values.<BR>
* If NULL, received bytes will be discarded.
* \param[in] len number of bytes which should be transfered
* \param[in] callback pointer to callback function which will be executed
* from DMA channel interrupt once the transfer is finished.
* If NULL, no callback function will be used, and PIOS_SPI_TransferBlock() will
* block until the transfer is finished.
* \return >= 0 if no error during transfer
* \return -1 if disabled SPI port selected
* \return -3 if function has been called during an ongoing DMA transfer
*/
int32_t PIOS_Overo_SetNewBuffer(const uint8_t *send_buffer, uint8_t *receive_buffer, uint16_t len)
{ {
bool valid = PIOS_OVERO_validate(overo_dev); struct pios_overo_dev * overo_dev = (struct pios_overo_dev *)overo_id;
PIOS_Assert(valid)
bool overrun = overo_dev->new_tx_buffer || overo_dev->new_rx_buffer;
/* Cache next buffer */
overo_dev->new_tx_buffer = (uint32_t) send_buffer;
overo_dev->new_rx_buffer = (uint32_t) receive_buffer;
/* No error */
return overrun ? -1 : 0;
}
/**
* Set the callback function
*/
int32_t PIOS_Overo_SetCallback(void *callback)
{
overo_dev->callback = callback;
return 0;
}
/**
* On the rising edge of NSS schedule a new transaction. This cannot be
* done by the DMA complete because there is 150 us between that and the
* Overo deasserting the CS line. We don't want to spin that long in an
* isr.
*
* 1. Disable the DMA channel
* 2. Check that the DMA counter is at the end of the buffer (increase an
* error counter if not)
* 3. Reset the DMA counter to the end of the beginning of the buffer
* 4. Swap the buffer
* 5. Enable the DMA channel
*/
void PIOS_OVERO_NSS_IRQHandler()
{
static uint32_t error_counter = 0;
bool valid = PIOS_OVERO_validate(overo_dev); bool valid = PIOS_OVERO_validate(overo_dev);
PIOS_Assert(valid) PIOS_Assert(valid);
/* Disable the SPI peripheral */ // DMA RX enable (enable IRQ) ?
SPI_Cmd(overo_dev->cfg->regs, DISABLE); }
/* Disable the DMA commands */ static void PIOS_OVERO_TxStart(uint32_t overo_id, uint16_t tx_bytes_avail)
DMA_Cmd(overo_dev->cfg->dma.tx.channel, DISABLE); {
DMA_Cmd(overo_dev->cfg->dma.rx.channel, DISABLE); struct pios_overo_dev * overo_dev = (struct pios_overo_dev *)overo_id;
/* Check that the previous DMA transfer completed */ bool valid = PIOS_OVERO_validate(overo_dev);
if(DMA_GetCurrDataCounter(overo_dev->cfg->dma.tx.channel) || PIOS_Assert(valid);
DMA_GetCurrDataCounter(overo_dev->cfg->dma.rx.channel))
error_counter++;
/* Disable and initialize the SPI peripheral */ // DMA TX enable (enable IRQ) ?
SPI_DeInit(overo_dev->cfg->regs);
SPI_Init(overo_dev->cfg->regs, (SPI_InitTypeDef*)&(overo_dev->cfg->init));
SPI_Cmd(overo_dev->cfg->regs, DISABLE);
/* Enable SPI interrupts to DMA */ // Load any pending bytes from TX fifo
SPI_I2S_DMACmd(overo_dev->cfg->regs, SPI_I2S_DMAReq_Tx | SPI_I2S_DMAReq_Rx, ENABLE); PIOS_OVERO_WriteData(overo_dev);
}
/* Reinit the DMA channels */ static void PIOS_OVERO_RegisterRxCallback(uint32_t overo_id, pios_com_callback rx_in_cb, uint32_t context)
DMA_InitTypeDef dma_init; {
struct pios_overo_dev * overo_dev = (struct pios_overo_dev *)overo_id;
DMA_DeInit(overo_dev->cfg->dma.rx.channel); bool valid = PIOS_OVERO_validate(overo_dev);
dma_init = overo_dev->cfg->dma.rx.init; PIOS_Assert(valid);
if (overo_dev->new_rx_buffer) {
/* Enable memory addr. increment - bytes written into receive buffer */
dma_init.DMA_Memory0BaseAddr = (uint32_t) overo_dev->new_rx_buffer;
dma_init.DMA_MemoryInc = DMA_MemoryInc_Enable;
dma_init.DMA_BufferSize = PACKET_SIZE;
}
DMA_Init(overo_dev->cfg->dma.rx.channel, &(dma_init));
DMA_DeInit(overo_dev->cfg->dma.tx.channel); /*
dma_init = overo_dev->cfg->dma.tx.init; * Order is important in these assignments since ISR uses _cb
if (overo_dev->new_tx_buffer) { * field to determine if it's ok to dereference _cb and _context
/* Enable memory addr. increment - bytes written into receive buffer */ */
dma_init.DMA_Memory0BaseAddr = (uint32_t) overo_dev->new_tx_buffer; overo_dev->rx_in_context = context;
dma_init.DMA_MemoryInc = DMA_MemoryInc_Enable; overo_dev->rx_in_cb = rx_in_cb;
dma_init.DMA_BufferSize = PACKET_SIZE; }
}
DMA_Init(overo_dev->cfg->dma.tx.channel, &(dma_init));
/* Make sure to flush out the receive buffer */ static void PIOS_OVERO_RegisterTxCallback(uint32_t overo_id, pios_com_callback tx_out_cb, uint32_t context)
(void)SPI_I2S_ReceiveData(overo_dev->cfg->regs); {
struct pios_overo_dev * overo_dev = (struct pios_overo_dev *)overo_id;
/* Enable the DMA endpoints for valid buffers */ bool valid = PIOS_OVERO_validate(overo_dev);
if(overo_dev->new_rx_buffer) PIOS_Assert(valid);
DMA_Cmd(overo_dev->cfg->dma.rx.channel, ENABLE);
if(overo_dev->new_tx_buffer)
DMA_Cmd(overo_dev->cfg->dma.tx.channel, ENABLE);
/* Reenable the SPI peripheral */ /*
SPI_Cmd(overo_dev->cfg->regs, ENABLE); * Order is important in these assignments since ISR uses _cb
* field to determine if it's ok to dereference _cb and _context
/* Indicate these buffers have been used */ */
overo_dev->new_tx_buffer = 0; overo_dev->tx_out_context = context;
overo_dev->new_rx_buffer = 0; overo_dev->tx_out_cb = tx_out_cb;
if (overo_dev->callback != NULL)
overo_dev->callback(error_counter);
} }
#endif #endif

11
flight/PiOS/inc/pios_overo.h
View File

@ -46,16 +46,7 @@ struct pios_overo_cfg {
struct stm32_gpio ssel[]; struct stm32_gpio ssel[];
}; };
struct pios_overo_dev { extern int32_t PIOS_OVERO_Init(uint32_t * overo_id, const struct pios_overo_cfg * cfg);
const struct pios_overo_cfg * cfg;
void (*callback) (uint32_t);
uint32_t new_tx_buffer;
uint32_t new_rx_buffer;
};
extern int32_t PIOS_Overo_Init(const struct pios_overo_cfg * cfg);
extern int32_t PIOS_Overo_SetCallback(void *callback);
extern int32_t PIOS_Overo_SetNewBuffer(const uint8_t *send_buffer, uint8_t *receive_buffer, uint16_t len);
#endif /* PIOS_OVERO_H */ #endif /* PIOS_OVERO_H */