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Code Issues Releases Activity

Merge remote-tracking branch 'revo/amorale/rm2' into rm2

Browse Source 
Conflicts:
	flight/PiOS/inc/pios_hmc5883.h
This commit is contained in:
James Cotton 2012-10-02 09:11:37 -05:00
commit 1dae196274
7 changed files with 128 additions and 62 deletions
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11
flight/PiOS/Common/pios_rfm22b.c
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@ -462,7 +462,7 @@ static const uint8_t reg_23[] = { 0xC5, 0x89, 0x12, 0x25, 0x
static const uint8_t reg_24[] = { 0x00, 0x00, 0x00, 0x02, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x05, 0x07, 0x07}; // rfm22_clk_recovery_timing_loop_gain1
static const uint8_t reg_25[] = { 0x0A, 0x23, 0x85, 0x0E, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x74, 0xFF, 0xFF}; // rfm22_clk_recovery_timing_loop_gain0
static const uint8_t reg_2A[] = { 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0D, 0x0D, 0x0E, 0x12, 0x17, 0x31, 0x50, 0x50, 0x50}; // rfm22_afc_limiter .. AFC_pull_in_range = ±AFCLimiter[7:0] x (hbsel+1) x 625 Hz
static const uint8_t reg_2A[] = { 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0D, 0x0D, 0x0E, 0x12, 0x17, 0x31, 0x50, 0x50, 0x50}; // rfm22_afc_limiter .. AFC_pull_in_range = <EFBFBD>AFCLimiter[7:0] x (hbsel+1) x 625 Hz
static const uint8_t reg_6E[] = { 0x04, 0x08, 0x10, 0x20, 0x41, 0x4E, 0x83, 0x9D, 0xC4, 0x08, 0x10, 0x20, 0x31, 0x41}; // rfm22_tx_data_rate1
static const uint8_t reg_6F[] = { 0x19, 0x31, 0x62, 0xC5, 0x89, 0xA5, 0x12, 0x49, 0x9C, 0x31, 0x62, 0xC5, 0x27, 0x89}; // rfm22_tx_data_rate0
@ -495,7 +495,7 @@ static const uint8_t ss_reg_23[] = { 0xC5, 0xD3}; // rfm22_clk_recovery_offset0
static const uint8_t ss_reg_24[] = { 0x00, 0x07}; // rfm22_clk_recovery_timing_loop_gain1
static const uint8_t ss_reg_25[] = { 0x0F, 0xFF}; // rfm22_clk_recovery_timing_loop_gain0
static const uint8_t ss_reg_2A[] = { 0xFF, 0xFF}; // rfm22_afc_limiter .. AFC_pull_in_range = ±AFCLimiter[7:0] x (hbsel+1) x 625 Hz
static const uint8_t ss_reg_2A[] = { 0xFF, 0xFF}; // rfm22_afc_limiter .. AFC_pull_in_range = <EFBFBD>AFCLimiter[7:0] x (hbsel+1) x 625 Hz
static const uint8_t ss_reg_70[] = { 0x24, 0x2D}; // rfm22_modulation_mode_control1
static const uint8_t ss_reg_71[] = { 0x2B, 0x23}; // rfm22_modulation_mode_control2
@ -633,13 +633,14 @@ int32_t PIOS_RFM22B_Init(uint32_t *rfm22b_id, uint32_t spi_id, uint32_t slave_nu
/**
* The RFM22B external interrupt routine.
*/
void PIOS_RFM22_EXT_Int(void)
bool PIOS_RFM22_EXT_Int(void)
{
if (!PIOS_RFM22B_validate(g_rfm22b_dev))
return;
return false;
// Inject an interrupt event into the state machine.
PIOS_RFM22B_InjectEvent(g_rfm22b_dev, RFM22B_EVENT_INT_RECEIVED, true);
return false;
}
/**
@ -1746,7 +1747,7 @@ static enum pios_rfm22b_event rfm22_init(struct pios_rfm22b_dev *rfm22b_dev)
// adc offset
rfm22_write(RFM22_adc_sensor_amp_offset, 0);
// temp sensor calibration .. –40C to +64C 0.5C resolution
// temp sensor calibration .. <EFBFBD>40C to +64C 0.5C resolution
rfm22_write(RFM22_temp_sensor_calib, RFM22_tsc_tsrange0 | RFM22_tsc_entsoffs);
// temp sensor offset

16
flight/PiOS/STM32F4xx/pios_tim.c
View File

@ -127,6 +127,15 @@ int32_t PIOS_TIM_InitClock(const struct pios_tim_clock_cfg * cfg)
case (uint32_t)TIM11:
RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM11, ENABLE);
break;
case (uint32_t)TIM12:
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM12, ENABLE);
break;
case (uint32_t)TIM13:
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM13, ENABLE);
break;
case (uint32_t)TIM14:
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM14, ENABLE);
break;
#endif
}
@ -486,6 +495,13 @@ static void PIOS_TIM_8_CC_irq_handler (void)
PIOS_TIM_generic_irq_handler (TIM8);
}
void TIM8_BRK_TIM12_IRQHandler(void) __attribute__ ((alias ("PIOS_TIM_12_irq_handler")));
static void PIOS_TIM_12_irq_handler (void)
{
PIOS_TIM_generic_irq_handler (TIM12);
}
/**
* @}
* @}

2
flight/PiOS/inc/pios_hmc5883.h
View File

@ -107,7 +107,7 @@ extern bool PIOS_HMC5883_NewDataAvailable(void);
extern int32_t PIOS_HMC5883_ReadMag(int16_t out[3]);
extern uint8_t PIOS_HMC5883_ReadID(uint8_t out[4]);
extern int32_t PIOS_HMC5883_Test(void);
bool PIOS_HMC5883_IRQHandler();
extern bool PIOS_HMC5883_IRQHandler();
#endif /* PIOS_HMC5883_H */
/**

2
flight/PiOS/inc/pios_l3gd20.h
View File

@ -141,7 +141,7 @@ extern int32_t PIOS_L3GD20_SetRange(enum pios_l3gd20_range range);
extern float PIOS_L3GD20_GetScale();
extern int32_t PIOS_L3GD20_ReadID();
extern uint8_t PIOS_L3GD20_Test();
bool void PIOS_L3GD20_IRQHandler();
extern bool PIOS_L3GD20_IRQHandler();
#endif /* PIOS_L3GD20_H */

18
flight/PiOS/inc/pios_rfm22b_priv.h
View File

@ -83,7 +83,7 @@ extern const struct pios_com_driver pios_rfm22b_com_driver;
#define RFM22_is1_icrerror BIT0 // CRC Error. When set to 1 the cyclic redundancy check is failed.
#define RFM22_is1_ipkvalid BIT1 // Valid Packet Received.When set to 1 a valid packet has been received.
#define RFM22_is1_ipksent BIT2 // Packet Sent Interrupt. When set to1 a valid packet has been transmitted.
#define RFM22_is1_iext BIT3 // External Interrupt. When set to 1 an interrupt occurred on one of the GPIO’s if it is programmed so. The status can be checked in register 0Eh. See GPIOx Configuration section for the details.
#define RFM22_is1_iext BIT3 // External Interrupt. When set to 1 an interrupt occurred on one of the GPIO<EFBFBD>s if it is programmed so. The status can be checked in register 0Eh. See GPIOx Configuration section for the details.
#define RFM22_is1_irxffafull BIT4 // RX FIFO Almost Full.When set to 1 the RX FIFO has met its almost full threshold and needs to be read by the microcontroller.
#define RFM22_is1_ixtffaem BIT5 // TX FIFO Almost Empty. When set to 1 the TX FIFO is almost empty and needs to be filled.
#define RFM22_is1_itxffafull BIT6 // TX FIFO Almost Full. When set to 1 the TX FIFO has met its almost full threshold and needs to be transmitted.
@ -123,7 +123,7 @@ extern const struct pios_com_driver pios_rfm22b_com_driver;
#define RFM22_opfc1_xton 0x01 // READY Mode (Xtal is ON).
#define RFM22_opfc1_pllon 0x02 // TUNE Mode (PLL is ON). When pllon = 1 the PLL will remain enabled in Idle State. This will for faster turn-around time at the cost of increased current consumption in Idle State.
#define RFM22_opfc1_rxon 0x04 // RX on in Manual Receiver Mode. Automatically cleared if Multiple Packets config. is disabled and a valid packet received.
#define RFM22_opfc1_txon 0x08 // TX on in Manual Transmit Mode. Automatically cleared in FIFO mode once the packet is sent. Transmission can be aborted during packet transmission, however, when no data has been sent yet, transmission can only be aborted after the device is programmed to “unmodulated carrier” ("Register 71h. Modulation Mode Control 2").
#define RFM22_opfc1_txon 0x08 // TX on in Manual Transmit Mode. Automatically cleared in FIFO mode once the packet is sent. Transmission can be aborted during packet transmission, however, when no data has been sent yet, transmission can only be aborted after the device is programmed to <EFBFBD>unmodulated carrier<65> ("Register 71h. Modulation Mode Control 2").
#define RFM22_opfc1_x32ksel 0x10 // 32,768 kHz Crystal Oscillator Select. 0: RC oscillator 1: 32 kHz crystal
#define RFM22_opfc1_enwt 0x20 // Enable Wake-Up-Timer. Enabled when enwt = 1. If the Wake-up-Timer function is enabled it will operate in any mode and notify the microcontroller through the GPIO interrupt when the timer expires.
#define RFM22_opfc1_enlbd 0x40 // Enable Low Battery Detect. When this bit is set to 1 the Low Battery Detector circuit and threshold comparison will be enabled.
@ -303,8 +303,8 @@ extern const struct pios_com_driver pios_rfm22b_com_driver;
#define RFM22_temp_sensor_calib 0x12 // R/W
#define RFM22_tsc_tstrim_mask 0x0F // Temperature Sensor Trim Value.
#define RFM22_tsc_entstrim 0x10 // Temperature Sensor Trim Enable.
#define RFM22_tsc_entsoffs 0x20 // Temperature Sensor Offset to Convert from K to ºC.
#define RFM22_tsc_tsrange0 0x00 // Temperature Sensor Range Selection. –64C to +64C 0.5C resolution
#define RFM22_tsc_entsoffs 0x20 // Temperature Sensor Offset to Convert from K to <EFBFBD>C.
#define RFM22_tsc_tsrange0 0x00 // Temperature Sensor Range Selection. <EFBFBD>64C to +64C 0.5C resolution
#define RFM22_tsc_tsrange1 0x40 // -40 to +85C with 1.0C resolution
#define RFM22_tsc_tsrange2 0x80 // 0C to 85C with 0.5C resolution
#define RFM22_tsc_tsrange3 0xC0 // -40F to 216F with 1.0F resolution
@ -350,7 +350,7 @@ extern const struct pios_com_driver pios_rfm22b_com_driver;
#define RFM22_antenna_diversity_register1 0x28 // R
#define RFM22_antenna_diversity_register2 0x29 // R
#define RFM22_afc_limiter 0x2A // R/W .. AFC_pull_in_range = ±AFCLimiter[7:0] x (hbsel+1) x 625 Hz
#define RFM22_afc_limiter 0x2A // R/W .. AFC_pull_in_range = <EFBFBD>AFCLimiter[7:0] x (hbsel+1) x 625 Hz
#define RFM22_afc_correction_read 0x2B // R
@ -365,11 +365,11 @@ extern const struct pios_com_driver pios_rfm22b_com_driver;
#define RFM22_dac_crc_iec16 0x02 //
#define RFM22_dac_crc_biacheva 0x03 //
#define RFM22_dac_encrc 0x04 // CRC Enable. Cyclic Redundancy Check generation is enabled if this bit is set.
#define RFM22_dac_enpactx 0x08 // Enable Packet TX Handling. If FIFO Mode (dtmod = 10) is being used automatic packet handling may be enabled. Setting enpactx = 1 will enable automatic packet handling in the TX path. Register 30–4D allow for various configurations of the packet structure. Setting enpactx = 0 will not do any packet handling in the TX path. It will only transmit what is loaded to the FIFO.
#define RFM22_dac_enpactx 0x08 // Enable Packet TX Handling. If FIFO Mode (dtmod = 10) is being used automatic packet handling may be enabled. Setting enpactx = 1 will enable automatic packet handling in the TX path. Register 30<EFBFBD>4D allow for various configurations of the packet structure. Setting enpactx = 0 will not do any packet handling in the TX path. It will only transmit what is loaded to the FIFO.
#define RFM22_dac_skip2ph 0x10 // Skip 2nd Phase of Preamble Detection. If set, we skip the second phase of the preamble detection (under certain conditions) if antenna diversity is enabled.
#define RFM22_dac_crcdonly 0x20 // CRC Data Only Enable. When this bit is set to 1 the CRC is calculated on and checked against the packet data fields only.
#define RFM22_dac_lsbfrst 0x40 // LSB First Enable. The LSB of the data will be transmitted/received first if this bit is set.
#define RFM22_dac_enpacrx 0x80 // Enable Packet RX Handling. If FIFO Mode (dtmod = 10) is being used automatic packet handling may be enabled. Setting enpacrx = 1 will enable automatic packet handling in the RX path. Register 30–4D allow for various configurations of the packet structure. Setting enpacrx = 0 will not do any packet handling in the RX path. It will only receive everything after the sync word and fill up the RX FIFO.
#define RFM22_dac_enpacrx 0x80 // Enable Packet RX Handling. If FIFO Mode (dtmod = 10) is being used automatic packet handling may be enabled. Setting enpacrx = 1 will enable automatic packet handling in the RX path. Register 30<EFBFBD>4D allow for various configurations of the packet structure. Setting enpacrx = 0 will not do any packet handling in the RX path. It will only receive everything after the sync word and fill up the RX FIFO.
#define RFM22_ezmac_status 0x31 // R
#define RFM22_ezmac_status_pksent 0x01 // Packet Sent. A 1 a packet has been sent by the radio. (Same bit as in register 03, but reading it does not reset the IRQ)
@ -378,7 +378,7 @@ extern const struct pios_com_driver pios_rfm22b_com_driver;
#define RFM22_ezmac_status_pkvalid 0x08 // Valid Packet Received. When a 1 a valid packet has been received by the receiver. (Same bit as in register 03, but reading it does not reset the IRQ)
#define RFM22_ezmac_status_pkrx 0x10 // Packet Receiving. When 1 the radio is currently receiving a valid packet.
#define RFM22_ezmac_status_pksrch 0x20 // Packet Searching. When 1 the radio is searching for a valid packet.
#define RFM22_ezmac_status_rxcrc1 0x40 // If high, it indicates the last CRC received is all one’s. May indicated Transmitter underflow in case of CRC error.
#define RFM22_ezmac_status_rxcrc1 0x40 // If high, it indicates the last CRC received is all one<EFBFBD>s. May indicated Transmitter underflow in case of CRC error.
#define RFM22_header_control1 0x32 // R/W
#define RFM22_header_cntl1_bcen_none 0x00 // No broadcast address enable.
@ -580,7 +580,7 @@ typedef bool ( *t_rfm22_RxDataCallback ) (void *data, uint8_t len);
// ************************************
void PIOS_RFM22_EXT_Int(void);
bool PIOS_RFM22_EXT_Int(void);
#endif /* PIOS_RFM22B_PRIV_H */

31
flight/RevoMini/System/pios_board.c
View File

@ -341,10 +341,11 @@ void PIOS_Board_Init(void) {
PIOS_TIM_InitClock(&tim_3_cfg);
PIOS_TIM_InitClock(&tim_4_cfg);
PIOS_TIM_InitClock(&tim_5_cfg);
PIOS_TIM_InitClock(&tim_8_cfg);
PIOS_TIM_InitClock(&tim_9_cfg);
PIOS_TIM_InitClock(&tim_10_cfg);
PIOS_TIM_InitClock(&tim_11_cfg);
PIOS_TIM_InitClock(&tim_12_cfg);
/* IAP System Setup */
PIOS_IAP_Init();
uint16_t boot_count = PIOS_IAP_ReadBootCount();
@ -356,8 +357,8 @@ void PIOS_Board_Init(void) {
HwSettingsSetDefaults(HwSettingsHandle(), 0);
AlarmsSet(SYSTEMALARMS_ALARM_BOOTFAULT, SYSTEMALARMS_ALARM_CRITICAL);
}
//PIOS_IAP_Init();
#if defined(PIOS_INCLUDE_USB)
@ -470,8 +471,26 @@ void PIOS_Board_Init(void) {
PIOS_Board_configure_com(&pios_usart_main_cfg, PIOS_COM_GPS_RX_BUF_LEN, -1, &pios_usart_com_driver, &pios_com_gps_id);
break;
case HWSETTINGS_CC_MAINPORT_SBUS:
// TODO
break;
#if defined(PIOS_INCLUDE_SBUS)
{
uint32_t pios_usart_sbus_id;
if (PIOS_USART_Init(&pios_usart_sbus_id, &pios_usart_sbus_main_cfg)) {
PIOS_Assert(0);
}
uint32_t pios_sbus_id;
if (PIOS_SBus_Init(&pios_sbus_id, &pios_sbus_cfg, &pios_usart_com_driver, pios_usart_sbus_id)) {
PIOS_Assert(0);
}
uint32_t pios_sbus_rcvr_id;
if (PIOS_RCVR_Init(&pios_sbus_rcvr_id, &pios_sbus_rcvr_driver, pios_sbus_id)) {
PIOS_Assert(0);
}
pios_rcvr_group_map[MANUALCONTROLSETTINGS_CHANNELGROUPS_SBUS] = pios_sbus_rcvr_id;
}
#endif
break;
case HWSETTINGS_CC_MAINPORT_DSM2:
case HWSETTINGS_CC_MAINPORT_DSMX10BIT:
case HWSETTINGS_CC_MAINPORT_DSMX11BIT:
@ -618,7 +637,7 @@ void PIOS_Board_Init(void) {
}
pios_rcvr_group_map[MANUALCONTROLSETTINGS_CHANNELGROUPS_GCS] = pios_gcsrcvr_rcvr_id;
#endif /* PIOS_INCLUDE_GCSRCVR */
#ifndef PIOS_DEBUG_ENABLE_DEBUG_PINS
switch (hwsettings_rcvrport) {
case HWSETTINGS_RV_RCVRPORT_DISABLED:

110
flight/board_hw_defs/revomini/board_hw_defs.c
View File

@ -962,17 +962,21 @@ static const struct pios_tim_clock_cfg tim_11_cfg = {
},
};
// Set up timers that only have inputs on APB2
static const TIM_TimeBaseInitTypeDef tim_1_time_base = {
.TIM_Prescaler = (PIOS_PERIPHERAL_APB2_CLOCK / 1000000) - 1,
// Set up timers that only have inputs on APB1
// TIM2,3,4,5,6,7,12,13,14
static const TIM_TimeBaseInitTypeDef tim_apb1_time_base = {
.TIM_Prescaler = (PIOS_PERIPHERAL_APB1_CLOCK / 1000000) - 1,
.TIM_ClockDivision = TIM_CKD_DIV1,
.TIM_CounterMode = TIM_CounterMode_Up,
.TIM_Period = 0xFFFF,
.TIM_RepetitionCounter = 0x0000,
};
// Set up timers that only have inputs on APB2
static const TIM_TimeBaseInitTypeDef tim_4_time_base = {
.TIM_Prescaler = (PIOS_PERIPHERAL_APB1_CLOCK / 1000000) - 1,
// TIM1,8,9,10,11
static const TIM_TimeBaseInitTypeDef tim_apb2_time_base = {
.TIM_Prescaler = (PIOS_PERIPHERAL_APB2_CLOCK / 1000000) - 1,
.TIM_ClockDivision = TIM_CKD_DIV1,
.TIM_CounterMode = TIM_CounterMode_Up,
.TIM_Period = 0xFFFF,
@ -981,7 +985,7 @@ static const TIM_TimeBaseInitTypeDef tim_4_time_base = {
static const struct pios_tim_clock_cfg tim_1_cfg = {
.timer = TIM1,
.time_base_init = &tim_1_time_base,
.time_base_init = &tim_apb2_time_base,
.irq = {
.init = {
.NVIC_IRQChannel = TIM1_CC_IRQn,
@ -994,7 +998,7 @@ static const struct pios_tim_clock_cfg tim_1_cfg = {
static const struct pios_tim_clock_cfg tim_4_cfg = {
.timer = TIM4,
.time_base_init = &tim_4_time_base,
.time_base_init = &tim_apb1_time_base,
.irq = {
.init = {
.NVIC_IRQChannel = TIM4_IRQn,
@ -1004,6 +1008,32 @@ static const struct pios_tim_clock_cfg tim_4_cfg = {
},
},
};
static const struct pios_tim_clock_cfg tim_8_cfg = {
.timer = TIM8,
.time_base_init = &tim_apb2_time_base,
.irq = {
.init = {
.NVIC_IRQChannel = TIM8_CC_IRQn,
.NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_MID,
.NVIC_IRQChannelSubPriority = 0,
.NVIC_IRQChannelCmd = ENABLE,
},
},
};
static const struct pios_tim_clock_cfg tim_12_cfg = {
.timer = TIM12,
.time_base_init = &tim_apb1_time_base,
.irq = {
.init = {
.NVIC_IRQChannel = TIM8_BRK_TIM12_IRQn,
.NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_MID,
.NVIC_IRQChannelSubPriority = 0,
.NVIC_IRQChannelCmd = ENABLE,
},
},
};
/**
* Pios servo configuration structures
@ -1133,50 +1163,50 @@ const struct pios_servo_cfg pios_servo_cfg = {
#include <pios_pwm_priv.h>
static const struct pios_tim_channel pios_tim_rcvrport_all_channels[] = {
{
.timer = TIM1,
.timer = TIM12,
.timer_chan = TIM_Channel_1,
.pin = {
.gpio = GPIOA,
.gpio = GPIOB,
.init = {
.GPIO_Pin = GPIO_Pin_8,
.GPIO_Pin = GPIO_Pin_14,
.GPIO_Speed = GPIO_Speed_2MHz,
.GPIO_Mode = GPIO_Mode_AF,
.GPIO_OType = GPIO_OType_PP,
.GPIO_PuPd = GPIO_PuPd_UP
},
.pin_source = GPIO_PinSource8,
.pin_source = GPIO_PinSource14,
},
.remap = GPIO_AF_TIM1,
.remap = GPIO_AF_TIM12,
},
{
.timer = TIM12,
.timer_chan = TIM_Channel_2,
.pin = {
.gpio = GPIOB,
.init = {
.GPIO_Pin = GPIO_Pin_15,
.GPIO_Speed = GPIO_Speed_2MHz,
.GPIO_Mode = GPIO_Mode_AF,
.GPIO_OType = GPIO_OType_PP,
.GPIO_PuPd = GPIO_PuPd_UP
},
.pin_source = GPIO_PinSource15,
},
.remap = GPIO_AF_TIM12,
},
{
.timer = TIM8,
.timer_chan = TIM_Channel_4,
.timer_chan = TIM_Channel_1,
.pin = {
.gpio = GPIOC,
.init = {
.GPIO_Pin = GPIO_Pin_9,
.GPIO_Pin = GPIO_Pin_6,
.GPIO_Speed = GPIO_Speed_2MHz,
.GPIO_Mode = GPIO_Mode_AF,
.GPIO_OType = GPIO_OType_PP,
.GPIO_PuPd = GPIO_PuPd_UP
},
.pin_source = GPIO_PinSource9,
},
.remap = GPIO_AF_TIM8,
},
{
.timer = TIM8,
.timer_chan = TIM_Channel_3,
.pin = {
.gpio = GPIOC,
.init = {
.GPIO_Pin = GPIO_Pin_8,
.GPIO_Speed = GPIO_Speed_2MHz,
.GPIO_Mode = GPIO_Mode_AF,
.GPIO_OType = GPIO_OType_PP,
.GPIO_PuPd = GPIO_PuPd_UP
},
.pin_source = GPIO_PinSource8,
.pin_source = GPIO_PinSource6,
},
.remap = GPIO_AF_TIM8,
},
@ -1198,35 +1228,35 @@ static const struct pios_tim_channel pios_tim_rcvrport_all_channels[] = {
},
{
.timer = TIM8,
.timer_chan = TIM_Channel_1,
.timer_chan = TIM_Channel_3,
.pin = {
.gpio = GPIOC,
.init = {
.GPIO_Pin = GPIO_Pin_6,
.GPIO_Pin = GPIO_Pin_8,
.GPIO_Speed = GPIO_Speed_2MHz,
.GPIO_Mode = GPIO_Mode_AF,
.GPIO_OType = GPIO_OType_PP,
.GPIO_PuPd = GPIO_PuPd_UP
},
.pin_source = GPIO_PinSource6,
.pin_source = GPIO_PinSource8,
},
.remap = GPIO_AF_TIM8,
},
{
.timer = TIM12,
.timer_chan = TIM_Channel_2,
.timer = TIM8,
.timer_chan = TIM_Channel_4,
.pin = {
.gpio = GPIOB,
.gpio = GPIOC,
.init = {
.GPIO_Pin = GPIO_Pin_15,
.GPIO_Pin = GPIO_Pin_9,
.GPIO_Speed = GPIO_Speed_2MHz,
.GPIO_Mode = GPIO_Mode_AF,
.GPIO_OType = GPIO_OType_PP,
.GPIO_PuPd = GPIO_PuPd_UP
},
.pin_source = GPIO_PinSource15,
.pin_source = GPIO_PinSource9,
},
.remap = GPIO_AF_TIM12,
.remap = GPIO_AF_TIM8,
},
};