1
0
mirror of https://bitbucket.org/librepilot/librepilot.git synced 2025-01-29 14:52:12 +01:00

For PIOS_SPI F4 do not enable the TX irq. Also do not wait for the

transmission to finish either.
This commit is contained in:
James Cotton 2012-02-02 11:23:59 -06:00
parent 8b1137c6a0
commit 77a6abb341

View File

@ -184,7 +184,6 @@ int32_t PIOS_SPI_Init(uint32_t * spi_id, const struct pios_spi_cfg * cfg)
/* Configure DMA interrupt */
NVIC_Init((NVIC_InitTypeDef*)&(spi_dev->cfg->dma.irq.init));
// DMA_ITConfig(spi_dev->cfg->dma.tx.channel, spi_dev->cfg->dma.irq.flags, ENABLE); /* XXX is this correct? */
return(0);
@ -630,12 +629,6 @@ void PIOS_SPI_IRQ_Handler(uint32_t spi_id)
/* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
while (!(SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_TXE))) ;
/* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
while (SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_BSY)) ;
} else {
/* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
while (!(SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_TXE))) ;
/* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
while (SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_BSY)) ;
}