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https://bitbucket.org/librepilot/librepilot.git
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d928676f5e
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1121 ebee16cc-31ac-478f-84a7-5cbb03baadba
456 lines
15 KiB
C
456 lines
15 KiB
C
/**
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******************************************************************************
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* @addtogroup PIOS PIOS Core hardware abstraction layer
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* @{
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* @addtogroup PIOS_SPI SPI Functions
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* @brief PIOS interface to read and write from SPI ports
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* @{
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*
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* @file pios_spi.c
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* @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2010.
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* Parts by Thorsten Klose (tk@midibox.org) (tk@midibox.org)
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* @brief Hardware Abstraction Layer for SPI ports of STM32
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* @see The GNU Public License (GPL) Version 3
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* @notes
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*
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* Note that additional chip select lines can be easily added by using
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* the remaining free GPIOs of the core module. Shared SPI ports should be
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* arbitrated with (FreeRTOS based) Mutexes to avoid collisions!
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*
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*****************************************************************************/
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <pios.h>
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#if defined(PIOS_INCLUDE_SPI)
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#include <pios_spi_priv.h>
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static struct pios_spi_dev * find_spi_dev_by_id (uint8_t spi)
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{
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if (spi >= pios_spi_num_devices) {
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/* Undefined SPI port for this board (see pios_board.c) */
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return NULL;
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}
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/* Get a handle for the device configuration */
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return &(pios_spi_devs[spi]);
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}
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/**
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* Initialises SPI pins
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* \param[in] mode currently only mode 0 supported
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* \return < 0 if initialisation failed
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*/
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int32_t PIOS_SPI_Init(void)
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{
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struct pios_spi_dev * spi_dev;
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uint8_t i;
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for (i = 0; i < pios_spi_num_devices; i++) {
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/* Get a handle for the device configuration */
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spi_dev = find_spi_dev_by_id(i);
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PIOS_DEBUG_Assert(spi_dev);
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/* Disable callback function */
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spi_dev->callback = NULL;
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/* Set rx/tx dummy bytes to a known value */
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spi_dev->rx_dummy_byte = 0xFF;
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spi_dev->tx_dummy_byte = 0xFF;
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switch (spi_dev->cfg->init.SPI_NSS) {
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case SPI_NSS_Soft:
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if (spi_dev->cfg->init.SPI_Mode == SPI_Mode_Master) {
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/* We're a master in soft NSS mode, make sure we see NSS high at all times. */
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SPI_NSSInternalSoftwareConfig(spi_dev->cfg->regs, SPI_NSSInternalSoft_Set);
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/* Since we're driving the SSEL pin in software, ensure that the slave is deselected */
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GPIO_SetBits(spi_dev->cfg->ssel.gpio, spi_dev->cfg->ssel.init.GPIO_Pin);
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GPIO_Init(spi_dev->cfg->ssel.gpio, &(spi_dev->cfg->ssel.init));
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} else {
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/* We're a slave in soft NSS mode, make sure we see NSS low at all times. */
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SPI_NSSInternalSoftwareConfig(spi_dev->cfg->regs, SPI_NSSInternalSoft_Reset);
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}
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break;
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case SPI_NSS_Hard:
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/* FIXME: Should this also call SPI_SSOutputCmd()? */
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GPIO_Init(spi_dev->cfg->ssel.gpio, &(spi_dev->cfg->ssel.init));
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break;
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default:
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PIOS_DEBUG_Assert(0);
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}
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/* Initialize the GPIO pins */
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GPIO_Init(spi_dev->cfg->sclk.gpio, &(spi_dev->cfg->sclk.init));
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GPIO_Init(spi_dev->cfg->mosi.gpio, &(spi_dev->cfg->mosi.init));
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GPIO_Init(spi_dev->cfg->miso.gpio, &(spi_dev->cfg->miso.init));
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/* Enable the associated peripheral clock */
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switch ((uint32_t)spi_dev->cfg->regs) {
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case (uint32_t)SPI1:
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/* Enable SPI peripheral clock (APB2 == high speed) */
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
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break;
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case (uint32_t)SPI2:
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/* Enable SPI peripheral clock (APB1 == slow speed) */
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
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break;
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case (uint32_t)SPI3:
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/* Enable SPI peripheral clock (APB1 == slow speed) */
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);
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break;
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}
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/* Enable DMA clock */
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RCC_AHBPeriphClockCmd(spi_dev->cfg->dma.ahb_clk, ENABLE);
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/* Configure DMA for SPI Rx */
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DMA_Cmd(spi_dev->cfg->dma.rx.channel, DISABLE);
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DMA_Init(spi_dev->cfg->dma.rx.channel, &(spi_dev->cfg->dma.rx.init));
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/* Configure DMA for SPI Tx */
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DMA_Cmd(spi_dev->cfg->dma.tx.channel, DISABLE);
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DMA_Init(spi_dev->cfg->dma.tx.channel, &(spi_dev->cfg->dma.tx.init));
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/* Initialize the SPI block */
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SPI_Init(spi_dev->cfg->regs, &(spi_dev->cfg->init));
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/* Configure CRC calculation */
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if (spi_dev->cfg->use_crc) {
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SPI_CalculateCRC(spi_dev->cfg->regs, ENABLE);
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} else {
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SPI_CalculateCRC(spi_dev->cfg->regs, DISABLE);
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}
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/* Enable SPI */
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SPI_Cmd(spi_dev->cfg->regs, ENABLE);
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/* Enable SPI interrupts to DMA */
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SPI_I2S_DMACmd(spi_dev->cfg->regs, SPI_I2S_DMAReq_Tx | SPI_I2S_DMAReq_Rx, ENABLE);
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/* Configure DMA interrupt */
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NVIC_Init(&(spi_dev->cfg->dma.irq.init));
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}
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return 0;
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}
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/**
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* (Re-)initialises SPI peripheral clock rate
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*
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* \param[in] spi SPI number (0 or 1)
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* \param[in] spi_prescaler configures the SPI speed:
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* <UL>
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* <LI>PIOS_SPI_PRESCALER_2: sets clock rate 27.7~ nS @ 72 MHz (36 MBit/s) (only supported for spi==0, spi1 uses 4 instead)
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* <LI>PIOS_SPI_PRESCALER_4: sets clock rate 55.5~ nS @ 72 MHz (18 MBit/s)
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* <LI>PIOS_SPI_PRESCALER_8: sets clock rate 111.1~ nS @ 72 MHz (9 MBit/s)
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* <LI>PIOS_SPI_PRESCALER_16: sets clock rate 222.2~ nS @ 72 MHz (4.5 MBit/s)
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* <LI>PIOS_SPI_PRESCALER_32: sets clock rate 444.4~ nS @ 72 MHz (2.25 MBit/s)
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* <LI>PIOS_SPI_PRESCALER_64: sets clock rate 888.8~ nS @ 72 MHz (1.125 MBit/s)
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* <LI>PIOS_SPI_PRESCALER_128: sets clock rate 1.7~ nS @ 72 MHz (0.562 MBit/s)
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* <LI>PIOS_SPI_PRESCALER_256: sets clock rate 3.5~ nS @ 72 MHz (0.281 MBit/s)
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* </UL>
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* \return 0 if no error
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* \return -1 if disabled SPI port selected
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* \return -2 if unsupported SPI port selected
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* \return -3 if invalid spi_prescaler selected
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*/
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int32_t PIOS_SPI_SetClockSpeed(uint8_t spi, SPIPrescalerTypeDef spi_prescaler)
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{
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struct pios_spi_dev * spi_dev;
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SPI_InitTypeDef SPI_InitStructure;
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/* Get a handle for the device configuration */
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spi_dev = find_spi_dev_by_id(spi);
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if (!spi_dev) {
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/* Undefined SPI port for this board (see pios_board.c) */
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return -2;
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}
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if(spi_prescaler >= 8) {
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/* Invalid prescaler selected */
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return -3;
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}
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/* Start with a copy of the default configuration for the peripheral */
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SPI_InitStructure = spi_dev->cfg->init;
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/* Adjust the prescaler for the peripheral's clock */
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SPI_InitStructure.SPI_BaudRatePrescaler = ((uint16_t)spi_prescaler & 7) << 3;
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/* Write back the new configuration */
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SPI_Init(spi_dev->cfg->regs, &SPI_InitStructure);
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PIOS_SPI_TransferByte(spi, 0xFF);
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return 0;
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}
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/**
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* Controls the RC (Register Clock alias Chip Select) pin of a SPI port
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* \param[in] spi SPI number (0 or 1)
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* \param[in] pin_value 0 or 1
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* \return 0 if no error
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* \return -1 if disabled SPI port selected
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* \return -2 if unsupported SPI port selected
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*/
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int32_t PIOS_SPI_RC_PinSet(uint8_t spi, uint8_t pin_value)
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{
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struct pios_spi_dev * spi_dev;
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/* Get a handle for the device configuration */
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spi_dev = find_spi_dev_by_id(spi);
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if (!spi_dev) {
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/* Undefined SPI port for this board (see pios_board.c) */
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return -2;
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}
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if (pin_value) {
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GPIO_SetBits(spi_dev->cfg->ssel.gpio, spi_dev->cfg->ssel.init.GPIO_Pin);
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} else {
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GPIO_ResetBits(spi_dev->cfg->ssel.gpio, spi_dev->cfg->ssel.init.GPIO_Pin);
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}
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return 0;
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}
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/**
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* Transfers a byte to SPI output and reads back the return value from SPI input
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* \param[in] spi SPI number (0 or 1)
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* \param[in] b the byte which should be transfered
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*/
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int32_t PIOS_SPI_TransferByte(uint8_t spi, uint8_t b)
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{
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struct pios_spi_dev * spi_dev;
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uint8_t dummy;
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uint8_t rx_byte;
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/* Get a handle for the device configuration */
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spi_dev = find_spi_dev_by_id(spi);
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PIOS_DEBUG_Assert(spi_dev);
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/*
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* Procedure taken from STM32F10xxx Reference Manual section 23.3.5
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*/
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/* Make sure the RXNE flag is cleared by reading the DR register */
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dummy = spi_dev->cfg->regs->DR;
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/* Start the transfer */
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spi_dev->cfg->regs->DR = b;
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/* Wait until there is a byte to read */
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while(!(spi_dev->cfg->regs->SR & SPI_I2S_FLAG_RXNE));
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/* Read the rx'd byte */
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rx_byte = spi_dev->cfg->regs->DR;
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/* Wait until the TXE goes high */
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while (!(spi_dev->cfg->regs->SR & SPI_I2S_FLAG_TXE));
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/* Wait for SPI transfer to have fully completed */
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while (spi_dev->cfg->regs->SR & SPI_I2S_FLAG_BSY);
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/* Return received byte */
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return rx_byte;
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}
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/**
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* Transfers a block of bytes via DMA.
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* \param[in] spi SPI number (0 or 1)
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* \param[in] send_buffer pointer to buffer which should be sent.<BR>
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* If NULL, 0xff (all-one) will be sent.
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* \param[in] receive_buffer pointer to buffer which should get the received values.<BR>
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* If NULL, received bytes will be discarded.
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* \param[in] len number of bytes which should be transfered
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* \param[in] callback pointer to callback function which will be executed
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* from DMA channel interrupt once the transfer is finished.
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* If NULL, no callback function will be used, and PIOS_SPI_TransferBlock() will
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* block until the transfer is finished.
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* \return >= 0 if no error during transfer
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* \return -1 if disabled SPI port selected
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* \return -2 if unsupported SPI port selected
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* \return -3 if function has been called during an ongoing DMA transfer
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*/
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int32_t PIOS_SPI_TransferBlock(uint8_t spi, const uint8_t *send_buffer, uint8_t *receive_buffer, uint16_t len, void *callback)
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{
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struct pios_spi_dev * spi_dev;
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DMA_InitTypeDef dma_init;
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/* Get a handle for the device configuration */
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spi_dev = find_spi_dev_by_id(spi);
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if (!spi_dev) {
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/* Undefined SPI port for this board (see pios_board.c) */
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return -2;
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}
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/* Exit if ongoing transfer */
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if (DMA_GetCurrDataCounter(spi_dev->cfg->dma.rx.channel)) {
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return -3;
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}
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/* Disable the SPI peripheral */
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SPI_Cmd(spi_dev->cfg->regs, DISABLE);
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/* Disable the DMA channels */
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DMA_Cmd(spi_dev->cfg->dma.rx.channel, DISABLE);
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DMA_Cmd(spi_dev->cfg->dma.tx.channel, DISABLE);
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/* Set callback function */
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spi_dev->callback = callback;
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/*
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* Configure Rx channel
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*/
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/* Start with the default configuration for this peripheral */
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dma_init = spi_dev->cfg->dma.rx.init;
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if(receive_buffer != NULL) {
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/* Enable memory addr. increment - bytes written into receive buffer */
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dma_init.DMA_MemoryBaseAddr = (uint32_t)receive_buffer;
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dma_init.DMA_MemoryInc = DMA_MemoryInc_Enable;
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} else {
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/* Disable memory addr. increment - bytes written into dummy buffer */
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spi_dev->rx_dummy_byte = 0xFF;
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dma_init.DMA_MemoryBaseAddr = (uint32_t)&spi_dev->rx_dummy_byte;
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dma_init.DMA_MemoryInc = DMA_MemoryInc_Disable;
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}
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if (spi_dev->cfg->use_crc) {
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/* Make sure the CRC error flag is cleared before we start */
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SPI_I2S_ClearFlag(spi_dev->cfg->regs, SPI_FLAG_CRCERR);
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}
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dma_init.DMA_BufferSize = len;
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DMA_Init(spi_dev->cfg->dma.rx.channel, &(dma_init));
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/*
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* Configure Tx channel
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*/
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/* Start with the default configuration for this peripheral */
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dma_init = spi_dev->cfg->dma.tx.init;
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if(send_buffer != NULL) {
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/* Enable memory addr. increment - bytes written into receive buffer */
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dma_init.DMA_MemoryBaseAddr = (uint32_t)send_buffer;
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dma_init.DMA_MemoryInc = DMA_MemoryInc_Enable;
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} else {
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/* Disable memory addr. increment - bytes written into dummy buffer */
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spi_dev->tx_dummy_byte = 0xFF;
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dma_init.DMA_MemoryBaseAddr = (uint32_t)&spi_dev->tx_dummy_byte;
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dma_init.DMA_MemoryInc = DMA_MemoryInc_Disable;
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}
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if (spi_dev->cfg->use_crc) {
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/* The last byte of the payload will be replaced with the CRC8 */
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dma_init.DMA_BufferSize = len - 1;
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} else {
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dma_init.DMA_BufferSize = len;
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}
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DMA_Init(spi_dev->cfg->dma.tx.channel, &(dma_init));
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/* Enable DMA interrupt if callback function active */
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DMA_ITConfig(spi_dev->cfg->dma.rx.channel, DMA_IT_TC, (callback != NULL) ? ENABLE : DISABLE);
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/* Flush out the CRC registers */
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SPI_CalculateCRC(spi_dev->cfg->regs, DISABLE);
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(void) SPI_GetCRC(spi_dev->cfg->regs, SPI_CRC_Rx);
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SPI_I2S_ClearFlag(spi_dev->cfg->regs, SPI_FLAG_CRCERR);
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/* Make sure to flush out the receive buffer */
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(void) SPI_I2S_ReceiveData(spi_dev->cfg->regs);
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if (spi_dev->cfg->use_crc) {
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/* Need a 0->1 transition to reset the CRC logic */
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SPI_CalculateCRC(spi_dev->cfg->regs, ENABLE);
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}
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/* Start DMA transfers */
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DMA_Cmd(spi_dev->cfg->dma.rx.channel, ENABLE);
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DMA_Cmd(spi_dev->cfg->dma.tx.channel, ENABLE);
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/* Reenable the SPI device */
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SPI_Cmd(spi_dev->cfg->regs, ENABLE);
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if (callback) {
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/* User has requested a callback, don't wait for the transfer to complete. */
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return 0;
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}
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/* Wait until all bytes have been transmitted/received */
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while(DMA_GetCurrDataCounter(spi_dev->cfg->dma.rx.channel));
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/* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
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while(!(SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_TXE)));
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/* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
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while(SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_BSY));
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/* Check the CRC on the transfer if enabled. */
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if (spi_dev->cfg->use_crc) {
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/* Check the SPI CRC error flag */
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if (SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_FLAG_CRCERR)) {
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return -4;
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}
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}
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/* No error */
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return 0;
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}
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void PIOS_SPI_IRQ_Handler(uint8_t spi)
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{
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struct pios_spi_dev * spi_dev;
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spi_dev = find_spi_dev_by_id (spi);
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PIOS_DEBUG_Assert(spi_dev);
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DMA_ClearFlag(spi_dev->cfg->dma.irq.flags);
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/* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
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while(!(SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_TXE)));
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/* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
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while(SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_BSY));
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if(spi_dev->callback != NULL) {
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bool crc_ok = TRUE;
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uint8_t crc_val;
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if (SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_FLAG_CRCERR)) {
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crc_ok = FALSE;
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SPI_I2S_ClearFlag(spi_dev->cfg->regs, SPI_FLAG_CRCERR);
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}
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crc_val = SPI_GetCRC(spi_dev->cfg->regs, SPI_CRC_Rx);
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spi_dev->callback(crc_ok, crc_val);
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}
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}
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#endif
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/**
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* @}
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* @}
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*/
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