mirror of
https://bitbucket.org/librepilot/librepilot.git
synced 2024-11-30 08:24:11 +01:00
357 lines
12 KiB
Plaintext
357 lines
12 KiB
Plaintext
/* This is the size of the stack for early init and for all FreeRTOS IRQs */
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_irq_stack_size = 0x800;
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/* Check valid alignment for VTOR */
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ASSERT(ORIGIN(BL_FLASH) == ALIGN(ORIGIN(BL_FLASH), 0x80), "Start of memory region flash not aligned for startup vector table");
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/*
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this sends all unreferenced IRQHandlers to reset
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*/
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PROVIDE ( Undefined_Handler = 0 ) ;
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PROVIDE ( SWI_Handler = 0 ) ;
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PROVIDE ( IRQ_Handler = 0 ) ;
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PROVIDE ( Prefetch_Handler = 0 ) ;
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PROVIDE ( Abort_Handler = 0 ) ;
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PROVIDE ( FIQ_Handler = 0 ) ;
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PROVIDE ( NMI_Handler = 0 ) ;
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PROVIDE ( HardFault_Handler = 0 ) ;
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PROVIDE ( MemManage_Handler = 0 ) ;
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PROVIDE ( BusFault_Handler = 0 ) ;
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PROVIDE ( UsageFault_Handler = 0 ) ;
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PROVIDE ( vPortSVCHandler = 0 ) ;
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PROVIDE ( DebugMon_Handler = 0 ) ;
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PROVIDE ( xPortPendSVHandler = 0 ) ;
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PROVIDE ( xPortSysTickHandler = 0 ) ;
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PROVIDE ( WWDG_IRQHandler = 0 ) ;
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PROVIDE ( PVD_IRQHandler = 0 ) ;
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PROVIDE ( TAMPER_IRQHandler = 0 ) ;
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PROVIDE ( RTC_IRQHandler = 0 ) ;
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PROVIDE ( FLASH_IRQHandler = 0 ) ;
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PROVIDE ( RCC_IRQHandler = 0 ) ;
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PROVIDE ( EXTI0_IRQHandler = 0 ) ;
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PROVIDE ( EXTI1_IRQHandler = 0 ) ;
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PROVIDE ( EXTI2_IRQHandler = 0 ) ;
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PROVIDE ( EXTI3_IRQHandler = 0 ) ;
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PROVIDE ( EXTI4_IRQHandler = 0 ) ;
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PROVIDE ( DMAChannel1_IRQHandler = 0 ) ;
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PROVIDE ( DMAChannel2_IRQHandler = 0 ) ;
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PROVIDE ( DMAChannel3_IRQHandler = 0 ) ;
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PROVIDE ( DMAChannel4_IRQHandler = 0 ) ;
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PROVIDE ( DMAChannel5_IRQHandler = 0 ) ;
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PROVIDE ( DMAChannel6_IRQHandler = 0 ) ;
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PROVIDE ( DMAChannel7_IRQHandler = 0 ) ;
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PROVIDE ( ADC_IRQHandler = 0 ) ;
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PROVIDE ( USB_HP_CAN1_TX_IRQHandler = 0 ) ;
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PROVIDE ( USB_LP_CAN1_RX0_IRQHandler = 0 ) ;
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PROVIDE ( CAN1_RX1_IRQHandler = 0 ) ;
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PROVIDE ( CAN1_SCE_IRQHandler = 0 ) ;
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PROVIDE ( EXTI9_5_IRQHandler = 0 ) ;
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PROVIDE ( TIM1_BRK_IRQHandler = 0 ) ;
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PROVIDE ( TIM1_UP_IRQHandler = 0 ) ;
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PROVIDE ( TIM1_TRG_COM_IRQHandler = 0 ) ;
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PROVIDE ( TIM1_CC_IRQHandler = 0 ) ;
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PROVIDE ( TIM2_IRQHandler = 0 ) ;
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PROVIDE ( TIM3_IRQHandler = 0 ) ;
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PROVIDE ( TIM4_IRQHandler = 0 ) ;
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PROVIDE ( I2C1_EV_IRQHandler = 0 ) ;
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PROVIDE ( I2C1_ER_IRQHandler = 0 ) ;
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PROVIDE ( I2C2_EV_IRQHandler = 0 ) ;
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PROVIDE ( I2C2_ER_IRQHandler = 0 ) ;
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PROVIDE ( SPI1_IRQHandler = 0 ) ;
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PROVIDE ( SPI2_IRQHandler = 0 ) ;
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PROVIDE ( USART1_IRQHandler = 0 ) ;
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PROVIDE ( USART2_IRQHandler = 0 ) ;
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PROVIDE ( USART3_IRQHandler = 0 ) ;
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PROVIDE ( EXTI15_10_IRQHandler = 0 ) ;
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PROVIDE ( RTCAlarm_IRQHandler = 0 ) ;
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PROVIDE ( USBWakeUp_IRQHandler = 0 ) ;
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PROVIDE ( TIM8_BRK_IRQHandler = 0 ) ;
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PROVIDE ( TIM8_UP_IRQHandler = 0 ) ;
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PROVIDE ( TIM8_TRG_COM_IRQHandler = 0 ) ;
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PROVIDE ( TIM8_CC_IRQHandler = 0 ) ;
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PROVIDE ( ADC3_IRQHandler = 0 ) ;
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PROVIDE ( FSMC_IRQHandler = 0 ) ;
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PROVIDE ( SDIO_IRQHandler = 0 ) ;
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PROVIDE ( TIM5_IRQHandler = 0 ) ;
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PROVIDE ( SPI3_IRQHandler = 0 ) ;
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PROVIDE ( UART4_IRQHandler = 0 ) ;
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PROVIDE ( UART5_IRQHandler = 0 ) ;
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PROVIDE ( TIM6_IRQHandler = 0 ) ;
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PROVIDE ( TIM7_IRQHandler = 0 ) ;
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PROVIDE ( DMA2_Channel1_IRQHandler = 0 ) ;
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PROVIDE ( DMA2_Channel2_IRQHandler = 0 ) ;
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PROVIDE ( DMA2_Channel3_IRQHandler = 0 ) ;
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PROVIDE ( DMA2_Channel4_5_IRQHandler = 0 ) ;
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/******************************************************************************/
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/* Peripheral memory map */
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/******************************************************************************/
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/*this allows to compile the ST lib in "non-debug" mode*/
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/* Peripheral and SRAM base address in the alias region */
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PERIPH_BB_BASE = 0x42000000;
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SRAM_BB_BASE = 0x22000000;
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/* Peripheral and SRAM base address in the bit-band region */
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SRAM_BASE = 0x20000000;
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PERIPH_BASE = 0x40000000;
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/* Flash registers base address */
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PROVIDE ( FLASH_BASE = 0x40022000);
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/* Flash Option Bytes base address */
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PROVIDE ( OB_BASE = 0x1FFFF800);
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/* Peripheral memory map */
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APB1PERIPH_BASE = PERIPH_BASE ;
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APB2PERIPH_BASE = (PERIPH_BASE + 0x10000) ;
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AHBPERIPH_BASE = (PERIPH_BASE + 0x20000) ;
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PROVIDE ( TIM2 = (APB1PERIPH_BASE + 0x0000) ) ;
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PROVIDE ( TIM3 = (APB1PERIPH_BASE + 0x0400) ) ;
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PROVIDE ( TIM4 = (APB1PERIPH_BASE + 0x0800) ) ;
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PROVIDE ( RTC = (APB1PERIPH_BASE + 0x2800) ) ;
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PROVIDE ( WWDG = (APB1PERIPH_BASE + 0x2C00) ) ;
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PROVIDE ( IWDG = (APB1PERIPH_BASE + 0x3000) ) ;
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PROVIDE ( SPI2 = (APB1PERIPH_BASE + 0x3800) ) ;
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PROVIDE ( USART2 = (APB1PERIPH_BASE + 0x4400) ) ;
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PROVIDE ( USART3 = (APB1PERIPH_BASE + 0x4800) ) ;
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PROVIDE ( I2C1 = (APB1PERIPH_BASE + 0x5400) ) ;
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PROVIDE ( I2C2 = (APB1PERIPH_BASE + 0x5800) ) ;
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PROVIDE ( CAN = (APB1PERIPH_BASE + 0x6400) ) ;
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PROVIDE ( BKP = (APB1PERIPH_BASE + 0x6C00) ) ;
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PROVIDE ( PWR = (APB1PERIPH_BASE + 0x7000) ) ;
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PROVIDE ( AFIO = (APB2PERIPH_BASE + 0x0000) ) ;
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PROVIDE ( EXTI = (APB2PERIPH_BASE + 0x0400) ) ;
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PROVIDE ( GPIOA = (APB2PERIPH_BASE + 0x0800) ) ;
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PROVIDE ( GPIOB = (APB2PERIPH_BASE + 0x0C00) ) ;
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PROVIDE ( GPIOC = (APB2PERIPH_BASE + 0x1000) ) ;
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PROVIDE ( GPIOD = (APB2PERIPH_BASE + 0x1400) ) ;
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PROVIDE ( GPIOE = (APB2PERIPH_BASE + 0x1800) ) ;
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PROVIDE ( ADC1 = (APB2PERIPH_BASE + 0x2400) ) ;
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PROVIDE ( ADC2 = (APB2PERIPH_BASE + 0x2800) ) ;
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PROVIDE ( TIM1 = (APB2PERIPH_BASE + 0x2C00) ) ;
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PROVIDE ( SPI1 = (APB2PERIPH_BASE + 0x3000) ) ;
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PROVIDE ( USART1 = (APB2PERIPH_BASE + 0x3800) ) ;
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PROVIDE ( DMA = (AHBPERIPH_BASE + 0x0000) ) ;
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PROVIDE ( DMA_Channel1 = (AHBPERIPH_BASE + 0x0008) ) ;
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PROVIDE ( DMA_Channel2 = (AHBPERIPH_BASE + 0x001C) ) ;
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PROVIDE ( DMA_Channel3 = (AHBPERIPH_BASE + 0x0030) ) ;
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PROVIDE ( DMA_Channel4 = (AHBPERIPH_BASE + 0x0044) ) ;
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PROVIDE ( DMA_Channel5 = (AHBPERIPH_BASE + 0x0058) ) ;
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PROVIDE ( DMA_Channel6 = (AHBPERIPH_BASE + 0x006C) ) ;
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PROVIDE ( DMA_Channel7 = (AHBPERIPH_BASE + 0x0080) ) ;
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PROVIDE ( RCC = (AHBPERIPH_BASE + 0x1000) ) ;
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/* System Control Space memory map */
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SCS_BASE = 0xE000E000;
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PROVIDE ( SysTick = (SCS_BASE + 0x0010) ) ;
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PROVIDE ( NVIC = (SCS_BASE + 0x0100) ) ;
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PROVIDE ( SCB = (SCS_BASE + 0x0D00) ) ;
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/* Sections Definitions */
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SECTIONS
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{
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/* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */
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.isr_vector :
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{
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PROVIDE (pios_isr_vector_table_base = .);
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KEEP(*(.isr_vector)) /* Startup code */
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. = ALIGN(4);
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} > BL_FLASH
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/* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */
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.flashtext :
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{
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. = ALIGN(4);
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*(.flashtext) /* Startup code */
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. = ALIGN(4);
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} > BL_FLASH
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/* the program code is stored in the .text section, which goes to Flash */
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.text :
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{
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. = ALIGN(4);
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*(.text) /* remaining code */
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*(.text.*) /* remaining code */
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*(.rodata) /* read-only data (constants) */
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*(.rodata*)
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*(.glue_7)
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*(.glue_7t)
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. = ALIGN(4);
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_etext = .;
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/* This is used by the startup in order to initialize the .data secion */
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_sidata = _etext;
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} > BL_FLASH
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/*
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* This stack is used both as the initial sp during early init as well as ultimately
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* being used as the STM32's MSP (Main Stack Pointer) which is the same stack that
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* is used for _all_ interrupt handlers. The end of this stack should be placed
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* against the lowest address in RAM so that a stack overrun results in a hard fault
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* at the first access beyond the end of the stack.
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*/
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.irq_stack :
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{
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. = ALIGN(4);
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_irq_stack_end = . ;
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. = . + _irq_stack_size ;
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. = ALIGN(4);
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_irq_stack_top = . - 4 ;
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_init_stack_top = _irq_stack_top;
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. = ALIGN(4);
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} >RAM
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/* This is the initialized data section
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The program executes knowing that the data is in the RAM
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but the loader puts the initial values in the FLASH (inidata).
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It is one task of the startup to copy the initial values from FLASH to RAM. */
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.data : AT ( _sidata )
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{
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .data secion */
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_sdata = . ;
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*(.data)
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*(.data.*)
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .data secion */
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_edata = . ;
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} >RAM
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/* This is the uninitialized data section */
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.bss :
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{
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .bss secion */
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_sbss = .;
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*(.bss)
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*(COMMON)
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .bss secion */
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_ebss = . ;
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} >RAM
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PROVIDE ( end = _ebss );
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PROVIDE ( _end = _ebss );
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/* this is the FLASH Bank1 */
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/* the C or assembly source must explicitly place the code or data there
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using the "section" attribute */
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.b1text :
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{
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*(.b1text) /* remaining code */
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*(.b1rodata) /* read-only data (constants) */
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*(.b1rodata*)
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} >FLASHB1
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/* this is the EXTMEM */
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/* the C or assembly source must explicitly place the code or data there
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using the "section" attribute */
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/* EXTMEM Bank0 */
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.eb0text :
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{
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*(.eb0text) /* remaining code */
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*(.eb0rodata) /* read-only data (constants) */
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*(.eb0rodata*)
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} >EXTMEMB0
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/* EXTMEM Bank1 */
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.eb1text :
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{
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*(.eb1text) /* remaining code */
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*(.eb1rodata) /* read-only data (constants) */
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*(.eb1rodata*)
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} >EXTMEMB1
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/* EXTMEM Bank2 */
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.eb2text :
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{
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*(.eb2text) /* remaining code */
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*(.eb2rodata) /* read-only data (constants) */
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*(.eb2rodata*)
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} >EXTMEMB2
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/* EXTMEM Bank0 */
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.eb3text :
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{
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*(.eb3text) /* remaining code */
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*(.eb3rodata) /* read-only data (constants) */
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*(.eb3rodata*)
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} >EXTMEMB3
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__exidx_start = .;
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__exidx_end = .;
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.boardinfo :
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{
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. = ALIGN(4);
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KEEP(*(.boardinfo))
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. = ALIGN(4);
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} > BD_INFO
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/* after that it's only debugging information. */
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/* remove the debugging information from the standard libraries */
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/DISCARD/ :
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{
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libc.a ( * )
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libm.a ( * )
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libgcc.a ( * )
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}
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/* Stabs debugging sections. */
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.stab 0 : { *(.stab) }
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.stabstr 0 : { *(.stabstr) }
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.stab.excl 0 : { *(.stab.excl) }
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.stab.exclstr 0 : { *(.stab.exclstr) }
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.stab.index 0 : { *(.stab.index) }
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.stab.indexstr 0 : { *(.stab.indexstr) }
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.comment 0 : { *(.comment) }
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/* DWARF debug sections.
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Symbols in the DWARF debugging sections are relative to the beginning
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of the section so we begin them at 0. */
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/* DWARF 1 */
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.debug 0 : { *(.debug) }
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.line 0 : { *(.line) }
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/* GNU DWARF 1 extensions */
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.debug_srcinfo 0 : { *(.debug_srcinfo) }
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.debug_sfnames 0 : { *(.debug_sfnames) }
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/* DWARF 1.1 and DWARF 2 */
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.debug_aranges 0 : { *(.debug_aranges) }
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.debug_pubnames 0 : { *(.debug_pubnames) }
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/* DWARF 2 */
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.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
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.debug_abbrev 0 : { *(.debug_abbrev) }
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.debug_line 0 : { *(.debug_line) }
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.debug_frame 0 : { *(.debug_frame) }
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.debug_str 0 : { *(.debug_str) }
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.debug_loc 0 : { *(.debug_loc) }
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.debug_macinfo 0 : { *(.debug_macinfo) }
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/* SGI/MIPS DWARF 2 extensions */
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.debug_weaknames 0 : { *(.debug_weaknames) }
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.debug_funcnames 0 : { *(.debug_funcnames) }
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.debug_typenames 0 : { *(.debug_typenames) }
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.debug_varnames 0 : { *(.debug_varnames) }
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}
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