2019-04-14 15:43:27 +02:00
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/*
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* Copyright © 2014 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef VC4_QPU_DEFINES_H
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#define VC4_QPU_DEFINES_H
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#include <assert.h>
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#include <stdint.h>
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2020-04-17 21:59:04 +02:00
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#include "vc4_qpu_enums.h"
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2019-04-14 15:43:27 +02:00
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static const char *qpu_cond_str[] = {
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[QPU_COND_NEVER] = "never",
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[QPU_COND_ALWAYS] = "always",
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[QPU_COND_ZS] = "zs",
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[QPU_COND_ZC] = "zc",
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[QPU_COND_NS] = "ns",
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[QPU_COND_NC] = "nc",
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[QPU_COND_CS] = "cs",
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[QPU_COND_CC] = "cc",
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};
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static const char *qpu_mux_str[] = {
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[QPU_MUX_R0] = "r0",
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[QPU_MUX_R1] = "r1",
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[QPU_MUX_R2] = "r2",
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[QPU_MUX_R3] = "r3",
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[QPU_MUX_R4] = "r4",
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[QPU_MUX_R5] = "r5",
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[QPU_MUX_A] = "a",
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[QPU_MUX_B] = "b",
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};
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static const char *qpu_sig_bits_str[] = {
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[QPU_SIG_SW_BREAKPOINT] = "sig_brk",
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[QPU_SIG_NONE] = "sig_none",
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2019-09-20 12:04:58 +02:00
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[QPU_SIG_THREAD_SWITCH] = "sig_thread_switch",
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2019-04-14 15:43:27 +02:00
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[QPU_SIG_PROG_END] = "sig_end",
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[QPU_SIG_WAIT_FOR_SCOREBOARD] = "sig_wait_score",
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[QPU_SIG_SCOREBOARD_UNLOCK] = "sig_unlock_score",
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2019-09-20 12:04:58 +02:00
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[QPU_SIG_LAST_THREAD_SWITCH] = "sig_last_thread_switch",
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2019-04-14 15:43:27 +02:00
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[QPU_SIG_COVERAGE_LOAD] = "sig_coverage_load",
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[QPU_SIG_COLOR_LOAD] = "sig_color_load",
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[QPU_SIG_COLOR_LOAD_END] = "sig_color_load_end",
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[QPU_SIG_LOAD_TMU0] = "sig_load_tmu0",
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[QPU_SIG_LOAD_TMU1] = "sig_load_tmu1",
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[QPU_SIG_ALPHA_MASK_LOAD] = "sig_alpha_mask_load",
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[QPU_SIG_SMALL_IMM] = "sig_small_imm",
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[QPU_SIG_LOAD_IMM] = "sig_load_imm",
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[QPU_SIG_BRANCH] = "sig_branch",
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};
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//Small immediate encoding
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//Returns the small immediate value to be encoded in to the raddr b field if
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//the argument can be represented as one, or ~0 otherwise.
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//48: Small immediate value for rotate-by-r5, and 49-63 are "rotate by n channels"
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2019-09-29 20:06:26 +02:00
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static uint8_t qpu_encode_small_immediate(uint32_t i)
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2019-04-14 15:43:27 +02:00
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{
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if (i <= 15)
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return i;
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if ((int)i < 0 && (int)i >= -16)
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return i + 32;
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switch (i) {
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2019-04-21 14:41:25 +02:00
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case 0x3f800000: //1.0
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2019-04-14 15:43:27 +02:00
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return 32;
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2019-04-21 14:41:25 +02:00
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case 0x40000000: //2.0
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2019-04-14 15:43:27 +02:00
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return 33;
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2019-04-21 14:41:25 +02:00
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case 0x40800000: //4.0
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2019-04-14 15:43:27 +02:00
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return 34;
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2019-04-21 14:41:25 +02:00
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case 0x41000000: //8.0
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2019-04-14 15:43:27 +02:00
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return 35;
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2019-04-21 14:41:25 +02:00
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case 0x41800000: //16.0
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2019-04-14 15:43:27 +02:00
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return 36;
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2019-04-21 14:41:25 +02:00
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case 0x42000000: //32.0
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2019-04-14 15:43:27 +02:00
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return 37;
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2019-04-21 14:41:25 +02:00
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case 0x42800000: //64.0
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2019-04-14 15:43:27 +02:00
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return 38;
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2019-04-21 14:41:25 +02:00
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case 0x43000000: //128.0
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2019-04-14 15:43:27 +02:00
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return 39;
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2019-04-21 14:41:25 +02:00
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case 0x3b800000: //1.0/256.0
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2019-04-14 15:43:27 +02:00
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return 40;
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2019-04-21 14:41:25 +02:00
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case 0x3c000000: //1.0/128.0
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2019-04-14 15:43:27 +02:00
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return 41;
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2019-04-21 14:41:25 +02:00
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case 0x3c800000: //1.0/64.0
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2019-04-14 15:43:27 +02:00
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return 42;
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2019-04-21 14:41:25 +02:00
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case 0x3d000000: //1.0/32.0
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2019-04-14 15:43:27 +02:00
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return 43;
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2019-04-21 14:41:25 +02:00
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case 0x3d800000: //1.0/16.0
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2019-04-14 15:43:27 +02:00
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return 44;
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2019-04-21 14:41:25 +02:00
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case 0x3e000000: //1.0/8.0
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2019-04-14 15:43:27 +02:00
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return 45;
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2019-04-21 14:41:25 +02:00
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case 0x3e800000: //1.0/4.0
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2019-04-14 15:43:27 +02:00
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return 46;
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2019-04-21 14:41:25 +02:00
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case 0x3f000000: //1.0/2.0
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2019-04-14 15:43:27 +02:00
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return 47;
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}
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return ~0;
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}
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static const char *qpu_unpack_str[] = {
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[QPU_UNPACK_NOP] = "nop",
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[QPU_UNPACK_16A] = "16a",
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[QPU_UNPACK_16B] = "16b",
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[QPU_UNPACK_8D_REP] = "8d_rep",
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[QPU_UNPACK_8A] = "8a",
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[QPU_UNPACK_8B] = "8b",
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[QPU_UNPACK_8C] = "8c",
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[QPU_UNPACK_8D] = "8d",
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};
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static const char *qpu_pack_a_str[] = {
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[QPU_PACK_A_NOP] = "nop",
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[QPU_PACK_A_16A] = "16a",
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[QPU_PACK_A_16B] = "16b",
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[QPU_PACK_A_8888] = "8888",
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[QPU_PACK_A_8A] = "8a",
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[QPU_PACK_A_8B] = "8b",
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[QPU_PACK_A_8C] = "8c",
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[QPU_PACK_A_8D] = "8d",
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[QPU_PACK_A_32_SAT] = "sat",
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[QPU_PACK_A_16A_SAT] = "16a.sat",
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[QPU_PACK_A_16B_SAT] = "16b.sat",
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[QPU_PACK_A_8888_SAT] = "8888.sat",
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[QPU_PACK_A_8A_SAT] = "8a.sat",
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[QPU_PACK_A_8B_SAT] = "8b.sat",
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[QPU_PACK_A_8C_SAT] = "8c.sat",
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[QPU_PACK_A_8D_SAT] = "8d.sat",
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};
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static const char *qpu_pack_mul_str[] = {
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[QPU_PACK_MUL_NOP] = "nop",
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[QPU_PACK_MUL_8888] = "8888",
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[QPU_PACK_MUL_8A] = "8a",
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[QPU_PACK_MUL_8B] = "8b",
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[QPU_PACK_MUL_8C] = "8c",
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[QPU_PACK_MUL_8D] = "8d",
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};
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static const char *qpu_branch_cond_str[] = {
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[QPU_COND_BRANCH_ALL_ZS] = "all_zs",
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[QPU_COND_BRANCH_ALL_ZC] = "all_zc",
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[QPU_COND_BRANCH_ANY_ZS] = "any_zs",
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[QPU_COND_BRANCH_ANY_ZC] = "any_zc",
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[QPU_COND_BRANCH_ALL_NS] = "all_ns",
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[QPU_COND_BRANCH_ALL_NC] = "all_nc",
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[QPU_COND_BRANCH_ANY_NS] = "any_ns",
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[QPU_COND_BRANCH_ANY_NC] = "any_nc",
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[QPU_COND_BRANCH_ALL_CS] = "all_cs",
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[QPU_COND_BRANCH_ALL_CC] = "all_cc",
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[QPU_COND_BRANCH_ANY_CS] = "any_cs",
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[QPU_COND_BRANCH_ANY_CC] = "any_cc",
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[QPU_COND_BRANCH_ALWAYS] = "always",
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};
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static const char *qpu_op_add_str[] = {
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[QPU_A_NOP] = "nop",
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[QPU_A_FADD] = "fadd",
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[QPU_A_FSUB] = "fsub",
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[QPU_A_FMIN] = "fmin",
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[QPU_A_FMAX] = "fmax",
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[QPU_A_FMINABS] = "fminabs",
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[QPU_A_FMAXABS] = "fmaxabs",
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[QPU_A_FTOI] = "ftoi",
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[QPU_A_ITOF] = "itof",
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[QPU_A_ADD] = "add",
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[QPU_A_SUB] = "sub",
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[QPU_A_SHR] = "shr",
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[QPU_A_ASR] = "asr",
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[QPU_A_ROR] = "ror",
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[QPU_A_SHL] = "shl",
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[QPU_A_MIN] = "min",
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[QPU_A_MAX] = "max",
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[QPU_A_AND] = "and",
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[QPU_A_OR] = "or",
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[QPU_A_XOR] = "xor",
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[QPU_A_NOT] = "not",
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[QPU_A_CLZ] = "clz",
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[QPU_A_V8ADDS] = "v8adds",
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[QPU_A_V8SUBS] = "v8subs",
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};
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static const char *qpu_op_mul_str[] = {
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[QPU_M_NOP] = "nop",
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[QPU_M_FMUL] = "fmul",
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[QPU_M_MUL24] = "mul24",
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[QPU_M_V8MULD] = "v8muld",
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[QPU_M_V8MIN] = "v8min",
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[QPU_M_V8MAX] = "v8max",
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[QPU_M_V8ADDS] = "v8adds",
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[QPU_M_V8SUBS] = "v8subs",
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};
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//read and write ops may mean different things...
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//hence two maps
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static const char *qpu_raddr_str[][52] = {
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{ //A
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2019-04-20 14:55:40 +02:00
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//ra0-31
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[QPU_R_FRAG_PAYLOAD_ZW] = "pay_zw",
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[QPU_R_UNIF] = "uni",
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[QPU_R_VARY] = "vary",
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[QPU_R_ELEM_QPU] = "elem",
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[QPU_R_NOP] = "nop",
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[QPU_R_XY_PIXEL_COORD] = "x_pix",
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[QPU_R_MS_FLAGS] = "ms_flags",
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[QPU_R_VPM] = "vpm_read",
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[QPU_R_VPM_LD_BUSY] = "vpm_ld_busy",
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[QPU_R_VPM_LD_WAIT] = "vpm_ld_wait",
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[QPU_R_MUTEX_ACQUIRE] = "mutex_acq"
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},
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{ //B
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2019-04-20 14:55:40 +02:00
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//rb0-31
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2019-04-14 15:43:27 +02:00
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[QPU_R_FRAG_PAYLOAD_ZW] = "pay_zw",
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[QPU_R_UNIF] = "uni",
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[QPU_R_VARY] = "vary",
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[QPU_R_ELEM_QPU] = "elem",
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[QPU_R_NOP] = "nop",
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[QPU_R_XY_PIXEL_COORD] = "y_pix",
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[QPU_R_REV_FLAG] = "rev_flag",
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[QPU_R_VPM] = "vpm_read",
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[QPU_R_VPM_ST_BUSY] = "vpm_st_busy",
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[QPU_R_VPM_ST_WAIT] = "vpm_st_wait",
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[QPU_R_MUTEX_ACQUIRE] = "mutex_acq"
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}
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};
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static const char *qpu_waddr_str[][64] = {
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{ //A
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2019-04-20 14:21:53 +02:00
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//ra0-31
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2019-04-14 15:43:27 +02:00
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[QPU_W_ACC0] = "r0",
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[QPU_W_ACC1] = "r1",
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[QPU_W_ACC2] = "r2",
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[QPU_W_ACC3] = "r3",
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[QPU_W_TMU_NOSWAP] = "tmu_noswap",
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[QPU_W_ACC5] = "r5",
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[QPU_W_HOST_INT] = "host_int",
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[QPU_W_NOP] = "nop",
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[QPU_W_UNIFORMS_ADDRESS] = "uniforms_addr",
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[QPU_W_QUAD_XY] = "quad_x",
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[QPU_W_MS_FLAGS] = "ms_flags",
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[QPU_W_TLB_STENCIL_SETUP] = "tlb_stencil_setup",
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[QPU_W_TLB_Z] = "tlb_z",
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[QPU_W_TLB_COLOR_MS] = "tlb_color_ms",
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[QPU_W_TLB_COLOR_ALL] = "tlb_color_all",
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[QPU_W_VPM] = "vpm",
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[QPU_W_VPMVCD_SETUP] = "vr_setup",
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[QPU_W_VPM_ADDR] = "vr_addr",
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[QPU_W_MUTEX_RELEASE] = "mutex_release",
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[QPU_W_SFU_RECIP] = "sfu_recip",
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[QPU_W_SFU_RECIPSQRT] = "sfu_recipsqrt",
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[QPU_W_SFU_EXP] = "sfu_exp",
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[QPU_W_SFU_LOG] = "sfu_log",
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[QPU_W_TMU0_S] = "tmu0_s",
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[QPU_W_TMU0_T] = "tmu0_t",
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[QPU_W_TMU0_R] = "tmu0_r",
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[QPU_W_TMU0_B] = "tmu0_b",
|
|
|
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[QPU_W_TMU1_S] = "tmu1_s",
|
|
|
|
[QPU_W_TMU1_T] = "tmu1_t",
|
|
|
|
[QPU_W_TMU1_R] = "tmu1_r",
|
|
|
|
[QPU_W_TMU1_B] = "tmu1_b",
|
|
|
|
},
|
|
|
|
{ //B
|
2019-04-20 14:21:53 +02:00
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|
|
//rb0-31
|
2019-04-14 15:43:27 +02:00
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|
|
[QPU_W_ACC0] = "r0",
|
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[QPU_W_ACC1] = "r1",
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[QPU_W_ACC2] = "r2",
|
|
|
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[QPU_W_ACC3] = "r3",
|
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[QPU_W_TMU_NOSWAP] = "tmu_noswap",
|
|
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[QPU_W_ACC5] = "r5",
|
|
|
|
[QPU_W_HOST_INT] = "host_int",
|
|
|
|
[QPU_W_NOP] = "nop",
|
|
|
|
[QPU_W_UNIFORMS_ADDRESS] = "uniforms_addr",
|
|
|
|
[QPU_W_QUAD_XY] = "quad_y",
|
|
|
|
[QPU_W_REV_FLAG] = "rev_flags",
|
|
|
|
[QPU_W_TLB_STENCIL_SETUP] = "tlb_stencil_setup",
|
|
|
|
[QPU_W_TLB_Z] = "tlb_z",
|
|
|
|
[QPU_W_TLB_COLOR_MS] = "tlb_color_ms",
|
|
|
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[QPU_W_TLB_COLOR_ALL] = "tlb_color_all",
|
|
|
|
[QPU_W_VPM] = "vpm",
|
|
|
|
[QPU_W_VPMVCD_SETUP] = "vw_setup",
|
|
|
|
[QPU_W_VPM_ADDR] = "vw_addr",
|
|
|
|
[QPU_W_MUTEX_RELEASE] = "mutex_release",
|
|
|
|
[QPU_W_SFU_RECIP] = "sfu_recip",
|
|
|
|
[QPU_W_SFU_RECIPSQRT] = "sfu_recipsqrt",
|
|
|
|
[QPU_W_SFU_EXP] = "sfu_exp",
|
|
|
|
[QPU_W_SFU_LOG] = "sfu_log",
|
|
|
|
[QPU_W_TMU0_S] = "tmu0_s",
|
|
|
|
[QPU_W_TMU0_T] = "tmu0_t",
|
|
|
|
[QPU_W_TMU0_R] = "tmu0_r",
|
|
|
|
[QPU_W_TMU0_B] = "tmu0_b",
|
|
|
|
[QPU_W_TMU1_S] = "tmu1_s",
|
|
|
|
[QPU_W_TMU1_T] = "tmu1_t",
|
|
|
|
[QPU_W_TMU1_R] = "tmu1_r",
|
|
|
|
[QPU_W_TMU1_B] = "tmu1_b",
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
#define QPU_MASK(high, low) ((((uint64_t)1<<((high)-(low)+1))-1)<<(low))
|
|
|
|
/* Using the GNU statement expression extension */
|
|
|
|
#define QPU_SET_FIELD(value, field) \
|
|
|
|
({ \
|
|
|
|
uint64_t fieldval = (uint64_t)(value) << field ## _SHIFT; \
|
|
|
|
assert((fieldval & ~ field ## _MASK) == 0); \
|
|
|
|
fieldval & field ## _MASK; \
|
|
|
|
})
|
|
|
|
|
|
|
|
#define QPU_GET_FIELD(word, field) ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT))
|
|
|
|
|
|
|
|
#define QPU_UPDATE_FIELD(inst, value, field) \
|
|
|
|
(((inst) & ~(field ## _MASK)) | QPU_SET_FIELD(value, field))
|
|
|
|
|
|
|
|
#define QPU_SIG_SHIFT 60
|
|
|
|
#define QPU_SIG_MASK QPU_MASK(63, 60)
|
|
|
|
|
|
|
|
#define QPU_UNPACK_SHIFT 57
|
|
|
|
#define QPU_UNPACK_MASK QPU_MASK(59, 57)
|
|
|
|
|
|
|
|
#define QPU_LOAD_IMM_MODE_SHIFT 57
|
|
|
|
#define QPU_LOAD_IMM_MODE_MASK QPU_MASK(59, 57)
|
|
|
|
# define QPU_LOAD_IMM_MODE_U32 0
|
|
|
|
# define QPU_LOAD_IMM_MODE_I2 1
|
|
|
|
# define QPU_LOAD_IMM_MODE_U2 3
|
|
|
|
|
|
|
|
/**
|
|
|
|
* If set, the pack field means PACK_MUL or R4 packing, instead of normal
|
|
|
|
* regfile a packing.
|
|
|
|
*/
|
|
|
|
#define QPU_PM ((uint64_t)1 << 56)
|
|
|
|
|
|
|
|
#define QPU_PACK_SHIFT 52
|
|
|
|
#define QPU_PACK_MASK QPU_MASK(55, 52)
|
|
|
|
|
|
|
|
#define QPU_COND_ADD_SHIFT 49
|
|
|
|
#define QPU_COND_ADD_MASK QPU_MASK(51, 49)
|
|
|
|
#define QPU_COND_MUL_SHIFT 46
|
|
|
|
#define QPU_COND_MUL_MASK QPU_MASK(48, 46)
|
|
|
|
|
|
|
|
|
|
|
|
#define QPU_BRANCH_COND_SHIFT 52
|
|
|
|
#define QPU_BRANCH_COND_MASK QPU_MASK(55, 52)
|
|
|
|
|
|
|
|
#define QPU_BRANCH_REL ((uint64_t)1 << 51)
|
|
|
|
#define QPU_BRANCH_REG ((uint64_t)1 << 50)
|
|
|
|
|
|
|
|
#define QPU_BRANCH_RADDR_A_SHIFT 45
|
|
|
|
#define QPU_BRANCH_RADDR_A_MASK QPU_MASK(49, 45)
|
|
|
|
|
|
|
|
#define QPU_SF ((uint64_t)1 << 45)
|
|
|
|
|
|
|
|
#define QPU_WADDR_ADD_SHIFT 38
|
|
|
|
#define QPU_WADDR_ADD_MASK QPU_MASK(43, 38)
|
|
|
|
#define QPU_WADDR_MUL_SHIFT 32
|
|
|
|
#define QPU_WADDR_MUL_MASK QPU_MASK(37, 32)
|
|
|
|
|
|
|
|
#define QPU_OP_MUL_SHIFT 29
|
|
|
|
#define QPU_OP_MUL_MASK QPU_MASK(31, 29)
|
|
|
|
|
|
|
|
#define QPU_RADDR_A_SHIFT 18
|
|
|
|
#define QPU_RADDR_A_MASK QPU_MASK(23, 18)
|
|
|
|
#define QPU_RADDR_B_SHIFT 12
|
|
|
|
#define QPU_RADDR_B_MASK QPU_MASK(17, 12)
|
|
|
|
#define QPU_SMALL_IMM_SHIFT 12
|
|
|
|
#define QPU_SMALL_IMM_MASK QPU_MASK(17, 12)
|
|
|
|
/* Small immediate value for rotate-by-r5, and 49-63 are "rotate by n
|
|
|
|
* channels"
|
|
|
|
*/
|
|
|
|
#define QPU_SMALL_IMM_MUL_ROT 48
|
|
|
|
|
|
|
|
#define QPU_ADD_A_SHIFT 9
|
|
|
|
#define QPU_ADD_A_MASK QPU_MASK(11, 9)
|
|
|
|
#define QPU_ADD_B_SHIFT 6
|
|
|
|
#define QPU_ADD_B_MASK QPU_MASK(8, 6)
|
|
|
|
#define QPU_MUL_A_SHIFT 3
|
|
|
|
#define QPU_MUL_A_MASK QPU_MASK(5, 3)
|
|
|
|
#define QPU_MUL_B_SHIFT 0
|
|
|
|
#define QPU_MUL_B_MASK QPU_MASK(2, 0)
|
|
|
|
|
|
|
|
#define QPU_WS ((uint64_t)1 << 44)
|
|
|
|
|
|
|
|
#define QPU_OP_ADD_SHIFT 24
|
|
|
|
#define QPU_OP_ADD_MASK QPU_MASK(28, 24)
|
|
|
|
|
|
|
|
#define QPU_LOAD_IMM_SHIFT 0
|
|
|
|
#define QPU_LOAD_IMM_MASK QPU_MASK(31, 0)
|
|
|
|
|
|
|
|
#define QPU_BRANCH_TARGET_SHIFT 0
|
|
|
|
#define QPU_BRANCH_TARGET_MASK QPU_MASK(31, 0)
|
|
|
|
|
|
|
|
#endif /* VC4_QPU_DEFINES_H */
|