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https://github.com/Yours3lf/rpi-vk-driver.git
synced 2024-12-01 13:24:20 +01:00
assembler now should be fully functional
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061d52907f
@ -301,7 +301,7 @@ uint64_t encode_load_imm(uint8_t pack_unpack_select,
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//write per element MS bit and LS bit across simd array
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uint64_t encode_load_imm_per_elem(
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uint8_t signed_or_unsigned, //0 for signed, 1 for unsigned
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uint8_t signed_or_unsigned, //1 for signed, 0 for unsigned
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uint8_t pack_unpack_select,
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uint8_t pack_mode,
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qpu_cond cond_add,
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@ -318,7 +318,7 @@ uint64_t encode_load_imm_per_elem(
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uint64_t tmp = 0;
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tmp = 0x71;
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tmp |= signed_or_unsigned << 1;
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tmp |= !signed_or_unsigned << 1;
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res |= tmp << 57;
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tmp = pack_unpack_select & 1;
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@ -353,23 +353,6 @@ uint64_t encode_load_imm_per_elem(
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return res;
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}
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/*
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Format:
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#comment
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sig_bit_optional ; dstAdd.pack_mode_optional = add_opcode.sf_optional.condition.unpack_mode_optional(srcA, srcB, imm_optional, raddr_a_optional, raddr_b_optional) ; dstMul.pack_mode_optional = mul_opcode.condition(srcA, srcB) ;
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sig_bit_branch ; dstAdd = branch.rel_optional.reg_optional.condition(address, srcA_optional) ; dstMul = branch() ;
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sig_bit_none ; dstAdd.pack_mode_optional = sem_inc.sf_optional.condition(sem_number, 27bit_imm_value_optional) ; dstMul.pack_mode_optional = sem_inc.condition() ;
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sig_load_imm ; dstAdd.pack_mode_optional = load32.sf_optional.condition(immediate_value) ; dstMul.pack_mode_optional = load32.condition() ;
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sig_load_imm ; dstAdd.pack_mode_optional = load16.signed_optional.sf_optional.condition(int16_imm, in16_imm) ; dstMul.pack_mode_optional = load16.condition() ;
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Examples:
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sig_none ; ra0.nop = add.sf.always(r0, r1, 0) ; rb0.nop = fmul.sf.always(r2, r3) ;
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sig_branch ; ra0 = branch.rel.reg.always(0xdeadbeef, ra1) ; rb0 = branch() ;
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sig_none ; ra0.nop = sem_inc.sf.always(1, 0x7ffffff) ; rb0.nop = sem_inc.always() ;
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sig_load_imm ; ra0.nop = load32.sf.always(0xdeadbeef) ; rb0.nop = load32.always() ;
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sig_load_imm ; ra0.nop = load16.sf.signed.always(1, 2) ; rb0.nop = load16.always() ;
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*/
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qpu_sig_bits parse_sig_bit(char* str)
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{
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unsigned num_sig_bits = sizeof(qpu_sig_bits_str) / sizeof(const char *);
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@ -459,17 +442,24 @@ void parse_dst(char** str, qpu_waddr* waddr, uint8_t* pack_mode, uint8_t* ws, un
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*pack_mode = pack_mode_res;
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}
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void parse_op_modifiers(char** str, uint8_t* sf, qpu_cond* condition, qpu_unpack* unpack_mode, uint8_t* rel, uint8_t* reg)
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void parse_op_modifiers(char** str, uint8_t* signed_or_unsigned, uint8_t* pm, uint8_t* sf, qpu_cond* condition, qpu_unpack* unpack_mode, uint8_t* rel, uint8_t* reg)
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{
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char* modifier = strtok(*str, ".");
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//at most 3 modifiers supported
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for(int c = 0; c < 3; ++c)
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//at most 4 modifiers supported
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for(int c = 0; c < 4; ++c)
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{
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if(modifier)
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{
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*str = modifier;
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if(strcmp(modifier, "pm") == 0)
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{
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*pm = 1;
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modifier = strtok(0, ".");
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continue;
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}
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if(strcmp(modifier, "rel") == 0)
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{
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*rel = 1;
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@ -491,6 +481,13 @@ void parse_op_modifiers(char** str, uint8_t* sf, qpu_cond* condition, qpu_unpack
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continue;
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}
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if(strcmp(modifier, "signed") == 0)
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{
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*signed_or_unsigned = 1;
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modifier = strtok(0, ".");
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continue;
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}
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unsigned found = 0;
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unsigned num_conds = sizeof(qpu_cond_str) / sizeof(const char *);
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@ -730,7 +727,7 @@ void parse_args_sem(char** str, uint8_t* sem, uint32_t* imm32)
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*str += 1;
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}
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void parse_args_branch(char** str, uint32_t* imm32, uint8_t* raddr_a)
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void parse_args_branch(char** str, uint32_t* imm32, qpu_branch_cond* branch_cond, uint8_t* raddr_a)
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{
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char* arg = strtok(*str, " \n\v\f\r\t,");
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@ -742,6 +739,23 @@ void parse_args_branch(char** str, uint32_t* imm32, uint8_t* raddr_a)
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arg = strtok(0, " \n\v\f\r\t,");
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if(arg)
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{
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unsigned num_branch_conds = sizeof(qpu_branch_cond_str) / sizeof(const char *);
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for(unsigned c = 0; c < num_branch_conds && arg; ++c)
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{
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if(qpu_branch_cond_str[c] && strcmp(arg, qpu_branch_cond_str[c]) == 0)
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{
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*branch_cond = c;
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*str = arg;
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break;
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}
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}
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}
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arg = strtok(0, " \n\v\f\r\t,");
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if(arg)
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{
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uint8_t raddr_a_res = 0;
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@ -815,34 +829,26 @@ void parse_args_load(char** str, qpu_load_type load_type, uint32_t* imm32, uint1
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}
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uint64_t* assemble_qpu_asm(char* str)
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void assemble_qpu_asm(char* str, uint64_t* instructions)
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{
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unsigned num_instructions = 0;
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char* ptr = str;
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while(ptr && *ptr != '\0')
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{
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ptr = strstr(ptr, ";");
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ptr = strstr(ptr+(ptr!=0), ";");
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ptr = strstr(ptr+(ptr!=0), ";");
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if(ptr)
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{
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ptr += 1;
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num_instructions += 1;
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}
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}
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printf("Num instructions: %i\n", num_instructions);
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if(!num_instructions)
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{
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return 0;
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}
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uint64_t* instructions = malloc(sizeof(uint64_t)*num_instructions);
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unsigned instruction_counter = 0;
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//delete lines that have comments in them
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char* comment_token = strstr(str, "#");
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while(comment_token)
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{
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while(*comment_token != '\n')
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{
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*comment_token = ' ';
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comment_token++;
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}
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*comment_token = ' ';
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comment_token = strstr(comment_token, "#");
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}
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//parse string token by token
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char* token = strtok(str, " \n\v\f\r\t;");
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while(token)
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@ -874,7 +880,7 @@ uint64_t* assemble_qpu_asm(char* str)
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uint16_t ls_imm16 = 0;
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uint8_t semaphore = 0;
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qpu_load_type load_type = QPU_LOAD32;
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uint8_t signed_or_unsigned = 0;
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uint8_t is_signed = 0;
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qpu_branch_cond branch_cond = QPU_COND_BRANCH_ALWAYS;
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sig_bit = parse_sig_bit(token);
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@ -893,7 +899,7 @@ uint64_t* assemble_qpu_asm(char* str)
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//get modifiers
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token = strtok(token, " \n\v\f\r\t(");
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parse_op_modifiers(&token, &sf, &cond_add, &unpack_mode, &rel, ®);
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parse_op_modifiers(&token, &is_signed, &pack_unpack_select, &sf, &cond_add, &unpack_mode, &rel, ®);
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if(type == QPU_ALU)
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{
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@ -911,7 +917,7 @@ uint64_t* assemble_qpu_asm(char* str)
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{
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//get arguments for branch
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token = strtok(token, ")");
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parse_args_branch(&token, &imm32, &raddr_a);
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parse_args_branch(&token, &imm32, &branch_cond, &raddr_a);
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}
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else if(type == QPU_LOAD_IMM)
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{
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@ -930,7 +936,7 @@ uint64_t* assemble_qpu_asm(char* str)
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//get modifiers
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token = strtok(token, " \n\v\f\r\t(");
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parse_op_modifiers(&token, &sf, &cond_mul, &unpack_mode, &rel, ®);
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parse_op_modifiers(&token, &is_signed, &pack_unpack_select, &sf, &cond_mul, &unpack_mode, &rel, ®);
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token = strtok(token, ")");
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@ -968,26 +974,99 @@ uint64_t* assemble_qpu_asm(char* str)
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}
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else
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{
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instructions[instruction_counter] = encode_load_imm_per_elem(signed_or_unsigned, pack_unpack_select, pack_mode, cond_add, cond_mul, sf, ws, waddr_add, waddr_mul, ms_imm16, ls_imm16);
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instructions[instruction_counter] = encode_load_imm_per_elem(is_signed, pack_unpack_select, pack_mode, cond_add, cond_mul, sf, ws, waddr_add, waddr_mul, ms_imm16, ls_imm16);
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}
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}
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instruction_counter++;
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token = strtok(token, " \n\v\f\r\t;");
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}
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return instructions;
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}
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void disassemble_qpu_asm(uint64_t instruction)
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{
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}
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/*
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Format:
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#comment
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sig_bit_optional ; dstAdd.pack_mode_optional = add_opcode.pm_optional.sf_optional.condition.unpack_mode_optional(srcA, srcB, imm_optional, raddr_a_optional, raddr_b_optional) ; dstMul.pack_mode_optional = mul_opcode.condition(srcA, srcB) ;
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sig_bit_branch ; dstAdd = branch.pm_optional.rel_optional.reg_optional(address, condition, srcA_optional) ; dstMul = branch() ;
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sig_bit_none ; dstAdd.pack_mode_optional = sem_inc.pm_optional.sf_optional.condition(sem_number, 27bit_imm_value_optional) ; dstMul.pack_mode_optional = sem_inc.condition() ;
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sig_load_imm ; dstAdd.pack_mode_optional = load32.pm_optional.sf_optional.condition(immediate_value) ; dstMul.pack_mode_optional = load32.condition() ;
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sig_load_imm ; dstAdd.pack_mode_optional = load16.pm_optional.signed_optional.sf_optional.condition(int16_imm, in16_imm) ; dstMul.pack_mode_optional = load16.condition() ;
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Examples:
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sig_none ; ra0.nop = add.pm.sf.always(r0, r1, 0) ; rb0.nop = fmul.sf.always(r2, r3) ;
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sig_branch ; ra0 = branch.pm.rel.reg.always(0xdeadbeef, ra1) ; rb0 = branch() ;
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sig_none ; ra0.nop = sem_inc.pm.sf.always(1, 0x7ffffff) ; rb0.nop = sem_inc.always() ;
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sig_load_imm ; ra0.nop = load32.pm.sf.always(0xdeadbeef) ; rb0.nop = load32.always() ;
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sig_load_imm ; ra0.nop = load16.pm.sf.signed.always(1, 2) ; rb0.nop = load16.always() ;
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#mov
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sig_none ; ra0.nop = or(r0, r0) ; rb0 = v8min(r1, r1) ;
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*/
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int main()
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{
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char asm_code[] =
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"sig_none ; ra0.nop = add.sf.always.nop(r0, r1, 0) ; rb0.nop = fmul.sf.always(r2, r3) ;"
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"sig_branch ; ra0 = branch.rel.reg.always(0xdeadbeef, ra1) ; rb0 = branch() ;"
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"sig_branch ; ra0 = branch.rel.reg(0xdeadbeef, always, ra1) ; rb0 = branch() ;"
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"#hello\n"
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"sig_none ; ra0.nop = sem_inc.sf.always(1, 0x7ffffff) ; rb0.nop = sem_inc.always() ;"
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"sig_load_imm ; ra0.nop = load32.sf.always(0xdeadbeef) ; rb0.nop = load32.always() ;";
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"#hello2\n"
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"sig_load_imm ; ra0.nop = load32.sf.always(0xdeadbeef) ; rb0.nop = load32.always() ;"
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"sig_load_imm ; ra0.nop = load16.sf.signed.always(0xdead, 0xbeef) ; rb0.nop = load16.always() ;";
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uint64_t* assembly = assemble_qpu_asm(asm_code);
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unsigned num_instructions = 0;
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char* ptr = asm_code;
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while(ptr && *ptr != '\0')
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{
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ptr = strstr(ptr, ";");
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ptr = strstr(ptr+(ptr!=0), ";");
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ptr = strstr(ptr+(ptr!=0), ";");
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if(ptr)
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{
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ptr += 1;
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num_instructions += 1;
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}
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}
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printf("Num instructions: %i\n", num_instructions);
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if(!num_instructions)
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{
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return 0;
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}
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uint64_t* instruction_size = sizeof(uint64_t)*num_instructions;
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uint64_t* instructions = malloc(instruction_size);
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assemble_qpu_asm(asm_code, instructions);
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for(int c = 0; c < instruction_size; ++c)
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{
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unsigned char d = ((char*)instructions)[c];
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printf("%#x,\t", d);
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if((c+1)%8==0)
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{
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printf("\n");
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}
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}
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const char asm_instructions[] =
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{
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0x53, 0x70, 0x9e, 0x2c, 0, 0x60, 0x2, 0x10,
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0xef, 0xbe, 0xad, 0xde, 0, 0x20, 0xfc, 0xf0,
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0xf1, 0xff, 0xff, 0xff, 0, 0x60, 0x2, 0xe8,
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0xef, 0xbe, 0xad, 0xde, 0, 0x60, 0x2, 0xe0,
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0xef, 0xbe, 0xad, 0xde, 0, 0x60, 0x2, 0xe2
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};
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for(int c = 0; c < num_instructions; ++c)
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{
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disassemble_qpu_asm(asm_instructions);
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}
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return 0;
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}
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