The F4 CPUs have 16KB x 4, 64KB x 1 and 128KB x 7 sectors
of flash. The FW image currently ends in the middle of a
128KB sector. FW_BANK is now increased to end on a sector
boundary.
The code in RCC_GetClocksFreq() uses HSE_VALUE to determine
the tick rate of the SYSCLK. This in turn is used by the
code in PIOS_DELAY_* to compute delays.
ST Library defaults this to 25MHz for the F4. Our board
actually has an 8MHz oscillator so delays were way off.
Mostly affects the bootloaders since most FW code uses RTOS
delays rather than busy-waiting using PIOS_DELAY_*.
Removes hard-coding of JTAG interface config in the
<board>_program make macros.
This allows the use of STLINKv2 for F4 boards while
continuing to use the FOSS JTAG revB on F1 boards.
