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2031cfe4d0
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1344 ebee16cc-31ac-478f-84a7-5cbb03baadba
81 lines
2.9 KiB
C
81 lines
2.9 KiB
C
/**
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******************************************************************************
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* @addtogroup PIOS PIOS Core hardware abstraction layer
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* @{
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* @addtogroup PIOS_WDG Watchdog Functions
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* @brief PIOS Comamnds to initialize and clear watchdog timer
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* @{
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*
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* @file pios_spi.c
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* @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2010.
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* Parts by Thorsten Klose (tk@midibox.org) (tk@midibox.org)
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* @brief Hardware Abstraction Layer for SPI ports of STM32
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* @see The GNU Public License (GPL) Version 3
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* @notes
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*
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* The PIOS Watchdog provides a HAL to initialize a watchdog
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*
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*****************************************************************************/
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "pios.h"
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#include "stm32f10x_iwdg.h"
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#include "stm32f10x_dbgmcu.h"
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/**
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* @brief Initialize the watchdog timer for a specified timeout
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*
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* It is important to note that this function returns the achieved timeout
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* for this hardware. For hardware indendence this should be checked when
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* scheduling updates. Other hardware dependent details may need to be
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* considered such as a window time which sets a minimum update time,
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* and this function should return a recommended delay for clearing.
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*
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* For the STM32 nominal clock rate is 32 khz, but for the maximum clock rate of
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* 60 khz and a prescalar of 4 yields a clock rate of 15 khz. The delay that is
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* set in the watchdog assumes the nominal clock rate, but the delay for FreeRTOS
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* to use is 75% of the minimal delay.
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*
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* @param[in] delayMs The delay period in ms
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* @returns Maximum recommended delay between updates
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*/
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uint8_t PIOS_WDG_Init( uint8_t delayMs )
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{
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uint16_t delay;
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delay = 60 / 16 * delayMs;
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if( delay > 0xfff )
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delay = 0xfff;
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DBGMCU_Config(DBGMCU_IWDG_STOP, ENABLE); // make the watchdog stop counting in debug mode
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IWDG_WriteAccessCmd( IWDG_WriteAccess_Enable );
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IWDG_SetPrescaler( IWDG_Prescaler_16 );
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IWDG_SetReload( delay );
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IWDG_ReloadCounter();
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IWDG_Enable();
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return delay / (60 / 16) * .75;
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}
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/**
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* @brief Clear the watchdog timer
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*
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* This function must be called at the appropriate delay to prevent a reset event occuring
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*/
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void PIOS_WDG_Clear()
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{
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IWDG_ReloadCounter();
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}
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