2012-03-29 10:59:24 +02:00
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/*
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Copyright (c) 2012 Arduino. All right reserved.
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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2012-04-28 15:16:13 +02:00
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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2012-03-29 10:59:24 +02:00
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See the GNU Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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2012-03-29 21:11:05 +02:00
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#include "chip.h"
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2012-04-30 19:34:27 +02:00
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#include <stdio.h>
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2012-03-29 10:59:24 +02:00
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#if SAM3XA_SERIES
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2012-05-03 14:32:24 +02:00
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static void (*gpf_isr)(void) = (0UL);
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2012-04-30 13:42:04 +02:00
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2012-05-03 17:12:46 +02:00
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//static volatile uint32_t ul_ep = (0UL);
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static volatile uint32_t ul_send_fifo_ptr[MAX_ENDPOINTS];
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static volatile uint32_t ul_recv_fifo_ptr[MAX_ENDPOINTS];
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2012-04-30 13:42:04 +02:00
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void UDD_SetStack(void (*pf_isr)(void))
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{
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gpf_isr = pf_isr;
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}
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void UOTGHS_Handler( void )
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2012-04-28 15:16:13 +02:00
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{
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2012-04-30 13:42:04 +02:00
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if (gpf_isr)
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gpf_isr();
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}
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2012-04-29 00:54:05 +02:00
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2012-04-30 13:42:04 +02:00
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uint32_t UDD_Init(void)
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2012-04-28 15:16:13 +02:00
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{
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2012-05-03 17:12:46 +02:00
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uint32_t i;
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for (i = 0; i < MAX_ENDPOINTS; ++i)
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{
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ul_send_fifo_ptr[i] = 0;
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ul_recv_fifo_ptr[i] = 0;
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}
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2012-04-28 15:16:13 +02:00
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2012-04-30 13:42:04 +02:00
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// Enables the USB Clock
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2012-04-28 15:16:13 +02:00
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pmc_enable_periph_clk(ID_UOTGHS);
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pmc_enable_upll_clock();
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pmc_switch_udpck_to_upllck(0); // div=0+1
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pmc_enable_udpck();
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2012-04-30 13:42:04 +02:00
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// Configure interrupts
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2012-04-28 15:16:13 +02:00
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NVIC_SetPriority((IRQn_Type) ID_UOTGHS, 0UL);
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NVIC_EnableIRQ((IRQn_Type) ID_UOTGHS);
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// Always authorize asynchrone USB interrupts to exit from sleep mode
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// for SAM3 USB wake up device except BACKUP mode
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2012-04-30 19:34:27 +02:00
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//pmc_set_fast_startup_input(PMC_FSMR_USBAL);
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// ID pin not used then force device mode
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otg_disable_id_pin();
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otg_force_device_mode();
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// Enable USB hardware
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otg_disable_pad();
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otg_enable_pad();
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otg_enable();
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otg_unfreeze_clock();
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2012-05-03 14:32:24 +02:00
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2012-04-30 19:34:27 +02:00
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// Check USB clock
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while (!Is_otg_clock_usable())
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;
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udd_low_speed_disable();
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udd_high_speed_disable();
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//otg_ack_vbus_transition();
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// Force Vbus interrupt in case of Vbus always with a high level
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// This is possible with a short timing between a Host mode stop/start.
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/*if (Is_otg_vbus_high()) {
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otg_raise_vbus_transition();
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}
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otg_enable_vbus_interrupt();*/
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otg_freeze_clock();
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2012-04-30 13:42:04 +02:00
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return 0UL ;
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2012-04-28 15:16:13 +02:00
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}
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2012-04-30 13:42:04 +02:00
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void UDD_Attach(void)
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2012-04-28 15:16:13 +02:00
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{
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2012-04-30 19:34:27 +02:00
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//USBCON = ((1<<USBE)|(1<<OTGPADE)); // start USB clock
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//UDIEN = (1<<EORSTE)|(1<<SOFE); // Enable interrupts for EOR (End of Reset) and SOF (start of frame)
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//UDCON = 0; // enable attach resistor
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irqflags_t flags = cpu_irq_save();
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2012-05-03 14:32:24 +02:00
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//printf("=> UDD_Attach\r\n");
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2012-04-30 19:34:27 +02:00
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otg_unfreeze_clock();
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// This section of clock check can be improved with a chek of
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// USB clock source via sysclk()
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// Check USB clock because the source can be a PLL
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while (!Is_otg_clock_usable());
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// Authorize attach if Vbus is present
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udd_attach_device();
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// Enable USB line events
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udd_enable_reset_interrupt();
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//udd_enable_suspend_interrupt();
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//udd_enable_wake_up_interrupt();
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//////////////udd_enable_sof_interrupt();
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// Reset following interupts flag
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//udd_ack_reset();
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//udd_ack_sof();
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// The first suspend interrupt must be forced
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// The first suspend interrupt is not detected else raise it
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//udd_raise_suspend();
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//udd_ack_wake_up();
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//otg_freeze_clock();
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cpu_irq_restore(flags);
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2012-04-28 15:16:13 +02:00
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}
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2012-04-30 13:42:04 +02:00
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void UDD_Detach(void)
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2012-04-28 15:16:13 +02:00
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{
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2012-05-03 14:32:24 +02:00
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//printf("=> UDD_Detach\r\n");
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2012-04-30 19:34:27 +02:00
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UOTGHS->UOTGHS_DEVCTRL |= UOTGHS_DEVCTRL_DETACH;
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}
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void UDD_InitEP( uint32_t ul_ep_nb, uint32_t ul_ep_cfg )
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{
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2012-05-03 14:32:24 +02:00
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ul_ep_nb = ul_ep_nb & 0xF; // EP range is 0..9, hence mask is 0xF.
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//printf("=> UDD_InitEP : init EP %d\r\n", ul_ep_nb);
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2012-04-30 19:34:27 +02:00
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// Reset EP
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2012-05-03 14:32:24 +02:00
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//UOTGHS->UOTGHS_DEVEPT = (UOTGHS_DEVEPT_EPRST0 << ul_ep_nb);
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2012-04-30 19:34:27 +02:00
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// Configure EP
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UOTGHS->UOTGHS_DEVEPTCFG[ul_ep_nb] = ul_ep_cfg;
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2012-05-03 14:32:24 +02:00
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// Allocate memory
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//udd_allocate_memory(ul_ep_nb);
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2012-04-30 19:34:27 +02:00
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// Enable EP
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2012-05-03 14:32:24 +02:00
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// UOTGHS->UOTGHS_DEVEPT |= (UOTGHS_DEVEPT_EPEN0 << ul_ep_nb);
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udd_enable_endpoint(ul_ep_nb);
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if (!Is_udd_endpoint_configured(ul_ep_nb)) {
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//printf("=> UDD_InitEP : ############################## ERROR FAILED TO INIT EP %d\r\n", ul_ep_nb);
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}
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2012-04-30 19:34:27 +02:00
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}
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2012-05-03 14:32:24 +02:00
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void UDD_InitEndpoints(const uint32_t* eps_table, const uint32_t ul_eps_table_size)
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2012-04-30 19:34:27 +02:00
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{
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uint32_t ul_ep_nb ;
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2012-05-03 14:32:24 +02:00
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for (ul_ep_nb = 1; ul_ep_nb < ul_eps_table_size; ul_ep_nb++)
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/*void UDD_InitEndpoints(const uint32_t eps_table[])
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{
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uint32_t ul_ep_nb ;
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//printf("=> UDD_InitEndpoints : Taille tableau %d %d\r\n", sizeof(eps_table), (sizeof(eps_table) / sizeof(eps_table[0])));
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for (ul_ep_nb = 1; ul_ep_nb < sizeof(eps_table) / sizeof(eps_table[0]); ul_ep_nb++)*/
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2012-04-30 19:34:27 +02:00
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{
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// Reset Endpoint Fifos
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/* UOTGHS->UOTGHS_DEVEPTISR[ul_EP].UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_TOGGLESQ | UDPHS_EPTCLRSTA_FRCESTALL;
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UOTGHS->UOTGHS_DEVEPT = 1<<ul_EP;
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//UECONX = 1;
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//UECFG0X = pgm_read_byte(_initEndpoints+ul_EP);
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UOTGHS->UDPHS_EPT[ul_EP].UDPHS_EPTCFG = _initEndpoints[ul_EP];
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while( (signed int)UDPHS_EPTCFG_EPT_MAPD != (signed int)((UOTGHS->UDPHS_EPT[ul_EP].UDPHS_EPTCFG) & (unsigned int)UDPHS_EPTCFG_EPT_MAPD) )
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;
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UOTGHS->UDPHS_EPT[ul_EP].UDPHS_EPTCTLENB = UDPHS_EPTCTLENB_EPT_ENABL;
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// UECFG1X = EP_DOUBLE_64;
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}*/
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2012-05-03 14:32:24 +02:00
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//printf("=> UDD_InitEndpoints : init EP %d\r\n", ul_ep_nb);
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2012-04-30 19:34:27 +02:00
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// Reset EP
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2012-05-03 14:32:24 +02:00
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//UOTGHS->UOTGHS_DEVEPT = (UOTGHS_DEVEPT_EPRST0 << ul_ep_nb);
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2012-04-30 19:34:27 +02:00
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// Configure EP
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UOTGHS->UOTGHS_DEVEPTCFG[ul_ep_nb] = eps_table[ul_ep_nb];
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2012-05-03 14:32:24 +02:00
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// Allocate memory
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//udd_allocate_memory(ul_ep_nb);
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2012-04-30 19:34:27 +02:00
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// Enable EP
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2012-05-03 14:32:24 +02:00
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//UOTGHS->UOTGHS_DEVEPT |= (UOTGHS_DEVEPT_EPEN0 << ul_ep_nb);
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udd_enable_endpoint(ul_ep_nb);
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if (!Is_udd_endpoint_configured(ul_ep_nb)) {
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//printf("=> UDD_InitEP : ############################## ERROR FAILED TO INIT EP %d\r\n", ul_ep_nb);
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}
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2012-04-30 19:34:27 +02:00
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}
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2012-05-03 14:32:24 +02:00
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2012-04-30 19:34:27 +02:00
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}
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// Wait until ready to accept IN packet.
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2012-04-30 13:42:04 +02:00
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void UDD_WaitIN(void)
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{
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//while (!(UEINTX & (1<<TXINI)));
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2012-05-03 17:12:46 +02:00
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while (!(UOTGHS->UOTGHS_DEVEPTISR[EP0] & UOTGHS_DEVEPTISR_TXINI))
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2012-04-30 13:42:04 +02:00
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;
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}
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void UDD_WaitOUT(void)
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{
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//while (!(UEINTX & (1<<RXOUTI)));
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2012-05-03 17:12:46 +02:00
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while (!(UOTGHS->UOTGHS_DEVEPTISR[EP0] & UOTGHS_DEVEPTISR_RXOUTI))
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2012-04-30 13:42:04 +02:00
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;
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}
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2012-04-30 19:34:27 +02:00
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// Send packet.
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2012-04-30 13:42:04 +02:00
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void UDD_ClearIN(void)
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{
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2012-05-03 14:32:24 +02:00
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//printf("=> UDD_ClearIN: sent %d bytes\r\n", ul_send_index);
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2012-04-30 13:42:04 +02:00
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// UEINTX = ~(1<<TXINI);
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2012-05-03 17:12:46 +02:00
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UOTGHS->UOTGHS_DEVEPTICR[EP0] = UOTGHS_DEVEPTICR_TXINIC;
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ul_send_fifo_ptr[EP0] = 0;
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2012-04-30 13:42:04 +02:00
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}
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void UDD_ClearOUT(void)
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{
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// UEINTX = ~(1<<RXOUTI);
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2012-05-03 17:12:46 +02:00
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UOTGHS->UOTGHS_DEVEPTICR[EP0] = UOTGHS_DEVEPTICR_RXOUTIC;
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ul_recv_fifo_ptr[EP0] = 0;
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2012-04-30 13:42:04 +02:00
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}
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2012-04-30 19:34:27 +02:00
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// Wait for IN FIFO to be ready to accept data or OUT FIFO to receive data.
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// Return true if new IN FIFO buffer available.
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2012-04-30 13:42:04 +02:00
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uint32_t UDD_WaitForINOrOUT(void)
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{
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//while (!(UEINTX & ((1<<TXINI)|(1<<RXOUTI))));
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//return (UEINTX & (1<<RXOUTI)) == 0;
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2012-05-03 17:12:46 +02:00
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while (!(UOTGHS->UOTGHS_DEVEPTISR[EP0] & (UOTGHS_DEVEPTISR_TXINI | UOTGHS_DEVEPTISR_RXOUTI)))
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2012-04-30 13:42:04 +02:00
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;
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2012-05-03 17:12:46 +02:00
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return ((UOTGHS->UOTGHS_DEVEPTISR[EP0] & UOTGHS_DEVEPTISR_RXOUTI) == 0);
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2012-04-30 13:42:04 +02:00
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}
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uint32_t UDD_ReceivedSetupInt(void)
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{
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2012-05-03 17:12:46 +02:00
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return UOTGHS->UOTGHS_DEVEPTISR[EP0] & UOTGHS_DEVEPTISR_RXSTPI;
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2012-04-30 13:42:04 +02:00
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}
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void UDD_ClearSetupInt(void)
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{
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//UEINTX = ~((1<<RXSTPI) | (1<<RXOUTI) | (1<<TXINI));
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2012-04-30 19:34:27 +02:00
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//UOTGHS->UOTGHS_DEVEPTICR[ul_ep] = (UOTGHS_DEVEPTICR_RXSTPIC | UOTGHS_DEVEPTICR_RXOUTIC | UOTGHS_DEVEPTICR_TXINIC);
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2012-05-03 17:12:46 +02:00
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UOTGHS->UOTGHS_DEVEPTICR[EP0] = (UOTGHS_DEVEPTICR_RXSTPIC);
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2012-04-30 13:42:04 +02:00
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}
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2012-05-03 17:12:46 +02:00
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void UDD_Send(uint32_t ep, const void* data, uint32_t len)
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2012-04-30 13:42:04 +02:00
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{
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2012-05-03 17:12:46 +02:00
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const uint8_t *ptr_src = data;
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uint8_t *ptr_dest = (uint8_t *) &udd_get_endpoint_fifo_access8(ep);
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uint32_t i;
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//printf("=> UDD_Send : ep=%d ptr_dest=%d len=%d\r\n", ep, ul_send_fifo_ptr[ep], len);
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for (i = 0, ptr_dest += ul_send_fifo_ptr[ep]; i < len; ++i)
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*ptr_dest++ = *ptr_src++;
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2012-04-30 13:42:04 +02:00
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2012-05-03 17:12:46 +02:00
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ul_send_fifo_ptr[ep] += i;
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2012-04-30 13:42:04 +02:00
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}
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2012-05-03 17:12:46 +02:00
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void UDD_Send8(uint32_t ep, uint8_t data )
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2012-04-30 13:42:04 +02:00
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{
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2012-05-03 17:12:46 +02:00
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uint8_t *ptr_dest = (uint8_t *) &udd_get_endpoint_fifo_access8(ep);
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//printf("=> UDD_Send8 : ul_send_index=%d data=0x%x\r\n", ul_send_index, data);
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ptr_dest[ul_send_fifo_ptr[ep]] = data;
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ul_send_fifo_ptr[ep] += 1;
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}
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2012-04-30 13:42:04 +02:00
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2012-05-03 17:12:46 +02:00
|
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uint8_t UDD_Recv8(uint32_t ep)
|
|
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{
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|
|
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uint8_t *ptr_dest = (uint8_t *) &udd_get_endpoint_fifo_access8(ep);
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uint8_t data = ptr_dest[ul_recv_fifo_ptr[ep]];
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2012-05-03 14:32:24 +02:00
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////printf("=> UDD_Recv8 : ul_recv_index=%d\r\n", ul_recv_index);
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2012-05-03 17:12:46 +02:00
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ul_recv_fifo_ptr[ep] += 1;
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return data;
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2012-04-30 13:42:04 +02:00
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}
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2012-05-03 17:12:46 +02:00
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void UDD_Recv(uint32_t ep, uint8_t* data, uint32_t len)
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2012-04-30 13:42:04 +02:00
|
|
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{
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2012-05-03 17:12:46 +02:00
|
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uint8_t *ptr_src = (uint8_t *) &udd_get_endpoint_fifo_access8(ep);
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uint8_t *ptr_dest = data;
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|
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uint32_t i;
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for (i = 0, ptr_src += ul_recv_fifo_ptr[ep]; i < len; ++i)
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*ptr_dest++ = *ptr_src++;
|
2012-04-30 13:42:04 +02:00
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|
2012-05-03 17:12:46 +02:00
|
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|
ul_recv_fifo_ptr[ep] += i;
|
2012-04-30 13:42:04 +02:00
|
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|
}
|
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|
|
|
|
|
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void UDD_Stall(void)
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|
|
|
{
|
|
|
|
//UECONX = (1<<STALLRQ) | (1<<EPEN);
|
2012-05-03 17:12:46 +02:00
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|
|
UOTGHS->UOTGHS_DEVEPT = (UOTGHS_DEVEPT_EPEN0 << EP0);
|
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|
|
UOTGHS->UOTGHS_DEVEPTIER[EP0] = UOTGHS_DEVEPTIER_STALLRQS;
|
2012-04-30 13:42:04 +02:00
|
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|
}
|
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|
2012-05-03 17:12:46 +02:00
|
|
|
uint32_t UDD_FifoByteCount(uint32_t ep)
|
2012-04-30 13:42:04 +02:00
|
|
|
{
|
2012-05-03 17:12:46 +02:00
|
|
|
return ((UOTGHS->UOTGHS_DEVEPTISR[ep] & UOTGHS_DEVEPTISR_BYCT_Msk) >> UOTGHS_DEVEPTISR_BYCT_Pos);
|
2012-04-30 13:42:04 +02:00
|
|
|
}
|
|
|
|
|
2012-05-03 17:12:46 +02:00
|
|
|
void UDD_ReleaseRX(uint32_t ep)
|
2012-04-30 13:42:04 +02:00
|
|
|
{
|
|
|
|
/* UEINTX = 0x6B; // FIFOCON=0 NAKINI=1 RWAL=1 NAKOUTI=0 RXSTPI=1 RXOUTI=0 STALLEDI=1 TXINI=1
|
|
|
|
clear fifocon = send and switch bank
|
|
|
|
nakouti a clearer
|
|
|
|
rxouti/killbank a clearer*/
|
|
|
|
|
2012-05-03 14:32:24 +02:00
|
|
|
//puts("=> UDD_ReleaseRX\r\n");
|
2012-05-03 17:12:46 +02:00
|
|
|
UOTGHS->UOTGHS_DEVEPTICR[ep] = (UOTGHS_DEVEPTICR_NAKOUTIC | UOTGHS_DEVEPTICR_RXOUTIC);
|
|
|
|
UOTGHS->UOTGHS_DEVEPTIDR[ep] = UOTGHS_DEVEPTIDR_FIFOCONC;
|
|
|
|
ul_recv_fifo_ptr[ep] = 0;
|
2012-04-30 13:42:04 +02:00
|
|
|
}
|
|
|
|
|
2012-05-03 17:12:46 +02:00
|
|
|
void UDD_ReleaseTX(uint32_t ep)
|
2012-04-30 13:42:04 +02:00
|
|
|
{
|
|
|
|
/* UEINTX = 0x3A; // FIFOCON=0 NAKINI=0 RWAL=1 NAKOUTI=1 RXSTPI=1 RXOUTI=0 STALLEDI=1 TXINI=0
|
|
|
|
clear fifocon = send and switch bank
|
|
|
|
nakini a clearer
|
|
|
|
rxouti/killbank a clearer
|
|
|
|
txini a clearer*/
|
|
|
|
|
2012-05-03 14:32:24 +02:00
|
|
|
//puts("=> UDD_ReleaseTX\r\n");
|
2012-05-03 17:12:46 +02:00
|
|
|
UOTGHS->UOTGHS_DEVEPTICR[ep] = (UOTGHS_DEVEPTICR_NAKINIC | UOTGHS_DEVEPTICR_RXOUTIC | UOTGHS_DEVEPTICR_TXINIC);
|
|
|
|
UOTGHS->UOTGHS_DEVEPTIDR[ep] = UOTGHS_DEVEPTIDR_FIFOCONC;
|
|
|
|
ul_send_fifo_ptr[ep] = 0;
|
2012-04-30 13:42:04 +02:00
|
|
|
}
|
|
|
|
|
2012-05-03 14:32:24 +02:00
|
|
|
// Return true if the current bank is not full.
|
2012-05-03 17:12:46 +02:00
|
|
|
uint32_t UDD_ReadWriteAllowed(uint32_t ep)
|
2012-04-30 13:42:04 +02:00
|
|
|
{
|
2012-05-03 17:12:46 +02:00
|
|
|
return (UOTGHS->UOTGHS_DEVEPTISR[ep] & UOTGHS_DEVEPTISR_RWALL);
|
2012-04-30 13:42:04 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void UDD_SetAddress(uint32_t addr)
|
|
|
|
{
|
2012-05-03 14:32:24 +02:00
|
|
|
//printf("=> UDD_SetAddress : setting address to %d\r\n", addr);
|
2012-04-30 13:42:04 +02:00
|
|
|
udd_configure_address(addr);
|
|
|
|
udd_enable_address();
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t UDD_GetFrameNumber(void)
|
|
|
|
{
|
|
|
|
return udd_frame_number();
|
|
|
|
}
|
2012-03-29 10:59:24 +02:00
|
|
|
|
|
|
|
#endif /* SAM3XA_SERIES */
|