The STM32 I2C block has a number of errata associated with it.
These errata are primarily related to timing sensitivities between
the peripheral and the interrupt handler. In particular, the
correct generation of the stop bit relies on the I2C IRQ running
immediately and not being held off for any reason.
NOTE: The I2C interrupts must be the highest priority IRQs in the
system to ensure correct operation.
I2C protocol is now implemented as a formal state machine.
See: stm32_i2c_fsm.{dot,jpg} for FSM description.
I2C init is now expressed by const initializers in pios_board.c
for both OP and AHRS boards.
I2C device drivers (ie. bmp085/hmc5843) now pass in const arrays
of an unlimited number of bus transfers to be done atomically.
The I2C adapter driver now handles all bus-level locking across the
list of transactions. Generation of start/restart/stop conditions
are handled automatically over the list of transactions.
Timeouts have been removed from the API for now. May be added
back later.
This driver has run error free on both the OP and AHRS boards for
up to 48hrs but it still sometimes fails earlier than that on the OP
board. There is another possible set of improvements to the driver
that could employ the DMA engine for transfers of >= 2bytes. This
change would reduce the timing sensitivities between the peripheral
and the driver but unfortunately, both the SPI and I2C interfaces
share the DMA1 engine. That means only one of these two peripherals
can use the DMA engine and right now, SPI between OP and AHRS is
already using it.
Failures are currently fatal and will lock up the CPU. This allows
useful information to be obtained in the failure cases.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1241 ebee16cc-31ac-478f-84a7-5cbb03baadba
To the outside world, the AHRS can be in one of only a few
primary states:
Not present - AHRS is absent or non-responsive via SPI
Inactive - Only link-level status messages are processed
Ready - Ready to receive the next application level message
Busy - Application level message is being processed
Internal to the AHRS, there are many more states that need to be
managed. This FSM provides the necessary decoupling between the
ISR (which is being driven by the SPI link) and the AHRS main
processing loop which must continue to run its filters independently
of the SPI messaging rate.
With this structure, SPI messages can be received at any time but
processed at only specific points within the filter chains.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@1005 ebee16cc-31ac-478f-84a7-5cbb03baadba
- Created a pluggable COM layer
- Converted COM + USART init into static initializers
rather than typedefs
- Generalized the USB HID COM API to match the USART
API.
- Changed USART and COM layers to be data driven rather
than #ifdef'ing/switching on the specifics of each port
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@760 ebee16cc-31ac-478f-84a7-5cbb03baadba
Added support for SPI slave configurations to the pios SPI layer.
Converted the board specific configuration for the PIOS SPI layer to
use const static initializers rather than #defines (see pios_board.c).
SPI interface between the OP board and the AHRS is now operational at
a basic level, capable of moving simple single byte messages between
boards. Multi-byte, CRC protected messages will be added on top of this.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@759 ebee16cc-31ac-478f-84a7-5cbb03baadba
