ISR, make sure the latency is less than 50 us to avoid framesync errors. Still
seeing a few nonsense packets on Overo side but fairly few. Probably need to
add CRC to whole packet now and call it done.
ISR. This leads to a possible condition where a copy is taking place in
userspace and then a buffer swap interrupts it. However, the copy should
always finish before the SPI DMA slave catches up to that place in memory at 10
MHz.
This fixes a common condition where the userspace task (low priority) was not
swapping buffers in time from user space and logs were corrupted.
from an ISR. This was causing lock ups. It's a bit higher latency probably
(trivially slow) but if we aren't keeping up with the Overo transactions then
using a proper DMA double buffer will be required.
