The bootloader has been enabling pull-ups on all GPIO
pins during early init. These pull-ups are disabled
immediately before jumping to the firmware. This transition
results in all servos seeing a wide pulse as the board
resets making them jerk sideways aggresively and then snap
back to neutral.
All channels at max when using the FrSKY 4ch D4FR in PPM
mode results in the frame pulse shrinking well below our
threshold of 3800us and we lose frame.
With all 8 channels at max, the frame pulse becomes
indistinguishable from the other channels. Using all 8
channels with the FrSKY in PPM mode is NOT recommended
even after this change.
Recommend using at most 7 active channels in this mode so
we can still find the frame pulse.
The bootloader has been enabling pull-ups on all GPIO
pins during early init. These pull-ups are disabled
immediately before jumping to the firmware. This transition
results in all servos seeing a wide pulse as the board
resets making them jerk sideways aggresively and then snap
back to neutral.
All channels at max when using the FrSKY 4ch D4FR in PPM
mode results in the frame pulse shrinking well below our
threshold of 3800us and we lose frame.
With all 8 channels at max, the frame pulse becomes
indistinguishable from the other channels. Using all 8
channels with the FrSKY in PPM mode is NOT recommended
even after this change.
Recommend using at most 7 active channels in this mode so
we can still find the frame pulse.
Support for receiver configuration (PPM, PWM and DSM)
There are still problems with Flexi port (not sure if related to a problem with my board) and Uart/SBUS that has the input always inverted.
The CC and PipX bootloader updater (BU) builds don't currently
work due to some recent changes in how LEDs are handled.
Remove them from the default BU targets so that the all_flight
target can build clean again.
Also fix a linker warning in OP build.
CPU was being hammered with FIFO empty IRQs if we queued data but
the host wasn't actively draining the FIFO.
This was entirely unexpected so this hack should probably be
removed once we can figure out why this was happening.
This is almost certainly hiding some other issue.
Make sure we don't clobber our endpoint configuration by
double configuring an Rx or Tx buffer against it. Wait for
the completion of the previous operation before allowing
endpoint configuration again.
Upper (COM) layer was calling down into the HID layer before
the HID interface had been enabled. This was leading to
interacting with the endpoint Rx and Tx FIFOs prior to init.
The FIFO config was then being clobbered when we the USB IF
was eventually enabled.
Error flags being set were causing flash erase operations to
fail. Not sure why these flags were set though so this might
be hiding some other problem.
HID driver was incorrectly giving back the HID interface
descriptor when asked for the HID descriptor. This should
let OP boards interact better with generic HID layer drivers
and also gives us nicer output in lsusb once the HID descriptor
is read.
