Add Easystar 3D model, using 3DS format and textures. First model with textures in the SVN for testing of ModelView with textures.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@677 ebee16cc-31ac-478f-84a7-5cbb03baadba
The previous fix in r652 was _almost_ right. There was
still a one word (4-byte) overlap between _irq_stack_top
and the start of the data segment.
_irq_stack_end + _irq_stack_size leaves the '.' pointer at
the word immediatly after the stack. This commit corrects
this error and places _irq_stack_top on the last word
_inside_ the reserved space for the irq stack.
[Before]
$ ./tools/arm-2009q3/bin/arm-none-eabi-nm -n ./build/openpilot/OpenPilot.elf
...
20000000 A SRAM_BASE
20000000 B _irq_stack_end
20000400 d LED_GPIO_PORT <--- overlap
20000400 B _irq_stack_top <--- overlap
20000400 D _sdata
20000408 d ADC_GPIO_PORT
...
[After]
$ ./tools/arm-2009q3/bin/arm-none-eabi-nm -n ./build/openpilot/OpenPilot.elf
...
20000000 A SRAM_BASE
20000000 B _irq_stack_end
200003fc B _irq_stack_top
20000400 d LED_GPIO_PORT
20000400 D _sdata
20000408 d ADC_GPIO_PORT
...
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@668 ebee16cc-31ac-478f-84a7-5cbb03baadba
Standalone compilation, not included on the top level project.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@661 ebee16cc-31ac-478f-84a7-5cbb03baadba
Both EVents and ERrors were mistakenly being mapped to the
EVent IRQ channel.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@659 ebee16cc-31ac-478f-84a7-5cbb03baadba
This commit fixes all existing warnings.
All basic compiler warnings will now be treated as errors.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@658 ebee16cc-31ac-478f-84a7-5cbb03baadba
This fixes the COM interface over USB HID to the point where
it can establish and maintain solid communications with the UAVObject
Browser in the GCS.
Tested only on Linux. The USB HID interface is still disabled for now
until it is tested successfully by a wider group.
Edit telemetry.c and set ALLOW_HID_TELEMETRY to 1 to enable telemetry
over the USB HID interface and report your results in the forum.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@656 ebee16cc-31ac-478f-84a7-5cbb03baadba
- New Attitude module for AHRS (skeleton)
- New AttitudeSettings UAVobject
- New AttitudeActual UAVobject
- Regenerated UAVobjects
- Added new UAVobjects to OpenPilot and GCS builds
- New PiOS driver for OpenPilot AHRS (stubs only)
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@655 ebee16cc-31ac-478f-84a7-5cbb03baadba
Since the EXTI and NVIC init routines automatically enable the IRQ when it
is configured, it is possible for the EOC interrupt to fire immediately
upon configuring the IRQ.
Since the handler for the EOC interrupt (EXTI15_10_IRQHandler) does a
xSemaphoreGiveFromISR, it is important to have the semaphore initialized
prior to enabling the interrupt.
Also, added missing include for altitude module.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@654 ebee16cc-31ac-478f-84a7-5cbb03baadba
The MSP (IRQ stack) was trampling across the data segment. This was
especially disastrous in the USB interrupts since they allocate and
fill buffers on the stack.
The root of this trampling was that no RAM was being reserved for the
MSP and a hard-coded value of (0x20000400) was used as the initial MSP
base address. This resulted in the first 1K bytes of the .data segment
overlapping with the IRQ stack. As can be expected, all sorts of badness
resulted when interrupts were firing and trampling over variables.
This change reserves the first _isr_stack_size bytes at the beginning of
RAM for the MSP. If an ISR call chain runs off of the end of the MSP,
a Hard Fault will be generated as the (now invalid) sp is accessed.
There are two stack pointers in the Cortex-M3 CPU. These are MSP (Main
Stack Pointer) and PSP (Process Stack Pointer).
Which stack is in use at any given time is determined by the following table:
Mode CONTROL[ASPSEL] Stack
---- --------------- -----
Thread 0 MSP
Thread 1 PSP
Handler x MSP
Out of reset, the CPU is in Thread mode using the MSP. The initial value
of the MSP is automatically loaded from address 0 (lowest word in boot
region -- typically FLASH) immediately prior to jumping to the reset vector.
When running at interrupt level, the Cortex-M3 always uses the MSP and the
ASPSEL bit is forced to zero.
FreeRTOS allocates a separate stack for each task upon task creation. These
task stacks are allocated from the heap. FreeRTOS sets the active stack to
the PSP whenever running in a task context (both in privileged mode and user
mode).
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@652 ebee16cc-31ac-478f-84a7-5cbb03baadba
NOTE: Delete any metaobjects that you may have saved in the SD card (delete all .obj files).
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@643 ebee16cc-31ac-478f-84a7-5cbb03baadba
This module reads from the BMP085 pressure sensor. It periodically
updates the pressure (kPa) and temperature (C) as well as the
calculated altitude (m).
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@640 ebee16cc-31ac-478f-84a7-5cbb03baadba
FreeRTOS has a strict requirement that even interrupt-safe API calls (ie.
those ending in "FromISR") can only be called from ISRs that are at lesser
or equal priorities to configMAX_SYSCALL_INTERRUPT_PRIORITY. See the
"configKERNEL_INTERRUPT_PRIORITY and configMAX_SYSCALL_INTERRUPT_PRIORITY"
section at:
http://www.freertos.org/a00110.html
The interrupt numbers used on the Cortex-M3 CPU has a somewhat backward
representation of the interrupt numbers so 255 = lowest priority and
0 = highest priority.
The calculation is further complicated by the STM32 implementation only using
the upper 4 bits of the priority value. Only 0x00, 0x10, 0x20, ..., 0xE0, 0xF0
represent useful interrupt priorities.
FreeRTOS requires that MAX_SYSCALL and KERNEL interrupt priorities are expressed
as raw unshifted 8-bit values to be programmed directly into the BASEPRI register.
The priority values passed to the NVIC initialization, however, are expected
to be 4-bit values and are shifted up by 4 within NVIC_Init() for you.
The end result is that we need this arrangement:
[highest priority]
NVIC_0 (Non-maskable-interrupt)
NVIC_1
NVIC_2
[Must NOT call FreeRTOS APIs above here]
configMAX_SYSCALL_INTERRUPT_PRIORITY (now at 48 = 0x30 = NVIC_3)
PIOS_IRQ_PRIO_HIGHEST (cur. NVIC_4)
PIOS_IRQ_PRIO_HIGH (cur. NVIC_5)
PIOS_IRQ_PRIO_MID (cur. NVIC_8)
PIOS_IRQ_PRIO_LOW (cur. NVIC_12)
configKERNEL_INTERRUPT_PRIORITY (240 = 0xF0 = NVIC_15)
[lowest priority]
The previous config had configMAX_SYSCALL_INTERRUPT_PRIORITY set at
191 (0xBF) which is effectively NVIC_11. This was allowing all of
the MID, HIGH and HIGHEST interrupt handlers to preempt the OS in
its critical sections. Since some of these ISRs were calling
FreeRTOS APIs, this would result in corrupting internal data structures
within the OS.
It should be ok to move the configKERNEL_INTERRUPT_PRIORITY to a higher
priority as long as it is less than configMAX_SYSCALL_INTERRUPT_PRIORITY.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@637 ebee16cc-31ac-478f-84a7-5cbb03baadba
This fixes the gdb stepi command to allow the M3 core to make
forward progress even when interrupts are pending. M3 Core interrupts
are masked/unmasked in pre and post command hooks.
git-svn-id: svn://svn.openpilot.org/OpenPilot/trunk@636 ebee16cc-31ac-478f-84a7-5cbb03baadba
